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1. 11 3 OPERATING 13 UE ND 13 3 1 1 TAM ALUNEIUTA RE 13 3 1 2 VOLTA AREE TASTE 14 32 505 T T 15 3 2 1 FPGA 15 3 22 c 16 4 VME INTERFACE sviscssississsssessssoossesecssisssoccosevssssovencasseisscoesebasisscevaccessccossesesissseccasessuscesecsssssdssanseedescesecseuses 17 41 REGISTER ADDRESS MAD certe there rre Sails wad abe Gauls wiley 17 4 1 1 EET 18 42 GEO ADDRESS REGISTER Ea a a a E S AE a AES SREE 18 4 3 MODULE RESET 19 4 4 FIRMWARE REVISION 5 0 002020 0 nnn nnn nnn n n 19 4 5 SCRATCH IG REGISTER seiso orane e aa a a A E aa a a Aa a Ea aE Oa TEENAA EATE EEEE 19 4 6 2 19 4 7 SELECT VME FPGA FLASH REGISTER anna enean nana naa 19 4 8 SELECT USER FPGA FLASH
2. 19 4 9 VME FPGA FLASH MEMORY 4 64 00000 20 4 10 USER FPGA FLASH 4 4 44 4 eren 20 4 11 USER FPGA CONFIGURATION 4 222 20 5 USER FPGA DEMOS AND 1 1 3 4 01 010 0 4 0230000018000440000040004 4022444 21 NPO Filename Number of pages Page 00117 04 V1495 MUTx 10 V1495 REVIO 40 3 ls for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 20 07 2010 10 Diels INTRODUCTION dha e eae 21 5 1 1 Advanced Demo applications susisiekia K E ENE EE A 22 5 2 REFERENCE DESIGN KIT ccccccsccccccccececccscccececececececececscecssesececscecscececesecscscesscecscececscssevscevesecscsvesevees 22 5 2 1 OS TAAL cues LM ML E TEE 22 2 2 2 COIN REFERENCE Design 23 9 3 INTERFACE DESCRIPTION ecrire ect e a lec eee eie lecce Eres rn EORR 24 5 3 1 cuta sob saltu Ie Lue LII LC SE 24 5 3 2 REGISTER AE ER SERRE SER
3. 18 TABLE 5 1 COIN REFERENCE 1 23 TABLE 5 2 V1495 MEZZANINE EXPANSION PORTS 25 TABLE 5 3 PDL CONFIGURATION INTERFACE SIGNALS c ccesssceseeecsseceseeecaeceeceecaeceneecsaeceeeecsaeeeeeecsaeceeeeesaeeeeee 26 TABLE 5 4 DELAY LINES AND OSCILLATORS SIGNALS enne 26 TABLE 5 5 SPARE INTERFACE SIGNALS terrere 26 TABLE 5 6 LED INTERFACE SIGNALS 27 TABLE 5 7 COIN REFERENCE REGISTER 28 TABLE 5 8 SELECTION OF THE DELAY LINE rabat 32 NPO Filename Number of pages Page 00117 04 V1495 MUTx 10 V1495 REVIO 40 5 CAEN Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 20 07 2010 10 1 General description 1 1 NPO Overview The Mod V1495 is a VME 6U board 1U wide suitable for various digital Gate Trigger Translate Buffer Test applications which can be directly customised by the User and whose management is handled by two FPGA s FPGA Bridge which is used for the VME interface and for the connection between the VME interface and the 2nd FPGA FPGA through a proprietary
4. NPO Filename Number of pages gt Page 00117 04 V 1495 MUTx 10 V1495 REVIO 40 18 Tools for Discover Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 20 07 2010 10 4 3 4 4 4 5 4 6 4 7 4 8 NPO This register allows read back of the level of GEO pins for the selected board The register content is valid only for the VME64X board version The register content for the VME64 version is 1 Module Reset Register Base Address 0x800A write only D16 D32 A dummy access to this register allows to generate a single shot RESET of the module Firmware Revision Register Base Address 0x800C read only D16 D32 Bit Function 15 8 X 7 0 Y This register contains the firmware revision number X Y coded on 16 bit For instance the REV 1 2 register content is 0x102 Scratch16 Register Base Address 0x8018 D16 D32 read write This register allows to perform 16 bit test accesses for test purposes Scratch32 Register Base Address 0x8020 D32 read write This register allows to perform 32 bit test accesses for test purposes Select VME FPGA Flash Register Base Address 0 800 read write D16 D32 This register allows the VME FPGA configuration update stored into on board flash memory via VMEBUS The configuration can be updated by the user by means of the CVUpgrade software developed and dis
5. SERE ROC RO PEOEPA REPRE NOE RET 24 5 3 3 V1495 Front Panel Ports PORT A B C G INTERFACE sse ener 25 5 3 4 V1495 Mezzanine Expansion Ports PORT D E F 25 5 3 9 PDL Configuration 26 5 3 6 Delay Lines and Oscillators 26 3 3 7 SPARE Interface itti ciet ite ei C estos trig pe oed iot tue eed 26 5 3 8 LED Interface iid estet ettari NOSE eet 26 5 4 REFERENCE DESIGN DESCRIPTION 2 2 27 5 4 1 Mezzanine board interfacing eese eee eene trennen trennen eene 30 5 5 REGISTER DETAILED 31 3 9 4 V1495 Front Panel Ports Registers 31 5 5 2 V1495 Mezzanine Expansion Ports Registers 31 5 5 3 Delay SCLECHHON ER 31 5 5 4 PDL DELAY VALUE SETTING AND 32 5 5 5 Delay Unit using PDLs et b E E E EA E A 33 53 0 Delay Unitusing DLOS rinne 34 5 6 QUARTUS II WEB EDITION PROJECT e ceeccesceeseeesecseecseeeseeeneeeceseceseceseceseceaeceaeceaecaeeeaeesaeseneeesenereearens 37 37 PIRMWARE UPGRADE pci E e 40 LIST OF FIGURES FIG 1 1 V1
6. Fig 5 10 Quartus II hierarchical structure In order to generate a new programmation file it is necessary to launch the compiler by clicking on the purple play button on the tool bar see arrow Quartus II D luca Work V 1495_ USER DEMO _QUARTUSII_PROJECT_REV_2 O FIT v1495usr_demo v1495usr_demo File Edit View Project Assignments Processing Tools Window Help demo Jdxeeeoc Project Navigator ax SRC 1495ust_demo v1 495usr_pkg vhd SRC 1495ust_demo coin_reference vhd 59 458 149 if itl vhd SRC vI485usr demo tristate if rtl hd Fr E s N 5 SRC vi495ust demo v1495usr demo vhd Z4 2 JSRC v1495usr demo v1495usr hal vqm dal Lm QUARTUSII Version 8 0 Documentation Fig 5 11 Quartus II compiler launching Filename Number of pages Page 00117 04 V1495 MUTx 10 V1495_REV10 40 39 CAEN Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 20 07 2010 10 Quartus at this point launches in sequence the steps of the flow chart synthesis fitting place amp route then shows the correct compiling and the following screen or Help press F1 Quartus 1 D luca Work V1495 USER DEMO Q
7. CH15 CH31 CH15 CH30 CH14 CH304 CH14 CH17 1 CH17 1 CH16 CH16 Fig 2 2 Multipin connector pin assignment Filename Number of pages Page 00117 04 1495 0 10 V1495 REVIO 11 40 CAEN Q Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 20 07 2010 10 The CAEN Mod A967 Cable Adapter allows to adapt each Robinson Nugent Multipin Connector into two 1 17 17 pin Header type male connectors 3M 4634 7301 with locks through two 25 cm long flat cables Fig 2 3 Mod A967 Cable Adapter NPO Filename Number of pages Page 00117 04 1495 0 10 V1495 REVIO 40 12 Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 20 07 2010 10 3 Operating modes 3 1 Timers Gate Trigger applications require the production of an output signal with programmable width Gate whenever an input signal Trigger occurs Gates can be produced in several ways according to the system set up which can be either synchronous or asynchronous Synchronous systems Input signals are referred to a system clock they can be sampled by the clock itself and the output is a gate signal obtained with a counter whose width and delay is a multiple of the clock period If the application requires a width and
8. Mask bit is active low A MASK H Ox100E D16 D32 WO Port A mask This register masks X FFFF A 31 16 Mask bit is active low MASK L 0x1010 D16 D32 WO Port B mask This register masks X FFFF B 15 0 Mask bit is active low B MASK H 0 1012 D16 D32 WO Port B mask This register masks X FFFF B 31 16 Mask bit is active low C_MASK_L 0 1014 D16 D32 Port C mask This register masks X FFFF NPO Filename Number of pages Page 00117 04 V1495 MUTx 10 V1495_REV10 40 28 ols for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 20 07 2010 10 ADDRESS DATASIZING ACCESS NOTES ssid DEF C 15 0 Mask bit is active low 0 1016 D16 D32 Port C mask This register masks C 31 16 Mask bit is active low 0 1018 D16 D32 Gate signal width This number X 0004 represents a multiple of the selected delay line period see detailed description Ox101A D16 D32 Port C control When the port C is X 0000 configured to be an output under register control see MODE register the status of C 15 0 is controlled by this register 0x101C D16 D32 Port C control When the port is X 0000 configured to be an output under register control see MODE register the status of C 31 16 is controlled by this register Ox101E D16 D32 It configures the behaviour of the X 0008 system Default 0x 1020 D16 D32 MODE 1 0 DELAY SEL Register Mode MODE
9. 3 UNIT MODB 0x1022 D16 D32 uu i 0 Coincidcence Unit 1 Register MODE 4 OPERATOR 0x1028 D16 D32 0x102A D16 D32 0 C AND B MODE S PULSE MODE See Description D16 D32 This register is available to test read X 5A5A and write to a register Only Bit 0 CONTROL 0 15 X 0000 used in this reference design It can be used to select G output level 0 TTL T NIM With A395D X 0000 bitl data bus direction 0 OUT 1 IN bitO2mezzanine output level 0 TTL 1 NIM bit15 2 reserved D port Data 15 0 X 0000 Read from IN Write to OUT D port Data 31 16 Read from IN Write to OUT With A395D X 0000 bit1 data bus direction 0 OUT 1 IN mezzanine output level 0 TTL 1 NIM bit15 2 reserved E port Data 15 0 X 0000 Read from IN Q Z 5 5 Q 2 o a a N a 2 4 o a t ah 5 GATEWIDTH C_CONTROL_L C_CONTROL_H SCRATCH G CONTROL D_DATA_L D_DATA_H E CONTROL H 0 102 D16 D32 E DATA L 0x1030 D16 D32 Write to OUT E DATA 0x1032 D16 D32 E port Data 31 16 X 0000 Read from IN NPO Filename Number of pages gt Page 00117 04 V 1495 MUTx 10 V1495 REVIO 40 29 Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose
10. Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 20 07 2010 10 TABLE OF CONTENTS 1 GENERAL DESCRIPTION oi 6 Wils OVERVIEW AER 6 12 BEOCK DIAGRAM eher rere Ie EE 7 2 TECHNICAL SPECIFICATIONS 8 2 1 8 22 POWER REQUIREMENTS 8 23 FRONI PANEL DISPLAYS Die ye e 8 24 50 9 2 5 MOTHERBOARD 10 26 62 VENTE TERR TEE coseesvacdecsseacaeess 10 2 7 MEZZANINE BOARDS nn nnns 11 2 8 FRONT PANEL CONNECTOR
11. Purpose VME Board 20 07 2010 10 The sequence to be followed is Step 1 write 0 1 the PDL CONTROL register Step2 update the dip switches value B updating of PDL1 delay via switch Step 1 write 0 5 in the PDL_CONTROL register Step 2 update the dip switches value C updating of PDLO delay via VMEbus Step 1 write 0x3 the PDL CONTROL register Step2 write the delay value in the PDL DATA register D updating of PDL1 delay via VMEbus Step 1 write 0 7 in the CONTROL register Step2 write the delay value in the PDL DATA register GATE WIDTH USING Delay Line Oscillators The GATEWIDTH register can be used to set the gate signal width on the G port see Delay Unit using DLOs see 5 5 6 5 5 5 Delay Unit using PDLs The following diagram shows the implementation of the DELAY UNIT using the one of the two programmable delay lines PDL available on the boards MONOSTABLE 360 ns pulse Fig 5 4 Delay Unit with PDLs NPO Filename Number of pages gt Page 00117 04 V 1495 MUTx 10 V1495 REVIO 40 33 Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 20 07 2010 10 NPO Tmon gt lt Tp COINC 7 1 PuxouUT _ sf PDL_PULSEOUT STARTDELAY STOPDELAY Fig 5 5 PDLs Delay line timing The pulse width generated using PDLs Tp can be adjusted setting t
12. f F Port A 32 IN ECL LVDS Port B 32 IN ECL LVDS Port C 32 OUT LVDS Fig 5 1 USER FPGA block diagram The Demo project is available at the download section of the webpage http www caen it nuclear product php mod V1495 and its source code can be adapted by updating the coin_reference vhd file Filename Number of pages Page 00117 04 1495 0 10 V1495_REV10 40 21 Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 20 07 2010 10 5 1 1 Advanced Demo applications Moreover in order to help the Users to develop advanced software applications for the V1495 CAEN provides several demo applications four applications are available so far freely available both source codes and documentation at the download section of the webpage http www caen it nuclear product php mod V1495 These applications do not use the HAL Hardware Abstraction Layer like the built in demo in order to help the hardware interfacing This is done in order to offer to the end user a further degree of freedom The applications implement the following capabilities Demo 1 o Gate Pattern AND OR function between I Os Single Read Write access on VME e Demo 2 o Pattern Recorder FIFO PLL Single Read Write access on VME Block Transfer Mode BLT
13. input range 4 to 5V Fail Safe input feature LVDS Robinson Nugent P50E A395B 32 Output Direct 100 250MHz 068 P1 SR1 TG type ohm 34434 pins Robinson Nugent P50E A395C 32 Output Direct ECL 300MHz 068 P1 SR1 TG type 34434 pins TTL IN Direct NIM TTL TTL OUT Direct selectable selectable NIM IN Invert 50 Rt NIM OUT Direct selectable A395D 8 250MHz LEMO 00 16bit resolution A395E 8 Output Analog 5V 10kQ RL LEMO 00 4V 2000 RL NPO Filename Number of pages Page 00117 04 V 1495 MUTx 10 V1495 REVIO 40 10 CAEN Document type Title User s Manual MUT Mod V1495 General Purpose VME Board NPO 2 7 Revision date Revision 20 07 2010 10 Mezzanine boards installation In order to install one A395x series mezzanine board on the V1495 motherboard it is necessary to follow these steps Remove unscrew the metal cover one at will Plug mezzanine board into the 100 pin connector on the motherboard Fix the mezzanine board with the screws WARNING A Mounting Option is necessary in order to install three A395C mezzanine boards on the V1495 see table 1 1 2 8 Front panel connector cabling Motherboard I O sections A B C and A395A A395B and A395C Mezzanine boards feature the Robinson Nugent P50E 068 P1 SR1 TG multipin connector whose pin set is shown in the following figure N C N C N C N C CH31
14. local bus FPGA Bridge manages also the programming via VME of the FPGA User FPGA User which manages the front panel I O channels FPGA User is provided with a basic firmware which allows to perform coincidence matrix I O register and asynchronous timers functions FPGA User can be also free reprogrammed by the user with own custom logic function see 5 1 It is connected as slave to the FPGA Bridge via CAEN Local Bus whose protocol shall be used in order to communicate with the FPGA Bridge and thus with the VME bus The I O channel digital interface is composed by four sections A B C G placed on the motherboard see 1 2 The channel interface can be expanded in the D E F sections by using up to 3 mezzanine boards see 2 6 and 2 7 which can be added choosing between the five types developed in order to cover the I O functions and the ECL PECL LVDS NIM TTL signals and 16bit DAC see 1 2 The maximum number of channels can be expanded up to 194 The FPGA User can be programmed on the fly directly via VME without external hardware tools without disconnecting the board from the set up without resetting it or turning the crate off allowing quick debug operations by the developer with his own firmware A flash memory on the board can store the different programming file which can be loaded to the FPGA User at any moment Four independent digital programmabl
15. register access is at user address space Active high V1495 Front Panel Ports PORT A B C G INTERFACE A_DIN IN 32 In A 32 x LVDS ECL B_DIN IN 32 In B 32 x LVDS ECL C_DOUT OUT 32 Out C 32 x LVDS NIM G_DIR OUT 1 Output Enable 0 gt 1 gt Input G_DOUT OUT 2 Out G LEMO 2 x NIM TTL G_DIN IN 2 In G LEMO 2 x NIM TTL V1495 Mezzanine Expansion Ports PORT D E F INTERFACE D IDCODE IN 3 D slot mezzanine Identifier D LEV OUT 1 D slot Port Signal Level Select the level selection depends on the mezzanine expansion board mounted onto this port DIR OUT 1 D slot Port Direction D DIN IN 32 D slot Data In Bus D_DOUT OUT 32 D slot Data Out Bus E_IDCODE IN 3 E slot mezzanine Identifier E_LEV OUT 1 E slot Port Signal Level Select the level selection depends on mezzanine expansion board mounted onto this port E_DIR OUT 1 E slot Port Direction E_DIN IN 32 slot Data In Bus E_DOUT OUT 32 E slot Data Out Bus F_IDCODE IN 3 F slot mezzanine Identifier 2 The I O channels of the A395D Mezzanine board are mapped on the 8 LSB of D DIN D DOUT E DIN E DOUT F DIN F DOUT signals NPO Filename Number of pages gt Page 00117 04 V 1495 MUTx 10 V1495 REVIO 40 23 Tools for Discover Document type Title Revision date Revision User s Manua
16. via jumper Standard or Backup FPGA VME Program Circuit P VME BUS VME FPGA 4 lt 5 FLASH lt lt FW SEL Fig 3 4 FPGA VME diagram Filename Number of pages 00117 04 1495 0 10 V1495_REV10 40 Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 20 07 2010 10 3 2 2 FPGA USER The microcontroller provides the firmware uploading at board s power on The flash memory contains one firmware image only Standard FPGA USER Program Circuit 2 o m FPGA VME lt gt gt A FPGA USER a FLASH C pu Fig 3 5 FPGA USER diagram FPGA VME aim is to handle the operation of FPGA USER which be programmed on the fly i e without turning off the system thus allowing quick debug operations by the Developer Register implemented on FPGA VME allows the following operations e FPGA USER flash memory programming FPGA USER updating NPO Filename Number of pages Page 00117 04 V 1495 MUTx 10 V1495 REVIO 40 16 Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 20 07 2010 10 4 VME Interface FPGA VME Firmware provides the following features Both 16 and 32 bit data mode accesses to F
17. 00117 04 V 1495 MUTx 10 V1495 REVIO 40 35 Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 20 07 2010 10 NPO COINC DLOx_GATE DLOx OUT I LI LI LI 1 PULSE STARTDELAY DELAY COUNTER 1 y 2 Y 3 4 STOPDELAY PULSE_OUT Fig 5 7 DLOs Delay line timing When a coincidence occurs leading edge of COINC signal the STARTDELAY signal becomes active high STARTDELAY enables the oscillator on external delay line DLOx selected via MODE register At the same time the DELAY_COUNTER is enabled The PULSE signal leading edge increases the counter until the value set via GATEWIDTH register is reached The PULSE signal corresponds in this reference with the selected PDL output On the first PULSE leading edge after the coincidence PULSE OUT is activated high and is kept high until a time GATEWIDTH times the period of the selected DLO The period in this case is constant The maximum pulse width is limited by the GATEWIDTH counter in the case of this reference design the GATEWIDTH register is 16 bit wide so a maximum width of 65536 Td Td is the intrinsic delay of the selected DLO Filename Number of pages Page 00117 04 V 1495 MUTx 10 V1495 REVIO 40 36 Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpo
18. 495 BLOCK 7 FIG 2 1 MODEL V1495 FRONT PANEL WITH A395A B C PIGGY BACK BOARDS 9 FIG 2 2 MULTIPIN CONNECTOR PIN ASSIGNMENT 11 FIG 2 3 MOD A967 CABLE ADAPTER icceswsevesaeisckoraduseveroanvebnenchsevedashichoesdsvatscesnarsesldniatedostieastesidenavensssicernaschsevanhes 12 FIG TIMERS d c e eR hee ne Ee PL Ee CER EXE EL he e ne EE E e COR 14 EG 3 2 GATE PULSE EXAMPLE EE EE 14 Fic 3 3 TIMER2 AND TIMER3 USED TOGETHER FOR HANDLING 8 15 FIG 3 4 FPGA 020 0 0 15 FIG 3 5 FPGA USER ttt ese E E EEEE eset esee 16 5 1 USER FPGA BLOCK DIAGRAM eene e e e enn n nnn nnn nnn nnn 21 FIG 5 2 FRONT PANEL PORTS INTERFACE 8 28 5 3 PDL CONTROL BIT FIELDS eee fuese eese 32 FIG 5 4 DELAY UNIT WITH 5 nneneses ese sse ese ese sse eset ese etes eset esee stesse 33 FIG 3 5 PDLS DELAY LINE TIMING eere ere 34 FIG 3 6 DELAY UNIT WITH DEOS 35 Filename Number of pages Page 00117 04 V1495 MUTx 10 V1495 REVIO 40 4 ls for Discovery Documen
19. 5 front panel with 395 piggy back boards NPO Filename Number of pages Page 00117 04 1495 0 10 V1495 REVIO 40 9 ls for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 20 07 2010 10 2 5 Motherboard Specifications The Mod V1495 Motherboard is composed by four I O sections see 1 2 described in the following table Table 2 2 V1495 Motherboard I O sections Board No of Ch Direction Logic Signal Bandwidth Front panel connector LVDS ECL PECL single ended TTL optional 1100hm Rt Robinson Nugent P50E A B 32 Input Direct Extended 200MHz 068 P1 SR1 TG type Common Mode 3434 pins input range 4 to 5 Fail Safe input feature LVDS Robinson Nugent P50E 32 Output Direct 068 P1 SR1 TG type 100 RI 250MHz 84434 pins TTL IN Direct NIM TTL TTL OUT Direct selectable selectable NIM IN Invert 50 Rt NIM OUT Direct selectable 250MHz LEMO 00 2 6 Mezzanine Specifications The five I O Mezzanine boards developed so far are described in the following table Table 2 3 V1495 Mezzanine boards Board No of Ch Direction Logic Signal Bandwidth Front panel connector LVDS ECL PECL single ended TTL optional 110 Rt Robinson Nugent P50E A395A 32 Input Direct Extended 200MHz 068 P1 SR1 TG type Common Mode 34 34 pins
20. 7 04 V 1495 MUTx 10 V1495_REV10 40 13 Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 20 07 2010 10 Tperiod gt __Iwidth 0 Tset Toffset Tdly Toffset Tset Toffset 30 2ns Tset SETBINARY Ins STARTx WIDTHMIN 3205 recommended 22ns absolute min STARTx PERIODMIN 640ns recommended 46ns absolute min Fig 3 1 Timers diagram The use of STARTx signals with timing shorter than those recommended is possible although the linearity on the set delay scale is no longer guaranteed 3 1 2 Timer2 Timer3 Each timer is made up of one digital circuit which produces a typical fixed time base with 10ns period and 50 duty cycle These timers are proposed for generating any Gate pulse gt 10ns with a 10ns step The following figure shows an example of a Gate generation made with Timer2 and n 3 PULSE width ISTART 2 c Teny a puse2__ LIT LI L IL Indy lt COUNT 2 COUNT 0 COUNT 1 COUNT 2 Fig 3 2 Gate pulse example FPGA USER drives a STARTx pulse and after Ten time FPGA USER will receive a PULSEx clock signal A counter with clock PULSEx implemented in the FPGA USER allows to generate a pulse with programmable duration It is possible to reduce to one half 5 5 the counter step by advancing the counter both sides of PULSEx Since the circu
21. D CONTROL E CONTROL or F CONTROL depending on which port the mezzanine card is plugged into e Read Write data from to mezzanine inputs read write register x DATA DATA x D E or depending on which port the mezzanine card is plugged into The mezzanine port directions can be set through x CONTROL register therefore if CONTROL 1 0 all mezzanine card ports are output all inputs when such bit is set to 1 Moreover with A395D mezzanine the ports can be individually used also as inputs even if the common I O direction is set to output since the A395D output stage has recessive state logical level 0 Therefore if x CONTROL 1 is set to 0 all ports outputs but for instance x DOUTR 0 is driven to 0 then it is possible to read port 0 value into corresponding x DIN 0 bit in this case 50Ohm termination on corresponding port through internal switches must be enabled NPO Filename Number of pages gt Page 00117 04 V 1495 MUTx 10 V1495 REVIO 40 30 Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 20 07 2010 10 5 5 REGISTER DETAILED DESCRIPTION NPO 5 5 1 V1495 Front Panel Ports Registers PORT A B C G The Front Panel ports A B C G can be configured and accessed using a set of registers The x MASK y x can be A B C y can be or H registers can be used to selectively mask a bit of a port Each st
22. Demo 3 o DAC Expansion A395E DAC Single Read Write access on VME e Demo 4 o Gate amp Delay Generator AND OR function between I Os Expansion A395D Single Read Write access on VME Prog Free Running Delay Line PDL FDL 5 2 Reference Design Kit 5 2 1 V1495HAL The V1495 Hardware Abstraction Layer V1495HAL is a HDL module provided in Verilog format at netlist level in order to help the hardware interfacing NPO Filename Number of pages gt Page 00117 04 V 1495 MUTx 10 V1495 REVIO 40 22 Tools for Discover Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 20 07 2010 10 5 2 2 COIN_REFERENCE Design COIN REFERENCE design VHDL entity is the interface to the V1495HAL If the User wishes to use V1495HAL to develop his own application on the V1495 platform the VHDL entity must not be modified this means that signals names and function of the COIN_REFERENCE entity must be used as shown in the following table Table 5 1 COIN REFERENCE signals PORT NAME DIRECTION WIDTH DESCRIPTION GLOBAL SIGNALS NLBRES IN 1 Async Reset active low LCLK IN 1 Local Bus Clock 40 MHz REGISTER INTERFACE REG_WREN IN 1 Write pulse active high REG_RDEN IN 1 Read pulse active high REG_ADDR IN 16 Register address REG_DIN IN 16 Data from CAEN Local Bus REG_DOUT OUT 16 Data to CAEN Local Bus USR_ACCESS IN 1 Current
23. ME Board PORTA C STATUS DIN A AND gt A STATUS C Revision date Revision 20 07 2010 10 CONTROL PORT C C DOUT gt ANODE 2 B_DIN B STATUS UNIT MODE COINCIDENCE LOGIC COINC G_DOUT 0 DELAY G_DOUT 1 1 READ ONLY REG 1 WRITE ONLY REG A A PDLO 0100 DLO1 Fig 5 2 Front Panel Ports Interface Diagram The following table illustrates the the register map of the USER FPGA reference design COIN_REFERENCE Table 5 7 COIN_REFERENCE register map NAME ADDRESS DATA SIZING ACCESS NOTES A_STATUS_L 0x1000 D16 D32 Port A status This register reflects A 15 0 bit status A_STATUS_H 0x1002 D16 D32 Port A status This register reflects A 31 16 bit status B_STATUS_L 0x1004 D16 D32 Port B status This register reflects B 15 0 bit status B_STATUS_H 0x1006 D16 D32 Port B status This register reflects B 31 16 bit status C_STATUS_L 0x1008 D16 D32 Port C status This register reflects C 15 0 bit status C_STATUS_H 0 100 D16 D32 Port C status This register reflects C 31 16 bit status A_MASK_L 0 100 D16 D32 WO Port A mask This register masks X FFFF A 15 0
24. NTROL is used to Select target PDL for read write operations Enable delay update Select programming mode via VME register or by on board switches The PDL CONTROL bit fields are shown in the following figure ESEGIES EQEESERESESERESESEZ ETERE lL WR PDL DIR gt PDL_SEL Fig 5 3 PDL_CONTROL bit fields PDL_WR 1 enables the updating of the PDL delay value in this way the delay value set either via dip switch or via PDL_DATA register is automatically loaded By setting this bit to 0 the delay value cannot be changed PDL_DIR allows to select the source of data for PDL programming 0 the selected PDL has as delay value on its parallel programming bus the dip switch value 1 the selected PDL has as delay value on its parallel programming bus the PDL_DATA register 8 LSB PDL SEL allows to select one of the PDL s PDLO and PDL1 for read write operations PDL DATA register is used to Write the delay value for the next delay update via VMEbus Read the on board switch status Examples updating of PDLO delay via switch the default value in the PDL CONTROL allows to update the delay directly via dip switch just after the board turning ON each change in the dip switch status set immediately a new delay value NPO Filename Number of pages gt Page 00117 04 V 1495 MUTx 10 V1495 REVIO 40 32 Document type Title Revision date Revision User s Manual MUT Mod V1495 General
25. PGA User memory space Base 0 1000 0 7 32 bit Block transfer BLT from FPGA User VME address space Base 0 0000 OxOFFC is reserved for BLT from FPGA User any BLT access to such space translates into a read access to Local Bus address 0x0000 V1495 DEMO2 package see S 5 6 provides an example of BLT handling in User FPGA N B FPGA VME Firmware releases older than 1 0 do not support 32bit single accesses BLT accesses 4 1 Register address map The Address map for the Model V1495 is listed in Table 4 1 All register addresses are referred to the Base Address of the board i e the addresses reported in the Tables are the offsets to be added to the board Base Address Table 4 1 Address Map for the Model V1495 Base 0 0000 USER FPGA Block transfer A24 A32 D16 D32 BLT R Base 0x8000 reserved A24 A32 016 032 Base 0x8002 reserved A24 A32 016 032 Base 0x8004 reserved 24 2 016 032 Base 0x8006 reserved 24 2 D16 D32 Base 0x8008 Geo Address_Register A24 A32 016 032 Base 0 800 Module Reset A24 A32 D16 D32 Base 0x800C Firmware revision A24 A32 016 032 Base 0x800E Select VME FPGA Flash A24 A32 D16 D32 Base 0x8010 VME FPGA Flash memory A24 A32 016 032 Base 0x8012 Select USER FPGA Flash A24 A32 D16 D32 Base 0x8014 USER FPGA Flash memory A24 A32 016 032 Base 0 8016 USER FPGA Configuration A24 A32 016 032 Base 0x8018 Scratch16 24 2 016 032 Ba
26. Technical Information Manual Revision n 10 20 July 2010 MOD V1495 GENERAL PURPOSE VME BOARD NPO 00117 04 V1495 MUT 10 CAEN will repair or replace any product within the guarantee period if the Guarantor declares that the product is defective due to workmanship or materials and has not been caused by mishandling negligence on behalf of the User accident or any abnormal conditions or operations CAEN declines all responsibility for damages or injuries caused by an improper use of the Modules due to negligence on behalf of the User It is strongly recommended to read thoroughly the CAEN User s Manual before any kind of operation 4 CAEN reserves the right to change partially or entirely the contents of this Manual at any time and without giving any notice Disposal of the Product The product must never be dumped in the Municipal Waste Please check your local regulations for disposal of electronics products MADE IN ITALY We stress the fact that all the boards are made in Italy because in this globalized world where getting the lowest possible price for products sometimes translates into poor pay and working conditions for the people who make them at least you know that who made your board was reasonably paid and worked in a safe environment this obviously applies only to the boards marked MADE IN ITALY we can not attest to the manufacturing process of third party boards ls for Discovery
27. UARTUSII PROJECT REV 2 O FIT v1495usr demo v1495usr demo Compilation Report Flow Summary Fie Edit Project Assignments Processing Tools Window Help 5 Ba 4 22 v1495usr_demo XL EZE Dr Yr Project Navigator ES amp Compilation Report Flow Summary Entity Memo Ba C lation Re Cyclone 20 400 SB id 02 860 w1495ust demo 0 Flow summary Flow Settings BES Flow Non Default Global Settir BES Flow Elapsed Time n amp B Flow Log a 0 Analysis amp Synthesis Flow Status Tue Jun 22 11 58 42 2n GA Fitter Quartus Il Version 8 0 Build 215 05 29 2008 SJ Full Version Assembler Revision Name 149 amp 1 Timing Analyzer Top evel Entity Name v1495usr_demo 1 gt Family Cyclone y Hierarchy B Files 2 Design Units Device EP1C20F400C6 gt gt gt gt Timing Models Final E Met timing requirements Yes Module Time 9 Total logic elements 918 20 060 5 Full Compilation 00 00 46 Total pins 275 301 91 Analysis amp Synthesis 00 00 14 Total vitual pins 0 Fitter aed Total memory bits 0 294412 0 essences 00 00 05 DSP block Sbit elements 0 Classic Timing Analyzer 00 00 03 Total PLLs 0 2 0 Total DLLs 0 lt gt Ls Message Tel Console Warning Found invalid timing assignments se
28. VME Board 20 07 2010 10 NAME ADDRESS DATA SIZING ACCESS NOTES DEFAULT PT F CONTROL L 0 1034 D16 D32 RW With A395D X 0000 bit1 data bus direction 0 OUT 1 IN mezzanine output level 0 2 TTL 1 NIM bit15 2 reserved DATA 0 1038 D16 D32 RW F port Data 15 0 X 0000 Read from IN Write to OUT F_DATA_H 0x103A D16 D32 RW F port Data 31 16 X 0000 Read from IN Write to OUT REVISION 0 103 D16 D32 RW Firmware revision For the register content for release 1 0 is X 0100 CONTROL 0 103 D16 D32 RW Bit 0 allows to either set the PDL 70001 delay 0 delay set via VMEbus content of PDL_DATA register 1 delay set via on board switches switch value is content of PDL_DATA register bit15 1 reserved D_IDCODE 0x 1042 D16 D32 Read Slot D mezzanine ID Code ID Code is X 0007 if no mezzanine is plugged E_IDCODE 0x 1044 D16 D32 Read Slot E mezzanine ID Code ID Code is X 0007 if no mezzanine is plugged F_IDCODE 0x 1046 D16 D32 Read Slot F mezzanine ID Code ID Code is X 0007 if no mezzanine is plugged 5 4 1 Mezzanine board interfacing The Reference Design can be used to interface with A395A B C D mezzanines interface with A395E is not supported see 5 1 1 when one mezzanine board is plugged into either D E F port then it is possible to e Select I O Direction logical level NIM TTL through x CONTROL registers
29. allows to read write into the USER FPGA registers which can be accessed via VMEbus The COIN REFERENCE module shows how to implement a set of registers The following table shows the registers map as it is provided Each register address is coded via constants in V1495pkg vhd file This file allows to modify the registers map all registers allow D16 D32 accesses write only read only or read write Registers default NPO 00117 04 V 1495 MUTx 10 Filename V1495 REVIO Number of pages gt Page 40 24 Tools for Discover Document type User s Manual MUT Revision date Revision 20 07 2010 10 Title Mod V1495 General Purpose VME Board value is the value after a reset for write only and read write registers read only registers return the status of the signals read by the FPGA and have no default value The Register Interface allows to abstract the VME registers access The User can access a simple register interface two signals REG_WREN e REG_RDEN are pulses with a one clock cycle duration which enables respectively a write or a read access to a register REG_ADDR signal represents the register address Writing into a register In case of a write operation into a register via VME the 16 bit datum is available through the REG_DIN signal The datum is guaranteed stable on the CLK leading edge where REG WREN is active The register access is valid only when USR_ACCESS is at logic level 1 Reading from a regi
30. atus register is split into two 16 bit register MASK L corresponds to MASK 15 0 while MASK H corresponds to MASK 31 16 There is not a MASK register associated with G port Each bit of the input ports A B mask registers are internally used in a logic AND operation with the corresponding bit of the port so it is an active low mask bit For instance when MASK L 0 is set to 0 the A 0 bit is internally masked logic 0 Each bit of the output port C mask register is internally used in a logic AND operation with the corresponding bit of the internal signal so it is an active low mask bit For instance when MASK _ is set to 0 the C 0 bit is masked output bit is stuck at 0 The x STATUS y x can be A B C y be or registers can be used to read back eack port bit Each status register is split into two 16 bit register STATUS_L corresponds to STATUS 15 0 while STATUS corresponds to STATUS 31 0 There is not a STATUS register associated with port The x STATUS vy register reflects the status of the unmasked input and output ports A control register C CONTROL is available to set the C port when the board is configured in I O register mode 5 5 2 V1495 Mezzanine Expansion Ports Registers PORT D E F The mezzanine expansion ports D E F can be configured and accessed using a set of registers In this reference design no mask register is implemented for the expansion ports The
31. d 20 07 2010 10 2 Technical specifications 2 1 Packaging The module is housed in a 6U high 1U wide VME unit The board is provided the VME P1 and P2 connectors and fits into both VME standard and V430 backplanes 2 2 Power requirements The power requirements of the modules are as follows Table 2 1 Model V1495 and mezzanine boards power requirements Power supply V1495 95 A395B A395C 950 A395E 5 1A 0 1A 0 1A 1 4A 1 1A 0 3A 2 3 Front panel displays The front panel refer to 8 2 4 hosts the following LEDs DTACK Color green Function it lights up green whenever a VME read write access to the board is performed USER Color green orange red Function programmable NPO Filename Number of pages gt Page 00117 04 V 1495 MUTx 10 V1495 REVIO 40 8 Is for Discover Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 20 07 2010 10 2 4 Front Panel Mod V1495 USER DTACK rom ooo lt r z rom oogc cr 2 GO G1 nou lt r GENERAL PURPOSE VME BOARD 2 1 Model V149
32. delay of the Gate signal synchronous but with step resolution higher than the system clock period this can be achieved by enabling the PLL in the USER FPGA and enter the reference clock on channel GO Asynchronous systems Input signals are not referred to a system clock As a consequence the gate signal will be generated without any time reference It is possible to use the implementation described above with the freedom of choosing the clock source between external or 40MHz internal The resulting Gate signal will have stable duration but with maximum position jitter equal to one clock period Such position jitter can be rejected by using the asynchronous timers present on the V1495 which allow to generate references synchronous with the occurred trigger 3 1 1 0 NPO Each timer is based on a programmable delay line FPGA USER drives a STARTx pulse and after the programmed delay it receives the return signal PULSEx The time difference between transmission and reception logic implementation inside the FPGA USER can be used to drive a gate signal The programming of the delay time can be done manually as binary value either 8 bit dip switches SW4 SW5 or via VME register with a 1ns step resolution max step delay 255ns The software setting has higher priority with respect to the dip switches The following figure shows a diagram of the timers usage Filename Number of pages Page 0011
33. e Ignored Timing Assignments report for detail Info Quartus II Classic Timing Analyzer was successful 0 errors 3 warnings Info Quartus II Full Compilation was successful 0 errors 47 warnings 2 gt 2 2 Processing 93 Extra Info Info 84 Warning 9 Critical Warming Suppressed 5 Flag 7 2 8 Message 0 of 656 4 21 2 E PEE AE CE NUM Fig 5 12 Quartus II compiling summary At this point an updated RBF file is generated in the project directory This file can be used for updating the firmware 5 7 Firmware upgrade It is possible to upgrade FPGA Bridge and the FPGA User firmware see 1 1 via VME by writing the Flash for this purpose download the software package and the CVUpgrade tool both available at http www caen it nuclear product php mod V 1495 The instructions are explained by the README text file included in the CVUpgrade folder NPO Filename Number of pages gt Page 00117 04 V 1495 MUTx 10 V1495 REVIO 40 40
34. e asynchronous timers are available for Gate Trigger applications It is possible to chain them for generating complex Gate Trigger pulse Table 1 1 Available items Code Description WV1495XAAAAA V1495 General Purpose VME Board WA395XAAAAAA A395A 32 LVDS ECL PECL input channels WA395XBAAAAA A395B 32 LVDS output channels WA395XCAAAAA A395C 32 ECL output channels WA395XDAAAAA A395D 8 NIM TTL input output channels WA395XEAAAAA A395E 8 channel 16Bit 5V DAC WPERS0149501 V1495 Customization 3 A395C Mounting Option WA967XAAAAAA A967 32 Channel Cable Adapter 1x32 to 2x16 WFW1495SCXAA FW1495SC 128 Channels Latching Scaler for V1495 Filename Number of pages Page 6 00117 04 1495 0 10 V1495_REV10 40 ls for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 20 07 2010 10 1 2 Block Diagram BRIDGE lt gt VME interface 8 bit USER PROGRAMMABLE FPGA FW LOADING optional v LPT FLASH USER FPGA Asyn Timers 4 Fig 1 1 Mod 1495 Block Diagram NPO Filename Number of pages Page 00117 04 1495 0 10 V1495 REVIO 40 7 CAEN Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Boar
35. ed according to the description provided with the manual in order to modify the card functionalities The tool provides a complete pinout of the FPGA it is also enabled to generate the file type of programming RBF format used for the flash programming This software tool requires the Quartus Il Web Edition rel 8 0 and newer and can be freely downloaded the download section of the webpage http www caen it nuclear product php mod V1495 Quartus 11 manual is available at www altera com website The following instructions require the User knowledge of the typical project flow for generating the firmware for an ALTERA FPGA Once the Quartus II Web Edition is installed on the PC host in order to open the new project launch the program then select in the upper toolbar the path File gt Open Project gt FIT Filename Number of pages Page 37 00117 04 V 1495 MUTx 10 V1495_REV10 40 Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 20 07 2010 10 Open Project Fig 5 8 Quartus II project browser browse the file project v1495usr_demo qpf Once the project is open the Project Navigator shows the following information There are 5 VHDL files and a Verilog netlist The reference design is included in the coin_reference vhd file The other files provide support to the project and shall not be midified by the developer HAL Hardware Abstract
36. ed to report the coincidence operator on A and B port In this case the C port can be masked through a mask register C MASK A gate pulse is generated on G port when data patterns on input ports A and B satisfy a trigger condition The trigger condition implemented in this reference design is true when a bit per bit logic operation on port A and B is true The logic operator applied to Port A and B is selectable by means of a register bit MODE Register Bit 4 If MODE bit 4 is set to 0 an AND logic operation is applied to corresponding bits in Port A and B i e 0 AND B 0 A 1 AND 1 etc In this case a trigger is generated if corresponding A and B port bits are 1 at the same time If MODE bit 4 is set to 1 an OR logic operation is applied to corresponding bits in Port A and B i e A 0 OR B 0 A 1 OR B 1 etc In this case a trigger is generated if there is a 1 on one bit of either port A or B Port A and B bits can be singularly masked through a register so that a 1 on that bit doesn t generate any trigger Expansion mezzanine cards can be directly controlled through registers already implemented in this design The expansion mezzanine is identified by a unique identification code that can be read through a register Filename Number of pages gt Page 00117 04 V 1495 MUTx 10 V1495_REV10 40 27 Tools for Discovery Document type User s Manual MUT Title Mod V1495 General Purpose V
37. ggy back identification All E LEV Set the logic level Output Bidirectional F F DIR Selects direction Bidirectional port F DIN Read the logic level Input Bidirectional F DOUT Set the logic level Output Bidirectional IDCODE Read IDCODE for piggy back identification All F LEV Set the logic level Output Bidirectional Filename Number of pages gt Page 00117 04 V1495 MUTx 10 V1495 REVIO 40 25 Tools for Discover Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 20 07 2010 10 5 3 5 PDL Configuration Interface PDL Configuration Interface signals are as follows Table 5 3 PDL Configuration Interface signals PDL WR OUT 1 Write Enable PDL_SEL OUT 1 PDL Selection 0 gt PDLO 1 gt PDL1 PDL_READ IN 8 Read Data PDL_WRITE OUT 8 Write Data PDL_DIR OUT 1 Direction 0 gt Write 1 gt Read 5 3 6 Delay Lines and Oscillators I O Delay Lines and Oscillators signals are as follows see also 5 5 5 and 5 5 6 Table 5 4 Delay Lines and Oscillators signals PDLO_OUT IN 1 Signal from PDLO Output PDL1_OUT IN 1 Signal from Output DLOO OUT IN 1 Signal from DLOO Output DLOI OUT IN 1 Signal from DLO1 Output PDLO_IN OUT 1 Signal to PDLO PDL1_IN OUT 1 Signal to Input DLOO_GATE OUT 1 Signal to DLOO Input DLO1_GATE OUT 1 Signal to DLOI Input 5 3 7 SPARE Interface These signals a
38. he PDL delay using either on board dip switches or through register When a coincidence occurs leading edge of COINC signal the STARTDELAY signal becomes active high STARTDELAY triggers a monostable in order to generate a pulse with a duration large enough to ensure maximum linearity performance of the This value should be more than 320 ns PDL see 3D3428 component datasheet The selected value in the reference design is 360 ns The PDL_PULSEOUT internal signal is generated as the logic OR of PDL_IN and PDL_OUT so generating a pulse whose width is proportional to the PDL actual delay The PDL_PULSEOUT signal falling edge is used to reset the flip flop state The pulse width Tp is Tp Tpd Tpf Where is the delay of the selected PDL programmable via VME or by on board dip switches whichever mode is enabled Tpf is the delay introduced by the FPGA pad and internal logic The maximum pulse width is limited by the PDL maximum delay in this case 5 5 6 Delay Unit using DLOs The following diagram shows the implementation of the DELAY UNIT using two oscillators based on delay lines DLO present on the board Filename Number of pages Page 00117 04 V 1495 MUTx 10 V1495 REVIO 40 34 Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 20 07 2010 10 DLOx DELAY COUNTER Fig 5 6 Delay Unit with DLOs NPO Filename Number of pages Page
39. ion Layer is implemented on the netlist Verilog v1495usr_hal vqm Project Navigator C3 Files B pod JSRC v1485usr demo v1485usr pkg vhd we SRC v1495ust_demo coin_reference vhd 1 69 SRC v1495usr demo spare if rtl vhd PHD ISRC v1485usr demo tristate if rtl vhd abo SRC v1495usr demo v14Sb5usr demo vhd abe 1 49 demo v14S5usr hal vqm B Files d Design Units Fig 5 9 Quartus netlist The first time the project is launched the hierarchy includes only the name of the head of the project v1495usr demo At the end of the project flow the whole hierarchical structure of the project is shown NPO Filename Number of pages gt Page 00117 04 V 1495 MUTx 10 V1495 REVIO 40 38 CAEN Q Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 20 07 2010 10 NPO Quartus Il D luca Work 1495_USER_DEMO_QUARTUSII_PROJECT_REV_2_O FIT v1495usr_demo v1495usr demo File Edit View Project Assignments Processing Tools Window Help Kr ggelD e Project Navigator 400 495usr de QUARTUS II Module Progress Time 9 Version 8 0 Documentation Quartus II Tcl Console Message Al Location Locate ar Help press F1
40. it is completely digital no recovery time is necessary between one stop and the following start it is thus possible to generate multiple gate pulses with very high rate Timer2 and Timer3 can be used together for handling one single Gate pulse from multiple overlapped triggers NPO Filename Number of pages Page 00117 04 V 1495 MUTx 10 V1495 REVIO 40 14 Tools for Discovery Document type Title Revision date User s Manual MUT Mod V1495 General Purpose VME Board 20 07 2010 3 2 ISTART 2 Coo LJ LT bL IL COUNT 2 COUNT 0 COUNT 1 COUNT 2 ISTART 3 PULSE 3 COUNT 3 COUNT 0 COUNT 1 COUNT 2 GATE Fig 3 3 Timer2 and Timer3 used together for handling a Gate pulse FPGA Programming The programming of FPGA VME and FPGA USER are handled by two independent microcontrollers flash memory The updating of the firmware contained in the flash memories does not require the use of external tools and can be executed via VME The flash related to FPGA VME contains the firmware dedicated to the interface of the board with the FPGA USER and the VME bus such firmware is developed by CAEN The flash related to the FPGA USER contains the firmware developed by the User according to his own application requirements 3 2 1 FPGA VME NPO The microcontroller provides the firmware uploading at board s power on The flash memory contains two versions of the firmware which can be selected manually
41. l MUT Mod V1495 General Purpose VME Board 20 07 2010 10 PORT NAME DIRECTION WIDTH DESCRIPTION F_LEV OUT 1 F slot Port Signal Level Select the level selection depends mezzanine expansion board mounted onto this port F_DIR OUT 1 F slot Port Direction F_DIN IN 32 slot Data In Bus F DOUT OUT 32 F slot Data Out Bus PDL CONFIGURATION INTERFACE PDL WR OUT 1 Write Enable PDL_SEL OUT 1 PDL Selection 0 gt PDLO 1 gt PDL1 PDL_READ IN 8 Read Data PDL_WRITE OUT 8 Write Data PDL_DIR OUT 1 Direction 0 gt Write 1 gt Read DELAY LINES AND OSCILLATORS I O PDLO_OUT IN 1 Signal from PDLO Output PDL1_OUT IN 1 Signal from PDL1 Output DLOO OUT IN 1 Signal from DLOO Output DLOI OUT IN 1 Signal from DLO1 Output PDLO IN OUT 1 Signal to PDL1_IN OUT 1 Signal to PDL1 Input DLOO_GATE OUT 1 Signal to DLOO Input DLO1_GATE OUT 1 Signal to DLOI Input SPARE INTERFACE SPARE OUT OUT 12 SPARE Data Out SPARE IN IN 12 SPARE Data In SPARE DIR OUT 1 SPARE Direction LED INTERFACE RED_PULSE OUT 1 RED Led Pulse active high GREEN_PULSE OUT 1 GREEN Led Pulse active high 5 3 Interface description 5 3 1 Global Signals The nLBRES must be used as an asynchronous reset signal by the user An active low pulse will be generated when a write is done at the Module Reset register address see 4 1 The LBCLK is a 40 MHz clock It is the FPGA main clock 5 3 2 REGISTER INTERFACE The signals of the Register Interface
42. llow to set and read the status of SPARE pin present on the board Table 5 5 SPARE Interface signals SPARE_OUT OUT 12 SPARE Data Out SPARE_IN IN 12 SPARE Data In SPARE_DIR OUT 1 SPARE Direction 5 3 8 LED Interface These signals when active for one clock cycle allow to generate a blink of the relevant Led NPO Filename Number of pages Page 00117 04 1495 0 10 V1495 REVIO 40 26 Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 20 07 2010 10 5 4 NPO Table 5 6 LED Interface signals RED_PULSE OUT 1 RED Led Pulse active high GREEN PULSE OUT 1 GREEN Led Pulse active high Reference design description The reference design preloaded into the USER FPGA is given as a design guide It is a full functional application of the usage of the board as a concidence and or I O register unit This reference design give access to A B C G ports So no mezzanine expansion cards are needed in order to use this design The MODE register can be used to set the preferred operating mode When the board is switched on the default operating mode is I O Register mode In I O Register Mode C port is directly driven by the C CONTROL register The coincidence is anyway still active so that a pulse in generated on G port when a coincidence event is detected In Coincidence Mode the C port is us
43. se 0x8020 Scratch32 A24 A32 032 Base 0x8100 0x81FE Configuration ROM 24 32 016 032 EPGA VME Firmware releases older than Rel 1 0 allow 016 accesses to Base 0x0000 0x7FFC memory space NPO Filename Number of pages Page 00117 04 V 1495 MUTx 10 V1495 REVIO 40 17 Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 20 07 2010 10 4 1 1 Configuration ROM The following registers contain some module s information according to the Table 3 2 they are D16 D32 accessible read only OUI manufacturer identifier IEEE OUI Version purchased version Board ID Board identifier Revision hardware revision identifier Serial MSB serial number MSB Serial LSB serial number LSB Table 4 2 ROM Address Map for the Model V1495 checksum checksum eng obi checksum ego omo oero ons eta constant mes oe s oem es loeu mao loa me loe mo oem eo emmo fea These data are written into one Flash page at Power ON the Flash content is loaded into the Configuration ROM 4 2 GEO Address Register Base Address 0x8008 read D16 D32 The register content is the following Bit Function 15 5 reserved 4 0 ADDRESS 4 0
44. se VME Board 20 07 2010 10 5 6 Quartus Il Web Edition Project NPO N B the User Demo described in this section is suitable for boards running FPGA VME Firmware Rel 1 0 and newer In order to upgrade to FPGA Firmware Rel 1 0 applications for the FPGA User developed originally on V1495 boards running older firmware releases for example FPGA VME Firmware Rel 0 3 V1495 USER DEMO Quartusll project Rel 1 1 e Download the V1495 VME FPGA Firmware Rel 1 0 Upgrade FPGA Bridge firmware to Rel 1 0 via VME through the CVUpgrade tool see 5 7 In order to generate a firmware for the USER FPGA through Altera Quartus II software compatible with V1495 VME FPGA Firmware Rel 1 0 Download the V1495 USER DEMO Quartusll project Rel 2 0 and follow the steps described in this section e At this point applications developed under FPGA Firmware Rel 0 3 and older V1495 USER DEMO Quartusll project Rel 1 1 and older must be updated by incrementing all internal registers address by 0x1000 for instance becomes Ox10FC The FPGA User is programmable and customizable the module is delivered configured with the Demo application described by sections 5 1 through 8 5 4 1 The freely available Altera Quartus II it can be downloaded from the Altera Web site software must be used in order to generate a user firmware for the USER FPGA It includes the source of VHDL reference design which can be modifi
45. ster In case of a read operation from a register via VME the datum to be returned must drive the DOUT and be stable on the CLK leading edge where REG RDEN is active The register access is valid only when USR ACCESS is at logic level 1 5 3 3 V1495 Front Panel Ports PORT A B C G INTERFACE These signals allows to handle the interface with the motherboard ports A B C G A DIN and B DIN signals show the logic level of A and B ports 32 bit input only The output logic level on port C can be set via C DOUT signal The logic level on port G LEMO connectors can be set via G LEV signal the direction DIR the datum to be written or to be read DIN 5 3 4 V1495 Mezzanine Expansion Ports PORT D E F INTERFACE These signals allows to handle the interface with the piggy back board ports D E F The following table explains the available signals Table 5 2 V1495 Mezzanine Expansion Ports signals Port Signal Function Applies to D D DIR Selects direction Bidirectional port D DIN Read the logic level Input Bidirectional D DOUT Set the logic level Output Bidirectional D IDCODE Read IDCODE for piggy back identification All D LEV Set the logic level Output Bidirectional E E DIR Selects direction Bidirectional port E DIN Read the logic level Input Bidirectional E DOUT Set the logic level Output Bidirectional E IDCODE Read IDCODE for pi
46. ster generates a configuration reload The configuration image Standard will be uploaded into the USER FPGA as the IMAGE_SELECT bit is set to 1 default Filename Number of pages Page 00117 04 1495 0 10 V1495 REVIO 40 20 Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 20 07 2010 10 5 USER FPGA Demos and Programming 5 1 CAEN LOCAL BUS NPO Introduction The CAEN V1495 board houses a user customizable FPGA called USER FPGA the board is delivered with a reference design kit loaded on the USER FPGA the detailed description is available in sections 5 2 through 5 4 1 This application allows a virtual access to the User FPGA through Hardware Abstraction Layer see S 5 2 1 and shows examples of e delay lines use e A B C G see 2 5 ports interface functions e Read write capabilities from to expansion boards A395A A395B A395C A395D E F G ports The COIN REFERENCE reference design illustrates how to use the USER FPGA to implement a Coincidence Unit amp I O Register Unit This design can be customized by the user in order to adapt its functionality to his own needs ON BOARD DELAY LINES iL HARDWARE ABSTRACTION LAYER MEZZANINE CARD y ON ned MEZZANINE CARD N ON SLOT N 5 USER DEFINED LOGIC MEZZANINE CARD ON SLOT
47. t type Title Revision date Revision Users Manual V1495 General Purpose VME Board 20 07 2010 10 7 2 DLOS DELAY LINE TIMING incite iin dalek tbl 36 FIG 5 8 QUARTUS II PROJECT BROWSER c sccessssceeeesececsessececsneeceesaececeesaeeesaeeecsesueeecsesaececseaeeceesaeeecseaeeecseeaeenees 38 FIG 5 9 QUARTUS IL NETIST RUE 38 FIG 5 10 QUARTUS II HIERARCHICAL STRUCTURE sceicco 39 FIG 5 11 QUARTUS II COMPILER LAUNCHING ccccsssccecsscececssncecseaeeeceseaecesseeeecsesuececseneecesseeeceeaeeesessaeeessenseeees 39 FIG 5 12 QUARTUS II COMPILING 68 222 2 1402 2 0400 0000000000000000000000000000000000000000000 00 40 LIST OF TABLES TABLE AVAILABLE ITEMS 6 TABLE 2 1 MODEL 1495 AND MEZZANINE BOARDS POWER REQUIREMENTS ccce eene ennt nnne en 8 TABLE 2 2 V1495 MOTHERBOARD I O 8 2 1200 0000 00010100000 enne nennen tenter enne 10 TABLE 2 3 V 1495 MEZZANINE BOARDS eer rne rte Pe e E erre see Fea EP Ce Pee Feo Ese 10 TABLE 4 1 ADDRESS MAP FOR THE MODEL V 1495 enne 17 TABLE 4 2 ROM ADDRESS MAP FOR THE MODEL 1495
48. tributed by CAEN see 5 7 Select USER FPGA Flash Register Base Address 0x8012 read write D16 D32 This register allows USER FPGA configuration update stored into on board flash memory via VMEBUS The configuration can be updated by the user by means of the CVUpgrade software developed and distributed by CAEN see 5 7 Filename Number of pages Page 00117 04 1495 0 10 V1495_REV10 40 19 Tools for Discover Document type Title User s Manual MUT Mod V1495 General Purpose VME Board NPO 4 9 Revision date Revision 20 07 2010 10 VME FPGA Flash Memory Base Address 0x8010 read write D16 D32 This register allows the VME FPGA configuration update stored into on board flash memory via VMEBUS The configuration can be updated by the user by means of the CVUpgrade software developed and distributed by CAEN see 5 7 4 10 USER FPGA Flash Memory Base Address 0x8014 read write D16 D32 This register allows the USER FPGA configuration update stored into on board flash memory via VMEBUS The configuration can be updated by the user by means of the CVUpgrade software developed and distributed by CAEN see 5 7 4 11 USER FPGA Configuration Register Base Address 0x8016 read write D16 D32 Bit Function 15 1 reserved 0 SELECT This register allows the update of the USER FPGA configuration A write access to this regi
49. x DATA y x can be y can be or H registers can be used to read back each port bit Each status register is split into two 16 bit register D DATA L corresponds to D 15 0 while D DATA H corresponds to D 31 16 The expansion ports can be bidirectional In case the port is configured as an output the register value set the port value In case the port is configured as an input the register content reflects current port value A x CONTROL register x can be D E F is available to set the corresponding port direction and logic level selection 5 5 3 Delay Selection The selection of the asynchronous timer is made through the MODE register by means of the DELAY SEL bit MODE 1 0 The selection of the delay line is made according to the following table Filename Number of pages gt Page 31 00117 04 V 1495 MUTx 10 V1495_REV10 40 Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 20 07 2010 10 Table 5 8 Selection of the delay line MODE 1 MODB 0 DELAY LINE 0 0 PDLO 0 1 PDLI 1 0 DLOO 1 1 DLOI 5 5 4 PDL DELAY VALUE SETTING AND READBACK The programmable delay lines chip available on board can be programmed with a specific delay using on board 8 bit dip switch SW6 for Delay 0 and SW5 for Delay1 on motherboard via VMEbus Two registers are available to configure PDLs PDL CONTROL PDL DATA PDL CO

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