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1. Decode PLD O Port B I O Port C 24 Combinatorial Outputs Device Security I O Port D d A106947 3 17 AN1426 APPLICATION NOTE PHYSICAL CONNECTION Connect your C167CR to the PSD4235 as shown in Figure 4 An 80 pin package is shown in the example The same connections can be used for all of the members of the PSD4000 family The JTAG programming channel LCD module latched address output and MCU I O signals are all optional This example design is similar to ST s DK4000 C167 Development kit available for purchase 149 US on the web www st com psm There are 11 unused PSD I O pins in this example Unused pins should be pulled to Vcc with a 100K resistor or tied to GND See Application Note 1153 for more information on the JTAG port Figure 4 Physical Connections C167CR and PSD4235 DATA BUS 2X16 LCD ue MODULE ADIOO e ADIO1 R W ADIO2 ADIO3 ADIO4 ADIO5 ADIO6 ADIO7 ADIO8 ADIO9 ADIO10 ADIO11 ADIO12 ADIO13 ADIO14 ADIOIS LA_Out 15 0 MCU I O SIGNALS 48 a RD __50 CI JTAG ISP X1XXXxX ASTIN j PE2 PSD4235 2B Connector RESET PES RR Al06948 FIRST DESIGN EXAMPLE ISP CAPABLE SYSTEM The first design example is only capable of ISP and not IAP It outlines the st2. Flash mem ory programming algorithms IAP loader code will be unavailable to the C167CR It is absolutely necessary to use an alternate memory array an independent memory that is not being programmed to store the IAP loader code A system designer must choose the type of alternate memory to store IAP loader code ROM SRAM FLASH or EEPROM each type has advantages and disadvantages This alternate memory may reside external to the MCU or on chip A top level view of an embedded IAP Flash memory system with external memory is shown in Figure 1 Figure 1 Embedded Flash System Capable of IAP 5 devices Main Flash Memory Host 512 KBytes Computer Alternate Memory PHN _for IAP Loader Code _ System SRAM Communication 2 KBytes Channel lt gt System I O Embedded System A106945 A Common Solution Without a PSD device implementing IAP with the C167CR and most other 16 bit MCUs can be difficult and time consuming For IAP some C167CR designers will use the fixed boot load er feature of the C167CR UART to download executable code into SRAM Then C167CR execution jumps to the SRAM to execute the remainder of the download process for programming the main Flash memory This can be a cumbersome and error prone exercise using re locatable code in volatile memory which is difficult to debug vulnerable to power outages and not supported by all emulators Additional
3. Simple C167CR PSD4235 Design OxFFFF C167 registers 0xF000 0xC000 i Unmapped 0xE800 XRAM 0xE000 PSD Control reg csiop 0xDF00 LCD Chip Sel Icd_e OxDE0O 0x8000 Unmapped Unmapped 0xD000 PSD SRAM rs0 0x4000 4Kx16 0xC000 PSD Secondary Flash Memory for boot code csboot0 1 8K x 16 Boot Configuration Al06952 Note 1 Only C167 page 0 is used for this demonstration no segmentation 64k max 2 Syscon and buscom0 used for memory access except for csiop and ice_e which use buscon1 Note the following about the sample memory map shown in Figure 5 m This simple example only requires 16 address bits m Only half 16 KBytes of the secondary Flash memory is used m The middle 32 KBytes of the memory map is unused m The upper 16 KBytes is allocated for the PSD SRAM rs0 the PSD control register csiop the LCD module and the C167CR registers and RAM The boot memory holds the following information m C167CR reset vector and initialization routines m C167CR interrupt vectors and service routines m I O management Since Figure 5 is asample memory map you may wish to change it To do so simply edit the chip select equations for the desired segments using the Design Assistant ky 5 17 AN1426 APPLICATION NOTE PSDsoft Express Design Entry Highlights of design entry will be given here This section is meant to show you just the essentials to get you going Here are
4. by implication or otherwise under any patent or patent rights of STMicroelectronics Specifications mentioned in this publication are subject to change without notice This publication supersedes and replaces all information previously supplied STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners 2002 STMicroelectronics All Rights Reserved STMicroelectronics group of companies Australia Brazil Canada China Finland France Germany Hong Kong India Israel Italy Japan Malaysia Malta Morocco Singapore Spain Sweden Switzerland United Kingdom United States STA 17 17
5. generated header files be sure to edit the generated C function source file to match the new header file names The three generated files may now be tailored and integrated into your compiler environment The file psd4235g2 h contains a define statement for each individual C function within the lt your_specified_name gt c file Edit psd4235g2 h and simply remove the comment delimiters from the define statement for each generated C function that you would like to be compiled with the rest of your C source code There are also coded examples available Click on the Coded Examples tab at the top of the C Code 10 17 Ta AN1426 APPLICATION NOTE Generation screen This sheet contains several examples that you may use as a basis for building your own C code application These are complete projects main functions and headers targeted toward var ious MCUs You may copy these files to some folder to browse them for ideas or cut and paste sections from the examples into your own MCU cross compiler environment Merge MCU Firmware with PSD Now that all PSD pins and internal configuration settings have been defined PSDsoft Express will create a single object file obj that is a composite of your firmware and the PSD configuration FlashLINK PSDpro and third party programmers can use this object file to pro gram a PSD device PSDsoft Express will create a file called EasyC167 obj for this design example During thi
6. il eal tl el TL wos ar orf oe JoJo re or o oo Jo frre fo eee 20 20 20 fas fet 73 75 Jas jac fan 53 fas 20 20 20 soosoo foo 20 20 jes 73 20 Jee jes 72 jes feo jer J21 fet 21 20 72 74 6F 20 joo j20 J20 j20 jz0 J20 ee f2o 20 20 ee J20 J20 Sans 129 20 20 20 joo 43 fer ee o7 72 J61 ra 7s Jec jer 7a 73 6F DK900 Eval Bd No need to fear need to fear i Uart demo Congratulat ions ISP Down 5 succ load If this is the first use of the PSDpro you ll need to designate the PSDpro as the device connected to your parallel port To do this click the SET H icon button at the top of the Conventional Programming screen and choose the PSDpro Then click on the H TEST icon to perform a test of the PSDpro and the PC par allel port After testing place a PSD4235G2 into the socket of the PSDpro and click on the Program icon The EasyC167 obj file is automatically loaded when this process is invoked The messaging of PSDsoft will inform you when programming is complete Note this window is also helpful even if you do not have a PSDpro device programmer Use this window to see where the Merge MCU Firmware utility has placed C167CR firmware within physical memory of the PSD For this design example click on the secondary PSD Flash memory icon Fb in the tool bar to see the C167CR vector at absolute MCU addresses 0001h and 0002h which translates to direct physica
7. NOTE Figure 2 Embedded Flash System Capable of IAP and ISP 2 devices Communication PSD4X35 Host Channel 512 KByte Main Flash JTAG Computer 16 bit Memory MCU MPU 32 KByte Secondary System Flash Memory VO 2 KByte SRAM Programmable Logic 0 Embedded System A106946 Let s take a quick look inside the Flash PSD4235 as shown in Figure 3 You can see the three indepen dent memory arrays which are selected on a segment basis when the proper MCU address is decoded in the Decode PLD The page register participates in memory decoding which greatly simplifies paging The MCU address data and control signals are routed throughout the chip and can be used within the general purpose PLD The GPLD has 24 combinatorial logic outputs for external device chip selects or general logic There are 52 I O pins that can be individually configured for many different functions A pow er management scheme can selectively shut down parts of the chip and tailor special power saving mech anisms on the fly The security feature can block access to all areas of the chip from a device programmer reader Finally the self contained JTAG ISP controller allows programming of all areas of the chip Figure 3 Top Level Block Diagram of PSD4235 PSD4235G2 MCU Address Data Control Bus 512 KByte Main Flash Memory 8 segments 32 KByte Secondary Flash Memory 4 segments 8 KByte SRAM VO Port A MCU
8. SZA CONTENTS See next page m Physical Connection m First Design Example ISP Capable System PSDsoft Express Design Entry m Enhanced Design Example m Conclusion m References July 2002 AN1426 APPLICATION NOTE Design Guide PSDsoft Express and PSD4235 Flash PSD4235 devices are members of a family of Flash memory based peripherals for use with embedded microcon trollers MCUs These programmable system devices PSDs consist of memory logic and I O When coupled with a low cost 16 bit MCU MPU the PSD forms a complete embedded Flash memory system that is 100 In System Programmable ISP and In Application Programmable IAP There are many features in the PSD silicon and in the PSDsoft development software that make using the PSD easy regardless of how much embedded design experience you have This document offers two designs using an ST PSD4235G2 and a Infineon C167CR MCU Note that a variety of 16 bit MCU MPUs can be used in place of the Infineon part Although the specifics of this document are based on the C167CR this document can be used as a guide for other MCU MPU applica tions The first design is a simple system to get up and running quickly for basic applications or to check out your prototype C167CR hardware The second design illustrates the use of enhanced features of PSD In System Programming ISP as applied to the C167CR You can start with the first design and migrate to the second as your f
9. ct a particular configuration for the MCU PSD interconnection Bus Widhe 16bit z Bus Mode Multiplexed Bus z ALE AS Activesevel High z Description for any selection above A RDA BHES MCU in 16 b mode Click OK Now you will be asked if you want to use the Design Assistant or a pre defined template Choose Design Assistant This exercise in the Design Assistant will help you become familiar with the design flow In the future you may choose to use a template which will make many of the choices for you based on your selection of MCU and PSD Pin Definitions You are immediately taken to the Pin Definitions screen which allows you to define each PSD pin function on a point and click basis Notice that some of the PSD pins that connect to the C167CR are already defined for you because their function is set You need only define the remaining pins We want to define the remaining pins based on the functional requirements presented in the sche 6 17 ki AN1426 APPLICATION NOTE matic Define the pins as follows m Set all the pins of Port A to MCU I O mode and label them MCUIOO to MCUIO7 m Define pb0 and pb1 as external active high chip selects Name pb0 Icd_e and pb1 rd_wr m Set all the pins on Port C to Address Input and give them the label a16 to a23 m The Port E pins peO to pe5 should be assigned to dedicated JTAG signals m Define the Port F and Port G pins to be Latch
10. e PSD configuration and MCU firmware Click OK to merge MCU firmware vath PSD ine This specification places firmware in PSD secondary Flash memory segments csboot0 and csboot1 PS Dsoft Express will extract any firmware that lies inside the file Tim n86 between MCU addresses 0000 and 3FFF and place it in PSD memory segment csboot0 1 Click OK to generate the composite object file EasyC167 obj Note the file Tim h86 will run on the DK4000 C167 development board from ST and display some messages on the LCD screen to indicate a successful ISP session For your own prototype project create a simple firmware file that configures your system hardware and per forms rudimentary tasks to check out your new hardware After your new hardware is proven you can add more code for advanced tasks including IAP of the PSD Flash memories Programming the PSD The EasyC167 obj file can be programmed into the PSD by one of three ways m The ST FlashLINK M JTAG cable which connects to the PC parallel port m The ST PSDpro device programmer which also uses the PC parallel port m Third party programmers from Stag Needhams and others See our web site at www st com psm for compatible third party programmers Programming with FlashLinK Connect the FlashLiNnK JTAG ISP cable to your PC parallel port Click the JTAG ISP box in the design flow window You will be asked how many devices are in your JTAG chain For this example select Onl
11. ed Address Out and give them the labels LA_out0 to LA_out15 where LA_out0 is assigned to pfO and LA_out15 to pg Your Pin Definition screen should now look like the screen capture below Pin Definitions CeeeeaeeeeeaeaeaeeaeeanaeaePeaeeaanaeaeeaezaeaeeeee i J i 2 J 3 pe a g J 3 oe 3 3 e A s y d s d Ld s s L d Ld s x Ld d s You can view a summary of your pin definitions by clicking the View button When you are satisfied that you have defined all the pins correctly click the Next gt gt button to be taken to the Page Register Definition screen Since we are not using paging in this example you can immediately click on the Chip Select Equations tab It is on this screen that you define your memory map for internal and external chip select Ti 7 17 AN1426 APPLICATION NOTE equations Chip Select Equations Your screen should be similar to the capture below E Design Assistant 5 x Page Register Definition Chip Select Equations For each chip select select a page number if memory paging is used the active address range and any Double cick any of the signal names additional signal qualifiers Ensure PSD page register bts have been defined if used here below to append the signal name to Signal qualifiers are listed in box on right Logically AND ae within same ine using amp symbol Create re apel nualan boae whare the logic OR by using nest line be
12. eps required to get a Flash memory C167CR system up and running quickly Basically the PSD s secondary Flash memory will be programmed with the JTAG ISP channel with code that will execute basic system tests and display some messages on the LCD The second design example takes advantage of concurrent memory operation and IAP using the main Flash memory in addition to the secondary Flash memory You should become famil iar with this first design before using the second A PSD4235G2 was used for this example However other members of the EasyFLASH family may be used instead with minor changes to the sample design See the PSD4000 series data sheets for a com parison of family members For this simple design we used a PSD4235G2 with the following memories m 512 KBytes main Flash memory broken into eight 64 KByte segments denoted fsi i 0 7 m 32 KBytes secondary Flash memory broken into four 8 KByte segments denoted csbootj j 0 3 m 8 KByte SRAM rs0 m 256 Byte PSD4235 configuration register csiop Note the PSD memory segments are defined using PSDsoft Express 4 4 17 AN1426 APPLICATION NOTE We ll use the PSD s secondary Flash memory to hold the boot code C167 interrupt vectors and common firmware functions For this example we ll execute from the PSD s secondary Flash memory only and not use the PSD s main Flash memory Let s examine the sample memory map in Figure 5 below Figure 5 Memory Map
13. ick on the rd_wr signal and type Gnd in the last column to keep the signal low at all times If the desire was to keep the signal high at all times you would have typed Vec instead You can click the View button at any time to see a Design Assistant summary Once you are satisfied with the results click the Done button Clicking Done starts a preliminary resource check of the information you have entered to ensure that there are no overlapping memory segments among other tests Any er rors encountered will be indicated Design Flow Once you have clicked on Done you are taken to the Design Flow window Use this win dow as your main navigational tool for PSDsoft Express Clicking on individual boxes within the flow di agram will invoke a process A box shadowed in red identifies the next process that needs to be completed The first three steps have been completed to this point If you invoke a process that invalidates other processes downstream the gray boxes indicate which processes must be invoked again and the red shadow indicates which process to invoke first The design flow should be in the following state ky 917 AN1426 APPLICATION NOTE Design Flow Specity Project Defne PSO and MOU Define PSD Pin Functions Conventional Programmers Additional PSD Settings Click on the Additional PSD Settings box This is where you may choose to set the security bit to prevent a device programmer f
14. l PSD addresses 80001h and 80002h respectively To see how all of your C167CR absolute addresses translated into direct physical PSD memory addresses view the report that PSDsoft generates under Reports from the main toolbar then s elect Address Translation Report Within the report the Start and Stop addresses are the absolute MCU system addresses that you have specified The addresses shown in square brackets are the direct physical addresses used by a device programmer to access the memory elements of the PSD in a linear fashion a special device programming mode that the MCU cannot access ENHANCED DESIGN EXAMPLE This section should be available in June 2000 It will detail how to use the PSD memories concurrently to perform IAP If you have any questions on this in the mean time contact an applications engineer at ap phelp wsiusa com CONCLUSION These examples are just two of an endless number of ways to configure the EasyFLASH PSD for your system Concurrent memories with a built in programmable decoder at the segment level offer excellent flex ibility The ability to expand your system does not require any physical connection changes as everything is configured internal to the PSD And finally the JTAG channel can be used for ISP anytime and anywhere with no participation from the MCU All of these features are crosschecked under the PSDsoft Express development environment to minimize your effort to design a Flash
15. low Use T symbol for logical NO List of chip selects Enter system memory information Page Hex Stat HexEnd Logical AND of Signal Quathers csiop Number Address Address more than one OK Ew E Eoo 3 Logical OR with next statement t5 M ee ii Logical OR with next statement cbaol F a i esboot3 ST PE EEEE P EN 1FFF hex locations max Let s start by defining the chip select for the internal SRAM rs0 Looking at the memory map of Figure 5 we see that 4 Kwords 8 KBytes of address space needs to be allocated to the PSD s internal SRAM So we enter the Hex Start Address of C000 and the Hex End Address of CFFF Here is a snapshot of what your screen should look like after you have entered the equations List of chip selects Enter system memory information gee acts Pane bay Logical AND of Signal Qualifiers more than one OK 7 E os om PO fe Now click on csiop and enter the equations according to Figure 5 Note the csiop is X 8 access Eligible signal qualifiers List of chip selects Enter system memory information Page Hex Start Micra End Logical AND of Signal Qualifiers Ei Number Address more than one OK 5m The boot code is stored in the secondary Flash memory in the lower 8 Kwords of address space from Oh 4 8 17 AN1426 APPLICATION NOTE to 3FFFh in csboot0 and csboot1 The equation for csbootO should be entered as follows Li
16. ly this meth od restricts the designer to using a UART to implement IAP A Better Integrated Solution Previously IAP required MCU participation to exercise a communication channel to implement a download to the main Flash memory However the PSD4235 offers an alternative to IAP This method ISP uses a built in IEEE 1149 1 JTAG interface which requires no MCU partici pation This means that a completely blank PSD can be soldered into place and the entire chip can be programmed in system using ST s FlashLINK JTAG cable 59 US and PSDsoft Express develop ment software available for free at www st com psm Figure 2 next page shows a two chip solution using a Flash PSD This system has ample main Flash memory a secondary Flash memory and SRAM All three of these memories can operate independently and concurrently meaning the MCU can operate from one memory while erasing writing the other The system has programmable logic expanded I O and design security Since the PSD4000 family is 100 ISP a blank PSD4235 can be connected to a ROM less MCU MPU and initially programmed through the JTAG port Therefore no IAP firmware needs to be written up front Just plug in the FlashLINK cable and begin programming memory logic and configuration This powerful new feature of the PSD4235 al lows immediate development of application code in your lab smart manufacturing techniques and easy field updates 4 2 17 AN1426 APPLICATION
17. memory based system capable of ISP and IAP 14 17 Ta AN1426 APPLICATION NOTE REFERENCES 3 PSD4000 Family Data Sheet 4 Application Note 1153 JTAG Information PSD8X lt XF for detailed use of the JTAG channel 5 DK4000 User Manual For information on the C167CR PSD4235G2 development kit 4 15 17 AN1426 APPLICATION NOTE Table 1 Document Revision History Date Rev Description of Revision Apr 2000 Document written AN069 in the WSI format 03 Jan 2002 1 4 Front page and back two pages in ST format added to the PDF file i References to Waferscale WSI and PSDsoft 2000 updated to ST ST and PSDsoft Express 25 Jul 2002 Document converted to ST format ky 16 17 AN1426 APPLICATION NOTE For current information on PSD products please consult our pages on the world wide web www st com psm If you have any questions or suggestions concerning the matters raised in this document please send them to the following electronic mail addresses apps psd st com for application support ask memory st com for general enquiries Please remember to include your name company location telephone number and fax number Information furnished is believed to be accurate and reliable However STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use No license is granted
18. rom examining or copying the contents of the PSD You can also click through the other sheets on this screen to set the JTAG USERCODE value and set sector protection on PSD Non Volatile memory segments as desired PSD Specific C Code Generation You can take advantage of the provided low level C code drivers for accessing memory elements within the PSD by clicking on the Generate C Code Specific to PSD box in the design flow window ANSI C code functions and headers are generated for you to paste into your C compiler environment Simply tailor the code to meet your system needs and compile C code generation can be performed anytime after a project is opened To generate ANSI C functions and headers simply specify the folder s in which you want the header files and the C source file to be written and name the C source file Select the categories of functions that you would like to include then click Generate Three files will be written to your specified folder s m lt your_specified_name gt c ANSI C source for all of the selected functions m psd4235g2 h ANSI C header file to define particular PSD registers m map4235g2 h ANSI C header file to define locations of system memory m elements Main Secondary Flash and PSD registers Notice that you do not have a choice to rename the two generated header files This is because those header files are specified by name within the generated C function source file If you edit the names of the
19. s merging process PSDsoft Express will input firmware files from your compiler linker in S record or Intel HEX format It will map the content of these files into the physical memory segments of the PSD according to the choices you made in the Chip Select Equations screen This mapping process translates the absolute system addresses inside firmware files into physical internal PSD addresses that are used by a programmer to program the PSD This address translation process is transparent All you need to do is type or browse the file names that were generated from your linker into the appropriate boxes and PSDsoft Express does the rest You can specify a single file name for more than one PSD chip select or a different file name for each PSD chip select It depends on how your linker has created your firmware file s For each PSD chip select in which you have specified a firmware file name PSDsoft Ex press will extract firmware from that file only between the specified start and stop addresses and ignore firmware outside of the start and stop addresses Click on Merge MCU Firmware in the main flow diagram First you will notice that PSDsoft Express will Fit your PSD configuration to the silicon architecture of the PSD After the fitting process is complete the Merging of MCU Firmware with PSD screen appears In the left column are individual PSD memory segment chip selects FSO FS1 and so on The next col umn shows
20. shown above to achieve minimum JTAG ISP programming times Refer to Application Note 1153 for details on six pins versus four To begin programming connect the JTAG cable to the target system power up the target system and click Execute on the JTAG screen The Log window at the bottom of the JTAG screen shows the progress There are optional choices available when the Properties button is clicked One choice includes setting the state of all non JTAG PSD I O pins during JTAG ISP operations make them inputs or outputs The default state of all non JTAG PSD I O pins is input which is fine for this design example The other choice allows you to specify a USERCODE value to compare before any JTAG ISP operation starts This is typically used in a manufacturing environment See the on screen description for details After JTAG ISP operations have completed you can save the JTAG setup for this programming session to a file for later use To do so click on the Save button in Step 3 To restore the setup of a previous session click the Browse button in Step 3 Programming with PSDpro Connect the PSDpro device programmer to your PC parallel port per the installation instructions Click on the Conventional Programmers box in the design flow window You will see this 13 17 AN1426 APPLICATION NOTE fj Conventional Programming a16xbhe obj No Hardware sa o o 25 o afe e lla sal Sa _ Mini aol
21. st of chip selects Enter system memory information Page Hex Stat Hex End Logical AND of Signal Qualifiers Number Address Address more than one OK ae Logical OR with next statement lt 2 peee Logical OR with next statement 22 2 D a SEABSASSEO NOON mW O Enter the information for csboot1 in a similar fashion where csboot1 will be valid from 2000h to 3FFFh Enter the external chip select equation for the LCD module X 8 access List of chip selects Enter system memory information Page Hex Stat Hex End Logical AND of Signal Qualifiers mi Number Adcers Addam foethanone OK H F n pec t DEFF t fvr Logical OR with next statement Paa peo g PEF fod Logical OR with next statement ma G Go o Resultant equation Extemal chp select or al PLD combinatorial logc output led_e adckess Be EDO ladia lt HDEFF amp fl wr laddiess gt WDE00 amp address lt hDEFF amp M_rd zj lt lt Prev Restan View Done Cancel Showa Note that since the LCD is external we must now include the _wr and _rd control signals in the chip select equation where this was taken care of automatically for internal chip selects Since the _wr and _rd sig nals are active low the symbol is required Also notice how after you have finished typing in the equation for the chip select the end result appears at the bottom of the screen if you select that signal again Lastly cl
22. the logic equations for selection of each internal PSD memory segment These equations re flect the choices that you made while defining PSD internal chip select equations in an earlier step In the middle of the screen are hexadecimal start and stop addresses that PSDsoft Express has filled in for you based on your chip select equations On the right are fields to enter browse the MCU firmware files Select Intel Hex Record for Record Type as shown Scroll all the way down to the bottom to get to the secondary Flash memory Now click on the Browse button for csboot0O and csboot1 and select the firm ware file PSDexpress examples Tim h86 Once you have filled in the file names your screen should look like the one below 4 11 17 AN1426 APPLICATION NOTE Merging of MCU Firmware with PSD x Step 1 MCU firmware placement Specily name of MCU fiermmane file for each memory select Edit Add fle stait and file stop addresses as needed Memory File Fie Select Mamoy Select Equations Address File Name Name Stat Stop Scroll to the Ipdn amp ap H ie t pE z bottom to get to CSBOOTO glat 220 jd pe Browse oF lads Erri pei the secondary Hlat5 8 ald 0138 flash csp00T1 wae 1a22 amp la21 amp a20 TE 000 Fe D pedexpress EXAMPL Browes la19 amp lal8t lai E lale a aaa EE e Boe T cS80073 O T E Record Type irtelHex Record C Motorola S Recced D pedexpress EXAMPL Step 2 Merg
23. the steps Invoke PSDsoft Express and Open a New Project m Start PSDsoft Express m Create a new project m Select your project folder and name the project in this example name the project EasyC167 in the folder PSDexpress my_ project Select an MCU In this example we re using an Infineon C167CR Select WR RD BHE for the control signals Select the PSD4000 series for the PSD Family Select a PSD4235G2 and use the 80 pin TQFP package U package Based on the above selections the Bus Width will be set to 16 bits automatically Select the Bus Mode to be multiplexed and the ALE AS level will automatically be set to high Now you have your project established based on a PSD4235G2 and a C167CR However there are many other MCU MPUs you could have chosen in place of the C167CR and still have use of this document The main reason for selecting the C167CR is that it is used in our DK4000 development kit MCU and PSD Selection This is what the screen should look like after you ve made the selections MCU and PSD Selection j x Step 1 Select Microcontroller MCU 5 Step 2 Specify the PSD device aged tN lerako koei ctl If your MCU does Use product selection wizard not appear on the list select Other then specify te control signal m Sauen pea Pooran aaa Menace irtnecr Pattunber Psparsea2 gt ee Package ann TaFP E Control Signal AVA 7RD BHE Vonage NSN Step 3 MCU Parameters Sele
24. unctional requirements grow In System Programming and In Application re Program ming Our industry uses the term In System Programming ISP in a general sense ISP is applicable to programmable logic as well as programmable Non Volatile Memory NVM However an additional term will be used in this document In Application Programming IAP There are subtle yet significant differences between ISP and IAP when microcontrollers are in volved ISP of memory means that the MCU is off line and not involved while memory is being programmed For IAP the MCU participates in programming the memory which is impor tant for systems that must be online while updating firmware Often ISP is well suited for manufacturing while IAP is appro priate for field updates PSD4235 devices are capable of both ISP and IAP Keep in mind that IAP can only program the mem ory sections of the PSD and not the configuration and program mable logic portions With ISP the entire PSD can be erased or programmed The IAP Problem Typically a host computer downloads firm ware into an embedded Flash memory system through a com munication channel that is controlled by the MCU This channel is usually a UART but any communication channel that the 1 17 AN1426 APPLICATION NOTE C167CR supports will do The C167CR must execute the code that controls the IAP process from an in dependent memory array that is not being erased or programmed Otherwise boot code and
25. y One You would only select More than One if you had more than one ISP device in your JTAG chain After you make your selection and clicked OK you should see the following screen 4 12 17 AN1426 APPLICATION NOTE JTAG ISP Operations Single Device x Step 1 Select ies ia file and PSD Select folder and programming file Select device P psdexpeess my_project E T 67 obj rowse Pso 423862 Step 2 Specify ints Bhp lope and conditions Select operation D region Select of JTAG pins to use Other conditions I Program gt fE pied operties JTAGISP necute Click here to pettorm specified JTAGSP operation Step 3 Save or retrieve JTAG ISP setup 1 poe e Meer cae os ultra E T esa P panic sadn on Select fokder and fle l Browse r PE E cabs Fa A N pla This window enables you to perform JTAG ISP operations and also offers a loop back test for your FlashLINK cable If this is your first use test your FlashLINK cable and PC parallel port by clicking the HW Setup button then click LoopTest button and follow the directions Now let s define our JTAG ISP environment PSDsoft Express should have filled in the folder and filename of the object file to program the PSD device and the JTAG ISP operation as shown in the screen above For this design example we have chosen to use all six JTAG ISP pins instead of four Be sure to indicate 6 pins as
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