Channel Link Demonstration Kit User Manual
Contents
1. Tolerance Unless Noted 0 00 000 Inch 1 01 005 Dimensions for Reference only Ordering Information 102XX 1210VE YT Contact Quantity See Table TS 0755 05 Note Use M2 5x8mm screws to mount to panel with max thickness of 2 0 mm one 3M Electronic Products Division 6801 River Place Blvd For technical sales or ordering information call Austin TX 78726 9000 800 225 5373 050 Mini D Ribbon MDR Connectors Surface Mount Right Angle Receptacle Shielded Contact Dimensions Quantity 002 002 C 002 20 1 081 27 45 650 16 51 475 12 07 26 1 230 31 26 800 20 32 625 15 88 40 1 581 40 15 1 150 29 21 975 24 77 center spacing 025 0008 center spacing 102 1210 Recommended Board Layout viewed from connector side Solder Pads for Solder Tail See below for more detail 21651421 016 0004 093 0004 Q 110 004 2X Screw Lock see notes below 118 3 0 d 1381351 256 6 5 PCB Ref Edge I Lockstand Solder Pad Outline 187 max 4 75 2 2 079 004 2X 000 Positioning Hole Solder Ta2. RxCLK SHIELD The diagram above illustrates the use of the Channel Link chipset Tx Rx This chipset is able to transmit 28 bits of LVTTL LVCMOS data using four LVDS channels for a total throughput of 2 38 Gbps 297 5 Mbytes s Input clock rate is specified to be between 20 MHz to 85 MHz maximum The interconnect between the two devices may be a variety of media including twisted pair cables twin ax cables and or backplanes for example Driving between the two devices is a function of interconnect skew and clock rate Distances up to ten meters are possible at the lower clock rates and distances of 1 to 2 meters is possible at the higher clock rates Please refer to the chipset datasheet for more information and parametric tables LIT CLINK3V28BT 85 UM National Semiconductor Corporation Rev 2 1 Interface Products Date 10 12 2005 Page 4 of 28 Channel Link Evaluation Kit User Manual How to set up the Evaluation Kit The PCB routing for the Tx input pins TxIN have been laid out to accept incoming data from 60 pin IDC connector The interface uses the connector and Spectra Strip cable This typical cable provides minimal skew between LVDS channels and can typically support longer lengths than atwisted pair cable Please follow these steps to set up the evaluation kit for bench testing and performance measurements 1 Connect one end of the Spectra Strip cable t
3. Transmitter Board 60 pin IDC Connector TxOUT LVDS signals 3M connector Pin1 2 PIN NAME GND TXIN2 TXOUTO 1 NC GND TXIN3 2 GND GND TXIN4 3 NC GND TXIN5 4 OUT1 GND TXIN6 5 OUT1 GND TXIN7 TXOUTO 6 OUT2 GND TXIN8 7 OUT2 GND TXIN9 8 GND TXIN10 9 NC GND TXIN11 GND TXIN12 GND TXIN13 GND TxiN14 GND TXIN15 GND 16 GND 17 gt GND 18 TXOUT1 GND 19 GND 20 GND TXIN21 TXOUT2 GND TXIN22 GND TXIN23 GND TXIN24 GND TXIN25 TXOUT2 GND TXIN26 GND TXIN27 GND TXCLKIN 59 GND 60 J1 TXCLKOUT Previous Cycle Next Cycle X X X TXIN23 XXN TXINTO XTXINS TXINZT TXOUT2 TXIN25 XTXINZ4 TXINZ2 TXINZT TXINZ0 TXINTS TXOUT1 X XX TXIN18 5 XTXIN14 X TXINT3 X 2 X 9 8 TXOUTO X X TXING X 2 X Parallel LVTTL LVCMOS Data Inputs Mapped to LVDS Outputs LIT CLINK3V28BT 85 UM National Semiconductor Corporation Rev 2 1 Interface Products Date 10 12 2005 Page 8 of 28 Channel Link Evaluation Kit User
4. BOARD 2 nua ini eu 11 SELECTABLE JUMPER SETTINGS FOR THE RX BOARD 0 12 LVDS MAPPING BY IDC 20 13 RX OPTIONAL SERIES TERMINATION FOR 00 14 BOM BILL OF MATERIALS eto cotto oa Fe es es ee cede 15 TROUBLESHOOTING o ccecccescaseccsceseerecnsssercoccocescusserenseccevenseeracecensseueccane 19 ADDITIONAL 20 5 ere 20 2 cosezecnescuscce cucsaucneusetsenszeaves 21 26 MiNI D CABLE AND CONNECTOR 0 0 11 1 0 rere rei perius 21 TRANSMITTER AND RECEIVER SCHEMATICS 2 2 5 28 LIT CLINK3V28BT 85 UM National Semiconductor Corporation Rev 2 1 Interface Products Date 10 12 2005 Page 2 of 28 Channel Link Evaluation Kit User Manual Introduction National Semiconductor Interface Products Group Channel Link evaluation kit contains a Transmitter Tx board a Receiver Rx board along with interfacing cables This kit will demonstrate the Channel Link chipset transmitting data streams using Low Voltage Differential Signaling LVDS The
5. E E GND TXIN6 GND TXIN7 GND E TXIN O GND TXIN8 Lee DN GND TXIN9 INS GND TXIN10 EHI GND TXIN13 GND TXIN14 avo n m GND TXIN15 Eris B GND TXIN16 ND 2 p z nekar ES cum t GND TXIN19 a 2 GND VCC eee GND GND 20 GND TXIN21 ap eal ms Cra GND TXIN22 ao Dee ns Nationa GND TXIN23 Semiconductor GND TXIN24 HSL TX 8 BIT GND TXIN25 60 26 MADE IN U S A TXIN27 us Tx 8 2 GND 59 60 Note JP1 is not used LIT CLINK3V28BT 85 UM National Semiconductor Corporation Rev 2 1 Interface Products Date 10 12 2005 Page 6 of 28 Channel Link Evaluation Kit User Manual Jumper Settings for the Tx Board Jumper Purpose Settings PD PowerDown ON e_e OFF JP2 Vec GND GND ON Tx is operational OFF Tx powers down Default setting is JP2 set HIGH to Vcc operational mode LIT CLINK3V28BT 85 UM National Semiconductor Corporation Rev 2 1 Interface Products Date 10 12 2005 Page 7 of 28 Channel Link Evaluation Kit User Manual Tx LVDS Mapping by IDC Connector The following two figures illustrate how the Tx inputs are mapped to the IDC connector J1 Note labels are also printed on the demo boards The 26 pin MDR connector pinout is also shown
6. Manual Tx Board Options 50 Ohm Termination for On the Tx demo board the 29 inputs have an option for 50 Ohm terminations There are 0402 pads for this purpose One side is connected to the signal line and the other side is tied to ground These pads are unpopulated from the factory but are provided if the user needs to install 50 Ohm termination R1 TO R28 associated with the Tx data input lines R29 is associated with CLKIN Some test equipment may require a 50 Ohm load Mapping of Transmitter Inputs for the Optional Termination Resistors is shown below Tx Pin Tx Pin Termination TxINO TxIN1 TxIN2 TxIN3 50 Ohm Termination TxIN4 Optional TxIN5 TxIN6 TxIN7 TxIN8 TxIN9 TxIN10 TxIN11 TxIN12 TxIN13 TxIN14 TxIN15 TxIN16 TxIN17 TxIN18 TxIN19 TxIN20 TxIN21 TxIN22 TxIN23 TxIN24 TxIN25 TxIN26 TxIN27 TxCLKIN LIT CLINK3V28BT 85 UM National Semiconductor Corporation Rev 2 1 Interface Products Date 10 12 2005 Page 9 of 28 Channel Link Evaluation Kit User Manual BOM Bill of Materials Transmitter PCB HSL Demo Board Schematic REV1 HSL8TXR1 10 11 Revision 1 Channel Link Item Qty Reference Part 1 C1 10 uF 4 C2 C6 C10 C14 0 1 uF 4 C3 C7 C11 C15 22 uF 3 C4 C8 C12 0 001 uF 3 C5 C9 C13 0 01 uF 2 2 3 PIN HEADER 1 J1 IDC30X2 1 J2 3M 29 R1 R2 R3 R4 R
7. Transmitter board accepts LVTTL LVCMOS data signals from an incoming data source along with the clock signal The LVDS Transmitter converts the LVTTL LVCMOS parallel lines into four serialized LVDS data pairs plus a LVDS clock The serial data streams toggle at 3 5 times the clock rate The Receiver board accepts the LVDS serialized data streams plus clock and converts the data back into parallel LVTTL LVCMOS data signals and clock The user simply needs to provide the proper LVTTL LVCMOS data input and clock to the Transmitter and the chipset will serialize transmit and deserialize the data converting it back into the LVTTL LVCMOS parallel bus plus clock A power down feature is also provided that reduces current draw when the link is not required LIT CLINK3V28BT 85 UM National Semiconductor Corporation Rev 2 1 Interface Products Date 10 12 2005 Page 3 of 28 Channel Link Evaluation Kit User Manual Contents of the Evaluation Kit 1 One Transmitter board with the DS90CR287MTD 28 bit Transmitter 2 One Receiver board with the DS90CR288AMTD 28 bit Receiver 3 One 2 meter Amphenol Spectra Strip Cable interface 4 One 60 pin IDC Flat Ribbon Cable 5 Evaluation Kit Documentation this manual 6 D890CR287 288A Datasheet 7 Channel Link Application Notes AN 1041 and AN 1108 Channel Link Typical Application TX RX LVDS Cable DS90CR287 media dependent M AL A LVCMOS LVTTL 25 26 26 27
8. times HIGH and 3 bit times LOW The differential signal should be typically 300mV These waveforms were acquired using the TEK P6248 Probes Clock rate is 85MHz LIT CLINK3V28BT 85 UM National Semiconductor Corporation Rev 2 1 Interface Products Date 10 12 2005 Page 17 of 28 Channel Link Evaluation Kit User Manual RxOUT Tek Run 5 00 5 5 Sample CUT H 1 Freq 185 22935 2 Chi 1 00V i1 00V M2 00ns Chi X 1 40 The plot above shows both the recovered PRBS data and also the regenerated Clock overlaid Note that the clock transitions slightly before the data transition and strobes the data on the rising edge of the clock The data and clock signals are low drive CMOS outputs The plot above is at 85MHz LIT CLINK3V28BT 85 UM National Semiconductor Corporation Rev 2 1 Interface Products Date 10 12 2005 Page 18 of 28 Channel Link Evaluation Kit User Manual Troubleshooting If the demo boards are not performing properly use the following as a guide for quick solutions to potential problems If the problem persists please contact the Interface Applications hotline number 1 408 721 8500 for assistance QUICK CHECKS 1 Check that Power and Ground are connected to both Tx AND Rx boards 2 Check the supply voltage typical 3 3V and also current draw with both Tx and Rx boards should be about 200mA with clock one data bit at 66 2 3 Verify input clock and input data s
9. 5 R6 R7 R8 Optional R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 8 R30 R32 R33 R34 R35 0 Ohm R36 R37 2 TP1 TP2 N A 1 Ul DS90CR287MTD 12 National Semiconductor Corporation Interface Products Pkg Size CASED 1206 3216 7343 D 0805 2012 0805 2012 0 1 spacing IDC60 26MDR 0402 PAD 0402 TP_ 2 X 2 56 pin TSSOP LIT CLINK3V28BT 85 UM Rev 2 1 Date 10 12 2005 Page 10 of 28 Channel Link Evaluation Kit User Manual Rx Channel Link Receiver Board J1 60 position provides access to the 28 bit LVTTL LVCMOS clock outputs The Channel Link Receiver board is powered from the pads show below For the receiver to be operational the Power Down pin must be set HIGH with the jumper The 3M MDR connector J2 provides the interface for LVDS signals for the Receiver board RxIN LVDS signals 3M MDR26 7 connector Vcc and Gnd MUST be applied externally here 3 6 MAX Tm vec CND vce e ej GND copyricHT z000 National Semiconductor HSL RX 8 BIT MADE IN U S A ASSY HSL RX 8 BIT 60 59 RXOUT27 RXOUT26 RXOUT25 RXOUT24 RXOUT23 RXOUT22 RXOUT21 RXOUT20 RXOUT19 RXOUT B RXOUTI7 RXOUT16 RXOUTIS RXOUT14 RXOUTIS RXOUT12 RXOUTII RXOUT10 RXOUT
10. 9 RXOUT 8 RXOUT 7 RXOUT 6 RXOUT 5 RXOUT 4 RXOUT 3 RXOUT 2 RXOUT 1 RXOUT 0 RXCLKOUT GND Nee 4 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND SND GND GND GND GND GND GND GND GND GND GND GND 2 1 2 National Semiconductor Corporation Interface Products 60 59 RXOUT27 GND RXOUT26 GND RXOUT25 GND RXOUT24 GND RXOUT23 GND RXOUT22 GND RXOUT21 GND RXOUT20 GND RXOUT19 GND RXOUT18 GND RXOUT17 GND RXOUT16 GND RXOUT15 GND RXOUT14 GND RXOUT13 GND RXOUT12 GND RXOUT11 GND RXOUT10 GND RXOUT9 GND RXOUT8 GND RXOUT7 GND RXOUT6 GND RXOUT5 GND RXOUT4 GND RXOUT3 GND RXOUT2 GND RXOUT1 GND RXOUTO GND RXCLKOUT GND GN 2 1 J1 Date 10 12 2005 Page 11 of 28 LIT CLINK3V28BT 85 UM Channel Link Evaluation Kit User Manual Selectable Jumper Settings for the Rx Board Jumper Purpose Settings PD PowerDown JP1 Vec GND Vec ON Rx is operational OFF Rx powers down Default setting is JP1 set HIGH to Vcc operational mode LIT CLINK3V28BT 85 UM National Semiconductor Corporation Rev 2 1 Interface Products Date 10 12 2005 Page 12 of 28 Channel Link Evaluation Kit User Manual LVDS Mapping by IDC Connector The following two figures illustrate how the Rx outputs are
11. Channel Link Evaluation Kit User Manua National Semiconductor Channel Link Demonstration Kit User Manual P N CLINK3V28BT 85 Rev 2 1 Interface Products LIT CLINK3V28BT 85 UM Date 10 12 2005 Page 1 of 28 Channel Link Evaluation Kit User Manual Table of Contents 2 0 3 CONTENTS OF DEMO KIT teer aetna 4 APPEICATIONS E E TA de E ee 4522 eer ee 4 FEATURES AND 5 TRANSMITTER nia ee 6 RECEIVER oe ose est cet ese cone Eo sce Er 11 HOW TO HOOK UP THE DEMO BOARDS OVERVIEW 5 TRANSMITTER 6 SELECTABLE JUMPER SETTINGS FOR THE TX 6 LVDS MAPPING BY IDC 0 4 41 44 6 TX OPTIONAL PARALLEL TERMINATION FOR 9 BOM BILL OF MATERIALS tod uth ant md caidas 10 REGEIVER
12. RUNT e Nos RXOUTIS 1 RXOUTIS RXOUTIO 26 25 RXIN1GND RXIN1 RXOUT14 46 E Ko 24 23 1 1 RXOUT13 RXOUT7 22 21 NC LVDS GND 44 20 19 RXIN2 LVDS GND RXOUT12 BXOUTTI RXOUTS 18 17 RXIN2GND RXIN2 RXOUT11 42 16 15 RXIN2 RXIN2 RXOUT10 BXOUTIO Bout 14 13 NC RXCLK IN vec 20 9 18 HXOUTS BXOUT2 2 11 RXCLK IN RXOUTS aap 100 9 NC 38 RXOUTS RXOUTI NC RXIN3 RXOUT8 RXOUTO 8 NC RXIN3 RXOUT7 36 RXCLKOUT RXCLKIN LVDS GND OE RXCLKINGND PLL GND PLL VCC 23 34 RXCLKIN PLL VCC PLL GND IDC30X2 NC 24 PLL GND NC Tr PWR DWN RXIN3 Fri 5 RXCLK OUT VCC a RXOUT2 RXIN3GND RXOUTO RXOUT2 RXIN3 ep 9 28 GND RXOUT1 NC MOUNTING 59028 HEADER RXOUTO 3M_MDR_EZ8B S HXCLKOUT VCC VCC1 3 LVDS VCC PLL VCC GND1 PLL_GND LVDS_GND GND 3 6V MAX VCC1 b 18 16 _ 2 2 GNDP2uF 001uF D O1uF 2uF C1 C2 10UF LVDS TP2 8 9 10 11 GND1 PLL gt 614 15 HSL Demo Board Schematic PLL_GND 001uF D O1uF 2uF i Document Number HSL8RX Date Monday August 21 2000 Sheet 1 of 1
13. WN NC 28 1 TXCLK IN 31 TXOUT3 L 24 26 TXOUT3GND 8 TXIN25 GND 22 9 TXOUT3 NC DS90CR287 MOUNTING INS 4 MOUNTING 626 27 3M MDR EZ8B A20 TXCLKIN 7 vcc 22 VCC JP LVDS_VCC PLL VCC HEADER GND1 35 PLL GND LVDS GND GND 3 6V VCC VCC1 3 4 5 6 7 is p _ 2 2 GNDe2uF 001uF 5D 01uF 2uF C1 C2 10uF 0 1uF LVDS VCC TP2 8 9 10 11 GND1 Z1 4 12 13 14 15 HSL Demo Board Schematic PLL_GND 001uF 0 01uF 2uF Document Number HSL8TX Date Monday August 21 2000 Sheet 1 3 6V MAX Ji RXOUT27 RXOUT27 RXOUT26 RXOUT26 RXOUT25 RXOUT25 RXOUT24 BXOUT24 96 55 RXOUT23 23 94 53 RXOUT22 RXOUT22 RXOUT21_ 90 49 RXOUT20 48 47 0119 46 45 a DS S 2 UIS yee 7 RXOUT21 18 gt P J2 CUTS d 2 RXOUT20 RXOUTI7_ 4 i SOUS poms m RXINO 5 1 RXOUT25 GND 22 RXOUTIS 156 35 LVDS GND 10 RXOUT18 RXOUT14 RXINOGND RXOUT26 RXOUT18 7 BXOUTIT BXOUTI37 34 33 RXINO RXOUT27 RXOUT17 22 32 31 LVDS GND RXOUT16 RXOUTIG RXOUTI2 150 29 We ee RXOUTIT_ 2
14. al Semiconductor Corporation Rev 2 1 Interface Products Date 10 12 2005 Page 13 of 28 Channel Link Evaluation Kit User Manual Rx Optional Series Termination for RxOut On the Rx demo board there are 29 outputs that have an 0402 pad in series which are shorted out These pads are unpopulated from the factory but are provided if the user needs to install a 450 Ohm series resistors This is required if directly connecting to 50 Ohm inputs on a scope To use this option the user must cut the signal line between the pads before installing the 450 Ohm series resistors R1 to R28 are associated with the DATA output lines R29 is associated with CLKOUT The total load presented to the receiver output is 500 Ohms 450 50 The waveform on the scope is 1 10 of the signal due to the resulting voltage divider 50 450 50 Optional Series Termination Resistor mapping is shown below Rx Pin Names Rx Pin Series Number Termination Resistor RX RxOUTO Series Termination RxOUT1 Optional RxOUT2 RxOUT3 RxOUT4 RxOUT5 RxOUT6 RxOUT7 RxOUT8 RxOUT9 RxOUT10 RxOUT11 RxOUT12 RxOUT13 RxOUT 14 RxOUT15 RxOUT16 RxOUT17 RxOUT18 RxOUT19 RxOUT20 RxOUT21 RxOUT22 RxOUT23 RxOUT24 RxOUT25 RxOUT26 RxOUT27 RxCLKOUT LIT CLINK3V28BT 85 UM National Semiconductor Corporation Rev 2 1 Interface Pro
15. assembly 14 26 3 6V Ji Bi TXINO TXINO BA TXIN 1 2 TXIN1 2 TXIN2 3 4 TXIN2 Gl TXINS 5 6 TXINS 2 4 7 8 4 Ui H 15 5 TXING 1 1 56 5 16 XN BE _TXINS TXINS TXINS 17 1g NB 3 1 6 TXIN2 24 J2 20 No 4 TXIN7 GND 22 H nc 22 SN Hoi GND 4 1 TXOUTO 28 24 YINI2 AL TXIN8 TXINO TXOUTOGND 25 26 GING 2 TXIN9 27 TXOUTO 27 28 XIN 8 TXIN10 LVDS GND ME NC 29 30 INTE 24 vcc TXOUTO NC 31 32 ange 2 TXINt 1 TXOUTO TXOUT1 33 34 ANY Ay 12 TXOUT1 TXOUT1GND 85 36 XNE TXIN13 TXOUT1 TXOUT1 37 38 19 5 3 GND LVDS VCC NC 39 40 INDO aN 154 4 LVDS GND TXOUT2 41 42 2 TXIN15 TXOUT2 TXOUT2GND 43 44 XIN22 TXIN16 TXOUT2 45 TXOUT2 45 46 TXiD3 ae L TXCLK OUT 40 NC 47 48 NA AE 18 1 7 TXCLK OUT 38 NC 49 50 2 8 TXOUTS NC 51 52 TXIN26 TXIN19 TXOUT3 36 NC 58 54 5 GND LVDS GND SIT GND TXCLKOUT 55 56 22 22 1 TXIN20 PLL GND 28 PLL VOC TXCLKOUTGND 25 3 TXIN21 PLL VCC TXCLKOUT 25 21 1 TXIN22 PLL GND 25 NC IDC30X2 TXIN23 PWR D
16. at www national com appinfo Ivds Application Notes AN 1041 Channel Link Moving and Shaping Information in Point to Point Applications AN 971 An Overview of LVDS technology AN 977 LVDS Signal Quality Jitter Measurement Using Eye Pattern AN 1059 High Speed Transmission with LVDS Devices AN 1108 Channel Link PCB and Interconnect Design In Guidelines Interface Applications Hotline The Interface Hotline number is 1 408 721 8500 LIT CLINK3V28BT 85 UM National Semiconductor Corporation Rev 2 1 Interface Products Date 10 12 2005 Page 20 of 28 Channel Link Evaluation Kit User Manual Appendix Cable and connector The next few pages provide a full description of the cable and connector For product request please contact 3M and Alliance Technology Enterprise 3M Connector Data is available at www mmm com Interconnects Spectra Strip Cable Data is available at www alliancet com Tx PCB Schematic Transmitter Board HSL Demo Board Schematic Document Number HSL8TX Rev 1 0 Rx PCB Schematic Receiver Board HSL Demo Board Schematic Document Number HSL8RX Rev 1 0 LIT CLINK3V28BT 85 UM National Semiconductor Corporation Rev 2 1 Interface Products Date 10 12 2005 Page 21 of 28 050 Mini D Ribbon MDR Connectors Surface Mount Right Angle Receptacle Shielded 140 Physical Insulation Material Flammability Color Contact Material Plating Underplate Wiping Area Shroud and Latch Hook Mate
17. bove procedure For evaluation of 21 bit device chipset user needs to pull TxIN 21 27 high or low Power Connection The Transmitter and Receiver boards must be powered by supplying power externally through TP1 Vcc and TP2 GND on EACH board Information on maximum supply voltage can be found on device datasheet s Absolute Maximum Ratings section The maximum voltage that should ever be applied to the Channel Link Transmitter DS90CR287 or Receiver 0590 288 Vcc terminal is 4V MAXIMUM LIT CLINK3V28BT 85 UM National Semiconductor Corporation Rev 2 1 Interface Products Date 10 12 2005 Page 5 of 28 Channel Link Evaluation Kit User Manual Channel Link Transmitter Board Description J1 60 position accepts 28 bit LVTTL LVCMOS data clock and also the control signal The Channel Link Transmitter board is powered externally For the transmitter to be operational the Power Down pin must be set HIGH with a jumper The 3M MDR connector J2 provides the interface for LVDS signals for the Receiver board 60 pin IDC Connector TxOUT LVDS signals 1 2 Vcc and Gnd MUST be 3M MDR connector applied externally here GND TXIN1 GND TXIN2 GND TXIN3 2
18. ducts Date 10 12 2005 Page 14 of 28 Channel Link Evaluation Kit User Manual BOM Bill of Materials Receiver PCB HSL Demo Board Schematic REV1 HSL8RXR1 Revision 1 Channel Link Item Qty Reference 10 11 12 29 C1 2 6 10 14 C3 C7 C11 C15 C4 C8 C12 C5 C9 C13 JP1 J1 J2 R1 R2 R3 R4 R5 R6 R7 R8 9 10 11 12 13 14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 R35 R36 R37 R38 R39 R40 R30 R31 R32 R33 R34 TP1 TP2 U1 Part 10 uF 0 1 uF 22 uF 0 001 uF 0 01 uF 3 HEADER IDC30X2 3M MDR Optional See previous page 0 Ohm 100 Ohm N A DS90CR288AMTD National Semiconductor Corporation Interface Products Pkg Size CASE D 1206 3216 7343 D 0805 2012 0805 2012 0 1 spacing IDC60 26MDR 0402 PAD 0402 0402 TP_ 2 X 2 56 pin TSSOP LIT CLINK3V28BT 85 UM Rev 2 1 Date 10 12 2005 Page 15 of 28 Channel Link Evaluation Kit User Manual Typical Connection Test Equipment The following is a list of typical test equipment that may be used to generate signals for the TX inputs 1 HFS9009 This pattern generator along with 9002 Cards may be used to generate input signals and also the clock signal 2 TEK DG2020 This generator may also be used to generate data and clock signals 3 TEK MB100 BERT This bit error rate tester may be used for both signal source and receiver 4 Any other signal patt
19. ern generator that generates the correct input levels as specified in the datasheet The following is a list of typically test equipment that may be used to monitor the output signals from the RX 1 TEK MB100 BERT Receiver 2 Any SCOPE with 50 Ohm inputs or high impedance probes LVDS signals may be easily measured with high impedance high bandwidth differential probes such as the TEK P6247 or P6248 differential probes The picture below shows a typical test set up using a generator and scope Signal Pattern Generator BERT Tester ee eee ese Ble T 1 i Optional Termination Transmitter Receiver i B ipe 450 ohm NS YL MEM LVDS Interface x Cable 50 ohm gt 50 ohm Oscilloscope 4 Optional 7 Termination ST BERT Tester CE LIB lm cos Typical Connection Test Equipment Setup LIT CLINK3V28BT 85 UM National Semiconductor Corporation Rev 2 1 Interface Products Date 10 12 2005 Page 16 of 28 Channel Link Evaluation Kit User Manual Typical Waveshapes LVDS Tek Run 5 0005 5 33 cas C1 Freq 5 52606MH2 The plot above shows both the LVDS Data channel with PRBS data and also the LVDS Clock over laid Note that the clock pattern is 4 bit
20. ignals meet requirements VIL VIH tset thold Also verify that data is strobed on the rising edge of the clock 4 Check that the Jumpers are set correctly 5 Check that the 2 meter cable is properly connected TROUBLESHOOTING CHART Problem Solution There is only the output clock There is no output data Make sure the data is applied to the correct input pin Make sure data is valid at the input No output data and clock Make sure Power is on Input data and clock are active and connected correctly Make sure that the 2 meter cable is secured to both demo boards Power ground input data and input clock are connected correctly but no outputs Check the Power Down pins of both boards and make sure that the devices are enabled PD Vcc for operation The devices are pulling more than 1A of current Check for shorts in the cables connecting the TX and RX boards After powering up the demo boards the power supply reads less than 3V when it is set to 3 3V Use a larger power supply that will provide enough current for the demo boards a 500mA power supply is recommended National Semiconductor Corporation LIT CLINK3V28BT 85 UM Rev 2 1 Date 10 12 2005 Page 19 of 28 Interface Products Channel Link Evaluation Kit User Manual Additional Information For more information on Channel Link Transmitters Receivers refer to the National s LVDS website
21. il Layout Detail s s Correspond to Connector Contact Shown on Previous Page 10 1 Connector Position Top Row 20 Pos Last 20 Pos 19 18 17 16 15 14 O Position Bottom Row PCB Ref Edge 57 Connector Position Top Row 26 Pos Last 26 Pos 25 24 23 22 21 20 O Position Bottom Row 57 Connector Position 5 4 3 2 m 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 PCB Ref Edge Position Bottom Row Recommended Panel Cut out Note Panel thickness 079 2 00 Max Contact Dimensions Quantity D E 20 94 23 8 1 081 27 45 26 1 09 27 6 1 231 31 26 40 1 44 36 5 1 581 40 15 N 319 004 8 1 Notes 1 Plated through holes for 062 board thickness 2 Use mounting screws M2 5 to fasten to board TS 0755 05 Sheet 3 of 3 3M Electronic Products Divisi
22. mapped to the IDC connector J1 Note labels are also printed on the demo boards The 26 MDR connector pinout is also shown Receiver Board 60 pin IDC Connector RxIN LVDS signals 60 59 3M MDR connector RXOUT27 GND E RXOUT26 GND PIN Z NAME RXOUT25 GND 1 NC RXOUT24 GND 2 GND RXOUT23 GND 3 NC RXOUT22 GND 4 CLK RXOUT21 GND 5 CLK RXIN2 RXOUT20 GND 6 NC RXOUT19 GND 7 NC RXOUT18 GND 8 GND RXOUT17 GND 9 NC RXOUT16 GND 10 GND RXOUT15 GND 11 NC RXOUT14 GND 12 INO RXIN1 RXOUT13 GND 13 INO RXOUT12 GND 14 IN3 RXOUT11 GND 15 IN3 RXOUT10 GND 16 NC RXOUT9 GND 17 GND RXOUT8 GND 18 NC RXOUT7 GND 19 NC RXOUT6 GND 20 IN2 umet re RXOUT5 GND 21 IN2 RXOUT4 GND 22 IN1 RXOUT3 GND 23 IN1 RXINO RXOUT2 GND 24 NC RXOUT1 GND 25 GND RXOUTO GND 26 NC RXCLKOUT GND RXCLKIN Previous Cycle Next Cycle RXNS X ARXOUT29X RXOUT17X RXOUT16X RXOUT1 1X RXOUT10X RXOUTS RXOUT27 X 7 XRXOUTZ6y RKOUT25 RKOUT2AX RXOUTZ2 RXOUTZNX RXOUTAYCRXOUTI X XRXOUTIBJ RXOUTISJ RXOUTIACRXOUTS RXOUTE RXNO X RXOUT X RXOUTe ROUTA XCRXOUTS RXOUTZ X RXOUTT X RXOUTO LVDS Data Inputs Mapped to LVTTL LVCMOS Outputs LIT CLINK3V28BT 85 UM Nation
23. o the transmitter board and the other end to the receiver board This is a standard pinout cable longer lengths are available for purchase from Alliance Technology see www alliancet com Jumpers have been configured at the factory they should not require any changes for operation of the chipset See text on Jumper settings for more details For the incoming data connect a flat ribbon cable to the transmitter board to a data source signal generator pattern generator BERT tester etc Connect the 60 pin flat cable from the receiver board to the receiver load BERT or other equipment Scope probes may also be connected directly to the pins if desired Mini coax cable with headers on one end may also be used This type of cable is supplied with some test equipment The 60 pin IDC equipment interface cable is supplied with this kit which can be used to build custom cables Power for the Tx and Rx boards must be supplied externally through TP1 Vcc Grounds for both boards are connected through TP2 GND see section below Data applied to the inputs is now serialized transmitted deserialized and re driven at the receiver outputs 2 3 4 5 This evaluation kit can also be used to evaluate the performance of other National Semiconductor s 28 bit and 21 bit Channel Link Serdes chipset Simply replace the existing DS90CR287 288A devices with a different 28 bit or 21 bit device chipset and follow the a
24. on 6801 River Place Blvd Austin TX 78726 9000 For technical sales or ordering information call 800 225 5373 Cable Assembly Part number MDR26 5 6 5 mdr 10126 6000 10126 6000 2 meters Spectra Strip cable Skew Clear twin ax Part number MDR26 5 6 5 Y Cable length Connector type 6 5 Ft 2 meter Number of twin Ax pairs 5 Connector number of positions 26 Cable assemby ordering information Alliance Technology Enterprise 521 Central Suite B Menlo Park 94025 650 329 8554 info allianceT com www AllianceT com National Semiconductor Channel Link Cable Assembley Pinout Alliance Technology part number MDR26 5 6 5C Pin Assignment Pin Assignment Side A Side B 3M Part 3M Mar Part 10126 6000 10126 6000 1 No Connect 26 No Connect 2 TxOutOGnd 25 TxOutGnd 3 No Connect 24 No Connect 4 TxOut1 23 RxIn1 5 TxOut1 22 RxIn1 6 TxOut2 21 2 7 TxOut2 20 RxIn2 8 Reserved 19 Reserved 9 No Connect 18 No Connect 10 TxClkoutGnd 17 RxInCikGnd 11 No Connect 16 No Connect 12 TxOut3 15 RxIn3 13 Txout3 14 Rxin3 14 TxOut0 13 RxInO 15 TxOut0 12 RxinO 16 No Connect 11 No Connect 17 TxOut1 Gnd 10 RxIn1Gnd 18 No Connect 9 No Connect 19 TxOut2gnd 8 Rxin2Gnd 20 Reserved 7 Reserved 21 Reserved 6 Reserved 22 TxClkOut 5 RxClkIn 23 TxClkOut 4 RxClkIn 24 No Connect 3 No Connect 25 TxOut3Gnd 2 RxIn3Gnd 26 No Connect 1 No Connect Pin 1 V Pin 13 Cable
25. rial Plating Screw Lock Material Plating Marking Electrical Current Rating Insulation Resistance Withstanding Voltage Environmental Temperature Rating Process UL File No E68080 3M Electronic Products Division 6801 River Place Blvd Austin TX 78726 9000 102XX 1210VE Series IMPORTANT NOTICE TO PURCHASER ALL STATEMENTS TECHNICAL INFORMATION AND RECOMMENDATIONS CONTAINED HEREIN ARE BASED ON TESTS WE BELIEVE TO BE RELIABLE BUT THE ACCURACY OR COMPLETENESS THEREOF IS NOT GUARANTEED AND THE FOLLOWING IS MADE IN LIEU OF ALL WARRANTIES EXPRESSED OR IM PLIED SELLER S AND MANUFACTURER S ONLY OBLIGATION SHALL BE TO REPLACE SUCH QUANTITY OF THE PRODUCT PROVED TO BE DEFECTIVE NEITHER SELLER NOR MANUFACTURER SHALL BE LIABLE FOR ANY INJURY LOSS OR DAMAGE DIRECT OR CONSEQUENTIAL ARISING OUT OF THE USE OF OR THE INABILITY TO USE THE PRODUCT BEFORE USING USER SHALL DETERMINE THE SUITABILITY OF THE PRODUCT FOR HIS INTENDED USE AND USER AS SUMES ALL RISK AND LIABILITY WHATSOEVER IN CONNECTION THEREWITH NO STATEMENT OR RECOMMENDATION NOT CONTAINED HEREIN SHALL HAVE ANY FORCE OR EFFECT UNLESS IN AN AGREEMENT SIGNED BY OF FICERS OR SELLER AND MANUFACTURER Date Issued February 5 1998 Glass Reinforced Polyester PCT UL 94V 0 Beige Copper Alloy C521 80 u 2 0 um Nickel QQ N 290 Class 2 20 u 0 50 um Min Gold MIL G 45204 Type II Grade Steel Nickel Copper Allo
26. y C521 Tin 3M Logo and Part Number 1A gt 5 108Q at 500 VDC 500 Vrms for 1 Minute 559 to 105 C Surface mount compatible up to 240 C peak for short durations For technical sales or ordering information call 800 225 5373 TS 0755 05 Sheet 1 of 3 050 Mini D Ribbon MDR Connectors Surface Mount Right Angle Receptacle Shielded 102XX 1210VE Series Contact 3M Part Dimensions Quantity Number A 008 B 006 C 006 006 20 10220 1210 1 32 133 4 1 081 27 45 650 16 51 646 16 4 26 10226 1210 1 50 38 2 1 231 31 26 800 20 32 795 20 2 40 10240 1210 VE 1 85 47 1 1 581 40 15 1 150 29 21 1 150 29 2 A _ position below pos 1 position above last position Ie 025 0 635 last position position 2 YV position 1 2X M2 5 Thread 010 0 25 Ol 4 i J 2X M2 5 Thread Position 1 see note in ordering info e m OH 189 4 80 Y IN O Position Positioning Boss 2x
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