Smt321 Product Manual Rev01 Iss01
Contents
1. Unit Module Name Frequency Generator Module Unit Module Number SMT321 Used On All ADC and DAC modules Document Issue 1 0 Date 10 05 2004 CONFIDENTIAL Approvals Date Managing Director Software Manager Design Engineer Sundance Multiprocessor Technology Ltd Chiltern House Waterside Chesham Bucks HP5 1PS This documents is the property of Sundance and may not be copied nor communicated to a third party without the written permission of Sundance Sundance Multiprocessor Technology Limited 1999 y UKAS QUALITY MANAGEMENT Certificate Number FM 55022 Revision History Changes Made 10 05 04 First release List of Abbreviations Abbreviation Explanation ADC Analog to Digital Converter BER Bit Error Rate BOM Bill Of Materials CDR Clock and Data Recovery DLL Delay Lock Loop DSP Digital Signal Processor FPGA Field Programmable Gate Array LSB Least Significant Bit LVDS Low Voltage Differential Signalling LVPECL Low Voltage Positive ECL MSB Most Significant Bit NA Not Applicable PC Personal Computer PCB Printed Circuit Board PCI Peripheral Component Interconnect POR Power On Reset SMT Sundance Multiprocessor Technology SPI Serial Peripheral Interface TBD To Be Determined TI Texas Instruments VCO Voltage Controlled Oscillator Table of Contents la2. two analog signals and two clock signals Triggers range from 75Hz to 5MHz and the high and low time of each trigger is programmable Each analog signal varies in frequency depending on the VCO mounted in the channel The VCO ranges available can be seen in Table 1 Clock signals range from 50MHz to 950MHz Standard Sundance Comports for easy interconnection to other Sundance products 1 3 Related Documents 1 TIM specifications ftp fto2 sundance com Pub documentation pdf files tim spec v1 01 pdf 2 MICREL SY89430VZC and SY89429AZC specifications http www micrel com 3 ANALOG DEVICES AD5235 specifications http www analog com 2 Functional Description 2 1 Module Overview The following shows a block diagram of the SMT321 Trigger Connector Trigger Connector Temprature Sensor o TTLto LVPECL TTLto T Comport3 LVPECL Analog M o Connector c VCO e o Control TexasInst Xilinx Spartan 3 FPGA n Signals MSP430F149 XC3S400 TQ144 n VCO e c Analog g Comport0 E LVPECL Connector F Clock Generation LVPECL Clock Serialnumber Generation Voltages from a board Clock Connector Clock Connector Figure 1 Functional Block Diagram of the SMT321 The user sets up the triggers analog and clock signals in the FPGA via the comports using a software interface on the Personal Computer This sets up the internal registers of the firmware design The triggers are generated by the FPGA itself It
3. 7 8 Read the SMT321 dip switches On the SMT321 there resides 8 dip switches which of 6 is connected to the FPGA Issuing this command reads the current configuration of the dips and displays it 7 9 Setup Trigger A Sets up trigger A by asking the user for the trigger s high and low time 0 65535 7 10 Setup Trigger B Sets up trigger A by asking the user for the trigger s high and low time 0 65535 7 11 Setup VCO 1 The user sets up the VCO1 frequency by giving it a frequency to output given the frequency is in the VCO s range 7 12 Setup VCO 2 The user sets up the VCO2 frequency by giving it a frequency to output given the frequency is in the VCO s range 7 13 Setup Clock A The user sets up the required clock frequency given it is in the correct range and clock synthesizers applies this frequency to the clock A output 7 14 Setup Clock B The user sets up the required clock frequency given it is in the correct range and clock synthesizers applies this frequency to the clock B output 7 15 Multiplex Trigger A CONT or PULSE User selects if trigger line A is a continuous trigger or a single pulse 0 for continuous or 1 for single pulse 7 16 Multiplex Trigger B CONT or PULSE User selects if trigger line B is a continuous trigger or a single pulse O for continuous or 1 for single pulse 7 17 Setup Pulse on Trigger A User sets up the pulse on trigger line A by giving the high time and generates
4. count bits Figure 13 Clock output equation For more information refer to the Micrel datasheets 2 4 4 3 Trigger Control Registers Registers 0x020 0x025 are used for trigger and pulse shaping Any value from 0 to 65535 16 bits can be written into these registers which shapes the triggers and pulses into high and low times There are six registers but only 3 influence one channel The Trigger A High Register Trigger B High Register One Pulse A High Register and One Pulse B High Register are all high counts counted in system clocks of the triggers Both the continuous trigger registers Trigger A High Register and Trigger B High Register and the pulse registers One Pulse A High Register and One Pulse B High Register starts counting from one Thus if for example the value 2 is written into Trigger A High Register and One Pulse A High Register the continuous trigger will be high for 2 system clocks and the pulse will be high for 2 system clocks The two low registers only have an influence on the continuous triggers which also needs a low time to shape the trigger A 1 high 1 low 1 in high register and 1 in low register would generate a continuous trigger shown in figure 14 sosti UU ts o MTT Figure 14 Trigger with 1 clock high and 1 clock low The channel can be switch between continuous trigger and pulse with the last two registers Trigger Pulse Multiplexers registers 0x026 and 0x027 If a 1 is written into any of t
5. mGMI32T NEEN ENEE 21 Table 5 Register Memory Maps sila ia ini ili 24 Table 6 Clock Control setup registers i 24 Table 7 Test een le HE EE 24 Table 8 Quiput divisioniconfig rations surreale rai 25 Table 9 Digital pod register setUp cs role iaia lepri 26 Table 10 Digital IO register setup vaare seerne 26 Table of Figures Figure 1 Functional Block Diagram of the SMT321 rea 8 Figure 2 Data path of the FPGA and Module 10 Figure 3 SMT321 PowWer StFUGHIUFe i lilla 13 Figure 4 Reset Generation and Distribution uk 14 Figure 5 Trigger path from FPGA to output ENNEN 15 Figure 6 Analog signal path from FPGA to output sssseessseeeeeeseeriieeteerrirrreesrrinnressrrene 16 Figure 7 Clock path from FPGA to Up eege erer 16 Figure 8 Connectors present on the SMT321 sea 17 Figure 9 Split JTAG Cable for SMT321 gli 17 Figure 10 Digital IOS connector present on the SMT321 18 Figure 11 Setup Packet Structure lilla aria 22 Figure 12 Control Register Read Sequence serenas 23 Figure 13 Glock outpuiequationz s ri elia ae woke eee eta 25 Figure 14 Trigger with 1 clock high and 1 clock IOW ll 25 Figure 15 One pulse generated on trigger A output ChannelATrigPulse 26 Figure 16 Module Top View nant 28 Figure 17 Module Bottom VEN Lue 28 Figure 18 Trigger A O h
6. scales a 10MHz clock by using two counters one for the high time of the trigger and one for the low time of the trigger Thus the maximum frequency attainable by the triggers is 5MHz The analog signals are generated by generating a variable voltage on the VCO using a 1024 position digital potentiometer Using the FPGA to program the potentiometer to a certain voltage the VCO s swings to new frequencies depending on the voltage applied to them Finally the clocks are generated by clock synthesizers The synthesizers are programmed to a certain frequency using the FPGA 2 2 Main Analog Characteristics The SMT321 comes in two different configurations The main differences on the two modules are clock generation and analog signal generation Table 2 shows the configuration of the lower frequencies module Table 1 shows the frequencies attainable by the various VCO s implemented on the SMT321 The high frequency configuration board is shown in Table 3 VCO Model Number Minimum Frequency Maximum Frequency UMS 150 A16 75MHz 150MHz UMS 300 A16 150MHz 300MHz UMS 535 A16 300MHz 535MHz UMS 1000 A16 500MHz 1000MHz Table 1 VCO models frequency ranges SMT321 Lower Frequencies Configuration Output Triggers LVPECL Channel A 75Hz 5MHz Channel B 75Hz 5MHz Analog Signals Analog Channel A 75MHz 150MHz Channel B 150MHz 300MHz 25MHz 400MHz 25MHz 400MHz Table 2 Analog ch
7. 321 Each connector s pin outs will be discussed in the following subsections 1 Xilinx Spartan 3 veo 4 XC35400 TQ144 Clock Sy nhesizer 5 2 Clock Sy nhesizer Figure 8 Connectors present on the SMT321 wll 8 L 3 D E 3 5 8 8 Jopauuogya lewu guong 2 10 1 FPGA amp MSP JTAG connector This connector is spilt up into the MSP and FPGA JTAG chain This cable shown in figure 9 is used to program both the MSP and FPGA 1 2 SPLIT JTAG Cable for the SMT 321 FPGA JTAG Conn SMT321 Conn Li MSP430 JTAG Conn Connector Type Connector Type 2mm IDC Type Connector 54mm Boxed Header or 2mm IDC Type Connector 2 54mm IDC Connector Signal Description Signal Description 2lFpgavRe ZIFpgavret SMT321 Side KI q SjMspims 6jFfpgatek MspTck n ia A H e 5 g 3 a Figure 9 Split JTAG Cable for SMT321 2 10 2 Digital IOS This connector has 14 pins with 8 pins directly connected to a register in the FPGA The remaining 6 pins are split up into 3 pins for 3V3 and 3 pins connected to GND Figure 10 shows the pin assignments on the digital IOS connector 87332 1410 Figure 10 Digital IOS connector present on the SMT321 2 10 3 Trigger Connectors Two trigger output connectors These triggers are LVPECL thus no ground termination must be present when implementing or measuring the signal 2 10 4 Analog Signal Connectors Two analog signal output conne
8. 5 Digital IOS output register This writeable register allows the host to pull the 8 digital IOS present on the SMT321 high or low Only the first byte MSB is used The packet is shown in table 10 Digital IOS Register Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 MSB Dig IO 7 Dig IO 6 Dig IO 5 Dig IO 4 Dig IO 3 Dig IO 2 Dig IO 1 Dig IO 0 1 LSB NO CARES Table 10 Digital IO register setup 4 4 6 Firm Ware Version This is a read only register which the host can read the firmware version 4 4 7 Com Out Scratch Registers These registers can only be read by the host and in loopback mode the host can write to the com in scratch registers and read them via the com out scratch registers 4 4 8 Smt321 Serial Number Registers The Module Serial Number registers can only be read by the Host Four registers form a unique 64 bit silicon serial number 4 4 9 Smt321 Air Temp and Smt321 Diode Temp The SMT321 has two temperature measurement registers which can only be read by the Host The data is a 255 bit representation of the module temperature measured at the MSP430 This data must be calibrated to be meaningful 4 4 10 Voltage registers of the module These registers are used to store all the voltages present on the module and to be able to take emergency actions if the voltages are suddenly out of range 4 4 11 FPGA Dip Register This register allows the host to read the FPGA
9. Data 3 Data 2 Data 1 Data 0 Figure 11 Setup Packet Structure 4 2 Reading and Writing Registers Control packets are sent to the SMT321 over Comport 3 This is a uni directional interface and data can only be sent to the SMT321 over Comport 3 Comport 0 is used to read control information back from the SMT321 Comport O is thus also a uni directional interface going from the SMT321 to the system host Data is read by issuing a Read Request control packet containing the address to be read over Comport 3 The SMT321 will collect the required data and send a Read Packet out over Comport O containing the requested data The format of a Read Packet is the same as that of a write packet 1 WritePacket Byte0 Command Address Byte Byte3 WriteData Byte4 WriteData omPort3 ComPorto 2 ReadPacket Byte0 Command Address Byte SMT321 Byte3 ReadData Byte4 ReadData Figure 12 Control Register Read Sequence 4 3 Memory Map The write packets must contain the address where the data must be written to and the read packets must contain the address where the required data must be read The following table shows the memory map for the writable and readable Control Registers on the SMT321 Address Writable Registers Readable Registers 0x000 Reserved Firm Ware Version 0x001 Com In Scratch Register 0 Com Out
10. Scratch Register 0 0x002 Com In Scratch Register 1 Com Out Scratch Register 1 0x003 Reserved Smt321 Serial Number A Register 0x004 Reserved Smt321 Serial Number B Register 0x005 Reserved Smt321 Serial Number C Register 0x006 Reserved Smt321 Serial Number D Register 0x007 Reserved Smt321 Air Temp 0x008 Reserved Smt321 Diode Temp 0x009 Reserved Smt321 D1V2 Register 0x00A Clock Control Register A Smt321 D2V5 Register 0x00B Clock Control Register B Smt321 D3V3 Register 0x00C Reserved Smt321 D5V0 Register 0x00D Reserved FPGA Dip Register Reserved Reserved Reserved Reserved 0x020 Trigger A High Register Reserved 0x021 Trigger A Low Register Reserved 0x022 Trigger B High Register Reserved 0x023 Trigger B Low Register Reserved 0x024 One Pulse A High Register Reserved 0x025 One Pulse B High Register Reserved 0x026 Trigger Pulse Multiplexer Channel A Reserved 0x027 Trigger Pulse Multiplexer Channel B Reserved Reserved Reserved Reserved Reserved 0x030 Digital Pod Register MSB Reserved 0x031 Digital Pod Register LSB Reserved Reserved Reserved Reserved Reserved 0x040 Digital IOS output register Reserved Table 5 Register Memory Map 4 4 Register Descriptions 4 4 1 Com In Scratch Registers Any value or data can be written to these 16bit registers These registers are more for debugging purposes and have no influence in the firmware design 4 4 2 Clock Control Registers These registers are use
11. a Sundance Carrier using L3 server When the application for the SMT321 is generated and run it will start by configuring the FPGA and then asking the user which SMT321 is present high frequency or low frequency The start up screen will show Start FPGA Configuration The FPGA is then configured and when it is done the following messages is shown FPGA Configuration Done After the message is shown the user is prompted to select which SMT321 is present on the board Specify type of SMT321 0 Low Freq 1 High Freq After the user has selected the board configuration a main menu will be displayed SMT321 Test Software v1 0 I Main Menu l Read SMT321 Firmware Version Write to the SMT321 Scratch Register Read the SMT321 Scratch Register Read SMT321 Temperatures Read the SMT321 Serial Number Read all the SMT321 Voltages Write any command to SMT321 Read the SMT321 dip switches RR e D ae 9 Setup Trigger A 10 Setup Trigger B 11 Setup VCO 1 12 Setup VCO 2 13 Setup Clock A 14 Setup Clock B 15 Multiplex Trigger A CONT or PULSE 16 Multiplex Trigger B CONT or PULSE 17 Setup Pulse on Trigger A 18 Setup Pulse on Trigger B 23 EXIT Select There are 19 selections available in the menu with the last selection 23 terminating the program The user must select the option by typing in the value of the selection For example if the frequency of VCO2 must be set the user will enter 12 and press enter which will the
12. aracteristics of SMT321 low frequency configuration Clock Signals LVPECL Channel A Channel B SMT321 Higher Frequencies Configuration Output Triggers LVPECL Channel A 75Hz 5MHz Channel B 75Hz 5MHz Analog Signals Analog Channel A 300MHz 535MHz Channel B 500MHz 1000MHz 50MHz 950MHz 50MHz 950MHz Table 3 Analog characteristics of SMT321 high frequency configuration Clock Signals LVPECL Channel A Channel B 2 3 Data Stream Description The module and the FPGA have three different data paths depending on the output Each architecture has two separate channels for a total of six outputs on the SMT321 The following figure illustrates the data path of the FPGA and module Trigger Setup x 2 Output Trigger Registers Trigger Output Pulse Setup x 2 Comport Decoding DigitalPod Registers Comport DigitalPod Setup Clock Setup x2 Figure 2 Data path of the FPGA and module Clock Registers The user configures the SMT321 via the comport decoding block in firmware All the registers needed for the generation of the test signals is configured by the decoding block and then all the setup blocks are enabled Once the setup blocks are enabled the registers values are clocked into the different blocks which activates the different signals If a change in any channel is desired the user sends the change to the specific register an
13. ctors These outputs are analog 2 10 5 Clock Connectors Two clock output connectors These clocks are LVPECL thus no ground termination must be present when implementing or measuring the signal 2 11 FPGA IOS Table 4 shows all of the FPGA s user IOS All pins are io standard LVTTL Pin Number lOS IO only Pin Description Standard Trigger output A LVTTL Trigger output B LVTTL Fpga to Dip switch 5 LVTTL Tim Connector 1 LVTTL Tim Connector 2 LVTTL Tim Connector 3 LVTTL 1 2 4 5 6 7 8 Tim Connector 7 LVTTL 12 Msp FPGA Bus 0 nRESET LVTTL 3 3 3 3 2 0 1 3 4 5 6 7 8 EXT10MOsc Ext 53 Osscilator LVTTL FpgaConfig12 FPGA 55 Leds LVTTL FpgaConfig13 FPGA 56 Leds LVTTL FpgaConfig10 FPGA 5 Leds LVTTL 7 5 i 0 8 9 Fpga via MSP Config LVTTL Fpga to Dip switch 3 LVTTL 6 Fpga to Dip switch 4 LVTTL 70 Fpga to Dip switch 2 LVTTL 73 Comport3 Control 1 LVTTL 5 5 6 6 6 74 Comport3 Control 2 LVTTL 86 Msp FPGA Bus4 LVTTL 95 96 7 8 9 107 Dig IOS Fpga Bus 4 LVTTL 108 Dig IOS Fpga Bus 5 LVTTL 112 Adjust Clock Control AO LVTTL 113 Adjust Clock Control A1 LVTTL 116 Dig IOS Fpga Bus 3 LVTTL 125 Adjust Clock Control B3 LVTTL 127 Adjust VCO Config 5 LVTTL 129 Adjust VCO Config 3 LVTTL 130 Adjust VCO Config 4 LVTTL 131 Adjust VCO Config 1 LVTTL 132 Adjust VCO Config 2 LVTTL 135 Dig IOS Fpga Bus 2 LVTTL 137 Adjust VCO Config 0 LVTTL Dig IOS Fpga B
14. d enables the activate pulse on the specific channel The new register value will be clocked into the specific setup block and the chosen signal will change accordingly 2 3 1 Description of Internal FPGA Blocks Comport Decoding This block receives the module setting made by the user via the DSP interface using the PC It then decodes the data and configures the specific registers Trigger Registers Trigger Setup Trigger Pulse Setup and Multiplexer The trigger setup consist of six 16 bits registers three enable signals and two multiplexer signals The last two signals are needed to select between a continuous trigger and a single pulse on each channel The enable signals are split up into one for both continuous triggers and one each for the pulse triggers Separate enables are needed on the pulse generators because when asserted a single pulse goes out on the channel and then the channel stays inactive till the next enable on the pulse generator There are six 16 bit registers for the trigger operation block in firmware They are split up between the two channels thus three per channel Each channel has a trigger high register trigger low register and a pulse high register The first two registers are used in the generation of the continuous trigger The first register sets up the high time for the trigger and the second the low time for the trigger The last register sets up the high time for the single pulse The channel is switched betwee
15. d in the setup of the clock outputs of the SMT321 The table below shows the setup of the registers Clock Control Register Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 NO CARES Test Bits Output Division M Count 1 M Count Table 6 Clock Control setup registers As the comport bit stream is 16 bits long both bytes are written simultaneously The most significant byte Byte 0 contains the test bits output division bits and one M count bit The test bits selects between various internal node values and is controlled by the T 2 0 bits in the serial data stream The node values are shown in table 7 TEST FOUT FOUT S_cLock N Table 7 Test bit configurations Output division on the clock synthesizers is achieved by the two output division bits found in the first byte of the clock control registers There configurations are shown in table 8 mn O Table 8 Output division configurations The M count bits are used to configure the clock output frequency given all the constraints set by the hardware and the clock setup bits The nine bits can be programmed with any value from 200 400 475 for higher frequency board All the setup bits are then used to calculate the output with the following equation FXTAL M FOUT g x i N FXTAL 16MHz external oscillator N Value in decimal set up by the division bits M Value in decimal set up by the M
16. dip configuration There are 6 dips available thus the status of the dips is the first 6 most significant bits of the received packet The following figures shows the top and bottom view of the SMT321 5 PCB Layout BottomPrimaryTIMConnector e V V N y d V q y x SAN Q Ss o 05 gt A MA NSA NZA PA D Synhesizer Synhesizer o OD ja O re o o O Pa je o j O Digital IOS TQ144 m Cc oO to ot awn ZO Ex FPGA MSP JTAG TopPrimaryTIMConnector Figure 16 Module Top View Figure 17 Module Bottom View 6 Waveform Outputs The following figures show some screen captures of the outputs on the SMT321 Figure 18 Trigger A 1 high time 1 low time Positive side of signal Figure 19 Trigger B 10 high time 2 low time Positive side of signal Figure 20 Clock B Freq 62MHz in time Positive side of signal MLE FP E ka MN MEL DMO Ut PI Figure 21 Clock B Freq 62MHz in frequency Max Volt 1 984 Min Volt 1 688 Figure 22 Clock B 233MHz in time Positive side of signal Freq 233 64 MHz LEDS 2029 MATH MO dB BO MAZI U I OSO EN EN Figure 23 Clock B 233MHz in frequency Figure 24 VCO2 247MHz in time Figure 25 VCO2 247MHz in frequency Figure 26 VCO1 91MHz in time PAL rv So E LIRE Figure 27 VCO1 91MHz in frequency 7 User Manual The following section describes the use of the SMT321 on
17. egisters The triggers are made from the system clock 10MHz which is then scaled by using counters Thus if the triggers are set up for a high time of one clock and a low time of one clock it attains a frequency of 5MHz which is the maximum trigger frequency attainable at the system clock of 10MHz From here the trigger can be shaped into any shape as the high and low time are independent of each other If the one pulse is activated and the multiplexer selects the one pulse module it pulses the channel with one pulse of a width determined by the pulse high register If the pulse high register is set up for one it will pull the channel high for one clock system clock and pull it low indefinitely In order for another pulse to be generated the pulse module must receive an enable signal which will once again send a pulse down the channel with a width depending on the register value The two channels are totally independent and thus can be used in this fashion For example having a pulse activated on Channel A with a width of 30 clocks and a continuous trigger on Channel B with a high time of 2 clocks and a low time of 10 clocks The trigger outputs are LVPECL A diagram of the trigger path from the FPGA is shown in figure 5 No ground on connector Figure 5 Trigger path from FPGA to output 2 8 Analog Signal Output As shown in Table 1 the analog signal which is generated in the two analog channels depends on the VCO present in the c
18. figures the registers accordingly and asserts the enable pin on the clock setup firmware The clock setup firmware generates the handshaking protocols and then clocks the data into the synthesizers The synthesizers then generate a clock depending on the setup given by the user 2 4 Clock Structure An external 100MHz oscillator provides the FPGA with a clock All the internal firmware operates on this frequency The Microcontroller is driven by an external 8MHz resonator Finally the two clock synthesizers are driven by external 16MHz crystal oscillators These are the only blocks needing clocks to operate 2 5 Power Supply and Reset Structure The SMT321 conforms to the TIM standard for single width modules The TIM connectors supply the module with 5 0V The module also requires an additional 3 3V power supply which must be provided by the two diagonally opposite mounting holes This 3 3V is present on all Sundance TIM carrier boards From the 5 0V the FPGA Core Voltage Vccint 1 2V and the FPGA Auxiliary voltage Vccaux 2 5V is generated The FPGA IO Voltage Vcco 3 3V is taken straight from the TIM mounting holes A TI MSP430 low power microprocessor is located on the module This microprocessor controls the power sequencing for the FPGA High efficiency DC DC converters are used to generate the lower voltages The MSP430 microprocessor also controls the reset structure for the SMT321 There are two possible reset sources f
19. hannel The VCO s are switched by the digital pod which has two outputs for both VCO s present on the board The digital pod can swing from 0 Volt to 18Volts but the VCO s only works from 1 Volt to 16 Volts High frequency boards works from 1 Volt 12 and 15 Volts which gives a decrease in the pod s resolution Depending on the VCO model and voltage applied to the VCO an analog signal can be generated in each channel independent of each other Figure 6 shows the analog signal path from the FPGA 10dBm typ Control Voltage Analogsignal Connector Digital Attenuator OdBm Pod 10dBm output GND Figure 6 Analog signal path from FPGA to output 2 9 Clock Output The two channels implemented by the clock signals each have its own setup register which contains a 14bit configuration word The clocks are generated by the two clock synthesizers present on the board And the output is LVPECL The user configures the registers via the comports and the resulting clock is then achieved When the user writes to the registers the firmware module is automatically updated and thus the clock Each channel can have a different clock running in them as there are two synthesizers and thus two different clocks Figure 7 shows the clock path from the FPGA to the output ve sad LVPECL No ground on connector Figure 7 Clock path from FPGA to output 2 10 Connectors Pin outs Figure 8 shows all the connectors on SMT
20. he two that specific channel switches to one pulse generation If a 0 is written into the register it switches to continuous trigger for the specific channel Figure 15 shows how a one pulse is enabled on the channel gt OnePulseAEnable gt TriggerPulseMUXChan Channel T rigPulse gt TriggerClock 1 Figure 15 One pulse generated on trigger A output ChannelATrigPulse If another pulse is needed the pulse high register value must be written again 4 4 4 Digital Pod Registers These writable registers are the digital pod control registers As explained earlier in the document to configure the digital pod a 24bit data word is needed which is clocked into the pod The comports however can only transmit 16 bits of data at a time so two registers is used and thus an 8 bit waste in the last register Table 9 shows the two 16 bit registers contents The MSB register contains the command address and data bits The LSB register only contains the last 8 bits of data from the word Digital Pod Register Byte Bit 7 Bit6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 MSB Command Address 1 MSB Data 2 LSB Data 3 LSB NO CARES Table 9 Digital pod register setup These registers are then combined and the last 8 bits left out making a 24 bit word in firmware which is then clocked into the digital pod For more information refer to the Analog Devices digital pod datasheets 3 4 4
21. igh time 0 low time Positive side of signal 29 Figure 19 Trigger B 10 high time 2 low time Positive side of signal 30 Figure 20 Clock B Freq 62MHz in time Positive side of sigma 31 Figure 21 Clock B Freq 62MHz in frequency aee 32 Figure 22 Clock B 233MHz in time Positive side of signal 33 Figure 23 Clock B 233MHz in frequency uuiiii i 34 Figure 24 VCO2 247MHZ in me ek NEEN 35 Figure 25 VGO2 247MHz In frequency irrita 36 Figure 26 VGOT S1MHZ initme cca oa iaia 37 Figure 27 VGO1 91MHZ in frequency criari detta sd 38 1 Introduction 1 1 Overview The SMT321 is a single width TIM module It is capable of generating two separate LVPECL triggers continuous or single pulse two separate analog test signals with the frequency depending on the VCO s on the board two separate LVPECL clock signals The triggers are generated by a Xilinx Spartan 3 FPGA XC3S400 TQ144 this FPGA also controls all the control register settings via the Comports The analog test signals are generated by two separate VCO s Microwave Corporations UMS series of VCO s for different frequency ranges Finally the two clock signals are generated by Micrel high frequency clock synthesizers 1 2 Module Features The main features of the SMT321 are shown in the following list Six seprate channels consisting of two triggers
22. it Line must be set for pulse option 15 7 18 Setup Pulse on Trigger B User sets up the pulse on trigger line B by giving the high time and generates it Line must be set for pulse option 16
23. n generate the sub menu for the particular selection in this case VCO2 Each selection will now be discussed in the following sections 7 1 Read SMT321 Firmware Version This command reads the SMT321 firmware register and displays the contents on the screen 7 2 Write to the SMT321 Scratch Register The user can write to the scratch register by using this command It has no effect on the working of the SMT321 7 3 Read the SMT321 Scratch Register Reads the scratch register by default 0x0000 7 4 Read SMT321 Temperatures Reads the MAXIM temperature sensor The sensor will display the local and remote temperature local on the chip self remote diode under the fpga 7 5 Read the SMT321 Serial Number When this command is executed the SMT321 unique serial number is read and displayed on the screen 7 6 Read all the SMT321 Voltages This command reads all the voltage registers which contains all the voltages present on the fpga and displays them 7 7 Write any command to SMT321 This command enables the user to send any command to the comports It is mainly used for debugging and values are sent in 32 bits The values are entered in decimal So if the hex value 0x10200002 is sent to the module the user must enter 270532610d and send it This command for example will setup the trigger A high register for 3 high clock cycles A thorough understanding of the SMT321 s registers is needed to use this command properly
24. n the two signals using a multiplexer and the multiplexer signal for the certain channel Digital Pod Registers and Digital Pod Setup As the comport is implemented on the SMT321 to be able to only send data in 16 bits the digital pod s registers are split up into two as it requires a 24bit data stream for setup The comport sends the first data which consists of the upper MSB 16 bits of the data word to the digital pod and then a second transmit which contains the lower LSB 8 bits of the digital pod s data word Thus 16 bits 8 bits 24 bits These two registers are then combined in a single register which is sent to the digital pod setup by sending the update signal to the digital pod firmware module Here the firmware generates a sequence of handshaking protocols and clocks the 24bit word into the digital pod The pod has a resolution of 1024 positions which is dealt into a O Volt to 18 Volt swing on the VCO s This results into a 0 0175V step size But most of the VCO s only operate from 1 Volt to 16 Volts thus some resolution is lost to these operating regions Clock Registers and Clock Setup There are two 16 bit registers in the clock setup The data word needed for the setup of the clock is only 14 bits long thus the 16 bit registers are sufficient to receive data from the comport in one cycle Each clock synthesizer two present on the board has its own register When the comport receives the data for the clock registers it con
25. nde o Bic lo q SSG 7 Weel VSI NICU PRETI ate Ro hac AR GR E EE T 7 1 2 Module Features sameie ii 7 1 3 Related Documents geess gdeeeEEguee e eegene gc 7 2 Functional Descriptions eege lio Mee ods 8 2 1 Module OVE ON ste EE 8 E ee ee Bee 9 2 3 Data Stream DESCMPUOM E 10 2 3 1 Description of Internal FPGA Blocks as 10 ee 11 2 5 Power Supply and Reset Structure alia 12 26 MSP Functional nelle earlier 14 257 Trigger ENEE Eed aiar 14 2 8 Analog Signal DUP ee 15 Rer 16 SERIES ee EE SE 16 2 10 1 FPGA amp ENEE e E 17 210 2 Digital OS quase ecra pasa datas posts la iii 18 2 10 3 Erigger GOnneCtOrs sacia es oleae baia a ene as 18 2 10 4 Analog Eet Melu EC 18 2105 RENE 18 2 PP GR OS Aer Ge 18 3 Description of MCN ACES ae ene osa 21 ST IMS ET er 21 3 2 Dignal Pod Interface i irreali 21 3 3 Glock Synthesizers Interface scarl ie sisi 21 3 4 TIM IEEE anelli eee pa 21 4 Control Register Settings rucola rina 21 4 1 Control Packet SUC UI Cease rai ne 21 4 2 Reading and Writing Registers A 22 43 Memory MIP saa 23 4 4 Register Ree TEEN 24 4 4 1 Com In Scratch Registers iaia 24 4 4 2 Clock Control Registers L vu retemuven vedatte 24 4 4 3 Trigger Control Registers secs 1a recat eege deeg Eder 25 4 4 4 Digital ee Mee TEE 26 4 4 5 Digital IOS output register prelati 26 4 4 6 Firm Ware Versione A cece tesa sas Mecca iii 27 4 4 7 Com Out Scratch Registers ss ute oases wie da ec ate eee 27 4 4 8 Sm
26. or the SMT321 1 A reset is received over the TIM connector 2 After power up an internal POR in the MSP430 causes a reset The MSP430 distributes the reset to the FPGA The following two diagrams illustrate the power distribution and the reset distribution on the SMT321 Tihi Connector D 240 IN Ve caux DC DC Converter Tm Connector D 5VO IN TM D 18 IN Mounting Hole jr ear DC DC D 3W3 IN Converter On Off Control MSP430 Microprocessor Main Module Figure 3 SMT321 Power Structure TIM Connector Reset PORReset ResetControl Fpga nReset Figure 4 Reset Generation and Distribution 2 6 MSP Functionality The MSP430 implements analog control functionality that is difficult to implement in the FPGA The microprocessor e Controls the power start up sequence e Controls the reset structure on the module e Read the temperature from the MAXIM temperature sensor e Read the serial number from the MAXIM silicon serial number package The measured information is passed on to the FPGA over a custom bus implementation between the microprocessor and the FPGA 2 7 Trigger Output As discussed in the internal data path of the FPGA the triggers operate in two channels and each channel has three setup registers Each channel can have a continuous trigger or a single pulse generated in one channel depending on the multiplexer The user configures the triggers via the comports which sets up the trigger r
27. t321 Serial Number Registers 27 4 4 9 Smt321 Air Temp and Smt321 Diode Temp nn 27 4 4 10 Voltage registers of the module eee 27 4 4 11 FPGA Dip RENSE ee 27 e EE 28 6 Waveform euer 29 FALO Eis Iii pib js RAP Ra Br reese dille ege GRE RE RE RAE E DOR RUM RE 39 7 1 Read SMT321 Firmware Versioni fusa nlanA Anta dae Ae gc 40 7 2 Write to the SMT321 Scratch Register e 40 7 3 Read RECKEN 40 7 4 Read SM 1321 Temperature ile 40 7 5 Read the SMT321 Serial Number ssrnnnnnnnrnnnvnnnnnnnarnrnnnnnarnrnnnennnnnnnnrnnnnnnnnnnnnn 41 7 6 Read all the SMT321 Voltages 2sarirnnansnimsiajejmnnrijempuea fanene iene 41 7 7 Write any command to SMT321 liana alari 41 78 Read the SMT321 dip switChes arretra 41 KO Setup Trigger EE 41 TAO Setup Trigger rreren RR A meet ate RA 41 LSP Di WEE 41 Role Stp VCO 2 used 42 LS OCU COC Ar see 42 7 14 Setup Clock E 42 7 15 Multiplex Trigger A CONT or PULSE o 42 7 16 Multiplex Trigger B CONT or PULSE o 42 TA 7 Setup Pulse on Trigger Ara hanger ek eink i ne es Ee 42 7 18 Setup Pulse on Trigger E 42 Table of Tables Table 1 VCO models frequency ranges ENER EEN 9 Table 2 Analog characteristics of SMT321 low frequency configuration 9 Table 3 Analog characteristics of SMT321 high frequency configuration 9 Table 4 User IOS of FPGA
28. the Comports The settings of the triggers the clock settings and the settings of the analog signals settings can be configured via the Control Registers 4 1 Control Packet Structure The data passed on to the SMT321 over the Comports must conform to a certain packet structure Only valid packets will be accepted and only after acceptance of a packet will the appropriate settings be implemented The first four bits indicate the operation which must be preformed There are four operations e Comport Reset bit sequence 1111 e Loop back Mode bit sequence 0000 e Comport Register Write Command bit sequence 0001 e Comport Register Read Command bit sequence 0010 The next 12 bits specifies the register to read or write In the first two commands Reset and Loop back the rest of the packet is NO CARES The read command packet only needs the first 2 bytes to read a specific register the last two bytes are NO CARES Write commands use the whole packet with the last 2 bytes being the data to be written to the specific register This structure is illustrated in the following figure Byte Content Byte Bit7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 Command Command Command Command Address Address Address Address 1 11 10 9 8 1 Address 7 Address 6 Address 5 Address 4 Address 3 Address 2 Address 1 Address 0 2 Data 15 Data 14 Data 13 Data 12 Data 11 Data 10 Data 9 Data 8 3 Data 7 Data 6 Data 5 Data 4
29. us 0 LVTTL Dig IOS Fpga Bus 1 LVTTL Table 4 User IOS of FPGA in SMT321 3 Description of interfaces 3 1 MSP430 Interface A custom interface is implemented between the FPGA and the microprocessor The microprocessor is the master and the FPGA is the slave This interface is used for issuing a reset command to the FPGA and for the microprocessor to write the ADC temperature and silicon serial number to the FPGA 3 2 Digital Pod Interface A three wire uni directional control interface is implemented between the FPGA and the digital trim pod This pod sets the voltage for the VCO s that generates the analog signal outputs 3 3 Clock Synthesizers Interface A three wire uni directional control interface is implemented between the FPGA and the clock synthesizers These synthesizers control the clock output of the SMT321 3 4 TIM Interface The SMT321 implements Comports O and 3 All configuration data is received and transmitted over these two ports Comport 3 is implemented as a uni directional receive interface and only receives data sent to the SMT321 Comport 0 is implemented as a uni directional transit interface and only transmits data from the SMT321 The Global Bus Interface is not implemented on the SMT321 Refer to 1 for a more detailed description of the TIM interface 4 Control Register Settings The Control Registers in the SMT321 control the complete functionality of the SMT321 These Control Registers are setup via
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