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TM8726 User`s Manual

1. LCD Panel x 3 58 2 Crystal COM 1 9 SEG1 41 E z 9 0 0 14 CUP LF 15 L Px t CUP r 15 32 768KHz EM XOUT PS VDD2 DIS R H VDDI ewr 55 R BAK Jou e 0 AA T 1 30 lu 05 GND 4 2 L TM8726 LE 4 _ EL R RESE P EL Plant 1 External INT s INT ELC Av G WIOA IOB IOC IOD Choke CL Buzzer Port i BZ BZB i 6 E Scanning Key Matrix Li power mode 1 4 Bias 1 9 Duty 12 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual Chapter2 8726 Internal System Architecture 2 1 Power Supply TM8726 can operate with 3 types voltage supplies Ag Li and EXT V all of these operating types are defined by the mask option The power supply circuitry also generates the necessary voltage level for driving the LCD panel with a different bias Shown below are the connection diagrams for 1 2 bias 1 3 bias 1 4 bias and no bias applications 2 1 1 Ag BATTERY POWER SUPPLY Operating voltage range 1 2V 1 8V The connection diagrams for different LCD bias applications are shown below 2 1 1 1 NO LCD BIAS NEED AT Ag BATTERY POWER SUPPLY Application circuit H xc H Nc L H Ne
2. 34 245 STACK REGISTER S TAGI 5 35 FOTNENP Myweb 36 2 8 WORKING REGISTER 37 2 0 ACCUMULATOR AC 38 2 10 ALU Arithmetic and Logic Unit 38 2 11 HEXADECIMAL CONVERT DECIMAL HCOD 38 2 MAMER pb TMR u u N 39 2 13 MERZ IMR2 5 5 uuu D nnn E M M DEI IPM I DDR D LDAP IEEE 42 2 14 STATUS REGISTER ST duni 47 2 15 CONTROL REGISTER 53 2 16 HALT FUNGTION Z uuu rr 57 2 17 HEAVY LOAD FUNCTION uuu quwan asal 58 2 18 STOP PUNGTUION STOP uuu k u nu uy 59 2 19 BACK UP IFUNGTION E u L uuu u IT pu Sei Swan tona EE 60 Chapter 3 Control Function 62 3 1 INTERRUPT FUNCTION 62 ae RESET FUNCTION u E 66 253 CLOCK GENERATOR u 71 3 4 BUZZER OUTPUT PINS 73 p INPUT OUTPUT PORTS 5
3. Instruction Bit Bite Bits Bito SPKX X X7 X6 X5 x3 x2 X SPK Rx AC2 AC1 ACO Rx3 R2 Rd Rx0 SPK HL T HL7 T HL6 T HL5 T HL4 T HL3 T HL2 T HL1 The following description shows the bit definitions in the operand of the SPKX instruction Xs 0 when HEF5 is set to 1 the HALT release request HRF5 will be set to 1 after the key depressed on the key matrix and then SCF8 will be set to 1 1 when HEF5 is set to 1 the HALT released request HRF5 will be set to 1 after each scanning cycle regardless of key depression and then SCF8 will be set to 1 X7Xs5X4 000 in this setting each scanning cycle only checks one specified column K1 K16 on the key matrix The specified column is defined by the setting of X3 Xo X3 Xo 0000 activates K1 column Xo 0001 activates K2 column Xo 1110 activates K15 column Xo 1111 activates K16 column 93 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual X7 X5X4 001 in this setting all of the matrix columns K1 K16 will be checked simultaneously in each scanning cycle Xs Xo are not a factor X7X5Xq4 010 in this setting the key matrix scanning function will be disabled Xo are not a factor X7X5X4 10X in this setting each scanning cycle checks 8 specified colum
4. 8726 MASK OPTION table Mask Option name Selected item POWER SOURCE 3 1 5V BATTERY BIAS 1 NO BIAS Note 1 The input output ports operate between GND and VDD1 Note 2 The backup flag BCF is set in the initial clear mode When the backup flag is set the oscillator circuit uses a larger driving force to operate and the oscillation conditions are improved but the operating current is also increased Therefore the backup flag should be reset unless otherwise required For information on the backup flag refer to 3 5 13 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual 2 1 1 2 MASK OPTION table CUPO r N C CUP1 0 1u CUP2 VDD4 VDD3 VDD2 VDD1 Internal BAK logic GND Mask Option name Selected item POWER SOURCE 3 1 5V BATTERY BIAS 2 1 2 BIAS Note 1 input output ports operate between GND and VDD1 1 2 BIAS amp STATIC AT Ag BATTERY POWER SUPPLY 45V Note 2 The backup flag BCF is set in the initial clear mode When the backup flag is set the oscillator circuit uses a larger driving force to operate and the oscillation conditions are improved but the operating current is also increased Therefore the backup flag should be reset unless otherwise required For
5. LCD frame frequency 1 SLOW 28Hz LCD frame frequency 2 TYPICAL 56Hz LCD frame frequency 2 FAST 113Hz LCD frame frequency 2 O P OHz LCD not used The following table shows the relationship between the LCD lighting system and the maximum number of driving LCD segments cousin Sion ettet Rona Duplex 1 2 bias 1 2 duty Connect VDD3 and VDD4 to VDD2 1 2bias 1 3duty Connect VDD3 and VDD4 to VDD2 1 2bias 1 4dut Connect VDD3 and VDD4 to VDD2 1 2bias 1 5duty Connect VDD3 and VDD4 to VDD2 1 2bias 1 6dut Connect VDD3 VDD4 to VDD2 1 2bias 1 7duty Connect VDD3 and VDD4 to VDD2 1 2bias 1 8dut Connect VDD3 and VDD4 to VDD2 1 2bias 1 9duty Connect VDD3 and VDD4 to VDD2 1 3 bias 1 3 duty Connect VDD4 to VDD3 1 3 bias 1 4 duty Connect VDD4 to VDD3 1 3 bias 1 5 duty Connect VDD4 to VDD3 1 3 bias 1 6 duty Connect VDD4 to VDD3 1 3 bias 1 7 duty Connect VDD4 to VDD3 1 3 bias 1 8 dut Connect VDD4 to VDD3 1 3 bias 1 9 duty Connect VDD4 to VDD3 1 4 bias 1 3 dut 1 4 bias 1 4 duty 1 4 bias 1 5 dut 1 4 bias 1 6 duty 1 4 bias 1 7 dut 1 4 bias 1 8 duty 99 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual When choosing the LCD frame frequency it is recommended to chose a frequency higher than 24Hz If the frame frequency is lower than 24Hz the pattern on the LCD panel will start to flash 4 2 DC OUTPUT TM8726 permits LCD driver output pins COM5 9 and SEG1 SEG41 to
6. 5 nnn rennes 131 5 7 DECIMAL ARITHMETIC 5 132 5 8 JUMP INSTRUCTIONS 133 5 9 MISCELLANEOUS INSTRUCTIONS weiner 135 Appendix 8726 Instruction Table eese 141 Symbol Desceripti n M 148 2 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual Chapter 1 General Description 1 1 GENERAL DESCRIPTION The TM8726 is an embedded high performance 4 bit microcomputer with LCD driver It contains all the of the following functions in a single chip 4 bit parallel processing ALU ROM RAM ports timer clock generator dual clock operation Resistance to Frequency Converter RFC EL panel driver LCD driver look up table watchdog timer and key matrix scanning circuitry 1 2 FEATURES Low power dissipation 2 Powerful instruction set 178 instructions e Binary addition subtraction BCD adjusts logical operation in direct and index addressing mode Single bit manipulation set reset decision for branch Various conditional branches 16 working registers and manipulators Table look up LCD driver data transfer 3 Memory capacity ROM capacity 4096 x 16 bits RAM capacity 512 x4 bits 4 LCD driver output outputs and 41 segment outputs up to dr
7. T2 T3 T4 Machine Cycle 4 Instruction gt Cycle 30 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual 2 3 PROGRAM COUNTER PC This is a 12 bit counter which addresses the program memory ROM for up to 4096 addresses The MSB of program counter PC11 is a page register Only CALL and JMP instructions can address the whole address range 000h FFFh the rest jump relative instructions can address either page 0 000h 7ffh or page 1 800h FFFh The program counter PC is normally increased by one 1 with every instruction execution PC PC 1 When executing JMP instructions subroutine call instructions CALL interrupt service routines or if reset occurs the program counter PC loads the specified address corresponding to table 2 1 PC specified address shows in Table 2 1 When executing any jump instruction except JMP and CALL the program counter PC loads the specified address in the operand of instruction All of these jump relative instructions can only address the current page That means when the current page is page 0 11 0 only the range 000 7FFh is reachable when the current page is page 1 PC11 1 only the range 800h FFFh is reachable PC current page 11 specified address in operand Return instruction RTS PC content of stack specif
8. VDD1 BAK Je elle EXTV Internal logic 19 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual MASK OPTION table Mask Option name Selected item POWER SOURCE 1 EXT V BIAS 2 1 2 BIAS Note 1 The input output ports operate between GND and VDD2 Note 2 At the initial clear mode the backup flag BCF is reset Note 3 At the backup flag set mode the operating current is increased Therefore the backup flag must be reset unless otherwise required 2 1 3 3 1 3 BIAS AT EXT V POWER SUPPLY CUPO wc CUP1 0 1u zx CUP2 VDD4 VDD3 VDD2 VDD1 EXIV Internal logic GND e MASK OPTION table Mask Option name Selected item POWER SOURCE 1 EXT V BIAS 3 1 3 BIAS Note 1 The input output ports operate between GND and VDD2 Note 2 At the initial clear mode the backup flag BCF is reset Note 3 At the backup flag set mode the operating current is increased Therefore the backup flag must be reset unless otherwise required 20 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual 2 1 3 4 1 4 BIAS AT EXT V POWER SUPPLY CUPO CUP1 CUP2 VDD4
9. Mask Option name Selected item IOA PULL LOW RESISTOR 1 USE IOA PULL LOW RESISTOR 2 NO USE 76 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual Initial clear SPA 1 Note M O is mask option This figure shows the organization of IOA port Note If the input level is in the floating state a large current straight through current flows to the input buffer The input level must not be in the floating state 3 5 1 1 Pseudo Serial Output IOA port may operate as a pseudo serial output port by executing the OPAS instruction IOA port must be set to output mode before executing the OPAS instruction 1 BITO and BIT1 of the port deliver RAM data 2 BIT2 of the port delivers the constant value of the OPAS 3 of the port delivers pulses Shown below is a sample program using the OPAS instruction 1 105 OAH 0 2 OPA OAH SPA OFH LDS 1 5 3 OPAS 1 1 Bit 0 output shift gate open 4 SRO 1 Shifts bit 1 to bit 0 5 OPAS1 1 Bit 1 output 77 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual 6 SRO 1 Shifts bit2 to bit 0 7 1 1 Bit2 output 8 SRO 1 Shifts bit 3 to bit 0 9 OPAS1 1 Bit3 output 10 OPAS1 1 Lastdata 11 OPAS1 0 Shiftgate closes The timing chart below illustrates the above program 1 2 3 4 5 6 7 8 9 10 11 0 5 2 1 IOA1 BitO for
10. 1 Enables the strong pull low device on INT pin X2 1 Turns off the LCD display temporarily X1 1 Sets the DED flag Refer to 2 12 3 for detail 1 Enables the re load function of timer 2 Resets flag Description of each flag 1 Disables the strong pull low device on INT pin X2 1 Turns on the LCD display 139 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual PLC Function Description X1 XO 1 Resets the DED flag Refer to 2 12 3 for detail 1 Disables the re load function of timer 2 Pulse control The pulse corresponding to the data specified by X is generated XO X1 X2 X3 5 6 X8 1 Halt release request flag HRFO caused by the signal at I O port C is reset 1 Halt release request flag HRF1 caused by underflow from the timer 1 is reset and stops the operating of timer 1 TM1 1 Halt or stop release request flag HRF2 caused by the signal change at the INT pin is reset 1 Halt release request flag HRF3 caused by overflow from the predivider is reset 1 Halt release request flag HRF4 caused by underflow from the timer 2 is reset and stops the operating of timer 2 TM2 1 Halt release request flag HRF5 caused by the signal change to L on KI1 4 in scanning interval is reset 1 Halt release request flag HRF6 caused by overflow from the RFC counter is reset 1 The last 5 bits
11. NEN Die size 1750um x 2580um L L L L L D Oooo0o000000000000000 20 The substrate of the chip should be connected to the GND 5 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual 1 5 PAD COORDINATE 1677 50 1677 50 1677 50 1677 50 SEG16 K16 1677 50 SEG17 1677 50 SEG18 1677 50 SEG19 1677 50 SEG20 1677 50 5 21 1677 50 5 22 1677 50 5 23 1558 50 SEG24 IOA1 CX 1430 45 SEG25 IOA2 RR 1305 00 SEG26 IOA3 RT 1164 50 SEG27 IOA4 RH 1024 00 SEG28 IOB1 ELC 881 50 SEG29 IOB2 ELP 766 50 SEG30 IOB3 BZB 651 50 SEG31 IOBA BZ 536 50 SEG32 IOC1 KI1 421 50 SEG33 IOC2 KI2 306 50 SEG34 IOC3 KI3 191 50 SEG35 IOC4 KI4 72 50 SEG36 IOD1 72 50 SEG37 IOD2 72 50 SEG38 IOD3 72 50 SEG39 IOD4 72 50 SEG40 72 50 SEG41 72 50 72 50 72 50 1677 50 1129 50 72 50 1359 50 6 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual 1 6 PIN DESCRIPTION Name 10 Description BAK Positive Back up voltage When using the Li power mode connect a 0 1u capacitor to GND VDD1 2 3 4 LCD supply voltage and positive supply voltage When using the Ag mode connect positive power to VDD1 When using the Li or ExtV power mode connect positive power to VDD2 RESET Input for external reset request signal built in internal
12. RU ANDD ANDI RyD 00 10 DDDD YYYY Ry lt Ry AND D tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual Instruction Machine Code Function Flag Remark EORI RyD 0011 1100 DDDD YYYY AC lt EOR D EORI Ry D 0011 1101 DDDD YYYY AC Ry lt Ry EOR D ORI Ry D 0011 1110 DDDD lt ORD ORI RyD 0011 1111 DDDD YYYY Ry lt Ry ORD INC Rx 0100 0000 OXXX XXXX Rx Rx 1 CF INC HL 0100 0000 1000 0000 AC R HL lt R HL 1 CF INC HL 0100 0000 1100 0000 AC R HL lt R HL 1 CF HL lt HL 1 DEC Rx 0100 0001 OXXX AC Rx lt 1 HL 0100 0001 1000 0000 AC R HL lt RGHL 1 CF DEC HL 0100 0001 1100 0000 AC R HL lt RQHL 1 CF HL lt HL 1 IPA Rx 0100 0010 OXXX AC Rx lt IOA 0100 0100 OXXX AC Rx lt Rx 0100 0111 OXXX XXXX lt IOC IPD Rx 0100 1000 OXXX lt 0100 1010 OXXX lt STS1 B3 CF B2 ZERO B1 No use BO No use MSB Rx 0100 1011 OXXX XXXX Rx lt STS2 SCF3 DPT B2 SCF2 HRx B1 SCF1 CPT BCF MSC Rx 0100 00 OXXX XXXX
13. VDD3 VDD2 VDD1 0 1u O 1u 0 1u BAK EXIV Internal logic GND e e MASK OPTION table Mask Option name Selected item POWER SOURCE 1 EXT V BIAS 4 1 4 BIAS Note 1 The input output ports operate between GND and VDD2 Note 2 At the initial clear mode the backup flag BCF is reset Note 3 At the backup flag set mode the operating current is increased Therefore the backup flag must be reset unless otherwise required 21 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual 2 2 SYSTEM CLOCK The XT clock slow clock oscillator and CF clock fast clock oscillator compose the clock oscillation circuitry and the block diagram is shown below BCLK T1 T2 T3 T4 Sclk Slow instruction Clock switch System clock circuit generator L Clock switch PHO circuit XT Clock CF Clock Single clock option Dual clock option The system clock generator provides the necessary clocks for execution of instruction The pre divider generates several clocks with different frequencies for the LCD driver frequency generator etc to use The following table shows the clock sources of system clock generators and pre divider under different conditions Slow clock only option XT clock XT clock fast clock only option CF cl
14. 1st 2nd 3rd 4th 5th 6th 7th 8th 52 64 64 64 64 64 64 64 4 count count count count count count count count TMS HRF1 ha I I I K Re load In this example S W enters the halt mode to wait for the underflow of TMR1 initiates the underflow counting register RE LOAD END 1 LDS 0 0 PLC 2 SHE 2 TMSX 34h SF 80h HALT INC 0 PLC 2 JB3 1 JMP RE LOAD RF 80 2 13 TIMER 2 TMR2 The following figure shows the TMR2 organization Re load RL2 enables the HALT release caused by TMR1 initiates the TMR1 value 52 and clock source is 9 enable the re load function increases the underflow counter clears HRF1 if the TMR1 underflow counter is equal to 8 exit subroutine disables the re load function FREQ 3 5 97 99 11 13 15 Operand Data X8 X7 X6 5 2 instruction IEF 4 R Initial reset TM2 6 bit binary down Interrupt counter s HRF4 SCF 6 Halt release HEF Operand Data 4 X5 X0 TM2 instruction TM2 instruction Interrupt accept signal R PLC 10h instruction Qu TENX Initial reset DED 5 Control signal of RFC counter falling edge of the 1st clock after TM2 is enabled 42 tenx technol
15. 10 83 SEG n 1 8 2 2 V Output M2 Voltage Vom22h lol h 10uA 1 2 2 2 2 6 V Vom23h lol h 10UA 3 3 8 4 2 V Output L Voltage Vol2h lol 1uA 1 2 0 2 V Vol3h_ lol 1uA 3 0 2 V Output H Voltage Voh12i loh2 10u0A 71 22 3 4 V Voh3i 10 83 5 8 V Output M1 Voltage Vom12i lol n 10UA 1 2 1 0 1 4 V Vom13i 101 100 3 COM n 1 8 2 2 V 10 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual Name Symb Condition For Min Typ Max Unit Output M2 Voltage Vom22i lol n 10UA 1 2 2 2 2 6 V Vom23i lol h 10uA 3 3 8 4 2 V Output L Voltage Vol12i lol 10u0A 71 22 0 2 V Vol3i lol210uA 73 0 2 V 1 4 Bias display Mode Output H Voltage Voh12j loh 1uA 1 2 4 6 V Output M2 Voltage Vom22j 101 100 1 2 SEG n 22 2 6 V Output L Voltage Vol12j 1 41 2 0 2 V Output H Voltage Voh12k 100 1 2 4 6 V Output M1 Voltage Vom12k lol n 10UA 1 4 2 COM n 1 0 1 4 V Output M3 Voltage Vom22k lol n 10UA 1 2 3 4 3 8 V Output L Voltage Vol12k 101 100 1 2 0 2 V 11 tenx technology inc Rev 1 1 2007 06 28 Advance Informa tion 1 8 TYPICAL APPLICATION CIRCUIT TM8726 User s Manual This application circuit is simply an example and is not guaranteed to work a
16. 76 2 5 EL PANEL DRIVER s ott 85 3 EXTERNAL INT PUN 87 1 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual 3 8 Resistor to Frequency Converter 88 3 9 Key Matrix SCI ia EE 93 Chapter 4 LCD DRIVER OUTPUI 97 4 1 LCD LIGHTING SYSTEM IN TM8726 bb a SR pai cii h uti 97 4 2 DG OUT PUT S 100 4 3 SEGMENT PLA CIRCUIT FOR LCD 101 Chapter 5 Detailed Explanation of the TM8726 Instructions 106 5 1 INPUT OUTPUT INSTRUCTIONS 255 DUUM 106 5 2 ACCUMULATOR MANIPULATION INSTRUCTIONS AND MEMORY 114 5 3 OPERATION INSTRUCTIONS eM bt mu MER iE 116 5 4 LOAD STORE INSTRUCTIONS a 126 5 5 CPU CONTROL INSTRUCTIONS 128 5 6 INDEX ADDRESS
17. SRA IZ AS o BRA Advance y tenx technology inc Information TM8726 4 Bit Micro Controller with LCD Driver User s Manual Tenx reserves the right to change or discontinue this product without notice tenx technology inc tenx technology inc v 1 1 2007 06 28 Advance Information TM8726 User s Manual CONTENTS Chapter 1 General Description 1122222 3 1 1 GENERAL DESCRIPTION bp 3 152 LU sime 3 1 29 BLOCK DIAGRAM uu u u ra ERR tuin HN Ban 4 t4 PAO DIAGRAN Rec uu uuu uy uu nus M 5 1 5 PAD COORDINATE 6 To PINDESGRIPTION SR u us s u ERR 7 CHARACTERIZATION u E Ua o uu Pt Expat gr Reda i aysasha 8 1 8 TYPICAL APPLICATION CIRCUIT a 12 Chapter2 8726 Internal System Architecture 13 Power Supply uuu uu u aus a ass uha 13 2 2 SYSTEM CLOCK CPP 22 2 3 31 2 4 PROGRAM TABLE MEMORY 32 2 5 INDEX ADDRESS REGISTER 2
18. Advance Information IEF2 Interrupt request HEF2 SCF2 Halt release request Mask option HRF 2 PLC 4h nitial clear pulse Interrupt 2 receive signal Mask option Open type Note For Ag battery power supply positive power is connected to VDD1 for anything other than Ag battery power supply it is connected to VDD2 This figure shows the INT Pin Configuration 3 8 Resistor to Frequency Converter RFC The resistor to frequency converter RFC can compare two different sensors with the reference resistor separately This figure shows the block diagram of RFC SRF 8h Controlled by Timer 2 SRF 18h SRF 28h CX pin signal interrupt request scro counter over flow flag enable CNT HRF6 16 bit counter CLKIN 4 bit data bus SRF 18h SRF 28h FREQ output from frequency generator to data memory and AC tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual This RFC contains four external pins CX the oscillation Schemmit trigger input RR the reference resister output pin RT the temperature sensor output pin RH the humidity sensor output pin this can also be used as another temperature sensor or can even be left floating These CX RR RT and RH pins are MUXed with IOA1 SEG37 to 4 SEG40 respectively and selected by mask option
19. 2 2 2 1 External 3 58MHz Ceramic Resonator oscillator MASK OPTION table Mask Option name Selected item FAST CLOCK TYPE FOR FAST ONLY OR DUAL 4 3 58MHz Ceramic Resonator CEOUT 5 3 cm 3 58MHz Ceramic Resonator Notes 1 Don t use 3 58MHz Ceramic Resonator as the oscillator when the Ag battery option is used 2 When the program has to reset the BCF flag to 0 in Li battery power mode don t use a 3 58MHz Ceramic Resonator as the oscillator 2 2 2 2 RC oscillator with External Resistor connection diagram is shown below 24 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual MASK OPTION table Mask Option name Selected item FAST CLOCK TYPE FOR FAST ONLY OR DUAL 3 EXTERNAL RESISTOR CFOUT R External Resistor 2 2 2 3 Internal RC Oscillator MASK OPTION table For 250KHz output frequency Mask Option name Selected item FAST CLOCK TYPE FOR FAST ONLY OR DUAL 1 INTERNAL RESISTOR FOR 250KHz For 250KHz output frequency Mask Option name Selected item FAST CLOCK TYPE FOR FAST ONLY OR DUAL 2 INTERNAL RESISTOR FOR 500KHz CFOUT FIN N C Z Q Internal RC FREQUENCY RANGE OF INTERNAL RC OSCILLATOR Option Mode BAK Min Typ Max 250KHz 1 5V 200KHz 300KHz 400KHz 3 0V 200KHz 250KHz 300KHz 500KHz 1 5V 450KHz 600KHz 750KHz
20. AC HL lt HL AC HL HL 1 Binary adds the contents of HL and AC the result is loaded to AC and the data memory HL The content of the index register HL will be incremented automatically after executing this instruction HL indicates an index address of data memory The carry flag CF will be affected AC Rx AC B 1 Binary subtracts the content of AC from the content of Rx the result is loaded to AC The carry flag CF will be affected AC lt HL AC B 1 Binary subtracts the content of AC from the content of HL the result is loaded to AC HL indicates an index address of data memory The carry flag CF will be affected AC lt HL AC B 1 HL HL 1 Binary subtracts the content of AC from the content of HL the result is loaded to AC The content of the index register HL will be incremented automatically after executing this instruction HL indicates an index address of data memory The carry flag CF will be affected 119 tenx technology inc Rev 1 1 2007 06 28 Advance Information SUB Rx Function Description SUB HL Function Description SUB Function Description ADN Rx Function Description ADN HL Function Description AND HL Function Description ADN Rx Function Description TM8726 User s Manual Rx lt Rx AC B 1 Binary subtracts the content of AC from the content o
21. DAT lt 8 RAM e lt 2 a 7 B is Working 8 Register 28 Y lt 80H 5 lt 1FFH 4 Bits This figure shows the Data Memory RAM and Working Register Organization 2 8 WORKING REGISTER WR The locations 70H to 7FH of the data memory RAM are not only used as general purpose data memory but also as working registers WR The following will introduce the general usage of working registers 1 They can be used to perform operations on the contents of the working register and immediate data Such as ADCI ADCI SBCI SBCI ADDI ADDI SUBI SUBI ADNI ADNI ANDI ANDI EORI EORI ORI ORI 2 They can be used to transfer data between the working register and any address in the direct addressing data memory RAM Such as MWR Rx Ry MRW Ry Rx 3 They can be used to decode or directly transfer the contents of the working register and output to the LCD PLA circuit Such as LCT LCB LCP 37 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual 2 9 ACCUMULATOR AC The accumulator AC is a register that plays the most important role in operations and controls By using it in conjunction with the ALU Arithmetic and Logic Unit data transfer between the accumulator and other registers or data memory is made possible 2 10 ALU Arithmetic and Logic Unit This is circuitry that performs arithmetic and logic operations The ALU provides the
22. Description SBC Rx Function Description SBC Function Description SBC Function Description ADD Rx Function Description ADD HL Function Description TM8726 User s Manual AC lt HL AC B CF Binary subtracts the contents of AC and CF from the content of HL the result is loaded to AC HL indicates an index address of data memory The carry flag CF will be affected AC lt HL AC B CF HL HL 1 Binary subtracts the contents of AC and CF from the content of HL the result is loaded to AC The content of the index register HL will be incremented automatically after executing this instruction HL indicates an index address of data memory The carry flag CF will be affected AC Rx lt Rx AC B CF Binary subtracts the contents of AC and CF from the content of Rx the result is loaded to AC and the data memory Rx The carry flag CF will be affected AC HL HL AC B CF Binary subtracts the contents of AC and CF from the content of HL the result is loaded to AC and the data memory HL HL indicates an index address of data memory The carry flag CF will be affected AC HL lt HL AC B CF HL HL 1 Binary subtracts the contents of AC and CF from the content of HL the result is loaded to and the data memory HL The content of the index register HL will be incremented automatically after
23. Halt release PH15 PH9 PH11 Operand data 5 0 TMS instruction Interrupt accept signal 2 2 TMS instruction Initial reset This figure shows the 1 organization FREQ PH3 39 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual 2 12 1 NORMAL OPERATION TMR1 consists of a programmable 6 bit binary down counter which is loaded and enabled by executing the TMS or TMSX instructions Once the TMR1 counts down to 3Fh it generates an underflow signal to set the halt release request flag 1 HRF1 to 1 and then stops counting down When HRF1 1 and the TMR 1 interrupt enable flag IEF1 1 an interrupt is generated When HRF1 1 if the IEF1 0 and the TMR1 halt release enable HEF1 1 the program will escape from halt mode if CPU is in halt mode and then set the start condition flag 5 SCF5 to 1 in the status register 3 STS3 After power on reset the default clock source of TMR1 is PH3 If watchdog reset occurs the clock source of TMR1 will remain the same The following table shows the definition of each bit in TMR1 instructions OPCODE Select clock TMSX X TMSRx 0 AC2 ACO Rx3 Rx2 Rx1 Rx0 TMS QHL bit6 bits Bit4 bit3 bit2 bitt bito The following table shows the clock source setting for TMR1 1 When the TMR2 clo
24. O 1 nday pot 1 aduy FRQX D X Function Frequency generator lt D X Description Loads the data X X7 X0 and D D1 DO to the frequency generator to set the duty cycle and initial value The following table shows the preset r 2 and the duty cycle setting am Bit7 Bit Bit5 Bit4 Bit2 bit 1 FRQX DX xz xe X5 x4 x3 X2 x1 xo Note X0 X7 represents the data specified in operand X Preset E D Duty Cycle 0 mur 0 1 nday 1 0 ty Pt tty 1 FRQ D Rx The content of Rx and AC as preset data N 2 FRQ D HL The content of table ROM specified by HL as preset data 3 FRQX D X The data of operand in the instruction assigned as preset data N TMS Rx Function Select the timer 1 clock source and preset timer 1 Description The content of the data memory specified by Rx and AC are loaded to timer 1 to start the timer 136 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual The following table shows the bit pattern for this instruction Select clock Presetting value of timer 1 The clock source selection for timer 1 L9 o i 1101 45 1 1 Output of frequency generator FREQ TMS HL Function Select the timer 1 clock source and preset timer 1 Description The content of the table ROM specified by HI is loaded to timer 1 to start the timer The f
25. lt Rx AC CF ADD HL 0010 0100 1000 0000 AC lt R HL AC CF ADD HL 0010 0100 1100 0000 R HL AC CF amp HL lt HL 1 ADD Rx 0010 0101 XXXX lt Rx AC CF ADD HL 0010 0101 1000 0000 R HL AC HL 0010 0101 1100 0000 AC R HL RQHL AC CF HL lt HL 1 SUB Rx 0010 0110 OXXX AC lt Rx 1 CF SUB HL 0010 0110 1000 0000 RGHL AC B 1 CF SUB HL 0010 0110 1100 0000 RGHL AC B 1 CF HL lt HL 1 SUB Rx 0010 0111 OXXX AC Rx lt Rx AC B 1 CF SUB HL 0010 0111 1000 0000 AC R HL lt R HL AC B 1 CF SUB HL 0010 0111 1100 0000 R HL lt R HL AC B 1 CF HL lt HL 1 ADN Rx 0010 1000 OXXX XXXX AC Rx AC ADN HL 0010 1000 1000 0000 AC RGHL AC ADN HL 0010 1000 1100 0000 lt R HL AC HL lt HL 1 ADN Rx 0010 1001 OXXX XXXX AC Rx lt AC ADN HL 0010 1001 1000 0000 R HL AC ADN HL 0010 1001 1100 0000 R HL lt R HL AC HL lt HL 1 AND Rx 0010 1010 OXXX xxxx Rx AND AC AND HL 0010 1010 1000 0000 lt R HL AND AC AND HL 0010 1010 1100 0000 lt R HL AND AC HL lt HL 1 AND Rx 0010 1011 XXXX Rx AND AC AND HL 0010 1011 1000 0000 AC R HL
26. 30 3 5 V Volic Ilol 400uA 1 0 2 0 3 0 4 V Output L Vol2c jlol 2mA 2 0 3 0 6 0 9 V Voltage Vol3c lolZ6mA Z3 0 5 1 0 1 5 V Segment Driver Output Characteristics Name Symb Condition For Min Typ Max Unit Static Display Mode Vohid loh 1uA 1 1 0 V Output H Voltage Voh2d loh 1uA 22 2 2 V Voh3d 1 3 SEG n 3 8 V Volid lol 1uA 1 0 2 V Output L Voltage Vol2d lol21uA 22 0 2 V Vol3d lol 1uA Z3 0 2 V 1 loh 10uA 1 1 0 V Output H Voltage Voh2e 10 82 2 2 V Voh3e 10 3 3 8 V Volle lol 10uA 1 0 2 V Output L Voltage Vol2e lol 10uA 2 0 2 V Vol3e 101 100 3 0 2 V 1 2 Bias Display Mode Output H Voltage Voh12f loh 1uA 1 2 2 2 V Voh3f jloh 1uA 3 SEG n 3 8 V Output L Voltage VoM2f jlol 1uA 1 2 0 2 V Vol3f lol21uA 23 0 2 V Output H Voltage Voh12g 10 81 82 2 2 V Voh3g 10 3 3 8 V Output M Voltage Vom12g lol n 10UA 1 2 1 0 1 4 V Vom3g lol h 10UuA 3 1 8 2 2 V 1 3 Bias display Mode Output H Voltage Voh12h loh 1uA 1 2 3 4 V Voh3h 1 3 5 8 V Output M1 Voltage 1 lol n 10UA 1 2 1 0 1 4 V Vom13h
27. 32ms PH8 8ms or PH6 2ms by executing the SCC instruction The default selection is PH10 after the reset cycle When the pins of the IOC port are set to output the signals applied to the output pins will be inhibited for the chattering prevention function The following figure shows the organization of chattering prevention circuitry SPC 1 SPC 2 mm m SPC 4 Edge S request SPC 8 detect 10C1 2 edge dectect amp HALT released chattering request IOC4 chattering pubs prevention PH6 a t nterrupt acce SCC S Q ae intruction 5 intruction Note The default prevention clock is PH10 This chattering prevention function works when the signal at the applicable pin ex IOC1 is changed from L level to H level or from H level to L level and the remaining pins ex IOC2 to OC4 are held at L level When the signal changes at the input pins of the IOC port specified by the SCA instruction occur and stay in that state for at least two chattering clock PH6 PH8 PH10 cycles the control circuit at the input pins will deliver the halt release request signal SCF 1 At that time the chattering prevention clock will stop due to the delivery of SCF1 The SCF1 will be reset to 0 by executing the SCA instruction the chattering prevention clock will be
28. Before Rx3 Rx2 Rx1 RxO After Rx2 Rx1 RxO 0 Rx n ACn lt Rx n 1 AC n 1 Rx 0 ACO 1 The Rx content is shifted left and 1 is loaded to the LSB The results are loaded to the AC Content of Bit3 Bit2 Bit1 BitO Rx Before Rx3 Rx2 Rx1 RxO After Rx2 Rx1 RxO 1 CF lt Rx 3 Bit3 of the content of Rx is loaded to the carry flag CF CF Zero flag The content of CF is loaded to AC and Rx The content of AC and the meaning of the bit after execution of this instruction are as follows Bit 3 CF Bit 2 Zero AC 0 flag Bit 1 No Use Bit 0 No Use 115 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual 5 3 OPERATION INSTRUCTIONS INC Rx Function Description INC HL Function Description INC HL Function Description DEC Rx Function Description DEC HL Function Description DEC Function Description Rx AC lt Rx 1 Adds 1 to the content of Rx the result is loaded to the data memory Rx and AC The carry flag CF will be affected HL AC R HL 1 Adds 1 to the content of HL the result is loaded to the data memory HL and AC the carry flag CF will be affected HL indicates an index address of data memory HL AC lt R HL 1 HL HL 1 Adds 1 to the content of HL the result is loaded to the data mem
29. HL AC and CF the result is loaded to AC The carry flag CF will be affected HL indicates an index address of data memory lt HL AC CF HL HL 1 Binary adds the contents of HL AC and CF the result is loaded to AC The content of the index register HL will be incremented automatically after executing this instruction The carry flag CF will be affected HL indicates an index address of data memory AC Rx Rx AC CF Binary adds the contents of Rx AC and CF the result is loaded to AC and the data memory Rx The carry flag CF will be affected AC HL lt HL AC CF Binary adds the contents of HL AC and CF the result is loaded to AC and the data memory HL The carry flag CF will be affected HL indicates an index address of data memory AC HL HL AC CF HL HL 1 Binary adds the contents of HL AC and CF the result is loaded to AC and the data memory QHL The content of the index register HL will be incremented automatically after executing this instruction The carry flag CF will be affected HL indicates an index address of data memory AC Rx AC B CF Binary subtracts the contents of AC and CF are from the content of Rx the result is loaded to AC The carry flag CF will be affected 117 tenx technology inc Rev 1 1 2007 06 28 Advance Information SBC Function Description SBC HL Function
30. MASK OPTION table Mask Option name Selected item SEG24 IOA1 CX 3 CX SEG25 IOA2 RR 3 RR 5 26 3 RT SEG27 IOA4 RH 3 RH 3 8 1 RC Oscillation Network The RFC circuitry may build up 3 RC oscillation networks through RR RT or RH and CX pins with external resistors Only one RC oscillation network may be active at a time When the oscillation network is built up executing SRF 1h SRF 2h and SRF 4h instructions to enable RR RT and RH networks respectively the clock will be generated by the oscillation network and transferred to the 16 bit counter through the CX pin It will then enable or disable the 16 bit counter in order to count the oscillation clock To build up the RC oscillation network 1 Connect the resistor and capacitor on the RR RT RH and CX pins Fig 2 24 illustrates the connection of these networks 2 Execute SRF 1h SRF 2h or SRF 4h instructions to activate the output pins for the RC networks respectively The RR RT RH pins will become a tri state type when these networks are disabled 3 Execute SRF 8 SRF 18h or SRF 28h instructions to enable the RC oscillation network and 16 bit counter The RC oscillation network will not operate if these instructions have not been executed and the RR RT and RH pins output a 0 state at this time To get a better oscillation clock from the CX pin activate the output pin for each RC network before the counter is enabled When the overflow fl
31. R HL AND AC HL 0010 1011 1100 0000 AC RGHL R HL AND AC HL lt HL 1 EOR Rx 0010 1100 xxxx Rx EOR AC EOR HL 0010 1100 1000 0000 lt RQHL EOR AC EOR HL 0010 1100 1100 0000 R HL EOR amp HL lt HL 1 EOR Rx 0010 1101 XXXX Rx EOR AC EOR HL 0010 1101 1000 0000 AC R HL R HL EOR EOR 0010 1101 1100 0000 AC RGHL R HL EOR HL lt HL 1 OR Rx 0010 10 OXXX XXXX AC lt Rx OR OR HL 0010 1110 1000 0000 AC R HL OR AC OR HL 0010 1110 1100 0000 RGHL OR AC amp HL lt HL 1 OR Rx 0010 1111 xxxx Rx OR AC OR HL 0010 1111 1000 0000 AC RGHL R HL OR AC OR HL 0010 1111 1100 0000 AC RGHL R HL OR AC HL lt HL 1 ADCI RyD 00 0000 DDDD YYYY AC Ry D CF CF ADCI RyD 00 0001 DDDD YYYY AC Ry Ry D CF CF SBCI RyD 0011 0010 DDDD YYYY AC Ry D B CF CF SBCI RyD 00 00 DDDD YYYY lt Ry D B CF CF ADDI Ry D 00 0100 DDDD AC lt 0 ADDI RyD 00 0101 DDDD YYYY AC Ry lt Ry D CF SUBI RyD 00 0110 DDDD YYYY AC lt Ry D B I CF SUBI Ry D 00 01 DDDD YYYY AC Ry lt Ry 8 CF ADNI Ry D 00 1000 DDDD YYYY AC Ry ADNI RyD 00 1001 DDDD YYYY AC Ry lt Ry ANDI Ry D 00 1010 DDDD
32. Rx lt R HL Description The content of the data memory specified by HL is loaded to AC and the data memory specified by Rx MWR Rx HL Function AC Rx lt R HL HL HL 1 Description The content of the data memory specified by HL is loaded to AC and the data memory specified by Rx The content of the index register HL will be incremented automatically after executing this instruction SRO Rx Function Rx n ACn lt Rx n 1 AC n 1 Rx 3 lt 0 Description The Rx content is shifted right and 0 is loaded to the MSB The result is loaded to the AC Content of Bit2 Bit1 BitO Rx Before Rx3 Rx2 Rx1 RxO After 0 Rx3 Rx2 Rx1 114 tenx technology inc Rev 1 1 2007 06 28 Advance Information SR1 Rx Function Description SLO Rx Function Description SL1 Rx Function Description MRA Rx Function Description MAF Rx Function Description TM8726 User s Manual Rx n ACn lt Rx n 1 AC n 1 Rx 3 lt 1 The Rx content is shifted right and 1 is loaded to the MSB The result is loaded to the AC Content of Bit3 Bit2 Bit1 BitO Rx Before Rx3 Rx2 Rx1 RxO After 1 Rx3 Rx2 Rx1 Rx n ACn lt Rx n 1 ACn 1 Rx 0 ACO 0 The Rx content is shifted left and 0 is loaded to the LSB The results are loaded to the AC Content of Bit3 Bit2 Bit1 BitO Rx
33. Stop release enable flag SRF7 SRFA SRF3 SRF5 52 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual 2 15 CONTROL REGISTER CTL The control register CTL comes in 4 types control register 1 CTL1 to control register 4 CTLA 2 15 1 CONTROL REGISTER 1 CTL1 The control register 1 CTL 1 being a 1 bit register 1 Switch enable flag 4 SEF4 Stores the status of the input signal change at pins of IOC set in input mode that causes the halt mode or stop mode to be released 2 Switch enable flag 3 SEF3 Stores the status of the input signal change at pins of IOD set in input mode that causes the halt mode or stop mode to be released Executed the SCA instruction may set or reset these flags The following table shows Bit Pattern of Control Register 1 CTL1 Bit 4 Bit3 Switch enable flag 4 Switch enable flag 3 SEF4 SEF3 Enables the halt release Enables the halt release caused by the signal caused by the signal change on IOC port change on IOD port The following figure shows the organization of control register 1 CTL1 Ed HALT ge Released detector R SEF4 equest SCA 10h Interrupt 0 request Edge IOD detector SEF3 PLC 1 SCF3 SCA 8h Interrupt accept 2 15 1 1 The Settings for Halt Mode If the SEF4 SEF3 is set to 1 the signal changed on the IOC IOD port will cause the halt mode to be released and SCF1 SCF3 will be set to 1 Becau
34. System clock for instruction Address of data RAM specified by HL IEFn Interrupt Enable Flag Back up Flag HRFn HALT Release Flag Generic Index address register HEFn HALT Release Enable Flag Content of generic Index address register Lz Address of LCD PLA Latch Content of lowest nibble Index register SRFn STOP Release Enable Flag Content of middle nibble Index register SCFn Start Condition Flag Content of highest nibble Index register Cch Clock Source of Chattering prevention ckt Address of Table ROM Cfq Clock Source of Frequency Generator H TQHL High Nibble content of Table ROM SEFn Switch Enable Flag L T HL Low Nibble content of Table ROM FREQ Frequency Generator setting Value TMR Timer Overflow Release Flag CSF Clock Source Flag Ctm Clock Source of Timer Program Page PDV Pre Divider RFOVF RFC Overflow Flag STACK Content of stack RFC Resistor to Frequency counter TM1 Timer 1 RFC n Bit data of Resistor to Frequency counter TM2 Timer 2 148 tenx technology inc Rev 1 1 2007 06 28
35. When the backup flag is set the oscillator circuit uses a larger driving force to operate and the oscillation conditions are improved but the operating current is also increased Therefore the backup flag should be reset unless otherwise required For information on the backup flag refer to 3 5 2 1 2 Li BATTERY POWER SUPPLY Operating voltage range 2 4V 3 6V The connection diagrams for different LCD bias applications are shown below 2 1 2 1 NO BIAS AT Li BATTERY POWER SUPPLY Application circuit ES J O 6 m H z Z Z LH LH 8 8B 0 E Bp 0 B BS a oO 0 5 8726 MASK OPTION table Mask Option name Selected item POWER SOURCE 2 3V BATTERY OR HIGHER BIAS 1 NO BIAS Note 1 The input output ports operate between GND and VDD2 15 tenx technology inc Rev 1 1 2007 06 28 Advance Information 2 1 2 2 1 2 BIAS AT Li BATTERY POWER SUPPLY The backup flag BCF must be reset after the operation of the halver circuit is fully stabilized and a voltage of approximately 1 2 VDD2 appears on the VDD1 pin Backup flag BCF BCF 0 TM8726 User s Manual BCF 1 CUPO N C CUP1 CUP2 VDD4 VDD3 VDD2 SW2 VDD1 Swi BAK Internal logic I
36. amp data memory address 10H R10 AC CF 0 DAA 10h Converts the content of AC to decimal format 38 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual The result in the data memory address 10H is O0 in the CF is 1 This represents the decimal number 10 Instructions DAS DAS DAS HL can convert the data from hexadecimal format to decimal format after any subtraction operation The conversion rules are shown in the following table and illustrated in Example 2 AC data before DAS CF data before DAS AC data after DAS CF data after DAS EN IV execution execution execution lt lt 9 CF 1 6 lt AC lt F AC ACHA Example 2 LDS 10h 1 Loads immediate data 1 to the data memory address 10H LDS 11h 2 Loads immediate data 2 to the data memory address 11H and AC SF 1h Sets CF to 1 which means no borrowing has occurred SUB 10h Content of data memory address 10H is binary subtracted the result loads to data memory address 10H Rio AC Fu CF 0 DAS 10h Converts the content of the data memory address 10H to decimal format The result in the data memory address 10H is 9 and in the CF is 0 This represents the decimal number 1 2 12 TIMER 1 TMR1 Re load RL1 M 5 TMS instruction IEF1 Initial reset 6 bit binary down PH5 Interrupt counter Pd SCF5 PH13
37. is set interrupt 1 4 is accepted and the instruction at address 18H 20H is executed automatically 2 Pre divider interrupt request An interrupt request signal HRF3 is delivered when the pre divider overflows In this case if the interrupt enable flag3 IEF3 is set interrupt 3 is accepted and the instruction at address 1CH is executed automatically 3 16 bit counter of RFC CX pin control mode interrupt request An interrupt request signal HRF6 is delivered when the 2nd falling edge applied on the CX pin and the 16 bit counter stops operating In this case if the interrupt enable flag6 IEF6 is set interrupt 6 is accepted and the instruction at address 28H is executed automatically 3 1 2 INTERRUPT PRIORITY If all interrupts are requested simultaneously during a state when all interrupts are enabled the pre divider interrupt is given the first priority and other interrupts are put on hold When the interrupt service routine is initiated all of the interrupt enable flags IEFO IEF6 are cleared and should be set on the next execution of the SIE instruction Refer to Table 3 1 64 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual Example Assume all interrupts are requested simultaneously when all interrupts are enabled and all of the the pins of IOC have been set to input mode Clear all of the HRF flags SCA 10h enable the interrupt request of IOC SIE 7Fh e
38. the reset signal is delivered MASK OPTION table IOC or pins are used as key reset Mask Option name Selected item IOC1 KI1 FOR KEY RESET 1 USE 2 2 FOR KEY RESET 1 USE FOR KEY RESET 1 USE IOCA KI4 FOR KEY RESET 1 USE IOC or pins aren t used as key reset Mask Option name Selected item IOC1 KI1 FOR KEY RESET 2 NO USE 2 2 FOR KEY RESET 2 NO USE IOC3 KI3 FOR KEY RESET 2 NO USE IOCA KI4 FOR KEY RESET 2 NO USE Doo IOC1 K11 5 ADD Key Scanning latch circuit W VDD Key Scanning latch circuit _ e reset 1 lOC3KI3 WW VDD lt Key Scanning latch circuit X CEP ipie eee VDD Key Scanning latch circuit 69 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual 3 2 4 WATCHDOG RESET The timer is used to detect unexpected execution sequences caused by software run away The watchdog timer consists of a 9 bit binary counter The timer input PH10 is the 10th stage output of the pre divider When the watchdog timer overflows it generates a reset signal to reset TM8726 Most of the functions in TM8726 will be initiated except for the watchdog timer which is still active The WDF flag will not be affected and PHO PH10 of the
39. 011 XXXX XXXX 8 7 6 111 Ctm PH13 Setting of Timer 2 8 7 6 110 Ctm PH11 8 7 6 101 Ctm PH7 X8 7 6 100 Ctm PH5 144 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual Instruction Machine Code Function Flag Remark 8 7 6 011 Ctm FREQ X8 7 6 010 Ctm PH15 X8 7 6 001 Ctm PH3 X8 7 6 000 Ctm PH9 5 0 Set Timer2 Value SHE X 1110 1000 OXXX 0 X6 Enable HEF6 RFC 5 Enable HEF5 KEY S X4 Enable HEF4 TMR2 X3 Enable HEF3 PDV X2 Enable HEF2 INT 1 Enable TMR1 SIE X 1110 1001 OXXX XXXX X6 Enable IEF6 RFC 5 Enable IEF5 KEY S X4 Enable IEF4 TMR2 Enable PDV x2 Enable IEF2 INT X1 Enable IEF1 TMR1 X0 Enable IEFO C DPT PLC X 1110 101X OXXX XXXX X8 Reset PH15 11 X6 0 Reset HRF6 0 SRF X 1110 1100 00XX XXXX x5 Enable Cx Control X4 Enable TM2 Control X3 Enable Counter ENX x2 Enable RH Output EHM x1 Enable RT Output ETP X0 Enable RR Output ERR SRE X 0 1101 XOXX X000 Enable SRF7 SRF7 KEY S x5 Enable SRF5 SRF5 INT X4 Enable SRF4 SRF4 C Port x3 Enable SRF3 SRF3 D port FAST 0 1110 0000 0000 Switch to High Speed Clock SLOW 0 1110 1000 0000 Switch to Low Speed Clock CPHL X 0 1111 XXXX Skip next instruction when X7 0 HL 7 0 SPKX x 1 0010 X6 1 KEY_S release by scanning cycle X6 0 KEY_S release by normal key sca
40. 2 Relative Instructions 1 LCT Lz Ry Decodes the content specified in Ry with the data decoder and transfers the DBUSA H to the LCD latch specified by Lz 2 LCB Lz Ry Decodes the content specified Ry with the data decoder and transfers the DBUSA H to the LCD latch specified by Lz DBUSA to DBUSH are all set to 0 when the input data of the data decoder is O 3 LCD Lz HL Transfers the table ROM data specified by HL directly to DBUSA through DBUSH without passing through the data decoder The mapping table is shown in table 2 32 4 LCP Lz Ry The data the RAM and accumulator are transferred directly to DBUSA through DBUSH without passing through the data decoder The mapping table is shown below 103 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual 5 LCT Lz HL Decodes the index RAM data specified in HL with the data decoder and transfers DBUSA H to the LCD latch specified by Lz 6 LCB Lz HL Decodes the index RAM data specified in HL with the data decoder and transfers the DBUSA H to the LCD latch specified by Lz The DBUSA to DBUSH are all set to 0 when the input data of the data decoder is 0 7 LCP Lz HL The data of the index RAM and accumulator are transferred directly to DBUSA through DBUSH without passing through the data decoder The mapping table is shown below Table 2 4 The mapping table of LCP and LCD
41. 28 Advance Information TM8726 User s Manual IPC Rx Function Description SPD X Function Description Rx AC lt I OC The data of the I OC port is loaded to AC and data memory Rx Defines the input output mode of each pin for IOD port and enables or disables the pull low device Sets the I O mode and turns the pull low device on or off The meaning of each bit of X X4 X3 X2 X1 X0 is shown below Bit pattern Setting Bit Setting OPD Rx Function Description IPD Rx Function Description SPKX X Function Description Enable the pull low Disable the pull low device on IOD1 1OD4 device on simultaneously IOD1 IOD4 simultaneously OD lt Rx The content of Rx is outputted to I OD port Rx AC lt I OD The data of the I OD port is loaded to AC and data memory Rx Sets the Key matrix scanning output state When SEG1 16 is are used for LCD driver pin s set X X7 0 to specify the key matrix scanning output state for each SEGn pin in the scanning interval Xs 0 when HEF5 is set to 1 the HALT released request HRF5 will be set to 1 after the key is depressed on the key matrix and then SCF7 will be set to 1 14 when HEF5 is set to 1 the HALT released request HRF5 will be set to 1 after each scanning cycle regardless of key depression and then SCF7 will be set to 1 X7X5X4 000 in this setting each scanning cycle only checks one specifi
42. A signal change in the INT pin 3 The stop release condition specified by the SRE instruction is met The data specified by X causes the halt mode to be released The signal change at port IOC IOD is specified The bit meaning of X X4 X3 is shown below Bit pattern Releases halt mode when signal is applied to IOC Releases halt mode when signal is applied to IOD X2 0 don t care Set Reset interrupt enable flag 128 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual The IEFO is set so that interrupt O Signal change at port IOC or IOD specified by SCA is accepted The IEF1 is set so that interrupt 1 underflow from timer 1 is accepted The IEF2 is set so that interrupt 2 the signal change at the INT pin is accepted The IEF3 is set so that interrupt 3 overflow from the predivider is accepted The IEF4 is set so that interrupt 4 underflow from timer 2 is accepted The IEF5 is set so that interrupt 5 key scanning is accepted SHE X Function Set Reset halt release enable flag Description X121 The HEF1 is set so that the halt mode is released by TMR1 underflow X2 1 The HEF2 is set so that the halt mode is released by signal changed on INT pin 3 1 HEF3 is set so that the halt mode is released by predivider overflow X4 1 The HEF4 is set so that the halt mode is released by TMR2 underflow X5 1 The is set so that the halt mode is released by the si
43. AC 0 If the content of AC is not 0 a jump occurs If 0 the PC increases by 1 The range of X is only 2K for one page Program counter jumps to X in current page if CF 0 If the content of CF is 0 a jump occurs If 1 the PC increases by 1 The range of X is only 2K for one page Program counter jumps to X in current page if AC 0 If the content of AC is 0 a jump occurs If 1 the PC increases by 1 The range of X is only 2K for one page Program counter jumps to X in current page if CF 1 If the content of CF is 1 a jump occurs If O the PC increases by 1 The range of X is only 2K for one page Program counter jumps to X in all pages Unconditional jump The range of X is for all pages STACK lt 1 Program counter jumps to X in all pages A subroutine is called The range of X is for all pages 134 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual RTS Function PC lt STACK Description A return from a subroutine occurs 5 9 MISCELLANEOUS INSTRUCTIONS SCC X Function Sets the clock source for IOD and IOC chattering prevention PWM output and frequency generator Description The following table shows the meaning of each bit for this instruction Bit pattern Clock source setting Bit pattern Clock source setting X671 The clock source of 6 0 The clock source of frequency generator frequency generator comes comes from the system fro
44. After the reset cycle the IOB port is set as input and each bit of port can be defined as input or output individually by executing SPB instructions Executing OPB instructions may output the contents of specified data memory to the pins set to output mode the other pins which are set to input will still be input If IPB instructions are executed they may store the signals applied on IOB pins into specified data memory locations When the IOB pins are set as the output executing the IPB instruction will save the data stored in the output latch into the specified data memory location Before executing the SPB instruction to set the pins to output the OPB instruction must be executed to output the data to the output latches This will prevent the chattering signal on the I O pin when the mode changes IOB port has a built in pull down resistor The pull low device for each pin is selected by mask option and executing the SPB instruction to enable disable the device 79 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual Pull low function option Mask Option name Selected item IOB PULL LOW RESISTOR 1 USE IOB PULL LOW RESISTOR 2 NO USE 3 5 3 IOC PORT IOC1 pins are MUXed with KI1 SEG32 2 SEG33 SEG34 and 4 SEG35 pins respectively by mask option MASK OPTION table Mask Option name Selected item SEG32 IO
45. CPHL X will be skipped if not equivalent the instruction behind CPHL X will be executed normally 34 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual Note During the comparison of the index address all the interrupt enable flags IEF have to be cleared to avoid malfunction The comparison bit pattern is shown below CPHL X XT X6 X5 X4 X3 X2 X1 XO HL IDBF7 IDBF6 IDBF5 IDBF4 IDBF3 IDBF2 IDBF1 IDBFO Example HL 30h CPHL 30h SIE Oh disable IEF JMP lable1 this instruction will be force as NOP JMP lable2 this instruction will be executed and than jump to lable2 lable1 lable2 2 6 STACK REGISTER STACK Stack is a specially designed register following the first in last out rule It is used to save the contents of the program counter sequentially during subroutine calls or execution of interrupt service routines The contents of the stack register are returned sequentially to the program counter PC when return instructions RTS are executed The stack register is organized by using 11 bits by 8 levels but with no overflow flag hence only 8 levels of subroutine calls or interrupts are allowed If the stacks are full and either an interrupt occurs or a subroutine call executes the first level will be overwritten Once the subroutine call or interrupt causes a stack register STACK overflow t
46. HL 1111 0001 0000 0000 T HL 6 1 KEY_S release by scanning cycle T HL 6 0 KEY_S release by normal key scanning T HL 7 5 4 Set one of KO1 16 1 by 000 T HL 3 0 T HL 7 5 4 Set all 1 001 T HL 7 5 4 Set all Hi z 010 T HL 7 5 4 Set eight of KO1 16 1 by 10X T HL 3 T HL 3 0 gt KO1 8 T HL 3 1 gt KO9 16 T HL 7 5 4 Set four of KO1 16 1 by 110 T HL 3 2 T HL 3 2 00 gt KO1 4 T HL 3 2 01 gt KO5 8 T HL 3 2 10 gt KO9 12 T HL 3 2 11 gt KO13 16 T HL 7 5 4 Set two of KO1 16 1 by 111 T HL 3 2 1 T HL 3 1 000 gt KO1 2 T HL 3 1 001 gt KO3 4 T HL 3 1 010 gt KO5 6 T HL 3 1 011 gt KO7 8 T HL 3 1 100 gt KO9 10 T HL 3 1 101 gt KO11 12 T HL 3 1 110 gt KO13 14 T HL 3 1 111 gt KO15 16 RTS 1111 0100 0000 0000 PC lt STACK CALL Return SCC X 1111 0100 1X0X XXXX X6 1 Cfq BCLK X6 0 PHO 4 1 Set IOC Cch X3 1 Set IOD Cch 2 1 0 001 Cch PH10 2 1 0 010 Cch PH8 2 1 0 100 Cch PH6 5 X 01 000 X000 X4 Enable SEF4 C1 4 x3 Enable SEF3 D1 4 SPA X 01 100X XXXX X4 Enable IOA4 1 Pull Low X3 0 Set IOA4 1 I O mode SPB X 01 101X XXXX X4 Enable 4 1 Pull Low X3 0 Set 4 11 mode SPC X 01 110X XXXX X4 Enable 4 1 Pull Low Low Level Hold X3 0 Set IOC4 1 I O mode SPD 01 111X XXXX X4 Enable IOD4 1 Pull Low X3 0 Set IOD4 1 I O mode SF X 10 X00X XXXX Enable TM1 Reload function RL1 X4 Enable watchdog timer WDF
47. SCF3 SCF2 SCF 1 Halt release Halt release caused Halt release The backup caused by the by SCF4 5 6 7 8 9 caused by the mode status in IOD port port TM8702 MSC Rx Function Rx lt SCF4 SCF5 SCF7 PH15 Description The SCF4 to SCF7 contents are loaded to AC and the data memory specified by Rx The content of AC and the meaning of the bit after the execution of this instruction are as follows Bit 3 Bit 2 Bit 1 Bit 0 Start condition flag The content of 15th Start condition flag Start condition flag 7 stage of the 5 4 SCF7 predivider SCF5 SCF4 Halt release Halt release Halt release caused by caused by 1 caused by INT pin predivider overflow underflow MCX Rx Function AC Rx lt SCF8 SCF6 SCF9 Description The SCF8 SCF6 SCF9 contents are loaded to AC and the data memory specified by Rx The content of AC and the meaning of the bit after the execution of this instruction are as follows Bit 3 Bit 2 Bit 1 Bit 0 Start condition NA Start condition Start condition flag 9 flag 6 flag 8 SCF9 SCF6 SCF8 NA Halt release Halt release Halt release caused by RFC caused by TM2 caused by the counter overflow underflow signal change to L applied on 1 4 in scanning interval 130 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual MSD Rx Function Rx AC lt WDF CSF RFOVF Description The watchdog flag system clock status and overflow flag of RFC c
48. Selected item SEG30 IOB3 BZB 3 BZB SEG31 IOB4 BZ 3 BZ 73 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual 05 ALM X X5 DCD This figure shows the organization of the buzzer output 3 4 1 BASIC BUZZER OUTPUT The buzzer output BZ BZB is suitable for driving a transistor for the buzzer with one output pin or driving a buzzer with BZ and BZB pins directly It is capable of delivering a modulation output in any combination of one signal of FREQ PH3 1024Hz PH4 2048Hz PH5 1024Hz and multiple signals of PH10 32Hz PH11 16Hz PH12 8Hz PH13 4Hz PH14 2Hz PH15 1Hz The ALM instruction is used to specify the combination The higher frequency clock is the carrier of modulation output and the lower frequency clock is the envelope of the modulation output Note 1 The high frequency clock source should only be one of PH3 PH4 PH5 or FREQ and the lower frequency may be any all of the combinations from PH10 PH15 2 The frequency in parentheses corresponding to the input clock of the pre divider PHO is 32768Hz 3 The BZ and BZB pins will output DCO after the initial reset Example Buzzer output generates a waveform with the 1KHz carrier and PH15 PH14 envelope LDS 20h ALM 70h Output the waveform 74 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual In this example the BZ and BZB pins will gene
49. TM8726 User s Manual 0 31 98 165 495 164 814 0 41 0 64 A3 69 234 057 233 082 0 42 A5 17 910 222 932 328 2 37 0 53 Note 1 Above variation does not include X tal variation 2 If PHO 65536Hz C3 B5 may have more accurate frequency During the application for melody output sound effect output or carrier output for remote controls the frequency generator needs to combine with the alarm function BZB BZ For detailed information about this application refer to section 3 4 3 3 3 Halver Doubler Tripler The halver doubler tripler circuits are used to generate the bias voltage for LCD and are composed of a combination of PH2 PH3 PH4 PH5 When the Li battery application is used the 1 2 VDD voltage generated by the halver operation is supplied to the circuits which are not related to input output operation 3 3 4 Alternating Frequency for LCD The alternating frequency for LCDs is a frequency used to make the LCD waveform 3 4 BUZZER OUTPUT PINS There are two output pins BZB and BZ Each are MUXed with IOB3 and 4 by mask option respectively BZB and BZ pins are versatile output pins with complementary output polarity When the buzzer output function is combined with the clock source from the frequency generator this output function may generate melodies sound effects or carrier outputs for remote controls MASK OPTION table Mask Option name
50. X3 HALT after EL driver enable 146 tenx technology inc Rev 1 1 2007 06 28 Advance Information Machine Code Instruction TM8726 User s Manual Function Flag Remark Enable EL panel driver Set BCF flag Set CF 1111 0111 00 OXXX Disable TM1 Reload function Disable watchdog timer Disable EL panel driver Reset BCF Reset CF 1111 10XX XXXX XXXX BCLKX PHO BCLK 8 BCLK 4 BCLK 2 BCLK 2 3 3 4 1 1 1 2 1 3 1 4 PH5 PH6 PH8 1 1 1 2 1 3 1 4 1111 110 FREQ DC 1 PH3 PHA PH5 DC 0 PH15 10 Enable INT strong Pull low dev Turn off all Segments Set DED flag Enable TM2 Reload function Disable INT powerful Pull low Release Segments Reset DED flag Disable TM2 Reload function Stop Operation 147 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual Symbol Description Content of Register Immediate Data Accumulator DE Complement of Immediate Data Content of Accumulator bit n PC Program Counter Complement of content of Accumulator CF Carry Flag Address of program or control data ZERO Zero Flag Address X of data RAM WDF Watch Dog Timer Enable Flag Bit n content of Rx 7SEG 7 segment decoder for LCD Address Y of working register BCLK
51. at the interrupt service address is executed automatically Refer to Table 3 1 In this case the CPU performs the following services automatically 1 The return address of the interrupt service routine and the addresses of the program counter PC installed before interrupt servicing began are saved in the stack register STACK 2 The corresponding interrupt service routine address is loaded in the program counter PC The interrupt request flag corresponding to the interrupt accepted is reset and the interrupt enable flags are all reset When the interrupt occurs the TM8726 will follow the procedure below Instruction 1 In this instruction interrupts are accepted NOP TM8726 stores the program counter data into the STACK At this time no instructions will be executed as with NOP instructions Instruction A The program jumps to the interrupt service routine Instruction B Instruction C RTS Finishes the interrupt service routine Instruction 1 re executes the instruction which was interrupted Instruction 2 Note If instruction 1 is halt instruction the CPU will return to halt after interrupt When an interrupt is accepted all interrupt enable flags are reset to 0 and the corresponding HRF flag will be cleared the interrupt enable flags IEF must be set again in the interrupt service routine as required 3 2 RESET FUNCTION TM8726 contains four reset sources power on reset RESET pin reset IOC po
52. caused by the key matrix MCX 10h Checks SCF8 SKI JBO ski release ski release IPC 10h reads the 1 4 input latch state JBO ki1 release JB1 ki2 release 95 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual JB2 ki3 release JB3 ki4 release ki1 release SPKX 40h Checks the key depressed K1 column PLC 20h Clears HRF5 to avoid the false HALT release CALL wait scan again Waits for the next key matrix scanning cycle The waiting period must be longer than the key matrix scanning cycle IPC 10h Reads the 1 input latch state JBO ki1_seg1 SPK 4fh Enables only the SEG16 scanning output PLC 20h Clear HRF5 to avoid the false HALT released CALL wait scan again Waits for the time over the halt LCD clock cycle to ensure and scans again IPC 10h Reads the 1 input latch state JBO kil seg16 wait scan again HALT PLC 20h RTS 96 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual CHAPTER 4 LCD DRIVER OUTPUT There are 41 segment pins with 9 common pins in the LCD driver outputs TM8726 All of these output pins can also be used as DC output ports through the mask option If more than one LCD driver output pin is defined as DC output the following mask option must be selected MASK OPTION table When all of SEG and COM pins have been used to drive LCD panel Mask Option name Selected ite
53. enable flag IEFx must be set again before exiting from the interrupt routine 2 15 4 CONTROL REGISTER 4 CTL4 Control register 4 CTL4 being a 3 bit register is set reset by SRE instruction The following table shows the Bit Pattern of Control Register 4 CTL4 Stop release SRF7 SRF5 SRF4 SRF3 enable flag Enable the stop release Enable the stop release Enable the stop release Stop release request caused by signal request caused by signal request caused by signal request flag change on KI1 4 SKI change on INT pin change on IOC IOD HRF2 55 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual When the stop release enable flag 7 SRF7 is set to 1 the input signal change at the 1 4 pins causes the stop mode to be released In the same manner when SRF4 SRF3 and SRF5 are set to 1 the input signal changes at the input mode pins of the IOC IOD port The signal change on the INT pin causes the stop mode to be released as well Example This example illustrates the stop mode released by the port IOC 1 4 and INT pin Assume all of the pins in IOD and have been set to input mode PLC 25h Resest the HRFO HRF2 and HRF5 SHE 24h HEF2 and HEF5 is set so that the signal change at INT or 1 4 pin causes start condition flag 4 or 8 to be set SCA 10h SEF4 is set so that the signal changes at port IOC cause the start conditions SCF1 to be set SRE O
54. following functions Binary addition subtraction INC DEC ADC SBC ADD SUB ADN ADCI SBUI ADNI Logic operation AND EOR OR ANDI EORI ORI Shift 5 0 5 1 510 SL1 Decision JBO JB1 JB2 JB3 JC JNC JZ and JNZ BCD operation DAA DAS 2 11 HEXADECIMAL CONVERT TO DECIMAL HCD Decimal format is another number format for TM8726 When the content of the data memory has been assigned as decimal format it is necessary to convert the results to decimal format after the execution of ALU instructions When the decimal converting operation is being processed all of the operand data including the contents of the data memory RAM accumulator AC immediate data and look up table should be in the decimal format or the results of conversion will be incorrect Instructions DAA DAA can convert data from hexadecimal to decimal format after any addition operation The conversion rules are shown in the following table and illustrated in example 1 AC data before DAA CF data before DAA AC data after DAA CF data after DAA execution execution execution execution 0x AC x9 6 0 lt lt 3 AC 6 Example 1 LDS 10h 9 Loads immediate data 9 to data memory address 10H LDS 11h 1 Loads immediate data 1 to data memory address 11H and AC RF 1h Reset CF to 0 ADD 10h Contents of the data memory address 10H and AC are binary added the result loads to AC
55. instruction HL indicates an index address of data memory AC Rx lt Rx AC Exclusive Ors the contents of Rx and AC the result is loaded to AC and the data memory Rx AC HL lt 6 AC Exclusive Ors the contents of HL and AC the result is loaded to and the data memory QHL HL indicates an index address of data memory AC HL lt HL AC HL HL 1 Exclusive Ors the contents of and AC the result is loaded to and the data memory HL The content of the index register HL will be incremented automatically after executing this instruction HL indicates an index address of data memory AC lt Rx AC Binary Ors the contents of Rx and AC the result is loaded to AC AC lt HL AC Binary Ors the contents of HL and AC the result is loaded to AC HL indicates an index address of data memory 122 tenx technology inc Rev 1 1 2007 06 28 Advance Information OR Function Description OR Rx Function Description OR HL Function Description OR HL Function Description ADCI Ry D Function Description ADCI Ry D Function Description SBCI Ry D Function Description TM8726 User s Manual AC lt HL AC HL HL 1 Binary Ors the contents of HL AC the result is loaded to AC The content of the index register HL will be incremented automatically after executing this inst
56. instruction must be used to reset the halt release request flag 2 HRF2 otherwise the SHE instruction must be used to reset the halt release enable flag 2 HEF2 2 Start condition flag 5 SCF5 Start condition flag 5 SCF5 is set when an underflow signal from Timer 1 TMR1 causes the halt release request flag 1 HRF1 to be outputted and the halt release enable flag 1 HEF1 is set beforehand To reset start condition flag 5 SCF5 the PLC instruction must be used to reset the halt release request flag 1 HRF 1 otherwise the SHE instruction must be used to reset the halt release enable flag 1 1 3 Start condition flag 7 SCF7 Start condition flag 7 SCF7 is set when an overflow signal from the pre divider causes the halt release request flag 3 HRF3 to be outputted and the halt release enable flag 3 HEF3 is set beforehand To reset start condition flag 7 SCF7 the PLC instruction must be used to reset the halt release request flag 3 HRF3 otherwise the SHE instruction must be used to reset the halt release enable flag HEF3 4 Contents of the pre divider on the 15th stage The MSC instruction is used to transfer the contents of status register 3 STS3 to the accumulator AC and the data memory RAM 49 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual The following table shows the Bit Pattern of Status Register 3 STS3 Bit 3 Bit 2 Bit 1 Bit 0 Start condition 15th stag
57. key matrix The specified columns are defined by the setting of X gt and X4 X3X2X1 000 activates the K1 K2 columns simultaneously X3X2X1 001 activates the K3 K4 columns simultaneously X3X2X1 110 activates the K13 K14 columns simultaneously X3X2X1 111 activates the 15 K16 columns simultaneously Xo is not a factor Sets the Key matrix scanning output state When SEG1 16 is are used for LCD driver pin s sets the contents of AC and Rx to specify the key matrix scanning output state for each SEGn pin in the scanning interval The bit setting is the same as the SPKX instruction The bit patterns of AC and Rx corresponding to SPKX are shown below Instruction Bit7 BitG Bits Bit4 Bits Bit2 Bit1 BitO SPK Rx AC2 AC1 ACO Rx3 Rx2 Rx1 0 SPKX X XT X6 X5 X4 X3 X2 X1 X0 111 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual SPK HL Function Sets the Key matrix scanning output state Description When SEG1 16 is are used for LCD driver pin s sets the content of table ROM HL to specify the key matrix scanning output state for each SEGn pin in the scanning interval The bit setting is the same as the SPKX instruction The bit pattern of the table ROM corresponding to SPKX is shown below Instruction Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 BitO SP
58. ports operate between GND VDD2 Note 2 The backup flag BCF is set in the initial clear mode When the backup flag is set the internal logic operated on VDD2 and the oscillator circuit becomes large in driver size When the backup flag is set the operating current is increased Therefore the backup flag should be reset unless otherwise required For information on the backup flag refer to 3 5 Note 3 The VDD1 level 1 2 VDD at the off state of SW1 is used as an intermediate voltage level for LCD driver 47 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual 2 1 2 4 1 4 BIAS AT Li BATTERY POWER SUPPLY The backup flag BCF must be reset after the operation of the halver circuit is fully stabilized and a voltage of approximately 1 2 VDD2 appears on the VDD1 pin Backup flag BCF BCF 0 BCF 1 CUPO CUP1 CUP2 VDD4 VDD3 VDD2 VDD1 BAK 0 1u 0 1u O tu 3 0V Internal logic 0 1u o GND It is recommanded that the option LCD reset OFF is not used in this power mode as the LCD segments cannot be turned off completely in the RESET cycle MASK OPTION table Mask Option name Selected item POWER SOURCE 2 3V BATTERY OR HIGHER BIAS 4 1 4 BIAS Note 1 The input output ports operate between GND and VD
59. pre divider will not be reset The following figure shows the organization of the watchdog timer During initial reset power on reset POR or reset pin the timer is inactive and the watchdog mask 9 bit counter PH10 HALT Edge detector WDF WDRST to reset TM8706 Reset pin POR RF 10H flag WDF is reset Instruction SF 10h will enable the watchdog timer and set the watchdog flag WDF to 1 At the same time the contents of the timer will be cleared Once the watchdog timer is enabled the timer will be paused when the program enters halt or stop mode When the 8726 wakes up from halt or stop mode the timer operates continuously It is recommended that you execute the SF 10h instruction before the program enters the halt or stop mode in order to initialize the watchdog timer Once the watchdog timer is enabled the program must execute the SF 10h instruction periodically to prevent timer overflow The overflow time interval of the watchdog timer is selected by mask option MASK OPTION table Mask Option name Selected item WATCHDOG TIMER OVERFLOW TIME INTERVAL 1 8 x PH10 WATCHDOG TIMER OVERFLOW TIME INTERVAL 2 64 x PH10 WATCHDOG TIMER OVERFLOW TIME INTERVAL 3 512 x PH10 Note timer overflow time interval is about 16 seconds when PHO 32 768KHz 70 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual 3 3 CLOCK GENERATOR 3 3 1 FREQUEN
60. reset BCF to 0 after the reset cycle automatically when the Ag and Li power mode option is used In the EXT V power mode option however BCF is set to 1 by default setting and cannot be reset to 0 BCF will be reset to 0 by default setting during normal operation Table 2 17 1 The back up flag status in different conditions Ag option EXT V option BCF 1 BCF 1 BCF 0 After reset cycle 1 1 0 SF 2 executed BCF 1 BCF 1 BCF 1 RF 2 executed BCF 0 BCF 0 BCF 0 To shorten the start up time of 32 768KHz Crystal oscillator TM8726 will set the BCF to 1 during the reset cycle and reset BCF to 0 after the reset cycle automatically when the Ag and Li power mode option is used In the EXT V power mode option however BCF is set to 1 by default setting and cannot be reset to 0 BCF will be reset to 0 by default setting during normal operation When the heavy load function is performed the current dissipation will increase Table 2 17 2 Ag power option Initial reset After reset STOP 6 2 RF2 BC 1 1 f 1 O Table 2 17 3 Li power option lniialreset After reset Stop mode SF2 RF2 1 58 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual Table 2 17 4 EXT V power option SC Initial reset After reset Stop mode SF2 RF2 BC 0 0 J f 1 1 Note When the program enters the stop mo
61. segments Segment PLA Figure 5 3 Principal Drawing of LCD Driver Section The LCD driver section consists of the following units Data decoder to decode data supplied from RAM or table ROM Latch circuit to store LCD lighting information LO to L5 decoder to decode the Lz specified data in sLCD related instructions which specifies the strobe of the latch circuit Multiplexer to select 1 2duty 1 3duty 1 4duty 1 5duty 1 6duty 1 7duty 1 8duty and 1 9duty LCD driver circuitry Segment PLA circuit connected between data decoder LO to L5 decoder and latch circuit The data decoder is used for decoding the contents of the working registers as specified in LCD related instructions They are decoded as 7 segment patterns on the LCD panel The decoding table is shown below Content of Output of data decoder data memory p O 1 110 e T i H Hel a 0 1 1 1 1 o 1 1 0 1 1 1 1 1 2 e D T T Note The DBUSF of decoded output can be selected as 0 or 1 by mask option The LCD pattern of this option is shown below 101 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual DBUSA DBUSA DBUSF DBUSB DBUSF DBUSB DBUSE DBUSC h DBUSC DBUSD DBUSH DBUSD n DBUSF 0 DBUSF 1 The following table shows the options table for displaying the digit 7 pattern MASK OPTION table Mask Option n
62. selection flag CSF to 0 Executing the FAST instruction will change the clock source BCLK of the system clock generator SCG to the fast speed oscillator CF clock and sets the system clock selection flag CSF to 1 For the operation of the system clock generator refer to 3 3 2 Watchdog timer enable flag WTEF The watchdog timer enable flag WDF indicates the operating status of the watchdog timer 3 Overflow flag of 16 bit counter of RFC RFOVF The overflow flag of 16 bit counter of RFC RFOVF is set to 1 when the overflow of the 16 bit counter of RFC occurs The flag will reset to O when this counter is initiated by executing the SRF instruction The MSD instruction can be used to transfer the contents of status register 4 STS4 to the accumulator AC and the data memory RAM The following table shows the Bit Pattern of Status Register 4 STS4 Bit 3 Bit 2 Bit 1 Bit 0 Reserved The overflow flag Watchdog timer System clock of 16 bit counter of Enable flag WDF selection flag RFC RFVOF CSF Read only Read only Read only Read only 51 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual 2 14 6 START CONDITION FLAG 11 SCF11 Start condition flag 11 SCF11 will be set to 1 in STOP mode when the following conditions are met A high level signal comes from the OR ed output of the pins defined as input mode in IOC port which causes the stop release flag of IOC port CS
63. shown below Instruction ROM memory space 2048 128 N words Table ROM memory space 256 16 N bytes N 0 16 Note The data width of table ROM is 8 bit The partition of memory space is defined by mask option as shown in the table below MASK OPTION table Mask Option name Selected item Instruction ROM Table ROM memory space memory space Words Bytes INSTRUCTION ROM lt gt TABLE ROM 1 N 0 2048 4096 INSTRUCTION ROM lt gt TABLE ROM 2 N 1 2176 3840 INSTRUCTION ROM lt gt TABLE ROM 3 2 2304 3584 INSTRUCTION ROM lt gt TABLE ROM 4 N 3 2432 3328 INSTRUCTION ROM lt gt TABLE ROM 5 4 2560 3072 INSTRUCTION ROM lt gt TABLE ROM 6 N 5 2688 2816 INSTRUCTION ROM lt gt TABLE ROM 7 N 6 2816 2560 INSTRUCTION ROM lt gt TABLE ROM 8 N 7 2944 2304 INSTRUCTION ROM lt gt TABLE ROM 9 N 8 3072 2048 INSTRUCTION ROM lt gt TABLE ROM 9 3200 1792 INSTRUCTION ROM lt gt TABLE ROM 10 3328 1536 32 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual Mask Option name Selected item Instruction ROM Table ROM memory space memory space Words Bytes INSTRUCTION ROM TABLE ROM C N 11 3456 1280 INSTRUCTION ROM TABLE ROM D 12 3584 1024 INSTRUCTION ROM TABLE ROM E 13 3712 768 INSTRUCTION ROM TABLE ROM F 14 3840 512 INSTRU
64. the halt mode SCF3 will be set Executing the SCA instruction will cause SCF3 to be reset to 0 48 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual Start condition flag 1 SCF1 When the SCA instruction specified signal change occurs at port IOC to release the halt mode SCF 1 will be set Executing the SCA instruction will cause SCF1 to be reset to 0 Start condition flag 2 SCF2 When a factor other than port IOA and IOC causes the halt mode to be released SCF2 will be set to1 In this case if one or more start condition flags in SCF4 5 6 7 9 is set to 1 SCF2 will also be set to 1 simultaneously When all of the flags in SCF4 5 6 7 9 are clear start condition flag 2 SCF2 is reset to O Note If start condition flag is set to 1 the program will not be able to enter halt mode Backup flag BCF This flag can be set reset by executing the SF 2h RF 2h instruction 2 14 3 STATUS REGISTER 3 STS3 When the halt mode is released by the start condition flag 2 SCF2 status register 3 STS3 will store the status of the factor in the release of the halt mode Status register 3 STS3 consists of 4 flags 1 Start condition flag 4 SCF4 Start condition flag 4 SCF4 is set to 1 when the signal change at the INT pin causes the halt release request flag 2 HRF2 to be outputted and the halt release enable flag 2 HEF2 is set beforehand To reset start condition flag 4 SCF4 the PLC
65. timer circuit tribler circuit To sound circuit This figure shows the Pre divider and its Peripherals 28 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual The PH14 delivers the halt mode release request signal setting the halt mode release request flag HRF3 In this case if the pre divider interrupt enable mode IEF3 is provided the interrupt is accepted and if the halt release enable mode HEF3 is provided the halt release request signal is delivered setting the start condition flag 7 SCF7 in status register 3 STS3 The clock source of the pre divider is PHO 4 kinds of frequencies of PHO can be selected by mask option MASK OPTION table Mask Option name Selected item PHO BCLK FOR FAST ONLY 1 PHO BCLK PHO lt gt BCLK FOR FAST ONLY 2 PHO BCLK 4 1 2 PHO lt gt BCLK FOR FAST ONLY 3 PHO BCLK 8 PHO lt gt BCLK FOR FAST ONLY 4 PHO BCLK 16 29 tenx technology inc Rev 1 1 2007 06 28 Advance Information 2 2 5 System Clock Generator TM8726 User s Manual For the system clock the clock switch circuit permits different clock inputs from XTOSC and CFOSC to be selected The FAST and SLOW instructions can switch the clock input of the system clock generator SGC The basic system clock is shown below SCLK T1
66. 0 OXXX AC Rx RFC 3 0 MRF2 Rx 0110 0101 OXXX XXXX Rx RFC 7 4 143 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual Instruction Machine Code Function Flag Remark MRF3 Rx 0110 0110 OXXX XXXX AC Rx lt RFC 11 8 MRF4 Rx 0110 0111 OXXX AC Rx lt RFC 15 12 STA Rx 0110 1000 OXXX Rx lt AC STA HL 0110 1000 1000 0000 HL lt STA HL 0110 1000 1100 0000 HL lt amp HL lt HL 1 LDA Rx 0110 00 OXXX XXXX AC lt Rx LDA HL 0100 00 1000 0000 AC lt R HL LDA HL 0100 00 1100 0000 AC lt R HL HL lt HL 1 MRA Rx 0110 01 OXXX XXXX CF lt Rx 3 MRW HL Rx 0110 10 OXXX AC R HL lt Rx MRW HL Rx 0110 10 1XXX XXXX AC R HL lt Rx HL lt HL 1 MWR Rx HL 0110 11 0 AC Rx lt R HL MWR Rx HL 0110 11 1XXX XXXX AC Rx lt R HL HL lt HL 1 MRW Ry Rx 0 OYYY YXXX XXXX lt Rx MWR 0 YYY YXXX XXXX lt JBO X 000 OXXX XXXX XXXX PC lt X 000h 7FFh 800h FFFh if AC O 7 1 JB1 X 000 1 XXXX XXXX PC lt X 000h 7FFh 800h FFFh 1 1 JB2 X 001 OXXX XXXX XXXX PC lt X 000h 7FFh 800h FFFh if AC 2 1 JB3 X 001 1 XXXX XXXX PC lt X 000h 7FFh 800h FFFh J
67. 06 28 Advance Information TM8726 User s Manual IPA Rx Function Rx AC lt I OA Description The data of I OA port is loaded to AC and the data memory Rx SPB X Function Defines the input output mode of each pin for IOB port and enables or disables the pull low device Description Sets the I O mode and turns the pull low device on or off The meaning of each bit of X X4 X3 X2 X1 X0 is shown below Bit pattern Setting Bit pattern Setting 4 1 Enable the pull low device 4 0 Disable the pull low on IOB1 IOB4 device on simultaneously 1 4 simultaneously IOB4 as input mode IOB3 as input mode 2 as input mode OB1 as input mode OPB Rx Function lt Rx Description The contents of Rx are outputted to port IPB Rx Function Rx AC lt I OB Description The data of I OB port is loaded to AC and data memory Rx SPC X Function Defines the input output mode of each pin for IOC port and enables or disables the pull low device or low level hold device Description The meaning of each bit of X X4 X3 X2 X1 X0 is shown below Bit pattern Setting Bit pattern Setting Enables all of the pull low and Disables all of the pull 4 1 disables the low level hold X4 0 low and enables the low devices level hold devices OPC Rx Function lt Rx Description The content of Rx is outputted to I OC port 109 tenx technology inc Rev 1 1 2007 06
68. 1 2 Duty 0 11 1 1 Duty FRQ D HL 0001 01DD 0000 0000 FREQ lt T HL FRQX D X 0001 10DD XXXX XXXX FREQ X MVL Rx 0001 1100 OXXX XXXX L 0 3 lt Rx MVH Rx 0001 1101 OXXX H 4 7 lt Rx MVU Rx 0001 1110 OXXX XXXX U 8 11 lt Rx ADC Rx 0010 0000 OXXX XXXX AC lt Rx AC CF CF ADC HL 0010 0000 1000 0000 AC R HL AC CF CF ADC HL 0010 0000 1100 0000 AC lt R HL AC CF CF HL lt HL 1 ADC Rx 0010 0001 OXXX XXXX AC Rx Rx AC CF CF ADC HL 0010 0001 1000 0000 R HL lt R HL AC CF CF ADC HL 0010 0001 1100 0000 R HL lt R HL AC CF CF HL lt HL 1 SBC Rx 0010 0010 OXXX lt AC B CF CF SBC HL 0010 0010 1000 0000 AC lt R HL AC B CF CF SBC HL 0010 0010 1100 0000 AC lt R HL AC B CF CF HL lt HL 1 SBC Rx 0010 0011 OXXX Rx lt AC B CF CF SBC HL 0010 0011 1000 0000 R HL lt R HL AC B CF CF SBC HL 0010 0011 1100 0000 AC R HL lt R HL AC B CF CF HL lt HL 1 141 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual Instruction Machine Code Function Flag Remark ADD Rx 0010 0100 OXXX XXXX AC
69. 3 0V 400KHz 500KHz 600KHz 25 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual 2 2 3 COMBINATION OF THE CLOCK SOURCES There are three combinations of clock sources that can be selected by mask option 2 2 3 1 Dual Clock MASK OPTION table Mask Option name Selected item CLOCK SOURCE 3 DUAL The operation of the dual clock option is shown in the following figure When this option is selected by mask option the clock source BCLK of system clock generator will switch between the XT clock and the CF clock according to the user s program When the halt and stop instructions are executed the clock source BCLK will switch to XT clock automatically In this option the XT clock provides the clock to the pre divider timer port chattering prevention and LCD circuitry in this option Halt Halt Halt mode Slow mode Slow Fast mode XTOSC active XTOSC active XTOSC active CFOSC stop HALT CFOSC stop E CFOSC active released Stop St released Reset R release Reset Reset state Reset Stop mode gt XTOSC active 4 XTOSC stop Power on reset Reset pin reset Watchdog timer reset Key reset CFOSC stop CFOSC stop State Diagram of Dual Clock Option shown above After executing FAST instructions the CF clock oscillator will start up and switch CF clock to BCLK after which the system clock generator will hold 12 CF clocks This will prevent the inco
70. 5 Bit1 for Rx 5 Bit2 for 5 Bit3 for Rx 5 y M 2 M M M um f 4 M 7 M gt lt t BCLK 2 If the 1 pin is used as the CX pin for the RFC function and the other pins IOA2 are used as normal IO pins the 1 pin must always be set to output mode to avoid being influenced by the CX when the input chattering prevention function is active On the other hand the RFC counter can receive signal changes on IOA1 when the RFC counter is enabled 3 5 2 IOB PORT IOB1 IOB4 pins are MUXed with ELC SEG28 ELP SEG29 BZB SEG30 and BZ SEG31 pins respectively by mask option MASK OPTION table Mask Option name Selected item SEG28 IOB1 ELC 2 IOB1 SEG29 IOB2 ELP 2 2 SEG30 IOB3 BZB 2 IOB3 SEG31 IOB4 BZ 2 4 78 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual The following figure shows the organization of IOB port bito Q L CLK Initial clear SPB 1 M O Initial clear 1 3 SPB2 lt Q Initial clear 4 H SPB 4 d Q Initial clear q HL SPB8 V ES Q gt O G SPB 10 H OPB OPBS Note M O is mask option Note If the input level is in the floating state a large current straight through current flows to the input buffer The input level must not be in the floating state
71. 7 Backup flag BCF Stop release enable flags SRF3 4 5 7 4 5 7 Switch enable flags 4 SEF3 4 C Halt release request flag HRF 0 6 Oe Halt release enable flags 1 HEF1 6 EE OO DCO to 3 Interrupt enable flags 0 to 3 IEFO 6 Alarm output ALARM DC 0 Pull down flags in I OD 1 with pull down resistor port Input output ports I OB PORT VOA VOC OD ae es VOD port chattering Cch clock EL panel driver pumping clock Celp source and duty cycle EL panel driver clearing clock Celc source and duty cycle i Frequency generator clock Cf PHO duty cycle is 1 4 output is source and duty cycle 4 inactive Resistor frequency converter nactive RR RT RH output 0 LCD driver output All lighted mask option 1 Ag Li version 0 EXTV version Timer 1 2 Inactive Watchdog timer WDT Reset mode WDF 0 XT clock slow speed clock in Clock source BCLK dual 2 P Notes PH3 the 3rd output of predivider PH10 the 10th output of predivider Mask option can unlighted all of the LCD output 68 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual 3 2 3 Port Key Matrix RESET The key reset function can be selected by mask option When the port or key matrix scanning input KI1 4 is in use the 0 signal is applied to all these pins that were set to the input mode at the same time KI1 4 pins need to wait scanning time
72. AC Rx lt STS3 B3 SCF7 PDV B2 PH15 B1 SCF5 TM1 BO SCFA INT MCX Rx 0100 01 OXXX XXXX lt 5 53 SCF9 RFC B2 No use B1 SCF6 TM2 BO SCF8 SKI MSD Rx 0100 10 OXXX XXXX AC Rx lt 5754 B2 RFOVF B1 WDF CSF SRO Rx 0101 0000 OXXX AC n Rx n lt Rx n 1 AC 3 Rx 3 0 SR1 Rx 0101 0001 OXXX XXXX AC n Rx n lt Rx n 1 AC 3 Rx 3 ga SLO Rx 0101 0010 OXXX XXXX AC n Rx n lt Rx n 1 AC O Rx O 0 SL1 Rx 0101 0011 OXXX XXXX AC n Rx n lt Rx n 1 AC O Rx O 1 DAA 0101 0100 0000 0000 AC lt BCD AC CF DAA Rx 0101 0101 OXXX XXXX lt DAA HL 0101 0101 1000 0000 AC R HL lt BCD AC CF DAA HL 0101 0101 1100 0000 AC R HL lt amp HL lt HL 1 DAS 0101 0110 0000 0000 AC lt BCD AC CF DAS Rx 0101 0111 OXXX XXXX Rx lt DAS HL 0101 0111 1000 0000 AC R HL lt DAS HL 0101 0111 1100 0000 AC R HL lt amp HL lt HL 1 LDS Rx D 0101 1DDD DXXX XXXX lt LDH Rx HL 0110 0000 OXXX XXXX lt H TQHL LDH Rx QHL 0110 0001 OXXX XXXX Rx lt H T HL amp HL lt HL 1 LDL Rx HL 0110 0010 OXXX XXXX AC Rx lt L TQHL LDL Rx HL 0110 0011 OXXX AC Rx lt L T HL HL lt HL 1 MRF1 Rx 0110 010
73. BF6 IDBF5 IDBF4 IDBF3 IDBF2 IDBF1 IDBFO 131 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual 5 7 DECIMAL ARITHMETIC INSTRUCTIONS DAA Function Description DAA Rx Function Description DAA HL Function Description DAA HL Function Description AC lt BCD AC Converts the content of AC to binary format and then restores to AC When this instruction is executed the AC must be the result of any added instruction The carry flag CF will be affected AC Rx lt BCD AC Converts the content of AC to binary format and then restores to AC and the data memory specified by Rx When this instruction is executed the AC must be the result of any added instruction The carry flag CF will be affected AC HL lt BCD AC Converts the content of AC to binary format and then restores to AC and the data memory specified by HL When this instruction is executed the AC must be the result of any added instruction The carry flag CF will be affected AC HL lt BCD AC HL HL 1 Converts the content of AC to binary format and then restores to AC and the data memory specified by HL The content of the index register HL will be incremented automatically after executing this instruction When this instruction is executed the AC must be the result of any added instruction The carry
74. CA KI1 2 IOC1 SEG33 IOC2 KI2 2 IOC2 SEG34 IOC3 KI3 2 IOC3 SEG35 lIOC4 K14 2 IOC4 After the reset cycle the port is set to input mode Each bit of port can be set to input or output mode individually by executing SPC instructions Executing the OPC instruction may output the contents of specified data memory to the pins set as output the other pins which are set to input will still remain in the input mode When IPC instructions are executed they may store the signals applied to the IOC pins in specified data memory locations When the IOC pins are set as output executing IPC instructions will save the data stored in the output latches in the specified data memory location Before executing SPC instructions to set the IOC pins as output the OPC instruction must be executed to output data to the output latches This will prevent the occurrence of the chattering signal when the IOC pins change to output mode The IOC port may select the pull low device or the low level hold device for each pin through the mask option or enable disable this device by program setting When the pull low device and low level hold device are both enabled through the mask option the reset will enable the pull low device and disable the low level hold device Executing the SPC 10h instruction will also enable the pull low device and disable the low level hold device Executing the SPC Oh instruction will disable the pull low device and enable the lo
75. CTION ROM TABLE ROM G 15 3968 256 INSTRUCTION lt gt TABLE ROM H 16 4096 0 2 4 1 INSTRUCTION ROM PROM There are some special locations that serve as interrupt service routines such as reset address 000H interrupt O address 014H interrupt 1 address 018H interrupt 2 address 010H interrupt 3 address 01CH interrupt 4 address 020H interrupt 5 address 024H and interrupt 6 address 028H in the program memory When the useful address range of PROM exceeds 2048 addresses 800h the memory space of PROM will automatically be defined as 2 pages Refer to section 2 3 Address address 000h Initial reset 000H 010h Interrupt 2 014h Interrupt O 018h Interrupt 1 zo 01Ch Interrupt 3 2 Low os Nibble 020h Interrupt 4 eo 024h Interrupt 5 028h Interrupt 6 XFFH 8 Bits 2048 128 X 15 N N 1 gt 15 4 4 16 bits Instruction ROM PROM organization This figure shows the Organization of ROM Table ROM TROM organization 33 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual 2 4 2 TABLE ROM TROM The table ROM is organized with 256 16 N x 8 bits that share memory space with the instruction ROM as shown in the figure above This memory space stores the constant data or look up table for the usage of main program All of the table ROM addre
76. CY GENERATOR The Frequency Generator is a versatile programmable divider that is capable of delivering a clock with wide frequency range and different duty cycles The output of the frequency generator may be the clock source for the alarm function timer1 timer2 and RFC counter The following shows the organization of the frequency generator 8 bit Programmable Duty Cycle gt gt Frequency output Divider Generator FREQ AC1 ACO Rx3 Rx0 BCLK PHO a SCC The SCC instruction may specify the clock source selection for the frequency generator The frequency generator outputs the clock with different frequencies and duty cycles corresponding to the preset data of FRQ related instructions The FRQ related instructions preset a letter N into the programming divider and the letter D into the duty cycle generator The frequency generator will then output the clock using the following formula FREQ clock source N 1 X Hz 1 2 3 4 for 1 1 1 2 1 3 1 4 duty This letter N is a combination of the data memory and the accumulator AC or the table ROM data or the operand data specified in the FRQX instruction The following table shows the bit pattern of the combination The table shows the bit pattern of the preset letter N The bit pattern of preset letter N bit5 54 Bit2 bit1 bito divider x0 DRx C2 AC1 ACO Rx3 R2 Rxt FRO
77. D2 Note 2 The backup flag BCF is set in the initial clear mode When the backup flag is set the internal logic operated on VDD2 and the oscillator circuit becomes large in driver size When the backup flag is set the operating current is increased Therefore the backup flag must be reset unless otherwise required For information on the backup flag refer to 3 5 Note 3 The VDD1 level 1 2 VDD at the off state of SW1 is used as an intermediate voltage level for LCD driver 18 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual 2 1 3 EXT V POWER SUPPLY Operating voltage range 3 6V 5 4V The connection diagrams for different LCD bias applications are shown below 2 1 3 1 NO BIAS AT EXT V BATTERY POWER SUPPLY CUPO N C CUP1 N C CUP2 N C VDD4 VDD3 VDD2 VDD1 logic BAK GND MASK OPTION table Mask Option name Selected item POWER SOURCE 1 EXT V BIAS 1 NO BIAS Note 1 The input output ports operate between GND and VDD2 Note 2 At the initial clear mode the backup flag BCF is reset Note 3 At the backup flag set mode the operating current is increased 2 1 3 2 1 2 BIAS AT EXT V POWER SUPPLY CUPO Nc CUP1 0 1u zz CUP2 VDD4 VDD3 VDD2
78. DNI Ry D Function Description ANDI Ry D Function Description ANDI Ry D Function Description EORI Ry D Function Description EORI Ry D Function Description ORI Ry D Function Description ORI Ry D Function Description TM8726 User s Manual AC Ry Ry D D represents the immediate data Binary ADDs the contents of Ry and D the result is loaded to AC and the working register Ry The result will not affect the carry flag CF D 0H FH lt Ry amp D D represents the immediate data Binary ANDs the contents of Ry and D the result is loaded to AC D 0H FH lt Ry amp D D represents the immediate data Binary ANDs the contents of Ry and D the result is loaded to AC and the working register Ry D 0H FH AC lt Ry EOR D D represents the immediate data Exlusive Ors the contents of Ry and D the result is loaded to AC D 0H FH AC Ry lt Ry D D represents the immediate data Exclusive Ors the contents of Ry and D the result is loaded to AC and the working register Ry D 0H FH AC lt Ry D D represents the immediate data Binary Ors the contents of Ry and D the result is loaded to AC D 0H FH AC Ry Ry D D represents the immediate data Binary Ors the contents of Ry and D the result is loaded to AC and the working register Ry D 0H FH 125 tenx techno
79. If the overflow flag is not set to 1 read the content of the counter if the overflow flag has been set to 1 you must reduce the time period and repeat the previous procedure again In this example use the RR network to generate the clock source Timer 1 is used to enable disable the counter LDS 0 0 sets the TMR1 clock source 9 LDS 1 3 initiates TMR1 setting value to 3F LDS 2 OFh SHE 2 enables halt release by TMR1 RE LDA 0 OR 1 combines the TMR1 setting value TMS 2 enables the TMR1 SRF 9 builds up the RR network and enables the counter HALT SRF 1 stops the counter when TMR1 underflows MRF1 10h reads the content of the counter MRF2 11h MRF3 12h MRF4 13h MSD 20h JB2 CNT1_OF checks the overflow flag of counter JMP DATA_ACCEPT CNT1_OF DEC 2 decreases the TM1 value LDS 20h 0 SBC 1 JZ CHG CLK RANGE changes the clock source of TMR1 PLC 1 clears the halt release request flag of TMR1 JMP RE CNT 90 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual 3 8 3 Enabling Disabling the Counter by Timer 2 TMR2 will control the operation of the counter in this mode When the counter is controlled by an SRF 18 instruction the counter will start to operate until TMR2 is enabled and the first falling edge of the clock source gets into TMR2 When the TMR2 underflow occurs the counter will be disabled and will stop counting the CX clock This mode can set an accurate time
80. K HL T HL 7 T HL 6 TQHL 5 T HL 4 T HL 3 T HL 2 T HL 1 T HL O SPKX X X7 X6 X5 X4 X3 X2 X1 X0 ALM X Function Sets the buzzer output frequency Description The waveform specified by X X8 X0 is delivered to the BZ and BZB pins The output frequency could be any combination in the following table The bit pattern of X for higher clock source 1 X 1 56 1 clock source higher frequency EEEEEEEEEEL ANNE FREQ DC1 t CPE 0 1 0 e PH KH po oO o 1 0 o 0 pco The bit pattern of X for lower frequency clock source PH12 8Hz PH11 16Hz PH10 32Hz Notes 1 FREQ is the output of the frequency generator 2 When the buzzer output does not need the envelope waveform X5 X0 should be set to 0 3 The frequency inside the bases on the PHO is 32768Hz 112 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual ELC X Function The bit control of the EL panel driver Description The meaning of each bit specified by X X9 X0 is shown below For ELP pin output clock setting X8 X7 X6 Pumping clock X9 X5 X4 Duty cycle frequency 000 10 JJ13 4duy BCLK 2 3 duty r HA ty Note represents don t care For ELC pin output clock setting frequency 00 8 00 14duy SRF X Function The operation control for RFC Description The meaning of ea
81. LCD frame frequency 2 TYPICAL 32Hz LCD frame frequency 2 FAST 64Hz LCD frame frequency 2 O P OHz LCD not used The LCD alternating frequency in 1 5 duty type Mask Option name Selected item Remark alternating frequency LCD frame frequency 1 SLOW 25Hz LCD frame frequency 2 TYPICAL 51Hz LCD frame frequency 2 FAST 102Hz LCD frame frequency 2 O P OHz LCD not used The LCD alternating frequency in 1 6 duty type Mask Option name Selected item Remark alternating frequency LCD frame frequency 1 SLOW 21Hz LCD frame frequency 2 TYPICAL 42Hz LCD frame frequency 2 FAST 85Hz LCD frame frequency 2 O P OHz LCD not used 98 tenx technology inc Rev 1 1 2007 06 28 Advance Information The LCD alternating frequency in 1 7 duty type TM8726 User s Manual Mask Option name Selected item Remark alternating frequency LCD frame frequency 1 SLOW 18Hz LCD frame frequency 2 TYPICAL 36Hz LCD frame frequency 2 FAST 73 2 LCD frame frequency 2 O P OHz LCD not used The LCD alternating frequency in 1 8 duty type Mask Option name Selected item Remark alternating frequency LCD frame frequency 1 SLOW 32Hz LCD frame frequency 2 TYPICAL 64Hz LCD frame frequency 2 FAST 128Hz LCD frame frequency 2 O P OHz LCD not used The LCD alternating frequency in 1 9 duty type Mask Option name Selected item Remark alternating frequency
82. MASK OPTION table Mask Option name Selected item POWER SOURCE 2 3V BATTERY OR HIGHER BIAS 2 1 2 BIAS Note 1 The input output ports operate between GND and VDD2 Note 2 The backup flag BCF is set in the initial clear mode When the backup flag is set the internal logic operated on VDD2 and the oscillator circuit becomes large in driver size 0 11 3 0V When the backup flag is set the operating current is increased Therefore the backup flag should be reset unless otherwise required For information on the backup flag refer to 3 5 Note 3 The VDD1 level 1 2 VDD2 at the off state of SW1 is used as an intermediate voltage level for the LCD driver 16 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual 2 1 2 3 1 3 BIAS AT Li BATTERY POWER SUPPLY The backup flag BCF must be reset after the operation of the halver circuit is fully stabilized and a voltage of approximately 1 2 VDD2 appears on the VDD1 pin Backup flag BCF BCF 0 BCF 1 CUPO wc CUP1 0 1u CUP2 VDD4 ge VDD2 SW2 VDD1 SWI BAK 30V Internal logic GND e MASK OPTION table Mask Option name Selected item POWER SOURCE 2 3V BATTERY OR HIGHER BIAS 3 1 3 BIAS Note 1 The input output
83. R to output The stop release enable flag 4 SRF4 is must be set beforehand A high level signal comes from the OR ed output of the pins defined as input mode in IOD port which causes the stop release flag of IOD port DSR to output The stop release enable flag SRF3 must be set beforehand A high level signal comes from the OR ed output of the signals latch for 1 4 which causes the stop release flag of Key Scanning SKI to output The stop release enable flag 4 SRF7 must be set beforehand The signal change from the INT pin causes the halt release flag 2 HRF2 to output The stop release enable flag 5 SRF5 must be set beforehand The following figure shows the organization of start condition flag 11 SCF 11 Scr41 Stop release request SRF7 5 The stop release flags SKI CSR DSR HRF2 were specified by the stop release enable flags SRFx These flags should be clear before the chip enters stop mode All of the pins in the IOA and IOC ports have to be set in input mode and keep in 0 state before the chip enters the STOP mode otherwise the program can not enter STOP mode Instruction SRE is used to set or reset the stop release enable flags SRF4 5 7 The following table shows the stop release request flags The OR ed The OR ed input The rising or latched signals for mode pins of falling edge on INT 1 4 IOC IOD port pin Stop release request flag CSR DSR HRF2
84. RFC application muxed with SEG24 27 by mask option RR RT RH ELC ELP O Output port for El panel driver muxed with SEG28 29 by mask option BZB BZ Output port for alarm clock or single tone melody generator muxed with SEG30 31 by mask option K1 K16 O Output port for key matrix scanning Shared with SEG1 SEG16 1 4 Input port for key matrix scanning Muxed with SEG32 SEG35 by mask option GND Negative supply voltage 7 tenx technology inc Rev 1 1 2007 06 28 Advance Information 1 7 CHARACTERIZATION ABSOLOUTE MAXIMUM RATINGS TM8726 User s Manual GND 0V Name Symbol Range Unit Maximum Supply Voltage VDD1 0 3 to 5 5 V VDD2 0 3 to 5 5 V VDD3 0 3 to 8 5 V VDD4 0 3 to 8 5 V Maximum Input Voltage Vin 0 3 to VDD1 2 0 3 V Maximum output Voltage Vout1 0 3 to VDD1 2 0 3 V Vout2 0 3 to VDD3 0 3 V Vout3 0 3 to VDD4 0 3 V Maximum Operating Temperature Topg 20 to 70 C Maximum Storage Temperature Tstg 25 to 125 ps POWER CONSUMPTION at Ta 20 C to 70 C GND 0V Name Sym Condition Min Typ Max Unit HALT mode uar Only 32 768KHz Crystal oscillator 2 uA operating without loading Ag mode VDD1 1 5V BCF 0 IHALT2 Only 32 768KHz Crystal oscillator 2 uA operating without loading Li mode VDD2 3 0V BCF 0 STOP mode sroP 1 uA Note When RC oscillator function is operating the current consumption w
85. T PIN RESET When H level is applied to the reset pin the reset signal will be issued There is a built in pull down resistor on this pin Two types of reset methods for the RESET pin and the type can be set with the mask option One is level reset and other is pulse reset It is recommended that you connect a capacitor 0 1uf between the RESET pin and the VDD This connection will prevent the issuance of the bounce signal on the RESET pin 3 2 2 1 Level Reset Once a H signal is applied on the RESET pin TM8726 will not release the reset cycle until the signal on the RESET pin is returned to 0 After the signal on the reset pin is cleared to 0 TM8726 begins the internal reset cycle and then releases the reset status automatically MASK OPTION table Mask Option name Selected item RESET PIN TYPE 1 LEVEL 67 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual 3 2 2 2 Pulse Reset Once a H signal is applied on the RESET TM8726 will escape from the reset state and begin normal operation after the internal reset cycle automatically no matter whether the signal on the RESET pin is returned to 0 or not MASK OPTION table Mask Option name Selected item RESET PIN TYPE 2 PULSE The following table shows the initial conditions of TM8726 in reset cycle Program counter PC Address 000H 0 Start condition flags 1 to 7 SCF1
86. When the TMR2 clock is PH15 TMR2 set time Set value error 32768 1 fosc KHz ms 4 When the TMR2 clock is PH5 TMR2 set time Set value error 32 1 fosc KHz ms 5 When the timer clock is PH7 TMR2 set time Set value error 128 1 fosc KHz ms 6 When the TMR2 clock is PH11 43 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual TMR2 set time Set value error 2048 1 fosc KHz ms 7 When the TMR2 clock is PH13 TMR2 set time Set value error 8192 1 fosc KHz ms Set value Decimal number of timer set value error the tolerance of set value 0 error 1 fosc Input of the predivider PH3 The 3rd stage output of the predivider PH5 The 5th stage output of the predivider PH7 7th stage output of the predivider PH9 The 9th stage output of the predivider PH11 The 11th stage output of the predivider PH13 The 13th stage output of the predivider PH15 The 15th stage output of the predivider 8 When the TMR2 clock is FREQ TMR2 set time Set value error 1 FREQ KHz ms FREQ refer to section 3 3 4 2 13 2 RE LOAD OPERATION TMR2 also provides the re load function the same as 1 The instruction SF2 1 enables the re load function the instruction RF2 1 disables it 2 13 3 TIMER 2 TMR2 IN RESISTOR TO FREQUENCY CONVERTER RFC TMR2 also controls the operation of RFC function TMR2 will set TENX flag to 1 to enab
87. XDX xz xe xo X4 x3 x2 xt xo Notes 1 T7 represents the data of table ROM 2 X0 X7 represents the data specified in operand X 71 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual The following table shows the bit pattern of the preset letter D Preset Letter D Dutv Cvcle DI p O 77 0 O 1 4duty oO 1 1 3duty 110 f 2duy The following diagram shows the output waveform for different duty cycles LJ LI LI LI LI LI LU LI 1 4 duty carrier out 1 3 duty carrier out j j 4 p 1 2 duty carrier out __ J 1 1 duty carrier out 3 3 2 Melody Output The frequency generator may generate frequencies for melody usage When the frequency generator is used to generate melody output the tone table is shown below 1 The clock source is PHO i e 32 768 Hz 2 The duty cycle is 1 2 Duty 2 3 FREQ is the output frequency 4 ideal is the ideal tone frequency 5 96 is the frequency deviation The following table shows the note table for melody application Tone FREQ Ideal FREQ Ideal C2 249 65 5360 65 4064 0 19 C4 62 260 063 261 626 0 60 E2 198 82 3317 824069 0 09 E4 49 327 680 329 628 0 59 72 tenx technology inc Rev 1 1 2007 06 28 Advance Information
88. Y LCD DUTY CYCLE 7 1 7 DUTY LCD DUTY CYCLE 8 1 8 DUTY 1 2 3 4 LCD DUTY CYCLE b 1 5 DUTY 6 7 8 9 LCD DUTY CYCLE 9 1 9 DUTY 97 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual LCD bias option Mask Option name Selected item BIAS 1 NO BIAS BIAS 2 1 2 BIAS BIAS 3 1 3 BIAS BIAS 4 1 4 BIAS The frame frequency for each lighting system is shown below these frequencies can be selected by mask option All of the LCD frame frequencies in the following tables are based on the clock source frequency of the pre divider PHO is 32768 2 The LCD alternating frequency in duplex 1 2 duty type Mask Option name Selected item Remark alternating frequency LCD frame frequenc 1 SLOW 16Hz LCD frame frequency 2 TYPICAL 32Hz LCD frame frequency 2 FAST 64Hz LCD frame frequency 2 O P OHz LCD not used The LCD alternating frequency in 1 3 duty type Mask Option name Selected item Remark alternating frequency LCD frame frequency 1 SLOW 21Hz LCD frame frequency 2 TYPICAL 42Hz LCD frame frequency 2 FAST 85Hz LCD frame frequency 2 O P OHz LCD not used The LCD alternating frequency in 1 4 duty type Mask Option name Selected item Remark alternating frequency LCD frame frequency 1 SLOW 16Hz
89. ag RFOVF 1 check by MSD instruction the 16bits counter will be disable to 0000h or not by mask option Mask Option name Selected item RFC OVERFLOW DISABLE COUNTER 1 USE RFC OVERFLOW DISABLE COUNTER 2 NO USE If select USE the RFOVF willn t be hold to 1 and counter willn t be disable to 0000h RFOVF just only be used as 17th bit of the counter here The RFC function provides 3 modes for the operation of the 16 bit counter Each mode will be described in the following sections 89 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual 3 8 2 Enabling Disabling the Counter by Software The clock input of the 16 bit counter comes from the CX pin and is enabled disabled by the S W When an SRF 8h instruction is executed the counter will be enabled and will start to count the signals on the CX pin The counter will be disabled when SRF 0 instruction is executed Executing MRF1 4 instructions may load the result of the counter into the specified data memory and AC Each time the 16 bit counter is enabled the content of the counter will be cleared automatically Example If you intend to count the clock input from the CX pin for a specified time period you can enable the counter by executing an SRF 8 instruction and setting timer1 to control the time period Check the overflow flag RFOVF of this counter when the time period elapses
90. al INT pin interrupt request By using the mask option either a rise or fall of the signal at the INT pin can be selected for applying an interrupt If the interrupt enable flag 2 IEF2 is set and the change signal on the INT pin matches the mask option it will issue the HRF2 Interrupt 2 is accepted and the instruction at address 10H is executed automatically It is necessary to apply level L before the signal rises and level H after the signal rises to the INT pin for at least 1 machine cycle 2 port IOC IOD interrupt request An interrupt request signal HRFO is delivered when the input signal changes at the I O port IOC IOD specified by the SCA instruction In this case if the interrupt enabled by flag 0 IEFO is set to 1 interrupt O is accepted and the instruction at address 14H is executed automatically 3 Key matrix Scanning interrupt request An interrupt request signal HRF5 is delivered when the input signal is generated in the scanning interval If the interrupt enable flag 5 IEF5 is set to 1 and interrupt 5 is accepted the instruction at address 24H will be executed automatically 3 1 1 2 Internal interrupt factor The internal interrupt factor involves the use of timer 1 TMR1 timer 2 TMR2 RFC counter and the pre divider 1 Timer1 2 TMR1 2 interrupt request An interrupt request signal HRF1 4 is delivered when timer1 2 TMR1 2 underflows In that case if the interrupt enable flag 1 4 IEF1 4
91. ame Selected item F SEGMENT FOR DISPLAY 7 1 ON F SEGMENT FOR DISPLAY 7 2 OFF Both LCT and LCB instructions use the data decoder table to decode the content of the specified data memory location When the content of the data memory location specified by the LCB instruction is 0 the decoded outputs of DBUSA DBUSH are all 0 this is used for blanking the leading digit 0 on the LCD panel The LCP instruction transfers data about the RAM Rx and accumulator AC directly from DBUSA to without passing through the data decoder The LCD instruction transfers the table ROM data T HL directly from to DBUSH without passing through the data decoder Table 2 2 The mapping table of LCP and LCD instructions DBUSA DBUSB DBUSC DBUSD DBUSE DBUSF DBUSG DBUSH There are 8 data decoder outputs from DBUSA to DBUSH and 64 LO to L5 decoder outputs from PSTB Oh to PSTB 3Fh The input data and clock signal of the latch circuit are DBUSA to DBUSH and PSTB Oh to PSTB 1Fh respectively Each segment pin has 9 latches corresponding to COM 1 9 The segment PLA performs the function of combining DBUSA outputs to DBUSH inputs and then sending them to each latch and strobe PSTB Oh to PSTB3Fh is selected freely by mask option Of the 512 signals obtainable by combining DBUSA to DBUSH PSTB Oh to PSTB 3Fh any one of 369 corresponding t
92. and FREQ has a 1 3 duty waveform SHE 40h enables the halt release caused by 16 bit counter SRF 28h enables the counter controlled by the CX signal HALT PLC 40h release is caused by the 274 rising edge on CX pin and then clears the halt release request flag MRF1 10h reads the content of the counter MRF2 11h MRF3 12h MRF4 13h 92 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual 3 9 Key Matrix Scanning TM8726 shares the timing of the LCD waveform to scan the key matrix circuitry These scanning output pins are SEG1 16 for easy to understand named these pins as K1 K16 The time sharing of the LCD waveform will not affect the display of the LCD panel The input port of the key matrix circuitry is composed of 1 4 pins these pins are muxed with SEG32 SEG35 pins and selected by mask option MASK OPTION table Mask Option name Selected item SEG32 IOC1 KI1 3 1 5 2 2 3 2 SEG34 IOC3 KI3 3 KI3 SEG35 IOCA KIA 3 4 The typical application circuit of the key matrix scanning is shown below Executing SPKX X SPK Rx and SPK instructions could set the scanning type of the key matrix The bit patterns of these 3 instructions are shown below K16 K15 14 K13 K12 K11 K10 K9 K8 K7 K6 K5 K4 K2
93. are held at L level When the signal changes at the input pins of IOD port specified by the SCA instruction occur and keep the state for at least two chattering clock PH6 PH8 and PH10 cycles the control circuit at the input pins will deliver the halt release request signal SCF3 At that time the chattering prevention clock will stop due to the delivery of SCF3 The SCF3 will be reset to 0 by executing SCA instruction and the chattering prevention clock will be enabled at the same time If the SCF3 has been set to 1 the halt release request flag 0 HRFO will be delivered In this case if the port IOD interrupt enable mode IEFO is provided the interrupt is accepted Since no flip flop is available to hold the information of the signal at the input pins IOD1 to IODA the input data at the port IOD must be read into the RAM immediately after the halt mode is released 3 6 EL PANEL DRIVER TM8726 provides an EL panel driver for the back light of the LCD panel The user can choose different voltage pumping frequencies duty cycle and ON OFF frequency to operate with few external components This circuitry could generate output voltage up to AC 150V or above for driving the EL plant the ELC and ELP output is MUXed with IOB1 SEG28 and IOB2 5 29 and is selected by mask option MASK OPTION table Mask Option name Selected item SEG28 IOB1 ELC 3 ELC SEG29 IOB2 ELP 3 ELP The ELP pin will output clocks t
94. ask option the input output function of the pins will be disabled 3 5 1 IOA PORT 1 IOA4 pins are MUX with CX SEG24 RR SEG25 RT SEG26 and RH SEG27 pins respectively by mask option MASK OPTION table Mask Option name Selected item SEG24 IOA1 CX 2 IOA1 SEG25 IOA2 RR 2 2 SEG26 IOA3 RT 2 IOA3 SEG27 IOA4 RH 2 IOA4 In initial reset cycle the port is set to input mode and each bit of port can be set to input or output mode individually by executing SPA instructions Executing OPA instructions may output the content of specified data memory to the pins defined as output mode the pins defined set to input mode will still remain in the input mode Executing IPA instructions may store the signals applied to the IO pins into specified data memory locations When the IO pins are set to output mode executing IPA instructions will store the contents of the latch of the output pin into the specified data memory location Before executing the SPA instruction to set the I O pins to output mode the OPA instruction must be executed to output the data to those output latches beforehand This will prevent the chattering signal on the I O pin when the I O mode changes The IOA port has a built in pull down resistor The pull low device for each pin is selected by mask option and then executing the SPA instruction to enable disable the device Pull low function option
95. atically before the program enters the stop mode 27 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual Halt Normal mode Halt Halt mode OSC active released OSC active Reset release Reset Stop Stop Release Stop mode OSC stop Reset mode OSC active Power on reset Reset Reset pin reset Watchdog timer reset Key reset This figure shows the State Diagram of Single Clock Option 2 2 4 PREDIVIDER The pre divider is a 15 stage counter that receives the clock from the output of clock switch circuitry PHO as input When is changed from H level to L level the contents of this counter changes The PH11 to PH15 of the pre divider are reset to 0 when the PLC 100H instruction is executed or during the initial reset mode The pre divider delivers the signal to the halver tripler circuit alternating frequency for LCD display system clock sound generator and halt release request signal 1 port chattering prevention clock Frequency Interrupt request Halt mode SLOW instruction FAST instruction Clock switch circuit XTOSC CFOSC Single clock option Dual clock option Clock switch circuit BCLK T1 T2 T3 T4 Sclk System clock generator PHO Initial PLC 8H Interrupt SCF7 Fall edge detector HALT release HRF3 request flag MSC instruction Data bus 2
96. bOh SRF7 5 4 are set so that the signal changes at 1 4 pins port IOC and INT pin cause the stop mode to be released STOP Enters the stop mode MEET STOP release MSC 10h Checks the signal change at INT pin that causes the stop mode to be released MSB 11h Check the signal change at port IOC that causes the stop mode to be released MCX 12h Checks the signal change at 1 4 pins that causes the stop mode to be released 56 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual 2 16 HALT FUNCTION The halt function is provided to minimize the current dissipation of the TM8726 when the LCD is operating During halt mode the program memory ROM is not in operation only the oscillator circuit pre divider circuit sound circuit port chattering prevention circuit and LCD driver output circuit are in operation If the timer has started operating the timer counter still operates in the halt mode After the HALT instruction is executed and no halt release signal SCF1 SCF3 HRF1 6 is delivered the CPU enters halt mode The following 3 conditions are available to release halt mode 1 An interrupt is accepted When an interrupt is accepted the halt mode is released automatically and the program will enter halt mode again by executing the RTS instruction after completion of the interrupt service When halt mode is released and an interrupt is accepted the ha
97. be defined as CMOS type DC output or P open drain DC output ports by mask option In these cases it is possible to use some LCD driver output pins as DC output and the rest of the LCD driver output pins as LCD drivers Refer to 4 3 4 The configurations of CMOS output type and P open drain type are shown below When the LCD driver output pins SEG are defined as DC output ports the output data on those ports will not be affected when the program enters stop mode or LCD turn off mode VDD P SEG Figure 5 1 CMOS Output Type Figure 5 2 P Open Drain Output Type Only unused COM and SEG pads can be defined as DC output pins The COM pad sequence for LCD drivers cannot be interrupted when the COM pads are defined as DC output ports For example when the LCD lighting system is specified as 1 5 duty the COM pad used for LCD driver must be COM1 COM5 Each of COM6 pad can be defined as DC output ports 100 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual 4 3 SEGMENT PLA CIRCUIT FOR LCD DISPLAY 4 3 1 PRINCIPLE OF OPERATION OF LCD DRIVER SECTION The explanation below explains how the LCD driver section operates when the instructions are executed gt Latch circuit 369 il AC amp RAM data decoder Strobe data oco Lj beoe strobe LO to L5 related a Jl instruction DBUSA DBUSH memory
98. both the pull low and L level hold devices are disabled The input level must not be in the floating state 3 5 4 1 Chattering Prevention Function and Halt Release The port IOD is capable of preventing high low chattering of the switch signal applied on the IOD1 to IOD4 pins Chattering prevention time can be selected as 10 32ms PH8 8ms or PH6 2ms by executing the SCC instruction the default selection is PH10 after the reset cycle When the pins of the IOD port are set as output the signals applied to the output pins will be inhibited for the chattering prevention function The following figure shows the organization of chattering prevention circuitry 84 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual IEFO Interrupt Edge mS Q HRFO request detect R edge dectect amp chattering SCF3 pHALT released request chattering PH10 prevention PH8 PLC 1 PH6 clcok S Q Interrupt accept SCC intruction R SCA intruction Note The default prevention clock is PH10 This figure shows the organization of chattering prevention circuitry This chattering prevention function works when the signal at the applicable pin ex IOD1 is changed from L level to H level or from H level to L level and the remaining pins ex IOD2 to IOD4
99. ch control bit X5 X0 is shown below the RC oscillation network the RC oscillation network of RR RR the RC oscillation network the RC oscillation network of RT RT penes the RC oscillation network the RC oscillation network of RH RH set to 1 when this bit is set to 1 iil 16 bit counter is controlled by the uu the CX pin to control the 16 bit signal on CX pin X3 must be set to 1 counter when this bit is set to 1 Note X4 and X5 can not be set to 1 at the same time 113 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual 5 2 ACCUMULATOR MANIPULATION INSTRUCTIONS AND MEMORY MANIPULATION INSTRUCTIONS MRW Ry Rx Function lt Rx Description The content of Rx is loaded to AC and the working register specified by Ry MRW HL Rx Function AC R HL lt Rx Description The content of the data memory specified by Rx is loaded to AC and the data memory specified by HL MRW HL Rx Function AC R HL lt Rx HL HL 1 Description The content of data memory specified by Rx is loaded to AC and the data memory specified by HL The content of the index register HL will be incremented automatically after executing this instruction MWR Rx Ry Function AC Rx lt Ry Description The content of the working register specified by Ry is loaded to AC and the data memory specified by Rx MWR Rx HL Function AC
100. ck is PH3 TMR2 set time Set value error 8 1 fosc KHz ms 2 When the TMR2 clock is PH9 TMR2 set time Set value error 512 1 fosc KHz ms 3 When the TMR2 clock is PH15 TMR2 set time Set value error 32768 1 fosc KHz ms 4 When the TMR2 clock is PH5 TMR2 set time Set value error 32 1 fosc KHz ms 5 When the timer clock is PH7 TMR2 set time Set value error 128 1 fosc KHz ms 6 When the TMR2 clock is PH11 TMR2 set time Set value error 2048 1 fosc KHz ms 7 When the TMR2 clock is PH13 40 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual TMR2 set time Set value error 8192 1 fosc KHz ms Set value Decimal number of timer set value error the tolerance of set value 0 error 1 fosc PH3 PH5 9 PH11 The 11th stage output of the predivider PH13 The 13th stage output of the predivider PH15 The 15th stage output of the predivider 8 When the TMR1 clock is FREQ 1 set time Set value error 1 FREQ KHz ms Input of the predivider The 3rd stage output of the predivider The 5th stage output of the predivider The 7th stage output of the predivider The 9th stage output of the predivider FREQ refer to section 3 3 4 2 12 2 RE LOAD OPERATION TMR1 provides the re load function which can extend any time interval greater than 3Fh The SF 80h instruction enables
101. de the BCF will set to 1 automatically to insure that the low speed oscillator will start up in a proper condition while stop release occurs 2 18 STOP FUNCTION STOP The stop function is another solution used to minimize the current dissipation for TM8726 In stop mode all of the functions in TM8726 are held including oscillators All of the LCD corresponding signals COM and Segment will output L level In this mode TM8726 does not dissipate any power in the stop mode Because the stop mode will set the BCF flag to 1 automatically it is recommended to reset the BCF flag after releasing the stop mode in order to reduce power consumption Before the stop instruction is executed all of the signals on the pins set to input modes on IOD and IOC ports must be in the L state and no stop release signal SRFn should be delivered The CPU will then enter stop mode The following conditions cause stop mode to be released One of the signals on the input mode pin of IOD or IOC port is in H state and holds long enough to cause the CPU to be released from halt mode A signal is changed at the INT pin The stop release condition specified by the SRE instruction is met When the TM8726 is released from stop mode the TM8726 enters the halt mode immediately and will process the halt release procedure If the H signal on the IOC IOD port does not hold long enough to set the SCF1 SCF3 once the signal on the IOC port returns to L t
102. dvance Information TM8726 User s Manual The default setting after the initial reset is ELP PHO clock of pre divider and 1 4 duty cycle ELC PH8 clock of pre divider and 1 4 duty cycle The timing of the duty cycle is shown below PHO PH8 1 4 duty 1 3 duty EE qui 1 1 duty Example ELC 110 ELP outputs BCLK clock with 1 3 duty cycle and ELC outputs 8 clock with 1 4 duty cycle SF 4h Enables the light control signal LIT and turns on the EL light driver RF 4h Disables the light control signal and turns off the EL light driver 3 7 EXTERNAL INT PIN The INT pin can be selected as a pull up pull down or open type by mask option The signal change either rising edge or falling edge by mask option sets the interrupt flag delivering the halt release request flag 2 HRF2 In this case if the halt release enable flag HEF2 is provided the start condition flag 2 is delivered If the INT pin interrupt enable mode IEF2 is provided the interrupt is accepted MASK OPTION table For internal resistor type Mask Option name Selected item INT PIN INTERNAL RESISTOR 1 PULL HIGH INT PIN INTERNAL RESISTOR 2 PULL LOW INT PIN INTERNAL RESISTOR 3 OPEN TYPE For input triggered type Mask Option name Selected item INT PIN TRIGGER MODE 1 RISING EDGE INT PIN TRIGGER MODE 2 FALLING EDGE 87 tenx technology inc Rev 1 1 2007 06 28 8726 User s Manual
103. e data memory specified by Rx Bit 3 RFC 11 Bit 2 RFC 10 Bit 1 RFC 9 Bit 0 RFC 8 Rx AC lt RFC 15 12 Loads the highest nibble data of the 16 bit counter of RFC to AC and the data memory specified by Rx Bit 3 RFC 15 127 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual Bit 2 RFC 14 Bit 1 RFC 13 Bit 0 RFC 12 5 5 CPU CONTROL INSTRUCTIONS NOP Function Description HALT Function Description STOP Function Description SCA X Function Description SIE X Function Description no operation no operation Enters halt mode The following 3 conditions cause the halt mode to be released 1 An interrupt is accepted 2 The signal change specified by the SCA instruction is applied to the ports IOC SCF1 or IOD SCF3 3 The halt release condition specified by the SHE instruction is met HRF1 HRF6 When an interrupt is accepted to release the halt mode the halt mode returns by executing the RTS instruction after the completion of the interrupt service Enters stop mode and stops all oscillators Before executing this instruction all signals on IOC port must be set to low The following 3 conditions cause the stop mode to be released 1 One of the signals on the input mode pin of IOD or IOC port is in H state and holds long enough to cause the CPU to be released from halt mode 2
104. e of the Start condition Start condition flag 7 pre divider flag 5 flag 4 SCF7 SCF5 SCF4 Halt release Halt release Halt release caused by pre caused by TMR1 caused by INT divider overflow underflow pin Read only Read only Read only Read only 2 14 4 STATUS REGISTER 3X STS3X When the halt mode is released with start condition flag 2 SCF2 status register 3X STS3X will store the status of the factor in the release of the halt mode Status register 3X STS3X consists of 3 flags 1 Start condition flag 8 SCF8 SCF8 is set to 1 when of 1 4 1 0 1 4 1 LED mode 1 4 0 in LCD mode causes the halt release request flag 5 HRF5 to be outputted and the halt release enable flag 5 HEF5 is set beforehand To reset the start condition flag 8 SCF8 the PLC instruction must be used to reset the halt release request flag 5 HRF5 otherwise the SHE instruction must be used to reset the halt release enable flag 5 HEF5 2 Start condition flag 6 SCF6 SCF6 is set to 1 when an underflow signal from timer 2 TMR2 causes the halt release request flag 4 HRF4 to be outputted and the halt release enable flag 4 HEF4 is set beforehand To reset the start condition flag 6 SCF6 the PLC instruction must be used to reset the halt release request flag 4 HRF4 otherwise the SHE instruction must be used to reset the halt release enable flag 4 HEF4 3 Start condition flag 9 SCF9 SCF9 is set when a finish
105. ecified by Lz is from 00H to 3FH 5 1 INPUT OUTPUT INSTRUCTIONS LCT Lz Ry Function Description LCB Lz Ry Function Description LCP Lz Ry Function Description LCD latch Lz lt data decoder lt Ry The working register contents specified by Ry are loaded to the LCD latch specified by Lz through the data decoder Lz 00 Ry 0 7H LCD latch Lz lt data decoder lt Ry The working register contents specified by Ry are loaded to the LCD latch specified by Lz through the data decoder If the content of Ry is O the output of the data decoder will consist entirely of O s Lz 00 Ry 0 7H LCD latch Lz Ry AC The working register contents specified by Ry and the contents of AC are loaded to the LCD latch specified by Lz Lz 00 3FH Ry 0 7H 106 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual Table 4 2 The mapping table of LCD latches with the contents of AC and Ry _ DBUSA DBUSB DBUSC DBUSD DBUSE DBUSF DBUSG DBUSH LCD Lz HL Function Description LCT Lz HL Function Description LCB Lz HL Function Description LCP Lz HL Function Description LCDX D Function Description LCD latch Lz lt TAB HL HL indicates an index address of table ROM The contents of table ROM specified by HL are loaded to the LCD latch specified by Lz di
106. ecified by a fix address in the program memory ROM is called The following table shows the flag and service of each interrupt Table 3 1 1 Interrupt information Interrupt INT pin IOC or TMR1 Pre TMR2 Key RFC source IOD port junderflow divider matrix counter overflow junderflow Scanning overflow vector Interrupt IEF2 IEFO IEF 1 IEF3 IEFA IEF5 IEF6 enable flag priority Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt request 2 0 1 3 4 5 6 flag 62 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual The following figure shows the Interrupt Control Circuit Interrupt 0 Specified signal change at Priority IOC or IOD port control circuit Interrupt 1 Timer TM underflow Interrupt Specified signal Interrupt 2 request change at INT pin signal Interrupt vector address generator Interrupt 3 Predivider overflow Interrupt 4 2 underflow Specified signal enable at Key Interrupt 5 matrix Scanning RFC counter Interrupt 6 overflow Interrupt accept signal SIE instruction Initial clear 63 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual 3 1 1 INTERRUPT REQUEST AND SERVICE ADDRESS 3 1 1 1 External interrupt factor The external interrupt factor involves the use of the INT pin IOC or IOD ports or Key matrix Scanning 1 Extern
107. ed column K1 K16 on the key matrix The specified column is defined by the setting of Xo X3 Xo 0000 activates the K1 column X3 7 Xo 0001 activates the K2 column X3 Xo 1110 activates the K15 column 110 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual SPK Rx Function Description Xo 1111 activates the K16 column X7X5X4 001 in this setting all of the matrix columns K1 K16 will be checked simultaneously in each scanning cycle Xo are not a factor X7Xs5X4 010 in this setting the key matrix scanning function will be disabled Xo are not a factor X7X5X4 10X in this setting each scanning cycle checks 8 specified columns on the key matrix The specified column is defined by the setting of 0 activates the K1 K8 columns simultaneously Xs 1 activates the K9 K16 columns simultaneously Xo are not a factor X7 X5X4 110 in this setting each scanning cycle checks four specified columns on the key matrix The specified columns are defined by the setting of X3 and X 4 00 activates the K1 K4 columns simultaneously X3X2 01 activates the K5 K8 columns simultaneously X3X2 10 activates the K9 K12 columns simultaneously X3X2 11 activates the K13 K16 columns simultaneously X1 Xo are not a factor X7X5X4 111 in this setting each scanning cycle checks two specified columns on the
108. enabled at the same time If the SCF1 has been set to 1 the halt release request flag 0 HRFO will be delivered In this case if the port IOC interrupt enable mode IEFO is provided the interrupt is accepted 82 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual Since no flip flop is available to hold the information of the signal at the input pins IOC1 to the input data at the port IOC must be read into the RAM immediately after the halt mode is released 3 5 4 IOD PORT IOD1 IOD4 pins are MUXed with SEG36 SEG37 SEG38 SEG39 pins respectively by mask option MASK OPTION table Mask Option name Selected item SEG36 IOD1 2 1001 SEG37 IOD2 2 IOD2 SEG38 IOD3 2 IOD3 SEG39 IOD4 2 IOD4 After the reset cycle the IOD port is set to input mode each bit of port can be set to input or output mode individually by executing SPD instructions Executing the OPD instruction outputs the contents of specified data memory locations to the pins set as output the other pins which are set as input will still remain the in the input mode Executing IPD instructions will store the signals applied to the IOD pins in the specified data memory locations When the IOD pins are set as output executing IPD instructions will save the data stored in the output latches in the specified data memory locations Before executing SPD instructions to define the IOD pins as out
109. equest to the next signal change at IOC IOD will be inhibited To release this mode the SCA instruction must be executed again Refer to 2 16 1 1 2 15 2 CONTROL REGISTER 2 CTL2 Control register 2 CTL2 consists of halt release enable flags 1 2 3 4 5 6 HEF1 2 3 4 5 6 and is set by SHE instruction The bit pattern of the control register CTL2 is shown below one HE Hes enable flag Enable the halt Enable the halt Enable the halt Halt release release caused by release caused by release caused by condition counter to be Key TMR2 underflow finished HRF6 Scanning HRF5 HRF4 ee m Dnm enable flag Enable the halt Enable the halt Enable the halt Halt release release caused by release caused by release caused by condition pre divider overflow INT pin HRF2 TM1 underflow HRF3 HRF1 When the halt release enable flag 6 HEF6 is set a finish signal from the 16 bit counter of RFC causes the halt mode to be released In the same manner when HEF1 to HEF4 are set to 1 the following conditions will cause the halt mode to be released respectively an underflow signal from TMR1 the signal change at the INT pin an overflow signal from the pre 54 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual divider and an underflow signal from TMR2 a H signal from OR ed output of KI1 4 latch signals When the stop release enable flag 5 SRF5 a
110. escription The contents of index RAM specified by HL are loaded to the LCD latch specified by Lz through the data decoder The range of multi Lz is specified by data D Refer to Table 4 3 D 0 3 LCPX D Function Mullti LCD latch Lz HL AC Description The contents of index RAM specified by HL and the contents of AC are loaded to several LCD latches Lz simultaneously Refer to Table 4 2 The range of multi Lz is specified by data D Refer to Table 4 3 D 0 3 SPA X Function Defines the input output mode of each pin for the IOA port and enables or disables the pull low device Description Sets the I O mode and turns the pull low device on or off The meaning of each bit of X X4 X3 2 X1 0 is shown below Bit pattern Bit pattern 4 1 Enable the pull low device X4 0 Disable the pull low on 1 4 device on simultaneously IOA1 1OA4 simultaneously 4 as output mode IOA4 as input mode X121 10 2 as output mode 2 as input mode as output mode as input mode X171 1 as output mode OA1 as input mode OPA Rx Function lt Rx Description The content of Rx is outputted to I OA port OPASRx D Function 1 2 Rx IOA3 D 4 lt pulse Description The content of Rx is outputted to the IOA port D is outputted to IOA3 and pulse is outputted to 4 D 00 1 108 tenx technology inc Rev 1 1 2007
111. executing this instruction HL indicates an index address of data memory The carry flag CF will be affected Rx AC Binary adds the contents of Rx and the result is loaded to AC The carry flag CF will be affected AC lt HL AC Binary adds the contents of HL and AC the result is loaded to AC HL indicates an index address of data memory The carry flag CF will be affected 118 tenx technology inc Rev 1 1 2007 06 28 Advance Information ADD HL Function Description ADD Rx Function Description ADD HL Function Description ADD Function Description SUB Rx Function Description SUB HL Function Description SUB OHL Function Description TM8726 User s Manual AC lt HL AC HL HL 1 Binary adds the contents of HL and AC the result is loaded to AC The content of the index register HL will be incremented automatically after executing this instruction HL indicates an index address of data memory The carry flag CF will be affected AC Rx lt Rx AC Binary adds the contents of Rx and AC the result is loaded to AC and the data memory Rx The carry flag CF will be affected AC HL lt HL AC Binary adds the contents of HL and AC the result is loaded to AC and the data memory HL HL indicates an index address of data memory The carry flag CF will be affected
112. ey scanning cycle the states of SKI1 4 will be latched and executing the IPC instruction could store these states into data RAM Executing the PLC 20h instruction clears the HRF5 flag Since the key matrix scanning function shares the timing of LCD waveform the scanning frequency corresponds to the LCD frame frequency and the LCD duty cycle The formula for the key matrix scanning frequency is shown below key matrix scanning frequency Hz LCD frame frequency x LCD duty cycle x 2 Note 2 is a factor For example if the LCD frame frequency is 32Hz and duty cycle is 1 5 duty the scanning frequency for the key matrix is 320Hz 32 x 5 x 2 94 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual L KI2 KI3 key scanning input amp latch key scanning input amp latch key scanning input amp latch key scanning input amp latch PLC 20h Initial Reset key scanning enable signal IPC Interrupt 5 request This figure shows the organization of Key matrix scanning input Example SPC Ofh Disables all the pull down devices on the internal IOC port Sets all of the IOC pins as the output mode SPKX 10h Generates HALT release request when a key is depressed Scanns every column simultaneously in each cycle PLC 20h Clears HRF5 SHE 20h Sets HEF5 HALT waits for the halt release
113. f Rx the result is loaded to AC and Rx The carry flag CF will be affected AC HL lt HL AC B 1 Binary subtracts the content of AC from the content of the result is loaded to and the data memory HL HL indicates an index address of data memory The carry flag CF will be affected AC HL lt HL AC B 1 HL HL 1 Binary subtracts the content of AC from the content of the result is loaded to AC and the data memory HL The content of the index register HL will be incremented automatically after executing this instruction HL indicates an index address of data memory The carry flag CF will be affected lt Rx AC Binary adds the contents of Rx and AC the result is loaded to AC result will not affect the carry flag CF AC lt HL AC Binary adds the contents of HL and AC the result is loaded to AC The result will not affect the carry flag CF HL indicates an index address of data memory AC lt HL AC HL HL 1 Binary adds the contents of HL and AC the result is loaded to AC The content of the index register HL will be incremented automatically after executing this instruction result will not affect the carry flag CF HL indicates an index address of data memory AC Rx lt Rx AC Binary adds the contents of Rx and AC the result is loaded to AC and data memory Rx The result will not a
114. ffect the carry flag CF 120 tenx technology inc Rev 1 1 2007 06 28 Advance Information ADN HL Function Description ADN Function Description AND Rx Function Description AND HL Function Description AND HL Function Description AND Rx Function Description AND HL Function Description Function Description TM8726 User s Manual AC HL lt HL AC Binary adds the contents of HL and AC the result is loaded to AC and the data memory HL The result will not affect the carry flag CF HL indicates an index address of data memory AC HL lt HL AC HL HL 1 Binary adds the contents of HL and AC the result is loaded to AC the data memory HL The content of the index register HL will be incremented automatically after executing this instruction The result will not affect the carry flag CF HL indicates an index address of data memory AC Rx amp AC Binary ANDs the contents of Rx and AC the result is loaded to AC AC lt HL amp AC Binary ANDs the contents of HL and AC the result is loaded to AC HL indicates an index address of data memory AC lt HL amp AC HL HL 1 Binary ANDs the contents of HL and AC the result is loaded to AC The content of the index register HL will be incremented automatically after executing this instruction HL indicates an inde
115. flag CF will be affected AC data before DAA CF data before DAA AC data after DAA CF data after DAA execution execution execution execution 0 lt lt 9 lt lt AC AC 6 0x AC x3 AC AC 6 DAS Function Description AC lt BCD AC Converts the content of AC to binary format and then restores to AC When this instruction is executed the AC must be the result of any subtracted instruction The carry flag CF will be affected 132 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual DAS Rx Function Description DAS HL Function Description DAS HL Function Description AC Rx BCD AC Converts the content of AC to binary format and then restores to AC and the data memory specified by Rx When this instruction is executed the AC must be the result of any subtracted instruction The carry flag CF will be affected lt BCD AC Converts the content of AC to binary format and then restores to AC and the data memory HL When this instruction is executed the AC must be the result of any subtracted instruction The carry flag CF will be affected AC HL lt BCD AC HL HL 1 Converts the content of AC to binary format and then restores to AC and the data memory HL The content of the index register HL will be incremented automatically after executing this instruction When this instruction
116. gnal L applied on 1 4 during scanning interval X671 The HEF6 is set so that the halt mode is released by RFC counter overflow Note X0 don t care SRE X Function Set Reset stop release enable flag Description SRF3 is set so that the stop mode is released by the signal changed IOD port SRF4 is set so that the stop mode is released by the signal changed on IOC port SRF5 is set so that the stop mode is released by the signal changed on INT pin X7 1 The is set so that the stop mode is released by the signal is L applied on 1 4 in scanning interval Note 2 0 are not a factor FAST Function Switches the system clock to CFOSC clock Description Starts up the CFOSC high speed osc and then switches the system clock to the high speed clock SLOW Function Switches the system clock to XTOSC clock low speed osc Description Switches the system clock to low speed clock and then stops the CFOSC 129 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual MSB Rx Function AC Rx lt SCF3 SCF2 BCF1 BCF Description The SCF1 SCF2 SCF3 and BCF flag contents are loaded to AC and the data memory specified by Rx The content of AC and the meaning of the bits after the execution of this instruction are as follows Bit 3 Bit 2 Bit 1 Bit 0 Start condition Start condition Start condition Backup flag flag 3 flag 2 flag 1 BCF
117. he TM8702 will enter stop mode The backup flag will be set to 1 automatically after the program enters stop mode normal mode 59 tenx technology inc Rev 1 1 2007 06 28 The following diagram shows the stop release procedure STOP HALT MODE STOP Yes released release Figure The stop release state machine HALT released decision Advance Information TM8726 User s Manual Before the stop instruction is executed the following operations must be completed Specify the stop release conditions through the SRE instruction Specify the halt release conditions corresponding to the stop release conditions if needed Specify the interrupt conditions corresponding to the stop release conditions if needed When stop mode is released by an interrupt request the TM8726 will enter the halt mode immediately While the interrupt is accepted the halt mode will be released by the interrupt request Stop mode returns by executing the RTS instruction after the completion of interrupt service After the stop release it is necessary that either the MSB or the MSC or the MCX instruction be executed to test the halt release signal Then the PLC instruction must be executed to reset the halt release signal Even when the stop instruction is executed in the state where the stop release signal SRF is delivered the CPU does not enter stop mode but instead enters halt mode When stop mode is released and an interru
118. he stack pointer will return to 0 and the contents of the level 0 stack will be overwritten by the PC value The contents of the stack register STACK are returned sequentially to the program counter PC when the RTS instruction is executed Once the RTS instruction causes a stack register STACK underflow the stack pointer will return to level 7 and the content of the level 7 stack will be restored to the program counter The following figure shows the diagram of the stack 35 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual Stack pointer CALL instruction Interru pi accepted RTS instruction STACK ring with first in last out function 2 7 DATA MEMORY RAM Static RAM is organized with 512 addresses x 4 bits and is used to store data The data memory may be accessed through two methods 1 Direct addressing mode The address of the data memory is specified by the instructions and the addressing range is from 00H to 7FH 2 Index addressing mode The index address register HL specifies the address of the data memory and all address space from OOH to 1FFH can be accessed 36 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual The 16 specified addresses 70H to 7FH in the direct addressing memory are also used as 16 working registers The function of working registers will be described in detail in section 2 6 A 00H 9 5
119. ied by the stack pointer Stack pointer stack pointer 1 Table 2 1 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PCO dniialreset 0 o wwen input port C or D timer 1 interrupt Interrupt 3 pre divider 1 1 1 interrupt Interrupt 4 timer 2 interrupt Interrupt 5 HUMUM Key Scanning LLLLLLLELL interrupt Interrupt 6 interrupt PTI 3839 7 P11 P8 P7 Pe P5 P4 P3 P2 P1 PO Subroutine P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 PO P10 to PO Low order 11 bits of instruction operand P11 page register 31 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual When executing subroutine call instructions or interrupt service routines the contents of the program counter PC are automatically saved to the stack register STACK 2 4 PROGRAM TABLE MEMORY The built in mask ROM is organized with 4096 x 16 bits There are 2 pages of memory space in this mask ROM Page 0 covers the address range from 000h to 7FFh and page 1 covers 800h to FFFh Page 0 000h Page 1 800h 7FFh FFFh Both instruction ROM PROM and table ROM TROM share this memory space The partition formula for PROM and TROM is
120. if AC 3 1 JNZ X 010 OXXX XXXX XXXX PC lt X 000h 7FFh 800h FFFh if AC 0 JNC x 010 1XXX XXXX XXXX PC lt X 000h 7FFh 800h FFFh if CF 0 JZ X 011 OXXX XXXX XXXX PC lt X 000h 7FFh 800h FFFh if AC 0 JC X 011 XXXX XXXX PC lt X 000h 7FFh 800h FFFh if CF 1 CALL PX 100 XXXX XXXX XXXX STACK lt PC 1 lt X 000h FFFh JMP 101 XXXX XXXX lt X 000h FFFh 5 Rx 110 0000 OXXX XXXX AC 3 2 11 Ctm FREQ Setting of Timer 1 AC 3 2 10 Ctm PH15 AC 3 2 01 Ctm PH3 AC 3 2 00 Ctm PH9 AC 1 0 Set Timer1 Value Rx 3 0 TMS HL 1110 0001 0000 0000 T HL 7 6 11 Ctm FREQ Setting of Timer 1 T HL 7 6 10 Ctm PH15 T HL 7 6 01 Ctm PH3 T HL 7 6 00 Ctm PHO T HL 5 0 Set 1 Value TMSX x 1110 001X XXXX XXXX X8 7 6 111 Ctm PH13 Setting of Timer 1 8 7 6 110 Ctm PH11 X8 7 6 101 Ctm PH7 X8 7 6 100 Ctm PH5 X8 7 6 011 Ctm FREQ X8 7 6 010 Ctm PH15 X8 7 6 001 Ctm PH3 X8 7 6 000 Ctm PH9 5 0 Set Timer1 Value TM2 Rx 1110 0100 OXXX XXXX AC 3 2 11 Ctm FREQ Setting of Timer 2 AC 3 2 10 Ctm PH15 AC 3 2 01 Ctm PH3 AC 3 2 00 Ctm PH9 AC 1 0 Set Timer1 Value Rx 3 0 TM2 HL 1110 0101 0000 0000 T HL 7 6 11 Ctm FREQ Setting of Timer 2 T HL 7 6 10 Ctm PH15 T HL 7 6 01 Ctm PH3 T HL 7 6 00 Ctm PHO T HL 5 0 Set Timer1 Value TM2X X 1110
121. ill depend on the frequency of oscillation ALLOWABLE OPERATING CONDITIONS at Ta 20 C to 70 C GND 0V Name Symb Condition Min Max Unit Supply Voltage VDD1 1 2 5 25 V VDD2 2 4 5 25 V VDD3 24 8 0 V VDD4 2 4 8 0 V Oscillator Start Up Voltage VDDB Crystal Mode 1 3 V Oscillator Sustain Voltage VDDB Crystal Mode 1 2 V Supply Voltage VDD1 Ag Mode 1 2 1 65 V Supply Voltage VDD2 EXT V Li Mode 24 5 25 V Input H Voltage Vih1 Ag Battery Mode VDD1 0 7 VDD1 0 7 V Input L Voltage Vil 0 7 0 7 V Input H Voltage Vih2 Li Battery Mode VDD2 0 7 VDD2 0 7 V tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual Name Symb Condition Min Max Unit Input L Voltage Vil2 0 7 0 7 V Input H Voltage Vih3 OSCIN at Ag Battery 0 8xVDD1 VDD1 V Input L Voltage Mode 0 0 2xVDD1 V Input H Voltage Vih4 OSCIN at Li Battery 0 8xVDD2 VDD2 V Input L Voltage Vil4 0 0 2xVDD2 V Input H Voltage Vih5 CFIN at Li Battery or EXT 0 8xVDD2 VDD2 V Input L Voltage Vil5 V Mode 0 0 2xVDD2 V Input H Voltage Vih6 RC Mode 0 8xVDDO VDDO V Input L Voltage Vil6 0 0 2xVDDO V Operating Freq 1 Crystal M
122. information on the backup flag refer to 3 5 2 1 1 3 1 3 BIAS AT Ag BATTERY POWER SUPPLY MASK OPTION table CUPO CUP1 m CUP2 0 1u zz VDD4 VDD2 VDD3 __ _ Internal VDD1 BAK 0 1 logic GND 2 15V Mask Option name Selected item POWER SOURCE 3 1 5V BATTERY BIAS 3 1 3 BIAS Note 1 The input output ports operate between GND and VDD1 Note 2 The backup flag BCF is set in the initial clear mode When the backup flag is set the oscillator circuit uses a larger driving force to operate and the oscillation conditions are improved but the operating current is also increased Therefore the backup flag should be reset unless otherwise required For information on the backup flag refer to 3 5 14 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual 2 1 1 4 1 4 BIAS AT Ag BATTERY POWER SUPPLY It is recommanded that the option LCD reset OFF is not used in this power mode as the LCD segments cannot be turned off completely in the RESET cycle MASK OPTION table Mask Option name Selected item POWER SOURCE 3 1 5V BATTERY BIAS 4 1 4 BIAS Note 1 The input output ports operate between GND and VDD1 Note 2 The backup flag BCF is set in the initial clear mode
123. ing timing of TMR2 re load function for RFC 46 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual 2 14 STATUS REGISTER STS The status register STS is organized with 4 bits and comes in 4 types status register 1 STS1 to status register 4 STS4 The following figure shows the configuration of the start condition flags for 8726 Chattering prevention PLCO IEFO SIE LE SCF1 1h HRFO interrupt SEF4 SCA 10h Initial reset Chattering Interrupt accept 3 output of 10D SEF3 SCF3 IEF1 SCF2 SCA 8h SIE 2h Timer1 underflow 1 gt SCF5 Interrupt 1 HEF1 SHE2h ES III Signal SIE 4h Interrupt 2 changed ANA PSS aeea 7 on INT pin N SCF 4 HEF 2 SHE 4h od MER an Interrupt 3 Predivid 0 Jl SHE 8h L IEF4 SIE 10h Interrupt 4 Timer2 HRF4 underflow N SCF 6 HEF 4 SHE 10h IEF5 SIE 20h Interrupt 5 Key Scanning overflow HRES a N SCF7 B HEF5 SHE 20h IEFG gt s M SIE 40h J Interrupt 6 counter HRF6 SCF 9 overflow HEF 6 J SHE 40h 47 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual 2 14 1 STATUS REGISTER 1 STS1 Status register 1 STS1 consists of 2 flags 1 Carry flag CF The carry flag is used to save the re
124. instructions _ DBUSA DBUSB DBUSC DBUSD DBUSE DBUSF DBUSG DBUSH Ei T HL1 m n T HL4 T HL5 T HL6 T HL7 T HL2 8 SF2 4h Turns off the LCD display 9 RF2 4h Turns on the LCD display 4 3 3 CONCRETE EXPLANATION Each LCD driver output corresponds to the LCD 1 9 duty panel has 9 latches refer to Figure Sample Organization of Segment PLA Option Since the latch input and the signal to be applied to the clock strobe are selected with the segment PLA the combination of segments in the LCD driver outputs is flexible In other words one of the data decoder outputs from DBUSA to DBUSH is applied to the latch input L and one of the PSTBO to PSTB3Fh outputs is applied to clock CLK TM8726 provide a flash type instruction to update the LCD pattern When the LCTX D LCBX D LCPX D and LCDX D instructions are executed the pattern of DBUS will be outputted to the16 latches Lz specified by D simultaneously Lz 00h OFh Lz 10h 1Fh Lz 20h 2Fh Lz 30h 3Fh Refer to Chapter 5 for detailed description of these instructions 104 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual Mask option Mask option Mask option Mask option Mask option Mask option DBUSA LL m Yn n l e a N n LCD Driver Figure Sample Organization of Segment PLA Op
125. ion Li power option EXT V option BCF 1 Increased Increased Increased BCF 0 Initial Increased Increased Increased reset After Normal Normal Increased reset 2 2 1 2 External RC oscillator MASK OPTION table Mask Option name Selected item SLOW CLOCK TYPE FOR SLOW ONLY OR DUAL 2 RC 23 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual 2 2 2 CONNECTION DIAGRAM OF FAST CLOCK OSCILLATOR CF CLOCK The CF clock is a multiple type oscillator mask option which provides a faster clock source to system In single clock operation fast only this oscillator will provide the clock to the system clock generator pre divider timer port chattering prevention clock and LCD circuitry In dual clock operation CF clock provides the clock to the system clock generator only When the dual clock option is selected by mask option this oscillator will be inactive most of the time except when the FAST instruction is executed After the FAST instruction is executed the clock source BCLK of the system clock generator will be switched to CF clock and the clock source for other functions will continue to come from XT clock Halt mode stop mode or SLOW instruction execution will stop this oscillator after which the system clock BCLK will be switched to XT clock There are 3 types oscillators that can be used in the slow clock oscillator selected by mask option
126. is executed the AC must be the result of any subtracted instruction The carry flag CF will be affected data before DAS CF data before DAS AC data after DAS CF data after DAS execution execution execution execution 0 lt lt 9 6 lt AC lt F 5 8 JUMP INSTRUCTIONS JBO X Function Description JB1 X Function Description Program counter jumps to X in current page if ACO 1 If bitO of AC is 1 a jump occurs If O the PC increases by 1 The range of X is only 2K for one page Program counter jumps to X in current page if AC1 1 If bit of AC is 1 a jump occurs If O the PC increases by 1 The range of X is only 2K for one page 133 tenx technology inc Rev 1 1 2007 06 28 Advance Information JB2 X Function Description JB3 X Function Description JNZ X Function Description JNC X Function Description JZ X Function Description JC X Function Description JMP P X Function Description CALL P X Function Description TM8726 User s Manual Program counter jumps to X in current page if AC2 1 If bit2 of AC is 1 a jump occurs If 0 the PC increases by 1 The range of X is only 2K for one page Program counter jumps to X in current page if AC3 1 If bit3 of AC is 1 jump occurs If 0 the PC increases by 1 The range of X is only 2K for one page Program counter jumps to X in current page if
127. ive 369 LCD segments 1 2 Duty 1 3 Duty 1 4 Duty 1 5 Duty 1 6Duty 1 7Duty 1 8Duty or 1 9Duty can be selected by MASK option 1 2 Bias 1 3 Bias or 1 4 Bias can be selected by MASK option Single instruction to turn off all segments COM5 9 SEG1 41 can be defined as CMOS or P_open drain type output by mask option 5 Input output ports Port IOA 4 pins with internal pull low muxed with SEG24 SEG27 Port 4 pins with internal pull low muxed with SEG28 SEG31 Port 4 pins with internal pull low low level hold muxed with SEG32 SEG35 The IOC port has built in input signal chattering prevention circuitry Port lOD 4 pins with internal pull low muxed with SEG36 SEG39 The IOD port has builtin input signal chattering prevention circuitry 8 level subroutine nesting Interrupt function e External factors 4 INT pin Port IOC IOD amp KI input Internal factors 4 Pre Divider Timer1 Timer2 amp RFC 3 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual 8 Built in EL light driver ELC ELP Muxed with SEG28 SEG29 9 Built in Alarm clock or single tone melody generator e BZB BZ Muxed with SEG30 SEG31 10 Built in resistance to frequency converter RR RT RH Muxed with SEG24 SEG27 11 Built in key matrix scanning function e K1 K16 Shared with SEG1 SEG16 e 1 4 Muxed with SEG32 SEG35 12 Two 6 bi
128. k up table specified by HL is loaded to the data memory specified by Rx 126 tenx technology inc Rev 1 1 2007 06 28 Advance Information LDH Rx HL Function Description LDL Rx HL Function Description LDL Rx HL Function Description MRF1 Rx Function Description MRF2 Rx Function Description MRF3 Rx Function Description MRF4 Rx Function Description TM8726 User s Manual Rx AC lt TAB HL high nibble HL HL 1 The higher nibble data of the look up table specified by HL is loaded to the data memory specified by Rx and then is increased in HL Rx AC lt TAB HL low nibble The lower nibble data of the look up table specified by HL is loaded to the data memory specified by Rx Rx AC TAB HL low nibble HL HL 1 The lower nibble data of the look up table specified by HL is loaded to the data memory specified by Rx and then is increased in HL Rx lt RFC 3 0 Loads the lowest nibble data of the 16 bit counter of RFC to AC and the data memory specified by Rx Bit 3 RFC 3 Bit 2 RFC 2 Bit 1 RFC 1 Bit 0 RFC 0 Rx AC lt RFC 7 4 Loads the 274 nibble data of the 16 bit counter of RFC to AC and the data memory specified by Rx Bit 3 RFC 7 Bit 2 RFC 6 Bit 1 RFC 5 Bit 0 RFC 4 Rx AC lt RFC 11 8 Loads the 3 nibble data of the 16 bit counter of RFC to AC and th
129. le the RFC counter once the TMR2 underflows the TENX flag will be reset to 0 automatically In this case Timer 2 can set an accurate time period without setting a value error like the other operations of TMR1 and TMR2 Refer to 2 16 for detailed information on controlling the RFC counter The following figure shows the operating timing of TMR 2 in RFC mode Clock source of Timer 2 TM2X X A MEME Timer2 HRF4 1 7 TENX TMR2 also provides the re load function when controlling the RFC function The SF2 1h instruction enables the re load function and the DED flag should be set to 1 by SF2 2h instruction Once DED flag had been set to 1 TENX flag will not be cleared to 0 while 44 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual TMR2 underflows but HRF4 will be set to1 The DED flag must be cleared to 0 by executing RF2 2h instruction before the last HRF4 occurs thus the TENX flag will be reset to O after the last HRF4 flag delivery After the last underflow HRF4 of TMR2 occurs disable the re load function by executing the RF2 1h instruction For example if the target set value is 500 it will be divided as 52 7 64 1 2 3 4 5 6 Set the initiate value of TMR2 to 52 and start counting Enable the TMR2 halt release or interrupt function Before the first underflow occurs enable the re load function and set the DED flag The TMR2 will continue coun
130. logy inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual 5 4 LOAD STORE INSTRUCTIONS STA Rx Function Description STA Function Description STA HL Function Description LDS Rx D Function Description LDA Rx Function Description LDA HL Function Description LDA HL Function Description LDH Rx HL Function Description Rx lt The content of AC is loaded to the data memory specified by Rx HL AC The content of AC is loaded to the data memory specified by HL HL indicates an index address of data memory HL AC HL HL 1 The content of AC is loaded to the data memory specified by HL The content of the index register HL will be incremented automatically after executing this instruction HL indicates an index address of data memory AC Rx lt D Immediate data D is loaded to the AC and the data memory specified by Rx D 0H FH lt Rx The content of Rx is loaded to AC AC lt HL The content specified by HL is loaded to AC HL indicates an index address of data memory AC lt HL HL HL 1 The content specified by HL is loaded to AC The content of the index register HL will be incremented automatically after executing this instruction HL indicates an index address of data memory Rx AC TAB HL high nibble The higher nibble data of the loo
131. lt release signal is reset automatically 2 The signal change specified by the SCA instruction is applied to port IOC SCF 1 or IOD SCF3 3 The halt release condition specified by the SHE instruction is met HRF1 HRF6 When the halt mode is released in either 2 or 3 it is necessary that either the MSB or the MSC or the MCX instruction is executed in order to test the halt release signal It is also necessary to execute the PLC instruction to reset the halt release signal HRF Even when the halt instruction is executed in the state where the halt release signal is delivered the CPU does not enter the halt mode 57 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual 2 17 HEAVY LOAD FUNCTION When heavy loading lamp light up motor start etc causes a temporary voltage drop in supply voltage the heavy loading function set 1 prevents TM8726 from malfunctioning especially where a battery with high internal impedance such as Li battery or alkali battery is used During back up mode the 32 768KHz Crystal oscillator will add an extra buffer in parallel and switch the internal power BAK from VDD1 to VDD2 Li power option only In this condition all of the functions in TM8726 will work under the VDD voltage range causing TM8726 to get better noise immunity To shorten the start up time of 32 768KHz Crystal oscillator TM8726 will set the BCF to 1 during the reset cycle and
132. m LCD ACTIVE TYPE 1 LCD When more than one of SEG or COM pins had been used for DC output port Mask Option name Selected item LCD ACTIVE TYPE 2 O P During the initial reset cycle the LCD lighting system may be lit or extinguished by mask option All of the LCD output will remain in the initial setting until instructions relative to the LCD are executed to change the output data MASK OPTION table Mask Option name Selected item LCD DISPLAY IN RESET CYCLE 1 ON LCD DISPLAY IN RESET CYCLE 2 OFF 4 1 LCD LIGHTING SYSTEM IN TM8726 There are several LCD lighting systems that can be selected by mask option in TM8726 they are 1 2 bias 1 2 duty 1 2 bias 1 3 duty 1 2 bias 1 4 duty 1 2bias 1 5duty 1 2bias 1 6duty 1 2bias 1 7duty 1 2bias 1 8duty 1 2bias 1 9duty 1 3 bias 1 3 duty 1 3 bias 1 4 duty 1 3 bias 1 5duty 1 3 bias 1 6duty 1 3 bias 1 7duty 1 3 bias 1 8duty 1 3 bias 1 9duty 1 4 bias 1 3 duty 1 4 bias 1 4 duty 1 4 bias 1 5duty 1 4 bias 1 6duty 1 4 bias 1 7duty 1 4 bias 1 8duty 1 4 bias 1 9duty All of these lighting systems are combined with 2 kinds of mask options one is LCD DUTY CYCLE and the other is BIAS MASK OPTION table LCD duty cycle option Mask Option Name Selected Item LCD DUTY CYCLE 1 LCD DUTY CYCLE 2 DUPLEX note 1 2 duty LCD DUTY CYCLE 3 1 3 DUTY LCD DUTY CYCLE 4 1 4 DUTY LCD DUTY CYCLE 6 1 6 DUT
133. m the PHO Refer to clock BCLK section 3 3 4 for 0 X4 X3 01 Chattering prevention X4 X3 10 2 1 0 001 clock of IOD port PHO 2 1 0 001 of IOC port PHO KIKO 2 1 0 010 clock of IOD port PH8 2 1 0 010 of IOC port PH8 OXI NOI 2 1 0 100 clock of IOD port PH6 X2 X1 X0 100 of IOC port PH6 X5 is reserved FRQ D Rx Function Frequency generator lt D Rx Description Loads the content of AC and the data memory specified by Rx and D D1 DO to the frequency generator to set the duty cycle and initial value The following table shows the preset data and the duty cycle setting 1 Thebit pattern of preset letter N Preset Letter D Duty Cycle DO x O 0 ty 0 11 aquy L1 ty D1 135 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual FRQ HL Function Frequency generator lt D T HL Description Loads the content of Table ROM specified by HL and D D1 DO to the frequency generator to set the duty cycle and initial value The following table shows the preset data and the duty cycle setting The bit pattern of preset letter N MERE Programming Bit7 Bit Bit5 Bit4 Bit3 Bit2 Bit1 divider T7 T6 15 T4 T3 T2 T1 TO Note TO T7 represents the data of table ROM Preset eted S D SS
134. mer 2 Description The data specified by X X8 X0 is loaded to timer 2 to start the timer The following table shows the bit pattern for this instruction OPCODE Select clock Presetting value of timer 2 TM2X X 138 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual SF X Function Description RF X Function Description SF2 X Function Description RF2 X Function Description The clock source selection for timer 2 PH5 x P PH11 PH13 Sets flag Description of each flag 1 The CF flag is set to 1 X1 1 The chip enters backup mode and the BCF flag is set to 1 X2 1 The EL panel driver output pin is active 1 For X271 when the SF instruction is executed at X371 the EL panel driver is active and the halt request signal is outputted The program then enters halt mode similar to HALT instruction X4 1 The watchdog timer is initiated and active and WDF flag is to 1 XT 1 Enables the re load function of timer 1 X6 5 is reserved Resets flag Description of each flag 1 The CF flag is reset to 0 X1 1 The chip escapes from backup mode and BCF flag is reset to O X2 1 The EL light driver is made inactive X4 1 The watchdog timer is disabled and WDF flag is reset to O XT 1 Disables the re load function of timer 1 X6 5 and 3 are reserved Sets flag Description of each flag
135. nable all interrupt requests a us all interrupts are requested simultaneously An interrupt caused by the predivider overflow occurs and interrupt service is concluded SIE 77h Enable the interrupt request except the predivider An interrupt caused by TM1 underflow occurs and interrupt service is concluded SIE 75h Enable the interrupt request except the predivider and TMR1 An interrupt caused by TM2 underflow occurs and interrupt service is concluded SIE 65h Enable the interrupt request except the predivider TMR1 and TMR2 An interrupt caused by RFC counter overflow occurs and interrupt service is concluded SIE 25h Enable the interrupt request except the predivider TMR1 T MR2 and the RFC counter interrupt is caused by IOC port and interrupt service is concluded SIE 24h Enable the interrupt request except the predivider TMR1 TMR2 counter and IOC port An interrupt is caused by the INT pin and interrupt service is concluded SIE 20h Enable the interrupt request except the predivider TMR1 TMR2 RFC counter IOC port and INT An interrupt is caused by Key matrix Scanning and interrupt service is concluded All interrupt requests have been processed 65 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual 3 1 3 INTERRUPT SERVICING When an interrupt is enabled the program in execution is suspended and the instruction
136. nd the HEF2 are set the signal change at the INT pin can cause the stop mode to be released When the stop release enable flag 7 SRF7 and the HEF5 are set the H signal from OR ed output 1 4 latch signals can cause the stop mode to be released 2 15 3 CONTROL REGISTER 3 CTL3 Control register 3 CTL3 is organized with 7 bits of interrupt enable flags IEF to enable disable interrupts The interrupt enable flag IEF is set reset by the SIE instruction The bit pattern of control register 3 CTL3 is shown below Interrupt enable flag IEF6 IEF5 IEF4 Enable the interrupt request Enable the interrupt request Enable the interrupt request Interrupt request flag caused by RFC counter to be caused by Key Scanning caused by TMR2 underflow finished HRF6 HRF5 HRF4 Interrupt flag Interrupt 6 Interrupt 4 Interrupt 4 Interrupt enable flag IEF3 IEF2 IEF1 Enable the interrupt request Enable the interrupt request Enable the interrupt request Interrupt request flag caused by poa overflow caused by TM1 underflow caused by INT pin HRF2 Interrupt flag mem 3 Interrupt 2 Interrupt 1 Interrupt enable flag IEFO 24 1 Enable the interrupt request Interrupt request flag caused by IOC or IOD port signal to be changed HRFO Interrupt flag Interrupt 0 When any of the interrupts are accepted the corresponding HRFx and the interrupt enable flag IEF will be reset to 0 automatically Therefore the desirable interrupt
137. nning X7 5 4 000 Set one of KO1 16 1 by X7 5 4 001 X3 0 X7 5 4 010 Set all 1 X7 5 4 10X Set all Hi z Set eight of KO1 16 1 by X3 X3 0 gt KO1 8 X7 5 4 110 X3 1 gt KO9 16 Set four of KO1 16 1 by X3 2 X3 2 00 gt KO1 4 X3 2 01 gt KO5 8 X3 2 10 gt KO9 12 7 5 4 111 3 2 11 gt 13 16 Set two of KO1 16 1 by X3 2 1 X3 1 000 gt KO1 2 3 1 001 gt 4 3 1 010 gt 5 6 3 1 011 gt 7 8 X3 1 100 gt KO9 10 X3 1 101 gt KO11 12 X3 1 110 gt KO13 14 X3 1 111 gt KO15 16 SPK Rx 1111 0000 OXXX XXXX 2 1 KEY S release by scanning cycle 2 0 KEY S release by normal key scanning 7 5 4 000 Set one of KO1 16 1 by Rx 8 0 AC 7 5 4 001 Set all 1 7 5 4 010 Set all Hi z AC 7 5 4 10X Set eight of KO1 16 1 by Rx 3 145 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual Instruction Machine Code Function Flag Remark Rx 3 0 gt KO1 8 AC 7 5 4 110 Rx 3 1 gt KO9 16 Set four of KO1 16 1 by Rx 3 2 Rx 3 2 00 gt KO1 4 Rx 3 2 01 gt KO5 8 Rx 3 2 10 gt KO9 12 AC 7 5 4 111 Rx 3 2 11 gt KO13 16 Set two of KO1 16 1 by X3 2 1 Rx 3 1 000 gt KO1 2 Rx 3 1 001 gt KO3 4 Rx 3 1 010 gt KO5 6 Rx 3 1 011 gt KO7 8 Rx 3 1 100 gt KO9 10 Rx 3 1 101 gt KO11 12 Rx 3 1 110 gt KO13 14 Rx 3 1 111 gt KO15 16 SPK
138. ns on the key matrix The specified column is defined by the setting of X3 0 activates K1 K8 columns simultaneously 1 activates K9 K16 columns simultaneously X Xo don t care X7 X5X4 110 in this setting each scanning cycle checks four specified columns on key matrix The specified columns are defined by the setting of X3 and X X3X2 00 activates K1 K4 columns simultaneously X3X 01 activates K5 K8 columns simultaneously X3X2 10 activates K9 K12 columns simultaneously X3X2 11 activates K13 K16 columns simultaneously X4 Xo don t care X7X5X4 111 in this setting each scanning cycle checks two specified columns on key matrix The specified columns are defined by the setting of and X1 X3X2X1 000 activates K1 K2 columns simultaneously X3X2X1 001 activates K3 K4 columns simultaneously X3X2X1 110 activates K13 K14 columns simultaneously X3X2X1 111 activates 15 K16 columns simultaneously Xo is not a factor When Kl1 4 is defined for the Key matrix scanning input by mask option it is necessary to execute the SPC instruction to set the internal unused IOC port to output mode before the key matrix scanning function is activated Fig 2 27 shows the organization of the Key matrix scanning input port Each one of the SKI1 4 changed to High will set HRF5 to 1 If HEF5 has been set to 1 beforehand this will cause SCF7 to be set as well as releasing the HALT mode After the k
139. o pump voltage to the EL plant the ELC pin will output the pulse to discharge the EL plant The EL plant driver will not operate until the light control signal LIT is enabled Once the light control signal LIT is enabled the ELC pin will output a 85 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual pulse to discharge the capacitor before the pumping clocks output to ELP pin This will insure that there is no residual voltage that may cause damage while the first pumping clock is applied When the light control signal LIT is disabled the ELC pin will output a pulse to discharge the EL plant after the last pumping clock Diod e ELP A ELC A This figure shows the application circuit of EL plant EL plant LIT ELP ELC This figure shows the output waveform of EL plant driver Executing ELC instructions can change the ELP ELC pulse frequency and the duty cycle When the ELC pin outputs the discharge pulse the clock on the ELP pin will be inhibited For ELP setting X8 X7 X6 Pumping clock frequency X9 X5 X4 Duty cycle P MB 3 4 duty BCLK 2 3 duty BCLK 2 1 2 duty BCLK 4 1 1 duty original BCLK 8 1 3 duty Eoo 000 1 4 duty Note X represents don t care For ELC setting X3 X2 Discharge pulse frequenc X1 X0 8 X PH8 00 2 1 4 duty NE 1 2 duty 1 1 dut 86 tenx technology inc Rev 1 1 2007 06 28 A
140. o the number of latch circuits incorporated in the hardware signals can be selected by programming the aforementioned segment PLA Table 2 7 shows the PSTB Oh to PSTB 3Fh signals 102 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual Table 2 3 Strobe Signal for LCD Latch in Segment PLA and Strobe in LCT Instruction strobe signal for Strobe in LCT LCB LCP LCD LCD latch instructions The values of Lz in LCT Lz Q PSTBO PSTB1 PSTB2 5 PSTB4 PSTB5 PSTB3Ah 3AH PSTB3Bh 3BH PSTB3Ch 3CH PSTB3Dh 3DH PSTB3Eh 3EH PSTB3Fh Note The values of Q are the addresses of the working register in the data memory RAM In the LCD instruction Q is the index address in the table ROM The LCD outputs can be turned off without changing segment data The execution of the SF2 4h instruction may turn off the displays simultaneously The execution of the RF2 4h instruction may turn on the display with the patterns turned off These two instructions will not affect the data stored in the latch circuitry When executing the RF2 4h instruction to turn off the LCD the program can still execute LCT LCB LCP and LCD instructions to update the data in the latch circuitry The new content will be outputted to the LCD while the display is being turned on again In the stop state all COM and SEG outputs of LCD drivers will automatically switch to the GND state to avoid DC voltage bias on the LCD panel 4 3
141. ock CF clock Initial state dual clock XT clock XT clock option Halt mode dual clock option XT clock XT clock Slow mode dual clock XT clock XT clock option Fast mode dual clock XT clock CF clock option 2 2 1 CONNECTION DIAGRAM OF SLOW CLOCK OSCILLATOR XT CLOCK This clock oscillation circuitry provides the lower speed clock to the system clock generator pre divider timer chattering prevention of IO port and LCD circuitry This oscillator will be disabled when the fast clock only option is selected by mask option otherwise it will be active all the time after the initial reset In stop mode the oscillator will be stopped There are 2 types oscillators which can be used in slow clock oscillators select with the mask option 22 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual 2 2 1 1 External 32 768KHz Crystal oscillator MASK OPTION table Mask Option name Selected item SLOW CLOCK TYPE FOR SLOW ONLY OR DUAL 1 X tal 15pf XOUT T 4 5pf XIN Ld ie 32768Hz Crystal 1 When backup flag BCF is set to 1 the oscillator operates with an extra buffer in parallel in order to shorten the oscillator start up time This increases the power consumption Therefore the backup flag should be reset unless otherwise required The following table shows the power consumption of Crystal oscillator under different conditions Ag power opt
142. ode 32 KHZ Fopg2 RC Mode 10 1000 KHZ Fopg3 CF Mode 1000 3580 KHz INTERNAL RC FREQUENCY RANGE Option Mode BAK Min Typ Max 250KHz 1 5V 200KHz 300KHz 400KHz 3 0V 200KHz 250KHz 300KHz 500KHz 1 5V 450KHz 600KHz 750KHz 3 0V 400KHz 500KHz 600KHz ELECTRICAL CHARACTERISTICS at 1 VDD1 1 2V Ag at 2 VDD2 2 4V Li at 3 VDD2 4V Ext V Input Resistance Name Symb Condition Typ Unit L Level Hold RIh1 Vi 0 2VDD1 1 10 40 100 Kohm Tr IOC Rilh2 Vi 0 2VDD2 2 10 40 100 Rilh3 Vi 0 2VDD2 3 5 20 50 Kohm IOC Pull Down Tr Rmad1 Vi VDD1 1 200 500 1000 Kohm Rmad2 Vi VDD2 2 200 500 1000 Kohm Rmad3 Vi VDD2 3 100 250 500 Kohm INT Pull up Tr Rintu1 Vi VDD1 1 200 500 1000 Kohm Rintu2 Vi VDD2 2 200 500 1000 Kohm Rintu3 Vi VDD2 3 100 250 500 Kohm INT Pull Down Tr Rintd1 Vi GND 1 200 500 1000 Kohm Rintd2 Vi GND 2 200 500 1000 Kohm Rintd3 Vi GND 3 100 250 500 Kohm RES Pull Down R Rres1 Vi GND or 10 40 100 Kohm VDD1 1 Rres2 Vi GND or 10 40 100 Kohm VDD2 2 Rres3 Vi GND or 10 40 100 Kohm VDD2 3 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual DC Output Characteristics Name Symb Condition Port Min Typ Max Unit Voh1c 2000 1 0 8 0 9 1 0 V Output H Voh2c loh 1mA 2 COM5 9 1 5 1 8 2 1 V Voltage Voh3c jloh 3mA 3 SEG1 41 2 5
143. of the predivider 15 bits are reset When executing this instruction X3 must be set to 1 simultaneously 140 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual Appendix A TM8726 Instruction Table Instruction Machine Code Function Flag Remark No Operation 7SEG Ry Ry 70H 77H TSEG Ry Blank Zero lt Ry AC lt R HL 78 R HL 78 RGHL Blank Zero lt RGHL AC T HL Multi Lz 00H OFH Multi Lz 10H 1FH Multi Lz 20H 2FH Multi Lz 30H 3FH 78 lt R HL Multi Lz 00H 0FH Multi Lz 10H 1FH Multi Lz 20H 2FH Multi Lz 30H 3FH LCBX D 0000 100D D000 0110 Multi Lz lt 7SEG lt R HL Blank Zero D 00 Multi Lzz00H 0FH D 01 Multi Lz 10H 1FH D 10 Multi Lz 20H 2FH D 11 Multi Lz 30H 3FH LCPX D 0000 100D D000 0111 Multi Lz lt R HL D 00 Multi Lz 00H OFH D 01 Multi Lz 10H 1FH D 10 Multi Lz 20H 2FH D 11 Multi Lz 30H 3FH OPA Rx 0000 1010 OXXX XXXX lt Rx OPAS Rx D 0000 1011 DXXX XXXX 10A1 2 3 4 lt Rx 0 Rx 1 D Pulse OPB Rx 0000 1100 OXXX XXXX IOB lt Rx OPC Rx 0000 1101 OXXX XXXX IOC lt Rx OPD Rx 0000 1110 OXXX XXXX IOD lt Rx FRQ D Rx 0001 00 OXXX XXXX FREQ lt Rx AC D 00 1 4 Duty D 01 1 3 Duty D 10
144. ogy inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual 2 13 1 NORMAL OPERATION TMR2 consists of a programmable 6 bit binary down counter which is loaded and enabled by executing either the TM2 or the TM2X instructions Once TMR2 counts down to 3Fh it stops counting then generates an underflow signal and sets the halt release request flag 4 HRF4 to 1 When HRF4 1 and the TMR2 interrupt enabler IEF4 is set to 1 the interrupt occurred When HRF4 1 IEF4 0 and the TMR2 halt release enabler HEF4 is set to 1 the program will escape from halt mode if CPU is in halt mode and HRF4 sets the start condition flag 6 SCF6 to 1 in the status register 4 STS4 After power on reset the default clock source of TMR2 is PH7 If watchdog reset occurs the clock source of TMR2 will remain the same The following table shows the definition of each bit in TMR2 instructions OPCODE Select clock TM2X X TM2Rx 0 AC3 AC2 AC1 ACO Rx3 Rx2 Rx1 Rx0 2 0 bit7 bit6 bits bit2 bito The following table shows the clock source setting for TMR2 L90 9 0 Pj 0 0 1 Eee ee PE L0 1 1 FREQ 1 0 0 PHS Alojai PH 1 1 0 PHM Notes 1 When the TMR2 clock is PH3 TMR2 set time Set value error 8 1 fosc KHz ms 2 When the TMR2 clock is PH9 TMR2 set time Set value error 512 1 fosc KHz ms 3
145. ollowing table shows the bit pattern for this instruction Select clock Presetting value of timer 1 ee PH Output of frequency generator FREQ TMSX X Function Selects the timer 1 clock source and preset timer 1 Description The data specified by X X7 is loaded to timer 1 to start the timer The following table shows the bit pattern for this instruction The clock source selection for timer 1 137 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual TM2 Rx Function Selects the timer 2 clock source and preset timer 2 Description The content of data memory specified by Rx and AC is loaded to timer 2 to start the timer The following table shows the bit pattern for this instruction OPCODE Select clock Presetting value of timer 2 TM2 Rx The clock source selection for timer 2 010 X QPH9 2 1 O PH15 1 Output of frequency generator FREQ 2 HL Function Selects the timer 2 clock source and preset timer 2 Description The content of the Table ROM specified by HL is loaded to timer 2 to start the timer The following table shows the bit pattern for this instruction OPCODE Select clock Presetting value of timer 2 TM2 HL Bit3 The clock source selection for timer 2 Bit6 clock source D O P Output of frequency generator FREQ TM2X X Function Selects the timer 2 clock source and preset ti
146. on Description SUBI Ry D Function Description ADNI Ry D Function Description TM8726 User s Manual AC Ry lt Ry D CF D represents the immediate data Binary subtracts the CF and immediate data D from the working register Ry the result is loaded to AC and the working register Ry The carry flag CF will be affected D 0H FH AC Ry D D represents the immediate data Binary ADDs the contents of Ry and D the result is loaded to AC The carry flag CF will be affected D 0H FH AC Ry Ry D D represents the immediate data Binary ADDs the contents of Ry and D the result is loaded to AC and the working register Ry The carry flag CF will be affected D 0H FH AC Ry D 1 D represents the immediate data Binary subtracts the immediate data D from the working register Ry the result is loaded to AC The carry flag CF will be affected D 0H FH AC Ry lt Ry Y 1 D represents the immediate data Binary subtracts the immediate data D from the working register Ry the result is loaded to AC and the working register Ry The carry flag CF will be affected D 0H FH AC lt Ry D D represents the immediate data Binary ADDs the contents of Ry and D the result is loaded to AC The result will not affect the carry flag CF D 0H FH 124 tenx technology inc Rev 1 1 2007 06 28 Advance Information A
147. ory HL and AC The content of the index register HL will be incremented automatically after executing this instruction The carry flag CF will be affected HL indicates an index address of data memory Rx AC lt Rx 1 Substrates 1 from the content of Rx the result is loaded to the data memory Rx and AC carry flag CF will be affected R HL lt R HL 1 Substrates 1 from the content of HL the result is loaded to the data memory HL and AC The carry flag CF will be affected e HL indicates an index address of data memory R HL lt R HL 1 HL HL 1 Substrates 1 from the content of HL the result is loaded to the data memory HL and AC The content of the index register HL will be incremented automatically after executing this instruction The carry flag CF will be affected OHL indicates an index address of data memory 116 tenx technology inc Rev 1 1 2007 06 28 Advance Information ADC Rx Function Description ADC HL Function Description ADC HL Function Description ADC Rx Function Description ADC HL Function Description ADC Function Description SBC Rx Function Description TM8726 User s Manual lt Rx AC CF Binary adds the contents of Rx AC and CF the result is loaded to AC The carry flag CF will be affected AC lt HL AC CF Binary adds the contents of
148. ounter are loaded to data memory specified by Rx and AC The content of AC and the meaning of the bit after the execution of this instruction are as follows Bit 3 Bit 2 Bit 1 Bit 0 Reserved The overflow flag Watchdog timer System clock of 16 bit counter of enable flag WDF selection flag RFC RFVOF CSF 5 6 INDEX ADDRESS INSTRUCTIONS MVU Rx Function QU Rx AC Description Loads the content of Rx to the index address buffer QU U3 Rx 3 U2 Rx 2 U1 Rx 1 UO2 RX O MVH Rx Function H lt Rx AC Description Loads the content of Rx to the index address buffer H H3 Rx 3 H2 Rx 2 H1 Rx 1 HO Rx O MVL Rx Function lt Rx Description Loads the content of Rx to the index address buffer L L3 Rx 3 L2 Rx 2 L1 Rx 1 LO Rx O CPHL X Function If HL X force the next instruction as NOP Description Compare the content of the index register HL in lower 8 bits H and L with the immediate data X Note In the duration of the comparison of the index address all the interrupt enable flags IEF have to be cleared to avoid malfunction If the compared result is equal the next executed instruction that is behind the CPHL instruction will be forced as NOP If the compared result is not equal the next executed instruction that is behind CPHL instruction will operate normally The comparison bit pattern is shown below CPHL X X7 6 5 X4 X3 X2 X1 XO HL IDBF7 ID
149. period with which to count the clock numbers on the CX pin For a detailed description of the operation of TMR2 please refer to 2 12 Each time the automatically SRF con trol Counter active Timer 2 Content of the counter Halt release request Example In this example use the RT network to generate the clock source SRF SHE TM2X HALT PLC MRF1 MRF2 MRF3 MRF4 1Ah 10h 20h 10h 10h 11h 12h 13h 16 bit counter is enabled the content of the counter will be cleared SRF 18h SRF 02h I 19h X 18h X Oh 3Fh X1X2X 3 X NX t counter starts Counting stops caused to count by the Timer 2 underflow This figure shows the timing of the RFC counter controlled by timer 2 builds up the RT network and enables the counter controlled by TM2 enables the halt release caused by TM2 sets the as the clock source of TM2 and the down count value as 20h Clears the halt release request flag of TM2 reads the content of the counter 91 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual 3 8 4 Enabling Disabling the Counter by CX Signal This is another use for the 16 bit counter In previous modes CX is the clock source of the counter and the program must either specify a time period by timer or subroutine to control the counter In this mode howe
150. pt is accepted the halt release signal HRF is reset automatically 2 19 BACK UP FUNCTION TM8726 provides a back up mode to avoid system malfunction when heavy loading occurs such as buzzer activation LED illumination etc Since heavy loading will cause a large voltage drop in the supply voltage the system will malfunction in this condition Once the program enters back up mode BCF 1 32 768KHz Crystal oscillator will operate in a large driver condition and the internal logic function operates with a higher supply voltage TM8726 will get a higher power supply noise margin while back up mode is active but it will also receive an increase in power consumption The back up flag BCF indicates the status of the back up function BCF flag can be set or reset by executing the SF or RF instructions respectively The back up function has different performance corresponding to different power mode options shown in the following table 1 5V battery mode TM8726 status BCF flag status Initial reset cycle 1 hardware controlled After initial reset cycle 1 hardware controlled Executing SF 2h instruction 1 Executing RF 2h instruction 0 HALT mode Previous state STOP mode BCF 1 hardware controlled 60 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual TM8726 status BCF 0 1 32 768KHz Crystal Oscillator Small driver Large dri
151. pull down resistor Input pin for external INT request signal Falling edge or rising edge triggers are defined by mask option Internal pull down or pull up resistor is defined by mask option Test signal input pin Switching pins for supplying LCD driving voltage to the VDD1 2 3 4 pins Connect the CUPO CUP1 and CUP2 pins with non polarized electrolytic capacitors when the chip is operated in the 1 2 1 3 or 1 4 bias mode When there is no BIAS mode application leave these pins open Time base counter frequency Clock specified LCD alternating frequency Alarm signal frequency or system clock oscillation The use of either the 32KHz Crystal oscillator or the external RC oscillator is defined by mask option System clock oscillation for the FAST clock alone or during DUAL clock operation The use of either the 3 58MHz ceramic resonator oscillator or the external R type oscillator is defined by mask option COM1 9 Output pins for driving the common pins of the LCD panel ee COM5 9 can be defined as either COMS or Open Drain type output mask option SEG1 41 O Output pins for driving the LCD panel segment Input Output port A muxed with SEG24 27 by mask option Input Output port B muxed with SEG28 31 by mask option 1 4 Input Output port C muxed with SEG32 35 by mask option IOD1 4 Input Output port D muxed with SEG36 39 by mask option CX 1 input pin and 3 output pins for
152. put the OPD instructions must be executed to output the data to those output latches This will prevent the chattering signal when the IOD pins change to output mode IOD port has a built in pull low device for each pin that is selected by mask option To enable or disable this device execute the SPD instruction When the IOD pin has been set to the output mode the pull low device will be disabled MASK OPTION table Pull low function option Mask Option name Selected item IOC PULL LOW RESISTOR 1 USE IOC PULL LOW RESISTOR 2 NO USE 83 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual a NZ D bitO Q CLK IOD1 gt bito bit1 De CLK Uu Initial clear er edge dectect amp SPD 8 chattering gt SCF3 Data Bus bit2 De Q CLK IOD3 bit2 bit Q CLK 1004 gt 5 q Control 2 Note M O is mask option IPD OPD V This figure shows the organization of IOD port Note If the input level is in the floating state a large current straight through current flows to the input buffer when
153. rate the waveform as shown in the following figure PH15 1HZ ewe L 1 f L j 1 PH5 1KHz WWW Z CCC c CCC i A BZ BZB O O U U 3 4 2 THE CARRIER FOR REMOTE CONTROL If buzzer output combines with the timer and frequency generator the output of the BZ pin may deliver waveforms for IR remote controllers For remote control usage the setting value of the frequency generator must be greater than or equal to 3 and the ALM instruction must be executed immediately after the FRQ related instructions in order to deliver the FREQ signal to the BZ pin as the carrier for IR remote controller Example SHE 1 TMSX 3Fh SCC 40h FRQX 2 3 ALM 1COh HALT v x TS Enable timer 1 halt release enable flag value for timer 1 is 3Fh and the clock source is PHO Set the clock source of the frequency generator as BCLK FREQ BCLK 4 2 setting value for the frequency generator is and duty cycle is 1 2 FREQ signal is outputted This instruction must be executed after the FRQ related instructions Wait for the halt release caused by timer 1 released Stop the buzzer output 75 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual 3 5 INPUT OUTPUT PORTS Four I O ports are available in TM8726 IOA IOB IOC and IOD Each I O port is composed of 4 bits and has the same basic function When the I O pins are defined as non IO functions by m
154. rectly Refer to Table 4 2 Lz 00 3FH LCD latch Lz data decoder lt HL The contents of index RAM specified by HL are loaded to the LCD latch specified by Lz through the data decoder Refer to Table 4 2 Lz 00 3FH LCD latch Lz data decoder lt HL The contents of index RAM specified by HL are loaded to the LCD latch specified by Lz through the data decoder Refer to Table 4 2 If the content of HL is 0 the output of the data decoder will consist entirely of O s Lz 00 3FH LCD latch Lz HL AC The contents of index RAM specified by HL and the contents of AC are loaded to the LCD latch specified by Lz Refer to Table 4 2 Lz 00 Mullti LCD latches Lz s lt TAB HL HL indicates an index address of table ROM The content of table ROM specified by HL are loaded to several LCD latches Lz simultaneously Refer to Table 4 2 The range of multi Lz is specified by data D D 0 3 Table 4 3 The range of multi Lz latches 107 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual LCTX D Function Mullti LCD latch Lz data decoder HL Description The contents of index RAM specified by are loaded to several LCD latches Lz simultaneously The range of multi Lz is specified by data D Refer to Table 4 3 D 0 3 LCBX D Function Mullti LCD latch Lz data decoder HL D
155. rrect clock from reaching the system clock in the start up duration of the fast clock oscillator 26 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual CF clock XT clock FAST BCLK K HOLD12CFCLOCKS This figure shows the System Clock Switching from Slow to Fast After executing SLOW instruction the system clock generator will hold for 2 XT clock cycles then switch XT clock to BCLK CF Fast clock stops operating clock XT clock SLOW BCLK This figure shows the System Clock Switching from Fast to Slow 2 2 3 2 Single Clock MASK OPTION table For Fast clock oscillator only Mask Option name Selected item CLOCK SOURCE 1 FAST ONLY For slow clock oscillator only Mask Option name Selected item CLOCK SOURCE 2 SLOW ONLY The operation of the single clock option is shown in the following figure Either the XT or the CF clock may be selected by mask option in this mode The FAST and SLOW instructions will perform as the NOP instruction in this option The backup flag BCF will be set to 1 autom
156. rt reset and watchdog timer reset When a reset signal is accepted TM8726 will generate a time period for its internal reset cycle There are two types of internal reset cycle times that can be selected by mask option One is PH15 2 and the other is PH12 2 Reset signal System clock Hold 16384 or 2048 clocks for pla Normal operation gt internal reset cycle 66 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual Internal reset cycle time is PH15 2 MASK OPTION table Mask Option name Selected item RESET TIME 1 PH15 2 In this option the reset cycle time will be extended at least 16384 clocks clock source come form pre divider Internal reset cycle time is PH12 2 MASK OPTION table Mask Option name Selected item RESET TIME 2 12 2 In this option the reset cycle time will be extended at least 2048 clocks clock source come form pre divider 3 2 1 POWER ON RESET TM8726 provides power on reset function If the power VDD is turned on or the power supply drops below 0 6V it will generate a power on reset signal The power on reset function can be disabled through the mask option MASK OPTION table Mask Option name Selected item POWER ON RESET 1 USE POWER ON RESET 2 NO USE 3 2 2 RESE
157. ruction HL indicates an index address of data memory AC Rx lt Rx AC Binary Ors the contents of Rx and AC the result is loaded to AC and the data memory Rx AC HL HL AC Binary Ors the contents of HL and AC the result is loaded to AC and the data memory HL HL indicates an index address of data memory AC HL lt HL AC HL HL 1 Binary Ors the contents of HL and AC the result is loaded to AC and the data memory HL The content of the index register HL will be incremented automatically after executing this instruction HL indicates an index address of data memory AC lt Ry D CF D represents the immediate data Binary ADDs the contents of Ry D and CF the result is loaded to AC The carry flag CF will be affected D 0H FH AC Ry lt Ry D CF D represents the immediate data Binary ADDs the contents of Ry D and CF the result is loaded to AC and the working register Ry The carry flag CF will be affected D 0H FH AC Ry D CF D represents the immediate data Binary subtracts the CF and immediate data D from the working register Ry the result is loaded to AC The carry flag CF will be affected D 0H FH 123 tenx technology inc Rev 1 1 2007 06 28 Advance Information SBCI Ry D Function Description ADDI Ry D Function Description ADDI Ry D Function Description SUBI Ry D Functi
158. se the input signal of IOC IOD port are ORed it is necessary to keep the unchanged input signals at 0 state only one of the input signal can change state 53 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual 2 15 1 2 The Settings for Stop Mode If SRFA SRF3 and SEF4 SEF3 are set the stop mode will be released to set the SCF1 SCF3 when a high level signal is applied to one of the input mode pins of IOC IOD port and the other pins stay in O state After the stop mode is released TM8726 enters the halt condition The high level signal must hold for a while to allow the chattering prevention circuitry of IOC IOD port to detect this signal and then set SCF1 SCF3 to release the halt mode otherwise the chip will return to stop mode again 2 15 1 3 Interrupt for CTL 1 The control register 1 CTL1 performs the following function in the execution of the SIE instruction to enable the interrupt function The input signal changes at the input pins in IOC IOD port will deliver the SCF1 SCF3 when SEF4 SEF3 has been set to 1 by executing the SCA instruction Once the SCF1 SCF3 is delivered the halt release request flag HRFO will be set to 1 In this case if the interrupt enable flag 0 IEFO is set to 1 by executing the SIE instruction the interrupt request flag 0 interrupt O will be delivered to interrupt the program If the interrupt 0 is accepted by SEF4 SEF3 and IEFO the interrupt 0 r
159. signal from mode of RFC function causes the halt release request flag 6 HRF6 to be outputted and the halt release enable flag 9 HEF9 is set beforehand In this case the 16 counter of RFC function must be controlled by CX pin please refer to 2 16 9 To reset the start condition flag 9 SCF9 the PLC instruction must be used to reset the halt release request flag 6 HRF6 otherwise the SHE instruction must be used to reset the halt release enable flag 6 HEF6 The MCX instruction can be used to transfer the contents of status register 3X STS3X to the accumulator AC and the data memory RAM The following table shows the Bit Pattern of Status Register 3X STS3X 50 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual Bit 3 Bit 2 Bit 1 Bit 0 Start condition NA Start condition Start condition flag 9 flag 6 flag 8 SCF9 SCF6 SCF8 Halt release Halt release Halt release caused by RFC caused by TMR2 caused by SKI counter finish underflow underflow Read only Read only Read only Read only 2 14 5 STATUS REGISTER 4 STS4 Status register 4 STS4 consists of 3 flags 1 System clock selection flag CSF The system clock selection flag CSF indicates which clock source of the system clock generator SCG is being used Executing the SLOW instruction will change the clock source BCLK of the system clock generator SCG to the slow speed oscillator XT clock resets the system clock
160. sses are specified by the index address register The data width can be 8 bits 256 16 N x 8 bits or 4 bits 512 16 N x 4 bits depending on usage Refer to the explanation in the instruction chapter 2 5 INDEX ADDRESS REGISTER HL This is a versatile address pointer for the data memory RAM and table ROM TROM The index address register HL is a 12 bit register and the contents of the register can be modified by executing MVH MVL and MVU instructions MVL instructions when executed will load the content of specified data memory to the lower nibble of the index register L In the same manner executing MVH and MVU instructions will load the content of the data RAM Rx to the higher nibble of the register H QU respectively QU register H register L register Bit3 Bit2 Bit Bit2 Bit BitO Bits Bit2 Bit4 BitO IDBF1 IDBF1 IDBF9 IDBF8 IDBF7 IDBF6 IDBF5 IDBF4 IDBF3 IDBF2 IDBF1 IDBFO 1 0 The index address register can specify the full range addresses of the table ROM and data memory index addressing DATA RAM TABLE ROM addressing This figure shows the diagram of the index address register The index address register is a write only register CPHL X instruction can specify 8 bit immediate data to compare with the content of H and L When the result of comparison is equivalent the instruction behind
161. sults of the carry or borrow during the arithmetic operation 2 Zero flag Z Indicates the accumulator status When the content of the accumulator is 0 the Zero flag is set to 1 If the content of the accumulator is not O the zero flag is reset to O 3 The MAF instruction can be used to transfer data in status register 1 STS1 to the accumulator AC and the data memory RAM 4 The MRA instruction can be used to transfer data of the data memory RAM to the status register 1 STS1 The bit pattern of status register 1 STS1 is shown below Bit 3 Bit 2 Bit 1 Bit 0 Carry flag AC Zero flag Z 2 14 2 STATUS REGISTER 2 STS2 Status register 2 STS2 consists of start condition flag 1 2 SCF1 SCF2 and the backup flag The MSB instruction can be used to transfer data in status register 2 STS2 to the accumulator and the data memory RAM but it is impossible to transfer data of the data memory RAM to status register 2 STS2 The following table shows the bit pattern of each flag in status register 2 STS2 Bit 3 Bit 2 Bit 1 Bit 0 Start condition Start condition Start condition Backup flag flag 3 flag 2 flag 1 BCF SCF3 SCF2 SCF 1 Halt release Halt release Halt release caused by the caused by caused by the 4 IOD port SCF4 5 6 7 9 IOC port Read only Read only Read only Read only Start condition flag 3 SCF3 When the SCA instruction specified signal change occurs at port IOD to release
162. t programmable timer with programmable clock source 13 Watchdog timer 14 Built in voltage doubler halver tripler quartic charge pump circuit 15 Dual clock operation Slow clock oscillation can be defined as X tal or external RC type oscillator by mask option Fastclock oscillation can be defined as 3 58MHz ceramic resonator internal R or external R type oscillator by mask option 16 HALT function 17 STOP function 1 3 BLOCK DIAGRAM B1 4 A1 4 ELC ELP CX es D1 4 BZBBZ RRRTRH COM 9 SEGI 41 VDD1 4 nooo 7777 1977 7777 0 em ooo B PORT LCD DRIVER A PORT C PORT EL DRIVER REC KEVIN D PORT ALARM SEGMENT PLA TII ERT m 4 BITS DATA BUS Tt LE FREQUENCY INDEX ROM ALU DATA RAM GENERATOR 256 16 N X8BITS 512 X 4 BITS L AE Gi 6 BITS PRESET 8 LEVELS INSTRUCTION j TIMER1 8 2 STACK DECODER 1 PROGRAM ROM OSCILLATOR a 2048 128N X 16 BITS 0 1 1 2 OUT CFINOUT RESET INT TM8726 BLOCK DIAGRAM BLOCK DIAGRAM N 0 gt 16 4 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual 1 4 PAD DIAGRAM
163. the re load function and RF 80h instruction disables it When the re load function is enabled the TMR1 will not stop counting until the re load function is disabled and TMR1 underflows again During this operation the program must use the halt release request flag or interrupt to check the wanted counting value It is necessary to execute either the TMS or the TMSX instructions to set the down count value before the re load function is enabled because TMR1 will automatically count down with an unknown value once the re load function is enabled Never disable the re load function before the last expected halt release or interrupt occurs If TMS related instructions are not executed after each halt release or interrupt occurs the will stop operating immediately after the re load function is disabled For example if the expected count down value is 500 it may be divided as 52 7 64 First set the initiate count down value of TMR1 to 52 and start counting then enable the TMR1 halt release or interrupt function Before the first time underflow occurs enable the re load function The TMR1 will continue operating even though TMR1 underflow occurs When halt release or interrupt occurs clear the HRF1 flag through a PLC instruction After a halt release or interrupt occurs 8 times disable the re load function counting is completed 41 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual
164. ting even if TMR2 underflows When halt release or interrupt occurs clear the HRF4 flag by PLC instruction and increase the counting value to count the underflow times When halt release or interrupt occurs for the 7 time reset the DED flag When halt release or interrupt occurs for the 8 time disable the re load function and the counting is completed In this example S W enters the halt mode to wait for the underflow of TM2 LDS 0 0 initiate the underflow counting register PLC 10h SHE 10h enables the halt release caused by TM2 SRF 19h enables RFC and controlled by TM2 TM2X 34h initiates the TM value 52 and clock source is 9 SF2 3h enables the re load function and set DED flag to 1 RE LOAD HALT INC 0 increases the underflow counter PLC 10h clears HRF4 LDS 20h 7 SUB 0 when halt is released for the 7 time reset DED flag JNZ NOT RESET DED RF2 2 resets DED flag NOT_RESET_DED LDA 0 stores underflow counter to AC JB3 END TM1 if the TM2 underflow counter is equal to 8 exit this subroutine JMP RE LOAD END 1 RF2 1 disable the re load function 45 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual 8th 64 ae E 5 2 cu 4 count TM2 HRF4 15 1 PLC H Re load DED TENX This figure shows the operat
165. tion 4 3 4 THE CONFIGURATION FILE FOR MASK OPTION When configuring the mask option of LCD PLA the cfg file provides the necessary format for editing the LCD configuration The syntax in the cfg file is as follows SEG COM PSTB DBUS SEG Specifies the segment pin No 1 41 represents segment pin No C5 C9 represents common pin No When the common pin COM is specified as the DC output pin assign C5 C9 in this column C5 C9 represents COM5 9 respectively COM Specifies the corresponding latch in each segment pin Only 0 1 2 3 4 10 can be specified this column 1 9 represents latch 9 latch respectively 0 is for CMOS type DC output option and 10 is for P open drain DC output option PSTB Specifies the strobe data for the latch DBUS Specifies the DBUS data for the latch 105 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual Chapter 5 Detailed Explanation of the TM8726 Instructions e It is necessary to initialize the content of the data memory after the initial reset because the initial content of the data memory is unknown e The working registers are part of the data memory RAM and the relationship between them is shown as follows The absolute address of working register Rx Ry 70H e Lz represents the address of the latch of LCD PLA PSTB data in cfy file the address range sp
166. ver Voltage on BAK pin VDD1 VDD1 Internal operating voltage VDD1 VDD1 3V battery or higher mode Initial reset cycle 1 hardware controlled After initial reset cycle 1 hardware controlled Executing SF 2h instruction 1 Executing RF 2h instruction 0 HALT mode Previous state STOP mode BCF 1 hardware controlled o y BOFA 32 768KHz Crystal Oscillator Small driver Large driver Voltage on BAK pin VDD1 VDD2 Internal operating voltage VDD1 VDD2 Ext V power mode Initial reset cycle 0 hardware controlled After initial reset cycle 0 hardware controlled Executing SF 2h instruction 1 RF 2h instruction 0 HALT mode Previous state STOP mode BCF 1 hardware controlled 0 1 32 768 2 Crystal Oscillator Large driver Large driver Voltage on BAK pin VDD2 VDD2 Internal operating voltage VDD2 VDD2 Note For power saving reasons it is recommended to reset BCF flag to 0 when back up mode is not used 61 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual Chapter 3 Control Function 3 1 INTERRUPT FUNCTION There are 7 interrupt resources 3 external interrupt factors and 4 internal interrupt factors When an interrupt is accepted the program in execution is suspended temporarily and the corresponding interrupt service routine sp
167. ver the counter has a different operation method Here the CX pin becomes the controlled signal to enable disable the counter and the clock source of the counter comes from the output of the frequency generator FREQ The counter will start to count the clock FREQ after the first rising edge signal applied on the CX pin when the counter is enabled Once the second rising edge is applied to the CX pin after the counter is enabled the halt release request HRF6 will be delivered and the counter will stop counting In this case if the interrupt enable mode IEF6 is provided the interrupt is accepted and if the halt release enable mode HEF6 is provided the halt release request signal is delivered setting the start condition flag 9 SCF9 in status register 4 STS4 Each time the 16 bit counter is enabled the content of the counter will be cleared automatically SRF SRF i 1 SRF control Enable counter C CX s 0 TEB Ns reo JUU HALT rel d Ear oe Caused bythe 2nd falling edge This figure shows the timing of the counter controlled by the CX pin Example SCC Oh selects the base clock of the frequency generator that comes from PHO XT clock FRQX 1 5 sets the frequency generator to FREQ PH0 3 5 the setting value of the frequency generator is 5
168. w level hold device When the IOC pin has been set to output mode both the pull low and low level hold devices will be disabled 80 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual bitO D lt Q CLK IOC1 bito bit1 bit1 IOC2 Initial clear Gov SPC 8 SCF1 Data Bus bit2 10C3 bit2 bit3 IOC4 bit3 M O gt 4 Control 2 20 Note M O is mask option IPC OPC V This figure shows the organization of IOC port Note If the input level is in the floating state a large current straight through current flows to the input buffer when both the pull low and L level hold devices are disabled The input level must not be in the floating state 81 tenx technology inc Rev 1 1 2007 06 28 Advance Information TM8726 User s Manual MASK OPTION table Pull low function option Mask Option name Selected item IOC PULL LOW RESISTOR 1 USE IOC PULL LOW RESISTOR 2 NO USE The low level hold function will not be available when pull low function is not activated Low level hold function option Mask Option name Selected item C PORT LOW LEVEL HOLD 1 USE C PORT LOW LEVEL HOLD 2 NO USE 3 5 3 1 Chattering Prevention Function and Halt Release The port IOC is capable of preventing high low chattering of the switch signal applied on IOC1 to pins The chattering prevention time can be selected as PH10
169. x address of data memory AC Rx lt Rx amp AC Binary ANDs the contents of Rx and AC the result is loaded to AC the data memory Rx AC HL lt HL amp AC Binary ANDs the contents of HL and AC the result is loaded to AC and the data memory HL HL indicates an index address of data memory AC HL lt HL amp AC HL HL 1 Binary ANDs the contents of HL and AC the result is loaded to AC and the data memory HL The content of the index register HL will be incremented automatically after executing this instruction HL indicates an index address of data memory 121 tenx technology inc Rev 1 1 2007 06 28 Advance Information EOR Rx Function Description HL Function Description EOR HL Function Description EOR Rx Function Description EOR HL Function Description EOR Function Description Rx Function Description OR HL Function Description TM8726 User s Manual AC lt Rx AC Exclusive Ors the contents of Rx and AC the result is loaded to AC AC lt Exclusive Ors the contents of HL and AC the result is loaded to AC HL indicates an index address of data memory AC lt Q HL AC HL HL 1 Exclusive Ors the contents of HL and AC the result is loaded to AC The content of the index register HL will be incremented automatically after executing this

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