PT8 Multi-standard Video Encoder User Manual
Contents
1. 05 05 05 05 2 SC ae Er 806 HSyncstat2 05 05 05 05 05 05 500 HSyncendi _ 34 34 34 34 34 34 0E H Sync end 2 06 06 06 06 06 06 1 we T RT e a he 14 Pedestal start2 S00 soo 00 soo soo so 15 Pedestal endi SCA SCA SCA er er 97 o _ 16 Pedestalend2 505 505 sos sos sos S05 17 Half line start 1 58 S58 58 E 18 Halflinesta2 02 02 02 02 soz 02 o 19 Equalising end 1 SFB 868 sra sra SFB SFB Z 1A Equalisingtend2 05 505 05 05 05 S05 1B Equalising2 end 1 98 es es 98 sos 98 SiC Equalising2 end2 02 502 02 02 S02 02 1D Broadiend1 D9 SD9 spe D9 D9 spe Broadiend2 01 01 01 01 01 S0 Broad2endi _ 1B sie IB 20 Broad end2 505 505 806 05 S05 S05 21 Burst gate start 1 52 52 49 49 S49 49 22 Burst gate start2 06 06 06 06 06 060 23 Burstgateendi S8F sap 80 S8D ap F Bee2. 0 0 48 2 o 2 4 1 0 __ Ons Default _ 1 37ns 1 0 346 0 000 0 p 1 ___ 1 0 4 1111 __ qp o 5 __ jO jo e po pe _______ off 7 the ET LA if set to 1 monochrome output Default 0 If VBI Pass is 1 then the VBI information is pass flat as described VBI_Pass Control 1 bit 1 If 1 and VBI Pass is 1 the BT656 video data is encoded picture area The gain control for Y is set by registers Pass 1 vertical blanking 15 from lines 623 5 23 5 and lines 311 335 for PAL and lines 1 20 and 263 5 283 5 for NTSC If 1 the vertical blanking is from lines 623 5 4 5 and 311 317 for PAL and lines 1 9 and 263 5 272 for NTSC During the vertical VBI interval lines 4 5 23 5 9 20 and lines 317 335 272 283 5 data on the BT656 Y input is passed to the output with a gain set by registers 2D and 2E Data on the Cb and Cr inputs is blanked Default 0 ei ER If 0 BT656 data is encoded If 1 a free running Black and is generated from the 27MHz clock Default 0 registers HPhase1 RW Delay between BT656 SAV and SPG horizontal counter R W Increments of 1 27MHz Maximum value 1715 or 1727 depending on the line standa
3. CTS 3 19 180 19 280 01337 21 147980 1470180 1471180 gen 2734 137580 1103214 47353 147 280 5 147680 91353 137680 74 c c J74 TININ YI Qt 333 73581 21 1383401725879 X73617 173 1AM 11 24 980 24 180 24 280 24 680 24 80 24 580 24 980 24 280 24 680 692509 2320190 gn 24 1180 147880 147180 147280 147980 147080 1447980 187 280 452 680 223 680 1470180 1371180 3149514 134 213 31 13431 21 9 2744 3724 47353 91353 m asrz3nzb p81 sl dn2y 010449 20040 10070 267 bJ 827 AIC IMP ugar 6 452 327 SEO E eer Ag U 6 144794 C 344 94 am 344794 C 244774 343 93 6 644794 C 81 4 4 1124724 13541 C dX758A3 TA78863 2575441 Ear Sand MEYE l SAZ SED 375421 lt 2445842 84 752 23 1478853 21 01 38070 INNON esses d AJENA Du 992 5 83 cay 1 NIA at Example schemat Figure 7 Interfacing to a DAC ISION PT8 User Manual Rev SingMai Electronics Specification Specification Comments B D G H I K N P
4. 27 Figure 17 FAL Horizomal UMNO errer shes bn ER kan KERE bad U KB R band kan EN 28 Figure 18 PAL 75 Colour 28 Figure 19 PAL Chroma Luma delay kak emnes 29 Br l Na A Neb AO TT 29 Figure 21 PAL Multiburst sinx x correction 30 Figure 22 PAL Noise spectrum 31 Figure 23 PAL Luma 32 PT8 User Manual Revision 0 9 Page 2 of 32 SingMai Electronics Introduction PT8 is multi standard video encoder supporting PAL M N B D G H I and NTSC M J outputs The intellectual property block accepts BT656 formatted data in either 8 or 10 bit format with the associated 27MHz clock and it encodes this data to a 10 bit digital composite video signal also at 27MHz which can be used to directly drive a digital to analogue converter or other output device Control and status registers are written to and read from using a conventional 8 bit wide microprocessor interface The intellectual property block is provided as an encrypted black box design for incorporation into an Altera FPGA as a netlist for Xilinx FPGAs or as RTL compliant Verilog source code for FPGAs from other vendors or for ASICs Typical resource usage for an Altera FPGA is shown in Table 1 Logic Elements Memory Bits blocks 9x9 Multipliers 18x18 mult
5. SingMai Electronics PTS Multi standard Video Encoder User Manual Revision 0 9 9 July 2011 SingMai Electronics Contents Sog M 2 qi 2 SS T 2 3 PT8 Module 4 erga 5 Celt OV GIS 7 H cceHurrf TEN T 8 M veipe Ee7 TE 9 mise cud RI UT TUNE 11 mises e 12 Horizontal timing 16 Default Register 65 220 001 eese nennen nennen aa W ka a ala a j eka da ala 18 a DAC AA MM HH 20 mM _ ____________ _____ __ 22 Measurements 23 Tables Table 1 Altera FPGA resource 5 3 Table 2 Input Output SIQNAlS ccccccccccccessssesesesceceeeeeeeeeeeseceeeeesesaesaeeseeeeeeeeesseaaaseeeeeeeesaeeeaas 6 Table 3 BI656 Signal Levels 7 Table 4 BT656 525 line selection 8 Table 5 BT656 625 line selectlOn nannte a rna nba tare
6. d na nad k a 8 Table 6 Register 15 Table 7 Default Register 19 Tables TO SS DOC CO 22 Figures Figure 1 Interconnection diagram Error Bookmark not defined c 7 Figure 9 PT BIOCK 9 Figure 4 Control interface Timing kend wanara b n An 11 Figure 5 NTSC horizontal timing kek k kanan kn dan d k ka dv a 16 Figure o PAL horizontal rilhigo eec cnc tes 17 Figure 7 Interfacing to a DAC Example 21 Figure 8 NTSC Vertical blanking interval nnne 23 Figure 9 NTSC Horizontal nnne nnne nennen nnns 24 Figure 10 NTSC 75 Colour as l kulleka klanan kek niada dek y kek kya keka nennen nnn nnne b k da da 24 Figure 11 NTSC Chroma Luma delay esses nennen nennen nnne nnn 25 wea CON EET es 25 Figure 13 NTSC Multiburst No sinx x 26 Figure 14 NTSC Noise Spectrum 26 Figure 15 NTSC Noise Spectrum ramp 27 Figure 16 PAL Vertical blanking kk kk kk
7. 11 bit value E Broad2 end 1 Beginning of the burst gate signal Increments of 1 27MHz Broad2 end 2 NEL gate start Maximum value 1715 or 1727 depending on the line standard 525 or 625 respectively Burst gate nominally starts 5 64us iii gate start after Hsync start 11 bit value Burstgatestart2 2 0 Burstgatestart1 7 0 Burst gate end 1 End of the burst gate signal Increments of 1 27MHz Maximum canal value 1715 or 1727 depending on the line standard 525 or 625 respectively Width of burst gate pulse Burstgatestart Burst gate end 2 Burstgateend 1 27MHz nominally 2 25us 11 bit value Burstgatestart2 2 0 Burstgatestart1 7 0 25 FSci RW LSB Of the 32 bit subcarrier seed word 526 2 The subcarrier seed word is calculated by the formula 27 R W FSc 27MHz 2432 For example for NTSC FSc 3 5795455 ope mi Seed 569408550 or 21 F804 21 FSc2 7C FSc1 26 528 Fsca MSB ofthe 32 bit subcarrier seed _____________ 529 NTSC Hue1 _____ Hue control NTSC output only NTSC Hue 2 11 bit value NTSCHue2 2 0 NTSCHue1 7 0 1 LSB 0 176 Sync Scaling 1 top amp control 9 bit value SyncScaling2 0 SyncScaling1 7 0 Output composite sync level nominally Sync scaling 256 Burst Scaling 1 RW Burst amplitude results in sync output between 16 sync
8. 8 105 104 104 103 103 102 102 101 101 100 100 99 99 98 38 97 36 36 95 et ist 2nd vereoge 32 gt 32 Figure 23 PAL Luma non linearity
9. Composite video gain used for matching to output stage CVBS gain 2 9 bit value CVBSgain2 0 C VBSgain1 7 0 Status aa Parity error count from BT656 receiver number of parity errors per frame limited at maximum value 255 Version No R 05 TP core version number ___________ Table 6 Register descriptions PT8 User Manual Revision 0 9 15 of 32 LLI Sin Horizontal timing registers Figures 5 and 6 show the timing requirements for NTSC and PAL BG respectively pua quel PUR pec OS LN Buru L ues 0 uno aui HEH AGS 4uepgH sic pu pua gt pua Durgiperib slt paysnipe aeb sung snd peo smd Gursyenby sand aur spaxid FF 9121 Figure 5 NTSC horizontal timing Page 16 of 32 al 2 2 gt tc 6 5 Qo H n LLI Sin 58 EBEL ues JUSH 0 uno aui HEH AGS E EINEN yng pus ab young snd peo Pus pe
10. Register settings PT8 User Manual Revision 0 9 Page 19 of 32 SingMai Electronics Interfacing to a DAC 10 bit digital composite output and the 27MHz clock can directly drive a suitably fast DAC Figure 7 shows the digital to analogue DAC interface that was used for the measurements at the end of the user manual Only the top part of the schematic is relevant for the PT8 The DACs used are Analog Devices AD9765 which are dual 12 bit DACs For the PT8 only the top ten bits should be connected to the CVBS out of the PT8 the bottom 2 bits are then connected to ground The Verilog code to use both DACs the second DAC can be copy of the CVBS information as in this example or other synchronous output video such as the Y component output is shown below Output DACs Format output to AD9765 DACs output stage always negedge 54M or negedge RESETn begin if RESETn begin pb pr lt 10 d0 cvbs y z 10 d0 end else if DAC begin cvbs y lt CVBS out 9 0 pb pr lt 10 d0 end else begin cvbs y lt CVBS out 9 0 pb pr lt 10 d0 end end assign dac iqwrt CIk 54M assign dac iqclk CIk 54M assign dac iqsel DAC assign dac reset 1 60 always negedge CIk 54M or negedge RESETn begin if IRESETn begin DAC clk lt 1 b0 end else begin DAC_clk lt 27M end end The 54MHz is a 2x version of the 27MHz
11. bottom and 256 sync PT8 User Manual Revision 0 9 Page 14 of 32 SingMai Electronics Register Register Name R W Bit Description Offset Value Burst Scaling2 RW 9 bit value BurstScaling2 0 BurstScalingt 7 0 UV Scaling 1 Output chrominance level UV Scaling 2 RW _____ 11 bit value UVScaling2 2 0 UV Scaling1 7 0 31 Sync Offset1 RW Ries value for the CVBS output effectively the level of the bit value 6 ncOffset2 0 SyncOffset1 7 0 33 Scaling1 Scaling between BT656 data and composite Y output 335 during the VBI interval EEE bit value VBIScaling2 1 0 VBIScaling1 7 0 ks vr Pedestal added during active video period NTSC M and PAL M only Y Offset 1 RAW Value to be subtracted from the BT656 luma input normally Y Offset 2 value 64 10 bit value 9 bit value Y Offset2 0 YOffset1 7 0 Luma Scaling 1 RW Scaling between BT656 Y data and composite Y output Luma Scaling 2 LAE applied during the active picture area nominally 560 940 1023 10 bit value LumaScaling2 1 0 LumaScalingt1 7 0 Cb Scaling 1 RW Scaling between BT656 Cb data and U nominally 0 493 511 Cb Scaling 2 RW 9bitvalue CbScaling2 0 CbScaling1 7 0 Cr Scaling 1 RW J Scaling between BT656 Cr data and V nominally 0 877 511 Cr Scaling 2 RN 9bitvalue CrScaling2 0 CrScaling1 7 0 CVBS gain 1 R W
12. signal is also blanked using a shaped clipping waveform and has programmable gain added whilst the composite sync signal has an approximation to a 2T wave shape added to ensure rise fall time conformance to the video specification The luminance chrominance and composite sync are then added together to generate the final 10 bit 27MHz digital PAL encoded output The encoder can also be set to a freerun mode in which it ignores the BT656 timing information and data and uses the 27 2 clock input to generate a black and burst output The vertical blanking interval data may be selected to be stripped passed flat Y channel only or encoded as per the active video Control of the encoder is via a conventional 8 bit wide microprocessor bus In addition status registers allow the monitoring of internal timing signals Two test outputs are also provided that may be programmed to monitor various internal signals PT8 User Manual Revision 0 9 Page 10 of 32 SingMai Electronics Register interface Figure 4 shows the timing diagram for the register interface it is a conventional microprocessor interface Each register is selected via an 8 bit address bus Writes to unused register locations are ignored To write to the selected register the PT8 CSn chip select input must be asserted low Whilst this is low the PT8 WHn must be taken low An internal write enable pulse is created at the next rising edge of the XTAL 27M clock and writi
13. to Figures 5 and 6 for details of the horizontal timing register settings Asserting the RESETn input sets the PT8 to Auto standard NTSC M and the registers are loaded with the default values for NTSC M Register Register Name R W Bit Description Offset Value EZ i es ee Auto standard When set 1 the hardwired values are used for PT8 control depending on the state of bit 6 Line standard When this bit is set to 0 the register values are used for PT8 control Default Vallee 2 1 L s es v sm v ers Tes NTSC PAL Default PAM Seer ee Interpolator 1 If set to 1 the 2 1 interpolator is bypassed else the interpolator is enabled Note there is a 19ns Y C delay error when the passed Default value 1 eee set to 1 the interpolator is expecting an 18 9375MHz input E else a 2 MHz input clock Default value 07 Control 2 e PT8 Test 1 0 output selection po Noted 5 Bts 84 _ Testtoutput Lo 10 0 10 10 11 pf o p Beh 1Ib ____________ Ti T PT8 User Manual Revision 0 9 Page 12 of 32 SingMai Electronics Register Register Name R W Bit Description Offset Value 802 ___ Control3 ___ RW Control register Y dea 74 7 Bt5 Bitt4
14. 8 Register CVBS out CVBS out 9 0 PT8 TestO PT8 TestO PT8 Testi PT8 5625 525n PT8 5625 525 Sync Comp Sync Page 6 of 32 PT8 User Manual Revision 0 9 SingMai Electronics Signal Levels The expected signal levels for the BT656 input are shown in Table 3 below 10 bit YCbCr signal Levels 100 0 100 0 m TN Cb 063961 960 j jk 164 960 49 512 10 bit YCbCr signal Levels 75 0 75 0 Red 200 DB 19 AB Table 3 BT656 Signal Levels The resulting nominal output levels for a 100 PAL colour bar input are shown in Figure 2 1004 1004 Figure 2 CVBS output levels PT8 User Manual Revision 0 9 Page 7 of 32 SingMai Electronics Test signals The PT8 is supplied with BT656 test waveforms to facilitate testing and verification The waveforms are supplied as Excel spreadsheets and are 75 saturation colour bars Other waveforms can be supplied to request for a small charge There are four elements to the complete frame of video and each element consists of 1716 515 line or 1728 625 line samples in a multiplexed Cb Y Cr Y sequence Each sample of each element should be clocked at 27MHz For 525 line the elements need to selected according to the following table Line No s Pattern Element 4 19 264 265 FOV1 1 1 3 266 282 2 20 263 75 Bars FO 3 283 525 75 Bars F1 4 Table 4 BT656 525 line selecti
15. AL M 25Hz 50Hz 30Hz 60Hz S 64us _63 555555us nn T 12us 1 5us 1 65 for PAL 4 7us 47 5 8us 45us 2 35us 23 ___ _ _ tt jt U _ 27 3us 27 0775 Rise Fall times of sync 250ns 250ns NTSC PAL M rise time edges should be 140ns and PAL I rise times should be 250ns Sync Pulse amplitude 300mV 40IRE Luminance white bar 700 100IRE amplitude as Vertical Sync Group 7 5 lines glnes J t No of equalizing pulses 5 5 6 6 J 4 MEME Chrominance Phase error lt 1deo Subcarrier Frequency 4 43361875MHz 3 5795455MHz PAL 8 fields 5 64us 2 25us 300mV lt 1 lt 1 lt 1 delay Signal to Noise ratio 65 black 65dB black Unweighted input input 58dB luma 58 ramp ramp Table 8 PT8 Specifications L N E 1 1 PT8 User Manual Revision 0 9 Page 22 of 32 nan The PT8 multistandard encoder was measured using a Altera Cyclone III develooment board with 3 55 FPGA The source was the PT6 video pattern generator IP core which provided the 10 bit BT656 input to the PT8 encoder The composite digital output was converted to analogue using an Analog Devices AD9765 12 bit digital to analogue converter top 10 bits driven The output from the DAC was amplified and filtered using an ADA4412 amplifier with the bandwidth set to 36MHz and the composite measurements were performed on a Tektronix VM700
16. dwidth 1SkMz te Full Tilt Null CO y t A 4 tad CO uj J 7 J oo d dh dh L O VV O YV O Wi B B B B Wad UV ios 4 50 ooo oO i eu gt 4 A e UIN 2 3 96 6 u sec from Sync 30 8 u sec Width an A lt gt 32 Figure 15 NTSC Noise Spectrum luma ramp MA ue aeae nl i EEE AAA mnn AAN ce EE Figure 16 PAL Vertical blanking interval PT8 User Manual Revision 0 9 Page 27 of 32 SingMai Electronics Figure 17 PAL Horizontal timing Figure 18 PAL 75 Colour bars PT8 User Manual Revision 0 9 Page 28 of 32 SingMai Electronics Figure 19 PAL Chroma Luma delay Figure 20 PAL K factor PT8 User Manual Revision 0 9 Page 29 of 32 Line 114 Amplitude 9 dB e 417 8 mU Flag 98 9 10 9 04 9 18 3 Figure 21 PAL Multiburst sinx x correction Noise Spectrum PAL Wim gt Pedestal Line 114 Amplitude 9 dB 700 Noise Level 65 1 dB rms Bandwidth 1SkHz to Full 5 0 10 ut ES 20 25 30 35 6 42 45 50 55 60 65 70 75 50 85 90 95 100 2 Figure 22 PAL Noise spectrum black Luminance Non Linearity PAL Wim gt Composite Line 114 Luminance Non Lineority 8 2 100 0 99 3 99 3 33 3 99
17. ets all regiisters written to read from Control data input bus PT8 Control chip select input active low Used in combination with the WhHn input to control writing to the control registers PT8 WHn Active low write enable input Used in combination with the CSn input to control writing to the control registers PT8 Register out 7 0 Control output data bus Outputs the control status register data selected by the A 7 0 bus CVBS out 9 0 The digital composite output The output format is straight binary with bit 9 being the MSB The output is valid on the rising edge of the Clock input PT8 TestO Used in combination with control register 2 to select internal test signals PT8 Used in combination with control register 2 to select internal test signals PT8 User Manual Revision 0 9 Page 5 of 32 SingMai Electronics Output signal signifying the line standard currently selected for the PT8 encoder 1 625 line 0 525 line Composite sync signal output May be buffered and used with monitors that require separate sync inputs Table 2 Input Output signals 5625 525 Sync The Verilog instantiation of PT8 is shown below Instantiate Video encoder PT8 encoder PT8 encoder PT8 encoder Clock Clk 27M XTAL_27M XTAL_27MHz BT656 data BT656 data 9 0 RESETn FPGA RESETn A PT8 A Din PT8 PT8 CSn PT8 CSn PT8 WRn PT8 WRn PT8 Register out PT
18. he half line 32us referenced to H Phase reset Increments of 1 27MHz Maximum value 1715 or 1727 depending on the line standard 525 or 625 respectively 11 bit value Halflinestart2 2 0 Halflinestart1 7 0 Half line end is H Sync start position Width of the first equalizing pulse whose leading edge is HSyncstart Increments of 1 27MHz Maximum value 1715 or 1727 depending on the line standard 525 or 625 respectively HSync start Equalising 1 end 1 27MHz is the equalizing pulse width nominally 2 35us 11 bit value Width of the second equalizing pulse whose leading edge is Half line start Increments of 1 27MHz Maximum value 1715 or 1727 depending on the line standard 525 or 625 respectively start Equalising 2 end 1 27MHz is the equalizing pulse width nominally 2 35us 11 bit value Equalising2end2 2 0 Equalising2end1 7 0 Width of the first broad pulse whose leading edge is HSyncstart Increments of 1 27MHz Maximum value 1715 or 1727 depending on the line standard 525 or 625 respectively HSync start Broad1 end 1 27MHz is the broad pulse width nominally 27 3us 11 bit value Broad1end2 2 0 Broad1end1 7 0 Width of the second broad pulse whose leading edge is Half line start Increments of 1 27MHz Maximum value 1715 or 1727 depending on the line standard 525 or 625 respectively Halfline start Broad 2 end 1 27MHz is the equalizing pulse width nominally 27 3us
19. i 5 FSc ie we 96 27 09 09 TT TT m PT8 User Manual Revision 0 9 Page 18 of 32 SingMai Electronics 29 NTSCHue1 00 00 00 00 00 00 NTSCHue2 00 00 00 00 00 00 Proc amp control 2B SyncScalingi 86 86 86 9E 9E Sync Scaling 2 m 2D BurstScalngi 48 48 48 He Burst Sealing 300 soo amp soo soo so MEME MM jus 5 sos soa soa Sa Te ww ow we we Pe I m 34 VBIScaling2 0 VBIScaling2 2 mj Pedestal 00 00 18 18 00 only operates for 525 line standards 536 Yoffset 40 40 40 m oon m m 38 LumaScalingi 3 3E 3E 8E 9A 39 LumaScaling2 01 01 01 01 01 01 3A Cb Scaling 1 60 60 60 5C 5C soc Z 38 CbScaling2 01 01 01 01 01 01 532 Cr Scaling 1 E8 E8 8 EA EA 3D CrScaling2 01 01 01 01 01 01 3E CVBSgani 1B 1B 1B 75 75 s 3F CVBSgain2 03 03 503 02 02 02 7 5 Table 7 Default
20. ipliers Table 1 PT8 Altera FPGA resource requirements PT8 User Manual Revision 0 9 Page 3 of 32 SingMai Electronics PT8 Module description The PT8 encoder comprises 8 Verilog modules PT8 encoder v PT8 BT656 receiver v PT8 Chroma modulator v PT8 output proc v Register control v PI8 SPG v PT8 Subcarrier gen v PT8 ROM v PT8 encoder v is the top level module of the hierarchy six of the other modules are instantiated from it The sin cos lookup table PT8 ROM v is called from PT8 Subcarrier gen v PT8 User Manual Revision 0 9 Page 4 of 32 SingMai Electronics Signal Interconnections The PT8 signal interconnect diagram is shown in Figure 1 gt PT8 encoder Clock 8 Register out 7 0 XTAL 27M CVBS out 9 0 BT656 data 9 0 PT8 TestO RESETn PT8 Test1 A 7 0 S625 525n Din 7 0 Comp Sync PT8 CSn PT8 WRn Figure 1 PT8 Interconnection diagram The signal descriptions are shown in Table 2 below Description 27MHz clock input synchronous with the BT656 input data The BT656 data should be stable at the rising edge of this clock Clock used for writing to the registers only If Clock is continuous and stable 27 may be connected to that input BT656 compliant input data If the input is 8 bit the bottom 2 bits should be connected to Asynchronous active low reset signal Asserting this input sets all the control registers to their default value and res
21. measurement set MM mene AMMM MM rum WM Figure 8 NTSC Vertical blanking interval SingMai Electronics Timing Measurement RS 170A Field 1 Line 55 gt gt gt 7 Figure 9 NTSC Horizontal Timing FCC Color Ber Field 1 Line 58 100 5 63 9 Figure 10 NTSC 75 Colour bar PT8 User Manual Revision 0 9 Page 24 of 32 SingMai Electronics UL LU XX ex oos NN INC ILU Chrono Gein 106 1 as BU II RES EN X IM a 8 21 3 38 gt 328 Pulse K Foctor 21019 e 1 L ne 53 595 0 a1 130 14 0 anna AER lt gt Figure 12 NTSC K Factor PT8 User Manual Revision 0 9 Page 25 of 32 SingMai Electronics Multi Burst Wim gt 1410 Multi o J Y e 1 Line 55 56 1 IRE Flog 0 05 0 21 1 0 2 0 3 0 Positioning is in use B INE C Vi 4 O M E E E O vi coe Vi c EN EN E EN O Figure 14 NTSC Noise Spectrum Black PT8 User Manual Revision 0 9 Page 26 of 32 SingMai Electronics Noise Spectrum Wim gt Romp Field 1 Line S amp S mol itude 0 dB 714 mU MM NL C Ban
22. n pus peolg smd Gursyenby Durgijerib said grt spend 9221 Figure 6 PAL BG horizontal timing Page 17 of 32 al 2 2 gt tc 6 5 Qo H n SingMai Electronics Default Register Settings Table 7 shows the default register settings in hexadecimal for the video standards supported by PT8 On assertion of RESETn the NTSC M standard settings are loaded into the registers Note that if Control Register bit 7 is asserted Auto standard 1 then the hard wired values for NTSC M or PAL B D G will be used by PT8 depending on the line standard selected by Control Register 6 The hard wired values are those shown in Table 7 Also note that for the 525 line standard the horizontal timing values wrap at 1715 6B3 and the vertical values at 524 0 20C For the 625 line standard the horizontal timing values wrap at 1727 6BF and the vertical values at 624 0 270 00 Contol1 40 40 60 20 00 00 2 01 2 00 00 00 00 00 00 O 02 Control3 60 60 60 60 60 60 Timing registers 03 H Phase1 2A 524 22A 504 2 00 00 00 00 00 00 O ELSE E 9060 1806 2 VPhase2 ____ 2 Dil sen bl i 3 mimm 09 Active picture endi
23. nc pulse FE width nominally 4 7us 11 bit value HSyncend2 2 0 HSyncend1 7 0 0F H starti start 1 Delay between H Phase reset and start of horizontal blanking 10 R W Increments of 1 27MHz Maximum value 1715 or 1727 ew TT insan depending on the line standard 525 625 respectively 11 bit Hblankstart2 2 0 Hblankstart1 7 0 PT8 User Manual Revision 0 9 Page 13 of 32 SingMai Electronics Register Register Name R W Bit Description Offset Value Pedestal start 1 RW Delay between H Phase reset and start of pedestal insertion 14 Pedestal start 2 R W for 525 line standards only Increments of 1 27 2 Maximum value 1715 11 bit value Pedestalstart2 2 0 Pedestalstart1 7 0 Pedestal end 1 Delay between H Phase reset and end of pedestal insertion for 525 line standards only Increments of 1 27MHz Maximum value 1715 Pedestal Pedestal start Pedestal end 2 1 27 2 is the pedestal insertion pulse width nominally 52us 11 bit value Pedestalend2 2 0 Pedestalend1 7 0 Equalising1 end 2 Equalising2 2 ome end 1 Delay between H Phase reset and end of horizontal blanking Increments of 1 27MHz Maximum value 1715 or 1727 depending on the line standard 525 or 625 respectively H blank end H blank start 1 27MHz is the blanking width nominally 5208 11 bit value Position of t
24. ng occurs at the next clock edge following that enable For the write to occur reliably the address A 7 0 and data Din 7 0 must be stable and valid during the PT8 WRn pulse The minimum width of the PT8 pulse is 80ns for a 27 2 clock The address input also selects the register data that is presented on the Register out 7 0 bus This output is independent of the other control signals or the Clk27 clock Latch Data EH y A 0 i A XTAL 27M Generated write enable 1 E Din 0 Valid aa 7 0 Register nut A Il Figure 4 Control interface Timing PT8 User Manual Revision 0 9 Page 11 of 32 SingMai Electronics Register descriptions Table 6 lists all of the control and status registers All of the registers are 8 bit wide although some are concatenated together to create longer words Unused register bits read back as Zeros Note that if Control Register bit 7 is asserted Auto standard 1 then the hard wired values for NTSC M or PAL B D G will be used by PT8 depending on the line standard selected by Control Register 6 and only the Control registers will affect the PT8 The hard wired values are those shown in Table 7 The registers may still be written to and read from in Auto Standard condition Please note that some registers can be set to values that are illegal and will produce invalid outputs Refer
25. on For 625 lines the elements need to be selected according to Table 5 Line No s Pattern Element 1 22 311 312 Fsync F1 1 313 335 624 625 Fsync F2 2 23 310 75 Bars F1 3 336 623 75 Bars F2 4 Table 5 BT656 625 line selection PT8 User Manual Revision 0 9 Page 8 of 32 SingMai Electronics Technical Overview A simplified block diagram of the PT8 PAL encoder is shown in Figure 3 PAL switch BT656 9 0 9 0 Bruch blanking NTS Frame 27 2 Composite Sync Y Cb Cr 27MHz Shaping and Burst ein Bruch blanking NTSC Frame Gate PAL switch Standard DPD 27MHz WI lt 4 Chroma Burst Amplitude Data in Address cs WR Data out Figure 3 PT8 Block Diagram The input to the encoder is an 8 or 10 bit BT656 formatted data stream and associated 2 MHz clock If the input is 8 bits the bottom 2 bits should be tied to logic 0 The 656 interface block identifies and extracts the TRS codes from the stream and demultiplexes and co times the Y Cb Cr data The TRS codes are also examined for the correct parity and if an error is found it is flagged and reported to the Status register The 27MHz clock and the frame and active video signals are used to synchronise a sync pulse generator SPG The principal purpose of the SPG is to generate a compatible composite sync output but it also generates the PAL switch signal 7 8 2 the Bruch Blanking se
26. quence for PAL burst blanking the Burst gate signal for inserting the colour burst into the output data and the video blanking pulse The Y Cb Cr data is conditioned to produce Y U V signal amplitudes before being interpolated from 4 2 2 format to 8 8 8 format 27 MHz sample rate The luminance and chrominance are interpolated using 47 tap FIR filters with a bandwidth of 5 5MHz for the luma and 1 5MHz for the chroma The 27MHz clock also drives a 32 bit ratio counter which generates a precise subcarrier frequency for the selected standard An 11 bit phase word from this ratio counter addresses 12 bit wide Sin and Cos look up tables To save on memory only one quadrant of the Sin and Cos tables are stored and the addressing and data is modified to generate the other three quadrants The resulting Sin and Cos data is then multiplied by the U and V data during the active video period and a shaped Burst Gate pulse 15 used to insert the colour burst PT8 User Manual Revision 0 9 Page 9 of 32 SingMai Electronics The colour frame output of the SPG ensures the burst is correctly inhibited whilst the PAL switch output of the SPG switches the 135deg and 225deg phase increments in the correct sequence For NTSC it is possible to add in a phase offset hue The resulting U sin 2rrfsc t V cos 2nfsc t data is added together to create the chrominance signal which has blanking added as well as programmable gain The interpolated luminance
27. rd 525 625 respectively 11 bit value HPhase2 2 0 HPhase1 7 0 05 VPhasei RW Delay between BT656 1 gt 0 transition of FFlag and SPG vertical V Phase 2 R W counter Increments of horizontal lines Maximum value 524 eet or 624 depending on the line standard 10 bit value INE Gu lu BEN of the digital blanking Value 0 is the first active pixel start 1 BEEN _ the TRS SAV Increments of 1 27MHz Maximum value Active picture 1715 or 1727 depending on the line standard 525 or 625 start 2 respectively 11 bit value _ 2 2 0 Active picture start1 7 0 Active P PL BEEN of the digital blanking Nominally set to 1440 active 1 7 for standard BT656 inputs Increments of 1 27MHz Active picture R W Maximum value 1715 or 1727 depending on the line standard 2 525 or 625 respectively 11 bit value i ive picture end1 7 0 Sync start1 start 1 f Delay between H Phase reset and start of horizontal sync H Sync start 2 Increments of 1 27MHz Maximum value 1715 or 1727 depending on the line standard 525 or 625 respectively 11 bit value HSyncstart2 2 0 HSyncstart1 7 0 02 HSyncend 1 RW Delay between H Phase reset and end of horizontal sync H Sync end 2 R W pulse Increments of 1 27MHz Maximum value 1715 or 1727 depending on the line standard 525 or 625 respectively H Sync end H Sync start 1 27MHz is the horizontal sy
28. with the rising edges aligned If the second DAC is not to be used then the DAC can be clocked with 27MHz and the dac igsel is connected to 0 or 1 depending on the DAC to be used The current output of the DAC is connected to a resistor to convert it to a voltage and fed to a buffer amplifier the Analog Devices ADA4412 This device provides a 2x gain so we can drive a series 75Q resistor for the correct termination and also provides a high performance low pass filter to reconstitute the DAC output and remove out of band components Resistors VH1 and VR3 provide nominal gain adjustment for the 2 DACs Note that the PT8 has no sinx x correction as it has 27MHz over sampling on its output However there is a small droop in the output above 4 8MHz The over sampling filters have a bandwidth of 5 5MHz luma channel but a small analogue compensation circuit could be needed if the full 5 5MHz flatness is to be achieved PT8 User Manual Revision 0 9 20 of 32 ICS n TI Tale S 30 9 32245 eee 0 ea EEE 2904 O9P 1845 Sotuo4399 3 5 TIJHON 1 YI 081338 33375 73501 214 1353481 2412 1961 1912 Jamol 14 ecays4 247080 180 280 1701 247980 580 247980 280 280 680 594615 2478180 nn 2471180 147980 m ind 3149514
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