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GN4124 x4 Lane PCI Express to Local Bridge - Digi-Key

1. Group Pin No No of Pin Name 1 0 Description Global A9 1 TDI JTAG Test Data Input Test Interface LVCMOS 3 3V input pull up F10 1 TMS l JTAG Test Mode Select Input LVCMOS 3 3V input pull up F11 1 TCK l JTAG Test Clock LVCMOS 3 3V input B12 1 TRST I JTAG Test Reset LVCMOS 3 3V input hysteresis pull up A14 1 TDO Oo JTAG Test Data Output LVTTL 3 3V output 6mA tristate D6 1 SCAN EN l Scan Enable Tied LOW for normal operations LVCMOS 3 3V input pull down E6 1 TEST_EN I Test Mode Enable Tied LOW for normal operations LVCMOS 3 3V input pull down A15 1 PLL_TEST_OUT VO PLL Test Output No connect for normal operations LVCMOS 3 3V bidirectional 4mA tristate Global B11 1 SCLK 1 0 Two wire Clock port 2 Wire LVCMOS 3 3V bidirectional 4mA tristate Interface C12 1 SDATA yo Two wire Data port LVCMOS 3 3V bidirectional 4mA tristate Global A6 B7 B6 C7 16 GPIO 15 0 yo General Purpose Input Output General F7 C8 A7 B9 LVCMOS 3 3V bidirectional 4mA tristate Purpose A10 A11 E11 Interface A13 D9 C10 D11 E12 Global A5 B5 C5 E7 8 DBG 7 0 l Debug Bus Port Tied LOW for normal Debug D7 B4 C6 A4 operations Interface LVCMOS 3 3V input pull down GN4124 x4 Lane PCI Express to Local Bridge Data Sheet 48407 1 May 2009 gennum 11 of 31 Proprietary amp Confidential Group
2. 3 1 3 Process Qualification sss enne nennen sinn n nete nr nns nnn n tenen nns 3 1 4 Product Qualification Approach sssssseeee ene enne eene enne nnns 3 2 Reliability Qualification Stresses sssssseeee enne eene nnnm 4 2 1 Environmental Tests ccccccccececeeeeeeeeeae cece ee eeceeaeeeeeeeseceeaaeeeeeeeseseaaaeceeeeesesecaeaeeeeseesenneeaeees 4 2 2 Electrostatic Discharge and Latch Up Tests ssssssee mee 5 5E Snc a ic cc ccscccaesisccecnencsnadeutesdccs cadena isetccnnsantaicads E E 6 GN4124 GN4121 2 of 6 Reliability Qualifcation Report GENDOC 052220 2 10 Apr 2014 Proprietary amp Confidential 1 Device Specifics 1 1 Manufacturing Summary Table 1 Manufacturing Summary Gennum Device Codes GN4124 GN4121 Silicon Fab Technology UMC 0 13um Assembly House ASE K Package Type 17mm x 17mm LBGA 1 2 Product Information The GN4124 is a four lane PCI Express to local bus bridge that is designed to work as a companion for FPGA devices to provide a complete bridging solution for general applications In addition to a 4 lane PCI Express compliant PHY It provides pin efficient local bus interface for easy attachment to popular low cost FPGA devices Uses SSTL I O for high speed data transfer Live on power up enables auto detection without FPGA activity FPGA bitstream loader allows easy configuration of the attached FPGA through PCle
3. X 050 Dfferental Sigral VJ 0 50 Ub t t D DU 1 1 1 1 D t D D t 0 2 01 020 01 02 03 04 05 06 OF 08 O03 10 11 12 Unit Intervals Figure 3 2 Typical Non Transition Signal Eye De emphasis Disabled Default Drive Setting ss SS eee o50 0257 Dfferental Sigral V e 8 JI2h s m M s n n nog mma p nr vsm Mi U2 t g 1 1 1 1 1 1 1 D D 02 01 020 01 02 03 04 05 06 07 08 O03 10 11 12 Unit Intervals GN4124 x4 Lane PCI Express to Local Bridge 20 of 31 Data Sheet 48407 1 May 2009 genn um Proprietary amp Confidential 3 4 2 PCI Express Receiver Characteristics Table 3 7 PCI Express Receiver Characteristics Symbol Description Min Typical Max Unit Voltage Parameters VRX DIFFp p Differential input voltage 170 1200 mV peak to peak VRX IDLE DET DIFFp p Differential input threshold voltage 65 235 mV peak to peak to assert TxldleDetect output VRX CM AC Receiver common mode voltage for 0 150 mV AC coupling TRX RISE TRX FALL Rise time Fall time of RxP RxN 160 ps inputs ZgRX DIFF DC Differential input impedance DC 80 100 120 Q ZRX COM DC Single ended input impedance 40 50 60 Q ZRX COM INITIAL DC Initial input common mode 5 50 60 Q impedance DC ZRX COM HIGH IMP DC Powered down input common mode 200k Q impedance DC RLRX DIFF Receiver D
4. Hj gmDgmr Gennum Corporation assumes no liability for any errors or omissions in this document or for the use of the circuits or devices described herein The sale of the circuit or device described herein does not imply any patent license and Gennum makes no representation that the circuit or device is free from patent infringement PCle and PCI Express mark are registered trademarks and or service marks of PCI SIG All other trademarks mentioned are the properties of their respective owners GENNUM and the Gennum logo are registered trademarks of Gennum Corporation O Copyright 2009 Gennum Corporation All rights reserved www gennum com GN4124 x4 Lane PCI Express to Local Bridge 31 of 31 Data Sheet 48407 1 May 2009 f gennum Proprietary amp Confidential ra P SEMTECH GENNUM PRODUCTS GN4124 GN4121 Reliability Qualification Report Reliability Qualifcation Report GENDOC 052220 2 10 Apr Proprietary amp Confidential Revision History Version ECR ECO Date Modifications Changes 0 151544 Mar 2009 New document 1 151730 Apr 2009 HTOL 2000hrs data added and GN4121 included as qualified Updated formatting minor corrections additional 2 ECO 018675 Mar 2014 qualification data to support PCN for bond wire change Contents UIS e Specifies cenere dea eera aa EKE ARAR ARa EEEE 3 1 1 Man facturing SUMMA icara eee A evn nee ec dances 3 12 Product Informati n T
5. May 2009 gennum 13 of 31 Proprietary amp Confidential Group Pin No No of Pin Name 1 0 Description Local Bus P10 N9 2 P WR REQ 1 0 Oo PCle Write Request Inbound Buffer SSTL 1 8V output Request Status N11 N12 2 P WR RDY 1 0 PCle Write Ready SSTL 1 8V input with ODT N6 1 RX ERROR Receive Error SSTL 1 8V input with ODT P11 P12 2 VC RDY 1 0 Oo Virtual Channel Ready Status This provides a VC RDY output to indicate the DL UP status of the Virtual Channel This can be used to provide a synchronous reset to the external application in the event one of the Virtual Channels goes down e g hot reset initiated by PCle host SSTL 1 8V output Local Bus B16 C16 E16 16 L2P DATA 15 0 Parallel Transmit Data Local PCle F16 J16 K16 SSTL 1 8V input with ODT Outbound L16 N16 C15 Data D15 E15 F15 J15 L15 M15 N15 H14 1 L2P DFRAME Transmit Data Frame SSTL 1 8V input with ODT H16 1 L2P VALID Transmit Data Valid SSTL 1 8V input with ODT G14 1 L2P EDB End of Packet Bad Flag When a packet is considered bad and is terminated with EDB SSTL 1 8V input with ODT G16 G15 2 L2P_CLKp Transmitter Source Synchronous Clock L2P_CLKn SSTL 1 8V input differential with ODT Local Bus F14 1 L2P_RDY Tx Buffer Full Flag Outbound SSTL 1 8V output Buffer Status J14 K14 2 L_WR_RDY 1 0 Local to PCle Write SSTL 1 8V output L14 M14 2 P_RD_D_RDY 1 0 P
6. Proprietary amp Confidential live 5 S signals GN4124 26 SSTL buffers DC electrical characteristics 18 V virtual channel support 6 GN4124 x4 Lane PCI Express to Local Bridge Data Sheet 48407 1 May 2009 gennum 30 of 31 Proprietary amp Confidential DOCUMENT IDENTIFICATION DATA SHEET The product is in production Gennum reserves the right to make changes to the product at any time without notice to improve reliability function or design in order to provide the best product possible CAUTION ELECTROSTATIC SENSITIVE DEVICES DO NOT OPEN PACKAGES OR HANDLE EXCEPT AT A STATIC FREE WORKSTATION GENNUM CORPORATE HEADQUARTERS 4281 Harvester Road Burlington Ontario L7L 5M4 Canada Phone 1 905 632 2996 E mail corporate gennum com Fax 1 905 632 2055 www gennum com OTTAWA 232 Herzberg Road Suite 101 Kanata Ontario K2K 2A1 Canada Phone 1 613 270 0458 Fax 1 613 270 0429 CALGARY 3553 31st St N W Suite 210 Calgary Alberta T2L 2K7 Canada Phone 1 403 284 2672 UNITED KINGDOM North Building Walden Court Parsonage Lane Bishop s Stortford Hertfordshire CM23 5DB United Kingdom Phone 44 1279 714170 Fax 44 1279 714171 INDIA 208 A Nirmala Plaza Airport Road Forest Park Square Bhubaneswar 751009 India Phone 91 674 653 4815 Fax 91 674 259 5733 SNOWBUSH IP A DIVISION OF GENNUM 439 University Ave Suite 1700 T
7. PRODDOCO004748 The Qualification Report has been reviewed and approved by design product engineering and reliability engineering GN4124 GN4121 3 of 6 Reliability Qualifcation Report GENDOC 052220 2 10 Apr 2014 Proprietary amp Confidential 2 Reliability Qualification Stresses 2 1 Environmental Tests Table 2 Environmental Tests Stress Conditions Duration Qualification Vehicle Sample Result Size High JESD22 A108 2000 hrs GN4124 80 Pass Temperature Operating Life Tj 2 125 C Voc 2 Veomax JESD22 A104 1000 cycles Bridged to 352 LBGA 25 each Pass Temperature MSL Preconditioning Package Qual Tromisdots Cycling 55 C to 125 C Condition B HAST JESD22 A118 100 hours Bridged to 256 PBGA 77 Pass unbiased MSL Preconditioning Test Vehicle 130 C 85 RH Moisture J STD 020 192hrs Bridged to 352 LBGA 75 Pass Sensitivity Package Qual Level MSL3 30 C 60 pos JESD22 A102 96hrs Bridged to 352 LBGA 22 Pass 121 C 10096 RH 2ATM Package Qual JESD22 A104 1000 cycles GN4124 Cu wire 7 Pass Temperature MSL Preconditioning Cycling 55 C to 125 C Condition B HAST JESD22 A118 100 hours GN4124 Cu wire 77 Pass unbiased MSL Preconditioning 130 C 85 RH Moisture J STD 020 192hrs GN4124 Cu wire 77 Pass Sensitivity Level MSL3 30 C 60 GN4124 GN4121 4of6 Reliability Qualifcation Report GENDOC 052220 2 10 Apr 2014 Proprietary amp Confidential 2 2 Electrostatic Discharge and Latch Up Tests Table 3 E
8. Bridge Data Sheet 48407 1 May 2009 gennum 12 of 31 Proprietary amp Confidential Group Pin No No of Pin Name 1 0 Description PCI Express T2 J1 H1 A2 4 PERn 3 0 PCle Receive Bus Lane A Link CML PCle Receive piv Note PERp 3 0 PERn 3 0 each receiver lane Input to the i ira device can be connected using either the indicated polarity or inverted polarity Inverted polarity may be chosen in order to simplify the PCB layout by avoiding signal crossover and additional PCB vias The GN4124 will automatically detect and compensate for polarity inversion during link training R2 K1 G1 B2 4 PERp 3 0 PCle Receive Bus Lane A CML Local Bus P14 R16 2 LCLK LCLKn Oo Local Bus Clock SSTL 1 8V differential K6 L4 M4 M5 4 LCLK MODE 3 0 Selects the clock mode LVCMOS 3 3V input pull down P16 1 RSTOUT18 Oo Reset Output 1 8V Active LOW CMOS 1 8V output Local Bus P9 1 P2L RDY Rx Buffer Full Flag PCle to Local SSTL 1 8V input with ODT Inbound Data P5 R4 R5 R6 16 P2L_DATA 15 0 Oo Parallel Receive Data R9 R11 R12 SSTL 1 8V output R13 T5 T6 T7 T8 T9 T10 T11 T13 R7 1 P2L DFRAME Oo Receive Frame SSTL 1 8V output P7 1 P2L VALID Oo Receive Data Valid SSTL 1 8V output P8 R8 2 P2L CLKp O Receiver Source Synchronous Clock P2L CLKn SSTL 1 8V output differential GN4124 x4 Lane PCI Express to Local Bridge Data Sheet 48407 1
9. PCI Special Interest group at 503 619 0569 or visit their Web site at http www pcisig com If you are not familiar with the PCI Express specification a good place to start is by reading one of several books on the subject One of the most popular is PCI Express System Architecture written by Tom Shanley Don Anderson and Ravi Budruk published by MindShare Inc GN4124 x4 Lane PCI Express to Local Bridge 8 of 31 Data Sheet 48407 1 May 2009 gennum Proprietary amp Confidential 2 Pin Descriptions 2 1 Pin Assignments Figure 2 1 GN4124 Pin Assignment 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SPRI PLL TEST A DBGO DBG7 GPIO15 GPIO9 me m GPIO7 GPIO6 DONE GPIO4 OUT r m m lll o Oe Bo ie LL NES G PECLKINp H 9 PECLKINn E i L LCLK MODE2 d oa o Soc LEE 8 D22 P2L_ P2L_ P2L_ P2L_ P2L_ R DATA14 DATA13 DATA12 DFRAME P2L CLKn DATA11 T P2L P2L P2L P2L P2L_ P2L_ DATA7 DATA6 DATAS DATA4 DATA3 DATA2 1 2 3 4 5 6 7 8 9 10 GN4124 x4 Lane PCI Express to Local Bridge zm Data Sheet E 48407 1 May 2009 gennum SPRI XI SPRI SCK TRST SWAP STATUS SPRI_ LB_REF_ L2P_ CONFIG SPRATA CLK MO DATA7 LB REF L2P_ BHO CLK MI DATA6 GPIO5 GPIOO L2P_ L2P_ NC L2P_EDB L2P_ DFRAME Y P RD L2P_ D_RDY1 DATA2 NC P RD L2P_ D_RDYO DATA1 P_WR P_WR TX_ L2P_ _RDY1 RDYO ERROR DATAO vc vc RDY1 RDYO EELK P2L P2L P2L NC DATA10 DATA9 DATA8 P2
10. The GN4121 is a single lane PCI Express to local bus bridge that is designed to work as a companion for FPGA devices to provide a complete bridging solution for general applications In addition to a PCI Express compliant PHY interface the GN4121 contains the link and transaction layers and an applications interface that is ideally suited to FPGA interfacing using a small number of pins 1 3 Process Qualification GN4124 GN4121 are manufactured in UMC 0 13um Logic Process Technology The UMC qualification report is accepted In Agile id GENDOC 036661 1 4 Product Qualification Approach GN4124 four lane PCI Express was chosen as the main test vehicle for qualification GN4121 is considered a subset of GN4124 using the same back end and fab process but with only a single lane PCI Express bus GN4121 Reliability Qualification has been bridged to GN4124 due to its similarities in architecture and design Package reliability stress experiments have been bridged to 352 LBGA 35x35mm body size Au wire ASE package qualification report which covers the GN4124 package envelope 17x17mm LBGA package The 35x35mm 352 LBGA ASE K Package Qualification Report is accepted in Agile ID GENDOC 047723 PCN 000163 was introducted with a change to copper wire from gold wire additional reliability stress experiments have been performed in a 256 LBGA 17x17mm GN4124 device as the test vehicle The ASE K Cu wire Package Qualificaiton Report is accepted in Agile ID
11. addition to a 4 lane PCI Express compliant PHY interface the GN4124 contains the link and transaction layers and an applications interface that is ideally suited to FPGA interfacing using a small number of pins Since the PCI Express transaction link IP is hard wired into the GN4124 there is no need to license PCle IP The level of integration and very low power operation of the GN4124 make it an ideal alternative to using a PIPE PHY where IP licensing and the cost of FPGA resources and power consumption is unattractive by comparison Using the GN4124 allows FPGA resources to be spent on what differentiates the product rather than on implementing the PCI Express protocol 1 1 Features e 4Lane PCI Express interface Complies with PCI Express Base Specification 1 1 On chip PHY transaction and link layer eliminates the cost of IP licensing Two hardware virtual channels supported Payload size of up to 512 bytes with up to three outstanding transactions in each direction Supports 3x64 bit base address registers Provides flexible power management capability e Provides pin efficient local bus interface for easy attachment to popular low cost FPGA devices Uses DDR SSTL I O for high speed data transfer up to 800MB s GN4124 x4 Lane PCI Express to Local Bridge www gennum com 4 of 31 Data Sheet 48407 1 May 2009 Proprietary amp Confidential FPGA source code provided for 64 bit master target read write buses for e
12. established GN4124 x4 Lane PCI Express to Local Bridge Data Sheet 48407 1 May 2009 gennum 15 of 31 Proprietary amp Confidential 3 Electrical Characteristics 3 1 Absolute Maximum Ratings Table 3 1 Absolute Maximum Ratings Parameter Value Core Supply Voltage 0 5V to 1 8 VDC SSTL IO Supply Voltage 0 5V to 42 5 Vpc LVCMOS IO Supply Voltage 0 5V to 44 6 Voc Input ESD Voltage HBM 2kV Storage Temperature Range 50 C lt T lt 125 C Solder Reflow Temperature 260 C 3 2 Operating Conditions Table 3 2 Operating Conditions All electrical characteristics are valid over the range of these operating conditions unless otherwise noted Parameter Symbol Conditions Min Typ Max Units Notes Core Supply Voltage on pins Vcore 1 14 1 2 1 26 V 5 VDDC VDD_PCIE VDDAUX PLL_AVDD PCIE_VDDA SSTL IO Supply Voltage on Vwcco18 Eus 1 71 1 8 1 89 V 5 pins VCCO18 LVCMOS IO and 3 3V Core Vvcco33 3 0 3 3 3 6 V 10 Supply Voltage pins VCCO33 VDDW VDDP Operating Temperature TA Ambient 0 25 85 C Range GN4124 x4 Lane PCI Express to Local Bridge zm 16 of 31 Data Sheet E ennum 48407 1 May 2009 9 Proprietary amp Confidential 3 3 DC Electrical Characteristics Table 3 3 DC Electrical Characteristics Power and current limits listed have been derived from design and characteristics data They are not 100 tested in
13. production Parameter Symbol Conditions Min Typ Max Units Notes Power Consumption Pp PCle x4 650 950 mW 1 LCLK 200MHz PCle x4 600 mW 2 LCLK 100MHz PCle x1 475 mW 3 LCLK 100MHz Total Core Supply Current on IcoRE 1104 mA pins VDDC VDD PCIE See Note 5 VDDAUX PLL AVDD PCIE VDDA SSTL IO Supply Current lvcco18 3406 mA See Note 5 LVCMOS IO and 3 3V Core lycco33 907 mA Supply Current pins VCCO33 See Note VDDW VDDP 5 1 Data is based on an application circuit equivalent to that used on the GN4124 RDK board Gullwing typical operating conditions PCle negotiated to 4 lanes default PCle PHY settings 200MHz local bus operation and with concurrent data traffic at 7596 bus utilization Doesn t include power dissipated by components outside of the GN4124 2 See Note 1 Typical operating conditions 100MHz local bus operation 3 See Note 1 Typical operating conditions 100MHz local bus operation PCle negotiated to 1 lane 4 This information is intended to guide power supply design Data is based on an application circuit equivalent to that used on the GN4124 RDK board Gullwing typical operating conditions 200MHz local bus operation and with concurrent data traffic at 75 bus utilization 5 Maximum supply current will vary greatly depending on the application circuit and device usage A specific application s maximum current can be be predicted by measuring
14. should be treated as asynchronous 2 Local bus control inputs are synchronized by the GN4124 Failure to meet setup time will simply delay the cycle in which the change is recognized Table 3 10 Local Bus Timing for Source Synchronous SSTL Input Signals Over Specified Operating Conditions TARGET SPECIFICATION Input signals include L2P_CLK L2P DATA 15 0 L2P_DFRAME and L2P VALID Symbol Description Min Max Units Ti p cik L2P_CLK Cycle Time or Unit Interval UI Ticik ns UTi2p ci L2P CLK input jitter tolerance cycle to cycle 100 ps Ti2P ciK Lock L2P CLK input lock time 1380 Cycles TLCLK to L2P_CLK Delay from LCLK to L2P_CLK 0 Ticik ns Ts Sample point for data relative to L2P CLK L2P CLK 909 rising and falling Tsy L2P DATA Required input set up time to L2P_CLK Ts 400 ps rising and falling Ty L2P DATA Required input hold time from L2P CLK Ts 400 ps rising and falling Table 3 11 Local Bus Timing for Source Synchronous SSTL Output Signals Over Specified Operating Conditions TARGET SPECIFICATION Output signals include P2L CLK P2L_DATA 15 0 P2L_DFRAME and P2L VALID Symbol Description Min Max Units Tra CLK P2L CLK Cycle Time or Unit Interval UI Ticik ns TicLK to P2L CLK Delay from LCLK to P2L CLK Ticik 2 1 2 Ticik 2 1 2 ns Tsy P2L_DATA Output set up time to P2L_CLK rising and falling 1200 ps Ty P2L DATA Output hold time from P2L CLK rising an
15. source for the LCLK PLL 0 LB REF CLK oscillator 20 40MHz This is recommended for low and predictable LCLK clock jitter 1 125MHz clock generated from the PCI Express link GN4124 x4 Lane PCI Express to Local Bridge 24 of 31 Data Sheet 48407 1 May 2009 gennum Proprietary amp Confidential 4 Overview A block diagram of the GN4124 is depicted in Figure 4 1 Figure 4 1 GN4124 Block Diagram DDR TX DES Buffers Local Bus Buffer Status and to FPGA Throttle Control DDR Rx SER Buffers Local um Clock MSI Type 0 Ctrl Extended Control Boot Config Reg Master Each of the internal blocks is described in detail in the GN412x PCI Express Family Reference Manual They are The PCI Express link is described in PCI Express Link section of the GN412x PCI Express Family Reference Manual This includes a description of the PCI Express related configuration registers The Local bus is described in Local Bus Interface section of the GN412x PCI Express Family Reference Manual The interrupt controller is described in Interrupt Control Unit section of the GN412x PCI Express Family Reference Manual The boot master mode of the 2 wire controller is described in Initialization from a 2 Wire EEPROM section of the GN412x PCI Express Family Reference Manual General purpose master target mode of the 2 wire controller is described in 2 Wire Interface section of the GN412x PCI Express Family Reference M
16. x1 PCle mode Therefore no design or PCB changes are required The GN4124 will be functionally identical to the GN4121 in a GN4121 based x1 PCle application Formal End of Life Notification will follow upon review of customer feedback Part Number s Affected Customer Part Number s Affected D N A GN4121 CBE3 Replacement or Alternate Part Number s C N A or Not Offered GN4124 CBE3 Last Time Buy LTB NA Must Accept Final NA Date Delivery by Sample Availability Now Qualification Report of Alt Part Availability of Alt Part Supporting Documents for Alternate or Replacement parts Attachments Now 1 GN4124 CBE3 Datasheet GENDOC 048407 2 GN4124 CBE3 Reliability Qualification Report GENDOC 052220 Semtech Corporation 200 Flynn Road Camarillo e Ca 93012 Phone 1 805 498 2111 5 ADVANCED PRODUCT DISCONTINUANCE f NOTIFICATION SENITECH Date March 10 2015 poy Additional Provisions We regret the inconvenience and impact this notice may cause your company Semtech s sales marketing and distribution personnel stand ready to assist you in placing your company s final orders or in providing the product information you require For product inquiries or purchase order information please contact your local Semtech sales representative Issuing Authority Semtech Business Unit SIPG Luis Blanco Semtech Corporation Sr Manager Quality Engineering E
17. 00 0 36 i N i i a Ball Diameter Mold Thickness a I I I a xA 7 7 n 0 50 054 T EC SEATING PLANE re j b 8S do GN4124 x4 Lane PCI Express to Local Bridge 27 of 31 Data Sheet gennum 48407 1 May 2009 Proprietary amp Confidential 5 2 Packaging Data Table 5 1 Packaging Data Parameter Value Package Type 17mm x 17mm 256 ball BGA Package Drawing Reference Moisture Sensitivity Level 3 Junction to Air Thermal Resistance 0j at zero airflow 27 CAN Junction to Air Thermal Resistance j a at 1m s airflow 24 CAN Junction to Air Thermal Resistance 6 5 at 2m s airflow 22 CAN Junction to Case Thermal Resistance 6 5 5 C W Psi 11 0 C W Pb free and RoHS compliant Yes 5 3 Ordering Information Table 5 2 Packaging Data Part Number Package Temperature Range GN4124 CBE3 256 BGA 0 C to 85 C GN4124 x4 Lane PCI Express to Local Bridge z 28 of 31 Data Sheet 48407 1 May 2009 gennum Proprietary amp Confidential Index Numerics 2 wire serial controller 7 A absolute maximum ratings electrical characteristics 16 application layer PCI Express 7 C configuration loader FPGA on the fly 6 D data sheet usage 7 DC electrical characteristics 17 E electrical characteristics absolute maximum ratings 16 DC 17 DC LVCMOS buffers 18 DC SSTL buffers 18 local bus timing 22 operating conditions 16 PCIe receiver 21 PCIe transmitter 18 F features
18. 4 FPGA on the fly configuration loader 6 G Gennum contact information 8 getting answers to PCI Express related questions 8 getting help from Gennum 8 GN4124 signals 26 I I2C serial controller 7 interrupt controller 7 introduction 4 L live on power up 5 local bus interface 6 local bus timing electrical characteristics 22 local clocks pins settings 24 LVCMOS buffers DC electrical characteristics 18 0 operating conditions electrical characteristics 16 ordering information 28 overview 25 P package dimensions 27 packaging and ordering information 27 packaging data 28 PCI Express application layer 7 PCI Express contact information 8 PCI Special Interest Group 8 PCIe receiver electrical characteristics 21 PCIe transmitter electrical characteristics 18 pin descriptions 10 pins global 10 global 2 wire interface 11 global debug interface 11 global general purpose interface 11 global serial programming interface 12 global test interface 11 ground 15 local bus 13 local bus inbound buffer request status 14 local bus local PCIe outbound data 14 local bus outbound buffer status 14 local bus PCIe to local inbound data 13 no connect 15 PCIe link PCIe receive input from the device 13 PCIe link PCIe transmit output from the device 12 PCIe link PCIe x4 PHY interface 12 power 15 power up GN4124 x4 Lane PCI Express to Local Bridge Data Sheet 48407 1 May 2009 gennum 29 of 31
19. 4281 Harvester Road Semtech Contact Info rion ON L7L 5M4 Iblanco semtech com Office 905 632 7253 Fax 905 632 2055 FOR FURTHER INFORMATION amp WORLDWIDE SALES COVERAGE _hitp www semtech com contact index html support Semtech Corporation 200 Flynn Road Camarillo Ca 93012 Phone 1 805 498 2111 PCI gennum EXPRESS GN4124 x4 Lane PCI Express to Local Bridge Data Sheet GN4124 x4 Lane PCI Express to Local Bridge www gennum com Data Sheet 48407 1 May 2009 1 of 31 Proprietary amp Confidential Revision History Version ECR Date Changes and Modifications 2 151915 May 2009 Created new document describing functionality and the register map for GN4124 amp GN4121 devices These common sections have been removed 1 151527 May 2009 It is now a Data Sheet Added the content of the document GN4124 x4 PCI Express to Local Bus Bridge User Manual Document ID 47719 to this data sheet This User Manual is no longer a stand alone document Changed some parameters in Table 2 1 EEPROM EN Table 3 2 Table 3 3 Table 5 2 and Table 13 2 Changed Figure 4 2 Figure 6 2 Figure 7 1 and Figure 9 16 Modified descriptions in 9 4 Operation 9 7 3 FCL FPGA Configuration and 9 7 4 FCL FSM FPGA Configuration Changes to registers to PCI BARO LOW PCI BAR2 LOW PCI BAR2 HIGH PCI BAR4 LOW PCI BAR4 HIGH PCI SUB VENDOR PCI SUB SYS PCIE DEVICE CAP PCIE DCR INT CTR
20. C noise on VREF may not exceed 2 of VREF 2 The termination voltage VTT should track the reference voltage VREF 3 4 PCI Express Electrical Characteristics 3 4 1 PCI Express Transmitter Characteristics Table 3 6 Transmitter Characteristics Symbol Description Min Typical Max Unit Voltage Parameters Vrx pirE Output voltage compliance typical swing Vrx pirrp peak to peak single 400 500 600 mV ended Vrx pirrpp peak to peak 800 1000 1200 mV differential VH Transmitter termination voltage 1 2 1 5 1 89 V VoL Low level output voltage Varr 1 5 VTX DIFFp V GN4124 x4 Lane PCI Express to Local Bridge 18 of 31 Data Sheet E ennum 48407 1 May 2009 9 Proprietary amp Confidential Symbol Description Min Typical Max Unit Vou High level output voltage Vor 0 5 VTX DIFFp V VTX DC CM Transmit common mode voltage 0 VTT VTX DIFFp 3 6 V VTX CM DCACTIVE Absolute Delta of DC Common Mode 100 mV IDLEDELTA Voltage During LO and Electrical Idle VTX DE RATIO De emphasized differential output 0 3 35 7 96 dB voltage V7X IDLE DIFFp Electric Idle differential peak voltage 20 mV VTX RCV DETECT Voltage change during Receive 600 mV Detection RL7X DIFF Transmitter Differential Return loss 10 dB RLtx cm Transmitter Common Mode Return 6 dB loss ZosE Single ended output impedance 40 50 60 Q ZTX DIFF DC DC Differential TX Im
21. Cle to Local Read Response Data Ready SSTL 1 8V output N14 1 TX_ERROR Transmit Error SSTL 1 8V output GN4124 x4 Lane PCI Express to Local Bridge Data Sheet 48407 1 May 2009 gennum 14 of 31 Proprietary amp Confidential Group Pin No No of Pin Name Pins 1 0 Description Power F5 K5 2 VDDW 3 3V R10 1 VREF vu 900mvV reference voltage for SSTL I O T14 1 PLL AVDD 1 2V PLL supply voltage D5 D8 D13 D16 E10 E13 F6 F12 F13 G12 H4 H15 J13 K15 L5 L6 L10 L13 M6 M10 M16 N8 N10 P6 P13 P15 T4 T12 28 VDDC 1 2V core power E1 K4 2 VDDP 3 3V H11 H12 J11 J12 L8 L9 M8 M9 8 VCCO18 Power for 1 8V I O E8 E9 F8 F9 4 VCCO33 Power for 3 3V I O Ground N13 1 PLL_AVSS PLL Ground This pin is internally connected to VSS and for noise isolation should not be connected to VSS externally Refer to the Gullwing RDK schematics and PCB layout for proper implementation A16 B15 C4 C14 D4 E4 G4 G6 G7 G8 G9 G10 G11 H6 H7 H8 H9 H10 H13 J4 J5 J7 J8 J9 J10 K3 K7 K8 K9 K10 K11 K12 L1 L11 L12 M7 M11 M12 N5 P4 R3 R15 T16 43 VSS Ground No Connect B3 D10 D14 E14 F4 G13 J6 K13 L7 M13 N4 N7 R14 T15 14 NC No Connect 1 Data Link Layer indicates that a connection with the upstream devices has been
22. L INT STAT INT CFGO 7 GPIO DIRECTION MODE GPIO OUTPUT ENABLE GPIO OUTPUT VALUE GPIO INT MASK GPIO INT MASK CLR Note formerly GPIO INT ENABLE GPIO INT MASK SET Note formerly GPIO INT DISABLE GPIO INT STATUS GPIO INT TYPE GPIO INT VALUE GPIO INT ON ANY and FCL CTRL D 151519 March 2009 Clarified output voltage and local bus timing in Table 3 6 and Table 3 11 C 150789 December 2008 Corrected pin assignments and definitions Updated electrical characteristics Corrected Figure 2 2 Updated Local Bus Interface clock range B 150182 August 2008 Corrected pin assignments part number and other updates A 148626 May 2008 New document Contents AU WAM OGL CH Oca C 4 Tuc m 4 1 2 Ive on POW ETH UD iones te in HERR e RR Dt tei dien AS 5 1 3 FPGA On the Fly Configuration Loader eee eeetenttenttenntennttnttnn 6 1 4 Local Bus Interface 1 5 Virtual Channel Support ethic e iei recidere needed cris 6 1 6 PCI Express Application Layer cssssssssssecsesssecseecssecseecssecseccssecseessecseecssecseesstecseesseesessnecneesees 7 127 Internat Controller ec 7 1 8 2 Wire Serial Controller reri teeenre bist iepei titia dece PER Quare eret 7 1 9 Data Sheet Usage D 7 1 10 Getting Help from Gennum runes A RAER RRR 8 GN4124 x4 Lane PCI Express to Loc
23. L P2L DATA1 DATAO 11 12 13 14 15 L2P_ DATA3 A Proprietary amp Confidential 16 L2P_ DATA15 L2P_ DATA14 L2P_ DATA13 L2P_ DATA12 L2P_ CLKp L2P_ VALID L2P_ DATA11 L2P_ DATA10 L2P_ DATA9 N uU zm 2d 8 c 16 2 2 Pin Descriptions Table 2 1 GN4124 Pin Descriptions Group Pin No No of Pin Name 1 0 Description Pins Global B8 RSTIN l Global Asynchronous Reset Active LOW LVCMOS 3 3V input hysteresis C9 RSTOUT33 0 Reset Output 3 3V Active LOW 3 3 V LVCMOS totem pole D12 LB REF CLK MI l Local Bus Reference Clock Crystal or Oscillator Input C13 LB REF CLK MO 0 Local Bus Reference Clock Crystal feedback output Functional mode only H3 J3 PCIE_VDDA P Clock Reference Analog Supply 1 2V G5 H5 PECLKINp l PCle Reference Clock Signal For a PCI Express PECLKINn add in card these signals should be driven by the card edge connector and AC coupled using 150nF capacitors E5 EEPROM EN l Used to report that EEPROM is present 1 present LVCMOS 3 3V input EEPROM EN should be tied HIGH to allow the internal GN4124 registers to load on power up from the EEPROM Refer to Initialization from a 2 Wire EEPROM from on what is required for EEPROM boot up options GN4124 x4 Lane PCI Express to Local Bridge Data Sheet 48407 1 May 2009 gennum 10 of 31 Proprietary amp Confidential
24. Pin No No of Pin Name 1 0 Description Pins Global A8 1 SPRI_CLK VO Serial Programming Interface FPGA Serial Configuration Loader Programming LVCMOS 3 3V bidirectional 12mA tristate Interface B10 1 SPRI DATAOUT yo Serial Programming Interface FPGA Configuration Loader LVCMOS 3 3V bidirectional 12mA tristate C11 1 SPRI_CONFIG y o Serial Programming Interface FPGA Configuration Loader LVCMOS 3 3V bidirectional 12mA tristate A12 1 SPRI DONE VO Serial Programming Interface FPGA Configuration Loader LVCMOS 3 3V bidirectional 12mA tristate B13 1 SPRI_XI_SWAP y o Serial Programming Interface FPGA Configuration Loader LVCMOS 3 3V bidirectional 12mA tristate B14 1 SPRI_STATUS yo Serial Programming Interface FPGA Configuration Loader LVCMOS 3 3V bidirectional 12mA tristate PCI Express A1 A3 C2 D2 16 VSS_PCIE G PHY VSS Link E3 F3 G2 H2 PCle x4 PHY J2 K2 L3 M3 interface N2 P2 T1 T3 B1 C3 D3 N3 6 VDD_PCIE P PHY VDD P3 R1 1 2V Core G3 1 VDDAUX P PHY VDDAUX 1 2V F1 1 VTT AB P PCle PHY transmit termination lanes A B Driven to voltage VTT 1 5V See Table 3 6 M1 1 VTT CD P PCle PHY transmit termination lanes C D Driven to voltage VTT 1 5V See Table 3 6 PCI Express N1 M2 E2 D1 4 PETn 3 0 Oo PCle Transmit Bus Lane A Link CML PCle Transmit Output from P1 L2 F2 C1 4 PETp 3 0 0 PCle Transmit Bus Lane A the device CML GN4124 x4 Lane PCI Express to Local
25. al 1 3 FPGA On the Fly Configuration Loader An FPGA bitstream may be downloaded from the host system over PCIe to the attached FPGA using the on chip FPGA configuration loader This eliminates the expense of a dedicated FPGA ROM and makes on the fly reconfiguration and firmware upgrades simple The ability to dynamically configure an attached FPGA over PCIe makes the GN4124 an ideal companion to all ranges of FPGA devices including large SerDes capable devices that require reconfiguration or firmware upgrades over PCIe 1 4 Local Bus Interface The local bus interface uses a combination of single and dual data rate SSTL I O to accomplish very high data rates in the fewest possible pins A singe data rate clock is used for SSTL control signals and separate dual data rate source synchronous clocking is used for the DDR SSTL data The SDR control signals operate at up to 200MHz and the DDR I O operate at up to 400MT s across 16 bits using a 200MHz DDR clock This provides 800MB s in each direction The local bus may operate asynchronously from the PCI Express rate In order to save power the local bus clock can operate at the lowest possible rate required by an application The local bus protocol facilitates four types of transactions e PCle to Local Target Writes A PCIe agent such as the host processor root complex writes data to the local bus e PCle to Local Target Reads A PCIe agent reads data from the local bus Reads are sp
26. al Bridge 2 of 31 Data Sheet gennum 48407 1 May 2009 Proprietary amp Confidential 1 11 Getting Answers to PCI Express Related Questions eee 8 2 Pin DOSCTIUPtlOMS le 9 2 1 Pim ASSIGNMENTS s ccascccssasccsscsscasssssesecsscesdaacasssasces ssecnesscescouseastosncsssssbaadesstasanschaeesensscassebiontitdaussuaneoeas 9 2 2 Pin Descriptions 5 5 eR tape Eee e HORE ENIMS IR SEHE REREN 3 Electrical Characteristics 3 1 Absolute Maximum Ratings scsssssdcssssssssesosscsnseseeconsscassscussnsscssconsvennnsoscesdsssstensesnvssosecsbsesdesiseens 16 3 2 Operating Conditions 0 sesssssssessssscseecseecseecsecsseecseecsescstecseecseeessesssecseecseeeseecstecseeesecseecasecaseess 16 3 3 DC Electrical Characteristics eee eenn tentent tenen tent tennttnnntennnti 17 3 4 PCI Express Electrical Characteristics 0 sssssssssecssscssscssecssecseecsccsscesseecsecsseesueesseecarseneerseense 18 3 4 1 PCI Express Transmitter Characteristics eese eee tenttentenntnnn 18 3 4 2 PCI Express Receiver Characteristics ssssssssssscssecssesssecseecssecssecnsecseecsseeseerstecseessses 21 3 4 3 Local Bus Timing s cscsassssessoscsaissussdcessescansershesnossbbenbectuecoseenstetbidasceassdtssseinsesecpbecnsedbsdbanees 22 3 4 4 Local Clocks Pins Settings pe caus 4 1 GN4124 Signals 5 Package amp Ordering Information sessssssssesssscseesssecsec
27. anual General purpose IO are described in General Purpose IO Block section of the GN412x PCI Express Family Reference Manual Details of all the internal registers and their respective register bit fields are described in Internal Registers section of the GN412x PCI Express Family Reference Manual GN4124 x4 Lane PCI Express to Local Bridge Data Sheet 48407 1 May 2009 gennum PCle Reference Clock POL EXPHESS x4 Lanes 25 of 31 Proprietary amp Confidential 4 1 GN4124 Signals Figure 4 2 depicts the signals of the GN4124 laid out in their logical groupings Figure 4 2 GN4124 Signal Groups Diagram Local Bus Interface PCle Link PETp 3 0 PETn 3 0 D PCle Transmit VA Outbound Data DDR SSTL Outbound Buffer Status Inbound Data DDR SSTL Inbound Buffer Request Status Local Bus Clock Output To Xtal or Oscillator Local Clock Mode Select C PERp 3 0 PERn 3 0 PECLKINp PECLKINn D Scan Test Control TDI TMS TCK TRST TDO SCAN EN TEST EN Reset Control RSTIN RSTOUT33 RSTOUT18 FPGA Configuration SPRI CLK SPRILDATAOUT SPRI_LCONFIG SPRI_LDONE SPRI_XI_SWAP SPRILSTATUS LB_REF_CLK_MI 2 Wire Interface LB_REF_CLK_MO SCLK LCLK_MODE 3 0 SBATA General Purpose IO GPIO 15 0 PCle Receive PCle Reference Clock IAE JTAG To other system logic 3 From PERST PCle CEM To FPGA To FPGA Serial Programming Interface To Seria
28. asy user logic attachment Local bus may be operated asynchronously to the PCIe clock rate for power optimization Live on power up On chip type 0 PCI configuration space enables auto detection without FPGA activity On chip extended configuration space supports power management serial number MSI and PCIe capability registers e FPGA bitstream loader Allows easy configuration of the attached FPGA through PCIe Provides on the fly FPGA reconfiguration capability e 2 wire master target Boot master mode allows PCI configuration space defaults to be loaded from a small EEPROM upon system reset General master mode allows attached 2 wire devices to be read written Target mode allows internal registers to be accessed from an external circuit or processor A simplified block diagram of the GN4124 chip is shown in Figure 1 1 Figure 1 1 GN4124 with FPGA Simplified Block Diagram GN4124 Pin Efficient Clock Boundary I Local Bus TX Data 7 PCI DDR SSTL N EXPRESS RX Data V x4 Lanes Control SDR SSTL Serial Programming Interface 1 2 Live on Power up Since the GN4124 contains a complete type 0 PCI configuration space it is live on power up so that a plug and play BIOS can auto detect it and enumerate it without an attached FPGA having to be configured GN4124 x4 Lane PCI Express to Local Bridge 5 of 31 Data Sheet gennum 48407 1 May 2009 Proprietary amp Confidenti
29. current under high temperature high supply and full load conditions To this resultant number the following factors needed to be added 25 for IcoRE 35 for lycco18 25 for lycco33 6 See Note 4 Based on use of 22 ohm serial termination and 51 ohm parallel termination in the application circuit 7 See Note 4 Also includes current draw from an LDO used to power VTT_AB and VTT_CD GN4124 x4 Lane PCI Express to Local Bridge 17 of 31 Data Sheet 48407 1 May 2009 genn um Proprietary amp Confidential Table 3 4 DC Electrical Characteristics for I VCMOS Buffers Parameter Symbol Conditions Min Typ Max Units Notes High level input voltage Vin 2 V Low level input voltage VIL 0 8 V Input leakage current IL 5 pA High level output voltage Vou IOH 100 pA 2 8 V Low level output voltage VOL IOL 100 pA 0 2 V Table 3 5 DC Electrical Characteristics for SSTL Buffers Parameter Symbol Conditions Min Typ Max Units Notes VREF input reference voltage VREF 833 900 969 mV 1 SSTL termination voltage Vit Vner 40 VREF Vrert 40 mV 2 High level input voltage DC Vin Vggpt125 Vvyccoigt mV 300 Low level input voltage DC Vi 300 Vner 125 mV High level input voltage AC Vin Vggpt250 mV Low level input voltage AC Vu Vnrer 250 mV 1 Typically the value of VREF is expected to be 5096 VDDQ of the transmitting device Peak to peak A
30. d falling 400 ps Tskew Skew between P2L_DATA lanes 300 ps GN4124 x4 Lane PCI Express to Local Bridge z 23 of 31 Data Sheet rs ennum 48407 1 May 2009 9 Proprietary amp Confidential 3 4 4 Local Clocks Pins Settings There are 3 local clocks used by the GN4124 and attached FPGA They are e LCLK LCLKn The primary clock generated by the GN4124 and driven to the FPGA in the form of a differential SSTL output e P2L CLKp n The source synchronous clock used by the GN4124 to communicate data to the FPGA It is derived from the same source as LCLK LCLKn e 2P CLKp n The source synchronous clock generated by the attached FPFA to communicate data to the GN4124 It is derived by the FPGA from LCLK LCLKn The local clock LCLK LCLKn may be derived from either the PCI Express clock or a low frequency crystal oscillator The options are described in Table 3 12 Table 3 12 GN4124 Clocks Pins Settings Signal Description LCLK MODE 2 Controls PLL Bypass 0 LCLK is generated by the PLL which is configurable This is recommended for low and predictable LCLK clock jitter 1 LCLK is driven by 125MHz clock generated from the PCI Express link LCLK MODE 1 Resets the PLL test clock divider 0 Resets the PLL test clock divider so that PLL TEST OUT 0 1 PLL TEST OUT pin outputs a clock with a frequency of the PLL clock divided by 1024 This is used for test purposes LCLK MODE 0 Selects the
31. e 300 300 PPM clocks on different ends of a link 1 Includes 0 to 0 5 spread spectrum 3 4 3 Local Bus Timing clock range Figure 3 3 illustrates the timing relationships of the three local bus clock domains Figure 3 3 Local Bus Timing LCLK LB Control Output from GN4124 LB Control Input to GN4124 L2P_CLK Output from FPGA as Received by GN4124 L2P_DATA 15 0 L2P_FRAME L2P_VALID L2P_EDB P2L_CLK P2L DATA 15 Output from GN4124 DATA 15 0 P2L FRAME P2L VALID H Teo TLCLK to L2P_CLK Tick ind EE Data TL2P_CLK pm sampled by GN4124 90 from rising falling of L2P_CLK 4 TL CLKao P2L CLK Tsu gt TH t L2P FRAME L2P_VALID sampled by GN4124 90 from falling of L2P_CLK TpaL cLk Tsu 1 Ty GN4124 x4 Lane PCI Express to Local Bridge m 22 of 31 Data Sheet 48407 1 May 2009 genn um Proprietary amp Confidential Table 3 9 Local Bus Signal Timing for Single Data Rate SSTL Over Specified Operating Conditions TARGET SPECIFICATION Symbol Description Min Max Units Ticik LCLK Cycle Time 5 10 ns Tco Clock to output delay for local bus control signals 0 7 5 0 ns Tsu Required input set up time to LCLK for local bus 1 02 ns control inputs Ty Required input hold time from LCLK for local bus 0 7 ns control inputs 1 Local bus control signals received by an attached FPGA
32. ifferential Return Loss 10 dB RLRX CM Receiver Common Mode Return Loss 6 dB Jitter Parameters TRX MAX JITTER Receiver maximum total jitter 0 65 UI tolerance TRX EYE Minimum Receiver Eye Width 0 35 Ul TRX EYE MEDIAN to MAX Maximum time between jitter 0 325 Ul JITTER median and max deviation from median Timing Parameters TRX SKEW Maximum skew across all 4 lanes of 20 ns the link Tepply Beacon Activity on channel to 33 100 ns detection of Beacon TRX IDLE ENTER Delay from detection of Electrical 10 20 ns Idle condition on the channel to assertion of TxldleDetect output TRX IDLE EXIT Delay from detection of LOs to LO 5 10 ns transition to de assertion of TxldleDetect output 1 Over a frequency range of 50MHz to 1 25GHz 2 This is a function of beacon frequency GN4124 x4 Lane PCI Express to Local Bridge a 21 of 31 Data Sheet 48407 1 May 2009 gen num Proprietary amp Confidential Table 3 8 Reference Clock PECLKINn Requirements Symbol Description Min Typical Max Unit VIL RC Low level CML CMOS input voltage 0 Vpp 0 5 V Vin RC High level CML CMOS input voltage Vpp V FnetClk Clock frequency range 99 5 100 100 03 MHz D C netclk Duty cycle 40 50 60 96 Tskew Ref Skew between PECLKINp PECLKINn 0 05 RCUI inputs TCCJITTER Cycle to Cycle jitter 150 ps TRRef TFRef Rise Fall time of PECLKINp PECLKINn 0 2 0 25 RCUI inputs PPM PPM difference between referenc
33. l PROM and or Processor GN4124 x4 Lane PCI Express to Local Bridge 26 of 31 Data Sheet 48407 1 May 2009 gennum Proprietary amp Confidential 5 Package amp Ordering Information 5 1 Package Dimensions The GN4124 is packaged in a 256 ball BGA as illustrated in Figure 5 1 Figure 5 1 GN4124 Package Dimensions A 90 10 DC 10 25 i C A B PIN 1 CORNER 90 50 3X REF 90 40 0 60 256X 234567 8 9 101112131415 JJ 16151413121110 9 8 76 54 32 1 A leopnoonoopboosonoouYl s B Q QOOQOOQOOO0QOOOOOQOGQoOoO B C 4160ooooooloooooooo D 14 940000000 O00000000 D E o OOO0O0000 0O00CCOC0C 0 E F OO OO0O0dO0O0O0QoOOo0Oo0O0O0cQo0Q0d F G g S OOQOoooooocQoodoooo G H 8 OOOOOOOO0OOcOocOocOocOoocOc H J e S OOOOOOOO0jOocOocOoOoOoo00 J fa D OOOOOOOOC OoOoOoOOOO00 L O OQOOoOOOoOOQdooooococodoo L OO0O0O000 0 000CCO0C0C0 M OO OOO O 000 0 TO OOo N P OOOOOO0O0O0O0O0O0O00000 P R OOOOO0O0O0O0O0OcOocOoOoOoOocO R T 6 000000 0 00008606 T Lt ies rer mH L l E 15 000 20 15 00 ZAAT 17 004 0 20 4 GS 2 o iB o i 2 q i 4vX S 2 0 20 4x Ball Pitch Substrate Thickness 2 RO 25 TYP AT i G3 1
34. lectrostatic Discharge and Latch Up Tests Stress Conditions Qualification Stress Sample Size Results Vehicle Level Human Body JESD22 A114 GN4124 1KV 2kV 6 Pass Model ESD Machine JESD22 A115 GN4124 100V 200 V 6 Model ESD Pass Charged JESD22 C101 GN4124 500V 700V 6 Device Model Pass ESD JESD78 GN4124 25 C 6 Latch Up 1 5 x Vcc 100 mA S Pass 85 C 6 Level Il Class A GN4124 GN4121 5 of 6 Reliability Qualifcation Report GENDOC 052220 2 10 Apr 2014 Proprietary amp Confidential 3 Conclusion Process qualification reports demonstrate that the processes used in the manufacture of the GS3490 are in volume production and are fully qualified by the suppliers and Semtech Corporation Gennum Products Group Semtech Corporation considers these process and libraries acceptable for use in the design and manufacture of Semtech products The GN4124 and GN4121 passed reliability tests No performance degradation was observed during the evaluation These products are considered suitable for production GN4124 GN4121 6 of 6 Reliability Qualifcation Report GENDOC 052220 2 10 Apr 2014 Proprietary amp Confidential
35. lit into a request phase address phase and a completion phase data phase e Local to PCIe Master Writes The attached FPGA writes data to a PCIe device such as host memory via a root complex e Local to PCIe Master Reads The attached FPGA reads data from a PCIe device The PCIe to Local transactions would typical involve a target controller implemented in the FPGA Local to PCle Master transactions allow a DMA controller in the FPGA to access PCI Express devices 1 5 Virtual Channel Support The GN4124 has two independent virtual channels that support the eight PCIe defined traffic classes This enables high local bus utilization by supporting non blocking traffic between virtual channels This is accomplished with separate on chip buffering resources for each of the two virtual channels For example when write buffering is full for VCO and VC1 has room then VC1 traffic may proceed without reference to the state of VCO Virtual channels may be used to separate different types of application traffic For example a DMA engine in the FPGA may be aggressively reading and writing host memory to stream video data At the same time another agent in the FPGA may need to communicate low bandwidth latency sensitive synchronization information If the two GN4124 x4 Lane PCI Express to Local Bridge 6 of 31 Data Sheet 48407 1 May 2009 genn um Proprietary amp Confidential types of traffic are segregated in terms of virtual chan
36. nels and traffic classes then the low latency traffic can be allowed to pass the high bandwidth traffic 1 6 PCI Express Application Layer The on chip applications layer transfers data between the PCI Express port and an attached FPGA using the local bus interface It provides a mechanism to access internal registers through configuration space access and through one of the Base Address Registers BAR4 The applications layer supports the transmission of message signalled interrupts 1 7 Interrupt Controller A flexible interrupt controller automatically generates PCIe message signalled interrupts from either external pins GPIO pins or internally generated interrupt sources The interrupt controller can route any interrupt source to up to four GPIO pins 1 8 2 Wire Serial Controller An on chip I C compatible controller provides both a master and target mode After device reset default configuration register values such as Subsystem Vendor ID and BAR sizes can be automatically loaded from a small serial EEPROM After initialization an external 2 wire master can access on chip registers to read write them 1 9 Data Sheet Usage The GN4124 Data Sheet includes detailed specifications on GN4124 device However there are other complementary documents to assist designers available on the Gennum Web site www gennum com mygennum A complete set of documentation includes the following e GN4124 Data Sheet this document e GN412x PCI Ex
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38. pedance 80 100 120 Q TTX RISE TTX FALL Rise Fall time of TxP TxN outputs 125 UB Jitter Parameters Ul Unit Interval 399 88 400 400 12 ps4 TTX MAX JITTER Transmitter total jitter 0 30 Ul peak to peak Trx EvE Minimum TX Eye Width 0 70 UI 1 TTX MAX JITTER Trx EvE MEDIAN to MaAx Maximum time between the jitter 0 15 UI JITTER median and maximum deviation from the median Timing Parameters LTX SKEW Transmitter data skew between any2 0 2UI ps lanes 200ps TTX IDLE SET TO IDLE Maximum time to transition to a 4 6 ns valid electrical idle after sending an Electrical Idle ordered set TElExit Time to exit Electrical Idle LOs state 12 16 ns into LO 1 Measured with Vtt 1 2V PHY CONTROL register bits HIDRV 0 LODRV 0 and DTX 0000 1x 2 The de emphasis ratio is determined through the DEQ bits of the PHY CONTROL register inside the GN4124 Typical value is based on recommended setting of the PHY CONTROL register 3 As measured between 20 and 80 points 4 UI does not account for SSC dictated variations 5 Measured using PCI Express Compliance Pattern GN4124 x4 Lane PCI Express to Local Bridge a 19 of 31 Data Sheet 48407 1 May 2009 9 ennum Proprietary amp Confidential Figure 3 1 Typical Transition Signal Eye De emphasis Disabled Default Drive Setting The eye diagram is generated from SIGtest Version 2 1 available from the PCI Special Interest Group up
39. press Family Reference Manual Document ID 52624 which provides the details on functionality and the register map associated with the GN412x family of chips e GN4124 Master List of Documents amp Electronic Files Document ID 52423 which provides a summary of the content of the documentation 6 electronic files to help navigate the content on MyGennum e Reference Design Kit RDK board and the asssociated documentation Following chapters detail the specifications of the GN4124 e 2 Pin Descriptions e 3 Electrical Characteristics e 5 Package 6 Ordering Information Before finalizing a system design based on the GN4124 please contact Gennum to verify that you have the most recent specifications GN4124 x4 Lane PCI Express to Local Bridge 7 of 31 Data Sheet gennum 48407 1 May 2009 Proprietary amp Confidential Gennum is constantly trying to improve the quality of its product documentation If you have any questions or comments please contact Gennum Technical Support 1 10 Getting Help from Gennum For technical support contact Gennum by telephone or e mail E mail ensures the quickest response The most up to date technical support information is also posted on the Gennum website E mail vbapps gennum com 1 11 Getting Answers to PCI Express Related Questions This data sheet assumes a basic understanding of the PCI Express Specification If you are looking for a copy of the specification please contact the
40. re ADVANCED PRODUCT DISCONTINUANCE NOTIFICATION SEMITECH Date March 10 2015 Pi L Semtech Corporation 200 Flynn Road Camarillo CA 93012 XX Semtech Canada Corporation 4281 Harvester Road Burlington Ontario L7L 5M4 Canada LI Semtech Irvine 5141 California Ave Suite 100 Irvine CA 92617 L Semtech Neuchatel Sarl Route des Gouttes d Or 40 CH 2000 Neuchatel Switzerland Nanotech Semiconductor Semtech Corporation 2 West Point Court Bristol United Kingdom BS32 4PY L Semtech Corpus Christi SA de CV Carretera Matamorros Edificio 7 Reynosa Tamaulipas Mexico 88780 Product Discontinuance Details Purpose Description and Effect of Change Due to unforeseen supply constraints we are no longer able to supply the GN4121 CBE3 x1 Lane PCle Bridge to Local Bus device However we are able to supply the GN4124 CBE3 x4 Lane PCle Bridge to Local Bus device as a fully compatible drop in replacement part The GN4121 and GN4124 parts are physically identical and share the same manufacturing flow and final test process Only the part number marking on the package distinguishes the difference between the two products All reliability and qualification data is identical for both part numbers In light of this we would like all existing GN4121 customers to switch to the GN4124 with immediate effect Existing GN4121 designs will have ball E4 tied to 3 3V VCC which will configure the GN4124 to operate as a GN4121 in
41. sscessecssccssccssecssessucessecsscesssesseenseesseesneesseenseesses 27 5 1 Package Dimensions T eae 27 DUM Packaging Dic H RN 28 5 3 Ordering Informations c cciecsisieccossciaeenvsssnderdeecestoneeensesdsicoussnesenoseussoasnsteccddsstsechsatanconscenssedbitnoeess 28 GN4124 x4 Lane PCI Express to Local Bridge 3 of 31 Data Sheet 48407 1 May 2009 gennum Proprietary amp Confidential PCI gennum EXPRESS GN4124 x4 Lane PCI Express to Local Bridge Data Sheet 1 Introduction For the past decade PCI has been a dominant interconnect for both PC and embedded systems With the shift to high speed serial interfaces PCI Express is quickly replacing parallel PCI As a leader in providing solutions for high speed serial communications Gennum has developed the GN4124 family of PCI bridge controller components to complement FPGA devices The GN4124 is specifically designed to take advantage of the architectural features of low cost FPGA devices that do not have PCI Express capable SerDes on chip The result is a low cost bridging solution for high performance native PCI Express bridging The GN4124 is a desirable companion to large FPGA devices where the requirement for firmware upgrading and on the fly reconfiguration are required The GN4124 is a 4 lane PCI Express to local bus bridge that is designed to work as a companion for FPGA devices to provide a complete bridging solution for general applications In

GN4124 x4 Lane PCI Express to Local Bridge - Digi-Key

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