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Inova K6 User`s Manual (2002)

1. enn l 10 Une Mee EE 1 10 Figure 1 51 Block DIA EE 1 10 1 52 Connector LO CANON ein 1 11 Figure ee 1 11 1 33 Connector DESCHIO NON curarse bb vs p i te 1 11 Table 1 53 Connector DESENPUON sii EE Reaves can ati 1 11 Table 1 53 Continued E 1 12 154 For NE FEE carril tee 1 12 Table 1 54 Front e 1 12 Figure 1 54 FrontPanel OpHons sonic cdi 1 13 Lao Intenace POSMIONS sv ls te dedicas 1 14 Figure SS INCAS andere Seks A 1 14 Doc PD00030010 011 2002 Inova Computers GmbH Page 1 1 Product Overview ICP K6 1 0 ICP K6 CPU Family The ICP K6 is the heart of a modular family of high performance CompactPCI single board com puters that satisfy the needs of a wide range of industrial automation military medical aerospace communication imaging process control and embedded OEM applications The ICP K6 is also the first of its kind to support true multiprocessing on a 3U form factor by utilising the features found on AMD s K6 range of low power high performance microprocessors combined with Digital s 21554 non transparent PCI PCI bridge In addition the ICP K6 family can communicate at very high speed with up to 255 x 7 cascaded peripherals like graphics motion control industrial I O or fast data acquisition modules on inter linked passive backplanes Based on the Socket 7 infrastructure and supporting AMDs range of high performance AMD K6 processors Inova s CPUs form the heart of any CompactPCI system All AMD K6
2. Page 24 2002 Inova Computers GmbH Doc PD00030010 011 ICP K6 Configuration Table 2 3 PC AT Interrupt Definitions Interrupt Interrupt Request Vector IRQO IRQ1 Function Assignment Timer Keyboard IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 70h IRQ10 IRQ11 08h IRQ2 OAh Slave 8259 OCh OEh Real Time Clock Redirected IRQ2 PS 2 Mouse IRQ14 IRQ15 Co processor Primary IDE Secondary IDE 72h IRQ12 74h 76h Entries may be reserved for ISA devices with the BIOS 2 Entries may be used for CompactPCI devices Note USB Ethernet and FireWire interrupts are dynamically assigned For more detailed information please refer to the K6 BIOS User s Manual PCI Devices Menu PCI PNP ISA IRQ Resource Exclusion and CompactPCI IRQ Configu ration Doc PD00030010 01 1 2002 Inova Computers GmbH Page 2 5 Configuration ICP K6 2 4 Interrupt Configuration The CompactPCI specification defines a total of six interrupt signals on the backplane INTA through INTD are used to route interrupts from the CompactPCI boards to the PIC on the proc essor board The interrupt request level generated by the device depends on the backplane slot number which the board is plugged into and the interrupt signal which is driven by the particular PCI device Note CompactPCI interrupts may be shared by multiple sources Table 2 4 CompactPCI Bus Interrupts CompactPCl Bus Interrup
3. 2 0 CompactPC ET ee 3 3 Figure 3 01 The 32 Bit CompactPCI Bus Interface Connector sse esseeenenenzznnnnnazknnzzzzanzzt 3 3 3 02 ICP K Connector J1 and J2 i 0cecruserencnancdaatevess seneoradhadadienscuotesmubised kes konede 3 3 Table 3 02 Inova s ICP K6 32 Bit CompactPCI J1 Pin Assignment noci n 3 4 Table 3 03 Inova s ICP K6 32 Bit CompactPCI J2 Pin Assignment Standard 3 5 Table 3 04 Inova s ICP K6 32 Bit CompactPCI J2 Pin Assignment for Rear I O A 3 6 Table 3 05 Inova s ICP K6 32 Bit CompactPCI J2 Pin Assignment for Rear I O B 3 7 Table 3 06 Inova s ICP K6 Rear I O J2 CPU Integration 3 8 3 1 CompactPCI Backplane 3 8 Figure 3 1 Inova s 32 Bit CompactPCI 7 Slot Backplane siirinsesi 3 9 3 Interfaces HEHEHE EE BBE EEE BBB BBB EEE EE EEE EE 3 A o SANNE 3 10 Figure 3 21 RIAS PINQUE ia AA Ad ni 3 10 Table 3 21 Ethernet Connector SIGNAS aiii ida 3 10 3 22 J17 VGA Interface rocio 3 11 Figure 3 22 High Density D Sub VGA Interface Pinout esses 3 11 Table 3 22 Video Output Connector Sigh ls 5 irr etre dg ee Edge ice 3 11 3 23 J8 USB Interface A dott dio data ETENEE 3 12 Figure 3 23 USB Interface PINO Escoria O RA E a 3 12 Table 3 23 USB tee 3 12 3 24 J6 FireWire Interface AEN 3 13 Figure 3 24 FireWire Interface PIROUL a siii rettet A Ad ener 3 13 Table 3 24 E le 3 13 3 25 112 FLASH Interface occiso 3 14 5 20 J
4. D COOC Oo 3 02 ICP K6 Connector J1 and Je Inova s ICP K6 CPU board has been designed as a 32 bit system slot device able to operate in either 5V or 3 3V I O systems The CompactPCI connector is keyed accordingly yellow for 3 3V and blue for 5V Doc PD00030010 011 2002 Inova Computers GmbH Page 3 3 Interfaces ICP K6 Table 3 02 Inova s ICP K6 32 Bit CompactPCI J1 Pin Assignment Pin Nr Row A Row B Row C Row D Row E J1 24 AD 1 5V V I O Appo oe Pull J1 23 3 3V AD 4 AD 3 5 J1 21 3 3V AD 9 AD 8 M66EN Gnd C BE O AD 12 GND AD 11 AD 10 31 19 3 3V AD 15 AD 14 GND AD 13 ND av EEE TU ET J1 16 DEVSEL GND V I O STOP LOCK J1 15 FRAME G J1 13 KEY AREA J1 11 AD 18 AD 17 AD 16 GND C BE 2 J1 09 C BE 3 AD 23 GND AD 22 J1 07 AD 30 AD 29 AD 28 GND AD 27 GND 5V N N N ND J1 05 RST N GNT J1 04 UPS GND V 1 O INTP INTS J1 03 INTA INTB INTC 5 INTD J1 02 5V D Reserved for use for Inova s Uninterruptable Power Supply UPS Page 3 4 2002 Inova Computers GmbH Doc PD00030010 011 ICP K6 Interfaces Table 3 03 Inova s ICP K6 32 Bit CompactPCI J2 Pin Assignment Standard Pin Nr Row A Row B Row C Row D J2 22 J2 20 CLK5 J2 18 IAN J2 16 FENEN J2 14 e 32 12 FEN J2 10 pico J2 08 pir J2 06 J2 04 V 1 0 SPEAKER J2 02 CLK2 CLK3 9 5V open collector signal 5V 100m4A
5. processors feature sixth generation x86 processing leading edge performance for Microsoft Windows op erating systems and a large number of real time operating systems 64kByte on chip L1 cache industry standard MMX instructions and state of the art manufacturing in AMD s 0 2511 process technology Inova s K6 family of CPUs are equipped with all the standard PC interfaces including COM LPT mouse keyboard and hard floppy disk as well as Fast Ethernet USB and FireWire Customers with the Composite Video version of this board do not have the FireWire nor USB interfaces Equipped with 32 MByte or 64 MByte SDRAM and 2 Mbit FLASH for the Phoenix BIOS soldered in place for mechanical stability the ICP K6 can be expanded using memory piggyback modules providing up to 128 MBytes SDRAM and up to 144 MBytes FLASH A 512 kByte pipelined burst static memory Level 2 cache is provided resulting in a performance improvement of up to 15 The ICP K6 makes use of 3 3V technology and split plane voltage CPU technology to minimise the system power requirement for high performance computing A low profile convection cooled heat sink is provided for the 266MHz low power embedded processors a local CPU fan is pro vided for the other gt 266MHz CPU family members Page 1 2 2002 Inova Computers GmbH Doc PD00030010 011 ICP K6 Product Overview 1 01 Interfacing For maximum communication flexibility multiple interfaces satisfying different
6. AREE 2 3 2 1 O Mapped Peripherals 2 3 2 2 Memory Mapped Peripherals 2 4 2 3 Interrupt Routing O A Table 2 3 P Inter pt Definitions sanas lesen Eege aa 2 5 2 4 Interrupt Configuration 2 6 Table 2 4 CompactPCI Bus Interrupts score dei ere 2 6 2 5 Timer Counter amp 7 3 0 CompactPCl J1 Je Connector 3 3 3 01 CompactPCI CONNECT E 3 3 Figure 3 01 The 32 Bit CompactPCI Bus Interface Connector cinco id 3 3 3 02 ICP K6 Connector J1 and J2 svada ee 3 3 Table 3 02 Inova s ICP K6 32 Bit CompactPCI J1 Pin Assignment sss 3 4 Table 3 03 Inova s ICP K6 32 Bit CompactPCI J2 Pin Assignment Standard 3 5 Table 3 04 Inova s ICP K6 32 Bit CompactPCI J2 Pin Assignment for Rear I O A 3 6 Table 3 05 Inova s ICP K6 32 Bit CompactPCI J2 Pin Assignment for Rear I O B 3 7 Table 3 06 Inova s ICP K6 Rear I O J2 CPU Integration sese 3 6 3 1 CompactPCI Backplane 3 8 Hgure 3 1 nova s 32 Bit CompactPCI 7 Slot Backplane uiid orar otn rosae od 3 9 3 LI e Interfaces HEHEHE EEE EEE EE EE EEE EEE EEE EE EE 3 A oO 32V 7 Fast EE 3 10 Figure 3 21 RIAS PINO us 3 10 Table 3 2 1 E Ee 3 10 3 22 reen 3 11 Figure 3 22 High Density D Sub VGA Interface Pinout eese 3 11 Table 3 22 Video Output Connector SIGNAS sta pa 3 11 32 JE USB he Le A ENESE AEREE EROP SoS 3 12 Figure 3 23
7. CLK2 CLK3 SYSEN J2 01 CLK1 GN REQ1 5V TTL signals from serial I O controller 2 Termination of USB lines on CPU The 5V and GND signals need fuses and inductors for decoupling USB specification d The 5V LPT signals need decoupling and pull up resistors near the backplane LPT 1 connector 9 5V open collector signal 5V 100m4A Note Applicable for Board Revision gt D 2 Option External Battery Note battery must be removed from CPU board U 3 4V to 3 6V bat 9 RS485 signals Doc PD00030010 01 1 2002 Inova Computers GmbH Page 3 7 Interfaces ICP K6 Table 3 06 Inova s ICP K6 Rear I O J2 CPU Integration REAR UO Rear I O OPTION E EA ETHERNET Yes BH Yes TTL COM 1 2 USB 1 2 BATTERY Currently three forms of rear UO are available and depending on the version currently in use decides which if any of the J2 signals are available to the rear J2 connector 3 1 CompactPCI Backplane The form factor defined for CompactPCI boards is based upon the Euro card industry standard Both 3U 100 mm by 160 mm and 6U 233 mm by 100 mm board sizes are defined A CompactPCI system is composed of up to eight CompactPCI cards The CompactPCI backplane consists of one System Slot and up to seven Peripheral Slots The System Slot provides arbitration clock distribution and reset functions for all boards on the bus The System Slot is responsible for performing system initialization by managing ea
8. USB Interface PINOUE citando 3 12 Table 3 23 USB Connector Signals sia lau lara 3 12 3 24 J6 FireWire Interface ovina 3 13 Figure 3 24 FireWire Interface Pinot 3 13 Table 3 24 FireWire Connector SIGNAS sanndansslansusnunbefudrbanngminanesud 3 13 3 25 J12 FLASH Mera Ge 3 14 3 26 J18 Floppy Disk Interf CE asorsisnisadaranedaa poesia 3 14 3 27 OM COME Interfaces ra in danne 3 14 Page 0 2 2002 Inova Computers GmbH Doc PD00030010 011 ICP K6 Preface Figure 3 27 COMI COM2 Interface PINOUE siria efe i 3 14 Table 3 27 COMT COM2 Connector Signals civic Ra 3 14 3 28 TET he enke 3 15 Figure 3 28 PT Interface POUE iii ir EA 3 15 Table 3 22 EPT Connector SIGNOS tri A AA 3 15 23129 IT T Keyboard Inket scarico 3 16 Figure 3 29 Keyboard Interface PIDOUL Lice tret rmi A 3 16 Table 3 29 Keyboard Connector SIGNAS deeds ae ritorno SE E ER Utt ENEE DUE eS ERU ERR AR 3 16 3 30 T T Mouse InterfaC sai 3 16 Figure 3 30 Mouse Interface PIQUE ainia ette enim err ne Herne un eee 3 16 Table 3 30 Mouse Connector Signals iie tica 3 16 3 31 19 110 Hard Disk intera e soriana ins 3 17 Doc PD00030010 011 2002 Inova Computers GmbH Page 0 3 Preface ICP K6 Unpacking and Special Handling Instructions This product has been designed for a long and fault free life nonetheless its life expectancy can be severely reduced by improper treatment during unpacking and installation Observe standard antistatic precautions when changing piggybac
9. connector will not be available for use Page 1 12 2002 Inova Computers GmbH Doc PD00030010 011 ICP K6 Product Overview Figure 1 54 Front Panel Options KEYBOARD ETHERNET ETHERNET ETHERNET MOUSE S FIELDBUS PanelLink PanelLink COM2 FIELDBUS The front panels shown in Figure 1 54 show the tremendous flexibility built into Inova s CPU concept From left the standard CPU is 4TE with Ethernet FireWire USB and VGA graphic con nections If instead of VGA graphics PanelLink is required then the piggyback is installed on J14 for this purpose TFT graphics are realised in a similar way except an extra 4TE front panel is required not shown to carry the flat band ribbon cables If the application requires the mouse keyboard and COM ports or if the CPU is equipped with a hard disk or FLASH that is greater than 24MByte then an 8TE front panel is selected Here the COM2 Fieldbus 9 pin D Sub connector can be used for the PanelLink too with remote connector and still maintain the VGA output The final CPU option shows PanelLink and optional composite video for PAL NTSC television signals Note this option is without the FireWire and USB connections LPT and COM2 interfaces are available on a dedicated panel shown to the right of Figure 1 54 7 If gt 24MByte FLASH is installed and a hard disk is required the HD is mounted separately Doc PD0003
10. intensive environments like those found in Microsoft s Win dows NT With 4 MBytes SGRAM available the controller supports resolutions up to 1280 x 1024 pixels with 24 bit True Colour depth or 1600 x 1200 pixels with 16 bit Hi Colour depth VGA SVGA XGA XSGA Composite video and TFT dual scan single scan colour panels are supported with config urable colour depths In addition Inova s CPU family caters for the needs of the LVDS and PanelLink user Doc PD00030010 011 2002 Inova Computers GmbH Page 1 3 Product Overview ICP K6 1 1 Specifications CPUs CPU Speed L2 Cache Memory BIOS FLASH FLASH Disk BIOS Battery Bus Interface Southbridge Northbridge PCI PCI Bridge Graphics Real Time Acc AMD s K6 2 E and K6 3 Super Socket 7 166MHz to 500MHz processor with split pane voltage technology 512 ebe 8ns synchronous pipelined burst with extended cacheability 32 64 MByte soldered synchronous DRAM Optional piggyback provides additional 32 64 MByte 2 Mbit on board Available as an option Disk on Chip providing up to 144 MByte FLASH Standard Phoenix BIOS 4 0 Release 6 0 with menu driven setup Rechargeable lithium cell for RTC Lifetime gt 10 years gt 0 5 year shelf life CompactPCI bus 33 MHz 8 slot Master M1543 ALI chipset Super I O 1 Floppy Disk Controller 1 Parallel Port 2 Serial Ports System Peripherals ISP 2 x 82C59 1 x 82C54 advanced features in t
11. up to 12 Mbit s An optoisolated RS485 interface galvanically separates the PROFIBUS device connected to the front panel 9 pin D Sub connector 1 33 INTERBUS S This piggyback provides an Interbus S master based on the 68332 microcontroller that features a PCP interface diagnostic functions synchronisation and hierarchical networks through the imple mentation of Generation 4 Phoenix Contact Firmware A 9 pin D Sub connector on the front panel supports the optoisolated RS485 physical layer for 500 kbit s transmission speeds All fieldbuses are available in two standard configurations The basic version has a 9 pin D Sub connector mounted directly on the piggyback allowing it to seat on the CPU with the physical interface appearing where the 15 pin high density D Sub VGA connector would also appear This configuration assumes that the application does not have any need for on board graphics The second version is seated on the CPU but the 9 pin D Sub connector is remote and replaces the front panel COM2 connection This allows the CPU to have on board graphics and a fieldbus piggyback without compromising functionality All fieldbuses are complete with the protocol stack software and licence but need the device drivers available on an extra CD Page 1 8 2002 Inova Computers GmbH Doc PD00030010 011 ICP K6 Product Overview 1 4 Software 1 41 VenturCom Hard real time scalability and embedded operation extensions are requi
12. 0010 011 2002 Inova Computers GmbH Page 1 13 Product Overview ICP K6 1 55 Interface Positions Figure 1 55 Interfaces I SDRAM EXTENSION KEY o CPCHCONNECTOR o FLASHDISK FLASHMEMORY Figure 5 5 shows the typical positioning of the front panel extension modules for mouse key board COM1 COM2 LPT1 and COM2 Fieldbus interfaces Note A hard disk if installed will generally be fitted to the piggyback containing the mouse keyboard COM1 and COM2 interfaces Page 1 14 2002 Inova Computers GmbH Doc PD00030010 011 ICP K6 Configuration Configuration Configuration Con tents 2 0 Memory Map sssnnunaannnnnuzunnununuz BB Figure 2 0 System Architecture vico eee da air i Ce ver eire Ea 2 2 Table 2 0 UMB Reservations TOP IS A andit perdes ton territa rata dps 2 3 Table 2 01 Port Addressing estonio 2 3 2 1 I O Mapped Peripherals 2 3 2 2 Memory Mapped Peripherals 2 4 2 3 Interrupt Routing O A Table 2 3 PC AT Interrupt Definitions ettet rH t eto dea 2 5 2 4 interrupt Configuration e 8 Table 2 4 CompactPCI Bus Interr pts s uasa teer rarae Na oD rO OnE UR g Ee 2 6 2 5 Timer Counter ennen ee au unn s E277 Doc PD00030010 01 1 2002 Inova Computers GmbH Page 2 1 Configuration iCP KG 2 0 Memory Map Figure 2 0 System Architecture Memory Address Addressable Memory Limit Area 4 GByte L Extend
13. 1024 pixels with 24 bit True Colour depth or 1600 x 1200 pixels with 16 bit Hi Colour depth VGA SVGA XGA XSGA Composite video and TFT dual scan sin gle scan colour panels are supported with configurable colour depths Figure 3 22 High Density D Sub VGA Interface Pinout a GA ale Lee o 15 11 Table 3 22 Video Output Connector Signals Analog RED Analog GREEN Analog BLUE N C CRT Ground CRT Ground Monitor ID USDA 13 HSYNC VSYNC 14 Doc PD00030010 011 2002 Inova Computers GmbH Page 3 11 Interfaces ICP K6 3 23 J8 USB Interface J8 is located on the front panel if this option is available TET LT Jd 2 3 4 Figure 3 23 USB Interface Pinout 1 Table 3 23 USB Connector Signals 5V USB PO USB P0 Tam Jr Page 3 12 2002 Inova Computers GmbH Doc PD00030010 011 ICP K6 Interfaces 3 24 J6 FireWire Interface J6 is located on the front panel if this option is available Figure 3 24 FireWire Interface Pinout SC Table 3 24 FireWire Connector Signals Pin No 1 2 IEEE 1394 S 12V 1A Fuse IEEE 1394 S GND 3 4 IEEE 1294 S TPB IEEE 1394 S TPB 5 6 IEEE 1394 S TPA 6 5 IEEE 1394 S TPA Note On CPU board revisions Bx Cx and D the pinout of this connector was different to the later versions The pinout for these earlier revisions i
14. 18 Floppy Disk interaccion iia 3 14 PERS FCO EA RE EE 3 14 Figure 3 27 COM1 COM2 Interface PINOUE iscritte rien tere it ee oH ee 3 14 Table 3 27 COM1 COM2 Connector Signals eee eee 3 14 3 28 J13 LPTI RET 3 15 Figure 3 28 LPT I tee 3 15 Table 3 22 4 PTT Connector SIGNAS cnc kw seine iia ATENEA us 3 15 3 29 J11 Keyboard Interface A iehe sie ee sion Sai lodo kai nie site ego 3 16 Figure 3 29 Keyboard Interface PINOLL iieri kenni ts i re e Re ent 3 16 Table 3 29 Keyboard Connector Signal 3 16 Doc PD00030010 011 2002 Inova Computers GmbH Page 3 1 Interfaces ICP K6 3 30 J11 Mouse Interface seen 3 16 Figure 3 30 Mouse Interface BIOG sue erret a 3 16 Table 3 30 Mouse Connector SIQHOIS rain is auc e ENS N 3 16 3 31 J9 J10 Hard Disk Interface aan 3 17 Page 3 2 2002 Inova Computers GmbH Doc PD00030010 011 ICP K6 Interfaces 3 0 CompactPGI J1 Je Connector The CompactPCI standard is electrically identical to the PCI local bus standard but has been en hanced to support rugged industrial environments and up to 8 slots The standard is based upon a 3U board size and uses a rugged pin in socket hard 2mm connector IEC 1076 4 101 3 01 CompactPCI Connector Figure 3 01 The 32 Bit CompactPCI Bus Interface Connector
15. 2 3 Configuration ICP KG 2 2 Memory Mapped Peripherals PC AT desktop computers ISA bus allow 24 bit memory addressed peripherals This decoding permits peripheral boards to be mapped in the Intel 80x86 memory map from Oh to OFFFFFFh Inova s CompactPCI systems allow the full 32 bit addressing capability of the AMD K6 range of processors so that memory mapped peripheral devices may be mapped locally to the processor board at any location in the memory map not being used by other devices e g system RAM The BIOS automatically assigns memory addresses required by peripheral boards and PCI devices at boot time based on the requirements of each device The assigned addresses can be deter mined by reading the configuration address space registers using PCI software tools Note Devices not located on the CPU side of the PCI PCI bridge are not normally accessible by DOS 2 3 Interrupt Routing The IBM compatible architecture includes one PC XT or two PC AT programmable interrupt controllers Intel 8259A compatible PICs configured to set the priority of interrupt requests to the CPU In the PC AT architecture one PIC is programmed as the master with one input IRQ2 being the cascaded interrupt from the second slave PIC This configuration allows for a total of 15 interrupt sources to the CPU Table 2 3 shows the interrupts with their corresponding vectors and sources as defined for AT PCs
16. 45 QNX This solution ports the Win32 API to a QNX kernel The Win32 API aims to define a standard for developing open systems applications that are optimized to run on Wintel platforms This oper ating system evolves around a small microkernel RTOS that produces a protected mode POSIX certified API Being fully modular and scalable this technology creates the smallest footprint that is beneficial to high end server applications 1 46 Jbed Esmertec s Jbed is a new generation of real time operating system Java based innovation provides unprecedented safety and ease of use without compromising resource efficiency native processor speed or hard real time performance In addition advanced features are implemented such as modularity hot updates deadline driven scheduling admission testing as well as a fast and pro ductive cross development environment Doc PD00030010 01 1 2002 Inova Computers GmbH Page 1 9 Product Overview ICP K6 1 5 Hardware 1 51 Block Diagram Figure 1 51 Block Diagram SECONDARY PCI BUS SDRAM CPU Extension 13 J4 AMD K6 J1 J2 32 MByte or 64 MByte AMD K6 2 AMD K6 2E L2 Mobile AMD K6 3 Cache PCI PCI SDRAM On Board North 32 MByte prid Tanaga or 64 MByte Non Transp Dev 0 Dev 3 ADsel 16 PRIMARY PCI BUS Dev 2 Dev 5 Dev 4 Dev 6 ve E PROM E PROM E PROM
17. A B C D 15 2 02 Doc PD00030010 011 2002 Inova Computers GmbH Page 0 5 Preface ICP K6 Three Year Limited Warranty Inova Computers Inova grant the original purchaser of Inova products the following hardware warranty No other warranties that may be granted or implied by anyone on behalf of Inova are valid unless the consumer has the expressed written consent of Inova Inova warrants their own products excluding software to be free from defects in workmanship and materials for a period of 36 consecutive months from the date of purchase This warranty is not transferable nor extendible to cover any other consumers or long term storage of the product This warranty does not cover products which have been modified altered or repaired by any other party than Inova or their authorized agents Furthermore any product which has been or is suspected of being damaged as a result of negligence misuse incorrect handling servicing or maintenance or has been damaged as a result of excessive current voltage or temperature or has had its serial number s any other markings or parts thereof altered defaced or removed will also be excluded from this warranty A customer who has not excluded his eligibility for this warranty may in the event of any claim return the product at the earliest possible convenience together with a copy of the original proof of purchase a full description of the application it is used on and a descr
18. COM2 would normally be present then it is physically impossible to mount the hard disk on the CPU Doc PD00030010 011 2002 Inova Computers GmbH Page 3 17 Interfaces ICP K6 This page has been left blank intentionally Page 3 18 2002 Inova Computers GmbH Doc PD00030010 011
19. IGP K6 High Performance CPU Boards A TA O USER S MANUAL fr Pn Publication Number PD00030010 xxx AB MAN ICP K6 f inova omputers lt This user s manual describes a product that due to its nature cannot describe a particular applica tion The content of this user s manual is furnished for informational use only is subject to change without notice and should not be constructed as a commitment by Inova Computers GmbH Inova Computers GmbH assumes no responsibility or liability for any errors or inaccuracies that may appear in this user s manual Except as otherwise agreed no part of this publication may be reproduced stored in a retrieval system or transmitted in any form or by any means electronic mechanical recording or other wise without the prior written consent of Inova Computers GmbH Products or brand names are trademarks or registered trademarks of their respective companies or organisations Inova Computers GmbH Inova Computers Inc Sudetenstrasse 5 270 Communication Way Bldg 46 D 87600 Kaufbeuren Hyannis MA 02601 Germany USA Tel 49 0 8341 62 65 Tel 1 508 771 4415 Fax 49 0 8341 62 69 Fax 1 508 771 4346 email info inova computers de email info inova computers com http www inova computers com ICP K6 Preface Preface Contents Unpacking and Special Handling Instruc ONS cra Revision History ussnnunununununununnunununununu D Thr
20. Note Applicable for Board Revision gt D 3 Option External Battery Note battery must be removed from CPU board Ub 3 4V to 3 6V Doc PD00030010 011 2002 Inova Computers GmbH Page 3 5 Interfaces ICP K6 Table 3 04 Inova s ICP K6 32 Bit CompactPCI J2 Pin Assignment for Rear I O A 4 5 J2 18 PORE J2 16 rike J2 14 Fike J2 12 Fie J2 10 FER J2 06 P A J2 04 VO SPEAKER G J2 02 CLK2 CLK3 SYSEN GNT2 Pin Nr Row A Row B Row C Row D RowE 2 22 J2 20 CLK5 GND COM 2 9 D ETH R78 D UBAT GN GN N D D D D D D 5V open collector signal 5V 100mA Note Applicable for Board Revision gt D Option External Battery Note battery must be removed from CPU board U 3 4V to 3 6V bat RS485 signals Page 3 6 2002 Inova Computers GmbH Doc PD00030010 011 ICP K6 Interfaces Table 3 05 Inova s ICP K6 32 Bit CompactPCI J2 Pin Assignment for Rear I O B Pin Nr RowA Row B Row C Row D Row E 42 22 J2 20 CLK5 GND ETH R78 J2 18 LPT STP G G G G G ND ND ND PE ND J2 16 LPT D0 LPT ACK UBAT J2 15 LPT ERR ND USB1 DATA GNT5 J2 14 LPT D19 LPT SLCT J2 13 LPT INIT gt ND V 1 0 ND ND ND ND ND D USB2 DATA 2 G J2 12 LPT D2 J2 11 LPT SLIN G J2 10 J2 09 6 V I O J2 08 LPT D5 B 22 07 LPT BUSY G V I O V I O USB2 DATA J2 06 A J2 05 V 1 0 J2 04 V O SPEAKER J2 03 CLK4 GNT3 J2 02
21. SB2 and the loudspeaker signals are present on the backplane if requested at time of order Other options may also be available including customer specific but are not referred to in this user s handbook In order to take full advantage of the rear I O features the CompactPCI backplane needs to support them Inova provides two standard versions one has the J2 connector at the CPU location extended to the rear of the backplane while the other version has all slots fitted with the J2 connector on both the front and rear Doc PD00030010 011 2002 Inova Computers GmbH Page 1 7 Product Overview ICP K6 1 3 Fieldbuses 1 31 CAN Equipped with a dedicated on board microcontroller for reception and transmission of CAN mes sages without host intervention this piggyback provides CAN bus master functionality with a variety of application layer protocols transparent to the host Consisting of a powerful C167C microcontroller with integrated 82527 CAN controller it inter faces the host via a 128 kByte dual ported memory area between the C167C FLASH code and SRAM data area The firmware fully implements CANopen master or DeviceNet application layer protocols supporting Baud rates up to 1 Mbit s The physical interface complies to the ISO 11898 standard 1 32 PROFIBUS Conforming to the EN50170 standard Inova s PROFIBUS piggyback provides DP master class 1 functionality by implementing the layer 2 in hardware to allow transmission rates
22. ble on the CPU front panel The RJ45 interface supports both the 10BaseT and 100BaseTX twisted pair standard 8 1 Table 3 21 Ethernet Connector Signals Figure 3 21 RJ45 Pinout Link LED not accessible on pins Active LED not accessible on pins 13 14 PE not accessible on pins Note Users taking advantage of the CPUS rear I O options are advised not to use the front panel interface if the rear interface is being used Possible damage to the board could occur and data integrity cannot be assured Page 3 10 2002 Inova Computers GmbH Doc PD00030010 011 ICP K6 Interfaces 3 22 J17 VGA Interface J17 is available on the CPU front panel if this option is required and if this position is not already occupied by a fieldbus piggyback or the PanelLink piggyback The 15 pin high density D Sub connector forms the physical interface for the video on the ICP K6 which is based on the Virge S3 dual display MX 2D 3D graphic accelerator The controller is a highly integrated 64 bit GUI Grahpical User Interface engine that has been optimized for handling graphic intensive environ ments like those found in Windows NT The controller uses a 64 bit data path to the SGRAM video memory a 24 bit high performance 135 MHz RAMDAC and a flat panel interface capable of controlling the latest STN and TFT panels All ICP K6 CPUs if prepared for graphics are equipped with 4 MByte high speed SGRAM support ing resolutions up to 1280 x
23. ch local board s IDSEL signal Physically the System Slot may be located at either end of the backplane but Inova have placed theirs on the right to cater for physical expansion due to heat sink hard disk extended function ality etc The Peripheral Slots may contain simple boards intelligent slaves or PCI bus masters Note Inova s 3U CompactPCI CPU boards can be used as either master or slave boards i e occupying either the system slot or the peripheral slot The choice of PCI PCI bridge multiprocessing or standard decides which of the slots is used Page 3 8 2002 Inova Computers GmbH Doc PD00030010 011 ICP K6 Interfaces Figure 3 1 Inova s 32 Bit CompactPCI 7 Slot Backplane SIA 9 6 006 6 66 6 sie 6 6 6 60 66 e 46 0 60 es e le ee stole eeo ee e cie site 8 9 616 4 dele sere O O eels e sje ee lesus ae esel sete 000000000000000000000000000000000 DO 0 L HOOD oAG0000060G000000008S006050 POCO OOOO MOU OO GAGA OOO O GSE D L U Note The logical slots are different to the phvsical slots Slot 1 phvsicallv is the Svstem Slot logical 0 and likewise slot 7 phvsicallv is slot 6 logicallv Doc PD00030010 011 2002 Inova Computers GmbH Page 3 9 Interfaces ICP K6 3 2 Interfaces 3 21 J7 Fast Ethernet J7 is availa
24. ed Memory 32 64 MByte Above 1 MByte FFFFFh 1 MByte E0000h D0000h Upper Memory 16 kByte FLASH Disk Blocks CCOOOh UMBs 48 kByte VGA BIOS CO000h CGA Screen Memory B8000h MDA Screen Memory BOOOOh VGA Screen Memorv A0000h Free User 640 kByte Meme Conventional Memory 00000h The UMB reservation may be set up with the BIOS Page 2 2 2002 Inova Computers GmbH Doc PD00030010 011 ICP K6 Configuration Table 2 0 UMB Reservations for ISA UMB Reservations for ISA Start Address Finish Address OCCOOh OCFFFh ODOOOh OD3FFh 0D400h OD7FFh OD800h ODBFFh ODCOOh ODFFFh Table 2 01 Port Addressing Port Addressing Port Address COM1 3F8h COM2 2F8h LPT1 378h 2 1 O Mapped Peripherals The original PC XT and PC AT desktop computer ISA bus specification allows for 10 bit I O addressed peripherals This permits peripheral boards to be I O mapped from Oh to 3FFh CompactPCl systems permit the full 16 bit addressing capability of the Intel 80x86 processors from Oh to OFFFFh All Inova CPU boards include peripheral devices requiring I O address space on board and hence the BIOS automatically assigns the I O address required by peripheral boards and PCI devices at boot time based on the requirements of each device The assigned addresses can be determined by reading the configuration address space registers using special software tools Doc PD00030010 01 1 2002 Inova Computers GmbH Page
25. ee Year Limited Warranty 6 7 0 ICP K6 CPU Family l 8 MeO Inter ANG ii ii as 1 3 MA AA o EU PS b nn 1 3 De 1 3 IDA e A Pe e 1 3 1 1 Specifications l A 1 2 Configuration l 56 Table 1 30 Processor OVerVIEW E 1 6 Figure 1 2 ICP K6 Overview ss sionin EEEE EEEE EEE E EEEE 1 7 1 3 Fieldbuses en nnn l 8 ipa v A 1 8 T32 PROA Ss cias 1 8 133 INTERBUS S neta ice 1 8 1 4 Software cccccccccc ERR m X 1 9 EE ait AA EEE SEE LE EE 1 9 TEPPE 1 9 1 239 e ere alg a ce we E eas cee opas ease eat eee 1 9 1 44 e CR ene 1 9 TASONA NE EE EE EEE NET 1 9 146 Ded EEE EE EN 1 9 1 5 Hardware rrnrn m HH 110 131 Block Digernes 1 10 Figure 1 31 Block DIA EEN 1 10 1 52 Connector Location E 1 11 Figure 1 52 Connector Locations osos oomen eroe e ternos nii exe ii i 1 11 1 53 Connector D scipHOl E 1 11 Table 1 53 Connector Description tica di buda emet E og va 1 11 Doc PD00030010 011 2002 Inova Computers GmbH Page 0 1 Preface ICP K6 AEREOS AM A 1 12 T5TP E 1 12 Tapie 1 54 Font Panels aora daa pes 1 12 Figura 1 54 FrontsPanel OPHONS ess gege iii ri nia ORSAI vasene 1 13 ds AA 1 14 Figure ERT 1 14 Q Memory Map HEHEHE EEE EEE EEE EEE EEE EE EEE 2 2 Figure 2 0 System Architecture senori retratos D OEA EAS AREA 2 2 Table 2 0 UMB Reservations TOFISA citrato kista irradia 2 3 Table 2 01 Port Address isaac iia WP
26. he DMA controller 2 X 82C37 Interrupt controller 82C59 Counter Timer 8254 compatible Distributed DMA 7 channels Keyboard controller 2 channel dedicated IDE controller USB interface M1531 CPU to PCI bridge memory cache and buffer controller Pipelined Burst SRAM Supports FPM EDO SDRAM Concurrent PCI architecture Enhanced power management The standard DS 21150 PCI PCI transparent bridge is fitter for standard Master CPU operation i a DS 21554 non transpar ent PCI PCI bridge is used for for multiprocessing Slave operation Optional 3 dual display Virge 2D 3D graphic accelerator with 4 MBytes SGRAM Supports VGA connection on front panel PanelLink TFT and composite video software selection between Ae or PAL are also available TFT requires additional 4TE front panel Common to all K6 based CPUs is LP Elektronik s real time accelera tor chip with proprietary CPLD code allowing real time functional ity within a Windows NT operating environment Page 1 4 2002 Inova Computers GmbH Doc PD00030010 011 ICP K6 Product Overview Fieldbus Piggyback option providing support for CAN PROFIBUS Interbus S and LON on request Protocols CANopen Layer 2 PROFIBUS DP Interbus S On Board I O USB amp FireWire or composite video Fast Ethernet 10BaseT and 100BaseTx VGA TFT or fieldbus PanelLink The TFT option requires an additional 4TE front panel Rear I O Standard to all CPU variants is the s
27. hernet Interface Doc PD00030010 011 2002 Inova Computers GmbH Page 1 11 Product Overview ICP K6 Table 1 53 Continued Connector Description J8 USB Interface Hard Disk Interface J11 COM1 Keyboard and Mouse Interfaces FLASH Extension Piggyback Connector for up to 144 MBytes J13 COM1 and LPT1 Interfaces J14 TFT Flat Panel or PanelLink Interface J17 15 Pin High Density D Sub VGA Graphics Interface J18 1 4 MByte Slim Line Floppy Drive Interface 2 May not be available on older CPU revisions 3 Different on older product revisions 1 54 Front Panel Features Table 1 54 Front Panels Interface Description amp Location Ethernet RJ45 Connector Common to all 4TE CPU Front Panels FireWire Firewire Connector on 4TE CPU Front Panel USB Connector on 4TE CPU Front Panel 15 Pin High Density D Sub Connector on 4TE CPU Front Panel PS 2 Style On 8TE CPU Front Panel PS 2 Style On 8TE CPU Front Panel 9 Pin D Sub On 8TE CPU Front Panel 9 Pin D Sub On 8TE CPU Front Panel or 4TE CPU Extension LPT1 25 Pin D Sub On 4TE CPU Extension Fieldbus 9 Pin D Sub On 4TE CPU Front Panel or 8TE CPU Front Panel PanelLink 9 Pin D Sub On 4TE CPU Front Panel or 8TE CPU Front Panel Optional If a Fieldbus PanelLink piggyback is present the VGA connector may not be available 5 COM2 on the 8TE CPU front panel may be used for a fieldbus or PanelLink piggyback 9 If this piggyback is installed either the COM2 or VGA
28. industrial stand ards are implemented LAN applications can take advantage of Inova s 10BaseT 100BaseTx Ether net implementation or if high speed system level serial interfacing is required the built in 100 400 Mbit s FireWire port is available Peripherals may be connected to the standard USB or as an option RS232 RS485 CAN PROFIBUS and Interbus S piggyback modules may be installed The Digital 21554 non transparent PCI PCI bridge is utilised for multiprocessing typically with the higher speed AMD K6 CPU cores 1 02 Peripherals The ICP K6 supports standard PC peripherals like floppy disk hard disk and CD ROM Hard disks may be connected directly to the base board and possess their own front panel offering COM ports and PS 2 style connectors for mouse and keyboard 1 03 Software The following operating systems have been verified with Inova s K6 3U CompactPCI CPU IT Microsoft Windows NT IT Microsoft Windows CE E Linux I VenturCom RTX Real Time Extension I Microware OS 9 and OS 9 x86 5 LP Elektronik VxWin WI Windriver VxWorks L4 Esmeralda Technology Jbed under development B onx Solaris x86 Hi psos All readily available application software designed for operation on the standard PC architecture will execute without modification 1 04 Graphics The S3 Virge controller is a highly integrated 64 bit GUI Graphical User Interface engine that has been optimized for handling graphic
29. ip technology allows the CPU board to be tailored with various quantities of FLASH to meet the needs of the application Table 1 30 Processor Overview CPU Family Processor CPU Speeds Multi Processing Cooling ICP MPKx fegsm K6 2E K6 3 166 to 500 MHz Yes Passive Active ICP MK6x fegsm Mobile K6 2 3 E up to 500 MHz No Passive Active ICP K62E fegsm K6 2E 166 266 MHz All CPU family members can possess up to 128 MByte SDRAM through a combination of soldered memory units and plug in modules FLASH up to 144 MByte may be realised in a similar manner All CPUs are equipped with a shielded front panel with typically VGA USB FireWire and Fast Ethernet interfaces installed Other front panels are available with mouse keyboard COM LPT TFT Fieldbus PanelLink or composite video interfaces The Virge S3 graphic controller complete with its 4MByte SGRAM is available as an option for all CPUs as is multiprocessing Page 1 6 2002 Inova Computers GmbH Doc PD00030010 011 ICP K6 Product Overview Figure 1 2 ICP K6 Overview FLASH Extension Up to 144 MByte FireWire EN K6 2 E K6 3 E Super Socket 7 USB j Fieldbus VGA LVDS cb PanelLink TFT PanelLink or LVDS Optional S3 Graphic Controller Fieldbus Extension Optional PROFIBUS LON Multiprocessing CAN Interbus S 32 64 MB SDRAM Extension Inova s CPUs have been prepared for rear I O operation Currently Ethernet COM1 COM2 USB1 U
30. iption of the defect to the original place of purchase Pack the product in such a way as to ensure safe transportation we recommend the original packing materials whereby Inova undertakes to repair or replace any part assembly or sub assembly at our discretion or to refund the original cost of purchase if appropriate In the event of repair refund or replacement of any part the ownership of the removed or replaced parts reverts to Inova and the remaining part of the original guarantee or any new guarantee to cover the repaired or replaced items will be transferred to cover the new or repaired items Any extensions to the original guarantee are considered gestures of goodwill and will be defined in the Repair Report returned from Inova with the repaired or replaced item Other than the repair replacement or refund specified above Inova will not accept any liability for any further claims which result directly or indirectly from any warranty claim We specifically exclude any claim for damage to any system or process in which the product was employed or any loss incurred as a result of the product not functioning at any given time The extent of Inova s liability to the customer shall not be greater than the original purchase price of the item for which any claim exists Inova makes no warranty or representation either expressed or implied with respect to its prod ucts reliability fitness quality marketability or abilit
31. ks ROM devices jumper set tings etc If the product contains batteries for RTC or memory backup ensure that the board is not placed on conductive surfaces as these can cause short circuits damage the batteries or disrupt the conductive tracks on the board Do not exceed the specified operational temperature ranges of the board version ordered If batteries are present their temperature restrictions must be taken into account Keep all the original packaging material for future storage or warranty shipments If it is necessary to store or ship the board re pack it as it was originally packed Before returning this product for repair please ask for an RMA Returned Material Authorization number and supply the following information Company name contact person shipping address and invoice address Product name and serial number Failure or fault description Clearly write the RMA number on the outside of the transportation carton Page 0 4 2002 Inova Computers GmbH Doc PD00030010 011 ICP K6 Preface Revision History Revision History Manual Publication Number Issue Revision Date of Issue PD00030010 001 17 9 98 PD00030010 002 22 9 98 PD00030010 002 13 10 98 A A A PD00030010 003 A B 3 10 98 PD00030010 004 A B 28 1 99 PD00030010 005 A B C 2 2 99 PD00030010 006 A B C 14 7 99 PD00030010 007 A B C D PD00030010 008 A B C D 22 11 99 PD00030010 009 A B C D PD00030010 010 A B C D 16 12 99 PD00030010 011
32. peaker output appearing on J2 As an option Ethernet COM1 COM2 USB1 USB2 and LPT1 are available on the backplane Other I O configurations including customized are possible but may no longer be conformant to the CompactPCI specification Mass Storage 1 44 2 88 MByte 3 5 flo drive and EIDE flex cable supportin S 2 hard disks SE CD ROM ii S Front Panels Extended front panel 4TE provides COM1 COM2 Fieldbus keyboard PS 2 mouse Extended front panel 4TE provides COMA LPT1 Connectors USB USB RJ45 Ethernet 6 pin FireWire FireWire 9 15 pin D Sub Fieldbus PanelLink 15 pin high density D Sub connector VGA CompactPCI 32 bit master interface 33 MHz bus with INT A INT B INT C and INT D support single slot operation Mechanics 3U 100 x 160 x 21mm 4 TE 3U 100 x 160 x 42mm 8 TE 3U 100 x 160 x 63mm 12 TE Power Cons 12W 333MHz fan reqd 10W 266MHz fan optional 6W E 166MHz Software Windows NTE Windows CE Linux Support VxWorks RTX amp OS 98 QNX pSOS amp Jbed Weight 230g ATE without fan Oper Temp 0 C 70 C Storage Temp 40 C 85 C Extended Temp 40 85 C 166MHz version Humidity 596 9596 non condensing Warranty Three year limited warranty Conformance CompactPCI R2 1 Note If a hard disk CD floppy disk or certain types of FLASH both on board or PCMCIA are present in the CompactPCI system the operational temperatures will be limited to ap
33. prox 50 C Doc PD00030010 011 2002 Inova Computers GmbH Page 1 5 Product Overview ICP K6 1 2 Configuration Inova s Super Connectivity Universal CPU family of high performance high density 3U boards support functionality and connectivity on all three major serial networking levels like Fast Ethernet FireWire and USB as well as most state of the art fieldbus standards such as PROFIBUS CAN and Interbus S Three CPU groups exist to cater for the needs of all aspects of CompactPCI integration The high end typically supports 64 MBytes soldered SDRAM the 3 graphic controller and is suitably equipped with an AMD K6 2 E 3 processor operating at up to 450 MHz For standard applications the same base layout is utilized however the soldered SDRAM and graphic controller are absent and the CPU is clocked at lower speeds to reduce power consumption and allow passive cooling Finally for multiprocessing applications the PCI PCI transparent bridge is replaced by the 21554 non transparent version All models are available with or without the S3 Virge graphics controller complete with its 4 MByte high speed SGRAM The built in graphic solution not only saves space within a rack that would otherwise be taken up by an additional graphics board but due to its extremely efficient use of hardware real estate enables costs to be cut too Modularity is further assured through the use of dedicated plug in SDRAM modules The use of Disk on Ch
34. red for Windows NT by HAL modification for deterministic interrupt handling at multiple priority levels This approach achieves response times in the us range and reduces hardware resource requirements while main taining full compatibility with the enormous range of standard software and device drivers written for the Windows NT operating system 1 42 LP Elektronik A Real Time Accelerator adds real time features to Windows NT and permits operation with Win dRiver s VxWorks running concurrently on the same PC so that depending on the required level of predictability the user can get the best of both worlds Windows NT and VxWorks communicate by shared memory TCP IP on the target hardware with the shortest response times 1 43 VxWorks WindRiver s run time system solution is a high performance RTOS with a scalable microkernel and sophisticated networking facilities like TCP IP The open architecture provides efficient support of PC based architectures and feature flexible intertask communication us interrupt handling POSIX 1003 1b real time extensions and fast and flexible I O system etc 1 44 OS 9 x86 Microware s real time operating system has a track record that has been proved in the industrial embedded market and has continued to provide reliable intelligence to sophisticated applica tions OS 9 x86 s flexibility modularity and reliability in conjunction with a rich driver structure allow its use in I O intensive applications 1
35. rie COM2 Ethernet Firewire AA E hie SGRAM n3 DS21143 TSB12LV21 ontrollen 4 MByte COMI AUX COM2 JS 14 Mouse Kevboard nt South T emp USB Bridge Controller J8 ALI M1543 Floppy e 34 18 2 S J Ethernet E PROM 16 Bit I O Fireware Physical External Piggyback Physical Hard Disk e 4 Layer Extension Layer 9 Clock Q56611 Bus TSBTILVO1 d Controller XBus J12 Lp Acc FLASH Watchdog Don BIOS DISK Accelerator Interface 7 J6 jiz This block diagram is applicable to all Inova s K6 based CPUs Components and or functionality may change without notice D This includes K6 K6 2 K6 2E K6 Mobile and K6 3 socket 7 based CPUs Page 1 10 2002 Inova Computers GmbH Doc PD00030010 011 ICP K6 Product Overview 1 52 Connector Location CAN PROFIBUS INTERBUS LON Figure 1 52 Connector Locations OPTIONAL 9 SDRAM EXTENSION 6 Oo NC al e KEY 4 CPCI CONNECTOR o FLOPPY DRIVE SLIM LINE J18 o Te FLASH DISK T g O16 FLASH MEMORY p KEYBOARD MOUSE HARD DISK COM Jo e o LPT1 COM2 1 53 Connector Description Table 1 53 Connector Description Connector Description J1 J2 CompactPCI Interface Connector J3 J4 SDRAM Piggyback Expansion Interface Connector for up 64 MBytes Interface Connector for Inova Master Fieldbus Modules 100 400 Mbit s FireWire Interface 10BaseT 100BaseTx Fast Et
36. s shown in brackets Doc PD00030010 011 2002 Inova Computers GmbH Page 3 13 Interfaces ICP K6 3 25 J12 FLASH Interface J12 is proprietary and not documented here 3 26 J18 Floppy Disk Interface J18 is proprietary and not documented here but observes the standard slim line floppy sip out 3 27 COM1 COM Interfaces Both serial COM ports feature a complete set of handshaking and modem control signals maskable interrupt generation and high speed data transfer rates A front panel with COM1 COM2 mouse and keyboard interfaces is either integrated into an 8TE standard CPU front panel or available as a separate 4TE unit The piggyback located behind these interfaces connects to the CPU mounted J11 and J13 connectors Figure 3 27 COM1 COM2 Interface Pinout a D Table 3 27 COM1 COM2 Connector Signals Signal Pin No RS232 RS485 Note The standard CPU configurations has COM set to R 232 and COM2 to RS485 RxD TxD communication A two wire RS485 protocol is observed RxD TxD provided by the UART itself DCD RxD TxD DTR GND The value of Dir the Register Value is 0B when sending data and 1B when receiv DSR ing The line is active when sending and inactive when receiving Bus direction is RTS CTS Page3 14 2002 Inova Computers GmbH Doc PD00030010 01 1 ICP K6 Interfaces 3 28 J13 LPT1 Interface An additional front panel providing COM2 and a buffered LPT parallel por
37. t interface is likewise con nected to the CPU board via flat band cable to J13 Figure 3 28 LPT1 Interface Pinout lo p o 14 25 Table 3 22 LPT1 Connector Signals STROBE 2 PDO PD4 ACK Er AUTOED ew Doc PD00030010 011 2002 Inova Computers GmbH Page 3 15 Interfaces ICP K6 3 29 J11 Keyboard Interface A front panel with COM1 COM2 mouse and keyboard interfaces is either integrated into an 8TE standard CPU front panel or available as a separate 4TE unit The piggyback located behind these interfaces connects to the CPU mounted J11 connector Figure 3 29 Keyboard Interface Pinout 3 30 J11 Mouse Interface A front panel with COM1 COM2 mouse and keyboard interfaces is either integrated into an 8TE standard CPU front panel or available as a separate 4TE unit The piggyback located behind these interfaces connects to the CPU mounted J11 connector Figure 3 30 Mouse Interface Pinout Page 3 16 2002 Inova Computers GmbH Doc PD00030010 011 ICP K6 Interfaces 3 31 39 J10 Hard Disk Interface J9 and J10 are proprietary and therefore not documented here However if a hard disk is mounted on the CPU it is normally associated with the piggyback hosting the COM1 COM2 mouse and keyboard interfaces An exception being if the host CPU has more than 24 MByte FLASH installed or a fieldbus or PanelLink piggyback equipped with the remote connector allowing the interface to appear where
38. ts INTA INTB INTC INTD INTP IRQ14 INTS IRQ15 Page 2 6 2002 Inova Computers GmbH Doc PD00030010 011 ICP KG Configuration 2 5 Timer Counter The IBM compatible architecture configures the programmable timer counter Intel 8254 com patible devices for system specific functions as shown in Table 2 5 The BIOS programs Timer 0 to generate an interrupt approximately every 55ms 18 2 times per second This interrupt known as the system timer tick updates the BIOS clock and turns off the floppy disk motor drive after a few seconds of inactivity for example The BIOS featured in Inova s CPUs programs the system timer tick for PC compatibility The inter rupt generated by the timer creates an interrupt request on IRQO of the programmable interrupt controller PIC which is serviced by the CPU as interrupt vector 08h In addition Timer 1 and Timer 2 are also initialised by the BIOS as necessary for the specific processor board functions Table 2 5 Timer and Counter Functions Timer Function Assignment Timer 0 System Timer Periodic Interrupt 55 ms Timer 1 SDRAM Refresh Speaker Frequency Generator Doc PD00030010 011 2002 Inova Computers GmbH Page 2 7 Configuration iCP KG This pages has been left blank intentionally Page 2 8 2002 Inova Computers GmbH Doc PD00030010 011 ICP K6 Interfaces Interfaces Interfaces Gontents 3 0 CompactPGI J1 Je Connector 3 3
39. y to fulfil any particular application or pur pose As a result the products are sold as is and the responsibility to ensure their suitability for any given task remains the purchaser s In no event will Inova be liable for direct indirect or consequential damages resulting from the use of our hardware or software products or docu mentation even if we were advised of the possibility of such claims prior to the purchase of or during any period since the purchase of the product Please remember that no Inova employee dealer or agent are authorized to make any modification or addition to the above terms either verbally or in any other form written or electronically transmitted without consent Page 0 6 2002 Inova Computers GmbH Doc PD00030010 011 ICP K6 Product Overview Product Overview Overview Contents 1 0 ICP K6 CPU Family 1 2 EE E 1 3 1202 PenpheralS Lae er iaa 1 3 LOS S TE qe 1 3 IRET EEE E A E E E 1 3 1 1 Specifications l A 1 2 Configuration l 56 lawe 1 30 Processor OV ELVICW ad ers 1 6 Fig re 1 2 ICP K6 OVerdem iii ii era ii a AA dee REV vigi 1 7 1 3 Fieldbuses enn l 8 EAN Guess erd dido 1 8 T32 PROF veka E KEERA 1 8 FS NERE ira pra dat 1 8 1 4 Software o l 9 I HR 0015 E 1 9 PETN 1 9 LAS VIO REE EEE EE AA 1 9 1 44 0519 186 kai i iii eee a e cia 1 9 TASONA TERN 1 9 A EE 1 9 1 5 Hardware

Inova K6 User`s Manual (2002)

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