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Using Different Versions of ISE

1. Process Properties x General Options Configuration Options Startup Options Readback Options Encryption Options 2 Auto Drive Done Pin High Property Name Property display level Advanced Cancel Detault Help 72 Using Different Versions of ISE Next check the Readback O ptions against the picture below Process Properties xj General Options Configuration Options Startup Options Readback Options Encryption Options Enable Fe Create ReadBack Data Files E Allow Select F Fins to Persist Create Logic Allocation File Create Mask File Property display level Advanced Cancel Detault Help Finally check the Encryption O ptions tab against the picture shown below Process Properties xj General Options Configuration Options Startup Options Readback Options Encryption Options EncyptBitstream o Moo Key 0 Hex Sting S O Key 1 Hex Sting S O Key 2 Hes Sting S O Key 3 Hex Sting o d Key 4 Hex Sting S O Key 5 Hex Sting S O Input Encryption Key File S O Mone Starting CBC Value Hex Property display level Advanced Cancel Default Help When all tabs have been checked click O K to enter the new settings 73 Using Different Versions of ISE Step 7 Building the Project At this point the project is ready to be built All of the required design files have been added to the project and the project build settings ha
2. After the user ap entity has been added to the project you will see which other source files are required below this entity Add the appropriate source files from the Src directory After you have added all of required VHDL source files from the Src directory there may still be red question marks against entities in the hierarchy These entities will correspond to Core Gen components that are placed in the Examplel ISE directory In the case of Examplel there is one Core Gen component called fifo15x32 that must be added to the project from the ISE directory With all relevant VHDL source added to the project the Module View should look similar to the picture shown below for the FPGA 5v1 conversion Sources in Project A Ex1_Fpga5v oe EA cev 1000 4fg456 coud eros Apt vhd il ttl 5 Commons TOP vid a he dram vit s Commons HE SDRAM vid bo huu iW he_ed_entrrtl 4 CormonSHE_ SDRAM vhd fee cata he_user rtl Commons HE_USER vhd fave i W her _Bf rtl 5 Commons HE w R_EF whd ep sd user ap examplel 5rc User Ap vhd hern mE ffol St fifo Ses eco bese sew WY hab tl 4Src4HSB 1 vhd BE hiodule View t orapshot wier Ir Library Wiem 45 Using Different Versions of ISE Step 4 Adding User Constraints The next step is to add user design constraints to the project Using Project Add Source add the user constraints file contained in the ISE
3. First add the appropriate files from the Common directory in order to replace the red question mark icons with correct entities To do this you will again need to use the Add Source menu item Navigate to the Common directory and select the files that have names that match the entities in the Module View of your new project Please note the HE RD OF entity is provided in the Common directory in the source file V2 RD 6PF When adding each file the correct Source Type will be VHDL Design File as was selected when adding top vhd 62 Using Different Versions of ISE When you have added all required Hardware Interface Layer components the Module View should look similar to the picture below for the FPG Adv1 conversion ps E Esl paavi ise a a See ed Ss he sdram ic 3 Comman HE SDRAM vhid A he_sd_cntr rtl Commons HE_SDR AM vhd bite S he_uzer rtl Commons HE_USER hd as M he_wr_Bf rtl Commons HE wR BF hd ie User ap EH Module View tI Snapshot wiew M Library view Next you will need to navigate to the Src directory of Examplel and add the User Ap file to the project Add Existing Sources az x map E Look irr 3 Sr ad t se History File name User_Apt vhd hu Neth work F Files of type Sources tet vhd2 vhdl v2 abl sca sch Y Cancel After the user ap entity has been added to the project y
4. SuperS ol HUNT ENGINEERING A yp treme Lis Sl Mf Chestnut Court Burton Row Brent Knoll Somerset TA9 4BP UK Tel 44 0 1278 760188 Fax 44 0 1278 760199 Email sales hunteng co uk http www hunteng co uk http www hunt dsp com Ted meta Using Different Versions of ISE Document version 1 0 R Williams 05 05 05 HUNT ENGINEERING is a trading style of HUNT ENGINEERING U K Ltd Co Reg No 3333633 Directors P Warnes amp N J Warnes Reg d office 34 amp 38 North St Bridgwater Somerset TA6 3YD VAT Reg d No GB 515 8449 31 COPYRIGHT This documentation and the product it is supplied with are Copyright HUNT ENGINEERING 2005 All rights reserved HUNT ENGINEERING maintains a policy of continual product development and hence reserves the right to change product specification without prior warning WARRANTIES LIABILITY and INDEMNITIES HUNT ENGINEERING warrants the hardware to be free from defects in the material and workmanship for 12 months from the date of purchase Product returned under the terms of the warranty must be returned carriage paid to the main offices of HUNT ENGINEERING situated at BRENT KNOLL Somerset UK the product will be repaired or replaced at the discretion of HUNT ENGINEERING Exclusions If HUNT ENGINEERING decides that there is any evidence of electrical or mechanical abuse to the hardware then the customer shall have no recourse to HUNT ENGINEERING or its agents In su
5. Ze Select the UCF file and click Open The following window will appear to allow you to specify the design file to which the user constraints should be associated Highlight top and click OK Associate with Source e ail iaieiaiaas affects a Cancel Help 29 Using Different Versions of ISE Step 5 Adding a Simulation Test Bench Typically a project will also include a test bench for simulation For Example there is a test bench provided in the Src directory of the project This file must also be added to the project using Project gt Add Source Navigate to the Src directory highlight the file that beings TB and click Open Add Existing Sources 7 x an sim _fif owhd FTE _Ex1 vhd Ei User_Apt vhd File name TB_EX1 wha Files of type Sources tet vAd vad iv abl xcosc Cancel Ze The following window will appear where you need to specify the source type Select VHDL Test Bench and click OK x TB ES vhd te which source type The suffis ig ambiguous as to type YHEL Module VHOL Package VHDL Test Bench 30 Using Different Versions of ISE At this point the Module View should look similar to the picture shown below for the FPG Ab5v1 conversion process Sources in Froject bon a Ext _Fpuaby sick WP held BFS ACommonk2 AO_EF whd WV herck 5 CommonsHE_ARW CLK hd
6. Startup Options tab against those shown in the picture below Process Properties x General Options Configuration options startup options Readback options Encryption options Property Name Value Enable termlDone PbS Release DLL Output Events Detauk Mov vat Match Cycle Default Mov vat Drive Done Fin High Cancel Default Help 35 Using Different Versions of ISE Next check the Readback O ptions against the picture below Process Properties x General Options Configuration options Startup options Readback options Encryption options Create ReadBack Data Files E Allow SelectMAP Pins to Persist Create Logic Allocation File Create Mask Fil Cancel Default Help Finally check the Encryption O ptions tab against the picture shown below Process Properties x General Options Configuration options Startup options Readback options Encryption options Oo Properyhame ale Erorien SSS KeyO HexSting O ketes O S Keates O o Keates OO o kestesi O o keS esin OOO o metEncrytionkeyPe OO o Stang cec vae SSC S O Cancel Default Help When all tabs have been checked click OK to enter the new settings 36 Using Different Versions of ISE Step 7 Building the Project At this point the project is ready to be built All of the required design files have been added to the project and the project build settings have been checked Example1
7. Property display level Advanced Cancel Detault Help Next check the Generate Programming File properties With the General O ptions tab at the front tick the Create ASCII Configuration File and then check that all other settings match for this tab Process Properties gs X Startup Options Readback Options Encryption Options General Options Configuration Options Run Design Rules Checker DAC O O Mo ooo Create Bt File O OOS E Create Binar Configuration File ooo Create ASCII Configuration File M o o Other Bitgen Command Line Options Lo oo Z oS Property display level Advanced Cancel Default Help 71 Using Different Versions of ISE Bring the Configuration Options to the front Select Pull Up for the Unused IOB Pins item With this done check the settings match those shown in the picture below Process Properties x Startup Options Readback Options Encryption Options General Options Configuration Options Configuration Pin Powerdown Pull Up TAG Pin TCE JTAG Pin TDI JTAG Pin TOO TAG Pin TMS nused IOB Fins UselD Code 8 Digit Hexadecimal sFFFFFFFF Reset DCM if SHUTDOWN amp AGHIGH performed Disable Bandgap Generator for OCMs to save power DCI Update Mode Luiet Orr Property display level Advanced Cancel Default Help Next check the settings for the Startup Options tab against those shown in the picture below
8. WP he_sdram 4 CommonkHE SDRAM vhd ha i he_ed_entr 4 CommonsHE_SDRAM vid iV he_user 5 Commons HE _USER vhd vee i he wr Ef 4 CommonsHE_WR_BF vhd a m user_ap L SrcAUser Api vhd RE fitol 532 fifo ese eco as e WY heb 45rcAHSE1 vhd EF Module views ra Snapshot vien M Library wiew Step 6 Setting Project Build Options The last step in creating a new project is to apply the necessary project settings that will allow the design to be built correctly Ensure the file top vhd is highlighted in the Module View and then right click on Synthesize in the Process View Select Properties to open the following window With the Synthesis O ptions tab at the front check that the settings match those shown below Process Properties L x Synthesis Options HDL Options Xilinx Specific Options PropertyHame Value c Synthesis Constrarts Fe oo Hererchy sepert I C Cancel Default Help 31 Using Different Versions of ISE Next bring the HDL Options tab to the front and check that the settings match those in the picture below Process Properties xj Synthesis Options HOL Options Alling Speciic Options Cancel Default Help Next bring the Xilinx Specific Options tab to the front Change the Number of Clock Buffers item to 0 and set the Pack I O Registers into IO Bs item to No With th
9. With the existing file deleted select the menu item File gt N ew Project to begin creating a new project The following window should be displayed New Project x Project Name Froject Location JE 1_Frgabv Je MpgaSv1 ExamplelsISE 7 Project Device Options PropertyName Wale Package O y peed Grade Design Flow mol VYHOL Cancel Help Enter the correct project name in the Project Name field For Example this should be set to be the same project name as the Example project file on the HUNT ENGINEERING CD minus the ise extension Next enter the correct location into the Project Location field This field should match the location of the Example1 ISE directory you have made on your local drive Then set the Project D evice O ptions to correctly reflect the appropriate device information according to the module type you are using If you are unsure of the correct information refer to the User Manual for that module type Ensure that the Design Flow is XST VHDL When you have correctly defined all fields click OK 10 Using Different Versions of ISE Step 3 Adding VHDL Source to the New Project The next step is to add design source starting with the top level of the hierarchy For all FPGA module projects the top level of the design is always contained in the file top vhd top vhd is always provided as part of the Common directory for each module
10. 1 The first step in upgrading to ISE 7 1 is to ensure you have installed the latest service pack In the initial release of ISE 7 the project file import process for converting old projects failed to correctly read the Hierarchy Separator setting in the Synthesis Options of the existing project This was fixed in Service Pack 1 Please ensure you have completed the installation of the latest service pack before continuing through this section The next step in upgrading an existing project is to replace the contents of the Common directory with the latest FPGA support from HUNT ENGINEERING Using either the latet HUNT ENGINEERING CD or by visiting the User Area of the HUNT ENGINEERING web site www hunteng co uk download the IP for the version of FPGA module you are using to a directory on your local drive With this done replace the contents of the FPGA projects Common directory with the latest Common FPGA IP Now you are ready to open the existing project in ISE Open the ISE 7 1 Project Navigator and click File O pen Project Select the project file you wish to open Y ou should then see a window similar to that shown below Update Project A gt CeifpgaSy 1iExample 1 ISeE Ex1 FogaSyv npl This project was generated by a previous version of Project Navigator and must be updated to the new project Format Once this project has been updated you will no longer be able to open it in earlier versions of P
11. 49 SEPA Buld Mm MEFO EC IE EE E E E S T EEA J3 CREATING PROJECTS FOR ISE scsvssescicacecssssvecseckucstessencecusucenebealescatecscuasectzencavess 56 CONVERTING EXAMPLE L FOR YOUR MODULE TYPE siine ienai a a a 57 Step 1 Copying Examplel from the HUNT ENGINEERING CD icccccccssssssscecccceeeneeeesecceeeaaanssseees 57 Step 2 Creating a New Project FC icccs ccc seuss scar eat nn eis O 58 Step 3 Adding VADL Source to the New Proje csccsccccsscossdesssccsdavecsstsesecocccussesscceddenessesseesccsdsassesss 61 Step d Wading User CONST INS cocaine Sian so ts idence aes ae a a 65 Sepo Adding a SUMMATION T est BEnCh aig dha vecisveicadccaicauen voles ra ceten sda vecaaseacsdeaieureMuradadeacsa venues 66 Step 6 Setting Project Build Options ncn ehh OG ae eae ne 68 SIC 7 Bula me Me TOPCO aaa ounces AEE T A TE T 74 4 Using Different Versions of ISE Introduction For users of FPGA modules there are many example projects provided on the HUNT ENGINEERING CD These projects are intended to be the starting point when making a new FPGA design with any of the HUNT ENGINEERING FPGA modules All of the example projects are designed to be used with the standard tool set provided by Xilinx there is a separate application note Using non ISE development tools available for users working with development tools such as Leonardo Spectrum or Synplicity The standard FPGA design tool from Xilinx is the integrated design environment ISE Over time X
12. ENGINEERING CD The first step in the conversion process is to copy Examplel onto your local hard drive Make a directory on your local drive in which to store Examplel On the HUNT ENGINEERING CD all FPGA examples are provided below the fpga directory The fpga directory is divided into sub directories that reflect the name of the module type In this document Examplel for the HERO N FPG A35 is to be converted so the directory fpga fpgadv1 will contain the appropriate project information Identify the appropriate CD directory according to your module type With the correct CD directory located you will need to copy Example 1 to your local drive This can be done in one of two ways The first method is to copy the Example 1 project by hand for the module type you are using The second method is to unzip the ZIP file for that module type onto your hard drive When using the first approach you will need to copy the Common directory and Example directory from the CD to a chosen directory on your local drive The Examplel directory contains all design source that forms Examplel and the Common directory provides design source common to all designs made for that module Please note when copying files from your CD by hand you may need to edit the file attributes after copying This is because on some operating systems Read Only files on the CD will become Read Only files on your local drive All files in th
13. example for each module type and should always be used as the first step in FPGA development This section describes how to convert Examplel for the HERON FPGADO as an example of the conversion process Although the design source varies for each module type the principles shown here are the same regardless of type Step 1 Copying Example1 from the HUNT ENGINEERING CD The first step in the conversion process is to copy Examplel onto your local hard drive Make a directory on your local drive in which to store Examplel On the HUNT ENGINEERING CD all FPGA examples are provided below the fpga directory The fpga directory is divided into sub directories that reflect the name of the module type In this document Example1 for the HERON FPGAbO is to be converted so the directory fpga fpgadv1 will contain the appropriate project information Identify the appropriate CD directory according to your module type With the correct CD directory located you will need to copy Example 1 to your local drive This can be done in one of two ways The first method is to copy the Example 1 project by hand for the module type you are using The second method is to unzip the ZIP file for that module type onto your hard drive When using the first approach you will need to copy the Common directory and Example directory from the CD to a chosen directory on your local drive The Examplel directory contains all design source t
14. of required VHDL source files from the Src directory there may still be red question marks against entities in the hierarchy These entities will correspond to Core Gen components that are placed in the Examplel ISE directory In the case of Examplel there is one Core Gen component called fifo15x32 that must be added to the project from the ISE directory With all relevant VHDL source added to the project the Module View should look similar to the picture shown below for the FPGA 5v1 conversion Sources in Project A Ex1_Fpga5v oe EA cev 1000 4fg456 coud eros Apt vhd il ttl 5 Commons TOP vid a he dram vit s Commons HE SDRAM vid bo huu iW he_ed_entrrtl 4 CormonSHE_ SDRAM vhd fee cata he_user rtl Commons HE_USER vhd fave i W her _Bf rtl 5 Commons HE w R_EF whd ep sd user ap examplel 5rc User Ap vhd hern mE ffol St fifo Ses eco bese sew WY hab tl 4Src4HSB 1 vhd BE hiodule View t orapshot wier Ir Library Wiem 28 Using Different Versions of ISE Step 4 Adding User Constraints The next step is to add user design constraints to the project Using Project Add Source add the user constraints file contained in the ISE directory of the project Add Existing Sources TES Look in EISE amp ce EE fifol 5x32 xc0 File name E 1 FogaSy uct Cancel Files of type Sources tet vad sco sch tby bmm
15. of the required design elements to ensure correct operation on that chosen module type These elements include a Hardware Interface Layer that is used to correctly control external devices user constraints information to control design timing and pin location and example VHDL to provide a structured starting point This section describes how to build an ISE 7 1 project from scratch using the design source provided on the CD This document uses Examplel as the starting point for the creation of a new project It is important to start from one of the standard examples provided on the HUNT ENGINEERING CD as this give the correct starting point for FPGA development with your FPGA module Please note if you are using this section in order to create a brand new project with functionality that does not match any of the standard CD examples then you must still start from Example1 Once you have created a correct project based around Examplel you may then insert your own unique code into the User Ap entity removing all unwanted logic When doing this you will need to refer to the relevant information in the Making your own FPGA design section of your FPGA User Manual 56 Using Different Versions of ISE Converting Examplel for your Module Type The HUNT ENGINEERING CD provides support for many different FPGA module types For each module there is always a standard Example project provided on the CD This example is the Getting Started
16. project you will see which other source files are required below this entity Add the appropriate source files from the Src directory After you have added all of required VHDL source files from the Src directory there may still be red question marks against entities in the hierarchy These entities will correspond to Core Gen components that are placed in the Examplel ISE directory In the case of Examplel there is one Core Gen component called fifo15x32 that must be added to the project from the ISE directory With all relevant VHDL source added to the project the Module View should look similar to the picture shown below for the FPGA 5v1 conversion Sources in Project A Ex1_Fpga5v oe EA cev 1000 4fg456 coud eros Apt vhd il ttl 5 Commons TOP vid a he dram vit s Commons HE SDRAM vid bo huu iW he_ed_entrrtl 4 CormonSHE_ SDRAM vhd fee cata he_user rtl Commons HE_USER vhd fave i W her _Bf rtl 5 Commons HE w R_EF whd ep sd user ap examplel 5rc User Ap vhd hern mE ffol St fifo Ses eco bese sew WY hab tl 4Src4HSB 1 vhd BE hiodule View t orapshot wier Ir Library Wiem 13 Using Different Versions of ISE Step 4 Adding User Constraints The next step is to add user design constraints to the project Using Project Add Source add the user constraints file contained in the ISE directory of the project Add Existing Sources TES Lo
17. type Select the menu item Project gt Add Source The following window will be displayed where you will need to navigate to the Common directory that was created on your local drive Select the file top vhd and click O pen E Fpga5v_tpl ucf 5l SIM_M5G vhd USER_4P_TPL vhd HE_CONY vhd El SIM_RD_6F vhd v2 _RD_6F vhd HE _RWCLK vhd B SIM_ SDRAM vhd Ea HE_SDRAM vhd SIM_WR_6F vhd HE_UISER vhd El SYN y _RD_6F vhd File name TOP vhd Files of type Sources tet vAd vad iv abl xcosc Cancel Ze The following window will then appear Select VHDL Module and click OK to add top vhd to the project Choose Source Type I x TOP vhd t which source type The suffis ig ambiguous as to type VHDL Package VHDL Test Bench Cancel Help Il Using Different Versions of ISE With this done the Module View window will now look similar to the picture below depending on the particular source files that are required by the module type you are using Sources in Projac pee fE Ex Fogaby ae 1 caw 1000 ika In the case of the FPG A5v1 example conversion after adding top vhd we can now see 6 more design entities are needed One of these entities is the User A pplication level of the design which contains the VHDL that makes this example the getting started example Example1 The other entities shown are part of the Hardware Interf
18. unzipping all examples for that module including Examplel When unzipping all project examples the read write attributes will automatically be set correctly The picture below shows a new directory on the local drive named fpga In the fpga directory are the copied Common and Example directories inf ISE 24 Using Different Versions of ISE Step 2 Creating a New Project File With the Examplel example directory and Common directory copied onto your Local Drive you can now begin building an ISE 5 project Open the ISE 5 Project Navigator if it is not already open Please note in the remainder of this section an example conversion is shown for Example 1 for the HERON FPGA S where this conversion is performed in ISE 5 2 If you are using a different ISE 5 version then although the windows shown may not perfectly match the conversion process is still the same Next delete the project file for the Examplel project in the new directory you have created on your local drive The project file will be located in the ISE sub directory of the Examplel directory and will have the extension ise This existing project file must be removed as it will not be useable in ISE 5 and must be replaced with an appropriately constructed project file With the existing file deleted select the menu item File gt N ew Project to begin creating a new project The following window should be displayed New Pr
19. Goal ss o EE Synthesis Constraints File 0 0 000000 Library Search Order O 2 00 Cores Search Directories Hierarchy Separator O O 0000 d HOLINI Fie o O Verilog Include Directories 2 2 2 2 202020222 Custom Compile File List OthersST Command Line Options Property display level Advanced x Cancel Detault Help 68 Using Different Versions of ISE Next bring the HDL Options tab to the front and check that the settings match those in the picture below Process Properties xj Synthesis Options HOL Options alins Specific Options Property Name Multiplier Style Property display level Advanced Cancel Detault Help Next bring the Xilinx Specific Options tab to the front Change the Number of Clock Buffers item to 0 and set the Pack I O Registers into IO Bs item to No With this done check that the settings match those in the picture below Process Properties x Synthesis Options HOL Options Alins Specific Options ey Number of Cock Bue Hove Last FipFlop Stage NJ Property display level Advanced Cancel Default Help 69 Using Different Versions of ISE Click on the OK button at the bottom of the window to apply the new settings Next the Translate Properties must be checked With the file top vhd still highlighted in the Module View nght click on Translate in the Process View Select Properties to
20. History 1 0 05 05 05 First Written 3 Using Different Versions of ISE TABLE OF CONTENTS INTRODUC TION i even evecnb ves A 5 HOW TO USE THIS DOCUMEN Piccsccccsscadavesiaietecccwsdacteieteasetenetstvessteceasccewseversdeasosenees 6 UPGRADING TO THE LATEST VERSION OF IS Biss 368 bil ie ko Re E 6 CONTINUING TO USE A PREVIOUS VERSION OF ISE eee eeesesseseeseeeeeneeseseessesssessssssssssesseeaaaaaeaaaeaaaeees 6 CREATING NEW PROSE CUS cogs cts cence cs casa exo ces E A asa a eon eee nee 6 UPGRADING EXISTING PROJECTS TO ISE 7 1 ccssssssscccsssssccccccesscees 7 CREA TING PROJECTS FOR ISE G4 svesieccesecscanctesscceceeteedevecetcaacesveudevedeecetueaieudevecoteaess 8 CONVERTING EXAMPLE FOR YOUR MODULE TYPE crinii e co nnspnode peonetbennetewadenenene semocsnecepens 9 Step 1 Copying Examplel from the HUNT ENGINEERING CD icccccccssssseesscccceeeeeeeeeeeceeeecaaseeseeees 9 Step 2 Credtins a New Project 1 Coie Boies canes Bia a sae NGl eal kes Aor sete ia ed tases 10 Step 3 Adding VHDL Source to the New Project cc sis cccccesteseesecccsacessvsssscodcessessseectecendeesssecedersosssase Il SLC Addie USEF CONSTA S cases eH oko aint a ci al a he Aare elise aloes oni oe 14 Sepa Addme a Simulation Test Bench arrra lesa iea etic ETEA eo See sen eta 13 Sep O setine Project Build OPNONS riesene ea E A AT 16 Sepo bula MENE PTO eCie E EN E E EE 22 CREATING PROJECTS FOR ISE 5 sdsssesccsscsscesccesssicase catssstivsscececestsest
21. NX provide no mechanism for converting post ISE 4 projects back to ISE 4 This document uses Example1 as the starting point for the creation of a new project It is important to start from one of the standard examples provided on the HUNT ENGINEERING CD as this give the correct starting point for FPGA development with your FPGA module Please note if you are using this section in order to create a brand new project with functionality that does not match any of the standard CD examples then you must still start from Example1 Once you have created a correct project based around Examplel you may then insert your own unique code into the User Ap entity removing all unwanted logic When doing this you will need to refer to the relevant information in the Making your own FPGA design section of your FPGA User Manual 8 Using Different Versions of ISE Converting Examplel for your Module Type The HUNT ENGINEERING CD provides support for many different FPGA module types For each module there is always a standard Example project provided on the CD This example is the Getting Started example for each module type and should always be used as the first step in FPGA development This section describes how to convert Examplel for the HERON FPGADO as an example of the conversion process Although the design source varies for each module type the principles shown here are the same regardless of type Step 1 Copying Example1 from the HUNT
22. R a DisetleRegster Ovteng Cancel Default Help 18 Using Different Versions of ISE Next check the Place and Route process properties For Examplel the Place amp Route Effort Level Overall typically needs to be set to Normal Make this change and check all other settings match the picture below and click OK Process Properties x Place amp Route Properties Propertyame ate Place amp Route Effort Level Overa Cc M Guide File Guide Mode Generate Detaied FAR Rep Mo Cancel Default Help Next check the Generate Programming File properties With the General O ptions tab at the front tick the Create ASCII Configuration File and then check that all other settings match for this tab TT x a Use Timing Constraints E Startup options Readback options Encryption options General Options Configuration options Oo Properyhame ate Cancel Default Help 19 Using Different Versions of ISE Bring the Configuration Options to the front Select Pull Up for the Unused IOB Pins item With this done check the settings match those shown in the picture below Process Properties xj Startup options Readback options Encryption options General Options Configuration options _PropertyName Ye O Conngwatone O ooo S p T ac Fin UME e Code 5 Digit Hexadecimal OxFFFFFFFF Reset DCM if SHUTDOWN amp AGHIGH perf
23. SE directory of the project Add Existing Sources Look ir aise d t ep E FifolSe32 xco My Documents My Computer c File name Ex _Fpgabw uct My Network F Cancel Files of type Sources tst vid vhdl ve abl eco sch Y Select the UCF file and click O pen The following window will appear to allow you to specify the design file to which the user constraints should be associated Highlight top and click OK he raclk he rdf Cancel he_uzer he_sdram Help 65 Using Different Versions of ISE Step 5 Adding a Simulation Test Bench Typically a project will also include a test bench for simulation For Example there is a test bench provided in the Src directory of the project This file must also be added to the project using Project gt Add Source Navigate to the Src directory highlight the file that beings TB and click Open Add Existing Sources eS My Documents My Computer TAE w E TB_EX1 vhd ho Network P Files of type Sources tst vid vhdl v abl eco sch Y Cancel The following window will appear where you need to specify the source type Select VHDL Test Bench File and click OK Choose Source Type TBE vid ts which source type The suffis ig ambiguous as to type igh File oK VHOL Test Bench File Cancel Help A
24. Select the type of Top Level module for the Project Top Level Module Type H L 4 Back Next gt Cancel Help Enter the correct project name in the Project Name field For Example this should be set to be the same project name as the Example project file on the HUNT ENGINEERING CD minus the ise extension Next enter the correct location into the Project Location field This field should match the location of the Examplel ISE directory you have made on your local drive Next ensure the Top Level Module Type field is set to HDL 40 Using Different Versions of ISE With these steps completed click on the Next gt button at the bottom of the window to display the following Mew Project i x Select the Device and Design Flow for the Project Property Name _ Yale __i Do y Top Level Module Type Synthesis Tool Simulator Generated Simulation Language Back Cancel Help Fill out the appropriate device information according to the module type you are using If you are unsure of the correct information refer to the User Manual for that module type When you have done this click the Next gt button The following window will then be displayed Simply click Next gt x Create a New Source SoueeFile Tye NewSouce TSS eee ees Remove Create a new source to add to the project optional Only one new source can be speched now Additional new sou
25. ace Layer and are found in the Common directory First add the appropriate files from the Common directory in order to replace the red question mark icons with correct entities To do this you will again need to use the Add Source menu item Navigate to the Common directory and select the files that have names that match the entities in the Module View of your new project Please note the HE RD OF entity is provided in the Common directory in the source file V2 RD OF When adding each file the correct Source Type will be VHDL Module as was selected when adding top vhd When you have added all required Hardware Interface Layer components the Module View should look similar to the picture below for the FPG Adv1 conversion Sources in Project mon A Ex1_Foogahv os a acy 1000 oe he dram alt 5 Commons HE SDRAM vhid ke a he_sd_cntr rtl 04 SCommonSHE_ SORAM hd Bese ay he_user rtl Common HE_USER vhd Heee H he wr _Bf rtl 4 Commons HE w A_EF hd m User ap EF hlodule view t snapshot wien M Library Wien 12 Using Different Versions of ISE Next you will need to navigate to the Src directory of Examplel and add the User Ap file to the project Look in Sy Sre ct EJ File name u ser Apl vhd Cancel AE Files of type Sources tat vads vhdl v abl sco ec T After the user ap entity has been added to the
26. ample wISE Project Type HDL Device Device Family Yirtex2 Device acev 1000 Package fg456 Speed Grade 4 Top Level Module Type HOL Synthesis Took 5T MHOL verlag Simulator SE Simulator Generated Simulation Language HDL lt Back Cancel Help 60 Using Different Versions of ISE Step 3 Adding VHDL Source to the New Project The next step is to add design source starting with the top level of the hierarchy For all FPGA module projects the top level of the design is always contained in the file top vhd top vhd is always provided as part of the Common directory for each module type Select the menu item Project gt Add Source The following window will be displayed where you will need to navigate to the Common directory that was created on your local drive Select the file top vhd and click O pen Add Existing Sources axl Look in E Common e c E ma Fpga5v_tpl ucf TOP hd a E HE_CONY vhd S USER_AP_TPL vhd History a HERCLE vhd We RD BF vhd HE SDRAM vhd HE_UISER vhd E HE_WR_6F vhd SIM_M5G vhd SIM_RD 6F vhd SIM_SDRAM vhd E SIM_WR_6F vhd a SY M_V2_RO_6F vhd Wip ce puter eo File name TOP vha My Network F pa Files of type Sources tet vhd vhdl v2 abl sco sch Y Cancel The following window will then appear Select VHDL Design File and click OK to add top vhd to the project Choose So
27. b directories that reflect the name of the module type In this document Examplel for the HERO N FPG A35 is to be converted so the directory fpga fpgadv1 will contain the appropriate project information Identify the appropriate CD directory according to your module type With the correct CD directory located you will need to copy Example 1 to your local drive This can be done in one of two ways The first method is to copy the Example 1 project by hand for the module type you are using The second method is to unzip the ZIP file for that module type onto your hard drive When using the first approach you will need to copy the Common directory and Example directory from the CD to a chosen directory on your local drive The Examplel directory contains all design source that forms Examplel and the Common directory provides design source common to all designs made for that module Please note when copying files from your CD by hand you may need to edit the file attributes after copying This is because on some operating systems Read Only files on the CD will become Read Only files on your local drive All files in the Example directory should be set to Read Write while all files in the Common directory must remain Read Only When using the second approach you will be unzipping all examples for that module including Examplel When unzipping all project examples the read write attributes will automatica
28. ch circumstances HUNT ENGINEERING may at its discretion offer to repair the hardware and charge for that repair Limitations of Liability HUNT ENGINEERING makes no warranty as to the fitness of the product for any particular purpose In no event shall HUNT ENGINEERING S liability related to the product exceed the purchase fee actually paid by you for the product Neither HUNT ENGINEERING nor its suppliers Shall in any event be liable for any indirect consequential or financial damages caused by the delivery use or performance of this product Because some states do not allow the exclusion or limitation of incidental or consequential damages or limitation on how long an implied warranty lasts the above limitations may not apply to you TECHNICAL SUPPORT Technical support for HUNT ENGINEERING products should first be obtained from the comprehensive Support section www hunteng co uk support index htm on the HUNT ENGINEERING web site This includes FAQs latest product software and documentation updates etc Or contact your local supplier if you are unsure of details please refer to www hunteng co uk for the list of current re sellers HUNT ENGINEERING technical support can be contacted by emailing Support hunteng demon co uk calling the direct support telephone number 44 0 1278 760775 or by calling the general number 44 0 1278 760188 and choosing the technical support option 2 Using Different Versions of ISE Document
29. directory of the project Add Existing Sources j 2x Look in Sy ISE amp eX FE Exl_Fpgasy B Ex1_Fpga5v uct fifol5x32 edn Fifo1sx32 vhd S ffol 532 xc0 File name Ex1_Fpga5v uci Files of type Sources tet vhd vad iv abl xcosc Cancel Ze Select the UCF file and click Open The following window will appear to allow you to specify the design file to which the user constraints should be associated Highlight top and click OK Associate with Source x ssociate Ex FogaSy uch with the source that it affects he_sdrami he_sd_cntr EE he User he_rd_6f he _ wr bf Help 46 Using Different Versions of ISE Step 5 Adding a Simulation Test Bench Typically a project will also include a test bench for simulation For Examplel there is a test bench provided in the Src directory of the project This file must also be added to the project using Project gt Add Source Navigate to the Src directory highlight the file that beings TB and click Open Add Existing Sources 8 8 ax Look ir E SIC do t be File name TB_EXt hid Files of type Cancel Sources tet vad vhdl vc abl sco ac T ZA The following window will appear where you need to specify the source type Select VHDL Test Bench File and click OK Choose Source Type x TB OES vhd i which source type The suffis
30. e Example directory should be set to Read Write while all files in the Common directory must remain Read Only When using the second approach you will be unzipping all examples for that module including Examplel When unzipping all project examples the read write attributes will automatically be set correctly The picture below shows a new directory on the local drive named fpga In the fpga directory are the copied Common and Example directories inf ISE 9 Using Different Versions of ISE Step 2 Creating a New Project File With the Examplel example directory and Common directory copied onto your Local Drive you can now begin building an ISE 4 project Open the ISE 4 Project Navigator if it is not already open Please note in the remainder of this section an example conversion is shown for Example 1 for the HERON FPGA S where this conversion is performed in ISE 4 1 If you are using a different ISE 4 version then although the windows shown may not perfectly match the conversion process is still the same Next delete the project file for the Examplel project in the new directory you have created on your local drive The project file will be located in the ISE sub directory of the Examplel directory and will have the extension ise This existing project file must be removed as it will not be useable in ISE 4 and must be replaced with an appropriately constructed project file
31. e front Change the Number of Clock Buffers item to 0 and set the Pack I O Registers into IO Bs item to No With this done check that the settings match those in the picture below Process Properties xj Synthesis Options HEL Options lins Specific Options PropertyHame Yawe _ Number of Clock Butters wooo eqister Duplication quivalent Register Removal eqister Balancing Move First Flip Flop Stage Move Last Flip Flop Stage lice Packing ack HO Registers into Bs Cancel Default Help 17 Using Different Versions of ISE Click on the OK button at the bottom of the window to apply the new settings Next the Translate Properties must be checked With the file top vhd still highlighted in the Module View nght click on Translate in the Process View Select Properties to open the following window Tick the item Allow Unmatched LOC Constraints check all other settings match and click OK Process Properties x Translate Properties _PropertyHame Yawe Macro Search Path LL a User Rules File for Metlister Launcher i Allow Unmatched LOC Constraints Preserve Hierarchy on Sub Module Cancel Default Help Next open the Process Properties window for the Map process Check that the settings match those in the picture below Process Properties B Map Properties PropertyWame Yawe _ Use cude Desi Fle ned OO Use RLOC constans
32. eady to be built All of the required design files have been added to the project and the project build settings have been checked Example1 should now build as far as bitstream generation without error Although each example project supplied on the HUNT ENGINEERING CD will differ from Examplel the process to create a new project for ISE 4 is the same The routine described in this section can therefore be repeated for each of the standard examples provided on the CD 22 Using Different Versions of ISE Creating Projects for ISE 5 For each FPGA module type each project contained on the CD provides all of the required design elements to ensure correct operation on that chosen module type These elements include a Hardware Interface Layer that is used to correctly control external devices user constraints information to control design timing and pin location and example VHDL to provide a structured starting point For users of ISE 5 design tools this document must be followed in order to convert the newer project format used on the HUNT ENGINEERING CD to the correct ISE 5 format This section describes how to build an ISE 5 project from scratch using the design source provided on the CD This process is necessary as the standard XILINX tool version has moved on from ISE 5 and XILINX provide no mechanism for converting post ISE 5 projects back to ISE 5 This document uses Examplel as the starting point for the creation of a new project It is
33. eceaseseeseesssstasess 23 CONVERTING EXAMPLE FOR YOUR MODULE TYPE sccscessassiixsnoscnd eapenthathsmacnleanecshaeeabastccevess a aa 24 Step 1 Copying Examplel from the HUNT ENGINEERING CD iiccccccccsssseesccccceeeeeeeeeecceeeaaaneseeees 24 Step 2 Creating d New Project FA Creag scecsticsrsshintnsrcaessirsseend einninciga cious sii siete 25 Step 3 Adding VHDL Source to the New Project ccccccccccsssseccccccccccseesseceeecaeesseeceeeeeaaassseseeseeaaaaeseees 26 LC Adin OU SCF CON SITING asea E cocoa lea es tied asides ad Goloeac as elas ees biactidees acetoacetate 29 Slepo Addmg a Simulati n Test BENCH tires k vescapenes se a e EEEE Behcadaanstaceimesad EE 30 Step 0 vettme Project Build OPNS o ncr Non A ae Dera ee eo aaa 31 SIC 7s Buldain Me PrO O ra ES A ETE TENA OE ORAS 37 CREATING PROJECTS FOR ISE 6 sssssceccccccssssccecccsssscccceccsssssscceeososssssceeeesssssss 38 CONVERTING EXAMPLE FOR YOUR MODULE TYPE crurponinea ea e a 39 Step 1 Copying Examplel from the HUNT ENGINEERING CD iicccccccssssssesccccceteeeeeesccceseaaaeeseeees 39 Step 2 Credting a New Project Files sean Rao E e a bate eae bee 40 Step 3 Adding VHDL Source to the New Project vcscsesscascccssiscsveccesensessssssccdevssvssssccscecedeesssesedsendessees 43 Sepa Addie User CONSTTATUS shes Sires le E E tee ones ele eeeelanen 46 SCD COIN OS UNO ON A ESB E saa r ccs ruben E lOve Gia Des anins texas ATE ORT 47 SLC O SUING Project buld ODTONS ricer e E E
34. eck the Readback O ptions against the picture below Process Properties x General Options Configuration Options Startup Options Readback Options Encryption Options Property Name Cancel Default Help Finally check the Encryption O ptions tab against the picture shown below Process Properties xj General Options Configuration Options Startup Options Readback Options Encryption Options Encrypt Bitstream ooo ooo Key 0 Hex Sting Key 1 Hex Stino 0 S Key 2 Hex Stino S Key 3 Hex Stino 0 Key 4 Hex Sting S Key 5 Hex Stino 0 d Input Encryption Key File o d Starting CBC Yalue Hemp Cancel Default Help When all tabs have been checked click O K to enter the new settings 54 Using Different Versions of ISE Step 7 Building the Project At this point the project is ready to be built All of the required design files have been added to the project and the project build settings have been checked Example1 should now build as far as bitstream generation without error Although each example project supplied on the HUNT ENGINEERING CD will differ from Examplel the process to create a new project for ISE 6 is the same The routine described in this section can therefore be repeated for each of the standard examples provided on the CD 55 Using Different Versions of ISE Creating Projects for ISE 7 For each FPGA module type each project contained on the CD provides all
35. el Help Fill out the appropriate device information according to the module type you are using If you are unsure of the correct information refer to the User Manual for that module type When you have done this click the Next gt button The following window will then be displayed Simply click Next gt New Project x Create a New Source SouceFile Tye NewSouce SS Tas Remove Create a new source to add to the project optional Only one new source can be speched now Additional new sources can be added after project creation using the Proyect gt New Source command Existing sources can be added on the next page Cancel Help 59 Using Different Versions of ISE The following window will then be displayed Again click Next gt CT ke i x Add Existing Sources Source File Type Copy to Projec 2E ia Add Source Remove Add existing sources to the project optional Additional sources can be added after project creation Using the Froject Add Source or Project 4dd Copy of Source commands Cancel Help Finally the following window is displayed providing a summary of all the project information you have entered Click Finish to make the new project file New Project Information x Project Navigator will create a new Project with the following specifications Project Name Ext Fogaby Project Location c fogaSy7 SE s
36. elete the project file for the Examplel project in the new directory you have created on your local drive This must be done as we are about to create a new project file With the existing file deleted select the menu item File gt N ew Project to begin creating a new project The following window should be displayed New Project I x Enter a Name and Location for the Project Project Name Project Location JE 1_Frgabv c Sipga5v SExarmplel ISE me Select the type of Top Level module for the Project Top Level Module Type H L 4 Back Next gt Cancel Help Enter the correct project name in the Project Name field For Example this should be set to be the same project name as the Example project file on the HUNT ENGINEERING CD minus the ise extension Next enter the correct location into the Project Location field This field should match the location of the Examplel ISE directory you have made on your local drive Next ensure the Top Level Module Type field is set to HDL 58 Using Different Versions of ISE With these steps completed click on the Next gt button at the bottom of the window to display the following New Project x Select the Device and Design Flow for the Project Virtex2 evice an DOU Grade o O Top Level Module Type Synthesis Tool oT HOLA enlog ISE Simulator Generated Simulation Language VHDL lt Back Canc
37. elopment with your FPGA module Please note if you are using this section in order to create a brand new project with functionality that does not match any of the standard CD examples then you must still start from Example1 Once you have created a correct project based around Examplel you may then insert your own unique code into the User Ap entity removing all unwanted logic When doing this you will need to refer to the relevant information in the Making your own FPGA design section of your FPGA User Manual 38 Using Different Versions of ISE Converting Examplel for your Module Type The HUNT ENGINEERING CD provides support for many different FPGA module types For each module there is always a standard Example project provided on the CD This example is the Getting Started example for each module type and should always be used as the first step in FPGA development This section describes how to convert Examplel for the HERON FPGAO as an example of the conversion process Although the design source varies for each module type the principles shown here are the same regardless of type Step 1 Copying Example1 from the HUNT ENGINEERING CD The first step in the conversion process is to copy Examplel onto your local hard drive Make a directory on your local drive in which to store Examplel On the HUNT ENGINEERING CD all FPGA examples are provided below the fpga directory The fpga directory is divided into su
38. ght click on Translate in the Process View Select Properties to open the following window Tick the item Allow Unmatched LOC Constraints check all other settings match and click OK Process Properties x Translate Properties Property Name Use LOC Constraints Nethst Translation Type Macro Search Path Create I O Pads from Parts User Rules File for Netlister Launcher Allow Unmatched LOC Constraints M S Other Nadbuild Command Line Options Cancel Default Help Next open the Process Properties window for the Map process Check that the settings match those in the picture below Process Properties q x Map Properties Perform Timing Driven Packing and Placement gt MAP Guide Design File ned o o O Coe eC iua Sn Tristate Buffer Transformation Mode JOR S Other Map Command Line Options o O Cancel Default Help 51 Using Different Versions of ISE Next check the Place and Route process properties For Examplel the Place amp Route Effort Level O verall typically needs to be set to Medium Make this change and check all other settings match the picture below and click OK Process Properties x Place amp Route Properties Place amp Route Effort Level Overal TESST E None omal Place and Route AR Guide Mode onver Guide File to 6 11 Format se Timing Constraints Cancel Detault Help Next check the Generate Programming Fi
39. hat forms Examplel and the Common directory provides design source common to all designs made for that module Please note when copying files from your CD by hand you may need to edit the file attributes after copying This is because on some operating systems Read Only files on the CD will become Read Only files on your local drive All files in the Example directory should be set to Read Write while all files in the Common directory must remain Read Only When using the second approach you will be unzipping all examples for that module including Examplel When unzipping all project examples the read write attributes will automatically be set correctly The picture below shows a new directory on the local drive named fpga In the fpga directory are the copied Common and Example directories inf ISE 57 Using Different Versions of ISE Step 2 Creating a New Project File With the Examplel example directory and Common directory copied onto your Local Drive you can now begin building an ISE 7 project Open the ISE 7 Project Navigator if it is not already open Please note in the remainder of this section an example conversion is shown for Example 1 for the HERON FPGA S where this conversion is performed in ISE 7 1 with Service Pack 1 installed If you are using a different ISE 7 version then although the windows shown may not perfectly match the conversion process is still the same Next d
40. ig ambiguous as to type WHOL Design File VHOL Test Bench File 47 Using Different Versions of ISE At this point the Module View should look similar to the picture shown below for the FPG A5v1 conversion process Sources in Project a E Esl_Fpgabw on Ed ecey1000 4fg456 PY oul Norch L ser Hal i l ss lad restbenehr ene ATB Ee vhd l U Ex1_Fpga5v uct AA he_rd_6f rtl 5 Common 2 _AD_EF vhd AP he_naclk rtl 5 Commons HE_RW CLK vid AA he_sdram rtl 5 Commons HE_SDARAM whd ee fF he ed_entrrl 4 CommonsHE_SDAAM vhd seve a he_user rtl Common HE_USER vd l ven a he wr _Ef rtl Commons HE WR_6F vhd a M user_ap esamplel SrcUser Ap vhd hene mE ffol 532 fifo 5532 eco Here soe WY habl Srch H561 whd EH hiodule View t ahapshot wier M Library Wien 48 Using Different Versions of ISE Step 6 Setting Project Build Options The last step in creating a new project is to apply the necessary project settings that will allow the design to be built correctly Ensure the file top vhd is highlighted in the Module View and then right click on Synthesize in the Process View Select Properties to open the following window With the Synthesis O ptions tab at the front check that the settings match those shown below Process Properties Synthesis Options HDL Options Xilinx Specific Options aintain ote Werilog I
41. ilinx make improvements to the ISE product and release major version changes As each new version of design tools is released HUNT ENGINEERING adapt the standard FPGA module examples so they continue to work as expected Each time a new version of ISE is released users may either continue working with their current version of tools or upgrade to the new version Whether continuing with their current version of ISE or upgrading this document describes what must be done to ensure that the HUNT ENGINEERING FPGA examples continue to work as expected In addition this document describes how to make a brand new FPGA project in ISE 5 Using Different Versions of ISE How to Use this Document The following three sections describe how to use this document depending on whether you are upgrading ISE continuing with your existing version or making a new project from scratch Upgrading to the Latest Version of ISE The latest version of ISE is version 7 1 The FPGA module examples on the current HUNT ENGINEERING CD are written to use ISE 7 1 For users upgrading to ISE 7 1 this simply means that any of the examples on the latet CD can be copied and used without any issue of upgrading the project In this situation therefore the remainder of this document does not apply However for users who are upgrading to ISE 7 1 any existing project based around FPGA modules will need to be upgraded To upgrade an existing FPGA module project to ISE 7 1
42. important to start from one of the standard examples provided on the HUNT ENGINEERING CD as this give the correct starting point for FPGA development with your FPGA module Please note if you are using this section in order to create a brand new project with functionality that does not match any of the standard CD examples then you must still start from Example1 Once you have created a correct project based around Examplel you may then insert your own unique code into the User Ap entity removing all unwanted logic When doing this you will need to refer to the relevant information in the Making your own FPGA design section of your FPGA User Manual 23 Using Different Versions of ISE Converting Examplel for your Module Type The HUNT ENGINEERING CD provides support for many different FPGA module types For each module there is always a standard Example project provided on the CD This example is the Getting Started example for each module type and should always be used as the first step in FPGA development This section describes how to convert Examplel for the HERON FPGADO as an example of the conversion process Although the design source varies for each module type the principles shown here are the same regardless of type Step 1 Copying Example1 from the HUNT ENGINEERING CD The first step in the conversion process is to copy Examplel onto your local hard drive Make a directory on your local drive in which to store Examp
43. is done check that the settings match those in the picture below Process Properties xj Synthesis Options HEL Options lins Specific Options PropertyHame Yawe _ Number of Clock Butters wooo eqister Duplication quivalent Register Removal eqister Balancing Move First Flip Flop Stage Move Last Flip Flop Stage lice Packing ack HO Registers into Bs Cancel Default Help 32 Using Different Versions of ISE Click on the OK button at the bottom of the window to apply the new settings Next the Translate Properties must be checked With the file top vhd still highlighted in the Module View nght click on Translate in the Process View Select Properties to open the following window Tick the item Allow Unmatched LOC Constraints check all other settings match and click OK Process Properties x Translate Properties _PropertyHame Yawe Macro Search Path LL a User Rules File for Metlister Launcher i Allow Unmatched LOC Constraints Preserve Hierarchy on Sub Module Cancel Default Help Next open the Process Properties window for the Map process Check that the settings match those in the picture below Process Properties B Map Properties PropertyWame Yawe _ Use cude Desi Fle ned OO Use RLOC constans R a DisetleRegster Ovteng Cancel Default Help 33 Using Different Versions of ISE Next check the Place and Route pr
44. le properties With the General O ptions tab at the front tick the Create ASCII Configuration File and then check that all other settings match for this tab Process Properties Startup Options Readback Options Encryption Options General Options Configuration Options Property Hame un Design Rules Checker DAC reate Bit File reate Binary Configuration File reate ASCII Configuration File reate IEEE 1532 Configuration File nable BitStream Compression Enable Debugging of Bitstream Enable Cyclic Redundancy Checking CRC Other Bitgen Command Line Options Ld Cancel Default Help 52 Using Different Versions of ISE Bring the Configuration Options to the front Select Pull Up for the Unused IOB Pins item With this done check the settings match those shown in the picture below Process Properties x Startup Options Readback Options Encryption Options General Options Configuration Options Configuration Rate O E A Pin TMS a Reset DCM SHUTDOWN LAGHIGH poiome O Disable Bandgap Generator for DCMs to save power TT Cancel Default Help Next check the settings for the Startup Options tab against those shown in the picture below Process Properties x General Options Configuration Options startup Uptions Readback Options Encryption Options re Ene liens Dae Cancel Default Help 53 Using Different Versions of ISE Next ch
45. lel On the HUNT ENGINEERING CD all FPGA examples are provided below the fpga directory The fpga directory is divided into sub directories that reflect the name of the module type In this document Example1 for the HERON FPGAbO is to be converted so the directory fpga fpgadv1 will contain the appropriate project information Identify the appropriate CD directory according to your module type With the correct CD directory located you will need to copy Example 1 to your local drive This can be done in one of two ways The first method is to copy the Example 1 project by hand for the module type you are using The second method is to unzip the ZIP file for that module type onto your hard drive When using the first approach you will need to copy the Common directory and Example directory from the CD to a chosen directory on your local drive The Examplel directory contains all design source that forms Examplel and the Common directory provides design source common to all designs made for that module Please note when copying files from your CD by hand you may need to edit the file attributes after copying This is because on some operating systems Read Only files on the CD will become Read Only files on your local drive All files in the Example directory should be set to Read Write while all files in the Common directory must remain Read Only When using the second approach you will be
46. lly be set correctly The picture below shows a new directory on the local drive named fpga In the fpga directory are the copied Common and Example directories inf ISE 39 Using Different Versions of ISE Step 2 Creating a New Project File With the Examplel example directory and Common directory copied onto your Local Drive you can now begin building an ISE 6 project Open the ISE 6 Project Navigator if it is not already open Please note in the remainder of this section an example conversion is shown for Example 1 for the HERON FPGA S where this conversion is performed in ISE 6 2 If you are using a different ISE 6 version then although the windows shown may not perfectly match the conversion process is still the same Next delete the project file for the Examplel project in the new directory you have created on your local drive The project file will be located in the ISE sub directory of the Examplel directory and will have the extension ise This existing project file must be removed as it will not be useable in ISE 6 and must be replaced with an appropriately constructed project file With the existing file deleted select the menu item File N ew Project to begin creating a new project The following window should be displayed New Project x Enter a Name and Location for the Project Project Name Project Locatior JE 1_Frgabv Je Mfpgav1 LE ample 415 E wae
47. nclude Directories O 2 2 2202020220220222 Custom Compile File List 2 2 2220220202022022 O OtheresST Command Line Options 2 20222 O Cancel Default Help z on 49 Using Different Versions of ISE Next bring the HDL Options tab to the front and check that the settings match those in the picture below Process Properties xj Synthesis Options HOL Options alins Specific Options Property Hame 5SM Encoding Algorithm ase Implementation Style SM Style AM Extraction Abl Style OM Extraction OM Style I z EKI 3 xE 3 ecoder Extraction nority Encoder Extraction hitt Register Extraction ogical Shifter Extraction OR Collapsing esource Sharing Multioher Style DHT DoS SDD ao 7 14 m ZS om ou i 2 lt lt iT T pi wi Next bring the Xilinx Specific Options tab to the front Change the Number of Clock Buffers item to 0 and set the Pack I O Registers into IO Bs item to No With this done check that the settings match those in the picture below Process Properties Synthesis Options HEL Options lins Specific Options nS mi s Optimize Instantiated Primitives I a 4 KIS Click on the OK button at the bottom of the window to apply the new settings 50 Using Different Versions of ISE Next the Translate Properties must be checked With the file top vhd still highlighted in the Module View ri
48. ocess properties For Examplel the Place amp Route Effort Level Overall typically needs to be set to Normal Make this change and check all other settings match the picture below and click OK Process Properties x Place amp Route Properties Propertyame ate Place amp Route Effort Level Overa Cc M Guide File Guide Mode Generate Detaied FAR Rep Mo Cancel Default Help Next check the Generate Programming File properties With the General O ptions tab at the front tick the Create ASCII Configuration File and then check that all other settings match for this tab TT x a Use Timing Constraints E Startup options Readback options Encryption options General Options Configuration options Oo Properyhame ate Cancel Default Help 34 Using Different Versions of ISE Bring the Configuration Options to the front Select Pull Up for the Unused IOB Pins item With this done check the settings match those shown in the picture below Process Properties xj Startup options Readback options Encryption options General Options Configuration options _PropertyName Ye O Conngwatone O ooo S p T ac Fin UME e Code 5 Digit Hexadecimal OxFFFFFFFF Reset DCM if SHUTDOWN amp AGHIGH performed O o i Disable Bandgap Generator for DLMs to save power DCI Update Mode Cancel Default Help Next check the settings for the
49. oject x Project Name Froject Location JE 1_Frgabv Je MpgaSv1 ExamplelsISE 7 Project Device Options PropertyName Wale Package O y peed Grade Design Flow mol VYHOL Cancel Help Enter the correct project name in the Project Name field For Example this should be set to be the same project name as the Example project file on the HUNT ENGINEERING CD minus the ise extension Next enter the correct location into the Project Location field This field should match the location of the Example1 ISE directory you have made on your local drive Then set the Project D evice O ptions to correctly reflect the appropriate device information according to the module type you are using If you are unsure of the correct information refer to the User Manual for that module type Ensure that the Design Flow is XST VHDL When you have correctly defined all fields click OK 25 Using Different Versions of ISE Step 3 Adding VHDL Source to the New Project The next step is to add design source starting with the top level of the hierarchy For all FPGA module projects the top level of the design is always contained in the file top vhd top vhd is always provided as part of the Common directory for each module type Select the menu item Project gt Add Source The following window will be displayed where you will need to navigate to the Common directory that
50. ok in EISE amp ce EE fifol 5x32 xc0 File name E 1 FogaSy uct Cancel Files of type Sources tet vad sco sch tby bmm Ze Select the UCF file and click Open The following window will appear to allow you to specify the design file to which the user constraints should be associated Highlight top and click OK Associate with Source e ail iaieiaiaas affects a Cancel Help 14 Using Different Versions of ISE Step 5 Adding a Simulation Test Bench Typically a project will also include a test bench for simulation For Examplel there is a test bench provided in the Src directory of the project This file must also be added to the project using Project gt Add Source Navigate to the Src directory highlight the file that beings TB and click Open Add Existing Sources 8 8 ax Look ir E SIC do t be File name TB_EX1 wha Files of type Cancel Sources tek vad vhdlv abl sco ac T Ze The following window will appear where you need to specify the source type Select VHDL Test Bench and click OK x TB ES vhd te which source type The suffis ig ambiguous as to type YHEL Module VHOL Package VHDL Test Bench 15 Using Different Versions of ISE At this point the Module View should look similar to the picture shown below for the FPG Ab5v1 conversion proces
51. ommon directory for each module type Select the menu item Project gt Add Source The following window will be displayed where you will need to navigate to the Common directory that was created on your local drive Select the file top vhd and click O pen Add Existing Sources x E Fpga5v_tpl ucf 5l SIM_M5G vhd i USER_AP_TPL vhd El HE_CONY vhd H SIM_RD_6F vhd 5 v2 _RO_6F vhd HE _RWCLK vhd B SIM_ SDRAM vhd i HE_SDRAM vhd El SIM_WR_6F vhd ey HE_UISER vhd El SYN y _RD_6F vhd File name TOP vhd Files of type Sources tet vad vad iv abl sco sc T Cancel Ze The following window will then appear Select VHDL Design File and click OK to add top vhd to the project Choose Source Type x TOP vhd t which source type The suffis i ambiguous as to type VHDL Test Bench File Cancel Help 43 Using Different Versions of ISE With this done the Module View window will now look similar to the picture below depending on the particular source files that are required by the module type you are using Sources in Projac pee fE Ex Fogaby ae 1 ace 00i oa In the case of the FPGAdv1 example conversion after adding top vhd we can now see 6 more design entities are needed One of these entities is the User Application level of the design which contains the VHDL that makes this example the getting started example Examplel The othe
52. open the following window Tick the item Allow Unmatched LOC Constraints check all other settings match and click OK Process Properties i xX Translate Properties Property Name Use LOC Constraints Netlist Translation Type Macro Search Path Create I O Pads from Parts User Rules File for Netlister Launcher oo Allow Unmatched LOC Constraints M o S Other Ngdbuild Command Line Options l o S Property display level Advanced Cancel Default Help Next open the Process Properties window for the Map process Check that the settings match those in the picture below Process Properties l x Map Properties Perform Timing Driven Packing and Placement TO Map to lnput Functions OOS E MAP Guide Design File ned OOOO o O Disable Register Ordering OO o CLB Pack Factor Percentage 100 Map Slice Logic into Unused Block RAMs Other Map Command Line Options Property display level Advanced Cancel Default Help 70 Using Different Versions of ISE Next check the Place and Route process properties For Examplel the Place amp Route Effort Level O verall typically needs to be set to Medium Make this change and check all other settings match the picture below and click OK Process Properties x Place amp Route Properties Place amp Route Effort Level Overal MERIT C PAR Guide Design File Laed OOOO o Other Place amp Route Command Line Options
53. ormed O o i Disable Bandgap Generator for DLMs to save power DCI Update Mode Cancel Default Help Next check the settings for the Startup Options tab against those shown in the picture below Process Properties x General Options Configuration options startup options Readback options Encryption options Property Name Value Enable termlDone PbS Release DLL Output Events Detauk Mov vat Match Cycle Default Mov vat Drive Done Fin High Cancel Default Help 20 Using Different Versions of ISE Next check the Readback O ptions against the picture below Process Properties x General Options Configuration options Startup options Readback options Encryption options Create ReadBack Data Files E Allow SelectMAP Pins to Persist Create Logic Allocation File Create Mask Fil Cancel Default Help Finally check the Encryption O ptions tab against the picture shown below Process Properties x General Options Configuration options Startup options Readback options Encryption options Oo Properyhame ale Erorien SSS KeyO HexSting O ketes O S Keates O o Keates OO o kestesi O o keS esin OOO o metEncrytionkeyPe OO o Stang cec vae SSC S O Cancel Default Help When all tabs have been checked click OK to enter the new settings 21 Using Different Versions of ISE Step 7 Building the Project At this point the project is r
54. ou will see which other source files are required below this entity Add the appropriate source files from the Src directory After you have added all of required VHDL source files from the Src directory there may still be red question marks against entities in the hierarchy These entities will correspond to Core Gen components that are placed in the Examplel ISE directory In the case of Examplel there is one Core Gen component called fifo15x32 that must be added to the project from the ISE directory 63 Using Different Versions of ISE With all relevant VHDL source added to the project the Module View should look similar to the picture shown below for the FPGA 5v1 conversion Sources in Project poe ia Ex Fogaby ise E Ed scev 1000 ffg456 soon ii sy a Gf rtl W Comman 2 AD 6F vhd AA he_ravelk rtl 5 Commons HE_AW CLE vhd AA he_sdram rtl 4 CommonSHE_SORAM whd Fa AA he_ec_entrrtl 5 Commons HE_SDRAM vhd AA he_userrtl 5 Commons HE_USER vhd ve A he vr Berth 4 Commons HE wA BF vhd Ee a a ati Srce ser pi whd vee ffol Ses fifo Ses eco TA habl rtl 45rc HSB 1 vk Be Module view t Snapshot View Ir Library yew 64 Using Different Versions of ISE Step 4 Adding User Constraints The next step is to add user design constraints to the project Using Project Add Source add the user constraints file contained in the I
55. pply to all hd files 66 Using Different Versions of ISE At this point the Module View should look similar to the picture shown below for the FPG A5v1 conversion process Sources in Project poe A Es1_Fpgabv ise E scgv 1000 ffg456 fe testbench Cerne SrchTE _EAT hd U Ex1_Fpga5v uct vee a he_rd_Bf rtl 4 SCormmnonky AD BF yh s DA he_nwelk ttl 4 Conmon HE_Aw CLK vhd El A he sdram Common HE_SDRAM vid A a he_sd_cntr rtl 5 WCormornsSHE SORAM Yhd vee A he_user rtl 4 Common HE_USER vhd sees a he_wr_Bf rtl Commons HE w ABF Yhd M User ap examplel 5re4U ser Api vhd e n C ffol Ses ffo Geese uca bese soo WA heb rtl Wore5HSB1 vhd Be Module view t Srapshot View Ir Library Wiew 67 Using Different Versions of ISE Step 6 Setting Project Build Options The last step in creating a new project is to apply the necessary project settings that will allow the design to be built correctly Ensure the file top vhd is highlighted in the Module View and then right click on Synthesize in the Process View Select Properties to open the following window With the Synthesis Options tab at the front set Optimization Effort to High and set Hierarchy Separator to Having done this check that the settings match those shown below Process Properties Synthesis Options HDL Options Xilinx Specific Options Optimization
56. r entities shown are part of the Hardware Interface Layer and are found in the Common directory First add the appropriate files from the Common directory in order to replace the red question mark icons with correct entities To do this you will again need to use the Add Source menu item Navigate to the Common directory and select the files that have names that match the entities in the Module View of your new project Please note the HE RD OF entity is provided in the Common directory in the source file V2 RD 6P When adding each file the correct Source Type will be VHDL Design File as was selected when adding top vhd When you have added all required Hardware Interface Layer components the Module View should look similar to the picture below for the FPG Aobv1 conversion Sources in Project A Es1_Fpga5v E bd xce 1000 ale a he dram a 5 CommontHE SDRAM whd a he_sd_cntr rtl 4 CommonSHE SORAM hd basen WA he_user rtl Common HE_USER hd Basen WA he wr _Bf rtl 4 Commons HE w A_EF hd m U er_a p EF hiodule view t Snapshot wien F Library Wien 44 Using Different Versions of ISE Next you will need to navigate to the Src directory of Examplel and add the User Ap file to the project Look in Sy Sre ct EJ File name u ser Apl vhd Cancel AE Files of type Sources tat vads vhdl v abl sco ec T
57. rces can be added after project creation using the Proyect gt New Source command Cancel Help 41 Using Different Versions of ISE The following window will then be displayed Again click Next gt ke i x Add Existing Sources Source File Type Copy to Projec 2E ia Add Source Remove Add existing sources to the project optional Additional sources can be added after project creation Using the Project 4dd Source or Proyect 4dd Copy of Source commands Cancel Help Finally the following window is displayed providing a summary of all the project information you have entered Click Finish to make the new project file New Project Information x Project Navigator will create a new Project with the following specifications Project Name Ext Fogaby Project Location c fogaSy7 SE sample wISE Project Type HDL Device Device Family Yirtex2 Device acev 1000 Package fg456 Speed Grade 4 Top Level Module Type HOL Synthesis Took 5T MHOL verlag Simulator Other Generated Simulation Language HDL lt Back Cancel Help 42 Using Different Versions of ISE Step 3 Adding VHDL Source to the New Project The next step is to add design source starting with the top level of the hierarchy For all FPGA module projects the top level of the design is always contained in the file top vhd top vhd is always provided as part of the C
58. roject Navigator The existing project will automatically be archived and stored at D FogaSv1 ExamplelISE Ex1 FogaSy_ise bak zip in the event you later decide to return bo the older version Please note that starting in 1i the new extension For the project File willbe vise This project will be converted to Ex1 FogaSy ise Do you want bo update the project This window indicates that the project needs updating Also note that the project file extension changes from npl to ise with version 7 Click Yes to continue You will now be able to continue development on the converted project in ISE 7 1 7 Using Different Versions of ISE Creating Projects for ISE 4 For each FPGA module type each project contained on the CD provides all of the required design elements to ensure correct operation on that chosen module type These elements include a Hardware Interface Layer that is used to correctly control external devices user constraints information to control design timing and pin location and example VHDL to provide a structured starting point For users of ISE 4 design tools this document must be followed in order to convert the newer project format used on the HUNT ENGINEERING CD to the correct ISE 4 format This section describes how to build an ISE 4 project from scratch using the design source provided on the CD This process is necessary as the standard XILINX tool version has moved on from ISE 4 and XILI
59. s Sources in Froject bon a Ext _Fpuaby sick WP held BFS ACommonk2 AO_EF whd WV herck 5 CommonsHE_ARW CLK hd WP he_sdram 4 CommonkHE SDRAM vhd ha i he_ed_entr 4 CommonsHE_SDRAM vid iV he_user 5 Commons HE _USER vhd vee i he wr Ef 4 CommonsHE_WR_BF vhd a m user_ap L SrcAUser Api vhd RE fitol 532 fifo ese eco as e WY heb 45rcAHSE1 vhd EF Module views ra Snapshot vien M Library wiew Step 6 Setting Project Build Options The last step in creating a new project is to apply the necessary project settings that will allow the design to be built correctly Ensure the file top vhd is highlighted in the Module View and then right click on Synthesize in the Process View Select Properties to open the following window With the Synthesis O ptions tab at the front check that the settings match those shown below Process Properties L x Synthesis Options HDL Options Xilinx Specific Options PropertyHame Value c Synthesis Constrarts Fe oo Hererchy sepert I C Cancel Default Help 16 Using Different Versions of ISE Next bring the HDL Options tab to the front and check that the settings match those in the picture below Process Properties xj Synthesis Options HOL Options Alling Speciic Options Cancel Default Help Next bring the Xilinx Specific Options tab to th
60. s with correct entities To do this you will again need to use the Add Source menu item Navigate to the Common directory and select the files that have names that match the entities in the Module View of your new project Please note the HE RD OF entity is provided in the Common directory in the source file V2 RD OF When adding each file the correct Source Type will be VHDL Module as was selected when adding top vhd When you have added all required Hardware Interface Layer components the Module View should look similar to the picture below for the FPG Adv1 conversion Sources in Project mon A Ex1_Foogahv os a acy 1000 oe he dram alt 5 Commons HE SDRAM vhid ke a he_sd_cntr rtl 04 SCommonSHE_ SORAM hd Bese ay he_user rtl Common HE_USER vhd Heee H he wr _Bf rtl 4 Commons HE w A_EF hd m User ap EF hlodule view t snapshot wien M Library Wien 27 Using Different Versions of ISE Next you will need to navigate to the Src directory of Examplel and add the User Ap file to the project Look in Sy Sre ct EJ File name u ser Apl vhd Cancel AE Files of type Sources tat vads vhdl v abl sco ec T After the user ap entity has been added to the project you will see which other source files are required below this entity Add the appropriate source files from the Src directory After you have added all
61. should now build as far as bitstream generation without error Although each example project supplied on the HUNT ENGINEERING CD will differ from Examplel the process to create a new project for ISE 5 is the same The routine described in this section can therefore be repeated for each of the standard examples provided on the CD 37 Using Different Versions of ISE Creating Projects for ISE 6 For each FPGA module type each project contained on the CD provides all of the required design elements to ensure correct operation on that chosen module type These elements include a Hardware Interface Layer that is used to correctly control external devices user constraints information to control design timing and pin location and example VHDL to provide a structured starting point For users of ISE 6 design tools this document must be followed in order to convert the newer project format used on the HUNT ENGINEERING CD to the correct ISE 6 format This section describes how to build an ISE 6 project from scratch using the design source provided on the CD This process is necessary as the standard XILINX tool version has moved on from ISE 6 and XILINX provide no mechanism for converting post ISE 6 projects back to ISE 6 This document uses Examplel as the starting point for the creation of a new project It is important to start from one of the standard examples provided on the HUNT ENGINEERING CD as this give the correct starting point for FPGA dev
62. urce Type VHOL Test Bench File Cancel Help Apply to all hd files 61 Using Different Versions of ISE With this done the Module View window may look something like the picture below Sources in Project oe ia Es FogaSy ise E 1 acey 1000 bai ie cn BI he Ei see F he_rwek ee he_sdrari z he_user fen he w _Ef a user ap In this picture we can see that the path shown for top vhd is absolute That is it shows the complete path The project needs to be changed to use relative path information To do this left click on the entity top With top selected right click to bring up a menu and select Toggle Paths The Module View should now look similar to the picture below depending on the particular source files that are required by the module type you are using Note the path information has now changed to reflect a relative path to the Common directory Sources in Project oe ia Ex FogaSy ise E Ed cw 1000 a a ag a Cr ve F herck 2 he_sdram he_user vee he_ wr Bt ne uger ap In the case of the FPGA5v1 example conversion after adding top vhd we can now see 6 more design entities are needed One of these entities is the User Application level of the design which contains the VHDL that makes this example the getting started example Examplel The other entities shown are part of the Hardware Interface Layer and are found in the Common directory
63. ve been checked Example1 should now build as far as bitstream generation without error Although each example project supplied on the HUNT ENGINEERING CD will differ from Examplel the process to create a new project for ISE 7 is the same The routine described in this section can therefore be repeated for each of the standard examples provided on the CD 74 Using Different Versions of ISE
64. was created on your local drive Select the file top vhd and click O pen E Fpga5v_tpl ucf 5l SIM_M5G vhd USER_4P_TPL vhd HE_CONY vhd El SIM_RD_6F vhd v2 _RD_6F vhd HE _RWCLK vhd B SIM_ SDRAM vhd Ea HE_SDRAM vhd SIM_WR_6F vhd HE_UISER vhd El SYN y _RD_6F vhd File name TOP vhd Files of type Sources tet vAd vad iv abl xcosc Cancel Ze The following window will then appear Select VHDL Module and click OK to add top vhd to the project Choose Source Type I x TOP vhd t which source type The suffis ig ambiguous as to type VHDL Package VHDL Test Bench Cancel Help 26 Using Different Versions of ISE With this done the Module View window will now look similar to the picture below depending on the particular source files that are required by the module type you are using Sources in Projac pee fE Ex Fogaby ae 1 caw 1000 ika In the case of the FPG A5v1 example conversion after adding top vhd we can now see 6 more design entities are needed One of these entities is the User A pplication level of the design which contains the VHDL that makes this example the getting started example Example1 The other entities shown are part of the Hardware Interface Layer and are found in the Common directory First add the appropriate files from the Common directory in order to replace the red question mark icon
65. you will need to work through the section Upgrading Existing Projects to ISE 7 1 Continuing to Use a Previous Version of ISE The latest version of ISE and HUNT ENGINEERING CD examples is version 7 1 If you are continuing to use a version of ISE earlier than ISE 7 and have an existing project then you may continue development without needing to work through the remainder of this document If however you wish to work with any of the new example projects on the current HUNT ENGINEERING CD you will need to work through one of the following sections depending on your current tool version The section that applies will be one of the following Creating Projects in ISE 4 Creating Projects in ISE 5 Creating Projects in ISE 6 or Creating Projects in ISE 7 Creating New Projects To create a brand new FPGA project in ISE you will need to work through the appropriate section from either Creating Projects in ISE 4 Creating Projects in ISE 5 Creating Projects in ISE 6 or Creating Projects in ISE 7 depending on the version of ISE you are using You will also need to refer to the Making your own FPGA design section of the User Manual for the FPGA module you are using for module specific information 6 Using Different Versions of ISE Upgrading Existing Projects to ISE 7 1 This section describes how to upgrade an existing FPGA module project to work with the latest version of ISE version 7

Using Different Versions of ISE

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