DNR-AI-208 Product Manual - United Electronic Industries
Contents
1. Tel 508 921 4600 www ueidaq com Vers 4 6 Date November 2013 File AI208 Chap2 fm 7 DNx Al 208 Analog Input Layer Chapter 2 Programming with the High Level API Configure channels 0 1 to use a gain of 100 in differential mode program the excitation to 10V and turn on scaling with excitation session CreateAIExChannel pdna 192 168 100 2 Dev0 Ai0 1 0 1 0 1 UeiSensorFullBridge 10 0 true UeiAIChannelInputModeDifferential 2 3 Configuring the Timing 2 4 Reading Data You can configure the Al 208 to run in simple mode point by point or buffered mode ACB mode In simple mode the delay between samples is determined by software on the host computer In buffered mode the delay between samples is determined by the Al 208 on board clock The following sample shows how to configure the simple mode Please refer to the UeiDaq Framework User s Manual to learn how to use the other timing modes session ConfigureTimingForSimpleIO Reading data from the Al 208 is done using a reader object There is a reader object to read raw data coming straight from the A D converter There is also a reader object to read data already scaled to volts or mV V The following sample code shows how to create a scaled reader object and read samples Create a reader and link it to the session s stream CUeiAnalogScaledReader reader session GetDataStream read one scan the buffer must be big enough to2. 0 0 rn 7 2 2 Configuring Channels and Excitation 00 00 cece eee 7 2 3 Configuring the Timing 0000 c eee RH Ie 8 2 4 Reading Data wie is eee RR bee Rte eg Ee E ue pee eed beens 8 2 5 Cleaning up the Session 00 00 cts 8 Chapter 3 Programming with the Low Level API eseeseesee 9 3 1 Configuration Settings lille 9 3 2 Channel List Settings llllilsieseleeeseele eee 10 3 3 Layer specific Commands and Parameters 0 0 cc cece eee eee 11 3 4 Using Layer in ACB Mode 0 00 cece teens 14 3 5 Using Layer in DMap mode 000 eee tenes 16 Appendix A Accessories 00 c cece eee eee eee nn n n n n nnn 18 A 1 DNA STP AI 208 Screw Terminal Panel 00 000 elles 18 A 2 Other Accessories 24 A 3 Layer Calibration sess sasae na ianea seed exa ke py Rer eR ep ied aa aa dads 24 Appendix B Shunt Calibration 00 00 ee 25 B 1 IMTOGUCTION sas iecee EL 25 B 2 THEO 244 tate nie den dti eb koala dda ead bees Ve bd s 25 B 3 Using Shunt Resistors on the AI 208 0 00 eee 28 B 4 Configuring Framework for Shunt Calibration 0000 cee eee eee 29 B 5 Shunt Calibration in C 0 0 0 0 isses 30 B 6 Shunt Calibration in LabVIEW ssssesesee lh 31 MAER eR 33 Zs terete bam TRUM Tel 508 921 4600 WwWwW Uueidaq com Vers 1 8 wy l Date August 2009 Al 208TOC fm Table of Contents List of Figures
3. Chapter 1 Introduction 2 0 0 e eee eee nnn 1 1 1 Photos of DNR and DNA AI 208 Boards sese 4 1 2 Block Diagram of DNx AI 208 Device Architecture eene 4 1 3 DB 37 I O Connector Pinout ssssssssssesseseeeeee eene nnne nre nennen nens 5 1 4 Recommended Ground Connections for Analog Inputs esssssssss 6 Chapter 2 Programming with the High Level API 0 0000 lesen 7 None Chapter 3 Programming with the Low Level API sllseeseeeeeeeeee 9 None Appendix A Accessories 0 000 cece eee nn n n n n nnn 18 A 1 Photo of DNA STP AI 208 Screw Terminal Panel sse 18 A 2 Pinout Diagram for the DNA STP AI 208 sssssssssssseeeeerennene nennen 20 A 3 Single Channel Wiring Diagram Full Bridge ssseeeee 20 A 4 Single Channel Wiring Diagram Half Bridge sse 21 A 5 Single Channel Wiring Diagram Quarter Bridge sssssssee 22 A 6 Physical Layout of STP AI 208 Board sss 23 Appendix B Shunt Calibration sllseeeeeeeeeeee nnn 25 B 1 Strain Gauge Bridge e bx Pee aa a a a EEEE 25 B 2 Strain Gauge with Shunt Resistance Rs Added ssssssssssss 26 B 3 Using Shunt Resistors on the DNA AI 208 Layer ssssseeee 28 Zs Copyright 2009 Tel 508 921 4600 www
4. 1 FALSE STEP 6 Clean up DqAcbDestroy bcb DqStopDQEngine pDqe DqCloseIOM hd0 ifndef WIN32 DqCleanUpDAQLib endif 3 5 Using Layer include PDNA h in DMap mode STEP 1 Start DQE engine ifndef WIN32 DqInitDAQLib endif Start engine DqStartDQEngine 1000 10 amp pDqe NULL open communication with IOM hd0 DqOpenlOM IOM IPADDRO DQ UDP DAQ PORT TIMEOUT DELAY amp DQRdCfg Receive IOM crucial identification data DqCmdEcho hd0 DQRdCfg Copyright 2009 Tel 508 921 4600 www ueidaq com Vers 4 6 emendis Date November 2013 File AI208 Chap3 fm DNx Al 208 Analog Input Layer Chapter 3 15 Programming with the Low Level API for i 0 i DQ MAXDEVN i if DQRdCfg devmod il printf Model x Option x n DQRdCfg gt devmod il DQRdCfg option il eise break STEP 2 Create and initialize host and IOM sides DgDmapCreate pDqe hd0 amp pBcb UPDATE PERIOD amp dmapin amp dmapout STEP 3 Add channels into DMap for i 0 i lt CHANNELS i DqDmapSetEntry pBcb DEVN DQ SSOIN i DQ ACB DATA RAW 1 amp ioffset il DqDmapInitOps pBcb DqeSetEvent pBcb DQ eDataAvailable DQ ePacketLost DO eBufferError DQ ePacketOOB STEP 4 Start operation DqeEnable TRUE amp pBcb 1 FALSE STEP 5 Process data while keep looping DqeWaitForEvent amp pBcb 1 FALSE timeout amp eventsin if eventsin amp
5. Quarter Bridge The Bridge Completion Resistors in the table are shown in the bridge circuit wir ing diagrams illustrated in Figure A 4 and Figure A 5 SENECA e o Nero m LLLLLLLLLLLLLZLZLMILIMMSsssus Copyright 2009 Tel 508 921 4600 www ueidag com Vers 4 6 eee ee sere Date November 2013 File Al 208 App A fm DNx Al 208 Analog Input Layer The Pinout for the DNA STP AI 208 DB 37connector is as follows DB 37 male 37 pin connector S7 20 P7 21 AGND 22 S6 23 PS6 24 S5 25 DIOO EXT_TRIG S7 PS7 S6 P6 S5 p54 AGND S4 S3 29 10 PS4 P3 30 11 S3 AGND 31 12 PS3 S2 32 52 Ps2 33 14 P2 S1 34 15 S1 PS1 35 16 Pi S0 36 17 AGND Po 37 18 S0 19 PSO S4 27 WOON OU B W 20 37 Figure A 2 Pinout Diagram for the DNA STP AI 208 Figure A 3 shows a typical Single Channel Wiring diagram for a Full bridge Strain Gauge connected to the STP AI 208 panel As the figure indicates you should remove the board mounted jumper when you use a 6 wire Circuit Insert jumper when using a 4 wire connection Remove when using a 6 wire connection to DB 37 Connector Figure A 3 Single Channel Wiring Diagram Full Bridge Copyright 2009 Tel 508 921 4600 www ueidaq com Vers 4 6 illae p
6. United Electronic Industries The High Performance Alternative DNA DNR AI 208 Strain Gauge Analog I nput Layer User Manual 18 bit 8 channel 4 and 6 wire Strain Gauge Differential I nput Layers for the PowerDNA Cube and RACKtangle chassis November 2013 Version 4 6 PN Man DNx Al 208 1113 Copyright 1998 2010 United Electronic I ndustries I nc All rights reserved No part of this publication may be reproduced stored in a retrieval system or transmitted in any form by any means electronic mechanical by photocopying recording or otherwise without prior written permission Information furnished in this manual is believed to be accurate and reliable However no responsibility is assumed for its use or for any infringements of patents or other rights of third parties that may result from its use All product names listed are trademarks or trade names of their respective companies See UEI s website for complete terms and conditions of sale http www ueidaq com company terms aspx Contacting United Electronic Industries Mailing Address 27 Renmar Avenue Walpole MA 02081 U S A For a list of our distributors and partners in the US and around the world please see http www ueidaq com partners Support Telephone 508 921 4600 Fax 508 668 2350 Also see the FAQs and online Live Help feature on our web site Internet Support Support support ueidag com Web Site www ueidaq com FTP Si
7. amp bcb Let s assume that we are dealing with AI 208 device dquser initialize acb structure Now call the function DgAcbInitOps bcb amp Config 0 TrigSize NULL pDQSETTRIG TrigMode amp fCLClk 0 float fCVClk amp CLSize CL 0 uint32 ScanBlock amp acb printf Actual clock rate f n fCLCIlk Now set up events DgeSetEvent bcb DQ eFrameDone DQ ePacketLost DQ eBufferError DQ ePacketOOB STEP 3 Start operation Start operations DqeEnable TRUE amp bcb 1 FALSE STEP 4 Process data We will not use event notification at first just retrieve scans while keep looping DqeWaitForEvent amp bcb 1 FALSE EVENT TIMEOUT amp events if events amp DQ eFrameDone minrq acb framesize Copyright 2009 Tel 508 921 4600 www ueidag com Vers 4 6 Bi aia ela ila Date November 2013 File Al208 Chap3 fm DNx Al 208 Analog Input Layer Chapter 3 14 Programming with the Low Level API avail minrg while TRUE DqAcbGetScansCopy bcb data acb framesize acb framesize amp size amp avail samples size CHANNELS for i 0 i lt size CHANNELS i fprintf fo sf t float data i if i CHANNELS CHANNELS 1 fprintf fo n printf eFD d scans received d samples min d avail d n size samples minrq avail if avail lt minrq break STEP 5 Stop operation DgeEnable FALSE amp bcb
8. ers and switches is not negligible and needs to be measured and added to the global shunt resistance e Semiconductors involved in the shunt calibration circuitry have signifi cant changes in resistance with temperature change To overcome those problems UEI included 25 ppm C 5kOhm 0 1 resistors into shunt calibration circuitry When PS is connected to S on the screw termi nal panel internal circuitry makes it possible to measure voltage drop on one of those precision 25 ppm C resistors thus precisely measuring current through them By knowing current and voltage drop in the shunt calibration circuitry you can calculate total resistance of the switches resistors and multiplexers which is equal to the shunt resistance Due to the additional resistance in the shunt calibration circuitry and the 30 accuracy of 200kOhm digital potentiometer the shunt calibration resistance can be between 10k and 170k Ohms Copyright 2009 Tel 508 921 4600 www ueidaq com Vers 4 6 oe ends Date November 2013 File AI 208 App B fm B 4 Configuring Framework for Shunt Calibration Copyright 2009 United Electronic Industries Inc DNx Al 208 Analog Input Layer The Shunt Calibration method of calibration and reading uses a 4 wire sensor configuration When you use this method you should permanently connect the PS pin to the S pin and remove the jumper and other 6 wire connections to the PS pin The only connection to PS sho
9. sensor excitation is usually not required Precise measurement is achieved through the use of more than 8 channels internally in the Al 208 board NOTE For descriptions of connections used with quarter half and full bridge circuits refer to Figure A 3 Figure A 4 and Figure A 5 in the Appendix 1 4 4 Connectors The pinout of the 37 pin connector for the DNA DNR AI 208 Layer board is shown in Figure 1 3 A physical layout of the board is shown in Figure 1 3 PO 37 19 PSO AGND 22 4 S6 External Trigger P7 21 3 PS7 Input only s7 20 2 57 4 EXT_TRIG Figure 1 3 DB 37 I O Connector Pinout When using a long cable to a sensor be sure to use the same gauge wire for the excitation source GND and GND Sense lines Copyright 2009 Tel 508 921 4600 www ueidaq com Vers 4 6 United Electronie Ingustries Ine Date November 2013 File AI208 Chap1 fm DNx Al 208 Analog Input Layer Chapter 1 6 Introduction 1 4 2 Analog Input To avoid errors caused by common mode voltages on analog inputs follow the Ground recommended grounding guidelines in Figure 1 4 below Connections Type of Input Floating Grounded Input Typical Signal Sources Typical Signal Sources Configuration Thermocouples Instruments or sensors DC Voltage Sources with non isolated outputs Instruments or sensors with isolated outputs DNA STP 37 STP AI DNA STP AI U ee Differential T
10. DQ eDataAvailable datarcv printf ndata for i 0 i lt CHANNELS i printf s04x uint32 ioffset il STEP 6 Stop operation DgeEnable FALSE amp pBcb 1 FALSE STEP 7 Clean up DqDmapDestroy pBcb DqStopDQEngine pDqe DqCloseIOM hd0 ifndef WIN32 DqCleanUpDAQLib endif Copyright 2009 Tel 508 921 4600 www ueidag com Vers 4 6 Eee Date November 2013 File AI208 Chap3 fm DNx Al 208 Analog Input Layer Chapter 3 16 Programming with the Low Level API BHEHGEEENEEESCESCECXNCSG MN R Mo C 3 9 4 0 4 4 A Rt n XXX Copyright 2009 Tel 508 921 4600 www ueidaq com Vers 4 6 United Electronic Industries Inc Date November 2013 File AI208 Chap3 fm e a wro u DNx Al 208 Analog Input Layer Appendix A Accessories A 1 DNA STP Al The DNA STP AI 208 Screw Terminal Panel is an easy to use versatile acces 208 Screw sory for direct connection of strain gauge and other bridge type sensors to the Terminal DNA AI 208 Strain Gauge Analog Input Layer board It can accept signals from Panel 8 strain gauge type sensor channels in several types of bridge configurations full bridge 4 and 6 wire circuits half bridge 3 and 4 wire circuits and quar ter bridge 2 and 3 wire circuits configurations Note that quarter and half bridge configurations require user populated br
11. IOCTL208 READ PP measure P to AGND DQL IOCTL208 READ PS measure PS to AGND Copyright 2009 Tel 508 921 4600 www ueidaq com Vers 4 6 Unies c eatromte fndustries ne Date November 2013 File AI208 Chap3 fm DNx Al 208 Analog Input Layer Chapter 3 Programming with the Low Level API Because the resistance can differ from channel to channel current is flowing through different channels of the same multiplexer which can have different resistances you should set up the channel number to be used This function returns the number of samples requested for averaging Data is returned in raw format DgAdv208MeasureParams This function is used to measure a variety of Al 208 front end parameters see channel equivalent diagram VrefReference voltage Volts VexcExcitation voltage Volts VsVmeas for Rs Volts RsSwitch resistance Ohms VxVmeas for Rx Volts RxMux resistance Ohms VaVmeas for Ra Volts RaResistance of shunt resistor Ra plus 5k constant Ohms VbVmeas for Rb Volts RbResistance of shunt resistor Rb plus 5k constant Ohms Before the function can measure these parameters specify the measurement conditions ChannelChannel being used for measurements ExcAExcitation level A even channels 16 bit ExcBExcitation level B odd channels 16 bit RaShunt A level 8 bit 256 positions from 0 to 200k RbShunt B level 8 bit 256 positions from 0 to 200k The AI 208 layer has a 14 bit excitation DAC and an 8 bi
12. contain one value per channel double data 2 reader ReadSingleScan data 2 5 Cleaning up the Session The session object will clean itself up when it goes out of scope or when it is destroyed However you can also clean up the session manually to reuse the object with a different set of channels or parameters session CleanUp Copyright 2009 United Electronic Industries Inc Tel 508 921 4600 www ueidaq com Vers 4 6 Date November 2013 File AI208 Chap2 fm 8 DNx Al 208 Analog Input Layer Chapter 3 9 Programming with the Low Level API Chapter 3 Programming with the Low Level API This section describes how to program the PowerDNA cube using the Low level API The low level API offers direct access to PowerDNA DAQBios protocol and also allows you to access device registers directly We recommend that when possible you use the UeiDaq Framework High Level API see Chapter 2 because it is easier to use You should need to use the low level API only if you are using an operating sys tem other than Windows 3 1 Configuration Configuration settings are passed through the DqcmdSetCfg and DgAc Settings bInitOps functions Not all configuration bits apply to the Al 208 layer The following bits are used define DQ LN IRQEN 1L 10 enable layer irqs define DQ LN PTRIGEDGE1 1L 9 stop trigger edge MSB define DQ LN PTRIGEDGEO 1L 8 stop trigger edge 00 software 01
13. follows CUeiSession session 2 2 Configuring Channels and Excitation Framework uses resource strings to select each device subsystem and chan nels to use within a session The resource string syntax is similar to a web URL device class gt lt IP address gt lt Device Id Subsystem Channel list pdna 192 168 For PowerDNA the device class is pdna For example the following resource string selects analog input channels 0 2 3 4 on device 1 at IP address 192 168 100 2 100 2 Dev1 Ai0 2 3 4 The gain to be applied on each channel is specified with low and high input limits For example the Al 208 available gains are 1 2 4 8 10 20 40 80 100 200 400 800 and the maximum input range is 10V 10V To select a gain of 100 you must specify input limits of 0 1V 0 1 V Configure channels 0 1 to use a gain of 100 in differential mode session CreateAIChannel pdna 192 168 100 2 Dev0 Ai0 1 0 1 0 1 UeiAIChannelInputModeDifferential Copyright 2009 United Electronic Industries Inc To program the excitation circuitry you need to configure the channel list using the session object method CreateAIVExChannel instead of Cre ateAIChannel This method also gives you the ability to select the bridge configuration you want and to select whether or not you wish to obtain the acquired data already scaled in mV V acquired voltage divided by actual excitation voltage as follows
14. rising 02 falling define DQ LN STRIGEDGE1 1L 7 start trigger edge MSB define DQ LN STRIGEDGEO 1L 6 start trigger edge 00 software 01 rising 02 falling define DQ LN CLCKSRC1 1L 3 CL clock source MSB define DQ LN CLCKSRCO 1L 2 CL clock source 01 SW 10 HW 11 EXT define DQ LN ACTIVE 1L 1 STS LED status define DQ LN ENABLED 1L 0 enable operations For streaming operations with hardware clocking the user has to select the fol lowing flags DQ LN ENABLE DO LN CLCKSRCO DO LN STREAMING DQ LN IRQEN DQ LN ACTIVE DQ LN ENABLE enables all layer operations DQ LN CLCKSRCO selects the internal channel list clock CL source as a time base The AI 208 layer supports the CL clock only where the time between con secutive channel readings is calculated by the rule of maximizing setup time per channel If you d like to select the CL clock from an external clock source such as the SYNCx line set DQ LN CLCKSRC 1 as well Aggregate rate Per channel rate Number of channels Copyright 2009 Tel 508 921 4600 www ueidaq com Vers 4 6 United lecum Date November 2013 File AI208 Chap3 fm DNx Al 208 Analog Input Layer Chapter 3 10 Programming with the Low Level API 3 2 Channel List The Al 208 layer has a very simple channel list structure as shown below Settings Bit Name P
15. ueidaq com Vers 1 9 b d United Electronic Industries Inc Date November 2010 AI 208LOF fm DNx Al 208 Analog Input Layer Chapter 1 Introduction Chapter 1 Introduction This document outlines the feature set and use of the DNA DNR AI 208 strain gauge analog input layer s The DNA version is used with the PowerDNA Core Module the DNR with the rack mounted UeiDaq RACKtangle chassis This man ual describes the following products DNA DNR AI 208 18 bit 8 channel differential input analog input strain gauge layer board s DNA STP AI 208 Screw Terminal Panel Accessory Board designed as a convenient interface for connecting full half and quarter bridge strain gauge type sensors to the DNA DNR AI 208 board Accessory modules such as cables The DNR version is identical to the DNA version except that the DNR version is designed to plug into a RACKtangle backplane instead of a Cube 1 14 Organization This DNA DNR AI 208 User Manual is organized as follows NOTE Copyright 2009 Tel Introduction This chapter provides an overview of DNA DNR AI 208 board layer fea tures accessories and what you need to get started DNx Al 208 Layer This chapter provides an overview of the device architecture connec tivity logic and accessories for the DNA DNR AI 208 layer board Programming with High Level API This chapter provides a general overview of procedures that show how to create a session configure the session and g
16. Cable s 24 Calibration 24 Channel List Structure 10 Connector DB 37 5 Connectors 5 D DNA CBL 37 24 DNA CBL 37S 24 DNA STP 37 24 F Flat Ribbon Cable 18 Full bridge Strain Gauge 20 G Gain s 10 Ground Connections 6 H Half bridge Strain Gauge 21 l Input Mode ACB 14 Differential 4 Index Manual Conventions 2 Manual Organization 1 Mode DMap 16 P Photo of DNx AI 208 Boards 4 Photo of STP AI 208 Panel 18 Physical Layout of the STP AI 208 23 Pinout 20 Q Quarter bridge Strain Gauge 22 R Resistor divider Networks 21 22 Round Cable 18 S Screw Terminal Panel 18 Screw terminal panels 24 sEttings Channel List 10 Configuration 9 Gain 10 Shunt Calibration 25 Shunt Calibration in C 30 Shunt Calibration in LabVIEW 31 Shunt Calibration Resistors 28 Single channel Wiring 20 SOT23 21 22 Specifications 19 Strain Gage 12 W Wiring Diagram Half Bridge 21 Wiring Settings 19 SS ee ERE Copyright 2007 Tel 508 921 4600 www ueidaq com Vers 4 6 M EU dc Ng Date November 2013 File Al 2081X fm RETE
17. Isolation PSO PS7 32 bit 66 MHz bus f t E G s 2 2 o 2 4 Figure 1 2 Block Diagram of DNx Al 208 Device Architecture 1 4 Layer Two D A converters produce excitation voltages The first converter drives exci Connectors tation on even numbered channels and the second one to odd numbered chan and Wiring nels Excitation voltage can be switched on and off on a per channel basis When an AI 208 performs continuous acquisition it applies voltage to the next channel in the channel list while acquiring the current channel This technique gives a channel enough time to settle and limits current consumption and heat dissipation by the layer Copyright 2009 Tel 508 921 4600 www ueidaq com Vers 4 6 spere Date November 2013 File AI208 Chap1 fm GER cm M Ced a DNx Al 208 Analog Input Layer Chapter 1 5 Introduction The Al 208 layer can measure voltage on every channel between the S and S terminals differential mode channels 0 7 between the Px lines channels 0x10 0x17 and signal ground and between the PSx and signal ground chan nels 0x20 0x27 The AI 208 layer can also be used to measure signals from differential signal sources other than bridges using the S and S terminals In such application situations
18. S Date November 2013 File AI 208 App A fm DNx Al 208 Analog Input Layer Figure A 4 shows a typical single channel wiring diagram for a Half bridge Strain Gauge connected to the STP AI 208 panel As the figure indicates you should remove the board mounted jumper when you use a 4 wire circuit Note that a half bridge circuit requires that you solder precision resistors to the board where indicated in Figure A 6 to complete the measuring bridge As an alterna tive you can install precision Resistor Divider Networks in SOT23 packages directly on the board to complete the bridge circuits Insert jumper when using a 3 wire connection Remove when using a 4 wire connection Rn Chan SOT 2 3 package for precision dividers to DB 37 Connector User supplied User supplied bridge completion bridge completion resistors Soldered resistors resistor onto board or connected divider in SOT23 to screw terminals package soldered to board Figure A 4 Single Channel Wiring Diagram Half Bridge R Copyright 2009 Tel 508 921 4600 www ueidaq com Vers 4 6 ille lu UE Date November 2013 File AI 208 App A fm DNx Al 208 Analog Input Layer Figure A 5 shows a typical single channel wiring diagram for a Quarter bridge Strain Gauge connected to the STP AI 208 panel As the figure indicates you should remove the board mounted jumper when you use a 3 wire Circuit Note that a quarter bridge circuit requires that you
19. ble 256 steps fom 5K to 205K External Excitation voltage Isolation 350 Vrms Overvoltage protection 40V 55V 1 5V 10 05V software selectable Excitation current 85 mA per channel Excitation type Pulsing for overheating protection Power consumption bridge resistance excitation dependent 2 5W 4 5W Operating temp tested 40 C to 85 C Operating humidity 9096 non condensing Table 1 1 DNx Al 208 Technical Specifications mV 0 000763 0 076294 0 001526 0 076294 0 001526 0 038147 0 001526 0 030518 0 001526 0 015259 0 002289 0 011444 0 002289 0 005722 0 002289 0 004578 6 200 6 0 002289 0 002289 10 0 003815 0 001907 0 006866 0 001717 Tel 508 921 4600 Date November 2013 Table 1 2 Offset and Gain Calibration Limits www ueidaq com Vers 4 6 File AI208 Chap1 fm 3 DNx Al 208 Analog Input Layer Chapter 1 4 Introduction Figure 1 1 is a photo of the DNA and DNR AI 208 Layer boards 120 pin DNR 120 pin DNA P bus connector J bus connector Layer Position Jumpers DB 37 female 37 pin I O connectors Figure 1 1 Photos of DNR and DNA AI 208 Boards 1 3 Device The DNA DNR AI 208 Analog Input Layer board has eight individual analog Architecture input channels A Block Diagram of the board layer is shown in Figure 1 2 PO P2 P4 P6 Pit P3 PS P7 PO P7
20. channel Copyright c Boston PASE um IPO JTO ome XTRIG AGND Q com 2005 USA RB2 RBS BETTE RES re DNA STP AI 208 ei c amp RCO RCi 75S 004A weal Figure A 6 Physical Layout of STP AI 208 Board E Jumper for Ch 3 PSn Pn Sn Sn AGND Ch 1 Copyright 2009 United Electronic Industries Inc Tel 508 921 4600 Date November 2013 www ueidaq com Vers 4 6 File AI 208 App A fm A 2 Other Accessories A 3 Layer Calibration DNx Al 208 Analog Input Layer In addition to the DNA STP AI 208 screw terminal panel the following cables and accessories are available for the Al 208 layer DNA CBL 37 3ft 37 way flat ribbon cable connects DNA AI 208 to panels DNA CBL 37S 3ft 37 way round extender cable with thumbscrew connectors on both ends connects DNA AI 208 to screw termination panels and other devices DNA STP 37 37 way screw terminal panel Please note that once you perform layer calibration yourself the factory calibra tion warranty is void For AI 208 layers we recommend annual factory recalibration at UEI Copyright 2009 United Electronic Industries Inc Tel 508 921 4600 www ueidaq com Vers 4 6 Date November 2013 File AI 208 App A fm DNx Al 208 Analog Input Layer Appendix B Shunt Calibration Support in Framework B 1 Introduction Strain gauges and load cell measurements are typically based on the Wheat sto
21. eScan amp voltageWithoutShunt session Stop Turn on shunt calibration for the first channel shunt branch R4 and program the shunt resistance to 100kOhms pChannel gt EnableShuntCalibration true pChannel SetShuntLocation UeiShuntLocationR4 pChannel SetShuntResistance 100000 0 Take one measurement with shunt resistance enabled session Start reader ReadSingleScan amp voltageWithShunt Session Stop Retrieve the global shunt resistance for the first channel and the actual excitation voltage double Rs pChannel GetActualShuntResistance double Vex pChannel GetExcitationVoltage Assume all gauge resistances are 330 Ohms double Rgage 330 calculate actual and theoretical offset caused by shunt Copyright 2009 Tel 508 921 4600 www ueidag com Vers 4 6 Bi aia ela ila Date November 2013 File Al 208 App B fm B 6 Shunt Calibration in LabVIEW STEP 1 Copyright 2009 United Electronic Industries Inc DNx Al 208 Analog Input Layer double measuredDeltaV voltageWithShunt voltageWithoutShunt double calculatedDeltaV Vex Rgage 4 0 Rs 2 0 Rgage Calculate gain adjustment factor double gaf calculatedDeltaV measuredDeltaV Turn off shunt resistor pChannel gt EnableShuntCalibration false Starts the session again session Start Read calibrated measurements double calibratedVoltage reader ReadSingleScan calibra
22. enerate output on a DNA DNR AI 208 layer working with the UeiDaq Framework High Level API Programming with the Low Level API This chapter describes the Low Level API commands for configuring and using a DNA DNR AI 208 layer Appendices A Accessories This appendix provides a list of accessories available for use with a DNA DNR AI 208 layer B Shunt Calibration Support in Framework This appendix describes procedures for using Framework to perform shunt calibration of strain gauges It includes examples of C code and LabVIEW procedures for shunt calibration Index This is an alphabetical index of topics covered in this manual A glossary of terms used with the PowerDNA Cube and layers can be viewed and or downloaded from www ueidaq com 508 921 4600 www ueidaq com Vers 4 6 United Electronic Industries Inc Date November 2013 File AI208 Chap1 fm 1 NOTE DNx Al 208 Analog Input Layer Chapter 1 Introduction Manual Conventions To help you get the most out of this manual and our products please note that we use the following conventions Tips are designed to highlight quick ways to get the job done or reveal good ideas you might not discover on your own Notes alert you to important information CAUTION Caution advises you of precautions to take to avoid injury data loss and damage to your boards or a system crash Text formatted in bold typeface generally represents text that should be entered verbati
23. idge completion resistors Since the panel is supplied with a DB 37 board mounted connector that mates directly with the I O connector on a DNA AI 208 Layer board it can be plugged directly into the Layer in the Cube As an alternative you can use a DNA CBL 37 37 way Flat Ribbon Cable or a DNA CBL 37S 37 way Round Cable to mount the unit as a desktop panel A photo of the panel is shown in Figure A 1 below Figure A 1 Photo of DNA STP AI 208 Screw Terminal Panel SESE IE LLLLLLLLLLLLLZLZLMiocL IM ssus i o Copyright 2009 Tel 508 921 4600 www ueidag com Vers 4 6 eee ee sere Date November 2013 File Al 208 App A fm DNx Al 208 Analog Input Layer The Technical Specifications for the DNA STP AI 208 are listed in the table below Technical Specifications Number of channels Bridge Configurations Full Bridge Half Bridge Quarter Bridge Wiring Schemes Full Bridge 6 and 4 wire Half Bridge 4 and 3 wire Quarter Bridge 3 and 2 wire Operating temperature 20 C to 85 C Operating humidity 9096 non condensing Dimensions 4 x 2 5 x 0 7 The Wiring Settings for the DNA STP AI 208 panel are listed in the table below Bridge Wiring Jumper Bridge Completion Configuration Scheme Settings Resistors 6 wire J Off 4 wire J On 4 wire J Off Half Bridge Senne Zon RA RB or RN 3 wire J Off Ra Rs or RN 2 wire J On Rc RSTRAIN Full Bridge None required
24. k using specified channels The Al 208 layer is capable of providing two sources of excitation voltage Excitation A is connected to even channels and B is connected to odd channels Excitation voltage can be selected and set at any level from 1 5V to 10V This function sets up excitation voltage as close as possible to the requested level and reads it back from the selected channels The user can select either channels 0x10 through 0x17 to read the excitation voltage from the Px terminal four wire connection or channels 0x20 through 0x27 to read the excitation voltage from PSx terminals six wire connection All readings are performed relative to AGND The user has to use the read back excitation voltage from the terminal because of DACs there is a voltage drop in the strain gauge leads and DAQ output quantization error amounts to 1 1024 of the range Note that this function must be called before starting data acquisition or reading channels in order to set up the proper excitation voltage source before gathering data DgAdv208ReadChannel This function performs raw measurements of the following values 0x0 0x27 connect both differential inputs of the PGA to read 2 5V voltage reference DQOL IOCTL208 READ Rs measure switch resistance Rs DQOL IOCTL208 READ Rx measure multiplexer resistance DQOL IOCTL208 READ Ra measure shunt resistor Ra DQL IOCTL208 READ Rb measure shunt resistor Rb DOL IOCTL208 READ SS measure S to S DOL
25. lling the DqCmdSetC1k command after the first call to DgAdv208Read Copyright 2009 Tel 508 921 4600 www ueidaq com Vers 4 6 United Electronic Industries Inc Date November 2013 File AI208 Chap3 fm DNx Al 208 Analog Input Layer Chapter 3 11 Programming with the Low Level API Therefore you cannot call this function when the layer is involved in any streaming or data mapping operations If you specify a short timeout delay this function can time out when called for the first time because it is executed as a pending command and layer programming takes up to 10ms Once this function is called the layer continuously acquires data and every next call function returns the latest acquired data If you would like to cancel ongoing sampling call the same function with OXFFFFFFFF as a channel number DgAdv208SetControl This function allows you to set up different internal parameters The following sub functions are available DOL IOCTL208 SET Ra setvalue for shunt calibration resistor A in 256 steps P to S DOL IOCTL208 SET Rb setvalue for shunt calibration resistor B in 256 steps S to P DOL IOCTL208 SET EXC A setexcitation DAC A DOL IOCTL208 SET EXC B setexcitation DAC B DOL IOCTL208 SET EXC CH switch excitation channels on or off DOL IOCTL208 READ AGND analog ground DQL IOCTL208 READ REF DqAdv208SetExcVoltage Set excitation voltage for excitation sources A and B and measure it bac
26. m For instance it can represent a command as in the following exam ple You can instruct users how to run setup using a command such as setup exe Copyright 2009 United Electronic Industries Inc Tel 508 921 4600 www ueidaq com Vers 4 6 Date November 2013 File AI208 Chap1 fm 2 1 2 The DNx Al 208 Analog Input Layer Copyright 2009 United Electronic Industries Inc DNx Al 208 Analog Input Layer Chapter 1 Introduction This manual describes the DNA AI 208 18 bit 8 channel Strain Gauge Analog Input Board Layer It also describes the DNA STP 208 Screw Terminal Panel accessory board The technical specifications for the DNA DNR AI 208 Analog Input Layer are listed in Table 1 1 Number of channels 8 differential ADC resolution 18 bits Sampling rate 1S s 1 kS s per channel Input range 10V FIFO size 512 samples Wiring scheme 4 and 6 wire with Kelvin connection all channels share the same ground Bridge configurations Full Bridge Half Bridge with ext terminal panel Quarter Bridge with ext terminal panel Bridge resistance 120Q 3500 100082 and custom Input impedance 10MQ in parallel with SOpF Gains 1 2 4 8 10 20 40 80 100 200 400 800 Gain accuracy Offset accuracy See Table 1 2 Temperature drift Offset drift Gain drift 5uV C typ 30ppm C G 1 45ppm C G 800 Shunt calibration Onboard software selecta
27. ne bridge which allows the measurement of the very small resistance changes that characterize strain gauges The values measured from a Wheatstone bridge are very sensitive to the resis tance of its branches and there can be signal attenuation caused by lead resis tances Shunt calibration is used to compensate for the loss of sensitivity The strain gauge is desensitized Shunt calibration is the action of simulating a load on one of the branches of a Wheatstone bridge with a resistor of a known value and comparing the mea sured value to the calculated ideal value The ratio between the ideal value and the measured value is called Gain Adjustment Factor It should be very close to 1 Multiplying the measurement value by the gain adjustment factor compensates for the loss of sensitivity intro duced by the lead resistances in a four wire gauge B 2 Theory Load cell and strain gauge measurement are normally done through a Wheat stone bridge For load cells the Wheatstone bridge is built into the cell For Strain Gauges the bridge is part of the wiring Figure B 1 Strain Gauge Bridge Vex is the excitation voltage applied to the bridge by the instrument Vout is the output voltage measured by the instrument The formula to calculate Vout knowing Vex is R4 RI 4 Vout V _ o e n Eq 1 i R34R4 RI R Copyright 2009 Tel 508 921 4600 www ueidaq com Vers 4 6 illae p S Date November 2013 File AI 208 A
28. pp B fm DNx Al 208 Analog Input Layer Simulating a load is usually done by adding a larger resistance in parallel with one of the branches To simulate a compression load we need to add a shunt resistance to Rg and to simulate a tension load we need to add a resistance to R3 The following figure assumes that all branch resistances are equal to Rg strain gauge resistance and that the R4 branch was shunted with a resistance Rs shunt resistance Figure B 2 Strain Gauge with Shunt Resistance R Added After replacing R4 with R4 Rs R4 Rs in Equation 1 the voltage output of the bridge when the shunt calibration resistor is enabled is R4 RI E 2 Vout V RA Rs g e aa RA RI R2 RA c Rs The voltage output change after enabling the shunt resistor is AVout Vouts Vout RA Eq 3 AVout Vex Jt Hs Bc R34 R4 R3 R4 R4 Rs In most applications all branches of the Wheatstone bridge use the same resis tance Standard values for Rg are 120 350 and 1000 Ohms After setting R1 R2 R3 Rg Equation 3 becomes 4 AVout V cue Ega PS JRs 2Rg paus na Copyright 2009 Tel 508 921 4600 www ueidaq com Vers 4 6 United Electronic Industries Inc Date November 2013 File Al 208 App B fm DNx Al 208 Analog Input Layer Shunting branch R3 instead of R4 to simulate a tensile load gives Rg Eq 5 AVout Ve IE Rs 2 Re Now that we know how to calculate the theo
29. retical offset on the Wheatstone bridge output when one of the branch resistances is changed with a known value we can compare it with the measured value and get the Gain Adjustment Factor Eq 6 Gaf AVoutCalculated AVoutMeasured Multiplying each measured values by the Gain Adjustment Factor gives us cal ibrated measurements SSS Ee Copyright 2009 Tel 508 921 4600 www ueidaq com Vers 4 6 Bi aia Date November 2013 File Al 208 App B fm _ _ EE rr a UH o 3 DNx Al 208 Analog Input Layer B 3 Using Shunt There are two programmable digital shunt calibration resistors on the Al 208 Ra Resistors on and Rb The Shunt calibration resistor Ra shunts the branch R4 and Rb shunts the Al 208 R3 External Wiring STP Al 208 RL P O To use the shunt ___ H J Disconnect normal calibration feature O sense wiring from 5k 0 1 remove jumper PS y PS when shunt calibration is used i Ra S E Mux 9 5k 0 1 lt Rb RL p l Figure B 3 Using Shunt Resistors on the DNA AI 208 Layer The internal circuitry of the Al 208 makes it difficult to know the exact value of the resistance used to shunt the Wheatstone bridge due to the following factors The digital shunt resistor accuracy is only 3096 and needs to be mea sured prior to doing any calculation The resistance of internal components on the Al 208 such as multiplex
30. solder precision resistors to the board where indicated in Figure A 6 to complete the measuring bridge As an alternative you can install precision resistor divider networks in SOT23 pack ages directly on the board as shown in Figure A 6 to complete the bridge cir cuits Insert jumper when using a 2 wire connection Remove when using a 3 wire connection ae i Rw Chan J SOT 2 3 package for precision dividers RsTRAIN Rp Ro2 0 196 to DB 37 Connector User supplied eE e ea a bridge completion 19 p resistors resistor resistors Soldered dig divider in SOT23 onto board or connected to screw terminals Pacers soldered to board Figure A 5 Single Channel Wiring Diagram Quarter Bridge a o o o o oer N I n n Copyright 2009 Tel 508 921 4600 www ueidaq com Vers 4 6 ille lu UE Date November 2013 File AI 208 App A fm Solder terminals for external trigger connection Plug into Mating Connector on Al 208 Layer Solder terminals for SOT23 divider Solder terminals for bridge completion resistors Ground for connector shield DNx Al 208 Analog Input Layer Figure A 6 shows the physical layout of the STP AI 208 board indicating where you should install bridge completion resistors or resistor divider packages if required for your application It also shows which terminals to use for making the strain gauge connections for a typical
31. t shunt calibration digital potentiometer The digital potentiometer has a 30 initial resistance accuracy 60 150 Ohm runner resistance and a 35ppm temperature coefficient Thus measuring this resistor is crucial for shunt calibration An additional series resistor 4 99k 0 01 is inserted in the shunt calibration circuit to ensure precise measurement 3 4 Using Layer This is a pseudo code example that highlights the sequence of functions needed in ACB Mode to use ACB on the AI 208 layer A complete example with error checking can be found in the directory SampleACB208 include PDNA h unit configuration word define CFG208 DO LN ENABLED V DQ LN ACTIVE DQ LN CLCKSRCO DQ LN RAW32 uint32 Config CFG208 STEP 1 Start DQE engine ifndef WIN32 DgInitDAQLib endif Copyright 2009 Tel 508 921 4600 www ueidaq com Vers 4 6 United iecore industries hes Date November 2013 File AI208 Chap3 fm DNx Al 208 Analog Input Layer Chapter 3 13 Programming with the Low Level API Start engine DqStartDQEngine 1000 1 amp pDqe NULL Open communication with IOM hd0 DqOpenlOM IOM IPADDRO DQ UDP DAQ PORT TIMEOUT DELAY amp RdCfg Receive IOM crucial identification data DqCmdEcho hd0 DQRdCfg Set up channel list for n 0 n CHANNELS n CL n n STEP 2 Create and initialize host and IOM sides Now we are going to test device DgAcbCreate pDqe hd0 DEVN DQ SSOIN
32. te ftp ftp ueidaq com Product Disclaimer WARNING DO NOT USE PRODUCTS SOLD BY UNITED ELECTRONIC INDUSTRIES INC AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS Products sold by United Electronic Industries Inc are not authorized for use as critical components in life support devices or systems A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness Any attempt to purchase any United Electronic Industries Inc product for that purpose is null and void and United Electronic Industries Inc accepts no liability whatsoever in contract tort or otherwise whether or not resulting from our or our employees negligence or failure to detect an improper purchase NOTE Specifications shown in this document may change from time to time Check with UEI for current status Chapter 1 Introduction sseeseseeeee RR I hh hh 1 1 1 OLGaNIZAllON ED 1 1 2 The DNx Al 208 Analog Input Layer illii 3 1 3 Device Architecture use bosse buena dope eae dope ae soc ned gets 4 1 4 Layer Connectors and Wiring 0 060 cece ett 4 1 4 1 Collectors ive et RR ada RE al E be ER wee tae eee E EE 5 1 4 2 Analog Input Ground Connections 00 cece eller 6 Chapter 2 Programming with the High Level API lesen 7 2 1 Creating a session
33. tedVoltage calibratedVoltage calibratedVoltage gaf session CleanUp The following is an example of a typical LabVIEW procedure for performing shunt calibration for strain gauges The procedure is as follows Create a session to measure voltage with excitation Maximum range DELH Tel 508 921 4600 www ueidaq com Vers 4 6 Date November 2013 File AI 208 App B fm DNx Al 208 Analog Input Layer STEP 3 Measure bridge output with shunt enabled Enable shunt resistor on all channels ith shunt V and program shunt resistance ES UeiDaq Lo M STEP 4 Calculate Gain Adjustment Factor Bridge Gage resistance Ohms Dert Measurements with shunt V gaf Vexc Rgage 4 0 Rshunt 2 0 Rgage deltav Measurements without shunt V ain adjustment actor ChannelList AIVEx Excitation P ChannelList AIVEx ShuntResistance ChannelList AIVEx EnableShuntCal PEOR i a EE LLL Ir ILZZLLLLGLLLLLLLLGQIZIS E ZIU Copyright 2009 Tel 508 921 4600 United Electronic Industries Inc www ueidaq com Vers 4 6 Date November 2013 File Al 208 App B fm GT M e o Hg i u zzz BQ il Numerics 3 wire Circuit 22 6 wire Circuit 20 A Architecture 4 B Block Diagram 4 Board mounted Jumper 21 22 Bridge Completion Resistors 19 Bridge Configurations 18 C
34. uld be the connection to S shown in bold in Figure B 3 A low level API function allows activation and precise measurement of Ra and Rb Once Ra or Rb value is known the value can be inserted into Equation 4 or 5 to calculate the Gain Adjustment Factor Flow of operations The shunt calibration will be performed using the following steps Measure bridge output voltage without shunt Engage shunt and measure bridge output voltage again Calculate what the bridge out put offset should be theoreti cally using Eq 4 or 5 Calculate Gain Adjustment Fac tor Disengage shunt calibration resistors and apply adjustment factor to every measurement from now on Tel 508 921 4600 www ueidaq com Vers 4 6 Date November 2013 File AI 208 App B fm DNx Al 208 Analog Input Layer B 5 Shunt The following is an example of C code used for performing shunt calibration Calibration in of strain gauges C Create session for measurement with excitation set to 10V CUeiSession session CUeiAIVExChannel pChannel session CreateAIVexChannel pdna 192 168 100 2 Dev0 Ai0O 0 015 0 015 UeiSensorQuarterBridge 10 0 false UeiAIChannelInputModeDifferential Session ConfigureTimingForSimpleIO CueiAnalogScaledReader reader session GetDataStream double voltageWithoutShunt voltageWithShunt Take one measurement without shunt resistor session Start reader ReadSingl
35. urpose Macro 31 DQ LNCL NEXT Tells firmware that there is a Next Entry in the channel list 20 DQ LNCL TSRQ Request timestamp as the next data point 11 8 Gain DQ LNCL GAIN 7 0 Channel number Gains are different for different options of the Al 208 layer as listed in the follow ing table Layer type Range Gain Gain Min Allowed Number Settling Time us Al 201 208 10V 1 0 40 5V 2 1 50 2 5V 4 2 60 1 25V 8 3 70 1V 10 4 80 500mV 20 5 100 250mV 40 6 120 125mV 80 7 140 100mV 100 8 160 50mV 200 9 180 25mV 400 10 200 12 5mV 800 11 220 NOTE The Minimum Allowed Settling Time is the shortest time for which the firmware allows a channel to settle When the scan rate and channel are programmed the firmware allocates the minimum time for each channel depending on the gain selected and then stretches the settling time as much as possible to utilize at least 2 3 of the time between scan clocks 3 3 Layer The AI 208 layer has a number of layer specific functions as follows specific DqAdv208Read Commands This function uses DqgReadAIChannel but converts data using and internal knowledge of the input range and gain of every channel Parameters When this function is called for the first time the firmware stops any ongoing operation on the device specified and reprograms it in accordance with the channel list supplied This function uses the preprogrammed CL update frequency 10Hz You can reprogram the update frequency by ca
36. wo resistors 10k lt R lt 100k provide Add this connection to ensure that both grounds are at the same potential return paths to ground for bias currents NOT RECOMMENDED DNA STP AI U Single Ended Ground Referenced Figure 1 4 Recommended Ground Connections for Analog Inputs Because all analog input channels in Al 201 202 207 208 225 layers are isolated as a group you can connect layer AGND to the ground of the signal source and eliminate the resistors shown in Figure 1 4 for floating differential input signals Copyright 2009 Tel 508 921 4600 www ueidaq com Vers 4 6 United Electronic Industries Inc Date November 2013 File AI208 Chap1 fm DNx Al 208 Analog Input Layer Chapter 2 Programming with the High Level API Chapter 2 Programming with the High Level API 2 1 Creating a session This chapter describes how to program the PowerDNA DNR AI 208 using UeiDaq s Framework High Level API Since Framework is object oriented its objects can be manipulated in the same manner using different development environments such as Visual C Visual Basic or LabVIEW Although the following section focuses only on the C API the concept is the same no matter what programming language you use Please refer to the UeiDag Framework User Manual for more information on using other programming languages The Session object controls all operations on your PowerDNA device There fore the first task is to create a session object as
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