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GE Fanuc / SBS CM4 Manual

1. 3 17 Figure 3 9 Power up reset circuitry eee eee eee 3 18 Pie S FOR sio tee 3 19 Figure 3 11 PCI reset when CM4 is a system controller sese 3 21 Figure 3 12 PCI reset when CM4 is a peripheral card sese sese 3 21 Elgure 15 eege 3 23 Figure 5 14 Decoder CPLD PCI interrupt CIECO acia 3 24 Pigure 3 15 Decoder CPLD Interrupt CIGN senesssisivessinsensiecsswesssasennsisbsancestarensdeessaceseracens 3 25 Figure 3 16 CPU interrupt erer 3 26 Figure 3 17 Primary clock Cir AMA abba TUGLAS eo ES oma ekba gaki 3 27 Prone SES PORER CICULI EE 3 28 iento NCE LEO eT T 3 30 Figure 4 1 CM4 components front VIEW sss aiid or ged 4 1 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com CM4 User s Guide SBS Technologies Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com viii Table Sl Processor Volat Sia en ee ee edro ad 3 1 Table 3 2 CompactPCI connector P7201 pin assignment esse eee eee 3 3 Table 3 3 CompactPCI connector P7202 pin assignments esse ee eee 3 4 Table 3 4 PMC connectors P7101 and P7102 pin assignments sss eee eee eee 3 5 Table 3 5 PMC P7103 pin assignments sss sese eee eee 3 6 Table uereg 3 7 Table 3 7 Tsi107 memory map processor VIEW esse ee eee eee eee 3 10 Table 3 8 Tsil07 memory map PCI bus Master view sese eee eee eee eee 3 11 Table 3 2 X bus VO address BE 3 11 kis PPCM Os Ai it At OU T 3 11 Table 3 11 PCI IDSEL
2. 3 20 CM4 User s Guide SBS Technologies Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com s BS Board Description Decoder PCI 6254 Decoder CPLD PCI RSTA P RSTINA PCI S RSTOUTA CPLD Bridge Figure 3 11 PCI reset when CM4 is a system controller The PCI reset signal is the only signal affected by whether the CM4 is a system controller or peripheral card CM4 is a Peripheral Card When the CM4 is installed in a non system controller slot the PCI 6254 PCI Bridge changes to non transparent mode In non transparent mode the PCI 6254 appears as just another PCI device on the PCI bus The PCI 6254 receives the P_RSTIN reset which resets the primary PCI inter face but it does not pass the reset on to the secondary PCI interface In non transparent mode the secondary PCI interface reset output S_RSTOUT becomes an input for system resets from the system controller When the CM4 is a peripheral card a PCI reset S_RST is received through the CompactPCI connector P7201 and is routed through the Decoder CPLD An input buffer enabled by the de asserted SYSEN signal drives the PCI reset to the PCI 6254 secondary PCI interface on the S_RSTOUT line The PCI reset asserted on the PCI 6254 secondary interface resets secondary PCI interface configuration registers as shown in Figure 3 12 Decoder PCI 6254 Decoder CPLD PCI RSTA P RSTINZ PCI S RSTOUTA CPLD Bridge Figure 3 12 P
3. A rtisan Artisan Technology Group is your source for quality SL new and certified used pre owned equipment FAST SHIPPING AND SERVICE CENTER REPAIRS WE BUY USED EQUIPMENT DELIVERY Experienced engineers and technicians on staff Sell your excess underutilized and idle used equipment TENS OFTHOUSANDS OF at our full service in house repair center We also offer credit for buy backs and trade ins IN STOCK ITEMS www artisantg com WeBuyEquipment A EQUIPMENT DEMOS HUNDREDS OF Instra lea REMOTE INSPECTION LOOKING FOR MORE INFORMATION TO A Remotely inspect equipment before purchasing with Visit us on the web at www artisantg com 7 for more our interactive website at www instraview com 7 information on price quotations drivers technical LEASING MONTHLY specifications manuals and documentation RENTALS ITAR CERTIFIED e km Contact us 888 88 SOURCE sales artisantg com www artisantg com SBS Technologies CM4 Single Boa Conduction or P Convection Cooling pa i i gees PowerPC rocessors PPC 750 MPC755 MPC7410 4 53 Oulel JE JE Ak Rev F Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com SBS Copyright 2005 SBS Technologies Inc All rights reserved CM4 User s Manual Rev F This document and its contents are provided as is with no warranties of any kind whether express or
4. Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com SBS Customer Service 6 3 Customer Service The following is contact information for SBS Technologies Customer Service Department E mail support sbc sbs com Telephone 919 851 1101 Fax 919 851 2844 Mail SBS Technologies 6301 Chapel Hill Rd Raleigh N C 27607 5115 6 4 Warranty Information SBS Technologies provides a two year product warranty Included in the warranty are specific stipulations concerning application and use of the product Please review the warranty before requesting service 6 4 1 Warranty All Single Board Computer SBC products manufactured and sold by SBS Technologies Inc include a two year warranty for defects in workmanship and materials for hardware unless other wise stated in an Original Equipment Manufacturer OEM agreement or contract with SBS Tech nologies Software is warranted to be readable and functional upon receipt This warranty shall not apply to equipment that has been repaired or altered outside of SBS facilities in any way as to in the judgement of SBS affect its reliability Nor will it apply if the equipment has been used in a manner exceeding its specifications if the serial number has been removed or if the equipment has been subject to accident disaster improper or inadequate maintenance or electrical or physi cal misuse misapplication or abuse SBS will at its option repair or replac
5. Serial port COM2 Interrupt Mask O disable mask 1 enable mask Serial port COM 1 Interrupt Mask 0 disable mask 1 enable mask CM4 User s Guide SBS Technologies Guaranteed 888 88 SOURCE www artisantg com SBS CPLD Registers 5 6 Status Input Port Register The Status Input Port register is an 8 bit read only register that provides a status indication for the PCI bus frequency always set to 33MHz Flash EEPROM status and an optional external boot select jumper that allows a custom boot image to be loaded into the boot flash This register is external to the CPLD but is controlled by the CPLD Address offset OxFFOO_8050 Access Read only un mm o O 7 PCI BUS FREQ Master PCI Bus Frequency 1 33MHz FLASH EEPROM STS Flash EEPROM Status U programming or erase function in progress 1 data available BOOTSEL BOOTSEL signal status indicates the status of the BOOT SEL signal U jumper installed 1 jumper not installed NN CM4 does not include an on board BOOTSEL jumper however an external am may be attached to this signal 4to0 GA4 to GAO Geographical Address connects to GA pins on cPCI 7202 connector CM4 User s Guide SBS Technologies 5 5 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com SBS CPLD Registers 5 7 Status Output Port Register The Status Output Port register is an 8 bit read write register that controls the
6. Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com SBS Components 4 4 PCI 6254 PCI Bridge The PCI 6254 PCI Bridge provides isolation and connection between the PCI local bus and the cPCI bus The PCI 6254 PCI Bridge changes how it handles the connections between these two buses according to whether the CM4 is a system controller or peripheral card When the CM4 is a system controller the PCI 6254 operates 1n transparent mode which means that 1t passes PCI interrupt reset and clock signals from the local PCI bus to the cPCI backplane as though it were transparent When the CM4 is a peripheral card the PCI 6254 operates in non transparent mode which means that it appears as a PCI device to the Tsil07 Host Bridge and does not pass PCI resets interrupts and clocks from the PCI local bus to the cPCI backplane 4 5 SDRAM The CM4 offers one bank of 16M x 16 SDRAM chips up to four devices for a total on board system memory from 128MB to 512MB of SDRAM with a single 8 bit ECC device providing single bit error correction and double bit error detection The memory reside on a 72 bit IVOMHz memory bus The Ts1107 Host Bridge provides the memory controller and interface 4 6 Flash Memory The CM4 includes one 8M x 8 E28F640J3A 120 StrataFlash device for boot flash and four 64Mb RC28F640J3A 120 StrataFlash for a total of 64MB of extended flash memory 4 6 1 Boot Flash The CM4
7. controlled by application software Input ports have edge detection circuits which require a minimum input pulse width of 100ns Pulses less than 100ns may not be detected Once an edge in either direction is detected a bit is set in the DI O Interrupt Status Register If the corresponding bit in the DI O Interrupt Mask Reg ister is set the status register bit causes the assertion of an interrupt Software can disable the interrupt source by masking it or by writing a 1 to the bit in the DI O Interrupt Status Register to clear it The DINQ register is provided to allow software to read the state of the DI O ports Soft ware must read the current state of a DI O input to determine the direction of an edge that was detected Therefore software must consider the fact that a short pulse on an input port could cause the wrong conclusion to be drawn Output ports are directly controlled by the values of the five software controlled bits in the DOUT register The corresponding bit in the DOUTEN register must be set by software to make a port an output port since they default at reset to input ports Both of these registers are write only registers due to resource constraints in the CPLD 3 14 CM4 User s Guide SBS Technologies Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com SBS Board Description Technologies X bus Decoder DE P7202 DOUT Register D 1 00 0x8060 Write DOU
8. 20 ERL PE RE 3 20 3144 WW sn 3 21 Ses ilojn Qa ee 3 22 dy A Ol ee a NOOO N A 3 22 313 2 Obo RET BI e radios 3 25 CIOT C T eege 3 26 3 16 1 24MHz and 14 318MHz Clocks E 3 26 Se R al Time Clock E 3 26 3 16 3 Ts1107 Clock Distribution 20 0 cc eee 3 27 3 16 4 PCI 6254 PCI Bridge Clock Operation Transparent Mode 3 29 3 16 5 PCI 6254 PCI Bridge Clock Operation Non Transparent Mode 3 29 Chapter 4 Components 4 1 42 4 3 4 4 4 5 4 6 4 7 4 8 4 9 4 10 4 11 Component Location ege 4 1 EE ege EEGENEN 4 2 Ts1107 Host BJOG esla circos arco cesta nist 4 3 Al Stern Rue TEE 4 3 4 3 2 Memory Controller and Bus Interface sese sese 4 3 Any 0 BUS enge 4 3 Ad Intern A COMI EE 4 3 o RA R Hs TT 4 4 ARTE W 4 4 Flash MEMO rra ii E 4 4 BGA Boo r Nr 4 4 AA o sn siS EE 4 4 PEA TTT E OEA 4 5 a li o eebe 4 5 STIG6C2550 Dual Chame BEN KC 4 5 EE H 4 6 PS ei Cale Ume MI lo AMAN AP A a EE A 4 6 Chapter 5 CPLD Registers 5 1 Watchdog Control Register essa so TTT osito its does 5 1 CM4 User s Guide SBS Technologies Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 3 2 MCP Ticker Control a ascii oia 5 2 II MCP Ticker Reset L E immer jnoj evan voto toro ias 5 2 5 4 Interrupt Status Register sees ee eee 5 3 SD a e E eo RO 5 4 30 Status oput Port KS ur o mesada op ene 5 5 5 7 HEIEREN 5 6 Lo CPLD Version IRC ONSET easter cido 5
9. 300 Revision F Copyright 2005 SBS Technologies Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com A rtisan Artisan Technology Group is your source for quality SL new and certified used pre owned equipment FAST SHIPPING AND SERVICE CENTER REPAIRS WE BUY USED EQUIPMENT DELIVERY Experienced engineers and technicians on staff Sell your excess underutilized and idle used equipment TENS OFTHOUSANDS OF at our full service in house repair center We also offer credit for buy backs and trade ins IN STOCK ITEMS www artisantg com WeBuyEquipment A EQUIPMENT DEMOS HUNDREDS OF Instra lea REMOTE INSPECTION LOOKING FOR MORE INFORMATION TO A Remotely inspect equipment before purchasing with Visit us on the web at www artisantg com 7 for more our interactive website at www instraview com 7 information on price quotations drivers technical LEASING MONTHLY specifications manuals and documentation RENTALS ITAR CERTIFIED e km Contact us 888 88 SOURCE sales artisantg com www artisantg com
10. and 2 5V within a specified range If the 3 3V supply drifts above or below its specified range the power monitor will assert an interrupt INT3V to the Decoder CPLD If it is out of range for longer than 50us the power monitor asserts the reset out put BOARD RST which resets the CMA If the 2 5V supply drifts outside its specified range the power monitor will assert the VCC2 5OK signal that disables the LM2636 Buck Controller which provides the processor core voltages If the 2 5V supply is out of specification for longer than 50us the power monitor will assert the reset output BOARD_RST which resets the CM4 BOARD RSTf will remain asserted for 200ms even if the 3 3V or 2 5V supply returns to the specified range Table 3 1 Processor voltages Configuration resistors on the input of the LM2636 Buck Controller set processor core voltages VCCP according to the installed processor as listed in Table 3 1 CM4 User s Guide SBS Technologies 3 1 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com SBS Board Description Technologies 3 3 Connector Locations PMC P7101 PMC P7102 cPCI P7202 cPCI P7201 JTAG P1100 PMC P7103 Figure 3 1 Connector locations convection cooling version 3 4 Front Panel E D The CM4 front panel convection cooled configuration only provides access to a PMC module front panel It also includes a locking extracti
11. cz S RSTA S RSTOUTA cPCI P7201 Non transparent Bridge mode ls sss sss ss ACE A E A i wk Figure 3 10 Reset circuitry CM4 User s Guide SBS Technologies 3 19 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com s BS Board Description Emulator Reset The CM4 provides a JTAG COP port P1100 for board test and evaluation The COP port pro vides these reset signals Hard reset COP_HRST and Test reset COP_RST These reset signals are generated by test software downloaded to the CM4 through a emulator They allow the test software to perform hard resets complete system resets and test resets 3 14 2 Soft Resets The CM4 reset circuit includes two soft reset lines e 107_SRESET e COP_SRESET The Tsil07 Host Bridge outputs the 107_SRESET to the Decoder CPLD where it is ORed with the COP_SRESET from the COP port The 107_SRESET signal is triggered by application software The COP_SRESET is triggered by an emulator typically test software attached to the P1100 JTAG COP port If one of these reset lines is asserted the CPU_SRESET line is asserted causing the processor to perform a soft reset that resets the processor internal logic but does not directly affect the states of output signals 3 14 3 PCI Resets When the CM4 is installed in a system slot it can send PCI resets to peripheral cards in the sys tem through the CompactPCI backplane but cannot receiv
12. enables and controls the watchdog timer CM4 BSP firmware writes a 1 to the WD ON bit b0 to enable the watchdog timer The watchdog timer has a 0 5 second time out Optional CM4 BSP firmware can read the Watchdog Control Register to reset the count If the BSP firmware does not reset the count and it expires the watchdog circuitry issues a reset sig nal to the processor Address offset OxFFOO 8000 Access Read write HH TT H RSVD Reserved always read as 0 2 WD EXP Watchdog timer Expired indicates the watchdog timer has expired U timer has not expired 1 timer has expired NOTE Writing a 1 to this bit clears the bit 1 WD SET Watchdog timer forces the WD REL signal at the P7202 connector to 1 U WDG_REL is set if watchdog is expired 1 WDG_REL is always set WD_ON Watchdog timer Enable enables the watchdog timer U disable 1 enable CM4 User s Guide SBS Technologies 5 1 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com SBS CPLD Registers 5 2 MCP Ticker Control Register The MCP Ticker Control register is an 8 bit read write register that sets the duration of the reset timer and provides the ability to read the status of the Non Maskable Interrupt NMI The NMI is held de asserted when the T_SEL bits b2 0 are 000 Address offset OxFFOO 8001 Access Read write ag PR Bean Zeie 71717 RSVD Reserved always reads as 0
13. enton eme aeae nor Unused pulled up to Vcc 3 4 CM4 User s Guide SBS Technologies Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com SBS Technologies 3 5 2 PMC Connectors Table 3 4 PMC connectors P7101 and P7102 pin assignments PMC P7101 me ee 10 CI ex EN ES 40 LOCK AD12 48 ADTI E CIBETO CECI a y Not used pulled up to Vcc ES CM4 User s Guide SBS Technologies Artisan Technology Group Quality Instrumentation Board Description PMC P7102 a Tae o lem oa erao eee C BE 2 lm 3 5 Guaranteed 888 88 SOURCE www artisantg com SBS Technologies 3 6 Board Description Table 3 5 PMC P7103 pin assignments PMC P7103 Pin Assignment _ PMCI O 27 Artisan Technology Group Quality Instrumentation CAZEN e Puaro os CM4 User s Guide SBS Technologies Guaranteed 888 88 SOURCE www artisantg com SBS Board Description Tec EE 3 5 3 JTAG COP Port P1100 CM4 provides a JTAG COP port P1100 attached to the processor for single stepping through code on the processor The JTAG COP port is fully functional with EST VisionProbe II emulators Table 3 6 JTAG COP port pin assignments e am Pe we e oor ms epe COP HASTE Figure 3 3 JTAG COP port P1100 CM4 User s Guide SBS Technologies 3 7 Artisan T
14. technical support service and repair e Product warranty information e Return Material Authorization RMA information e Documentation Feedback form Returned product will not be accepted without a properly authorized RMA number An RMA number can be authorized by contacting SBS Technologies Customer Service Department see Customer Service on page 6 2 To avoid applicable charges the customer should make every effort to resolve issues including consulting the technical sections of this manual and con tacting Technical Support before securing an RMA SBS Technologies makes every effort to include all the information needed to properly install set up and operate our products in our User s Guides However if information 19 needed that cannot be found in the manual please include relevant comments suggestions and constructive criti cisms in the Documentation Feedback Form and return it to SBS Technologies 6 2 Updated User Guides and Data Sheets The latest revisions of product documentation including User s Guides and Data Sheets are avail able in PDF format from the SBS web site PDF documents can be viewed using Adobe Acrobat Reader which is available for downloading from the Adobe web site www adobe com at no charge All product documentation can be requested through SBS Technologies Customer Service Department see Customer Service on page 6 2 CM4 User s Guide SBS Technologies 6 1 Artisan Technology Group
15. through the RST_BUT signal available at CompactPCI connector P7202 see Figure 3 10 on page 3 19 When the RST_BUT signal is asserted the Decoder CPLD inputs the RST BUTF to a logical OR gate with the BOARD_RST and COP HRESET signal to assert the 107_HRESET line to the Ts1107PCI Bridge The Ts1107 then asserts the 107_CPUHRST signal that passes through the Decoder CPLD to reset the processor Inside the Decoder CPLD the 107 CPUHRST signal is also connected through a logical OR gate with the BOARD RST to assert the PCI_LRST The PCI_RST signal resets all PCI devices on the CM4 see PCI Resets on page 3 20 SBS Technologies offers a CM4 Transition Module that includes a reset switch on a rear panel or a RST BUTY pin in the 26 pin Miscellaneous connector 3 18 CM4 User s Guide SBS Technologies Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com s BS Board Description 107_SRESET O KI 107 HRESETA RARS P aot dee cop COP_HRSTH Sel P1100 COP_SRST gt CPC COP_RSTH E r CPLD Bridge Ethernet PCI_RST 82559ER Controller Power up BOARD RSTA Reset Circuitry PCI RST Boot flash PCI RST ST16C2550 UART qd gt Transceivers 2 pcs PCI RSTE PMC 3 P7102 PCI 6254 GPCI S_RSTOUT Bridge Transparent mode A cPCI C5 P7201 CM4 is a peripheral card CaN PCI 6254 cPCI
16. 6 CAT RE SCG iia 5 7 Mu DOT TER ES Ci careto Eee 5 7 SO DOUTEN uli EE 5 8 SE DINOR NT ee 5 8 3 10 DUO Interrupt Status A T mesada manO ok snb dta 5 9 5 11 DI O Interrupt Mask Register sese eee 5 10 Chapter 6 Customer Service Index 6 1 6 2 6 3 6 4 6 5 6 6 MOGUC e EE 6 1 Updated User Guides and Data Sheets sss 6 1 US esus T 6 2 Warranty a rS e ane TT 6 2 G L Waranty ATTRRRFRFFFFRFFRRFRFR R R R FR F RR RRVRFRRRRMVEFRVRFRwVFRrRpTIrTT TP P M 6 2 6 4 2 Non Warranty Terms and Conditions sss sees 6 3 Return Material Authorization RMA sse 6 3 Documentation Feedback Form gesteet naso soka sono kak Feba daad eege 6 5 CM4 User s Guide SBS Technologies Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com SBS Ta fa za j a Va eh us recnnorogies List of Figures Figure 1 1 Convection cooled confoeuraton 1 2 Figure 1 2 Conduction cooled configuration sese sese eee ee 1 2 Figure 1 3 CM4 Block ET e RE 1 4 Figure 2 1 Power regulation recommendations esse eee 2 2 Figure 3 1 Connector locations convection cooling version 3 2 Figure 3 2 Front panel convection cooled confeuratpon 3 2 Piette 5 5 JTAGICOP DORE HLT 3 7 Figure 3 4 Memory X bus network 3 9 Foue o Sena eiu dee Ee 3 13 Figure 3 6 Digital I O circuit digital port OU 3 15 A EIERE 3 16 Figure 3 8 PCI 6254 PCI Bridge in transparent and non transparent mode
17. BS Technologies 3 25 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com s BS Board Description Processor PPC 755 PPC 7410 Decoder CPLD INTA 82559ER Ethernet INTB A PMC_7101 _INTA Figure 3 16 CPU interrupt circuitry CPU_INT 3 16 Clock Circuitry The CM4 clock circuitry begins with one oscillator 14 318MHz input to the ICS9159C 02 clock generator The ICS9159C 02 clock generator uses the 14 318MHz clock as the main reference clock to generate three clock outputs 33MHz 24MHz and 14 318MHz as shown in Figure 3 17 on page 3 27 3 16 1 24MHz and 14 318MHz Clocks The ICS9159C 02 clock generator supplies a 24MHz clock to the two ST16C2550 Dual UART serial transceivers for the programmable baud rate generators The 14 318MHz clock provides timing to the Decoder CPLD 3 16 2 Real Time Clock The DS1685 Real Time Clock RTC requires and external oscillator to maintain time of day clock and memory status This is provided with a 32 768KHz oscillator 3 26 CM4 User s Guide SBS Technologies Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com s BS Board Description XSU9159 Clock 14 318MHz 14 318MHz Generator CLK33MHz Oscillator ST16C2550 CLK24MHz UART ST16C2550 UART 32 768KHZ XTAL DS1685 Real Time LJ Clock Decoder CPLD CLK14 318MHz Figur
18. CI reset when CM4 is a peripheral card 3 14 4 Watchdog Timer The Decoder CPLD includes an integrated watchdog timer that can reset the processor if develop ment application software forces the processor into an unstable condition After power up or reset the watchdog timer is disabled A write to the Watchdog Control Register WD ON bit b0 see Watchdog Control Register on page 5 1 enables the watchdog timer After the watchdog timer is enabled it counts down duration of the count is 0 5 seconds To reset the watchdog timer the application software must read the Watchdog Control Register before the count expires If the watchdog timer count expires it sends a hard reset signal WD_RESET to the LTCI727 Power Monitor which then asserts BOARD_RST as shown in Figure 3 10 on page 3 19 The application software can determine if a reset was triggered by the watchdog timer or some other cause by reading the Watchdog Control Register CM4 User s Guide SBS Technologies 3 21 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com s BS Board Description 3 15 Interrupt Circuitry The CM4 processor services interrupts generated from several on board devices as well as exter nal interrupts from an installed PMC module or from the CompactPCI backplane when the CM4 is installed in a system slot The Ts1107 Host Bridge includes an Embedded Programmable Inter rupt Controller EPIC that
19. Flash NVSRAM Tsi107 Host Bridge ST16C2550 UART Serial UO StrataFlash 4 pcs ST16C2550 UART Serial UO pa CPCI_P7201 i CPCI P7202 SY 82559ER Ethernet PCI 6254 PCI Bridge PMC Site Figure 1 3 CM4 Block diagram NOTE The Memory X bus represents a network of buses shown in greater detail in Mem ory X bus on page 3 8 1 4 CM4 User s Guide SBS Technologies Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com SBS Introduction 1 4 Technical Support Most issues can be resolved by referring to this manual If any problems cannot be resolved please contact SBS Technical Support by e E mail support sbc sbs com e Telephone 919 851 1101 ask for technical support e Fax 919 851 2844 For more information refer to Customer Service on page 6 2 1 5 Related Documents For more information on CM4 components refer to the following documents Components e MPC755 RISC Processor Hardware Specification Motorola Inc MPC750EC D Rev 6 September 2002 e MPC7410 RISC Microprocessor Hardware Specification Motorola Inc MPC7410EC D Rev 0 3 April 2001 e MPCIO7 PCI Bridge Memory Controller Users Manual Motorola Inc MPC107UM D Rev 0 November 2000 e Tsi107 PowerPC Host Bridge User s Manual Tundra Semiconductor Corpora tion 80C2000_MA001_03 Jan
20. Non Maskable Interrupt provides the status of the ef NMI signal 0 NMI disabled 1 NMI enabled 2to0 T_SEL b000 Time Select sets the interval for the MCP timer 000 timer disabled 100 2 34ms 001 0 29ms 101 4 67ms 010 0 58ms 110 9 34ms 011 1 17ms 111 18 69ms 5 3 MCP Ticker Reset Register The MCP Reset register is an a 8 bit write only register that when written to resets the NMI input to the MCP107 Host Bridge The data written can be any value Address offset OxFFOO 8002 Access Write only 5 2 CM4 User s Guide SBS Technologies Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com SBS CPLD Registers 5 4 Interrupt Status Register The Interrupt Status register is an 8 bit read only register that provides status indications for inter rupt signals from various CM4 components Address offset OxFFOO_8010 Access Read only Digital I O Interrupt U interrupt de asserted 1 interrupt asserted ENUM Interrupt U interrupt de asserted 1 interrupt asserted 3 3V Interrupt U interrupt de asserted 1 interrupt asserted Real Time Clock Interrupt U interrupt de asserted 1 interrupt asserted SER_INT4 Serial port COM4 Interrupt U interrupt de asserted 1 interrupt asserted SER INT3 Serial port COM3 Interrupt U interrupt de asserted 1 interrupt asserted Serial port COM2 Interrupt U interrupt de asserted 1 interru
21. Slide the CM4 into the slot guide applying even pressure to the front panel and lower ejector handle Be careful not to bend connector pins 5 Push up on the lower extraction handle to seat the CompactPCI connectors in the back plane connectors The red tab on the extraction handle should click when the board is locked into the chassis 6 Tighten the large screw on the front panel then tighten the smaller screw embedded in the extraction handle to secure the CM4 to the chassis Conduction cooled Configuration 7 Slide the CM4 into the slot guide applying even pressure to the upper and lower extrac tion levers Be careful not to bend connector pins 8 Use a 3 32 inch hex torque driver to tighten the top and bottom hex screws to 117 inch ounces 0 8 newton meters All Configurations 9 When the CM4 has been installed in the chassis install a serial cable from the host com puter to the CM4 through either the optional CM4 Transition Module or other serial port connected to the backplane 10 Install a Ethernet cable from the host computer or network connection to the CM4 through either the optional CM4 Transition Module or other Ethernet port connected to the back plane 11 Apply power to the chassis NOTE CM4 can be installed in a system controller or peripheral slot If the CM4 is not installed in a system slot a system controller card must be installed in the system slot to supply a PCI ref erence clock to CM4 CM4 U
22. Standards Department P1386 Rev 1 0 PICMG Specifications are available to PICMG members only SBS Technologies is not authorized to dis tribute copies of these specifications More information can be found at http www picmg org 2 Data sheets from hardware components can be downloaded from individual vendors web sites CM4 User s Guide SBS Technologies Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com SBS Technologies Chapter 2 Getting Started 2 1 What is included The CM4 is shipped with the following items e CM4 SBC printed circuit board 2 2 Equipment Needed The following items are needed to install and operate the CM4 e Host computer with terminal console program e CompactPCI compatible chassis with system controller card installed e CM4 Transition Module optional recommended for convection cooled applica tions e Ethernet cable e 1 1 Serial cable Caution Always use proper Electrostatic Discharge ESD protection when han dling printed circuit boards to avoid seriously damaging components Product han dlers must always be properly grounded CM4 User s Guide SBS Technologies 2 1 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com s BS Getting Started 2 3 Power The CM4 is designed for 3 3V operation but will tolerate 5 V The MIC2903 DC DC Converter taps the 3 3V rail to pro
23. TC is capable of 5V or 3 3V operation A 32 768KHz crystal oscillator provides timing to maintain the time of day clock and memory status when the CM4 is powered off SBS Technologies offers a CM4 Transition Module that provides connection to the BATT line through the Miscellaneous connector a 26 pin surface mounted connector 4 6 CM4 User s Guide SBS Technologies Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com SBS Technologies Components Table 4 2 Real Time Clock time calendar and alarm data modes aes punton 1 DI Hande Seconds Alarm 0 to 59 Minutes Alarm 0 to 59 Hours 24 hour mode 0 to 23 Hours Alarm 24 hour mode Alarm 24 hour mode 0 to 23 Data Mode Range 00 to 3B 00 to 59 00 to 3B 00 to 59 00to17 00 to 23 00 to 17 to 17 00 to 22 to 23 ae ose of Month ien 31 01to1F 0 aE W mon to 31 Pata Alarm haan 01to1iF t3 CM4 User s Guide SBS Technologies Artisan Technology Group Quality Instrumentation Guaranteed 888 4 7 88 SOURCE www artisantg com SBS gt s j tf J efa real t IELI iio UU Fr Te d ee Lr Chapter 5 CPLD Registers 5 1 Watchdog Control Register The CPLD includes watchdog timer circuitry that can reset the processor 1f development applica tion software forces the hardware into an unstable state The Watchdog Control register is an 8 bit read write register that
24. TEN Register DOUTENO 0x8061 Write A DINQ Register 0x8062 Read Figure 3 6 Digital I O circuit digital port 0 CM4 User s Guide SBS Technologies 3 15 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com s BS Board Description 3 12 Ethernet I O Communications The CM4 includes a 82559ER Fast Ethernet Controller that provides either IOBase T or 100Base TX Ethernet through the CompactPCI backplane The 82559ER Controller includes both a Media Access Controller MAC and a physical layer PHY that interfaces with the Ethernet transformer The 82559ER can operate in either full duplex or half duplex mode The 82559ER Controller is a PCI peripheral that includes a PCI interface It also includes a 4 bit EEPROM interface The serial EEPROM contains power on initialization as well as configura tion information The 82559ER chip auto negotiates for the fastest possible connection 82559ER Ethernet Ethernet Transformer Controller Transmit Serial EEPROM EESK EECS EEDI EEDO Figure 3 7 Ethernet circuitry 3 13 System Controller vs Peripheral Operation It is important to be aware as it relates to the following sections that the PCI 6254 handles reset and interrupt signals differently when the CM4 is installed in a system slot than when the CM4 is installed in a peripheral slot as shown in Figure 3 8 on page 3 17 When the CM4 is functioning as a system contr
25. Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com s BS Board Description 3 9 PCI IDSEL Each PCI device requires a unique PCI address connected to the IDSEL line Table 3 11 lists the IDSEL for each PCI device and address for the associated configuration registers Table 3 11 PCI IDSEL configuration registers PCI Config Register Device AD12 0x8000_60nn PCI 6254 PCI bridge AD13 0x8000_68nn 82599ER Ethernet controller AD14 0x8000_70nn PMC slot nn represents the address of the configuration register 3 10 Serial l O Communications The CM4 includes four asynchronous serial ports two RS 232 and two RS 422 485 imple mented in two dual ST16C2550 UARTS The UARTS are fully NS16450 and NS16550 compati ble Each UART includes a separate interrupt and a programmable baud generator capable of 50 1 5M baud Each UART communicates with the Tsil07 Host Bridge through the X bus Each UART channel is memory mapped to locations listed in Table 3 12 Figure 3 5 on page 3 13 shows the serial communications circuitry Table 3 12 Serial port addresses COM1 OxFFOO 8020 to OxFFOO 8027 COM2 0xFF00 8028 to OXFFOO 802F COM3 0xFF00 8030 to 0xFF00 8037 COM4 0xFF00 8038 to OXFFOO 803F NOTE The COM3 and COM4 TXD and RTS drivers are disabled after bootup These drivers can be enabled through the Data Terminal Ready DTR output of the COM3 and COM4 controllers 3 12 CM4 User s Gui
26. X Bus The 8 bit X bus connects the Decoder CPLD NVSRAM Boot flash RTC or two UART Trans ceivers to Tsil07PCI Bridge through a 16 bit bus switch The 16 bit bus switch changes the direc tion of data flow between read and write cycles 3 8 CM4 User s Guide SBS Technologies Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com s BS Board Description SDRAM f l j Extended Flash 1 im Flash 2 Extended i Extended Flash Extended S md y ECC L gt 16 bit bus 16 bit bus transceivers transceivers Gam Figure 3 4 Memory X bus network CM4 User s Guide SBS Technologies 3 9 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com s BS Board Description 3 Memory Map The Ts1107 Host Bridge supports two memory maps Memory Map A and Memory Map B Mem ory Map A conforms to the now obsolete PowerPC Reference Platform PReP specification Memory Map B conforms to the PowerPC microprocessor Common Hardware Reference Plat form CHRP specification At power up or reset CM4 selects Memory Map B as default The memory map can be viewed from two perspectives e Processor view e PCI bus master view Table 3 7 lists the memory map as seen from the processor point of view Table 3 8 lists the mem ory map as seen from the PCI bus master point of view Table 3 7 Ts1107 memory
27. at when enabled contains the digital output values to be sent to the cPCI bus Address offset OxFFOO 8060 Access Write only EON po 1 een sipion 6 oouvre gn s peoos w pedom o 2 pi_our2 wo bebww SSS I mem Mon o o peovro N Digital Op 777 CM4 User s Guide SBS Technologies 5 7 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com SBS CPLD Registers 5 9 2 DOUTEN Register The DOUTEN register is an 8 bit write only register that enables buffers for the digital output lines to the cPCI bus Address offset OxFFOO 8061 Access Write only ER RSVD o kem le OO reads 0 UN DIG OUTEN 6 NN Digital Output Enable 3 enables output buffer for port 6 Swi to 4 RSVD 00000 INA N A Reserved always reads 0 q q 3 j reads Reserved always reads 0 1 1 14 b mund DIG OUTEN 3 NN Digital Output Enable 3 enables output buffer for port 3 DIG_OUTEN_2 Digital Output Enable 2 enables output buffer for port 2 l DIG OUTEN 1 Digital Output Enable 1 enables output buffer for port l NUN DIG OUTEN 0 gt Digital Output Enable 0 enables output buffer for port U 5 9 3 DINQ Register The DINQ register is an 8 bit read only register that contains the input values sampled from the cPCI bus Address offset OxFFOO_8062 Access Read only Bis Field RIE ICO NA Dese 6 meine wo Daum OOOO a pomos w Donen mem wo Do O 1
28. board system memory of 128MB to 512MB Error Checking and Correction ECC is also included It also accesses four 64Mb StrataFlash devices for a total on board flash memory of 64MB The memory bus also connects with the X bus to access the SMB StrataFlash boot flash 32KB NVSRAM Real Time Clock and Decoder CPLD The Ts1107 Host Bridge also provides a 32 bit PCI bus interface that connects with the 10 100Mbps 82559ER Ethernet Controller PCI 6254 PCI Bridge and a single PMC site The 82559ER Ethernet Controller with integrated Medial Access Control MAC and physical layer PHY provides a 10Base T and 100Base TX network communications interface through the cPCI P7202 P2 connector to the backplane or an optional CM4 Transition Module TM which provides either a RJ 45 connector mounted on a rear panel or a surface mounted connector The CM4 includes two ST16C2550 Dual Channel UART Transceivers that provide two RS 232 serial ports and two RS 422 485 serial ports All four channels operate in full duplex mode and include 16 bytes of FIFO transmit and 16 bytes of FIFO receive memory In addition to serial and Ethernet I O the CM4 offers four programmable digital I O channels that can be used for manufacturing process control lines The PCI 6254 PCI Bridge connects the PCI bus bus 0 to the cPCI backplane bus1 Because the CM4 can function as a system controller or a peripheral card the PCI 6254 PCI Bridge formerly CM4 User s Guide SBS T
29. boot flash consists of one 8M x 8 E28F640J3A 120 StrataFlash device It is located on the 8 bit X bus and is memory mapped to a fixed address range from OxFF80_0000 to OxFFFF_FFFF in the Ts1107 Host Bridge The CM4 is shipped with a boot loader pre installed in boot flash SBS Technologies offers a CM4 Board Support Package BSP which includes a boot image for the CM4 To implement a custom boot image an external boot jumper not included on CM4 installed on the BOOTSEL pin can redirect the boot process to a different location in boot flash The BOOTSEL signal is available on the P7202 D4 The boot flash programming is disabled after CM4 power up however 1t can be enabled by writ ing a 1 to the VPEN BOOT bit b0 in the Status Output Port register see Status Output Port Register on page 5 6 4 6 2 Extended Flash The CM4 extended flash consists of one bank of four 64Mb RC28F640J3A 120 StrataFlash devices for a total of 64MB on board extended flash memory The extended flash is located on the memory bus and is memory mapped from 0x7C00_0000 to Ox 7FFF_FFFF in the Ts1107 Host Bridge The extended flash programming is disabled after CM4 power up however it can be enabled by writing a 1 to the VPEN FLASH bit b1 in the Status Output Port register see Status Output Port Register on page 5 6 4 4 CM4 User s Guide SBS Technologies Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www art
30. ces the processor and the PCI bus Memory transactions are routed through the 100MHz 64 bit memory interface and memory buses The memory data bus is separated into two 32 bit buses Data high and data low see Memory X bus on page 3 8 The high and low memory buses also access the 64Mb extended flash devices One 8 bit data bus taps the high data bus and connects to the X bus through a 16 bit bus trans ceiver The X bus carries data to and from the Decoder CPLD NVSRAM Boot flash RTC and two serial ST16C2550 UART Transceivers 4 3 3 PCI Bus Interface The 32 bit 33MHz PCI bus interface connects the Ts1107 with the 82559ER Ethernet Controller and PCI 6254 PCI Bridge which connects the Ts1107 to the PCI backplane through P7201 and P7202 It also connects to an installed PMC module through connectors P7101 and P7102 4 3 4 Interrupt Controller The Ts1107 includes an Embedded Programmable Interrupt Controller EPIC that integrates five hardwire interrupt lines The CM4 uses these interrupt lines to implement four PCI interrupts INTA INTBA INTCH and INTD and one combined interrupt S YSIRQ from the on board devices The four PCI interrupts are input lines when the CM4 is functioning as a system control ler When the CM4 is a peripheral card three of the PCI interrupts INTBA INTC and INTD are disabled and the INTA becomes an output to the cPCI backplane through the Decoder CPLD CM4 User s Guide SBS Technologies 4 3
31. configuration registers sees eee eee eee 3 12 EE Serial en de 3 12 Table 3 13 Rotated PMC interrupt connections sese eee eee 3 22 Table 3 14 Processor system clock 3 27 Table 4 1 Processor Ee 4 2 Table 4 2 Real Time Clock time calendar and alarm data modes 4 7 SBS Technologies List of Tables Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Chapter 1 Introduction 1 1 Overview The CM4 is a 3U CompactPCI Single Board Computer SBC designed for network switching routing and front end processing applications It is available with multiple processor options and offers the flexibility of functioning as a system controller or peripheral card The CM4 is available in configurations for convection cooled or conduction cooled environments The CM4 offers two PowerPC Reduced Instruction Set Computer RISC processor options e MPC755 400MHz e MPC7410 S00MHz Each processor includes 32KB LI instruction and 32KB Llidata caches The MPC755 comes with IMB of backside L2 cache the MPC7410 processor comes with 2MB of backside L2 cache The CM4 implements the Ts1107 Host Bridge replacing the MPC107 PCI Bridge chip that includes a 64 bit 1OOMHz system bus interface a memory controller with a 64 bit 100MHz mem ory interface and a 32 bit 33MHz PCI interface The memory interface accesses up to four 16M x 16 SDRAM chips for a total on
32. de SBS Technologies Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Ss BS Board Description Technologies UART P7202 TXD1 ls _TXD COM1 MAX232A S1 RXD X bus mu S2_ TXD RA bus COM2 RxD tt RXD MAX UART TXD3 EE TXD X bus COM3 So TXD 53 RXD RXD A S3 RXD RA bus COM4 sa TXD S4_RXD S4_RXD p DTR4 RTS4 Figure 3 5 Serial port circuitry CM4 User s Guide SBS Technologies Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com s BS Board Description 3 11 Digital UO Communications The CM4 provides five digital control I O ports for users to control external process functions A set of CPLD registers enables the software applications to separately control the direction and usage of each port Figure 3 6 on page 3 15 shows the circuitry for digital I O port 0 Each regis ter uses five bits 6 3 0 one for each port see Digital I O Registers on page 5 7 The CPLD s DOUTEN register provides five bits to control whether each port is an input or an output The reset value for this register sets all ports to be inputs Input ports are readable and have edge detection circuitry that drives a maskable interrupt function A port set to be an output is still readable but its edge detection circuitry is disabled The level on output ports is directly
33. e 3 17 Primary clock circuitry 3 16 3 Tsi107 Clock Distribution The 33MHz output from the clock generator provides Table 3 14 Processor system clocks clocks to most of the other major CM4 components through the Ts1107 Host Bridge The Ts1107 supplies a 100MH7 system clock to the processor CPU CLK and SDRAM The processor uses the reference clock com bined with the Phase Locked Loop PLL configuration settings to determine the processor clock The processor clocks are listed in Table 3 14 The pro cessor provides timing for on board L2 cache The L2 cache runs at 200MHz for all processors The Ts1107 distributes the 33MHz clocks through a PCI clock fanout buffer The CPU and SDRAM clocks go through a Delay Locked Loop DLL buffer to minimize trace delay effects The 33MHz clocks are output to the following CM4 devices as shown in Figure 3 18 on page 3 28 e PCI 6254 PCI bridge e 82559ER Ethernet controller e PMC module through P7101connector CM4 User s Guide SBS Technologies 3 27 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com XSU9159 Clock Generator CLK33MHz Board Description Processor 100MHz CPU_CLK A PPC 7410 L2 Cache 200MHz L2 Cache PCI 6254 PCI 33MHz Pork pol Bridge 82559ER Ethernet 33MHz PCLK ETH PMC_P7101 33MHz PCLK_PMC IS SDRAM 16M x 8 Up to 4pcs 100MHz sp cum a TVB 19 4pcs Figure 3 18 PCI clock circui
34. e Memory controller with 64 bit IOOMHZ memory interface e 2DMA controllers Memory e 72 bit wECC 100MHz SDRAM 128 512MB supported e 64 bit 64MB flash memory e bit SMB boot flash e 32kB non volatile SRAM automatic data transfer to and from EEPROM Communications e Serial ports asynchronous full duplex 16550 compatible UARTs 2 RS 232 ports 2 RS 422 485 ports e Fast Ethernet 82559ER IOBase T 100Base TX Auto negotiation e Digital I O 4 register controlled ports CM4 User s Guide SBS Technologies Artisan Technology Group Quality Instrumentation Introduction Power Requirements e 4 3 3V e 5V e 12V for installed PMC only Software e BSP with VxWorks O S Environmental Requirements e Operating temperature Standard 0 to 70 C Extended 40 to 85 C e Storage temperature Standard 40 to 85 C Extended 55 to 105 C e Humidity 5 95 40 C e Altitude Operating 15 000 tt 4 5Km Storage 40 000 ft 12Km e Shock C style 128 6ms R style 20g 6ms N style 100g 6ms e Vibration C style 2g rms 5 to 100Hz R style 2g rms 5 to 2KHz N style 14g rms 5 to 2KHz N style 30 min utes each axis All values under typical conditions w o PMC module installed Warranty e Two year warranty Guaranteed 888 88 SOURCE www artisantg com SBS Introduction 1 3 Block Diagram Processor L2 PPC 755 Cache PPC 7410 JTAG COP P1100 SDRAM Decoder Boot STK14C88 4 pcs CPLD
35. e PCI resets When the CM4 is installed in anon system controller slot it can receive a PCI reset from the system controller but cannot send PCI resets out to the system This dual mode capability is made possible through the trans parent non transparent modes of the PCI 6254 PCI Bridge as previously discussed see System Controller vs Peripheral Operation on page 3 16 and the SYSEN signal which is asserted when the CM4 is installed in a system slot CM4 is a System Controller When the CM4 is functioning as a system controller and it receives a hard reset the Decoder CPLD asserts the 107 HRESETY signal to reset the Ts1107 Host Bridge and processor see Fig ure 3 10 on page 3 19 The Decoder CPLD also asserts the PCI reset output which resets the fol lowing PCI devices on the CM4 e PCI 6254 PCI Bridge primary interface e 2559ER Ethernet Controller e StrataFlash boot flash e Two ST16C2550 UART Transceivers e PMC site When the CM4 is the system controller the PCI 6254 PCI Bridge operates in transparent mode In transparent mode the PCI 6254 receives the PCI reset signal on the primary PCI interface reset input P_RSTIN input When P_RSTIN is asserted in transparent mode the secondary PCI interface reset output S_RSTOUT is asserted The S_RSTOUT line goes back to the Decoder CPLD where the asserted SYSEN signal enables an output buffer that drives the reset onto the cPCI backplane as shown in Figure 3 11 on page 3 21
36. e the defective item at its factory under the terms of this watranty subject to the provisions and specific exclusions listed herein SBS does not assume any liability for consequential damages as a result of the use of its products Under no circumstances shall the liability of SBS exceed the original selling price of the equip ment The equipment warranty shall constitute the sole and exclusive remedy of any buyer of SBS equipment and the sole and exclusive liability of SBS its affiliates successors or assigns in con nection with equipment purchased and in lieu of all other warranties expressed implied or statu tory including but not limited to any implied warranty of merchant ability or fitness for a particular purpose and all other obligations or liabilities of SBS its affiliates successors or assigns The equipment must be returned securely packaged in anti static bags and labeled with a Return Material Authorization RMA number written on the outside of the package The package must be insured and the shipping cost must be paid SBS will repair or replace failed parts within the limits of the warranty statement referenced above and return the item at no charge Standard 6 2 CM4 User s Guide SBS Technologies Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com SBS Customer Service repair charges may apply if there is a lack of proof of the date of purchase modificatio
37. echnologies 1 1 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com SBS Introduction Technologies HB6 must change how it handles data and PCI signals according to the mode in which the CM4 is operating When the CM4 is a system controller the PCI 6254 is in transparent mode which means the PCI host the Ts1107 Host Bridge looks through the PCI 6254 to the backplane to the PCI devices on other peripheral cards throughout the system When the CM4 is a peripheral card the PCI 6254 PCI Bridge is in non transparent mode which means that it sees the Ts1107 Host Bridge as PCI device but cannot look past it to the backplane This affects how the PCI 6254 handles interrupts and reset signals The CM4 incorporates additional flexibility with a PMC site for adding additional I O capability with over 30 user defined I O lines The CM4 offers configurations for either convection cooled or conduction cooled environment Figure 1 2 Conduction cooled configuration 1 2 CM4 User s Guide SBS Technologies Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com SBS 1 2 Specification Processor e MPC755 400MHz e MPC7410 SOOMHz e On chip L1 cache 32KB instruction 32KB data all processors L2 Cache e MPC755 1MB e MPC7410 2MB Tsi107 Host Bridge e 64 bit 100MH7 system bus interface e 32 bit 33MHz PCI bus interface
38. echnology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com s BS Board Description 3 6 Memory X bus The Memory X bus shown in the block diagram see Figure 1 3 on page 1 4 represents a net work of memory data address and parity buses and an X bus as shown in Figure 3 4 on page 3 9 Memory Data Buses The MCP107 Host Bridge provides a memory controller with a 64 bit memory data bus inter face The memory data interface is divided into two 32 bit sections high data and low data The 32 bit high data bus transports data to and from two 16 bit SDRAM chips and two 16 bit extended flash memory chips The 32 bit low data bus transports data to and from the remaining two 16 bit SDRAM chips and 16 bit extended flash memory chips The high data bus also provides an 8 bit data bus that connects to the X bus through a 16 bit bus transcelver Address Bus The 14 bit address bus provides addressing for the SDRAM and ECC devices It also sends addressing information to a 16 bit bus transceiver which sends the addressing information to the RA bus Parity Bus The 8 bit parity bus transports parity bits between the Ts1107 Host Bridge and the SDRAM Error Checking and Correction ECC device It also connects to the RA bus RA Bus The 24 bit RA bus carries address and parity information from two 16 bit bus transceivers to the four extended flash devices Decoder CPLD NVSRAM Boot flash and two UART Transceivers
39. eee 5 5 Status Output port eee eee 5 6 watchdog control 5 1 Customer SCEVICO geen 6 2 D Decoder CPLD EE 4 5 Dial rro as 3 14 E Ethernet controller 4 5 A OT 8 sesrosisresereercnnenn 3 16 CM4 User s Guide SBS Technologies Index E Flash Memory A eTo dese 4 4 Front panel ME 3 2 Installation sss sese eee 2 3 Interrupt circuitry esse ee ee eee eee 3 22 M Memory MAD arras 3 10 MORON AA 3 8 N NN SEAM AP 4 6 P PCTOZ54 PCI Ads screeningen 4 4 PCI arbitration esse eee eee 3 11 POD T E 3 12 Physical description sss sese eee 3 1 Ss a rats edson 3 1 Sae asociada 4 2 Product specification eee eee 1 3 R Real Time Clock sese 4 6 Related Documents sese 1 5 RESPECICUMIS saboti rica 3 17 Return Material Authorization 6 3 S SDRAM sacra ceda iio 4 4 DONATO eege 3 12 Index 1 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com T U Technical Support esse eee eee eee 1 5 UT KE 4 5 Ts1107 Host Bridge s 4 3 W A A E N 6 2 Index 2 CM4 User s Guide SBS Technologies Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com S I DDR E Technologies 7401 Snaproll Albuquerque NM 87109 4358 Tel 505 875 0600 Fax 505 478 1400 Email info Osbs com www sbs com Document No 70000340 300 and 70000345
40. erted 1 interrupt asserted CM4 User s Guide SBS Technologies 5 9 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com SBS CPLD Registers 5 11 DI O Interrupt Mask Register The DI O Interrupt Mask register is an 8 bit read write register that provides the capability of masking the digital I O interrupts Setting a bit 1 allows the corresponding signal to assert the interrupt Address offset OxFFOO 8013 Access Read write et Feld bea seen TT a RSVD Reserved always reads as 0 DI O6_INT_MSK Digital UO o Interrupt Mask U disable mask 1 enable mask RSVD Reserved always reads as 0 DI O3_INT_MSK Digital I O 3 Interrupt Mask U disable mask 1 enable mask DI O1_INT_MSK Digital I O 1 Interrupt Mask U disable mask 1 enable mask DI OO_INT_MSK Digital I O_0 Interrupt Mask U disable mask 1 enable mask DI O2_INT_MSK Digital I O 2 Interrupt Mask U disable mask 1 enable mask 5 10 CM4 User s Guide SBS Technologies Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com SBS 1 J E 7 Fy tales R ER ETC J G A i i li I i f j i J Te se Ke K P A F NA ku J Lr Chapter 6 Customer Service 6 1 Introduction This chapter provides forms and information for requesting product service or repair The follow ing information is included e Contact information for
41. esses written in hexadecimal are designated with the prefix Ox e g 0xF000 0000 CM4 User s Guide SBS Technologies ii Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com SBS Technologies Table of Contents Chapter 1 Introduction LE e E 1 1 UE EE Te e E 1 3 Lo POR RE AAA TTT 1 4 L Ke Te AN SO AA e Pe ei RECO TA 1 5 L gt C2 Giro RR ENT sesensremin n A EET EEEE E 1 5 Chapter 2 Getting Started Sech AE EA H 2 1 Dek Sie TT ees E 2 1 e PON EE 2 2 2A ra E E ere 2 3 gt A ere ALDER ED O TT 3 1 VAN ra oca etica 3 1 Oe COMME CIOL SOC ANONS inserta Doe 3 2 S EE er IT 3 2 3 5 1 CompactPCI Connectors esse eee eee eee 3 3 oJ PMO Core ARS cenansesetevedananovansvibeoisnantsasceseteamdsnabonounobenasweesaaeastuecsnante canes 3 5 JAG JAG COP Pot P LOO dee 3 7 Oe Enter E E 3 8 SE A 3 10 EN MOD Te T 3 11 So PCL ye ea TTT 3 11 2 GUI T een err ES E A E A N AEA 3 12 3 10 Serial I O Communications sss sssssccssssscssssscsssssscsssssesssssessassscssssssos 3 12 Disital VO Communications usina 3 14 CM4 User s Guide SBS Technologies iii Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com SBS 312 3 13 3 14 3 16 Ethernet VO Communications spun srn dE 3 16 System Controller vs Peripheral Operation 3 16 Reset EE 01 EE 3 17 Sole siro EE get 3 17 AZ DOM ss ss i E ES ida 3
42. gure 3 13 Interrupt circuitry CM4 User s Guide SBS Technologies Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 3 23 3 24 Board Description Decoder CPLD C_INTA CM4 is system controller C_INTA INTA C_INTB INTB C_INTC INTC C_INTD INTD SYSEN P6254 PINTAR P6254 SINTA Figure 3 14 Decoder CPLD PCI interrupt circuitry CM4 User s Guide SBS Technologies Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com s BS Board Description 3 15 2 On board Interrupts The CM4 employs the Decoder CPLD to combine the interrupts from several on board devices into one interrupt signal S YSIRQ as shown in Figure 3 13 on page 3 23 The Decoder CPLD receives inputs from the following on board devices e Two Dual ST16C2550 UART serial transceivers e Real Time Clock e LTC 1727 power monitor e PCI 6254 PCI Bridge The Decoder CPLD provides the capability of masking any of these device interrupts through the Interrupt Mask register as shown in Figure 3 15 Eege Interrupt Decoder N _X bus y Mask CPLD k i Register INT_SER1 INT_SER1 INT_SER2 INT_SER3 INT_SER4 INT_RTC INT3V S ENUM l l l El B 3 l l 1 8 Digital I O 6 fj Set register Digital I O Mask register W N E b E Figure 3 15 Decoder CPLD interrupt circuitry CM4 User s Guide S
43. ile element built into it In SRAM mode the NVSRAM operates as a fast static RAM device In non volatile mode data stored in static RAM is trans ferred to the non volatile elements or data stored in the non volatile elements is transferred to the static RAM A capacitor attached to the STK14C88 NVSRAM is charged to 5V This capacitor stores enough power to perform one store operation where data in the 32KB static RAM is transferred to the non volatile elements if supplied power suddenly fails When power is restored the device per forms a recall operation and the stored data in the non volatile elements is transferred back to the static RAM 4 11 DS1685 Real Time Clock The CM4 provides a 100 year calendar including a century register a data alarm register a timer with periodic interrupt and 242 bytes of user defined non volatile RAM The periodic interrupt is software controlled The DS1685 RTC is connected to the Ts1107 Host Bridge through the X bus and is memory mapped to the I O space at OxFFOO_0040 index register and OxFFOO_0041 data register Table 4 2 on page 4 7 provides the address offsets for internal time calendar and alarm data registers for the DS1685 RTC The CM4 does not provide battery backup for the DS1685 RTC so when the CM4 is not powered on the DS1685 RTC requires an external power source A power can be applied through the BATT line available on the cPCI backplane through cPCI connector P7202 The DS 1685 R
44. implied includ ing warranties of design merchantability and fitness for a particular purpose or arising from any course of dealing usage or trade practice The content of this manual is furnished for informational use only and is subject to change without notice Reverse engineering of any SBS product is strictly prohibited In no event will SBS be liable for any lost revenue or profits or other special indirect incidental and consequential damage even if SBS has been advised of the possibility of such damages as a result of the usage of this document and the product that this document describes SBS shall have no liability with respect to the infringement of copyrights trade secrets or any patents by this docu ment or any part thereof SBS and the SBS logo are trademarks of SBS Technologies Intel is a trademark of Intel Corporation IBM and PowerPC are trademarks of International Business Machines IBM CompactPCI is a trademark of the PCI Industrial Computer Manufacturers Group VxWorks is a trademark of WindRiver Systems Inc SBS Technologies 7401 Snaproll Albuquerque NM 87109 4358 Tel 505 875 0600 Fax 505 478 1400 Email info sbs com Document 70000340 800 Rev E and 70000345 800 Rev E Conventions The following conventions are used in this user s guide e Signal names are designated with all capital letters e g SYSEN e Signal names followed by the pound sign are active low e g SYSEN e Data addr
45. isantg com SBS Components 4 7 Decoder CPLD The XC95144XL Decoder CPLD located on the X bus provides the CM4 with discrete pro grammable logic and registers for the following CM4 circuity e Reset e Interrupt e Digital I O The Decoder also provides control status and masking registers as detailed in Chapter 5 CPLD Registers It also provides logic for many write protect enable and chip select functions as well as timer counters such as the watchdog timer and MCP counter 4 8 82559ER Ethernet Controller The CM4 provides LAN network communications through the 10 100 fast 82559ER Ethernet Controller The 82559ER controller provides IEEE 802 3 compatibility at both LOMb and 100Mb data rates and includes an integrated Physical Layer PHY unit with auto negotiation for full and half duplex at both 10 and 100Mbps data rates The 82559ER Controller includes Media Access Control MAC which includes a PCI interface with PCI reset A 1K B EEPROM attached to the 82559ER Controller provides configuration data storage The Ethernet signals are routed to the cPCI backplane through cPCI connector P7202 SBS Technologies offers a CM4 Transition Module that provides 10 100 Ethernet connection through either a rear panel RJ 45 connector or a surface mounted connector 4 9 ST16C2550 Dual Channel UARTs The CM4 includes two ST16C2550 Dual Channel UARTS for serial communications Each UART device consists of two NS16450 and NS16550 compliant UART T
46. map processor view E mee Coniqwaton Adress reise EEE 0000 REE Ferr Comiqwaton Dataregister NOTES 1 A PC compatibility gap exists from address 0x0000 A000 to OxOOOO_FFFF A config uration register can set this memory space to either to PCI memory or system memory Maximum memory space is 512MB Ox 1 FFF_FFFF 3 Maximum extended flash memory is 64MB from addresses 0x7C00_0000 to 7FFF_FFF Maximum extended flash is located from address 0x7C00 0000 to 0x77FFF_FFFE 5 Location of board specific I O devices SMB of ROM located from 0xFES0 0000 to Ox FFFF_FFFE 3 10 CM4 User s Guide SBS Technologies Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com s BS Board Description Table 3 8 Ts1107 memory map PCI bus master view sam agg 0xFDFF Fere PON memory space EE 0000 a e OxFF80_0000 to OxFFFF_FFFF Flash ROM space 3 7 1 UO Devices The Ts1107 Host Bridge provides memory mapping for the devices listed in Table 3 9 through the X bus Table 3 9 X bus I O address map bus VO Address Range naie 3 8 PCI Arbitration The Tsi107 provides bus arbitration for PCI devices on the PCI bus listed in Table 3 10 Table 3 10 PCI bus arbitration PCI Bus Request PCI Master CPU internal Tsi107 Host Bridge REQ GND 0 PCI 6254 PCI bridge REQ GND 1 82559ER Ethernet controller REQ GND 2 PMC site CM4 User s Guide SBS Technologies 3 11 Artisan
47. ng the accuracy and usability of product manuals This feedback should include Additional information that would be helpful to set up and operate the product Missing information Information that is incomplete inaccurate or misleading Information that is difficult to understand and needs further clarification Information that was beneficial or that made the manual easier to use Print the form below fill it out and fax it to SBS Technologies 919 851 2844 MALA Chapter 2 T Getting Started Chapter 4 Components Other Comments and Suggestions CM4 User s Guide SBS Technologies 6 5 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com SBS mm Ea ga S i E lechnologies B Block diagram sss ss sss 1 4 C Clock ra udo alear 3 26 CM4 overview eee 1 1 Component location sse eee ee eee 4 1 Conduction cooled config 1 2 Connector locations sse eee 3 2 Connectors compactPCI eee eecccececeseeseeeeeeeeees 3 3 JEAGICOP EEE 3 7 ER eege 3 5 Convection cooled config 1 2 CPLD register DIG e 5 2 CPLD registers digital VO 252 arrede ended 5 7 digital I O interrupt status 5 9 digital VO mask 5 10 interrupt mask cece e cece eee ee eee e eee 5 4 interrupt status esse eee eee 5 3 MPC ticker control 5 2 status input port esse eee eee
48. ns have been performed the unit has been operated outside its specifications and or if the warranty period has expired This description of SBS limited warranty is only a summary please review the terms of the prod uct warranty for specific coverage and exclusions 6 4 2 Non Warranty Terms and Conditions Payment for all out of warranty repairs must be prearranged through a purchase order or credit card information before a RMA number can be issued SBS Technologies charges a firm fixed price for repair of non warranty boards Third party products purchased through SBS and returned for repair will follow the warranty schedule for that manufacturer Non warranty repairs require a purchase order upon receipt of a repair quote and prior to any work being performed 6 5 Return Material Authorization RMA Important An RMA number must be issued before product can be returned To receive an RMA number 1 Contact the SBS Single Board Computer Technical Support through the RMA Coordinator Phone 919 851 1101 choose the Technical Support option then choose RMA option Fax 919 851 2844 Email rma sbc sbs com Please provide the following information Company name Contact person Telephone Email Name of product 2 The RMA Coordinator will contact you and issue an RMA number The following informa tion will be needed Name of product Serial number Purchase order number if out of warranty Description of problem Impo
49. nt mode In non transparent mode the PCI 6254 receives the PCI clock from the SCLKO input on the secondary PCI interface seven of the eight SCLK outputs are disabled and SCLKO becomes an input for the PCI clock from the backplane through CompactPCI connec tor P7201 In non transparent mode the secondary interface receives its timing from the SCLKO input and the secondary interface clock input S_CLK is ignored CM4 User s Guide SBS Technologies 3 29 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com A s na lo gies Board Description Tsi107 Host Bridge PCI 6254 PCI Bridge PCLK PCI POLK CPCI P7201 S CLK CPCI P7202 SYSEN Figure 3 19 cPCI clock circuitry CM4 User s Guide SBS Technologies Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com SBS Technologies Chapter 4 Components 4 1 Component Location II III II 111111 LL Figure 4 1 CM4 components front view EKE en en _ em en _ em _ em _ em en an en _ Ts1107 Host Bridge replacing the MPC107 PCI Bridge Two Dual NS16550 UARTs MPC755 or MPC7410 processor SMB Boot flash memory PCI 6254 PCI bridge Real Time Clock EN aS CM4 User s Guide SBS Technologies 4 1 Artisan Technology Group Quality Instrumentation Guara
50. nteed 888 88 SOURCE www artisantg com SBS Components Technologies Figure 4 2 CM4 components back side 1 L2 Cache 5 Decoder CPLD 2 NVSRAM 6 SDRAM 3 Extended StrataFlash memory 7 82559ER Ethernet controller 4 SDRAM ECC 8 Ethernet transformer 4 2 Processors The CM4 offers two processor options MPC755 and MPC7410 Table 4 1 compares the param eters of each of the processor options Table 4 1 Processor parameters Feature res MPC755 ASSA 0 4 2 CM4 User s Guide SBS Technologies Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com SBS Components 4 3 Tsi107 Host Bridge The CM4 features the Ts1107 Host Bridge device that provides the following functions e 100MH7 60x system bus interface s IOOMHZ memory interface e Memory controller e PCI bus interface e Interrupt controller e Two channel DMA controller NOTE The Motorola MPC107 PCI Bridge chip has been replaced by the Tundra Tsi107 Host Bridge chip 4 3 1 System Bus Interface The Ts1107 system bus interface include a 32 bit 100MHZz address bus and 64 bit data bus The system bus conforms to a subset of the 60x bus protocol that support the single beat and burst data transfers The address and data bus are decoupled to support pipelined transactions 4 3 2 Memory Controller and Bus Interface The Ts1107 memory controller handles memory transactions between the 16M x 16 SDRAM devi
51. oller the PCI 6254 PCI bridge is in transparent mode meaning it is effectively transparent to PCI reset signals sent from the Ts1107 Host Bridge out to the PCI backplane and interrupts received from the backplane to the Ts1107 When the CM4 is functioning as a peripheral the PCI 6254 PCI Bridge is in non transparent mode which means that it appears to the Ts1107 as a PCI device on the PCI bus The function of the MCP107 Host Bridge as PCI host does not change whether the CM4 is functioning as a sys tem controller or peripheral 3 16 CM4 User s Guide SBS Technologies Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com s BS Board Description CM4 as system controller Transparent Mode PCI 6254 cPCI Backplane PCI Bridge PCI interrupts PCI resets CM4 as peripheral Non transparent Mode PCI 6254 cPCI Backplane PCI Bridge PCI interrupts PCI resets Kiepuooas Figure 3 8 PCI 6254 PCI Bridge 1n transparent and non transparent mode 3 14 Reset Circuitry The CM4 reset circuitry consists of hard and soft resets Hard resets are asserted during power up or by a voltage drifting out of a specified range a manual reset or a PCI reset from the Compact PCI backplane discussed separately from hard resets Soft resets are triggered by application or test and evaluation software 3 14 1 Hard Resets The Decoder CPLD receives hard resets from the following source
52. on handle at the bottom of the front panel and two screws a large screw at the top and a smaller screw embedded in the extraction handle to secure the CM4 to the chassis The conduction cooled configuration of the CM4 has two extraction levers with no front panel see Figure 2 2 on page 2 4 Figure 3 2 Front panel convection cooled configuration 3 2 CM4 User s Guide SBS Technologies Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com SBS Board Description Technologies 3 5 Connectors 3 5 1 CompactPCI Connectors Caution The CM4 is not compatible with a 64 bit backplane Table 3 2 CompactPCI connector P7201 pin assignments RBE EE E EE SN E E ROSEN CN IA a saw fao aw CA rare s r Ja mo Sr hoe bao suo laso lao uw fern ose we IS DEVSEL RES S VI O IES STOP DGND J1 12 to 14 ivo isma faw feam feao oao sz Lia Jona loo sw eto sm E ze le Jes livo Je Mo mo ue le e de he ome CM4 User s Guide SBS Technologies 3 3 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com SBS Board Description Technologies Table 3 3 CompactPCI connector P7202 pin assignments Se ee a RECH E lae peon m Ex foo S2 TXD DI O 00 ES 17 E CTS S4 CTS DGND OIO 11 DI O 02 ES 20 ES TXD S4 RTS4 DGND mw Jeo eons lemon sano ovo en e eno
53. outputs for an optional external BITOK LED the Serial Presence Detect EEPROM and the write protection for boot and extended flash memory Address offset OxFFOO_8051 Access Read write TOM ET Renas 1 1 RSVD Reserved always reads as 0 3 BITOK BITOK Status LED drives an open drain output that can control an off board LED O LED is off 1 LED is on NOTE After reset the BITOK bit is cleared 0 WP_SPD SPD Serial EEPROM Write Protect U write protect enabled I write protect disabled NOTE After reset the WP_SPD bit is cleared 0 VPEN Extended Flash Write Protect U write protect enabled I write protect disabled NOTE After reset the VPEN_FLASH bit is cleared 0 7 VPEN BOOT Boot Flash Write Protect U write protect enabled 1 write protect disabled NOTE After reset the VPEN BOOT bit is cleared 0 5 8 CPLD Version Register The CPLD Version register is an 8 bit read only register that provides the CPLD version number Address offset OxFFOO_8053 Access Read only 5 6 CM4 User s Guide SBS Technologies Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com SBS CPLD Registers 5 9 Digital UO Registers The Digital I O interface consists of four registers that direct the flow of digital control signals Each digital I O register uses bits 4 0 and bit 6 5 9 1 DOUT Register The DOUT register is an 8 bit write only register th
54. pomora wo Don O o DIGANPUT 0 wo atan 7 777 7 5 8 CM4 User s Guide SBS Technologies Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com SBS CPLD Registers 5 10 DI O Interrupt Status Register The DI O Interrupt Status register is an 8 bit read write register that provides status indications for digital I O interrupts A bit set in this register indicates a transition edge was detected on the cor responding signal The DI O Interrupt Mask register see page 5 10 does not prevent bits from appearing to be set in this register Writing a 1 to a bit in this register clears the bit and the corre sponding interrupt NOTE Bits in this register may be set during board reset but they will not assert the interrupt since the reset will assert the associated mask bits Application software should clear the five dig ital I O interrupt bits before using this function after any reset Address offset OxFFOO 8012 Access Read write Defaut Description Reserved always reads as 0 Digital I O 6 Interrupt U interrupt de asserted 1 interrupt asserted Reserved always reads as 0 Digital I O 3 Interrupt U interrupt de asserted 1 interrupt asserted Digital I O 1 Interrupt U interrupt de asserted 1 interrupt asserted Digital I O 0 Interrupt U interrupt de asserted 1 interrupt asserted 2 Digital I O 2 Interrupt U interrupt de ass
55. provides five hardwire interrupt inputs The CM4 uses four of these interrupt inputs to implement external PCI interrupts from the PCI backplane CM4 functioning as a system controller or from an installed PMC module CM4 functioning either as system con troller or peripheral card The Ts1107 uses the fifth interrupt line for a combined interrupt from the on board devices 3 15 1 PCI Interrupts CM4 is a System Controller When the CM4 is functioning as a system controller the Ts1107 Host Bridge can receive up to four PCI interrupts C_INT A D from the CompactPCI backplane through cPCI connector P1701 In the Decoder CPLD these four interrupts are ANDed with the system enable signal SYSEN to enable open collector outputs INT A D to the Ts1107 EPIC unit as shown in Figure 3 14 on page 3 24 The SYSEN signal is asserted when the CM4 is installed in a system slot CM4 is a Peripheral Card When the CM4 is a peripheral card inputs C INT B D are disabled in the Decoder CPLD and input C_INTA becomes an output from the Decoder CPLD driven by the PCI 6254 PCI Bridge secondary PCI interface P6254_SINTA The INTA output from the Decoder CPLD to the Ts1107 EPIC unit is driven by the PCI 6254 primary interface interrupt signal P6254_PINTA The output is enabled by the de asserted SYSEN PMC PCI Interrupts If a PMC module is installed on the CM4 it can output four PCI interrupts to the Ts1107 Host Bridge through interrupt ou
56. pt asserted SER INTI Serial port COMI Interrupt U interrupt de asserted 1 interrupt asserted CM4 User s Guide SBS Technologies 5 3 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com SBS CPLD Registers 5 5 Interrupt Mask Register The Interrupt Mask register is an 8 bit read write registers that provides the capability of masking or inhibiting interrupt signals from various interrupt sources such as the two ST16C2550 Dual Channel UART Transceivers Real Time Clock and digital I O circuitry Address offset OxFFOO_8011 Access Read write an E DUO INT MSK MI WW INT3V MSK NOTE Writing a 0 to the INT3V_MSK bit also clears the corresponding interrupt if Digital I O Interrupt Mask U disable mask 1 enable mask ENUM Interrupt Mask U disable mask 1 enable mask 3 3V Interrupt Mask U disable mask 1 enable mask the 3 3V monitor circuit is no longer detecting an error RTC_INT_MSK SER INT4 MSK write only always reads 0 SER_INT3_MSK write only always reads 0 SER_INT2_MSK write only always reads 0 SER INT1 MSK write only always reads 0 5 4 Artisan Technology Group Quality Instrumentation Real Time Clock Interrupt Mask U disable mask 1 enable mask Serial port COM4 Interrupt Mask O disable mask 1 enable mask Serial port COM3 Interrupt Mask O disable mask 1 enable mask
57. ransceivers The CM4 implements these channels as two full duplex RS 232 transceivers and two RS 422 485 trans ceivers Each device includes 16 bytes of transmit FIFO memory and 16 bytes of receive FIFO memory which extends the overall service interval required by the processor Each UART chan nel includes a separate chip select and interrupt line NOTE With the external 24MHz clock each channel is capable of data rates up to 1 5Mbps however drivers provided by the optional CM4 BSP only support a maximum baud rate to 38400 Baud Each ST16C2550 UART device is connected to the Ts1107 Host Bridge through the X bus and is connected to the cPCI backplane through cPCI connector P7202 SBS Technologies offers a CM4 Transition Module that provides serial port COM1 connection through a rear panel DB9 connector or a surface mounted connector The remaining serial ports COM2 COM3 and COM4 are implemented in surface mounted connectors CM4 User s Guide SBS Technologies 4 5 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com SBS Components 4 10 STK14C88 NVSRAM The CM4 provides 32KB of non volatile static RAM with an AutoStore feature The STK14C88 NVSRAM is located on the X bus and is memory mapped from OxFF00_0000 to OxFFOO_7FFFF in the Ts1107 Host Bridge I O space The STK14C88 NVSRAM has two modes of operation SRAM mode and non volatile mode Each SRAM memory cell has a non volat
58. rtant The RMA Coordinator will determine if warranty applies CM4 User s Guide SBS Technologies 6 3 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com SBS Customer Service 3 When an RMA number is received attach the RMA number to the product and ship to SBS Technologies Attn insert RMA number here 6301 Chapel Hill Rd Raleigh N C 27607 5115 4 The product must be securely packaged in an anti static envelope and placed in a cush ioned corrugated carton use the original shipping carton if possible AN Caution Always use proper Electrostatic Discharge ESD protection when han dling printed circuit boards to avoid seriously damaging components Product han dlers must always be properly grounded 6 4 CM4 User s Guide SBS Technologies Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com SB s Customer Service Technologies 6 6 Documentation Feedback Form The object of a user s guides is to communicate technical information concerning the product s setup and operation from the people who designed the product to the people who will use the product In our continuous attempt to improve the usefulness of the manuals that accompany our products we provide this form to give customers and end users the opportunity to feedback com ments suggestions and constructive criticisms to SBS Technologies concerni
59. s e Power monitor reset BOARD_RST e Manual reset button RST_BUT e External emulator reset P1100 COP_HRST and COP_TRST Power Monitor Reset After power up or manual reset when the processor core voltages VCCP has been established to the processor the LM2636 Buck Controller de asserts the PWRGOODF signal to the LTCI727 Power Monitor The LM2636 asserts the PWRGOODFEF signal when the processor core voltage see Table 3 1 on page 3 1 goes outside a 10 window and de asserts it when the core voltage travels back into an 8 window for at least 10ms CM4 User s Guide SBS Technologies 3 17 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com s BS Board Description The LTCI727 Power Monitor tracks the 3 3V and 2 5V lines as well as the PWRGOOD sig nal If the 3 3V or 2 5V drift out of a 1 5 window for more than 50us or if PWRGOOD is asserted the LTCI727 asserts the BOARD_RST output to the Decoder CPLD and extended flash devices as shown in Figure 3 9 The watchdog timer output WD_RESET from the Decoder CPLD can also assert the PWRGOODF line LTC1727 Decoder 3 3V Power CPLD 2 5V Monitor PWRGOODA BOARD RSTA o LM2636 Buck PWRGOOD VID Controller Processor MPC755 MPC7410 BOARD_RSTH Figure 3 9 Power up reset circuitry Manual Reset Button The CM4 does not include a physical reset button however 1t provides for an external manual reset
60. ser s Guide SBS Technologies 2 3 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com SBS Getting Started Technologies 2 4 E 2 Figure 2 3 Convection cooled configuration Figure 2 2 Conduction cooled configuration CM4 User s Guide SBS Technologies Artisan Technology Group Quality Instrumentation Quaranteed 888 88 SOURCE www artisantg com SBS gt s j tf O Fu FR Fa l a a reci QIOG Fa Y d ze Chapter 3 Board Description 3 1 Physical Description Height 100mm 3 9 inches Length 160mm 6 3 inches Operating temperature 40 to 85 C ambient Storage temperature 40 to 85 C N style 55 C to 105 C Humidity 10 to 95 non condensing Cooling Forced air 200 LFM min Power 3 3 VDC 5 normal 1 3A 4 29W Power 5 VDC 5 normal 1 9A 9 5W Highest achievable operating temperature depends on processor type speed and ambient conditions card edge temperature Also all temperature values are typical conditions without PMC module installed 3 2 Power The CM4 inputs two voltage rails 5V and 3 3V see Cau tion on page 2 2 A linear regulator taps the 3 3V line and outputs a 2 5V line VI O is taken from either the 3 3V for Processor Core Voltage the MPC755 processors or 2 5V for the MPC7410 processor The LTC1727 power monitor tracks these voltages 3 3V
61. tputs INT A D regardless of whether CM4 is functioning as sys tem controller or peripheral card as shown in Figure 3 16 on page 3 26 The PMC PCI outputs are rotated so that PMC INTA is connected to PCI INTD from the Decoder CPLD as listed in Table 3 13 This is done to reduce interrupt PMC INTA having to share an interrupt with the busier PCI interrupt INTA Table 3 13 Rotated PMC interrupt connections PMC PCI Interrupts PCI Interrupts INTA INTDA INTBA INTA INTC INTC INTD INTC The 82559ER Ethernet controller can also output an interrupt connected to INTB to the Ts1107 Host Bridge The Ts1107 Host Bridge interrupt controller accepts interrupts on the four PCI inter rupt lines and asserts the CPU_INT lines as shown in Figure 3 16 on page 3 26 3 22 CM4 User s Guide SBS Technologies Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com s BS Board Description CPCI_7201 C INTAZ Decoder NTA elver Joo GELD ree oa en JI me o a enoe tI mno senum A wpe YE SYSEN S VI O CPCI 7201 WW SYSEN Bus Y PMC 7101 INTAS INTB PCI 6254 PCI P6254 PINTAZ Bridge 56254 SINTAZ 82559ER Ethernet ST16C2550 UART INT SER1 Decoder SES SYSIRQ ST16C2550 UART INT SER3 Serial UO INT SER4 Real Time Clock INT RICH LTC 1727 Power INT3V Monitor Fi
62. try CM4 User s Guide SBS Technologies Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com s BS Board Description 3 16 4 PCI 6254 PCI Bridge Clock Operation Transparent Mode When the CM4 is functioning as a system controller the CM4 is installed in a system slot and the SYSEN signal is asserted on the S_CLKOFF input the PCI 6254 PCI Bridge functions in the transparent mode The Ts1107 Host Bridge provides a 33MHz PCI clock to the PCI 6254 PCI Bridge The PCI 6254 receives the PCI clock from the Ts1107 through its primary PCI interface clock input PCLK_PCI In transparent mode the 33MHz PCI input clock at the PCLK_PCI input supplies eight 33MHz clock outputs on the PCI 6254 secondary PCI interface These eight SCLK clock outputs are enabled by the asserted SYSEN signal on the S_CLKOFF input The secondary clock output SCLK9 provides the PCI clock to the secondary interface through the secondary PCI clock input S_CLK Six clock outputs SCLK 1 6 are routed to the PCI backplane through CompactPCI connector P7202 SCLKO is routed through CompactPCI con nector P7201 as shown in Figure 3 19 on page 3 30 3 16 5 PCI 6254 PCI Bridge Clock Operation Non Transparent Mode When the CM4 is functioning as a peripheral board the CM4 is installed in a peripheral slot and the SYSEN signal is not asserted on S_CLKOFF input the PCI 6254 PCI Bridge functions in non transpare
63. uary 2004 e PCI 6254 HB6 Dual Mode Universal PCI to PCI Bridge DataBook PLX Tech nology Inc Version 2 0 May 2003 e 3Volt Synchronous Intel StrataFlash Memory Data Sheet Intel Corporation Order number 290737 004 February 2002 e 82559ER Fast Ethernet PCI Controller Data Sheet Intel Corporation Order num ber 714682 002 Revision 1 3 March 2001 XC95144XL High Performance CPLD Xilinx Inc Preliminary Production Speci fication Version 1 2 November 1998 e STK14C88 32K x 8 AutoStore nvSRAM QuantumTrap CMOS Nonvolatile Static RAM Simtek Corporation Document Control ML0014 rev 0 0 December 2002 e STI6C2550 3 3V and 5V DUART with 16 bit FIFO EXAR Corporation Rev 4 1 March 2002 e DS1685 DS1687 3V 5V Real Time Clock Dallas Semiconductor Corporation DS1685 DX 1687 CM4 User s Guide SBS Technologies 1 5 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com SBS Introduction Specifications 1 6 e PowerPC Reference Platform Specification IBM Corporation Version 1 1 e PICMG 2 0 CompactPCI Specification Rev 3 0 October 1999 e PICMG 2 3 PMC on CompactPCI Rev 1 0 August 1998 e PCI Local Bus Specification PCI Special Interest Group Revision 3 0 e Draft Standard for Common Mezzanine Card Family CMC IEEE Standards Department P1386 Draft 2 0 e Draft Standard Physical and Environmental layers for PCI Mezzanine Cards PMC IEEE
64. vide a 2 5V line The LTCI727 Power Monitor monitors the 3 3V and 2 5V line A Caution Processor manufacturers recommend the following power restrictions for long term product reliability To comply with these power restrictions it is recom mended the CompactPCI chassis use a dual power supply that complies with the ATX Power Supply Design Guide Version 1 2 Figure 2 1 Power regulation recommendations NOTES l VCC3 3 3V must not exceed VCC 5V by more than 0 6V for more than 20ms at any time including power up and power down 2 VCCS 5V must not exceed VCC3 3 3V by more than 3 6V for more than 20ms at any time including power up and power down 2 2 CM4 User s Guide SBS Technologies Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com s BS Getting Started 2 4 Installation This installation procedure is a sample bootup scheme that assumes the CM4 will boot from a CM4 BSP VxWorks image located on a network or host computer 1 Copy the BSP from the CD ROM to a permanent storage location either on a network or the host computer At a minimum the VxWorks image must be available in an FTP server location for the CM4 during bootup 2 Remove the CM4 from the static safe envelope 3 Install the CM4 in a 3U 32 bit CompactPCI compliant chassis A Caution The CM4 is not compatible with a 64 bit backplane Convection cooled Configuration 4

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