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Power Aware Simulation User`s Manual

1. Incorrect Level Shifter Check Total 1 Incorrect level shifters Source power domain PD_midl gt Sink power domain PD mid2 Total count 1 1 LS count 1 Candidate Port tb TOP mid1 out1 bot connected mask 0001 count 1 level shifter cell tb TOP lsinsti1 O l1s buf Domain PD mid1 Source port tb TOP midi1 outi bot connected mask 0001 count 1 LowConn gt Sink port tb TOP mid2 in1 bot connected mask 0001 count 1 LowConn e Valid Level Shifter Total 1 Valid level shifters Source power domain PD_midl gt Sink power domain PD mid2 Total count 1 1 LS count 1 Candidate Port tb TOP mid1 out1 bot connected mask 0010 count 1 level shifter cell tb TOP lsinsti 1 1s buf Domain PD mid1 Source port tb TOP midi1 outi i bot connected mask 0010 count 1 LowConn gt Sink port tb TOP mid2 in1 bot connected mask 0010 count 1 LowConn Redundant Level Shifter Total Redundant level shifter Source power domain PD_midl gt Sink power domain PD mid2 Total count 1 1 LS count 1 Candidate Port tb TOP mid2 ini1 bot connected mask 0100 count 1 level shifter cell tb TOP lsinst2 O l1s buf Domain PD mid2 Source port tb TOP midi1 outi i bot connected mask 0100 count 1 LowConn gt Sink port tb TOP mid2 in1 bot connected mask 0100 count 1
2. 24 Chapter 3 Power Aware Simnimlanon aos zu teasrertes REPE PRA YPAXKER EERE EKO 4 RE RR Ex 27 Inputs Required for Power Aware Simulation 0 00 cece eee eese Zi Commands Used For Power Aware Simulation 0 0 0 0 cece eee eee nee 27 General Steps for Running Power Aware 0 0 cece eee eee eens 28 Power Aware Simulation Flows 29 246422565 2Sis40u 2g See ss CdR isos essed 28 Using the Standard Flow 06 64 2c4s c4ea Caddies eme ER hx Hk e RE RR 29 Compil 253v 9pm paro E SUE ESTES ene etis x psa esae e Neb Ears 20 Ro nr RR RTT 30 vwundpo c CCP m 31 Using the Delayed Optimization Flow 1 1 2 2 0 cece eee eee 32 Using the No Optimization FloW nanena e ew Rr Rr RR Re Rx 33 Working with Liberty Libraries 1 44 sse e pe er anunue 35 Liberty Library MOUSIS i o ee EE reter n ern oed bd E E 35 Using Liberty Files with vopt ia ce acre we E RxOCee d rk e Rees Ex aU ach a 35 Creating and Saving a Liberty Database lllllleeeeeeeeeeeeA 36 Using a Previously Created Liberty Database lllslleleeeeeeees 36 Using Liberty Miles Directly o ea ince RE cohen RR OCERCCDH UU RESPRHER AES 36 Updating a Liberty Database a curent a Rep ra P ede OF ded 37 Refreshing a Liberty Database 25 2 asese sia i RR E E E RR FER 37 PDU Based SIMU ANON 255 42 tea OH CK acp Re ET E Erates A don SE E 37 Power Aware Simulation Debug 02 eee eee tenes 38 Power Aware
3. ackport altgenname case flathiername genblk ignorepgports ignorepgportsaon ignoresupply_expr mapcells nonameclash nonlrmstatenames relatedsnet s v wildcard Description To specify more than one value for this argument use the operator between values there is no order dependency when specifying multiple values For example vopt pa_upfextensions relatedsnet genblk v e To enable all values specify the following vopt pa_upfextensions all Power Aware Simulation User s Manual v10 2c 265 UPF Commands and Reference Supported UPF Extensions Toenable a limited number of values see default in Table C 5 specify either of the following vopt pa upfextensions default vopt pa upfextensions Table C 5 Power Aware Actions for vopt pa upfextensions Action Enables specifies all values of the pa_upfextensions argument Enforces the rule of the the ack_port of create_power_switch UPF command requires a mandatory supply set on the power switch in UPF 2 0 Disable this to revert to UPF 1 0 behavior altgenname Supports the synthesis style hierarchical paths for generate blocks Power Aware simulation recognizes a hierarchical path with an escaped generate scope of the form that a synthesis tool generates and maps such a name to a hierarchical name of conventional form For example each of the following styles lt prefix gt gen_label index n
4. string Example memctrl scope top dut memory unit memctrl SCOPE memctrl scope arbiter inst path top pdl instl instli POWER PDINST11 inst path cell1 Sinst path gl obal vdd1 amp inst path vd1l local vdd 11 Include Statement The ability to textually include another PCF file include statement allows PCF files to be created is provided through the include statement The on a hierarchical or power island or voltage domain basis It also allows the specification of common reusable information in a separate file for easier maintenance For example the data type corruption mapping information can be specified once and then included in any design PCF that uses that specific mapping include statement include filepath name stmt end filepath name a simple file name a relative file path name or an absolute file path name Simple filenames will be searched in the current working directory of the tool processing the PCF Relative file path names will be searched using the current working directory of the tool as the starting point for the search Absolute file path names are searched without regard to the current working directory The filepath name must conform to the UNIX file path name convention Itis an error if the specified include file does not exist Example include corruption map pcf corruption map pcf must exist in current working directory in
5. ce sets the corruption extent which takes one of the following values o outputs only os outputs and sequential elements osw outputs and sequential and non sequential wires sc sequential and combination logic based on UPF corruption semantics honoring all sequential and combination logic for corruption excluding any buffers in the path for corruption scb sequential combination and buffer logic Description Specify in either a UPF file vopt pa upf or a Tcl file vopt pa tclfile Changes the corruption extent of the power domains created by the UPF file Example Change the corruption semantics of domains P1 and P2 created in the scope tb to outputs only set scope tb set corruption extent domains P1 P2 ce o 132 Power Aware Simulation User s Manual v10 2c Power Aware Commands and Options Additional Commands You Can Use with Power Aware set feedthrough object Syntax set feedthrough object function function list package package name Arguments e function function list a required list of one or more function names you must specify at least one function name e package package name detects only functions from the specified package package name Optional Description Allows conversion functions to be treated as feedthroughs for UPF based corruption The objective is to detect conversion functions in the PA RTL and treat them as feedthrough paths
6. query supply port Support for UPF Standard v1 0 not applicable v2 0 yes Arguments Argument Comments Restrictions domain is supply detailed Usage Notes Returns state information about a previously created supply port Power Aware Simulation User s Manual v10 2c 229 UPF Commands and Reference save upf save upf Support for UPF Standard v1 0 yes partial v2 0 yes partial Arguments Argument Comments Restrictions scope See Usage Notes below version Currently version is supported only when its value is the same as input file version ModelSim extension Optional argument not specified in UPF v2 0 Uninterpreted mode only not part of UPF standard You can specify UPF commands in a separate file that is loaded by specifying the filename as the argument to the pa tcl command line option Specifically you can use this functionality to avoid putting non standard commands or commands with non standard arguments in the main UPF file which allows you to keep the file portable Also navigation commands such as set scope must be used in the pa tcl file to ensure that UPF commands in that file are applied in the appropriate scope Usage Notes Power Aware simulation supports two modes for using the save upf command interpreted and uninterpreted Interpreted mode default In interpreted mode any command or argument that is not supported by
7. set isolation Partial Partial Specifies the ports on the domain to isolate using the specified strategy set isolation control Partial Partial Specifies the control signals for a previously defined isolation strategy set level shifter Partial Power Aware Simulation User s Manual v10 2c Partial Specifies a strategy for level shifting during implementation 175 UPF Commands and Reference Supported UPF Commands Table C 1 List of Supported UPF Commands Command set partial on translation UPF Support 1 0 2 0 Description Defines the translation of PARTIAL ON to FULL ON or OFF for purposes of evaluating the power state of supply sets and power domains set pin related supply set port attributes Defines the related power and ground pins for signal pins on a library cell Specifies information relevant to ports on the interface of power domains set power switch Partial Extends a switch by adding the input supply port output supply port and states to the switch set retention Partial Partial Specifies a set of objects in the domain that need to be retention registers and identifies the save and restore behavior set retention control Partial Partial Specifies the control signals and assertions for a previously defined retention strategy set retention elements Not supported set scope set simstate behavior Sp
8. yes partial Arguments Argument j 0 Comments Restrictions elements models attribute Refer to Table C 4 for a list of UPF attributes supported for this argument exclude_elements Not supported 232 Power Aware Simulation User s Manual v10 2c UPF Commands and Reference set design top set design top Support for UPF Standard v1 0 yes v2 0 yes Arguments none Power Aware Simulation User s Manual v10 2c 233 UPF Commands and Reference set domain supply net set domain supply net Support for UPF Standard v1 0 yes v2 0 yes Arguments Comments Restrictions primary power net primary ground net 234 Power Aware Simulation User s Manual v10 2c UPF Commands and Reference set isolation set isolation Support for UPF Standard v1 0 yes partial v2 0 yes partial Power Aware Simulation User s Manual v10 2c 235 UPF Commands and Reference set isolation Arguments Argument Comments Restrictions domain elements Complex data types of System Verilog such as structs are not supported However you can specify bit or part selects of one or more signals Example set isolation ISO1 domain PD1 elements out1 2 out2 2 1 applies to isolation power net isolation ground net no isolation isolation supply set Supports only a single value no list multiple clamp values supplies and enable isola
9. yes v2 0 yes Arguments Comments Restrictions wm T Usage Notes Creates a power state table PST Power Aware Simulation User s Manual v10 2c 203 UPF Commands and Reference create supply net create supply net Support for UPF Standard v1 0 yes v2 0 yes Arguments Argument Comments Restrictions domain reuse resolve The value of parallel is implemented differently for v1 0 and v2 0 See Usage Notes below Usage Notes UPF v1 0 implemented a slight error in the semantic specification for UPF command create supply net resolve parallel which has been corrected in UPF v2 0 Power Aware simulation follows the UPF v2 0 specification in this case since it is the later standard and its definition reflects what was intended to be the semantics for UPF v1 0 Specifically if multiple switches drive a supply net with parallel resolution and the state of at least one but not all switch outputs is fully ON and the remaining switch outputs are OFF then e UPF v1 0 says the state of the driven supply net should be fully ON e UPF v2 0 says the state of the driven supply net should be partially ON Therefore in following the UPF v2 0 specification the state of the driven supply net will be partially ON 204 Power Aware Simulation User s Manual v10 2c UPF Commands and Reference create supply port create supply port Support for UPF Standard v1 0 yes v2 0 yes A
10. Any additions you may need to make to the specification file to achieve correct Power Aware functionality For example certain sections of the design that are non synthesizable such as a test bench should not be inside a power domain The report may suggest that you put this section of the design inside an always on power domain e Behavioral constructs that must be in an always on power domain Generating Reports for Power Aware You can use different values with the pa_genrpt argument of vopt to generate a variety of Power Aware data for the reports Table 4 1 lists the values for pa genrpt and their corresponding reports for UPF Power Aware reports are generated in two steps Use the vopt command with the following options o pa genrpt generates the necessary information o pa reportdir optional changes the default location of where the reports are written 2 Usethe pa report command from the vsim prompt to write out the reports How to Generate a Report with vopt pa genrpt Syntax vopt pa genrpt nv v ud us u b pa de Power Aware Simulation User s Manual v10 2c 45 Power Aware Reports UPF Reports Note For additional reference information on the pa_genrpt argument refer to the vopt command in the ModelSim Reference Manual Description The pa_genrpt argument generates data for the report files listed in Table 4 1 If you do not specify a value for the pa genrp
11. In addition you can specify an existing value conversion table VCT using the following UPF command and argument connect supply net vct Note Power Aware simulation provides several predefined VCT definitions see Value Conversion Tables that you with connect supply net vct However if the VCT specification for a connection is not applicable or valid then Power A ware simulation applies the default 1 bit connection semantics Examples RTL Specification Verilog module memory input VSS VDD endmodule Power Aware Simulation User s Manual v10 2c 285 UPF Commands and Reference Value Conversion Tables RTL Specification VHDL entity memory is port VSS in std logic VDD in std logic end entity UPF specification connect supply net VDD switchable ports mem sv VDD connect supply net VSS switchable ports mem sv VSS vct UPF GNDZERO2SV LOGIC connect supply net VDD switchable ports mem vhd VDD connect supply net VSS switchable ports mem vhd gnd vct UPF GNDZERO2VHDL SL RTL Specification Verilog module memory input VSS endmodule UPF specification connect_supply_net VSS_switchable ports mem_sv VSS vct SV LOGIC2UPF GNDZERO Data flow for the connection is UPF to HDL but VCT is specified as HDL to UPF As a result the specified VCT is not applicable Simulation Semantics for UPF Supply Connections Power Aware simulation semantics are autom
12. PCF Power Specification File To perform Power Aware verification you need to provide a power specification file that identifies the low power specification of the design A power specification file is analogous to a standard delay file SDF used for annotating timing and timing check information into a simulation Using a power specification file is the key to the verification flow using Power A ware This file provides the following information required to overlay verification with the power control network and Power Aware functionality Power regions voltage domains and power islands Retention sequential models their type and the regions they are in including nodebug encrypted and protected regions e State and output corruption behavior in power down situations Power control signals and the portions of the design they control The power specification file is designed to capture all Power Aware characteristics of the design at the RTL or higher in a compact form that can be easily used by the simulator Formats This power specification file can be written using Power Configuration File PCF A preliminary file format specific to ModelSim that was developed to meet the specific needs of various customers and semiconductor companies Refer to Power Configuration File Reference for more information on PCF Using a PCF as Part of Power Aware Verification You can use a power specification file written as a P
13. Performing actions on selected power aware checks Power Aware Check Selection Note _____ If you do not specify any of these options the command selects all dynamic power aware checks except the ones with severity NOTE message numbers These numbers are found in the violation message of the power aware check The numbers you specify select the associated power aware checks For example pa msg 8920 8931 selects the power aware checks associated with message numbers 8920 and 8931 e pa checks spec This option is the same as that specified with the vopt command For example pa msg pa checks irc upc selects the isolation race and switching off of isolation and retention supply checks e all This option selects all dynamic PA Checks Fine Control of Check Selection e scope scope name This option defines the scope of the command where the scope is restricted to apply from this scope downward By default the scope is the design top scope Note This option is meaningful when you specify it with domain strategy or ports The scope is dependent on how you specify scope name o If you specify an absolute path name starting the argument with a slash then the scope is becomes your explicit argument pa msg scope tb TOP mid1 138 Power Aware Simulation User s Manual v10 2c Power Aware Commands and Options Power Aware Messages o Ifyou do not sp
14. Power Aware Simulation User s Manual ModelSim SE Software Version 10 2c 2010 2013 Mentor Graphics Corporation All rights reserved This document contains information that is proprietary to Mentor Graphics Corporation The original recipient of this document may duplicate this document in whole or in part for internal business purposes only provided that this entire notice appears in all copies In duplicating any part of this document the recipient agrees to make every reasonable effort to prevent the unauthorized use and distribution of the proprietary information This document is for information and instruction purposes Mentor Graphics reserves the right to make changes in specifications and other information contained in this publication without prior notice and the reader should in all cases consult Mentor Graphics to determine whether any changes have been made The terms and conditions governing the sale and licensing of Mentor Graphics products are set forth in written agreements between Mentor Graphics and its customers No representation or other affirmation of fact contained in this publication shall be deemed to be a warranty or give rise to any liability of Mentor Graphics whatsoever MENTOR GRAPHICS MAKES NO WARRANTY OF ANY KIND WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE MENTOR GRAPHICS SHALL NOT BE LIABLE FOR ANY IN
15. The simulator restores the value previously saved for the inferred registers or latches to the corresponding signal s in the design Restoration of a value results in an event on the corresponding signal to facilitate propagation of known good states throughout a block that has had power restored event pa restore x The simulator restores re initializes the inferred registers or latches to an unknown state specified by the corruption value for the signal s data type The simulator propagates an event on the restored corruption value event pa corrupt register corrupt the register The simulator corrupts the current value of the signal corresponding to the inferred registers or latches The corruption value used is determined by the data type corruption value table specified separately No event is propagated due to the corruption NOTE See Usage Note for Sequence Requirements below event pa set register set the register The simulator sets the current value of the signal corresponding to the inferred register or latch to a set value which is inferred from the RTL code The simulator propagates an event on the set signal value event pa reset register reset the register The simulator sets the current value of the signal corresponding to the inferred register or latch to a reset value which is inferred from the RTL code The simulator propagates an event on the reset signal value event pa restore hold registe
16. absolute path separator character relative path Another application may provide a mechanism external to the PCF to specify information equivalent to a scope statement being specified immediately after the header statement This usage model supports the use of the same PCF with different test benches or in block level as well as chip level verification Examples SCOPE root dut Set initial scope to DUT SCOPE memctrl arbiter Set scope to memctrl arbiter instance down design hierarchy from current scope Variable Statement Variable statements are used to store frequently used values The values are treated as untyped and are applied to the context specified and then interpreted They are very similar to UNIX environment variables or macros An example usage would be to define a path to a common level of hierarchy from which many instance signal etc paths will then be defined variable statement identifier value stmt end S identifier The lexical form of the identifier adheres to the rules for identifiers in Verilog IEEE Std 1364 2005 The identifier must be prefixed by the dollar sign symbol in both the specification of its value and the referencing of that value No white space is permitted between the symbol and the identifier Power Aware Simulation User s Manual v10 2c 303 Power Configuration File Reference PCF Syntax and Contents value a double quoted
17. tb top q regvl Where the sections contain the following information e Section 1 Header information about the isolation strategy e Section 2 Specifies the isolation supplies with the full hierarchical path name of the supply nets e Section 3 Provides additional information related to the isolation strategy specifically o Isolation Control The control signal triggering the isolation clamp value o Isolation Sense The sense of the control signal at which the clamp value is applied on the isolated port o Clamp Value The clamp value specified o Location The location specified in the isolation strategy Section 4 Specifies a list of candidate ports for isolation with full hierarchical path names of the port Level Shifter Strategy The information regarding the level shifter strategy is specified under this heading followed by the strategy name and UPF file reference UPF Command for Level Shifting set level shifter pd 1s domain pd applies to both Report File Sections and Subheadings 1 Level Shifter Strategy pd 1s File test upf 51 2 Rule both Threshold 0 Applies to both Location automatic 3 Level Shifted Candidate Ports 1 Signal tb top q combvl 2 Signal tb top q latvl 3 Signal tb top q regvl 4 Signal tb top set 5 Signal tb top reset 6 Signal tb top clk 58 Power Aware Simulation User s Manual v10 2c Power Aware Reports UPF Reports
18. yes partial v2 0 yes partial Arguments Argument domain Comments Restrictions elements retention power net retention ground net retention supply set Powers the register holding the retained value no retention Specifies that storage elements specified by the retention strategy do not have retention capability added use retention as primary Powers the storage element and the output drivers of the register using the retention supply save signal restore signal instance Recognizes the special attributes present on the specified instance applies the appropriate simulation semantics and makes the connections Refer to Usage Notes for set_retention for more information exclude_elements Allows adding elements and supplies to a previously created power domain Not supported restore_condition retention_condition save_condition parameters Not supported transitive 250 Not supported Power Aware Simulation User s Manual v10 2c UPF Commands and Reference set retention Usage Notes for set retention Restrictions Corruption of retention element and saved value is not supported The implicit corruption semantics are also applied to the shadow latch used to preserve the data during retention period In order to remove the shadow latch from corruption you must specify it in an exclude file v
19. 1 Pst MyPowerStateTable File prototype upf 80 2 Scope tb 3 Header gt PD ALU primary power PD RAM sw out sw PD RAM Reboot prototype upf 84 s state ram s Sleep prototype upf 85 r state ram s Hibernate prototype upf 86 r state ram r Complete on prototype upf 87 o state ram o 4 List of possible states on PD ALU primary power source supply port out sw PD ALU Power Aware Simulation User s Manual v10 2c 59 Power Aware Reports UPF Reports File prototype upf 12 1 o state 4 20 2 r state 3 20 3 S state 2 20 out sw PD RAM source supply port out sw PD RAM File prototype upf 65 1 ram s 3 80 4 20 4 80 2 ram r 8 20 3 ram o 6 20 4 off state OFF Where the sections contain the following information Section 1 Header information about the level shifter strategy e Section 2 Specifies the hierarchical path of the scope where the PST is created e Section 3 Specifies hierarchical paths of the supply nets ports that form the columns of the PST The hierarchical paths are relative to the Scope of the PST The lines that follow contain the rows of the PST as mentioned in the UPF and the corresponding states of the supply nets ports mentioned in the PST header At the end a list of all possible states present on the objects mentioned in the header is shown This includes detailed information of the states listed with the voltage information e Section 4 Specifies a list of al
20. 7 Signal tb top d Where the sections contain the following information e Section 1 Header information about the level shifter strategy Section 2 Information related to the level shifting strategy including the following o Rule Shift Direction o Threshold Threshold value in volts o Applies to The value of the applies to argument specified in the set level shifter command o Location The location specified with the set level shifter command e Section 3 A list of candidate ports for level shifting with full hierarchical path names of the port Power State Tables PSTs Report information for power state tables PST is listed under the heading Pst UPF Command for Power State Table add port state PD ALU sw out sw PD ALU state s state 2 2 state r state 3 2 state o state 4 2 state off state off add port state PD RAM sw out sw PD RAM state ram s state ram r state ram o 3 8 4 2 4 8 JN 5 2JN 6 2 state off state off create pst MyPowerStateTable supplies PD ALU primary power add pst state add pst state add pst state add pst state PD RAM sw out Sw PD RAM Reboot pst MyPowerStateTable state s state ram sj Sleep pst MyPowerStateTable state r state ram sj Hibernate pst MyPowerStateTable state r state ram r Complete on pst MyPowerStateTable state o state ram o Report File Sections and Subheadings
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22. GND NET VDI D_PRI create_power_switch P1_SW domain P1 V output supply port VDD SW input supply port control port ctr11 on state full s1 VI off state off s0 ctr11 lements dut1 domain P1 VDD PRIj du VDD SW Inl VDD NET t sleep DD SW 1 Inl ctrl1 Power Aware Simulation User s Manual v10 2c Visualization of Power Aware Operations Power Aware Schematic Display create power domain P2 elements dut2 create supply port VDD P2 domain P2 create supply net VDD N domain P2 connect supply net VDD N ports VDD P2 create supply port GND P2 domain P2 create supply net GND_N domain P2 connect supply net GND N ports GND P2 create supply net VDD P domain P2 set domain supply net P2 primary power net VDD P primary ground net GND NET create power switch P1 SW2 domain P2 output supply port VDD SW VDD PRI input supply port VDD SW In1 VDD NET control port ctrll dut sleep on state full s1 VDD SW In1 ctrl1 off state off sO0 ctr11 create power domain P3 elements dut3 create supply port VDD P3 domain P3 create supply net VDD NE domain P3 connect supply net VDD NE ports VDD P3 create supply port GND P3 domain P3 create supply net GND NE domain P3
23. NPM FF Denotes all Non Power Management Flip Flops of a Power Domain NPM LA Denotes all Non Power Management Latches of a Power Domain UPF Static Report Report Output report upf txt Command vopt pa_genrpt us u b The UPF static report typically contains the information that was specified in the specification file and how Power Aware simulation has processed that information You can use this report to statically validate the power intent specified by UPF and check whether it is properly applied This report file contains information regarding the power domain power supplies power switches and their characteristics retention isolation and level shifter strategies and information regarding the power states and power state tables PSTs Specifying a value of b writes bitwise expanded information for isolated and level shifted ports into this report file Note The content and structure of this report is same as that of report pa txt and includes all objects that are either added or modified by applying power intent to the design The following sections are described in the section about report pa txt Power Domain including supplies Power Switch including supplies Retention Strategy including supplies Isolation Strategy including supplies Level Shifter Strategy Power State Tables PSTs Example of UPF Static Report File Example 4 3 Example File for Static UPF Re
24. Power Aware Coverage Analysis Coverage Type Power Aware Refer to the section Power Aware Coverage Detailed Report for a detailed description of this report Generating HTML Reports As an alternative to the text based reports you can create a navigation ready HTML report of your power aware coverage data Command line coverage report pa html GUI o Menu Tools gt Coverage Report gt HTML o Coverage HTML Report dialog box Other Options Power Aware Accessing Coverage Data for Post Simulation Analysis Prerequisites Enable coverage collection during your power aware flow Refer to the section Power Aware Coverage Collection Create a UCDB based on a the power aware simulation Refer to the section Generating a UCDB File for Power Aware Procedure 1 Load UCDB vsim viewcov lt name gt ucdb This loads the UCDB into the GUI for your analysis 2 Generate reports coverage report pa details Refer to the Chapter Coverage and Verification Management in the UCDB in the User s Manual for information on using UCDB files Power Aware Simulation User s Manual v10 2c 99 Power Aware Coverage Power Aware Coverage Report Reference Power Aware Coverage Report Reference This section contains an overview of the various coverage reports you can generate as described in the section Generating Power Aware Coverage Reports Power Aware Coverage Summary This report provides an ove
25. Power Switch state ON Power Domain PD BOT Note vsim 8916 MSPA UPF RET CTRL INFO Time 40 ns Retention Strategy PD BOT retention Retention RESTORE tb ret bot reg Retention Sense negedge switched to polarity 0 Power Domain PD BOT Power Aware Simulation User s Manual v10 2c 53 Power Aware Reports UPF Reports ote vsim 8914 MSPA UPF ISO CTRL INFO Time 65 ns Isolation gy PD BOT isolation Isolation Control tb iso bot Isolation Sense HIGH switched to polarity 1 Power Domain PD BOT o T te vsim 8902 MSPA PD STATUS INFO Time 70 ns Power domain is powered down Note vsim 8913 MSPA UPF SWITCH CTRL INFO Time 70 ns Power Switch PD BOT sw Control Signal tb pg bot switched to polarity 0 Power Switch state OFF Power Domain PD BOT Note vsim 8902 MSPA PD STATUS INFO Time 85 ns Power domain PD BOT is powered up 4 Note vsim 8913 MSPA UPF SWITCH CTRL INFO Time 85 ns Power Switch PD BOT sw Control Signal tb pg bot switched to polarity 1 Power Switch state ON Power Domain PD BOT Note vsim 8914 MSPA UPF ISO CTRL INFO Time 90 ns Isolation Strategy PD BOT isolation Isolation Control tb iso bot Isolation Sense HIGH switched to polarity 0 Power Domain PD BOT Architecture Report Report Output
26. SEPARATOR Optional This keyword value pair identifies the separator character used to separate one scope level from the next If not specified the separator character is defined by the tool processing the PCF or if the tool defines no default it is the slash character Although defined by a string value the separator character string value must be exactly one character in length e STMT_TERM Optional This keyword value pair identifies the statement termination In PCF 1 0 the default statement termination is CRLF For PCF 2 0 or later the default statement termination is semicolon The only permissible values are CRLF 6699 or e VENDOR string Optional This keyword value pair specifies a vendor s tool specific entry Vendors may define their own tool specific header information Vendor specific information must be tagged by the prefix VENDOR in the keyword Vendor specific header information cannot be used to change the PCF syntactic or semantic information as defined in this specification It can be used for general informational purposes for example to identify the tool and tool version that generated or is targeted for consuming the PCF Vendor specific keyword values must be double quoted strings Example This example shows the use of a secondary prefix MGC that identifies the specific vendor in this case Mentor Graphics Corporation Such keyword naming conventions are encourag
27. Summary Active Hits Misses Covered States 5 0 5 0 0 Transitions 25 0 25 0 0 POWER STATE COVERAGE UPF OBJECT Metric Goal Status At Least Power Aware Simulation User s Manual v10 2c 101 Power Aware Coverage Power Aware Coverage Report Reference TYPE SUPPLY SI SUPPLY SET tb CPU1 PD RAM SS Power State PD RAM SS ON1 bin ACTIVE Power State PD RAM SS ON2 bin ACTIVI Power State P bin ACTIVI RAM SS ON3 How Power State DEFAULT_CORRUPT bin ACTIVE SUPPLY SET tb CPU1 PD_RAM_SS bin PD_RAM_SS_ON2 gt D RAM SS ON1 TYPE SUPPLY Sl Power State Transitions bin PD RAM SS ON1 gt PD RAM SS ON2 bin PD RAM SS ON1 PD RAM SS ON3 bin PD RAM SS ON1 gt PD RAM SS ONA4 bin PD RAM SS ON1 gt PD RAM SS ON5 bin PD RAM SS ON1 gt PD RAM SS ON6 bin PD RAM SS ON1 gt DEFAULT NORMAL bin PD RAM SS ON1 gt DEFAULT CORRUPT P P bin PD_RAM_SS_ON2 gt D_RAM_SS_ON3 bin DEFAULT_NORMAL gt PD_RAM_SS_ON5 bin bin bin bin bin bin bin bin bin gt DEFAULT CORRUPT DEFAULT CORRUPT DEFAULT CORRUPT DEFAULT CORRUPT DEFAULT CORRUPT DEFAULT CORRUPT iT CORRUPT TOTAL POWER STATE COVERAGE JdHAaAH I M gt PD_RAM_SS_ON6 DEFAULT_CORRUPT PD_RAM_SS_ON1 PD_RAM_SS_ON2 PD_RAM_SS_ON3 PD_RAM_SS_ON4 PD_RAM_SS_ON5 PD_RAM_SS_ON6 gt DEFAULT_NORMAL 75 0 100 Uncovered ET coverage instance tb CPU1 pa_cov
28. Working with Liberty Libraries Liberty Library Models Liberty libraries define standard cells and macro cells that can be used in a system Liberty models include information that defines how power supplies provided to instances of such cells are used to power logic receiving inputs or driving outputs of those cell instances Liberty models also include other information pertaining to power management cells The information contained in a Liberty library may be of use in both RTL and Gate Level simulations as well as in mixed RTL GL simulations For example Liberty models of hard macros may be of use in applying power intent to the RTL portion of a design and information about standard cells in a Liberty library may be of use in applying power intent to the gate level portion of a design Power Aware simulation uses the information present in the Liberty library to create proper connection of the supplies and the control signals that are defined in the UPF power intent specification Power Aware simulation also uses such information to assist in automatic recognition of power management cells that are present in a design Liberty libraries can be preprocessed to extract power related information into a database that can be used during UPF processing in preparation for power aware simulation This preprocessing step enables most efficient use of Liberty libraries when the same library will be used many times Liberty libraries can also be read d
29. e Path N identifies the hierarchical path of the scope in the rest of the report e signal identifies the name of the signal e keyword one of the following values indicating whether the signal is acting as a state element or a retention element o NPM LA Non retention Latch Power Aware Simulation User s Manual v10 2c 63 Power Aware Reports UPF Reports o NPM FF Non retention Flip Flop o MEM Non retention Memory o UDP LA Non retention UDP Latch o UDP FF Non retention UDP Flip Flop o R Retention element o lt no keyword gt Combinatorial logic Example Design Elements Report Excerpt for State Elements pd Path3 q combvl pd Path3 q regvl R pd Path3 q latvl NPM LA pd aon Pathl1 q regvl NPM FF Retention Signals The signals in the design performing retention behavior are marked with a special keyword R after the signal name The signals in the design performing retention behavior are listed in the same way as Corrupted Signals along with the keyword R after the signal name Format The report format for listing corrupted signals is the following power domain Path lt N gt lt signal gt R where e power domain identifies the name of the power domain When power domain is represented by two dashes it indicates that the signal was excluded using exclusion rules e Path N identifies the hierarchical path of the sc
30. receiver supply driver supply related power port related ground port related bias ports repeater supply pg type Z Z Z Z Z 2 Z Z Z Z Z Z Z K K Z S ee No support for pg_type for UPF created supply ports exclude_domains Not supported exclude_elements Not supported exclude_ports Not supported Z z zzz Z z zzz transitive Not supported Power Aware Simulation User s Manual v10 2c 247 UPF Commands and Reference set port attributes Usage Notes Power Aware Simulation does ot support the specification of an attribute on an index or record field specification as appropriate for the type of an object Specifically bit and part selects for Verilog VHDL indexed name for array elements slice names for array subranges or selected names for record elements The clamp value source off clamp and sink off clamp arguments affect the filtering of ports specified by the set isolation command Power Aware simulation assumes the driver receiver logic supply to be the same as specified related supplies that is corruption isolation and level shifting behavior is in accordance with the specified related supplies When the supply specified using set port attributes using related power port or related ground port is a different supply than that of actual driver or receiver logic Power Aware simulation gives a vopt error message vopt
31. supply nets logic variables that contribute to the power states If a header is associated with a power domain or supply set you can double click on it to view the state transitions of that state machine For PSTs the column headers show ports and nets from the creation of the PST with the create pst UPF command and you can double click on them to view the state transitions of that state machine o Rows Shows values for the time selected in the Time Mode widget where green indicates the current value and yellow indicates the previous value Power Aware Simulation User s Manual v10 2c 121 Visualization of Power Aware Operations Power State and Transition Display Popup Menu Table 7 4 Power Aware State Machine Viewer Window Popup Menu Popup Menu Item Description Transition View Full Text Displays the full text of all condition expressions View UPF Show States Table Opens the UPF file and displays the line creating the power aware state machine Toggles the display of the states table for supply sets and power domains Zoom Full Fits the bubble diagram into the visible space Set Context Sets the context env command of the session based on your selection Add to Adds the selected or all state machines to the Wave window List window or to the log add log Properties Displays the Power Aware State Machine Properties dialog box which contains detailed information a
32. tb TOP bot3 in2 bot count 1 LowConn 3 LS count 0 Candidate Port tb TOP botil outi bot count 1 level shifting strategy my 1s PD pd bot Source port tb TOP botl outl bot count 1 LowConn gt Sink port tb TOP bot4 in2 bot count 1 LowConn Source power domain pd aon gt Sink power domain pd top Total count 1 1 LS count 1 Candidate Port tb TOP bot2 out1 bot count 1 level shifting strategy my 1s PD pd aon Source port tb TOP bot2 outl bot count 1 LowConn gt Sink port tb TOP bot2 outl1 bot count 1 HighConn Report File dump for the level shifter strategy Total 2 Valid level shifters Level shifting strategy my ls Power domain pd aon 1 Candidate port tb TOP bot2 outl bot count 1 Inferred type Valid count 1 Source port tb TOP bot2 outi bot LowConn Domain pd aon gt Sink port tb TO P bot2 outi1 bot HighConn Domain pd top Level shifting strategy my ls Power domain pd bot 3 Candidate port tb TOP boti outi1 bot count 1 Inferred type Valid count 0 Source port tb TOP boti outi bot LowConn Domain pd bot gt Sink port tb TO P bot4 in2 bot LowConn Domain pd aon Inferred type Valid count 0 Source port tb TOP boti outi bot LowConn Domain pd bot gt Sink port tb TO P bot3 in2 bot LowConn Domain pd aon Power Aware Simulation User s Manual v10
33. test upf 7 UPF vopt 9693 Power Aware for tb topl1 mid1 bot2 test upf 7 UPF vopt 9693 Power Aware for tb topl mid2 bot1 test upf 7 UPF vopt 9693 Power Aware for tb topl1 mi Power Aware Simulation User s Manual v10 2c simul simul simul simul elements mid3 lation ation ation ation semantics semantics semantics semantics 255 UPF Commands and Reference set simstate behavior eo Tip You can suppress the above messages by using the following argument with the 256 vopt command vopt suppress 9693 Example C 14 When Both models and lib Arguments Are Specified upf version 2 0 set scope tb topl create power domain pdl set simstate behavior ENABLE model mid lib lib_namel set simstate behavior DISABLE model top lib lib name2 create supply net VDD N domain pd1 create supply net GND_N domain pd1 Example C 15 Specify Simstate Behavior For All Models in a Library upf version 2 0 set scope tb topl create power domain pdl set simstate behavior ENABLE lib lib _namel set simstate behavior DISABLE lib lib name2 create supply net VDD N domain pd1 create supply net GND_N domain pd1 Example C 16 Use elements Argument to Override or Specify Simstate Behavior single element upf version 2 0 set scope tb topl create power domain pd1 set simstate behavior ENABLE elements tb
34. this cell type is equivalent to two mapping statements that are identical except for cell type where one statement cell type is FF CKLO and the cell type of the other equivalent mapping statement is LA ENLO ANY CKFR Generically matches any inferred sequential element without regard to edge or level sensitivity A mapping statement specifying this cell type is equivalent to four mapping statements that are identical except for the cell type The Ist equivalent statement has cell type FF CKHI the 2nd equivalent statement has cell type FF CKLO the 3rd equivalent statement has cell type LA ENHI and the 4th equivalent statement has cell type LA ENLO RETMEM Matches an inferred memory to a model that will determine under what conditions the memory contents would be corrupted If the pacell type is RETMEM then the region definition must specify a signal s signal for memory contents It is an error if any other region definition is specified NON RETMEM Matches an inferred memory to corruption only semantics memory contents are always corrupted in power down situations In the case of NON RETMEM pacell type the model module name must indicate the built in corruption model bi nonret memory The builtin corruption model applies the corruption value as governed by the corruption map in effect for that scope interface information optional The pacell spec can optionally specify a named mapping of power control signals
35. top ti1 sig3 Note exclude txt 1 vopt 9013 Excluding signal sig4 in power aware module bot mod in path top ti1 sig4 Note exclude txt 1 vopt 9013 Excluding signal sig2 in power aware module bot mod in path top ti1 sig2 Direct Power Aware processing to skip signal or net sig present in the scope of all instantiations of bot mod found within the instance top t1 Entry in the exclude file bot mod top tl sr sig Log messages for the vopt command Note exclude txt 1 vopt 9013 Excluding signal sig in power aware module bot mod in path top ti1 blk fg 5 sig Note exclude txt 1 vopt 9013 Excluding signal sig in power aware module bot mod in path top ti1 blk fg 4 sig Note exclude txt 1 vopt 9013 Excluding signal sig in power aware module bot mod in path top t1 blk fg__3 sig Note exclude txt 1 vopt 9013 Excluding signal sig in power aware module bot mod in path top t1 blk fg__2 sig Note exclude txt 1 vopt 9013 Excluding signal sig in power aware module bot mod in path top t1 blk fg__1 sig Note exclude txt 1 vopt 9013 Excluding signal sig in power aware module bot mod in path top tl blk sig Note exclude txt 1 vopt 9013 Excluding signal sig in power aware module bot mod in path top ti s
36. you can specify the upf is leaf cell attribute along with set design attributes command for the specific module Detection of Power Management Cells Power Aware simulation automatically detects isolation level shifter and retention cells in the netlist and infers them for any corresponding UPF strategies Power Aware simulation will then validate the cells with respect to strategies in the UPF and run power aware check on them Gate level netlists may have some of the power management cells isolation level shifter or retention corresponding to the UPF strategy already instantiated in the netlist Some of these cells may already be specified as a value for the instance argument of the set isolation set level shifter or set retention commands of the UPF strategy in UPF file For the rest of the cells that are not specified in the UPF file Power Aware simulation automatically detects the right UPF strategy to which they belong and treats them in a similar way to cells of that strategy specified with an instance argument Auto detection of power management cells leverages the following information for Liberty attributes o is isolation cell o is level shifter o retention cell lib cells specified with the following UPF commands o map isolation cell o map level shifter cell Arguments for the UPF name format command 40 Power Aware Simulation User s Manual v10 2c Power Aware Simulation Applying Power Intent to the Des
37. 0 0 add_port_state VSS_SW state ON 0 state OFF off eS oe a SS ee Sa oe SS Se a a SS Se eS Create power state table SSS SSS SSeS SS See Se eS create_pst top_pst supplies VDD 0d99 VDD 0d81 VSS VSS_SW add pst state ON pst top pst state ON ON ON ON add_pst_state SLEEP pst top pst state ON ON ON OFF add pst state OFF pst top pst state OFF OFF ON OFF The power states of the system in Figure E 1 are defined in the above power state table Note that these power states are the same as the operating modes of the system plus the state in which the system is completely turned off Isolation and Level Shifting Even though each power domain may be independently powered on and off their logical and physical connections to other power domains remain therefore when one domain is turned off it is still connected logically and electrically to other domains These connections between power domains require special cells to mediate the interaction between domains as their respective power states change Two kinds of cells are involved isolation cells and level shifting cells Isolation cells ensure that signals coming from unpowered domains are clamped to a well defined logic value while the source domain is powered down so that any sink domain that is powered up sees reliable inputs Depending upon t
38. 14 Power Aware Simulation User s Manual v10 2c Getting Started With Power Aware Simulation Where Is Power Aware in Your Design Flow Verification including Questa PASim Questa ADMS Questa Formal Questa Codelink and Questa VM Power Efficient Design Design of hardware that involves active power management This includes design decisions involved in allocating power budget partitioning the design into power domains and defining the power management architecture the power control logic and the power control software as well as products used for verification and implementation of such designs This relates to the entire range of Mentor Graphics products that are involved in the design verification and implementation of low power IP chips and systems Figure 1 1 Typical Location of Power Aware Simulation in Design Flow Design Capture RTL Architecture Formal Verification Definition of Power Intent RTL Power Aware Design Coverage Synthesis GLS Power Aware Power Aware Simulation User s Manual v10 2c 15 Getting Started With Power Aware Simulation Documentation Scope and Organization Documentation Scope and Organization Power Aware simulation augments normal HDL simulation capabilities with the ability to specify model and simulate the effects of active power management logic that will be added to the design during implementation The success of applying Power Aware features depends on
39. 41 Retention Supplies power tb V pd net ground tb G pd net Retention SAVE tb ret Retention Sense posedge Retention RESTORE tb ret Retention Sense negedge Retained Signals 1 Scope tb top vh File reg vh vhdl 12 Model upf retention ret 1 tb top vh q regvh 2 Scope tb top vl File reg vl v 1 Model upf retention ret 1 tb top vl q regvl Isolation Strategy pd isolation File test upf 48 Isolation Supplies power tb V pd net ground tb G pd net Isolation Control tb iso Isolation Sense HIGH Clamp Value 1 Location parent Isolated Signals Signal tb top vh q combvh 2 Signal tb top vh q latvh 3 Signal tb top vh q regvh 4 Signal tb top vl q combvl 5 Signal tb top vl q latv 6 Signal tb top vl q regvl Design Elements Report Report Output report de txt Command vopt pa_genrpt de This report contains all the information related to elements present in user design and its corresponding Power Aware information The contents of this report are similar to that provided in the report mspa txt file but it is presented in a different format that makes it easier to extract information from the report Report information is listed in single line records that contain keywords indicating the specific Power Aware characteristics This report file contains information regarding the following Power Aware Simulation User s
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41. Aware Simulation User s Manual v10 2c Automatic Checking Quick Reference Comparison of Static and Dynamic Check Arguments module ISO AND pg type primary power input logic pwr rail pg type primary ground input logic gnd rail isolation cell enable pin TRUE input logic en isolation cell data pin TRUE input data output logic out assign out data amp en endmodule Method 2 Pragma information to the instantiation is generated by the synthesis application For example ISOLODIBWP isoinsti1 I o1 Z w1 ISO ctrl synopsys isolation upf iso PD mid1 PD midi where iso PD midl is the UPF strategy for this isolation cell instance and PD midl is the Power domain for which strategy has been specified Method 3 Create this instance by assigning an isolation prefix or suffix string to it as specified by the UPF name format command For example ISO isoinst2 UPF ISO I o1 Z w1 ISO ctr1 Quick Reference Comparison of Static and Dynamic Check Arguments Table 5 7 Static and Dynamic Checks Comparison Missing Level Shifter pa_checks sml pa_checks uml Redundant Level Shifter pa_checks srl Incorrect Level Shifter pa_checks sil pa_checks uil Unanalyzed level shifter pa_checks snl Valid level shifter pa_checks svl Uninserted level shifter pa_checks sdl Missing Isolation Cell pa_checks smi pa_checks umi Red
42. Boeckman Road Wilsonville Oregon 97070 7777 Telephone 503 685 7000 Toll Free Telephone 800 592 2210 Website www mentor com SupportNet supportnet mentor com Send Feedback on Documentation supportnet mentor com doc feedback form Table of Contents Chapter 1 Getting Started With Power Aware Simulation eeeeeeeees 13 Where Is Power Aware in Your Design Flow 0 0 cece eee ees 14 Documentation Scope and Organization 0 0 cee eee eee eee 16 Contents of This Manual 2 c0c0ucesteeasee See eeneesdenaseesQeeeueecderasee Eq 17 How to Use This Manual zu ogseciadeeeeeyueagheddndetededaseGhad Pa ERE RN 17 Related Documentatlon a222cccebpecesce seti AA Re PRI qu RO Ad REP ER TAJqEeR S 18 Chapter 2 Concepts for Using Power Aware Simulation eeeeeee eee 19 Power Intent Specification ssa esr RR ioe een OCA RO C YO ERGO ER GR e aa eage 19 Power Aware Modeling 22 34 2642 bre PdrREERRIMERERCE Pd AXE deRE EE 19 Modeling Corruption 1 25 24 os end EE EN RARESIARAXAXRPEASREAT eyes eee Sas 20 Corr ption Vales oacexecemdecebe eR CERES PA REUCKP CEP UR D Rabe seed 21 Default Corruption Semantics vus 24646495609 hee oh a REO REUS ER ER CERE 21 Modeling Isolation erer reene rO cP EREA NER T O ERER ddr Va Eds 22 Modeling Retention uus quse x ax rn Uy RC HUESCA ON PR ah e Ce AREAS 22 Edge sensitive and Level sensitive Control of Retention Models 23 Modlina TIS
43. HM P2 related ground port GND HM P2 RTL Attributes For HM1 UPF related power pin VDD HM pl UPF related ground pin GND HM pi input in4 UPF related power pin VDD HM p2 UPF related ground pin GND HM p2 input in5 For HM2 UPF related power pin VDD HM p1 UPF related ground pin GND HM pi input in7 UPF related power pin VDD HM p2 UPF related ground pin GND HM p2 input in8 UPF related power pin VDD HM p2 UPF related ground pin GND HM p2 output o2 Power Aware Simulation User s Manual v10 2c 155 Power Aware Commands and Options Creating Feedthrough For RTL Conversion Functions Liberty File Attributes library PALIB cell HM pg pin VDD_HM P1 pg type primary power user pg type abc voltage name COREVDD1 j pg pin GND HM P1 pg type primary ground voltage name COREGND1 pg pin VDD HM P2 pg type backup power user pg type abc voltage name COREVDD1 pg pin GND HM P2 pg type backup ground voltage name COREGND1 j pin inl direction input related ground pin GND HM P1 related power pin VDD HM P1 pin in2 direction input related ground pin GND HM P2 related power pin VDD HM P2 j pin outl direction input related ground pin GND HM P2 related power pin VDD HM P2 j Creating Feedthrough F
44. Integrated Circuits IEEE Tcl Tk Documentation Tcl Developer Xchange http www tcl tk Power Aware Simulation User s Manual v10 2c 333 Supplemental Information Power Aware Verification of ARM Based Designs 334 Power Aware Simulation User s Manual v10 2c ABCDEFGHIJKLMNOPQRSTUVWXYZ A Accellera 171 B Backus Naur Format 300 BNF 300 D Design flow 14 F Feedthrough 157 H Hard macro 152 IEEE standard for low power 18 L Liberty libraries 35 database 35 Low power 13 IEEE standard for 18 Lower boundary ports 238 M Macro hard 152 Macromodels 152 Messages 136 MTI_LIBERTY_PATH 39 Multi voltage analysis 145 N Named events 160 ze PA GL 13 PA RTL 13 PCF Power Configuration File 299 Power Aware 13 documentation 16 Power Aware verification 170 Power Aware Simulation User s Manual v10 2c Index Power Configuration File 299 Power gating 13 Power intent specification file 19 Power State Table PST 145 203 PST 145 203 U Unified Power Format UPF 19 169 UPF 19 169 170 supported commands 172 V Value converstion table VCT 280 VCT 280 Verilog named events 160 Voltage level shifting 145 335 ABCDEFGHIJKLMNOPQRSTUVWXYZ 336 Power Aware Simulation User s Manual v10 2c End User License Agreement The latest version of the End User License Agreement is available on line at ww
45. MSPA RET PD OFF Time 85 ns Power for domain PD is not ON 0 when retention is enabled for retention elements tb top midl bot latchl File src pa all checks Line 2 Power Domain PD Power Aware Simulation User s Manual v10 2c 79 Automatic Checking Dynamic Checking in Power Aware Clock Latch enable Table 5 3 Dynamic Retention Checks cont Usage Syntax vopt pa_checks rcs Description Example Message Certain Power A ware models require that the clock latch enable must be at a certain value when retention takes place Reports an error when this condition is not satisfied If latch is enabled and can change its value triggering retention can potentially cause race conditions in the stored value This is also a check against such conditions Error vsim 8905 MSPA RET CLK STATE Time 85 ns LatchEn is not at proper level LOW 1 for the retention element s of type AHRLA of power domain PD tb top midl bot latchl File Line 2 Power Domain PD Error vsim 8905 MSPA RET CLK STATE Time 207 ns Clock is not at proper level LOW 1 for the retention element s of type CLRFF of power domain PD tb top midl bot ff File Line 3 Power Domain PD Clock toggle vopt pa_checks rsa Some Power Aware models require that the clock not toggle when the power is down This check helps in monitoring this condition Error vsim PA 8906 MSPA RET SEQ ACT Time 20
46. Manual v10 2c 61 Power Aware Reports UPF Reports Design Element Scopes and Power Domains Corrupted Signals State Elements Retention Signals Design Element Scopes and Power Domains This information identifies the extent of power domains such that all scopes in the design belonging to a particular power domain are listed in this report Format The report format for listing domains scopes and elements is the following power domain Path lt N gt scope element SIM lt gt where e power domain identifies the name of the power domain When power domain is represented by two dashes it indicates that the element was excluded using exclusion rules Path N identifies the hierarchical path of the scope in the rest of the report scope keyword that identifies that this line is a design element scope to assist in using a grep search element identifies the full hierarchical path of the design element its scope SIM optional keyword that identifies a power domain referring to simulation only elements such as processes always blocks or signals e lt gt optional identifies a scope that is present at the power domain boundary Example Excerpt of UPF Commands set scope tb create power domain pd aon include scope create power domain pd elements top vl top vh Example Design Elements Report Excerpt for Scopes and Power D
47. P Rue ECL eee AP LE RE PRSE EO PE E EIS 54 Power DOD stiio s ses iude eias du es ET RARE e Impp Aa Mies Paesi suh 54 Power SWitchl scsi serenite sadna PEINE ERAOLARM quU EE EAD QE ROC UAPU Ted qe RS 53 Retention Strategy ss ooo eed ex ae n Se eei Rx ear eii dude ese sitara s 57 Isolation Strategy cocos REPERTA ERPWRERPEREER Pee eG ELE eee e IMP e EE 57 Level Shifter Strategy sou exor 4 ARHRENGRERRPRENCE AY REEGSRGDURPERIU DER RENS S 58 Power State Tables PSTSs eR imena D ee edn Pika uk CREER Packs 59 Sample Power Architecture Report 24224004 e2 ee0eeebecaseioreeenwaiteceus 60 Design Elements Report 2ic cs4c0s44ase esoGess E ER EORR TRUE se Gases Ghisea seus 61 Design Element Scopes and Power Domains 62 Corrupted Signals ci 22iics idiedasdeeoa Rudi E eA P dex avs es des es 63 Stat Elements EPMMDC 63 Retention Signals PPP 64 Working With A Design Element Report 0 0 0 eee eee eee 65 Behavioral Element Reporting 2i2 lt si esas us e iR E REE ERR gh ot ic e E E Ru 67 Chapter 5 Automatic C BeCIIBE a aas io PEER VRRDRCI CR FEDERE DERE o Pres Ce pre ORS 69 Static and Dynamic Checking Overview 0 0 cece eee eee eens 69 Level Shifter Checking iaces DRERRI Gade tad Rp DRE ERA RR x RU RR E 69 fsolaton CBECEBIE 256454 aise eine a a PUDE RUNE CRF DIM E SES 70 Static Checking in Power Aware Vs sonzechkei Aera x a c re ht RSR ERAT ESAE ER KS 70 Usage Notes for Static Checking 2 203 a
48. Power Aware simulation is written as a comment at the end of the saved UPF file This file contains supported commands as interpreted by Power Aware simulation which are written after performing various operations such as semantic checks resolving net port connections and resolving design objects related to a command Note that save upf dumps the complete power intent of the scope not just the UPF commands in effect at the point where save upf command is given Uninterpreted mode 230 Power Aware Simulation User s Manual v10 2c UPF Commands and Reference save upf In uninterpreted mode all the UPF commands are saved in the output file without any processing even if the commands are not supported by Power Aware simulation This mode filters out any TCL specific constructs in the UPF and writes only the UPF commands to the output UPF file To write the output file in uninterpreted mode do either of the following o Specify save upf u Note that in uninterpreted mode the scope and version arguments of the save upf command are not supported Also the saved UPF file is a complete replica of the original UPF file but without any TCL constructs o Specify vopt pa dumpupf filename This saves the UPF file in uninterpreted mode to the filename file Power Aware Simulation User s Manual v10 2c 231 UPF Commands and Reference set design attributes set design attributes Support for UPF Standard v1 0 no v2 0
49. RTL and higher abstraction simulations Together both sets of functionality can be used to verify the correctness of the model The example below shows the use of conditional compilation to control inclusion of functional code the Power Aware code or both in a simulation Modeling using conditional compilation implies that the model would be compiled twice into different libraries for use in gate level and RTL simulations An alternative would be the use of parameters and conditional generates to control the inclusion of functionality In any case the ability to specify a single model for use at multiple abstraction levels simplifies the support and maintenance associated with the development and deployment of Power Aware IP models Named Events in Power Aware The following declarations of named events in a Power Aware Verilog model control simulator activity as indicated 160 Power Aware Simulation User s Manual v10 2c Model Construction for Power Aware Simulation Named Events in Power Aware event pa store value The simulator stores the current value of the inferred registers or latches that the Power Aware model is associated within the power specification file event pa store x The simulator stores a corruption value for the inferred registers or latches Corruption values depend on the type of data inferring the register or latch A table mapping corruption values to data types is specified separately event pa restore value
50. Race Check tb CPU1 out alu UPF ISO pa iso cell checks vec iso port toggle pos iso toggle posedge 0 3 Isolation Race Check tb CPU1 out alu UPF ISO pa iso cell checks vec iso port toggle neg iso toggle negedge 0 2 Toggle Check tb CPU1 out alu UPF ISO pa iso cell checks vec mspa iso on act 0 0 Missing Level Shifter Power Aware Simulation User s Manual v10 2c 103 Power Aware Coverage Power Aware Coverage Report Reference tb CPU1 pa missing ls check 1 mspa upf missing ls chk 0 4 Missing Isolation tb CPU1 pa missing iso check 2 mspa upf missing iso chk 0 4 Control Signal Corruption Check tb CPU1 pa upf control check 1 mspa ctrl crpt chk 0 5 Control Signal Corruption Check tb CPU1 RAM1 pa rcs check vec 6 rcs checks 2 ctrl chk 3 3 104 Power Aware Simulation User s Manual v10 2c Chapter 7 Visualization of Power Aware Operations You can use ModelSim GUI windows to visualize aspects of your Power Aware design and simulation The following sections describe the ModelSim windows provided for Power Aware visualization e UPF Object Display The Objects Structure and Wave windows provide visibility into UPF objects Power Aware Schematic Display The Schematic window provides color coding of design elements in different power domains Power Aware Waveform Display The Wave window provides highlighting of bias corruption and isolation Power State and Transition Dis
51. Simulation User s Manual v10 2c 3 Table of Contents Capturing Information for Post simulation Debug llleleeeeeleeeees 38 Debugging Designs Containing Liberty Cells llle eese 39 Applying Power Intent to the Design 00sec eee eee leen 39 Detection of Gate level Cells oc cover guseu se REESE ERERI EG P PEERS ERRARE 40 Detection of Power Management Cells 00 0 2 cee eee ee ene 40 Automatic Insertion of Power Management Cells 0 0 0 0 e eee eee ee 42 Automatic Corruption and Retention of UDPs 0 0c eee eee 42 UDP Corruption and Retention Modes 0 00 0 cece eee eee ee 42 Chapter 4 Power Aware Repor s i ass skr o qua ir t anier E Coe euees EDE dnc KR p 45 Generating Reports for Power Aware 0 0 cece eee tenet nee 45 How to Generate a Report with vopt pa_genrpt 0 0 0 0 eee ee eee ee 45 WIPE Reports bete espe rime eid ease Sete caSee ede cast ca dees qvae re eq ed 46 UPF Power Intent Report 24 004 eer da uon dore due pra ah ds eod ORA dela e 47 Example of UPF File and Power Intent Report 0 0 0 cee eee ee eee 49 UPF Static REPO o2 zai eGenp 33 sade ago Mocs ng dp X aes BAU eRe SUR dap ER deg 51 Example of UPF Static Report File 15 52secest RR Rn x9 REIR 51 Static Checking UPF REpOLDss a sctueo nah i ohare e IHE C Eo Pr d 52 Dynamic UPF Report 22 cies p RE IDRETES RU E RE Ax x RE e UR RE Rep RID 33 Architecture Report 2 oo Sex EXE
52. Specify in either a UPF file vopt pa upf or a Tcl file vopt pa tclfile Power Aware Simulation User s Manual v10 2c 133 Power Aware Commands and Options Additional Commands You Can Use with Power Aware set related supply net Syntax set related supply net object list objects reset power power net name ground ground net name Arguments object list objects List of ports or pins that is to have a related power or ground supply defined Pins or ports are referenced relative to the active scope e power power net name The related supply power net referenced relative to the active scope You can specify this switch by itself or in combination with ground ground ground net name The related supply ground net referenced relative to the active scope You can specify this switch by itself or in combination with power reset not currently supported Description Allows associating an instance signal pin or a hierarchical port with specific supply nets Thus you can create a supply net based on supply pins so you can specify your related supplies of cells Specify with vopt pa upfextensions see Using pa upfextensions Power Aware simulation internally maps this command to the set port attributes command that you specify in the UPF file specifically the following arguments related power pin power net name related ground pin ground net name Note th
53. applies to power control statements power model mapping statements and voltage domain statements 316 Power Aware Simulation User s Manual v10 2c Power Configuration File Reference Rule Precedence When a rule is defined for an instance and a rule is defined for a signal belonging to that instance at same hierarchical level then for that signal the rule defined for the signal takes precedence over the rule defined for the process In case more than one rule is defined at the same power element a fatal error shall be reported and no verification will be terminated Power Aware Simulation User s Manual v10 2c 317 Power Configuration File Reference Rule Precedence 318 Power Aware Simulation User s Manual v10 2c Appendix E Supplemental Information This appendix provides supplemental information on applications of Power A ware Power Aware Verification of ARM Based Designs This section contains an application note written by Ping Yeung and Erich Marschner of Mentor Graphics Corporation Abstract Power dissipation has become a key constraint for the design of today s complex chips Minimizing power dissipation is essential for battery powered portable devices as well as for reducing cooling requirements for non portable systems Such minimization requires active power management built into a device In a System on Chip SoC design with active power management various subsystems can be independently powered up or dow
54. cell type but map to different retention models then the first mapping statement is used and a warning message issued The precedence of Power Aware cell types is as follows from highest to lowest precedence a Clock enable specific and sequential element specific types FF CKHI FF CKLO LA ENHI LA ENLO b Clock enable free sequential element specific types FF CKFR LA ENFR c Clock enable specific sequential element generic types ANY CKHI ANY CKLO d Clock enable free sequential element generic type ANY CKFR The default mapping for an inferred latch is to LA ENHI This default mapping is considered only under the following conditions The enable condition for latches may be complex whether the latch is intentional or unintentional For enable conditions that are not simply low or high values such as an equality expression e g en cond 101 the mapping will be made to an LA ENHI model if such a mapping is specified where the true condition is considered high Forlatches inferred from a typically unintentional situation such as the failure to assign all outputs in all branches of a process the inferred latch will be mapped to a LA ENHI Power Aware type e If there is an ambiguity as to which latch Power Aware type to map an inferred latch it will be mapped to LA ENHI The power model mapping statement may be terminated by a CRLF or by a semicolon If terminated by a CRLF then line continuation
55. debug by loading the WLF file containing the information as follows vsim view vsim wlf Power State and Transition Display Because power domains are not limited to two states ON or OFF and multi voltage capability allows designs to assign different voltage levels to different states tracking combinations of states in different power domains has become increasingly difficult Power State and Transition Concepts In UPF you can add states on the following objects and model a Power Aware state machine PASM corresponding to each PST resulting from the add_pst_state UPF command e Supply port resulting from the add port state UPF command e Supply net resulting when a PST contains a supply net entry Power domain resulting from the add power state UPF command e Supply sets resulting from the add power state UPF command A power state table PST defines the allowable combinations of power states of supply ports and nets those combinations of states that can exist at the same time during simulation of the design As a result changing the power state supply port nets changes the state of PST Power Aware Simulation User s Manual v10 2c 115 Visualization of Power Aware Operations Power State and Transition Display The UPF command add power state adds power states on power domains and supply sets The power states associated with supply sets determine the simulation semantics of connected design elements
56. design must be partitioned into separate functional areas that can be independently powered Additional logic must be inserted into the design to perform special functions such as power switching state retention isolation and level shifting These additional components constitute the power management architecture for a given system Operating Modes Designing the power management architecture for a given system starts with characterization of the functions and operating modes of the system Since the goal of active power management is to optimize the use of power based on the function and performance required of the system at any given time the first step involves identifying the distinct combinations of functionality and performance that will be required of the device in use Analysis of the set of distinct operating modes allows the designer to determine how to partition the design into independently powered subsystems or subcomponents so that any given operating mode can be supported by providing the necessary subset of system components with the appropriate power For example Figure E 1 shows a block diagram of a design that has two operating modes ON and SLEEP 322 Power Aware Simulation User s Manual v10 2c Supplemental Information Power Aware Verification of ARM Based Designs Figure E 1 A Power Managed Design PD top DUT Controller gt 45 s mc0 OTADA T 2E Interleaver i0 PD interleaver 0 81V Always
57. doesn t exist in library lib1 Power Aware Simulation User s Manual v10 2c 211 UPF Commands and Reference load simstate behavior Example C 5 Error Warning Conditions File Contains Wrong Commands It is an error if the specified file contains UPF commands other than set simstate behavior main upf upf version 2 0 set scope tb topl load simstate behavior lib1 file sim upf sim upf set scope midi set simstate behavior ENABLE model mid Vopt Message Error sim upf 1 UPF vopt 9754 Command set scope not allowed in file specified via command load simstate behavior 212 Power Aware Simulation User s Manual v10 2c UPF Commands and Reference load upf load upf Support for UPF Standard v1 0 yes v2 0 yes Arguments Argument Comments Restrictions scope version Power Aware Simulation User s Manual v10 2c 213 UPF Commands and Reference load upf protected load upf protected Support for UPF Standard v1 0 no v2 0 yes Arguments Argument Comments Restrictions hide globals params scope version Usage Notes This command loads a UPF file in a protected environment that prevents corruption of existing variables 214 Power Aware Simulation User s Manual v10 2c map isolation cell Support for UPF Standard v1 0 no v2 0 yes Arguments Argument filename UPF Commands and Reference map isolation cell Com
58. for Power Aware simulation Foralist of all values refer to Table A 1 For additional reference information refer to the vopt command in the Reference Manual Foralist of static and dynamic checks according to elements defined for a given power domain refer to Table 5 7 78 Power Aware Simulation User s Manual v10 2c Automatic Checking Dynamic Checking in Power Aware To specify more than one checking use the plus operator between values For example vopt pa_checks ropt cpta To enable all dynamic checks specify the pa_checks d argument Dynamic Retention Checking You can specify any of the values in Table 5 3 to provide retention checking Table 5 3 Dynamic Retention Checks Usage Syntax Description Example Message Power off vopt pa checks rop Reports that there were retention signals mapped to the power domain However these signals were not asserted when the power was switched off Error vsim 8903 MSPA RET OFF PSO Time 35 ns Retention control x for the following retention elements of power domain PD is not asserted during power shut down tb top mid1 bot_latch1 File src pa_all_checks Line 2 Power Domain PD Power on vopt pa checks rpo Reports that there was an error in the sequence of triggering of the retention and power signal For retention to succeed the power should be high However this check is triggered when that is not the case Error vsim 8904
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60. mode is indicated by blue highlighting Corruption is indicated by red cross hatch highlighting Isolation is indicated by green highlighting Tip When you hover the mouse cursor over an isolation highlight region a balloon popup appears This indicates the clamp value and location along with he actual signal value Also when you click to expand an isolation highlighted signal on the to the left of the signal name associated signals are displayed that provide more information about the isolation Figure 7 7 Power Aware Highlighting in the Wave Window EE Bias Mode Corruption Isolation blue red green 114 Power Aware Simulation User s Manual v10 2c Visualization of Power Aware Operations Power State and Transition Display Using Power Aware Highlighting To enable Power Aware highlighting use the following flow 1 Enable highlighting during elaboration by adding the pa enable highlight option to your vopt command line 2 Enable highlighting during simulation by adding the pa highlight option to the vsim command This argument enables the generation of the WLF data used by the Wave window to display the highlighting 3 Enable highlighting in the GUI by selecting Wave gt Tools gt Wave Preferences gt Display tab gt PA waveform highlighting You only need to perform this action upon your first invocation or if your GUI settings are reset 4 View Power Aware activity in post simulation
61. off and mediate interactions between portions of the system that are powered differently Power Aware simulation makes it possible to model these power management aspects of a system in simulation even before the power management features have been implemented in the design To do so additional logic is included in the simulation model This additional logic does the following Defines the power management architecture to be imposed on the design Implements the behavior of power management elements e Adapts the behavior of the design itself to reflect changes in power Power Aware Simulation User s Manual v10 2c 19 Concepts for Using Power Aware Simulation Power Aware Modeling To run Power Aware simulation the normal build process for constructing the simulation model is modified so that this additional logic can be added Power Aware simulation provides default Verilog models for the behavior of power management elements and the behavior of the design under active power management The default models are provided in your installation directory at the following location install dir verilog src upf pack With the model mapping capability defined in the power intent specification you can simulate power on power off and retention using a model that accurately describes the power down power up sequence power down up behavior as well as the save and restore sequence and behavior based on actual silicon You can use Power Aware
62. on state ISO PWR amp amp get supply on state ISO GND always negedge ISO pg sig assert ISO CTRL else Sdisplay n At time 0d isolation supply is switched OFF during isolation period ISO CTRL b time ISO CTRL endmodule Design module tb top top endmodule module top mid vl testl vl mid vl test2 vl mid vl test3 vl endmodule 186 Power Aware Simulation User s Manual v10 2c UPF Commands and Reference bind checker module mid v1l endmodule e UPF upf_version 2 0 set_scope tb TOP create_supply_net ISO_PWR create supply net ISO GND create supply port ISO PWR PORT create supply port ISO GND PORT connect supply net ISO PWR port ISO PWR PORT connect supply net ISO GND port ISO GND PORT create supply set ISO SS function power ISO PWR function ground ISO GND create power domain PD mid1 supply primary set isolation iso PD mid1 domain PD_mid1 applies to outputs isolation supply set ISO SS location self isolation signal ctrl bind checker iso supply chk module ISO SUPPLY CHECKER bind to mid v1 ports ISO CTRL PD midil iso PD midi1 isolation signal ISO PWR ISO SS power ISO GND ISO SS ground ISO_SS Power Aware simulation inserts ISO SUPPLY CHECKER in all instances of the mid vl module in your design You should ensu
63. pa release register initial begin 0 if pa timeO0param 1 amp amp PWR 1 bx PWR 1 5b0 gt pa_corrupt_register end always negedge PWR gt pa_corrupt_register always posedge PWR gt endmodule pa_release_register Example Register Model The following Verilog code represents a behavioral model of a Clock Free Retention Flip Flop CFRFF modified to use many of the listed named events The RTL verification event generation functionality is separated from the gate level cell functionality to demonstrate how a single model can be defined for use at both RTL and gate levels for Power Aware verification as well as facilitat e the verification of both functional aspects of the model module CFRFF PWR RET CLK SET RESET ifdef PA GLS FUNC Extra ports would be left unconnected D Q It isn t necessary to conditionally endif compile them out for RTL PA G input PWR input RET input CLK input SET Not used in this model input RESET ifdef PA Gl LS PFUNC Power Aware Simulation User s Manual v10 2c 165 Model Construction for Power Aware Simulation Example Register Model 166 input D output Q reg Q reg reg q reg reg q ret reg ret value reg restore value reg posedge power w reset reg negedge ret w reset reg reset active endif PA GLS FUNC ifdef PA RTL FUNC MG event declar
64. partial on translation FULL ON off tools questa Example C 10 Error Warning Conditions Same String in Different Lists It is an error if the same string for a tool name occurs in both the full on tools and off tools lists In the following example for Power Aware simulation the error occur only if questa tool name is specified in both the full on tools and off tools string lists upf version 2 0 set scope tb set partial on translation OFF full on tools questa off tools questa Vopt Message Error test upf 5 UPF vopt 9762 The same string occurs in both the full on tools and off tools string lists 244 Power Aware Simulation User s Manual v10 2c UPF Commands and Reference set partial on translation Usage set partial on translation OFF FULL ON full on tools string list off tools string list Example C 11 Error Warning Conditions set partial on translation Invoked More Than Once A Warning message is issued if set partial on translation is invoked more than once upf version 2 0 set scope tb set partial on translation OFF full on tools questa set partial on translation FULL ON Vopt Message Warning test upf 6 UPF vopt 9763 Command set partial on translation invoked more than once Ignoring previous specification s of this command Power Aware Simulation User s Manual v10 2c 245 UPF Commands and Reference set pin related supply set pin related supply Suppo
65. pg type attribute Value of the pg type attribute of the port matches with the pg type value specified using UPF commands Simulation semantics of all the design elements whose ports are automatically connected to power supply are disabled see Simulation Semantics for UPF Supply Connections Automatic Connections for Supply Nets You can define automatic connection semantics on individual supply nets using the following UPF command connect supply net pg type domain cells Questa will automatically connect the specified supply net with the supply ports on the specified cell or the design elements within the extent of power domain which fulfills the necessary conditions for automatic connection semantics You can also specify Value Conversion Tables VCTs for automatic connection semantics by using the vct argument 272 Power Aware Simulation User s Manual v10 2c UPF Commands and Reference UPF Supply Connections Using the vct argument has a restriction that all the ports that are connected using connect supply net should have matching types since the type matching for VCT will produce error during connections For example connect supply net snet domain PD pg type primary power vct my sv vct This will produce an error message when domain PD has a VHDL instance contain supply port with pg type primary power and different type and create the connection assuming a 1 bit connection Command Syntax UPF
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67. real is any numerical value that specifies a voltage threshold Use this argument with the vopt command when you know that level shifting is not required for particular range of voltage differences You can then specify a global threshold otherwise Power Aware simulation will flag missing level shifter errors even if the potential difference between two domains is within an acceptable range Level Shifter Instances If you have used the set level shifter instance command in a UPF file to instantiate level shifters Power Aware simulation will detect those instances and perform level shifting checks on them see Static Checking in Power Aware An instance is recognized as a level shifter instance in any of the following cases The level shifter instance is specified with instance argument of set level shifter command Fora gate level design any of the following o Theis level shifter attribute is specified for the module Example is level shifter 1 module 1s buf pg type primary power input logic pwr rail 146 Power Aware Simulation User s Manual v10 2c Power Aware Commands and Options Restricting Isolation and Level Shifting on a Port pg type primary ground input logic gnd rail level shifter data pin 1 input data output logic out assign out data endmodule o Instantiation has prefix or suffix string for level shifter specified with name format UPF command Example LVL
68. running Power A ware simulation you should have worked through the following stages of your design flow Design creation RTL architecture Formal verification Definition of power intent After running a Power Aware RTL simulation you would typically use the results to make appropriate topology or performance changes to your power sensitive design blocks After a gate level simulation GLS you would typically make library cell changes based on performance characteristics The scope of Power Aware as a low power solution spans multiple manifestations of design architecture Power Aware Simulation Simulation that includes active power management elements and their behavior The power management architecture is specified in UPF the behavior of those elements is inferred from the UPF specification This relates specifically to Power Aware Simulation Power Aware Verification Collaborative usage of various products and methods for verifying that a design operates correctly under active power management These include power aware simulation for verifying the correct operation of the power management architecture formal verification for verifying correct operation of power control logic and hardware software co verification for verifying that software power control interacts correctly with power control logic This relates to all of the components of the Questa Verification Platform that can be used for Power Aware
69. specifications along with model mappings specify retention sequential objects and both impact the simulated behavior of the design the voltage statement and voltage specification have no simulation semantics defined voltage domain statement POWER VDD tag region definitions voltage specification stmt end voltage specification op voltages vdd level sig op voltages real literal real literal The voltage domain statement begins with the keyword POWER VDD e tag a mnemonic name for the VDD region region definition the same as defined in section Region Definitions op voltages a list of one or more real values that specify the allowable voltages under which the domain may operate in units of volts A list of voltage values provides the ability to specify voltage domains where clock frequency is reduced to lower dynamic power consumption vdd level sig optional specifies a voltage level signal or legal Verilog signal expression This signal must be an integral type Its value indicates which operating voltage level is in operation at any given point in time The integral value shall match the positional value of the operating voltages with the value of 0 corresponding to the first operating voltage level specified 1 corresponding to the 2nd operating voltage level specified etc Power Aware Simulation User s Manual v10 2c 315 Power Configuration File Reference Regular Expression
70. state as a reserved keyword D Detailed Support for supply net type For UPF 2 0 the definition of supply net type was redefined from UPF 1 0 Accellera UPF Standard 1 0 Key changes include 260 ON state changed to FULL ON Ensure you rewrite any UPF v1 0 files to match this change Type state changed from 32 bit vector to an enum Addition of the UNDETERMINED state for supply net type which has the following impact on the power aware functionality Ensure you rewrite any UPF v1 0 files to take account of this new state Oo Power Aware switches can go to the UNDETERMINED state as described in the following situations defined in the IEEE Std 1801 2009 Section 6 20 e Multiple on or partial on conditions are true with different root supply drivers Both off state and on state conditions or on partial state condition are true Any error state condition is true Control signals go to x or z e Simstate of the supply set associated with the switch is anything other than NORMAL For UPF 1 0 under these conditions the output port of the switch would go to the OFF state You can switch to UPF 1 0 type functionality with the vopt pa_upfversion 1 0 option which sets the upf version of the UPF file to UPF 1 0 Due to introduction of this UNDETERMINED state switch output may go to UNDETERMINED state in delta periods if any of these conditions is true due to input delta activities A supply net may go to UNDETER
71. supply expr specifications for that power state of the referenced supply set in the definition of the power state 182 Power Aware Simulation User s Manual v10 2c UPF Commands and Reference add pst state add pst state Support for UPF Standard v1 0 yes v2 0 yes Arguments Argument Comments Restrictions pst state Usage Notes Allows specifying a power state table PST to define states on a supply net Power Aware Simulation User s Manual v10 2c 183 UPF Commands and Reference associate supply set associate supply set Support for UPF Standard v1 0 no v2 0 yes Arguments Comments Restrictions handle All predefined handles for supply set are supported Usage Notes Associates a supply set or supply set ref to a power domain power switch or strategy supply set handle 184 Power Aware Simulation User s Manual v10 2c UPF Commands and Reference bind checker bind checker Support for UPF Standard v1 0 yes v2 0 yes Arguments Comments Restrictions module elements Elements should be relative to the active scope bind to arch ports The net name argument accepts symbolic references Refer to Usage note for additional information Usage Notes Note This command is only supported in the vopt flow This command inserts a checker module into your design without modifying the design code or introducing functional changes ne
72. the instance specification and not to the instances declared below that Corruption of instance outputs will be applied to the outputs of all the instances listed in the POWER statements In the case of an instance declared without nr output corruption will be applied to the outputs of the top of the instance and not to the instances below that That is recursive application of corruption applies only to inferred registers and latches never to outputs Process Definition To identify specific processes within a block instance and not all processes within a block instance the PCF supports the specification of processes individually o p indicates that the region definition applies to only the specified process The HDL path identifies the relative hierarchical path to the process s label The sequential elements in the process and the outputs drivers of the process will be corrupted If two processes in one single instance are controlled by different power control signals the sequential elements of the different processes need to be corrupted separately Power Aware Simulation User s Manual v10 2c 307 Power Configuration File Reference PCF Syntax and Contents Example POWER PDO s top pd11 s1 nr top pd11 w11 p top pd11 c111 p1 top pd11 c112 top global vdd 1 amp top vdl local va d 11 A power island named PDO is defined by the signals top global vdd 1 bit wise anded
73. the name of the simulation ready output file to be generated other vopt args any other vopt arguments used to control optimization Usage Notes Power Aware simulation involves register latch detection in order to identify state elements in the design that need to be corrupted and may need to have their state retained during power down However your design may contain code that is not at the appropriate level of abstraction for register latch detection so you may need to exclude such code from power intent processing Also you may want to exclude parts of the design from Power Aware simulation for other reasons see Excluding Design Elements from Power A ware in Appendix A ModelSim provides additional vopt arguments for Power Aware simulation that you can use when generating the optimized design For more information on these arguments refer to the section ModelSim Commands Used for Power Aware A simulation model created for Power Aware simulation contains specific Power Aware simulation artifacts and cannot be used for normal simulation Simulate After you compile and optimize the design run the vsim command on the optimized design using the pa argument to perform Power Aware simulation pa Enables PA simulation including features for gate level simulation pa lib optional Instructs Questa SIM to load Power A ware information from the specified library If unspecified defaults to the current directory Powe
74. top1 mid1 create supply net VDD N domain pd1 create supply net GND_N domain pd1 Power Aware Simulation User s Manual v10 2c UPF Commands and Reference set simstate behavior Example C 17 Use elements Argument to Override or Specify Simstate Behavior list of elements upf version 2 0 set scope tb topl create power domain pd1 set simstate behavior ENABLE model mid set simstate behavior DISABLE elements mid1 mid2 create supply net VDD N domain pd1 create supply net GND_N domain pd1 Example C 18 Error Warning Conditions lib Argument Without a Library It is an error if the specified library with lib argument does not exist upf version 2 0 set scope tb topl create power domain pdl set simstate behavior ENABLE lib libl Vopt Message Error test upf 4 UPF vopt 9753 Library libl does not exist Example C 19 Error Warning Conditions model Argument Without a Model It is an error if the specified model using model argument does not exist in the specified library using lib argument upf version 2 0 set scope tb topl create power domain pdl set simstate behavior ENABLE model mad lib work Vopt Message Error test upf 4 UPF vopt 9655 Model mad doesn t exist in library work Power Aware Simulation User s Manual v10 2c 257 UPF Commands and Reference set simstate behavior Example C 20 Error Warni
75. type of check with detailed information Command line coverage report assert pa verbose xml Power Aware Simulation User s Manual v10 2c 97 Power Aware Coverage Power Aware Coverage Analysis e GUI o Menu Tools gt Coverage Report gt Text o Coverage Text Report dialog box e Verbosity Details Coverage Type Assertions and Power Aware Output Mode XML Format It is suggested that you output to XML format for usability You can then open the xml file with a spreadsheet program or other XML parser Report Pathname Specify a filename with the xml suffix Refer to the section Power Aware Coverage Verbose Report for a detailed description of this report Power Aware State Coverage Summary This produces a summary report showing coverage information organized by state machine instance Command ine coverage report pa e GUI o Menu Tools gt Coverage Report gt Text o Coverage Text Report dialog box e Verbosity Default Coverage Type Power Aware Refer to the section Power Aware Coverage Summary for a detailed description of this report Power Aware State Coverage Detailed Report This produces a detailed report showing coverage information organized by machine instance Command line coverage report pa details GUI o Menu Tools Coverage Report Text o Coverage Text Report dialog box e Verbosity Details 98 Power Aware Simulation User s Manual v10 2c Power Aware Coverage
76. understanding the structure of your design and having the ability to run ModelSim plus more generally your goals of using simulation and verification software products The purpose of this manual is to provide basic usage and reference information on how to run a Power Aware simulation in ModelSim The primary focus is on how to define the power intent of your design and then apply your conventional ModelSim simulation flow to verify power gating behavior Note that there are some areas related to Power Aware operation that this manual is not intended to cover UPF standards The UPF Commands and Reference appendix lists the UPF commands and arguments that are currently supported for both v1 0 and v2 0 of the UPF standard However complete usage information from those standards is not duplicated in this manual Basic and advanced ModelSim usage Please refer to the other manuals of ModelSim documentation for information on operations related to Power Aware simulation such as command usage the graphical user interface GUI design optimization waveform analysis and finite state machines Power design Reporting power estimation or creating an RTL architecture for optimized power implementation Specifically the scope of this manual falls into the following broad areas Usage Terminology definitions Basic operating instructions for Power Aware simulation ModelSim commands specific to Power Aware Differen
77. vhdl 12 Model Default UPF Retention 1 tb top vh qd regvh 2 tb top vh q latvh 2 Scope tb top vl File reg vl v 1 Model Default UPF Retention 1 tb top vl q regvl 2 tb top vl q latvl Where the sections contain the following information e Section 1 Defines the retention strategy e Section 2 Specifies the retention supplies listing the full hierarchical path of the supply nets e Section 3 Specifies the retention control signals and the retention sense e Section 4 Specifies signals that have retention applied Isolation Strategy Report information for the isolation strategy is listed under this heading followed by the name of the strategy and the reference to the UPF source file where the strategy was created UPF Commands for Isolation set isolation pd isolation domain pd isolation power net V pd net clamp value 1 applies to outputs set isolation control pd isolation domain pd isolation signal iso isolation sense high location parent Power Aware Simulation User s Manual v10 2c 57 Power Aware Reports UPF Reports Report File Sections and Subheadings 1 Isolation Strategy pd isolation File test upf 45 2 Isolation Supplies power tb top V pd net ground tb top G pd net 3 Isolation Control tb top iso Isolation Sense HIGH Clamp Value 1 Location parent 4 Isolated Signals 1 Signal tb top q combvl 2 Signal tb top q latvl 3 Signal
78. vsim cont Using pa enable and pa disable The values for the pa enable and pa disable arguments to the vopt command listed in Table A 3 allow you to enable or disable certain actions that performed during Power Aware simulation Syntax vopt pa_enable lt value gt lt value gt vopt pa_disable lt value gt lt value gt Description Each argument uses the same set of values which means using a value with either argument toggles that action from its default state or from a previously specified state Table A 3 lists each value a brief description of the Power Aware action performed and which argument used for that value by default e You can specify one or more values for either argument there is no order dependency when specifying multiple values To specify more than one value for either argument use the operator between values For example vopt pa_enable lowerboundary insertiso vopt pa_disable sourcesink relatedsupplies Table A 3 Power Aware Actions for vopt pa enable and pa disable Action Default ackportbehavior For UPF 2 0 power switches with the pa enable ack port switch require a supply set pa enable Issues an error if this condition is not met pa disable allows violation of this condition and uses an always on supply set Essentially reverting to UPF 1 0 functionality anonupfobjects Create anonymous supply sets or nets for pa disable future replaceme
79. with top vd I local vdd 11 In other words the power is ON for PDO only when both vdd and vdd 11 are on 1 When the power for PDO is off the following are corrupted The signal top pdl I sl The block instance top pdl I w11 inferred registers latches and outputs The inferred registers or latches for the process top pd1 1 c112 Example POWER VD1 top vd1 top global vdd1 The instance top vdl is controlled by power control signal top global vddl If corruption extent is set to ALL then the outputs of top vd1 are corrupted when top global vddl is 0 as are inferred registers and latches in top vd and all sub blocks below top vdl Example POWER PD1 top pdl1 top global vddl amp top vdl local vdd 12 POWER signal always on s top pdil outi 1 With this power specification file the output top pd11 out will not be corrupted when the power for power domain PD1 goes off Example Note This example describes the combinatorial logic powered by top VDD1 which is an output out of an instance m2 00 which is powered from VDD2 POWER PD1 s top m2 00 out1 top VDD1 308 Power Aware Simulation User s Manual v10 2c Power Configuration File Reference PCF Syntax and Contents POWER PDO top m2 00 top VDD2 This means if the VDD1 goes off the out1 needs to go X but VDD2 has no effect on t
80. working directory or to a library that you can specify using the pa lib switch 3 If you are importing a UPF package into a Verilog test bench or file and the mtiUPF variable is not defined in your modelsim ini file you must use the vlog command with the L argument to compile the test bench as follows vlog filename L mtiUPF Note that this variable is defined by default so you generally do not have to do this Alternatively if you want to use a UPF package with VHDL you must include it in your VHDL file as follows library IEEE use IEEE UPF all UPF Standards At this time two versions of the UPF standard have been published Version 1 0 of the UPF Standard Version 2 0 of the UPF Standard IEEE Std 1801 2009 Power A ware simulation currently supports v2 0 of the UPF standard by default 170 Power Aware Simulation User s Manual v10 2c UPF Commands and Reference UPF Standards In addition Power Aware simulation also supports portions of v1 0 published by Accellera which you can implement in a given UPF file by inserting the following text as the first line upf version 1 0 Version 1 0 of the UPF Standard The technological foundation for the UPF standard was originally developed by Accellera Organization Inc UPF 1 0 was approved as an Accellera standard in February 2007 Version 1 0 of the standard was administered by the P1801 Low Power Working Group of the IEEE For more information on this workin
81. written with respect to the DUT top level module other vopt args any other vsim arguments used to control simulation Then in simulation include the pa top argument on the vsim command for example vsim TB top pa top DUT path pa other vsim args where e TB top is the name of the top level module of the test bench e pa top DUT path is the path from the test bench top to the design top instance e pa invokes simulation in Power Aware mode other vsim args any other vsim arguments used to control simulation Limitations Only one module can be specified as a PDU with pa_top in a given simulation Power Aware Simulation Debug This section provides additional information on setting up yhour Power Aware simulation for post sim debug Capturing Information for Post simulation Debug Power Aware simulation allows you to create a database of information that for analyzing the results after completion of a live simulation This is most useful when you need to debug a power aware simulation that has been run in a regression setup or another situation where you are not able to debug a live simulation The database contains information that allows you to perform supply network debugging and information for colorizing power information in the Dataflow window To create the post simulation debug database use the pa_enable supplynetworkdebug option on the vopt command in the three step stan
82. 0 eese 289 Method 2 Isolation needs to b added iiis acess ease tabs Ry Rx E REUS ERES 289 Specifying Isolation Cells 44 5 date eer e ACA RR UR RH RE CAU RO S aay 290 Fic PT 201 Defining Retention xu vescne Rex REG ERR RE RES a EE d ACER RR RR 291 retention Supply 8602s spes wal suspen 9 Q3 REOR bade da RO ec ds ed cin UN 202 sno Ielentlol rzada eX kv ad e aA RR Gd d e x ra doe DER Sad cR Ad A Rd 293 us _rete tion us DISP goed s i pr PC PERO FF TA C TE ERTER ERENS 295 Appendix D Power Configuration File Referente ueawwsexckeer ther n EY Ea PC RC AA ERES 299 Power Specification File iiid en e E RE GU REGE RGUDE ees a KG e bene aan ee 299 FORMA hy pit eRe awe dhe sa PES eS Sa gays E iR mordax 200 Using a PCF as Part of Power Aware Verification 0 0 0 cece ee eee eee 299 PCF Syntax and Cont nts asss sisi asss tiesas EE ROTE CREE OLRA d hd acts esses 300 Basic PCF Statement L ypess iius RR RR RR XAR x REX RR RE LEER RE 300 Statement Termination eese edes s hp a koe RECETA RE RE ERA PRETI essen Ep 301 Header Statement os ou odekesuexlskes ERA REA IMP ELA Aha MEN Paci e ut 301 Context Statements 5 24 esce reena e CEPERCAPRC RARE CARP KRE ROC KaqUE EQ PAS QNS 302 Scope SGINE METTE 303 Variable Statement se cess ether eeen hese RE REOR RrRRCRER I GEE i M ee hele 303 Ine We SCGIUOIDBIE van oie sS tee eu nee ee ei neia dhe ONE Ae RERGE twee sees 304 Corruption Extent Statement 22 sc2bsiedohactcasadalieas GE HR ERRARE d
83. 0000 170 UPF Standards 2 442406 ves e e aee XGUDR EORR RA COR UE ORC EY C ORE CREER RR RR 170 Version 1 0 of the UPF Standard sepu op pesa Ey aaxpRXX UP SR A RGqES 171 Version 2 0 of the UPF Standard IEEE Std 1801 2009 02054 171 Syntax and Semantic Differences Between UPF 1 0 and UPF2 0 171 UPF 2 0 Syntax Differences udce ou ea ieee ec ex e dr eRrt ea rex re dar eek 172 UPF 2 0 Semantic DUTerenbeSa cud eR qe ERR REC X RAM dee lt eeeeye REIR RR KEq 172 Supported UPF C ommoatids es e656 acs ches aden eae GASES HE ee wea abe Gh ee swe ae Nene 172 add domain elements nece Bed eset reedene netini eaueeedeed Seda ges Ame RE 177 add OH ES Lese quac bed e gel hg ye eire eu ine arenae sensed trendiest 178 add power SAGs Loic Er EQ RE aC OE REF dea EX PA EGER ERS 179 add pst ME Sd due e al dee SS e dp e dol as Ra RUM REA RUE ab UE LN 183 associate supply Sel ip eka re RARE don end C ER Ados CREER quce C e abad eds 184 DING Checker s es 35 00 42h doi AR SOWA OS HORROR sais 185 connect logic Nel sese acer esa Rex OR Rt A RR OR OEE 4 ORE OER ETA eee RR RNS 188 COMNECH SUDDTS MCU basa touc RNa Syn aS Pace Cana x os 19 Powe we 189 CONNEC supply SED ess een Peet ede hiri REEF EPA ERA RE nee ease Mie ERR 190 create composite domal es vi resi qu rer t henr Et Eor PETER CHI TM CHR e 191 eredte DgISupE Votes tee eeu die ee eta esee wes UE VexE RUN PERS a Pp Esos 197 Greste loric Net aoi quedo RRUR HH RICE eoee even
84. 06 Power Aware Simulation User s Manual v10 2c Power Configuration File Reference PCF Syntax and Contents e Signal Definition o S specifies that the given signal Aidl path is part of the power island and must be corrupted on power down The signal is the lowest level of granularity for power region definition Instance Definition Instance regions are recursive by default That is the corruption includes the specified instance and extends to any additional instances contained within the design hierarchy sub tree rooted at the specified instance through the lowest leaves of that sub tree You can target individual instances within generate using two underscore characters __ instead of square brackets o i For block instances the argument i is optional since it is the only region definition that does not require a argument to identify the kind of region It is recommended that you specify the i argument for clarity o nr If the corruption should not extend beyond the immediately specified instance then you can specify the nr argument since nr specifies non recursive corruption Note The nr argument applies to all instance names that match a regular expression The nr argument is meaningful only during all corruption CEXTENT ALL When you specify this argument the simulator applies the corruption only to the inferred registers and latches contained in the root of the sub tree defined by
85. 2c 7T Automatic Checking Dynamic Checking in Power Aware Inferred type Valid count 1 Source port tb TOP boti outi bot LowConn Domain pd bot gt Sink port tb TO P bot2 in2 bot LowConn Domain pd aon Note Sometimes you may find the level shifter count for a particular source to sink path may be 0 This happens when there is only one level shifter identified for insertion at that boundary even though there are multiple fanouts possible but the value for set_level_shifter location is not specified as fanout In that case the level shifter insertion is counted for only one of the paths while the other paths will have level shifter counts reported as 0 Dynamic Checking in Power Aware Use the pa checks argument of the vopt command to perform more comprehensive dynamic rule checking to validate the behavior of power intent and specification in the designs The values you specify activate dynamic checking of signals for various power conditions Dynamic Retention Checking Dynamic Isolation Checking Dynamic Level Shifter Checking Miscellaneous Dynamic Checking o Toggle o Control Signal Corruption Checking o Always On Power Domain Checking o Power Domain Status Table 5 7 shows a quick reference comparison of static and dynamic checks Usage Notes The pa checks argument of the vopt command has numerous possible values that you can assign to enable either dynamic or static checking
86. 5 eder en ee S ue ee eee ee eee aor dr ewes een qol Nor oer 225 quan Dsbe s ies sauna kaos eee ceo ew See eee eG Se ee Ge eee ee ERAS xd 226 QUCty pst SIMIC sore R Je een eed ER RENGARSRRE EAE RENT PE PX RGG GE REESE 227 query supply H t one curd eed CERE CE CENA CASA REOR eee ee deee RE E RUP 228 query Supply POM seio us eddie xd ra gates oe Gas s dU ario eR eq bdo d ae etre 220 Power Aware Simulation User s Manual v10 2c 7 Table of Contents SuyE HDI ccekenrsebeE as dubpeRIX Re REPRE Qu eb See cee PEE EA PEE ED ESTEE Ed 230 set design attributes 25654 ers ERERSRS MASQUER REESE ERG E REA ds 232 SEL SUCSION TODOS ptu gedaan REC Beta ce Saeed LIKES IE DRE RERO POM 233 set domain Supply Heb ees b eed eo ese RR xx a ex LPS AF RARE C qnd b pxRCR SE ERE 234 set isolation e See ERI EXE FG UeRNNE Peut RECA TUI PI qe PEE REI dUeREX ERE 235 SEE sola COntOl s eio devo dO Vus VERI eux NRI SE PIG seed PIE QAI EI 239 set level shilftet 2 a vere e aeree esa due ea 240 Bet parual on SANSA Less ora score IRR sa dee Poet RC RR CLR 243 set pin related s pply 2 2 4 cces s e rh RR P RR REY aun RE Sd C ES 246 SEL port AMIDES lt b Fook oases cab Reh eU bate ORO lc eg OA edd aac d a die 247 SEL power SwHOh iiiiepaxahas ek ka ba MER adeste RR EERSGadarceRPARA E 249 TTu 250 ser retention Control duo os queo e Ede ns eeu a ed ck eaa d Edu aee 252 Sel SCOPE e ui sod ee RO RE EORR ERU RI CREE eee wea nee RP ECCE CE ERE 253 set_si
87. 8 ns clock toggled during retention period for retention element s tb top midl bot ff 80 vopt pa_checks r Power Aware Simulation User s Manual v10 2c Automatic Checking Dynamic Checking in Power Aware Dynamic Isolation Checking Isolation checks trigger messages when a particular isolation strategy has failed or a noise has been detected in isolating a particular hierarchy Table 5 4 Dynamic Isolation Checks Check Usage Syntax Description Example Message Isolation vopt pa_checks icp Ensures isolation cell is clamping to correct clamp Clamp Value value specified in UPF file Catches any functional Check issue in isolation cell inserted in RTL or applied isolation Performed during active isolation period Error vsim 8930 MSPA ISO CLAMP CHK Time 40 ns Isolated port for isolation cell strategy iso PD mid2 2 on port tb TOP mid2 in2 bot having value x is different from clamp value 1 during isolation period File test upf Line 125 Power Domain PD_mid2 Isolation vopt pa checks idp Flags violation if isolation control of isolation Disable cell strategy is disabled during power shut OFF of Protocol source power domain power domain of driving ports Check and sink power domain ON Error vsim 8919 MSPA ISO DIS PG Time 250 ns Isolation control is disabled during power shut OFF 0 for the following Port tb TOP mid3 in2 bot 3 2 File test upf Line 113 Power D
88. 9 2 Sireno O AE SARM 9 e 286 QQQQahn Ll EM MI To Search y 6 vddi_p vddo_p vddi w top i pwr uw vddi w B2 ne Using VCT Commands You can use the create upf2hdl vct and create hdl2upf vct commands in the UPF file for modeling complex connections between a supply net and RTL port Power Aware simulation also automatically inserts VCT for pins detected as power and ground pins when you specify vopt pa upfextensions Examples The following examples show the create upf2hdl vct and create hdl2upf vct commands in a UPF file create hdl2upf vct VHDL SL2UPF hdl type vhdl table U OFF Ox Co ei Cz CL C Cw OFF OFF ON OFF OFF ON OFF OFF create upf2hdl vct UPF GNDZERO2SV LOGIC 280 Power Aware Simulation User s Manual v10 2c UPF Commands and Reference Value Conversion Tables hdl type sv table PARTIAL ON X OFF 1 ON 0 EE If VCT definition for a connection is not applicable or fails then default 1 bit connection semantics will be applied For example module memory input gnd endmodule connect_supply_net gnd_switchable ports mem_sv gnd vct SV_LOGIC2UPF_GNDZERO Data flow for the connection is UPF to RTL but VCT is specified as RTL to UPF Hence specified VCT is not applicable Limitations Only the following HDL data types are supported e System Verilog logic bit
89. 9814 You can use the warning argument of vopt to change the severity of this message to a warning so that simulation may continue vopt warning 9814 Refer to Power Aware Messages for more information on changing the level of message severity Example 248 set port attributes ports top out source off clamp 1 Power Aware Simulation User s Manual v10 2c UPF Commands and Reference set power switch set power switch Support for UPF Standard v1 0 yes partial v2 0 yes Arguments Argument 0 Comments Restrictions output_supply_port input_supply_port control_port on_state supply_set When the supply set simstate is anything other than NORMAL the state of the output supply port of a switch is OFF and the acknowledge ports are corrupted Note that this differs from UPF v2 0 which states that the state of the output supply port of a switch is UNDETERMINED on_partial_state off_state error_ state Usage Notes The following is not supported e In order to model the definition of a power switch the tool currently treats UNDETERMINED state as OFF state for simulation This implies that when the state of supply set is NOT NORMAL the state on the output supply port will be OFF instead of UNDETERMINED state Power Aware Simulation User s Manual v10 2c 249 UPF Commands and Reference set retention set retention Support for UPF Standard v1 0
90. Aware simulation of RTL designs e Support for Power Aware simulation of Gate Level and Mixed RTL Gate Level designs More robust support for isolation of arbitrary SystemVerilog data types Visualization of isolation and level shifter cells in dataflow and schematic windows Power management objects in structure waveform and object windows e Support for coverage data collection for power states and transitions and power aware checks e Support for user defined power aware assertions using the UPF bind checker command Automatic power aware testplan generation The no optimization flow is not recommended except for certain very specific applications that do not yet support the optimized flows One such application is the use of Power Aware simulation together with Questa ADMS Using the Standard Flow This section describes the three step standard command flow used to perform Power Aware simulation for RTL Gate level or mixed RTL Gate level designs This flow consists of the following sequence of operations 1 Compile 2 Optimize 3 Simulate Compile Compile your design by running either the vcom for VHDL or the vlog for Verilog command as you would for any VHDL or Verilog SystemVerilog design Noe Do not use the novopt argument with either vcom or vlog when you compile for Power Aware simulation For more information on using vcom refer to Compiling a VHDL Design the vcom Command in th
91. Behavior With the power management architecture implemented on top of the design it should be possible to repeatedly power up each power domain and later power it down again Each time a domain is powered up it should reach a well defined state from which to continue its 328 Power Aware Simulation User s Manual v10 2c Supplemental Information Power Aware Verification of ARM Based Designs operations That state may be the initial reset state or a state saved before the power domain was last powered down or a combination of the two While a power domain is powered down its elements cannot drive their outputs to well defined logic values As a result those outputs may float to 1 or float to 0 or may be at an intermediate value In this situation those outputs are considered corrupted This is not a problem as long as no other active power domain sinks those corrupted values otherwise logical and or electrical problems could result During the power down process it is essential for the isolation cells in the design to be enabled before the domain s primary supply is shut off for those isolation cells to clamp signals from the powered down domain to appropriate values and for the isolation cells to remain enabled until the shut off domain s primary supply is turned on again Similarly when two interconnected power domains have been put into respective power states that involve different supply voltages the level shifters in the design m
92. CIDENTAL INDIRECT SPECIAL OR CONSEQUENTIAL DAMAGES WHATSOEVER INCLUDING BUT NOT LIMITED TO LOST PROFITS ARISING OUT OF OR RELATED TO THIS PUBLICATION OR THE INFORMATION CONTAINED IN IT EVEN IF MENTOR GRAPHICS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES U S GOVERNMENT LICENSE RIGHTS The software and documentation were developed entirely at private expense and are commercial computer software and commercial computer software documentation within the meaning of the applicable acquisition regulations Accordingly pursuant to FAR 48 CFR 12 212 and DFARS 48 CFR 227 7202 use duplication and disclosure by or for the U S Government or a U S Government subcontractor is subject solely to the terms and conditions set forth in the license agreement provided with the software except for provisions which are contrary to applicable mandatory federal laws TRADEMARKS The trademarks logos and service marks Marks used herein are the property of Mentor Graphics Corporation or other parties No one is permitted to use these Marks without the prior written consent of Mentor Graphics or the owner of the Mark as applicable The use herein of a third party Mark is not an attempt to indicate Mentor Graphics as a source of a product but is intended to indicate a product from or associated with a particular third party A current list of Mentor Graphics trademarks may be viewed at www mentor com trademarks Mentor Graphics Corporation 8005 S W
93. F create upf2hdl vct UPF GNDZERO2VHDL BIT hdl type vhdl bit table PARTIAL ON 1 OFF 1 ON 0 create_hdl2upf_vct VHDL_BOOL2UPF hdl type vhdl boolean table TRUE ON FALSE OFF create upf2hdl vct UPF2VHDL BOOL hdl type vhdl boolean table PARTIAL_ON FALSE ON TRUE OFF FALSE create hdl2upf vct VHDL BOOL2UPF GNDZERO hdl type vhdl boolean table FALSE ON TRUE OFF create upf2hdl vct UPF GNDZERO2VHDL BOOL hdl type vhdl bit table PARTIAL ON TRUE OFF TRUE ON FALSE Connections Using Value Conversion Tables VCTs You can model more complex connections between supply nets and HDL ports by using either of the following UPF commands to define value conversions create upf2hdl vct create hdl2upf vct 284 Power Aware Simulation User s Manual v10 2c UPF Commands and Reference Value Conversion Tables Limitations Only following types are supported in HDL data types e SystemVerilog logic bit wire reg Verilog wire reg e VHDL bit std logic std ulogic Boolean Any subtypes of these are not supported Examples create hdl2upf vct VHDL SL2UPF hdl type vhdl table U OFF X OFF O OFF 1 ON Z OFF L OFF H ON W OFF OFF create upf2hdl vct UPF GNDZERO2SV LOGIC hdl type sv table PARTIAL ON X OFF 1 ON 0
94. FF create upf2hdl vct UPF GNDZERO2SV LOGIC hdl type sv table PARTIAL ON X OFF 1 ON 0 282 Power Aware Simulation User s Manual v10 2c UPF Commands and Reference Value Conversion Tables create upf2hdl vct VHDL TIED HI hdl type vhdl table ON 1 j PARTIAL ON X OFF X create upf2hdl vct SV TIED HI hdl type sv table ON 1 PARTIAL ON X OFF X create upf2hdl vct VHDL TIED LO hdl type vhdl table ON 0 PARTIAL ON 0 OFF X create upf2hdl vct SV TIED LO hdl type sv table ON 0 PARTIAL ON X OFF X create hdl2upf vct SV BIT2UPF hdl type sv bit table 1 ON 0 OFF JJ create upf2hdl vct UPF2SV BIT hdl type sv bit table PARTIAL ON 0 ON 1 OFF 0 create_hdl2upf_vct SV_BIT2UPF_GNDZERO hdl_type sv bit table 0 ON 1 OFF create upf2hdl vct UPF_GNDZERO2SV_BIT hdl type sv bit table PARTIAL ON 1 OFF 1 ON 0 create_hdl2upf_vct VHDL_BIT2UPF hdl_type vhdl bit table 1 ON Power Aware Simulation User s Manual v10 2c 283 UPF Commands and Reference Value Conversion Tables 0 OFF create upf2hdl vct UPF2VHDL BIT hdl type vhdl bit table PARTIAL ON 0 ON 1 OFF 0 create_hdl2upf_vct VHDL_BIT2UPF_GNDZERO hdl type vhdl bit table 0 ON 1 OF
95. FULL ONj add power state PD2 state PD2 S2 logic expr ctrl supply expr VDD1 FULL ON amp amp GND1 FULL ONj Power Aware Simulation User s Manual v10 2c 277 UPF Commands and Reference UPF Supply Connections Example C 26 Dependency Specified with add power state supply expr Case 1 In this example from supply expr of PD1_S1 and PD2 S2 VDD state Power Aware simulation determines that state PD1 S1 and PD2 S2 cannot co exist add power state PD1 state PD1 S1 supply_expr VDD1 FULL ON amp amp GND1 FULL ON amp amp VDD FULL ONj add power state PD2 state PD2 S2 supply_expr VDD1 FULL ON amp amp GND1 FULL ON amp amp VDD OFF Example C 27 Dependency Specified with add power state supply expr Case 2 In this example from supply expr of PD1_S1 and PD2 S2 VDD state Power Aware simulation determines that state PD1_S1 and PD2 S2 cannot co exist add power state PD1 state PD1 S1 supply_expr VDD1 FULL ON amp amp GND1 FULL ON amp amp VDD FULL ON add power state PD2 state PD2 S2 supply_expr VDD1 FULL ON amp amp GND1 FULL ON amp amp VDD FULL ON Example C 28 Dependency Specified with add power state supply expr Case 3 In this example from supply expr of PD1 S1 and PD2 S2 VDD voltage range Po
96. G pin in the Liberty model In this case the connect_supply_net command to these ports is ignored This is equivalent to using vopt pa connectpgpin i ignorepgportsaon Bypasses connection of a supply net to a port using the connect supply net command when the port is missing in the verification model but is a power or ground PG pin in the Liberty model In this case connect supply net command to these ports is ignored and the Power Aware simulation semantics of the parent instance of the port are disabled This is equivalent to using vopt pa_connectpgpin a ignoresupply expr Ignores supply expr when both supply and logic expressions are present in an add power state command Power Aware Simulation User s Manual v10 2c 267 UPF Commands and Reference Supported UPF Extensions Table C 5 Power Aware Actions for vopt pa upfextensions cont mapcell Supports the use of lib cells specified in map power switch map isolation cell and map level shifter cell UPF commands in lt libraryname cellname gt format For example map power switch PD ONE domain PD SUP lib cells LIB NODE nonameclash Ignores the name clash error that occurs for ports of the set power switch command that are specified for the input supply port or output supply port arguments and that already exist in RTL nonlrmstatenames Allows non standard UPF names in state name of add_port_state command F
97. Getting Started With Power Aware Simulation Note The functionality described in this chapter requires an additional license feature for ModelSim SE Refer to the section License Feature Names in the Installation and Licensing Guide for more information or contact your Mentor Graphics sales representative Some designs require that you minimize dynamic and static power consumption A common low power design technique power gating involves switching off certain portions of the design when their operation is not needed and restoring power when operation is needed again Other low power design techniques include the use of multi voltage supplies state retention isolation and level shifting ModelSim supports Power Aware simulation for VHDL or Verilog designs that use the above techniques in both register transfer level PA RTL and gate level PA GL simulation To apply Power Aware simulation you use your conventional ModelSim simulation flow along with some power specific options to the vopt and vsim commands and a power intent specification written using IEEE 1801 Unified Power Format UFP With Power Aware simulation you can perform functional verification of low power designs together with the power management structures defined by your power intent Different types of power gating designmanagement structures can be verified such as Multiple switchable power domains with a single voltage Multiple switchable
98. HLD1BWP lsinst2 UPF LS I w2 Z w4 Limitations on Level Shifting e Support for VHDL and Verilog synthesizable data types Restricted support for SystemVerilog array struct Level shifters not specified at the power domain boundary are not considered for multi voltage checks Restricting Isolation and Level Shifting on a Port The set_isolation and set_level_shifter UPF commands each have source and sink arguments which you can use to apply isolation or level shifting only to certain paths of a specific port in your design When you specify either or both of these arguments Power Aware simulation identifies all the paths through the given port and applies isolation or level shifting to only those paths whose driver and receiver supplies match the specified source and sink supplies Isolation and Level Shifting Behavior Using the source and sink arguments affects Isolation and Level Shifter insertion behavior in the following ways Determine all the paths passing through a given port To determine the path all the buffers isolation cells and level shifter cells are treated as feedthroughs and actual drivers and receivers are determined Insert isolation or level shifter cells after matching source or sink supplies if specified To match equivalent supplies the driver nets of primary power and ground nets are matched Determine via the location argument for both commands the placement of an isolatio
99. Header gt VDD 0899 VDD_0d81 VSS ON UPF rtl top upf 133 ON ON ON OFF UPF rtl top upf 134 ON ON ON List of possible states on VDD 0d99 source supply port VDD 0d99 File UPF rtl top upf 21 ON 0 99 1 10 1 21 VDD 0d81 source supply port VDD 0d81 File UPF rtl top upf 22 ON 0 81 0 90 0 99 VSS source supply port VSS File UPF rtl_top upf 23 1 ON 0 00 0 00 0 00 Power Aware Simulation User s Manual v10 2c 145 Power Aware Commands and Options Voltage Level Shifting Multi Voltage Analysis Level Shifter Specification Reporting Power Aware simulation parses the set level shifter command in the UPF file and selects a list of candidate ports for level shifter insertion These ports are also dumped into the UPF report file report upf txt as in the following example Level Shifter Strategy my 1s File src simple mv7 test upf 63 Rule high to low Threshold 0 Applies to outputs Level Shifted Candidate Ports 1 Signal tb TOP bot2 outl bot Level Shifter Strategy my ls bot3 File src simple mv7 test upf 69 Rule low to high Threshold 0 Applies to outputs Level Shifted Candidate Ports Signal tb TOP bot3 outi1 bot Threshold Control for Level Shifters You can set a global threshold level for a Power Aware analysis containing multiple voltage levels using the following command vopt pa Isthreshold real where
100. LowConn Not Analyzed Level Shifter Total 1 Not Analyzed level shifters Source power domain PD midl gt Sink power domain PD mid2 Total count 1 1 LS count 1 Candidate Port tb TOP mid2 ini1 bot connected mask 1000 count 1 level shifter cell tb TOP lsinst2 1 1s buf Domain PD miG32 Source port tb TOP midi1 outi i bot connected mask 1000 count 1 LowConn gt Sink port tb TOP mid2 in1 bot connected mask 1000 count 1 LowConn 76 Power Aware Simulation User s Manual v10 2c Automatic Checking Static Checking in Power Aware Reporting for a Valid Level Shifter e pa checks svl Indicates the valid level shifters that have matching voltage information and proper direction of shift Message from vopt Note vopt 9693 UPF LS STATIC CHK Found Total 2 Valid level shifters Report File dump for the power domain report static txt Total 2 Valid level shifters Source power domain pd bot gt Sink power domain pd aon Total count 1 1 LS count 1 Candidate Port tb TOP botil outi bot count 1 level shifting strategy my ls PD pd bot Source port tb TOP botl outl bot count 1 LowConn gt Sink port tb TOP bot2 in2 bot count 1 LowConn 2 LS count 0 Candidate Port tb TOP boti out1 bot count 1 level shifting strategy my ls PD pd bot Source port tb TOP botl outl bot count 1 LowConn gt Sink port
101. MINED state as defined by resolution methods provided for create supply net command defined in the IEEE Std 1801 2009 Section 6 22 2 Specifically for any error condition in resolution techniques such as Power Aware Simulation User s Manual v10 2c Oo UPF Commands and Reference Accessing Generate Blocks in UPF e For ONE HOT resolution if at any point in time more than one supply source that is driving the net is anything other than OFF e For PARALLEL resolution if any of the potentially conducting paths can be traced to more than one root supply driver For UPF 1 0 under these conditions the state of the supply net was set to OFF For UPF 2 0 the default state of supply nets and ports is set to OFF You can change this to FULL ON with the vopt option pa_disable defaultoff Accessing Generate Blocks in UPF In order to access hierarchy as defined in individual languages or as Power Aware simulation accepts it UPF uses square bracket pairs This is because UPF is written in Tcl so in some contexts square brackets can be interpreted as special command substitution characters though you usually need to use escape characters with them for that purpose The exception to this when using a UPF command argument that takes a list of values enclosed in braces because that is not actually command substitution The following examples show how to generate references in UPF for both Verilog and VHDL create power domain p
102. N Power Aware Simulation User s Manual v10 2c Visualization of Power Aware Operations Power Aware Schematic Display 1t 108 na Supply Port EnumVariable voltage 0 IntVanable out_sw_PD_RAM OFF 0 Supply Port state OFF in_sw_PD_RAM state OFF Enum Variable voltage 0 IntVanable ctri_sw_PD_RAM Ihi Control Port ftb PD ALU sw in2 sw PD ALU i state 4 voltage 4 tb PD_ALU_sw in_sw_PD_ALU state 4 voltage E4 tb PD_ALU_sw out_sw_PD_ALU state voltage u tb PD ALU sw ctrl sw PD ALU Power Aware Schematic Display You can perform debugging at the same time you run a Power Aware simulation by adding the debugdb argument to both of the vopt and vsim commands The results of both the Power Aware analysis and the debug operation are provided as Power Aware schematic in the Schematic window You can also view a correlation between the UPF power intent and the design display in the Schematic window Refer to the Schematic Window Chapter of the User s Manual for more information Note Debugging in Power A ware is supported for RTL usage flow only it is not available for gate level simulation GLS Power Aware Simulation User s Manual v10 2c 107 Visualization of Power Aware Operations Power Aware Schematic Display Top Down Debugging From the Test Bench You can run Power Aware analysis and debugging from the top of the design test bench with or without spec
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104. O Buffer When buffer set related supply net supply goes off Input Port Corruption is seen on the input port Output Port Corruption is seen on the logic or port driven by output port Power Aware Simulation User s Manual v10 2c 135 Power Aware Commands and Options Power Aware Messages Power Aware Messages This section describes the ways in which you can control messaging within the ModelSim power aware functionality Dynamic Power Aware Check Message Control Use the pa msg command to finely control the appearance of messages resulting from power aware checks during simulation Note When you disable a message for a specific power aware check you also disable the underlying assertion as well This means that the any messages are disabled as well as any resulting coverage collection The syntax for the command is pa msg enable disable severity note warning error fatal stopafter lt number gt message number pa_checks lt spec gt scope scope name domain pd name strategy strategy name ports ports list glitch window duration all Concepts of pa msg Command scope scope When you do not specify the scope argument the scope of the command is set to the design top specifically it applies to the entire design from design top scope downwards Use of this option changes the scope of command to the specified scope For
105. O 304 Power Statements FMMPTCT nm 305 Region Definitions 2224 aces tees ue rac ex eR EA ORG Rada qu bee Ru EL EREPTR n pede 306 Power Model Mapping Statement olo cried RF RS ESET E Eee RET Gs SEES 310 Mapping Statement Precedence cies se a ex e RR E a Rok RR OR ees 312 Specifying Default Model Mappings sslsseleeeeee ee 313 Retention Statement es sque box eroaa E a E R eae FTN qd S EE SERE 314 Corruption Semantics s iacere Ecrire RV ER dAHeRI eA Pa ee Ea RES A kes 314 Voltage Domains 133 Suas Seer oa ped e Rex d Sr bach EROR shasta 315 COMMEUS PCT 316 Regular Expressions and Variables iaces ae marea e CR eo E RA RS race RE 316 Rule Precedence sas seni er nite RA ERPEE EA REER enr eE E ERE MMUCePE EE 316 Appendix E Supplemental Information icici o ecos eth eth E RRRRRRRRREER REP kasines 319 Power Aware Verification of ARM Based Designs llslleeeeeeeeeeeee 319 ADSICdOl 1292 RODRPER REC EDQU PACCO NU xORADQUE RE APRES EA See Hebe sees 319 IntcoGuCcHolls 42 o3 edd eee seh di es eee bene sh eee Ress ER eee ek EU ds 320 Active Power Management 645 an cca y Yee Pee ene eee RI EI Ra PEE Ear eS eR Ed 320 Power Management Techniques a ise sx ere eu ESE EEARESAREEGSa REA cs 320 Power Management Specification 3 425 000346 scanned ep dee snes eee Rede Kader ens 321 Power Management Architecture oso snper Re ER IEEE RES EH o Rn DR 322 Power Aware Simulation User s Manual v10 2c 9 10
106. OP midi1 outi1 bot connected mask 0010 count 1 Isolation cell tb TOP isoinsti1 1 ISO AND Domain PD midl1 Source port tb TOP mid1 out1 bot connected mask 0010 count 1 LowConn gt Sink port tb TOP mid2 in1 bot connected mask 0010 count 1 LowConn Redundant Isolation Total 1 Redundant isolation cells Source power domain PD midi gt Sink power domain PD mid2 Total count 1 ISO count 1 Candidate Port tb TOP mid2 in1 bot connected mask 0100 count 1 Isolation cell tb TOP isoinst2 O ISO AND Domain PD mid2 Source port tb TOP mid1 out1 bot connected mask 0100 count 1 LowConn gt Sink port tb TOP mid2 in1 bot connected mask 0100 count 1 LowConn Not Analyzed Isolation Source power domain PD mid1 gt Sink power domain PD mid2 Total count 1 ISO count 1 Candidate Port tb TOP mid2 in1 bot connected mask 1000 count 1 Isolation cell tb TOP isoinst2 1 ISO AND Domain PD mid2 Source port tb TOP mid1 out1 bot connected mask 1000 count 1 LowConn gt Sink port tb TOP mid2 in1 bot connected mask 1000 count LowConn Static Level Shifter Checks You can apply various static checking functions for level shifters by using the vopt pa checks command The value you specify determines the check
107. P corruption Refer to the section UDP Corruption and Retention Modes for more information undeterminedstate Controls behavior related to power aware pa enable switches or supply nets ports going into an UNDETERMINED state as defined by UPF 2 0 Refer to the section Detailed Support for supply net type for more information pa enable enables UPF 2 0 behavior pa disable reverts to UPF 1 0 behavior verbosereporting Toggles the addition of a full hierarchical pa disable path of the power domain for static and dynamic reporting 130 Power Aware Simulation User s Manual v10 2c Power Aware Commands and Options Additional Commands You Can Use with Power Aware Additional Commands You Can Use with Power Aware Power Aware simulation supports the following additional Tcl commands which are not UPF commands that you specify in either a UPF file vopt pa_upf or a Tcl file vopt pa tclfile set corruption extent set feedthrough object set related supply net Power Aware Simulation User s Manual v10 2c 131 Power Aware Commands and Options Additional Commands You Can Use with Power Aware set corruption extent Syntax set corruption extent domains domain name ce o os osw sc scb Arguments domain name the name of any power domain in the current scope You can specify multiple domain names in a space separated list enclosed in braces
108. PA GLS you can generate various level shifter and isolation checks Related Topics Voltage Level Shifting Multi Voltage Modeling Isolation Analysis Level Shifting for Gate Level Checking You can create a gate level instance of a model that will be recognized as a level shifter instance by either of the methods given below This type of level shifter instance will be recognized for static and dynamic Level Shifter Checks Method 1 Specify the Liberty is level shifter attribute as part of the module definition to identify the level shifter cell For example is level shifter 1 module 1s buf pg type primary power input logic pwr rail pg type primary ground input logic gnd rail level shifter data pin 1 input data output logic out assign out data endmodule Method 2 Assign a level shifting prefix or suffix string to the instance as specified by the UPF name format command For example LVLHLD1BWP lsinst2 UPF LS I w2 Z w4 Isolation for Gate Level Checking A gate level instance of a model that will be recognized as an isolation instance can occur by any of the methods given below Method 1 Create this instance by specifying the Liberty is isolation cell attribute as part of the module definition to identify the isolation cell Also set the isolation cell enable pin TRUE on the instance enable pin For example is isolation cell 1 88 Power
109. PT CORRUPT ON ACTIVITY CORRUPT STATE ON CHANGE and CORRUPT STATE ON ACTIVITY Error vsim 8918 MSPA ISO EN PSO Time 20 ns Isolation control x is not enabled when driving supply isin CORRUPT ON ACTIVITY simstate for the following Port tb TOP midl outl bot File test upf Line 62 Power Domain PD_mid1 Isolation Functionality Check vopt pa_checks ifc 82 Ensures that when isolation is not applied the value at isolation cell s output is same as that at its input This is to catch any functional error because of applied isolation cell Performed during in active isolation period During inactive isolation period it will catch occurrences where value of isolated port is different than the ports value Error vsim 8931 MSPA ISO FUNC CHK Time 100 ns Isolated port for isolation cell strategy iso PD mid2 on port tb TOP mid2 in2_bot having value x is different from port value 1 during non isolation period File test upf Line 111 Power Domain PD mid2 Power Aware Simulation User s Manual v10 2c Automatic Checking Dynamic Checking in Power Aware Table 5 4 Dynamic Isolation Checks cont Check Usage Syntax Description Example Message Isolation vopt pa checks ira Flags violation if there was no requirement of isolation Redundant such as driving logic is not in an OFF or CORRUPT Activity state when receiving logic is in an ON state and there is Check activation
110. Power Aware Coverage Power Aware Coverage Report Reference Power Aware Coverage Verbose Report This report provides a view of all coverage information collected about the dynamic checks analyzed during the simulation It is suggested that you generate this file in XML format to be loaded in a spreadsheet program for ease of use Generation coverage report pa verbose xml file pa checks xml Power Aware Checks Coverage Summary This report provides a basic overview of the coverage statistics including information collected from state and transition counts and dynamic check counts Generation coverage report assert pa Example Total Coverage By Instance filtered view 62 5 POWER AWARE CHECKs COVERAGE SUMMARY NEVER FAILED 75 0 ASSERTIONS 24 Power Aware Checks Coverage Detailed Report This report provides a detailed view of all the dynamic checks analyzed during the simulation The information includes the type of check a hierarchical path to the check and the failure and pass counts of the check Generation coverage report assert pa details Example Total Coverage By Instance filtered view 62 5 POWER AWARE CHECKs COVERAGE RESULTS Check Coverage Failure Pass Type Object Count Count Isolation Functionality Check tb CPU1 out alu UPF ISO pa iso cell checks vec mspa iso func chk 0 2 Isolation Clamp Value Check tb CPU1 out alu UPF ISO pa iso cell checks vec mspa iso clamp chk 3 2 Isolation
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112. RENX GO RARE E PADHERV EE ACRE NU ees 138 Examples qe Lc 140 Controlling Power Aware Message Severity During vopt Stage 04 141 Excluding Design Elements from Power Aware 0 00 eee eee eee eee ees 142 Voltage Level Shifting Multi Voltage Analysis llle 145 Power State Tables iyo esq dedu ier ERE SER UM ade 3 RUE a nd aci dA SCR 145 ls cn KP rPx CDTMMT 145 Level shifter SpDeCIDICHBOB sodes pd ea Rd ph AIR iiaii iaa adai Ret deis 146 Reporting site car oe Rx eias RO RR ER PK RYXa RC ETREDREERY Rap CPS RR PRSE 146 Threshold Control for Level Shifters 13 as ceaca Rep EXP RR Ra EE X dO 146 Level Shifter Instances ase see oe y OR RR RERO EA KEENE EE ne VE RP AR ER Rd 146 Limitations on Level SWlfltle sa 225 4 ex etaxerESA a hEIREWCENQUD RP EP ERI qan 147 Restricting Isolation and Level Shifting on a Port 0 0 0 cece eee eee 147 Isolation and Level Shifting Behavior llle 147 How to Apply the source and sink Arguments 0 0 0 cece eee eee ee 148 Simulating Designs Containing Macromodels 0 0 0 eee ee eee eee 152 Usine UPF Commands oa 404 46 esrb IERI RE RORIS RR PR ee PR PUR 152 Attributes im RTL ssskuesu RR LA RU a E EE ROCKS a DH ETA RSE PS RC 153 IF iA PREMIT i a a ee NO eee E wee Re a a a el 154 Example of Power Intent on a Hard Macro 0 eee eee 154 UPF Commands ieas ea e aaa a a a a a a E a a E a a 155 REL AUQripites 42 4544 e854 bo ad bi o
113. Refer to IEEE Std 1801 2009 for complete details Table C 2 Supported UPF Package Functions for VHDL function supply on pad name IN string value IN real return boolean function supply off pad name IN string return boolean function supply partial on pad name IN string value real return boolean function get supply value pad name IN string return supply net type function get supply voltage value IN supply net type return real function get supply on state value IN supply net type return boolean function get supply on state value IN supply net type return bit function get supply state value IN supply net type return net state Table C 3 Supported UPF Package Functions for SystemVerilog Function Name function bit supply on string pad name real value function bit supply off string pad name function bit supply partial on string pad name real value function supply net type get supply value string name function real get supply voltage supply net type arg function bit get supply on state supply net type arg Power Aware Simulation User s Manual v10 2c 259 UPF Commands and Reference Supported UPF Package Functions Table C 3 Supported UPF Package Functions for SystemVerilog Function Name function bit 1 0 get supply state supply net type arg Note UPF 2 0 introduced
114. Sense posedge Retention RESTORE tbi ret1 Retention Sense negedge Retention Strategy PD TOP retention2 File src bitwise 1 test upf 61 Retention Supplies power tb1 VDD net ground tb1 GND net Retention SAVE tb1 ret2 Retention Sense posedge Retention RESTORE tbl ret1 Retention Sense negedge Retention Strategy PD TOP retention1 File src bitwise_1 test upf 64 Retention Supplies power tb1 VDD_net ground tb1 GND net Retention SAVE tb1 ret1 Retention Sense posedge Retention RESTORE tbl ret1 Retention Sense negedge Power Domain PD BOT File src bitwise_1 test upf 70 report mspa txt Total tbl upf retention ret 1 upf retention sr 12 NPM FF 12 NPM LA 2 OUTPUT 38 294 Power Aware Simulation User s Manual v10 2c UPF Commands and Reference Supply Nets PD TOP sub total tbl topl1 bot1 upf retention ret 1 tb1 topl1 bot1 tdsig 0 upf_retention_sr 12 tb1 topl bot1 tdsig 2 1 tbl topl botl tdsig 3 1 tbl topl botl tdsig 4 1 tbl topl botil tdsig 5 1 tbl topl botil tdsig 6 1 tb1 topl bot1 tdsig 7 1 tb1 topl1 bot1 tdsig 8 tbl topl botl tdsig 9 1 tb1 topl1 boti tdsig 10 tb1 topl1 boti tdsig 11 tb1 topl1 boti tdsig 12 tb1 topl1 boti tdsig 13 NPM FF 1 tbl1 topl boti tdsig 1 1 PD TOP2 sub
115. Table of Contents Operating MOUSS s secure PIX RE IAeRENE ER HR EH xe ed REP E REED 322 Power DOMAINS 4 62424342 o55 25282eun ee eha Senses ee eth se she EASIER pre Ua 323 Power Distribution a cuo ecabere ues erac tr poa ata en ee ea ea xd 324 Power States xs ad oes px d pax ep bea Ra dd d udpu Leda EO E T G S 326 Isolation and Level Shifting sce d eR EN sooo ERE Bee ee LE ERR ERA E SA PES EE 326 Stale Retention RPM MT ede eG tae Be ede aw eee Rees 328 Power Managed Behavior ao sso debe pra sand oadnea Rea a haces e C d Ro eee 328 Power Control DOO uoo ace acie EC Ag PR ROC 4 bed eae PP eR S 329 Power Aware Verification Flow 0 ccc eee n ene 329 Verifying the Power Management Architecture 330 Verifying Power Managed Behavior 331 Verifying Power Control Logic 2522s decns0saaenndd oo aoe nhs eeeendecaaexe he 332 SUMMA yesse gi oa oa oh okay eae eae E od a ee en eens eee 332 Acknowledgements ccc eee eS a raner PEPRECRRIdRRE TEAM CREATA ERES 333 Referees osse EAE RRRASERRRS APS GR SEER SESE MER Otte eS OEE SUE eRe Kee PRAES 333 Power Aware Simulation User s Manual v10 2c List of Tables Table 4 1 Generating UPF Reports for Power Aware 000 e eee eee eee 46 Table 5 1 Static Isolation Checks 2 cence bes 4r Rp RR REA CR drs Ganga ROS 12 Table 5 2 Static Level Shifter CheCkS sua euer o pO A Ro E RE P RCHRR A ane 74 Table 5 3 Dynamic Retention Checks 52 2 eo RR RETE EIER 79 Table 5 4 Dynamic Isola
116. The related power pin and related ground pin attributes are defined at the pin level for output input and inout pins These attributes associate a predefined power and ground pin with the corresponding signal pins under which they are defined A default related power pin and related ground pin will always exist in any cell Example of Power Intent on a Hard Macro Figure A 3 shows an example of a block diagram of hard macro power domains using the following top level UPF definition Set scope top create power domain PD top include scope create power domain PD HM1 elements HM1 set domain supply net PD top primary power net VDD primary ground net GND set domain supply net PD HM1 primary power net VDD HM P1 primary ground net GND HM P1 154 Power Aware Simulation User s Manual v10 2c Power Aware Commands and Options Simulating Designs Containing Macromodels Figure A 3 Design Consisting of Hard Macros VDD HM Pl VDD HM P2 GND HM Pl GND HM P2 VDD GND top Inl In2 Inl In2 In3 Ol The following sections show how to define the hard macro power intent for each method UPF Commands Constraints are specified on pins set pin related supply HM1 pins i4 related power pin VDD HM P1 related ground pin GND HM P1 set port attributes ports HM2 i7 related power port VDD HM P1 related ground port GND HM P1 set port attributes ports HM2 i8 HM2 02 HM1 i5 related power port VDD
117. User s Manual v10 2c 151 Power Aware Commands and Options Simulating Designs Containing Macromodels set isolation iso3 domain PD7 sink PD4 location fanout set isolation iso4 domain PD3 elements F sink PD4 location fanout set isolation iso5 domain PD4 elements H location parent Places two isolation cells at Port F and isolates only port H with relative ordering Port F gt iso6 gt iso7 This means the clamp value o p of iso7 will be seen at Port H All other ports M F and I will not have clamp value during power down set isolation iso6 domain PD7 sink PD4 location fanout set isolation iso7 domain PD3 elements F sink PD4 location parent Simulating Designs Containing Macromodels A macromodel is a block level model in a design that has been optimized for power area or timing and has been silicon tested Defining the power intent for a macromodel depends on whether you have access to its internal structure logic and topology If internal access is not available you can specify power intent only on its external pins this is referred to as a hard macro To specify power intent for a hard macro you define related supplies attributes on these accessible pins as boundary ports Similarly you can isolate a hard macro from the rest of the design by applying the isolation on its boundary ports Specifying power intent for a hard macro is available by any of the fol
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120. _value lt ret_value if RESET posedge power w reset lt 1 begin if RET begin wait PWR wait CLK wait CLK posedge power w reset 0 end end endif PA GLS FUNC ifdef PA RTL FUNC Functionality in this section is used for Power Aware RTL or higher abstraction verification It can also be combined with the gate level functionality for the purpose of verifying both al al lways posedge RET pa store value lways negedge RET begin if RESET amp amp PWR gt pa_reset_register end always posedge PWR Power Aware Simulation User s Manual v10 2c 167 Model Construction for Power Aware Simulation Example Corrupt Model begin if RET begin pa restore value end end always negedge PWR gt pa_corrupt_register endif PA_RTL_FUNC endmodule Example Corrupt Model The following Verilog code shows how to create a simple corruption model that initiates and releases corruption on a register module CORRUPT PWR input PWR event pa_corrupt_register event pa_release_register always negedge PWR pa corrupt register always posedge PWR gt pa_release_register endmodule corrupt where The pa_corrupt_register statement causes the simulator to corrupt the current value of the signal corresponding to the inferred registers or latches The pa_release_register statement caus
121. a ee N E a ee a ee ay ee ee a Set the default for top level power domain Y AAEE E a a ee age Pg set_domain_supply_net PD_top primary power net VDD 0d99 primary ground net VSS Additional UPF commands could be used to propagate the top level supply nets into subordinate power domains and to define a power switch to create a switched ground VSS SW for one of the power domains Create sub domain supply nets MENDA ES create supply net VDD 0d81 domain PD interleaver reuse create supply net VDD 0d81 domain PD mem ctrl reuse create supply net VDD 0d99 domain PD sram reuse create supply net VSS domain PD interleaver reuse create supply net VSS domain PD mem ctrl reuse create supply net VSS domain PD sram reuse rr ee ee Create supply net for switch output SoS Se See eee Se Sa ae a ee a se ee ee ee eee ce ec create_supply_net VSS_SW domain PD_mem_ctrl PS ae Se ty P lie Create power switch for memory controller domain switch on ground side of supply network create power switch mem ctrl sw domain PD mem ctrl output supply port vout p VSS SW input supply port vin p VSS control port ctrl_p mc pwr c on state
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123. al verification is particularly suited to verifying complex control logic In contrast to simulation which runs one input sequence at a time to test a device formal verification considers all valid input sequences in one pass A formal verification tool can therefore identify all possible behaviors of the power control logic which enables it to automatically find any corner cases in which the generated control sequences may not be complete or in the correct order Formal verification is driven by assertions so use of formal verification requires creation of assertions about the expected behavior of the power control unit Although this takes some effort the ability to thoroughly verify the power control logic makes it worthwhile Summary Active power management is becoming a necessary part of today s SoC designs To add active power management to a design and verify that it is working correctly it is critical to have a well defined methodology that addresses all aspects of active power management The methodology needs to support defining and verifying an appropriate power management architecture verifying that the design behaves correctly under the power management architecture and verifying that the power control signals controlling the power management architecture are generated correctly IEEE Std 1801 2009 UPF supports such a methodology as does static analysis of power management architecture power aware simulation of power managed des
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125. ame2 lt suffix gt gen_label index name2 is the new name of the instance name2 within scope gen_label index lt prefix gt gen_label index name2 lt suffix gt The new name could also be double escaped lt prefix gt gen_label index name2 lt suffix gt Use as a path separator for generate scopes would map to prefix gen label index name2 suffix gt Allows you to specify predefined option values like TRUE FALSE high low posedge and latch in case insensitive form 266 Power Aware Simulation User s Manual v10 2c UPF Commands and Reference Supported UPF Extensions Table C 5 Power Aware Actions for vopt pa upfextensions cont default flathiername Enables specifies only the following values of the pa upfextensions argument case genblk ignorepgports mapcell nonameclash nonameclash relatedsnet S V NOTE Specifying vopt pa upfextensions with no values has the same effect Allows hierarchical names within the UPF file that refer to flattened gate level hierarchies in the design genblk Allows generate block to be used in set_scope find_objects and create_power_domain elements argument commands ignorepgports Bypasses connection of a supply net to a port using the connect_supply_net command when the port is missing in the verification model but is a power or ground P
126. and Limitations Power Aware simulation is unable to determine whether retention logic is already present in a sequential UDP and therefore routinely inserts retention logic for such UDPs Use the UPF set retention command with the instance inst name option to avoid application of retention semantics to UDPs that already include retention logic Power Aware simulation is unable to determine whether a UDP is power aware that is whether the UDP references supply ports and corrupts its outputs based on the values of those supply ports Consequently Power Aware simulation assumes that all UDPs are not power aware and routinely applies corruption on UDP logic Power Aware simulation is unable to process sequential UDPs that involve multiple clocks Power Aware Simulation User s Manual v10 2c 43 Power Aware Simulation Applying Power Intent to the Design 44 Power Aware Simulation User s Manual v10 2c Chapter 4 Power Aware Reports You can use the vopt and pa report commands in a two step process to generate reports for a Power Aware simulation run and then examine them to validate the application of the power intent on your design This flow generates power aware reports containing the following The intent of the low power defined in the power specification file For UPF either static or dynamic information on the current Power Aware simulation including connections to supply and ground nets See UPF Reports
127. and Transition Display Accessing Access the window as follows From the Power Aware State Machine List Window double click on the power aware state machine you want to analyze Figure 7 9 Power Aware State Machine Viewer Window Example dut pa coverageinfo top pst top pst pst state info state var Default Nel 157612000 ps I A top pst VDD_0d99 VDD_0d81i VSS mem_ctrl_sw vout_p ON_STATE ON_STATE Orr STATE GNISTATEN ONISTATEN on stare GFRISTATES undefined undefined undefined GUI Elements of the Power Aware State Machine Viewer Window This section describes GUI elements specific to this window Window Element Descriptions Title bar The UPF type and hierarchical path Tab label Leaf name of the state machine e State Diagram All states of a state machine and their transitions o Bubbles Information associated with logic expression supply expression simstate legality Information appears in properties box associated with each state bubble 120 Power Aware Simulation User s Manual v10 2c Visualization of Power Aware Operations Power State and Transition Display Color Green represents the current state and yellow represents the previous state A thick red border identifies an illegal state as allowed with add power state Label State name o Transitions Directional arrows showing transitions between the states o Time Mode upper right h
128. and corner The time of the current state transition which decides yellow and green Also affects States table Goto Previous and Next State buttons Allows synchronization between other state machine windows and the wave window and the objects window e Synchronization By default this window is synchronized with the Wave window Objects window and other Power Aware State Machine View windows State Machine to State Machine State machines opened will remain synchronized with each other related to the simulation time stamp This enables you to work with multiple power aware state machines State Machine to Wave The Wave window and Power Aware State Machine Viewer windows are synchronized to facilitate your debugging When you move a wave window time cursor to observe various values of signals in wave window the Power Aware State Machine Viewer window changes to mach the same simulation time stamp and the reverse is true e States table Only appears for supply sets power domains and PSTs Shows current and previous values of objects that decide the power state of the supply set or power domain This table helps you perform root cause analysis of your power aware states When you encounter an unexpected power state this feature allows you to understand the reason behind it specifically when looking for unexpected illegal or undefined power states o Column headers Shows objects power domains supply sets
129. and reports IEEE 1801 2009 Standard for Design and Verification of Low Power Integrated Circuits This IEEE standard defines the Unified Power Format UPF a notation used for specifying power intent for HDL designs Power Aware Simulation User s Manual v10 2c Chapter 2 Concepts for Using Power Aware Simulation This chapter provides a brief description of basic usage elements for running Power Aware simulation in the following sections Power Intent Specification Power Aware Modeling Modeling Corruption Modeling Isolation Modeling Retention Modeling Bias Power Intent Specification To perform Power Aware simulation you need to provide a power intent specification that defines the planned power management architecture for the design A power intent specification is written using commands defined in the IEEE 1801 Unified Power Format UPF standard For more information on this format refer to Unified Power Format UPF definition Power Aware Modeling Verilog and VHDL both make the fundamental assumption that all logic is powered on at the beginning of simulation and remains powered on throughout simulation However this assumption is no longer true for most complex devices being designed today In these systems power is typically provided to a given portion of a chip only when that part needs to function This involves inclusion of additional hardware to control power save state when power is turned
130. are Simulation User s Manual v10 2c 217 UPF Commands and Reference map level shifter cell map level shifter cell Support for UPF Standard v1 0 no v2 0 yes Arguments Argument Comments Restrictions filename Text file that defines level shifter strategy domain lib cells elements A list of ports to use from the strategy defined in the lt textfile gt provided with this command 218 Power Aware Simulation User s Manual v10 2c map retention cell Support for UPF Standard v1 0 parital v2 0 partial Arguments Argument domain UPF Commands and Reference map retention cell Comments Restrictions elements Not supported exclude elements lib cells lib cell type lib model name Power Aware Simulation User s Manual v10 2c Port connectivity using port argument of this option is not supported Verification semantics of lib model are not honored for UDP retention where flops and latches are written as UDPs and retention is applied on them 219 UPF Commands and Reference name format name format Support for UPF Standard v1 0 yes partial v2 0 yes partial Arguments Argument 0 Comments Restrictions isolation prefix isolation suffix level shift prefix level shift suffix implicit supply suffix Not supported implicit logic prefix Not supported impli
131. argument to process the UPF power intent specification and apply it to the design You must also specify the pa enableznonoptimizedflow option Power Aware simulation reads and processes the UPF file without generating an optimized output Example vopt TB top pa upf TB upf pa lib work pa_enable nonoptimizedflow other vopt args where e TB top the name of the top level module of the test bench e pa upf TB upf the name of the UPF specification written with respect to the test bench top level module e pa lib work the name of the destination library pa enableznonoptimizedflow required for any flow using novopt other vopt args any other vopt arguments used to control UPF processing or optimization Simulate After you have compiled your design and processed the UPF file run the vsim command on the test bench using the pa and novopt arguments to invoke Power Aware simulation with no optimization on the design Example vsim TB top pa novopt pa lib work other vsim args 34 Power Aware Simulation User s Manual v10 2c Power Aware Simulation Working with Liberty Libraries where TB top is the name of the top level module of the test bench e pa invokes simulation in Power Aware mode novopt instructs ModelSim to disable optimization e pa lib work the name of the destination library other vsim args any other vsim arguments used to control simulation
132. ases the subthreshold leakage current due to its exponential relationship with the threshold voltage 1 Leakage currents lead to power dissipation even when the circuit is not doing any useful work which limits operation time between charges for battery operated devices and creates a heat dissipation problem for all devices Minimizing power dissipation starts with minimizing the dynamic power dissipation associated with the clock tree by turning off the clock for subsystems that are not in use This technique has been in use for many years But at 90nm and below static leakage becomes the dominant form of power dissipation Active power management minimizes static leakage through various techniques such as shutting off the power to unused subsystems or varying the supply voltage or threshold voltage for a given component to achieve the functionality and performance required with minimum power Active Power Management Active power management can be thought of as having three major aspects the power management architecture which involves the partitioning of the system into separately controlled power domains and the logic required to power those domains mediate their interactions and control their behavior the power managed behavior of the design which involves the dynamic operation of power domains as they are powered up and down under active power management as well as the dynamic interactions of those power domains to achieve
133. at domain UPF v2 0 is not clear on this e Supply sets Oo Each supply set handle name provided with the supply argument is searched for in the existing supply sets list for that composite domain If found the presence of supply set reference is checked for that handle A warning message is displayed if the reference is present but its name does not match the current the supply set reference name If the supply set handle did not contain a reference before but now a reference name has been provided Power Aware simulation searches the current scope and updates the handle with this reference It will be an error if any matching reference is not found If the supply set handle does not exist Power Aware simulation creates a new handle and populates the reference Power Aware simulation adds the new handle to the list of supply sets for the current composite domain and adds it to each subdomain You can add new subdomains and supply set handles to a composite domain subject to the checks mentioned above Power states Oo The add power state command is supported which means power states for composite domains are available e Support for save upf command Oo 192 In the interpreted mode Power Aware dumps instances of the create composite domain command once for each composite domain with all the updates included All the commands applied on a composite domain are applied to all the subdomains down to the leaf lev
134. at v2 0 of the UPF standard interprets the related power net and related ground net attributes as defining the driver supply set of an output port or the receiver supply set of an input port The standard also declares that it is an error in the following cases ifthe actual driving logic is present and its supply is not the same as the driver supply e if the actual receiving logic is present and its supply is not the same as the receiver supply As a result use of set related supply net for any purpose other than specifying the driver supply set of a macro model output or the receiver supply set of a macro model input may generate errors Specifically Power Aware simulation gives a vopt error message vopt 9814 You can use the warning argument of vopt to change the severity of this message to a warning so that simulation may continue vopt warning 9814 134 Power Aware Simulation User s Manual v10 2c Power Aware Commands and Options Additional Commands You Can Use with Power Aware Refer to Power Aware Messages for more information on changing the level of message severity Default Behavior The functionality in the section is enabled by default For top level ports in the absence of boundary information it is left up to the simulator to decide how to handle the primary input and output ports You can define the supply related to the primary input and output ports and instruct the simulator as to what voltage the inpu
135. ategy context will not be automatically connected to design elements owing to separate infrastructure in instance e Supply nets in supply sets functioning as predefined supply set functions are not automatically connected as per their predefined function Explicit specification of automatic connections must be specified Command Syntax Using connect supply set connect supply set supply set ref connect supply function pg type list elements element list exclude elements exclude list transitive Using create power domain create power domain define func type supply function pg type list Examples create power domain PD define func type power primary power define func type always on backup power connect supply set PD primary connect power primary power elements TOP connect supply set PD ISO isolation supply set connect iso power primary power connect iso ground primary ground connect supply set PD RET retention supply set connect ret backup power backup power connect switchtable supply primary power 274 Power Aware Simulation User s Manual v10 2c UPF Commands and Reference UPF Supply Connections Power State Composition States of ports and nets carry voltage and on off information which means combinations of power states of supply ports and or nets are important in identifying the requirement of isolation cells and level shifters on bou
136. atically disabled for design elements that are explicitly or automatically connected to a particular supply net or supply set Simulation semantics are disabled for all the descendants of the instance of model Examples RTL Specification Verilog module memory input vdd endmodule RTL Specification VHDL 286 Power Aware Simulation User s Manual v10 2c UPF Commands and Reference Supply Nets entity memory is port vdd in std logic end entity UPF specification create power domain mem pd elements mem connect supply net vdd switchable ports mem vdd Usage Note When automatic connection semantics are applied simulation semantics of all the instances whose ports are automatically connected will be disabled This may display a notification message similar to the following Note top upf 12 vopt 9693 Power Aware simulation semantics disabled for testbench rtl top mem It is recommended that you use vopt suppress 9693 to suppress this message Supply Nets This section describes how to use UPF commands with Power A ware simulation to define supply net behavior for Power A ware Resolving Drivers on a Supply Net Supply nets are often connected to the output of a single switch However if you have a design where the output of multiple switches are connected to the same supply net you need a resolution mechanism to determine the state and voltage of the net depending on the values supplied by th
137. ation data retention and other aspects relevant to power management of an electronic design The UPF file is the key to using Power Aware verification on your design This file provides the following information required to overlay RTL or gate level verification with the power control network and Power Aware functionality Power regions voltage domains and power islands Power Aware Simulation User s Manual v10 2c 169 UPF Commands and Reference UPF Standards Retention sequential models their type and the regions they are in e State and output corruption behavior in power down situations Power control signals and the portions of the design they control Using a UPF File as Part of Power Aware Simulation The following procedure describes how to use a UPF file as part of basic Power Aware simulation see Using the Standard Flow 1 Use a text editor to create a UPF file that contains commands that specify the Supply Network over your design These commands are TCL functions as described in the current UPF standard 2 Specify this UPF file as part of the vopt command using the pa upf switch as follows vopt o opt top Design Top pa upf upf file Result vopt creates a parallel hierarchy that contains the power supply network of the design This hierarchy also triggers the control signals that are used to control corruption retention or isolation Also Power A ware data is written to either the current
138. ation of not supporting enum types For ports of type enum Power Aware reverts to the implementation approach used in previous releases In that approach an isolation cell is not actually inserted into the design Instead internal mechanisms such as the force command make an existing design port highconn or lowconn behave as if isolation were present Note that the isolation effect of these two approaches is identical you will see exactly the same results in reports and in the GUI The only difference is that the new architecture shows explicit instances of isolation cells that have been added to the design Defining Retention To define retention registers in a power domain and set the corresponding save and restore signals for the retention registers you use the set retention command in your UPF file In particular you can use the following arguments which are supported only in UPF v2 0 to define your retention strategy e retention supply set Defines the supply set used to power the logic inferred by the retention name strategy Power Aware Simulation User s Manual v10 2c 291 UPF Commands and Reference Supply Nets no retention Storage elements specified by this argument are prevented from having retention capability use retention as primary Specifies that the storage element and its output are powered by the retention supply retention supply set Description This argument defines the sup
139. ations event event event event event event endif pa store value pa store x pa restore value pa restore x pa corrupt register pa reset register PA RTL FUNC ifdef PA GLS FUNC Functionality in this section is used only in Gate Level simulations or in the verification of the PA RTL functionality triggering of the appropriate events at the appropriate time initial begin Q ret_val restore_value posedge_power_w_reset negedge_ret_w_reset reset_active end always Lue mm oo0ooooo PWR RESET RET reg_q ret_value Would not be needed in GLS posedge_power_w_reset negedge_ret_w_reset begin output_mux if PWR begin Q lt 1 bx end else if posedge_power_w_reset Q lt reg_q else if negedge_ret_w_reset Q lt reg_q else if RET begin Q lt reg_q_ret end else Q lt reg_q end Power Aware Simulation User s Manual v10 2c always RESET begin reset active RESET end Model Construction for Power Aware Simulation Example Register Model always posedge CLK or negedge RESET begin ff process if RESET reg q lt 1 b0 else reg q lt D end always posedge CLK begin ret_ff_process if RET reg q ret lt D end always posedge RET begin ret value lt reg q end always negedge RET always negedge PWR restore
140. avior to follow UPF 2 0 specification as well 1 http www accellera org Power Aware Simulation User s Manual v10 2c 171 UPF Commands and Reference Supported UPF Commands UPF 2 0 Syntax Differences You can review the specifications for UPF 2 0 and UPF 1 0 to determine the syntax changes between the two The UPF command upf version defines the syntax within the UPF file If you do not specify this command Power Aware simulation assumes the version is UPF 2 0 UPF 2 0 Semantic Differences By default Power Aware simulation applies the semantic behavior applicable to UPF 2 0 however you can override this behavior by specifying the pa_upfversion 1 0 option with your vopt command The following are some noticeable differences between UPF 2 0 and UPF 1 0 Default port state OFF in UPF 2 0 while FULL ON in UPF 1 0 Refer to the section Detailed Support for supply net type for more information You can control the behavior specific to this semantic difference with the defaultoff argument to the vopt pa enable or pa disable switches Undetermined state functionality This state did not exist in UPF 1 0 This impacts power switch behavior and resolution semantics Refer to the section Detailed Support for supply net type for more information You can control this behavior with the undeterminedstate argument to the vopt pa enable or pa disable switches ACK port behavior This requires a mandatory supply
141. b out in the example below This net can be used as a control signal The following are not supported Logic nets with the same name but different creation scope Dumping of logic nets with save upf command Implicit port net semantics for logic ports nets Example set scope tb create logic net net tb set scope tb pmb connect the logic net to an output port on the power management block connect_logic_net net_tb ports pmb_out set_scope tb dut create_logic_port p_dut create_logic_net net_dut connect_logic_net net_dut ports p_dut set_scope connect_logic_net net_tb ports dut p_dut 198 Power Aware Simulation User s Manual v10 2c UPF Commands and Reference create logic port create logic port Support for UPF Standard v1 0 no v2 0 yes Arguments Comments Restrictions Usage Notes The following are not supported Implicit port net semantics for logic ports nets Application of isolation strategies on logic ports Power Aware Simulation User s Manual v10 2c 199 UPF Commands and Reference create power domain create power domain Support for UPF Standard v1 0 yes partial v2 0 yes Arguments Argument simulation only Comments Restrictions elements See Usage Notes below include scope supply scope define_func_type update Allows adding elements and supplies to a previously created power domain for a progressive
142. ble is not specified or is incomplete Warning vopt 9693 UPF LS STATIC CHK Found Total 1 Not analyzed level shifters Valid Level vopt pa checks svl Indicates the valid level shifters that have matching Shifter voltage information and proper direction of shift Also see Reporting for a Valid Level Shifter Note vopt 9693 UPF LS STATIC CHK Found Total 2 Valid level shifters Uninserted vopt pa checks sdl Reports level shifter strategies that are defined with the Level Shifter set level shifter no shift command in UPF file but are not inserted Inferred type Not inserted count 1 Source port tb TOP bot4 bot5 outl bot LowConn Domain pd bot gt Sink port tb TOP bot4 outl bot HighConn Domain pd top All Static vopt pa checks sl Enables all static level shifter checks Writes Static Level Shifter Checks report to report static txt file Checks All Static vopt pa checks s Enables all static level shifter and static isolation Checks checks Power Aware Simulation User s Manual v10 2c 75 Automatic Checking Static Checking in Power Aware Level Shifter Cell Instance Checking If you have used the set level shifter instance command in a UPF file to instantiate RTL level shifter cells Power Aware simulation will detect those cells and perform the following level shifting checks on them instance checking results are written to report static txt
143. ble maps OFF to 1 ON to 0 and PARTIAL_ON to X Note that this reverses the default conversion values 264 Power Aware Simulation User s Manual v10 2c UPF Commands and Reference Supported UPF Extensions e Usea predefined VCT provided by Questa see Predefined VCTs Supported from the UPF Standard to perform the conversion mapping In this example the UPF GNDZERO2VHDL SL table performs this conversion Note SE Using a predefined VCT is easier but it requires implementation of UPF 2 0 IEEE Std 1801 2009 so both methods are shown here 2 Implement the VCT conversion in your UPF file by using the vct argument of the connect supply net command Continuing with the examples from Step 1 use either one of the following e Assign the name of the VCT you defined upf2vhdl vss to the vct argument connect supply net power supply net HDL port vct upf2vhdl vss Assign the name of the predefined VCT you selected UPF GNDZERO2VHDL SL to the vct argument connect supply net power supply net HDL port vct UPF GNDZERO2VHDL SL Supported UPF Extensions Using pa upfextensions The pa upfextensions argument to the vopt command allows you to define and apply various UPF behaviors that are not supported by the current standard UPF v2 0 Table C 5 lists the values for this argument that you can specify to override supported UPF behavior Syntax vopt pa_upfextensions default all
144. both isolation cell and retention cell Assuming it to be a isolation cell Power Aware Simulation User s Manual v10 2c 41 Power Aware Simulation Applying Power Intent to the Design Automatic Insertion of Power Management Cells Power Aware simulation inserts power management cells level shifter isolation and retention into the netlist based on UPF strategy commands You can selectively disable each type of insertion with the following vopt arguments e pa disable insertiso to disable isolation cell insertion e pa disable insertls to disable level shifter cell insertion e pa disable insertret to disable retention cell insertion For pure gate level designs in which all isolation level shifting and retention cells are already all present and therefore none of these cells need to be inserted the following vopt argument can be used as a shorthand pa gls equivalent to pa disable insertiso pa disable insertls pa disable insertret Automatic Corruption and Retention of UDPs Power Aware simulation detects sequential UDPs in the design and applies corruption or retention behavior based on the corresponding UPF strategies This functionality is not supported in the no optimization flow In that flow a warning will be issued if there is any sequential UDP in the design UDP Corruption and Retention Modes This section defines different modes of operation of the retention and corruption logic f
145. bout the selection FSM View Menu For Power Aware State Machines 122 Table 7 5 FSM View Menu Specific to Power Aware State Machines FSM View Menu Item Show States Table Toggles the display of the states table for supply sets and power domains Show States Counts Show Transition Counts Displays the coverage counts for each state in the state bubble Displays the coverage counts for each transition Show Transition Conditions Displays the condition for each transition Enable Info Mode Popups The condition format is based on the GUI_expression_format Operators Displays popup information when you hover over a state or transition Track Wave Cursor Displays current and previous state information based on the cursor location in the Wave window Power Aware Simulation User s Manual v10 2c Visualization of Power Aware Operations Power State and Transition Display Table 7 5 FSM View Menu Specific to Power Aware State Machines cont FSM View Menu Tem Transitions to Reset Controls the display of transitions to a reset state e Show All e Show None will also add a hide all note to the lower right hand corner Hide Asynchronous Only Combine Common Transitions default creates a single transition for any transitions to reset that use the same condition The transition is shown from a gray diamond that acts as a placeholder Options Displays the FSM D
146. c Isolation Checks cont Check Usage Syntax Description Example Message Missing vopt pa_checks umi Catches failure occurring whenever source domain is Isolation OFF and sink domain is ON for a power domain Cell crossing and isolation strategy is not specified for that domain crossing Error vsim 8929 MSPA UPF MISSING ISO CHK Time 130 ns Missing isolation cell for domain boundary PD midl PD wrapper2 for following Source port tb TOP midl outl bot connected mask 1 LowConn Sink port tb TOP mid2 wrapperl wrapper2 inl connected mask 1 LowConn File test upf Line 25 Power Domain Power on vopt pa checks upc Catches switching off of retention isolation supplies during active retention isolation period Error vsim 8920 MSPA UPF PG CHK Time 0 ns Power for Isolation strategy ISO FA4 1 3 of power domain PD_FA4_1 is switched OFF during isolation File test upf Line 121 Power Domain PD FAA 1 vopt pa_checks 1 Enable isolation checking performed by all arguments this value enables only iep idp irc icp ifc and it Dynamic Level Shifter Checking You enable dynamic checking functions for level shifters by using the vopt pa checks command The value you specify determines the checking function performed as shown in Table 5 5 Operating Voltage for Dynamic Checking It is recommended to change the operating voltages of those domains during simula
147. ce options All of these power management techniques must be implemented in a manner that preserves the intended functionality of the design This requires creation of power management logic to ensure that the design operates correctly as the power supplies to its various components are switched on and off or switched between voltage levels Since this power management logic could potentially affect the functionality of the design it is important to verify the power management logic early in the design cycle to avoid costly respins Power Management Specification The power management architecture for a given design could be defined as part of the design and ultimately it will be a part of the design s implementation A better approach however is to specify the power management architecture separate from the design This simplifies exploration of alternative power management architectures reduces the likelihood of unintended changes to the golden design functionality and maintains the reusability of the design data This is the approach supported by IEEE Std 18017M 2009 Standard for Design and Verification of Low Power Integrated Circuits This standard is also known as the Unified Power Format UPF version 2 0 Initially developed by Accellera UPF is currently supported by multiple vendors and is in use worldwide 5 Power Aware Simulation User s Manual v10 2c 321 Supplemental Information Power Aware Verification of ARM Based Desig
148. ces between RTL and GLS UPF commands for the power specification file Reporting of results Design General discussion of low power design and Power Aware simulation 16 Power Aware Simulation User s Manual v10 2c Getting Started With Power Aware Simulation Contents of This Manual HDL models used for Power Aware simulation Flow General discussion of low power analysis as part of overall design flow The distinctions between RTL and gate level simulations and the advantages of each at different points in the flow Contents of This Manual This manual contains both an introductory overview of the Power Aware simulation capabilities and detailed reference information about Power A ware simulation features and usage Chapters 2 through 6 provide an introductory overview of basic usage Appendices A through F provide more detailed reference information How to Use This Manual If you are just beginning to learn about Power Aware simulation read the following chapter Concepts for Using Power Aware Simulation If you are looking for an overview of Power Aware simulation concepts and capabilities and how they are used read the following chapter Power Aware Simulation If you are looking for an overview of the information provided by ModelSim during power aware simulation to help you understand how active power management is working in your design identify problem areas and track what has been verifi
149. cification VHDL entity memory is port vdd in std logic end entity UPF specification connect supply net vdd switchable ports mem vdd Explicit Connections to Supply Ports of Power Switch You can use the connect supply net command to define connections to supply ports of power switch For example create power switch SW input supply ports IN SW connect supply net VDD IN ports SW IN SW Power Aware Simulation User s Manual v10 2c 271 UPF Commands and Reference UPF Supply Connections You can also specify connections using the create power switch command For example create power switch SW input supply ports IN SW VDD IN Automatic Connections Questa supports the UPF automatic connection semantics of supply nets and supply sets as defined by IEEE Std 1801 2009 UPF v2 0 Automatic connections semantics are defined for Supply nets using the connect supply net command see Automatic Connections for Supply Nets Supply sets using either the connect supply set or create power domain command see Automatic Connections for Supply Sets The necessary conditions for the supply nets or supply nets of supply sets to automatically connected to the supply ports of design elements are Design element has a port with pg type attribute The pg type attribute includes o String type HDL attribute named either pg type or UPF pg type o Implementation library model with
150. cit logic suffix Not supported 220 Power Aware Simulation User s Manual v10 2c UPF Commands and Reference query design attributes query design attributes Support for UPF Standard v1 0 not applicable v2 0 yes Arguments Argument Comments Restrictions element model detailed Usage Notes Returns state information about attributes for a design element or model Power Aware Simulation User s Manual v10 2c 221 UPF Commands and Reference query port state query po rt state Support for UPF Standard v1 0 not applicable v2 0 yes Arguments Argument state Comments Restrictions detailed Usage Notes Returns state information for a specified port 222 Power Aware Simulation User s Manual v10 2c query power domain Support for UPF Standard v1 0 not applicable v2 0 yes partial Arguments Argument non leaf Comments Restrictions UPF Commands and Reference query power domain all not supported no elements detailed Usage Notes Returns parameters of a power domain Power Aware Simulation User s Manual v10 2c 223 UPF Commands and Reference query power state query power state Support for UPF Standard v1 0 not applicable v2 0 yes Arguments Argument Comments Restrictions state detailed Usage Notes Returns the state information for a power domain or su
151. ck The register output gets corrupted when the primary power or retention power goes off On primary power up and also if retention power is on retention behavior or normal behavior of the register resumes Retention power off corrupts the register output and the retained value regardless of the primary power For dual control signals the retained value and register value both get corrupted when save and restore signals are simultaneously active Modeling Bias Power Aware simulation provides support for bias modes that allow for state retention in a different manner In the power intent specification you can specify bias power states of the primary supply of a power domain to simulate bias functionality When you use a bias mode the power domain is powered on but running with reduced functionality Depending upon the 24 Power Aware Simulation User s Manual v10 2c Concepts for Using Power Aware Simulation Power Aware Modeling particular bias mode involved activity inside the domain may corrupt the contents of the domain Implementing a bias mode performs retention behavior without inserting explicit retention registers This saves in area usage and also helps to reduce the leakage power However the electrical characteristics of the domain during this period prohibit normal logic functioning and thus timing requirements may not be met Power Aware Simulation User s Manual v10 2c 25 Concepts for Using Power Aware Sim
152. clude memctrl memctrl pcf Search in memctrl subdirectory of current working dir include u home tsmith projs memctr Absol Corruption Extent Statement By default corruption semantics are applied onl corruption in power down situations should be a 304 memctrl pcf lute path to a PCF file to include y to what has been specified Frequently pplied more extensively The corruption extent Power Aware Simulation User s Manual v10 2c Power Configuration File Reference PCF Syntax and Contents statement allows the specification of the extent that corruption is applied in power down situations corruption extent CEXTENT extent keyword stmt end extent keyword OUTS SEQ AND WIRES OUTS AND SEQ OUTPUTS e OUTS SEQ AND WIRES corrupts registers and signals that are driven by logic which is powered down OUTS AND SEQ corrupts output ports and sequential elements within the power domain OUTPUTS corrupts only the output ports of a power domain Power Statements Power statements define voltage domains power islands mapping of inferred registers and latches to Power Aware models and corruption behavior power statement power control statement power model mapping Power Control Statement The power control statement defines the power islands by mapping a power control signal to the design power elements to which it applies power control statement POWER ta
153. connect supply net GND NE ports GND P3 create supply net VDD PR domain P3 set domain supply net P3 primary power net VDD PR primary ground net GND NE create power switch P1 SW3 domain P3 output supply port VDD SW VDD PRI input supply port VDD SW In1 VDD NET control port ctrll dut sleep on state full s1 VDD SW In1 ctrl1 off state off sO0 ctr11 Example 7 2 ModelSim Commands to Run Power Aware Debugging vlog sv mid v top v vopt pa upf test upf top debugdb vsim debugdb pa L mtiPA vopt do test do top Power Aware Simulation User s Manual v10 2c 111 Visualization of Power Aware Operations Power Aware Schematic Display Example 7 3 Schematic Displays for Power Aware Debugging Figure 7 3 Color Coded HDL Design Elements 112 Power Aware Simulation User s Manual v10 2c Visualization of Power Aware Operations Power Aware Waveform Display Figure 7 5 UPF Source File Right Click and Choose Power Domain View Selection E Declaration WwW Zoom Instantiation Fold Unfold D FSM Power Domain Expand Net To gt M Event Traceback r Highlight This Window 1 New Window Edit r Find Ctrl S show Figure 7 6 UPF Source File Hover the Mouse and View Tool Tip finterleaver_tester interleaverl in2wire DU Type Module DU Path work rdyacpt fast Power Domain PD in2w UPF file interleaver upf 77 create powe
154. control PD TOP retention3 domain PD TOP save signal ret3 posedge restore signal reti negedge set retention PD TOP retention2 domain PD TOP retention power net VDD net elements topl bot1 tdsig set retention control PD TOP retention2 domain PD TOP save signal ret2 posedge restore signal ret1 negedge set retention PD TOP retention1 domain PD TOP retention power net VDD net elements topl bot1 tdsig 0 0 set retention control PD_TOP_retentionl domain PD TOP save signal ret1 posedge restore signal ret1 negedge As a result of this UPF command no retention strategy is applied to top1 bot1 tdsig 0 1 Power Aware Simulation User s Manual v10 2c 293 UPF Commands and Reference Supply Nets Reports report upf txt Power Domain PD TOP File src bitwise 1 test upf 7 Creation Scope tb1 Primary Supplies power tb1 PD TOP primary power ground tb1 GND net Power Switch PD TOP sw File src bitwise_1 test upf 34 Output Supply port out sw PD TOP tb1 PD TOP primary power Input Supply ports 1 in sw PD TOP tb1 VDD net Control Ports 1 ctrl sw PD TOP tb1l pg Switch States 1 normal working ON ctrl sw PD TOP 2 off state OFF ctrl sw PD TOP Retention Strategy PD TOP retention3 File src bitwise 1 test upf 58 Retention Supplies power tb1 VDD net ground tb1 GND net No Retention Retention SAVE tb1 ret3 Retention
155. created supply set is treated as both the receiver supply and driver supply set receiver supply If you use this argument and if the receiving logic is within the logic design starting at the design root it shall be an error if its supply is not the receiver supply driver supply If you use this argument and if the driver logic is within the logic design starting at the design root it shall be an error if its supply is not the driver supply Command set pin related supply This command defines the related power and ground pins for signal pins on a library cell It conveys information similar to related power pin and related ground pin in Liberty but it may override them This command is restricted to only leaf library cells and non synthesizable hierarchical modules Attributes in RTL You can define the following attributes in RTL to specify the power intent of hard macros UPF related power pin Power Aware Simulation User s Manual v10 2c 153 Power Aware Commands and Options Simulating Designs Containing Macromodels e UPF related ground pin System Verilog Example UPF related power pin my Vdd output my Logic Port VHDL Example attribute UPF related power pin of my Logic Port signal is my Vdd UPF related power pin my Vdd output my Logic Port Liberty File You can define the following attributes at the pins in a Liberty file related power pin related ground pin
156. d el top vl forgen vl bot vil create power domain pd top vl Limitati forgen vl on lements top vh for genvh 1 bot vh inst inst elements top vh for genvh 1 bot vh inst bot vil inst Connections from UPF to HDL port of inout type are not supported for inout capability These connections are made in such a way that UPF is driving data to the HDL port Supported UPF Attributes Power Aware simulation supports the use of UPF attributes used to express the power intent in an HDL model You can specify these attributes using the following methods e UPF commands set design attributes set port attributes set isolation set pin related supply set simstate behavior set retention elements Power Aware Simulation User s Manual v10 2c 261 UPF Commands and Reference Supported UPF Attributes e VHDL or SystemVerilog attributes Liberty cell specification Table C 4 lists the UPF attributes supported by Power Aware simulation Table C 4 Supported UPF Attributes HDL Attribute Value s UPF Command UPF clamp value OlllZllatchlany set isolation clamp value value set port attributes clamp value UPF sink off clamp value Ol1lZllatchlany set isolation value sink off clamp value set port attributes sink off clamp value UPF source off clamp value Oll1lZllatchlany set isolation value source off clamp value set port attributes source
157. d in add power state command of various power states from power domains or supply sets A valid combination of two power states of domains supply sets is equivalent to a valid combination of power states of certain supply ports supply nets state and voltages Power Aware simulation uses this net state and voltage information to determine whether isolation or level shifting is required or not Note 3 For the cases where Power A ware simulation is statically not able to determine whether the state combination of two power domain supply sets is invalid or these power states cannot co exist at any point of time Power Aware simulation assumes it to be a valid state combination In the following example for static analysis Power Aware simulation assumes that PD1 ON and PD2_ON may co exist at some point of time Power Aware Simulation User s Manual v10 2c 275 UPF Commands and Reference UPF Supply Connections add power state PD1 state PD1 ON supply expr VDD1 FULL ON amp amp GND1 FULL ON add power state PD2 state PD2 ON supply expr VDD2 FULL ON amp amp GND2 FULL ON This information corresponds that VYDD 1 is FULL ON GND1 is FULL ON VDD2 is FULL ON GND2 is FULL ON may exist at some point of time Note 2 For better static analysis it is recommended to include the state information of primary 3 nets of power domain in supply expression of add power state for pow
158. dard flow or in the voptargs argument to the vsim command in the two step delayed optimization flow for example 38 Power Aware Simulation User s Manual v10 2c Power Aware Simulation Applying Power Intent to the Design vopt top pa upf top upf o DebugOut pa enable supplynetworkdebug other vopt args Then when you run simulation add the pa debugdir directory option which creates the necessary debug information for you to access post simulation for example vsim pa debugdir padebug pa DebugOut do log r run all After simulation has completed load the WLF file and debug database to perform any debug activities on the results vsim view vsim wlf pa debugdir padebug pa Debugging Designs Containing Liberty Cells To enable debugging of designs containing Liberty cells you need to specify the location of the Liberty library file s and you also need to specify the debugdb argument as part of the vopt command For example vopt libertyfiles a lib b lib debugdb This enables schematic viewing and causality analysis using Liberty logic cell definitions Note You can also enable debugging and schematic viewing by setting the MTI LIBERTY PATH environment variable to the directory location containing Liberty library source lib files prior to running the vopt step Applying Power Intent to the Design When you run a mixed RTL and gate level design through the power aware flow the fol
159. de ao Pores heh desea ee RA RE REI a ke 109 Schematic Window Visualization for Debugging 20 cee eee eee 109 Power Aware Waveform Display 5 2 ss ar e a RE VERE A EE REEF E 113 Using Power Aware Highlighting 122 ssesaeze e rr he RR 115 Power State and Transition Display lseleeeeeeeee eh 115 Power State and Transition Concepls iss crees aree ERE REG ERR eR a RE 115 Differences Between a Conventional RTL FSM and a PASM 116 Visualizing Power Aware State Machines susuusuuuuenua urunane 116 Power Aware State Machine List Window 0c eee eee eee eens 117 Power Aware State Machine Viewer Window 0 0 0 c eee eee eee ee 119 Power Aware Simulation User s Manual v10 2c 5 Table of Contents Appendix A Power Aware Commands and Options 0c cece cece cece cece cece ee eeees 125 ModelSim Commands Used for Power Aware 0 0 cee eee eens 126 Using pa_enable and pa disables 4 2 4 oi o6444 s ome RR 406445000 REALES 128 Additional Commands You Can Use with Power Aware 000 c eee eee eee 131 Power Awate MSSSIDOR 4 402035 24S ea her ew bY Rowse E Ha ed p e op Ieee 136 Dynamic Power Aware Check Message Control llleleleeeeeeleeeeee 136 CONCEPIS OF pa MSg euahecedetaderR Rt FDArdpr a P rPx dec Rede PIDE PE 136 Dse Model for pase os iaa pa Em MERSO Rack ex ew iren C a teu Bul ees 137 Option Descriptions of pa Ise ceo doee yq ERG UR
160. domain set isolation cd iso domain pd2 update elements hier inst leaf inst2 localout leaf set isolation cd iso domain pd3 update elements hier inst leaf inst3 localout leaf Incorrect usage example create composite domain cd subdomains pd2 pd3 supply primary pdsub ss set isolation cd iso domain cd update clamp value 0 applies to outputs isolation signal iso isolation sense high location parent elements hier inst leaf inst3 scanout leaf hier inst leaf inst3 localout leaf Error message Error test upf 90 UPF vopt PA 9809 The isolation strategy cd ret is defined on the composite domain cd Specifying elements or instances on this strategy is invalid Please specify the member elements instances on the subpower domains strategies by using the update argument Help message power aware Message 9809 A composite domain cannot contain design objects as elements members So a UPF command applied to a composite domain cannot cannot directly refer to design objects in its elements instances list These elements instances should be populated individually for each sub power domain using the strategy command with update argument after applying the strategy command on the composite domain set isolation control This command will be applied to all the subdomains of a composite domain set level shifter This command will be applied to all the
161. domains referred to as subdomains each of which has a primary supply set as necessary common property A composite domain contains these attributes primary supply set handles power states Operations on a supply set UPF v2 0 states that all operations performed on a composite domain are transitively applied to each subdomain This implies that many UPF commands may refer to a composite domain either directly using the domain s argument or by using a handle name in case of supply sets UPF commands applied on a composite domain are applied only to those domains that are present at that time in the subdomain tree of that composite domain they will not be applied to the subdomains added later Implementation e Checks o Ifa composite domain with the given composite domain name exists in the current scope you must specify the update argument or it will be flagged as an error Similarly if the composite domain is new and does not exist in the current scope it will be an error to use the update argument e Subdomains o For each subdomain provided in the subdomain list it will be an error if any of given rooted name does not match a power domain or composite domain in the current scope Power Aware Simulation User s Manual v10 2c 191 UPF Commands and Reference create composite domain Oo A domain can be a subdomain to multiple composite domains However this may lead to conflicting commands being applied on th
162. dut inst If pa_top is specifying the hierarchy other than UPF root scope then an Error message will be displayed Error src ss error l test upf 2 UPF vopt 9782 PA Top tb top dut inst top inst is specifying incorrect hierarchy for UPF scope DUT Do not use the vopt pa prefix and pa replacetop arguments with pa top If you do the pa prefix and pa replacetop arguments are ignored and a Warning message is displayed Warning UPF vopt 9780 Option pa prefix pa replacetop is not applicable with option pa top Ignoring option pa prefix pa replacetop Schematic Window Visualization for Debugging You can open the Schematic window to view debugging results from a Power Aware analysis In particular these results are shown as follows Power Domain All design elements are colored and highlighted according to their respective power domains see Figure 7 3 o Alldesign elements such as mux flip flops and gates are colored according to the power domain specification o The granularity of power domain visualization is at the instance level o Any simulation only power domains that are specified on a process or signal are not highlighted o Colorization supports up to 16 different power domains o Ifthe power domain is in the OFF state the schematic will be filled with a grey color see Figure 7 4 Power Aware Simulation User s Manual v10 2c 109 Visualization of Power Aware O
163. e PD mid2 normal File src testcase4 test upf 66 Supply Expression mid2 MAIN NET FULL_ON 4 20 amp amp mid2_GND_NET FULL_ON 1 30 Function States 1 Ground mid2 GND NET FULL_ON 1 30 Power mid2_MAIN NET FULL ON 4 20 Power State Combinations for connected domains Power Domain PD mid1 Power Domain PD wrapper1 PD midi off PD wrapperl1 normal Power Domain PD mid1 Power Domain PD wrapper2 PD midl1 off PD wrapper2 normal PD midl1 normal PD wrapper2 normal Power Domain PD midl Power Domain PD mid3 PD midl1 off PD mid3 off PD midl1 off PD mid3 normal PD midl1 normal PD mid3 off PD midl1 normal PD mid3 normal Power Domain PD wrapperl1 Power Domain PD mid3 PD wrapperl1 normal PD mid3 off PD wrapperl1 normal PD mid3 normal Power Aware Simulation User s Manual v10 2c 279 UPF Commands and Reference Value Conversion Tables Value Conversion Tables A value conversion table VCT is a UPF definition IEEE Std1801 2009 of how to convert or map a value from a supply net state relevant to an HDL variable type and from an HDL variable type to a supply net state This mapping enables complex modeling of connections between supply nets and RTL ports You can visualize which VCT is used for a given pin in the Wave window by hovering over the waveform for the port net as shown in Figure C 1 Figure C 1 Viewing VCT Information in the Wave Window WTE Hee
164. e User s Manual Power Aware Simulation User s Manual v10 2c 29 Power Aware Simulation Power Aware Simulation Flows For more information on using vlog refer to Invoking the Verilog Compiler in the User s Manual Usage vcom files vlog files Optimize After you compile the design use the vopt command with the following arguments pa top optional Specifies the hierarchical name of the design top instance If unspecified the default is the topmost instance of the design hierarchy pa upf Specifies the name of the UPF file containing the power intent specification Power Aware simulation reads the UPF file and generates information required to run Power Aware simulation pa lib optional Specifies a destination library in which the power aware information will be stored Note that you must use the vlib command to creates the library then use the library name as the value for this argument If unspecified the default is the work library O Specifies the name for the resultant optimized design Note that you can also specify any other vopt arguments for conventional optimization to create the optimized design This sequence is similar to the conventional three step optimization flow You can write the UPF power intent specification in one of two ways either with respect to the top of the design under test DUT or with respect to the top of the testbench TB If the UPF specification is written with res
165. e checks belonging to strategy iso mid2 pa msg all strategy iso mid2 It applies to all power aware checks which belong to the iso mid2 strategy only If you want to control iso mid2 of tb TOP PD top only then you should specify pa msg all domain TOP PD top strategy iso mid2 or pa msg all scope tb TOP domain PD top strategy iso mid2 Enable all isolation checks at time 0 Before running simulation specify pa msg enable pa_checks i After this command and when simulation has run all failing isolation checks even those at time 0 will be flagged Controlling Power Aware Message Severity During vopt Stage You can use the following vopt arguments to suppress or control the severity of messages that occur while running Power Aware suppress lt msg_num gt Suppresses a particular message by its ID number msg_num Messages are not displayed and processing continues warning msg num Changes the severity of a particular message to Warning Messages are displayed and processing continues error msg num Changes the severity of a particular message to Error Messages are displayed and processing continues note msg num Changes the severity of a particular message to Note Messages are displayed and processing continues fatal msg num Changes the severity of a particular message to Fatal Messages are displayed and processing stops Applying different severity levels allows y
166. e eR DOR E E EE E OR CR RO ER OR 155 Liberty File Attributes 2664 656 x xo ERERERYSI KP ERE Neer REB CEA ee eee PET 156 Creating Feedthrough For RTL Conversion Functions eee 156 Appendix B Model Construction for Power Aware Simulation eere 159 Assumptions and Advantages 04 656 0s60 604 essed n e Ry ERRORES REA EE ees 159 Basic Model Structures sas vasa re rs E Aa eR ERE RS GAGS a ee EN RU CR Re RR Reg 159 Named Events in Power AWale 0550600 es 4 ghe vd xp eda s aas Su ea aui s 160 Usage Note for Sequence Requirements 0 0 0 162 ATCIDU OS s 12d bd oA dea EP red Ru ROC ADQUEMAPRAqCQE RS esbed K ROCA QUO p Adae S 162 Retention Cells and Memories 41uesae ce hex Rex ea eens wade sex a doi pr 162 Isolation Cells ease cou Ru REC cde ee Ghee shen Geese eee eee EE DES E CET 163 Devel SIGS 3 42 Gos NTC 163 Model buterface POMS 27 lt 822 deesde0sSteusesadeewhe Ca5R eerie pa deee nde a Seanad 164 Customizing Activity at Time Zero cu 2265 3405 runacr eR R 4404 aeons EC EeRE DURER 164 Example Register Model 2 0 0 0 eee eect eee eh 165 Examole omupt Model c2 2 45 522058 4s Pu eX RERIPU LAU ERIQMRERERIE de ERES 168 6 Power Aware Simulation User s Manual v10 2c Table of Contents Appendix C UPF Commands aud Referenc uns ka rien EE ERR RR oed RR X Oe Rm dn 169 Unified Power Format UPF sssr esreasis gerug nka pE ees 169 Using a UPF File as Part of Power Aware Simulation 0000
167. e each of the individual switches Version 1 0 of the UPF Standard UPF v1 0 defines the semantics of using the create supply net command to determine the resolution of different drivers on a supply net In UPF v1 0 the resolution is mainly dependent on the state and voltage value of the supply network In particular the resolve argument provides the following values which you to select a method of multiple drivers on a supply net refer to Section 5 1 5 unresolved one hot parallel Power Aware Simulation User s Manual v10 2c 287 UPF Commands and Reference Supply Nets Note that resolution can only be defined on the supply net and not on supply ports As a result you can have multiple ports driving a supply net but not multiple supply nets driving a supply port Example In the following example ports p1 p2 and p3 are driving the resolved supply net resol net which has one hot resolution specified A voltage value and supply state would be driven on resol net depending on the resolution one hot specified and the state of the drivers p1 p2 p3 In a case of a error in resolution the supply net is turned off and voltage value is driven to 0 An error message is displayed that lists the voltages and states of all the drivers The following is an example of the error message for one hot and parallel resolution respectively set scope tb create power domain PD TOP create suppl create suppl create
168. e exclude file bot mod 2 3 top mid Log messages for the vopt command Note vopt 9691 Excluding power aware module bot mod2 in path top instl Note vopt 9691 Excluding power aware module bot mod3 in path top inst2 Examples Excluding Signals Nets The following examples show entries in the exclude file 1 Direct Power A ware processing to skip signal net sig present in all instantiations of bot mod found within the instance top t1 Entry in the exclude file bot mod top tl s sig Log messages for the vopt command Power Aware Simulation User s Manual v10 2c 143 Power Aware Commands and Options Excluding Design Elements from Power Aware 144 Note exclude txt 1 vopt 9013 Excluding signal sig in power aware module bot mod in path top ti sig A warning message will be reported if there was no match found in exclude file for signal sig in module bot mod in instance top t1 Warning exclude txt 1 vopt 9014 No match found in exclude file for signal sig in module bot mod in instance path top t1 Direct Power Aware processing to skip signals or nets sig2 sig3 sig4 present in all instantiation of bot mod found within the instance top t1 Entry in the exclude file bot mod top t1 s sig 2 4 Log messages for the vopt command Note exclude txt 1 vopt 9013 Excluding signal sig3 in power aware module bot mod in path
169. e isolation power net of associated isolation strategy UPF_ISO_GND Specific to ModelSim Refers to the isolation ground net of associated isolation strategy UPF GENERIC DATA Refers to the port on which the cell is to be placed UPF GENERIC OUTPUT Refers to the output of the isolation cell isolation signal Refers to the isolation control signal of associated isolation strategy isolation signal index Not supported isolation supply set function name The function name extension refers to the supply net corresponding to the function it provides to the isolation supply set isolation supply set index function name Not supported Example C 6 Specifying Argument Values for map isolation cell set isolation ISO GEN domain CO isol ation power net PDO VNET ISO OUT clamp value 1 appl ies to outputs set isolation control ISO GEN domain CO isol ation signal tb iso isol ation sense low location parent 216 Power Aware Simulation User s Manual v10 2c UPF Commands and Reference map isolation cell map isolation cell ISO GEN domain CO elements mid inst outi lib model name iso cell 0 vh port iso UPF ISO ENABLE map isolation cell ISO GEN domain CO elements mid inst outi lib model name iso cell 0 vh port iso tb iso port cell in UPF GENERIC DATA port cell out UPF GENERIC OUTPUT Power Aw
170. e power domain boundaries The following UPF commands would be used to define these power domains l elements mcO0j Create power domains A create power domain PD top create power domain P create power domain PD mem ctr create power domain PD sram el Power Aware Simulation User s Manual v10 2c lements ml m2 m3 m4 323 Supplemental Information Power Aware Verification of ARM Based Designs The elements option on each command lists the instance names of the elements to be included in the specified power domain Power Distribution Each power domain may have one or more power supplies The primary supply provides power for most of the functional elements in that domain Additional supplies may provide power for retention isolation or level shifting cells associated with the power domain The primary supply may be a switched supply which can be turned on and off via a control input to the switch Either the VDD or VSS supply may be switched A supply may be driven by multiple switches connected to the same voltage source The switches are turned on incrementally to minimize rush currents when the supply is switched on A supply may also be driven by multiple switches connected to different voltage sources so that the supply voltage level delivered to elements of t
171. ecifies the active UPF scope Specifies the simulation simstate behavior for a model or library upf version 176 Specifies the UPF version for interpreting subsequent commands Power Aware Simulation User s Manual v10 2c UPF Commands and Reference add domain elements add domain elements Support for UPF Standard v1 0 yes v2 0 yes Arguments Argument Name Comments Restrictions Usage Notes This command adds design elements to the power domain Power Aware Simulation User s Manual v10 2c 177 UPF Commands and Reference add port state add port state Support for UPF Standard v1 0 yes v2 0 yes Arguments Comments Restrictions Eme LT Usage Notes Adds state information to a supply port which can represent off chip supply sources that are not driven by the test bench 178 Power Aware Simulation User s Manual v10 2c UPF Commands and Reference add power state add power state Support for UPF Standard v1 0 no v2 0 yes Power Aware Simulation User s Manual v10 2c 179 UPF Commands and Reference add power state Arguments Argument Comments Restrictions state The name you specify here is simply an identifier it has no semantic meaning supply expr Including but not limited to support for power FULL ON similarly SS power FULL ON primary SS Statel similarly PD primary SS_State1 primary power FULL ON similar
172. ecify an absolute path name not starting with a slash then scope becomes design scope scope name For example assuming the design top scope is tb pa msg scope TOP mid1 the scope of the command will be tb TOP mid1 strategy strategy name This option selects a power aware check belonging to the specified strategy If you use this option with domain then checks belonging to domain strategy will be selected For example the following command will select the Isolation functionality check associated with message 8931 for isolation strategy iso top pa msg 8931 strategy iso top The following command will select all isolation checks which belong to strategy iso mid1 of power domain Scope Of Command gt PD_mid1 pa msg pa checkszi domain PD mid1 strategy iso mid1 This option will be ignored if you use it to finely control checks that do not belong to any strategy For example the following checks do not have any UPF strategy o Power domain status check pa_checks p which refers to message 8902 o Power domain toggle check pa checks t which refers to message 8908 o Missing level shifter check pa_checks uml which refers to message 8915 o Missing isolation check pa checks umi which refers to message 8929 o Non retention register reset check pa_checks npu which refers to message 8912 Note MM MM It the specified strategy name does not
173. ed as they facilitate the ability of tools to easily identify header information that has meaning to them HEADER VERSION 2 0 SEPARATOR VENDOR_MGC_SOURCE PX VENDOR MGC SOURCE VERSION 2006 05 Context Statements By setting the current design scope as the implicit prefix to all instance paths you can significantly reduce the amount of text required in the PCF Context statements provide the ability to define specific context items that apply to all power and context statements that follow until another context statement makes a subsequent change context statement Scope statement variable statement include statement corruption_map_statement 302 Power Aware Simulation User s Manual v10 2c Power Configuration File Reference PCF Syntax and Contents corruption extent Scope Statement The scope statement sets the current scope context within the hierarchy of the design being verified including the test bench All relative paths used in subsequent context or power statements will be equivalent to an absolute path starting with the current scope and proceeding through the relative path specified in the statement The most recent scope statement shall apply to each relative path specified in the PCF Scope statement SCOPE instance path stmt end instance path relative path absolute path relative path hdl identifier separator character hdl identifier
174. ed read the following chapters Power Aware Reports e Automatic Checking Visualization of Power Aware Operations e UPF Commands and Reference For more detailed reference information about specific topics such as UPF and its use Power Aware simulation commands and flows report formats messages read the appropriate appendices of this manual Power Aware Simulation User s Manual v10 2c 17 Getting Started With Power Aware Simulation How to Use This Manual Related Documentation Other documents that may be useful for understanding Power Aware simulation include the following 18 ModelSim User s Manual This manual explains how to use ModelSim for simulation of hardware designs It contains descriptions of basic ModelSim usage especially simulation optimization debugging assertions and GUI visualization of design source schematics and waveforms ModelSim Reference Manual This manual contains a comprehensive listing and description of ModelSim commands arguments and values ModelSim Tutorial This manual presents an introductory tutorial on the use of ModelSim for Power Aware simulation It provides a simple exercise on how to run a Power Aware simulation on RTL design data for the Interleaver example provided as part of the ModelSim installation This exercise includes creating a UPF power intent specification defining isolation and retention for the power domain and evaluating simulation results waveforms
175. ed PE AID PNE EI PE ese 198 Greate TOf POs cxx oper Rec E E ERGARa E np S hod cd pe eut eho 199 create DOWOI COMIN ode RETRPCDRE C RA RECTA Seb anes Fa quU Pe E RE ERE 200 create power SWitCh dace cd hoards adu tt de deaa abd aan a dare ACRI eon 202 create pst ios Vedas OR OSES bx RARE A or equi Ped acd e Rab uy 203 create s pply H t MPPCITC x 204 create Supply port iz azeRazdesxecet del tiasana ikiita REA RAER E 205 creat SUDDIS SEL eid ossa a eudan t Doa deed i a E HUE d a Ea d iced i e 206 create pl 2nd Vel i22 eet ke eR IER Gas aves Y qa P Gedo eas ERE KR RE EETR DRE 207 find DBIeblSsu eoe bi ecxRE ERI eater odes EAD EDS MURCIA EPA EM P e EE 208 l d s mstate BelidvIOE aso ezerkek kselaee 4 Ee RERAREARONXAGR AX RENE REGE AGE 210 load ME Trpo 213 Ipad MPT pr tect d ic ih oo sh oa ipn eo GN been e Rack eR dU Wines d qa A RR Be ees 214 Map 150 4000 cell ceecmeedye sed tease soe eevee rch beds IDE PENES Gd UM EE 215 m p level shitter Sell 244 2 chacdwies nse a Ree I ena ades DX Ru 218 map retention cell adis E Re RRREd ES eadadsee saga Eg dx ddasi e 2 9 nz esu m 220 query design attributes epa REY ed dls RR GR HORGUCRROREN RU ER RO EN RO eae 221 query port st t s C dea oi oct dU Re ceo a acteur UE Sono DR Net EUR De acad RERO 222 query power dofmdll isizikeczuee be RR RAE ERRARE ERR ERE RRRTIqunE dq 223 CUCEY p wWer State PP mm 224 que POWer AWC 4 03 0
176. ed at the RTL or higher levels through specification of output corruption However it is necessary to attribute the gate level library isolation cell models to ensure that the gate level design matches the verified and specified RTL or higher functionality The is isolation cell attribute is Boolean Example is isolation cell According to IEEE 1364 is equivalent to is isolation cell 1 Level Shifters this Level shifters imply no functional behavior at RTL or higher However they are required to ensure proper operation and scaling of signal values from one voltage domain to another Attributing level shifter cells in the gate level library ensures the gate level design matches the verified and specified RTL or higher design specification The is level shifter attribute is Boolean Example is level shifter According to IEEE 1364 is equivalent to is level shifter 1 this Power Aware Simulation User s Manual v10 2c 163 Model Construction for Power Aware Simulation Model Interface Ports Model Interface Ports The model must define the necessary ports using the names as specified in this section All ports are required even if the optional functionality does not apply to a specific inferred register or latch This port interface specification allows generic models that can be applied to a variety of inferred registers and latches Al
177. efinition and PCF coverage of all inferred sequential elements with as few power model mapping statements as possible When the cell type is specified then only inferred sequential elements that match that type are mapped to the Power Aware model specified in the mapping statement The cell types are defined as follows Oo FF CKHI Inferred registers flip flops active on the positive edge of the clock signal FF CKLO Inferred registers active on the negative edge of the clock signal FF CKFR All inferred registers regardless of the edge sensitivity of the clock signal LA ENHI Inferred latches active when the enable signal is high LA ENLO Inferred latches active when the enable signal is low LA ENFR All inferred latches regardless of the level sensitivity of the enable signal ANY CKHI Generically matches any inferred sequential element register or latch that is active on the posedge of a clock or high level of an enable signal That is this cell type is equivalent to two mapping statements that are identical except for cell type where one statement cell type is FF CKHI and the cell type of the other equivalent mapping statement is LA ENHI Power Aware Simulation User s Manual v10 2c 311 Power Configuration File Reference PCF Syntax and Contents Oo ANY CKLO Generically matches any inferred sequential element that is active on the engaged of a clock or low level of an enable signal That is
178. el power domains Because a composite domain can contain only subdomains supply sets and power states Power Aware simulation does not store strategies nets or other objects on it As a result these commands appear as multiple commands applied to each power domain that was a part of the subdomain hierarchy of a composite domain In uninterpreted mode Power A ware simulation saves the command texts as is and the create composite domain command may appear multiple times with update Also the commands applied on a composite domain are directly dumped Power Aware Simulation User s Manual v10 2c UPF Commands and Reference create composite domain Interaction of composite domains with other UPF commands add power state associate supply set In Section 6 15 of UPF v2 0 It is valid to refer to the primary supply of a composite domain because there is exactly one primary supply common to all subdomains It is not valid to refer to other supply set handles or strategies in the composite domain because they are not necessarily common to all sub domains This statement asserts that you cannot refer to a supply set handle in a composite domain other than primary supply set Currently the associate supply set command is supported only for the primary supply For other supplies you can associate them by using either of the following Ways o associate supply set on each sub power domain individually o using create composite domain upda
179. ells Static vopt pa checks sdi Reports isolation strategies as Not inserted when Not Inserted isolation is not required for a power domain crossing and isolation strategies specified with set isolation no isolation Warning vopt 9750 UPF ISO STATIC CHK Found Total 1 Not inserted isolation cells All Static vopt pa checkszsi Perform all static isolation checks smi sri sii svi Isolation sni sdi Checks Isolation Cell Instance Checking When you use the set isolation instance command in a UPF file to instantiate RTL isolation cells Power Aware simulation detects those cells and performs the following isolation checks on them reporting the information in the file report static txt Incorrect Isolation Check Total Incorrect isolation cells Source power domain PD mid1 gt Sink power domain PD mid2 Total count 1 ISO count 1 Candidate Port tb TOP mid1 outl_bot connected mask 0001 count 1 Isolation cell tb TOP isoinsti1 O ISO AND Domain PD mid1 Source port tb TOP mid1 out1 bot connected mask 0001 count 1 LowConn gt Sink port tb TOP mid2 in1 bot connected mask 0001 count LowConn e Valid Isolation PD mid2 Total count 1 Power Aware Simulation User s Manual v10 2c 73 Automatic Checking Static Checking in Power Aware 1 ISO count 1 Candidate Port tb T
180. els of Power Aware cells These models encapsulate the Power Aware behaviors of various types of design state such as clock low retention flip flops and active high retention latches Verilog HDL constructs and attributes for Power Aware models provided by a silicon or library vendor These models trigger relevant events for the simulator to modify the runtime behavior of the design Typically these modifications consist of corrupting states and output values and storing or restoring state values based on power control network activity Typically your UPF power specification file relates inferred registers or latches to these models However it is possible to capture Power Aware functionality in combination with register and latch functionality in a single model Because of this you can create Power Aware models in Verilog to specify Power A ware behavior for inferred registers and latches as well as provide the functionality directly through direct instantiation of the Power Aware models Combining both of these functional descriptions in a single model facilitates the testing of the model for use in Power Aware verification Noe Use of these models is only allowed in the novopt simulation flow Refer to the section Using the No Optimization Flow for more information Assumptions and Advantages The silicon foundry is respon
181. emptedimmed switch 3 Generate UCDB refer to the section Generating a UCDB File for Power Aware 4 Generate reports refer to the section Generating Power Aware Coverage Reports 5 Analyze data after simulation refer to the section Accessing Coverage Data for Post Simulation Analysis Concepts 94 Dynamic check coverage A particular dynamic check will be performed when test vector will provide stimuli so that check is hit in simulation For example when you want to check for missing isolation cell for all power domain crossings you can enable this check with the pa check umi switch to vopt To trigger this check during simulation for a particular power domain crossing such as PD SRC gt PD SINK your test vector should create a stimuli such that power domain PD SRC is OFF and PD SINK is ON If test vectors are not creating this scenario then this particular Power Aware Simulation User s Manual v10 2c Power Aware Coverage Power Aware Coverage Collection dynamic check will not be hit during simulation In this case see that there are no missing isolation cells in the design but in fact this check is not even hit by test vectors PA Check Exclusions Any power aware checks for gate level cell instance scopes will not be taken into account for coverage In this case they will be excluded for coverage calculation You can find the list of excluded assertion information in the report pachecks excluded
182. ents in rtl region definition is OFF retention specification optional The power control statement may optionally specify the signal s used to control retention behavior throughout the power island defined by the power control statement The retention specification is described in the section Retention Statement POWER VDD voltage specification optional To facilitate a concise specification in the situation where the voltage domain and the power island are the same the power control statement may optionally specify the operating voltages for the power island voltage domain The voltage specification is described in the section Voltage Domains Region Definitions The region definitions are a list of signal instance and process definitions This will allow declaring a power island by specifying various combinations of elements which are controlled by the power island on off state region definitions region definition region definition region definition signal definition instance definition process definition signal definition s hdl path instance definition i nr hdl path process definition p hdl path In each region definition the HDL path is relative to the context that has previously been set through a SCOPE statement The path must terminate at an object or scope appropriate for the type of definition a signal or port block instance or process instance 3
183. er domain or its associated supply set Also to determine the state relation between two power domains supply sets Power A ware simulation uses the information specified in power states of those two power domains supply sets For example create supply net VDD create supply net GND set domain supply net PD1 primary power net VDD primary ground net GND add power state PD1 state PD1 ON logic_expr PD2 PD2 OFF supply expr VDD FULL ON amp amp GND FULL_ON Determining State Dependency with add power state Arguments You can use the following arguments of the UPF add power state command to determine whether power states of different power domains can co exist e logic expr e supply expr The following examples show various ways of using these arguments Example C 22 Dependency Specified with add power state logic expr Case 1 In this example from logic expr of PD1_S1 Power Aware simulation determines that state PD1_S1 and PD2 S2 cannot co exist add power state PD1 state PD1 S1 logic_expr PD2 PD2_S2 supply expr VDD1 FULL ON amp amp GND1 FULL_ON add power state PD2 state PD2 S2 supply_expr VDD1 FULL ON amp amp 276 Power Aware Simulation User s Manual v10 2c UPF Commands and Reference UPF Supply Connections GND1 FULL_ON Example C 23 Dependency Specified with add power state logic expr Case 2 In this example from logic exp
184. er s Manual v10 2c 117 Visualization of Power Aware Operations Power State and Transition Display Figure 7 8 Power Aware State Machine List Example Power Aware State Machine List States Transitions UPF TYPE VDD 0d99 port state info state var 2 4 PORT V VDD 0d81 port state info state var 2 4 PORT E vout_p_port_state_info state_var 3 9 PORT T 3S port state info state var 2 4 H top pst pst state info state var 3 9 PST VDD 0d99 port state info state var 2 4 PORT VDD Od81 port state info state var 2 4 PORT f VSS port state info state var 2 4 PORT L8 vout p port state info state var 3 9 PORT nm GUI Elements of the Power Aware State Machine List Window This section describes GUI elements specific to this window Column Descriptions Table 7 1 Power Aware State Machine List Window Columns Instance Instance name of the state machine The hierarchical display shows state dependency specifically those instances where states of a particular power state machine depend upon states of other power state machines States Number of states Transitions Number of transitions between the states One of the following PORT NET PST POWER DOMAIN SUPPLY SET 118 Power Aware Simulation User s Manual v10 2c Popup Menu Visualization of Power Aware Operations Power State and Transition Display Table 7 2 Power Aware State Machine List Window P
185. erageinfo PD_RAM_SS PS_PD_RAM_SS 75 0 100 Uncovered 100 0 100 Covered 1 1 Covered 100 0 100 Covered 1 1 Covered 100 0 100 Covered 1 1 Covered 100 0 100 Covered 4 1 Covered 14 2 100 Uncovered ET coverage instance tb CPU1 pa_coverageinfo PD_RAM_SS PS_TRANS_PD_RAM_SS 14 2 14 2 100 Uncovered 100 Uncovered ERO NNNNNWN ERO OOr oom ooo PRRRPBRPRRER NNQ El El ES e ZERO ZERO ZERO Covered Covered Covered ZERO ZERO Covered 0 1 ZERO ROORKKH GOS PRpprRrPP ERP 43 7 POWER STAT ERAGE 12 TYPES POWER AWARE CHECKs COVERAGE RESULTS Check Coverage Type Object Failure Pass Count Count Isolation Functionality Check tb CPU1 out alu UPF ISO pa iso cell checks vec mspa iso func chk 0 2 Isolation Clamp Value Check tb CPU1 out alu UPF ISO pa iso cell checks vec mspa iso clamp chk 3 2 Isolation Race Check tb CPU1 out alu UPF ISO pa iso cell checks vec iso port toggle pos iso toggle posedge 0 3 Isolation Race Check tb CPU1 out alu UPF ISO pa iso cell checks vec iso port toggle neg iso toggle negedge 0 2 Toggle Check tb CPU1 out alu UPF ISO pa iso cell checks vec mspa iso on act 0 Missing Level Shifter tb CPU1 pa missing ls check 1 mspa upf missing ls chk 0 4 Missing Isolation tb CPU1 pa missing iso check 2 mspa upf missing iso chk 102 0 4 Power Aware Simulation User s Manual v10 2c
186. es the simulator to release any forced values on a register If the register is combinational the simulator re evaluates the register 168 Power Aware Simulation User s Manual v10 2c Appendix C UPF Commands and Reference This appendix provides information on Unified Power Format UPF which is a standardized set of low power design specifications for use throughout design analysis verification and implementation Unified Power Format UPF e UPF Standards e Supported UPF Commands Supported UPF Package Functions Accessing Generate Blocks in UPF Supported UPF Attributes Supported UPF Extensions e UPF Supply Connections e Value Conversion Tables e Supply Nets Unified Power Format UPF You apply UPF as a user defined file that specifies the Power Aware characteristics of a design for use by the simulator UPF file format adheres to v1 0 of the UPF standard by default In addition Mentor also supports portions of v2 0 IEEE Std1801 2009 Mentor supports the use of the industry wide standard known as Unified Power Format UPF which consists of commands and statements in a Tcl text file that define the low power intent for a design A UPF file is designed to capture all Power Aware characteristics of the design at the RTL or gate level in a compact form that can be easily used by the simulator The scope of the UPF file is to provide a standardized format for specifying the supply network switches power isol
187. eset or clear The functionality of this port is optional and the port will not be connected if there are no inferred reset or clear conditions The tool infers the control signal and its polarity and will automatically negate the signal s value when it is connected to the model if it is active low or active negedge Power and retention ports may be connected to an expression involving two or more signals each Customizing Activity at Time Zero The default models present in the mtiPA library are equipped to handle any power aware activity at time zero 0 However there may be instances where you want to use your own custom simulation models for power aware verification In such cases if you require power aware activity at time 0 to be honored then you need to ensure that your models are equipped to do so 164 Power Aware Simulation User s Manual v10 2c Model Construction for Power Aware Simulation Example Register Model To utilize time zero corruption through your own models instead of the default ones mtiPA you must add som e extra logic in his model as follows parameter int pa timeO0param 0 initial begin 0 if pa timeOparam 1 amp amp PWR 1 bx PWR 1 50 pa corrupt register end The changed models like corrupt v andupf retention ret v etc have same extra logic as follows module CORRUPT PWR parameter int pa timeO0param 0 input event event PWR pa corrupt register
188. etention consists of saving the value of a design element in a power domain prior to switching off the power to that element then restoring that value after power to the element is switched back on The set retention and in UPF 1 0 set retention control UPF command determines which registers in a power domain need to be retention registers and set the corresponding save and restore signals for the retention registers In UPF you specify a retention strategy where state preservation is required e Latch flip flop or memory retention Retention power supply Retention controls to trigger retention 22 Power Aware Simulation User s Manual v10 2c Concepts for Using Power Aware Simulation Power Aware Modeling The general sequence for specifying retention in UPF is 1 Define your power domains create power domain 2 Specify the retention strategy a set of registers in the domain requiring retention set retention 3 Specify the retention control signals for the strategy set retention in UPF 2 0 set retention control in UPF 1 0 In simulation two additional processes are added for each register that is to be retained to model the retention behavior Oneis sensitive to the save signal in accordance to the save sense The second is sensitive to the restore signal in accordance to the restore sense A retention memory is also created for each sequential element that needs to be retained Edge sensitive and Le
189. example if tb is the design top the scope from which vsim was invoked then pa msg with no arguments applies to all objects from the tb scope While pa msg scope tb dut applies to all objects from the tb dut scope The pa msg command also applies to all objects from the scope of the command It also applies to all domains and all relevant objects from scope downwards specifically o If you specify domain the command is restricted to apply only to all instances within that domain o If you specify strategy or ports the command applies only to those objects with in the scope or domain o Any names specified with domain or ports should be relative to the scope of the command 136 Power Aware Simulation User s Manual v10 2c Power Aware Commands and Options Power Aware Messages Other examples show you how to apply the command to all objects of the power domain tb dut mid1 PD_mid1 pa msg scope tb dut mid1 domain PD_mid1 Also when you do not specify scope names associated with ports or domain are relative to design top pa msg domain dut mid1PD dut ports dut mid1 P1 dut mid1 P2 2 Use of all When you specify all the command applies to all dynamic power aware check messages pa msg lt options gt all Otherwise when you do not specify all it applies to all messages except the ones with severity NOTE pa msg lt options gt Disabling checks also disables assertions When yo
190. exist tool will flag a NOTE message as shown below and will ignore this option Warning vsim 4086 Strategy iso PD mid3 specified with strategy option not found e ports list of ports This option restricts your selection power aware checks for specified ports only where the names of ports should be relative to Scope of Command For example to select Isolation clamp value check for Ports tb TOP mid1 P1 and tb TOP mid1 P2 which belong to strategy iso_mid1 of power domain PD1 use the command pa msg pa checkszicp domain PD1 strategy iso mid1 scope tb TOP mid1 ports P1 P2 This option is applicable only to the following checks Power Aware Simulation User s Manual v10 2c 139 Power Aware Commands and Options Power Aware Messages o Isolation race check pa checks irc which refers to message 8910 o Isolation functionality check pa_checks ifc which refers to message 8931 o Isolation clamp value check pa_checks icp which refers to message 8930 o Isolation toggle check pa_checks it which refers to message 8908 If you specify this option with checks other than these you ll receive a NOTE message and the option will be ignored For example the command pa msg 8918 domain PD1 strategy iso mid1 scope tb TOP mid1 ports P1 P2 Issues the error Note vsim 4087 The command pa msg is ignored for message number 8918 as option ports is not applicable for this message number because po
191. f any data type for VHDL and SystemVerilog support The model communicates with the simulator only by triggering the defined named events The simulator will then map the event trigger into the appropriate Power A ware behavior for the inferred register or latch that the Power Aware model is associated using the Power Specification File The port interface to the Power Aware model can contain additional port declarations For example a Power Aware latch model might define enable data in and data out ports For the purpose of Power Aware RTL verification these additional ports are ignored and will not be connected to the design s functional network As additional ports are permitted but ignored it is feasible to define a Power Aware model that can be verified as functionally correct as it can be instantiated into a test circuit and exercised to ensure it triggers the Power Aware events at the appropriate time and that saved and restored values match what is expected A benefit of this approach is that a single Power Aware model can be created for both gate level verification and Power Aware RTL verification The gate level functionality can be used in gate level simulations and would include the cell s Power Aware functionality but not the triggering of the Power Aware events that are designed for use in RTL or higher abstraction level simulations The Power Aware events can be used without the overhead of the gate level functionality for
192. fined in the HDL It works on the logical hierarchy and only searches in the scope or in and below the scope when transitive is specified The search pattern can be any of the following exact pattern match tcl glob expression or regular expression There are different behaviors for case sensitivity e VHDL search is always case insensitive e Verilog search by default is case sensitive Use ignore case to set to case insensitive Note Search for a multi dimensional array of instances is currently not supported You can search for generates and within generate hierarchies when you specify the pa_upfextensions genblk argument with vopt Examples Tcl glob pattern matching examples find_objects top pattern a find_objects top pattern bc 0 3 find_objects top pattern e 208 Power Aware Simulation User s Manual v10 2c UPF Commands and Reference find objects find objects top pattern d f find objects top pattern g 0 Tcl Glob Search Find all nets find objects top pattern a object type net Regex Search Find Out ports find objects top pattern a object type port direction out regex Exact Search Find Process find objects top pattern a proc object type process exact Finding objects when generates are involved Given the following design hierarchy o Default mode find objects top pattern object type inst Return
193. g osw os o region definitions boolean expr retention specification POWER VDD voltage specification stmt end tag a name without any white space spaces tabs etc that provides a descriptive handle or identifier for the power island or power control mapping being defined osw os o command options that allow you to override the global corruption extent of the vopt pa ce command for specific power domains o OSW sets the corruption extent to outputs and sequential and non sequential wires o os sets the corruption extent to outputs and sequential elements o O sets the corruption extent to outputs only Power Aware Simulation User s Manual v10 2c 305 Power Configuration File Reference PCF Syntax and Contents For example you can use o to define a specific power domain with non synthesizable RTL to prevent register latch detection even though you the command line specifies vopt pa_ce os region definitions a list of signal instance and process definitions that allow the declaration of a power island by specifying various combinations of elements which are controlled by the power island on off state Refer to the section Region Definitions for detailed information boolean expr a Verilog boolean expression When the expression evaluates TRUE power to the specified elements in rtl region definition is powered ON When it evaluates FALSE power to the specified elem
194. g group refer to the following web location http www accellera org activities p1801 upf You can obtain a copy of v1 0 of the UPF standard February 2007 in PDF format from the following web location http www accellera org apps group public download php 989 upf v1 0 pdf Version 2 0 of the UPF Standard IEEE Std 1801 2009 In May 2007 Accellera donated UPF v1 0 to the IEEE for the purposes of creating an IEEE standard The donation was assigned to the P1801 working group and was eventually developed into a formal standard titled the JEEE Standard for the Design and Verification of Low Power Integrated Circuits IEEE Std1801 2009 Although this standard is the first official IEEE version it represents the second version of what is more informally referred to as UPF v2 0 When you use v2 0 Power Aware simulation parses all UPF v2 0 commands and displays a warning message for the following e Unsupported commands Anyunsupported arguments for a supported command Syntax and Semantic Differences Between UPF 1 0 and UPF 2 0 The release of Version 2 0 of the UPF Standard from IEEE introduced syntactical and semantic differences from the Version 1 0 UPF Standard from Accellera Power Aware simulation provides functionality to help you control its behavior for these changes By default Power Aware simulation assumes that the UPF file is written in UPF 2 0 and expects proper syntax from that specification and will treat semantic beh
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196. h the direction of the voltage difference at domain crossing For example domain crossing requires low to high level shifter but level shifter specified is high to low then it will be reported as incorrect Error MPSA UPF INCORRECT LS CHK Shift mismatch for level shifter my ls bot3 rule low to high Domain pd aon at domain boundary pd aon Operating Voltage 2 000000 V gt pd top Operating Voltage 1 000000 V for following Source port tb TOP bot3 outl bot LowConn gt Sink port tb TOP bot3 outl bot HighConn Time 90 ns Scope mspa top mspa upf top msp a0 pd tb mspa3 pd top mspa5 pd aon my ls bot3 MPSA UPF INCORRECT LS CHK 1 File src inc Is dyn checkl top upf Line 4 vopt pa_checks ul Enables all dynamic level shifter checks Power Aware Simulation User s Manual v10 2c 85 Automatic Checking Dynamic Checking in Power Aware Miscellaneous Dynamic Checking Table 5 6 lists values you can specify for vopt pa checks that perform the following checking operations Table 5 6 Miscellaneous Dynamic Checks Usage Syntax Description Error Messages vopt pa_checks t Enables the simulator to catch a condition where inputs to the power domain toggle even when the power domain is turned off Error vsim PA 8908 MSPA PD OFF ACT Time 36 ns tb top clk toggled during power down of power domain PD Control vopt pa checks ep During simulation this check hel
197. he out Example POWER PDO s top pdl11 s1 nr top pd11 w11 p top pd11 c pi top pd11 c112 top global vdd 1 amp top vdl local vad 11 RETENTION top vdl1 save top vdl restore POWER VDD 0 5 Example POWER PD1 Process pl is in a different p top m2 00 p1 power island top VDD1 POWER PD2 Than process p2 p top m2_00 p2 But both exist in the same block top VDD2 module m2 il i2 i3 i4 iso al a2 clock reset output a 1 a2 reg all a21 input il i2 i3 34 input clk reset Belong to PD1 always il or i2 or i3 begin pl all lt i1 amp i2 amp i3 end Belong to PD2 always il or i2 or i3 begin p2 endmodule Power Aware Simulation User s Manual v10 2c 309 Power Configuration File Reference PCF Syntax and Contents Power Model Mapping Statement The mapping statement defines how an inferred register or latch signal or variable in the design maps to a model from the Power Aware model library that defines its run time behavior Need to allow mapping of a Power Aware model to all inferred sequential items regs latches in a scope or to specific signals whole signals not bit part or selected elements of a signal in a scope Wildcard matching will apply 310 power model mapping MAP model module name pacell spec ret ctrl signals region definitions stmt end ret ctr
198. he architecture of the design and the 326 Power Aware Simulation User s Manual v10 2c Supplemental Information Power Aware Verification of ARM Based Designs particular characteristics of a signal that crosses from one power domain to another e g how many power domains it fans out to and when those power domains are on or off with respect to the source domain it may be appropriate to insert isolation cells at either the source of the signal or at its sink s However since the isolation cell must be powered on when the source domain is powered off isolation cells are typically powered by a separate always on supply voltage The following UPF commands specify the addition of isolation for the PD mem ctrl power domain in the example in Figure E 1 The first command defines the supplies powering the isolation cell and specifies its clamp value The second command defines the control signal for the isolation cell Mem ctrl chip amp write enables clamp to 1 set isolation mem ctrl iso 1 domain PD mem ctrl isolation power net VDD 0d99 isolation ground net VSS clamp value 1 elements mc0 ceb mc0 web set isolation control mem ctrl iso 1 domain PD mem ctrl isolation signal mc iso c isolation sense high location parent Level shifting cells ensure that a signal coming from a power domain operating at one voltage is correctly interpreted when it is received by a powe
199. he power domain may be varied Switches may be on chip or off chip Power is distributed to power domains via supply ports interconnected by supply nets Supply ports may represent external supplies or may be driven by internal supply sources Supply ports are connected to supply nets each of which is ultimately connected to a power domain Each supply port has one or more supply states defined The port may drive only one state at any given time That state is propagated by the supply net connected to the port For the example in Figure E 1 the following UPF commands could be used to define top level supply ports and to define and connect supply nets to those ports create supply port VDD 0d99 domain PD top create supply port VDD 0d81 domain PD top create supply port VSS domain PD top create supply net VDD 0d99 domain PD top create supply net VDD 0d81 domain PD top create supply net VSS domain PD top Connect top level power domain supply ports to supply nets connect supply net VDD 0d99 ports VDD 0d99 connect supply net VDD 0d81 ports VDD 0d81 connect supply net VSS ports VSS 324 Power Aware Simulation User s Manual v10 2c Supplemental Information Power Aware Verification of ARM Based Designs The following UPF command would be used to identify a particular pair of supply nets as the primary power and ground supplies for a given power domain
200. ied signal shall infer a sequential element register or latch that will be mapped to the Power Aware model A warning shall be issued if a sequential element has not been inferred for the specified signal An error shall be issued if the pacell type is specified and the Power Aware cell type inferred for the specified signal does not match Instance All sequential elements inferred within the instance will be mapped to the specified Power Aware model By default the mapping is recursive to all child instances of the specified instance The nr switch may be used to specify non recursive mapping to the instance only not to any child instances A warning shall be issued if pacell type is specified and no inferred sequential elements of that type are present in the region Process All sequential elements inferred within the process will be mapped to the specified Power Aware model A warning shall be issued if there are no inferred sequential elements for the specified process A warning shall be issued if pacell type is specified and no inferred sequential elements of that type are present in the region e pacell type specifies the type of inferred sequential cell to which the mapping statement applies Specification of the Power Aware cell type avoids unintentional mapping of the incorrect Power Aware model to an inferred sequential element of a different type while permitting all types of cells to be inferred in the same region d
201. ifying an optimized design unit These methods resemble the conventional two step and three step optimization flows No optimized design unit This flow resembles the conventional two step flow where you use the vopt command to specify a Power Aware simulation and debugging only no optimization is performed When you run the vsim command it performs debugging and runs vopt internally to perform optimization see Using the Delayed Optimization Flow For example vlog design v vcom design vhdl vopt pa upf config file debugdb tb vsim tb pa debugdb vopt Optimized design unit This flow resembles conventional three step flow where you use the vopt command to specify a Power Aware simulation the name of the design unit to be optimized and debugging When you run the vsim command it begins simulation on the optimized design unit and runs debugging General Steps for Running Power A ware For example vlog design v vcom design vhdl vopt o optdu pa upf config file debugdb tb vsim optdu pa debugdb Bottom Up Debugging From the Design Under Test You can run Power Aware analysis from the DUT hierarchy and debugging on the complete design Running vopt pa top captures the DUT hierarchy for Power Aware analysis 108 No optimized design unit This flow resembles conventional two step flow where you use the vopt command to specify a Power Aware simulation and debugging without optimization Use the pa
202. ig Power Aware Simulation User s Manual v10 2c Power Aware Commands and Options Voltage Level Shifting Multi Voltage Analysis Voltage Level Shifting Multi Voltage Analysis This section describes the voltage level shifting capability of Power Aware which is primarily implemented as Unified Power Format UPF commands and Power Aware arguments to the ModelSim vopt command The supply network state provides information about the possible power states of the network Power Aware simulation uses that information to detect level shifters wherever a signal crosses from a power domain operating at a voltage level that may be different than the voltage level of another power domain to which it connects also known as multi voltage analysis Power State Tables Power Aware simulation uses information from a Power State Table PST in Power Aware analysis PSTs are also parsed and dumped to the UPF report file report upf txt It is assumed that the PST is complete any domains that are not mentioned in PST will not be used for analysis The traversal does not skip any power switches encountered in the supply network path The traversal goes only behind direct connectivity of supply ports and supply nets that are created in UPF It does not go behind a supply net present in the design or the UPF supply net port that is directly connected to an HDL supply net or port Example Pst top pst File UPF rtl top upf 127
203. ign o level shift prefix o level shift suffix o isolation prefix o isolation suffix e Synopsys pragmas o isolation upf o retention upf Reports The cells detected as an instance of some strategy are reported in report upf txt for example Power Domain A File src casel test upf 11 Creation Scope tb dut Isolation Strategy ISO1 File src casel test upf 22 Isolation Supplies power tb dut VDD 0d99 ground tb dut VSS 0899 Isolation Control tb dut restore Isolation Sense HIGH Clamp Value 0 Location fanout Signals with instance isolation cells 1 Signal tb dut instA out isolation cell tb dut iso 1 UPF ISO Messages When Power Aware simulation is unable to detect the UPF strategy of an isolation level shifter cell Power Aware simulation semantics are disabled and the cell is treated as always ON The following message is displayed Warning vopt 9768 Power aware simulation semantics disabled for tb dut instA ls 0 UPF LS as its power aware strategy could not be identified For a cell identified as a retention cell Power Aware simulation flags a warning if the cell is also identified as a level shifter or isolation cell Power Aware simulation then processes it as either a retention or an isolation level shifter cell and the following message is displayed Warning UPF vopt 9823 Power aware cell tb dut iso 1 identified as
204. ignal isolation_sense Source sink Filters the ports receiving a net that is driven by logic powered by the supply set Filters the ports driving a net that fans out to logic powered by the supply set sink_off_clamp Not supported source_off_clamp Not supported transitive Power Aware Simulation User s Manual v10 2c Not supported 237 UPF Commands and Reference set isolation Usage Notes The isolation strategy defined by set isolation causes Power A ware to perform insertion of isolation cells together with an analysis of the power state table to see whether adjacent power domains can be in different power states and therefore require isolation The instance argument prevents insertion of a redundant isolation cell at a port where one already exists see map isolation cell When both source and sink are specified a port is included if it has a source as specified and a sink as specified This command supports isolation of lower boundary ports of a power domain which is defined in UPF v2 0 as The highconn side of ports defined on design elements in other power domains but instanced within design elements in the extent of the domain set scope tb create power domain PD TOP elements top inst create power domain PD BOT elements top inst bot inst set isolation PD TOP isolation1 domain PD TOP isolation power net VDD PD TOP net clamp va
205. igns and formal verification of power control logic These methods provide a comprehensive solution for defining and verifying active power management 332 Power Aware Simulation User s Manual v10 2c Supplemental Information Power Aware Verification of ARM Based Designs Acknowledgements The authors would like to acknowledge the thoughtful commentary and suggestions for improvement provided by Barry Pangrle on the penultimate draft of this paper References l N S Kim T Austin T Blaauw T Mudge K Flautner H S Hu M J Irwin M Kandemir and V Narayanan Leakage current Moore s law meets static power IEEE Computer 36 12 68 75 2003 S Shigematsu S Mutoh Y Matsuya Y Tanabe and J Yamada A 1 V High Speed MTCMOS Circuit Scheme for Power Down Application Circuits IEEE J Solid State Circuits Vol 32 No 6 pp 861 869 1997 Hyo Sig Won Kyo Sun Kim Kwang Ok Jeong Ki Tae Park Kyu Myung Choi Jeong Taek Kong An MTCMOS design methodology and its application to mobile computing Low Power Electronics and Design 2003 ISLPED 03 Proceedings of the 2003 International Symposium on vol no pp 110 115 25 27 Aug 2003 Zyuban V Kosonocky S V Low power integrated scan retention mechanism Low Power Electronics and Design 2002 ISLPED 02 Proceedings of the 2002 International Symposium on vol no pp 98 102 2002 IEEE 1801 2009 Standard for Design and Verification of Low Power
206. im arguments used to control simulation Using the No Optimization Flow In conventional simulation you can perform simulation without optimizing the design at all This no optimization flow is also supported for Power Aware simulation In this flow the vopt step is still performed but only to process the UPF specification you do not use the o argument for vopt so optimization is not performed until you invoke the vsim command use the novopt argument to prevent implicit optimization from being performed for the simulation session nl ee RR This flow is not recommended for use except for certain very specific applications that do not yet support the optimized flows One such application is the use of Power Aware simulation together with Questa ADMS Power Aware Simulation User s Manual v10 2c 33 Power Aware Simulation Power Aware Simulation Flows Compile Compile your design by running either the vcom for VHDL or the vlog for Verilog command as you would for any VHDL or Verilog SystemVerilog design For more information on using vcom refer to Compiling a VHDL Design the vcom Command in the User s Manual For more information on using vlog refer to Invoking the Verilog Compiler in the User s Manual Usage vcom files vlog files Process UPF After you compile your design run the vopt command on the test bench top with the pa upf argument and TB upf but without the o
207. in VHDL or SystemVerilog You can also specify all supported attributes using VHDL or SystemVerilog VHDL example attribute UPF pg type of vdd backup signal is backup power System Verilog example UPF pg type backup power input vdd backup Specifying Supply Nets in UPF The connect supply net command specifies connection to a supply net that conforms to the behavior described in 6 13 of IEEE Std 1801 2009 A UPF supply net is propagated through implicitly created ports and throughout the logic hierarchy of the scope in which the net is created Power Aware Simulation User s Manual v10 2c 263 UPF Commands and Reference Supported UPF Attributes Format of Assigned Net Values A supply net connected by this command is a composite signal consisting of a real voltage value in LV and an enumerated supply state ON OFF For Power Aware simulation the default voltage value is 81uV on both VDD and VSS GND nets a voltage value is not used for dynamic simulation For simulating a digital design the more important information for the net is whether its supply state is ON or OFF Regardless of whether the power supply net is VDD or GND when the power supply state is ON the state value assumes an integer value of 1 When the supply state is OFF the state value assumes an integer value of 0 By default the power state is ON Consequently Power Aware simulation reports the two default values of 81 and 1 to a power ne
208. in accordance with the RETPWR logic For a user defined model without a RETPWR port A warning is issued during the vsim simulation For example 292 Power Aware Simulation User s Manual v10 2c UPF Commands and Reference Supply Nets Warning vsim PA 8944 Retention Model MyRetModel does not have Port RETPWR Ignoring it Region mspa top blk0 instO0 MyRetModel no retention Description This argument disables retention on specified storage elements Example upf version 2 0 set scope tbl create power domain PD TOP elements topl bot1 tdsig create power domain PD TOP2 elements topl ql create power domain PD TOP3 elements top1 set domain supply net PD TOP primary power net PD TOP primary power primary ground net GND net set domain supply net PD TOP2 primary power net PD TOP primary power2 primary ground net GND net set domain supply net PD TOP3 primary power net PD TOP primary power3 primary ground net GND net create power switch PD TOP sw domain PD TOP output supply port out sw PD TOP PD TOP primary power input supply port in sw PD TOP VDD net control port ctrl sw PD TOP pg on state normal working in sw PD TOP ctrl sw PD TOP off state off state ctrl sw PD TOP set retention PD TOP retention3 domain PD TOP retention power net VDD net elements top1 bot1 tdsig 0 1 no retention set retention
209. information through the use of vopt pa_tcl which allows your UPF file to remain portable 254 Power Aware Simulation User s Manual v10 2c Usage Notes UPF Commands and Reference set simstate behavior The set simstate behavior command defines the simulation simstate behavior for a model or library You can use this command to override the default setting of simstate semantics Examples Example C 12 Enable Simstate Behavior Using set simstate behavior In the following example automatic connections led to disablement of simstate semantics of model mia The set simstate behavior command enables the simstate semantics of instances of the model upf version 2 0 set scope tb topl create power domain pdl set simstate behavior ENA create supply net VDI create supply net GNI DN DN domain pd1 domain pd1 BLE model mid Example C 13 Disable Simstate Behavior Using set simstate behavior In the following example set simstate behavior disables the simulation semantics all instances of model bot set scope tb topl set simstate behavior ENA Vopt Message Note disabl ed Note disabl ed Note disabl ed Note disabl ed BLE model mid set simstate behavior DISABLE model bot create power domain pdl create supply net VDD N domain pd1 test upf 7 UPF vopt 9693 Power Aware for tb topi1 mid1 botl
210. ing function performed as shown in Table 5 2 Table 5 2 Static Level Shifter Checks Check Usage Syntax Description Example Message Missing vopt pa_checks sml Checks that if level shifter is required at domain Level Shifter crossing and level shifter strategy is not specified Warning vopt 9693 UPF LS STATIC CHK Found Total 1 Missing level shifters 74 Power Aware Simulation User s Manual v10 2c Automatic Checking Static Checking in Power Aware Table 5 2 Static Level Shifter Checks cont Check Usage Syntax Description Example Message Incorrect vopt pa_checks sil Checks that if the direction of level shifters specified Level Shifter for domain crossing does not match with the direction as per voltage difference of domain crossing For example domain crossing requires low to high level shifter and level shifter specified is high to low then it will be reported as incorrect Warning vopt 9693 UPF LS STATIC CHK Found Total 1 Incorrect level shifters Redundant vopt pa_checks srl Checks for any level shifter whose source and sink Level Shifter power domains have no voltage difference flagging this as a redundant level shifter Warning vopt 9693 UPF LS STATIC CHK Found Total 1 Redundant level shifters Unanalyzed vopt pa checks snl Reports level shifter strategies that are not analyzed Level Shifter because of insufficient information such as when a power state ta
211. ing user supplied power aware simulation models Verifying Power Managed Behavior Power aware simulation can be used to visualize the effects of active power management on the dynamic behavior of the design as well as visualizing the behavior of the power management architecture itself under control of power management logic In a power aware simulation the internal state and outputs of a power domain will be set to X to reflect the corruption of those signals when the primary supply to that domain is turned off When the supply is turned on again the X values will be replaced as the power domain reinitializes or has its state restored Signals driven by outputs of a powered down domain should be clamped to 0 or 1 so that downstream power domains see a well defined value and won t be affected by corrupted outputs of a power domain that has been powered down Retention should be evident in that the state of signals following power up will correspond to the state of signals prior to the previous power down Visualizing the effects of active power management helps the designer confirm that all of the necessary power domains and power states required to implement the operation modes of this Power Aware Simulation User s Manual v10 2c 331 Supplemental Information Power Aware Verification of ARM Based Designs device have been defined and that all the necessary isolation level shifting and retention cells necessary to enable power management ha
212. ion cells at Port H and I for the same port F set isolation isol domain PD3 source PD3 SS location fanout Using source and location parent Places isolation cells at Ports E and F Places only one Isolation Cell at Port F which isolates both Paths F H and F I set isolation iso2 domain PD3 source PD3 SS location parent Places isolation at Port G Relative ordering is maintained with iso3 cell in front of iso4 cell means Iso3 iso4 gt port G 150 Power Aware Simulation User s Manual v10 2c set isolation iso3 domain PD3 el clamp 1 Power Aware Commands and Options Restricting Isolation and Level Shifting on a Port lements E set isolation iso4 domain PD4 el clamp 0 lements G Figure A 2 Multiple Isolation Cells location fanout location parent Multiple Strategies in a Path Examples Refer to Figure A 2 for the following examples on using multiple strategies in a path Places isolation cell at Port H and isolates path M F H set isolation isol domain PD7 sink PD4 location fanout Places isolation cell at Port M and isolates only path M F H This means the clamp value will be seen at Port H All other ports M F and I will not have clamp value during power down set isolation iso2 domain PD7 sink PD4 location parent e Places three isolation cells at Port H with relative ordering 1503 gt iso4 gt iso5 gt port H Power Aware Simulation
213. ioral Element Reporting S top out I top bot 68 Power Aware Simulation User s Manual v10 2c Chapter 5 Automatic Checking This chapter describes how to perform static and dynamic checking as part of Power Aware simulation To implement either mode of checking use the pa checks argument of the vopt command This argument takes on a variety of values which are listed and described in the following sections e Static Checking in Power Aware Dynamic Checking in Power Aware Implementing Checking at Gate Level Note You can enable all power aware checks static and dynamic by specifying the pa_checks all argument You can enable all dynamic power aware checks by specifying the pa_checks d argument or pa checks without any argument You can enable all static power aware checks by specifying the pa_checks s argument Static and Dynamic Checking Overview This section provides an overview of static and dynamic checking for level shifters and isolation Level Shifter Checking A level shifter cell is present in the design description if a set level shifter instance command in your UPF file identifies that cell in the design description as a level shifter cell A level shifter cell is implied by a level shifting strategy if the set level shifter command exists with the appropriate options for the appropriate power domain Level shifting is statically required for a power domain crossing if the source and
214. irectly during the UPF processing step for a single simulation run Using Liberty Files with vopt You can specify one or more Liberty files to use with the vopt command with the pa libertyfiles argument By default using Liberty files creates an internal database in which power related data extracted from a Liberty library is stored You can control how this database is used with the following vopt arguments Power Aware Simulation User s Manual v10 2c 35 Power Aware Simulation Working with Liberty Libraries e pa dumplibertydb e pa libertyupdate e pa libertyrefresh e pa loadlibertydb Creating and Saving a Liberty Database Use the vopt command to parse the Liberty files and create a saved database containing information extracted from the Liberty files that will be used in power aware simulation Note that you can specify multiple files with the pa libertyfiles argument by separating file names with a comma vopt pa libertyfiles a lib b lib pa dumplibertydb 1lib db where pa libertyfiles specifies the Liberty files to read e pa dumplibertydb specifies the name of the Liberty database to be saved for future use Using a Previously Created Liberty Database Use the vopt command again with other Power Aware arguments to include information from a previously created Liberty database in the UPF processing for a design vopt design top pa upf compile upf pa lib work pa loadlibertydb lib db other vop
215. isplay Options dialog box which allows you to control how FSM information is added to the Wave Window how much information is shown in the Instance Column Power Aware Simulation User s Manual v10 2c 123 Visualization of Power Aware Operations Power State and Transition Display 124 Power Aware Simulation User s Manual v10 2c Appendix A Power Aware Commands and Options Note The functionality described in this chapter requires an additional license feature for ModelSim SE Refer to the section License Feature Names in the Installation and Licensing Guide for more information or contact your Mentor Graphics sales representative This appendix provides reference information on the following ModelSim Commands Used for Power Aware a summary of the arguments for the vopt and vsim commands that you use to implement a Power Aware simulation Additional Commands You Can Use with Power Aware a summary of Tcl commands that you can use to control a Power Aware simulation Power Aware Messages basic information on message handling for Power Aware simulation Excluding Design Elements from Power Aware a description of how to use vopt pa excludefile to skip Power Aware processing for any module its instances in a particular hierarchical path in the design or signals in the design Voltage Level Shifting Multi Voltage Analysis Restricting Isolation and Level Shifting on a Port Simulating Desig
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217. l ports specified below are input ports The simulator will connect the ports to the corresponding functional and power control network signals by name Verilog is case sensitive e PWR Power control network signal that indicates whether power is on or off for the power island that this model is associated with This port is always connected Retention port s One of the following must be defined by the module and the retention port s will always be connected o RET Power control network signal that indicates whether or not the state of the inferred register or latch must be saved or restored o SAVE RESTORE Separate ports to signal save and restore separately CLK Functional network data in enable signal For registers this would be a clock signal For latches this will be the enable signal This port will always be connected e SET Functional network control signal indicating that the inferred sequential model s value should be set or preset The functionality of this port is optional and the port will not be connected if there are no inferred set or preset conditions This port needs to be modeled active high or active posedge The tool infers the control signal and its polarity and will automatically negate the signal s value when it is connected to the model if it is active low or active negedge e RESET Functional network control signal indicating that the inferred sequential model s value should be r
218. l possible states present on the objects mentioned in the header The detailed information of the states is listed with the voltage information as well This information is similar to what was specified in the corresponding add port state UPF command The source supply port mentioned in brackets is the name of the supply port on which the add port state command is called or its the supply net port which is directly connected to the port on which add port state command was called The UPF file reference corresponds the file and line number of the add port state command Sample Power Architecture Report QuestaSim Version DEV main 2294369 2011 01 Generated on g Tue Jan 25 09 37 28 20 This report file contains information about all the Power Aware Architecture elements in the design Power Domain pd aon File test upf 4 Creation Scope tb Primary Supplies power tb vd d net ground tb gnd net Power Domain pd File test upf 16 Creation Scope tb 60 Power Aware Simulation User s Manual v10 2c Power Aware Reports UPF Reports Primary Supplies power tb pd pwr ground tb G pd net Power Switch pd sw File test upf 37 Output Supply port out sw pd tb pd pwr Input Supply ports 1 in sw pd tb V pd net Control Ports 1 ctrl sw pd tb pwr Switch States 1 normal working ON ctrl sw pd 2 off state OFF ctrl sw pd Retention Strategy pd retention File test upf
219. l signals ret signal name ret save sig name ret restore sig name pacell spec pacell type interface information pacell type FF CKHI FF CKLO FF CKFR LA ENHI LA ENLO LA ENFR ANY CKHI ANY CKLO ANY CKFR RETMEM NON RETMEM interface information named parameter assignment named parameter assignment model module name specifies a Verilog module that defines the Power A ware retention behavior that will be mapped to the regions specified by region definition Normal Verilog library search will be used to locate the module e g L my lib It is an error if the specified module cannot be found or if found does not conform to the modeling guidelines for Power Aware models For more information refer to Model Construction for Power Aware Simulation ret ctrl signals specifies either a single signal name that will be connected to the RET port of the Power Aware model or a pair of retention signal names that are connected to the SAVE and RESTORE ports of the Power Aware model For more information refer to the chapter Model Construction for Power Aware Simulation region definitions determines which regions defined in the section Region Definitions shall be supported in the power model mapping statement with the following semantics for each region Power Aware Simulation User s Manual v10 2c Oo Power Configuration File Reference PCF Syntax and Contents Signal The specif
220. lO none pa lib library pathname pa libertyrefresh database path pa libertyupdate Power Aware Simulation User s Manual v10 2c Power Aware Commands and Options ModelSim Commands Used for Power Aware Table A 1 Power Aware Arguments for vopt cont vopt Argument Argument Value s pa Isthreshold real pa_loadlibertydb pa_modeltype lt database_path gt pa nopcefctrlcheck pa out pa prefix hier path pa replacetop string pa reportdir pa reportfile lt pathname gt lt filename gt pa_rtlinfo none pa_tclfile pa_top lt filename gt lt pathname gt pa_upf lt filename gt pa_upfextensions pa_upfsyntaxchecks Supported UPF Extensions none pa_upfversion 1 0 2 0 default Table A 2 Power Aware Arguments for vsim vsim Argument Argument Value pa none pa allowtimezeroevent all pa debugdir directory pa disabletimezeroevent none pa_gls none previously used for purely gate level designs You can now use pa option instead pa_highlight none pa_lib lt pathname gt pa togglelimit integer pa top Power Aware Simulation User s Manual v10 2c lt pathname gt 127 Power Aware Commands and Options ModelSim Commands Used for Power Aware Table A 2 Power Aware Arguments for
221. les 1 dummy ss handle Anonymous gt 2 primary tb ss Functions 1 power tb snet pwr 2 ground Anonymous gt 5 Supply Set handles 1 primary tb my second ss Ref Gnd tb gnd net Functions 1 power tb vd d net Where the sections contain the following information e Section 1 Defines the power domain e Section 2 Specifies the full hierarchical path of the creation scope e Section 3 Specifies the primary supplies of the power domain When a power domain is not connected to a primary supply a warning message similar to the following is displayed and that domain is treated as always on Warning test upf 7 vopt 9665 Power domain pd created in scope top vl doesn t have a primary power ground supply Ignoring it e Section 4 Specifies supply set handles associated with the power domain This provides the names of all handles and the absolute hierarchical path of the supply set associated with them The supply set functions are listed below the handle name as well as the individual functions and associated supply nets Note If a handle is left unassociated with a supply set or supply net the report will display Anonymous in the relevant field e Section 5 Shows an example of the reference ground specified in the supply set Power Switch The power switches associated with the power domain are listed in this section of the report This listing contain
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223. lowing steps are performed automatically 1 Detect gate level cells in the mixed netlist and perform the application of corruption based on the corresponding UPF strategies 2 Detect the power aware cells in the design and match them with corresponding UPF strategies at that point in the design and run and flag power aware checks to report the valid cases and error out for anomalous cases 3 Insert power aware cells wherever required by the corresponding UPF strategy and not already present in the netlist 4 Detect UDPs and apply corruption and retention based on the corresponding UPF strategy Power Aware Simulation User s Manual v10 2c 39 Power Aware Simulation Applying Power Intent to the Design Detection of Gate level Cells Power Aware simulation automatically treats a module as a gate level cell if either of these conditions are satisfied the module contains the celldefine attribute the module contains the specify block Corruption will only occur on the output ports of any detected gate level cells For RTL cells the standard processing of driver based corruption still occurs In some cases you may not want this flow to corrupt certain cells For example PAD cells of buffer cells which might be written with a celldefine attribute in the design There may be other cases where you don t want a cell to be treated as a gate level cell but would rather have driver based corruption on the modules For these instances
224. lowing methods e Ina UPF file with the commands o Set port attributes o Set pin related supply Related supplies attributes in RTL Using a Liberty file in GLS Using UPF Commands To specify hard macro power intent use the UPF commands and their arguments described below Command set port attributes 152 Power Aware Simulation User s Manual v10 2c Power Aware Commands and Options Simulating Designs Containing Macromodels Arguments receiver supply This argument specifies the supply of the logic reading the port If the receiving logic is not within the logic design starting at the design root it is presumed the receiver supply is the supply for the receiving logic driver supply This argument specifies the supply of the logic driving the port If the driving logic is not within the logic design starting at the design root it is presumed the driver supply is the supply for the driver logic and the port is corrupted when the driver supply is in a simstate other than NORMAL related power port related ground port related bias ports Any of these arguments create an implicit supply set containing the supply nets connected to the ports The behavior differs depending on the mode of the port being attributed in mode the implicitly created supply set is treated as the receiver supply set out mode the implicitly created supply set is treated as the driver supply set inout mode the implicitly
225. lt if a default mapping within a context scope creates an ambiguity with another default mapping within that same context In such ambiguous situations the first default mapping will be used and subsequent default mappings ignored Retention Statement Normally the Power Control Statement will specify the retention control signal s for an entire power island However to provide the ability for a power island to have more than one set of retention control signals as well as the flexibility to specify retention control signals separate from the power control statement and the default model mappings the retention statement is provided The retention statement may be paired with the use of default mappings to specify the information that is region specific for inferred sequential elements Specifically the retention control signals that are specific to a region are specified so they can be connected to the Power Aware models associated with the default mapping to inferred sequential elements retention statement retention specification region definitions stmt end retention specification RETENTION ret ctrl signals The retention control signals specified must match the Power Aware model that is mapped to the inferred sequential elements The Model Construction for Power Aware Simulation allows the use of one or two retention control signals Corruption Semantics Corruption occurs on power down Corruption can be applied to state va
226. luating the power state of supply sets and power domains The state of a supply set is evaluated after the tool specific translation of PARTIAL ON to FULL ON or OFF for each supply net in the set By default Power Aware translates PARTIAL ON is translated to OFF Therefore you must use the set partial on translation command to change the default translation behavior to FULL ON You can also define a list of tools for which translation of PARTIAL ON to FULL ON takes place and the tools for which PARTIAL ON to OFF takes place All tool names are case insensitive You can also specify default behavior for an unlisted tool Note To define PARTIAL ON translation behavior for Power Aware simulation specify questa in the tools list In Power Aware simulation PARTIAL ON has an enum value of 2 The supply partial on function would also assign the same enum value of 2 Power Aware Simulation User s Manual v10 2c 243 UPF Commands and Reference set partial on translation Example C 7 Set the Translation of PARTIAL ON to FULL ON For All Tools upf version 2 0 set scope tb set partial on translation FULL ON Example C 8 Set the translation of PARTIAL ON to FULL ON Only for ModelSim and to OFF for Others upf version 2 0 set scope tb set partial on translation OFF full on tools questa Example C 9 Set the translation of PARTIAL ON to OFF Only for ModelSim and to FULL ON for Others upf version 2 0 set scope tb set
227. lue 0 applies to inputs location parent This command will isolate both the inputs ports of the instance tb top inst as well as outputs of the instance tb top inst bot inst lower boundary ports 238 Power Aware Simulation User s Manual v10 2c UPF Commands and Reference set isolation control set isolation control Support for UPF Standard v1 0 yes v2 0 yes Arguments Argument domain Comments Restrictions isolation signal isolation sense location Usage Notes The sibling value is not supported The location argument defines the isolation behavior so that it appears in the specified location which is used by synthesis and or place and route to guide insertion of actual isolation cells Power Aware Simulation User s Manual v10 2c 239 UPF Commands and Reference set level shifter set level shifter Support for UPF Standard v1 0 yes partial v2 0 yes partial 240 Power Aware Simulation User s Manual v10 2c Arguments Argument domain UPF Commands and Reference set level shifter Comments Restrictions elements Complex data types of SystemVerilog such as structs are not supported However you can specify bit or part selects of one or more signals no shift threshold applies to rule location The location argument defines where level shifter cells are to be placed in the design If y
228. ly PD primary power FULL ON RET supply SS State2 similarly PD RET supply SS State2 RET supply power FULL ON similarly PD RET supply power FULL ON logic expr Jegal illegal 180 Power Aware Simulation User s Manual v10 2c Argument simstate Usage Notes UPF Commands and Reference add power state Comments Restrictions Values CORRUPT The power level of the supply set is either off one or more supply nets in the set are switched off terminating the flow of current or at such a low level that it cannot support switching and the retention of the state of logic nets cannot be guaranteed to be maintained even in the absence of changes or activity in the elements powered by the supply CORRUPT ON ACTIVITY The power level of the supply set is insufficient to support activity However the power level is sufficient that logic nets retain their state as long as there is no activity within the elements connected to the supply CORRUPT STATE ON ACTIVITY The power level of the supply set is sufficient to support combinational logic but it is not sufficient to support activity inside state elements whether that activity would result in any state change or not CORRUPT STATE ON CHANGE The power level of the supply set is sufficient to support combinational logic but it is not sufficient to support a change of state for state elements NORMAL The power level of the s
229. ly set PD1 SS create power domain PD1 associate supply set PD1 SS handle PD1 primary create supply set PD2 SS create power domain Pl 2 D ET associate supply set PD2 SS handle PD2 primary D create power domain Pl 148 3 Power Aware Simulation User s Manual v10 2c Power Aware Commands and Options Restricting Isolation and Level Shifting on a Port Figure A 1 Supply Paths to Power Domains A C E 6 Source Examples Place isolation cell at Port C and isolate Path A C set isolation isol domain PD3 source PD1 SS location parent Place isolation cell at Port B and isolate Path B D set isolation iso2 domain PD3 source PD2 SS location fanin Sink Examples Place isolation cells at Port G and Port H and isolate Path E G and F H set isolation isol domain PD3 sink PDA SS location fanout Place isolation cell at Port H and isolate Path F H set isolation iso2 domain PD3 elements F sink PD4 ss location fanout Place isolation cell at Port F and isolate Path F H set isolation iso3 domain PD3 elements F sink PD4 ss location parent Power Aware Simulation User s Manual v10 2c 149 Power Aware Commands and Options Restricting Isolation and Level Shifting on a Port Differential Supply Examples You can prevent the application of isolation into a path from driver to receiver for isolation strategy by using the diff supply only arg
230. ments Restrictions Text file that defines isolation strategy and power domain domain elements This argument takes the list of ports on which user defined isolation cell is to be placed If no list specified then user defined cells are applied to all the elements belonging to the specified isolation strategy lib cells lib cell type lib model name Usage Notes Specifies the name of the cell module to be picked up for isolation This module must be present in a library visible to the Power Aware vopt command Provides information about the ports of the library cell This argument connects the specified net ref to a port of the model see Usage Notes below This command maps a particular isolation strategy to a library cell or range of library cells to be inserted for isolation It has an effect only if isolation cells have been inserted see set isolation The information about the ports of the library model is specified using port argument which connects the specified net ref to a port of the model A net ref may be one of the following Alogic net name Asupply net name Power Aware Simulation User s Manual v10 2c 215 UPF Commands and Reference map isolation cell Oneofthe following symbolic references Q UPF_ISO_ENABLE Specific to ModelSim Refers to the isolation control signal of associated isolation strategy UPF_ISO_PWR Specific to ModelSim Refers to th
231. mstate_behavior 0 0 eee ee Ras 254 pl VerstOll ve whet anecaveeaderntdesSeeunesadeeued RELIS xA deer AO RE DET TSS 259 Supported UPF Package Functions uis esee hh he e hp eh 250 Detailed Support for supply net type lleleseeeeeee eee eee 260 Accessing Generate Blocks m UPE ys ono x es Rao Ea ee pr Res ES XX 261 linca PRETI 261 Supported UPF Attributes 24g scere eU PC Ee eee RC RR ACA eae 261 Specifying Attributes uxo 16a Rx a Ru D REC x Ea REG RARO REY ER RUE RO ES RU ER des 262 Limitations MPO i a E a a a a a a a a a 263 Attributes in VHDL or SystemVerilog 2 224 echo ERE REA EROR RE 263 Specifying Supply Nets in UPF si 62 ecdeantet ener Re I P BeRLCLeqQE ES EA Iq 263 Format of Assigned Net Values 0 0 2 e cece cee eee eee ee eenee 264 Changing the Default Supply State Values for VHDL Models 264 Supported UPF Extensions 2 4 cswss nee nsd oe Eee eed dee eh betian edk Enni M 265 Using pa UPlexteNSiGUS 6 2 radeeshieRbues3e ede 43 hers ke tede besides uis 265 UPF Supply Connections oaa 2d me pO d ARE PR E d Ee OR LUND el ce 269 Implicit Connections ise zi ce ee UR ER be REES RURREREREquORR ERES RA RUPES 269 Expect COmmectiOns 325444409 226 5G4bS ooh ro R SEQ eee dee eS ep ERA lt 270 Explicit Connections to HDL Ports 0 0 0 cee cee nee 270 i Clin 4202402 cade ane cave nodes eee ee a a obeeseedens eee eee 244 270 Explicit Connections to 1 bit HDL Ports 271 Explicit Connec
232. must be used if a CRLF is inserted in the middle of the statement Semicolon termination is encouraged as CRLF is provided primarily for backward compatibility Specifying Default Model Mappings A likely scenario is for a design to use a single technology library from a single vendor In this situation repeating the model mapping specifics repeatedly for multiple parts of the design becomes excessively redundant The DEFAULT MAP statement is provided for the purpose of defining default mappings of Power Aware models to various Power Aware cell types To increase the usefulness of the default mapping statements their lifetimes are defined to extend to the context scope they are defined within To allow a global set of default mappings together with locally overridden mappings the default mapping statements conform to the precedence rules defined in the sections Rule Precedence and Mapping Statement Precedence Power Aware Simulation User s Manual v10 2c 313 Power Configuration File Reference PCF Syntax and Contents Each default mapping statement is independent of other default mapping statements defined within the same scope This allows the default mapping for one type of Power A ware cell to be overridden in a nested context while other default mappings are not Furthermore a Power Model Mapping Statement overrides any default mapping that might otherwise apply DEFAULT MAP model module name pacell type stmt end A warning will resu
233. n List all retention signals in the design Command grep R report de txt grep v Output pd Path2 q regvh R pd Path3 q regvl R Expand the Path Id Command grep Path2 report de txt Power Aware Simulation User s Manual v10 2c 65 Power Aware Reports UPF Reports Output pd Path2 scope tb top vh lt gt Search a particular signal for power intent Command 1 grep tb top_vh gt report de txt Output 1 pd Path2 scope tb top vh lt gt Command 2 grep Path2 q_regvh report de txt Output 2 pd Path2 q regvh R implies that tb top vh q regvh is a retention register inside power domain pd Identify instances at power domain boundary Command grep report de txt Output pd Path2 pd Path3 scope tb top vh lt gt scope tb top vl lt gt Sample Power Aware Design Element Report QuestaSim Version Generated on This report file contains PA information about all the elements in user design pd aon Path1 scope tb pd aon Path2 scope tb top aon pd Path3 scope tb top vh lt gt Path4 scope tb top vl lt gt pd aon Pathij tie high low pd aon Path1 q combaon pd aon Path1 q latchaon pd aon Path1l q_regaon 66 Power Aware Simulation User s Manual v10 2c Power Aware Reports Behavioral Element Reporting pd aon Path1 q combvh pd aon Path1 q latchvh pd aon Path1 q reg
234. n SystemVerilog resume their normal sensitivity list operation All continuous assignments and other combinational processes are evaluated at power up to ensure that constant values and current input values are properly propagated Sequential elements will be re evaluated on the next clock cycle after power up Corruption Values Signals are corrupted by assigning them their default initial value such as X for 4 state types Default corruption values for Verilog and SystemVerilog are e 4 state logic types X e 2 state logic types 0 e SystemVerilog user defined types SystemVerilog default value Default corruption values for VHDL are Logic types X Real types 0 0 For any type T T LEFT Default Corruption Semantics During power aware simulation if the driver of a net is powered down then the driver s output is corrupted and this corrupted value propagates to all sinks of that net To understand how corruption will occur in a given design it is necessary to understand which elements of the design represent or contain drivers In RTL code any statements involving arithmetic or logical operations or conditional execution are interpreted as representing drivers and cause corruption when powered down Unconditional assignments and Verilog buf primitives do not represent drivers Power Aware Simulation User s Manual v10 2c 21 Concepts for Using Power Aware Simulation Power Aware Modeling and therefore d
235. n and or powered at different voltage levels It is important to verify that the SoC works correctly under active power management When a given subsystem is turned off its state will be lost unless some or all of the state is explicitly retained during power down When that subsystem is powered up again it must either be reset or it must restore its previous state from the retained state or some combination thereof When a subsystem is powered down it must not interfere with the normal operation of the rest of the SoC Power aware verification is essential to verify the operation of a design under active power management including the power management architecture state retention and restoration of subsystems when powered down and the interaction of subsystems in various power states In this presentation we summarize the challenges of power aware verification and describe the use of IEEE Std 1801 2009 UPF to define power management architecture We outline the requirements and essential coverage goals for verifying a power managed ARM based SoC design Power Aware Simulation User s Manual v10 2c 319 Supplemental Information Power Aware Verification of ARM Based Designs Introduction The continual scaling of transistors and the end of voltage scaling has made power one of the critical design constraints in the design flow Trying to maintain performance levels and achieve faster speeds by scaling supply and threshold voltages incre
236. n enclosed in quotation marks a an optional switch that enables recursive exclusion of module name hier path the full pathname to the instance of the module you want to exclude When a module instance is skipped Power Aware simulation displays the following message Note vopt 9691 Excluding power aware module module name in path hier path When used with a specifying hier path limits the recursive exclusion to a particular scope 142 Power Aware Simulation User s Manual v10 2c Power Aware Commands and Options Excluding Design Elements from Power Aware Entries for instances or signals must be of the following form module name instance pathname s r signal name s specifies signal exclusion r specifies recursion applied to s where all occurrences inside only that module scope will be excluded Examples Excluding a Module The following examples show entries in the exclude file 1 Direct Power Aware processing to skip all instantiation of bot mod found within the top hierarchy Entry in the exclude file bot mod Log messages for the vopt command Note vopt 9691 Excluding power aware module bot mod in path top t1 Note vopt 9691 Excluding power aware module bot mod in path top ti t2 2 Direct Power Aware processing to skip all instantiation of bot mod2 and bot mod3 found within the top hierarchy Entry in th
237. n be in a different always block for example but it must be next in the sequence Attributes To assist in the identification of Power A ware cells and facilitate their mapping inferred sequential elements attributes are placed within the module to provide easily located information The attributes names and allowed values as well as contexts in which they are used are as specified Retention Cells and Memories The attribute name is is retention and the allowed attribute values are the strings corresponding to the pacell type specified in the section Power Model Mapping Statement is retention pacell type string Where pacell type string is one of FF_CKHI FF_CKLO FF CKFR 162 Power Aware Simulation User s Manual v10 2c Model Construction for Power Aware Simulation Attributes LA ENHI LA ENLO LA ENFR RETMEM CKHI RETMEM CKLO RETMEM CKFR Note that within this context the pacell types of ANY CKHI ANY CKLO and ANY CKFR have no meaning as these types are used to map any inferred register or latch Within the context of attributing a retention cell that cell will be either a register or latch and that information will be known at the time of attribution Example is retention FF CKFR Clock free register is retention RETMEM CKHI Retention memory sensitive on posedge of clock Isolation Cells The behavior of isolation cells is automatically introduc
238. n or level shifter cell You can specify any of the following values for set isolation location or set level shifter location Power Aware Simulation User s Manual v10 2c 147 Power Aware Commands and Options Restricting Isolation and Level Shifting on a Port Oo Fanout isolation or level shifter cell is placed at all fanout locations sinks of the port Fanin isolation or level shifter cell is placed at all fanin locations sources of the port Faninout isolation or level shifter cell is placed at all fanout locations sinks for each output port or at all fanin locations sources for each input port Parent isolation or level shifter cell is placed in the parent of the domain whose interface port is being isolated or shifted Automatic same as Parent Self isolation or level shifter cell is placed inside the domain whose interface port is being isolated or shifted Sibling same as Self Note 2 3 Level shifter cells are not currently inserted in RTL their effect will not be present in simulation Only Power Aware checking vopt pa checks will validate these cells How to Apply the source and sink Arguments Figure A 1 shows a block diagram of power domains ports and paths for use in the examples that follow Example A 1 UPF Commands That Define Power Domains The following list shows fragments of UPF commands used to define the diagram of Figure A 1 create supp
239. n pd 1lib model name upf retention ret lib cell type FF CKHI associate supply set pd aon ss handle pd pd retentionl supply Report 296 report mspa txt Total tb upf_retention_ret 2 NPM_FF 1 NPM_LA 3 OUTPUT 3 pd sub total tb top vh tb top vl upf retention ret 1 tb top vl q regv NPM LA 2 tb top vh q latvh tb top vl q latv OUTPUT 2 tb top vh q combvh 1 tb top vl q combvl 1 pd pd retentioni use retention as primary sub total tb top vh upf retention ret 1 tb top vh q regvh 1 pd aon sub total tb top aon NPM FF 1 tb top aon q regvl NPM LA 1 tb top aon q latv OUTPUT 4 1 tb top aon q combvl 1 TS NPM FF Denotes all Non Power Management Flip Flops of a Power Domain NPM LA Denotes all Non Power Management Latches of a Power Domain Power Aware Simulation User s Manual v10 2c UPF Commands and Reference Supply Nets QUTPUT Denotes all outputs and power signals which are not sequential elements of a Power Domain Power Aware Simulation User s Manual v10 2c 297 UPF Commands and Reference Supply Nets 298 Power Aware Simulation User s Manual v10 2c Appendix D Power Configuration File Reference In addition to the UPF format see UPF Commands and Reference Mentor also supports a format for specifying the power intent of a design that is referred to as Power Configuration File
240. nal Dynamic UPF Report Report Output Transcript window Command vopt pa genrptz ud u b Specifying a value of ud or u displays dynamic UPF information to the Transcript window The dynamic report display includes time and polarity of controls such as control port of a power switch retention save and restore signals isolation enable signal plus Power Domain Status in the form of Power Domain name Strategy name Control signal names Active Sense Current polarity value Specifying a value of b for this argument vopt pa_genrpt ud b includes bitwise expanded information for isolated and level shifted ports Example of UPF Dynamic Report Note vsim 8916 MSPA UPF RET CTRL INFO Time 15 ns Retention Strategy PD BOT retention Retention SAVE tb ret bot reg Retention Sense posedge switched to polarity 1 Power Domain PD BOT Note vsim 8902 MSPA PD STATUS INFO Time 20 ns Power domain PD BOT is powered down Note vsim 8913 MSPA UPF SWITCH CTRL INFO Time 20 ns Power Switch PD BOT sw Control Signal tb pg bot switched to polarity 0 Power Switch state OFF Power Domain PD BOT Note vsim 8902 MSPA PD STATUS INFO Time 35 ns Power domain PD BOT is powered up Note vsim 8913 MSPA UPF SWITCH CTRL INFO Time 35 ns Power Switch PD BOT sw Control Signal tb pg bot switched to polarity 1
241. nd specification in the designs The values you specify for the pa checks argument activate static checking of signals for the power conditions Static Isolation Checks and Static Level Shifter Checks The static checking functionality does the following Displays a vopt summary related to all the checks performed and the result Generates a detailed report file report static txt containing the result of static checks in the following formats o Domain wise dumping all the ports are identified and collected with respect to connectivity between power domains o Level shifter strategy wise dumping the same information displayed with respect to individual level shifting strategy It helps to correlate easily with the list of candidate ports dumped in the UPF report file report upf txt For all static isolation or level shifter checks Power Aware simulation analyzes any specified Power State Tables PSTs and power states added on power domains and supply sets in the UPF file The purpose of this is to detect the power domain relative OFF ON condition and relative operating voltages If state dependencies between two connected power domains are not present in PST add power state then Power Aware simulation cannot determine power domain relative 70 Power Aware Simulation User s Manual v10 2c Automatic Checking Static Checking in Power Aware ON OFF states statically In this case static isolation checking will repo
242. nd UPF objects such as retention isolation level shifter cells You can define these connections in the following ways Implicit Connections Explicit Connections Automatic Connections Power State Composition Implicit Connections Implicit connections provide a way to connect supply nets to elements that do not have supply ports Any design element that is present in the extent of power domain and does not have supply ports connected or is excluded from Power A ware processing pa excludefile will be implicitly connected with the primary supplies power and ground of the power domain Thus the corruption of that element will be depend on the state of the primary power net and primary ground net of the power domain Power Aware Simulation User s Manual v10 2c 269 UPF Commands and Reference UPF Supply Connections Explicit Connections You can explicitly connect a supply net to a supply port using the following UPF command connect supply net This explicit connection overrides has higher precedence than the implicit and automatic connection semantics that might otherwise apply Explicit connections include Connections to UPF created supply ports Connections to HDL created supply ports supply net type or 1 bit type Connections to supply ports of power switches Explicit connection to an HDL supply port has simulation semantics disabled by default see Simulation Semantics for UPF Supply Connections Drivi
243. ndaries between two power domains Because a power state added on one domain supply set can reference other power states added on another domain supply set Power Aware simulation can statically infer such dependencies These dependencies help in determining the combinations of power states of supply nets and or ports You can add composite power states to your design as follows e Supply net power state information state and voltage level is defined by the supply net type declaration of the HDL cell see Explicit Connections to HDL Ports e Supply port power state information state and voltage level is defined by the supply net type declaration of the HDL cell see Explicit Connections to HDL Ports e Supply set composed of two or more supply nets so its power state is specified in terms of those supply nets Power domain power state is determined by the state of supply sets associated with the domain Power Aware simulation performs level shifter and isolation cell analysis checks from information provided with add power state UPF commands and also reports the power domain state dependencies in report files To know whether an isolation or level shifting is required on a boundary between power domains a static analysis is required to determine state dependencies between these power domains or supply sets associated with these domains The dependency information is extracted from supply logic expression mentione
244. needs to be reprocessed Refreshing a Liberty Database If a Liberty database has been created already with a previous version of Power Aware simulation the database can be modified to work with a later version of Power Aware simulation by using the pa libertyrefresh argument vopt design top pa upf compile upf pa lib work pa loadlibertydb lib db pa libertyrefresh other vopt args This will refresh lib db to be used with current version of ModelSim PDU Based Simulation In conventional simulation it is often desirable to optimize the design under test DUT separately from the test bench so that you can use the same optimized DUT model pre optimized design unit or PDU with multiple test benches You can also apply this approach to run Power Aware simulation provided that the DUT appears at the same location in each test bench To use this approach include the pa_defertop argument on the vopt command in the three step standard flow or in the voptargs argument to vsim in the two step delayed optimization flow For example vopt DUT top pa defertop pa upf DUT upf other vopt args Power Aware Simulation User s Manual v10 2c 37 Power Aware Simulation Power Aware Simulation Debug where DUT top specifies the name of the top level module of the design under test pa defertop specifies that the location of the DUT will be defined later e pa upf DUT upf specifies the name of the UPF file
245. ng Conditions Conflicting Simstate Behaviors Itis an error if a model has conflicting simstate behaviors specified upf version 2 0 set scope tb topl create power domain pdl set simstate behavior ENABLE model mid top set simstate behavior DISABLE model mid Vopt Message Error vopt 9730 Attribute upf simstate behavior DISABLE on design object midl conflict Example C 21 Error Warning Conditions DISABLE Argument Used Without Supply Ports It is an error if DISABLE is specified and the model has no supply ports upf_version 2 0 set scope tb topl create power domain pdl set simstate behavior DISABLE model mid create supply net VDD N domain pd1 create supply net GND_N domain pd1 Vopt Message Error test upf 6 UPF vopt 9756 Power aware simulation semantics cannot be disabled for design element tb topl mid1 Error test upf 6 UPF vopt 9756 Power aware simulation semantics cannot be disabled for 258 Power Aware Simulation User s Manual v10 2c UPF Commands and Reference upf version upf version Support for UPF Standard v1 0 yes v2 0 yes Arguments none Supported UPF Package Functions Power Aware simulation Supports the UPF 2 0 package that is part of IEEE Std 1801 2009 The following tables list the UPF 2 0 package functions supported for VHDL Table C 2 and System Verilog Table C 3
246. ng an HDL port from UPF overrides its RTL connection Explicit Connections to HDL Ports Using the connect supply net command you can connect a UPF created supply net to an HDL created supply port and a UPF created supply port to an HDL created supply net To ensure the supply net state and voltage values are propagated and modeled in the various HDLs you must use the supply net type datatype You can make these datatypes visible by importing UPF defined HDL packages refer to Appendix B in UPF v1 0 and Annex B in IEEE Std 1801 2009 Examples HDL specification Verilog module memory input supply net type vdd endmod le HDL specification VHDL entity memory is port vdd in supply_net_type end entity UPF specification connect supply net vdd switchable ports mem vdd 270 Power Aware Simulation User s Manual v10 2c UPF Commands and Reference UPF Supply Connections Explicit Connections to 1 bit HDL Ports UPF also allows supply connections between supply nets and 1 bit Verilog VHDL ports for building simple functional models In these cases HDL supply ports are connected to the ON OFF state bit of the supply net For complex modeling you can use value change tables VCTs for the conversion from the supply net state to values relevant to an HDL type or vice versa Limitation Enumerated HDL types are not supported Examples HDL specification Verilog module memory input vdd endmbdiate HDL spe
247. nified Coverage Data Base UCDB file Refer to Saving Code Coverage in the UCDB in the User s Manual for more information Collecting Power Aware Coverage Information on Dynamic Checks You can collect coverage information on dynamic checks and analyze the results within the ModelSim environment Refer to the section Dynamic Checking in Power Aware for more information Power Aware Simulation User s Manual v10 2c 93 Power Aware Coverage Power Aware Coverage Collection Prerequisites Enable dynamic checks with the pa checks switch to vopt Procedure 1 Compile You do not need to alter your existing commands 2 Optimize and Simulate o Enable the default coverage behavior Specifically a power aware dynamic check is marked as covered when the check has been attempted and never failed fail count 0 vopt Add the pa_coverage checks switch e vsim No changes needed o Enable advanced coverage behavior Specifically a power aware dynamic check is marked as covered when the check has never failed and has passed at least once fail count 0 and pass count gt 0 vopt Add the pa_coverage checks switch vsim Add the assertcover switch o View any unattempted power aware check assertions Specifically the coverage data includes information about any unattempted power aware checks You can use this in combination with the other two options vopt Add the pa_coverage checks switch vsim Add the unatt
248. normal working vin p ctrl_p off state off state ctrl_p Power distribution logic may also include on chip analog components such as regulators and sensors A regulator takes an input supply voltage and generates a specific output voltage A sensor monitors a supply rail and signals when the voltage has stabilized at its nominal value with respect to ground Sensors enable construction of a feedback loop so that power control logic can determine when a power rail has completed transitioning Analog components such as these are not specifiable in UPF but can be modeled in HDL code using UPF package functions to model the ramp up and ramp down of power supplies as they switch on and off Power Aware Simulation User s Manual v10 2c 325 Supplemental Information Power Aware Verification of ARM Based Designs Power States UPF provides commands for defining a power state table that captures the possible power states of the system The power state table defines system power states in terms of the states of supply ports or nets For the example in Figure E 1 the following UPF commands define the possible states of the supply ports VDD 0d81 VDD 0499 and VSS as well as the switched ground supply VSS SW add port state VDD 0d99 state ON 0 99 1 10 1 21 add port state VDD 0d99 state OFF off add port state VDD 0d81 state ON 0 81 0 90 0 99 add port state VDD 0d81 state OFF off add port state VSS state ON 0
249. ns UPF provides the concepts and notation required to define the power management architecture for a design A UPF specification can be used to drive the implementation of power management for a given design during synthesis or subsequent implementation steps A UPF specification can also be used to drive verification of power management during RTL simulation gate level simulation or even via static verification methods The ability to use UPF in conjunction with RTL simulation enables early verification of the power management architecture The ability to use UPF across all of these applications eases implementation and validation by enabling reuse of power management specifications throughout the flow UPF syntax is defined as an extension of Tcl 6 which enables UPF descriptions to leverage all of the control features of Tcl UPF captures the power management architecture in a portable form for use in simulation synthesis and routing reducing potential omissions during translation of that intent from tool to tool Because it is separate from the HDL description and can be read by all of the tools in the flow the UPF side file is as portable and interoperable as the logic design s HDL code The concepts introduced in the following sections are illustrated with the UPF commands used to specify them Power Management Architecture In order to employ active power management techniques such as power gating and multiple voltage supplies the
250. ns Containing Macromodels Creating Feedthrough For RTL Conversion Functions Power Aware Simulation User s Manual v10 2c 125 Power Aware Commands and Options ModelSim Commands Used for Power Aware ModelSim Commands Used for Power Aware Tables A 1 and A 2 list the arguments for the vopt and vsim commands that you use to run a Power Aware simulation Refer to the ModelSim Reference Manual for a more comprehensive description of these commands and their arguments 126 Table A 1 Power Aware Arguments for vopt vopt Argument Argument Value s pa all none pa behavlogfile filename pa_ce o l os osw I sc scb pa_cfg lt filename gt pa_checks Quick Reference Comparison of Static and Dynamic Check Arguments pa_checkseq pa_connectpgpin lt tl gt lt unit gt tn2 ilale pa_corrupt pa_nocorrupt real integer pa_dbgstatic msk rsn pa_defertop none pa_dbgstatic msk rsn pa_disable Using pa_enable and pa_disable pa_dumplibertydb lt database_path gt pa_dumpupf lt filename gt pa_enable Using pa_enable and pa_disable pa_excludedelayedbuffer none pa_excludefile lt filename gt pa_genrpt nv vj tus ud uj b pa de pa_gls none required for purely gate level designs pa_hiersep lt alphanum_character gt pa intcrptva
251. nt by associated objects 128 Power Aware Simulation User s Manual v10 2c Table A 3 Power Aware Actions for vopt pa enable and pa disable cont defaultoff Power Aware Commands and Options ModelSim Commands Used for Power Aware Changes the default state of supply nets aud ports to either OFF or FULL ON e pa disable defaultoff sets default to FULL ON pa_enable defaultoff sets default to OFF Default pa_enable detectiso detectret Detect isolation cells present in the design Detect retention cells present in the design pa_enable pa_enable detectls detectsw Detect level shifter cells present in the design Detect switches instantiated in the design and their association with a UPF create_power_switch command pa_enable pa_disable highlight ignorespecialdrivers ignoregroundsupplyconn ignorehangingoutput ignorepowersupplyconn ignoretielow ignoretiehigh ignoreundriveninput Enables highlighting in the Wave window If you enable any of these options the tool disables the automatic insertion of level shifter and isolation cells based on the following scenarios It also disables any static level shifter isolation checking or dynamic checks missing level shifter or missing isolation All of the following scenarios Ports connected to ground supplies Unconnected output ports Ports connected to power supplies Ports tied to 0 Ports tied to 1 Undriven inpu
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253. nts or instance arguments This may cause conflict in the subdomains o The elements can be individually updated for each strategy in all the sub power domains o If any error occurred in transitively applying this command on a subdomain it will not be applied to that subdomain The usage and error messages for incorrectly specifying elements are instance arguments are similar to set isolation set retention control This command will be applied to all the subdomains of a composite domain use interface cell Not supported 196 Power Aware Simulation User s Manual v10 2c UPF Commands and Reference create hdl2upf vct create hdl2upf vct Support for UPF Standard v1 0 yes v2 0 yes Arguments Argument Comments Restrictions hdl type User defined types not supported table Usage Notes Defines a value conversion table VCT from an HDL logic type to the net state type of the supply net value when that value is propagated from HDL port to a UPF supply net Power Aware Simulation User s Manual v10 2c 197 UPF Commands and Reference create logic net create logic net Support for UPF Standard v1 0 no v2 0 yes Arguments Comments Restrictions net name The name of a logic net that you want to create in the active scope Usage Notes Results in the created net reflecting the same value as a port that you connect to it using the connect logic net command net dut and pm
254. o not cause corruption when powered down but they may propagate corrupted signals from upstream drivers In Gate Level code all cell instances are interpreted as containing drivers As a result buffer cell instances in a gate level netlist will cause corruption when powered down Refer to the section Detection of Gate level Cells for information on the detection of any particular model as a gate level cell Modeling Isolation Isolation is used to ensure correct logical and electrical interactions between a powered down domain that is the source of a signal and a powered up domain that is the receiver of that signal Isolation ensures that the receiving power domain sees a stable known logic value while at the same time preventing so called crowbar current due to an indeterminate source value partially enabling both transistors of a CMOS inverter at the same time Note LLL Isolation cells themselves must be powered in order to function correctly If the power supply for an isolation cell is turned off the isolation output is corrupted regardless of the state of the source power domain A given power domain may be powered off while another domain is operating in normal mode Isolation ensures the following Powered down regions do not drive unknown values into the rest of the design isolation on outputs Therest of the design receives values that are functionally correct isolation on inputs Modeling Retention R
255. of an isolation control signal In general this ensures that if activation of isolation control occurs that it is required by power management behavior Error vsim 8934 MSPA ISO REDUNDANT ACT Time 430 ns Redundant activity on isolation control signal for crossing PD_mid1 gt PD_mid2 Port tb TOP mid1 out1_bot File test upf Line 44 Power Domain PD_mid1 Isolation vopt pa checks irc The value on isolated ports should not change when Race Check isolation is enabled at the time of assertion of isolation control and when isolation 1s disabled at the de assertion of isolation control This check flags any toggling of isolated port s value at assertion de assertion of isolation control signal Error vsim 8910 MSPA ISO PORT TOGGLE Time 50 ns Isolated port for isolation cell strategy iso PD midl on port tb TOP mid1 out2_bot toggled when its control signal is activated File test upf Line 70 Power Domain PD_mid1 Isolation vopt pa_checks it Catches any change in isolated ports value during Toggle isolation period such as in between the period when Check isolation 1s enabled till isolation is disabled Performed during active isolation period Error vsim PA 8908 MSPA ISO ON ACT Time 60 ns tb TOP midl outl bot toggled when isolation signal was active Power Aware Simulation User s Manual v10 2c 83 Automatic Checking Dynamic Checking in Power Aware Table 5 4 Dynami
256. off clamp value UPF pg type pg type value set port attributes pg type UPF related ground pin port name set pin related supply related ground pin set port attributes related ground port UPF related power pin port name set pin related supply related power pin set port attributes related power port UPF related bias pin port name set port attributes related bias port UPF retention required optional set retention elements retention UPF simstate behavior ENABLE DISABLE set simstate behavior Specifying Attributes You can use the set design attributes and set port attributes commands to specify attributes for Power Aware simulation The following arguments for these UPF commands are now supported set design attributes 262 Power Aware Simulation User s Manual v10 2c UPF Commands and Reference Supported UPF Attributes elements models attribute set port attributes ports domains elements model attribute clamp value sink off clamp value source off clamp value related power port related ground port pg type Limitations In some cases related power port related ground port might not work properly with model pg type might not work on UPF created supply ports nets e source off clamp value sink off clamp value clamp value only affects the filtering of ports affected by the set isolation command Attributes
257. olation upf Example ISOLODIBWP trafficWriteEnable UPF ISO I trafficWriteEnable ISO n16 Z n57 synopsys isolation upf PD C2 ISS1 PD C2 o Liberty attribute is isolation cell Example cell ISO LO is isolation cell true o HDL attribute is isolation cell Example 290 Power Aware Simulation User s Manual v10 2c UPF Commands and Reference Supply Nets is isolation cell 1 module ISOCELL ISO Z2 endmodule o Cellin accordance with map isolation cell UPF command Example UPF Command map isolation cell mem ctrl iso 0 domain PD mem ctrl l ib cells ISO LOJj Instantiation in hdl ISO LO addr O I n158 ISO n174 Z address 0 o Instance name in accordance with name format UPF command Example UPF Command name format isolation prefix MY ISO isolation suffix UPF ISO Instantiation in hdl SEN OR2 4 MY ISO t state 21 UPF ISO A1 n151 A2 n354 X t state 21 Limitations If isolation is required and is not present and identified with set isolation instance then Power Aware simulation effectively inserts an isolation cell The current Power Aware architecture implements isolation by actually inserting a cell an instance of a behavioral model for isolation into the design where isolation is required However ports on an isolation cell inserted this way have a limit
258. omain PD_mid3 Isolation vopt pa_checks iep Flags violation if isolation control of isolation Enable cell strategy is not enabled when source power domain Protocol power domain of driving ports is switched OFF and Check sink power domain ON Error vsim 8918 MSPA ISO EN PSO Time 358 ns Isolation control 0 is not enabled when power is switched OFF for the following Port tb 25 FA4 inst FA inst2 d Power Aware Simulation User s Manual v10 2c 81 Automatic Checking Dynamic Checking in Power Aware Table 5 4 Dynamic Isolation Checks cont Check Usage Syntax Description Example Message Isolation Disable Protocol Check for COA States vopt pa checks idpcoa Isolation Enable Protocol Check for COA States vopt pa checks iepcoa Flags violation if isolation control is disabled when the driving power domain is in the following CORRUPT simstates and receiving logic does not have a CORRUPT simstate CORRUPT CORRUPT ON ACTIVITY CORRUPT STATE ON CHANGE and CORRUPT STATE ON ACTIVITY Error vsim 8919 MSPA ISO DIS PG Time 60 ns Isolation control is disabled during driving supply CORRUPT ON ACTIVITY simstate 1 for the following Port tb TOP midl outl bot File test upf Line 62 Power Domain PD_mid1 Flags violation if isolation control is not enabled when a driving power domain goes into any of the following states and receiving logic does not have CORRUPT simstate CORRU
259. omain argument when provided create pst Creates a power state table PST create supply net create supply port Creates a supply net Defines a supply port create supply set Creates the supply set name within the active scope create upf2hdl vct Defines a value conversion table for the two LSBs of the supply state type state value when that value is propagated from a UPF supply net into a logic port defined in an HDL describe state transition Not supported find objects Finds logical hierarchy objects within a scope get supply set load simstate behavior Not supported Loads a UPF file containing the defaults of simstate behavior for a library load upf Sets the scope to the specified instance and executes the set of UPF commands in the specified UPF file load upf protected Loads a UPF file in a protected environment that prevents corruption of existing variables map isolation cell Maps an isolation strategy to a library cell or range of library cells to be inserted for isolation map level shifter cell map power switch N N Maps a particular level shifter strategy to a simulation or implementation model Not supported map retention cell 174 Partial Partial Constrains retention strategy implementation choices and may also specify functional retention behavior for verification Power Aware Simulati
260. omains pd aon Pathl scope tb top aon pd Path2 scope tb top vh lt gt pd Path3 scope tb top vl lt gt 62 Power Aware Simulation User s Manual v10 2c Power Aware Reports UPF Reports Corrupted Signals The signals inside the power domain corrupted when the supply of the power domain is switched off Format The report format for listing corrupted signals is the following power domain Path lt N gt lt signal gt where power domain identifies the name of the power domain When power domain is represented by two dashes it indicates that the signal was excluded using exclusion rules e Path N identifies the hierarchical path of the scope in the rest of the report signal identifies the name of the signal Example Design Elements Report Excerpt for Corrupted Signals pd aon Path1 q combvl pd Path2 q latvh NPM LA pd Path3 q_regvl R State Elements The signals in the design acting as state elements are listed in the same way as Corrupted Signals along with a special keyword that identifies the kind of state element Format The report format for listing corrupted signals is the following power domain Path lt N gt lt signal gt keyword where e power domain identifies the name of the power domain When power domain is represented by two dashes it indicates that the signal was excluded using exclusion rules
261. on 0 99V Arnannnnannnnannnnnnannnn an njan B pana eds nmm PD mem ctrl switched 0 81V VDD 04d81 VSS VDD 0d99 LJ PD sram 0 99V 3 Always on SRAM ml E l iu n SRAM a m2 SRAM m3 TE SRAM gt m4 r PAD PAD IN PAD IN PAD IN MESARERESARERS3A In the ON mode it reads input data streams interleaves them and stores them in the memory before driving them onto outputs In the SLEEP mode it monitors inputs and maintains the state of its memory but it does not process inputs Power Domains Each independently powered subsystem or subcomponent is called a power domain At the RTL stage a power domain is typically somewhat abstract consisting of some or all of the RTL logic within a given portion of the design hierarchy At the logical netlist stage a power domain consists of a collection of cells that will share the same primary power and ground supplies At the physical level the cells associated with a given power domain may be placed in a contiguous region of a chip or distributed over multiple discontiguous regions of the chip The design in Figure E 1 has several major components These include the interleaver block the memory controller block and the memory itself Each of these can be defined as a separate power domain The top level of the design is also a separate power domain The dotted lines in Figure E 1 indicat
262. on User s Manual v10 2c UPF Commands and Reference Supported UPF Commands Table C 1 List of Supported UPF Commands UPF Support Command merge power domains name format 1 0 N Partial 2 0 N Partial Description Not supported Defines the format for constructing names of implicitly created objects query design attributes query port state N A Returns state information about attributes for a design element or model Returns state information for a specified port query power domain query power state Partial Returns parameters of a power domain Returns the state information for a power domain or supply set query power switch query pst N A Returns information for a UPF power switch Returns information for any defined PSTs query pst state N A Returns state information for a PST query supply net N A Returns state information about a previously created supply net query supply port N A Returns state information about a previously created supply port save upf Partial Y Creates a UPF file of the structures in the relative to the active scope set design attributes Partial Sets the specified attributes for models or design elements set design top set domain supply net Y Specifies the root of the design Associates the power and ground supply nets with the primary supply set for the domain
263. onn Domain pd top Possible reason Level shifter is specified as no shift e pa_dbgstatic msk Captures the connection mask of the signal taken in a particular path For example if there is a vector taking a different path the phrase connected mask provides Power Aware Simulation User s Manual v10 2c 71 Automatic Checking Static Checking in Power Aware information about which bits are used in connecting the particular source and sink Report File example report static txt Inferred type Incorrect count 0 Source port tb TOP bot4 outl bot connected mask 0100 LowConn Domain pd aon gt Sink port tb TOP bot4 out 1 bot connected mask 0100 HighConn Domain pd top Static Isolation Checks Table 5 1 lists a summary of the various static isolation checks you can apply by specifying different values for the vopt pa checks command All static isolation check results are written to the report file report static txt Table 5 1 Static Isolation Checks Usage Syntax Description Example Message Static vopt pa_checks smi For domain crossings where the source domain is Missing relatively OFF with respect to sink domain Reports missing isolation cells for any isolation strategies not specified for such crossings Warning vopt 9750 UPF ISO STATIC CHK Found Total 1 Missing isolation cells Static vopt pa checks sri If power domain crossings occ
264. ope in the rest of the report signal identifies the name of the signal e R indicates a retention signal Example Excerpt of UPF Commands set retention pd retention domain pd retention power net V pd net set retention control pd retention domain pd save signal ret posedge restore signal ret negedge 64 Power Aware Simulation User s Manual v10 2c Power Aware Reports UPF Reports Example Design Elements Report Excerpt for Retention Signals pd Path3 q_regvl R pd Path2 q_regvh R Working With A Design Element Report General Information The name of the report and other information are presented as commented text at the top of the report Comments are marked with double hyphens at the beginning of a line For example QuestaSim Version DEV 10 0 2238002 2010 11 Generated on Mon Nov 22 13 44 03 2010 Extracting Information from a Design Element Report The structure and keywords of a Power A ware design element report allow you to extract the information related to power intent easily and effectively using any string matching utility such as the grep command The following examples show how to use the grep command to extract specific details of your power intent List all instances in the design belonging to a power domain Function Search all scopes belonging to power domain pd aon Command grep pd aon report de txt grep scope Output pd aon Pathl scope tb top ao
265. opt pa excludefile Notes about instance e If there is a port of type pg type present on the instance then Power Aware simulation automatically connects the primary power and primary ground pins with primary power and primary ground nets of the power domain It connects the backup power and backup ground pin specified on the instance with the retention power and ground nets specified in the strategy If there is no port of type pg type present on the instance then Power Aware simulation applies implicit corruption semantics according to the primary power and ground nets specified for the power domain Power Aware Simulation User s Manual v10 2c 251 UPF Commands and Reference set retention control set retention control Support for UPF Standard v1 0 yes partial v2 0 yes partial Arguments Argument 0 Comments Restrictions domain save_signal restore_signal assert_r_mutex Not supported assert_s_mutex Not supported assert_rs_mutex Not supported 252 Power Aware Simulation User s Manual v10 2c UPF Commands and Reference set scope set scope Support for UPF Standard v1 0 yes v2 0 yes Arguments Comments Restrictions The syntax of set scope in UPF only allows hierarchical path up to instances design elements This has been extended under the above mentioned switch to accept hierarchical path of generate blocks as well This allows
266. opup Menu Popup Menu Item Description View State Machine Displays a graphical representation of the power aware state transitions in the Power Aware State Machine Viewer Window View UPF Opens the UPF file and displays the line creating the power aware state machine Add to Adds the selected or all state machines to the Wave window List window or to the log add log Properties PA State Machines Menu Displays the Power Aware State Machine Properties dialog box which contains detailed information about the selection Table 7 3 PA State Machines Menu View State Machine Displays a graphical representation of the power aware state transitions in the Power Aware State Machine Viewer Window View UPF Opens the UPF file and displays the line creating the power aware state machine Adds the selected or all state machines to the Wave window List window or to the log add log Options Opens the State Machine Display Options dialog box that allows you to control e Specific instructions when adding state machines to the Wave window Limit the number of path elements in the Instance column Power Aware State Machine Viewer Window Use this window to view a state diagram of any of your power aware state machines This window is very similar to the FSM Viewer Window Power Aware Simulation User s Manual v10 2c 119 Visualization of Power Aware Operations Power State
267. or sequential UDPs in a gate level or mixed RTL and gate level simulation These modes describe the functionality of different sequential UDPs introduced to mimic corruption and retention behavior e Save mode single control Occurs when save is active Save mode dual control Occurs when save is active and restore is inactive Restore mode single control Occurs when save is inactive Restore mode dual control Occurs when save is inactive and restore is active Error mode dual control When the UPF set retention parameter SAV RES COR is true the output of the register and the retained value of the register are both corrupted if the save and restore both are active and save condition and restore condition are true This occurs only when neither the save signal nor the restore signal are edge sensitive 42 Power Aware Simulation User s Manual v10 2c Power Aware Simulation Applying Power Intent to the Design e No change mode dual control Occurs when save and restore are both inactive In this case the register is neither in save nor in restore mode Therefore the behavior would be as if it is a normal register with no retention facility present Note User defined models specified using the map retention cell command will not be honored for sequential UDP retention However the RTL portion of design will follow the user defined model simulation semantics given with map retention cell comm
268. or RTL Conversion Functions In RTL logic a function call normally creates a driver in the design to which Power Aware will attempt to apply the specified power intent However functions that are intended only to 156 Power Aware Simulation User s Manual v10 2c Power Aware Commands and Options Creating Feedthrough For RTL Conversion Functions convert or assign data types should not be considered as part of the power intent they do not require isolation retention or corruption You can create a Tcl file to identify such functions in your design so that they are excluded from your power intent These are referred to as a feedthrough functions In the Tcl file you use the set feedthrough object command for each function you want to exclude Syntax set feedthrough object function function list package package name When you run Power Aware use vopt pa tclfile to specify the name of this Tcl file function function list a list of function name This is a mandatory option and at least one function name should be specified e package package name optional detects functions from the specified package only Power Aware Simulation User s Manual v10 2c 157 Power Aware Commands and Options Creating Feedthrough For RTL Conversion Functions 158 Power Aware Simulation User s Manual v10 2c Appendix B Model Construction for Power Aware Simulation Power Aware verification uses Verilog behavioral mod
269. or example add port state VN1 state 1p1 1 0 relatedsnet Supports the behavior for the Tcl command set related supply net Allows relative paths in set scope command For example set scope Allows automatic insertion of vct for pins detected as power and ground pins mapcell Supports the use of lib cells specified in map power switch map isolation cell and map level shifter cell UPF commands in lt libraryname cellname gt format For example map power switch PD ONE domain PD SUP lib cells LIB NODE 268 Power Aware Simulation User s Manual v10 2c UPF Commands and Reference UPF Supply Connections Table C 5 Power Aware Actions for vopt pa upfextensions cont wildcard Supports the use of the wildcard character to the following UPF commands add domain elements elements bind checker elements connect logic net ports connect supply net ports connect supply set elements create power domain elements exclude elements map isolation cell elememts map level shifter cell elements map retention cell elements set design attribute elements set isolation elements set level shifter elements set retention elements set pin related supply pins set related supply net objects set port attribute elements ports UPF Supply Connections Supply connections between various UPF objects can made between supply nets supply sets supply ports power switches a
270. or pd HEEE FE HE HE HE HE HE HE HE E HE FE HE HE HE HE E HE HE HE HE E HE H E H H H H H Power Aware Simulation User s Manual v10 2c 49 Power Aware Reports UPF Reports set retention pd retention domain pd retention power net V pd net set retention control pd retention domain pd save signal ret posedge restore signal ret negedge map retention cell pd retention domain pd 1lib model name upf retention ret lib cell type FF CKHI TEE EE HE HE HE TE FE E E E HE E E HE HE HE E ERE HE E ERE EE E E EG E isolation Strategy for pd TEE EE HE HE HE TE HE E HE E HE E E HE HE HE E E E EE E E EE EHHH set_isolation pd isolation domain pd isolation power net V pd net clamp value 1 applies to outputs set isolation control pd isolation domain pd isolation signal iso isolation sense high location parent Example 4 2 UPF Power Intent Report Total tb upf retention ret 2 NPM FF 1 NPM LA 3 OUTPUT 3 pd sub total tb top vh tb top vl upf retention ret 2 tb top vh q regvh 1 tb top vl q regvl 1 SS NPM LA 2 tb top vh q latvh tb top vl q latvl TS OUTPUT 2 tb top_vh q_combvh 1 tb top_vl q_combvl 1 pd aon sub total tb top aon NPM FF 1 tb top aon q regv NPM LA 1 tb top aon q latv OUTPUT 1 tb top aon q combvl 1 50 Power Aware Simulation User s Manual v10 2c Power Aware Reports UPF Reports
271. ormation on Dynamic Checks 93 Collecting Power Aware Coverage Information on States and Transitions 95 Power Aware Coverage Analysis uda pw E Eia Sede c pu ee p dees tap EX ES 96 Generating a UCDB File for Power Aware lssseeeeeee ee 96 Generating Power Aware Coverage Reports lleeeeeeeeeeeeeee 96 Generating HTML Reports 22 082scnseeebevebs barca ERR AR RE LER REG 99 Accessing Coverage Data for Post Simulation Analysis llle esee 99 Power Aware Coverage Report Reference 0 cece eee cece e eee eens 100 Power Aware Coverage Summary 2 ssec ese sr rh er pe REEL RE TRE 100 Power Aware Coverage Detailed Report 0 0 0 eee eee eee eee 100 Power Aware Coverage Verbose Report 0 00 ee eens 103 Power Aware Checks Coverage Summary 0 0 c cece eee eee eee eens 103 Power Aware Checks Coverage Detailed Report 0 0 0 ee eee eee eee 103 Chapter 7 Visualization of Power Aware Operations 0 cece ccc c cece cece rn 105 UPF Object Display 2 449 nac ds tees HEU ERES ER RENTERET RENI E oe eR eee eee ey 105 Visualizing UPF Objects in the GUI issu sour RE EGRE RR Ex ERE 105 Power Aware Schematic Display is vkes hxc eR RR Rex RARE REA RE ghar 107 Top Down Debugging From the Test Bench slseeeeleeeeeeeee 108 Bottom Up Debugging From the Design Under Test 0 020204 108 Usage NoI88 ior ierni rip E
272. ou specify a value of fanout a level shifter will be identified for placement at all fanout locations for valid level shifters and the count is incremented accordingly in the report If you specify self parent sibling or automatic then only one level shifter will be identified for placement at a fanout location Thus the report may show a count of level shifters in some paths to be 0 Supports only the following values self parent fanin fanout faninout Example set level shifter LS1 domain pd1 elements out3 out4 2 1 instance Recognizes the special attributes present on the specified instance applies the appropriate simulation semantics currently disables the Power Aware simstate semantics Power Aware Simulation User s Manual v10 2c Allows adding elements and supplies to a previously created power domain for a progressive refinement of power intent 241 UPF Commands and Reference set level shifter Argument 0 Comments Restrictions force shift input supply set output supply set internal supply set name prefix name suffix source Selects the ports receiving a net that is driven from a port on the interface of the specified domain See Usage Notes below Selects the ports driving a net that fans out to a port on the interface of the specified domain See Usage Notes below transitive Not supported U
273. ou to prevent stoppage of vopt operation or inconsistent behavior in processing and resolve phases when the error is encountered An Power Aware Simulation User s Manual v10 2c 141 Power Aware Commands and Options Excluding Design Elements from Power Aware example of this is when vopt stops for errors in the processing phase while continuing when the same errors occur in the resolve phase When you suppress or lower the severity of an error message you may not see the desired Li result since the corresponding UPF command behavior gets bypassed or ignored Examples Use vopt to suppress or change the severity of a single message vopt pa upf top upf o t tb suppress msg num Use vopt to suppress or change the severity of multiple messages vopt pa upf top upf o t tb warning msg num i msg num2 msg num3 Excluding Design Elements from Power Aware You can exclude Power Aware processing for any module instance or signal within a particular hierarchical path in a design Usage vopt pa excludefile filename Description The pa excludefile option instructs Power Aware processing to skip any module listed in the specified exclude file filename The name of a text file that specifies modules instances or signals you want to exclude from Power Aware verification Entries for modules must be of the following form module name a hier path module name any regular expressio
274. ower Aware General Steps for Running Power Aware 1 Map your libraries vlib library name 1 Map Libraries vmap work library name 2 Compile your VHDL or Verilog design files ignore statements within translate off on and synthesis off on 2 Compile Design pragmas vcom design files vlog design files 3 Elaborate Design 3 Elaborate your top level design and apply the UPF power intent to the design vopt design top pa upf upf file o 4 Simulate optimized output There are multiple methods of using the vopt command to prepare and optimize a Power Aware simulation 4 Simulate the Power Aware version of your design vsim pa optimized output Power Aware Simulation Flows There are three major flows available for use with Power Aware simulation including The standard three step flow where you explicitly invoke an optimization step The delayed optimization two step flow where optimization is invoked implicitly before simulation The no optimization flow where you do not invoke optimization either explicitly or implicitly 28 Power Aware Simulation User s Manual v10 2c Power Aware Simulation Power Aware Simulation Flows The first two flows are strongly recommended The optimization step used in these flows whether invoked explicitly or implicitly provides the following advantages for power aware simulation Dramatically better performance for Power
275. ower Configuration File PCF as part of a Power Aware analysis at the RTL level as follows Power Aware Simulation User s Manual v10 2c 299 Power Configuration File Reference PCF Syntax and Contents 1 Code the functional design using normal RTL coding guidelines Specifically the power control network is not wired through the RTL functional network Model the power management blocks including the definition of the power control signals These signals either indicate the on off status of power to specific power islands or flag the storing and restoring of state information Use the PCF to specify how the power control network overlays connect to the functional network Use a Power Aware library of Verilog models provided by the silicon or library vendor The library models trigger relevant events for the simulator so that the simulator can modify the run time behavior of the RTL design to corrupt state and outputs and store or restore state values based on power control network activity For more information refer to Model Construction for Power Aware Simulation Use the PCF to map the Power Aware models to sequential elements in the design Use the Power Aware model library it is presumed to be precompiled as it does not change Compile the RTL design normally Simulate the design see Using the Standard Flow When the design is simulated the simulator will take the PCF as input as well as the compiled design P
276. pect to the DUT top then you must specify vopt pa_top lt pathname gt to specify the path from the top module down to and including the DUT instance Example 1 If the UPF specification is written with respect to the top of the design under test DUT and this module is instantiated in the testbench top module TB as TB dut then you need to invoke vopt as follows vopt TB pa top TB dut pa lib work pa upf DUT upf o SimModel other vopt args where TB the name of the top level module of the test bench e pa top TB dut the path from the test bench top down to the design top instance e pa upf DUT upf the name of the UPF file written with respect to the DUT top level module 30 Power Aware Simulation User s Manual v10 2c Power Aware Simulation Power Aware Simulation Flows e pa lib work the name of the destination library oSimModel the name of the optimized output for your vsim run e other args any other vopt arguments used to control optimization Example 2 If the UPF specification is written with respect to the top of the testbench TB then you need to invoke vopt as follows vopt TB top pa_upf TB upf pa lib work o SimModel other vopt args where e TB top the name of the top level module of the test bench pa upf TB upf the name of the UPF file written with respect to TB top e pa lib work the name of the destination library e oSimModel
277. perations Power Aware Schematic Display o Isolation cells will be filled in with a green color o Level shifter cells will be filled in with a purple color Excluded Domains shown as default schematic color You can define a power domain to be excluded o Power Aware exclude file support vopt pa excludefile o Currently PG type connected instances are excluded There is no analysis information to decide whether they inherit the parent power domain create their own or have multiple power domains like memories Both are supported with instance level granularity signal and process level exclusion will not be visualized UPF Source Viewing You can display the source text of the UPF file for power domain specifications Power domain information can be viewed for a design element in either of the following ways o Right click and select View Selection Power Domain Displays UPF source code see Figure 7 5 o Hover the mouse cursor Displays a Tool Tip that concatenates the HDL source file with the appropriate line number in the UPF source file see Figure 7 6 Example 7 1 UPF Flle to Demonstrate Schematic Visualization for Debugging 110 set design top top create power domain P1 el create supply port create suppl connect supply net create supply port create suppl connect supply net net net create supply net set domain supply net P1 primary power net VDD PRI primary ground net
278. pf load simstate behavior lib2 file load2 upf create power domain pdl set simstate behavior ENABLE elements mid1 bot1 create supply net VDD N domain pd1 create supply net GND_N domain pd1 where load1 upf consists of set simstate behavior ENABLE model mid set simstate behavior DISABLE model bot load2 upf consists of set simstate behavior ENABLE model top 210 Power Aware Simulation User s Manual v10 2c UPF Commands and Reference load simstate behavior Example C 2 Error Warning Conditions Unknown Library Name Itis an error if the specified library cannot be resolved upf version 2 0 set scope tb topl load simstate behavior lib1 file simstate filel upf Vopt Message Error test upf 6 UPF vopt 9753 Library lib1 does not exist Example C 3 Error Warning Conditions Library File Does Not Exist It is an error if specified file does not exist upf version 2 0 set scope tb topl load simstate behavior lib1 file sim upf Vopt Message Error test upf 6 UPF vopt 9718 Can t open file sim upf Example C 4 Error Warning Conditions Model Cannot Be Found It is an error if a model specified in file cannot be found main upf upf version 2 0 set scope tb topl load simstate behavior lib1 file sim upf sim upf set simstate behavior ENABLE model mad Vopt Message Error sim upf 1 UPF vopt 9655 Model mad
279. phics all reasonable information and assistance to settle or defend the action and c grant Mentor Graphics sole authority and control of the defense or settlement of the action 12 13 14 15 16 17 11 2 If aclaim is made under Subsection 11 1 Mentor Graphics may at its option and expense a replace or modify the Product so that it becomes noninfringing b procure for Customer the right to continue using the Product or c require the return of the Product and refund to Customer any purchase price or license fee paid less a reasonable allowance for use 11 3 Mentor Graphics has no liability to Customer if the action is based upon a the combination of Software or hardware with any product not furnished by Mentor Graphics b the modification of the Product other than by Mentor Graphics c the use of other than a current unaltered release of Software d the use of the Product as part of an infringing process e a product that Customer makes uses or sells f any Beta Code or Product provided at no charge g any software provided by Mentor Graphics licensors who do not provide such indemnification to Mentor Graphics customers or h infringement by Customer that is deemed willful In the case of h Customer shall reimburse Mentor Graphics for its reasonable attorney fees and other costs related to the action 11 4 THIS SECTION 11 IS SUBJECT TO SECTION 8 ABOVE AND STATES THE ENTIRE LIABILITY OF MENTOR G
280. play The FSM List and FSM Viewer windows provide finite state machine information on power state tables and multi state transitions UPF Object Display You can view objects created through the UPF file in the Structure Objects and Wave windows by adding the pa_enable supplynetworkdebug option to your vopt command A special icon is used to identify UPF objects in these windows Figure 7 1 UPF Object Icon Visualizing UPF Objects in the GUI This task outlines how you can enable the visualization of UPF objects in the Structure Objects and Wave windows Prerequisite Have an existing power aware simulation flow Power Aware Simulation User s Manual v10 2c 105 Visualization of Power Aware Operations UPF Object Display Procedure Open the ModelSim GUI 2 Add the pa_enable supplynetworkdebug option to your vopt command 3 Run your power aware simulation flow as you normally would 4 Ensure the Objects Structure and Wave windows are open o view structure o view objects o view wave 5 Locate and select a UPF object in the Structure Window refer to Figure 7 2 106 a Click the UPF object to view additional port and net information in the Objects window b Right click the UPF object and select Add Wave to add all of the related ports and nets in the Wave window The default value of supply ports and nets in these windows are Voltage Decimal e State Enum UNDETERMINED FULL ON OFF PARTIAL O
281. ply net gnd net ports gnd port set domain supply net pd aon primary power net vdd net primary ground net gnd net HEEE FE E HE HE HE E ERE HE HE HE HE H E H H H ERE pd Power Domain HEEE FE E HE HE HE HE HE HE HE HE HE HE H H H H H HH create_power_domain pd elements top vl top vh create supply port V pd port domain pd create supply port G pd port domain pd create supply net V pd net domain pd create supply net G pd net domain pd create supply net pd pwr domain pd THERE HE HE HE HE HE ERE HE HE HE HERE HE HE HERE ERE HE HE HE HE HE HE HE HE HE REESE ERE RE ERE connect supply ports to supply nets TEE FE HE HE HE TEE HE HE HERE HERE HERE EE HH EE EE EHE HE HE HE HE HE NE NE HH connect supply net V pd net ports V pd port connect supply net G pd net ports G pd port set domain supply net pd primary power net pd pwr primary ground net G pd net HEHE FE TE EE HE TEE HE HE RE HE FE TE HE RE E EE EE EE ERE EE EHE HE HE HE HE HE NE H H Header switch for pd THERE HE HE HE HE HE ERE HE HE FE HE HE HE HE HE HE TEE HE HERE HERE HE HE H HE ERE H H ERE ERE create_power_switch pd_sw domain pd output supply port out sw pd pd pwr input supply port in sw pd V pd net control port ctrl sw pd pwr on state normal working in sw pd ctrl sw pd off state off state ctrl sw pd HEEE FE E TEE TEE HE HE TEE ERE ERE HE E HE HE HE HE E HE H H H H EE NE Retention Strategy f
282. ply set used to power the register holding the retained value Note the following cases e If you have specified both retention power and retention ground nets using this command creates an implicit retention supply set and is used with the specified strategy The retention power net serves the power function in the retention supply set and the retention ground net serves the ground function in the retention supply set If you have specified the retention power net but not the retention ground net then the domain s primary supply sets ground function is used as the retention ground If you have specified the retention ground net but not the retention power net then the domain s primary supply sets power function is used as the retention power Note that the power of the retention cell is preserved an extra port RETPWR Retention Power 1s added to the retention models Whenever the power of a retention cell RETPWR goes down the value stored in retention cell gets corrupted and the X value is restored when restore signal is triggered Example Consider the following logic added in a retention model store x in RETPWRDOWN always negedge RETPWR begin pa store x end An extra port RETPWR has been added in the Power Aware retention models Whenever you use your own retention models using the map retention cell UPF command For a user defined model with RETPWR port and corresponding logic Behavior will be
283. ported map power switch Not supported map retention cell Not supported set isolation This command will be transitively applied to all the subdomains of a composite domain The following are also in effect o Set isolation domain composite domain cannot have elements exclude elements instance argument This may cause conflict in the subdomains o The elements can be individually updated for each strategy in all the sub power domains o Ifany error occurred while transitively applying this command it will not be applied to that subdomain o Ifa strategy has already been applied on a subdomain trying to set a strategy of that same name directly on that subdomain without update will be an error Correct usage example create composite domain cd subdomains pd2 pd3 supply primary pdsub ss set isolation cd iso1 domain cd clamp value 0 applies to inputs isolation signal iso isolation sense high location parent set isolation cd iso2 domain cd clamp value 0 applies to outputs isolation signal iso isolation sense high location parent Alternate correct usage create composite domain cd subdomains pd2 pd3 supply primary pdsub ss set isolation cd iso domain cd update clamp value 0 applies to outputs isolation signal iso isolation sense high location parent 194 Power Aware Simulation User s Manual v10 2c UPF Commands and Reference create composite
284. porting report upf txt Power Domain pd File src supplyl prefix test upf 7 Creation Scope tb top Primary Supplies power tb top pd pwr Power Aware Simulation User s Manual v10 2c 51 Power Aware Reports UPF Reports ground tb top G pd net Power Switch pd sw File src supplyl_prefix test upf 35 Output Supply port out sw pd tb top pd pwr Input Supply ports 1 in sw pd1 tb top V pd net1 2 in sw pd2 tb top V pd net2 Control Ports 1 ctrl sw pdl tb top pwrl 2 ctrl sw pd2 tb top pwr2 Switch States 1 normal working2 ON ctrl sw pd2 amp amp ctrl sw pd1 2 normal workingl1 ON ctrl sw pd1 amp amp ctrl sw pd2 3 off state OFF ctrl sw pd1 amp amp ctrl_sw_pd2 Retention Strategy pd retention File src supplyl prefix test upf 39 Retention Supplies power tb top V pd net ground tb top G pd net Retention SAVE tb top ret Retention Sense posedge Retention RESTORE tb top ret Retention Sense negedge Isolation Strategy pd isolation File src supplyl_prefix test upf 45 Isolation Supplies power tb top V pd net ground tb top G pd net Isolation Control tb top iso Isolation Sense HIGH Clamp Value 1 Location parent Isolated Signals 1 Signal tb top q combvl 2 Signal tb top q latvl 3 Signal tb top q regvl Level Shifter Strategy pd ls File src supplyl prefix test upf 51 Rule both Threshold 0 Applies
285. power aware simulation Power Aware simulation reads Liberty libraries to collect this information and takes it into account in building and executing a power aware simulation model Power aware simulation also requires a specification of power intent for the design to be simulated Power intent is specified using the IEEE 1801 Unified Power Format UPF Power Aware simulation supports both UPF 1 0 and UPF 2 0 Commands Used For Power Aware Simulation You invoke Power Aware simulation with the same commands used for conventional ModelSim simulation although the optimization vopt and simulation vsim commands have additional arguments For conventional ModelSim simulation you use the following commands vlog or vcom Used to compile Verilog SystemVerilog or VHDL source code For Power Aware simulation these commands are used in the same manner Power Aware Simulation User s Manual v10 2c 27 Power Aware Simulation Power Aware Simulation Flows vopt Used to enable or disable optimization in the HDL design For Power Aware simulation the vopt command also processes the UPF power intent specification e vsim Used to run simulation on the HDL design For Power Aware simulation the vsim command also applies Power Aware simulation semantics to the HDL design For a complete listing of the Power Aware arguments beyond what is discussed in this section provided for these commands refer to ModelSim Commands Used for P
286. power domain Power domain elements can be in one of the following simstates based on which power states of the related supply set are true at a given simulation time NORMAL CORRUPT CORRUPT ON ACTIVITY CORRUPT STATE ON CHANGE or CORRUPT STATE ON ACTIVITY Typically power states are composed hierarchically while creating power intent for example the power state of a top level power domain depends upon power states of any contributing power domains These contributing power states leaf level power domains then depend upon power states of their supply sets Power states of a supply set depend upon power states of supply nets associated with functions of the supply set Therefore as design complexity increases such as with IP level hierarchical power intent these power states become drivers for the whole power aware verification and it becomes important to provide debugging facilities for power states Note You can find an example of a UPF file with a PST at install dir examples pa sim example one rtl top upf Differences Between a Conventional RTL FSM and a PASM Some conceptual differences between conventional RTL Finite State Machines FSM and Power Aware state machines are Power Aware State machines are asynchronous in nature there use no concept of clock Power Aware state machines can reach multiple states at a time Nondeterministic Situation Power Aware state machines are modeled by Power A wa
287. power domains with different fixed voltages per domain Power domains that can be put into bias mode for state retention with low static leakage To verify these structures you create a UPF Power Intent Specification that includes the following Definition of the power domains within your design and the instances that belong to each power domain Definition of the power states of those power domains their corresponding primary supplies and the simstates associated with primary supply states Power Aware Simulation User s Manual v10 2c 13 Getting Started With Power Aware Simulation Where Is Power Aware in Your Design Flow Definition of strategies for inserting powering and controlling retention cells in a power domain to retain state during power down Definition of strategies for inserting powering and controlling isolation cells and level shifter cells at power domain boundaries to mediate interactions between power domains in different states or at different voltage levels Definition of supply networks including supply ports nets and power switches required to provide power to each domain Where Is Power Aware in Your Design Flow Before you begin to use Power A ware to perform a power aware simulation on your RTL design you should evaluate where you are in your overall design flow Figure 1 1 shows an approximation of a typical design sequence and where Power Aware might occur in that sequence Before
288. pply set Specifically listing the previously defined power states for the specified object name which can be a power domain or a supply set 224 Power Aware Simulation User s Manual v10 2c UPF Commands and Reference query power switch query power switch Support for UPF Standard v1 0 not applicable v2 0 yes Arguments Comments Restrictions eae S S Usage Notes Returns information for a UPF power switch Power Aware Simulation User s Manual v10 2c 225 UPF Commands and Reference query pst query pst Support for UPF Standard v1 0 not applicable v2 0 yes Arguments Comments Restrictions eae S S Usage Notes Returns information for any defined PSTs 226 Power Aware Simulation User s Manual v10 2c UPF Commands and Reference query pst state query pst state Support for UPF Standard v1 0 not applicable v2 0 yes Arguments Argument Comments Restrictions pst detailed Usage Notes Returns state information for a PST Power Aware Simulation User s Manual v10 2c 227 UPF Commands and Reference query supply net query supply net Support for UPF Standard v1 0 not applicable v2 0 yes Arguments Argument domain Comments Restrictions detailed Usage Notes Returns state information about a previously created supply net 228 Power Aware Simulation User s Manual v10 2c UPF Commands and Reference query supply port
289. ps catch conditions Signal when the power signal to any power domain gets Corruption corrupted This check will not flag a violation when both the source and sink power domain supplies are off For UPF this check is applicable to control ports of a switch isolation enable signal of an isolation strategy and retention save and restore signals of a retention Strategy Error vsim 8901 MSPA_CTRL_SIG_CRPT Time 240 ns Control Signal tb pg_array 1 is corrupted Current Value x File test upf Line 29 Power Domain PD_TOP Power vopt pa_checks p This check identifies when each power domain is Domain switched on or off Status MSPA PD STATUS INFO Power domain PD is powered down at time 20 MSPA PD STATUS INFO Power domain PD is BIASED down at time 20 CORRUPT ON CHANGE MSPA PD STATUS INFO Power domain PD is BIASED up at time 24 CORRUPT ALL ON ACT 86 Power Aware Simulation User s Manual v10 2c Automatic Checking Dynamic Checking in Power Aware Table 5 6 Miscellaneous Dynamic Checks cont Usage Syntax Description Error Messages Illegal or vopt pa checks pis This check flags a violation if there is an undefined or Undefined illegal state on a PST or supply port State A state is undefined or illegal if the state of nets or ports is not a valid combination as related to the power state table in the UPF file A state on a supply port is undefined if it is not defined
290. r The simulator restores the value previously saved and holds that value until a pa release register event is raised NOTE See Usage Note for Sequence Requirements below event pa release register Power Aware Simulation User s Manual v10 2c 161 Model Construction for Power Aware Simulation Attributes The simulator releases any forced values on a register If the register is combinational the simulator re evaluates the register NOTE See Usage Note for Sequence Requirements below event pa release reeval register The simulator re evaluates a latch at powerup Forces the register to be re evaluated if the latch enable is active when power is restored event pa iso on The simulator is notified that an isolation period has begun Use pa release register event to identify the end of an isolation period The model is responsible for raising the named event when the model of the Power A ware cell is in the appropriate state For instance when the retention signal goes high and the clock is in the proper state in a CLRFF clock low retention flip flop the model should raise the pa store value event When the power goes low the pa corrupt register event should be raised Usage Note for Sequence Requirements When you use a pa restore hold register or pa corrupt register event you must include a corresponding pa release register or pa release reeval register event in the model in the next sequence The release event ca
291. r Aware Simulation User s Manual v10 2c 31 Power Aware Simulation Power Aware Simulation Flows Example vsim SimModel pa pa lib work other vsim args where e SimModel the name of the simulation ready output file generated by vopt e pa invokes simulation in Power Aware mode e pa lib work loads power aware information from library work e other vsim args any other vsim arguments used to control simulation Using the Delayed Optimization Flow This section describes the two step delayed optimization command flow used to perform Power Aware simulation for RTL Gate Level or mixed RTL Gate Level designs This flow consists of the following sequence of operations 1 Compile 2 Simulate In conventional simulation you can perform what is referred to as a two step optimization flow In this flow you do not use the o argument for vopt so that optimization is delayed until you invoke the vsim command at which point it is done implicitly EEE This delayed optimization flow is also supported for Power Aware simulation This flow may be useful in certain cases such as automated scripts that assume only two steps are involved in building and running a simulation Compile Compile your design by running either the vcom for VHDL or the vlog for Verilog command as you would for any VHDL or Verilog SystemVerilog design Noe 5 Do not use
292. r Intent Verbose Dynamic vopt pa genrpt Description Displays the hierarchical path of individual Power Aware elements Includes time and polarity of controls such as control port of a power switch retention save and restore signals isolation enable signal plus Power Domain Status in the form of Power Domain name Strategy name Control signal names Active Sense Current polarity value Report Output report mpsa txt Transcript window no file Static Includes power domains and their supplies power switches retention isolation level shifting strategies and power state tables report upf txt Dynamic and Static Combined dynamic and static reporting Transcript window dynamic report upf txt static Bitwise expanded port data Writes bitwise expanded information for isolated and level shifted ports report upf txt Architecture Lists all information related to the Power Aware architecture in the design report pa txt Design Elements Contains information on power design elements in the design report de txt Isolation Cell Information Dumps hierarchical path of isolation cells placed for a candidate port UPF Power Intent Report Report Output report mspa txt report upf txt Command vopt pa genrptznv v This report file contains information related to the power intent that has been applied on
293. r domain PD in2w elements in2wire Power Aware Waveform Display When using the conventional Wave window display it can be difficult to see the effects of Power Aware simulation For example a zero on a signal may represent normal simulation behavior it may be the result of an isolated port clamped to zero or it could be corruption on a bit type Power Aware Simulation User s Manual v10 2c 113 Visualization of Power Aware Operations Power Aware Waveform Display In particular isolation has been difficult to confirm through simulation that the intent has been met Typically you would want results to show isolation buffer placement and clamping identify the corrupted and clamp values associated with that buffer and confirm that isolation happens at the proper time To do this you can activate Power A ware highlighting in the Wave window which provides visual indicators for the isolation corruption and biasing behavior in your simulation results These waveform indicators provide valuable information by visually distinguishing values caused by Power Aware activity This should help quickly determine if their power intent is correctly applied The visual indicators provided by Power Aware highlighting show the power state of signals viewed in the Wave window Highlighting on waveforms appears during the interval when they are corrupted isolated or biased Figure 7 7 show an example of waveform highlighting where Bias
294. r domain operating at a different voltage Depending upon the relative voltage levels of the two power domains a level shifter may increase or decrease the operating voltage of the signal As with isolation cells level shifters may have separate power supplies that are always on or they may be powered by the primary supplies of the source and sink domains respectively Define level shifters set level shifter interleaver ls in domain PD interleaver applies to inputs location self set level shifter interleaver ls out domain PD interleaver applies to outputs location parent Power Aware Simulation User s Manual v10 2c 327 Supplemental Information Power Aware Verification of ARM Based Designs The UPF commands above specify addition of level shifters for the PD_interleaver power domain in the example in Figure E 1 The first command specifies addition of level shifters for inputs the second command specifies addition of level shifters for outputs Whether level shifters will actually be inserted depends upon the respective supply voltages of the source and sink domains involved State Retention When a power domain is powered down any normal state elements within the power domain will lose their state When the power domain is powered on again the power domain must be brought to a predictable state again This may involve resetting all state elements in the domain or resetting some subset
295. r of PD1 S1 and PD2 S2 Power Aware simulation determines that state PD1_S1 and PD2 S2 cannot co exist as one requires ctrl to be 1 and other requires it to be 0 add power state PD1 state PD1 S1 logic_expr ctrl supply expr VDD1 FULL ON amp amp GND1 FULL ONj add power state PD2 state PD2 S2 logic expr ctrl supply expr VDD1 FULL ON amp amp GND1 FULL ONj Example C 24 Dependency Specified with add power state logic expr Case 3 In this example from logic expr of PD1 S1 PD3_S3 Power Aware simulation determines that state PD1_S1 and PD2 S2 cannot co exist add power state PD1 state PD1 S1 logic expr PD3 PD3 S3 supply expr VDD1 FULL ON amp amp GND1 FULL_ON add power state PD2 state PD2 S2 logic_expr ctrl supply expr VDD1 FULL ON amp amp GND1 FULL ONj add power state PD3 state PD3 S3 logic_expr PD2 PD2_S2 supply expr VDD3 FULL ON amp amp GND3 FULL_ON Example C 25 Dependency Specified with add power state logic expr Case 4 In this example from logic expr of PD1 S1 and PD2 S2 Power Aware simulation determines that state PD1_S1 and PD2 S2 cannot co exist as one requires ctrl to be 1 and other requires it to be 0 add power state PD1 state PD1 S1 logic_expr ctrl 1 supply expr VDD1 FULL ON amp amp GND1
296. rage scope which represents all of the power aware state and transition coverage data inside the related design instance named pa coverageinfo The coverage scope contains information related to supply sets power domains ports nets and power state tables Name conflicts of pa coverageinfo are resolved by adding a counter to the end of the name pa coverageinfo n for the second and any further occurrences Power Aware Coverage Analysis Generating a UCDB File for Power Aware Generating Power Aware Coverage Reports Accessing Coverage Data for Post Simulation Analysis Generating a UCDB File for Power Aware When you save your coverage statistics to a UCDB file you are able to accumulate and analyze the results during post simulation analysis Refer to the Chapter Coverage and Verification Management in the UCDB in the User s Manual for information on using UCDB files Prerequisites Complete a simulation where you have enabled coverage collection as described in the section Power Aware Coverage Collection Procedure Generate the UCDB containing information about all coverage for the whole design coverage save lt name gt ucdb Alternatively if you want to generate a UCDB containing coverage data with only your power aware information use the following command adding pa coverage save pa lt name gt ucdb Generating Power Aware Coverage Reports You can generate several formats of report to anal
297. raphics grants to Customer a temporary nontransferable nonexclusive license for experimental use to test and evaluate the Beta Code without charge for a limited period of time specified by Mentor Graphics This grant and Customer s use of the Beta Code shall not be construed as marketing or offering to sell a license to the Beta Code which Mentor Graphics may choose not to release commercially in any form 4 2 If Mentor Graphics authorizes Customer to use the Beta Code Customer agrees to evaluate and test the Beta Code under normal conditions as directed by Mentor Graphics Customer will contact Mentor Graphics periodically during Customer s use of the Beta Code to discuss any malfunctions or suggested improvements Upon completion of Customer s evaluation and testing Customer will send to Mentor Graphics a written evaluation of the Beta Code including its strengths weaknesses and recommended improvements 4 3 Customer agrees to maintain Beta Code in confidence and shall restrict access to the Beta Code including the methods and concepts utilized therein solely to those employees and Customer location s authorized by Mentor Graphics to perform beta testing Customer agrees that any written evaluations and all inventions product improvements modifications or developments that Mentor Graphics conceived or made during or subsequent to this Agreement including those based partly or wholly on Customer s feedback will be the exclusive property of Me
298. re Simulation User s Manual v10 2c Generation coverage report pa details Example Excerpt Power Aware Coverage Power Aware Coverage Report Reference PA State Machine Instance tb pa coverageinfo MyPowerStateTable UPF Object PST tb MyPowerStateTable PA State Coverage Enabled Coverage Active Hits Misses Covered States 5 0 5 0 0 Transitions 25 0 25 0 0 az2zzzl2zczzzlzzzlzzczzlzzzczzccz czc c cz c pA State Machine Detailss 2222 2222 2 2 2 2 2 2 2 2 2 z2 PA State Coverage for PA State Machine instance tb pa coverageinfo MyPowerStateTable PSM ID MyPowerStateTable pst state info state var Current State Object MyPowerStateTable pst Line State Name Value 118 Complete on 5 118 Hibernate 4 118 Sleep 3 118 Reboot alias 2 118 Reboot I Uncovered States State Complete_on Hibernate Sleep Reboot_alias Reboot Uncovered Transitions state_info state_var Line Trans_ID Transition 124 7 Complete_on gt Complete_on 123 8 Complete_on gt Hibernate 122 9 Complete_on gt Sleep 121 10 Complete on Reboot alias 120 T1 Complete on Reboot 124 13 Hibernate Complete on 123 14 Hibernate Hibernate 123 32 Reboot Hibernate 122 33 Reboot Sleep 121 34 Reboot Reboot alias 120 35 Reboot Reboot Excluded States State Exclusion undefined E hit Excluded Transitions Line Trans ID Transition Exclusion 118 0 undefined undefined E hit
299. re simulation There are a few interdependent Power A ware state machines For example a PST state machine runs in accordance to supply port net Power Aware state machines Visualizing Power Aware State Machines Dynamic visualization with debugging capabilities of power states is useful for verification of power intent 116 Power Aware Simulation User s Manual v10 2c Visualization of Power Aware Operations Power State and Transition Display Prerequisites Your UPF file contains power state information add power state create pst add port state and or add pst state UPF commands vsim command includes coverage option Process 1 Begin your simulation 2 Analyze state machines from your design in the Power Aware State Machine List Window 3 View bubble diagrams of individual state machines in the Power Aware State Machine Viewer Window Power Aware State Machine List Window Use this window to view a list of power aware state machines after beginning a Power Aware simulation This window lists all of the Power Aware State Machines in the design with the hierarchical path of their creation For example if a PST has been created in dut top then this PST will be visible in scope dut top pa coverageinfo This window is very similar to the FSM List Window Accessing Access the window using either of the following e View gt PA State Machine List Command view powerstatelist Power Aware Simulation Us
300. re the net name arguments to ports are present in the target instance scope or the parent scope If you want to associate an object present in the active UPF scope then prefix net name with For example PD mid1 was created in scope therefore PD midl iso PD midl isolation signal is directly accessible If something is created in active scope such as if you are not sure if it would be present in scope of the target instance you should include the prefix as is done for ISO SS power and ISO SS ground Power Aware Simulation User s Manual v10 2c 187 UPF Commands and Reference connect logic net connect logic net Support for UPF Standard v1 0 no v2 0 yes Arguments Comments Restrictions Pes Usage Notes Connects a logic net to a logic port 188 Power Aware Simulation User s Manual v10 2c connect supply net Support for UPF Standard v1 0 yes partial v2 0 yes partial Arguments Argument ports UPF Commands and Reference connect supply net Comments Restrictions pg type Using an element list is not supported vct pins cells domain rail connection Usage Notes Refer to UPF Supply Connections Power Aware Simulation User s Manual v10 2c Not supported 189 UPF Commands and Reference connect supply set connect supply set Support for UPF Standard v1 0 no v2 0 yes partial Argument
301. rectly in a given mode Corruption refers to the situation where the value of a signal becomes unpredictable when the power supply for the element driving that signal is disconnected changes to OFF or drops below some threshold Corruption of a signal is represented by assigning a particular value to the signal The corruption value depends upon the type of the signal and is user definable Corruption is typically applied to the drivers of signals and will propagate to all sinks of the signal that have not been isolated from their source 20 Power Aware Simulation User s Manual v10 2c Concepts for Using Power Aware Simulation Power Aware Modeling When a design instance is turned off every sequential element within the powered down instance and every signal driven from within the powered down instance is corrupted As long as the power remains off no additional activity takes place within the powered down instance all processes within the powered down instance become inactive regardless of their original sensitivity list Events that were scheduled before the power was turned off and whose target is inside a powered down instance have no effect When a design instance is turned on restored corruption of sequential elements and signals within the powered down element ends Continuous assignments once again become sensitive to changes to their right hand side expressions and other combinational processes such as an always comb block i
302. refinement of power intent exclude_elements Usage Notes For the elements argument e You can specify a hierarchical path within the active scope in the list of design elements e You can specify bit or part selects of one or more signals However complex data types of SystemVerilog such as structs are not supported e According to UPF only hierarchical path of instances can be accepted inside elements element list This has been extended under the above mentioned switch to allow generate hierarchy to be specified in the extent of a power domain This feature is only available for corruption and retention and not for isolation and level shifting This implies that if a generate block is added in the extent of a power domain it will only show corruption and if it contains a retention register retention behavior as well However there will not be any level shifters isolation cells placed at the generate boundary create power domain PD forgen elements forgen 1 Examples Results in an effective element list of topl top2 create power domain PD1 elements sig 2 sig1 2 11 200 Power Aware Simulation User s Manual v10 2c UPF Commands and Reference create power domain create power domain PD elements topi create power domain PD elements top2 update Defines automatic connection semantics on supply sets Supply nets of supply sets are automatically connected to the supply po
303. report pa txt Command vopt pa_genrpt pa This report contains information related to Power Aware architecture that results from the power intent defined in the UPF file as applied to the design being simulated The content and structure of this report is same as that of report upf txt and includes all objects that are either added or modified by applying power intent to the design This report file contains information regarding the following Power Domain including supplies e Power Switch including supplies Retention Strategy including supplies Isolation Strategy including supplies Level Shifter Strategy Power State Tables PSTs Power Domain The power domains are listed under the Power Domain section of the report This section contains the name of the power domain and the reference to the UPF file that contains the UPF command that created the power domain All the other characteristics are listed in the following lines shifted by a tab space and starting with the property name such as Creation Scope Primary Supplies Retention Strategy 54 Power Aware Simulation User s Manual v10 2c Power Aware Reports UPF Reports UPF Command for Power Domain create power domain pd include scope Report File Sections and Subheadings 1 Power Domain pd File src supply1 prefix test upf 7 2 Creation Scope tb top 3 Primary Supplies power tb top pd pwr ground tb top G pd net 4 Supply Set hand
304. rguments Argument Comments Restrictions direction The value of inout is not supported domain Power Aware Simulation User s Manual v10 2c 205 UPF Commands and Reference create supply set create supply set Support for UPF Standard v1 0 no v2 0 yes Arguments Argument function Comments Restrictions reference gnd This option is accepted during parsing however it has no impact on simulation update 206 Power Aware Simulation User s Manual v10 2c UPF Commands and Reference create upf2hdl vct create upf2hdl vct Support for UPF Standard v1 0 yes v2 0 yes Arguments Argument Comments Restrictions hdl type User defined types not supported table Usage Notes Defines a value conversion table VCT for the two LSBs of the supply state type state value when that value is propagated from a UPF supply net into a logic port defined in an HDL Power Aware Simulation User s Manual v10 2c 207 UPF Commands and Reference find objects find objects Support for UPF Standard v1 0 no v2 0 yes Arguments Argument Comments Restrictions pattern object type direction transitive regexp exact ignore case non leaf leaf only not supported Usage Notes Use this command to find logical hierarchy objects within a scope Specifically use it to search for design elements nets or ports that are de
305. riables inferred registers and latches and to the outputs of a block The corruption of inferred registers and latches and outputs results in a change in the current value of these signal objects in the simulation to the corruption value No events are propagated as a result in these changes in values That is corruption shall not result in the activation of any processes sensitive to the state variables if signals or outputs that are corrupted Upon restoration of a retained value for inferred registers and latches the current value of these signal objects will be changed and events are propagated to ensure that the restored state is propagated to outputs Only inferred registers and latches may have retained values restored The restored values are specified by the Power Aware model mapped by the PCF to the inferred 314 Power Aware Simulation User s Manual v10 2c Power Configuration File Reference PCF Syntax and Contents registers and latches For more information refer to Model Construction for Power Aware Simulation Voltage Domains Voltage domains may be specified along with power islands There are 2 key pieces of information for a voltage domain Whether power is on or off This information is already specified by the power control statement The voltage level or range of levels under which the domain operates Voltage domain statements are optional Whereas power control statements specify power islands and retention
306. roceed with the simulation normally as the test bench triggers power down signals for various power islands while save and restore occur as required The purpose of the verification is to ensure the design functions correctly within the dynamic context of power islands being turned off and on PCF Syntax and Contents This section describes the syntax and semantics of the PCF using Backus Naur Format BNF grammar to specify the syntax Basic PCF Statement Types The PCF consists of header and power or context statements The header statement must be the first statement in the PCF Power and context statements can be intermixed Context statements apply to all statements that follow the context statement unless and until overridden by a subsequent context statement 300 Power Aware Simulation User s Manual v10 2c Power Configuration File Reference PCF Syntax and Contents Statement Termination You should terminate all statements with a semicolon However for backward compatibility with earlier PCF formats a statement may be terminated by a new line CRLF When using a new line to terminate a statement use the backslash V character to indicate line continuation instead of termination immediately prior to the new line Only one form of statement termination can be used in a simulation session stmt end CRLF Header Statement The header statement is mandatory for PCF version 2 0 or later It is an error if
307. rt for UPF Standard v1 0 yes v2 0 yes Arguments Argument Comments Restrictions pins related power pin related ground pin Usage Notes Questa SIM assumes the driver receiver logic supply to be the same as specified related supplies that is corruption isolation and level shifting behavior is in accordance with the specified related supplies When the supply specified using set pin related supply using related power pin or related ground pin is a different supply than that of actual driver or receiver logic Power Aware simulation gives a vopt error message vopt 9814 You can use the warning argument of vopt to change the severity of this message to a warning so that simulation may continue vopt warning 9814 Refer to Power Aware Messages for more information on changing the level of message severity 246 Power Aware Simulation User s Manual v10 2c UPF Commands and Reference set port attributes set port attributes Support for UPF Standard v1 0 no v2 0 yes partial Arguments Argument Comments Restrictions ports This option takes precedence over any other set port attributes with any other option such as elements domains or model Z domains Z lt elements Complex data types of SystemVerilog such as structs are not supported applies_to model attribute clamp_value sink off clamp source off clamp
308. rt isolation strategies as Not Analyzed Table 5 7 shows a quick reference comparison of static and dynamic checks Usage Notes for Static Checking The pa_checks argument of the vopt command has numerous possible values that you can assign to enable either dynamic or static checking for Power Aware simulation Fora quick listing of all values refer to Table A 1 For additional reference information refer to the vopt command in the ModelSim Reference Manual Fora listing of static and dynamic checks according to elements defined for a given power domain refer to Table 5 7 To specify more than one value use the plus operator between values for example vopt pa_checks sni sdi Related Topics Voltage Level Shifting Multi Voltage Modeling Isolation Analysis Debugging Static Checks You can perform debugging on static checking for isolation or level shifters by using the vopt pa dbgstatic command The available values determine the debugging behavior performed as described below e pa dbgstatic rsn Power Aware simulation appends information at the end of a report following the phrase Possible reason to help determine the cause of the check Report file example report static txt Inferred type Not inserted count 1 Source port tb TOP bot4 bot5 outl bot connected mask 1 LowConn Domain pd bot gt Sink port tb TOP bot4 outl1 bot connected mask 0001 HighC
309. rts is not applicable with message 8918 Actions for Power Aware Checks Use the following options to specify the action to be taken on the selected power aware checks e enable or disable Use these options to enable or disable a particular power aware check which was selected using the selection and fine control options e severity note warning error fatal gt Use this option to change default severity of a selected check e stopafter number Use this option to specify a maximum count If a selected check exceeds this specified count then simulation will stop glitch window duration Use this option to specify the maximum allowed time window of a glitch It is applicable for glitch checks pa_checks ugc only If specified with any other checks it will be ignored Examples The following commands show several usage examples of the pa msg command Disable all isolation functionality and clamp value checks for isolation strategy iso mid belonging to power domain tb TOP midl1 PD mid pa msg disable pa_checks ifc icp scope tb TOP mid1 domain PD mid strategy iso mid In this command if action is to be taken only for Port tb TOP mid1 P3 then you would specify pa msg disable pa_checks ifc icp scope tb TOP mid1 domain PD mid strategy iso mid ports P3 140 Power Aware Simulation User s Manual v10 2c Power Aware Commands and Options Power Aware Messages Disable all power awar
310. rts of design elements based on the purpose of the supply set in a given domain or strategy context and the function that a supply net performs in the context of supply set create power domain PD elements topi create power domain PD elements top2 update Power Aware Simulation User s Manual v10 2c 201 UPF Commands and Reference create power switch create power switch Support for UPF Standard v1 0 yes partial v2 0 yes Arguments Argument domain Comments Restrictions output supply port input supply port control port on state off state supply set on partial state When the supply set simstate is anything other than NORMAL the state of the output supply port of a switch is OFF and the acknowledge ports are corrupted Note that this differs from UPF v2 0 which states that the state of the output supply port of a switch is UNDETERMINED ack port ack delay error state Usage Notes The following is not supported e In order to model the definition of a power switch Power A ware simulation currently treats UNDETERMINED state as OFF state for simulation This implies that when the state of supply setis NOT NORMAL the state on the output supply port will be OFF instead of UNDETERMINED state 202 Power Aware Simulation User s Manual v10 2c UPF Commands and Reference create pst create pst Support for UPF Standard v1 0
311. rview of information about all power aware coverage metrics including state and transition coverage and power aware check coverage Generation coverage report pa Example Coverage Report Summary Data by PA state machine instance Total Coverage By Instance filtered view 37 8 PA State Machine Instance tb CPU1 pa coverageinfo PD RAM sw out sw PD RAM UPF Object PORT tb CPU1 PD RAM sw out sw PD RAM Enabled Coverage Active Hits Misses Covered States 4 0 4 0 0 Transitions 16 0 16 0 0 PA State Machine Instance tb pa coverageinfo out sw PD ALU UPF Object PORT tb out sw PD ALU Enabled Coverage Active Hits Misses Covered States 4 0 4 0 0 Transitions 16 0 16 0 0 PA State Machine Instance tb pa coverageinfo PD ALU sw out sw PD ALU UPF Object PORT tb PD ALU sw out sw PD ALU Enabled Coverage Active Hits Misses Covered States 4 2 2 50 0 Transitions 16 2 14 12 5 PA State Machine Instance tb pa coverageinfo MyPowerStateTable UPF Object PST tb MyPowerStateTable Enabled Coverage Active Hits Misses Covered States 5 0 5 0 0 Transitions 25 0 25 0 0 TOTAL POWER STATE COVERAGE 43 7 POWER STATE COVERAGE TYPES 12 POWER AWARE CHECKs COVERAGE SUMMARY NEVER FAILED 75 0 ASSERTIONS 24 Power Aware Coverage Detailed Report This report provides detailed information about the state and transition coverage metrics followed by details about the power aware check coverage metrics 100 Power Awa
312. s Power gating is one of the most common active power management techniques Switching off the power to a subsystem when it is not in use eliminates the leakage current in that subsystem when it is powered down and hence the overall leakage power dissipation through that subsystem is reduced However this technique also results in loss of state in the subsystem when it is switched off Also the outputs of a power domain can float to unpredictable values when they are powered down Another common technique is the use of different supply voltage levels for different subsystems A subsystem that has a higher voltage supply can change state more quickly and therefore operate with higher performance at the expense of higher static leakage and dynamic power A subsystem with a lower voltage supply cannot change state as quickly and consequently operates with lower performance but also with less static leakage and dynamic power This technique allows designers to minimize static leakage in areas where higher performance is not required Multiple voltage supplies can also be used for a single subsystem for example by enabling it to dynamically switch between a higher voltage supply and a lower voltage supply This allows the system to select higher performance for that subsystem when necessary but minimize static leakage when high performance is not required Multi voltage and power gating techniques can be combined to give a range of power performan
313. s Argument Comments Restrictions connect elements exclude elements Not supported transitive Not supported Usage Notes Defines automatic connection semantics on supply sets Supply nets of supply sets are automatically connected to the supply ports of design elements based on the purpose of the supply set in a given domain or strategy context and the function that a supply net performs in the context of supply set Restrictions e Supply sets specified in strategy context are not automatically connected to design elements e Supply nets in supply sets functioning as predefined supply set functions are not automatically connected according to their predefined function You must specify explicit automatic connections Examples connect supply set PD primary connect power primary power elements TOP connect supply set PD ISO isolation supply set connect iso power primary power connect iso ground primary ground connect supply set PD RET retention supply set connect ret backup power backup power connect switchtable supply primary power 190 Power Aware Simulation User s Manual v10 2c UPF Commands and Reference create composite domain create composite domain Support for UPF Standard v1 0 no v2 0 yes Arguments Argument Comments Restrictions subdomains supply update Usage Notes A composite power domain is a set of
314. s top mid find objects top pattern object type inst transitive TRUE Returns top mid top genl bot find objects top genl pattern object type inst Returns Invalid Scope Error o Running with vopt pa upfextensions genblk find objects top pattern object type inst Returns top mid top genl find objects top pattern object type inst transitive TRUE Returns top mid top genl top gen1 bot find objects top genl pattern object type inst Returns top genl bot Power Aware Simulation User s Manual v10 2c 209 UPF Commands and Reference load simstate behavior load simstate behavior Support for UPF Standard v1 0 no v2 0 yes Arguments Comments Restrictions library name Name of a ModelSim library Required file Name of a file containing set simstate behavior commands Usage Notes The load simstate behavior command loads a UPF file containing the defaults of simstate behavior for a library This file consists solely of set simstate behavior commands which are applied to the models in the library specified by the library name argument You can load only one file per occurrence of this command Examples Example C 1 Load Files With load simstate behavior Commands The following example shows how to use the load simstate behavior command to load simstate semantics for 1ib1 and 1ib2 main upf upf version 2 0 set scope tb topl load simstate behavior lib1 file loadl u
315. s an explicit cell instance that functions as an isolation cell The UPF file includes a set isolation instance command that identifies this explicit instance as an isolation cell In this case e No isolation needs to be added Power Aware will not insert an additional isolation cell Power Aware will not modify the explicit isolation cell that is present it is assumed that the user provided isolation cell does what it is supposed to do Method 2 Isolation needs to be added In this case you use the set isolation command to provide an isolation strategy without the instance option Power Aware simulation then implicitly inserts an isolation cell on any port that satisfies all of the following Matches the criteria defined in the isolation strategy Requires isolation because the power state table indicates that the two power domains on either side of the port can be ON OFF or OFF ON respectively Does not already have an explicit isolation cell present and identified per Method 1 By default if Power Aware simulation does insert an isolation cell Power Aware simulation will use a built in behavioral model for isolation However you can cause the simulation to insert a different model when required by using the map isolation cell UPF command to identify the isolation model to be used WNote LLL To prevent a redundant isolation cell from being inserted on a port use the set isolation instance command to iden
316. s and Variables Comments A comment may appear anywhere on the line The start of a comment is denoted by The comment extends to the end of the line comment any text CRLF Regular Expressions and Variables In order to make it easy to group instances signals and labels within instances regular expressions are supported The common subset of syntax and rules of Perl and Tcl are supported More specifically the following sets of meta characters are supported e Single Character Matches or for example ab c a b any character c a bc d abd or acd e Multiple Character Matches or n m for example ab c a zero or more b s c ab 2 4 c a two to four b s c The only difference is that the regular expression will be delimited by quotation marks Examples The following matches all the instances DFF_ 0 to DFF_ 99 within the top pdll instance POWER PDO top pd11 DFF 0 9 1 2 top global vdd1l amp top vdl local va d 11 The following matches all instances DFF 0 to DFF_99 for any sub instance with a name beginning with pd2 under top POWER PD2 top pd2 DFF 0 9 1 2 top global vdd1l amp top vdl local vdd 12 Rule Precedence When more than one rule applies to a given power element the rule defined at the lowest hierarchical level takes precedence over the rules defined at higher hierarchical level This
317. s combinatorial logic that belong to the power domain During simulation they get corrupted only when power domain is switched off o USER DEFINED For any user defined retention models the names of the model will be printed Line 6 After the consolidated counts all the power domains are then listed in the following format PD NAME sub total Instance hierarchial path The instance hierarchical paths indicate those instances that contain objects affected by the current power domain Line 8 The individual CELL TYPES for that power domain Power Aware Simulation User s Manual v10 2c Power Aware Reports UPF Reports Lines 9 10 The hierarchical paths of objects belonging to those CELL TYPEs are then listed with the individual count These lines only appear in verbose mode pa genrpt v Example of UPF File and Power Intent Report Example 4 1 shows an excerpt from a UPF specification file that defines power domains supply ports switching behavior retention strategy and isolation strategy Example 4 2 shows an excerpt of a power intent report Example 4 1 UPF File Excerpt upf version 1 0 set scope tb create power domain pd aon include scope create supply port vdd port domain pd aon create supply port gnd port domain pd aon create supply net vdd net domain pd aon create supply net gnd net domain pd aon connect supply net vdd net ports vdd port connect sup
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319. s the name of the power switch and the reference to the UPF source file Power Aware Simulation User s Manual v10 2c 55 Power Aware Reports UPF Reports where that switch was created All the output and input supply ports are listed followed by control ports and the switch states mentioned in the UPF file UPF Command for Power Switch create power switch pd sw domain pd output supply port out sw pd pd pwr j input supply port in sw pd1 V pd netl input supply port in sw pd2 V pd net2 control port ctrl sw pd1l pwrl control port ctrl sw pd2 pwr2 on state normal workingl in sw pd1 ctrl sw pd1 amp amp ctrl_sw_pd2 on state normal working2 in sw pd2 ctrl sw pd2 amp amp ctrl sw pd1 off state off state ctrl sw pd1 amp amp ctrl sw pd2 Peak N Report File Sections and Subheadings 1 Power Switch pd_sw File test upf 35 2 Output Supply port out sw pd tb top pd pwr 3 Input Supply ports 1 in sw pd1 tb top V pd netl 2 in sw pd2 tb top V pd net2 4 Control Ports 1 ctrl sw pdl tb top pwrl 2 ctrl sw pa2 tb top pwr2 5 Switch States 1 normal working2 ON ctrl sw pd2 amp amp ctrl sw pd1 2 normal working1 ON ctrl sw pd1 amp amp ctrl sw pd2 3 off state OFF ctrl sw pdl amp amp ctrl sw pa32 6 Switch Instances 1 tb dut SW INST 1 2 tb dut SW INST 2 Where the sections contain the following informa
320. sage Notes When source and sink are specified a port is included if it has a source as specified or a sink as specified For a selected output port on the interface of a domain for which this strategy is specified level shifting is performed only on the subset of the fanout that drives an element in the domain specified by the sink option For a selected input port on the interface of a domain for which this strategy is specified level shifting is performed only on the subset of the fanin driven by an element in the domain specified by the source option Notes about location 242 Power Aware Simulation User s Manual v10 2c UPF Commands and Reference set partial on translation set partial on translation Support for UPF Standard v1 0 no v2 0 yes Arguments Argument Comments Restrictions OFF FULL ON OFF defines a default translation from PARTIAL ON to OFF when evaluating the power state of supply sets and power domains default FULL ON defines a default translation from PARTIAL ON to FULL ON when evaluating the power state of supply sets and power domains full on tools Defines a list of tools products for which translation of PARTIAL ON to FULL ON take place off tools Defines a list of tools for which translation of PARTIAL ON to OFF take place Usage Notes The set partial on translation command defines the translation of PARTIAL ON to FULL ON or OFF for purposes of eva
321. sensitive and two different signals are used for save and restore the Dual control edge sensitive model is selected Level sensitive Retention Model Protocol Example The level sensitive model accurately duplicates the behavior of a level sensitive Liberty cell Based on the save restore level the retention register switches between normal and retention operations as follows When save is active normal register behavior occurs a balloon latch keeps latching the output of the register When save is de asserted a balloon latch on the register output saves the register value When restore is active the saved value is retained When restore is de asserted the retained value is loaded into the register again The save or restore events are defined as trailing edge of the level sensitive event So for this command the register output is saved when save restore goes from high to low the save event and the retained value is transferred to the register output at the low to high the restore event transition of the save restore signal The following is an example of the protocol followed by level sensitive model In the save phase normal register operation happens D Q at clock edges At the save event defined above the register output gets latched In the restore phase D has no effect on Q so Q gets the retained value At the restore event normal operation resumes and Q will get new value of D from next active edge of clo
322. set on the power switch in UPF 2 0 and was always on in UPF 1 0 You can control this behavior with the ackportbehavior argument to the pa enable or pa disable options Lower boundary isolation support Refer to the section set isolation for additional information You can control this behavior with the lowerboundary argument to the vopt pa enable or pa disable switches Supported UPF Commands This section provides reference information on the UPF commands that you can use with Power Aware simulation These commands are listed in Table C 1 Note 172 Note that some commands in Table C 1 have arguments that are not supported and some commands or arguments are supported only if the UPF file contains the command upf version 2 0 Power Aware Simulation User s Manual v10 2c UPF Commands and Reference Supported UPF Commands Table C 1 lists UPF commands that are not supported for this release of Power Aware simulation Table C 1 List of Supported UPF Commands UPF Support Command add domain elements 1 0 2 0 Description Adds design elements to the power domain add port state Adds state information to a supply port which can represent off chip supply sources that are not driven by the test bench add power state Attributes one or more power states to a supply set or a power domain add pst state Specifies a power state table PST to define states on a supply net a
323. sible for the specification of these models to match the behavior of their Power Aware cell technology Capturing the Power Aware behavior in standard Verilog gives the vendor the flexibility to add new cell types and behaviors without creating additional simulation requirements for those cells Foundries providing Power Aware models have control over the protection of their intellectual property IP Basic Model Structure Model vendors can implement the Verilog model in any style The cells communicate important events to the simulator using named events Power Aware verification defines a standard set of Power Aware Simulation User s Manual v10 2c 159 Model Construction for Power Aware Simulation Named Events in Power Aware named event identifiers that are used in the model Each named event corresponds to a particular action to be taken by the simulator The simulator communicates with the model by connecting the model to the clock reset power on off and power retention signals Through events on these signals the model determines when the Power Aware events are triggered notifying the simulator that the normal RTL behavior must be modified to reflect power control network activity Because the only inputs are single bit inputs and the only output to the simulator is the triggering of named events the models at the RTL or higher abstraction level are general purpose and can work with inferred registers and latches o
324. simulation for both Register Transfer Level RTL Gate Level GL and mixed RTL GL designs Power aware simulation involves adding power intent to the design under test as appropriate For an RTL design with no power management content this may involve inferring power domains retention cells isolation cells level shifters and the power supply network from the UPF power intent specification For a GL design that has been created by a synthesis tool that reads and implements UPF some of the power management content may already be present and therefore less of the power management content may need to be inferred from the UPF specification Application of power intent to the design includes addition of functionality to model the corruption of signal values when insufficient power is provided for normal operation It also includes addition of functionality to model the saving and restoring of system state that will be performed by state retention elements in the power managed system Addition of this functionality is done automatically as part of the preparation for power aware simulation It is also possible for you to construct custom models for these behaviors Refer to 6 Appendix B Model Construction for Power Aware Simulation for more information on Power Aware modeling Modeling Corruption Corruption refers to the change of a signal from its current value to a corrupted value when a power domain is insufficiently powered to operate cor
325. sink domains can be both powered on at the same time and the difference between the maximum voltages exceeds a certain threshold Level shifting is dynamically required for a power domain crossing if the source and sink domains are both powered on at the same time and the difference between the maximum voltages exceeds a certain threshold The direction of a level shifter must be Power Aware Simulation User s Manual v10 2c 69 Automatic Checking Static Checking in Power Aware high to low if the maximum voltage powering the source domain is higher than the maximum voltage powering the sink domain low to high if the maximum voltage powering the source domain is ower than the maximum voltage powering the sink domain Isolation Checking An isolation cell is present in the design description if a set isolation instance command in your UPF file identifies that cell in the design description as an isolation cell An isolation cell is implied by an isolation strategy if a set isolation command exists with the appropriate options for the appropriate power domain e Isolation is statically required for a power domain crossing if the source domain can be off when the sink domain is on Isolation is dynamically required for a power domain crossing if the source domain is off when the sink domain is on Static Checking in Power Aware The pa checks argument enables static checking to validate the behavior of power intent a
326. ssociate supply set bind checker Associates a supply set or supply set ref to a power domain power switch or strategy supply set handle Inserts a checker module into your design without modifying the design code or introducing functional changes connect logic net connect supply net Partial Partial Connects a logic net to a logic port Connects a supply net to the specified ports connect supply set create composite domain N A Partial Defines automatic connection semantics on supply sets Defines a set of domains create hdl2upf vct create logic net Defines a value conversion table V CT that can be used in converting HDL logic values into state type values Creates a net reflecting the same value as a port that you connect to it using the connect logic net command create logic port create power domain Partial Power Aware Simulation User s Manual v10 2c Creates a logic port on the active scope Defines a set of design elements that share a common primary supply set can specify additional supply sets used within the domain and any isolation level shifting or retention strategies 173 UPF Commands and Reference Supported UPF Commands Table C 1 List of Supported UPF Commands UPF Support Command create power switch 1 0 Partial 2 0 Description Defines an instance of a power switch in the active scope or the scope of the d
327. subdomains of a composite domain The following arguments are not supported they can also refer to composite domain o source domain name o sink domain name The following are also in effect o Set level shifter domain composite domain cannot use the elements exclude elements or instance arguments This may cause conflict in the subdomains o Theelements can be individually updated for each strategy in all the sub power domains Power Aware Simulation User s Manual v10 2c 195 UPF Commands and Reference create composite domain o If any error occurred in transitively applying this command on a subdomain it will not be applied to that subdomain Usage and error messages for incorrectly specifying elements or instance arguments are similar to those for set isolation set port attributes If a composite domain is included in the domains argument of this command it will be replaced by its sub power domains listed transitively Example create composite domain cd subdomains pdl pd2 pd3 supply primary pdsub ss set port attributes domains cd applies to inputs attribute pin type data in This is equivalent to set port attributes domains pdl pd2 pd3 applies to inputs attribute pin type data in set retention This command will be applied to all the subdomains of a composite domain The following shall also apply o Set isolation domain composite domain cannot have elements or exclude eleme
328. suppl create suppl ly por ly por ly por y net t cr ct p2 p3 elements pl domain PD TOP domain PD TOP domain PD TOP resol net domain PD TOP topi include scope direction in direction in direction in resolve one hot HEHHEHE Supply Net Resolution connect supply net resol net ports pl connect supply net resol net ports p2 connect supply net resol net ports p3 Error vsim 8928 MSPA RSLV ONE HOT Time 20 ns More than one driver is ON for one hot supply net tb resol net Drivers are tb pl 0 uV OFF tb p2 5 uV ON tb p3 10 uV ON d Error vsim 8927 MSPA RSLV PARALLEL Time 15 ns Different voltages driven by ON drivers of parallel supply net tb resol net se OSE OE 288 Drivers are tb p1 tb p2 tb p3 0 uV OFF 5 uV ON 10 uv ON Power Aware Simulation User s Manual v10 2c UPF Commands and Reference Supply Nets Defining Isolation Isolation is used to separate signals that originate in a design element with power off from a part of the design that has power on and that can still read the signals from the powered down element A particular domain may be powered off while another domain is operating in normal mode There are two methods for defining an isolation cell Method 1 Isolation is already explicitly present In this case the design in either a RTL or a GL netlist contain
329. system functionality the power control logic that ultimately drives the control inputs to the power management architecture which may be implemented in hardware or software or a combination thereof All three of these aspects need to be verified to ensure that the design will work properly under active power management Ideally such verification should be done at the RTL stage This enables verification of the active power management capability much more efficiently than would be possible at the gate level which in turn allows more time for consideration of alternative power management architectures and simplifies debugging Power Management Techniques Several power management techniques are used to minimize power dissipation clock gating power gating voltage scaling and body biasing are four of them Clock gating disables the 320 Power Aware Simulation User s Manual v10 2c Supplemental Information Power Aware Verification of ARM Based Designs clock of an unused device to eliminate dynamic power consumption by the clock tree Power gating uses a current switch to cut off a circuit from its power supply rails during standby mode to eliminate static leakage when the circuit is not in use Voltage scaling changes the voltage and clock frequency to match the performance required for a given operation so as to minimize leakage Body biasing changes the threshold voltage to reduce leakage current at the expense of slower switching time
330. t args where design top the name of the top level module of the test bench pa upf compile upf the name of the UPF file written with respect to the design top module pa lib work the name of the destination library pa loadlibertydb the name of the Liberty database from which to load information Using Liberty Files Directly Liberty files can also be read in directly when processing UPF power intent without creating a database first 36 Power Aware Simulation User s Manual v10 2c Power Aware Simulation PDU Based Simulation The following command vopt design top pa upf compile upf pa lib work pa libertyfiles a lib b lib analyzes a lib and b lib files and creates an internal database for these libraries This internal database is used for Liberty data in a Power Aware analysis the internal database is deleted at the end of the vopt run Updating a Liberty Database If a Liberty database already exists for a Liberty library you can replace the existing database with a new one using the pa libertyupdate argument Assuming that a Liberty database has been created already at location home user libdbs LVT for Liberty files a lib b lib the command vopt pa libertyfiles a lib b lib pa dumplibertydb home user libdbs LVT pa libertyupdate which analyzes a lib and b libb files again and overwrites the previous database with a new one This can be used when a lib file has been edited to correct an error and
331. t argument all data is generated e To specify more than one reporting value for pa genrpt use the plus sign operator between values For example vopt pa_genrpt nv us de When you execute the pa report command to write out the reports the default location is the current working directory To change the location where report files are saved add the following argument to your vopt command vopt pa reportdir lt pathname gt UPF Reports If you are using a UPF file for your Power Aware analysis you can generate the data for the following reports by specifying values for vopt pa genrpt described in Table 4 1 e UPF Power Intent Report report mpsa txt UPF Static Report report upf txt e Static Checking UPF Reports report static txt report nretsyncff txt Dynamic UPF Report displayed in transcript window Architecture Report report pa txt Design Elements Report report de txt Table 4 1 Generating UPF Reports for Power Aware Report Type vopt Description Report Output pa genrpt Power Intent Displays a count of the Power Aware report mpsa txt Non verbose elements in the design with respect to default power domains along with additional information on power intent This is the default if you do not specify nv or v 46 Power Aware Simulation User s Manual v10 2c Power Aware Reports UPF Reports Table 4 1 Generating UPF Reports for Power Aware cont Report Type Powe
332. t as 81 0000000001 Note that the output of a switch in UPF whose control port has been driven to the OFF state is always OuV and a 0 supply state reported by Power Aware simulation as 0 0000000000 Changing the Default Supply State Values for VHDL Models When you connect a supply net to an HDL port to extend the UPF supply network directly to an HDL model Power Aware simulation connects the net to the HDL port and converts the enumerated supply state to the HDL port type By default Power Aware simulation performs the following conversion supply state type state supply state type state ON gt HDL bit type 1 b1 OFF gt HDL bit type 1 b0 However for VHDL models in the design such as memory models this results in a logical 1 on ground and VSS nets To change this default conversion you need to define a UPF to VHDL Value Conversion Table VCT from that converts UPF supply states to their corresponding VHDL bit values You then need to apply the conversion when connecting the supply net in the UPF file 1 Define a Value Change Table for UPF to VHDL conversion by doing either of the following Use the create upf2hdl vct command to create a VCT that defines the conversion For example create_upf2hdl_vct upf2vhdl_vss hdl_type vhdl std_logic table OFF 1 ON 0 PARTIAL_ON X where upf2vhdl_vss is the name of the table hdl_type specifies VHDL std_logic for the data type and ta
333. t name argument to ports The ports argument accepts the following symbolic references for the net name argument isolation signal scope name pd name iso stratgy name isolation signal isolation supply set scope name pd name iso stratgy name isolation supply set isolation power net scope name pd name iso stratgy name isolation power net isolation ground net scope name pd name iso stratgy name isolation ground net e supply set function name ISO SS primary Power Aware Simulation User s Manual v10 2c 185 UPF Commands and Reference bind checker save signal of retention strategies scope name pd name retention stratgy name save signal restore signal of retention strategies scope name pd name retention stratgy name restore signal retention supply set scope name pd name retention stratgy name supply retention power net scope name pd name retention power net retention ground net scope name pd name retention ground net Example This example shows you could create a low power assertion to Flag if an isolation supply goes down during an isolation period Checker module module ISO SUPPLY CHECKER ISO CTRL ISO PWR ISO GND import UPF input ISO CTRL input supply net type ISO PWR input supply net type ISO GND reg ISO pg sig assign ISO pg sig get supply
334. t ports pa_disable pa_disable insertiso insertret Insert isolation cells Controls retention cell insertion pa_enable insertret enables retention cell insertion in the gate level flow pa_gls pa_disable insertret disables retention cell insertion in the RTL or mixed RTL gate level flows pa_enable pa_enable insertls Insert level shifter cells Power Aware Simulation User s Manual v10 2c pa_enable 129 Power Aware Commands and Options ModelSim Commands Used for Power Aware Table A 3 Power Aware Actions for vopt pa enable and pa disable cont Default lowerboundary Perform isolation on the ports present in pa enable lower boundary of power domain modsrns Enables or disables support of the non pa enable LRM UPF command set related supply net nonoptimizedflow Must be enabled if you use novopt on the pa disable vopt command line relatedsupplies Define related supplies attributes on the pa enable boundary ports accessible pins of hard macros sourcesink Apply pathwise analysis of isolation or pa_enable level shifting supplynetworkdebug Enables or disables the appearance of UPF pa_disable objects created in the Structure Object and Wave windows udpnoret Enables or disables the retention of pa_disable sequential UDPs in a gate level or mixed RTL gate level power aware simulation This does not impact the default behavior of UD
335. t ports can be driven and what voltage the output ports can drive If you use the source sink or diff supply only options for setting isolation strategies the related supply tells the simulator what supply is powering the cell on the other side of the domain boundary which can then be used to determine whether or not isolation is necessary based upon your constraints This related supply information is useful for static analysis This command relates the specified power and or ground net to the port or pin specified When you use set related supply net on a primary port Input port assumes the supply net specified is the driver of the input port Output port assumes the supply net specified is the receiver of the output port That is the command specifies the external supplies In other words a buffer insertion takes place at the location parent Forinput port Buffer Input port For output port Output Port gt Buffer Static analysis honors this information of related supplies As buffers are now inserted in design just like isolation when supply of buffer goes off then buffer output gets corrupted For this case when isolation is also applied on the port at which srns is defined Forinput ports buffer is applied at location parent followed by isolation cells Buffer ISO Input port Foroutput ports buffer is applied at location parent preceded by isolation cells Output Port IS
336. te supply supply set handle supply set ref It will be an error if the primary supply handle already exists in a subdomain and points to a different supply set Correct usage example create composite domain cd subdomains pd2 pd3 supply primary associate supply set pd ss handle cd primary Alternate correct usage example create composite domain cd subdomains pd2 pd3 create composite domain cd supply ssh pd ss Incorrect usage example create composite domain cd subdomains pd2 pd3 supply ssh associate supply set pd ss handle cd ssh Error message Error test upf 88 UPF vopt 9765 It is invalid to use the associate supply set command with any composite domain supply set handle other than the primary handle Domain cd supply set handle pd ss create power switch The power switch will be created in the creation scope of composite domain Power Aware Simulation User s Manual v10 2c 193 UPF Commands and Reference create composite domain create supply net The supply net will be created in the creation scope of composite domain The command will also be applied with a reuse argument to each subdomain If the subdomain belongs to a different creation scope the command will be applied without reuse create supply port The supply port will be created in the creation scope of composite domain map isolation cell Not supported map level shifter cell Not sup
337. ted with some supply sets when add power state is invoked are valid Note n It is an error when there are no supply nets associated with the handles and the handles are used in the expression Power domain The power state of a domain is determined by the state of supply sets associated with the domain For example the definition of a domain s MY DOMAIN IS ON power state would logically require that the primary supply set be in a power state that is a NORMAL simstate all supply nets of the primary supply set are on and the current delivered by the power circuit sufficient to support normal operation Similarly a SLEEP mode for the domain may require the primary supply set to be in power state whose simstate is not NORMAL perhaps CORRUPT while appropriate retention and isolation supplies are NORMAL You can define the power state for a domain directly in terms of supply nets using supply expr in addition to the logic expr fadomain s power state logic expr specification includes comparison of another domain s active state to a power state defined on that domain it is equivalent to including the logic expr and supply expr specifications for that power state of the referenced domain in the definition of the power state e Ifadomain s power state logic expr specification includes comparison of a supply set s active state to a power state defined on that supply set it is equivalent to including the logic expr and
338. that will be sufficient to cause the rest of the domain to reach a well defined state after a few clock cycles Another alternative is to save the state of certain state elements before the domain is powered down and restore those statements to their saved state after the power domain is powered up again Retention cells are special memory elements that preserve their data during power down Such cells involve extra logic and possibly complex timing to save and restore their values across powered down periods 2 Various kinds of retention cells have been designed 2 3 4 Some of these use balloon latch mechanisms 2 which are made up of high threshold transistors to minimize leakage through them They are separated from the critical path of the design by transmission gates and thus are not required to be timing critical Others depend on complex sequences of different controls to achieve data retention The following UPF command specifies where retention should occur in the example in Figure E 1 set retention mem ctrl ret domain PD mem ctrl retention power net VDD 0d81 save signal mc save c high restore signal mc restore c low This command identifies the power domain PD mem ctrl within which retention registers should be used specifies the power supply used to maintain retained values and specifies the control signals required for saving and restoring the values of retention registers Power Managed
339. the novopt argument with either vcom or vlog when you compile for Power Aware simulation For more information on using vcom refer to Compiling a VHDL Design the vcom Command in the User s Manual For more information on using vlog refer to Invoking the Verilog Compiler in the User s Manual 32 Power Aware Simulation User s Manual v10 2c Power Aware Simulation Power Aware Simulation Flows Usage vcom files vlog files Simulate To implement simulation for this flow run the vsim command on the test bench using the pa argument along with the voptargs argument specifying a UPF file to invoke Power Aware simulation When you invoke vsim on the test bench top module it implicitly performs UPF processing and optimizes the design before beginning the Power Aware simulation Example vsim TB top pa voptargs pa upf test upf pa lib work other vopt args other vsim args where e TB top is the name of the top level module of the test bench e pa invokes simulation in Power Aware mode voptargs instructs Questa SIM to apply arguments for the vopt command For this flow specify the following vopt arguments o pa upf filename to cause vopt to apply the power intent specification o pa lib work the name of the destination library o other vopt args any other vopt arguments used to control UPF processing or optimization other vsim args any other vs
340. the PCF version is not specified or if there is no header statement prior to the occurrence of the first power or context statement Future versions of the PCF may define additional header information That is why the header statement is defined as a comma separated list of keyword value pairs that are specified only once in a PCF file header_statement HEADER keyword_value_pair keyword_value_pair stmt_end keyword_value_pair keyword value keyword VERSION SEPARATOR STMT_TERM user or vendor defined Note Currently the only information defined in the header statement is the PCF version number and separator character The verification tool provider will specify which versions numbers they support Future versions of the PCF specification may identify additional keywords and the values associated with them VERSION Required This keyword value pair identifies the PCF specification version number and must be the first keyword specified in the header statement as this information can determine whether or not subsequent keywords are recognizable and supported The version number will be of the form Power Aware Simulation User s Manual v10 2c 301 Power Configuration File Reference PCF Syntax and Contents lt positive gt lt natural gt Vendors may not extend or add to the version number as it applies to the version of the PCF specification and not to a vendor s tool version
341. tify the instance of the existing isolation cell Power Aware Simulation User s Manual v10 2c 289 UPF Commands and Reference Supply Nets Specifying Isolation Cells Power Aware simulation reads the set isolation command in the UPF file and identifies ports as candidates for isolation cell insertion These ports are also dumped into the UPF report file report upf txt as in Example C 29 Example C 29 UPF Report File for Isolation Ports report upf txt Isolation Strategy iso PD mid1 File test upf 44 Isolation Supplies power tb TOP tb pow ground tb TOP mid1l GND NET Isolation Control tb TOP ctrl Isolation Sense HIGH Clamp Value 1 Location automatic Isolated Signals Signal tb TOP mid1 out2 bot 2 Signal tb TOP midl outl bot Isolation Cell Instances If you have used the set isolation instance command in a UPF file to instantiate RTL isolation cells Power Aware simulation will infer those cells and perform isolation checks on them Power Aware simulation automatically infers the right UPF strategy for cells that are not e specified in the UPF file For more information refer to Detection of Power Management Cells A cell instance is identified as an isolation cell in any of the following cases Instance is specified with instance argument of set isolation command e Fora GLS design any of the following is present o Synopsys pragma synopsys is
342. tion Section 1 Port information appears in the format of formal port name externally connected net e Section 2 Displays the output supply port of the switch e Section 3 Displays the input supply ports e Section 4 Displays the control ports e Section 5 Displays the states of the switch listing each state in the following format state name switch state Boolean expression e Section 6 Displays the switch instances in the design associated with the UPF switch command This information is dependent upon specification of the pa_enable detectsw argument 56 Power Aware Simulation User s Manual v10 2c Power Aware Reports UPF Reports Retention Strategy Report information for the retention strategies is listed under this heading followed by the name of the strategy and the reference to the UPF source file where the strategy was created UPF Commands for Retention set retention pd retention domain pd retention power net V pd net set retention control pd retention domain pd save signal ret posedge restore signal ret negedge Report File Sections and Subheadings 1 Retention Strategy pd retention File test upf 39 2 Retention Supplies power tb top V pd net ground tb top G pd net 3 Retention SAVE tb top ret Retention Sense posedge Retention RESTORE tb top ret Retention Sense negedge 4 Retained Signals 1 Scope tb top vh File reg_vh
343. tion In some cases the dynamic checks report the operating voltage of one of the domains as 0 this happens when you have not changed the voltage on the primary power and ground pin of the domain and you are operating with default unknown voltage levels You can change the 84 Power Aware Simulation User s Manual v10 2c Automatic Checking Dynamic Checking in Power Aware operating voltages by using the supply on or supply off commands defined in the UPF SystemVerilog package Table 5 5 Dynamic Level Shifter Checks Usage Syntax Description Example Message Missing vopt pa_checks uml During simulation checks if a level shifter is required Level Shifter between domain crossing and reports if a level shifter strategy is not specified Also strategies specified with set level shift no shift in the UPF file are checked for any missing level shifters Error MPSA UPF MISSING LS CHK Missing level shifters for domain boundary pd aon Operating Voltage 2 000000 V gt pd top Opera ting Voltage 1 000000 V for the following Source port tb TOP bot4 outl bot LowConn gt Sink port tb TOP bot4 outl bot HighConn Time 90 ns Scope mspa top mspa upf top mspaO pd tb mspa3 pd top mspa5 pd aon MPSA UPF MISSING LS CHK 0 File src inc_ls_dyn_check1 top upf Line 4 Incorrect vopt pa checks uil Checks if the direction of level shifters specified for Level Shifter domain crossing does not matc
344. tion Checks 0 cc eee een eee 81 Table 5 5 Dynamic Level Shifter Checks cc00nseeceeeweusnsasneeseeess 85 Table 5 6 Miscellaneous Dynamic Checks 0 0 cece eee ene 86 Table 5 7 Static and Dynamic Checks Comparison 0 0 00 cece eee eee eee 89 Table 7 1 Power Aware State Machine List Window Columns 118 Table 7 2 Power Aware State Machine List Window Popup Menu 119 Table 7 3 PA State Machines Menu iios xxu RIA RE E RE E ERRRERESRET es 119 Table 7 4 Power Aware State Machine Viewer Window Popup Menu 122 Table 7 5 FSM View Menu Specific to Power Aware State Machines 122 Table A 1 Power Aware Arguments for vopt ssseeseeeee eh 126 Table A 2 Power Aware Arguments for vsim 0 0 c cece eee eens 127 Table A 3 Power Aware Actions for vopt pa_enable and pa_disable 128 Table C 1 List of Supported UPF Commands 0 0 cece cece eee ee eeee 173 Table C 2 Supported UPF Package Functions for VHDL 0000 5 259 Table C 3 Supported UPF Package Functions for SystemVerilog 259 Table C4 Supported UPF Attributes 2s oss ser eX Rr REEL ARO RES deen Rh 262 Table C 5 Power Aware Actions for vopt pa upfextensions llle 266 Power Aware Simulation User s Manual v10 2c 11 12 List of Tables Power Aware Simulation User s Manual v10 2c Chapter 1
345. tion strategies are not supported name prefix name suffix clamp value Specifying a user defined value for latch is not supported location Supports only the following values self parent fanin fanout faninout 236 Power Aware Simulation User s Manual v10 2c Argument instance update UPF Commands and Reference set_isolation Comments Restrictions Recognizes the special attributes present on the specified instance applies the appropriate simulation semantics and makes the connections as follows If there is a port of type pg type present on the instance then Power Aware simulation automatically connects the appropriate power and ground pins of the respective strategy and disable the implicit corruption semantics If there is no port of type pg_type present on the instance then Power Aware simulation applies implicit corruption semantics according to the primary_power and ground nets specified for the strategy Allows adding elements and supplies to a previously created power domain applies_to_clamp applies_to_sink_off_clamp applies_to_source_off_clamp diff_supply_only No isolation is introduced into the path from the driver to the receiver for an isolation strategy defined on a port on the interface of ref_domain_name where the driver is powered by the same supply as a receiver of the port force_isolation isolation_s
346. tions to Supply Ports of Power Switch 0000005 2 1 Automatic Connections ua 2655 exi hou RR do ued ewhedacadad o9h Sei a hag wee gs 272 Automatic Connections for Supply Nets 20 0 cece eee eee eee ee 272 Automatic Connections for Supply Sets 0 0 0 0 c eee eee eee 273 Power State Composition vsu on nd ena Sea debe need GH epee POE eee ee EERE ps 275 Determining State Dependency with add power state Arguments 276 Power State Reporting 0 c22ecadesavieee RO ER ARR ERR ERX RT EXA ARR RUE 278 Value Conversion Tables 262 22 4 c2enar 2vagedeudeeene widadi I d RR Edda ga 280 Using VCT Commands 224 cr kk ar ER DERE EIE ERG RURER E Ruhr RES ea sage 280 Examples M PM CT PE 280 Linm altons os 9 ES IRDERERE ERYaX Es PAPER RARE x Addons ean 281 Predefined VCTs Supported from the UPF Standard 0 0 00 eee eee 281 Connections Using Value Conversion Tables VCTs lesse eese 284 Simulation Semantics for UPF Supply Connections eleeeeeeeeeeess 286 Power Aware Simulation User s Manual v10 2c Table of Contents Supply NES e eaux uo er d hee ERU dr e ee n f eee Dee Pe eee CERE ERES 287 Resolving Drivers on a Supply Met iiissouokwessek 4 eR REEATIERACERTARSAE RARE E AA 287 o cou Seg HFC OPT SECPNRES 288 Defining Isolation 225 usc Ra ERR CS Qa eS PXSU seek Cp pad eaten ES qb ia 289 Method 1 Isolation is already explicitly present 0
347. to both Location automatic Level Shifted Candidate Ports 1 Signal tb top q combvl Signal tb top q_latvl Signal tb top q regvl Signal tb top set Signal tb top reset Signal tb top clk Signal tb top d Signal tb top iso Signal tb top ret 0 Signal tb top pwr2 1 Signal tb top pwrl HI p oo0 JovUim UC hh Static Checking UPF Reports Report Output report static txt Command vopt pa checkszs In Power Aware you can perform a static check of the design using the power intent specified in the UPF file report static txt The pa report command generates this text file if you used the pa checks argument to perform static checks For Static checking Power Aware simulation verifies the design for the defined power intent without doing actual simulation This static analysis uses the power intent definition to report any missing power related information or inconsistencies Because a simulation run is not 52 Power Aware Simulation User s Manual v10 2c Power Aware Reports UPF Reports required you only need to run vopt to perform static checking Results from static checking are written to the report static txt report file Report Output report nretsyncff txt Command vopt pa checksznpu This report file is generated only when you specify vopt pa_checks npu It contains a list of hierarchical paths of those flip flops in the design that do not have an asynchronous control sig
348. to the ports of the PA model This allows the names of the signals in the design to differ from the names of the pins on the PA cell The syntax used is straight from the Verilog 1364 LRM for named parameter assignment The actual may be a simple name a hierarchical name a bit or part select or struct record element selection During verification the Power Aware behavior is mapped from the specified Power Aware model to all inferred sequential elements matching the cell type in order to determine when to save and restore the state or specified corruption value of the sequential element according to the semantics defined in the PA Verification Guidelines for Power Aware Modeling Mapping Statement Precedence The general precedence ordering defined in section Rule Precedence applies when multiple mapping statements refer to the same region Specifically the precedence for mapping statements is as follows 312 A mapping to an instance lower in the design hierarchy takes precedence over a mapping to an instance of a parent scope in the hierarchy A mapping to a process takes precedence over a mapping applied to a parent instance scope Power Aware Simulation User s Manual v10 2c Power Configuration File Reference PCF Syntax and Contents A mapping to a signal takes precedence over either a process or instance mapping applied to a parent scope e If two or more mapping statements map to the same region and the same Power A ware
349. top argument to capture the DUT hierarchy for Power Aware analysis When you run the vsim command it performs debugging and runs vopt internally to perform optimization see Using the Delayed Optimization Flow For example vlog design v vcom design vhdl vopt pa upf config file tb debugdb pa top tb dut vsim tb pa debugdb vopt Optimized design unit This flow resembles the conventional three step flow where you use the vopt command to specify a Power Aware simulation the name of the design unit to be optimized and debugging Use the pa top argument to capture the DUT hierarchy for Power A ware analysis For example Power Aware Simulation User s Manual v10 2c Visualization of Power Aware Operations Power Aware Schematic Display vlog design v vcom design vhdl vopt o optdu pa upf config file tb debugdb pa top tb dut vsim optdu pa debugdb This DUT based flow with an optimized design unit not only does common analysis for Power Aware and debugging but also provides flexibility to enable Power Aware analysis from specific hierarchy and do code generation in one step Usage Notes The pa top argument is used to specify hierarchy of UPF root scope This supports Power Aware analysis of UPF from hierarchy other than the vopt TOP hierarchy If vopt is run from test bench tb and UPF scope is starting from DUT which is instantiated in test bench as dut inst then you need to specify vopt pa top tb
350. total tb1 topl OUTPUT 1 tbl topl q1 1 PD TOP3 sub total tb1 topl NPM FF 7 tbl1 topi1 d1 6 4 3 tb1 top1 d1 3 0 4 OUTPUT 11 tbl topl1 out buf 1 tbl topl out reg 1 tbl topl1 out lat 1 tbl topl out uniso 1 tb1 topl1 d2 7 NPM FF Denotes all Non Power Management Flip Flops of a Power Domain NPM LA Denotes all Non Power Management Latches of a Power Domain QUTPUT Denotes all outputs and power signals which are not sequential elements of a Power Domain use retention as primary Description This argument powers the storage element and the output drivers of the register using the retention supply Example upf version 2 0 set scope tb create power domain pd aon include scope Power Aware Simulation User s Manual v10 2c 295 UPF Commands and Reference Supply Nets connect supply net vdd net ports vdd port connect supply net gnd net ports gnd port create supply set pd aon ss function power vdd net function ground gnd net HEEE FE HE HE HE HE E HE TEE RE ERE HE HE HE E HE HE HE HE E HE H E H ERE E E Retention Strategy for pd HEEE FE E HE HE HE E HE HE E HE ERE HE HE HE E HE HE HE HE E HE H E H H H H H set_retention pd_retentionl domain pd save signal ret posedge restore signal ret negedge elements top vh use retention as primary map retention cell pd retention1 domai
351. ture for the whole system including the specific requirements for power distribution switching and state retention for each power domain and the requirements for isolation and level shifting between interacting power domains The Power Control Unit PCU is a hardware implementation of power control logic that drives power control signals for each domain in the correct order The Cortex R4 CPU is an embedded ARM processor that drives system level power state changes by sending transactions to the PCU Verifying the Power Management Architecture Verifying the sufficiency of the power management architecture can be done in part through static analysis Given a complete definition of the power domains and power states for a given design it is relatively straightforward to verify that the necessary isolation cells and level shifters are present or implied by a UPF specification to ensure that the power domains will interact correctly and will not be adversely affected when their neighboring power domains are 330 Power Aware Simulation User s Manual v10 2c Supplemental Information Power Aware Verification of ARM Based Designs powered down Static analysis can also ensure that the necessary supply structures are present to provide the ability to control power to each power domain However static analysis is not always possible Depending upon the sequencing of power state changes and the ramping of power supplies as they transition there ma
352. txt Collecting Power Aware Coverage Information on States and Transitions You can collect coverage information on power aware states and transitions as created in your UPF file and analyze the results within the ModelSim environment Refer to the section Power State and Transition Concepts for more information Prerequisites Include power aware state information in your UPF file Procedure 1 Compile You do not need to alter your existing commands 2 Optimize You do not need to alter your existing command 3 Simulate Add the coverage option to your existing command 4 Generate UCDB refer to the section Generating a UCDB File for Power Aware 5 Generate reports refer to the section Generating Power Aware Coverage Reports 6 Analyze data after simulation refer to the section Accessing Coverage Data for Post Simulation Analysis Concepts Undefined Power State During simulation when none of the named states including predefined states of a state object is active the tool created Undefined state becomes active This tool inserted undefined state is representative of all the power states that are missing in the UPF while adding states on a particular UPF objects such as power domain Supply set Supply port PST Power Aware Simulation User s Manual v10 2c 95 Power Aware Coverage Power Aware Coverage Analysis pa coverageinfo The simulator generates a power aware cove
353. u disable a particular power aware check the underlying assertion for that check is also disabled resulting the following o disabling the messages of selected checks o disabling the associated coverage collection of that assertion Power aware checks are disabled at time 0 zero By default all dynamic power aware checks are disabled at time 0 resulting in no messages at this time You can change this behavior with pa msg before running your simulation for example if you want to enable Power Status Info pa_checks p at time 0 do the following vsim gt pa msg enable pa_checks p vsim gt run 1ns Use Model for pa msg You can use this command at any time during simulation It will have impact in simulation after the time stamp of its usage until the time any new pa msg command overrides the previous one for example In the following example the power aware check umi missing iso will be disabled after 100ns and it will be re enabled at 150ns Therefore in the time window from 100ns to 150ns this pa check will be disabled run 100ns pa msg pa checkszumi disable run 50ns pa msg pa checkszumi enable Power Aware Simulation User s Manual v10 2c 137 Power Aware Commands and Options Power Aware Messages Option Descriptions of pa msg The options to the pa msg command are organized broadly into three categories e Selecting power aware checks e Taking finer control over selected power aware checks
354. ual v10 2c pa_checks pis Automatic Checking Quick Reference Comparison of Static and Dynamic Check Arguments Power Aware Simulation User s Manual v10 2c 91 Automatic Checking Quick Reference Comparison of Static and Dynamic Check Arguments 92 Power Aware Simulation User s Manual v10 2c Chapter 6 Power Aware Coverage Power aware coverage data helps you ensure that your regression suites are adequately testing power aware elements of your design specifically Dynamic power aware checks as specified with the pa checks switch to the vopt command Power aware states and transitions as created through the UPF file with the add power state add port state or add pst state commands This chapter describes the following topics Power Aware Coverage Collection provides procedures for collecting coverage data Power Aware Coverage Analysis provides procedures for analyzing your collected coverage data Power Aware Coverage Report Reference provides reference information about the power aware coverage reports Power Aware Coverage Collection This section describes how you can alter your existing scripts to collect coverage data for your design and test suite Collecting Power Aware Coverage Information on Dynamic Checks Collecting Power Aware Coverage Information on States and Transitions You can view the coverage information during a live simulation or analyze it later by saving it to a U
355. ulation Power Aware Modeling 26 Power Aware Simulation User s Manual v10 2c Chapter 3 Power Aware Simulation Inputs Required for Power Aware Simulation 0 cece cece ce eeeeee 27 Commands Used For Power Aware Simulation eere 27 Power Aware Simulation Flows 0 cece cece cece cece cece enhn 28 Working with Liberty Libraries 6 cscceccscceveses sees sess eevee vesceenes 35 POU Based Sumulatencaircsnw rw Ee RR OR ADU ARR AGER ORC ORC hee hee eens 37 Power Aware Simulation Debug 0 c cece cece cece e cece cece hh nn nn 38 Applying Power Intent to the Design cc ccc cece cece cece eee e cence 39 Inputs Required for Power Aware Simulation Power aware simulation requires a complete HDL representation of the design including simulation models for leaf level instances The HDL representation may be expressed in Verilog SystemVerilog or VHDL code or any combination of these languages and it may be synthesizable RTL code behavioral RTL code Gate Level netlist or any combination of these forms Power Aware simulation supports all of the above For designs that are or that include a Gate Level netlist and for designs that include instances of hard macros a Liberty library may be available that specifies the characteristics of the standard cells and or hard macros used in the design Liberty models typically include power related information that must be considered during
356. ument to the The set isolation command For these examples assume that PD2 PD3 and PD4 all have same supply sets create supply set PD2 SS create power domain PD2 associate supply set PD2 SS handle associate supply set PD2 SS handle associate supply set PD2 SS handle D2 primary D3 primary D4 primary U u U Ct ict ict Place isolation cells at Ports C and F and isolate Paths A C and F I Do not isolate path F H set isolation isol domain PD3 applies to both diff supply only TRUE location parent Place isolation cells at Ports A and I and isolate Paths A C and F I set isolation iso2 domain PD3 applies to both diff supply only TRUE location faninout Place isolation cell at Port A and isolate Path A C set isolation iso3 domain PD3 applies to both source PD1 SS diff supply only TRUE location faninout Multiple Strategies Example Isolate the same port F with different Sinks Here Port H will be isolated with isol and port I with iso2 set isolation isol domain PD3 elements F sink PDA SS location fanout clamp 1 set isolation iso2 domain PD3 elements F sink PD5 SS location fanout clamp 0 Multiple Isolation Cells Examples Refer to Figure A 2 for the following examples on using multiple isolation cells Using source and location fanout Isolates all output port paths and places isolation cells at Ports G H and I Places two isolat
357. undant Isolation Cell pa_checks sri Incorrect Isolation Cell pa checks sii Power Aware Simulation User s Manual v10 2c 89 Automatic Checking Quick Reference Comparison of Static and Dynamic Check Arguments 90 Table 5 7 Static and Dynamic Checks Comparison Valid Isolation pa checks svi Isolation not analyzed pa_checks sni Isolation not inserted pa_checks sdi Isolation Enable Protocol pa_checks iep Isolation Disable Protocol Isolation Race Check pa_checks idp pa checks irc Isolation Enable Protocol Check for COA States pa_checks iepcoa Isolation Disable Protocol Check for COA States pa_checks idpcoa Isolation Functionality Check pa_checks ifc Isolation Clamp Value Check Isolation Redundant Activity Check pa_checks icp pa_checks ira Isolation Toggle Check pa_checks it Retention Enable Protocol pa_checks rop Retention Enable Disable Protocol pa_checks rpo Latch Enable Clock Level Protocol pa_checks rcs Latch Enable Clock Toggle Protocol pa_checks rsa Primary Supply pa_checks cp Isolation and Retention Supply pa checks upc Non Retention Register Reset pa_checks npu Glitch Detection pa_checks uge Toggle Always on Power Domain pa_checks t pa_checks a Power Domain Status pa_checks p Illegal or Undefined State Power Aware Simulation User s Man
358. upply set is sufficient to support full and complete operational switching capabilities with characterized timing NOT NORMAL This is a special placeholder state It allows early specification of a non operational power state while deferring the detail of whether the supply set is in the CORRUPT CORRUPT ON ACTIVITY CORRUPT STATE ON CHANGE or CORRUPT STATE ON ACTIVITY simstate If the supply set matches a power state specified with simstate NOT NORMAL the semantics of CORRUPT shall be applied unless overridden by a tool specific option NOT NORMAL semantics shall never be interpreted as NORMAL This command attributes one or more power states to a supply set or a power domain Power Aware Simulation User s Manual v10 2c 181 UPF Commands and Reference add power state Supply set A supply set is a grouping of supply nets that collectively define a complete power supply The power state of a supply set is specified in terms of the supply nets that constitute the set It is the combined states of the constituent supply nets that determine the following Whether there is current available to power an element The voltage level of the supply Simstates are associated with power states of supply sets Semantics for supply set simulation are applied to the elements connected to the supply set when you enable simstate behavior You can also reference supply sets in add power state as handles Here only those handles associa
359. ur where isolation Redundant strategies are specified but isolation is not required for power domain crossing then these strategies will be reported as redundant Reports redundant isolation cells when isolation is not required from driving power domain to sink power domain and isolation cell is placed for the power domain crossing Warning vopt 9750 UPF ISO STATIC CHK Found Total 3 Redundant isolation cells Static vopt pa_checks sii Reports incorrect isolation cells when isolation is Incorrect required for power domain crossing but isolation strategy is specified with set isolation no isolation Warning vopt 9750 UPF ISO STATIC CHK Found Total 3 Incorrect isolation cells 72 Power Aware Simulation User s Manual v10 2c Automatic Checking Static Checking in Power Aware Table 5 1 Static Isolation Checks cont Usage Syntax Description Example Message vopt pa checks svi Isolation is required for a power domain crossing and valid isolation strategies are specified for domain crossing Note vopt 9750 UPF ISO STATIC CHK Found Total 1 Valid isolation cells Static vopt pa checks sni Reports isolation strategies as Not analyzed if power Not state table PST information is not sufficient to Analyzed analyze whether isolation is required or not for input and output power domains of an isolation strategy Warning vopt 9750 UPF ISO STATIC CHK Found Total 1 Not analyzed isolation c
360. ure that voltage dependent delays in ramping up or down the power supply are factored into control signal sequencing Power Aware Verification Flow Verifying RTL level specification of active power management for a given design involves several steps First we need to verify that the power management architecture is correctly structured given the operating modes of the device and the power states that have been defined to reflect those modes Second we need to verify that the design both each power domain individually and all of them collectively behave correctly when power management control Power Aware Simulation User s Manual v10 2c 329 Supplemental Information Power Aware Verification of ARM Based Designs signals are given in the correct sequence Third we need to verify that the power control logic will always generate power control signals in the correct sequence Figure E 2 shows the high level design of an ARM based SoC with active power management The above verification steps as applied to this example are described below Figure E 2 An ARM based SoC with Active Power Management Control Data Interface Interface Y JPEG 1 Encoder Video Controller This design consists of multiple functional units communicating over the AXI bus Each functional unit may be defined as a separate power domain or even as a collection of power domains A UPF file for this design would specify the power management architec
361. user to create power domains inside a generate blocks e g set scope mid forgen 1 create power domain PD forgen include scope Power Aware Simulation User s Manual v10 2c 253 UPF Commands and Reference set simstate behavior set simstate behavior Support for UPF Standard v1 0 no v2 0 yes Arguments Argument Comments Restrictions ENABLE DISABLE ENABLE applies simstate simulation semantics for every supply set automatically connected to an instance of a model Elements implicitly connected to a particular supply set have simstate semantics enabled by default DISABLE disables simstate simulation semantics recursively for all the descendants of the instance of the model Elements automatically or explicitly connected to a particular supply set have simstate semantics disabled by default When both lib and model are specified the simstate behavior is defined for the specified models in the specified library If model is not defined and lib is specified the simstate behavior is defined for all models in the specified library The elements argument has higher priority over model and lib elements lt list gt ModelSim extension Optional argument not specified in UPF v2 0 You specify a list of element names as the value to this argument which determines the simulation simstate behavior for one or more design elements Because this is a non standard argument you can specify this
362. ust convert logic 1 signal voltage levels in the source domain to logic 1 signal voltage levels in the sink domain Although level shifters function continuously and therefore do not need to be enabled dynamic changes in the supply voltages for the respective power domains may result in unexpected situations Power Control Logic Power management may involve both software and hardware control For example a power control unit PCU can be specified in RTL internal to the SoC The PCU may be under software control by an embedded processor The combination of these power management controls drive the signals that define the PCN based on the system s power management strategy signaling power domains to retain state enable isolation power down turn off switches power up turn on switches disable isolation and restore state Correct operation of the power management architecture depends upon correct sequencing of power control signals For example outputs of a domain must be isolated before the power is shut off and must remain isolated until after power is turned on again Thus the control signal initiating isolation must come before the control signal that turns off the power switch Similarly the control signal that turns on the power switch must occur before the control signal that terminates isolation In fact turning power on and off may involve handshaking between the PCU and the supply source or a sensor monitoring the supply to ens
363. v1 0 connect supply net net name ports list pins list lt cells list domain domain name rail connection rail type pg type pg type vct vct name UPF2 0 connect supply net net name ports list pg type pg type list element list j vct vct name pins list cells list domain domain name rail connection rail type Currently the connect supply net command in UPF2 0 is modeled as its equivalent command in UPF v1 0 That is connect supply net command in UPF v2 0 will not accept element list in pg type argument Examples connect supply net VDD domain PD SW pg type primary power connect supply net Vdd backup cells RET CELL pg type backup power connect supply net VSS domain PD SW pg type primary ground vct UPF GNDZERO2SV LOGIC Automatic Connections for Supply Sets You can define automatic connection semantics on supply sets using either of the following UPF commands connect supply set connect create power domain define func type Power Aware Simulation User s Manual v10 2c 273 UPF Commands and Reference UPF Supply Connections Power Aware simulation automatically connects supply nets of supply sets to the supply ports of design elements This connection is based on the purpose of the supply set in a given domain or strategy context and the function that a supply net performs in the context of supply set Limitations e Supply sets specified in str
364. ve been added If there are errors in the power management architecture they will very likely cause signal corruption that does not go away after power up which in turn will lead to functional errors in the design Debugging power management errors can be performed by tracking corruption of signals in the waveform view but that method is tedious and error prone A much more effective method is the use of assertions to check for correct operation of the design under active power management For example an assertion to check that an output of a power domain is clamped to the correct value when the power domain is powered down will immediately catch any error related to the clamp value or the powering of the isolation cell involved rather than just generating an X and letting it propagate Such assertions can be automatically generated by the power aware simulator Verifying Power Control Logic Power aware simulation can also be used to verify the control logic driving the power management architecture provided that the control logic is part of the design rather than being implemented in a test bench For software based power control logic simulation is the only method available In particular hard ware software co simulation is necessary if the power control logic is split between hardware and software components as is often the case For hardware based power control logic such as a power control unit another alternative is available Form
365. veenvces deer RR E REe RS A RAS avtease 71 Debugging Static Checks sv vidi es ROSE ted redt RIPE OR Dd ERRORES 71 Static Isolation CHECKS c oos nue ea ete ERCCREC a nia EE EEEE EREA Eig Eque 72 Static Level Shifter Checks 2 0 24 dudec esac ee Xx REEF Rates dades 74 Reporting for a Valid Level Shifter 2o occisus eser Rr RR ERR TT Dynamic Checking in Power Aware 401024444 tene ser kRR RR RR b n 78 4 Power Aware Simulation User s Manual v10 2c Table of Contents Usage NOIBS osse SER eREX eed Gee Eee ee SE KD ee Ce Keer SEE CREE Rd 78 Dynamic Retention Checking 22 h2 lt ek 4 os acu eee g ideas eae he oe need REESE 79 Dynamic Isolation Checking 2 06s crseeehesiderntdesBeeenersdeenheresdeas 81 Dynamic Level Shifter Checking i ssec pe iR RRR ER ECERERE D ARR E REC EE 84 Operating Voltage for Dynamic Checking leleeeeeeeeeeeeeeee 84 Miscellaneous Dynamic Checking i iare sosedees eed dias av eR ER ER EY RAPERE 86 Implementing Checking at Gate Level 0 0 cece eect eee 88 Level Shifting for Gate Level Checking 2 02 20 404220ese ees rhe RR RR Re 88 Isolation for Gate Level Checking 0 cece eect eee 88 Quick Reference Comparison of Static and Dynamic Check Arguments 89 Chapter 6 Power Aware COVELOBE acea so ac RR A d ORAE RC cR e Bo Cope ap obe ina ec ar a 93 Power Aware Coverage Collection 2 2456 3a Rer EXVPbERUERRCUC RUE Se RA RAE R E CERS 93 Collecting Power Aware Coverage Inf
366. vel sensitive Control of Retention Models Power Aware simulation provides default Verilog models for retention cells that support both edge sensitive and level sensitive detection of input control signals for save and restore functions Note that there are separate models for single and dual control signals e Single control signal uses opposite inverted edge or level of one input signal to initiate save and restore Dualcontrol signals uses edge or level of two different input signals to initiate save and restore Automatic Model Selection Based on the retention control signals specified in the UPF specification Power Aware simulation automatically selects an edge sensitive or level sensitive model for retention Automatic selection occurs according to the following conditions e If both save_signal and restore signal are level sensitive and the same signal is used for both the Single control level sensitive model is selected e If both save signal and restore signal are level sensitive and two different signals are used for save and restore the Dual control level sensitive model is selected e If any control signal save or restore is edge sensitive and the same signal is used for both save and restore the Single control edge sensitive model is selected Power Aware Simulation User s Manual v10 2c 23 Concepts for Using Power Aware Simulation Power Aware Modeling If either save signal or restore signal is edge
367. vh pd aon Path1 q combvl pd aon Path1 q latchvl pd aon Path1 qd regvl pd aon Path1 ret pd aon Path1 iso pd aon Path1 pwr pd aon Path1 set pd aon Path1 rst pd aon Path1 clk pd aon Path1 d pd aon Path2 q_combvl pd aon Path2 q_regvl NPM FF pd aon Path2 q_latvl NPM LA pd Path3 q combvh pd Path3 q_regvh R pd Path3 q latvh NPM LA Path4j q combvl Path4 q_regvl R Path4 q_latvl NPM LA Behavioral Element Reporting Use the pa_behavlogfile argument to generate a report on behavioral constructs in the design that need to be in an always on power domain Usage vopt pa_behavlogfile lt filename gt Description This argument creates a report filename of all the non synthesizable constructs found in design This report allows you to identify all the constructs that have to be put in an always on power domain The format for the constructs of this argument is the following I hierarchical path of instance for non synthesizable instances P hierarchical path of block process always initial for non synthesizable process always initial blocks S hierarchical path of signals for signals writers falling in non synthesizable unnamed process always initial block Example Excerpt from a Behavioral Log File S top out P top 11 P top 12 Power Aware Simulation User s Manual v10 2c 67 Power Aware Reports Behav
368. w mentor com eula IMPORTANT INFORMATION USE OF ALL SOFTWARE IS SUBJECT TO LICENSE RESTRICTIONS CAREFULLY READ THIS LICENSE AGREEMENT BEFORE USING THE PRODUCTS USE OF SOFTWARE INDICATES CUSTOMER S COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH IN THIS AGREEMENT ANY ADDITIONAL OR DIFFERENT PURCHASE ORDER TERMS AND CONDITIONS SHALL NOT APPLY END USER LICENSE AGREEMENT Agreement This is a legal agreement concerning the use of Software as defined in Section 2 and hardware collectively Products between the company acquiring the Products Customer and the Mentor Graphics entity that issued the corresponding quotation or if no quotation was issued the applicable local Mentor Graphics entity Mentor Graphics Except for license agreements related to the subject matter of this license agreement which are physically signed by Customer and an authorized representative of Mentor Graphics this Agreement and the applicable quotation contain the parties entire understanding relating to the subject matter and supersede all prior or contemporaneous agreements If Customer does not agree to these terms and conditions promptly return or in the case of Software received electronically certify destruction of Software and all accompanying items within five days after receipt of Software and receive a full refund of any license fee paid ORDERS FEES AND PAYMENT 1 1 To the extent Customer or if
369. wer Aware simulation determines that state PD1_S1 and PD2 S2 cannot co exist add power state PD1 state PD1 S1 supply_expr VDD1 FULL ON amp amp GND1 FULL ON amp amp VDD FULL ON 0 8 1 4 add power state PD2 state PD2 S2 supply_expr VDD1 FULL ON amp amp GND1 FULL ON amp amp VDD FULL ON 1 6 2 4 Power State Reporting Power Aware simulation provides the following types of information in the report files Information about the power state added on power domain supply sets Power State dependencies between connected power domains 278 Power Aware Simulation User s Manual v10 2c UPF Commands and Reference UPF Supply Connections Example Report Excerpt Power state info of Power domain PD tb 1 Power state PD tb normal File src testcase4 test upf 15 Supply Expression tb pow z z FULL ON 3 30 amp amp tb gnd FULL ON 1 00 Function States 1 Ground tb gnd FULL ON 1 00j Power tb pow FULL ON 3 30 Power state info of Power domain PD mid2 1 Power state PD mid2 off File src testcase4 test upf 67 Supply Expression mid2 MAIN NET OFF amp amp mid2_GND_NET OFF Function States 1 Ground mid2 GND NET OFF Power mid2 MAIN NET OFF 2 Power stat
370. wire reg e Verilog wire reg e VHDL bit std logic std ulogic Boolean NOTE Any subtypes of these are not supported Predefined VCTs Supported from the UPF Standard Power Aware simulation provides several predefined VCTs described in Annex C of IEEE Std1801 2009 which you can use with the connect supply net vct command The predefined VCT definitions provided with Power Aware simulation are listed below create hdl2upf vct VHDL SL2UPF hdl type vhdl table U OFF X OFF 0 OFF 1 ON Z OFF L OFF H ON W OFF OFF Power Aware Simulation User s Manual v10 2c 281 UPF Commands and Reference Value Conversion Tables create upf2hdl vct UPF2VHDL SL hdl type vhdl table PARTIAL ON X ON 1 OFF 0 create_hdl2upf_vct VHDL_SL2UPF_GNDZERO hdl type vhdl table U OFF X OFF O ON 1 OFF Z OFF L ON H OFF W OFF OFF create upf2hdl vct UPF_GNDZERO2VHDL_SL hdl type vhdl table PARTIAL ON X OFF 1 ON 0 create hdl2upf vct SV_LOGIC2UPF hdl type sv table X OFF Z PARTIAL ON 1 ON 0 OFF JJ create upf2hdl vct UPF2SV LOGIC hdl type sv table PARTIAL ON X ON 1j OFF 0 create_hdl2upf_vct SV_LOGIC2UPF_GNDZERO hdl_type sv table X OFF 0 ON 1 OFF Z O
371. with add port state for the supply port Error vsim 8933 MSPA UPF ILLEGAL STATE REACHED Time 80 ns PST eth pci pst reached an undefined state tb pow tb nom 4 800000 V midl MAIN NET undefined 4 000000 V mid2 MAIN NET NOM2 5 300000 V File src illegal pst 2 test upf Line 79 PST state UNDEFINED Error vsim 8933 MSPA UPF ILLEGAL STATE REACHED Time 90 ns Port TB PRI reached an undefined state TB PRI undefined 4 099999 V Glitch vopt pa checks ugc Catches any spurious spikes glitches on control lines Detection so that it does not cause false switching of control ports of various control logic such as isolation power switch and retention You can use pa msg glitch window command to specify time window for glitch checking Non vopt pa checks npu Checks that non retention registers are reset when the Retention power domain containing them is powered up Register Reset Error vsim 8912 MSPA NRET ASYNCFF Time 12 ns Asynchronous set reset control for the following flop s of power domain PD1 is not asserted at power up tb top inst outl File test upf Line 4 Power Domain PD1 Also generates the report file report nretsyncff txt Power Aware Simulation User s Manual v10 2c 87 Automatic Checking Implementing Checking at Gate Level Implementing Checking at Gate Level For Power Aware simulation on gate level designs
372. y be a requirement for level shifters that is not obvious from the power state table Also the power state table may not be complete and power states that are not defined might actually occur during operation of the device Finally external supply sources may be switched or may vary in voltage beyond what is defined in the power state table For these and other reasons simulation is often required In this case power aware simulation is necessary to ensure that the power management architecture and its controls are taken into account during simulation Power Aware simulation enables functional verification of power management in the context of an RTL design A power aware simulation run does the following Compiles the design and UPF specifications Infers sequential elements from the RTL design registers latches and memories Applies the UPF specified power management architecture to the RTL design e Augments the simulation model with appropriate power aware models e Dynamically modifies the RTL behavior to reflect the impact of active power management Using the UPF and sequential element information the simulator is able to augment the normal RTL behavior with the UPF specified power aware behavior power distribution and control retention corruption and isolation This involves selecting the appropriate simulation models to implement the UPF specified power management architecture It may also involve recognizing and integrat
373. your design File contents are structured according to power domains and provide hierarchical path names of the signals and instances that are affected by the power intent This report also Power Aware Simulation User s Manual v10 2c 47 Power Aware Reports UPF Reports contains the count of retention and non retention cells The report mspa txt file does not report on objects hierarchy instances that are excluded from Power Aware co Nyonu d CO Pho S 48 Total tb upf retention ret 2 NPM FF 1 NPM LA 3 OUTPUT 3 pd sub total tb top vh tb top vl upf retention ret 2 tb top vh q regvh 1 tb top vl q regvl 1 NPM LA 2 tb top vh q latvh 1 tb top vl q latvl 1 OUTPUT 4 2 tb top vh q combvh 1 tb top vl q combvl 1 Line 1 The keyword Total followed by the top design module specified in parentheses Lines 2 5 A consolidated count of all the types of cells in the design in the format CELL TYPE Count where CELL TYPE could be any of the following o NPM FF Represents non power management flip flops or corrupt flip flops which do not have retention associated with them During simulation they get corrupted only when power domain is switched off o NPM LA Represents non power management latches or corrupt latches which do not have retention behavior associated with them During simulation they get corrupted only when power domain is switched off o OUTPUT Represent
374. yze the results of your power aware coverage This section describes how you generate each type of report from either the command line or through the GUI during a live simulation 96 Power Aware Simulation User s Manual v10 2c Power Aware Coverage Power Aware Coverage Analysis If you want to generate reports and do not want to open a simulation you should substitute coverage report with vcover report and add the UCDB file as an argument for example vcover report pa ucdb assert pa Power Aware Checks Coverage Summary This produces a simple report including a summary of the checks that never failed Command ine coverage report assert pa GUI o Menu Tools gt Coverage Report gt Text o Coverage Text Report dialog box e Verbosity Default Coverage Type Assertions and Power Aware Refer to the section Power Aware Checks Coverage Summary for a detailed description of this report Power Aware Checks Coverage Detailed Report This produces a detailed report showing each type of check with pass and failure information Command line coverage report assert pa details e GUI o Menu Tools Coverage Report Text o Coverage Text Report dialog box e Verbosity Details Coverage Type Assertions and Power Aware Refer to the section Power Aware Checks Coverage Detailed Report for a detailed description of this report Power Aware Checks Coverage Verbose Report This produces a expansive report showing each

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