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XtremeDSP Development Kit-IV User Guide ( ver1, 10031 KB )

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1. Header Pin User FPGA 2V3000FG676 Number PIN No l ADJIN lt 12 gt L26 2 ADJIN lt 13 gt M26 3 ADJIN 10 M25 4 ADJIN I1 M24 5 ADJIN lt 8 gt M23 6 ADJIN lt 9 gt M22 7 ADJIN lt 6 gt M21 8 ADJIN lt 7 gt M20 9 ADJIN lt 4 gt N25 10 ADJIN lt 5 gt N24 ll ADJIN lt 2 gt 19 12 ADJIN lt 3 gt NI9 13 ADJIN lt 0 gt K26 14 ADJIN lt 1 gt K25 15 ADJIN lt 14 gt 119 16 ADJIN lt 15 gt K20 17 ADJIN 16 L21 18 ADJIN lt 17 gt L20 19 ADJIN lt 18 gt L24 20 ADJIN lt 19 gt L23 21 ADJIN lt 20 gt K22 22 ADJIN lt 21 gt K21 23 ADJIN lt 22 gt K24 24 ADJIN lt 23 gt K23 25 ADJIN lt 24 gt 26 ADJIN lt 25 gt J20 27 ADJIN lt 26 gt J23 28 ADJIN lt 27 gt J22 29 3 3V n c 30 GND n c 31 n c n c 32 n c n c 33 n c n c 34 n c n c NT107 0272 Issue March 9 2005 Table 20 Adjacent Bus Digital I O Header www nallatech com 51 The StrathLED is an optional module from Nallatech that can be plugged into this header to provide an array of LEDs for display purposes For more information please contact support nallatech com 7 3 Firmware The Digital I O in your design is configured according to the specific of the connected FPGA The Virtex 4 Datasheet and handbook from Xilinx provide extensive information on standards that can be supported by pins on the Virtex 4 device 7 4 Software There is no specific support for controlling the Di
2. 52 52 g B s 53 53 lati C 54 Physical Location of EEDS uoa d ancien niue wissen apes unu 54 Interface ance 55 User LEDS 56 Firmware mM C P 56 SONWANE Susa un 57 FUSE Software LED Function os ep hierro Paper EIUS 57 Listing of Calls in the FUSE API for LED Control 58 U MMC s 59 s n S 59 59 vi www nallatech com NT107 0272 Issue March 9 2005 Reset 5 0 59 ole ee 60 SOIC WV A ass tars 6 RUSE Software Reset ke bed 61 Listing of Calls in the FUSE API for Reset Control 62 So 63 BO RENE M EMEN 63 secat irt pneri ttu nip deni bana 64 Physical Clock ReSOBMPCBS uela bieten ts p Dile iu 64 Clocking Configuratio nt 65 BONES DESCrIptiohS ua dE
3. CPLD PSU Controller 9500 General JTAG General JTAG Chain Header J14 Drives JTAG JTAG TDO Return Paths iF F F F R P F an P B P P P F P F P PIP m a a BenADDA Interface FPGA Interface FPGA Module XC2V80 Configuration s Configuration amp XC4VSX35 1800 1 1800 0 123456789 Figure 74 General JTAG Chain top and General JTAG Connector J14 bottom Pin Name Description 3 3V 3 3 Volts Supply 2 GND Signal Ground 3 N C Not connected do not use 4 TCK ALT JTAG TCK Signal 5 N C Not connected do not use 6 TDO ALT JTAG TDO Signal 7 TDI ALT JTAG TDI Signal Table 50 General JTAG Header Pinouts NT107 0272 Issue March 9 2005 www nallatech com 127 FPGA Configuration NALLATECH Description 8 TRST ALT JTAG TRST Signal 9 TMS ALT JTAG TMS Signal Table 50 General JTAG Header Pinouts Care must be taken when using this method to program a module Inadvertent programming of either the PSU Controller or Interface Boot proms on your Kit could render it inoperable or in extreme cases damage could occur 128 www nallatech com NT107 0272 Issue March 9 2005 NALLATECH The High Performance FPGA Solutions Company Part V Hardware Examples This part of the User Guide provides hardware example applications which enable you to start using the XtremeDSP Development Kit IV NT107
4. 208 importing data into MATLAB workspace from Chip SCOPE neier mp pata a a musquy apasha Pa aa 220 208 real time debug 2 215 OVeF VIEW eise EI P s 191 using the co simulation flow Rd n er 200 using the cosimulation 200 using the HDL Netlist Flow 2192 Overview 200 e 192 simulating the example 2222 192 XtremeDSP Development overview 3 Z ZBT SRAM 41 bus utilization 41 u an a uwa assis cycle times firmware Dra ri pra clock and control signals for ZBT bank 45 ZBT address signals ss 45 237 2 data signals eee 45 237 126 u retient neon 4l OVEN VIEW ustedes S STR MATRE RUE 41 ZBT SRAM to User FPGA interconnect 42 256 www nallatech com NT107 0272 Issue March 9 2005 Remarks Form We welcome any comments you may have on our product and its documentation Your remarks will be examined thoroughly and taken into account for future versions of this product XtremeDSP Development Kit IV User Guide 107 0272 Issue 09 03 05 Errors Detected Suggested Improvement Please send this c
5. XtremeDSP Development Kit IV User Guide Index analyzing the design sse 171 creating the ICON and 164 manually instantiating ICON and ILA cores 169 OVErVIEN 164 connecting a JTAG download 163 OVENVIEW P 163 m 18 clock sources trn oriri 22 external clock input MCX connector 22 on board 105MHz crystal programmable oscillators clocks nere channel irrena aa ADC and DAC clocks channel clock configuration fiFmWAare u u u u u YY clock selection and jitter timing constraints clock skew front end configuration clocking the ADCs and 73 IARE Ware AT cis tern wizard aaa 71 key FEATURES DIME II system ua 63 maximum clock input to ADC devices available clocks eene 63 operation EE STORES 20 external clock input via module MCX connection 66 19 eU 70 ADIO signal E 115 fixed external oscillator 66 Adjacent No a 79 inter FPGA clock 68 Adjacent Out bus 79 clock feedbacks for de skewing and clock
6. Configuration u u u uuu u 2 FPGA assess cesta ete 123 Configuration Options M 123 Module and Device Numbering within 123 Key Steps for FPGA Configuration l a 124 Using the FUSE APIs or DIMEscript 124 Access through JTAG 2222222 125 FPGA Configuration using the FUSE Probe Tool 125 FPGA Configuration using the FUSE 125 FPGA Configuration using DIMESscript es 126 FPGA Configuration using General JTAG Chain 126 Part V Hardware Examples i 129 Feature Examples u u u Q 131 iiaee Uleni o p Simple ADC Hookup Example Example OyervieW usual nuqa aa 131 SOUN C 131 implementati 131 R nning the Example Reo tU REIN EE Usnu niii 132 ADC ta DAC Examples uu 135 viii www nallatech com NT107 0272 Issue March 9 2005 Example aun ua Sana y hD Saa esiste quqayay hrs 135 BOUNCE 135 Implementation 135 Running the Example u 35 Host Interface Example 138 Example OVi
7. xiii using the Kit outside the board case 102 product registration ra programmable clocks V programmable power supply voltage controlled oscillator 32 NT107 0272 Issue March 9 2005 www nallatech com 255 writing to Interface FPGA from User FPGA 116 X Xilinx EDK support eere 179 design notes eene entente tentent tentem 181 qi MEE 181 using the ZBT as a 181 support m EDK example eerte connect via XMD 185 load the FPGA design with FUSE 184 start the software debugger 186 rd 181 Xilinx Impact Support serene 153 Cal m 155 set up a connection 155 connecting download 155 launch impact 157 open card to enable power supplies 155 Xilinx ISE support a u common settings 7 synthesis and implementation settings 149 Xilinx System Generator support 189 Chipscope use in System Generator 208 Chipscope Pro
8. 0 for j 0 j lt 256 j if WriteData j ReadData j printf error if error 0 printf else printf Close the card viDIME_Close viHandle DIME CloseCard hCardl Closes down the card IlFinally the last thing that should be done is to close down the locate DIME CloseLocate hLocate printf getchar return 0 With this handle data is then transferred and then read back to the host using functions such sa viDIME_DMAWrite Finally a simple check is carried out to ensure that the readback data matches the written data Close down the viDIME handle to freee resources on the host Then close the card handle to free allocate resources Relevant Application Notes There are a number of relevant application notes on the supplied CDs with additional examples This section lists the application notes that may be of interest with a brief description of their contents 146 XtremeDSP Kit Ping Example Provides another example of building a host interface to a design on the main User FPGA XtremeDSP Kit Analog Capture Provides an example of loading data to memory in the design where stimulus from the DACs is captured via the ADCs and read back to the host This example also makes use of the FUSE Toolbox for MATLAB which allows the FUSE API to be used directly within MATLAB scripts ZBT Controller XtremeDSP Kit ZBT Design www nallatech com Gives details
9. XtremeDSP Development Kit IV User Guide NT107 0272 Issue March 9 2005 user 0 1 pitch pin headers refer to the features section Digital on page 49 JTAG headers refer to the features section Board and System Level Monitoring Capabilities on page 83 clocking options refer to the features section Clocks on page 63 temperature sense capabilities refer to the features section Board and System Level Monitoring Capabilities on page 83 www nallatech com 7 XtremeDSP Development Kit IV Overview A NALLATEC Y FPGA Solutions Company 8 www nallatech com NT107 0272 Issue March 9 2005 NALLATECH XtremeDSP Development Kit IV User Guide The High Performance FPGA Solutions Company Section 2 Introduction to Nallatech Systems and Solutions In this section Introduction Motherboards and Modules DIME II Standard FUSE MATLAB DIMEscript DIMEtalk 2 1 Introduction Nallatech provides professional low risk high performance FPGA computing solutions for customers challenging applications Our customers benefit from the advantages Nallatech solutions provide with the reassurance that they are using a complete solution from a trusted supplier with over ten years experience in FPGA systems technology This is backed by a committed team worldwide who are dedicated to delivering world class product solutions customer service and support to a global customer base 2 2
10. 99 Power Supply TEDS 101 102 External Ole CEPS 104 Enabling Power Supplies at using External Power Supply and NT107 0272 Issue March 9 2005 www nallatech com vii CONNECTOFS SETTE RR T e I05 Environmental Specifications 107 M S 107 Operating Temperat res I07 Storage Temperatures u 107 Relative 107 Part lll System Level 109 Building a Host Interface HI o lli HardWare lli Design Partitioning Interface Communications Bus 113 E A E 114 Interface FPGA to User FPGA Interface 114 Implementing the Communications Mechanism 114 Communications Bus Protocol tenda eripe 115 Further Information on Interface Core u 118 SOWA 118 FUSE API Interlinks u 118 Interface 119 Part
11. FPGA Clock Period ns Clock Pin Location 25 Create Testbench Override with Doubles According to Block Settings Simulink System Period sec 1 324 J Generate Figure 140 System Generator Parameters for Chipscope Example I0 HDL Netlist Generation At this point the Xilinx System Generator software calls both the Core Gen erator and Chipscope generator to create the netlist and cores The CORE Generatortm is used to generate the Sine Cosine table and Counter netlists Chipscope Generator is called to create an Internal Logic Analyzer ILA core and an ICON core to communicate with the Chipscope Pro software via the JTAG port 11 Generate Programming file Once the System Generator generates the file successfully navigate to your SYSGEN examples chipscope netlist directory and double click on clk file in order to open Xilinx Project Navigator In Project Navigator highlight chip clk wrapper structural under the Sources in Project window Under the Processes for Source window right click on Generate Programming files and select Properties For the XtremeDSP Development Kit IV the following parameter needs to be setup Properties gt Startup Options gt FPGA Start Up Clock gt JTAG Clock Set up the appropriate parameters if a different board is used Generate the bitstream by double clickin
12. Figure 84 Programming Dialog Click OK to start the programming You will see the operation being executed 160 www nallatech com NT107 0272 Issue March 9 2005 NALLATECH The High Performance FPGA Solutions Company Part VIII Chipscope ILA Support This part of the User Guide provides details on how to use the Xilinx Chipscope ILA Tool in conjunction with the XtremeDSP Development Kit IV NT107 0272 Issue March 9 2005 www nallatech com 161 NALLATECH erformance FPGA Solutions C 162 www nallatech com NT107 0272 Issue March 9 2005 NALLATECH XtremeDSP Development Kit IV User Guide Section 20 Chipscope ILA Support In this section Introduction Support for the Xilinx Chipscope ILA Tool How to Establish a Connection Using Chipscope with the XtremeDSP Development Kit IV 20 1 Introduction Xilinx supply an optional tool called Chipscope Pro which is not included in the Kit However details of its use are included here as some users may have access to Chipscope and may wish to use it on the Kit This section provides information on using Chipscope through a worked example that is included the XtremeDSP Development Kit IV CD in the folder CD ROM Drive Examples chipscope_example Full details on the Chipscope tool are provided in the Chipscope User Guide supplied with the product Please refer to this User Guide for more details on the use of Chipscope Note that deta
13. UserDefined Set Oscillator Frequencies 50000 SYSCLK Frequency in Khz DSPCLK Frequency in Khz PIXCLK Frequency in Khz FIFOs LEDs Resets Oscillator Frequencies 0 00000000 10 00000000 Nallatech BenADDA IV Virtex Virtex IV 4VSX35 Words to Transfer Current Address Write Data 1 10 00000000 Read Data Linear Sequence Table Size Clear to zero 32 Session Log Console benone card opened Bitfile D wip BenADDA_IV_Tests Examples edk_example implementation download bit assigned to benone card benone Sys Clock Set to 120 0MHz benone Sys Clock Set to 50 0MHz Virtex IV 4 5 35 on the Nallatech BenADDA IV Virtex4V3X35 FF668 on the benone card has been configured Figure 106 EDK Example Assigning download bit File Set the Oscillators to 50Mhz i e 50000 in the FUSE Probe Tool Right click on the XC4VSX35 and select to configure it You will see the result in the main session log as shown in Figure 106 on page 184 Finally toggle the resets to the design Check and then uncheck both the System Reset signal to ensure proper startup of the design At this point you will see the LEDs numbers and 2 on the module toggling through a short sequence showing that a test program is running on the Kit www nallatech com 107 0272 Issue March 9 2005 NALLATECH XtremeDSP Development Kit IV User Guide
14. Boundary Scan Slave Serial SelcctMAP Desktop Configuration 4 ID 02 Versace 0 501 Added Device 1102 3 Magutactuw y ID 921440 Vernon 4 1T Ranting D dara ach 14409 bnd INFO MPACT 501 Addad Device xP bil raconta For press F1 Contig z ston Mose Boundary Scan Paralel Figure 82 Showing Detected Devices www nallatech com NT107 0272 Issue March 9 2005 ANA High Perfo LLATECH XtremeDSP Development Kit IV User Guide FPGA Solutio Impact will then prompt for configuration files for each device in the chain It is not necessary to assign configuration files at this time as this can be carried out manually Please note that the XC95144XL CPLD should not be programmed and nor should XCI8V02 PROM unless a manual firmware update is being carried out Setting Cable Speeds One aspect to the support for different cables is that different configuration rates are supported by different cable leads The Parallel IV pod can support a ribbon cable header a flying lead header The ribbon cable due to it s nature can operate at a higher rate than the flying lead connections Therefore if you are using flying leads ensure that a suitable rate is being selected Go to the main menu in Impact Edit gt Preferences This brings up the dialog shown in Figure 83 on
15. INTERFACE gt MAIN USER FPGA FPGA Virtex 4 4 5 35 USB or PCI 10FF668 CLOCK FPGA Virtex II XC2V80 4CS1 44 Figure 33 Reset Distribution The Virtex 4 FPGA resets are controlled from the Interface FPGA via FUSE software Both of these resets are active low One or both reset signals can be used within an FPGA design NT107 0272 Issue March 9 2005 www nallatech com 59 Resets 60 9 3 RSTI has been renamed to ONBOARD_RESETI has been renamed to SYSTEM_RESETI Firmware Please note that reset signals are described here as the ONBOARD_RESETI and the SYSTEM_RESETI The l suffix indicates that these are active low signals Also note that the naming here has been changed slightly from that used in the DIME II standard This is for clarity when using the Kit When designing Firmware if you are using DCM in the Virtex 4 in your design it is recommended that you use an inverted version of either the ONBOARD RESETI or SYSTEM RESETI to reset the DCM Use the locked signals from DCMs to generate the reset to the rest of your design Figure 34 on page 60 provides an example of this GND RESET lt not IBUFG Instantiation for CLK IN UO IBUFG IBUFG port map I gt CLKi FB 9 gt CLKIN OSC l BUFG Instantiation for CLKFB UO BUFG BUFG port map I 7 CLKFB OSC gt CLK OSC DCM Instantiation f
16. Write 12400000000 1000000000 900000000 600000000 600000000 000000000 00000000 00000000 0500000000 1000000000 1000000000 1000000000 1000000000 000000000 0 00000000 000000000 000000000 0500000000 000000000 000000000 10500000000 mannnannn Words to Trantter Current Address 000000000 White Data Linear Sequence Clear 10 2510 Table Size NT107 0272 Issue March 9 2005 Figure 94 Initial FUSE Probe Tool Window www nallatech com 171 Chipscope ILA Support NALLATECH The High Performance FPGA Solutions Company 172 Once the FUSE Probe Tool has appeared the card should be opened for access To do this click on the Open Card button and select the appropriate interface i e PCI or USB Frust Probe file Eat Hun Configuration Card Conto System 10200000000 10500000000 Locate Dialog to select interface type i e PCI or USB to look for cards in the host 2 A A FOS LEOS Resets Oscillator Frequencies 000006000 0 0000 1000000000 1000000000 000000000 1000000000 0000060600 000000000 0400000000 000000000 000000000 000000000 000000000 00000000 Current Address _ wwom Linear Sequence Open Card Button Size system Figure 95 Open Card and Select Interface FUSE then detects all cards i
17. gt XQ veo pm h Denone v PCI PROM 33V PCIPROM Power Slot 0 Notice that the ledsnake bitfile is shown as assigned here gt gt ee E gt E gt LEOS Resets Osctiatar Frequencies Elle Ean Run Contguraton Care Commo System x el l 5 lt Vintexavsx35 7668 lolxi Read 000000060 benone Nallatech BenADDA4V Virtex 0500000000 600000060 Virtex IV AVSX35 0400000000 000000000 00000000 1000000000 Words lo Tranator god 0 00000000 Datas 000000000 10000000000 Datas 00000000 00000000 0400000000 0400000000 Curt Address pr00000000 050000000 000000000 031912 100000000 0000990000 1090000060 Write Ox Read Data J O81814 10x00000000 1 02115 000000000 0 06000000 Oaar 10200000000 00090000 Datat7 000000000 0100000000 Linear Sequence Clear to zero 04 16 1000000060 1 021219 100000000 950005000 Oata70 0x00000066 60666000 Table Size P 0221 1000000000 000000000 041422 0400000000 0 00000000 04923 000000000 0400000000 10200000009 10170009000 _ fena 0 25 000000000 1000000000 1000000000 1000000000 Data27 0000660 000000000 79 000000009 1000000000 03279 000000000 10500000000 004220 0900000000 10000000000 D34331 1000000000 10 00000000 Session Log console benone Sys Clock Set 50 0
18. 2 80 4 5144 and XC4VSX35 10FF668 in the Kit can configured via a variety of methods Using the FUSE Probe Tool Using DIMEScript Using FUSE Software APIs Using an external JTAG programmer via the General JTAG chain and pin header 16 1 1 Module and Device Numbering within FUSE When configuring FPGAs using FUSE it is necessary to use Module ID and Device ID numbers to target the correct FPGA for configuration as the Kit has multiple FPGAs The only exception to this is when using the FUSE Probe Tool where the software allows FPGAs to be targeted graphically Each FPGA must be uniquely identified in order that the user can target the correct bitfile to each device The system used for identifying FPGAs and also any PROMs in the general JTAG chain consists of a module ID which identifies the module the FPGA is on and a device ID which identifies the device within that module The module ID and device ID are determined by the order in which the devices are detected and how many modules and devices are present The module ID always starts at 0 and increments for each additional module to be configured therefore the maximum module ID depends upon the number of modules fitted In the case of the XtremeDSP Development Kit IV there are effectively two modules Module 0 is the BenADDA DIME II module and Module consists of the other components in the JTAG chain that reside on the BenONE Kit Motherboard The device ID works
19. DesiredFrequency is the requested frequency in MHz When this function is called it will try and set the selected clock to the desired frequency If the desired frequency is not supported then the actual frequency set will be reported This is because the programmable oscillators used in the 76 www nallatech com NT107 0272 Issue March 9 2005 NALLATECH XtremeDSP Development Kit IV User Guide Kit only support a specific set of frequencies Figure 48 on page 77 shows an example of the how to control the clocks via the C C FUSE API Change the oscillators double ActualFrequency Try and set oscillator 1 the system clock to 41 23456MHz DIME SetOscillatorFrequency hCard1 1 41 23456 amp ActualFrequency printf Actual frequency is f n ActualFrequency Figure 48 Getting Information on the Located Cards Please note that the CLKC net is not from a programmable oscillator as it is connected to a socket to support a crystal oscillator Calls to set CLKC may however still return a value to say the control register has been set to request a specific frequency The FUSE API Developers Guide included on the FUSE CD provides further details on this function NT107 0272 Issue March 9 2005 www nallatech com 77 TN NALLATECH Performance FPGA Solutions C 78 www nallatech com NT107 0272 Issue March 9 2005 NALLATECH XtremeDSP Development Kit IV User Guide
20. Xilins ChipS cope Core mask link This block inserts ChipScope Pro ICON and ILA cores Parameters Number of Trigger Ports l WW Display Options for Trigger Port Number of Match Units for Trigger Port Match of Trigger Pot D Basic with Edges Use Trigger Ports as Data Number of Data Ports 2 Depth of Capture Buffer 51 2 Ghipsoope Use SRL1Bs when possible OK Cancel Help Apply Figure 136 Parameterized Chipscope GUI Connect the Chipscope Block The signal used to trigger Chipscope is the counter output The two bus ses to probe are the sine and cosine from the Sine Cosine table Connect the signals appropriately as shown in Figure 137 on page 212 Fix 8 7 i tpt double Sine Gateway Qut SineCosine os pt double Cosine Gateway Out3 Counter ChipScope Figure 137 Connecting the Chipscope Block www nallatech com NT107 0272 Issue March 9 2005 NALLATECH XtremeDSP Development Kit IV User Guide The High Performance FPGA Solutions Company 8 Prepare for JTAG download Now that the design is fully implemented and simulates correctly the next step is to prepare it for connection to the hardware target Although it can work on any hardware plat form the process is described for the XtremeDSP Development Kit IV Two pins should be locked down in this design the trigger pin to connect it t
21. the card Enable the resets Reset the circuit and clear the PCI FIFOs for the card DIME_CardResetControl hCard drONBOARDFPGA drENABLE 0 DIME CardResetControl hCard drSYSTEM drENABLE 0 DIME CardResetControl hCard drlNTERFACE drTOGGLE 0 Set the clocks DIME_SetOscillatorFrequency hCard 80 000 amp ActualFrequency printf ClkA Actual frequency is f DIME_SetOscillatorFrequency hCard 2 40 000 amp ActualFrequency printf ClkB Actual frequency is DIME_SetOscillatorFrequency hCard 3 50 000 amp ActualFrequency printf ClkB Actual frequency is Configure the FPGAs Now configure the modules primiary FPGA with the bif file DIME_ConfigDevice hCard Filename2 ModuleNumber SecondaryFPGA DeviceNum 0 0 Now configure the modules primiary FPGA with the bif file DIME_ConfigDevice hCard Filename ModuleNumber PrimaryFPGADe 0 0 Disable the resets DIME CardResetControl hCard drONBOARDFPGA drDISABLE 0 DIME CardResetControl hCard drSYSTEM drDISABLE 0 Sleep 500 Enable the resets DIME_CardResetControl hCard drONBOARDFPGA drENABLE 0 DIME_CardResetControl hCard drSYSTEM drENABLE 0 DIME CardResetControl hCard drlNTERFACE drTOGGLE 0 Sleep 500 Disable the resets DIME CardResetControl hCard drONBOARDFPGA drDISABLE 0 DIME CardResetControl hCard drSYSTEM drDISABLE 0 Sleep 500 Give it a couple second for the embedded proc to sort
22. 22 Analog Performance 22 ADC Front End u u 23 ass 27 Timing Constraints u e 28 NT107 0272 Issue March 9 2005 www nallatech com v 29 29 DAC Archit et rez u a ananman aQ EA HA UR 30 HardWare ceca ty en care 31 PLL Clock Multiplier oti aab bf uuu 31 DAG Modes of GR Cyr ce Rob arses 32 Analog DAC CDS unun uha 33 Nuit HEE u u 34 DAC Clocking s s n aa uq s n q aq na uu 36 FIRMWARE sa nn asas uiia 37 Two s Complement vs Offset Binary 38 Timing Cos UNES sposato ierit an ieies eiiie eai iei e niari eioi 39 39 41 nt educti nmu 41 Hardware eorom tomb en ehe did utm e 42 ZBT SRAM Clocking 47 u EN 47 47 49 49 Hardware R pone 50 User 1 O Header Interfacing 50 P Link Bus Header uuu y y uqu uma 50 Adjacent Bus Header 50
23. A simple loop is carried out to create some test data in the WriteData array The first step is to obtain a handle to the cards detected in the system by FUSE This is done using the DIME LocateCard function which returns a handle It is important to note here that the PCI interface type has been selected If you wish to detect cards on the USB interface this should be changed dlUSB www nallatech com NALLATECH High Performance FPGA Solutions Company NT107 0272 Issue March 9 2005 NT107 0272 Issue March 9 2005 ATECH GA Solutions Company XtremeDSP Development Kit IV User Guide the details for each card detected for LoopCntr 1 LoopCntr lt NumOfCards LoopCntr printf Details of card number d of d printf The card driver for this card is a s printf The cards motherboard type is d IAt this stage we now have all the information we need to open card up up the first card found To open the nth card found simple change the second argument to n hCardl DIME OpenCard hLocate dccOPEN NO OSCILLATOR SETUP opens up card with default flags if NULL check to see if the open worked t printf Card Number One failed to open DIME_CloseLocate hLocate printf getchar return 1 Change the LEDs LEDs DIME ReadLEDs hCardl DIME WriteLEDs hCardl LEDs 1 printf LEDs now changed
24. Infer two registers process RST CLKBi begin if RST I then REGI lt others gt 0 REG2 lt others gt 1 elsif CLKBi event and CLKBi 1 then if REGI WR I then REGI lt 31 downto 0 end if if REG2 WR I then REG2 lt DATA 3l downto 0 end if end if end process The Interface to User FPGA Interface Core is now instantiated with generics set appropriately Please see application note NT302 0000 Spartan to Virtex Interface for more details on these generics This core is instantiated and then the interface side signal are connected to top level ports The user side signals are assigned to internal nets Note that DMA Sel is not used in this example as it is as sumed a single DMA channel is desired Note that the DMA channels are set by the DMA Sel and are purely for decoding the location of the burst data on the card Instantiate the FIFO that will be used to store burst of data This FIFO is used to demonstrate how to connect to the sv iface component In user designs the FIFO may be any other specific component that can receive data The FIFO data ports are connected to the DMA DATA port on the sv iface core It is important for the sake of interfacing that some measure of FIFO contents are fed back to the sv iface component to indicate when the FIFO is almost full Using the FIFO status along with the control signals from the interface core FIFO read and write ena
25. NALLATECH XtremeDSP Development Kit IV User Guide ZBT Address Signals for ZBT Bank A Signal Name ZBTA_A lt 0 gt User FPGA Signal Name XC4VSX35 10FF668 PIN No ZBTA A II User FPGA 5 35 10 668 PIN No ZBT A I Y3 ZBTA lt 12 gt ACA ZBTA lt 2 gt ADI3 ZBTA lt 3 gt AB3 ZBTA A 3 Y2 ZBTA lt 14 gt AC3 ZBTA lt 4 gt ZBTA lt 5 gt ZBTA lt 5 gt ADI2 ZBTA lt 16 gt AC2 ZBTA lt 6 gt ZBTA lt 7 gt ZBTA lt 17 gt ZBTA lt 18 gt ZBTA A 8 AB4 ZBTA lt 9 gt AF4 ZBTA lt 10 gt AD3 Table 63 ZBT Address Signals Pinouts Bank ZBT Data Signals for ZBT Bank A Signal Name User FPGA XC4VSX35 10FF668 PIN No ZBTA D 0 AC7 ZBTA lt gt AC6 ZBTA D 2 Y5 ZBTA D 3 AE4 ZBTA_D lt 4 gt AB7 ZBTA_D lt 5 gt AB6 ZBTA_D lt 6 gt AF6 ZBTA_D lt 7 gt AD4 ZBTA_D lt 8 gt 10 ZBTA_D lt 9 gt Y9 ZBTA_D lt 10 gt AE9 ZBTA_D lt l I gt AC8 ZBTA_D lt 12 gt AFIO ZBTA_D lt 13 gt AC9 ZBTA_D lt 14 gt AA8 NT107 0272 Issue March 9 2005 Table 64 ZBT Data Signals Pinouts Bank A www nallatech com 235 Pinout Information NALLATECH Signal Name User FPGA XC4VSX35 10FF668 PIN ZBTA_D lt 15 gt Y7 ZBTA_D lt 16 gt AB9 ZBTA_D lt 17 gt Y8 ZBTA_
26. Signal Name DIME II Connector PIN User FPGA XC4VSX35 10FF668 PIN No LBUS lt 10 gt 2 19 05 lt 11 gt T20 LBUS 12 5 21 LBUS lt 13 gt PBI6 T23 LBUS 14 PBI7 T24 LBUS 15 PBI8 T26 LBUS 16 PBI9 RI9 LBUS 17 PB20 R20 LBUS 18 2 R23 LBUS lt 19 gt PB22 R24 LBUS lt 20 gt PB24 R25 LBUS lt 21 gt PB25 R26 LBUS lt 22 gt PB26 PI9 LBUS lt 23 gt PB27 P20 LBUS lt 24 gt PB28 P22 LBUS lt 25 gt PB29 P23 LBUS lt 26 gt PB30 P24 LBUS lt 27 gt PB3I P25 LBUS lt 28 gt PB33 N20 LBUS lt 29 gt PB34 N23 LBUS lt 30 gt PB35 21 LBUS lt 31 gt PB36 N22 Table 53 Local Bus Pinouts 4 5 35 10 668 242 Adjacent Out Bus Interface Communications Signal Name DIME II Connector PIN User FPGA XC4VSX35 I0FF668 PIN No ADJOUT lt 0 gt PD29 R4 ADJOUT lt I gt PD30 R3 ADJOUT lt 2 gt R2 ADJOUT lt 3 gt PD32 RI ADJOUT lt 4 gt PD33 P7 ADJOUT lt 5 gt PD34 P Table 54 Adjacent OUT BUS Pinouts User FPGA XC4VSX35 10FF668 230 www nallatech com NT107 0272 Issue March 9 2005 NALLATECH XtremeDSP Development Kit IV User Guide Signal Name DIME II Connector PIN User FPGA XC4VSX35 I0FF668 PIN No ADJOUT lt 6 gt PD35 P5 Table 54 Adjacent OUT BUS Pinouts User FPGA XC4VSX35 10FF668 24 3 Adjacent Header J8 Signal Name DIME
27. FPGA Clock Period ns 9 5 Override with Doubles According to Block Settings Simulink System Period sec 1 324 Figure 113 QAM System Generator Options Set the compilation target at HDL Netlist Set the part as Virtex 4 XC4VSX35 OFF668 if using the XtremeDSP Development Kit IV Note the FPGA Clock Period setting 9 5ns in this case as this determines how fast the design is capable of running if using a free running clock The dialog box should then be similar to that shown in Figure 113 on page 195 5 Once these parameters have been set click generate to start the System Generator flow This will create the VHDL for the design and will also create a Xilinx ISE Project Navigator File for the next stage of creating the implemented design on the FPGA itself 6 Now open the ISE Project Navigator file that has been created The file will be located in the folder you selected as the target directory The default is ples system_generator_examples QAM sygenqam1 6_work Open the file sysgenqam1 6_dplr_clk_wrapper npl within Xilinx ISE Project Navigator as shown in Figure 114 on page 196 NT107 0272 Issue March 9 2005 www nallatech com 195 System Generator Support NALLATECH IEEE The High Performance FPGA Solutions Company 196 yew Project douce Process Window DEUO BRK
28. System Clocks on page 63 Scope Please note that this User Guide provides information exclusively on the XtremeDSP Development Kit IV It does not provide details on previous versions of the XtremeDSP Development Kit Comments and Suggestions At the back of this book you will find a remarks form We welcome any comments you may have on our product or its documentation Your remarks will be examined thoroughly and taken into account for future versions of Nallatech products xvi www nallatech com NT107 0272 Issue March 9 2005 A NALLATEC XtremeDSP Development Kit IV User Guide The High Performance FP GA Solutions Company NT107 0272 Issue March 9 2005 www nallatech com xvii NALLATECH erformance FPGA Solutions C xviii www nallatech com NT107 0272 Issue March 9 2005 NALLATECH The High Performance FPGA Solutions Company Part L Introduction This part of the User Guide provides an introduction to the XtremeDSP Development Kit IV and outlines its key features and functionality NT107 0272 Issue March 9 2005 www nallatech com NALLATECH erformance FPGA Solutions C www nallatech com NT107 0272 Issue March 9 2005 NALLATECH XtremeDSP Development Kit IV User Guide The High Performance FPGA Solutions Company Section XtremeDSP Development Kit IV Overview In this section i XtremeDSP Development Kit IV Key Features 4 XtremeDSP Development Kit IV Functional D
29. The High Perfo NALLATEC FPGA Solutions Company XtremeDSP Development Kit IV User Guide 4 Drag the generated block into the mac fir xtremedspkit demo model Connect an output gateway block and another scope as shown in Figure 131 on page 207 mac fir xtremedspkit demo File Edit View Simulation Format Tools Browser mac fii stremedspkit demo d System Generator Drag the generated block Low Pass Filter LowPass Slider into the model LowPass double Sine Wave MAC FIR double Noise Source fir xtremedspkit hweosim Create another gateway out block and another scope Figure 131 Adding the Runtime Cosimulation Block to the Model 5 Double click on the mac_fir_xtremedspkit_demo_hwcosim block to bring up the control dialog shown in Figure 132 on page 207 Block Parameters mac_fir_xtremedspkit_demo hwcosim MremeDSP Kt Hardware Cosimulation mask Cosimulation block for the XtremeDSP kit development board Parameters Bt File Name dupdate MAChir netlist xtremedspkit_demo ck wra 5 Clock 5 Stepped Cancel Help Figure 132 Hwcosim Parameters These block parameters control the selection of the bitfile which is set automatically during the gener ation and also the selection of the clock In this case make sure that the s
30. WEN RST gt RST D gt IN Q gt FIFO_OUT FIFO_STATUS gt FIFO_STATUS FULL gt open FIFO_EMPTY gt FIFO_EMPTY gt CLKBi FIFO data FIFO_IN lt DMA_DATA DMA_DATA lt FIFO_OUT when DMA_DIRECTION l else others gt 7 Create a fifo almost full signal FIFO_AFULL lt FIFO_STATUS 3 and control FIFO_REN lt when ENABLE l DMA_DIRECTION l and l and FIFO_EMPTY 0 else 0 FIFO WEN lt when ENABLE l and DMA_DIRECTION 0 DATA AVAILABLE l and FIFO_AFULL 0 else 0 DMA REN lt FIFO WEN Create a registered version of some of the control signals process CLKBi RST begin if RST I then DMA WEN lt 0 elsif CLKBi event and CLKBi 1 then DMA WEN FIFO REN end if end process Two registers control REGI WR lt I when WRITE STROBE I and ADDRESS 3 downto 0 00 o else 0 REG2 WR lt l when WRITE_STROBE l and ADDRESS 3 downto 0 011 else 0 REGI RD lt when READ_STROBE l and ADDRESS 3 downto 0 0010 else 0 REG2 RD lt when READ STROBE l and ADDRESS 3 downto 0 0011 else 0 to the DATAbus when reading either register depending upon selection DATA lt REGI when REGI_RD l else others gt Z DATA lt REG2 when REG2 RD l else others gt Z
31. clock or disable part of the function until the design comes back into the allowed operating range The specific action taken is dependant on the user design Extreme care should be taken with the temperature levels of the FPGA Commercial grade silicon has a junction temperature range of 0 C 85 C and 40 C 100 C for Industrial grade silicon Incorporating the ALERTI signal into an FPGA design provides thermal protection to the FPGA The ALERTI signal should have a pull up instantiated in the FPGA design It is recommend that for any high power FPGA designs a heat sink should be fitted to the FPGA FUSE Probe Tool Monitoring Plug in The XtremeDSP Development Kit IV is supplied with a version of FUSE that provides a software GUI called the FUSE Probe Tool This tool now has a plug in to facilitate monitoring of the Kit s temperature and voltages v To start the FUSE Probe Tool Monitoring Plug in use the following procedures l To open the FUSE Probe Tool either click on the Nallatech Icon on the taskbar or go to the Start menu and then click on Progams gt FUSE gt Software gt FUSE Probe This will launch the FUSE Probe Tool shown in Figure 51 on page 85 Double click the Temp Sensor button to start the temperature GUI Y FUSE Probe Filo Edn View Run Care Control System Help benone Nallatech BenADDA4V Virtex 4VSX35 Words to Transfer Curren
32. 22 1 Introduction Xilinx have developed a tool called System Generator which may be included as an evaluation version in the XtremeDSP Development Kit IV pack Alternatively contact Xilinx for details on the availability of evaluation versions of System Generator This section provides information on using System Generator through worked examples that are also included on the Kit CD in the folder CD ROM DrivelExamplesWystem generator examples If you have selected to install the examples locally then this folder will also be present on the PC Full details on the System Generator are provided through online help accessible within MATLAB Also please refer to the System Generator documentation for further details on the use of System Generator Details of System Generator are included here as some users may wish to use it on the XtremeDSP Development Kit IV Three main examples are included here to show the standard HDL netlist flow when using the Kit QAM example cosimulation flow MAC FIR example and finally an example of using Chipscope ILA with System Generator 22 2 Overview of System Generator System Generator is a system level modelling tool that facilitates FPGA hardware design and extends Simulink in various ways in order to provide a powerful modelling environment that is well suited to hardware design The tool provides high level abstractions that are automatically compiled into an FPGA at the push of a button The tool also prov
33. Bandwidth KBytes Sec 120000 110000 100000 90000 70000 60000 50000 40000 30000 20000 10000 0 32 bit amp 64 bit PCI Bandwidth Performace ree pe AA 0 20000 40000 60000 80000 100000 120000 140000 160000 180000 200000 220000 240000 260000 280000 Number of Words Transfered Read Max Windows 2000 64 bit Write Max Windows 2000 64 bit Read Max Windows 2000 32 bit Write Max Windows 2000 32 bit Figure 71 PCI Interface Performance Please note that the 32 bit PCI interface is supplied in the Kit www nallatech com NT107 0272 Issue March 9 2005 NALLATECH The High Performance FPGA Solutions Company Part IV FPGA Configuration This part of the User Guide provides information for configuration of the FPGAs in the XtremeDSP Development Kit IV NT107 0272 Issue March 9 2005 www nallatech com 121 NALLATECH erformance FPGA Solutions C 122 www nallatech com NT107 0272 Issue March 9 2005 NALLATECH XtremeDSP Development Kit IV User Guide Section l6 FPGA Configuration In this section FPGA Configuration Options Key Steps for FPGA Configuration FPGA Configuration using FUSE Probe Tool FPGA Configuration using FUSE APIs FPGA Configuration using DIMEscript FPGA Configuration using General JTAG Chain 16 1 Configuration Options User FPGAs
34. Standard DIME II hardware makes use of modular power supplies to provide the voltages required by specific modules There are two types of power modules the Fixed Power Supply FPS unit and the Programmable Power Supply PPS unit Details of the two types of modules are provided later in this section In addition to the power modules the Kit hardware uses a number of linear regulators to generate the voltages required by some of the devices on the motherboard itself Figure 61 on page 99 shows the voltage generation and use in the Kit hardware XtremeDSP ZBT 1Development Kit 4 FPS Linear Regulator i 3 3 1 6 PSU D Standalone Power R V 4 I O to Analog Connector 5v 12V E and 12V Clock PPSDCDC 1 2 6A PSU 1 User FPGA XC2V80 V 4 FPGA Cores PCI Connector IADCs Xilinx Virtex 4 XC4VSX35 10FF668 5v 12 1 Disk Drive Connector 5v I2V FPS Linear Regulator 2 5v PSU A Vccaux Spartan ll Interface FPGA Linear Regulator 2 5 1 2 Spartan II Interface Core Figure 61 On board Power Set up There are three FPS units on the Kit hardware The first FPS Power Supply B PSU_B provides 3 3V to the side banks i e the DIME II Local Bus of the main User FPGA and the two ZBT devices on the BenADDA DIME II module The FPS uni
35. and select the osc clock 2v80 bit file Right click on the Virtex 4 XC4VSX35 10FF668 in the card browser and select Assign Bitfile In the fle window that appears browse to Examples system_generator_examples QAM 16 work and select the sysgenqaml6 dplr clk wrapper bit file Note that if you have not generated this bitfile yourself though ISE in the previous steps a pre generated bitfile is provided in Examples system_generator_examples QAM bitfiles called sysgenqaml6 dplr 4 5 35 I OFF668 bit Right click on the Virtex2 2v80 in the card browser and select Configure Device to configure the FPGA Right click on the Virtex 4 XC4VSX35 in the card browser and select Configure Device to configure the FPGA NT107 0272 Issue March 9 2005 www nallatech com 197 System Generator Support NALLATECH E The High Performance FPGA Solutions Company TY FUSE Probe File Eat View Run Configurason Card Control System Help tech VirtexaVSX35 660 16500000000 00000000 benone Nallatech BenADDA4V Virtex VOO osc clock 2 90 bit 1000000000 00000000 000000000 0 00000000 Virtex IV 4VSX35 BB Nattatech Denone 000000000 00000000 3 SV PCIPROM 000000000 1000000000 33V POPROM 000000000 000000000 Power Control Slot 0 0 00000000 000000000 F 000000000 000000000 000000000 1000000000 000000000 01000000000 000000000 000000000 px0000
36. 21 3 2 Connect via then used to connect to the design for the purposes of debugging From within XPS go to tools and the click on XMD XMD will then connect to the chain and then the 405 0 in the main User FPGA design The successful connection is shown in Figure 107 on page 185 IR Length Part Name 09608093 8 xc95144x1 05025093 8 XC18UG2 05025093 8 18002 02088093 18 RC4USK35 61616693 6 Assuming Device No 4 contains the MicroBlaze system Connected to the JTAG MicroBlaze Debug Module lt MDM gt No of processors MicroBlaze Processor 1 Configuration No of PC Breakpoints No of Read Addr Data Wa No of Write fiddr Data Matchpoints 1 Instruction Cache Support Data Cache Support JTAG MDM Connected to MicroBlaze 1 Connected to mh target id Starting GDB server for mb target Cid gt at TCP port no 1234 Figure 107 Successful XMD Connection NT107 0272 Issue March 9 2005 www nallatech com 185 Xilinx Embedded Developer s Kit EDK Support A NALLATECH The High Performance FPGA Solution 21 3 3 Start the Software Debugger Once XMD has successfully connected the software debugger can be started In XPS go to tools and then Software Debugger m Figure 108 Software Debugger The software debugger starts showing the main code It is now necessary to connect the software debugger to the TCP port o
37. Click on the Card Menu and select the USB interface to detect cards on A list of detected cards is dis played Click on the selected card Click on Update Firmware Programming should take approximately between 18 and 22 minutes to configure via USB although this time depends upon the USB configuration The firmware change is implemented the next time the power is cycled Converting from PCI Firmware only to 5VIO PCI and USB firmware This procedure can only be performed with the card plugged into a PCI slot as the USB firmware is not currently present in the board To convert from PCI firmware only to 5VIO PCI and USB firmware use the following procedures With the PC powered OFF insert your Kit in a PCI slot After the PC starts up open Windows Explorer and navigate to the firmware folder containing the Benone 32PCl USB exe program Double click on file Benone 32 USB exe to launch the application Click on the Card Menu and select the PCI interface to detect cards on A list of detected cards is dis played Click on the selected card Click on Update Firmware Programming should take approximately 10 to 20 seconds to configure via PCI The firmware change is implemented the next time the power is cycled NT107 0272 Issue March 9 2005 www nallatech com 225 Changing the Firmware NALLATEC Y FPGA Solutions Company 226 www nallatech com NT107 0272 Issue March 9 2005 NALLATECH The High P
38. JTAG Header Positions on Card General JTAG Header Flying Lead Connection This is a JTAG header that connects to the chain which runs through the standard JTAG pins on the User FPGA devices in the Kit and also some of the PROMs and CPLDs It is a standard 0 1 pitch header and can therefore support flying lead connections for the Parallel IV pods The header is shown in Figure 126 on page 203 123456789 Figure 126 General JTAG Connector J14 Pin Name Description 3 3V 3 3 Volts Supply 2 GND Signal Ground 3 N C Not connected do not use 4 TCK ALT JTAG TCK Signal 5 N C Not connected do not use 6 TDO ALT JTAG TDO Signal 7 TDI ALT JTAG TDI Signal 8 TRST ALT JTAG TRST Signal NT107 0272 Issue March 9 2005 Table 51 General JTAG Header 14 Pinouts www nallatech com 203 System Generator Support NALLATECH Description 9 TMS ALT JTAG TMS Signal Table 51 General JTAG Header J14 Pinouts Fitting a Parallel IV Ribbon Cable The header 24 on the motherboard allows a Xilinx Parallel IV ribbon cable to be plugged in Note that this header is in parallel with the General JTAG header 14 The connector is keyed and follows the pinout the datasheet supplied with the Parallel IV cable from Xilinx Please note that the Kit is not supplied with a Parallel IV ribbon cable This section provides information on how to connect the cable only if one is availa
39. Output Events Enable Outputs Output Events Release Write Enable Output Events Default 6 Release DLL Output Events Match Cycle Dnve Done Pin High 5 Defautt NoWat Defaut NoWat Figure 115 Setting the JTAG Startup Option www nallatech com NT107 0272 Issue March 9 2005 XtremeDSP Development Kit IV User Guide 8 Now click on Generate Programming File and select Run You will see ISE run through synthesis place and route and finally generation of the programming file Once this is complete ISE should be closed 9 Open FUSE to power up the board Select Start gt Programs gt FUSE gt Software gt FUSE Probe From FUSE select Card Control gt Open Card Then select USB for the interface click Locate Card At this point FUSE locates the BenONE Kit Motherboard and the top left corner of the FUSE Probe Tool displays the FPGA information as shown in Figure 116 on page 197 If you have the card plugged into a PCI slot then select to open the card via PCI Virtex2 80 i Virtex IV 4V8X35 E m Nallatech Ml sv PCI PROM M 33v PCI PROM BB Power Control Slot 0 Figure 116 Opening the Card in FUSE 10 Assign two bitfiles to the devices as follows Right click on the Virtex2 2v80 in the card browser and select Assign Bitfile the file window that appears browse to Exampleslsystem generator examples
40. PB36 N22 BUSY ADJOUT lt 0 gt PD29 R4 EMPTY ADJOUT lt I gt PD30 R3 RDI_WR ADJOUT lt 2 gt R2 AS 091 ADJOUT lt 3 gt PD32 RI RENI_WENI ADJOUT lt 4 gt PD33 P7 INTI ADJOUT lt 5 gt PD34 P6 RSTI ADJOUT lt 6 gt PD35 P5 Table 47 Interface to User FPGA Comms Signals Also DSP_CLK should be connected to CLK sometimes referred to as CLKB Interface General Bus Signal DIME II Connector User FPGA XC4VSX35 COMMSignal Name PIN No IOFF668 Pin No DSP_CLK CLKI PC3I 16 Table 48 Interface to User FPGA Clock Requirements 15 2 2 Interface Communications Bus The Interface Communications Bus is an important communications channel as it provides a path for data communication between the User FPGA the Interface PCI or USB FPGA and onto the host PC This bus has a pre defined communications protocol to facilitate communications to the Interface FPGA In order to communicate with the Interface FPGA from the User FPGA the User FPGA application design must incorporate a mechanism to communicate over this bus This communications mechanism can be implemented directly by the user in the design or by using Nallatech s drop in IP core the PCI to User FPGA Interface Core This core implements the Interface to User FPGA Comms communications mechanism and offers the user a simplified interface to which they can connect their own designs NT107 0272 Issue March 9 2005 www nallatech com 113 Building a Hos
41. The High Performance FPGA Solutions Comp any 6 2 Hardware The memory chips are driven exclusively by the User FPGA Figure 27 on page 42 illustrates the inter connect between the ZBT SRAM and the User FPGA CLK Bank A ZBT SRAM 512k x 32 Xilinx Virtex 4 User FPGA CLK XC4VSX35 IOFF668 Bank B ZBT SRAM 512k x 32 Figure 27 ZBT SRAM Interface Each ZBT device has advanced synchronous periphery circuitry and a 2 bit burst counter The SRAM is optimized for 10076 bus utilization eliminating any turnaround cycles for READ to WRITE or WRITE to READ transitions All synchronous inputs pass through registers controlled by a positive edge triggered single clock input The synchronous inputs include all addresses all data inputs chip enable synchronous clock enables write enables and Read Write The asynchronous inputs include the output enable clock and snooze enable and a burst mode that can select between interleaved and linear modes 42 www nallatech com NT107 0272 Issue March 9 2005 NALLATECH XtremeDSP Development Kit IV User Guide Clock and Control Signals for ZBT Bank A Signal Name User FPGA XC4VSX35 10FF668 PIN No ZBTA_CLK ABIO ZBTA_CLK_FB_OUT ACIO ZBTA_CLK_FB_IN 12 ZBTA_ADV ZBTA_CKEI AAI4 ZBTA CSI 0 4 ZBTA_CSI lt I gt ACI4 ZBTA_OEI ZBTA_WEI ADII Table 12 ZBT Clock and Control Signals Pinouts Bank A ZBT A
42. Toggle the System reset DIME CardResetControl handle drSyYS Gl 1 M drTOGGLE 0 Toggle the interface FPGA reset DIME CardResetControl handle drINTERFACE drToggle 0 Figure 36 Examples of Using DIME_CardResetControl For further details on resets please refer to the FUSE C C API Developers Guide on the supplied FUSE CD www nallatech com NT107 0272 Issue March 9 2005 NALLATECH XtremeDSP Development Kit IV User Guide Section lO Clocks In this section Introduction to the Clocking Structure Hardware Aspects Firmware Aspects Software Aspects 10 1 Introduction XtremeDSP Development Kit IV has a comprehensive and flexible clock management system The features available are as follows 105MHz crystal source on the module primarily to provide low jitter clock source for the analog devices An external clock input via one of the MCX connectors Two software programmable clock sources on the motherboard which can be set to a number of frequencies These provide two general purpose system clocks for user designs Single fixed oscillator socket on the motherboard Please note that no oscillator is provided and this socket allows for use of specific oscillators in user applications The clock nets on the Kit have been designed to eliminate clock
43. UO 65 Inter FPGA Clock reete baden oe loi HE ES A 68 ADC and DAC CIBC u anu qa ua aa 69 69 A Ae 70 Using the Virtex 4 a an na eie ia eost 70 Clocking the ADCs and 73 75 Setting the Clocks in FUSE nd 75 Listing of Calls in the FUSE to Set the Clocks 76 BUS SEF CEUES 79 MDE UN 79 iE 79 80 8 8 Board and System Level Monitoring 83 Introduction RR ERR RR RIEN 84 Temperature Monitoring 84 JTAG Chain 92 General JTAG Header tisse Pieve Deka ed nan 93 Par llel IV TAG Header nana 93 Configuration Status Monitoring eae 95 Power Specifications u 97 na aqha 97 External Standalone Power Supply 2 2111 97 PCI Power Specification 98 mig
44. 2 Hardware 10 2 1 Physical Clock Resources Figure 37 on page 64 shows where all the devices and inputs related to clock sources are on the actual hardware CLKC MCX Input Socket CLKC Fixed Connector not populated Oscillator Socket Input to Main User FPGA Input to Main User MCX External Clock Input to CLK FPGA ma S Module Oscillator Source 105 MHz crystal Input to CEKA and CLER Programmable Clock Drivers Input to Main User FPGA Figure 37 Physical Location of Clock Related Hardware 64 www nallatech com NT107 0272 Issue March 9 2005 NALLATECH XtremeDSP Development Kit IV User Guide The High Pe nce FPGA Solutions Co 10 2 2 Clocking Configuration Figure 38 on page 65 provides an overview of the XtremeDSP Development Kit IV clock structure CLKA 05 CLK KG pi ADC_CLKAI ADC_CLKB Clock FPGA GI OP AMP y 28 Virtex II ADC CLKBI XC2V80 DAC CLKA DI _ 212 DAC CLKB GIO N N A N35 N35 2319 N35 N35 94 TATI 94 ZBTA This net is the Main FPGA same physical Virtex 4 length as the XC4VSX35 ZBI CK ZBTA FB signal to the ZBT Memory lt This allows for de skewing ZBTB_CLK ZBTB_CLK_FB_OUT Z
45. 4 6 25 0 8 24 100 0 0 Table 11 Recommended Presale Ratio Settings 32 www nallatech com NT107 0272 Issue 1 March 9 2005 NALLATECH XtremeDSP Development Kit IV User Guide Input Data MODI Zero Divide by N ratio Rate stuffing 5 5 12 50 0 2 6 25 0 4 3 12 5 8 Table 11 Recommended Presale Ratio Settings 5 2 3 Analog DAC Outputs The Kit has five through hole MCX connectors that allow interfacing to and from the module All Analog Input and Output signals to the BenADDA DIME II module are conducted via four MCX connectors on the top of the module The fifth MCX connector provides an input source for an external clock Figure 21 on page 33 outlines the positioning of these connectors Qui External Clock DACI Analogue Input input iene ADCI Output Analogue Input ee Output Figure 21 MCX connectors Please note when the Kit is still in the blue board case the function of each MCX connector is labelled on the lid NT107 0272 Issue March 9 2005 www nallatech com 33 NALLATECH The High Performance FPGA Solutions Comp any Interfacing to MCX connectors via supplied cable The Kit is supplied with five cables that are suitable for connecting between the on board MCX connectors and a user input output BNC connections The cable assembly is shown in Figure 22 on page 34 Hea
46. 40 External MCX Clock Connector Input VOCM is set at 1 25V to comply with the typical VICM value for the Virtex ll FPGA using LVDS voltage specifications The Differential Driver Output Voltage for LVDS is specified as 250 450 typ 350mV It is therefore advised to limit the magnitude of the clock input signal at the MCX input to an unbiased sinewave input of 125mVpp 225mVpp The maximum input signal the Clock FPGA can accommodate is 3 3Vpp In order to ensure that the Clock FPGA cannot be accidentally blown the supply of the AD8131 is limited between to 3 3V Clock Signal Description Signal Name CLOCK FPGA Pin External Clock source via Op_Amp CLK_Op_Amp B6 GCLK6S Complement of External Clock CLK Ampl C6 GCLK7P source via Op Amp Table 25 Pinout information for Module MCX External Clock Input Module board 105MHz Oscillator An on board crystal oscillator that generates an LVTTL clock signal is supplied with the standard build of the BenADDA DIME II module The LVTTL clock signal generated by this oscillator is driven directly into the Clock FPGA This clock signal can then be used to derive the differential clock signals used to clock both the DACs and the ADCs The crystal oscillator supplied with the BenADDA DIME II module has a low jitter characteristic and its speed will be matched to the sampling frequency of the ADCs For the ADC AD6645 a 105 MHz crystal oscillator is supplied Clock Si
47. 61 ii S scope Of MANUAL xvi Spartan ll device eerte 6 system level design eerte 109 building a host IHI design partitioning eese II interface communications 113 designing with the FUSE 118 interface performance seen 119 interface FPGA to User FPGA interface core 114 further information on 118 implementing the comms 114 T temperature monitoring u using FUSE Probe using the FUSE DIME_ModuleControl DIME ModuleStatus DIME PPSStAtUs L inen teet tette temperature sensor signal datasheetu uy hp p e timing information eerte tenentes troubleshooting typographical considerations sss Xv Programmable Power 1 recommended power max for Kit U recommended specification user guide format xiii using the Kit in the board case user guide
48. A 29 lt 4 30 Chipscope ILA support e 161 36 Chipscope example 4 4 4 4 164 ha 37 www nallatech com 253 NALLATECH The High Performance FPGA Solutions Comp any 254 timing constraints 39 two s complement vs offset binary format 38 hardware analog DAC outputs modes of operation PLL clock multiplier key E banaa output configurations differential outputs using termination resistors 36 single ended DC coupling using op amp 35 Ml 29 digital firmware NardWar adjacent bus header 8 50 PLink bus header J10 user I O header introduction u asas DIME Il communication busses 80 DIME II standard uu nnn DIME II system clocks DIMEscript features n plici example network 0 21 E EMPTY neret 115 environmental specificat
49. Declare a signal for the internal clock signal produced by the DCM the clock module signal CLKBi std_logic Declare a signal for the locked signal from the clock module signal CLKB_LOCKED std_logic Declare delayed versions of some of the host interface control signals signal EMPTYdI EMPTYd2 std_logic signal AS_DSIdI AS_DSId2 std_logic control signal DMA_WEN std_logic signal DMA_REN std_logic control signal DMA_ENABLE std logic signal DIRECTION std logic signal DMA RDY std logic signal DATA AVAILABLE std logic signal DATA std logic vector 31 downto 0 Register control signal ADDRESS std logic vector 30 downto 0 signal WRITE STROBE std logic signal READ STROBE std logic signal DATA std logic vector 31 downto 0 Declare an internal version of the interrupt signal to the host interface signal INT std logic Declare the output reset signal from the host interface signal RST std logic Declare the inverted version of the external reset signal This is the active high version signal RST EXT std logic Declare and internal reset signal this is based on the locked signal from DCM in clock module signal RST INTI std logic data status control signal FIFO AFULL std logic signal FIFO std logic signal FIFO STATUS std logic vector 4 downto 0 signal FIFO
50. EW e aS ashaka qaa uama qes 138 a RON RR e 138 Impl mentation 138 Running th Example 139 Relevant Application Notes u 146 Part VI Xilinx ISE Support 147 Common ISE Settings 112222222222222 22 149 Synthesis and Implementation Settings 149 Synthesis Sere ARR 149 Implementation u y i Dra pe URS 149 Part VII Xilinx Impact Support 153 rU UMEN URN 155 lt C esse 155 Set up a Connection MAT a UE DA d 155 Connect a JTAG Download Cable u 155 Open the Card to Enable Power Supplies serene 155 Alternative Method of Enabling Power Supplies sss 156 Launch eR e MQ 157 Part ILA SUpport 161 Chipscope ILA Support 163 mau u mau a una 163 Connect JTAG Download 163 XtremeDSP Development Kit IV Chipscope Example 164 OVERVIEW 164 Creating the ICON and ILA tk ro nert teen 164 Manually Instantiating the ICON and
51. ILA Cores in your Design 169 Analyzing the Design 171 9 Part IX Xilinx Embedded Developer s Support I79 Xilinx Embedded Developer s Kit EDK 181 181 uie T NE T 181 NESS oM 181 Using the ZBT as Peripheral 181 XMD SUB PONE M 182 unu 183 NT 107 0272 Issue March 9 2005 www nallatech com Load the FPGA Design with FUSE eie rtr u 184 Connect via A a D u EE 185 Start the Software vei e ute DR 186 Part X Xilinx System Generator SUpport 189 System Generator Support tte 191 u ete 191 Overview of System Generator 191 Installing the System Generator Plug In for the Kit 192 Using the HDL Netlist Flow QAM 192 coii s MARTIN tariis 192 Simulating the QAM EXSImiples 192 Using the Cosimulation Flow MAC FIR Example 200 Ex
52. IV User Guide The High Performance FPGA Solutions Company 3 2 3 Right Side Parallel IV JTAG Cable Access USB Power Figure 7 Board Case right side showing USB power and Parallel IV Access 3 3 XtremeDSP Development Kit IV Hardware Physical Layout 3 3 1 Front View Figure 8 on page 17 highlights the key features on the front of the board 2 Pin User I O Main User PLink Nallatech Test uP General Parallel IV 65Mhz Oscillator Header FPGA Header Headers JTAG JTAG JTAG Header Power Supply Status LEDs ADC2 MCX Input s ADCI MCX Input External MCX Clock Inpu a DAC2 MCX Input Power DACI MCX Output Connector Power Supply Status LEDs USB Connection Additional User FPGA with ZBT Memory idc Adjacent Bus PCI Power Fan fitted FPGA Header Connection Interconnect 25200 Figure 8 Front View of Board Physical Layout NT107 0272 Issue March 9 2005 www nallatech com 17 Physical Layout NALLATECH The Clock FPGA 2 80 4 5144 is located the underside of the module and is not visible in Figure 8 on page 17 3 3 2 Back View There are no specific user features on the back of the board Figure 9 on page 18 is displayed for reference only 3 3V power 5V power indicator indicator m COP Figure 9 Back View of Board Physical Layout 18 www nallatech com NT107 0272 Issue March 9 2005 NALLATECH
53. Performance FPGA Solutions Company XtremeDSP Development Kit IV User Guide The design should now run on the chip to test it request a capture of samples by clicking on the black arrow button in the top left toolbar in Figure 104 on page 177 After a short delay the samples are shown in the waveform and you can see a counting sequence as expected ChipScope Pro Analyzer new project File View JTAG Chain Device Trigger Setup Waveform Window Help 2 DEV 1 MyDevice1 XC18V0 7 I DEV 2 MyDevice2 18 0 3 MyDevice3 XC4VSX UNIT 0 MyILA0 ILA Setup ENE Trigger Ports Apply Settings and Arm Trigger 27777 Counter Type Window gt Windows 1 Depth 2048 Position 0 Storage Qualification Bus Signal r DataPort 0 DataPort 1 DataPort 2 DataPort 3 DataPort 4 DataPort 5 DataPort 6 DataPort 7 I DataPort 8 DataPort 9 All Data 5 UNIT O MyILAO ILA 4120 1280 1440 1600 1760 1920 DONE NT107 0272 Issue March 9 2005 Figure 104 Captured Da
54. Simulation Format Tools Help 056865 UFix 10 Trig tpt double Trigg Slice Gateway 5 Gateway Out2 sin E 2 Sin double e System xS y 99 Gateway Ovt SineCosine Cos double Cosine Counter tot Gateway Out3 1 lode45 Figure 134 chip mdl NT107 0272 Issue March 9 2005 www nallatech com 209 System Generator Support NALLATECH The High Performance FPGA Solutions Comp any 210 Simulate the model by clicking on the Start simulation icon shown right At this point without modifying the model the plot shown in Figure 135 on page 210 should appear b Scopel L DJ xj jam ABB Figure 135 Scopel Displayed Waveforms The first plot represents the most significant bit of the 8 bit counter The MSB becomes when the counter output is within the range of 128 through 255 The second plot represents the full output of the counter The third plot shows the sine Zoom in at the beginning of time to see 2 clock cycle delay due to the pipelining implemented in the SineCosine table The fourth output represents the cosine This output has the same 2 clock cycle delay as the Sine Wave Integrate Chipscope in the Simulink model The Chipscope block can be found in the Simulink Library Browser in the Xilinx Blockset under the Tools library While holding down the left mouse
55. Testing EMC Memory Generic External Memory 1 XStatus status print Starting MemoryTest for Generic External Memory z n print Running 32 bit test status XUtil MemoryTest32 Xuint32 XPAR GENERIC EXTERNAL MEMORY MEMO BASEADDR if status XST SUCCESS print PASSED z n 0 testresult 0 0 WriteToGPOutput XPAR LEDS BASEADDR testresult D Program stopped at line 82 0x ffe010c Figure 110 First Line Breakpoint From this point the debugging controls can be used to step through the program and look at local variable and memory NT107 0272 Issue March 9 2005 www nallatech com 187 Xilinx Embedded Developer s Kit EDK Support NALLATEC Y Solutions Company 188 www nallatech com NT107 0272 Issue March 9 2005 NALLATECH The High Performance FPGA Solutions Company Part X Xilinx System Generator Support This part of the User Guide provides details on how to use the Xilinx System Generator Tool in conjunction with the XtremeDSP Development Kit IV NT107 0272 Issue March 9 2005 www nallatech com 189 NALLATECH erformance FPGA Solutions C 190 www nallatech com NT107 0272 Issue March 9 2005 NALLATECH XtremeDSP Development Kit IV User Guide Section 22 System Generator Support In this section Introduction Overview of Xilinx System Generator Using the HDL Netlist Flow Using the Cosimulation Flow Chipscope Use in System Generator
56. The High Performance FPGA Solutions Company 8 4 Software 8 4 1 FUSE Software LED Function The four PCI LEDs can be controlled from software using the FUSE API or the FUSE Probe Tool as shown in Figure 31 on page 57 order to toggle each LED choose the LED tab circled red and check the corresponding LED box Please note that you must open and select a card in the FUSE Probe Tool before controlling the LEDs A 1 File Edit View Run Configuration Card Control System Help s e s lt M Dench M Data Number Read Write 3 dit Data 0x00000000 0 00000000 benone Nallatech BenADDA IV Virtex Virtex2 V80 000000000 00 Virtex IV 4VSX35 10 00000000 Nallatech Benone 0 00000000 0 00000000 E PCI PROM 0 00000000 0 00000000 3 3 PCI PROM 000000000 0000000 Power Control Slot 0 gt J Words to Transfer 0 00000000 0 00000000 0 00000000 0 00000000 0 00000000 0 00000000 0 00000000 Current Address 0 00000000 0 00000000 0 00000000 0 00000000 0 00000000 1000000000 0 00000000_ Write Data Read Data 0 00000000 0 00000000 0 00000000 0 00000000 0 00000000 0 00000000 0x00000000 0x00000000 Linear Sequence Clear to zero 000000000 000000000 0 00000000 0 00000000 0 00000000 0 00000000 Table Size B2 0 00000000 0 00000000 serDefined 0 00000000 0 00000000 0 00000000
57. The High Performance FPGA Solutions Company Section Bus Structure In this section i Introduction to the Bus Structures in the Kit Hardware Aspects Firmware Aspects Software Aspects Introduction There a number of busses used in the XtremeDSP Development Kit IV which can be used to communicate with the host computer as well as for user defined purposes The Kit hardware uses a single main FPGA therefore most of the user specific busses are brought out to headers where possible This section provides some discussion on the general bus structure and also a brief discussion on the naming and terminology of specific busses Bus Naming On initial reading some of the bus names may be confusing The particular names have been selected based on the DIME II module standard to which the hardware has been designed To support the large volume of communications between DIME II modules and DIME II motherboards the following busses provide a robust infrastructure the XtremeDSP Development Kit IV Adjacent In Bus Adjacent Out Bus Comm PLINK Busses Local Bus In the DIME II standard the Adjacent Comm PLINK and Local Busses permit data to be transferred to all the various devices used in larger multi FPGA DIME II based systems Below a brief introduction to these busses Comms Parallel Link PLINKs arel2 bit bi directional point to point busses that allow the DIME II module to com
58. With the PC powered OFF insert your Kit in a PCI slot 2 After the PC starts up click the Windows start menu and launch Programs gt XtremeDSP Devel opment Kit IV gt Software gt Update to PCI Firmware Only Alternatively open Windows Explorer and navigate to the firmware folder in the XtremeDSP Development Kit IV installation and run the Benone_32PCI_64PCl exe program see Figure 150 on page 224 3 Click on the Card Menu and select the PCI interface to detect cards on A list of detected cards is dis played Click on the selected card 4 Click on Update Firmware 5 Programming should take approximately 10 to 20 seconds to configure via PCI 6 The firmware change is implemented the next time the power is cycled BenOne Firmware v1 Update Utility BEE File Card Located Cards Update Status Not begun Total firmware update progress Current device progress Update firmware Figure 150 Firmware Update Utility 224 www nallatech com NT107 0272 Issue March 9 2005 A NALLATECH XtremeDSP Development Kit IV User Guide The High Performance FPGA Solutio ns Company Updating via USB v 23 3 2 To update via USB use the following procedures Apply power to the Kit via the external power connector Attach the Kit to your host PC using the USB cable once the PC has finished starting up Double click on file Benone 32 32PCl exe to launch the application see Figure 150 on page 224
59. XtremeDSP Development Kit IV User Guide The High Performance FPGA Solutions Company Section 4 ADCs In this section Introduction to the ADCs Hardware Aspects Firmware Aspects Software Aspects 4 1 Introduction BenADDA DIME II module used in the XtremeDSP Development Kit IV has two analog input channels with each channel providing independent data and control signals to the FPGA Two sets of 4 bit wide data fed from two ADCs AD6645 devices each of which has an isolated supply and ground plane Figure 10 on page 19 illustrates the interfacing between one of the ADCs and the FPGA Virtex 4 User FPGA Data Ready output CLK FPGA Virtex ll FPGA XC2V80 4 5144 AD6645 14 ADC Analog Data XC4VSX35 IOFF668 Clock Feedback Figure 10 ADC to FPGA Interface NT107 0272 Issue March 9 2005 www nallatech com 19 NALLATECH ADCs The High Performance FPGA Solutions Comp any The main features of the on board ADC channels are 14 bit ADC resolution 2 s complement format I05MSPS sampling data rate Single ended 500 impedance analog inputs with population changes differential inputs 3rd order filter on analog Inputs 3dB point of 58 ADCs clocked differentially 4 1 1 ADC Architecture The ADC AD6645 is straightforward to operate the user is only requir
60. an active high reset that is required by a number of components such as the DCM components in the clock module The locked signal from the DCM in the clock module is then used after a register as the reset for the rest of the system end process NT107 0272 Issue March 9 2005 www nallatech com 141 Feature Examples 142 Main interface host interface HI_IFACE SV_IFACE generic map NUM_BLOCKSg gt I BLOCK SIZEg gt 4 NUM REGSg gt 3 port map CLK gt CLKBi RSTI gt INTI BUSY gt BUSY EMPTY gt EMPTY AS DSI gt AS 051 DMA WEN gt DMA WEN DMA REN gt DMA REN INT gt INT RENI_WENI gt RENI_WENI RDI_WR gt RDI_WR INTI gt INTI ADDRESS gt ADDRESS WRITE_STROBE READ_STROBE gt WRITE STROBE gt READ STROBE COUNT gt open DMA ENABLE DMA ENABLE DIRECTION gt DIRECTION DMA SEL gt open DMA RDY DMA RDY DMA DATA AVAILABLE gt DMA DATA AVAILABLE RST gt open SYNC RESET gt RST DMA_RESET gt open ADIO gt ADIO DATA gt DATA DMA_DATA gt DMA_DATA test to allow demonstration of interface of the host interface This could be any component capable of receiving bursts of data In this case it is simply a 511 32 H2_FIFO SYNCFIFO port map RCLK WCLK gt CLKBi READ EN gt REN WRITE gt
61. and delivery In addition to the invoiced value the buyer is liable for all import duty as may be applicable in the buyer s location If there is any documentation required for import formalities whether or not for the purposes of duty assessment the buyer shall make this clear at the time of order Quotations are made by Nallatech upon the customer s request but there is no obligation for either party until Nallatech accepts the customer s order Nallatech reserves the right to increase the price of goods agreed to be sold in proportion to any increase of costs to Nallatech between the date of acceptance of the order and the date of delivery or where the increase is due to any act or default of the customer including the cancellation or rescheduling by the customer of part of any order XtremeDSP Development Kit IV User Guide Nallatech reserves the right without prejudice to any other remedy to cancel any uncompleted order or to suspend delivery in the event of any of the customer s commitment with Nallatech not being met DELIVERY All delivery times offered by the company are to be treated as best estimates and no penalty can be accepted for non compliance with them Delivery shall be made by the company using a courier service of its choice The cost of the delivery plus a nominal fee for administration will be added to the invoice issued Payment of all inward customs duties and fees are the sole responsibility of the buye
62. at any time shall be packaged in the original packaging or its direct equivalent and must be adequately insured by the buyer Any equipment sent to the company for any purpose including but not limited to equipment originally supplied by the company must be adequately insured by the buyer while on the premises of the company PAYMENT Nallatech Ltd terms of payment are 30 days net Any charges incurred in making the payment either currency conversion or otherwise shall be paid by the buyer www nallatech com 249 Standard Terms and Conditions 250 The company reserves the right to charge interest at a rate of 2 above the base rate of the Bank of Scotland PLC on any overdue accounts The interest will be charged on any outstanding amount from said due date of payment until payment is made in full such interest will accrue on a daily basis TECHNICAL SUPPORT The company offers a dedicated technical support via telephone and an E mail address It will also accept faxed support queries Technical support will be given free of charge for 90 days from the date of invoice for queries regarding the use of the products in the system configuration for which they were sold Features not documented in the user manual or a written offer of the company will not be supported Interfacing with other products other than those that are pre approved by the company as compatible will not be supported If the development tools and syst
63. button select the Chipscope block and drag it into the open chip Simulink model www nallatech com NT107 0272 Issue March 9 2005 A NALLATECH XtremeDSP Development Kit IV User Guide The High Performance FPGA Solutions Company 6 Double click on the Chipscope block in order to set the following parameters Number of Trigger Ports Multiple trigger ports allow a larger range of events to be detected and can reduce the number of values that must be stored Up to 16 trigger ports can be selected In this example only one is used Display Options for Trigger Port For each trigger port the number of match units the match type need to be set The pull down menu displays options for a particular trigger port For ports the display options for trigger port 0 N I can be shown In this example one Trigger port named Trig0 is used This option should therefore be set to 0 Number of Match Units for Trigger Port Using multiple match units per trigger port increases the flexibility of event detection One to four match units can be used in conjunction to test for a trigger event In this example this option should be set to since only one condition is checked for i e the 8 bit counter value Set the trigger value at run time in the Chipscope Pro Analyzer Match for Port This option set of the following six types Basic performs or lt gt comparisons Bas
64. create say a C based application which may be overkill for a simple setup or specific test 2 7 DIMEtalk DIMEtalk is a design tool for implementing communications networks within FPGAs DIMEtalk provides an integrated design environment which allows users to implement communications networks within an FPGA system using simple block components such as routers nodes and edge components DIMEtalk also provides a library of software functions which are accessible via the FUSE software These functions provide easy access to the FPGA network from a software environment A DIMEtalk network is composed of routers helping nodes communicate using packets Each DIMEtalk connected process is represented by a node which acts as a doorway into the network The simplest form of node can be thought of as an area of memory accessible by processes on the DIMEtalk network and the associated process behind the node An evaluation copy of DIMEtalk is provided with the Kit on the Nallatech Evaluation Software CD NT107 0272 Issue March 9 2005 www nallatech com ll Introduction to Nallatech Systems and Solutions NALLATECH BEN The High Performance FPGA Solutions Company Figure 4 on page 12 represents an example DIMEtalk network DIMETalk Example Network Physical Link Process Block Physical Link Nodes are the points at which data enters or leaves the network Routers route the data through the network Br
65. downto 0 common ground signal GND std_logic begin GND lt 0 RESET lt not RESETI r lock deskew section IBUFG Instantiation for CLK_IN UO IBUFG IBUFG port map I gt CLKI FB O CLKIN OSC y BUFG Instantiation for CLKFB 00 BUFG BUFG port map I gt CLKFB OSC O gt CLK_OSC DCM Instantiation for internal deskew of CLK0 U0_DCM DCM port map CLKIN gt CLKIN_OSC CLKFB gt CLK OSC DSSEN gt GND PSINCDEC gt GND PSEN gt GND PSCLK gt GND RST gt RESET CLKO gt CLKFB_OSC LOCKED gt RSTI of clock deskew module configured CONFIG_DONE lt 0 set low pass filter response and no zero stuffing for both DACs DACI_MODO0 lt 0 DACI_MODI lt 0 DAC2 MODO lt DAC2 MODI lt 0 disable resets for DACs RESET lt 0 DAC2 RESET lt 0 optimum settings for sampling rate DACI DIVO lt l DACI DIVI H DAC2 DIVO DAC2 DIVI lt In this example the DCM and clock circuitry are manually included at this level of the VHDL rather than using a generated clock module This is to show how it is done manually in the code Note that the DCM has been declared to be in the low frequency mode This is suitable for this example as the 105MHz clock input is within the LOW frequency operating mode of the DCM GND is declared as a signal so it can be assigned a value to improve the readab
66. in a similar way to the module ID it always starts at 0 and increments for each additional device to be configured within a module or virtual module so the maximum device ID depends upon the number of device present The numbering for the hardware as supplied in the Kit is shown in Figure 72 on page 124 NT107 0272 Issue March 9 2005 www nallatech com 123 NALLATECH The High Performance FPGA Solutions Comp any 124 5V PCI Boot PROM C Mod IDev 0 Clock FPGA z XC2V80 3 3V PCI Boot Mod 0 Dev 0 PROM 24 Mod IDev I Main User FPGA i XC4VSX35 PSU Mod 0 Device 1 Controller Mod IDev 2 INTERFACE FPGA Figure 72 Module and Device Numbering the XtremeDSP Development Kit IV 16 2 Key Steps for FPGA Configuration 16 2 1 Using the FUSE APIs or DIMEscript When developing applications incorporating FPGA configuration using FUSE APIs or DIMEScript there are a number of key steps that need to be performed As an example the FUSE C C API is used to show these key steps although the principle is the same for any of the FUSE APIs or DIMEscript To communicate with the Kit the software must first find the card in the host system This can be achieved by using the DIME LocateCard int LocateType DWORD void LocateTypeArgs DWORD DriverVersion Flags function Various arguments are required by the function to locate the ca
67. ledsnake in the design 170 www nallatech com NT107 0272 Issue March 9 2005 NALLATECH The High Performance FPGA Solutions Company XtremeDSP Development Kit IV User Guide Once this code has been updated the actual design needs to be implemented An ISE project has already been created called chipscope_example npl and is included on the XtremeDSP Development Kit IV CD in the following location ROM Drive Examples chipscope_example has also been created and is included in the top level of the Chipscope example called ledsnake bit 20 3 4 Analyzing the Design Once the bitfile has been created the design must be analyzed using the Chipscope Pro Analyzer Follow the steps below to analyze the ledsnake design Setup the Design Using FUSE Probe Tool The simplest way to setup the design in the FPGA is to use the Nallatech FUSE Probe Tool This is opened either from the Windows start menu or by double clicking on the Nallatech icon in the Windows task bar gt E gt E gt H gt E gt E gt E gt PY FUSE Probe file Edit View Run Confguration Card Contro System Help System Resets fPOAReset System Reset Interface Reset LEDS Oacimstar Frequencies 1000000000 00000000 1000000000 0200000000 000900000 00000000 0 00000000 0x00000000 000000000 600000000 04120 0500000000 Session Log Console
68. note the following mapping ZBT 0 to 18 lt fpga 0 Generic External Memory A lI to 29 Note that this can simply be replicated for the second independent bank of ZBT memory on the board 21 2 3 XMD Support XMD is used to debug code running on embedded microprocessors It is possible to connect to XMD via a JTAG or UART connection The JTAG headers on the board can be used to provide XMD access via a JTAG connection i e a OPB UART peripheral Note that the main User FPGA is device 4 in the JTAG chain for XMD Alternatively a serial port connection can be used There is a Nallatech specific test header J9 and 12 that also provides RS232 level shifters No cable is provided in the Kit to connect to this header however the pinouts are given in Part Xll Reference Information on page 227 The header allows a straight wiring connection to be made with the serial ports on a PC The RS232 level shifters translate between the voltage specification of the FPGA and that of the serial ports on the PC www nallatech com NT107 0272 Issue March 9 2005 NALLATEC The High Performance FPSA Solutions Company XtremeDSP Development Kit IV User Guide 21 3 EDK Example A simple example is provided on the XtremeDSP Development Kit IV CD in the following location ROM Drive Examples edk_example folder This example platform contains the following Microblaze core OPM MDM Debug module Two EMC peripher
69. of a Nallatech ZBT core Gives details on using the Nallatech ZBT controller core to interface to the ZBT used in the Kit NT107 0272 Issue March 9 2005 NALLATECH The High Performance FPGA Solutions Company Part VI Xilinx ISE Support This part of the User Guide provides information on common Xilinx ISE settings for FPGA designs running on the XtremeDSP Development Kit IV hardware NT107 0272 Issue March 9 2005 www nallatech com 147 NALLATECH erformance FPGA Solutions C 148 www nallatech com NT107 0272 Issue March 9 2005 NALLATECH XtremeDSP Development Kit IV User Guide Section 18 Common ISE Settings In this section Synthesis and Implementation Settings 18 1 Synthesis and Implementation Settings This section details the synthesis and implementation settings which should be used for the development of FPGA designs to run on Nallatech hardware 18 1 1 Synthesis Options When developing FPGA designs to run on Nallatech hardware it is not necessary to select any specific settings for the synthesis of HDL code for FPGA designs 18 1 22 Implementation Options Developing FPGA designs to run on Nallatech hardware with on board Xilinx FPGAs will ultimately require use of the Xilinx Implementation tools to take the synthesized design to the hardware device These tools are available in a variety of formats including Alliance Foundation and ISE When performing the implementation stag
70. on the module power supplies If using the Kit standalone with the external power supply To enable the power supplies when using the external power supply jumper 17 must be fitted This allows the module power supplies to come on as soon as power is supplied to the board It also sets both CLK A and CLK B to 40MHz If using the Kit in a PCI slot To enable the power supplies when using the Kit in a PCI slot open the Kit in the FUSE Probe Tool as shown in Figure 77 on page 156 Using the Kit in a PCI slot provides greater bandwidth and therefore faster cosimulation for the Kit NT107 0272 Issue March 9 2005 www nallatech com 155 Impact Support NALLATECH The High Performance FPGA Solutions Company resets and these tabs 2 I9 2 3 To setup the oscillators for the design use 151 Filo Edn Run Confguraton System x Al xn Benno DAY vitant IEEE REB benone Nallatech BenADDAAV Virtex Virtex IV 4VSX35 Words to Transfer eiDefined Data Read Data Linear Sequence Charto zero 4 Table Size 2 Click open card button bring up the open card dialog box Session Log Simply select none ock Set to 5 k 1 tenme Sys Clock Set to 50 000 the interface itfile D wipMBendfoA IV Testa Dxamplesichipacope exwxpleVledsnake bit assigned
71. out the DIMETalk network i e reset control etc the handle to vidime viHandle viDIME Open hCardl 0 The locate handle can then be used to fund out information on the cards that have been detected in the system The DIME LocateStatus function uses the locate handle and can retrieve information about the hardware such as motherboard types etc The next key step is to obtain a handle to a specific card in the system This is done using the DIME_OpenCard function Again this uses the locate handle but now returns a specific card handle Status information can be obtained about a specific card given a specific card handle The DIME_CardStatus function can be used for this As a test of the host PC communication to the PCI or USB interface on the Kit hardware simply change the user status FPGAs on the motherboard Now enable the resets set the clocks to the required frequencies and then configure each FPGA whilst the system is in reset Once the configuration is complete a standard reset sequence is followed to make sure the device and design properly start A handle can now be obtained for the actual interface to the Interface to User FPGA Core This is done using the viDIME_Open function www nallatech com 145 Feature Examples CH I7 5 Result viDIME_DMAWrite viHandle WriteData 256 0 NULL NULL 5000 Result viDIME DMARead viHandle ReadData 256 0 NULL NULL 5000
72. plugged into the socket The configuration of the slot is shown in Figure 39 on page 66 Ext Osc Connector Socket 8 Pin Crystal Socket 14 Pin Crystal Socket Pin Numbers Figure 39 Oscillator Socket Configuration The clock nets on the Kit allow either a fixed frequency oscillator to be used or an external clock as the external clock connector is located under the fixed frequency oscillator socket External Clock Input via Module MCX Connection External clock sources can be brought into the Kit for on board use The external clock input shown in Figure 40 on page 67 is only initially connected to the Clock In order to meet the signal input specifications for the PGA_FPGA an op_amp is used to provide DC biasing to level shift the input signal above 0V The MCX clock input is setup as a 50R single ended input At the heart of the external clock circuit is the AD8131 Differential Driver This converts single ended inputs into differential outputs suitable for the Clock FPGA The AD8131 has internal feedback with a fixed gain of 2 which allows for better thermal matching and tolerance levels The common mode level of the differential output is set by VOCM thereby level shifting the input signal suitable for driving the Clock FPGA www nallatech com NT107 0272 Issue March 9 2005 NALLATECH XtremeDSP Development Kit IV User Guide The High Performance FPGA Solutions Company External Clock Input Figure
73. set the clock i e for a 40MHz clock type 40000 Please note you must open and select card in the FUSE Probe Tool in order to control the oscillators Please note the following naming conventions for the clocks CLKA This is SYSCLK in the DIME II standard naming CLKB This is DSPCLK in the DIME II standard naming CLKC This is PIXCLK in the DIME II standard naming Also note that i e PIXCLK in the DIME II standard is not connected to a programmable oscillator and so this control is effectively redundant in the Kit hardware NT107 0272 Issue March 9 2005 www nallatech com 75 NALLATECH High Performance FPGA Solutions Company 2205327055 E 01 File Edit View Run Configuration Card Control System Help m a l a m Read 000000000 000000000 benone Nallatech BenADDA IV Virtex Virtex2 V80 atal 0 00000000 0x00000000 Virtex IV 4 8 36 2 000000000 _ 0 00000000 Nallatech Benone 0 00000000 0 00000000 5v PCI PROM 0 00000000 0 00000000 5 SSNPCLRROM 600000000 0 00000000 Power Control Slot 0 0 00000000 000000000 Words to Transfer P 0 00000000 0 00000000 0 00000000 0 00000000 0 00000000 0 00000000 0 00000000 0 00000000 Current Address 0 00000000 0 00000000 0 00000000 0 00000000 000000000 000000000 000000000 Write Data Read Data 0 00000000 0 00000000 0 00000000 0 00000000 0 00000000 0 00000000 0 000
74. setup of the main FPGA and the clock FPGA designs ADC CLKA E4 ADC CLKAI DI ADC CLKB GI ADC CLKBI FI DAC CLKA DAC_CLKAI DI2 DAC_CLKB GI0 DAC_CLKBI 2 Table 29 Clocking for DACs and ADCs 10 2 6 7 Clocks The two ZBT banks in the Kit are clocked by independent clocks with the addition of feedback clock signals Each bank has a signal that can be de skewed within the User FPGA which ensures that the clock at the ZBT SRAM Banks and the feedback pin have coincident clock edges with minimum skew This process ensures the internal logic is clocked in phase with the data entering the ZBT chips Driving the ZBT SRAM clock from the FPGA ensures maximum flexibility in the clocking mechanism during system design as it can be derived from any of the clock sources in the system The pinouts for the various clock signals associated with the ZBTs are shown in Table 30 on page 69 Signal Name User FPGA XC4VSX35 10FF668 PIN No ZBTA_CLK ABIO ZBTA_CLK_FB_OUT ACI0 ZBTA_CLK_FB_IN 12 ZBTB_CLK AEI4 ZBTB CLK FB OUT ABI7 Table 30 ZBT Clock Pinouts NT107 0272 Issue March 9 2005 www nallatech com 69 NALLATECH The High Performance FPGA Solutions Comp any Signal Name User FPGA XC4VSX35 10FF668 PIN No ZBTB CLK FB IN ACI7 Table 30 ZBT Clock Pinouts ZBT SRAM Clocking Example An example of a typical clock arrangement for driving the ZBT Ban
75. slightly reduced airflow Therefore when the lid is fitted it is recommended that designs use up to 2 75 Amps the 1 2V core FPGA supply The 2 75 Amp limit will cover almost all designs for example a design that uses 7576 of the flip flops with a 10076 toggle rate draws 2 051 Amps when run at 200MHz Beyond the 2 75 Amps you should remove the lid from the board case to increase the airflow and allow the FPGA to operate up to the limits documented in page 98 Limits with Lid Removed or when Fitted in a PCI Slot The power and current readings are for the 1 2V supply only i e the FPGA core power supply The results shown in Figure 62 on page 103 indicate that even when the Kit is fitted to a PCI slot the thermal limits of the Virtex 4 are a key factor The figures also indicate that the max draw on 1 2V is 8W or 6 67 Amps The recommended maximum limit is therefore 6 Amps when using PCI 102 www nallatech com NT107 0272 Issue March 9 2005 NALLATECH XtremeDSP Development Kit IV User Guide Power vs Temperature e Test Data 1047 2222 Thermal Limit 90 4 80 70 60 50 40 Temperature 30 20 10 4 0 1 2 3 4 5 6 7 Power W Figure 62 Power vs Temperature with Lid on Case The recommended power max for the Kit is 25Watts 5Volts 5 Amps as defined in the PCI specification The Kit requires 5Volts and 12Volts If you wish to exceed t
76. the Kit contains LEDs which indicate the status of the main power supplies for the motherboard itself Table 22 on page 56 defines their use Purpose General Operation State DIO 2 5 power indicator GREEN 014 3 3V power indicator GREEN Table 22 Motherboard Main Power LEDs 8 2 3 User LEDs Module User LEDs BenADDA DIME II module has two user tricolor LEDs which can be used for specific design purposes Signal Description User LED Signal Name Main User FPGA XC4VSX35 IOFF668 Pin Green Diode for LED2 D2 LED_Green2 AL29 Red Diode for LED2 D2 LED_Red2 AL30 Green Diode for LEDI DI LED Greenl AK6 Red Diode for LEDI DI LED AK7 Table 23 Module User LEDs Motherboard User Status LEDs The BenONE Kit Motherboard has four software controllable LEDs These LEDs are connected to the Interface FPGA and can only be controlled via software calls to the card and NOT via signals from the main User FPGA Please see Software on page 57 for details of the relevant software calls 8 3 Firmware The LEDs are illuminated when the corresponding pin is logic 0 otherwise the LED is not illuminated Active LOW Applying logic 0 to either Cathode will cause that color to illuminate and applying logic 0 to both Cathodes green and red will cause a third color yellow to illuminate www nallatech com NT107 0272 Issue March 9 2005 y NALLATECH XtremeDSP Development Kit IV User Guide M
77. the User FPGA followed by a burst of data Again the DATA int bus shows the internal data waiting to be driven onto the ADIO bus It should be noted that after the first read the next set of data will not be available until one clock cycle after the read So long as the reads are continuous data will then follow every clock cycle Writing to Interface FPGA from User FPGA Writing to the Interface FPGA is similar to writing to a FIFO If the Interface can receive more data the BUSY signal is LOW and when the Interface FPGA cannot receive more data the BUSY signal is HIGH To help meet timing specifications the User FPGA application is allowed to over run by two further data samples In other words after the BUSY signal is asserted two further data samples can be written to the Interface FPGA The diagram in Figure 68 on page 117 shows a Burst Write function in operation and also demonstrates the maximum data over run of 2 www nallatech com NT107 0272 Issue March 9 2005 NALLATECH XtremeDSP Development Kit IV User Guide The High Performance FPGA Solutions Company CLK EMPTY BUSY ASIDS REN VVEN DONEENES j j Figure 68 Burst Write Transfer Timing Information The information in Table 49 on page 117 provides the timing information required to write the User Constraints File UCF for implementing a design into an FPGA These are recommended co
78. then similar timing constraints should be associated with them as well 5 4 Software Please refer to the XtremeDSP Analog Capture Datasheet on the XtremeDSP Development Kit IV CD at the location CD ROM DriveMApplication NotesNT302 0035 XtremeDSP Kit Analogue CaptureiDocuments This provides basic example design for the DACs on the XtremeDSP Development Kit IV NT107 0272 Issue March 9 2005 www nallatech com 39 DACs NALLATECH Performance FPGA Solutions C 40 www nallatech com NT107 0272 Issue March 9 2005 NALLATECH XtremeDSP Development Kit IV User Guide The High Performance FPGA Solutions Company Section 6 ZBT SRAM Memory In this section Introduction to the ZBT SRAM Memory Hardware Aspects Firmware Aspects Software Aspects 6 1 Introduction The Kit provides two independent banks of ZBT SRAM Each bank is configured as 512 x 32 This memory can provide on board storage capabilities via a 32 bit data bus to each bank The main features of the ZBT Memory devices include Fast cycle times 6 5 7 5 5 10 5 100 bus utilization Advanced control for minimum signal interface Single R W Read Write control pin Clock controlled and registered addresses data 5 and control signals Common data inputs and data outputs Linear or interleaved burst modes NT107 0272 Issue March 9 2005 www nallatech com 41 ZBT SRAM Memory NALLATECH
79. to benone card PCI or USB gt Yirtex IV 4V2X35 the Wallatech BenADDA IV 4 5 35 FF668 on the benone card has been configured generally Figure 77 Open Card Enabling Module Power Supplies After opening the card in FUSE carry out the following procedures Enable the resets to the cards by checking the reset box You should enable the resets during configura tion and release them once all devices have been configured Set the oscillators to the required frequencies before configuring your design Alternative Method of Enabling Power Supplies To enable the power supplies when using the external power supply jumper 17 must be fitted This allows the module power supplies to come on as soon as power is supplied to the board 156 The power supplies the module on when the power good LEDs for PSUB to D are green rather than red Please refer to page 100 for more details on the module power supplies Note that the power supplies are not closed down when the card is closed in FUSE Therefore you only need open the card once during initial mains power on to enable the module power supplies However you still need to open a card in FUSE to control the oscillators and the resets www nallatech com NT107 0272 Issue March 9 2005 NALLATEC XtremeDSP Development Kit IV User Guide gh Performance FPGA Solutions Company 19 2 4 Launch Impact The Impact tool can be launched from
80. tool optimizing out parts of the registers that are not specifically in use In real designs the outputs of the registers actually provide a specific purpose In this case as we only write and read from them with no part of the following circuit being dependent upon them the synthesis tool removes the registers in part The inclusion of the dependency of the dummy signal on the register values ensures that for the sake of this example the registers are not optimized out www nallatech com 143 Feature Examples C Code Listing OpeningASingleCard c 144 Obening Cards Demo This is a simple program to show how to locate and open card pe Id that in this project settings dimesdl lib is included IIdimesdl h is required to gain access to the FUSE API functions IIdimesdl h and dimesdl lib can both be found in the FUSE include directory include dimesdl h include vidime h include lt stdio h gt DWORD ModuleNumber 0 NUMBER NEEDS CHANGED THE DESIRED MODULE NUMBER DWORD PrimaryFPGADeviceNum l ITHIS NUMBER NEEDS TO BE CHANGED TO THE MODULE DEVICE NUMBER DWORD SecondaryFPGADeviceNum 0 ITHIS NUMBER NEEDS TO BE CHANGED TO THE MODULE DEVICE NUMBER char Filenamel host_interface bit char Filename2 osc_clock_2v80 bit int main int argc char argv hLocate NULL DWORD ErrorNum NumOfCards LoopCntr
81. two on board FPGAs determines the status of the FPGAs on the module The FPGA_DONE signal is connected directly to the carrier motherboard where it is then connected to the Interface FPGA This signal has a weak pull up applied to it on the motherboard When the FPGAs the BenADDA DIME II module are NOT configured the base of the two transistors MMUN22ILTI will be switched on by the 3 3V pull up With the base of the transistors switched on the FPGA DONE signal connected to the motherboard via the DIME II connector will be pulled LOW through the transistor Once the FPGA has been configured the user should send out a LOW signal on the appropriate CONFIG DONE pin i e a LOW would be driven out of on the FPGA This turns the base of the transistor off and the FPGA DONE value is now subject to the status of the complete system Once all other FPGAs in the system are configured the FPGA DONE signal will be HIGH via the pull up on the motherboard However if one FPGA is not configured the FPGA DONE signal from that device will still be pulled LOW meaning that FPGA DONE for the entire system would be LOW The system designer will therefore be able to read the value of FPGA DONE via FUSE software at the input on the various FPGAs to determine the overall state of the system NT107 0272 Issue March 9 2005 www nallatech com 95 Board and System Level Monitoring Capabilities If the Config DONE signal is to be ut
82. via 3 3V 5V PCI 32 bit 33 MHz or USB vl l interfaces Status LEDs JTAG configuration headers User 0 1 pitch pin headers connected directly to user programmable FPGA BenADDA DIME II module Virtex 4 User FPGA XC4VSX35 OFF668 2 independent ADC channels AD6645 ADC 14 bits up to 105 MSPS 2 independent DAC channels AD9772 DAC 14 bits up to 160 MSPS Support for external clock on board oscillator and programmable clocks Two banks of ZBT SRAM 133MHz 512Kx32 bits per bank www nallatech com NT107 0272 Issue March 9 2005 The High Performance FPGA Solutions Co XtremeDSP Development Kit IV User Guide Multiple Clocking Options Internal amp External Status LEDs External power supply US Mains cable with separate UK European or Australian mains adaptors Wide ranging input 90 264Vac multiple output power supply generating 5 Volts 5A 12 Volts 2A 12 Volts 800mA USB vl l compatible cable 2 metres long 5 MCX to BNC cables for connecting to the ADC DAC and external clock connectors PCI Backplate and 2 screws 2x BNC jack to jack adaptors for use in loop back configurations Large blue Kit carrying case XtremeDSP Installation Pack containing Nallatech FUSE Field Upgradeable Systems Environment Software CD Provides the ability to control and configure FPGAs and provides facilities to transfer data between the Kit and a host PC via a GUI or a C based API Nallatech XtremeDSP Developme
83. 0 00000000 0000000000 _ 0 00000000_ 0 00000000 0 00000000 0 00000000 0 00000000 serDefined 0 00000000 0 00000000 0 00000000 0 00000000 LEDs 2 0 00000000 0 00000000 De 0 00000000 0 00000000 Data31 0 00000000 0 00000000 UserDefined Ds Session Log console q benone card opened UserDefined Figure 31 Reset using FUSE Probe Tool For more information on using the FUSE Probe Tool please see the FUSE System Software User Guide on the supplied FUSE CD NT107 0272 Issue March 9 2005 www nallatech com 57 NALLATECH LEDs 8 4 2 Listing of Calls in the FUSE API for LED Control The FUSE C C API provides two functions for controlling the LEDs in the Kit These are DIME_ReadLEDs DIME WriteLEDs The FUSE 5 require a data word to be written with the bits of that word controlling the LEDs The LEDs are illuminated when a 0 is written to the location So for example when the four least significant bits of the data word are 1001 LEDs and D4 will illuminate The bits of the data word that control the LED mapping are given in Table 24 on page 58 LED Dataword Bit Number D2 0 D3 D4 2 D5 3 Table 24 PCI Status LEDs An example of how to control the LEDs using the FUSE C C FUSE API is shown in Figure 32 on page 58 include lt dimesdl h gt This is held in the inclu
84. 0 0000600 1066000000 10200000000 10500000000 000000000 0 00000000 10000000000 0000000 000000000 10400000000 1000000000 10100000000 Qv00000000 950000000 000000000 10100000000 10200000000 10000000000 Set the SYSCLK oscillator to 50Mhz by entering a value of 50000 x Session Log console Bitfile D wip BenADDA IV Tests Fxamplesichipscope examplelledsnake bic assigned to benone card Aj 2 n FN 2 Virtax IV 43535 e the Mallatech BanADDA IV 77660 on the benone card har been configured benone Sys Clock Set to 30 0mMs Figure 99 Setting the Oscillator Now configure the main User FPGA by right clicking on the Virtex 4 XC4VSX35 10FF668 and configure the device After a delay which is significantly longer on USB a message is returned reporting the configuration of the device Confguraon Cam Conro System Help yle e lt m benone Data Nallatoch FF 668 2 Nallatech BenADDA IV Virtex Virtex IV 4 5 35 00000000 000000066 7000000000 000000000 10100000000 1000000000 100000000 1000000000 10100000000 1000000000 0 00000009 0 00000000 1000000000 0000000005 000660666 10500000068 000000000 1000000000 1000000000 0000 0002 0100000000 1000000000 1000000000 475555 the Nallatech BenADOA IV 1 4 5 25 FFG60 on the benone card bas been
85. 00 Bitfile Di uip BerADOA IV Taata Exaapierichipacope exaaple ledanake bit assigned to benone card Yirtex IV 4V3X35 the Mallatech BerADDA IV Virtex4Y5X35 FF668 on the benone card has been configured Set both resets to the design NT107 0272 Issue March 9 2005 Figure 98 Enable Resets www nallatech com I73 NALLATECH The High Performance FPGA Solutions Company Chipscope ILA Support Once the resets are enabled the clocks should be set In this example only one of the clocks is used and so only one clock is set FI FUSE Probe Eie Vew Run Confguason CargCeetrol System x mle 39 benone Data Number Read vente amp Ben ADDA vites 068 os mu benone Nallatech BenADDA IV Virtex veo Datas 10100000000 Data2 10400000000 1200000000 4VS Hi testiatoch Benone Dates 1000000000 10000000000 POLPROM TA 1000000000 2 3 POLPROM patas 0100000000 10100000000 Power Control Biol 0 7 1000000000 050990000 joata 000000000 000000000 Oates 000000000 10400000000 Ostaa 10400000000 0000000000 10 00000000 10 00000000 000000000 000000000 ESH 0 00000000 650000000 n 1000000000 0900000000 Ossia 0300000000 10000000000 ost 00000000 00000000 Omai 000000000 0000000 1000000000 522000000 Datos Ux0000COO0 000000000 Oaa 000006600 10100000000 000000000 0 20000000 000060600 21040000000 00000000 042000000
86. 000 0x00000000 0 00000000 5V PCI PROM 0x00000000 3 3V PCI PROM 0 00000000 0 00000000 BB Power Control Slot 0 _ Dx00000000 0x00000000_ 0 00000000 0 00000000 0 00000000 0 00000000 0 00000000 0 00000000 0 00000000 0 00000000 0 20000000 0 00000000 0 00000000 0 00000000 0 00000000 0 00000000 0 00000000 0 00000000 0 00000000 0 00000000 000000000 ined 00000000 ox00000000 0x00000000 0 00000000 0 00000000 0 00000000 0 00000000 0 00000000 1000000000 0 00000000 UserDefined 0200000000 000000000 0 00000000 0 00000000 0 00000000 0 00000000 0 00000000 UserDefined 0 00000000 0 00000000 System Resets 0 00000000 0 00000000 0 00000000 0 00000000 0 00000000 0 00000000 0 00000000 0 00000000 v FPGA Reset 0x00000000 0 00000000 0 00000000 0 00000000 benone Nallatech BenADDA IV Virtex Words to Transfer Current Address Write Data Linear Sequence Table Size Save Data As 0 00000000 Read Data Clear to zero 32 F Bystem Resel Session Log Console benone card opened Interface Reset 5 scillator Frequencies UserDefined Figure 35 Reset using FUSE Probe Tool In the FUSE Probe Tool the ONBOARD is re
87. 0000 1000000000 1000000000 1000000000 0 00000000 000000000 000000000 0 00000000 0 00000000 1000000000 x00000000 000000000 0100000000 0x00000000 000000000 Clear to 200 000000000 000000000 ERR 1000000000 000000000 0 00000000 000000000 32 0 00000000 1000000000 0 00000000 10500000000 1000000000 1000000000 10 00000000 1000000000 1000000000 1000000000 1000000000 10500000000 1000000000 1000000000 1000000000 1000000000 1000000000 1000000000 1000000000 10500000000 0500000000 1000000000 Session Log benone card opened Bitfile DiWwipiBenADDA IV Tests Examples system generator examplesiAQANABitfilesiose clock 2v amp 0 bit assigned to Bitfile Di utp BenADDA TV Testa Dxsnplesisysten generator examples QAM Ricfiles sysgenqani clk vrapper bit 2 2 n ry ry ry verte F fo Reed Fifo ful FiFOs LEDs Resets Oscitator Frequencies Figure 117 Card Opened in FUSE Assigning Bitfiles 11 View the output the oscilloscope Connect two of the cables from the DAC outputs on the board to channels on the oscilloscope Set the display mode of the scope to X Y if it supports it You will see either two streams of data Figure 119 on page 199 or the constellation if using X Y Figure 118 on page 199 Some modification of time and voltage scales may be necessary dependent upon the scope us
88. 00000 0 00000000 Linear Sequence Clear to zero 0 00000000 0 00000000 0 00000000 0 00000000 0 00000000 0 00000000 Table Size 132 0 00000000 0 00000000 UserDefined 0x00000000 0 00000000 0 00000000 0 00000000 0 00000000 0 00000000 __ 0 00000000 0 00000000 0 00000000 0 00000000 0 00000000 0 00000000 0 00000000 0 00000000 0x00000000 0x00000000 50000 SYSCLK Frequency in Khz 0 00000000 0 00000000 Data31 0 00000000 0 00000000 DSPCLK Frequency in Khz Session Log consote PIXCLK Frequency in Khz card opened benone Sys Clock Set to 50 0MHz FIFOs LEDs Oscillator Frequencies Set Oscillator Frequencies UserDefined UserDefined UserDefined Figure 47 Setting Clock Frequencies in FUSE Probe Tool 10 4 2 Listing of Calls in the FUSE to Set the Clocks The FUSE C C API provides a function for controlling the programmable oscillators in the Kit from the interface FPGA These are DIME_SetOscillatorFrequency Essentially the command takes two parameters a resetNum and cmdMode OscillatorNum determines which clock is changed where 0 All Clocks This SYSCLK in the DIME II standard naming 2 CLKB This is DSPCLK in the DIME II standard naming 3 This is PIXCLK in the DIME II standard naming
89. 0272 Issue March 9 2005 www nallatech com 129 NALLATECH erformance FPGA Solutions C 130 www nallatech com NT107 0272 Issue March 9 2005 NALLATECH XtremeDSP Development Kit IV User Guide Section 17 Feature Examples In this section i Introduction Simple ADC Hookup Example ADC to DAC Example Host Interface Example Relevant Application Notes 17 1 Introduction This section details a number of examples that are included with the Kit It also makes reference to some of the application notes on either the FUSE CD or the XtremeDSP Development Kit IV CD Apart from these examples related to specific features on the hardware there are some additional examples later in the User Guide that deal with support for specific tools such as Xilinx Impact In each example the top level source is included with notes added to explain the function in each example 17 2 Simple ADC Hookup Example 17 2 1 Example Overview The purpose of this example is to show how to connect up to the ADCs on the hardware The code brings in the data from each ADC and registers it then uses some of the bits to drive the LEDs on the Kit hardware Remember that the LEDs are active low i e a low will turn them on 17 2 2 Source The source files are provided in the folder CD ROM Drive ExamplesWimple adc hookup source on the XtremeDSP Development Kit IV CD 17 2 3 Implementation A UCF is also provided in the source
90. 105025093 3 XC4VSX35 02088093 4 MyDevice4 2 80 01010093 Cancel Read USERCODEs Advanced gt gt Figure 102 Detected Devices in Chain should be 5 Click OK to continue The communication should now be established and the ILA units and signals are displayed Further details on driving the Analyzer are provided in the Chipscope documentation Elle View Cham Device Tnggergetue Waveform Window Help ew Project DEV WOewce1 DEV 16 00 C OEV 3 ACPI UNIT 0 GLA Trigger Setup Data Port Tngger Ports Counter Trigger Conditon Name Trigger Condiben Equation TngperConamond Tee modom vreao 16354 21 Storage Qualifcation AI Dats 1 DEV 3 Mylwvice3 XCZVP30 UNIT O MYILAO ILA bsraport 6 DataPort 1 Detelort 2 Databort 3 DataPorc 4 DataPert 5 Davarort s DataPort 8 Detaloct 9 DataPort 20 111 slej apo fo INFO Found 1 Core Unit in the device Chain Parallel Cable Core Command kon Status Figure 103 Connected to ILA Units 176 www nallatech com NT107 0272 Issue March 9 2005 NALLATECH The High
91. 3 is the most significant bit This is an input to the DAC DACI MOD 0 Invokes digital high pass filter response i e half wave digital mixing mode Active High This is an input to the DAC DACI MOD I Invokes Zero Stuffing Mode Active High Note quarter wave digital mixing occurs with MODO also set HIGH This is an input to the DAC DACI DIV I downto 0 DIVI along with DIVO sets the DAC PLL s prescaler divide ration This is an input to the DAC DACI PLLLOCK This is the lock signal from the internal PLL of the DAC devices Phase Lock Loop Lock Signal when PLL clock multiplier is enabled High indicates PLL is locked to input clock Provides x clock output when PLL clock multiplier is disabled This is an input to the FPGA DACI RESET Resets internal divider by bringing momentarily high when PLL is disabled to synchronize internal clock to the input data and or multiple AD97724 devices This is an input to the DAC Please note that the input to the DACs is offset binary format NT107 0272 Issue March 9 2005 www nallatech com 37 DACs 38 The control signals should always be set In particular it is important not to leave the DAC I RESET and DAC2 RESET control lines floating If the DAC RESET controls are not being actively used these should be set low by default Figure 25 on page 38 shows the example code for setting fixed DAC control signals set low pass filter response and no zero stuffing fo
92. 32 Nallatech RS232 Test Header 9 and 12 233 DIME II Control and Monitoring Signals 233 DIME II Sbecifi PINS op L DI dosis undae Par tad 233 234 On Board Temperature Sensor u 234 www nallatech com NT107 0272 Issue March 9 2005 234 ZBT SRAM Bank 234 ZBT SRAM Bank 236 Inter FPGA Clock Infrastructure Signals 238 Clock sources arriving at Clock FPGA a 238 Clock FesdbackSipinls aid Lob ter S ot i DIEN a uuu aswa 239 Clocking Pinouts for DACs and ADGS5 239 DAC Signal PINOUTS du ban hdd pii dam 239 ADC Signal PIDOUES oos tem ti sterii a edt emi eis ds 240 User LO Header J16 on module ictus de matin 241 Part XIII Troubleshooting 243 p lome 245 XtremeDSP Development Kit IV FAQS 1 245 NT107 0272 Issue March 9 2005 www nallatech com xi xii www nallatech com NT107 0272 Issue March 9 2005 NALLATECH XtremeDSP Development Kit IV User Guide The High Performance FPGA Solutions Company About this User Guide This User Guide provides detailed information on the XtremeDSP Development Kit IV It allows yo
93. 4 DAC2_D lt 5 gt F9 DACI_D lt 6 gt A4 DAC2_D lt 6 gt E9 DACI_D lt 7 gt B3 DAC2_D lt 7 gt 9 NT107 0272 Issue March 9 2005 Table 71 DAC Signal Pinouts www nallatech com 239 Pinout Information User FPGA 5 35 10 668 Signal DAC 1 PIN No DACI_D lt 8 gt Signal Name DAC 2 DAC2_D lt 8 gt NALLATECH User FPGA XC4VSX35 I0FF668 PIN No DACI_D lt 9 gt E6 DAC2_D lt 9 gt C8 0 lt 10 gt D6 DAC2_D lt 10 gt E7 DACI_D lt I1 gt A6 DAC2 D II D7 DACI_D lt 12 gt A5 2 0 lt 12 gt 9 DACI_D lt 13 gt B4 DAC2 D 13 F7 DACI DIVO F4 DAC2 DIVO 2 DACI_DIVI DACI MODO MODI DAC2 DIVI DAC2 MODO DAC2 MODI DACI_PLLLOCK 6 DAC2_PLLLOCK BIO RESET E5 2 RESET 10 Table 71 DAC Signal Pinouts 24 10 ADC Signal Pinouts User FPGA XC4VSX35 10 668 PIN No Signal DAC 1 Signal Name DAC 2 User FPGA XC4VSX35 IOFF668 PIN No ADCI_D lt 0 gt ADC2_D lt 0 gt ADCI_D lt I gt DI9 ADC2_D lt I gt D25 ADCI_D lt 2 gt D20 ADC2_D lt 2 gt C26 ADCI_D lt 3 gt ADC2_D lt 3 gt ADCI_D lt 4 gt ADC2_D lt 4 gt ADCI_D lt 5 gt DI8 ADC2_D lt 5 gt C25 ADCI_D lt 6 gt CI9 ADC2 lt 6 gt D22 lt 7 gt C20 ADC2 lt 7
94. 7 11 LED Greenl lt 0 else LED Greenl lt end if 11 then if ADC2 Di 6 downto 0 111 LED Red2 lt 0 else LED Red2 lt end if 1 then if ADC2 Di 13 downto 7 11 LED Green2 lt 0 else LED Green2 lt end if end if end process 11 then end structural Registering the ADC inputs is important to ensure that the data is properly captured into the clock domain This is to en sure timing requirements are met This process is a simple setup to look for specific values on the ADC inputs Remember that the ADC inputs are 2s complement format therefore the current default values used here to match are for an overall value of The process will illuminates LEDs if any of the values match Note that for the LEDs to light they require a LOW i e 0 value must be driven into them For the sake of experimentation these match values or even the slicing of the ADC data buses can be changed if required NALLATECH High Performance FPGA Solutions Company NALLATECH XtremeDSP Development Kit IV User Guide The High Performance FPGA Solutions Company 17 3 ADC to DAC Example 17 3 1 Example Overview The purpose of this example is to demonstrate a simple ADC to DAC hookup with a count driven out of the LEDs The design captures data from the ADCs registering it and then outputs this on the DACs with a slight conversion to change from Two s
95. AC and DACI DIV etc Note the inclusion of the CONFIG DONE output signal which should be driven low when the design configures to indicate to the reset of the system that it has configured www nallatech com NT107 0272 Issue March 9 2005 FPG NT107 0272 Issue March 9 2005 ATECH Solutions Company XtremeDSP Development Kit IV User Guide architecture Behavioral of Toplevel is clock components component BUFG port l in std logic out std logic end component component IBUFG port l in std_logic O out std_logic end component component DCM generic DLL FREQUENCY MODE string LOW DUTY CYCLE CORRECTION string TRUE STARTUP WAIT string FALSE y port CLKIN in std logic CLKFB n std logic DSSEN n std logic PSINCDEC in std logic PSEN in std logic PSCLK std logic RST in std logic CLKO out std logic CLK90 out std logic 80 out std logic CLK270 out std logic CLK2X out std logic CLK2X 180 out std logic CLKDV out std logic CLKFX out std logi CLKFX180 out std logic LOCKED out std logic PSDONE out std logic STATUS out std logic vector 7 downto 0 end component end of clock components internal clock and reset signals signal CLKIN_OSC CLKFB_OSC CLK_OSC RESET RSTI std logic temporary registers signal ADCI ADC2 std_logic_vector 13
96. B USB Cable 2m Long MCX to BNC Cable Im Long BenADDA DIME II Module PECA PCI Backplate assembly BNC Jack to Jack Adaptor Power Supply Unit XtremeDSP Development Kit IV Carry Case XtremeDSP Development Kit IV CD Wallet Table 2 Kit Contents NT107 0272 Issue March 9 2005 www nallatech com Physical Layout E 3 2 XtremeDSP Development Kit IV Board Case Layout The main hardware for the Kit is fitted inside a small blue case which provides protection for the board and also a degree of EMI shielding Figure 5 on page 16 highlights the key features of the board case Cooling to the main FPGA is provided by a small fan that draws cold air in through a main fan vent The FPGA can be configured with a design that will create a large amount of heat Therefore it may be necessary to remove the lid of the case when running certain high power designs Please refer to Cooling on page 102 for more details 3 2 1 Front Fan Vent Motherboard Status LEDs NALLATECH Main Power Input Power ADC inputs LEDs DAC outputs USB Connection External Clock input Va MEX Parallel IV JTAG connectar P Cable Access ower LEDs User Tricolor LEDs Figure 5 Board Case Front 3 2 2 Left Side MCX Connectors Figure 6 Board Case left side showing MCX Connectors 16 www nallatech com NT107 0272 Issue March 9 2005 A NALL ATECH XtremeDSP Development Kit
97. B inverting the top bit of the ADC data The reason for the ADC2 lt ADC2 D additional inversion of the whole value is because the op amp DACI D lt not not ADCI 13 amp ADCI I2 downto 0 DAC2 D lt not not ADC2 13 amp ADC2 12 downto 0 that drives out of the final MCX connector is an inverting ob end if amp end process flasher section led flash counter process CLK_OSC RSTI variable COUNT std_logic_vector 26 downto 0 Finally a counter is inferred and the more significant bits are begin connected up to the LEDs on the module if RSTI 0 then COUNT others gt 0 led assignments LEDI_Red lt 0 LED2_Red lt 0 LEDI Green lt 0 LED2_Green lt 0 elsif CLK_OSC l and CLK OSC event then COUNT COUNT 1 led assignments LEDI_Red lt COUNT 26 LED2_Red lt COUNT 25 LEDI_Green lt COUNT 25 LED2_Green lt COUNT 26 end if end process end of led flasher 17 4 Host Interface Example 17 4 1 Example Overview The XtremeDSP Development Kit IV CD and installation also includes an example of a host interface that makes use of the Interface FPGA to User FPGA Interface Core This example is based on the information included in the applications notes PCI to User Interface Core Included on the FUSE CD XtremeDSP Kit Ping Example Included on the XtremeDSP Development Kit IV CD This example is in
98. BTB_CLK_FB_IN Figure 38 Clock Structure 10 2 3 Source Descriptions Programmable Oscillators The Programmable Oscillators are controlled via FUSE Software through any of the available interfaces APls The available operating frequencies of the programmable oscillators are as follows 20 MHz 25 MHz 30 MHz 33 33 MHz 40 MHz 45 MHz 50 MHz 60 MHz 66 66 MHz 70 MHz 75 MHz 80 MHz 90 MHz 100 MHz 120 MHz NT107 0272 Issue March 9 2005 www nallatech com 65 Clocks 66 When a frequency is requested using FUSE which does not exactly match one of the fifteen frequencies supported by the oscillators the firmware looks at the available frequencies and selects the one that is numerically closest to the frequency requested Additionally for interfacing with the Interface 25200 or where the Nallatech Interface FPGA to User FPGA Interfacing core is used this interfacing should be clocked by the Clock B which should be set within the range 35MHz 40MHz One programmable oscillator drives CLKA net and the other drives CLKB net into the main User FPGA See Part Ill System Level Design on page 109 for more details Motherboard Fixed External Oscillator A Fixed Oscillator can be fitted to the Kit hardware to provide a clock source which matches the user s frequency jitter specification for more specialized applications The socket accepts 4 pin or 8 pin type 3 3V oscillator packages which can be
99. BUS lt 3 gt PB4 25 ADIO lt 4 gt LBUS lt 4 gt PB6 U20 ADIO lt 5 gt LBUS lt 5 gt PB7 21 ADIO lt 6 gt LBUS lt 6 gt PB8 U22 ADIO lt 7 gt LBUS lt 7 gt PB9 U24 ADIO lt 8 gt LBUS lt 8 gt PBIO U25 ADIO lt 9 gt LBUS lt 9 gt PBI U26 ADIO lt 10 gt LBUS 10 PBI2 TI9 ADIO lt I gt LBUS lt I gt T20 ADIO I2 05 lt 12 gt 5 21 ADIO lt 13 gt LBUS lt 13 gt 16 T23 ADIO lt 14 gt LBUS lt 14 gt PBI7 T24 ADIO lt 15 gt LBUS lt 15 gt PBI8 T26 lt 16 gt LBUS lt 16 gt 19 RI9 ADIO lt 17 gt LBUS lt 17 gt PB20 R20 ADIO lt 18 gt LBUS lt 18 gt 2 R23 ADIO lt 19 gt LBUS lt 19 gt PB22 R24 ADIO lt 20 gt LBUS lt 20 gt PB24 R25 ADIO lt 21 gt LBUS lt 21 gt PB25 R26 ADIO lt 22 gt LBUS lt 22 gt PB26 PI9 ADIO lt 23 gt LBUS lt 23 gt PB27 P20 ADIO lt 24 gt LBUS lt 24 gt PB28 P22 ADIO lt 25 gt LBUS lt 25 gt PB29 P23 ADIO lt 26 gt LBUS lt 26 gt PB30 P24 ADIO lt 27 gt LBUS lt 27 gt 25 ADIO lt 28 gt LBUS lt 28 gt PB33 N20 ADIO lt 29 gt LBUS lt 29 gt PB34 N23 ADIO lt 30 gt LBUS lt 30 gt PB35 21 Table 47 Interface to User FPGA Comms Signals www nallatech com NT107 0272 Issue March 9 2005 The High Performance FPGA Solutions Company NALL ATECH XtremeDSP Development Kit IV User Guide Interface COMM General Bus Signal DIME II Connector User FPGA XC4VSX35 Signal Name PIN No IOFF668 Pin No ADIO lt 31 gt LBUS lt 31 gt
100. CLKOP Generated N8 GCLKIS 2 Generated 7 GCLK6P 5 Generated Clock GEN_CLKD N7 GCLK7S 4 Generated Clock D Table 68 Clock Signals at CLK FPGA 238 www nallatech com NT107 0272 Issue March 9 2005 NALLATECH The High Performance FPGA Solutions Comp 24 8 2 Signal Clock Feedback Signals CLK FPGA 2V80 Pin No XtremeDSP Development Kit IV User Guide User FPGA XC4VSX35 10FF668 PIN No Signal Description CLKI_FB J2 4 Feedback to User FPGA CLK3_FB H4 BI5 Feedback to User FPGA CLK2 FB HI2 15 Feedback to User Table 69 Clock Feedback Signals 24 8 3 Clocking Pinouts for DACs and ADCs Signal Name Clock FPGA XC2V80 4CS144 Pin No ADC CLKA E4 _ 1 ADC_CLKB GI ADC_CLKBI FI DAC_CLKA DI3 DAC CLKAI DI2 DAC CLKB GIO DAC CLKBI FI2 Signal Name DAC I DACI_D lt 0 gt Table 70 Clocking Pinouts for DACs and ADCs 24 9 DAC Signal Pinouts User FPGA 5 35 10 668 Signal Name DAC 2 DAC2_D lt 0 gt User FPGA 5 35 10 668 PIN No DACI_D lt I gt C7 DAC2_D lt I gt FIO DACI_D lt 2 gt B7 DAC2_D lt 2 gt CIO DACI D 3 DACI D 4 DAC2 D 3 DAC2 lt 4 gt DACI_D lt 5 gt C
101. Component Generation Once the ICON component has been generated Figure 88 on page 166 click Start Over to generate the ILA component Generate the ILA Core The second component to generate is the ILA Integrated Logic Analyzer In the screen shown in Figure 89 on page 166 select ILA as the type ChipScope Pro Core Generator Select Core To Generate C ICON ntegrated Controller Qehegraled Logic Analyzer ILNATC ntoprated Logic Analyzer with Agilent Trace Core Qmegratod Bus Analyzer for On Chip Peripheral Bus C IBAJPLB integrated Dus Analyzer for Processor Local Dus Virtual Core C Aglent Trace Core 2 Figure 89 Actual Component Generation www nallatech com NT107 0272 Issue March 9 2005 NALLATEC e a XtremeDSP Development Kit IV User Guide Click Next to continue to the settings for the ILA component and set the output netlist folder as shown in Figure 90 on page 167 M Design Hes icon ean Device Settings Device Fora ICON Parameters number orceenoi Pons 7 gt Select the output netlist Disaete Boundary Scan Component Instance folder For the sake of Boundary Sean Chain mem h 4 h Disable Clock BUFG Insertion t e examp e set It to t e nabio Used powder Scan Pors same location as the Xilinx ISE project file
102. D lt 18 gt AF8 ZBTA_D lt 19 gt AA7 ZBTA_D lt 20 gt 10 ZBTA 0 lt 21 gt 9 ZBTA D 22 AF9 ZBTA D 23 AD8 ZBTA D 24 Y6 ZBTA D 25 AE6 ZBTA D 26 AB5 ZBTA D 27 AD5 ZBTA D 28 AF7 ZBTA D 29 AD6 ZBTA D 30 AF5 ZBTA D 3l 5 Table 64 Data Signals Pinouts Bank 24 7 2 ZBT SRAM Bank B Clock Control Signals for ZB T Signal Name User FPGA XC4VSX35 10FF668 PIN No ZBTB_CLK AEI4 ZBTB CLK FB OUT ABI7 ZBTB CLK FB IN ACI7 ZBTB ADV 17 ZBTB_CKEI 17 ZBTB_CSI lt 0 gt 14 ZBTB_CSI lt I gt 15 ZBTB_OEI ACI8 ZBTB_WEI AEI8 Table 65 ZBT Clock and Control Signals 236 www nallatech com NT107 0272 Issue March 9 2005 NALLATECH ZBT Address Signals for Bank B ZBTB_A lt 0 gt Signal Name User FPGA XC4VSX35 IOFF668 PIN No ZBTB A II Signal Name XtremeDSP Development Kit IV User Guide ZBTB lt gt Y25 ZBTB lt 12 gt AF24 ZBTB lt 2 gt Y18 ZBTB_A lt 13 gt AA26 ZBTB_A lt 3 gt AE24 ZBTB_A lt 14 gt AB26 ZBTB_A lt 4 gt 5 ZBTB lt 15 gt Y26 ZBTB lt 5 gt AFI8 ZBTB lt 16 gt AD25 ZBTB lt 6 gt ZBTB lt 7 gt ZBTB lt 17 gt ZBTB lt 18 gt ZBTB A 8 W25 ZBTB_A lt 9 gt AC24 ZBTB_A lt 10 gt AB25 User FPGA XC4VSX35 10 668 PIN Table 66 ZBT Address Signals Pinouts Bank ZBT Data Signal
103. DCs and DACs as ADCI D in std logic vector 13 downto 0 well as the main User FPGA ADC2 D std logic vector 13 downto 0 adc dry signals ADCI DRY std logic ADC2 DRY std logic led flash signals used to give some indications LED Redl out std logic LED Red2 out std logic LED Greenl out std logic LED Green2 out std logic end simple adc hookup architecture structural of simple adc hookup is signal ADCI Di ADC2 Di std logic vector 13 downto 0 internal versions of the ADC data signals begin module configured CONFIG DONE lt 0 register the adc inputs NT107 0272 Issue March 9 2005 www nallatech com 133 Feature Examples 134 www nallatech com NT107 0272 Issue March 9 2005 adcDataRegisters process FB begin if RESETI 0 then ADCI_Di lt others gt 0 ADC2_Di lt others gt 0 elsif CLKI_FB l and CLKI_FB event then ADCI Di lt ADCI D ADC2 Di ADC2 D end if end process led flasher section process FB RESETI begin if RESETI 0 then led assignments LED lt LED Red2 LED Greenl lt 1 LED Green2 lt elsif and FB 1 then led assignments inverted as leds are active low if Di 6 downto 0 I111111 then LED lt 0 else LED Redl lt 1 end if if ADCI_DI 13 downto
104. ETURN RETURN RETURN wm G N Table 45 Mini DIN Pinout Additional Power Connector J20 If you are developing large designs with the board plugged in PCI connection you may require high current ratings Nallatech therefore advise the use of this additional power input connector to increase the power rating You will see however that this connector is limited to supplying only the positive supplies Supply Voltage Pin Looking at connector 12 7 gt gt RETURN 2 Y RETURN 3 LI 5V 4 Table 46 Additional Power Connector Disk Drive Style 104 www nallatech com NT107 0272 Issue March 9 2005 A NALLATECH XtremeDSP Development Kit IV User Guide The High Performance FPGA Solutions Company If the Kit is connected to a PCI slot this connector if used must be connected to the same ATX power supply that is powering the slot Alternatively if the Kit is operating as a standalone unit this can be connected to any external source However ensure that if a power supply is also connected to the Mini DIN connector it is not attempting to power the 5V and 12V rails 13 3 Enabling Power Supplies at Power On using External Power Supply and JTAG connectors The USB firmware has the option of automatically turning on the power supplies to the module when the main power is applied from the ext
105. FPGA Clock nets Note that clock C is NOT initially available in the Kit It is a socket source clocks generated lt User Signals part or in whole associated with to allow users to populate their own crystals if required clocks and feedback clock the FPGAs nets gt Figure 49 Bus Functional Diagram 11 3 Firmware Nallatech provide cores for connecting the Local Bus and Adjacent Out Bus to user designs Please see Part Ill System Level Design on page 109 which describes how to build a host interface 11 4 Software There are no specific software functions in the FUSE API for controlling the actual bus functionality as this is a defined hardware architecture NT107 0272 Issue March 9 2005 www nallatech com 81 Bus Structure NALLATEC Performance FPGA Solutions Company 82 www nallatech com NT107 0272 Issue March 9 2005 NALLATECH XtremeDSP Development Kit IV User Guide Section 12 Board and System Level Monitoring Capabilities In this section Introduction to the System Monitoring Capabilities of the Kit Hardware Aspects Firmware Aspects Software Aspects NT107 0272 Issue March 9 2005 www nallatech com 83 Board and System Level Monitoring Capabilities NALLATECH The High Performance FPGA Solutions Comp any 84 12 1 Introduction The Kit has a number of mechanisms for monitoring and or board level hardware control These can be broken down i
106. G port eliminating the need to drive data off chip using I O pins Please refer to the following Web page for further details on Chipscope Pro http www xilinx com chipscope 22 6 3 in System Generator This example shows how to modify a Simulink model to integrate the Chipscope block and to select the data to be captured and viewed for debugging The steps are as follows v To modify a Simulink model for Chipscope integration use the following procedures From the MATLAB console change the directory SYSGEN examples chipscope Here SYSGEN represents the location in which you have installed System Generator the default location is MATLAB toolbox xilinx sysgen The following files are located in this directory chip mdl Your working model chip_soln mdl Solution model including the Chipscope blockset osc clock 2v80 bit Bitstream to program the XC2V80 device on the Kit This device is used for clock management and is required for proper operation 2 Open chip mdl model from the MATLAB console This model represents a simple sine cosine table driven by an 8 bit counter Both sine and cosine functions have been selected enabling you to probe and later plot both waveforms 3 The 8 bit counter counts modulo 255 This is used to trigger Chipscope The most significant bit is extracted with a slice block and drives a LED on the XtremeDSP Development Kit IV ES inj xj File Edt View
107. IGNED all entity Toplevel is Top level entity In this example FB is fed down from 136 port main clock input from oscilator FB std logic main reset input from mb RESETI in std logic configuration done signal CONFIG DONE out std logic dac 14 bit data outputs DACI D outstd logic vector 13 downto 0 DAC2 D outstd logic vector 13 downto 0 adc 14 bit data inputs ADCI D std logic vector 13 downto 0 ADC2 D std logic 13 downto 0 dac reset signals DACI RESET out std logic DAC2 RESET out std logic dac setup DACI MODO out std logic DACI MODI out std logic DAC2 MODO out std logic DAC2 MODI out std logic dac clock divider setup out std logic DACI DIVI out std logic DAC2 DIVO out std logic DAC2 DIVI out std logic led flash signals LEDI Red out std logic LED2 Red out std logic LEDI Green out std logic LED2 Green out std logic end Toplevel the Clock FPGA to the User FPGA Tthe standard clock bitfile osc clk 2v80 bit is used that simply takes the 105MHz module crystal clock source and sends it to the ADCs and DACs as well as the main User FPGA In this example the RESETI is the active low System Reset signal that can be controlled via FUSE It connects the data buses from the ADCs and DACs also has pins defined to control the operational mode of the DACs These pins are D
108. II Connector PIN User FPGA XC4VSX35 I0FF668 PIN No ADJIN lt 0 gt PA29 K26 ADJIN I PA30 K25 ADJIN lt 2 gt 19 ADJIN lt 3 gt PA32 NI9 ADJIN lt 4 gt PA33 N25 ADJIN lt 5 gt PA34 N24 ADJIN lt 6 gt PA35 21 ADJIN lt 7 gt PA36 M20 ADJIN lt 8 gt PA38 M23 ADJIN lt 9 gt PA39 M22 ADJIN lt 10 gt PA40 M25 ADJIN lt I I PA4I M24 ADJIN lt 12 gt PA42 L26 ADJIN 13 PA43 M26 ADJIN lt 14 gt PA44 119 ADJIN 15 PA45 K20 ADJIN 16 PA47 L21 lt 17 gt 48 120 ADJIN lt 18 gt PA49 L24 ADJIN lt 19 gt PA50 L23 ADJIN lt 20 gt PAS K22 ADJIN lt 21 gt 52 K2l ADJIN lt 22 gt 5 24 ADJIN lt 23 gt PA54 K23 ADJIN lt 24 gt PA56 J21 ADJIN lt 25 gt PA57 J20 ADJIN lt 26 gt PA58 J23 ADJIN lt 27 gt PA59 J22 Table 55 Adjacent IN BUS Pinouts User FPGA XC4VSX35 10FF668 NT107 0272 Issue March 9 2005 www nallatech com 231 Pinout Information NALLATECH 24 4 PLINKS 0 PLINK Header J10 Signal Name DIME II Connector PIN No User FPGA 4 5 35 10 668 PIN No PPOLK 0 PA2 W7 PPOLK lt 1 gt PA3 v7 PPOLK lt 2 gt PAA T8 PPOLK lt 3 gt PA5 U7 PPOLK lt 4 gt PA6 R8 PPOLK lt 5 gt PA7 R7 PPOLK lt 6 gt PA8 P8 PPOLK lt 7 gt PA9 N8 PPOLK lt 8 gt PAI N7 PPOLK lt 9 gt PAI2 M7 PPOLK lt 10 gt PAI3 M8 PPOLK II PAI4 L8 Table 56 PLINK Pinouts User FPGA 4 5 35 10 668 24 5 PLINKS 7 Nallatech RS232 Connectio
109. IMEscript User Guide FUSE CD Nallatech FUSE C C API Developers Guide FUSE CD Nallatech FUSE System Software User Guide FUSE CD Nallatech PCI to User FPGA Interface Core Application Note FUSE CD Xilinx Virtex ll and Virtex 4 Datasheet available on Xilinx Website Abbreviations ADC Analog to Digital Converter Application Program Interface ATX Advanced Technology eXtended BIST Built In Self Test DAC Digital to Analog Converter DCM Digital Clock Manager DIME DSP and Image Processing Modules for Enhanced FPGAs DLL Delay Locked Loop EDK Embedded Developer s Kit Effective Number of Bits FPGA Field Programmable Gate Array FPS Fixed Power Supply www nallatech com NT107 0272 Issue March 9 2005 The High Performance FPGA Solutions Company XtremeDSP Development Kit IV User Guide FUSE GUI ILA HO JTAG LVDS LVTTL PCB PCI PLL PPS SNR SRAM VCO VHDL 7 Field Upgradeable System Environment Graphical User Interface Integrated Logic Analyzer Input Output Joint Test Action Group Low Voltage Differential Signalling Low Voltage Transistor Transistor Logic Printed Circuit Board Peripheral Component Interconnect Phase Locked Loop Programmable Power Supply Signal to Noise Ratio Static Random Access Memory Voltage Controlled Oscillator VH
110. IV Overview 3 XtremeDSP Development Kit IV Key Features 4 XtremeDSP Development Kit IV Functional Diagram 6 Introduction to Nallatech Systems and Solutions 9 9 Motherboards and Modules 9 eee eects ee eer ee ona 10 FUSE Operating SyStem ae M orci aei e aci eda 10 u masan sa II DIMESCFIPt a a ann E Buc d E Part ll XtremeDSP Development Kit IV Features Physical Layout anne eee oni 15 XtremeDSP Development Kit IV Overview ss 15 XtremeDSP Development Kit IV Board Case l6 re eR 16 efe side a ss s ee 16 Right Te NR ERU 17 XtremeDSP Development Kit IV Hardware Physical Layout 17 Front 17 Back 18 19 D 19 ADC Architect re M u 20 Hardware ua u E 21 Analog ADC M 21 ADC Clocking u u
111. LEDs char ErrorString 1000 DIME_HANDLE hCardl double ActualFrequency VIDIME_HANDLE viHandle DWORD Result error 0 DWORD 0 DWORD ReadData 2048 DWORD WriteData 2048 for j 0 j lt 2048 j WriteData j j 1 ReadData j 0 printf BIST Embedded Test Test the function to locate all Nallatech cards on the PCI interface if hLocate DIME_LocateCard dIPCl mbtALL NULL dldrDEFAULT dIDEFAULT NULL Error hLocate NULL Print the error then terminate the program DIME_GetError NULL amp ErrorNum ErrorString printf Error Number d printf s exit 1 Determine how many Nallatech cards have been found NumOfCards DIME_LocateStatus hLocate 0 dINUMCARDS printf d Nallatech card s found Header files are included here Dimesdl h contains the main FUSE header for the API This contains a number of declarations that are used in the following code Vidime h contains the header for the functions used to simplify the software interface to the Interface FPGA to User FPGA Core A few variables are defined here for ease of use They are pre set for the XtremeDSP Kit and do not need to be changed Filenames are then specified for the purposes of the example The main function includes more declarations for variables in the system Also some data areas are reserved statically i e ReadData and WriteData These are used to demonstrate data transfer to and from the interface
112. LL is not locked due to the PLL being disabled or an unstable clock PLL LOCKED toggles between high and low in an asynchronous manner 5 2 2 DAC Modes of Operation In the introduction the MOD and DIV input control pins were highlighted These control the way in which the DAC operates The MOD and the DIV signals are controlled from the main User FPGA 4 5 35 10 668 As outlined earlier in this section the interpolation filter can be set to either a low or high pass characteristic depending on whether you wish to capture baseband or IF signals This feature of the 9772 and also the zero stuffing option is controlled by the FPGA The operation of the pins is summarized in Table 10 on page 32 Digital Mode Digital Filter Zero Stuffing Baseband 0 0 LOW NO Baseband 0 LOW YES Direct IF 0 HIGH NO Direct IF HIGH YES Table 10 Controlling Digital Modes of AD9772A The AD9772A contains an internal Voltage Controlled Oscillator VCO which can operate at up to 400MSPS To ensure the optimum phase noise and successful locking of the PLL a pre scalar stage is incorporated to allow the sampling clock to be divided down as required for slower data rates The divide by ratio is selected by the DIV0 and DIVI inputs as shown in Table 11 on page 32 Input Data MODI Zero Divide by N ratio Rate stuffing 5 5 48 160 0 0 0 24 100 0 0 2 12 50 0 0
113. MPI 85 Terral clock distribution i e BUFG and OBUFs and Ono 84 s12 SX N35 K D N35 N35 DCM Internally de skewed ABIQ 2 circuit This net is the same physical length as the ZBTA CLK_FB_OUT ZBT signal to the AEI2 ZBTA FB IN ZBT Memory This allows for de skewing Main FPGA Virtex 4 XC4VSX35 ZBTB CLK ZBTB CLK FB OUT ZBTB CLK FB IN Figure 46 Using one of the DIME Clocks to Clock the ADCs and DACs This is achieved by feeding through any one of the DIME clocks to one of the GEN CLK nets within the main User FPGA On the Clock FPGA this is distributed to the ADCs DACs and also fed back down one of the FB nets for use in designs on the main FPGA The CLK FB nets and the nets to the ADCs and DACs are the same physical lengths the board and so the skews on signals travelling down these nets will be matched Therefore to ensure the clocks reach the ADCs and and a clock in the main User FPGA create a DCM circuit to de skew the internal to the main User FPGA Aspects of Clock Selection and Clock Jitter With the number of available clocking options available it is important to understand some of the factors involved when deciding how to manage the clocks in your design One of these key factors is selecting the clock for the ADCs and DACs Th
114. Motherboards and Modules Nallatech provide a comprehensive range of motherboards and modules which can be used in a variety of applications The XtremeDSP Development Kit IV provides a PCI USB motherboard that can support a single specific module The module used is the BenADDA that provides FPGA resources in addition to ADC inputs and DAC outputs Nallatech motherboards and modules are designed to a standard called DIME II NT107 0272 Issue March 9 2005 www nallatech com 9 Introduction to Nallatech Systems and Solutions 2 3 DIME II Standard DIME II is a modular standard developed specifically for Field Programmable Gate Arrays FPGAs which allows design engineers to develop re programmable systems with the opportunity to alter or experiment with the partitioning of their designs at any stage of the design cycle DIME II has been introduced in response to ever increasing bandwidth and performance requirements This standard addresses the high performance needs for future generations of reconfigurable computers Software support for DIME II hardware is provided by FUSE 2 4 FUSE Operating System Nallatech s FUSE System Software provides configuration control and communications functionality between host systems and Nallatech FPGA computing hardware This enables developers to design complex processing systems with seamless integration between software hardware and FPGA applications FUSE provides several interfaces
115. N No CONFIG_DONE _ PC40 CONFIG_DONE N A ACI CLK0 CLKA PC24 AFI2 CLKI CLKB PC3I 16 CLK2 CLKC PC42 AFI I RESETI RESETI PCI5 H3 SLOT_ID0 SLOT_ID0 PC5I H5 SLOT IDI SLOT IDI PC52 H4 Table 59 User FPGA Specific Pinouts 4 5 35 10 668 a CONFIG DONE is driven from the I O of the Virtex ll into the base of the transistor to signal that the on board User FPGA has been configured successfully User to drive this pin LOW once the FPGA is configured NT107 0272 Issue March 9 2005 www nallatech com 233 Pinout Information NALLATECH The High Perform FPGA Solutions Comp any 24 6 2 User LEDs Signal Name User FPGA XC4VSX35 10FF668 PIN No LED_Green E26 LED D26 LED_Green2 D3 LED_Red2 F3 Table 60 User LED Pinouts User FPGA XC4VSX35 10FF668 24 6 3 On Board Temperature Sensor Signal Name User FPGA XC4VSX35 10FF668 PIN No Table 61 Temperature Sensor Pinouts 4 5 35 10 668 24 7 ZBT SRAM 24 7 ZBT SRAM Bank A Clock and Control Signals for ZBT Signal Name User FPGA XC4VSX35 10FF668 PIN No ZBTA_CLK ABIO ZBTA_CLK_FB_OUT ACI0 ZBTA_CLK_FB_IN 12 ZBTA_ADV ZBTA_CKEI AAI4 2 51 lt 0 gt 14 ZBTA_CSI lt I gt ACI4 7 _ ZBTA_WEI ADII Table 62 ZBT Clock and Control Signals 234 www nallatech com NT107 0272 Issue March 9 2005
116. ORT DWORD viDIME DMARead VIDIME HANDLE handle DWORD xData DWORD WordCount DWORD DMAChannel volatile DWORD Terminate DWORD Currcount DWORD Timeout NALLAEXPORT DWORD viDIME_DMAWrite VIDIME HANDLE handle DWORD Data DWORD WordCount DWORD DMAChannel volatile DWORD Terminate DWORD xCurrcount DWORD Timeout CMANGLE NALLAEXPORT DWORD viDIME GetVersionNumber void Figure 69 Section of vidime h After you have obtained a handle to the card the FUSE API DIME_LocateCard and DIME_OpenCard functions allow access to the interface in the design Full details of these functions are available in the FUSE C C API Developers Guide included on the FUSE CD v To use the FUSE API to send and receive data across the PCI or USB interface l Obtain a Locate Handle to the detected hardware in the system using the DIME LocateCard Function 2 Obtain Card Handle for a specific card the system using the DIME OpenCard function Use the Locate Handle as a parameter 3 Then use the Card Handle with the functions to control the resets clocks and configure the FPGAs www nallatech com NT107 0272 Issue March 9 2005 NALLATECH XtremeDSP Development Kit IV User Guide AEN ihe High Performance FPGA Solutions Company 4 Now obtain a handle for talking to the vidime interface do this use the viDIME_Open function This function locks down required memory and other initialization functions for the other
117. SIC Very High Speed Integrated Circuits Hardware Description Language Zero Bus Turnaround memory Typographical Conventions The following typographical convention are used in this manual i Red text indicates a cross reference to information within the document set you are currently reading Click the red text to go to the referenced item To return to the original page right click anywhere on the current page and select Go To Previous View Blue underlined text indicates link Web page Click blue underlined text browse the specified Web site Italics denotes the following items References to other documents See the FUSE System Software User Guide for more information Emphasis in text NT107 0272 Issue March 9 2005 Enable Loopback should not be enabled until all other registers have been set up www nallatech com xv NALLATECH The High Performance FPGA Solutions Comp any FUSE Naming Conventions Please note that the XtremeDSP Development Kit IV clocks are named differently in the FUSE System Software compared to this User Guide The clock naming conventions are shown in Table on page xvi Clock Names in FUSE Clock Names in Documentation System Clock SYSCLK Clock CLK DSP Clock DSPCLK Clock B CLK B Pixel Clock PIXCLK Clock C CLK C Table 1 FUSE Naming Conventions For more information on how the clocks are named please see
118. SOFTWARE LICENSING AGREEMENT Nallatech Ltd software is licensed for use by end users under the following conditions By installing the software you agree to be bound the terms of this license If you do not agree with the terms of this license do not install the Software and promptly return it to the place where you obtained it l License Nallatech Ltd grants you a licence to use the software programs and documentation in this pack age Licensed materials you have a single license on only one computer at a time or by only one user at a time if you have acquired multiple licenses the Software may be used on either stand alone computers or on com puter networks by a number of simultaneous users equal to or less than the number of licenses that you have acquired and if you maintain the confidentiality of the Software and documentation at all times 2 Restrictions This software contains trade secrets in its human perceivable form and to protect them except as permitted by applicable law you may not reverse engineer disassemble or otherwise reduce the software to any human perceivable form You may not modify translate rent lease loan or create derivative works based upon the software or part thereof with out a specific run time licence from Nallatech Ltd 3 Copyright Licensed Materials Copyrighted Accordingly you may either make one copy of the Licensed Materials for backup and or arc
119. Smponent P FAS r Figure 16 Assembly Drawing 4 3 Firmware The ADC is connected to the main User FPGA via a number of signals The following signals are highlighted here for ADCI although there are a corresponding set of signals for ADC2 ADCI D 13 downto 0 This is the two complement output of the ADC Bit 13 is the most significant bit ADCI DRY This is the Data Ready Output from the ADC This is a is an inverted and delayed version of the encode clock Any change in the duty cycle of the clock will correspondingly change the duty cycle of DRY ADCI OVR Overrange Bit high indicates analog input exceeds t Full Scale FS Please note that the output of the ADC is in twos complement format NT107 0272 Issue March 9 2005 www nallatech com 27 NALLATECH The High Performance FPGA Solutions Comp any The only signals you require the actual data bits i e ADCI_D 13 downto 0 for and ADC2 13 downto 0 for ADC2 It is recommended that when these signals come into your FPGA design they are registered clocked in by your relevant design clock Figure 17 on page 28 shows an example adcDataRegisters process FB begin if 1 0 then 0 1 Di lt others gt 0 DC2 Di lt others gt 0 elsif FB l and FB event then ADC Di lt ADCl D ADC2 Di lt ADC2 D end if en
120. Software 15 4 1 FUSE API Interlinks The C C FUSE API provides a number of low level functions for sending and receiving data across the PCI or USB interface In order to simplify the software interface when using the Interface FPGA to User FPGA interface core an additional library has been created called This is provided as a header file vidime h with associated library files vidime lib is the COFF format library suitable for Microsoft Visual Studio and other tools that use the COFF format vidimomf lib is the OMF equivalent library for use with tools such as Borland that use the OMF object model format All these files are located in the include sub folder where FUSE was installed typedef void VIDIME_HANDLE CMANGLE NALLAEXPORT DWORD viDIMEError CMANGLE NALLAEXPORT char viDIMEErrorText 200 define viDMACSRREG 0 def ine viDMACOUNTREG 1 4 ine viDMADISABLE 0 define viDMAENABLE 1 def ine viDMAREADDIRECTION 0 2 def ine viDMAWRITEDIRECTION 0 NALLAEXPORT VIDIME HANDLE viDIME Open DIME_HANDLE DHandle DWORD flags NALLAEXPORT void viDIME Close VIDIME HANDLE handle NALLAEXPORT DWORD viDIME WriteRegister VIDIME HANDLE handle DWORD Address DWORD Data DWORD Timeout NALLAEXPORT DWORD viDIME ReadRegister VIDIME HANDLE handle DWORD Address DWORD Timeout CMANGLE NALLAEXPORT DWORD viDIME DMAA bort VIDIME HANDLE handle NALLAEXP
121. Sources n Propet I syegengam 16 doi ck wacoer rel 4245 10553 conv conv pig ved 7 gengan 16_dpkr_ck_nrnpper eteoctuni sysgenqum 16 doi ck V syegercas 16 ryegencam 16 doi fies vd syspenamm 16 doi adactve eauakzeretructunsl sysgengam 1E 16 dol slu structursl nysgenqem 16 dok fles 16 dpr 9949 behavior inyagencem 16 4 7 adder attracter_vrtex4_7_0_1135763902026 Processes for Source sysgenqam 16 ck wrapper structural Manaty Pisce 8 Route FPGA Eater Generate Senuistion Model Pace Route Rapat Aionas Delay Repot B Pad Report Gode Rents Recor Generate Post Place 8 Static Ting Edt Design Roceplanner Wen Edt Routed Design FPGA Editor Generate Post 1 Route Sexulaton Model O Musu Place amp Route Bacicannctate Pin Locations 8 entity sysgenqaml dpir cik wrapper pert Figure 114 QAM Design in ISE Project Navigator Right click the process for Generate Programming File and select Properties This brings up the options for creating the bitstream for the FPGA itself Click on the Startup tab and set the startup clock to JTAG as shown in Figure 115 on page 196 Process Properties FPGA Start Up Clock Enable intemal Done Pipe Done
122. T_D lt 29 gt AD6 ZBT_D lt 30 gt AF5 ZBT_D lt 31 gt AC5 Table 14 ZBT Data Signals Pinouts Bank A 44 www nallatech com NT107 0272 Issue March 9 2005 NALLATECH Clock and Control Signals for ZBT Bank B Signal Name User FPGA XC4VSX35 10FF668 PIN No XtremeDSP Development Kit IV User Guide ZBTB CLK AEI4 ZBTB CLK FB OUT ABI7 ZBTB CLK FB IN ACI7 ZBTB ADV YI7 ZBTB CKEI AAI7 ZBTB 51 lt 0 gt ADI4 ZBTB_CSI lt I gt 15 ZBTB_OEI ACI8 ZBTB_WEI AEI8 ZBT Address Signals for Bank B Signal Name ZBTB_A lt 0 gt User FPGA XC4VSX35 10FF668 PIN ZBTB A II Signal Name Table 15 ZBT Clock and Control Signals Pinouts Bank B User FPGA XC4VSX35 10FF668 PIN ZBTB lt gt Y25 ZBTB_A lt 12 gt AF24 ZBTB_A lt 2 gt 8 ZBTB A I3 AA26 ZBTB lt 3 gt AE24 ZBTB lt 14 gt AB26 ZBTB lt 4 gt ACI5 ZBTB lt 15 gt Y26 ZBTB A 5 7 _ lt 16 gt ZBTB lt 6 gt ZBTB lt 17 gt ZBTB lt 7 gt 18 ZBTB_A lt 18 gt ABI8 ZBTB A 8 W25 ZBTB lt 19 gt AC26 ZBTB lt 9 gt AC24 ZBTB lt 10 gt AB25 ZBT Data Signals for Bank B Signal Name User FPGA XC4VSX35 10FF668 PIN No Table 16 ZBT Address Signals Pinouts Bank B ZBTB 0 lt 0 gt Y22 ZBTB D I Y23 ZBTB D 2 AB23 NT107 0272 Issue March 9 2005 Table 17 ZBT Data Signals P
123. WEN std logic signal FIFO_REN std logic signal FIFO IN std logic vector 31 downto 0 signal FIFO OUT std logic vector 31 downto 0 Define signals for the registers in the design signal REGI 4 logic vector 31 downto 0 signal REG2 std logic vector 31 downto 0 signal REGI WR std logic signal REG2 WR std logic signal REGI RD std logic signal REG2 RD std logic begin Invert the active low reset input to the FPGA to convert it to an active high reset RST EXT lt not RSTI Instantiate the clock module Inst dimeclk module dimeclk module port map rst gt RST EXT clkin gt CLKB locked out gt CLKB LOCKED out gt CLKBi y Create a register to register the locked signal into the clock domain before use in the rest of the system process CLKBi begin if CLKBi event and CLKBi 1 then RST INTI lt CLKB LOCKED end if This declaration is for a 511x32 FIFO which is included as a target for data The target can be burst to or from for read and writes from the host PC In this design we make use of a generated clock module that has been produced using the DCM Architecture Wizard in the Xilinx ISE tools Various internal signals are declared A number of signals are declared that represent the registers in the design Corresponding read and write control signals are also declared here The external active low reset is inverted here to provide
124. XtremeDSP Development Kit IV User Guide 107 0272 Issue I Document Name XtremeDSP Development Kit IV User Guide Document Number 107 0272 Issue Number Issue 1 Date of Issue 09 03 05 Revision History Date Issue Number Revision Trademark Information The Nallatech Logo the DIME logo the DIME II logo FUSE FIELD Upgradeable Systems Environment DIME DIME II XtremeDSP Development Kit IV and the Bally Ben and Strath product name prefixes are all trademarks of Nallatech Limited The Algorithms to Hardware Company Making Hardware Soft FPGA Centric Systems the only logical solution and software defined systems are Service Marks of Nallatech Limited All products or brand names mentioned herein are used for identification purposes only and are trademarks registered trademarks or service marks of their respective owners Copyright Information This document which is supplied in confidence is the copyright property of Nallatech Limited Neither the whole nor any extract may be disclosed loaned copied or used for any purpose other than those purposes for which written permission was given at the time of release Application for any uplifting or relaxation of these restrictions must be made in writing to Nallatech Limited who may at their discretion refuse any such application or give it qualified or absolute approval Copyright 1993 2005 Nallatech Limited All Rights Reserved www nall
125. ZBT you can use your own ZBT core or use an existing core provided by Nallatech On the XtremeDSP Development Kit IV CD an application note NT302 0036 XtremeDSP Kit ZBT Design is provided at the location ROM Drive Documentation Application_Notes This shows how a Nallatech specific core can be connected to the ZBT devices and also to a host interface so that data can be transferred to and from the ZBT by the host PC Details of the specific core are given in another application note NT302 0005 ZBT Controller in the same folder Please refer to both of these application notes for further details 6 4 Software There is no specific support for accessing the ZBT SRAM memory in the Kit from within the FUSE System Software If you want to capture data and read it back into the host machine this functionality needs in part to be provided by the user design Please refer to Part 5 Level Design on page 109 where aspects of building a host interface are discussed NT107 0272 Issue March 9 2005 www nallatech com 47 NALLATEC Y FPGA Solutions Company 48 www nallatech com NT107 0272 Issue March 9 2005 NALLATECH XtremeDSP Development Kit IV User Guide The High Performance FPGA Solutions Company Section 7 Digital In this section Introduction to the Digital I O Headers in the Kit Hardware Aspects Firmware Aspects Software Aspects 7 1 Introduction There are several features
126. abilities 11 2 Hardware DIME II Communication Busses Table 31 on page 80 provides details on the available I O for each of the communication busses Communication Bus XC4VSX35 10FF668 Notes Adjacent IN 28 bits Connects directly to the digital I O ADJACENT HEADER 8 Adjacent OUT 7 bits Provides the control and status signals for the interface to main User FPGA communication bus Local Bus 32 bits All 32 bits are used as the ADIO signals in the interface to main User FPGA communication bus Comm Link 0 12 bits Connects directly to the digital I O header 10 Comm Link 7 4 bits Connects to a Nallatech specific test header RS232 J9 Table 31 Bus Summary www nallatech com NT107 0272 Issue March 9 2005 NALL ATECH XtremeDSP Development Kit IV User Guide The High Performance FPGA Solutions Co Bus Structure Figure 49 on page 81 provides an overview of the bus structure in the Kit Spartan ll Interface FPGA Local Bus LBUS Virtex ll gt XC2V80 4CS144 User Clock Configured with Adjacent Out Bus ADJOUT ropriate Interface Control Virtex 4 Firmware 4 5 35 10 668 BEES Main User FPGA Programmable Clock Source B c Adjacent Comms P In Bus Link O ADJIN KEY Connected bus lt gt Signals predominantly associated with the general kit i e JTAG access lt Inter
127. age 21 with the MCX inputs corresponding to the ADCs The LEDs will change depending on the levels selected in the code 132 www nallatech com NT107 0272 Issue March 9 2005 ATEC XtremeDSP Development Kit IV User Guide FPGA Solutions Company Listing simple_adc_hookup vhd Title simple adc hoockup Project File simple adc hookup vhd Author lt derekstark DELL2000AXP gt Company Created 2003 11 11 Last update 2003 11 11 Platform Standard VHDL 87 Description Showing a simple ADC hookup in the XtremeDSP kit This code simply brings in the data from each ADC and registers it It then simply uses some of the bits from them to drive the LEDs on the kit hardware Remember that the LEDs are active low i e a low will turn them on Copyright 2003 Revisions Date Version Author Description 2003 11 11 1 0 derekstark Created library IEEE use IEEE STD_LOGIC_ 1164 use IEEE STD_LOGIC_ARITH all use IEEE STD_LOGIC_UNSIGNED all entity simple_adc_hookup is parel level entity this example is fed down from A reset input fom mb the Clock FPGA to the User FPGA The standard clock bitfile In st logic uid configuration done signal clk 2v80 bit is used that takes the 105MHz module lt A ss std_logic crystal clock source and sends it to the A
128. al Layout on page 17 Details of configuring through the JTAG chain is provided in FPGA Configuration using General JTAG Chain on page 126 Further details on using the headers with specific software such as Chipscope EDK and Impact are also provided later in the User Guide www nallatech com NT107 0272 Issue March 9 2005 A NALLATECH XtremeDSP Development Kit IV User Guide The High Perform ance FPGA Solutions Company 12 3 1 General Header The General JTAG header Figure 57 on page 93 connects to the chain that runs through the standard JTAG pins on the User FPGA devices in the Kit It also connects to some of the PROMs and CPLDs that are used It is a standard 0 1 pitch header which supports flying lead connections for amongst others the Xilinx Parallel Ill or Parallel IV pods The header pinouts are shown in Table 39 on page 93 123456789 Figure 57 General JTAG Connector 14 Description 3 3V 3 3 Volts Supply 2 GND Signal Ground 3 N C Not connected do not use 4 TCK ALT JTAG TCK Signal 5 N C Not connected do not use 6 TDO ALT JTAG TDO Signal 7 TDI ALT JTAG TDI Signal 8 TRST ALT JTAG TRST Signal 9 TMS ALT JTAG TMS Signal Table 39 General JTAG Header 14 Pinouts 12 3 2 Parallel IV JTAG Header This is a JTAG header that connects to the chain running through the standard JTAG pins on the User FPGA devices in the Kit and also some of t
129. als to connect to the two independent ZBT banks OPB GPIO peripheral OPB UartLite UART peripheral for STDIO DCM block for handling the system clock Two DCM blocks for handling the clock to the ZBT banks The intention of this design example is to show how certain aspects of the Kit can be used in the EDK tool rather than providing insight into using EDK The EDK tools are supplied with an extensive documentation set to explain the flow tools and components used The main EDK Platform Studio project is provided in the example folder and is called system xmp Open this file to show the main project which is displayed in Figure 105 on page 183 x n Console Log PM SPEC Xilinx path component is C EDK Project pened Ready NT107 0272 Issue March 9 2005 amp amp xx Ps Xilinx Platform Studio D wip BenADDA_IV_Tests Examples edk_example system xmp system pbd Edit Project Tools Options Add Window Help ike 505 w lu TER x system Optons Components S56 s n ime Categories All Components gt Bus Infrastructure moo CPUs Z 1 Peripherals 4 Components chipscope_icon chipscope_ila chipscope_opb_iba chipscope_plb_iba chipscope_vio v Heel medda e
130. ample VERVIEW ji uy an HH 200 Simulating the FIR Cosimulation Example esent 200 Cosim lation aaa 202 Chipscope Use in System Generator ees 208 Example odio ibd pu ME 208 Chipscop amp Pro DyVerview i gone a DICH MUN e 208 Chipscape in System Generator a 209 Real time debug EE 215 Importing Data Into MATLAB Workspace From 220 Part Firmware i 221 Changing the 223 223 The Firmware Utilities 223 Performing a Firmware 224 Converting from 5VIO PCI and USB firmware to 5VIO and 3 3VIO PCI firmware 224 Converting from PCI Firmware only to 5VIO PCI and USB firmware 225 Part XII Reference Information 227 Pinout Information u LLULLA li i aaa 229 Local Bus Pinouts Interface Communications 229 Adjacent Out Bus Interface Communications 230 Adjacent Header 8 ioa near t ia its i ananas n reati Oei 231 PLINKS 0 PLINK Header J10 232 PLINKS 7 Nallatech RS232 Connections in Part 2
131. ance FPGA Solutions Company the DIME CloseCard DIME HANDLE CardHandle function Additionally the handle returned from DIME LocateCard should also be closed This can be achieved using the DIME CloseLocate LOCATE HANDLE LocateHandle function Please consult the FUSE C C API Developers Guide on the FUSE CD for further details on all the available DIME software functions 16 2 2 Access through JTAG Headers When using JTAG headers it is important to understand the operation of power supplies for the DIME II module used in the Kit When the hardware is initially powered on the power supplies PSU A to PSU D are disabled This allows the DIME II hardware to check the power supply levels requested by the module to see if they can be supplied by the motherboard prior to switching the power supplies on The easiest way to enable the power supplies to the module is to open the card within FUSE This can be in the FUSE Probe Tool one of the FUSE APIs or DIMEscript The power supplies will remain on after the card is closed down in FUSE If you are using a JTAG header then these module power supplies need to be enabled in order to access all the devices in the JTAG chain Without this the JTAG chain will not be complete and you will receive errors 16 3 FPGA Configuration using the FUSE Probe Tool The FUSE Probe Tool is an easy to use software interface which allows users to access a subset of the functionality provided by FUSE Full inst
132. anism to communicate over this bus using the appropriate protocol can be implemented directly by the user in their design A block diagram for the implementation of this core is shown in Figure 65 on page 114 User FPGA Interface Comms Bus Figure 65 Implementation with Own Communications Mechanism www nallatech com NT107 0272 Issue March 9 2005 The High Performance FPGA Solutions XtremeDSP Development Kit IV User Guide 15 33 Communications Bus Protocol Data is transferred between the User FPGA and the Interface FPGA with the use of 5 control signals Three of these signals are driven by the PCI or USB interface These are AS DSL EMPTY and BUSY ASIDSI EMPTY BUSY RENI WENI ADIO RDI WR This is an address strobe data strobe signal When this is HIGH the data being transferred to the User FPGA is an address and when this signal is LOW the data being transferred to the User FPGA is data from to the last address given Generally addresses are only sent from the PCI FPGA to the User FPGA This signal is always in sync with the data passed through the internal FIFOs of the PCI FPGA The internal FIFO can have a mixture of actual data and addresses and this AS DS line will automatically indicate the true type of data This signal indicates that there is data waiting to be written from the PCI or USB FPGA interface to the User FPGA This signal will go HIGH when there is no more d
133. ant if you wish to use one of the DIME Clocks i e CLKA CLKB CLKC that can be set higher than 105 MHz Please refer to Clocks on page 63 for details on how the Clock FPGA can be used 4 2 3 Analog Performance The ADC channels the BenADDA DIME II module can typically resolve between 11 and 12 bits using the on board 105 2 oscillator The ENOB Effective Number of Bits characteristics were obtained using signals at I dBFS An improvement on these figures would be expected if the input signal levels were reduced slightly The SNR Signal to Noise Ratio of the AD6645 is at best 74 5dB suggesting that the maximum number of bits attainable is 12 1 Please note that the measured ENOB in the BIST Built in Self Test will be slightly reduced due to slight loss interference pickup as a result of the BNC jack to jack adaptors 22 www nallatech com NT107 0272 Issue March 9 2005 A NALLATECH XtremeDSP Development Kit IV User Guide The High Performance FPGA Solutions Company The ENOB characteristics worsen slightly when using an external clock The ADC channels can resolve between and 12 5 bits The frequency responses of both ADC channels display a 3dB point of 58MHz Each channel features a 3rd order passive low pass filter which with a theoretical cut off frequency of 58MHz would expect to suppress signals at 350MHz by 60dB The actual attenuation at this frequency is 59dB The pass band ripple measures 0 15dB whilst the c
134. ardware and can speed up simulation dramatically 22 3 Installing the System Generator Plug In for the Kit The XtremeDSP Development Kit IV CD contains an install file to provide support for the Kit within the Xilinx System Generator Environment v To install the plug in run the following command from the Matlab command window l First change to the directory on the CD that contains the install program by typing cd D System_Generator_Plugin where D is the drive letter of the CDROM drive 2 Then run the actual installer program by typing xlInstalllP v2Pro v4 Board Support Package zip Once the installer completes the following message appears in the Matlab command window System Generator v6 3 XtremeDSP V2Pro and V4 Development Kit files installed successfully It is recommended that MATLAB is restarted after running this installation program 22 4 Using the HDL Netlist Flow QAM Example 22 4 Example Overview This example shows a QAM example that is worked through the HDL Netlist Compilation flow The output of System Generator is taken through ISE to produce a bitfile that can then be programmed onto the hardware Tool Requirements ISE 6 3i and System Generator 6 3 The example will also require the use of an oscilloscope with a minimum of 2 channels ISE 6 3i must be used in conjunction with System Generator 6 3 Earlier versions of ISE will not function with System Generator 6 3 22 4 2 Simulating the QAM E
135. ata to be written to the User FPGA This signal indicates that the PCI or USB FPGA interface can receive data from the User FPGA When this signal goes HIGH no more data should be written to the Interface FPGA The User FPGA drives the two remaining control signals These are RDL WR and RENL WENL This signal is a read write enable signal When this signal is LOW if the R W signal is HIGH data is on the bus ready to be written to the PCI FPGA If the signal is LOW and R W is LOW then data will be driven onto the data bus from the PCI FPGA on the next clock edge When this signal is HIGH there should be no data on the bus This is the data bus that is used to transfer data between the PCI FPGA and the User FPGA lt is a 32 bit bidirectional bus that can be driven by both the PCI FPGA and the User FPGA The general functionality is similar to that of FIFOs The EMPTY and BUSY signals act similarly to EMPTY and FIFO FULL signals The WR and WENI signals combine to give the RENI and WENI signals of a FIFO This signal determines the direction of the data transferred between the Interface FPGA and the User FPGA If this signal is LOW data is being read from the Interface FPGA and so the Interface FPGA drives the data bus If the signal is HIGH data is being written to the Interface FPGA and so the User FPGA drives the data bus The clock used for the Interface FPGA to User FPGA communications is always DSPCLK Readi
136. atech com NT107 0272 Issue March 9 2005 Technical Support For technical support issues please contact Xilinx see below for contact details Contacting Xilinx XILINX WWW Go to http support xilinx com Emaail support xilinx com Contacting Nallatech NALLATECH WWW 4 The High Performance FPGA Solutions Company www nallatech com Product Registration Nallatech XtremeDSP Development Kit IV support lounge The XtremeDSP Development is provided with an initial 90 day access to the support lounge upon registration This lounge provides access to Nallatech software updates and relevant application notes as they become available Continued access beyond the 90 days to this lounge is available on establishment of a maintenance agreement with Nallatech The support lounge is available on the internet at www nallatech com solutions products kits In the actions section of this web page you will see an option to register your product Registration requires the serial number of the XtremeDSP Development Kit IV The serial number is located on the bottom of the small blue board case NT107 0272 Issue March 9 2005 www nallatech com iii www nallatech com NT107 0272 Issue March 9 2005 Contents About this User Guide xii Part EIntFOOUEt Or toot aerea XtremeDSP Development Kit
137. be clocked on the same clock edge as the data in the DACs and ADCs There are total of three feedback pins from the Clock FPGA to the User FPGA These feedback signals ensure that the clock to the DACs or ADCs and the feedback pins have coincident clock edges with minimum skew The feedback signals from the Clock FPGA to the User FPGA are matched in physical length with the clock signals sent to the DACs and ADCs This design ensures minimum skew between the data clocked through the ADCs DACs and the data clocked in the User FPGA Table 28 on page 69 outlines the set up between the Clock FPGA and User FPGA for these feedback signals There are only three clock feedback pins due to clock pin resource constraints www nallatech com NT107 0272 Issue March 9 2005 NALLATECH XtremeDSP Development Kit IV User Guide The High Performance FPGA Solutions Comp Clock Signal Signal Name Clock FPGA Pin XC2V80 User FPGA Pin Description 4CS144 XC4VSX35 10FF668 Clock Feedback CLKI_FB J2 4 Clock Feedback 2 CLK3_FB H4 BI5 Clock Feedback 3 CLK2 FB HI2 15 Table 28 Feedback Clock Pinouts 10 2 5 ADC and DAC Clocks The Clock FPGA is used to directly clock each ADC and DAC device independently The ADCs and DACs are clocked differentially from the Clock FPGA and can be clocked at various speeds The speed at which the ADCs and DACs are clocked depends how the clocks are used which in turn depends upon the
138. ble This is the recommended header if the Xilinx JTAG Cosimulation option in the Xilinx System Generator tool is chosen to be used with a Parallel IV ribbon cable When the board is used inside the blue board case the cable is brought out through the small gap marked in the side of the case This case should be opened the cable fitted and then the case closed again To fit the cable remove the four screws round the sides of the case and remove the lid Then plug one end of the cable into the keyed header and bring the cable out to the small opening in the base of the case as shown in Figure 127 on page 204 Figure 127 Routing the Parallel IV Cable Out from Header Then fit the lid back onto the case refitting the screws if necessary and ensure that the ribbon cable is not caught between the top and bottom of the blue case Finally connect the Parallel IV pod to the exposed end of the ribbon 204 www nallatech com NT107 0272 Issue March 9 2005 NALLATECH XtremeDSP Development Kit IV User Guide cable as shown in Figure 128 on page 205 Both the connector on the cable and the socket on the pod are keyed for ease of use Figure 128 Re fitting the Case Lid first Connecting the Parallel IV Pod second Setting up for PCI Cosimulation Flow Using the cosimulation flow via the PCI interface assumes that you have the board properly installed into an available PCI slot Please follow the instruc
139. ble signals are generated Some of these control signals require to be registered to allow for safe usage Decoding of the address and control signals is now required in order to create read and write control signals for the individual registers in the design When the registers are selected for readback to the host their values are put onto the bi direcitonal databus to the interface core Infer the actual two registers www nallatech com NALLATECH NT107 0272 Issue March 9 2005 formance FP NT107 0272 Issue March 9 2005 A NALLATECH GA Solutions Company XtremeDSP Development Kit IV User Guide map part of each of the two registers to the output LEDs for visual feedback LEDS 3 downto 0 lt REGI 3 downto 0 LEDS 7 downto 4 REG2 3 downto 0 Create a dummy signal to stop the tool optimising out the rest of the registers REGI and REG2 that are not used as outputs process RST CLKBi begin if RST I then DUMMYSIGNAL 0 elsif REGI X 00000000 and REG2 X 00000000 then DUMMYSIGNAL lt 1 end if end process Simply tie the interupt line low in this example as it is not used INT lt 0 end host interface arch Map part of the two registers to the LEDs on the hardware Note that 8 LEDs appear to be specified but in the actual implementation only 4 are wired to physical LEDs The dummy signal is used here to stop the synthesis
140. ce FPGA Solutions Comp any 92 12 3 JTAG Chain Access The JTAG chain is used for test and configuration purposes All DIME II modules such as the BenADDA DIME II module used in the Kit have a JTAG based Plug and Play PnP facility to enable auto detection of the modules present in a system Each DIME II module has a unique ID number The BenADDA ID is listed in Table 38 on page 92 ID Number Hex Description 32988033 User FPGA 4 5 35 10 668 Clock FPGA 2 80 4 5144 Table 38 BenADDA Assigned Code Listing The physical order of the devices in the JTAG chain illustrated in Figure 56 on page 92 is l User FPGA 2 Clock FPGA To establish the module order in the JTAG chain FUSE is deployed The software initially scans the chain to identify and index the devices on the BenADDA DIME II module The device nearest the output of the module is identified as device O on that module For each device upstream on the JTAG chain the index is incremented Figure 56 on page 92 shows the device numbers that are assigned for the BenADDA DIME II module used in the Kit CLK FPGA XC2V80 4CS144 JTAG DEVICE 0 USER XC4VSX35 10FF668 TDI gt JTAG DEVICE Figure 56 JTAG Device Indexing There are a number of headers on the board that allow access to the JTAG chain The location of each of these headers is shown in Front View of Board Physic
141. complement ADCs to offset binary DACs 17 32 Source The source files are provided on the XtremeDSP Development Kit IV CD in the folder ROM DriveExamplesladc to dac hookup source or is installed to the location where you installed the Kit CD 17 33 Implementation Apart from the source files a Xilinx ISE project has been included on the XtremeDSP Development Kit IV CD at the location CD ROM to dac to dac hookup or is installed to the location where you installed the Kit CD This project has been created in Xilinx ISE 6 3i A UCF is also provided in the source folder that includes all pin LOC and timing constraints 17 3 4 Running the Example Please note that although this example can be run it is primarily intended as a simple introduction to creating an ADC to DAC link The primary purpose is to highlight the differences in data format between the ADCs and DACs and how to convert between them The bitfiles for the example have already been generated v To run the ADC to DAC example use the following procedures Start the FUSE Probe Tool and assign the following bitfiles Osc_clk_ 2v80 bit to the Clock FPGA Adc_to dac_hookup bit to the main User FPGA 2 Finally toggle the resets by doing the following Check FPGA Reset to enable the reset to the main User FPGA Check System Reset to enable the reset common to both FPGAs Click the but
142. configured benone Sys Clock Set to 50 00 Wirtex 1V 4V3X35 the Wallatech BenADDA IV Virtex4Ymx3s FF668 on the benone card has bern configured Figure 100 Log Configuration Result 174 www nallatech com NT107 0272 Issue March 9 2005 NALLATECH The High Performance FPGA Solutions Compan y XtremeDSP Development Kit IV User Guide Finally go back to the Resets tab and do the following Uncheck FPGA Reset Uncheck System Reset Click the Interface Reset button Check the FPGA Reset again Check the System Reset again Uncheck the System Reset again Uncheck the FPGA Reset again Chipscope Pro Analyzer The design is now ready to be examined in the Chipscope Pro Analyser tool This can be opened from the Windows Start menu SY x ChipScope Pro Figure 101 Initial Chipscope Pro Analyzer Start up screen NT107 0272 Issue March 9 2005 www nallatech com I75 Chipscope ILA Support NALLATECH 5 The High Performance FPGA Solutions C Once the analyzer has started it must now establish a connection through the JTAG cable Go to the menu and select Cable gt Xilinx Parallel Cable The tool scans the JTAG chain and provides a list of devices detected ChipScope Pro Analyzer JTAG Chain Device Order XC9500XL 149608093 Device IR Length Device IDCODE USERCODE 1 1 18 00 105025093 2 MyDevice2 xC18V00
143. ct the Parallel IV pod to the exposed end of the ribbon cable as shown in Figure 59 on page 94 Both the connector on the cable and the socket on the pod are keyed for ease of use Figure 59 Re fitting the case lid first Connecting the Parallel IV pod second www nallatech com NT107 0272 Issue March 9 2005 NALLATECH XtremeDSP Development Kit IV User Guide The High Performance FPGA Solutions Company 12 3 3 Configuration Status Monitoring The BenADDA DIME II module has a mechanism for detecting the configuration status of the module This signal is designed for larger systems where there are multiple modules present There is the provision of a signal called CONFIG DONE which is related to the configuration of the on board FPGA The DIME II standard allows a design to be implemented based on the status of the entire system The CONFIG signal provides built in control that can be used by the system designer This feature allows a designer to synchronize all aspects of the configuration startup of complete system 3 3V je MMUN22ILTI C CONFIG DONE CLKFPGAA DIME II CONNECTOR to DIME II Motherboard PC40 FPGA DONE YI Main User FPGA MMUN22ILTI CONFIG DONE_USERFPGA ACI Figure 60 CONFIG DONE Circuit Figure 60 on page 95 shows the set up of the CONFIG_DONE signal the BenADDA DIME II module The FPGA_DONE signal to the
144. d move the slider Figure 124 on page 202 to change the noise level Then view the changes on the scope Slider Gain Help Close Figure 124 Slider Gain Control 22 5 3 Cosimulation Flow After simulating the model within Simulink the next step is to make use of the cosimulation flow If the Kit is used with the USB connection and the external power supply use the JTAG cosimulation flow with a Parallel IV JTAG download cable If the Kit is plugged into a PCI slot then the cosimulation can be carried out through the PCI interface itself Setting up for JTAG Cosimulation Flow If the Kit is used via the standalone non PCl then the cosimulation flow can be carried out using a Parallel IV download cable Connect the Parallel Cable to the available JTAG headers on the Kit If using the Parallel IV pod with the ribbon cable a keyed socket J24 is available on the board If using a flying lead connection a 0 1 pitch General JTAG header 14 is provided To enable the power supplies to the User FPGA 4 5 35 10 668 without opening the card via USB ensure J17 has its jumper fitted This enables the power supplies shortly after power is applied to the board by the external power unit www nallatech com NT107 0272 Issue March 9 2005 XtremeDSP Development Kit IV User Guide General JTAG PCI Connection Parallel IV JTAG header Standalone Power Connector USB Connection Figure 125
145. d process Figure 17 Registering of the ADC Inputs The full version of this code snippet can be found in the XtremeDSP Development Kit IV CD at the following location CD ROM Drive Examples simple_adc_hookup The main use of the ADCI_OVR and ADC2_OVR signals is to detect if the input is out of range This can be used as a valid signal to part of your design use of this signal depends upon your application The ADCI_DRY and ADC2_DRY signals indicate when there is valid data on the databuses from the ADCs This is only of use when the ADC is in a different clock domain from the input registers that are capturing the databus values The DRY signals can be used to indicate when it is valid to capture data from the ADC data outputs 4 3 1 Timing Constraints It is necessary to account for the setup and hold times required for the ADC devices These timings are given in full in the Analog Devices AD6645 Datasheet on the XtremeDSP Development Kit IV CD at the location ROM Drive Documentation Datasheets The timing requirements depend on your design although you should account for a Ins delay for traversing the PCB in your calculations For example in the simple_adc_hookup example shown in Figure 17 on page 28 the following timing constraint on the data signals is used NET adcl_d lt gt OFFSET 5 ns BEFORE clkl_fb This is a suggested constraint and the actual constraint depends on the design 4 4 So
146. d when using an op amp configuration at the output of the AD9772A The full scale current output IOUTFS from the AD9772A DAC is 20mA When this output current is driven through the two 500 resistors a voltage of 2Vpp appears at the MAX4144 input Since the op amp has a fixed gain of 2 the MAX4144 output is 4Vpp The 500 DAC channel output impedance combined with the assumed 500 impedance of the connecting system at the output MCX connector ensures that the signal magnitude at the MCX connector is 2Vpp Final Output to user via MCX connector MAX4144 Figure 23 AD9772A Single Ended DC coupled Output The op amp used in the design is an instrumentation amplifier with an inverting X2 gain from MAXIM Therefore the output configuration will drive an output voltage of into 500 load Please note that the output from the DAC itself is inverted due to the use of an inverting op amp NT107 0272 Issue March 9 2005 www nallatech com 35 NALLATECH The High Performance FPGA Solutions Company Differential Outputs using Termination Resistors Nallatech Custom Build is also possible to drive differential outputs using a pair of termination resistors However this 15 a specific build option from Nallatech and is not provided with the standard Kit It is included here for completeness Differential Output to MCX connector Figure 24 AD9772 Differential Directly Coupled Option When te
147. ddress Signals for ZBT Bank A Signal Name User FPGA XC4VSX35 Signal Name User FPGA XC4VSX35 IOFF668 PIN No IOFF668 PIN No ZBTA_A lt 0 gt ZBTA A II ZBTA lt gt Y3 ZBTA lt 12 gt ACA ZBTA A 2 ADI3 ZBTA A 13 AB3 ZBTA A 3 Y2 ZBTA lt 14 gt AC3 ZBTA lt 4 gt ZBTA_A lt 15 gt ADI ZBTA_A lt 5 gt 7 _ lt 16 gt ZBTA_A lt 6 gt ZBTA_A lt 17 gt ZBTA_A lt 7 gt 12 ZBTA_A lt 18 gt ACI2 ZBTA_A lt 8 gt AB4 ZBTA lt 19 gt AB2 ZBTA A 9 AF4 ZBTA lt 10 gt AD3 Table 13 ZBT Address Signals Pinouts Bank A NT107 0272 Issue March 9 2005 www nallatech com 43 ZBT SRAM Memory NALLATECH ZBT Data Signals for ZBT Bank A Signal Name User FPGA XC4VSX35 10FF668 PIN No ZBT_D lt 0 gt AC7 ZBT_D lt gt AC6 ZBT_D lt 2 gt Y5 ZBT_D lt 3 gt AE4 ZBT_D lt 4 gt AB7 ZBT_D lt 5 gt AB6 ZBT_D lt 6 gt AF6 ZBT_D lt 7 gt AD4 ZBT_D lt 8 gt 10 ZBT_D lt 9 gt Y9 ZBT 0 lt 10 gt AE9 ZBT lt gt AC8 ZBT D I2 ZBT_D lt 13 gt AC9 ZBT_D lt 14 gt AA8 ZBT_D lt 15 gt Y7 ZBT_D lt 16 gt AB9 ZBT_D lt 17 gt Y8 ZBT_D lt 18 gt AF8 ZBT_D lt 19 gt AA7 ZBT_D lt 20 gt YIO ZBT_D lt 21 gt AA9 ZBT_D lt 22 gt AF9 ZBT_D lt 23 gt AD8 ZBT_D lt 24 gt Y6 ZBT_D lt 25 gt AE6 ZBT_D lt 26 gt AB5 ZBT_D lt 27 gt AD5 ZBT_D lt 28 gt AF7 ZB
148. de directory within FUSE DIME HANDLE hCardl HANDLE hLocate DWORD LEDs Locate the Cards on the PCI interface hLocate DIME_LocateCard d1PCI mbtALL NULL dldrDEFAULT d1DEFAULT Open the first card found in the locate hCardl DIME OpenCard hLocate 1 dccOPEN DEFAULT Change the LEDs LEDSs DIME ReadLEDs hCard1 DIME WriteLEDs 1 LEDs 1 Close the card down DIME CloseCard hCard1 Finally close the locate down DIME CloseLocate hLocate Figure 32 FUSE API Commands for PCI LEDs The FUSE API Developers Guide included on the FUSE CD provides further details on both these functions 58 www nallatech com NT107 0272 Issue March 9 2005 NALLATECH XtremeDSP Development Kit IV User Guide The High Performance FPGA Solutions Company Section 9 Resets In this section i Introduction to the Reset Structure in the Kit Hardware Aspects Firmware Aspects Software Aspects 9 1 Introduction There are reset signals provided from the interface FPGA XC2S200 to the user programmable FPGAs XC4VSX35 10 668 and XC2V80 4CS144 in the XtremeDSP Development Kit IV This section details the structure of these resets and how they can be used in your designs 9 2 Hardware 9 2 1 Reset Structure The configuration of the resets on the Kit is shown in Figure 33 on page 59
149. design partitioning inter FPGA communications and building a host interface NT107 0272 Issue March 9 2005 www nallatech com 109 NALLATECH erformance FPGA Solutions C 110 www nallatech com NT107 0272 Issue March 9 2005 NALLATECH XtremeDSP Development Kit IV User Guide Section 15 Building a Host Interface In this section Creating a Hardware Software interface for Designs on the Kit Aspects of Hardware Firmware and Software Design 15 1 Introduction The Kit often requires an interface to be built between a design running in the FPGA and the PC host This section provides details on how such an interface can be created provides an introduction to a core called the Interface FPGA to User FPGA that aids in building the link between the hardware and software 15 2 Hardware 15 2 1 Design Partitioning The Kit allows the user to partition the functionality of their application between software and hardware easily and effectively The design partitioning of the Kit is shown in Figure 63 on page 111 B PCI USB Interface in Nallatech Low Level i BenONE FPGA n DIME II Module rivers PCI BUS i e BenADDA External Sources Software running on host PC Figure 63 Design Partitioning The green blocks do not require any further design from a user perspective The interface is pre configured with either PCI or USB and the external sources are assu
150. ditional Components 1 5 Regulators Clock XC2V80 4CS144 0 5 Regulators ZBT Components 0 7 Linear Regulators FPGA Sidebank 0 8A Linear Regulators Digital 0 25 Linear Regulators Main User Core 1 25A SA I 2V converted from via 96 efficiency DC to DC converter PPS see 5V to 2 later in this section TOTAL 5A 5V abs limit of external supply Table 40 Power Budget with External Power Supply NT107 0272 Issue March 9 2005 www nallatech com 97 Power Specifications NALLATECH The High Performance FPGA Solutions Comp any 98 13 1 2 PCI Power Specification The Kit hardware can be used in a PCI slot which means the external power supply is not used to power the board Therefore the power specification is determined by regulators on the Kit hardware and also by the PCI specification If you are using a high power design you should where possible make use of a PCI slot due to the additional power capabilities The recommended specification in Table 41 on page 98 is made for a Kit connected to a PCI slot Power Rail Volts Current Rating Amps Description 1 2 5 Virtex 4 Main Core and Clock Core 3 3 1 2 Virtex 4 FPGA I O 3 3 1 2 Virtex 4 FPGA I O and ZBT devices 3 3 1 2 Spartan Il FPGA I O 2 5 1 2 Spartan ll FPGA Core Table 41 On board Power Supplies The recommended power max for the K
151. down to the main User FPGA as well as to the ADCs and DACs Figure 45 on page 73 shows a suggested design Internal clock distribution i e BUFG and OBUFs and Clock FPGA Virtex ll E OSC_CLK j M6 XC2V80 OP N35 2915 N35 1 N35 3915 N35 84 SIV ld AFII ABIO ZBTA CLK This net is the same physical length as the ZBT CLK signal to the ZBT AFI2 acio ZBTA CLK FB OUT Memory This Main FPGA Virtex 4 jsp AGE de XC4VSX35 ZBTB_CLK AEI4 2878 FB OUT ZBTB FB IN Figure 45 Using the Crystal or MCX Input to Clock the ADCs DACs An example of this clock circuit is provided on the XtremeDSP Development Kit IV CD at the following location ROM Drive Examples Clock_Designs There is VHDL source for an example showing the 105MHz crystal oscillator input osc_clock vhd and an example of using the external MCX clock input ext_clock vhd Each of these VHDL files has an associated the same folder NT107 0272 Issue March 9 2005 www nallatech com 73 Using DIME Clocks If you wish to make use of the DIME clocks to drive the ADC and DAC components this must be driven up to the Clock FPGA from the User FPGA as shown in Figure 46 on page 74 Clock FPGA Virtex II OSC XC2V80 CLK_OP_AMP B5 CLK OP A
152. e DCMs themselves add output jitter dependent upon the input jitter and the period jitter of the DCM itself 74 www nallatech com NT107 0272 Issue March 9 2005 NALLATECH XtremeDSP Development Kit IV User Guide The High Performance FPGA Solutions Company The DCMs add a small additional amount of jitter to the output clock a factor to consider when you are clocking ADCs this leads to aperture uncertainty which can reduce the accuracy of the ADC conversion Therefore dedicated crystal is provided on the module with the additional option of fitting dedicated crystal on the motherboard This allows for highly accurate and low jitter clock sources The programmable clock sources on the board that drive the DIME clock nets such as CLKA are generated by Epson MG 7010SA PLL oscillators A full datasheet is provided for these oscillators on the XtremeDSP Development Kit IV CD at the following location ROM Drive Documentation DatasheetsV The jitter for these clocks is 14ps rms The datasheet Pletronics Crystal pdf for the module crystal oscillator is also included in same folder The jitter for this crystal is specified at Ips rms 10 4 Software 10 4 1 Setting the Clocks in FUSE The FUSE Probe Tool can be used to set the programmable oscillators via the oscillator frequencies tab highlighted in red in Figure 47 on page 76 Simply type the desired frequency in kHz in the box for the specific clock and hit Enter to
153. e maximum alert should be set to in degrees Celsius Table 33 DIME_CardResetControl ResetNum Argument Options 86 www nallatech com NT107 0272 Issue March 9 2005 NALLATECH XtremeDSP Development Kit IV User Guide The High Performance FPGA Solutions Company ResetNum Description dinfTEMPALERTMIN This command mode is used to set the minimum temperature level for the temperature alert signal Once set if the FPGA die temperature falls below this the temperature alert signal is triggered Note that the power on default setting for this temperature is 0 degrees Celsius Value should be the integer value that the minimum alert should be set to in degrees Celsius dinfTEMPALERTCLEAR This clears the temperature alert signal if set Note that if either the maximum or minimum temperature limits are still exceeded then the alert signal will immediately be set Value should to set to 0 Table 33 DIME_CardResetControl ResetNum Argument Options Value This argument is command mode specific CmdMode Description drDISABLE This de asserts the reset line for the selected reset drENABLE This asserts the reset line for the selected reset drTOGGLE This toggles the reset line for the selected reset Table 34 DIME_CardResetControl CmdMode Argument Options The value argument is not used in this function and is only included for consistency Return Returns on error Description This function is u
154. e of the design process some settings are mandatory and need to be specified for the design to configure and run on Nallatech hardware This section details these settings Necessary Settings l Enable Readback and Reconfiguration 2 Select the JTAG Startup Clock selected configuration clock These settings are easily accessed and set in the Xilinx ISE Foundation tools The following screen captures are taken from the ISE 6 3i release NT107 0272 Issue March 9 2005 www nallatech com 149 Common ISE Settings A 150 NALLATECH The High Performance FPGA Solution If you right click on the process for Generate Programming File go to properties on the pop up menu and then select the tab for Startup Options You will see the options shown in Figure 75 on page 150 Process Properties General Options Configuration options Startup options Readback options Encryption options Property Hame Value FPGA Start Up Clock Enable Internal Done Pipe Done Output Events Default 4 Enable Outputs Output Events Default 5 Release Enable Output Events Default 6 Release DLL Output Events Default NoWait Match Cycle Default Drive Done Pin High Cancel Default Help Figure 75 Startup Options Simply click the pull down menu for the FPGA Startup Clock and select JTAG Clock Now click the Readback options tab You will see the options shown i
155. ection The internal PLL clock multiplier of the AD9772A is also described to provide you with an insight into the internal operations of the DAC 5 2 1 PLL Clock Multiplier Figure 20 on page 31 illustrates how the BenADDA DIME II module supports PLL enabled or disabled Note that PLL is enabled by default Please contact Nallatech if you wish to disable the PLL function To supply the PLLVDD pin you can populate a jumper to supply the pin with a 3 3v signal or else tie the pin to ground The supply for the PLLVDD pin is shared with the supply of the CLKVDD pin and both the CLK and PLL grounds on the chip share the same separate ground plane When the PLL is disabled and the PLLVDD pin is tied to ground the filter components for the LPF pin internal loop filter for the PLL on the DAC are not populated This leaves the LPF with an open connection VDD AD9772A PLLVDD CLK_GND Figure 20 PLL Jumper Option When the PLL is set to the default value enabled the AD9772A will generate its own 2x clock from the reference clock This allows you to transmit data at the same rate as the reference clock The internal PLL can also generate another phase clock that allows the zero stuffing option to be selected under the same circumstances If the PLL is disabled the input data rate must be half the reference clock frequency This is due to the interpolation filter that adds extra samples every other clock cycle Addi
156. ector is labelled on the lid NT107 0272 Issue March 9 2005 www nallatech com 21 NALLATECH The High Performance FPGA Solutions Comp any Interfacing to MCX connectors via supplied cable The Kit is supplied with five cables that are suitable for connecting between the on board MCX connectors and the user input output BNC connections The cable assembly is shown in Figure 13 on page 22 Heatshrink w Part No 100cm of Internal Identity MCX Straight NT501 1690 RG316 Cable BNC Crimp Crimp Plug Plug Gold Figure 13 Supplied Cable Assembly The MCX connectors are a push fit design therefore the MCX crimp plug on the supplied cable pushes into the MCX connector on the Kit hardware 4 2 2 ADC Clocking Each ADC device is clocked directly by an independent differential LVPECL signal This LVPECL signal is driven from the Virtex ll 2 80 4 5144 FPGA Clock FPGA which is dedicated to managing the various methods for clocking each ADC and DAC device in the Kit The way the ADCs are clocked depends on the bitfile that is assigned to the dedicated Clock FPGA A number of clock sources can be used through the Clock FPGA including On board 105MHz crystal External clock input via the middle MCX connector Clocks from the programmable oscillators available in the Kit Please note that the ADC devices AD6645 can only support a clock input of up to 105 This is import
157. ed Remember to set the input coupling for the channels 500 on the oscilloscope 198 www nallatech com NT107 0272 Issue March 9 2005 NALLATECH XtremeDSP Development Kit IV User Guide The High Performance FPGA Solutions Company tt tt x lt w pP vw kd Wo 1 1 1 x a a 8 28 j 25 6 5 1 0 0 55 V STOPPED Figure 118 Oscilloscope DAC Output from QAM Demo Design XY Display 18 98 Reading Floppy Diek Drive 9 27 24 I a hoa J 4 x 2 2 2 re 8 58 V F 1 s Y 2 ve 8 56 V t B ps 397 sweeps average high sigre pkpk 2 2 915 V 2 080 2 031 8 011 meant 8 5 0 260 4 235 5 79 9 sdew 2 708 94 634 8 773 5 28 3 rms 2 713 44 637 8 774 5 28 2 2 we BAL anpii 1 344 V 8 642 1 920 9 439 5 V M s v M 25 MS s v 1 1 060 55 v 4 5 v STOFPED Figure 119 Oscilloscope DAC Output from QAM Demo Design Dual Display NT107 0272 Issue March 9 2005 www nallatech com 199 System Generator Support NALLATECH High Performance FPGA Solutions Comp any 200 22 5 22 5 1 Using the Cosimulation Flow MAC FIR Example Example Overview This example shows how the cosimulation flow can be used with the Kit The example shows a 32 tap MAC based FIR design The design of coefficients
158. ed to apply data and a clock input There are no set up or control signals Figure on page 20 shows the internal architecture of the ADC JS THI gt gt TH3 THS Timing Digital Error Correction Logic Figure 11 ADC AD6645 Internal Architecture Theory of ADC AD6645 Operation The AD6645 has complementary analog inputs each input is centred at 2 4V and should swing 0 55V around this 2 4V reference This means that the differential analog input signal will be 2 2Vpp as both input signals AIN and AIN are 180 degrees out of phase with each other When data arrives at the AD6645 both analog inputs are buffered prior to the first track and hold THI The analog signals are held in THI while the ENCODE CLK pulse is high and then data is applied to the input of a 5 bit coarse ADC The digital output of ADC I is fed into the 5 bit DACI The output from the DACI is subtracted from the delayed analog signal at the input of TH3 to generate a first residue signal The purpose of TH2 is to provide a pipeline delay to compensate for the digital delay of ADCI This first residue signal is then applied to the second conversion stage Again a similar process is achieved through this stage which finally leads onto obtaining a second residue signal that is applied to a third 6 bit ADC Finally the digital outputs of ADCI ADC2 and ADC3 are added together and corrected in the digital error correction logic to generate the final outpu
159. eete 239 DIME II control and monitoring signals inter FPGA clock infrastructure signals local Nallatech RS232 connections PLink Header 10 User I O ZBT power specifications 97 ADC heatsinks cooling considerations main external connectors additional power connector 20 standalone power 104 external standalone power supply Fixed Power Supply sss GVerVIeW PCI power specification eee 98 power supply 101 DIME II module power supply LEDs motherboard main power LEDs XtremeDSP Development Kit IV User Guide R reading from Interface FPGA to User FPGA 115 reference information 227 related documentation xiv 3 S T firmware overview reset control in FUSE 62 Signal NAMES ERE 60 SEFU CEUFG s iiic ecco ieri ore HE 59 toggle using FUSE probe tool
160. el of integration that allows the user to develop applications for a Nallatech DIME based system straight from the MATLAB environment Each function of the toolbox is a wrapping of the corresponding function from the FUSE C C library where appropriate The software interface is implemented as a set of mex files see FUSE Toolbox for MATLAB Developer s Guide These mex files provide access to the C C FUSE API through calls from the MATLAB environment An evaluation copy of FUSE Toolbox for MATLAB is provided with the Kit 2 6 DIMEscript DIMESscript has been developed by Nallatech as a simple method of accessing motherboards and modules without the need to resort to programming using high level languages like DIMEscript is an interpreted language which means that the language is read in line by line and appropriate actions taken This in turn means that any errors in the script are only found when the relevant line is executed This is in contrast to a compiled language where the required action is checked in advance and made into a more machine friendly form In the case of the compiled language syntax and other features can be fully checked before running the code DIMEscript enables users to open a Nallatech card read data from the card write data to the card access various specific card functions The intention of DIMEscript is to provide a useful scripting language to control DIME based systems without having to
161. em hardware is demonstrably working no support can be given with application level problems WARRANTY The company offers as part of a purchase contract 12 months warranty against parts and defective workmanship of hardware elements of a system The basis of this warranty is that the fault be discussed with the companies technical support staff before any return is made If it is agreed that a return for repair is necessary then the faulty item and any other component of the system as requested by those staff shall be returned carriage paid to the company Insurance terms as discussed in the INSURANCE Section will apply Returned goods will not be accepted by the company unless this has been expressly authorized After warranty repair goods will be returned to the buyer carriage paid by the company using their preferred method Faults incurred by abuse of the product as defined by the company are not covered by the warranty Attempted repair or alteration of the goods as supplied by the company by another party immediately invalidates the warranty offered The said warranty is contingent upon the proper use of the goods by the customer and does not cover any part of the goods which has been modified without Nallatech s prior written consent or which has been subjected to unusual physical or electrical stress or on which the original identification marks have been removed or altered Nor will such warranty apply if repair or parts
162. ems that introduce channel effects and Doppler content into the data source Scopes are provided at impor tant nodes for analysis purposes The operation of receiver is best illustrated with a long simulation duration so that the points in the de rotated constellation have sufficient time to converge 3 Simulate the model by clicking on the Start simulation icon shown right At this point without modifying the model you should be able to see the plots shown in Figure 112 on page 194 NT107 0272 Issue March 9 2005 www nallatech com 193 System Generator Support A NALLATEC 5 The High Performance FPGA Solutions Company TX CONSTELLATION Figure 112 Simulink Simulation Output You will see the filter values settling and the constellation output changing The next step is to create the VHDL for the model and take the output to the Xilinx ISE tools to create a bitstream to program the FPGA 4 Double click on the System Generator block in the model to bring up the parameters to set the compi lation target 194 www nallatech com NT107 0272 Issue March 9 2005 NALLATEC XtremeDSP Development Kit IV User Guide The High Performance FPGA Solutions Company System Generator sysgenqam16 dplr Xilinx System Generator Compilation HOL netist Part G 4 35 101668 Target Directory Jsygendgam15 work Synthesis Tool Hardware Description Language x r
163. ent and CLKBi 1 then RST lt CLKB LOCKED end if end process Figure 44 Using the DCM Locked Signal Figure 44 on page 72 shows a section of code using a generated clock module in VHDL The code is taken from the host interface vhd code in the host interface basic example that is included on the XtremeDSP Development Kit IV CD The example shows the active low reset RSTI being inverted to produce an active high reset required by the DCM The locked signal from this DCM is then registered to produce a synchronous reset for use by the rest of the system Please refer to the relevant section in the Virtex 4 Handbook for detailed information on DCMs and their usage for all types of configuration 72 www nallatech com NT107 0272 Issue March 9 2005 NALLATECH XtremeDSP Development Kit IV User Guide 10 3 2 Clocking the ADCs and DACs There are a number of ways in which the ADCs and DACs can be clocked and a degree of flexibility due to the inter FPGA clocking structure between the main User FPGA 4 5 35 10 668 and the Clock FPGA XC2V80 4CS144 The options are further increased by the clock sources options described in Source Descriptions on page 65 Using the Module 105MHz Crystal or External MXC Clock Both these clocks are directly input to the Clock FPGA They do not directly connect to the main User FPGA therefore a design is required in the Clock FPGA to send the clock input
164. er LEDs will change from green to red 246 www nallatech com NT107 0272 Issue March 9 2005 NALLATECH XtremeDSP Development Kit IV User Guide The High Performance FPGA Solutions Company I Have Problems Opening Multiple Cards over USB i e a StrathNUEY and a BenONE XtremeDSP Kit How do Resolve This There is a known issue when opening a StrathNUEY and then trying to open a BenONE XtremeDSP Kit card There is a current work around if you open the cards by type there doesn t seem to be a problem i e Select Open Card specify USB and for card type select BenONE then Select Open Card specify USB and for card type select StrathNUEY This currently gets round the problem Does the FUSE API Support Borland C Yes the FUSE API supports Borland C Libraries are provided in both COFF and OMF formats to allow for compatibility The OMF format is required by Borland The libraries can be found in the following locations l In the include folder in the location on the host machine where FUSE was installed commonly gram Files FUSE include OR 2 The FUSE CD in lt CDROM gt Software Include Where Can find the FUSE API Header and Library Files The files are available in the following locations l In the include folder in the location on the host machine where FUSE was installed commonly C Pro gram Files FUSE include OR 2 The FUSE CD lt CDROM gt Software Include How many Pr
165. eral JTAG pin header on the motherboard via a JTAG programmer such as the Xilinx Parallel Ill programmer Therefore this is where to connect the IV cables in order to use products such as Chipscope ILA The General JTAG chain has built in switches which only switch DIME II module site into the chain if a module is populated Therefore if a module is not populated in a slot the chain skips that slot Please note that specific information about builds for different front end configurations is for reference only Attempted repair or alteration of the goods as supplied by Nallatech immediately invalidates the www nallatech com NT107 0272 Issue March 9 2005 NALLATECH XtremeDSP Development Kit IV User Guide warranty Nallatech will not provide support upon alteration and cannot guarantee performance characteristics subsequently obtained If you are using a JTAG header then these module power supplies need to be enabled in order to access all the devices in the JTAG chain Without this the JTAG chain will not be complete and you will receive errors See Enabling Power Supplies at Power On using External Power Supply and JTAG connectors on page 105 for information on enabling module power supplies at power on The General JTAG chain configuration is shown in Figure 74 on page 127 along with the header to access the chain The header pinout is detailed in Table 50 on page 127 Interface FPGA Drives JTAG
166. erformance FPGA Solutions Company Part XTI Reference Information This part of the User Guide provides reference information on the XtremeDSP Development Kit IV and includes pinout information NT107 0272 Issue March 9 2005 www nallatech com 227 NALLATECH erformance FPGA Solutions C 228 www nallatech com NT107 0272 Issue March 9 2005 The High Perform ance FPGA Solutions Comp any NALLATECH XtremeDSP Development Kit IV User Guide Section 24 Pinout Information In this section Local Bus Pinouts Interface Communications Adjacent Out Bus Interface Communications Adjacent Header PLinks 0 PLink Header J10 PLinks 7 Nallatech RS232 Connections DIME II Control and Monitoring Signals ZBT SRAM Inter FPGA Clock Infrastructure Signals DAC Signal Pinouts ADC Signal Pinouts User Header 24 1 Local Bus Pinouts Interface Communications Signal Name DIME II Connector PIN User FPGA XC4VSX35 10FF668 PIN No LBUS lt 0 gt PBI U23 LBUS I PB2 V23 LBUS lt 2 gt PB3 V26 LBUS lt 3 gt PB4 25 LBUS lt 4 gt 6 020 LBUS lt 5 gt PB7 021 LBUS lt 6 gt PB8 U22 LBUS lt 7 gt PB9 U24 LBUS lt 8 gt PBIO U25 LBUS lt 9 gt PBI U26 Table 53 Local Bus Pinouts XC4VSX35 10FF668 NT107 0272 Issue March 9 2005 www nallatech com 229 Pinout Information NALLATECH
167. ernal power supply To enable this feature fit a jumper default on J17 This is useful when working with tools such as System Generator or Impact and you do not wish to open the card via USB to enable the power supplies to complete the JTAG chain NT107 0272 Issue March 9 2005 www nallatech com 105 Power Specifications Y FPGA Solutions Company 106 www nallatech com NT107 0272 Issue March 9 2005 XtremeDSP Development Kit IV User Guide Section 14 The High Performance FPGA Solutions Company Environmental Specifications In this section Outline of the Environmental Specification of the Kit 14 1 Specifications 14 1 1 Operating Temperatures The Kit has been tested under operation within the following temperature ranges 0 to 30 14 1 2 Storage Temperatures The Kit may be stored within the following temperature ranges 20 C to 80 C 14 1 3 Relative Humidity The Kit has been tested in the following conditions 20 to 95 non condensing NT107 0272 Issue March 9 2005 www nallatech com 107 Environmental Specifications NALLAT EC Y FPGA Solutions Company 108 www nallatech com NT107 0272 Issue March 9 2005 NALLATECH The High Performance FPGA Solutions Company Part Level Design This part of the User Guide provides information on how to create a complete system design based on the XtremeDSP Development Kit IV and includes details on
168. es information on the actual USB interface chip This LED will be green if the device itself has started up It should always be green when the Kit is powered up DIME II Module Power Supply LEDs The DIME II standard requires that a number of voltages be supplied to a DIME II module from the DIME II motherboard it is fitted to In the case of the Kit four power supplies provide specific power to the module For each of these power supplies an LED shows the power good signal when each power supply is turned on These power supplies are termed PSUA to PSUD The actual voltage generated for each is given in Table 21 on page 55 Silk Screen Color State State Description State Initial power After LED Voltage on state opened in FUSE Identifier Output PSUA Off Off i e RED On i e GREEN PSUA On D8 Red PSUB Off ov Off i e RED On i e GREEN Green PSUB On 3 3V Table 21 DIME II Module Power Supply LED States NT 107 0272 Issue March 9 2005 www nallatech com 55 LEDs 56 NALLATECH Silk Screen Color State State Description State Initial power After card LED Voltage on state opened in FUSE Identifier Output DI2 Red PSUC Off OV Off i e RED On i e GREEN Green PSUC On 1 5 DI3 Red PSUD Off ov Off i e RED On i e GREEN Green PSUD On 3 3V Table 21 DIME II Module Power Supply LED States Motherboard Main Power LEDs In addition to the power supplies for the module
169. eyond repair PASSING OF RISK AND TITLE The passing of risk for any supply made by the company shall occur at the time of delivery The title however shall not pass to the buyer until payment has been received in full by the company And no other sums whatever shall be due from the customer to Nallatech If the customer who shall in such case act on his own account and not as agent for Nallatech shall sell the goods prior to making payment in full for them the beneficial entitlement of Nallatech therein shall attach to the proceeds of such sale or to the claim for such proceeds The customer shall store any goods owned by Nallatech in such a way that they are clearly identifiable as Nallatech s property and shall maintain records of them identifying them as Nallatech s property The customer will allow Nallatech to inspect these records and the goods themselves upon request In the event of failure by the customer to pay any part of the price of the goods in addition to any other remedies available to Nallatech under these terms and conditions or otherwise Nallatech shall be entitled to repossess the goods The customer will assist and allow Nallatech to repossess the goods as aforesaid and for this purpose admit or procure the admission of Nallatech or its employees and agents to the premises in which the goods are situated INTELLECTUAL PROPERTY The buyer agrees to preserve the Intellectual Property Rights IPR of the company a
170. f 160 5 5 Additional control signals exist between the DAC and the FPGA to enable full control of the DACSs functionality The main features of the AD9772A are 14 bit DAC resolution Note that they are offset binary input for more details please see Firmware on page 37 160 5 5 max input data rate LVPECL clock inputs from the XC2V80 4CS144 Clock FPGA internal Phase Locked Loop PLL clock multiplier device feature single ended DC coupled 500 outputs via MCX connectors as standard 5 1 1 DAC Architecture The AD9772A s architecture comprises four key areas as shown in Figure 19 on page 30 IdGOW IAIA CLK Mode Select Filter MUX Ix 2x Control mE Control Edge 14 bit data Triggered Interpolation 14 bit DAC Latches Filter Ix CLK Current Outputs Figure 19 AD9772 Architecture Figure 19 on page 30 shows the internal architecture of the AD9772A Initially the user feeds 4 bits of data into the 9772 This data is latched into edge triggered latches on the rising edge of the reference clock interpolated by factor of 2 by the digital filter and then fed to the 14 DAC The filter characteristic can be set to either low pass or high pass for baseband and IF applications respectively The MODO input is used to control this function of the AD9772A The interpolated data can feed the DAC directly or undergo a ze
171. ferred to as FPGA RESET For more information on resets and using the FUSE Probe Tool please see the FUSE System Software User Guide on the supplied FUSE CD NT107 0272 Issue March 9 2005 www nallatech com 61 Resets 62 9 4 2 Listing of Calls in the FUSE API for Reset Control Both the XtremeDSP Development Kit IV resets are controlled via the following functions DIME_CardResetControl DIME_CardResetStatus When a design has been downloaded into the and the oscillators have been set to the desired frequency it is good practice to toggle all the resets within the design Essentially both functions consist of two parameters resetNum and a cmdMode resetNum is used to select between the different resets on the card cmdMode is effectively a command for the reset i e to enable assert LOW disable deassert HIGH Figure 36 on page 62 shows an example of the how to control the clocks via the C C FUSE API Enable the reset DIME CardResetControl handle drONBOARDFPGA drENABLE 0 Disable the OnBoardFPGA reset DIME CardResetControl handle drONBOARDFPGA drDISABLE 0 Toggle the OnBoardFPGA reset DIME CardResetControl handle drONBOARDFPGA drTOGGLE 0 Enable the System reset DIME CardResetControl handle drSYSTEM drENABLE 0 Disable the System reset DIME CardResetControl handle drSYSTEM drDISABLE 0
172. folder that includes all pin LOC and timing constraints Apart from the source files a Xilinx ISE project has been included on the XtremeDSP Development Kit IV CD at the location ROM DriveXExamples simple adc hookupWselimple adc hookup or is installed to the location where you installed the Kit CD This project has been created in Xilinx ISE 6 3i A UCF is also provided in the source folder that includes all pin LOC and timing constraints NT107 0272 Issue March 9 2005 www nallatech com 131 Feature Examples NALLATECH 17 2 4 Running the Example Please note that although this example can be run it is primarily intended as a simple introduction to ADC connection The bitfiles for the example have already been generated v To run the ADC Hookup example use the following procedures l Start the FUSE Probe Tool and assign the following bitfiles Osc clk 2v80 bit to the Clock FPGA Simple_adc_hookup bit to the main User FPGA 2 Toggle the resets Check FPGA Reset to enable the reset to the main User FPGA Check System Reset to enable the reset common to both FPGAs Click the button for Interface Reset to reset the interface core i e reset the Interface FIFOs Uncheck Reset to disable the reset to the main User Uncheck System Reset to disable the reset common to both FPGAs 3 You then connect a suitable input signal as specified in Analog ADC Inputs on p
173. ftware Please refer to the XtremeDSP Analog Capture Datasheet the XtremeDSP Development Kit IV CD at the location ROM Drive Application_Notes NT302 0035_XtremeDSP_Kit_Analogue_Capture Documents This provides example design for Analog capture using the XtremeDSP Development Kit IV 28 www nallatech com NT107 0272 Issue March 9 2005 NALLATECH XtremeDSP Development Kit IV User Guide The High Performance FPGA Solutions Company Section 5 DACs In this section Introduction to the DACs Hardware Aspects Firmware Aspects Software Aspects 5 1 Introduction The BenADDA DIME II module used in the XtremeDSP Development Kit IV has two analog output channels with each channel having independent data and control signals from the FPGA Two sets of 14 bit wide data busses are fed to the two DACs AD9772A devices each of which has an isolated supply and ground plane Figure 18 on page 29 illustrates the interfacing between one of the DACs and the FPGA Xilinx Virtex 4 User FPGA DAC AD9772A Data 0 13 Mode 0 1 Divide 0 1 XC4VSX35 Analog IOFF668 Data CLK FPGA Virtex II FPGA XC2V80 Clock Feedback 4CS144 Figure 18 DAC Interface NT107 0272 Issue March 9 2005 www nallatech com 29 NALLATECH The High Performance FPGA Solutions Comp any DAC device offers 4 bit resolution and a maximum conversion rate o
174. functions in the vidime h library 5 Now you can use this handle to the vidime interface the other functions such as viDIME DMAWrite DMARead 6 Once finished close the handle to the vidime interface using viDIME Close This frees up memory allo cated 7 Finally close the card handle and locate handles using the DIME CloseCard and DIME CloseLocate functions An example of this is provided on the XtremeDSP Development Kit IV CD at the following location ROM DriveXExampleslhost interface basic The main file OpeningASingleCard c is in the subfolder CCodeTester The actual VHDL source for this example is also included 15 4 2 Interface Performance Interface performance is largely affected by the type of interface used USB or PCI and PC performance This section provides performance figures recorded on a standard Nallatech PC configuration meeting minimum requirements for the XtremeDSP Development Kit IV USB 1 1 Interface USB Bandwidth 35 25 Read average R Write average 20 Bandwidth KBytes sec 256 512 768 1024 1280 1536 1792 2048 3072 5120 7168 9216 11264 13312 15360 17408 19456 Size of Transfer Words Figure 70 USB Interface Performance NT107 0272 Issue March 9 2005 www nallatech com 119 Building a Host Interface NALLATECH e FPGA Solutions Company 120 PCI Interface
175. g on the Generate Programming File process 214 www nallatech com NT107 0272 Issue March 9 2005 A NALLATECH XtremeDSP Development Kit IV User Guide 22 6 4 Real time debug The next step is to run the design on the Kit and view the probed outputs with the Chipscope Pro Analyzer l Connect the Parallel Cable to the available JTAG headers on the Kit If a Parallel IV pod is used with the ribbon cable a keyed socket J24 is available on the board If a flying lead connection is used a 0 1 pitch General JTAG header J14 is provided It is also necessary to connect the board to the USB port for power up if using the standalone power supply General JTAG Standalone Power Connector USB Connection PCI Connection Parallel IV JTAG header Figure 141 JTAG Header Positions on Card General JTAG Header Flying Lead Connection This is JTAG header that connects to the chain which runs through the standard JTAG pins on the user FPGA devices in the Kit and also some of the PROMs and CPLDs It is a standard 0 1 pitch header and can therefore support flying lead connections for the Parallel IV pod The header is shown in Figure 142 on page 215 123456789 Figure 142 General JTAG Connector J14 Pin Name Description 3 3V 3 3 Volts Supply 2 GND Signal Ground 3 N C Not connected do not use Table 52 General JTAG Header J14 Pinouts NT107 0272 Issue March 9 2005 www nal
176. gic is reset DMA RESET out std logic Data IO between Spartan and Virtex ADIO inout std logic vector 31 downto 0 Internal data bus DATA inout std logic vector 31 downto 0 Internal DMA data bus DMA DATA inout std logic vector 31 downto 0 end component The level entity makes use of the CLKB DIME Clock as the Primary Clock In the documentation this is sometimes referred to as CLKI or even DSP_CLK The entity has signals on it related to the interface to main User FPGA communications bus This is the declaration of the main for the Interface to User FPGA Interface Core described in application note NT302 0000 Spartan to Virtex Interface www nallatech com NT107 0272 Issue March 9 2005 NALLATECH GA Solutions Company XtremeDSP Development Kit IV User Guide component SYNCFIFO port RCLK std logic WCLK in std logic READ EN in std logic WRITE EN std logic FIFO RST std logic D in std logic vector 31 downto 0 Q out std logic vector 31 downto 0 FIFO STATUS out std logic vector 4 downto 0 FIFO FULL out std logic FIFO out std logic end component Declare the clock module that contains the DCM component dimeclk module port rst in in std logic clkin std logic locked out out std logic out out std logic end component
177. gital available in the Kit as there are simply connections to on the main User FPGA 52 www nallatech com NT107 0272 Issue March 9 2005 NALLATECH XtremeDSP Development Kit IV User Guide The High Performance FPGA Solutions Company Section 8 LEDs In this section Introduction to the LEDs in the Kit Hardware Aspects Firmware Aspects Software Aspects 8 1 Introduction The XtremeDSP Development Kit IV contains a number of user definable and status LEDs which allow you to check the operation and status of the Kit There are LEDs provided for user designs User LEDs and for displaying aspects of system status such as interface configuration and power Interface LEDs The LEDs used in the Kit are tricolor each LED displays a total of three different colors meaning each LED can act as three individual LEDs Each LED has a RED and GREEN diode inside their chip allowing for the display of RED GREEN and YELLOW ORANGE colors NT107 0272 Issue March 9 2005 www nallatech com 53 LEDs 54 NALLATEC MME The High Performance FPGA Solutions Company 8 2 Hardware 8 2 1 Physical Location of LEDs Figure 28 on page 54 shows the physical location of the LEDs on the board case lid Module User Motherboard User Status LEDs LED DI D3 D4 05 06 PSUA 2 5 Power Indicator D7 PSUB 3 3V Power Indicator D8 PSUC 1 2V Power Indicator D12 PSUD 3 3V Power Indicat
178. gnal Description Signal Name CLOCK FPGA Pin LVTTL Clock Oscillator Osc_CLK M6 GCLK4P Table 26 On board Crystal Oscillator Pinout Although the BenADDA DIME II module is supplied with a crystal oscillator that complements the speed of the ADCs this part can easily be replaced with an alternative exhibiting a lower speed rating The oscillator is fixed onto the BenADDA sockets and can simply lifted out Any 3 3v Oscillator with similar characteristics can be bought and placed into the socket pins The Oscillator supplied with NT107 0272 Issue March 9 2005 www nallatech com 67 Clocks NALLATECH The High Performance FPGA Solutions Comp any 68 the BenADDA is an 8 pin DIL package from Pletronics This oscillator is powered from 3 3V and any replacement oscillator should be the same specification Please contact support nallatech com for advice on replacing the standard oscillator 10 2 4 Inter FPGA Clock Management Overview There are a number of clock nets between the main User FPGA XC4VSX35 10FF668 and the Clock FPGA XC2V80 4CS144 These clock nets allow for a flexible routing of clock signals between the two to support the range of clocking structures and clock sources They also provide facilities to deskew the clock nets passed in between the two FPGAs There are signals for passing generated clock signals from the main FPGA to the Clock FPGA and also feedback signals from the Clock FPGA to t
179. gt C24 D 8 B20 ADC2 D 8 21 lt 9 gt BI7 ADC2 D 9 D24 lt 10 gt 17 ADC2 lt 10 gt C23 ADCI_D lt 11 gt 18 ADC2_D lt 11 gt D23 lt 12 gt 19 ADC2_D lt 12 gt A22 ADCI_D lt 13 gt A20 ADC2_D lt 13 gt C22 ADCI_DRY D21 ADC2_DRY B21 Table 72 ADC Signal Pinouts www nallatech com NT107 0272 Issue March 9 2005 The High Performance FPGA Solutions Comp NALLATECH XtremeDSP Development Kit IV User Guide Signal Name DAC I User FPGA Signal Name DAC 2 User FPGA XC4VSX35 XC4VSX35 IOFF668 PIN No 10FF668 PIN No ADCI_OVR DI7 ADC2 A23 Table 72 ADC Signal Pinouts 24 11 User I O Header J16 on module Signal Name User FPGA XC4VSX35 10FF668 PIN No User E25 User IO 2 E24 Table 73 User Header Pinouts NT107 0272 Issue March 9 2005 www nallatech com 241 Pinout Information NALLAT EC Y FPGA Solutions Company 242 www nallatech com NT107 0272 Issue March 9 2005 NALLATECH The High Performance FPGA Solutions Company Part XIII Troubleshooting This part of the User Guide provides troubleshooting information on the XtremeDSP Development Kit IV It includes Kit information in the form of a Frequently Asked Questions list Product Registration Updated troubleshooting information or product updates may be available in the Nallatech XtremeDSP Development Kit IV support lounge The Xtre
180. h Performance FPGA Solutions Company Part XI Board Firmware This part of the User Guide provides details on how to update the firmware supplied with the XtremeDSP Development Kit IV NT107 0272 Issue March 9 2005 www nallatech com 221 NALLATECH erformance FPGA Solutions C 222 www nallatech com NT107 0272 Issue March 9 2005 NALLATECH XtremeDSP Development Kit IV User Guide Section 23 Changing the Firmware In this section Introduction The Firmware Utilities How to Perform a Firmware Update 23 1 Introduction The Kit comes preconfigured with a 32bit 33MHz PCI core for 5V PCI signal environment and USBI I core for connecting the board via USB cable lt may be necessary to carry out a firmware update or to change the firmware so the card can be used in a 3 3V PCI signalling PCI slot as highlighted in the Getting Started Guide Please note that the interface firmware is provided in two PROMs One prom can be used for 5V PCI signalling whilst the other can be used for either 3 3V PCI signalling or USB Therefore if you configure the second PROM to allow for use in a 3 3V PCI signalling slot the USB interface on the Kit is disabled However you can change the firmware back if necessary This section describes two utility programs for loading in the specific firmware Please note that if power is removed from the card during reconfiguration or there is a power outage then the card may need to be retu
181. hannel to channel frequency response variation is limited to 0 085dB over f 2 Both ADC channels display a measure of crosstalk 80 5dB for Channel 1 73dB for Channel 2 However the Effective Resolution in both cases measures 12 4 bits and 12 3 bits respectively These figures are higher than the ENOB characteristics and suggest there is very little contribution to the pass band noise For more detailed information on the analog performance of the hardware please refer to the BenADDA Datasheet supplied on the XtremeDSP Development Kit IV CD at the location ROM Drive Documentation Datasheets 4 2 4 ADC Front End Configuration The BenADDA DIME II module used in the Kit has been designed to take either single ended or differential analog inputs The choice between single ended or differential inputs is made when the board is built Therefore in the case of the XtremeDSP Development Kit IV the module configuration has been set for single ended inputs The analog input signal is dc coupled through a differential op amp AD8138 which is fed into the actual ADC AD6645 The op amp has been configured to support either single ended or differential inputs and always outputs differential signal This means that all data will be input to the AD6645 differentially which helps to reduce noise induced on the input signal The hardware has also been designed with a 3rd order filter on the front end of the ADC which helps to reduce the overall
182. he PROMs and CPLDs that are used The header J24 on the motherboard allows a Xilinx Parallel IV cable to be plugged in The connector is keyed and follows the pinout on the datasheet supplied with the Parallel IV cable from Xilinx Please note that the Kit is not supplied with a Parallel IV download cable and that this section provides information on how to connect the cable only if one is available This is the recommended header to use if you are using the Xilinx JTAG Cosimulation option in the Xilinx System Generator tool NT107 0272 Issue March 9 2005 www nallatech com 93 Board and System Level Monitoring Capabilities NALLATECH 5 The High Pe FPGA Solutions Company 94 When the board is used inside the blue board case the Parallel IV ribbon cable is brought out through the small gap marked P IV in the side of the case This case should be opened the Parallel IV ribbon cable fitted and then the case closed again Fitting the cable To fit the cable remove the four screws round the sides of the case and remove the lid Then plug one end of the Parallel IV ribbon cable into the keyed header and bring the cable out to the small opening in the base of the case as shown in Figure 58 on page 94 Figure 58 Routing Cable Out from Header Then fit the lid back onto the case refitting the screws if necessary and ensure that the ribbon cable is not caught between the top and bottom of the blue case Finally conne
183. he main FPGA Generated Clock Signals from User FPGA Another method of clocking the DACs and ADCs is to use clock signals generated by the User FPGA Within the User FPGA there are three DIME II system clocks CLKA CLKB and see DIME II System Clocks on page 63 for more information Please note that in the Kit only CLKA and CLKB clock sources are programmable and CLKC is connected to a socket for a crystal oscillator These system clocks can be used to derive an appropriate clock frequency within the User FPGA and then driven into the Clock FPGA where they can be forwarded out to the appropriate DACs and or ADCs These generated clock signals are forwarded from the User FPGA to the Clock FPGA as four single ended signals From the Clock FPGA the forwarded clock signals can then be sent out to the DACs ADCs as differential signals Table 27 on page 68 shows the generated clock signals Clock Signal Signal Name Clock FPGA Pin XC2V80 User FPGA Pin Description 4CS144 XC4VSX35 IOFF668 Generated Clock GEN_CLKA K7 GCLK0P Generated Clock 5 BI2 Generated Clock B GEN CLKB M7 GCLK6P 5 Generated D GEN_CLKD 7 GCLK7S 14 Table 27 Generated Clock Pinouts Clock Feedbacks for De skewing and Clock Routing Feedback signals between the Clock and the User are necessary to allow all data going to and from the User FPGA to
184. heir employees to the exclusion of all other representations conditions or warranties express or implied The buyer agrees to execute and return any license agreements as may be required by the company in order to authorize the use of those licensable items If the licensable item is to be resold this condition shall be enforced by the re seller on the end customer Each order received by the company will be deemed to form a separate contract to which these conditions apply and any waiver or any act of non enforcement or variation of these terms or part thereof shall not bind or prejudice the company in relation to any other contract The company reserves the right to re issue its price list at any time and to refuse to accept orders at a price other than at the price stated on the price list in force at the time of order The company reserves the right to vary the specification or withdraw from the offer any of its products without prior warning The company reserves the right to refuse to accept any contract that is deemed to be contrary to the companies policies in force at the time PRICING All prices shown on the company s price list or on quotations offered by them are based upon the acceptance of these conditions Any variation of these conditions requested by the buyer could result in changes in the offered pricing or refusal to supply All quoted pricing is in Pounds Sterling and is exclusive of Value Added Tax VAT
185. his function returns module status information Example temperatures DWORD ModuleNum DWORD FPGATemp FPGATemp DIME _ Read the modu ModuleTemp DIME ber ModuleTemp MaxAlert MinAlert Read the FPGA temperature degr read the temperature alert levels and both the module and FPGA 0 oduleStatus hCardl le temperature d Modul L ModuleNumber dinfFPGATEMP S MaxAlert DI MinAlert DIME Read the minimum alert threshold temperature degrees c leStatus hCard1 ModuleNumber dinfTEMPAL grees c eStatus hCard1 ModuleNumber dinfMODULETEMP Read the maximum alert threshold temperature degrees c leStatus hCard1 ModuleNumber dinfTEMPALERTMAX NT107 0272 Issue March 9 2005 Figure 54 Reading Temperature Levels www nallatech com 89 Board and System Level Monitoring Capabilities NALLATECH DIME PPSStatus Syntax DIME PPSStatus DIME HANDLE handle DWORD ModuleNum DWORD SupplyNum DWORD CmdMode Arguments handle is a valid handle to a DIME carrier card ModuleNum This is the module number CSupplyNum This argument is used to specify the targeted power supply Valid supply numbers are given below dppsSUPPLYA Power Supply is selected dppsSUPPLYB Power Supply B is selected dppsSUPPLYC Power Supply C is selected dppsSUPPLYD Power Sup
186. his level please consider the cooling requirements for the system Table 44 on page 103 lists all the necessary jumper configurations for each fan Please note that each fan jumper is a 2 pin header one pin supplies 5 volts to the fan and the other provides a ground One of these headers is fitted with a lockable fan connector whilst the other is simply a 2 pin 0 1 pitch header This is intended to provide flexibility for the user to fit other fans if required for their own applications The silkscreen on the PCB for each fan jumper is a white box with a corner missing Pin is always nearest the missing corner Fan Jumper Name Description Supplies power to a 5 Volt Cooling Fan Pin 1 Ground J5 Pin 2 5 Volts Table 44 Fan Jumpers NT107 0272 Issue March 9 2005 www nallatech com 103 Power Specifications NALLATECH Fan Jumper Name Description Supplies power to a 5 Volt Cooling Fan Pin 1 Ground J6 Pin 2 5 Volts Table 44 Fan Jumpers Note that one of these connectors is already allocated to the fan fitted above the main User FPGA ADC Heatsinks Each ADC device AD6645 is fitted with a copper heatsink that has an optimal pin configuration for low airflow situations 13 2 3 External Connectors Standalone Power Connector This is a standard 8 way mini DIN connector Supply Voltage Looking at connector on BenONE Kit Motherboard 5V 5V 5V 12V 2 R
187. hival purposes or copy the Licensed Materials to another medium and keep the original Licensed Materials for backup and or XtremeDSP Development Kit IV User Guide archival purposes Additionally if the package contains multiple versions of the Licensed Materials then you may only use the Licensed Materials in one version on a single computer no event may you use two copies of the Licensed Materials at the same time 4 Warranty Nallatech Ltd warrants the media to be free from defects in material and workmanship and that the software will substantially conform to the related documentation for a period of ninety 90 days after the date of your purchase Nallatech Ltd does not war rant that the Licensed Materials will be free from error or will meet your specific requirements 5 Limitations Nallatech Ltd makes no warranty or condition either expressed or implied including but not limited to any implied warranties of merchantability and fitness for a particular purpose regarding the Licensed Materials Neither Nallatech Ltd nor any applicable Licenser will be liable for any incidental or consequential damages including but not limited to lost profits 6 Export Control The Software is subject to the export control laws of the United States and of the United Kingdom The Software may not be shipped transferred or re exported directly or indirectly into any country prohibited by the United States Export Administrati
188. i e Examples chipscope exa mple Figure 90 ICON Component Settings Then set the trigger width and data depth settings as they are requested ChipScope Pro Core Generator Trigger Port Options Trigger input and Match Una Settings Number af input Trigger Ports 1 Number of Match Units Used Trigger Matcn Type Basic Match Units Counter wiatr TRIGO Trigger Condition Settings Set the trigger width at 16 bits f Enable Trigger Sequencer Mai Number of Sequencer Lewis 16 lt and leave it as a basic match type Storage Qualification Condition Settings V Enable Storage Qualification Trigger Output Settings Enable Trigger Ovtpul Port Previous Net Figure 91 Setting ILA Trigger Width NT107 0272 Issue March 9 2005 www nallatech com 167 168 Chipscope ILA Support NALLATECH The High Performance FPGA Solutions Company EZChipScope Pro Core Generator Data Port Settings Data Depth Samples Data Same As Trigger Aggregate Data Width 16 Number of Block RAMs 17 Previous Next gt Include TRIGO widthz16 Set the Data Same as Trigger to be checked Also set the Data Depth to be 16384 samples Figure 92 Setting Data Capture Depth 8 ChipScope Pra Core Generator HDL Example Fie Settings FZ Generate HOL Example File HOL Language vr Synthesi
189. iagram For installation instructions please refer to the Getting Started Guide supplied in the XtremeDSP Development Kit IV CD wallet and also on the XtremeDSP Development Kit IV CD This guide covers all installation procedures for the Kit including hardware installation and FUSE software installation NT107 0272 Issue March 9 2005 www nallatech com 3 XtremeDSP Development Kit IV Overview NALLATECH 5 The H igh Performance FPGA Solutions Company 1 1 XtremeDSP Development Kit IV Key Features The XtremeDSP Development Kit IV serves as an ideal development platform for the Virtex 4 technology and provides an entry into the scalable DIME II systems available from Nallatech Its dual channel high performance ADCs and DACs as well as the user programmable Virtex 4 device are ideal to implement high performance signal processing applications such as Software Defined Radio 3G Wireless Networking HDTV or Video Imaging Figure I XtremeDSP Development Kit IV The key features of the Kit include Hardware XtremeDSP development board consisting of a motherboard populated with a module daughter card in a blue stand alone board case The motherboard is referred to as the BenONE Kit Motherboard and the module is referred to as the BenADDA DIME II module Motherboard Supports the supplied BenADDA DIME II module only Spartan ll FPGA for 3 3V 5V PCI or USB interface Host interfacing
190. ic With Edges in addition to the basic operations high low low high transitions can also be detected Extended performs lt gt gt lt lt gt comparisons Extended With Edges in addition to the extended operations high low low high transitions can also be detected Range performs lt gt gt gt lt lt in range not in range comparisons Range With Edges in addition to the range operations high low low high transitions can also detected In this example set the Match Type to Basic With Edges Number of Data Ports Up to 256 bits can be captured per sample meaning that the sum over all ports of the bits used per port must be less than or equal to 256 System Generator propagates the data width automatically therefore only the number of data ports needs to be specified this example the sine and cosine should be viewed therefore enter 2 Depth of Capture Buffer The depth of the capture buffer is a power of 2 up to 16384 samples for Virtex II Pro and Spartan 3 device families and 4096 for Virtex Virtex E Spartan ll and Spartan llE device families In this example set the depth to 512 NT107 0272 Issue March 9 2005 www nallatech com 211 System Generator Support NALLATECH 5 The High Performance 212 After parameterization the Chipscope GUI should look similar to that shown in Figure 136 on page 212 Block Parameters ChipScope l x
191. ic vector 47 downto 0 end ledsnake architecture ledsnake arch of ledsnake is ICON Pro core component declaration component icon port control0 out std logic vector 35 downto 0 y end component ILA Pro core component declaration component ila port control in std logic vector 35 downto 0 clk in std logic trigO in std logic 15 downto 0 y end component signal LEDi std logic vector 47 downto 0 signal COUNT integer ILA Pro core signal declarations signal control std logic vector 35 downto 0 signal trig0 std logic vector I5 downto 0 begin ICON Pro core instance i icon icon port map control0 gt control ILA Pro core instance i_ila ila port map control gt control ck gt CLK trig0 gt trig0 trig0 lt LEDi 15 downto 0 Invert as active low LEDs LED lt not LEDi DOSNAKE process RSTI CLK begin if RSTI 0 then active low LEDi lt others gt 0 elsif CLK event and CLK then LEDi lt LEDi 1 end if end process DOSNAKE end ledsnake_arch Declare the components for the ICON controller and the ILA logic analyzer Instantiate the ICON core Instantiate the ILA core Connect the trigger port to the internal LEDs signal Invert the internal LEDs signal and connect to the actual LEDs port on the top level Create a process that produces the actual counter that creates the
192. ides access to underlying FPGA resources through lower level abstractions allowing you to implement highly efficient FPGA designs Programming an FPGA using System Generator means describing a computation as a Simulink model generating a hardware description from this model and then compiling this hardware description into an FPGA configuration file called a bitstream The final step of compiling a hardware description into a bitstream is not unique to System Generator System Generator blocksets allow you to construct bit accurate and cycle accurate models of an FPGA circuit in Simulink Nevertheless it is universally true that a hardware engineer wants to see the design running in hardware System Generator provides hardware cosimulation interfaces that make it possible to incorporate an FPGA directly into a Simulink simulation The code generator has Hardware Cosimulation compilation targets analogous to the HDL Netlist target that automatically create a bitstream After creating the bitstream System Generator NT107 0272 Issue March 9 2005 www nallatech com 191 System Generator Support NALLATECH The High Performance FPGA Solutions Comp any 192 automatically incorporates an FPGA hardware platform configured with this bitstream back into Simulink as a run time block When the design is simulated in Simulink results for the compiled portion are calculated in hardware This allows the compiled portion to be tested in actual h
193. idges move data between physical devices across a defined physical media Edges are special types of node that indicate data entering leaving the network from another data transfer standard such as Figure 4 DIMEtalk Example Network www nallatech com Process Block NT107 0272 Issue March 9 2005 NALLATECH The High Performance FPGA Solutions Company Part XtremeDSP Development Kit IV Features This part of the User Guide provides information on the key features of the XtremeDSP Development Kit IV including physical layout ADCs DACs ZBT memory digital LEDs resets clocks bus structure system monitoring power and environmental considerations NT107 0272 Issue March 9 2005 www nallatech com 13 NALLATECH erformance FPGA Solutions C www nallatech com NT107 0272 Issue March 9 2005 NALLATECH XtremeDSP Development Kit IV User Guide Section 3 Physical Layout In this section XtremeDSP Development Kit IV Overview XtremeDSP Development Kit IV Board Case Layout XtremeDSP Development Kit IV Physical Layout 3 1 XtremeDSP Development Kit IV Overview Table 2 on page 15 lists the individual items that are supplied in the Kit Item Description BenONE PCI DIME II Motherboard PECA XtremeDSP Development Kit IV Board Case Quantity Australian Travel Adaptor UK Travel Adaptor EURO Travel Adaptor US Power Cord A
194. ied out 21 2 2 Using the ZBT as a Peripheral The ZBT can be connected to the embedded systems using the OPB EMC External Memory Controller peripheral provided in the EDK distribution There are a number of parameters that need set for this controller as follows PARAMETER C MEMO WIDTH 32 PARAMETER SYNCH MEM 0 PARAMETER MEM WIDTH 32 The following pins are used to connect to the ZBT chips NT107 0272 Issue March 9 2005 www nallatech com 181 Xilinx Embedded Developer s Kit EDK Support NALLATECH The High Performance FPGA Solutions Comp any 182 PORT Mem fpga_0_Generic_External_Memory_Mem_DQ which is STD_LOGIC_VECTOR 3I downto 0 port PORT Mem fpga 0 Generic External Memory Mem A which is a STD_LOGIC_VECTOR 3I downto 0 port PORT Mem WEN fpga 0 Generic External Memory Mem WEN which is a STD LOGIC port PORT Mem CKEN fpga 0 Generic External Memory Mem CKEN which is a STD LOGIC port PORT fpga 0 Generic External Memory Mem which is a STD LOGIC port PORT Mem CEN fpga 0 Generic External Memory Mem CEN which is a STD LOGIC port PORT ADV LDN 0 Generic External Memory Mem ADV which is a STD LOGIC port When physically connecting the address bus from the EMC peripheral to the address lines of the ZBT note that some translation of the address pins is required In the case of the XtremeDSP Development Kit IV
195. igure 143 on page 217 216 www nallatech com NT107 0272 Issue March 9 2005 A NALLATECH XtremeDSP Development Kit IV User Guide The High Performance FPGA Solutions Company Figure 143 Routing the Parallel IV Cable Out from Header Then fit the lid back onto the case refitting the screws if necessary and ensure that the ribbon cable is not caught between the top and bottom of the blue case Finally connect the Parallel IV pod to the exposed end of the ribbon cable as shown in Figure 144 on page 217 Both the connector on the cable and the socket on the pod are keyed for ease of use Figure 144 Re fitting the Case Lid first Connecting the Parallel IV Pod second 2 Open FUSE to power up the board Select Start gt Programs gt FUSE gt Software gt FUSE Probe From FUSE select Card Control gt Open Card Then select USB for interface click Locate Card At this point FUSE locates the BenONE Kit Motherboard and the top left corner of the FUSE Probe Tool displays the FPGA information as shown in Figure 116 on page 197 you have the card plugged into a PCI slot then select to open the card via PCI NT107 0272 Issue March 9 2005 www nallatech com 217 System Generator Support 218 B benone El Nallatech Virtex4VSxX35 FF668 Virtex2 80 Virtex IV 4V8X35 m Nallatech Benone Bl 5V PCI PROM Bl 3 3V PCI PROM BB Power Control S
196. ility of the code further down GND is then assigned to be a single bit and to be LOW The reset signal is active Low when it is input to the chip However the reset signal needs to reset a DCM which has an active high reset input Hence the need for the inversion of the input active low reset signal Following this the IBUFG BUFG and DCM components are instantiated to create a typical CLKO DCM circuit The CONFIG DONE signal is driven low as this allows the reset of the system to determine that the main User FPGA has successfully configured The DAC mode control signals are set to specific values for operation In this example these are fixed in the design but these could equally be set by a value in a software controllable register in a user design It is important that the reset signals to the DACs are not left floating In this example these are tied to 0 www nallatech com 137 Feature Examples ALL AT E CH The High Pe FPGA Solution 138 digital output of adc to digital input of DAC DataRegisters process RSTI begin This process is used to create a simple set of registers for the data captured the ADCs before it is sent to the DACs ADC2 lt 00000000000000 DACI_D lt 00000000000000 The data to the DACs is 2s complement ADC Peu pt pp AER converted to offset binary for the DACs This is converted by ADCI lt ADCI_D
197. ilized a system the user should ensure that B is driven low once the has been successfully configured Alternatively if a system initialisation sequence is required then B can driven low after this The FPGA then polls IOB to see that all other in the system have been configured 96 www nallatech com NT107 0272 Issue March 9 2005 NALLATECH XtremeDSP Development Kit IV User Guide Section 13 Power Specifications In this section Introduction to the Power Specification for the Kit i Hardware Enabling Power Supplies at Power On 13 1 Introduction The XtremeDSP Development Kit IV can be powered using either the standalone power supply provided with the Kit OR a PCI Slot This section details the overall power specification with a breakdown of power capabilities for individual power supplies The actual power requirements of a User FPGA design vary depending upon the design in terms of clock frequency toggle rates and device utilization 13 1 1 External Standalone Power Supply Specification A triple voltage 12V 12V 5V 45W external power supply is used The unit is capable of the following maximums 5 5V 2A 12V 0 8A 0 12 Note that the 2 and 3 supplies are generated from the 5V supply Therefore the absolute maximums provided in Table 40 on page 97 Component Effective 5V power draw Generation Kit Board Ad
198. ils on how to make use of Chipscope within the Xilinx System Generator tool are contained in Part X Xilinx System Generator Support on page 189 20 2 Connect a JTAG Download Cable A download cable is required in order to connect to the general JTAG chain through which the User FPGAs are configured Supported cables are the Parallel Ill or Parallel IV cables from Xilinx which can be connected to the two headers on the board One header supports flying lead connections from either pod and the other supports the faster ribbon Details of these headers are included on page 215 and page 216 NT107 0272 Issue March 9 2005 www nallatech com 163 Chipscope ILA Support NALLATECH 20 3 XtremeDSP Development Kit IV Chipscope Example 20 3 1 Overview This example is based around a simple ledsnake design which consists of a counter connected to available LEDs with the remaining bits connected to a header which can be studied on a logic analyzer The following steps should be followed to add Chipscope to a design Create the ICON and ILA components using the corresponding Chipscope applications These are effectively a controller component and a data capture component ILA Manually instantiate the generated components in the design and connect them up appropriately Alternatively the Chipscope Pro inserted tool can be used to manually insert components into existing designs Connect to the design using JTAG do
199. including the scripting language DIMEscript FUSE Probe Tool and the FUSE development APIs for C C with optional APIs also available for Java and MATLAB FUSE is available as FUSE for Windows and FUSE for Linux In the XtremeDSP Development Kit IV FUSE for Windows is only provided as part of the Kit Key features include fast and simple device configuration multiple card support multiple interface support interfacing and control of Nallatech hardware features Figure 3 on page 10 provides an overview of the FUSE operating system FUSE Reconfigurable Computer Operating System Third party tools support FUSE Tools User Application ILA FUSEprobe Application ISE DIMEscript System Generator FUSE FUSE APIs Tools and Toolbox for CIC Languages Matlab Java Reconfigurable FUSE Computing OS Windows Linux Vx Works Others e g NetBSD Standard OS Local DIME II Hardware Local PC Personal Computer qm DIME II Platform TCP IP Link 4 E Ethernet v Remote PC Personal Computer Ed DIME II Platform Figure 3 FUSE Overview Further details on FUSE are provided in the documentation supplied on the FUSE CD or installed as part of the FUSE installation process www nallatech com NT107 0272 Issue March 9 2005 NALLATECH XtremeDSP Development Kit IV User Guide The High Performance FPGA Solutions Company 2 5 MATLAB The FUSE Toolbox MATLAB is another lev
200. ingle stepped clock is selected NT107 0272 Issue March 9 2005 www nallatech com 207 System Generator Support NALLATECH The High Performance FPGA Solutions Comp any 208 6 Simulate the model by clicking on the Start simulation icon shown right Open both scopes and also the gain slider control as shown in Figure 133 on page 208 After a few seconds dur b ing which the FPGA is configured the simulation begins and waveforms appear in the scopes Slider Gain When the cosimulation is running you can adjust the gain control to see the effect on the hardware Scope shows the simulink simulation results Scope shows the results of when running through the actual FPGA hardware 0 50 100 150 200 250 300 350 40 Time offset 4400 Figure 133 Cosimulation Results 22 6 Chipscope Use in System Generator 22 6 1 Example Overview This example demonstrates how to connect and use Chipscope Pro the Xilinx Debug Tool within Xilinx System Generator The integration of Chipscope Pro in the System Generator flow allows real time debugging at system speed By inserting a Chipscope block into your System Generator design you can debug and verify all the internal signals and nodes within the FPGA After reviewing some characteristics of the Chipscope Pro Debug tool this example then describes the process of running the Chipscope block to a simple Simulink model deploying it
201. inouts Bank B www nallatech com 45 ZBT SRAM Memory Signal Name User FPGA XC4VSX35 10FF668 PIN No 46 NALLATECH ZBTB_D lt 3 gt AA24 ZBTB_D lt 4 gt AF21 ZBTB_D lt 5 gt AB22 ZBTB_D lt 6 gt AF22 ZBTB_D lt 7 gt AC23 ZBTB_D lt 8 gt ACI9 ZBTB 0 lt 9 gt AB20 ZBTB 0 lt 10 gt AF20 ZBTB lt gt AC2I ZBTB D I2 AC20 ZBTB D 13 W20 ZBTB_D lt 14 gt 21 ZBTB_D lt 15 gt AE21 ZBTB_D lt 16 gt 19 ZBTB_D lt 17 gt Y20 ZBTB_D lt 18 gt 21 ZBTB 0 lt 19 gt W2l ZBTB_D lt 20 gt 19 ZBTB_D lt 21 gt AFI9 ZBTB D 22 AA20 ZBTB D 23 21 ZBTB_D lt 24 gt V22 ZBTB_D lt 25 gt AC22 ZBTB_D lt 26 gt AA23 ZBTB_D lt 27 gt AD23 ZBTB_D lt 28 gt W22 ZBTB_D lt 29 gt AD22 ZBTB_D lt 30 gt AF23 ZBTB_D lt 31 gt AE23 Table 17 ZBT Data Signals Pinouts Bank B www nallatech com NT107 0272 Issue March 9 2005 A NALLATECH XtremeDSP Development Kit IV User Guide The High Performance FPGA Solutions Company 6 2 1 ZBT SRAM Clocking There is a simple setup for clocking the ZBT A common clock is sent to both ZBT chips with a feedback net which is the same matched length as the nets going to the clock pins on the ZBT devices This arrangement allows for de skewing of the ZBT clock Full details on this are provided in the Clocks feature section under ZBT Clocks on page 69 6 3 Firmware When building an interface to the
202. ion Language XST 21 Clock Pin Location Clock Period ns 25 Feed Create Testbench Import as Configurable Subsyst etiist Browse selection field Version XtremeDSP Kits had a number of FPGA options Override with Doubles Simulink System Period sec h 1324 According to Block Settings Generate ETT J cancer l Help Figure 129 System Generator Settings for PCI Cosimulation Flow 3 Once the parameters have been set click on the Generate button to start the System Generator flow The flow will create the netlist of the design but will also run the design through the synthesis and implementation tools to create a bitfile automatically The process execution is carried out in a com window shown in Figure 130 on page 206 Once complete a new library is created which con tains a single block for the cosimulation of the design This is the runtime block nt 206 pk it init5 MATLAB6p5p1 sys perl win3 The scripts will run to produce the implemented design Note that this could take a few minutes dependent upon the speed of the host PC When it completes a new library will be created for the design within the co simulation flow mac fir xtremedspkit demo hweosim Figure 130 Command Window and Generated Runtime Library www nallatech com NT107 0272 Issue March 9 2005
203. ion device in a design Local Bus LBUS Interface Virtex Il 2 80 4 5144 Configured with Adjacent Out Bus ADJOUT Es User Clock FPGA Appropriate Interface Control Virtex 4 gt Firmware i e USB PCI XC4VSX35 10FF668 Main User FPGA Programmable Clock Source B 09 gt Adjacent Comms In Bus Link 0 ADJIN Note that clock C is NOT initially available in the Kit It is a socket to allow users to populate their own crystals if required Connected bus Signals predominantly associated with the general kit i e JTAG access Inter FPGA Clock nets source clocks generated 7 7 clocks and feedback clock nets gt User Signals part or in whole associated with the FPGAs Figure 2 XtremeDSP Development Kit IV Functional Diagram For more information on communications between the User FPGA and the Spartan ll Interface FPGA refer to Interface FPGA to User FPGA Interface Core on page 114 ADCs refer to the features section ADCs on page 19 DACs refer to the features section DACs on page 29 ZBT SRAM memory refer to the features section ZBT SRAM Memory on page 41 2 status LEDs refer to the features section LEDs page 53 www nallatech com NT107 0272 Issue March 9 2005 NALLATEC The aah eae EE
204. ions sess 107 operating temperatures relative 107 storage 107 evaluation SoftWare sarreria 5 F LEDS 53 p o E s s s s 56 firmware nt interface LEDs 55 firmware Iiic DIME II module power supply LEDs 55 performing a firmware update interface FPGA configuration LED 55 update the firmware eene motherboard main power LEDs 56 fixed power supply seen USB physical interface LED 55 FPGA configuration 2 2 1 di eRRe4h Ga OEE iter 84 56 physical location access through JTAG headers set LEDs in FUSE 58 semg PEREAT 124 set LEDs in FUSE Probe Tool 57 module and device numbering within FUSE 123 A using FUSE Probe Tool mo d le user using general JTAG chain motherboard user status 56 using the FUSE G Local B s 80 LEGA DONEC 98 LVTTL clock oscillator 67 FPGAS on testate 6 www nallatech com NT107 0272 Issue March 9 2005 functional diagram eene 6 FUSE nami
205. it is 25Watts 5Volts 5Amps as defined the specification The Kit requires 5Volts and I 2Volts If you wish to exceed this level please consider the cooling requirements for the system For more information on system cooling please see Cooling on page 102 If the Kit is connected to PCI slot and you are developing large designs that may require high current ratings i e over 25W Nallatech recommend the use of the disk drive connector to increase the power rating The disk drive connector can ONLY be used when the Kit is inserted in a PCI slot The power source for the disk drive connector MUST be from the same power source as the PCI Slot The power requirements of the Virtex 4 FPGAs depend upon the density and speed of the application designs running in them The Xilinx Power Estimator can be used to estimate the power requirements of application designs For more information on the Xilinx Power Estimator use the following link http support xilinx com ise power_tools index htm www nallatech com NT107 0272 Issue March 9 2005 A NALLATECH XtremeDSP Development Kit IV User Guide The High Performance FPGA Solutions Company 13 2 Hardware The Kit has a number of devices that generate specific voltages required in the hardware As the Kit is based on the DIME II module standard it follows the standard approach in DIME II for providing voltages required by the module and also those required by the motherboard itself
206. k A with the input clock at the FPGA e g CLKA CLKB or CLKC is illustrated in Figure 41 on page 70 INPUT CLOCK CLOCK DISTRIBUTION SOURCE i e CLKA AF12 ZBT_CLK De skewed for ZBT ZBT_FB_IN ABIO AE12 clocking ZBT Data ZBT_ FB_OUT 10 User This net is the same physical length as the ZBT_CLK signal to the ZBT Memory KS This allows for de skewing Figure 41 ZBT SRAM Clocking Example CLKA Source Note that the physical length of the net running from the FB_OUT to FB_IN pin is the same as the length of the ZBT_CLK nets from the pin on the User FPGA to the pin on the ZBT devices The above arrangement ensures that the device is triggered in phase 10 3 Firmware After looking at the clocks from a hardware perspective it is important to understand how to make best use of them This Firmware section includes a brief discussion on the use of DCM Digital Clock Managers that are available in the Virtex 4 silicon and provides some notes and examples on using the clocks for specific purposes 10 3 1 Using the Virtex 4 DCMs Nallatech recommend use of the architecture wizard that is provided in the Xilinx ISE tools For Virtex 4 targets this provides a GUI based input to create a VHDL clock module that can be added to your project To use the Architecture wizard from an existing project simply go to the menu Project gt New Source The screen for a new source is sh
207. latech com 215 System Generator Support NALLATECH The High Performance FPGA Solutions Comp any Pin Name Description 4 TCK ALT JTAG TCK Signal 5 N C Not connected do not use 6 TDO ALT JTAG TDO Signal 7 TDI ALT JTAG TDI Signal 8 TRST ALT JTAG TRST Signal 9 TMS JTAG TMS Signal Table 52 General JTAG Header J14 Pinouts Fitting a Parallel IV Ribbon Cable The header J24 on the motherboard allows a Xilinx Parallel IV cable to be plugged in Note that this header is simply in parallel with the General JTAG header J14 The connector is keyed and follows the pinout on the datasheet supplied with the Parallel IV cable from Xilinx Please note that the Kit is not supplied with a Parallel IV download cable This section provides information on how to connect the cable only if one is available This is the recommended header if the Xilinx JTAG Cosimulation option in the Xilinx System Generator tool is chosen When the board is used inside the blue board case the Parallel IV ribbon cable is brought out through the small gap marked in the side of the case This case should be opened the Parallel IV ribbon cable fitted and then the case closed again To fit the cable remove the four screws round the sides of the case and remove the lid Then plug one end of the Parallel IV ribbon cable into the keyed header and bring the cable out to the small opening in the base of the case as shown in F
208. le 6 on page 26 displays the jumper settings for Differential coupling Jumper J Jumper J2 Position 1 3 0Q Position 1 3 0Q Position 2 4 240 Position 2 4 240 Table 5 Single Ended Configuration Jumper J Jumper J2 Position 1 2 00 Position 1 2 00 Position 3 4 DNP Position 3 4 DNP Table 6 Differential Configuration a DNP Do Not Populate Default Configuration Settings Unless otherwise stated the front end of the BenADDA DIME II module in the Kit is built to the configuration described in Table 7 on page 26 and Table 8 on page 26 The default settings include a filter and single ended coupling Roy 330 Ras 330 Rog 330 R30 330 3 3pF C 3 3pF Ce 3 3pF 3 3pF 33pF um 33pF T 82nH L4 82nH Ly 82nH Ls 82nH Table 7 Default Filter Configuration Note that component values have 1 tolerance Jumper J Jumper J2 Position 3 00 Position 1 3 00 Position 2 4 240 Position 2 4 240 Table 8 Default Coupling Configuration www nallatech com NT107 0272 Issue March 9 2005 NALLATECH XtremeDSP Development Kit IV User Guide The High Performance FPGA Solutions Company Assembly Drawing The reference designators for the filters and the jumpers are highlighted in Figure 16 on page 27 NOTE R5 R6 R7 amp R8 have NO silkscreen outline NOTE R33 is a Resistor Array L J
209. lot 0 Figure 145 Opening the Card in FUSE Open Chipscope Pro Analyzer Select Start gt Programs gt Chipscope Pro gt Chipscope Pro Analyzer Open JTAG Chain by clicking on JTAG Chain gt Xilinx Parallel Cable and selecting Xilinx Parallel IV Cable Note the index for the Virtex 4 devices available the XtremeDSP Kit XC4VSX35 10FF668 is index 3 and xc2v80 is index 4 Configure the using the following procedures Under the New Project Window right click on Device 3 and select Configure gt Device 3 At this point you need to look for the bistream which was generated in Step 11 on page 214 Select New File and scroll to your project directory SYSGEN examples chipscope netlist chip_clk_wrapper bit After configuration the status window at the bottom of the Chipscope Analyzer should reflect that one Chipscope core was found in the JTAG chain Similarly select Device 4 and Configure it with the osc clock 2v80 bitfile provided in the Chipscope project directory This second bitstream is used to program the clock driver FPGA on the board Import Chipscope Project File System generator creates a project file for Chipscope in order to group data signals into busses A bus is created for each data port so that it can be viewed in the same manner sign and precision in which it was viewed in the Simulink environment Load this project file by going under File gt Import gt Select New File and select chi
210. ly as shown in Figure 148 on page 219 ata vs tmd C data vs data Display fire Bus Selection v data0 v m datat w 1 0 99219 FEE o 52 Y 0 7362 Figure 148 Chipscope Bus Plot NT107 0272 Issue March 9 2005 www nallatech com 219 NALLATECH System Generator Support E The Nigh merter manta any 22 6 5 Importing Data Into MATLAB Workspace From Chipscope The data captured by Chipscope can now be exported back into the MATLAB workspace Export data from Chipscope Pro Analyzer Select File gt Export option from within Chipscope Pro Ana lyzer Select ASCII format and choose All Signals Buses to export Press the Export button and save the file as sinecos prn 2 Start MATLAB and change the current working directory to the location where you saved sinecos prn Type xILoadChipScopeData sinecos prn This loads the data from the prn file into the MATLAB work space In the workspace there are two new arrays named data0 and datal 3 The values be plotted using the MATLAB plot function Type plot 1 512 data0 1 512 which gives the plot shown in Figure 49 on page 220 File Edit View Insert Tools Window Help 82 T 1 0 100 200 300 400 500 600 Figure 149 Plotted Data in MATLAB 220 www nallatech com NT107 0272 Issue March 9 2005 NALLATECH The Hig
211. meDSP Development Kit IV is provided with an initial 90 day access to the support lounge upon registration This lounge provides access to Nallatech software updates and relevant application notes as they become available Continued access to this lounge beyond 90 days is available on establishment of a maintenance agreement with Nallatech The support lounge is available on the internet at www nallatech com solutions products kits In the actions section of this web page you will see an option to register your product Registration requires the serial number of the XtremeDSP Development Kit IV The serial number is located on the bottom of the small blue board case You can also refer to the Xilinx Answers Database that can be searched by going to http support xilinx com NT107 0272 Issue March 9 2005 www nallatech com 243 NALLATECH erformance FPGA Solutions C 244 www nallatech com NT107 0272 Issue March 9 2005 NALLATECH XtremeDSP Development Kit IV User Guide Section 25 FAQ In this section Frequently Asked Questions Please note that this FAQ contains a list of questions common at the time of print The current FAQ can be obtained after registration from within the Nallatech Support lounge during the support period 25 1 XtremeDSP Development Kit IV FAQs How do l Identify the Type of PCI Connection PCI defines two types of signalling environment which operate at either 3 3v or 5v The Be
212. med to be in place The user needs to design application designs for any FPGAs on the hosted DIME II module the BenADDA in this case The software running on the host PC is available as a pre designed GUI For users who require additional functionality and wish to have their own software front end the FUSE Software Library provides functions for use in application programs These facilitate functionality such as FPGA configuration reset clock speed setting data transfer NT107 0272 Issue March 9 2005 www nallatech com 6 Building a Host Interface 112 NALLATECH In order to make use of these software interfacing functions for specific data transfer to their designs certain signals must be connected into the design These signals are listed the Interface COMM Signal column in Table 47 page 112 and Table 48 on page 113 A core for use in the User FPGA is provided to aid the process of integration and communication with these signals For further details please see the PCI to User FPGA Interface Application Note provided on the FUSE CD at the location CD ROM Drive Application Notes NT302 0000 Spartan to Virtex Interface Interface COMM General Bus Signal DIME II Connector User FPGA XC4VSX35 Signal Name PIN No IOFF668 Pin No ADIO lt 0 gt LBUS lt 0 gt 023 ADIO lt I gt LBUS I PB2 V23 ADIO lt 2 gt LBUS lt 2 gt PB3 V26 ADIO lt 3 gt L
213. mmand modes ResetNum Description dinfFPGATEMP This command mode returns the die temperature of the FPGA in degrees Celsius Temperatures are accurate to degree dinfMODULETEMP This command mode returns the temperature of the module in degrees Celsius Temperatures are accurate to degree Note that this temperature is measured next to the User FPGA and hence usually follows the FPGA temperature It shows the temperature of the module as a whole but not one specific device Table 35 DIME_ModuleStatus CmdMode Argument Options 88 www nallatech com NT107 0272 Issue March 9 2005 XtremeDSP Development Kit IV User Guide ResetNum Description dinfTEMPALERTMAX This command mode is used to set the maximum temperature level for the temperature alert signal Once set if the FPGA die temperature exceeds this temperature the then the temperature alert signal is triggered Note that the power on default setting for this temperature is 255 degrees Celsius dinfTEMPALERTMIN This command mode is used to set the minimum temperature level for the temperature alert signal Once set if the FPGA die temperature falls below this the temperature alert signal is triggered Note that the power on default setting for this temperature is O degrees Celsius Table 35 DIME_ModuleStatus CmdMode Argument Options Return The return value is dependant upon the command mode Returns on error Description T
214. monitoring capability for the on board FPGA The API functions provide the ability to readback the junction of the FPGA and the external PCB temperature Other functions include the ability to set the minimum and maximum temperature thresholds The temperature thresholds are linked to the ALERTI signal when either threshold is reached the ALERTI signal to the on board FPGA is asserted Voltages can also be returned for the whole module or simply for one of the individual power supplies depending upon the API calls arguments The details of the module power supplies i e PSU_A are given in Power Specifications on page 97 The C C API functions detailed below are taken from the FUSE C C API Develobers Guide that is provided on the FUSE CD DIME_ModuleControl Syntax DWORD DIME ModuleControl DIME HANDLE handle DWORD ModuleNum DWORD CmdMode DWORD Value Arguments handle is a valid handle to a DIME carrier card ModuleNum is the module that is being addressed Note modules are numbered from 0 CmdMode This argument is used to specify what particular aspect of module is to be controlled ResetNum Description dinfTEMPALERTMAX This command mode is used to set the maximum temperature level for the temperature alert signal Once set if the FPGA die temperature exceeds this the temperature alert signal is triggered Note that the power on default setting for this temperature is 255 degrees Celsius Value should be the integer value that th
215. municate directly with external data There are two types of adjacent busses the Adjacent In bus and Adjacent Out bus These busses are designed to facilitate the use of pipelined architectures on multiple DIME II module systems where the resultant data processed one DIME II module can be passed to the next module for further processing Although the Adjacent busses are defined as Adjacent In and Adjacent Out note that both these busses connect to bi directional on the FPGA therefore the Adjacent In and Out busses can both be considered as bi directional despite their naming The sectioning into an In and Out bus is a historical DIME II naming convention where the names were used to highlight the potential dataflow in a multiple DIME II module system NT107 0272 Issue March 9 2005 www nallatech com 79 Bus Structure NALLATECH 80 The Local Bus is coupled from the Interface FPGA and the main User FPGA in the system In the Kit this is the XC4VSX35 10FF668 main User FPGA on the module On other Nallatech hardware this may be an FPGA on the motherboard itself The Local Bus is intended to be used as an overall system control or broadcast bus which can typically be utilized to memory map internal registers and memory space in the FPGA into microprocessor memory space As the hardware supplied in the Kit is based on a single DIME II module then most communication busses are used to provide digital or host interfacing cap
216. n Figure 76 on page 150 Process Properties x General Options Configuration options Startup options Readback options Encryption options Property Hame Value Security able Readback and Reconfiguratio i Create ReadBack Data Files Allow SelectMAP Pins to Persist Create Logic Allocation File Create Mask File Figure 76 Startup Options is not already selected click pull down menu Security and select Enable Readback and Reconfiguration Failure to enable readback and reconfiguration will result in the value being returned from the Virtex 4 status register of 0x0 during the configuration sequence which will be flagged as an error This will manifest itself in the configuration software reporting an error of DONE LOW INIT LOW No CRC errors If reconfiguration has not been enabled and you configure once it is necessary to cycle the power to the in order to clear the security protection on the FPGA www nallatech com NT107 0272 Issue March 9 2005 A NALLATEC XtremeDSP Development Kit IV User Guide The High Performance FP GA Solutions Company NT107 0272 Issue March 9 2005 www nallatech com 151 Common ISE Settings NALLATEC Y FPGA Solutions Company 152 www nallatech com NT107 0272 Issue March 9 2005 NALLATECH The High Performance FPGA Solutions Company Part VII Xilinx Impact Support This par
217. n as the Xilinx ISE project file i e Examples chipscope exa mple Disable Boundary Scan Component Instance Figure 86 ICON Generation Options I On the next dialog Figure 87 on page 165 leave the settings as VHDL provided you are using VHDL Then click Generate Core to produce the ICON core ChipScope Pro Core Generator EXAMPLE CODE Example Code Generation Options Design Entry Synthesis Tool gt Generate Example Files Select to generate the ICON core Previous Figure 87 ICON Generation Options NT107 0272 Issue March 9 2005 www nallatech com 165 Chipscope ILA Support NALLATECH High Perform nce FPGA Solutions Company 166 EZ ChipScope Pro Core Generator Generate Generating Core Messages reating eflist Xcon edn Component Name icon Device Family Virtex2 Control port count 1 Enable BSCAN instance true BSCAN chain USER1 Enable JTAG global clock buffer true Enable unused BSCAN ports false Once the code generation Warning EDIF Netlist being generated completes select START Processing com xilinx ip icon_pro icon_pro OVER as now need to Writing 9 generate the ILA core Post Processing EDIF netlist Generating constraints file ticon ncf Example Usage File icon_xst_example vhd CORE GENERATION COMPLETE Previous Figure 88 Actual ICON
218. n the system and returns a list of those detected on the specific interface Open the selected cards Open Cards Cancel Figure 96 Open Card Dialog www nallatech com NT107 0272 Issue March 9 2005 ANNE The High Performance FPGA Solutions Company NALLATECH XtremeDSP Development Kit IV User Guide Select a specific card and then click the Open Cards button to open the card in FUSE as shown in Figure 97 on page 173 z m m 68 Ele Edt Run Contgwraton System x 0 06000080 Verga to Transtar hb 0 06000020 we Data Road Data Lines Sequence Curar t zero Table Size fe few Data 10000002020 100000020 benene Sys Chock det to 90 00 Pittie D wip BenADOA Deaplesichipscope exasplelieiznuke bit assigned to besone card Nistex IT 47202 on the Wallacech BenlOA IY Yirtex 7235 77068 on the benene card has beem configured Figure 97 XtremeDSP Development Kit IV Hardware Opened in FUSE Now assign the ledsnake bit bitfile to the main User FPGA 4 5 35 10 668 To do this right click on the Virtex 4 4 5 35 10 668 device listed in the device tree Then select Assign Bitfile to bring up a dialog to browse to the bitfile Select the ledsnake bitfile from Examples chipscope_example folder Now click on the Resets Tab and enable all the resets as shown in Figure 98 on page 173
219. n user FPGA device 1 on Module 0 with the bit file Bitfile bit Status2 DIME_ConfigDevice hBenONE Bitfile bit 0 1 NULL 0 DIME DIME_CloseLocate hLocate Figure 73 Example C code to configure FPGAs with FUSE C C API 16 5 FPGA Configuration using DIMEscript DIMEscript is a high level scripting language which provides users with an easy to use language for the configuration and control of DIME systems DIMEscript uses a simple command set eliminating the need for developers to use complicated programming interfaces to control and communicate with application designs running in FPGAs DIMEscript also offers platform portability through ASCII based scripts allowing users to use DIMEscript on both Windows and Linux installations DIMEscript can be used either to write script files which can then be executed as a single process or can be used from a command line interface with the user executing commands as required Full instructions how to use DIMEscript are provided in the DIMEscript User Guide which is the FUSE CD at the location ROM Drive Documentation FUSE 16 6 FPGA Configuration using General JTAG Chain The General JTAG chain is the principal JTAG chain in the Kit and facilitates the configuration of the FPGAs on the DIME II module hosted on the BenONE Kit Motherboard The JTAG Chain is driven by the interface FPGA or can driven from the Gen
220. n which the Kit s FPGAs may be configured Hardware Examples Provides number of implemented examples of using particular hardware features NT107 0272 Issue March 9 2005 www nallatech com xiii NALLATECH The High Performance FPGA Solutions Comp any Xilinx ISE Support Details support and use of the Kit within the Xilinx ISE tool flow Xilinx Impact Support Details support for the Xilinx Impact programming tool Xilinx Chipscope ILA Support Details support for the Xilinx Chipscope ILA tool Xilinx Embedded Developers Kit Provides details on support for the Xilinx EDK tools Xilinx System Generator Support Provides details on support for the Xilinx System Generator tool Board Firmware Gives details on how to update or change the firmware for the host interface on the hardware Reference Information Provides full user pinout details for the main FPGAs available for programming Troubleshooting Contains help and a FAQ for common queries Related Documentation There are a number of additional sources of information on specific products used in the Kit Generally these are included in the documents folder in the CDs indicated in brackets Analog Devices Analog Devices AD6645 ADC Datasheet XtremeDSP Kit CD AD9772A DAC Datasheet XtremeDSP Kit CD Maxim 1617 Datasheet XtremeDSP Kit CD Micron ZBT SRAM Datasheet XtremeDSP Kit CD Nallatech BenADDA Datasheet XtremeDSP Kit CD Nallatech D
221. nONE Kit Motherboard is a universal card and can therefore be used in either signalling environment as shown in Figure 151 on page 245 back plate end back plate end Figure 151 5V top and 3 3V bottom signalling PCI Connectors If you wish to install the BenONE Kit Motherboard in PC using PCI slot please note that in the default configuration provided with the Kit User Guide the BenONE Kit Motherboard will only function correctly in a 5V PCI Signalling environment This is because one of XC 1800 proms is programmed with a 5VIO PCI bitstream and the other PROM that can contain the 3 3VIO PCI bitstream has been used for the USB bitstream This means that if you wish to use the hardware in a 3 3VIO PCI NT107 0272 Issue March 9 2005 www nallatech com 245 FAQ slot you will need to update the firmware Please refer to Changing the Firmware on page 223 for details on how this is performed What State Should the Module Power Supply LEDs be Showing Once the BenONE Kit Motherboard BenADDA DIME II module have been opened the power LEDs for the supplies used change from red to green as shown below in Figure 152 on page 246 Figure 152 Power LEDs Note that if a power supply is not used then the power indicator for that supply will remain RED indicating it is not switched on For example on the BenADDA DIME II module all four supplies are required therefore the four pow
222. ng conventions xvi FUSE overview FUSE interfaces key features 0606 H hardware examples eren ADC hookup example ADC to DAC example eee 135 host interface example senes 138 131 relevant application 146 hardware features 4 3 installation pack contents introduction certet J JTAG chain 222111 92 configuration status monitoring 95 general JTAG header eene 93 parallel IV JTAG header 93 fitting the 94 physical order of devices in JTAG chain 92 K e 4 Mg e 13 The High Performance FPGA Solutions Company cable assembly a IS Interfacing to connectors 22 N Nallatech systems and solutions ss 9 P physical layout u aa 15 back view front view ui pinout information u uu 229 ADC adjacent header 8 231 adjacent out 230 DAC signals eter r
223. ng from Interface FPGA to User FPGA Reading from the Interface FPGA is similar to reading from a FIFO The EMPTY signal goes LOW to indicate that there is data to be read The FIFO whose data is read from on the Interface FPGA is a First Word Fall Through with a latency of one clock cycle When reading from the Interface FPGA the user must ensure that the read enable is not active until at least one clock after the EMPTY signal goes LOW The read enable should go inactive immediately after the EMPTY signal goes HIGH although no data will be read if EMPTY is HIGH and the read enable is active NT107 0272 Issue March 9 2005 www nallatech com 115 Building a Host Interface NALLATECH The High Performance FPGA Solutions Company 116 The diagram in Figure 66 on page 116 shows functional representation of data reads in operation These are single word transfers DATA int Address ADIO Figure 66 Single Read Transfer The first read sends an address from the Interface FPGA to the User FPGA whilst the second read sends the data across The DATA int bus shows the internal data waiting to be driven onto the ADIO bus The diagram in Figure 67 on page 116 shows a burst read in operation h Address Data L Data Data K J X Figure 67 Burst Read Transfer This example shows a single address being sent from the Interface FPGA to
224. noise induced on the input signal thereby improving the resolution at the output of the ADC circuit Please note that the following information on specific builds for different front end configurations is for reference only Attempted repair or alteration of the goods as supplied by Nallatech immediately invalidates the warranty Nallatech will not provide support upon alteration and cannot guarantee performance characteristics subsequently obtained NT107 0272 Issue March 9 2005 www nallatech com 23 bes NALLATECH The High Performance FPGA Solutions Comp any Filter Details Channel I The BenADDA DIME II module front end for Channel is illustrated in Figure 14 on page 24 AIN AIN Figure 14 BenADDA Front End Schematic for Channel The adjustable filter components in Figure 14 on page 24 have the reference designators identified Table 3 on page 24 shows the possible filtering options and the related component values Please refer to the assembly drawing on page 27 for the location of these reference designators Filter Roll off decade Presenta 57 9MHz 330 330 3 3pF 3 3pF 33pF 82nH 82nH 60dB Absent 250MHz gt 242 240 I pF I pF DNP 009 00 0 25 0 25 Table 3 Filter component values for Channel a Default Build b Analog BW of AD6645 c DNP Do Not Populate d Resistor Value Note that component values have 1 tole
225. ns in Part Signal Name DIME II Connector PIN User FPGA XC4VSX35 10FF668 PIN No PP7LK lt 0 gt sC47 El 7 lt gt 5 48 lt 2 gt 5 49 G2 PP7LK lt 3 gt SC51 GI PP7LK lt 4 gt SC52 E3 PP7LK lt 5 gt SC53 E2 PP7LK lt 6 gt SC54 G4 PP7LK lt 7 gt SC55 G3 PP7LK lt 8 gt SC56 D2 PP7LK lt 9 gt SC57 DI PP7LK 10 SC58 2 PP7LK lt I I gt 5 60 CI Table 57 PLINK Pinouts User FPGA XC4VSX35 10FF668 232 www nallatech com NT107 0272 Issue March 9 2005 NALLATECH XtremeDSP Development Kit IV User Guide The High Performance FPGA Solutions Comp 24 5 1 HNallatech RS232 Test Header J and J12 Note that this header is intended for Nallatech debug purposes No cable is supplied for connection to this header Details are provided here for fullness of information about the headers on the card Signal Name User FPGA XC4VSX35 Header Pin IOFF668 PIN No R2 El J9 pin 2 T2 FI J9 pin RI E3 JI2 pin 2 TI E2 JI2 pin Table 58 Nallatech RS232 Test Header Pinouts Note that pins 3 and 4 on both 9 12 are ground connections Pin on J9 or J12 is marked the silk screen as the top left on each header 24 6 DIME II Control and Monitoring Signals 24 6 1 DIME II Specific Pins DIME II Connector Signal Name DIME II Connector PIN No User FPGA PIN No XC4VSX35 IOFF668 PI
226. nstraints Signal In Out Details EMPTY In 9ns before clock BUSY In 8ns before clock AS_DSI In 9ns before clock RDI_WR Out l Ins after clock RENI_WENI Out l Ins after clock ADIO In 5ns before clock ADIO Out 12 5ns after clock Table 49 Timing Information Timing specifications should be written into the UCF as a NET lt name gt OFFSET lt spec gt specification in other words NET EMPTY OFFSET 9ns BEFORE CLK Other signals There are two other signals between the User FPGA and the Interface FPGA These are RSTI and INTI RSTI This signal is driven by the PCI or USB FPGA Interface and can be used as a global reset within the User FPGA device INTI This signal is driven by the User FPGA and can used to signal an interrupt to the Interface and cause a PCI interrupt NT107 0272 Issue March 9 2005 www nallatech com 117 Building a Host Interface NALLATECH The High Performance FPGA Solution 15 3 4 Further Information on Interface Core Further information on the interface core is available in the following application notes PCI to User FPGA Interface Application Note available on the FUSE CD XtremeDSP Kit Ping Example Application Note available on the XtremeDSP Development Kit IV Please note that the following software section may provide more up to date support library information than the PCI to User FPGA Interface Application Note for the core 15 4
227. nt sem Component Name RegEx Filter em Orientation are system pbd TATED N gt J Figure 105 Main XPS Project www nallatech com 458 34 183 Xilinx Embedded Developer s Kit EDK Support NALLATECH High Performance FPGA Solutions Company 184 The design has already been created and the ISE project is included in the proj nav subfolder A User Constraint File UCF is also included called system ucf 21 3 1 Load the FPGA Design with FUSE Prior to connecting the debugger to the design the design should be loaded the oscillators setup and the resets to the design toggled Launch the FUSE Probe Tool and assign the implementation download bit file to the main User FPGA XC4VSX35 OFF668 FUSE Probe Edit View Run Configuration Card System Help benone Nallatech BenADDA IV Virtex4VSX35 FF668 Virtex2 v80 UserDefined benone 0 00000000 Dx00000000 1000000000 1000000000 0 00000000 10 00000000 10 00000000 10 00000000 0 00000000 0 00000000 0 00000000 0 00000000 0 00000000 0 00000000 0 00000000 0 00000000 0 00000000 10 00000000 400000000 1000000000 10 00000000 0 00000000 1000000000 1000000000 0 00000000 10 00000000 0 00000000 10 00000000 10 00000000 Ls
228. nt Kit IV CD that provides documentation on the Nallatech hardware as well as hardware support files for the use within the Nallatech FUSE environment Optional Nallatech evaluation software Xilinx XtremeDSP Software Evaluation CD supplied separately Evaluation for the Xilinx Foundation ISE Evaluation for the Xilinx System Generator for DSP Evaluation for MATLAB Simulink NT107 0272 Issue March 9 2005 www nallatech com 5 XtremeDSP Development Kit IV Overview NALLATECH The High Performance FPGA Solutions Compan y I 2 XtremeDSP Development Kit IV Functional Diagram The XtremeDSP Development Kit IV features three Xilinx FPGAs a Virtex 4 User a Virtex II FPGA for clock management a Spartan ll Interface FPGA The Virtex 4 device is available exclusively for user designs whilst the Spartan ll is supplied pre configured with firmware for PCI USB interfacing PCI USB interfacing firmware and low level drivers abstract the PCI USB interfacing from the user resulting in a simplified design process for user designs applications The Interface FPGA communicates directly with the larger User FPGA 4 5 35 10 668 via a dedicated communications bus that is made up of the LBUS and ADJOUT busses shown in Figure 2 on page 6 The Virtex 4 4 5 35 10 668 device is intended to be used for the main part of a user s design The Virtex ll XC2V80 4CS 144 is intended to be used as a clock configurat
229. nteger range to 29 8 Number of registers NUM REGSg integer range 029 4 port Interface clock CLK std_logic Global reset RSTI std_logic Indicates whether Spartan can receive data BUSY std_logic Indicates whether Spartan has data to send EMPTY std_logic Indicates that ADIO is address or data AS DSI std_logic DMA engine is writing data out DMA WEN std_logic DMA engine is reading data in DMA REN std_logic Interrupt INT std_logic Read Write enable WENI out std logic Indicates if Spartan is being read or being written to RDI WR out std logic Interrupt to Spartan INTI out std logic Current active address ADDRESS out std logic vector 30 downto 0 Write data into register WRITE STROBE out std logic Read data from register READ STROBE out std logic Current DMA count COUNT out std logic vector 31 downto 0 Enable DMA engine DMA ENABLE out std logic DMA direction DIRECTION out std logic DMA select DMA SEL out std logic vector 3 downto 0 DMA control is ready for DMA engine to send data DMA RDY out std logic DMA control has data for DMA engin to read DATA AVAILABLE out std logic Reset to rest of Virtex RST out std logic Synchronous reset SYNC RESET out std lo
230. nto the following categories Temperature monitoring JTAG Chain Access Configuration Status Monitoring 12 2 Temperature Monitoring On board Temperature Sensor The Kit is fitted with a User FPGA which can become very hot when running at full potential in certain environments As result the Kit is fitted with a temperature device that monitors the heat levels within the main User and also the ambient temperature of the module Figure 50 on page 84 shows the temperature sensor interface on the BenADDA DIME II module Main User FPGA Temperature Sensor Figure 50 Temperature Sensor Interface The Temperature Sensor used the BenADDA DIME II module is supplied from MAXIM Part Number MAX1617MEE For full details on the specification of this device please refer to the datasheet MAX 6 l 7 which is supplied the XtremeDSP Development Kit IV CD the following location CD ROM Drive Documentation Datasheets Signal Name User FPGA XC4VSX35 10FF668 PIN No Table 32 Temperature Sensor Pinouts 2V3000 The ALERTI signal is an active low signal that allows the temperature sensor to signal to the main User FPGA design that a user set temperature threshold has been exceeded This feature allows the design to automatically slow it s www nallatech com NT107 0272 Issue March 9 2005 NALLATEC The High Performance FPGA Solutions Company XtremeDSP Development Kit IV User Guide
231. o an LED and the clock pin Trigger Pin Double click on the Trigger Gateway Out select Specify Location constraint and type in D3 as shown in Figure 138 on page 213 Specify Location Constraints Pad Locations cell 5 1587 Show Implementation Parameters Figure 138 Trigger Pin Location Clock Pin Double click on the System Generator block set the clock period to 25ns and the clock pin location to A16 as shown in Figure 139 on page 213 FPGA Clock Period ns Clock Pin Location 25 16 Figure 139 Clock Pin Location a customized board is used pin location should be modified appropriately 9 Generate the netlist The last parameter to be updated before generating the netlist is the target device Double click on the System Generator token and select the following part Virtex 4 XC4VSX35 10 668 depending on which part is the board NT107 0272 Issue March 9 2005 www nallatech com 213 System Generator Support NALLATECH Check that the System Generator parameters match the ones shown in Figure 140 on page 214 and press Generate Xilinx System Generator Compilation gt XtremeDsP Development Kit PCI Part gt Virtex4 4 5 101668 Target Directory netlist Browse Synthesis Tool Hardware Description Language VHDL
232. o pin 0 1 pitch header that connects directly to the User FPGA There is no assigned function for this two pin header which is therefore free to be used for your desired application The two pin header is connected directly to the Virtex 4 User FPGA and therefore signals applied to this MUST be within the range of 0V to 3 3V Virtex 4 devices are NOT 5V tolerant Table 18 on page 50 contains the pinout information for the User header Pin Name User FPGA XC4VSX35 10FF668 PIN No User IO E25 User IO 2 E24 Table 18 Pinouts of User I O Header 7 2 2 P Link Bus Header J10 This header is connected to P LinkO the DIME II module slot Header Pin Number Name User FPGA XC4VSX35 IOFF668 PIN No l PPOLK lt 0 gt W7 2 PPOLK I V7 3 PPOLK lt 2 gt T8 4 PPOLK lt 3 gt U7 5 PPOLK lt 4 gt R8 1 2 6 PPOLK lt 5 gt R7 7 PPOLK lt 6 gt P8 8 PPOLK lt 7 gt N8 13 14 9 PPOLK lt 8 gt N7 10 PPOLK lt 9 gt 7 ll PPOLK 10 M8 12 PPOLK II L8 13 GND N A 14 GND N A Table 19 Pinouts of P Link Bus Header J10 7 2 3 Adjacent Bus Header J8 This header is a 28 bit general purpose bus and is connected to the Adjacent IN Bus the DIME II module slot which in turn is connected to on the main User FPGA www nallatech com NT107 0272 Issue March 9 2005 NALLATECH XtremeDSP Development Kit IV User Guide
233. o the power supplies for the module there are several LEDs which indicate the status of the main power supplies for the motherboard itself Table 43 on page 101 defines their use LED Purpose General Operation State DI4 3 3V power indicator GREEN Table 43 Motherboard Main Power LEDs NT107 0272 Issue March 9 2005 www nallatech com 101 Power Specifications NALLATECH The High Performance FPGA Solutions Comp any Purpose General Operation State DI5 5V power indicator GREEN Table 43 Motherboard Main Power LEDs 13 2 2 Cooling Main FPGA A single fan is attached to the main User FPGA Figure 62 on page 103 shows the range of experimental results for temperature vs power for the 4 5 35 10 668 FPGA when fitted with a fan The limits of the cooling depend on whether the board is used inside the blue board case with the lid fitted used with the lid removed or used with the board fitted in a PCI slot Where possible it is recommended that the temperature measurement facilities described in Temperature Monitoring on page 84 are used in high power designs to ensure the main FPGA operates within its allowable temperature range In addition to this Xilinx provide the XPower tool which is a useful way of approximating the power requirements of designs Limits when Used in the Board Case with the Lid Fitted The default setup is to use the hardware fitted inside the blue board case In this configuration there is
234. ogrammable Clocks are there on the BenONE There are two programmable clocks CLKA and CLKB Historically these clocks have sometimes been referred to as SYSCLK and DSPCLK Is CLKC Programmable in the XtremeDSP Kit CLKC is not a programmable oscillator in the Kit This is connected to a fixed oscillator socket for a Fixed Oscillator on the motherboard By default there is no crystal fitted as this is socket allows users to fit a specific crystal if needed When Configuring the FPGA via the FUSE software is it loading via JTAG or via a Serial or Select Map Mode JTAG is the configuration method Hence JTAG clock must be selected in bitfile options as the startup clock If CCLK is selected the programming fails and errors out NT107 0272 Issue March 9 2005 www nallatech com 247 i NALLATECH Performance FPGA Solutions C 248 www nallatech com NT107 0272 Issue March 9 2005 NT107 0272 Issue March 9 2005 Standard Terms and Conditions GENERAL These Terms and Conditions shall apply to all contracts for goods sold or work done by Nallatech Limited hereinafter referred to as the company or Nallatech and purchased by any customer hereinafter referred to as the customer Nallatech Limited trading in the style Nallatech the company submits all quotations and price lists and accepts all orders subject to the following conditions of contract which apply to all contracts for goods supplied or work done by them or t
235. ompleted form to Nallatech Boolean House One Napier Park Cumbernauld Glasgow G68 0BH United Kingdom If you prefer you may send your remarks via E mail to support nallatech com by fax to 44 0 1236 789599 If you want Nallatech to reply to your comments please include your name address and telephone number
236. on hardware platform and probing internal signals The following topics are discussed Chipscope Pro Overview Chipscope within System Generator Real Time Debug with the Chipscope Pro Analyzer Importing data back into MATLAB workspace from Chipscope Tool Requirements ISE 6 31 System Generator 6 3i or later Chipscope PRO 6 31 or later 22 6 2 Chipscope Pro Overview As the density of FPGA devices increases so does the impracticality of attaching test equipment probes to these devices under test The Chipscope Pro tools integrate key logic analyzer hardware components with the target design inside Xilinx Virtex Virtex E Virtex ll Virtex II Pro Virtex 4 Spartan ll Spartan IIE and Spartan 3 devices www nallatech com NT107 0272 Issue March 9 2005 XtremeDSP Development Kit IV User Guide Chipscope Pro tools communicate with these components during system operation and in effect provide the designer with a logic analyzer for nodes inside the Xilinx FPGA Chipscope provides a deep trace memory fast clock speeds and multiple trigger options which can vary in complexity is possible to capture and view signal activity inside FPGA without having to dedicate critical logic space come up with complex capture schemes or allocate additional 1 O pins Data samples are captured based on user defined trigger conditions and stored in internal block memory All control and data transfer is done via the JTA
237. on Act 1969 as amended and the regula tions there under or be used for any purpose prohib ited by the Act USER GUIDE CONDITIONS Information in this User Guide is subject to change without notice Any changes will be included in future versions of this document Information within this manual may include technical typing or printing inaccuracies or errors and no liability will arise therefrom This User Guide is supplied without warranty or condition either expressed or implied including but not limited to any implied warranties of merchantability and fitness for a particular purpose regarding the information provided herein Under no circumstances will Nallatech Limited be liable for any incidental or consequential damage or expense of any kind including but not limited to loss of profits arising in connection with the use of the information provided herein www nallatech com 251 Standard Terms and Conditions NALLATEC Y FPGA Solutions Company 252 www nallatech com NT107 0272 Issue March 9 2005 NT107 0272 Issue March 9 2005 The High Performance FPGA Solutions Company A abbreviations ADES e 19 analog inputs a 21 analog 22 architecture assembly drawing 7 CLOCKING JD P coupling specifications default configuration settings filter details
238. on the Kit hardware that provide digital I O for user designs The following digital I O is available 14 pin PLINK Bus Header the motherboard This provides 12 direct bi directional connections to the main User FPGA with the other two pins providing GND connections A 34 pin Adjacent Bus Header on the motherboard This provides 28 direct bi directional connections to the main User FPGA The remainder of the pins provide a 3 3V connection a GND connection and the remainder are no connects NC A 2 pin user header on the module This provides 2 direct bi directional connections to the main User FPGA Commonly the digital I O is used for interfacing to other hardware for the purposes of debug though the use of logic analyzers The naming conventions of the headers initially seem confusing but the naming conventions carried through from those used in the DIME and DIME II architectures Despite the header names it should be noted that these headers are simply bi directional user that connect directly to the pins of the main User FPGA To see where these headers appear on the Kit please refer to XtremeDSP Development Kit IV Hardware Physical Layout on page 17 NT107 0272 Issue March 9 2005 www nallatech com 49 The High Performance FPGA Solutions Company 50 7 2 Hardware 7 2 1 User Header Interfacing The BenADDA DIME II module used the Kit has a tw
239. or D13 Module User LED D2 Figure 28 Board Case Lid showing LED Locations Figure 29 on page 54 and Figure 30 on page 55 show the physical location of the Kit LEDs described in this section Module User Motherboard User LED DI Status LEDs PSUA 2 5 Power Indicator D7 PSUB 3 3V Power Indicator D8 USB Startup Indicator D9 PSUC 1 2 Power Indicator 012 PSUD 3 3V Power Indicator D13 Module User 5V Power nterface LED D2 Indicator FPGA DONE 010 Signal 012 Figure 29 Front View of Physical LED Locations www nallatech com NT107 0272 Issue March 9 2005 NALLATECH XtremeDSP Development Kit IV User Guide 3 3V power dd power indicator D14 indicator DI5 Figure 30 Back View of Physical LED Locations 8 2 2 Interface LEDs The interface LEDs provide information on aspects of the Kit such as power good signals from the power supplies that provide the required voltages to the BenADDA DIME II module There is also LED to show the output of the DONE signal for the interface FPGA to check it has successfully started up Interface FPGA Configuration LED LED 012 illuminates when the interface FPGA is fully configured If this LED is not lit shortly after power has been applied this means that the interface FPGA has failed to boot from the Xilinx 8 02 PROMs used on the Kit hardware USB Physical Interface LED The LED 09 provid
240. or internal deskew of port CLKIN gt CLKIN_OSC CLKFB gt CLK OSC DSSEN gt GND PSINCDEC gt GND PSEN gt GND PSCLK gt GND RST gt RESET gt CLKFB OSC LOCKED gt 5 1 Figure 34 Example of Reset and Setup This code snippet is taken from the adc to dac hookup example included on the XtremeDSP Development Kit IV CD at the location CD ROM 4 to dac hookup www nallatech com NT107 0272 Issue March 9 2005 NALLATECH The High Performance FPGA Solutions Company XtremeDSP Development Kit IV User Guide 9 4 9 4 1 The Kit resets can be asserted using the FUSE Probe Tool as shown in Figure 35 on page 61 Use the check boxes for either the FPGA or SYSTEM reset assets i e drives a LOW 0 Uncheck them to leave them de asserted HIGH 1 The INTERFACE RESET button simply toggles the interface FPGA to clear the data FIFOs as previously discussed Software FUSE Software Reset Function Please note that you must open and select a card in the FUSE Probe Tool prior to controlling the resets Probe File Edit View Run Configuration Card System Help lol x Data Number Read Data0 0 00000000 Write 0 00000000 Virtex2 80 ata1 0 00000000 0 00000000 Virtex IV 4 8 35 Data2 0 00000000 0 00000000 Nallatech Benone Data3 0 00000
241. ore information on customizing the global buffers Clock Buffer pute Input CE S Global Butfer CLKO CLKO More Info Output 0 4 OUT Cancel Figure 43 Virtex Il DCM Wizard For the input frequency it is recommended that you set the value to the desired clock frequency This sets the low or high frequency mode of the DCM For example for the DIME Clocks i e CLKA you should set this to an appropriate frequency for the design Here 80MHz has been specified as this is the frequency we intend to set the clock generator at in the software The selection of external feedback must be set when you are using an external feedback mechanism for example CLK FB IN net for the ZBT NT107 0272 Issue March 9 2005 www nallatech com 71 Using the DCM Locked Signal for Reset It is good design practice to generate the reset signal from the locked signal of the DCM to the rest of your design that depends on the generated clock Invert the active low reset input to the to convert it to an active high reset RST_EXT lt RST1 Instantiate the clock module Inst dimeclk module dimeclk module port map rst in gt RST EXT clkin in gt locked_out gt CLKB_LOCKED clk0O_out gt CLKBi Create a register to register the locked signal into the clock domain before use in the rest of the system process CLKBi begin if CLKBi ev
242. ote however that the card interface type should be changed in the code to match the Kit hardware interface PCI or USB The executables are located in CD ROM Examples host_interface_basic C CodeTester release or CD ROM Examples host_interface_basic CCodeTester debug NT107 0272 Issue March 9 2005 www nallatech com 139 Feature Examples NALLATECH High Performance FPGA Solutions Company VHDL Listing host interface vhd 140 library IEEE use IEEE std logic 1164 entity host interface is port Interface clock CLKB std_logic Global reset RSTI in std logic Indicates whether Spartan can receive data BUSY in std logic Indicates whether Spartan has data to send EMPTY std_logic Indicates that ADIO is address or data AS DSI std_logic Read Write enable WENI out std logic Indicates if Spartan is being read or being written to WR out std logic Interrupt to Spartan INTI out std logic Test LEDs LEDS out std logic vector 7 downto 0 Data IO between Spartan and Virtex ADIO inout std logic vector 31 downto 0 DUMMYSIGNAL out std logic end host interface architecture host interface arch of host interface is component SV IFACE generic Number of memory blocks in memory in bit size NUM BLOCKSg integer range to 29 4 Block size BLOCK SIZEg i
243. own in Figure 42 on page 71 Select Architecture Wizard and then DCM 70 www nallatech com NT107 0272 Issue March 9 2005 NALLATECH The High Performance FPGA Solutions Company XtremeDSP Development Kit IV User Guide User Document VHDL Module IP Schematic VHDL Library VHDL Package VHDL Test Bench Test Bench Waveform BMM File MEM File Implementation Constraints File Architecture Wizard State Diagram ChipScope Definition and Connection File File Name Location E SampleEDKProject xDSP_u Add to project The Xilinx DCM W In the DCM Wizard shown in Figure 43 on page 71 select the options that are appropriate for your application izard Figure 42 New Source Selection Input Clock Frequency Feedback Source 4 Internal Value 1K Phase Shift None C Fixed 84 MHz C ns DCM Instance Name PSEN PSINCDEC PSCLK CLKIN Source Intemal p 3 External Duty Cycle Correction C Extemal None Cx Yes No C Variable Advanced Bp 34 z More Info Xilinx DCM Wizard General Setup x DCM_INST a7 PSDONE Xilinx DCM Wizard Clock Buffers x This dialog sets up the clock buffers for all the DCM clock outputs selected in the General Setup dialog Clock Buffer Settings C Customize using grid below Reference the More Info button for m
244. p chipscope cdc Plot the Sine Waves In the New Project window under Device 3 gt Unit 0 ILA double click on Bus Plot A Bus Plot window appears as shown in Figure 146 on page 219 Select data0 and datal in the Bus Selection section and then arm the trigger Since no trigger conditions have been set values are captured immediately Both the sine and cosine appear as shown in Figure 146 on page 219 The display option can be changed to represent the wave forms with points lines or both www nallatech com NT107 0272 Issue March 9 2005 NALLATECH XtremeDSP Development Kit IV User Guide erformance GA Soluti Plot data vs time C data vs data Display gt line 7 Bus Selection Figure 146 Chipscope Bus Plot 7 Setup Trigger In the Trigger Setup window shown in Figure 147 on page 219 change the current XXXX XXXX value with 0000 0000 Once the counter hits 0 Chipscope starts capturing values Ear lier the buffer was setup to 512 so 512 data points can be visualized in Chipscope Re capture the data Trigger Setup Device 3 0 0000 0000 Bin Figure 147 Trigger Setup Again a 2 clock delay is seen at the beginning of time on the sine due to the 2 clock latency through the SineCos Look Up Table Modify the trigger value to 0000 0010 decimal 2 and re capture the data Now the sine and cosine start at 0 and respective
245. page 159 Preferences Configuration Operation System ACE Operating Made C Continue on fail Novice Stop on fail C Expert Message Level Startup Clock FPGA Detailed Automatic Correction C Brief Indicate Error C Ignore Setting Cable Leads PC IV C Ribbon Cable 5 MHz Flying Leads 2 5 MHz C Custom Connection 200 KHzJ IV Concurrent Mode CPLD amp PROM Use HIGHZ instead of BYPASS Automatic Checksum Insertion CPLD amp PROM Keep intermediate SVF file System Figure 83 Setting Cable Preferences There is a section for Cable Leads PC IV If you are using the flying leads this should be set to 2 5MHz if you are using the ribbon cable this may be set to a higher setting Assigning Bitfiles and Configuring To assign bitfiles to the Clock FPGA and the main User FPGA right click on each device and select Assign New Configuration File This brings up a dialog to browse to the bitfile of your choice Please note that you may wish to change the Files of type to bit unless already selected NT107 0272 Issue March 9 2005 www nallatech com 159 Impact Support NALLATECH After assigning bitfiles you should now configure the devices To do this right click on each device in turn and select Program This will bring up the programming dialog shown in Figure 84 on page 160 Program Options Verity Virtex l Pro Cancel Help
246. pened by In the software debugger go to Run gt Connect to target In the dialog that appears select the target type and hostname as shown in Figure 109 on page 186 Click OK to bring up a prompt which states that a connection was established Target Selection Set breskpoint at main Connection Target Remote TCP XMD hd Hostname localhost Set breakpoint at V Set breakpoint at exit Port 1234 V Display Download Dialog Use xterm as inferior s Figure 109 Set the Target Selection 186 www nallatech com NT107 0272 Issue March 9 2005 NALLATECH Fee cte XtremeDSP Development Kit IV User Guide Then go to Run gt Run You will see the program ELF file being downloaded to the BRAM in the design Once it is complete it will breakpoint at the first valid line as shown in Figure 110 on page 187 TestApp c Source Window DER Run View Control Preferences Help SOOO Qo sema gt restapp c 61 62 i lt gpio_width 1 i XGpic_mSetDataReg BaseAddress 1 j 64 2 3 lt lt 65 for k 0 k 1000000 k 4 66 wait 67 es numTimes 70 3355 zi ROR int main void Mote these are initialised high I want to show active low leds on for passes int testresult 0 0 WriteToGPOutput KPAR_LEDS_BASEADDR testresult D
247. ply D is selected dppsALLSUPPLYS All supplies are selected Table 36 DIME_PPSStatus Supply Number Options CmdMode This argument is used to specify what particular aspect of programmable power supplies information is required Description dppsVOLTAGE This command mode selects that only voltage information is returned The voltage returned is given in millivolts and has an error of 100millivolts Table 37 DIME_PPSStatus Command Mode Options Return The return is dependant upon the selected command mode Description Returns status information for the programmable power supplies Note The voltage capabilities are only applicable to DIME II systems 90 www nallatech com NT107 0272 Issue March 9 2005 NALLATEC XtremeDSP Development Kit IV User Guide The High Performance FPGA Solutions Company Example Get the Voltage for module 0 power supply C DWORD Voltage Voltage DIME PPSStatus hCardl dppsMODULEO dppsSUPPLYC dppsVOLTAGE printf Core Voltage is d millivolts n Voltage Get the Voltage for all of module O0 Voltage DIME PPSStatus hCardl dppsMODULEO dppsALLSUPPLIES dppsVOLTAGE printf The total Voltage for Module 0 is d n Voltage Figure 55 Getting Information on Power Supply Voltages NT107 0272 Issue March 9 2005 www nallatech com 91 Board and System Level Monitoring Capabilities NALLATECH The High Performan
248. pplying voltages the range IV to 3 3V at a maximum current of 15A abs max Note that no user intervention is required to set up the PPSs these are automatically configured by the system Modular Fixed Power Supply FPS Nallatech offer the fixed power supply option which has a reduced output current capability and produces a fixed voltage output This option reduces the flexibility of the BenONE Kit Motherboard as only DIME II modules with the same power supply requirements will function Power supplies are configured at the time of manufacture voltages in the range of IV to 3 3V are available with a maximum output current of 7A abs max Although the unit is capable of supplying 7A abs max the actual output voltage and more importantly the drop from the input to the output limits the operating range of the unit due to its ability to dissipate the heat generated by the conversion The following calculations can be used to work out the max power that can be drawn For a FPS that is supplying 3 3V to the system with an ambient temperature TA of 25 C and a thermal coefficient of 35 C W 7 0 gt T T 0 xP ax where0 235 C W T 2125 C max T 25 gt 125 25 35xP gt 2 857W P MAX lout yax x V Vour 2 857 Iout yx x 5 3 3 louty x 1 681 www nallatech com NT107 0272 Issue March 9 2005 NALLATECH XtremeDSP Development Kit IV User Guide For a FPS
249. r If multiple shipments are requested by the buyer multiple delivery charges will be made In the case of multiple deliveries separate invoices will be raised If requested at the time of ordering an alternative delivery service can be used but only if account details are supplied to the company so that the delivery can be invoiced directly to the buyer by the delivery service The buyer accepts that any to be advised scheduled orders not completed within twelve months from the date of acceptance of the original order or orders held up by the buyers lack of action regarding delivery can be shipped and invoiced by the company and paid in full by the buyer immediately after completion of that twelve month period INSURANCE All shipments from the company are insured by them If any goods received by the buyer are in an unsatisfactory condition the following courses of action shall be taken If the outer packaging is visibly damaged then the goods should not be accepted from the courier or they should be signed for only after noting that the packaging has sustained damage If the goods are found to be damaged after unpacking the company must be informed immediately Under no circumstances should the damaged goods be returned unless expressly authorized by the company If the damage is not reported within 48 hours of receipt the insurers of the company shall bear no liability Any returns made to the company for any reason
250. r both DACs 1 MODO lt DAC1_MOD1 lt lt DAC2_MODO lt DAC2_MOD1 lt disable resets for DACs DAC1_RESET lt DACZ RESET lt optimum settings for sampling rate DAC1_DIVO lt DAC1_DIV1 lt DAC2_DIVO lt DAC2_DIV1 lt 5 3 1 Figure 25 Code Example of Setting fixed DAC Control Signals Two s Complement vs Offset Binary Format The DACs expect an input in offset binary format In this format An input of ALL 055 is the lowest value and would give the minimum full scale output from the DAC For this input the DAC device AD9772A will generate an output of IV An input of ALL 15 214 1 is the highest value and would give the maximum full scale output from the DAC For this input the DAC device AD9772A will generate an output of IV There is however an inverting op amp on the output of each DAC prior to the signal being output via the MCX connector This means that the output from the DAC is inverted Therefore in actual operation An input of ALL 0 s is the lowest value and would give the minimum full scale output from the DAC For this input the DAC device AD9772A will generate an output of 1 An input of ALL 1 214 1 is the highest value and would give the maximum full scale output from the DAC For this input the DAC device AD9772A will generate an output of IV www nallatech com NT107 0272 Issue March 9 2005 NALLATECH XtremeDSP Development Kit IV User Guide Conve
251. rance 24 www nallatech com NT107 0272 Issue March 9 2005 A NALLATECH XtremeDSP Development Kit IV User Guide The High Perform ance FPGA Solutions Company Channel 2 BenADDA DIME II module front end for Channel 2 is illustrated in Figure 15 on page 25 AIN AIN Figure 15 BenADDA Front End Schematic for Channel 2 The adjustable filter components in Figure 15 on page 25 have the reference designators identified Table 4 on page 25 shows the possible filtering options and the related component values Please refer to the assembly drawing on page 27 for the location of these reference designators Filter Roll off decade Present 57 9MHz 330 330 3 3 3pF 33pF 82nH 82nH 60dB Absent 250MHzb 240 240 pF I pF 00 0 25 0 25 Table 4 Filter Component Values for Channel 2 a Default Build b Analog BW of AD6644 c DNP Do Not Populate d Resistor Value Note that component values have 1 tolerance NT107 0272 Issue March 9 2005 www nallatech com 25 ADCs 26 NALLATECH Coupling Specifications BenADDA DIME II module front end be configured for Single ended or Differential coupling The configurable jumper JI in Figure 14 on page 24 J2 in Figure 15 on page 25 determine the coupling arrangement Table 5 on page 26 displays the jumper settings for Single Ended coupling whilst Tab
252. rd For example LocateType and MBType respectively determine which interface and motherboard type should be searched for Once the software has found the Kit the next step is to open the card using DIME OpenCard LOCATE HANDLE LocateHandle int CardNumber DWORD Flags This is required to open the card and perform all the necessary set up procedures in order to interface to the BenONE Kit Motherboard This function requires several arguments to open the card LocateHandle is the handle returned by the DIME LocateCard function CardNumber is the index of the card within the locate handle that the user wishes to open while Flags is a parameter which allows users to customize the card opening process The DIME OpenCard handle is passed to later functions in order to allow these functions to communicate with the card Once the board is open a number of software functions can then be called to perform operations on the re programmable devices in the chain This stage covers functions such as configuration of individual devices setting bitfile names resetting FPGA devices and other functions Once the application has finished using the Kit hardware the handle returned from DIME should be closed in order to free all the resources used to interface to the card on the host system This can be accomplished by using www nallatech com NT107 0272 Issue March 9 2005 A NALLATECH XtremeDSP Development Kit IV User Guide The High Perform
253. required as a result of causes other than ordinary authorized use including without limitation accident air conditioning humidity control or other environmental conditions Under no circumstances will the company be liable for any incidental or consequential damage or expense of any kind including but not limited to personal injuries and loss of profits arising in connection with any contract or with the use abuse unsafe use or inability to use the companies goods The www nallatech com company s maximum liability shall not exceed and the customers remedy is limited to either i repair or replacement of the defective part or product or at the companies option ii return of the product and refund of the purchase price and such remedy shall be the customer s entire and exclusive remedy Warranty of the software written by the company shall be limited to 90 days warranty that the media is free from defects and no warranty express or implied is given that the computer software will be free from error or will meet the specification requirements of the buyer The terms of any warranty offered by a third party whose software is supplied by the company will be honoured by the company exactly No other warranty is offered by the company on these products Return of faulty equipment after the warranty period has expired the company may at its discretion make a quotation for repair of the equipment or declare that the equipment is b
254. rminated into 500 load this option provides a fully differential 0 5 Vp p output signal swing 5 2 5 DAC Clocking Each DAC device is clocked directly by an independent differential LVPECL signal This LVPECL signal is driven from Virtex ll 2 80 4 5144 FPGA Clock FPGA which is solely dedicated to managing the various methods for clocking each ADC and DAC device in the Kit The way the DACs are clocked depends on the bitfile that is assigned to the dedicated Clock FPGA A number of clock sources can be used through the Clock FPGA including On board 105MHz crystal External clock input via the middle MCX connector Clocks from the programmable oscillators available in the Kit Please note that although the DAC devices can support a clock frequency up to 160MHz the ADC devices can only support a clock input up to 105MHz This is important if you are creating your own specific clock configuration for the Clock FPGA Please refer to Clocks on page 63 for details on how the Clock FPGA be used 36 www nallatech com NT107 0272 Issue March 9 2005 NALLATECH XtremeDSP Development Kit IV User Guide The High Performance FPGA Solutions Company 5 3 Firmware The DACs are connected to the main User FPGA a number of signals The following signals are highlighted here for DACI although there are a set of corresponding signals for ADC2 DACI D 13 downto 0 This is the offset binary input to the DAC Bit 1
255. rned for default configuration re programming 23 2 The Firmware Utilities Getting the Firmware Update Utilities Please note that these utilities are not provided on the CD and can be downloaded from the support lounge if required Benone_32PCI_USB exe This file allows the BenONE Kit Motherboard to be configured with a 32 bit 33MHz PCI core for the 5V PCI signal environment and a USB core for a connection to the host PC Benone 32PCI 64 This file allows the BenONE Kit Motherboard to be configured with a 32 bit 33MHz PCI core for the 5V PCI signal environment and a 64bit 33MHz PCI core for the 3 3V PCI signal environment NT107 0272 Issue March 9 2005 www nallatech com 223 Changing the Firmware NALLATECH The High Performance FPGA Solutions Comp any 23 3 Performing a Firmware Update It is strongly advised to update the firmware via a PCI slot if available generally a 32 bit PCI slot Updating over USB takes significantly longer and therefore raises the risk of problems due to power or host computer problems USB should only be used for changing the board firmware if there is no way of using a 32 bit PCI slot 23 3 Converting from 5VIO PCI and USB firmware to 5VIO and 3 3VIO PCI firmware The firmware can be updated using the PCI connection or the USB connection however using a 32 bit PCI slot is highly recommended Updating via PCI v To update via PCI use the following procedures l
256. ro stuffing process enabled using MODI This process involves inserting a mid scale sample after every data sample originating from the digital filter which improves the pass band flatness of the DAC and also allows for the extraction of higher frequency images The AD9772A generates a variety of clock frequencies to operate its elements at the correct rates To achieve these frequencies it utilizes an internal PLL whose VCO can generate clock rates of up to 400MSPS The AD9772A can be operated with the PLL enabled or disabled both operations are supported the BenADDA DIME II module used the Kit The combination of the MOD ad DIV input control signals determines the effective operation of the DAC devices The hardware section which follows provides more details on the MOD and DIV pins 30 www nallatech com NT107 0272 Issue March 9 2005 A NALLATECH XtremeDSP Development Kit IV User Guide The High Performance FPGA Solutions Company Full details of the DAC AD9772A device are provided in the Analog Devices AD9772A Datasheet on the XtremeDSP Development Kit IV CD at the location Drive Documentation Datasheets 5 2 Hardware The BenADDA DIME II module supports two output configurations a single ended DC coupled output and differential directly coupled output The standard Kit is configured to have single ended DC coupled outputs from the DACs Both these output configurations are described later in this s
257. routing 68 AS DS signal 115 generated clock signals from User 68 i e B Jr T on board 65MHz oscillator BenADDA je physical clock resources board case layout programmable oscillators set clocks in FUSE Wn rc set clocks using FUSE Probe Tool 75 right side source descriptions 65 board monitoring 84 using module 65MHz crystal or external MXC clock73 o pil using the DCM locked signal for 72 temperature monitoring using the DIME clocks eee temperature using the Virtex ll DCMs using FUSE ZBT docks e using FUSE Probe Tool ZBT SRAM clocking 70 BUS SCrUCtUre M comms parallel link bus communications bus protocol 115 DIME II communication busses Config DONE signal s 95 functional 1 contact details iii BUSY eiecti D C DAC
258. rting from Two s Complement to Offset Binary It is a straight forward process to convert from two s complement to Offset binary format which involves taking two s complement input and inverting the top most bit Figure 26 on page 39 shows the example code for this conversion digital output of adc to digital input of DAC DataRegisters process OSC RSTIl begin if RSTl 0 then ADC1 lt ADC2 lt 00 100 DAC1_D lt i DAC2_D lt 00 10000 elsif CLK OSC and CLK OSC event then ADC1 lt ADC1_D ADCZ lt 2 D 1 D lt not not ADC1 13 6 ADC1 12 downto 0 DAC2 D lt not not ADC2 13 amp ADC2 12 downto 0 end if end process Figure 26 Code from adc to dac hookup Example 5 3 2 Timing Constraints It is necessary to account for the setup and hold times required for the DAC devices These timings are listed in full in the DAC AD9772A Analog Devices AD9772A Datasheet on the XtremeDSP Development Kit IV CD at the location CD ROM Drive Documentation Datasheets The timing requirements depend on your design You should account for a Ins delay for traversing the PCB in your calculations In che adc to dac hookup the following example timing constraint on the data signals is used NET 4 lt gt OFFSET OUT 2 ns AFTER fb This is a suggested constraint and the actual constraint depends on the design Note that if the control signals are not fixed
259. ructions on how to use the tool are provided in the FUSE System Software User Guide on the FUSE CD 16 4 Configuration using the FUSE APIs The FUSE Software development API enables users to call functions to control DIME hardware in their own programs This allows users to develop software applications to complement the FPGA application designs running on DIME hardware An example of FPGA configuration using the FUSE API is provided in Figure 73 on page 126 FUSE 5 are available to support a number of development languages including C MATLAB Java and Tcl Full instructions on how to use the 5 are provided in the relevant FUSE Developers Guide on the FUSE CD NT107 0272 Issue March 9 2005 www nallatech com 125 FPGA Configuration NALL ATECH The High Pe FPGA Solution 126 include dimesdl h contains the API functions Declare variables DWORD Statusl Status2 Status3 Status4 DIME HANDLE hBenONE LOCATE HANDLE hLocate if hLocate DIME_LocateCard d1USB mbt THEBENONE NULL dldrDEFAULT d1DEFAULT NULL Error Could not locate the BenONE PCI return 1 Exit the if hBenONE DIME OpenCard hLocate 1 dccOPEN DEFAULT NULL Error Could not open the BenONE PCI return 1 Exit the app Boot the clock FPGA device 0 on Module Owith the bit file BitfileC bit Statusl DIME_ConfigDevice hBenONE BitfileC bit 0 0 NULL 0 Boot the mai
260. s Toot xST Bus Signal Name Example File Settings Generate Bus Signal Name Example File cdc Batch Mode Argument Example File Settings Generate Batch Mode Argument Example File arg lt Previous Generate Core Select to generate the ILA core When Generate Core is selected the tool runs and produces the ICON core Then click on Close Button to exit the Core Generator Figure 93 Final ILA Settings www nallatech com NT107 0272 Issue March 9 2005 A NALLATECH XtremeDSP Development Kit IV User Guide The High Performance FPGA Solutions Company 20 3 3 Manually Instantiating the ICON and ILA Cores in your Design Once the cores have been created they should be inserted into the actual design you wish to monitor In this example this is done manually in the VHDL through component declaration and instantiation of the ICON and ILA components Details are provided in the following listing on page 170 NT107 0272 Issue March 9 2005 www nallatech com 169 Chipscope ILA Support High Performance FPGA Solutions Company Listing ledsnake vhd c Nallatech 1999 ledsnake c This applications snakes a running stream of lit LED Intended as a confidence tester library IEEE use IEEE std_logic_1164 all use IEEE std_logic_unsigned all entity ledsnake is port CLK in std logic RSTI in std logic LED out std log
261. s for Bank B Signal Name User FPGA XC4VSX35 10FF668 PIN No ZBTB D 0 Y22 ZBTB D I Y23 ZBTB D 2 AB23 ZBTB D 3 AA24 ZBTB_D lt 4 gt ZBTB D 5 AB22 ZBTB D 6 AF22 ZBTB D 7 AC23 ZBTB D 8 ACI9 ZBTB 0 lt 9 gt AB20 ZBTB 0 lt 10 gt AF20 ZBTB D II AC2I ZBTB D I2 AC20 ZBTB D 13 W20 ZBTB 0 lt 14 gt 21 ZBTB_D lt 15 gt AE21 Table 67 ZBT Data Signals Pinouts Bank B NT107 0272 Issue March 9 2005 www nallatech com 237 Pinout Information NALLATECH Signal Name User FPGA XC4VSX35 10FF668 PIN No ZBTB 0 lt 16 gt 19 ZBTB_D lt 17 gt Y20 ZBTB_D lt 18 gt 2 ZBTB 0 lt 19 gt 21 ZBTB_D lt 20 gt 19 ZBTB_D lt 21 gt AFI9 ZBTB D 22 AA20 ZBTB D 23 21 ZBTB 0 lt 24 gt V22 ZBTB_D lt 25 gt AC22 ZBTB_D lt 26 gt AA23 ZBTB_D lt 27 gt AD23 ZBTB_D lt 28 gt W22 ZBTB_D lt 29 gt AD22 ZBTB_D lt 30 gt AF23 ZBTB_D lt 31 gt AE23 Table 67 ZBT Data Signals Pinouts Bank B 24 8 Inter FPGA Clock Infrastructure Signals 24 8 1 Clock sources arriving at Clock FPGA Signal Name CLK FPGA 2V80 User FPGA XC4VSX35 Signal Description Pin No IOFF668 PIN No CLK_Op_Amp B6 GCLK6S N a External CLK source via Op_Amp CLK Op Ampl C6 GCLK7P N a Complement of External CLK source via Amp Osc CLK M6 N a LVTTL Clock Oscillator GEN CLKA K7 G
262. sed to control certain aspects of the selected module NT107 0272 Issue March 9 2005 www nallatech com 87 Board and System Level Monitoring Capabilities NALLATECH The High Pe FPGA Solution Example DWORD 1 65 DWORD MinAlert 0 DWORD ModuleNumber 0 Set the max and min alert levels degrees 1 degrees n MinAlert once you ve dealt with the alert line to the FPGA cleared n ModuleNumber if DIME ModuleControl hCard1 ModuleNumber dinfTEMPALERTMAX MaxAlert 0 printf Maximum FPGA Temperature set to if DIME ModuleControl hCard1 ModuleNumber dinfTEMPALERTMIN MinAlert 0 printf Minimum FPGA Temperature set to this code should be place in your temperature alert handler if DIME_ModuleControl hCard1 ModuleNumber dinfTEMPALERTCLEAR 0 0 printf The temperature alert line for module d has been and desire to clear the alert Figure 53 Setting Maximum and Minimum Temperature Alert Limits DIME_ModuleStatus Syntax DWORD DIME ModuleStatus DIME HANDLE handle DWORD ModuleNum DWORD CmdMode Arguments handle is a valid handle to a DIME carrier card ModuleNum is the module that is being addressed Note modules are numbered from 0 CmdMode This argument is used to specify what particular aspect of module status information is to be returned The table below gives details of the available co
263. skew at the FPGA destinations This is done by using clock nets of the same length between the on board clock drivers and the DIME II module slot DIME II System Clocks The BenADDA DIME II module can make use of three system clocks fed from the motherboard to the User FPGA These are called CLKA CLKB The clock signals are generated on the DIME II motherboard and routed into the module site where the BenADDA DIME II module is placed These clocks can be controlled by the user and are routed to Global Clock pins to provide maximum flexibility on the User FPGA However note that the functionality of these DIME II clocks is determined by the motherboard When the BenADDA DIME II module is fitted to the BenONE Kit Motherboard as in the XtremeDSP Development Kit IV configuration the available DIME II clocks are NT107 0272 Issue March 9 2005 www nallatech com 63 NALLATECH Clocks r MES oY available programmable oscillator on the BenONE Kit Motherboard CLKB available programmable oscillator on the BenONE Kit Motherboard CLKC connected to a socket to support a crystal oscillator Please note that no oscillator is supplied and this option on the BenONE Kit Motherboard allows users to fit a specific crystal Full details of the generation of these clock signals is shown in Clocking Configuration on page 65 For details on how the clocks are named see FUSE Naming Conventions on page xvi 10
264. t 20 www nallatech com NT107 0272 Issue March 9 2005 NALLATECH XtremeDSP Development Kit IV User Guide The High Performance FPGA Solutions Compan y 4 2 Hardware 4 2 1 Analog ADC Inputs The inputs to the ADC devices are connected via MCX connectors on the front of the module The standard shipped configuration exhibits 50Q single ended inputs each featuring a 3rd order anti aliasing filter with a 3dB point at 58MHz The AD6645 ADC inputs are connected to the AD8138 op amp which is connected directly to the MCX input The recommended maximum signal magnitude at the MCX input to attain best performance characteristics is 2V p p I V The Kit has five through hole MCX connectors that allow interfacing to and from the module All Analog Input and Output signals to the BenADDA DIME II module are conducted via four MCX connectors on top of the module The fifth MCX connector provides an input source for an external clock Figure 12 on page 21 outlines the positioning of these connectors ADEE External Clock DACI Analogue Input N ADCI Output Analogue Input Pei xA Output Figure 12 MCX Connectors Figure 12 on page 21 shows there are two Analog Input channels two Analog Output channels and one external clock source input Details on the DAC inputs and the external clock input are provided in DACs on page 29 Please note when the Kit is still in the blue board case the function of each MCX conn
265. t Address Data g 600000000 Road Data Certo zero Session Log console benone Sys Clock Set to 50 0 Bittiie Yirtex IV 4V3X35 Di uip BerdADDA IV Teata Exampler chipacope excample the Mallatech BenADBA TV Virtex4VY3X35 FF668 on the benone ledsnake bit t benone card card has been configured Figure 51 FUSE Probe showing Temp Sensor NT107 0272 Issue March 9 2005 www nallatech com Plug in 85 Board and System Level Monitoring Capabilities NALLATECH 2 Double click on the temperature sensor button in the right hand pane of the FUSE Probe Tool to launch the Temperature GUI 1 Get hanche Modde Select Stoo Reset Temperature Setting Maium FPGA 0 2 0 5 10 15 20 25 30 35 0 45 Click on the Start Mrexm FPGA Tem esanae sj Reading number button to start ecce Temptunae Diode FPGA Simply click the reading back ete tabs to switch Voliage Mee ve R x b t etween viewing information x 25 Moers 2 temperatures and voltages ave Modde Tengassue Num Figure 52 Temperature and Voltage Monitoring FUSE Software API Monitoring Functions Software functions through the FUSE API provide temperature
266. t Interface NALLATECH The High Performance FPGA Solutions Company 114 15 3 Firmware 15 3 1 Interface FPGA to User FPGA Interface Core The Interface to User FPGA Interface Core is a drop in IP core which can be incorporated into the User FPGA Application Design This core implements a mechanism which deals with the protocol to communicate over the Interface Communications Bus This abstracts the complexities of the protocol and provides a simplified user interface offering a memory mapped address space for registers peripherals and DMA channels for high speed data transfer A block diagram for the implementation of this core is shown in Figure 64 on page 114 User FPGA Interface Backend NALLATEC HET ser Bus Interface to User FPGA Core Comms Bus Figure 64 Implementation with PCI or USB to User FPGA Interface Core For full details of the Interface to User FPGA Interface Core please refer again to PCI to User FPGA Interface Application Note provided the FUSE CD at the location CD ROM Drive Application Notes NT302 0000 Spartan to Virtex Interface The necessary VHDL code and an EDIF file for the core are also provided on the CD Please note that this is a generic Application Note whether PCI or USB interfacing is used 15 3 2 Implementing the Communications Mechanism Instead of communicating over the Interface Comms bus using the Interface to User FPGA Interface Core a mech
267. t all times and that no contract for supply of goods involves loss of IPR by the company unless expressly offered as part of the contract by the company GOVERNING LAW This agreement and performance of both parties shall be governed by Scottish law NT107 0272 Issue March 9 2005 NT107 0272 Issue March 9 2005 NALLATECH e High Performance FPGA Solution Any disputes under any contract entered into by the company shall be settled in a court if the company s choice operating under Scottish law and the buyer agrees to attend any such proceedings action can be brought arising out of any contract more than 12 months after the completion of the contract INDEMNITY The buyer shall indemnify the company against all claims made against the company by a third party in respect of the goods supplied by the company SEVERABILITY If any part of these terms and conditions is found to be illegal void or unenforceable for any reason then such clause or Section shall be severable from the remaining clauses and Sections of these terms and conditions which shall remain in force NOTICES Any notice to be given hereunder shall be in writing and shall be deemed to have been duly given if sent or delivered to the party concerned at its address specified on the invoice or such other addresses as that party may from time to time notify in writing and shall be deemed to have been served if sent by post 48 hours after posting
268. t is capable of providing 1 6Amps 3 3V and therefore there is 800mA min available for the side bank FPGA I O The second FPS power supply D PSU D is used to power the Digital of the ADC and DACs and the corresponding I O of the main User FPGA Again this FPS is capable of 1 6Amps 3 3V which allows for dependent O The third FPS power supply A PSU A is used to power Vcaux of the Virtex 4 There is one PPS power supply C PSU_C used on the Kit hardware to provide the core voltage on 1 2V for the User FPGA on the BenADDA DIME II module The PPS can supply up to 15Amps but for the purpose of the Kit and due to limits of the external power supply the recommended max is 5 1 2V as described in the previous specifications When using the Kit in a PCI slot the limits that apply are the 15 rating of the PPS unit and the thermal limit of the Virtex 4 silicon but in practice the recommend max is 5 max when using the PCI slot There are several linear regulators supplying 3 3V and 2 5V power for the interface FPGA but these are dedicated to the interface and do not affect user designs NT107 0272 Issue March 9 2005 www nallatech com 99 Power Specifications NALLATECH The High Performance FPGA Solutions Comp any 100 Modular Programmable Power Supply PPS is possible to dynamically adjust the voltages applied to the module slot using the on board DC DC converters Each supply is capable of su
269. t of the User Guide provides details on how to use the Xilinx Impact Support Tool in conjunction with the XtremeDSP Development Kit IV NT107 0272 Issue March 9 2005 www nallatech com 153 NALLATECH erformance FPGA Solutions C 154 www nallatech com NT107 0272 Issue March 9 2005 NALLATECH XtremeDSP Development Kit IV User Guide Section 19 Impact Support In this section Support for the Xilinx Impact Tool How to Establish a Connection Program User FPGAs via a Download Cable 19 1 Introduction The Xilinx Impact tool can be used to configure the User FPGAs in the XtremeDSP Development Kit IV This section details how the Impact tool can be used with the Kit 19 2 Set up a Connection 19 2 1 Connect a JTAG Download Cable A download cable is required in order to connect to the general JTAG chain through which the User FPGAs are configured Supported cables are the Parallel Ill or Parallel IV cables from Xilinx which be connected to the two headers on the board One header supports flying lead connections from either pod and the other supports the faster ribbon Details of these headers are included on page 93 19 2 2 Open the Card to Enable Power Supplies In order to detect all the devices in the JTAG chain the module power supplies must be enabled The power supplies for the module are on when the power good LEDs for PSUB to D are green rather than red Please refer to page 98 for more details
270. t volue for C Sanche tio C Diterennator 2 m Design Method C In uU Figure 121 Simple Low Pass Filter Design FDATool The filter coefficients for the designed filter can be used in the actual MAC FIR block by using the xlfda_numerator function This function returns the numerator of the filter object stored in the Xilinx FDATool block shown in Figure 121 on page 201 Block Parameters Low Pass Filter ntap MAC FIR Filter mask FIR filter with n coefficients aus Obtaining the Parameters i Ue coefficients from the numerator LowPass FDATool Number of Bits per Coefficient 12 Binary Point for Coefficient 11 Number of Bits per Input Sample 12 Binary Point for Input Samples 8 Input Sample Period 1 x Figure 122 Obtaining the Coefficients from the Simulate the model by clicking the Start simulation Icon shown right At this point with out modifying the model you should be able to see the plot shown in Figure 123 on page 202 NT107 0272 Issue March 9 2005 www nallatech com 201 System Generator Support NALLATECH High Performance FPGA Solutions Comp any 202 DAR Figure 123 Scope Waveform 4 Double click on the Slider Gain Block an
271. ta www nallatech com 177 Chipscope ILA Support NALLATEC Y FPGA Solutions Company 178 www nallatech com NT107 0272 Issue March 9 2005 NALLATECH The High Performance FPGA Solutions Company Part IX Xilinx Embedded Developers Support This part of the User Guide provides details on how to use the Xilinx Embedded Developer s Support Tool in conjunction with the XtremeDSP Development Kit IV NT107 0272 Issue March 9 2005 www nallatech com 179 NALLATECH erformance FPGA Solutions C 180 www nallatech com NT107 0272 Issue March 9 2005 NALLATECH XtremeDSP Development Kit IV User Guide Section 21 Xilinx Embedded Developer s Kit EDK Support In this section Introduction Design Notes EDK Example 21 1 Introduction The Xilinx Embedded Developers Kit is a set of tools which allows designers to create designs for Xilinx FPGAs that make use of either the Microblaze soft processor core in the Virtex 4 silicon The EDK tools are not included in the Kit and the details provided here are provided to support users who have access to the EDK tools and wish to make use of them with the Kit 21 2 Design Notes 21 2 1 Resets The resets that can be controlled from the host interface are all active LOW which is important to consider when designing a system You can create a microprocessor design as a submodule in a top level design where the clock management and reset management are carr
272. tended to provide additional information and insight on the software code to allow for a greater understanding on building a host interface to your Kit designs 17 4 2 Source In this example there is source for both VHDL and for C The VHDL source files are provided on the XtremeDSP Development Kit IV CD in the location CD ROM Drive Examples host_interface_basic source C source files are provided the XtremeDSP Development Kit IV CD in the folder Drive Examples host_interface_basic CCodeTester 17 4 3 Implementation Apart from the source files a Xilinx ISE project has been included on the XtremeDSP Development Kit IV CD at the location CD ROM Drive Examples host_interface_basic ise host_interface or is installed to the location where you installed the Kit CD This project has been created in Xilinx ISE 6 31 UCF is also provided in the source folder that includes all pin LOC and timing constraints www nallatech com NT107 0272 Issue March 9 2005 A NALLATECH XtremeDSP Development Kit IV User Guide The High Performance FPGA Solutions Company In addition to this a Microsoft Visual Studio project and workspace are available The project files are in CD ROM Drive Examples host_interface_basic CCodeTester 17 44 Running the Example To help run the example a Microsoft Visual Studio project has already been compiled into both a debug and release executable Running either of these files N
273. that is supplying 2 5V to the system TA Pmax g 0 JA gt T T 0 xPuax where0 4 35 C W T 125 C max T4 25 125 25 35xPyay 5 2 857W Pmax loutuaxx Viv Ss 2 857 2 5 gt loutyAx 1 143A 13 2 1 Power Supply LEDs The feature section LEDs on page 53 provides details on the specific power supply LEDs on the card This information is repeated here for reference only DIME II Module Power Supply LEDs DIME II standard requires that a number of voltages be supplied to a DIME II module from the DIME II motherboard to which it is fitted In the case of the XtremeDSP Development Kit IV four power supplies provide power to the module For each of these power supplies a corresponding LED shows when each power supply is turned on These power supplies are termed PSUA to PSUD The actual voltage generated for each is given in Table 42 on page 101 Silk Screen Color State State Description State Initial power After card LED Voltage on state opened in FUSE Identifier Output D7 Red PSUA Off ov Off i e RED Off i e GREEN Green PSUA On 2 5V D8 Red PSUB Off ov Off i e RED On ie GREEN Green PSUB On 3 3V DI2 Red PSUC Off OV Off i e RED On i e GREEN Green PSUC On 1 2V DI3 Red PSUD Off OV Off i e RED On i e GREEN Green PSUD On 3 3V Table 42 DIME II Module Power Supply LED States Motherboard Main Power LEDs In addition t
274. the Xilinx ISE gt Accessories program group On startup you are presented with a selection of the operation mode as shown in Figure 78 on page 157 Operation Mode Selection What do you want to do first C Prepare Configuration Files C Load Configuration File cdf pdr Figure 78 Operation Mode Selection To configure devices in the general JTAG chain select Configure Devices Then click to continue Configure Devices C Slave Serial Mode SelectMAP Mode C Desktop Configuration Mode lt Back Cancel Hep Figure 79 Configure Devices Dialog NT107 0272 Issue March 9 2005 www nallatech com 157 Impact Support NALLATECH 158 Select Boundary Scan Mode as we are using JTAG to configure the devices the hardware Click on Next to continue Boundary Scan Mode Selection C Enter a Boundary Scan Chain lt Back Cancel Help Figure 80 Boundary Scan Mode Selection Select to automatically connect to and identify boundary scan chain Click to continue You will then see the scan of the JTAG devices running as shown in Figure 81 on page 158 Operation Status Executing command Figure 81 Scanning for Devices Once this scan completes five devices should be shown in the chain 3 untitled Configuration Mode iMPACT 0 Ele Edt View Mode Ogeraboss Output Help SRO 232 uro
275. tionally if the zero stuffing option is selected the input data must be one quarter of the reference clock frequency For example the maximum reference clock of 60MSPS with the PLL disabled and the zero stuffing option selected gives a maximum input data rate of 40MHz NT107 0272 Issue March 9 2005 www nallatech com 3l Sis NALLATECH The High Performance FPGA Solutions Comp any The internal PLL also deals with the phase relationship between the data and the reference clock This means that when PLL is enabled you do not need to use the RESET input to ensure correct alignment of clock and data If the PLL is disabled consult the Analog Devices AD9772A datasheet provided on the XtremeDSP Development Kit IV CD at the location CD ROM Drive Documentation Datasheets This provides more information on how the RESET input is used to ensure correct synchronization Table 9 on page 32 provides a summary of the DAC input data rates PLL Disabled PLL Enabled Zero stuffing ON Zero stuffing OFF Zero stuffing OFF Zero stuffing ON Input Data Rate 1 2 reference clock 1 4 reference clock Ix reference clock Ix reference clock Table 9 DAC Input Data Rates A PLL LOCKED signal from each AD9772A is connected to the FPGA see note PLL Clock Multiplier on page 31 on the BenADDA DIME II module This signal goes high to indicate the PLL has locked to the input reference clock If the P
276. tions in the Getting Started Guide supplied with your Kit for details on how to install the hardware into a PCI slot The Getting Started Guide is also available on the Kit CD in the following location lt CD ROM Drive gt Documentation Product Performing the Cosimulation The following steps describe how to run the MAC FIR example using the cosimulation flow v To perform the cosimulation use the following procedures l If the mac_fir_xtremedspkit_demo mdl model is not open open the model 2 Double click on the System Generator block Set the compilation target If the PCI connection is used select Hardware cosimulation gt XtremeDSP Development Kit gt PCI If the JTAG Parallel cable connection is used select Hardware cosimulation gt XtremeDSP Development Kit gt JTAG Set the part as XC4VSX35 10FF668 if using the XtremeDSP Development Kit IV Note the FPGA Clock Period setting 25ns in this case as this determines how fast the design is capable of running if using a free running clock The dialog box should be similar to that shown in Figure 129 on page 206 NT107 0272 Issue March 9 2005 www nallatech com 205 System Generator Support NALLATECH The High Performance FPGA Solutions Company System Generator sysgenqam16_dplr Note the part Xilinx System Generator Compilation Virtex2P xc2vp30 5ff1152 Target Directory Synthesis Tool Hardware Descript
277. to produce a low pass filter is carried out using the Filter Design and Analysis Tool FDATool The example shows how the MAC FIR example can be targeted to be run on the actual Kit hardware using the cosimulation flow Tool Requirements ISE 6 3i or later System Generator 6 3i or later 22 5 2 Please note that you will probably need to copy the MACFir example folder to a local folder that contains no spaces in the complete folder path i e C temp MACFir By default the installer places the XtremeDSP Development software and examples to C Program Files FUSE XtremeDSP Development Kit IV The space in Program Files causes an error in the generation of the cosimulation files you will get a popup stating that an error has occurred The examples should be run from a folder that has no spaces in the path to remove this problem Simulating the MAC FIR Cosimulation Example To simulate the MAC FIR Cosimulation example use the following procedures From the MATLAB console change the directory to the folder Exam plessystem generator examples MACFir If you have chosen to install the examples in the XtremeDSP Development Kit IV then this folder will be present where you chose to install the Kit software If you have chosen not to install these files they can be copied from the examples folder on the supplied Kit CD The following file is located in this directory mac fir xtremedspkit demo mdl Your working model Open mac fir x
278. ton for Interface Reset to reset the interface core i e reset the Interface FIFOs Uncheck FPGA to disable the reset to the main User FPGA Uncheck System Reset to disable the reset common to both FPGAs NT107 0272 Issue March 9 2005 www nallatech com 135 Feature Examples NALLATECH High Performance FPGA Solutions Company 3 You can then connect a suitable input signal as specified in Analog ADC Inputs on page 21 with the MCX inputs corresponding to the ADCs Also the DACs can be connected to a suitable display such as an Oscilloscope The LEDs will move through a count and the input signal is sent through to the output Listing adc_to_dac_hookup vhd Title adc_to_dac_hookup Project adc_to_dac_hookup File adc_to_dac_hookup vhd Author lt derekstark DELL2000AXP gt Company Nallatech Ltd Created 2003 11 12 Last update 2003 11 12 Platform DIME II Standard VHDL 87 Description Simple adc to dac hookup with a count being driven out the LEDs The design simply captures data from the ADCs registering it and then outputs this on the DACs with a slight conversion to change from 25 complement to offset binary Copyright c 2003 Revisions Date Version Author Description 2003 11 12 1 0 derekstarkCreated library IEEE use IEEE STD LOGIC 1164 all use IEEE SSTD LOGIC ARITH all use IEEESTD LOGIC UNS
279. tremedspkit demo mdl model from the MATLAB console This model represents a sim ple 32 tap MAC FIR with stimulus noise and sinewave sources as shown in Figure 120 on page 200 mac fir xtremedspkit demo File Edit Simulation Format Tools Help D GHS 5 Model Browser EN EE mac fir stremedspkit demo H System Generator 25 Low Pass Filter 2 LowPass 25 Slider Gain s System LowPass Generator ode45 Figure 120 Simulink Model fir xtremedspkit demo mdl www nallatech com NT107 0272 Issue March 9 2005 The High Performance FPGA Solutions Company XtremeDSP Development Kit IV User Guide The model shows two input sources a sinewave simulink source and a slider gain controlled noise source These sources are combined and fed through the MAC FIR to be displayed on the scope block along with the source signal The gateway blocks yellow allow for translation of the double to fix point numbers A FDATool block is also included Double click on the FDATool block to launch the tool The filter design chosen here is for illustrative purposes only Block Parameters LowPass git anan Ves bep DENSAN ASLLKH OR p r Magnitude Id Shushan Drect lom PIR de N Sectors Y Sabe Ves Responi 6 C r Enter a weigh
280. tshrink a w s Part No 100cm of Internal Identity MCX Straight NT501 1690 RG316 Cable BNC Crimp Crimp Plug Plug Gold Figure 22 Supplied Cable Assembly The MCX connectors are a push fit design therefore the MCX crimp plug on the supplied cable pushes into the MCX connector on the Kit hardware Please see the following section for details on the output configuration of the DACs 5 2 4 Output Configurations The AD9772A DAC supports can support two output configurations The following are supported as build options on the BenADDA DIME II module Single ended 500 output DC coupling using an op amp Kit default Differential outputs using termination resistors Custom build from Nallatech Please note the following specific information about the builds for different front end configurations is for reference only Attempted repair or alteration of the goods as supplied by Nallatech immediately invalidates the warranty Nallatech will not provide support upon alteration and cannot guarantee performance characteristics subsequently obtained 34 www nallatech com NT107 0272 Issue March 9 2005 NALLATECH XtremeDSP Development Kit IV User Guide The Hig h Performance FPGA Solutions Company Single Ended DC Coupling Using an Op Amp XtremeDSP Development Kit IV Default The op amp configuration is suitable for applications requiring DC coupling Figure 23 on page 35 illustrates the set up adopte
281. u to become acquainted with the Kit its features and the functionality it provides Before reading this manual it is recommended you read the Getting Started Guide supplied with the Kit for installation procedures The Kit User Guide provides details on the individual features available and how they are used as well as information on support for certain tools At the end of the User Guide you will find a reference section containing pinout information and a troubleshooting guide Symbols Used Throughout this guide there are symbols to draw attention to important information v The red arrow symbol indicates a set of procedures to follow such as installing software or setting up hardware The blue i symbol indicates useful or important information The red symbol indicates a warning which requires special attention User Guide Format The User Guide is divided into Sections which are grouped into Parts The parts divide the document as follows i Introduction Provides an introduction to the User Guide and the key aspects of the underlying hardware and software architecture XtremeDSP Development Kit IV Features This part provides details on the key features provided in the Kit such as the use of the ADC and DAC components System Level Design Provides information creating complete system uses Kit hardware and the FUSE API in a host application Configuration Discusses the different ways i
282. wnload cable such as the Parallel Ill or Parallel IV and analyze the design using the Chipscope Pro Analyzer In this example Chipscope Pro 6 3i has been used However similar procedures can be used for more recent versions of the tool 20 3 2 Creating the ICON and ILA Cores Chipscope Pro provides tool called Chipscope Pro Core Generator This can be launched from the start menu as shown in Figure 85 on page 164 Core To Generate Contorer ILA etagrated Logic Analyzer ILNATC integrated Logic Analyzer wih Agent Trace Core IBNOPE Bus Analyzer Chip Peripheral Bus IBA PLB integrated Bus Analyzer for Processor Local Bus Virhuat ineutiOuteut Core Agilent Trace Core 7 Figure 85 Chipscope Pro Core Generator 164 www nallatech com NT107 0272 Issue March 9 2005 NALLATEC The High Performance FPGA Solutions Company XtremeDSP Development Kit IV User Guide Generate the ICON Core This first component to generate is the ICON Integrated Controller component Select it and click Next ChipScope Pro Core Generator Design Hes output acon ean Device Settings Device Fami ICON Parameters Number of Central Ports 1 Select the output netlist folder the sake of At the example set it to the Unable Unosed Boundary Scan Port si nec same locatio
283. xample v To simulate the QAM Example use the following procedures l From the MATLAB console change the directory to the folder ples system_generator_examples QAM If you have chosen to install the examples in the XtremeDSP Development Kit IV then this folder will be present where you chose to install the Kit software If you have chosen not to install these files they can be copied from the examples folder on the supplied Kit CD The following file is located in this directory www nallatech com NT107 0272 Issue March 9 2005 NALLATEC XtremeDSP Development Kit IV User Guide The High Performance FPGA Solutions Company Sysgenqaml6 dplr mdl Your working model 2 Open sysgenqaml6 dplr mdl model from the MATLAB console This design implements an equalized 16 demodulator for use in a software defined radio The receiver architecture provides sub systems that demonstrate adaptive channel equalization and carrier tracking on a random QAM data source gat Format Tools Heb D SUs e amp KJ 16 QAM Demodulator for Software Defined Radio Model Brome 3715 w ES bj Adaptive Equekzer Cane Recovery db CHANNEL da CHANNEL OUT By Dermed Corntete bj Doppler FSE Ou 3 QAM 16 See G Figure 111 16 QAM Demodulator Example In addition to the System Generator demodulator components the model includes Simulink subsyst

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