Renesas R0K5562T0S000BE Datasheet
Contents
1. enum RiicStatus t data1 enum RiicBusStatus t data2 Return value None Notes See section 4 2 3 Enumerations for details on the arguments R01ANO0637EJ01 Sep 27 2011 00 Rev 1 00 Page 12 of 29 34 NE SAS RX62T Group Communication with EEPROM Using the Renesas IC Bus Module RIIC 4 4 Flowchart This section presents the flowcharts for the functions in this sample program main C oO oO L_ CpuC CPU initialization lIC_Create IIC initialization SampleEepromWrite Example of EEPROM write processing IICAckPolling Acknowledge polling SampleEepromRead Example of EEPROM read processing L1 LJ fil L_ estroy IIC termination processing Figure 7 Main Processing CpuCreate Clock settings ICLK 100 MHz PCLK 50 MHz EXTAL 12 5 MHz CpulntCreate CPU interrupt settings IICPortCreate IIC port settings Clear the module stop bit Clears the module stop bit End Figure 8 CPU Initialization CpulntCreate Sets the interrupt event priority to 4 IPR settings ICEEIO ICRXIO ICTXIO and ICTEIO Clear the IR flag Clears the interrupt request flag IEN settings Enables interrupts Note however that it is also necessary to set the interrupts enabled disabled state with the ICIER register End Figure 9 CPU Interrupt Settings RO1AN0637EJ0100 Rev 1 00 Page 13 of 29 Sep 27 2011 ztENESAS2. End Figure 24 NACK Detection Interrupt IIC RXI Int What is the internal mode EEPROM read processing EEPROM write processing Other state IIC RXI IntEepRead IIC Error IIC Error End Figure 25 Receive Data Full Interrupt R01ANO0637EJ0100 Rev 1 00 Page 22 of 29 Sep 27 2011 34 NE SAS RX62T Group Communication with EEPROM Using the Renesas I C Bus Module RIIC IIC RXI IntEepRead Interrupt after slave No address reception Is remaining data to read count 2 or less Set SCL to be held low after the 9th clock generated Is remaining data to read Is remaining data to read count 3 or less Yes Set SCL to be held low after the 9th clock generated Is remaining data to read count 2 or less Yes count 1 or less Set up NACK transmission when the next data is received I Dummy ICDRR read Set up NACK transmission when the next data is received Is remaining data to read count 1 or less Yes No v Clear ICSR2 STOP Read out the receive data Prepare to generate a stop condition Read the last receive data and generate a stop condition Decrement read counter Clear SCL to be held low afte
3. RX62T Group Communication with EEPROM Using the Renesas IC Bus Module RIIC IICPortCreate Set the data direction register Sets the data direction register to the input direction Set the input buffer control Enables the input buffer register End Figure 10 IC Port Settings SampleEepromWrite Transmit data settings Sets up the sample transmit data 0x00 0x01 0x02 Set the EEPROM memory address Sets the EEPROM write address 0x0000 Sets up the argument data for IIC_EepWrite Set up the IIC EepWrite EEPROM slave address memory address length memory address argument buffer storage buffer pointer transmit data count and transmit data storage buffer pointer IIC EepWrite Starts the write to EEPROM Waits for the completion of data transmission to EEPROM Mo Has IIC communication completed Yes p dme IIC_GetStatus Waits for the IIC bus free state No Yes End Figure 11 Sample EEPROM Write Processing R01ANO0637EJ0100 Rev 1 00 Page 14 of 29 Sep 27 2011 34 NE SAS RX62T Group Communication with EEPROM Using the Renesas IC Bus Module RIIC SampleEepromRead Clear the receive data buffer Clears the receive data buffer Set the EEPROM memory address Sets the address data for reading from EEPROM 0x0000 Sets up the argument data for IIC RandomRead Set up the IIC RandomRead EEPROM slave address
4. memory address length memory address argument buffer storage buffer pointer receive data count and receive data storage buffer 4 pointer Starts the read from EEPROM IIC RandomRead a IIC GetStatus Waits for the completion of data reception from EEPROM Has IIC communication completed x D o IIC GetStatus Waits for the IIC bus free state Yes End Figure 12 Sample EEPROM Read Processing RO1AN0637EJ0100 Rev 1 00 Page 15 of 29 Sep 27 2011 34 NE SAS RX62T Group Communication with EEPROM Using the Renesas I C Bus Module RIIC IICAckPolling Set the EEPROM memory address Set up the IIC EepWrite argument buffer N No IIC EepWrite Has IIC communication completed Sind Yes NACK response Yes Wait for the interval required for the next acknowledge polling operation rd i No Y ACK response No Have the specified number of iterations completed Yes End Sets the EEPROM write address 0x0000 Sets up the argument data for IIC_EepWrite EEPROM slave address Starts acknowledge polling Waits for IIC communication to complete Iterates acknowledge polling either until an ACK response is received or until the specified iteration count completes During each iteration the function waits for the interval specified in the arg
5. R01ANO0637EJ0100 Rev 1 00 Sep 27 2011 Page 11 of 29 34 NE SAS RX62T Group Communication with EEPROM Using the Renesas I C Bus Module RIIC IIC RandomRead Overview Starts a read from the EEPROM Header r apn iic h Declaration int8 t lIC RandomRead lIC API T Description This function reads data from the EEPROM using both master transmission and master reception If the I C bus is busy or the RIIC is already communicating it does not start a master transmission Arguments IC API T data1 Return value If communication starts up normally RIIC OK If the I C bus is busy RIIC BUS BUSY If the RIIC module is communicating RIIC MODE ERROR If the argument value is illegal RIIC PRM ERROR See section 4 2 1 Structures for details on the argument IIC API T data1 See section 4 2 3 Enumerations for details on the return value The argument is recognized as illegal if both the memory address counter and the data counter are 0 Bit 0 in the slave address SlvAdr which is a member of the argument structure must be set to 0 IIC GetStatus Overview Acquires the status of the RIIC module Header Declaration r apn iic h void IIC_GetStatus enum RiicStatus t enum RiicBusStatus t Description This function stores the IIC status in the area indicated by the first argument It also stores the IIC bus state in the area indicated by the second argument Arguments
6. 0 Page 26 of 29 Sep 27 2011 34 NE SAS RX62T Group Communication with EEPROM Using the Renesas IC Bus Module RIIC IIC Error Figure 34 Error Handling R01ANO0637EJ0100 Rev 1 00 Page 27 of 29 Sep 27 2011 34 NE SAS RX62T Group Communication with EEPROM Using the Renesas IC Bus Module RIIC 5 Reference Documents Hardware Manual RX62T Group User s Manual Hardware Rev 1 10 The latest version can be downloaded from the Renesas Electronics Web site Software Manual RX Family User s Manual Software Rev 1 00 The latest version can be downloaded from the Renesas Electronics Web site Development Environment Manual Rev 1 01 RX Family C C Compiler Package User s Manual The latest version can be downloaded from the Renesas Electronics Web site Technical Updates The latest information can be downloaded from the Renesas Electronics Web site RO1AN0637EJ0100 Rev 1 00 Page 28 of 29 Sep 27 2011 34 NE SAS RX62T Group Website and Support Renesas Electronics Website http www renesas com Inquiries http www renesas com inquiry All trademarks and registered trademarks are the property of their respective owners Communication with EEPROM Using the Renesas I C Bus Module RIIC R01ANO0637EJ0100 Rev 1 00 Sep 27 2011 3 NE SAS Page 29 of 29 Revision Record Description Rev Date Page Summary 1 00 Sep 27 11 First edition issued A 1 Gener
7. Create Overview Initializes the RIIC module Header r apn iic h Declaration void IIC_Create void Description Performs the following settings e Transfer speed setting 400 kbps e Interrupt settings e Timeout settings Arguments None Return value None Notes IIC Destroy Overview Stops the RIIC module Header r apn iic h Declaration void IIC_Destroy void Description Arguments Stops the RIIC module and clears all the RIIC module related registers None Return value None Notes If this function is called during a communication operation it forcibly stops the RIIC module IIC EepWrite Overview Starts a write to the EEPROM Header r apn iic h Declaration int8 tlIC EepWrite llC API T Description Uses master transmission to write to the EEPROM If the I C bus is busy or if the RIIC module is in the communication in progress state it does not start master transmission Arguments IC API T data1 Return value If communication starts up normally RIIC OK If the I C bus is busy RIIC BUS BUSY If the RIIC module is communicating RIIC MODE ERROR See section 4 2 1 Structures for details on the argument IIC API T data1 See section 4 2 3 Enumerations for details on the return value Bit 0 in the slave address SlvAdr which is a member of the argument structure must be set to 0
8. In a similar way the states of pins in a product that is reset by an on chip power on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited The reserved addresses are provided for the possible future expansion of functions Do not access these addresses the correct operation of LSI is not guaranteed if they are accessed Clock Signals After applying a reset only release the reset line after the operating clock signal has become stable When switching the clock signal during program execution wait until the target clock signal has stabilized When the clock signal is generated with an external resonator or from an external oscillator during a reset ensure that the reset line is only released after full stabilization of the clock signal Moreover when switching to a clock signal produced with an external resonator or by an external oscillator while program execution is in progress wait until the target clock signal is stable Differences between Products Before changing from one product to another i e to one with a different type number confirm that the change will not lead to problems The characteristics of MPU MCU in the same group but having different type numbers may differ because of the differences in internal memory capacity and la
9. RENESAS APPLICATION NOTE RX62T Group Communication with EEPROM E Using the Renesas IC Bus Module RIIC Sep 27 2011 Introduction This application note presents a sample program that communicates with an EEPROM in single master mode using the Renesas MCU IC bus interface module Target Device RX62T Group Other members of the RX Family that have the same I O registers peripheral unit control registers as the RX62T Group products can also use the code from this application note Note however that since certain aspects of the functions used may be changed in other devices due to function additions or other differences the documentation for the device used must be checked carefully before using this code When using this code in an end product or other application its operation must be tested and evaluated thoroughly Contents Specifications osses 2 2 Operation Confirmation Environment essent enne nennt nnne enne 3 CEN SCC 4 Ah OPW ENG EPRL 6 5 Reference DOCUMENIS cccccceeeeceeeeeeeeeeeeeeeeeeeeeeeeeeeeeeaeeeseeaaeaeeseaaeeescaaeaesecaaeseseeaaeeeseeseneneeseneees 28 RO1AN0637EJ0100 Rev 1 00 Page 1 of 29 Sep 27 2011 34 NE SAS RX62T Group Communication with EEPROM Using the Renesas IC Bus Module RIIC 1 Specifications This sample program comm
10. ROM Using the Renesas IC Bus Module RIIC Table 10 IIC Bus Status enum RiicBusStatus t Defined Name Description RIIC BUS STATUS FREE IIC bus free HIIC BUS STATUS BBSY IIC bus busy Table 11 Internal Modes enum RiiclnternalMode t Defined Name Description IIC MODE IDLE Idle mode The internal mode transitions to idle mode on initialization by IC Create or when a stop condition is detected IIC MODE EEP READ EEPROM read mode The internal mode transitions to this mode at the start of communication due to IIC_RandomRead IIC MODE EEP WRITE EEPROM write mode The internal mode transitions to this mode at the start of communication due to IIC_EepWrite Table 12 IIC EepWrite and IIC_RandomRead Return Value enum RiicEepFnc t Defined Name Description RIIC OK This value is returned when communication starts up normally RIIC BUS BUSY This value is returned when the lC bus is busy RIIC MODE ERROR This value is returned when the RIIC module has a communication operation in progress RIIC PRM ERROR This value is returned when an illegal argument value is passed Only the function IIC_RandomRead uses this value RO1AN0637EJ0100 Rev 1 00 Page 10 of 29 Sep 27 2011 34 NE SAS RX62T Group Communication with EEPROM Using the Renesas I C Bus Module RIIC 4 3 Function Specifications This section presents the specifications of the sample code functions that control the RIIC module IIC
11. RWData Pointer for Data buffer typedef struct str IIC API T IIC API T Figure 5 Structure Uses as an Argument to IIC EepWrite and IIC RandomRead Table6 Members of the Structure IIC API T Structure Member Range of Values Description SlvAdr 00h to FEh Slave address Since the low order bit is the R W bit it should always be set to 0 PreCnt 00h to FFh Memory address counter This is always set to 2 in this sample program pPreData Memory address storage buffer pointer On write The address in EEPROM to write data to write destination On read The address in EEPROM to read data from read Source RWOnt 0000 0000h to Data counter FFFF FFFFh On write Number of data items to write to EEPROM On read Number of data items to read from EEPROM pRWData Data storage buffer pointer On write Storage source for data to write to EEPROM On read Storage destination for data read from EEPROM RO1AN0637EJ0100 Rev 1 00 Page 7 of 29 Sep 27 2011 34 NE SAS RX62T Group 4 2 2 Functions Communication with EEPROM Using the Renesas I C Bus Module RIIC Tables 7 and 8 list the functions in this sample program Table7 Functions in the File main c Function uint8 t trm buff 256 Description Transmit data buffer uint8 trcv buff 256 Receive data buffer uint8 t trm eeprom adr 2 EEPROM slave address storage buffer for write uint8 t rcv eeprom adr 2 IIC API T iic buff
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13. TATUS IDLE The idle state The status transitions to this state after initialization in the function IIC Create The status also transitions to this state after either an EEPROM write or an EEPROM read completes normally after a stop condition is detected RIIC STATUS ON COMMUNICATION Communication in progress The status transitions to this state when communication is initiated by either IIC_EepWrite or IIC_RandomRead HIC STATUS NACK NACK received The status transitions to this state when a NACK is received RIIC STATUS FAILED Communication failure The status transitions to this state when a stop condition is detected before either an EEPROM write or an EEPROM read completes In this sample program since a stop condition is generated on either a timeout or an arbitration lost the status will transition to this state on either of those events as well After reset is cleared Communication start niin Idle state NACK received NACK received Start of communication n gt Communication 1 in progress Normal completion Communication start of communication Stop condition abnormality detected Communication failure Initialization IIC_Create Start of communication Either IIC EepWrite or IIC_RandomRead Figure 6 IIC Status State Transition Diagram RO1AN0637EJ0100 Rev 1 00 Page 9 of 29 Sep 27 2011 ztENESAS RX62T Group Communication with EEP
14. al Precautions in the Handling of MPU MCU Products The following usage notes are applicable to all MPU MCU products from Renesas For detailed usage notes on the products covered by this manual refer to the relevant sections of the manual If the descriptions under General Precautions in the Handling of MPU MCU Products and in the body of the manual differ from each other the description in the body of the manual takes precedence Handling of Unused Pins Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual The input pins of CMOS products are generally in the high impedance state In operation with an unused pin in the open circuit state extra electromagnetic noise is induced in the vicinity of LSI an associated shoot through current flows internally and malfunctions occur due to the false recognition of the pin state as an input signal become possible Unused pins should be handled as described under Handling of Unused Pins in the manual Processing at Power on The state of the product is undefined at the moment when power is supplied The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied In a finished product where the reset signal is applied to the external reset pin the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed
15. ation with EEPROM Using the Renesas l C Bus Module RIIC Tables 4 and 5 list the functions in this sample program The functions that are not in bold are static functions Table4 Functions in File main c Function Name Operation Notes main Main processing Figure 7 SampleEepromWrite EEPROM write processing example Figure 11 SampleEepromRead EEPROM read processing example Figure 12 IICAckPolling Acknowledge polling Figure 13 CpuCreate CPU initialization Figure 8 CpulntCreate CPU interrupt setting Figure 9 IICPortCreate IIC port settings Figure 10 Table5 Functions in File iic c Function Name Operation Notes lIC Create IIC initialization Figure 14 IIC Destroy IIC termination processing Figure 15 lIC EepWrite EEPROM write start processing Figure 16 IIC RandomRead EEPROM read start processing Figure 17 lIC GetStatus IIC status check Figure 18 lIC EEI Int Communication error or event interrupt Figure 19 IIC EEI IntTimeOut Timeout detection interrupt Figure 20 Called from within IIC EEI Int IIC EEI IntAL Arbitration lost detected interrupt Figure 21 Called from within IIC EEI Int IIC EEI IntSP Stop condition detected interrupt Figure 22 Called from within IIC EEI Int IIC EEI IntST Start condition detected interrupt Figure 23 Called from within IIC EEI Int IIC EEI IntNack NACK detected interrupt Figure 24 Called from within IIC EEI Int lIC RXI Int Receive data full int
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17. de and the counter Generates a start condition Figure 17 EEPROM Read Start Processing R01ANO0637EJ0100 Rev 1 00 Sep 27 2011 34 NE SAS Page 18 of 29 RX62T Group Communication with EEPROM Using the Renesas I C Bus Module RIIC IIC GetStatus Check the IIC status Check the IIC bus state Stores the IIC status in the buffer indicated by the argument Stores the IIC bus state bus busy or bus free in the buffer indicated by the argument Figure 18 IIC State Verification Processing IC EEI Int No Timeout interrupt handling Yes CT eere T Arbitration lost interrupt No handling Yes T rem T Enables the timeout detection interrupt and furthermore if a timeout detection interrupt has occurred handles the timeout detection interrupt Enables the arbitration lost interrupt and furthermore if an arbitration lost interrupt has occurred handles the arbitration lost interrupt No Stop condition detected interrupt handling Yes CT eene T Enables the stop condition detection interrupt and furthermore if a stop condition detection interrupt has occurred handles the stop condition detection interrupt ACK detected interrupt Ne handling Yes CT eee naar T Enables the NACK detection interrupt and furthermore if a NACK detection interrupt has occurred handles the NACK detection
18. e indicates the address for the write operation in EEPROM After the transmission of all the data has completed the RIIC module issues a stop condition P and releases the bus Note that the write address in memory used in this application note is 0000h Figure 2 shows an example of the signals used when writing the EEPROM A A A A C C c c S12345678k12345678K12345678K12345678k12 78 SCL Stat Slave address s 1st Memory 2nd Memory A Write Data A Write Data amp Stop A6h K address K address K K n x Figure2 Signals when Writing to EEPROM 3 2 Reading from EEPROM A compound format consisting of master transmission and master reception is used for reading data from EEPROM First the RIIC module issues a start condition S and then it transmits the EEPROM slave address and then a two byte 2 x 8 bits memory address At this time the RIIC module sends 0 as the R W bit in the EEPROM slave address transmission master transmission After that it issues a restart condition Sr and sends the EEPROM slave address again At this time it transmits 1 as the R W bit in the transmission to the EEPROM master reception After the EEPROM slave address has been sent the data is read out from the EEPROM by the generation of the next clock cycle During the read operation the RIIC module transmits an ACK each time it receives a single byte For the last data however it returns a NACK After that it generates a stop condition P Note t
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20. errupt Figure 25 IIC RXI IntEepRead EEPROM read processing master reception section Figure 26 Called from within IIC RXI Int lIC TXI Int Transmit data empty interrupt Figure 27 IIC TXI IntEepWrite EEPROM write processing Figure 28 Called from within IIC TXI Int IIC TXI IntEepRead EEPROM read processing master transmission section Figure 29 Called from within IIC TXI Int lIC TEI Int Transmission complete interrupt Figure 30 IIC TEI IntEepWrite Transmission end processing used after an EEPROM write Figure 31 Called from within IIC TEI Int IIC TEI IntEepRead Transmission end processing used after an EEPROM read Figure 32 Called from within IIC TEI Int IIC GenCIkSP Stop condition generation used when an error occurs Figure 33 Called from within IIC EEI IntTimeOut and IIC EEI IntAL lIC Error Error handling Figure 34 R01ANO0637EJ0100 Rev 1 00 Page 6 of 29 Sep 27 2011 34 NE SAS RX62T Group Communication with EEPROM Using the Renesas IC Bus Module RIIC 4 2 Variables 4 2 1 Structures Figure 5 shows the structure used as the argument to the functions IIC EepWrite and IIC RandomRead Also table 6 lists the members of this structure struct str IIC API T uint8 t SlvAdr Slave Address Don t set bitO It s a Read Write bit uintl16 t PreCnt Number of Predata uint8 t pPreData Pointer for PreData Memory Addr of EEPROM uint32 t RWCnt Number of Data uint8 t p
21. et Enable timeouts Enables timeouts N Yes IIC Error Even though an internal reset was performed SCL was set high while another device was holding it low d Clears MST TRS protection and sets up master Set up master mode dan P _ transmission mode No i Yes Loop Cnt 0 cnt lt 10 cnt N Yes Processing when the remote device is holding SDA low Generate 1 clock cycle One possibility is that a bit displacement occurred between the RIIC module and the remote device No In that case it may be possible to release SCL by generating a few clock cycles Has the one clock cycle completed No Use the ICCR1 CLO bit and generate one clock cycle at a time Each time check whether SDA is high or nine iterations have been performed Yes Did a timeout occur Have 9 clock Yes cycles been generated and is SDA low IIC Error a No Is the bus busy If the bus is busy generates a stop condition Yes In all other cases performs an internal reset and switches T from master transmission mode to slave reception mode idle IIC internal reset Generate a stop condition mode Enable MST TRS protection Enables MST TRS protection Set up timeout operation Generates timeouts when SCL is high i End Figure 33 Stop Condition Generation Processing when an Abnormal State Occurs R01AN0637EJ0100 Rev 1 0
22. ev 1 00 Page 24 of 29 Sep 27 2011 3 NE SAS RX62T Group Communication with EEPROM Using the Renesas IC Bus Module RIIC IIC TEI Int What is the internal mode EEPROM write processing EEPROM read processing Other state IIC TEI IntEepWrite IIC TEI IntEepRead IIC Error End Figure 30 Transmission Complete Interrupt IIC_TEI_IntEepWrite Disable the transmission complete interrupt complete interrupt Clear ICSR2 STOP Clear ICSR2 STOP Generate a stop condition Generate a stop condition Figure 31 Transmission Complete Processing after EEPROM Write Processing IIC TEI IntEepRead Clear ICSR2 START Clear ICSR2 START Enable start condition detection Enable start condition interrupt detection interrupt Disable the transmission Disable the transmission complete interrupt complete interrupt Generate a restart condition Generate a restart condition Figure 32 Transmission Complete Processing after EEPROM Read Processing RO1AN0637EJ0100 Rev 1 00 Page 25 of 29 Sep 27 2011 ztENESAS RX62T Group Communication with EEPROM Using the Renesas IC Bus Module RIIC IIC_GenClkSP Stops output to SCL and SDA and resets the Internal reset _ internal state Set up timeout operation Generates timeouts on SCL high or SCL low Waits for the SCL and SDA release times due pane ees tothe internal res
23. hat the memory address read by this sample program is 0000h Figure 3 shows an example of the signals used when reading the EEPROM A A A Cc Cc 12345678 12345678k 1234 678KS 12345 RT VILLA UU UT MUUUUU TUL UU Statt Slave address 1st Memory 2nd Memory A Re Slave address N Stop A6h K address K address x Start A7h x Read Data n K Master transmission Master Reception Figure3 Signals when Reading from EEPROM R01ANO0637EJ0100 Rev 1 00 Page 4 of 29 Sep 27 2011 34 NE SAS RX62T Group Communication with EEPROM Using the Renesas IC Bus Module RIIC 3 3 Acknowledge Polling Acknowledge polling is used as the method for determining whether or not the EEPROM is in the write in progress state To perform acknowledge polling the sample program issues a start condition and then sends the EEPROM slave address and then a stop condition At this time if the EEPROM is writing it will return a 1 on the ACK clock NACK Inversely if the write has completed it will return 0 ACK This allows the sample program to determine whether or not a write is in progress Figure 4 shows the acknowledge polling signals S 12 34 5 6 7 8 K P SCL SDA IL JI Start Slave address ACK Stop A6h NACK Figure 4 Acknowledge Polling Signals RO1AN0637EJ0100 Rev 1 00 Page 5 of 29 Sep 27 2011 34 NE SAS RX62T Group 4 Software 4 1 Functions Communic
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25. interrupt No Start condition detected interrupt handling Yes D eem Enables the start condition detection interrupt and furthermore if a start condition detection interrupt has occurred handles the start condition detection interrupt End Figure 19 Communication Error and Event Interrupts R01AN0637EJ0100 Rev 1 00 Sep 27 2011 34 NE SAS Page 19 of 29 RX62T Group Communication with EEPROM Using the Renesas IC Bus Module RIIC IIC EEI IntTimeOut E IIC GenCIkSP St pconaiti n generation processing usea when J an abnormality occurs Figure 20 Timeout Detection Interrupt IIC EEI IntAL IIC GenCIkSP St p conaiti n generation processing usea when an abnormality occurs Figure 21 Arbitration Lost Detection Interrupt RO1AN0637EJ0100 Rev 1 00 Page 20 of 29 Sep 27 2011 34 NE SAS RX62T Group Communication with EEPROM Using the Renesas IC Bus Module RIIC Clear ICSR2 NACKF Clear ICSR2 STOP Clear NACKF here when NACK detected Clear the STOP flag Interrupt settings Enable the timeout interrupt Enable the arbitration lost interrupt Disable the start condition detection interrupt Interrupt settings Enable the stop condition detection interrupt Enable the NACK received interrupt Enable the receive data full interrupt Disable the transmission complete interrup
26. iption Catalog number R1EX24512ASASOA Capacity 512 K 64 kword x 8 bit Slave address Slave address A6h Bit 0 is the R W bit Bits 1 and 2 depend on the AO and A1 pins respectively e Pin AO High e Pin A1 High Write protection Always released e WP pin Low 2 Operation Confirmation Environment Table 3 lists the environment used for confirming the operation of this application example Table 3 Operation Confirmation Environment Item Description Device RX62T R5F562TAADFP Board Renesas Starter Kit ROK5562TOSOOOBE Power supply voltage 5 0 V Supplied from E1 Input clock 12 5 MHz ICLK 100 MHz PCLK 50 MHz Operating temperature Room temperature HEW Version 4 09 00 007 Toolchain RX Standard Toolchain V 1 0 2 0 Debugger Emulator E1 emulator Debugger component RX E1 E20 SYSTEM V 1 01 00 RO1AN0637EJ0100 Rev 1 00 Page 3 of 29 Sep 27 2011 ztENESAS RX62T Group Communication with EEPROM Using the Renesas IC Bus Module RIIC 3 Operation 3 1 Writing to the EEPROM This sample program uses master transmission for writing to an external EEPROM device The RIIC module issues a start condition S and then sends the EEPROM s slave address Since the eighth bit at this time is the R W bit a 0 must be sent at write time master transmission After that the memory address is sent as two 8 bit bytes and then the data to be written is sent to the EEPROM in order The 2 byte memory address transmitted at this tim
27. p 27 2011 34 NE SAS Page 17 of 29 RX62T Group Communication with EEPROM Using the Renesas l C Bus Module RIIC IIC EepWrite Is this device communicating Yes No Store the argument in the IIC buffer No Is the bus free Yes Set internal RAM mode and the counter Generate a start condition return RIIC OK Figure 16 IIC RandomRead Is this device communicating Yes No Store the argument in the IIC buffer No Is the argument legal Yes No Is the bus free Yes Set internal RAM to internal mode and set the counter Generate a start condition return RIIC OK return RIIC MODE ERROR return RIIC BUS BUSY return RIIC MODE ERROR return RIIC PRM ERROR return RIIC BUS BUSY Checks the internal mode Cancels the write if a communication operation is in progress Stores the argument in the IIC buffer Checks the IIC bus state Cancels the write if the bus is busy Sets up internal RAM mode Sets the internal mode and the counter Generates a start condition EEPROM Write Start Processing Checks the internal mode Cancels the read if a communication operation is in progress Stores the argument in the IIC buffer Checks the argument value Cancels the read if the value is illegal Checks the IIC bus state Cancels the read if the bus is busy Sets up internal RAM mode Sets the internal mo
28. prm 2 EEPROM slave address storage buffer for read Structure used as the argument to the functions IIC_EepWrite and IIC_RandomRead Table 8 Functions in the File iic c Function static IIC_API_T iic buff Description Structure used as the argument to the functions IIC_EepWrite and IIC_RandomRead Used by both IIC_EepWrite and IIC RandomRead static int8 tiic mode Internal mode static int8 tiic status static uint32 tiic trm cnt static uint32 tiic rcv cnt R01ANO0637EJ0100 Rev 1 00 Sep 27 2011 IIC status Internal IIC transmit counter Internal IIC receive counter Page 8 of 29 34 NE SAS RX62T Group Communication with EEPROM Using the Renesas IC Bus Module RIIC 4 2 3 Enumerations The IIC status the IC bus status the internal mode and the return value from the functions IIC EepWrite and IIC RandomRead are all declared as enumerations The IC status values are listed in table 9 and their state transition diagram are shown in figure 6 Also table 10 lists the IIC bus status values table 11 lists the internal modes and table 12 lists the return values of the functions IIC EepWrite and IIC RandomRead The IIC status is stored at the address given by its first argument when the function IIC GetStatus is called The internal mode is only used in the IIC related functions in this sample program Table9 IIC Status Values enum RiicStatus t Defined Name Description RHIIC S
29. r the 9th clock generated v Decrement read counter Increment internal counter en Figure 26 EEPROM Read Processing Master Reception Section RO1AN0637EJ0100 Rev 1 00 Sep 27 2011 ztENESAS Page 23 of 29 RX62T Group Communication with EEPROM Using the Renesas IC Bus Module RIIC IIC TXI Int What is the internal mode EEPROM write processing EEPROM read processing Other state IIC TXI IntEepWrite IIC TXI IntEepRead IIC Error E End Figure 27 Transmit Data Empty Interrupt IIC TXI IntEepWrite Increment internal counter Slave address transmission This counter counts the number of transmitted __ data items Yes Memory address transmission Transmit the slave address n No Write data transmission Transmit the memory Enable the transmission address complete interrupt Transmit the data re Figure 28 EEPROM Write Processing IIC TXI IntEepRead Increment internal counter Slave address transmission This counter counts the number of transmitted data items Yes Memory address transmission Transmit the slave address Enable the transmission Transmit the memory e complete interrupt aqaress e Figure 29 EEPROM Read Processing Master Transmission Section R01AN0637EJ0100 R
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31. t Enable the transmitted empty interrupt What is the internal mode EEPROM write processing EEPROM read processing Idle state Other state Is the unsent bis s the not received No data empty data empty Yes Yes No se nae en Set the IIC status to Set the IIC status to communication failure communication failure NACK received Set the IIC status to idle state v IIC Error E Yes Set the IIC status to idle state Set the internal mode to idle Clear the internal counter ii Figure 22 Stop Condition Detection Interrupt IIC EEI IntST Clear ICSR2 START Clear the start condition detected flag Disable the start condition Disable the start condition detection detection interrupt interrupt This transmits the EEPROM slave address Transmit the EEPROM slave address Here bit 8 in the transmitted data must be set to 1 master reception End Figure 23 Start Condition Detected Interrupt RO1AN0637EJ0100 Rev 1 00 Page 21 of 29 Sep 27 2011 34 N SAS RX62T Group Communication with EEPROM Using the Renesas IC Bus Module RIIC IIC EEI IntNack Set the internal status to NACK Set the internal status to NACK received received Disable the NACK detection interrupt Disable the NACK detection interrupt Clear ICSR2 STOP Clears the stop condition detected flag Transmit the EEPROM device address Generates a stop condition
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33. ument Figure 13 Acknowledge Polling RO1AN0637EJ0100 Rev 1 00 Sep 27 2011 ztENESAS Page 16 of 29 RX62T Group Communication with EEPROM Using the Renesas I C Bus Module RIIC IIC Create RIIC reset Transfer speed setting Timeout setting Invalidate slave address Clear ACKBT protection Interrupt settings Initialize RAM used in the RIIC module Enable IIC transfer operations Reset all RIIC registers and its internal state by setting ICCR1 ICE to 0 and ICCR1 IICRST to 1 Sets the transfer speed to 400 kbps Sets up timeout operation Only count when SCL is high and use long mode Disables slave address detection Enables writing to ACKBT To enable NACK responses from EEPROM during read processing Interrupt settings Enable the timeout interrupt Enable the arbitration lost interrupt Disable the start condition detection interrupt Enable the stop condition detection interrupt Enable the NACK received interrupt Enable the receive data full interrupt Disable the transmission complete interrupt Enable the transmitted empty interrupt Initializes the RIIC internal RAM Enables RIIC transfer operations Figure 14 IC Initialization IIC Destroy RIIC reset Reset all RIIC registers and its internal state by setting ICCR1 ICE to 0 and ICCR1 IICRST to 1 Figure 15 IIC Termination Processing R01ANO0637EJ0100 Rev 1 00 Se
34. unicates with the EEPROM to write 8 bytes of data and then read the written data back Between the write and read operations it uses acknowledge polling to verify that the EEPROM write has completed 1 1 Connection Diagram Figure 1 shows the connections in the application example presented in this application note RSK ROK5562TOSOOOBE RX62T EEPROM R5F562TAADFP R1EX24512ASASO0A PB1 SCL SCL AO A1 PB2 SDA SDA WP Slave address A6h Bit 0 is the R W bit Figure 1 Connection Diagram 1 2 RIIC Settings Table 1 lists the RIIC settings described in this application note Table1 RIIC Settings Item Settings Operating frequencies e Input clock EXTAL 12 5 MHz e System clock ICLK 100 MHz e Peripheral module clock PCLK 50 MHz e Internal reference clock IlC 12 5 MHz Master slave Single master Address format 7 bit address format Transfer speed 400 Kbps Timeout detection e The detection function counts while the SCL line is low e Long mode 16 bit counter IIC about 5 24288 ms RO1AN0637EJ0100 Rev 1 00 Page 2 of 29 Sep 27 2011 ztENESAS RX62T Group Communication with EEPROM Using the Renesas IC Bus Module RIIC 1 3 EEPROM Table 2 lists the specifications of the EEPROM used in the application example described in this application note Table2 EEROM Specifications Item Descr
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