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MN101C46F/F46F LSI User`s Manual

1. CRHSH CRI Capture Start Timing Control Register 1 High x 03E11 CRI1SWH CRI Capture Start Timing Control Register 1 High x 03E31 CRHS Capture Start Timing Control Register 1 x 03E10 CRI1SW CRI Capture Start Timing Control Register 1 x 03E30 Bi 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 CRIIS CRIIS CRIIS CRIIS CRIIS CRIIS CRIIS CRIIS CRIIS CRIIS 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 1 1 1 1 1 1 1 1 1 1 1 R W R R R R R RW RW RW R W RW RW RW RW RW RW RW CRI1S 10 0 Start position for CRI capture 1 Valid range x 000 to x 7FF CRHEH CRI Capture Stop Timing Control Register 1 High X 03E13 CRI1EWH CRI Capture Stop Timing Control Register 1 High x 03E33 CRHE CRI Capture Stop Timing Control Register 1 x 03E12 CRHEW CRI Capture Stop Timing Control Register 1 x 03E32 Bit 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 CRIE CRUE 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 R W R R R R R RW RW RW RW RW RW RW RW RW RW RW CRI1E 10 0 Stop position for CRI capture 1 Valid range x 000 to x 7FF CRI2SH Capture Start Timing Control Register 2 High X O3E1
2. 0 Pullup off 1 Pullup on E 0 POS IRQ1 1 ADINO EP POMD3 0 Port input 1 Port output SM PODIR3 0 Port low output Pi 1 Port high output iu NT POOUT3 B 4 X POINS IRQ1 amp fc 5 Schmidt trigger ADINO lt AAA Figure 4 4 P03 ADINO IRQ1 Port 0 MN101C46F LSI User Manual Panasonic Semiconductor Development Company 70 Panasonic I O Ports I O Port Circuit Diagrams 0 Pullup off 1 Pullup on POPUPn E 0 P04 P05 P06 1 ADIN1 ADIN2 ADINS POMDn 0 Port input 1 Port output PODIRn Pin 0 Port low output 1 Port high output POINn amp 1 ADIN2 ADIN3 D n 4 P04 n 5 P05 n 6 P06 Note Figure 4 5 P04 ADIN1 5 2 and P06 ADIN3 Port 0 MN101C46F LSI User Manual Panasonic Semiconductor Development Company 71 Panasonic I O Ports 1 0 Port Circuit Diagrams 0 Pullup off 1 Pullup on POPUP7 P1PUPn 0 PO7 P10 P11 P12 1 ADIN4 ADIN5 ADIN6 ADIN7 POMD7 P1MDn i 0 Port input 1 Port output PODIR7 P1DIRn 0 Port low output 1 Port high output POOUT7 P1OUT
3. OSD Registers OSD1 OSD Register 1 x 03EB6 Bit 7 6 5 4 3 2 1 0 HPOL VPOL POL OSD Reset 0 0 0 0 0 0 0 0 RW RW RW RW RW HPOL and VPOL HSYNC and VSYNC input polarity select Y HPOL HSYNC and VPOL VSYNC selects 0 Active low The value written to bit 2 of OSD1 1 Active high is valid from the leading edge of the YSPOL YS output polarity next VSYNC When the OSD func TEM tion is on the OSD starts operating 5 from the VSYNC after this bit is set 1 Active low to 1 When the OSD function is off OSD OSD function switch the OSD stops operating at the next Off VSYNC after 0 is written S n OSD2 OSD Register 2 x 03EB8 1 Bit 7 6 5 4 3 2 1 0 AP CN GCOL COLB When you stop the OSD function to a 7 i 5 5 7 eset lower current consumption 0 is BAV lw TRAY written to OSDPOFF to stop the OSD clock immediately after 0 is written to OSD OSD function off will not be valid so current con sumption may not decrease If this occurs stop the OSD clock after writing 0 to OSD after VSYNC input APONT Address pointer enable 0 Address pointer off AP of VRAM line disabled The maximum number of horizontally displayable characters is 38 1 Address pointer on AP of VRAM line enabled The maximum number of horizontally displayable characters is 61 GCOL 1 0 Graphics color mode 0 8 color mode 1 4 color mode COLB C
4. 103 6 3 1 Example of Cascade Connection 5 4 104 6 4 8 Bit Timer Control Registers ore uut Lek Pee en Bee bee RAS 106 6 4 1 Control Registers gu GAR a uyay Rad A EU ea E ps 106 6 4 2 Programmable Timer Registers 1 2 107 6 4 3 Aimer Mode Registers Se Rak South ERES CR AD RR ERE RA a ER RU asss 108 7 On Screen 109 7 1 Description nih ath vee apart sya ahora gar Wt PU URL P dee debba 109 722 Power Saving Considerations in the OSD 111 7 3 OSD Operation epp PEA GR MUR phe A et de itte gut e dete 112 7 3 1 Operating Clock RUOREDI T RUE MPa tard hited Tu ep 112 7 3 2 External Input Synchronization Signal 112 7 3 3 Display Control System 5 tessa gah eid sede Sea red ep e be 112 7 3 3 1 TEX 2x5 kya s Kuna XU OE DRIED NS CE URINE DANT T D 112 7 3 3 2 Graphic Layers 2 eb Bas cee u k HERR IU LE ORE IS 112 7 3 4 Output Pin Setup cues P DEUM DIESE 112 7 3 5 Microcontroller Interface 222222222 e REA VR RE EXER E EE DENS 112 7 3 6 Basic VRAM Operations coe se ee Whee Ee Le EUER EAE 1
5. 216 13 4 Setting up the Bus Connection 218 13 5 SDA and SCL Waveform Characteristics 219 13 6 IC Interface Setup Examples DI XD IRR TUE S reds vga Saas 220 13 6 1 Setting up a Transition from Master Transmitter to Master Receiver 220 13 6 1 1 Pie configurmg i Lee UR eb eeu eub E IP RM 220 13 6 1 2 Setting up the First Interrupt 220 13 6 1 3 Setting up the Second 221 13 6 1 4 Setting up the Third 1 44 221 13 6 2 Setting up a Transition from Slave Receiver to Slave 222 13 6 2 1 Pr configuring u 55225902 ERE GU Ob eda T eg eR eR 222 13 6 2 2 Setting up the First Interrupt sunsu Saeed REIR US 222 13 6 2 3 Setting up the Second 223 13 6 2 4 Setting up the Third 2 1 223 13 7 Bus Interface R gistets Ru oe eed Tie EU LEER I debe e Cete 224 14 Pulse Width Modulator 227 14 1 14 B
6. 1 4 53 3 6 Processing Sequence for Maskable 2 55 3 7 Processing Sequence for Nested 57 4 1 POO RMIN IRQO Bort 0y RERO RANA P Re ADR ARS eee ee 67 4 2 POI SDAI and P41 SDAO Dual Use C 68 4 3 P02 SCL1 and P42 SCL0 Dual Use C Pins e eese et UR UR OR ERU 69 4 4 POS ADINU IRQIT Port O 2 iu sS UE A UP ueber eee wear E Me VXEEiPSN D EE E 70 4 5 POS ADIN2 and POG ADING Port 0 71 4 6 P07 ADIN4 Port 0 PIO ADINS P11 ADING and P12 ADIN7 Port 1 72 4 7 P13 SYSCLK E Sek eds Me esi eene er Eee 73 4 8 PIA PWMO Pott T ee C tate s tte a RR DR RUNE RUN RR RR eR ace 73 MNIOIC46F LSI User Manual Panasonic Semiconductor Development Company ix Panasonic List of Figures 4 9 P15 PWMI and P16 PWM2 1 74 4 10 2 Port 1 and P20 PWM4 IRQ3 2 75 4 11 P21 PWMS RQA Port 2 melee Rye RE RAE ODER y RR e 76 442 P22 CLL and P23 CLH Pott 2 open e eee eee p Uude e ep TI 4 13 P24 VREFHI and
7. 18 1 18 Sample Power Circuit Emitter Follower 18 2 1 Block Steucture and Functions u ade REL au oak eas 21 2 2 Organization of the Instruction Execution Controller 0 0 0 eee eee 24 2 3 single Chip Mode e eue vue ERE RO Reed oy EAE SR eS be 31 2 4 Function Block Diagram of the Bus 1 34 2 5 Transitions between Operating Modes 36 2 6 Clock Switching Circuit ewe PA le eee tA deae RE Chu 36 2 7 Sequence for Invoking and Exiting Standby 40 2 8 Minimum Reset Pulse Width co naa aa RR RR iR b EUR pul eect add 43 2 9 Reset Clearing Sequence r uba asus ee BUR PIU euis 44 2 10 Function Block Diagram of the Oscillator Stabilization 44 3 1 Block Diagram for Interrupt 1 48 3 2 Interrupt Handling Sequence Maskable 49 3 3 Example of Interrupt Levels 1 7 51 3 4 Interrupt Acceptance Process iu ya aus pa ps a uyasapa abe mre reme 52 3 5 Stack Status during
8. 8 bit data Trailer Ignored 8 bit data Remote ignal input Edge detection 1 i hi 8 bit data reception detection Trailer detection Leader detection 8 bit data reception DEN 7 X 0 0 E counter A Counter reset Figure 11 4 Reception of 8 Bit Data with Leader MN101C46F LSI User Manual Panasonic Semiconductor Development Company 202 Panasonic IR Remote Signal Receiver IR Remote Signal Receiver Operation 11 3 4 Identifying the Data Format The microcontroller determines the logic levels of the data by testing the interval between remote signal edges Table 11 1 shows the intervals that the microcon troller interprets as 0 and 1 for both HEAMA and 5 6 bit formats Table 11 2 shows the conditions for identifying long and short data Table 11 1 Logic Level Conditions for Data Formats I Logic Level Conditions Operating Mode Data 0 Data 1 HEAMA format lt 6 Ts cycles gt 6 Ts cycles 5 6 bit format lt 12 Tg cycles gt 12 Ts cycles Table 11 2 Long and Short Data Identification Operating Mode Long Data Short Data HEAMA format gt 10 Ts cycles lt 2 Ts cycles 5 6 bit format 2 20 Ts cycles lt 4 Ts cycles The 6 bit counter regulates data format detection When the microcontroller detects a data leader it sets the LONGDF bit of the clock status register RMCS to indicate long data Figure 11 5 is a graphic representation of all the
9. 1 205 11 5 HEAMA and 5 6 Bit Data Pulse 1 6 205 12 1 ROM Correction Address Match and Data 211 13 1 IC Bus Terminology 213 13 2 Operating Modes for Devices on an TAR euh dass ase CoA dep Le eit 214 13 3 Control Registers for Clamping 216 13 4 Registers Settings for SDAO SCLO or SDAI SCLI Ports 218 13 5 SDA and SCL Waveform 219 13 6 STA and STP Settings upaya RW ES bu tee HE oe ee 224 14 1 Added Pulse Overlapping 228 1 Register Map 03 00 03 235 A 2 Register Map X 03B00 X 0SEFE BORER aE Rae ee 235 B 1 Programming Times for PROM Writers 239 Panasonic Semiconductor Development Company MN101C46F LSI User Manual viii Panasonic List of Figures List of Figures 1 1 MN101C46F Pin Configuration 1 1 2 22 2 4 1 2 MN101C46F Pin Configuration ec Re RR HEURE RR RR SIR Rc
10. A A 3 VP HP x22 a up ie mh a a Nes ESAME ECC TEE gt i 1st line VSZ 3 Graphic Graphic 6 CH x 002 CH x 001 palette 1 palette 3 VP x 40 2nd line HSZ 0 1X Y HP x 4 Text Graphic Graphic Graphic Text Graphic 8 010 013 013 013 013 014 Space Space 016 palette 1 palette 1 palette 1 palette 1 palette 1 palette 2 alette 2 3 consecutive displays 2 consecutive spaces VP x 58 3rd line Y HSZ 3 4X NN xp E Graphic Graphic CH x 181 CH x 182 VSZ 1 palette 1 palette 2 2X End of display S J Figure 7 3 Display Example with AP Panasonic Semiconductor Development Company MN101C46F LSI User Manual 117 Panasonic On Screen Display VRAM 7 5 VRAM 7 5 1 Bit Assignments in Internal RAM Table 7 6 VRAM Bit Assignment Bits 2 linked odd 15 14 13 12 10 9 8 7 6 5 4 3 2 1 0 odd odd odd odd odd odd odd odd even even even even even even even even even bytes bp bps bps bp4 bp3 bp2 bpi bpo bp7 bp bps bp4 bp3 bp2 bp 0 CC 0 0 CGSEL PLTI PLTO E 5 CH8 CH7 CH6 5 CH4 CH3 CH2 CHI CH0 Text code ID code C G Palette select Text character graphic tile address 512 of each select COL normal mode 1 0 BS
11. MON bbc e irte rS eee hee 169 9 1 1 Watchdog Timer Block 169 9 2 Operation of the Watchdog 2 170 9 2 1 Watchdog Timer 1 170 9 2 1 1 Using Watchdog Timer Functions 1 170 9 2 1 2 Methods of Software Fault Detection 170 9 2 1 3 Clearing the Watchdog Timer cin x o eon LE XE REPE RR 170 Panasonic Semiconductor Development Company MN101C46F LSI User Manual iv Panasonic Contents 9 2 1 4 Time Out Period te Sis eum DRIN Tee e Ev 171 9 2 1 5 Lower Limit at which Watchdog Can 1 171 9 2 1 6 Relationship between Watchdog Timer and CPU 171 9 2 2 Setup Examples for the Watchdog 7 172 9 3 Watchdog Timer Control 173 10 Closed Caption 174 10 1 Description v sv pO HOLT De R SER OG eee a Sel AEE EE NORD RERO 174 10 2 Block Diagram uo tis ets thee th hee ied E e eee 174 10 3 Functional Description negesnclebheeeebe eh ree
12. 2 2 lt 5 E TEE scat gt 1st line VSZ 3 Graphic Graphic 6 CH x 002 CH x 001 i i palette 1 palette 3 VP x 40 2nd line HSZ 0 1X Y HP x 4 Text Graphic Graphic Graphic Graphic Text Graphic ka pasas 010 013 013 013 013 014 Space Space 016 palette 1 palette 1 palette 1 palette 1 palette 1 palette 2 alette 2 3 consectuive displays 2 consecutive spaces VP x 58 3rd line Y HSZ 3 4X BM 40 Graphic Graphic CH x 181 CH x 182 VSZ 1 palette 1 palette 2 2X End display X J Figure 7 2 Display Example without AP Panasonic Semiconductor Development Company MN101C46F LSI User Manual 115 Panasonic On Screen Display Display Setup Examples Z 4 2 Setting Up the Display with AP This section shows how to set up the display data in the VRAM with AP B Register settings RAMEND x 003EB4 x BE 00 x 0B IAP x 003ECE x FF IHPH x 003ECB x 08 IHP x 003ECA x 22 x 003ECD x 18 IVP x 003ECC x 03 OSD2 x 003EB8 x 00 Table 7 5 Example Text VRAM Settings VRAM end address x 0BFF IAP x BFF IAP x BFF IHP x 22 IHSZz x 1 HP x 22 IHSZ x 1 x 03 IVSZ x 3 IVP x 03 IVSZ x 3 APCNT 1 8 co
13. Bit 7 6 5 4 3 2 1 0 TM2 TM2 TM2 TM2 TM2 TM2 TM2 TM2 OC6 5 OC4 OC3 OC2 OCI OCO Reset x x x x x x x x R W R W R W R W R W R W R W R W R W TM3OC Timer 3 Compare Register Bit 6 5 4 3 2 1 0 TM3 TM3 TM3 TM3 TM3 TM3 TM3 TM3 7 OC6 5 OC4 OC3 OC2 OCI OCO Reset x x x x x x x x R W R W R W R W R W R W R W R W R W TM4OC Timer 4 Compare Register Bit 7 6 5 4 3 2 1 0 TM4 TM4 TM4 TM4 TM4 TM4 TM4 TM4 OC7 OC6 OC5 OC4 OC3 OC2 OCI OCO Reset x x x x x x x x R W R W R W R W R W R W R W R W R W 2 Timer 2 Binary Counter Bit 7 6 5 4 3 2 1 0 TM2 TM2 TM2 TM2 TM2 TM2 TM2 TM2 BC7 BC6 5 BC4 BC3 BC2 BCO Reset x x x x x x x x R W R W R W R W R W R W R W R W R W TM3BC Timer 3 Binary Counter Bit 7 6 5 4 3 2 1 0 TM3 TM3 TM3 TM3 TM3 TM3 TM3 TM3 BC7 BC6 BC5 BC4 BC3 BC2 BCO Reset x x x x x x x x R W R W R W R W R W R W R W R W R W Timer 4 Binary Counter Bit 7 6 5 4 3 2 1 0 TM4 TM4 TM4 TM4 TM4 TM4 TM4 TM4 BC7 BC6 5 BC4 BC3 BC2 BCI BCO Reset x x x x x x x x R W R W R W R W R W R W R W R W R W x 03F5A x 03F5B x 03F62 x 03F58 x 03F59 x 03F60 Panasonic Semiconductor Development Company 107 Panasonic MN101C46F LSI User Manual 8 Bit Timers 8 Bit Timer Control Registers 6 4 3 Timer Mode Registers The timer mode registers are read write registers that control timers 2 through 4 TM2M
14. Basic perfor Internal operating frequency max 3 58 MHz mance Fastest instruction execution 1 cycle Fastest operation between registers 2 cycles Fastest load store 2 cycles Conditional jumps 2 3 cycles Pipeline Three stages instruction fetch decoding and execution Address space 256 Kbytes maximum 64 Kbytes for data Space shared by instructions and data External bus Addresses 18 bits max Data 8 bits Shortest bus cycle 1 clock 279 3 ns Interrupts Vector interrupt system 3 levels Power down modes STOP and HALT modes MN101C46F LSI User Manual Panasonic Semiconductor Development Company 20 Panasonic Basic CPU Functions Block Functions 2 3 Block Functions 2 3 1 Block Diagram Data registers D0 Processor status word T1 Clock lt Source oscillation Address registers D1 PSW T2 generator Stack pointer D2 SP A1 D3 1 Instruction execution ABUS controller BBUS Instruction decoder Program counter i Incrementer Instruction Interrupt queue controller Y T 1 Program address Operand address Interrupt bus Y Y Bus controller ry i ROM bus RAM bus Peripheral expansion a Y CSIC interfac
15. Reset 0 0 0 0 1 0 0 0 R W R W R W R W R W R W R W R W a SLPULSEL Polarity select for the CRI cycle transition detection 0 Detect 0 to 1 transitions Always tie the bits in FC to fixed 1 Detect 1 to 0 transitions settings CRICSEL Detection interval select for the CRI frequency width 0 CRI capture interval only 1 CRI capture interval and transition detection interval NCRIGSEL Sampling pulse generation interval 0 Disable the CRI capture interval 1 Enable the CRI capture interval CNTSTAP 4 0 Caption data sampling start position Valid range x 00 to x 1F SLCNT Slice Level Calculation Control Register x 03E01 SLCNTW Slice Level Calculation Control Register x 03E21 Bit 7 6 5 4 3 2 1 0 FCP SYNC HCNT HCNT SLICE SLICE SLICE SLICE SEL SEL SEL1 SELO SEL LD2 LD1 Reset 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W This register contains the settings for selecting either a hardware or soft 1 ware slice level When you do not use a bit or field in this register tie it to the setting indicated below Always tie the bits in SLCNT to For designs using the closed caption decoder always tie bits 6 to 0 fixed settings FCPSEL Hard soft sampling start position select 0 Select hardware calculation 1 Select software setting set in SFTSTAP 10 0 field of STAP SYNCSEL Sync signal select HSYNC VSYNC
16. x O3F5F x 03F66 TM4PSC1 TM4PSCO TM4BAS Clock selected 0 0 0 fosc 4 0 1 0 fosc 16 1 0 0 fosc 32 1 1 0 fosc 64 0 1 fs 2 e 1 1 fs 4 MN101C46F LSI User Manual Panasonic Semiconductor Development Company 96 Panasonic Prescalar Operation of the Prescalar Function 5 3 Operation of the Prescalar Function 5 3 1 Prescalar Operation Prescalars 0 and 1 Prescalars 0 and 1 are free running counters of 7 and 3 bits respectively that output clocks produced by dividing the reference clocks Start and stop them incrementing using the PSCEN flag of the prescalar control register PSCMD Count timing prescalars 0 and 1 Prescalar 0 increments on the negative edge of fosc Prescalar 1 increments on the negative edge of fs Peripheral functions that use the divided clocks output by the prescalars The following functions can use the divided clocks output by the prescalars The 1 associated control registers for selecting clocks also shown Table 5 6 Peripheral Functions that Can Use Prescalar Clocks To use a prescalar divided clock i k Function Control Register first enable the prescalar count then start the peripheral function Timer 2 count clock CK2MD Timer 3 count clock CK3MD Timer 4 count clock CK4MD 5 3 2 Example of Prescalar Operation Setup Selecting a count clock for timer 2 The following example shows and describes setup procedures f
17. 5 1 3 OSC1 and OSC2 Oscillator 8 121 4 4 8 1 4 External Connection Example for Closed Caption Decoder 10 1 5 Composite Video Signal Specification 2 11 1 6 PC Interface Timimng np bn 11 1 7 Start and Stop Conditions 4 12 1 8 HSYNC VSYNC Input Conditions 13 1 9 Correct Connection Technique for the Vpp 14 1 10 Incorrect Connection Technique for Vpp and 14 1 11 Handling Unused Pins Dedicated for 15 1 12 Handling Unused Pins Dedicated for Input 2 15 1 13 Input Inverter Structure and Characteristics 16 1 14 Handling Unused I O Pins Output Is Hi Z 16 1 15 Power and Input Pin 1 17 1 16 Power and Reset Input 1 17 1 17 Design Considerations for the Power
18. EVODH Field ID Control Register HIgh x OSEBF EVOD Field ID Control Register x OSEBE 7 6 5 4 3 2 1 0 7 6 5 4 2 1 0 EO FR EO FREG FREG FREG FREG FREG FREG FREG FREG SEL MON MON 23 22 21 20 13 12 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R R R R R R EOSEL Even odd field select R W 0 Select the smaller counter value as the display start field 1 Select the larger counter value as the display start field FRMON Field counter load monitor R Monitors which field register FREG loads the counter value on the lead ing edge of VSYNC 0 Loaded to FREG2 3 0 1 Loaded to FREGI 3 0 EOMON Even odd field monitor R Flagged during display field interval 0 No display start field detected 1 Display start field detected FREG2 3 0 Field register 2 4 bit register storing field counter value R FREG1 3 0 Field register 1 4 bit register storing field counter value R HCOUNTH Vertical Display Position Counter x 03EBD HCOUNT Vertical Display Position Counter x 03EBC 7 6 5 4 3 2 1 0 7 6 3 4 3 2 1 0 HCNT HCNT HCNT HCNT HCNT HCNT HCNT HCNT HCNT HCNT 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 These registers hold the HSYNC count They are cleared to 0 on the rising edge of VSYNC MN101C46F LSI User Manual Panasonic Semiconductor Development Company 148 Panasonic On Screen Display
19. 137 7 9 Bit Settings for Controlling Shutter Movement 139 7 10 Bit Settings for Controlling Shuttering 141 7 11 EOMON Output Criteria u eerta RR EAR eR epe eee er Ree ee 145 8 1 A D Conversion Functions sorore eet e rb Ue en Ao etwas 159 8 2 Setting up the A D Conversion Input Pins 163 8 3 A D Conversion Clocks and Cycles 163 8 4 A D Conversion Sampling Time and Conversion 164 8 5 Controlling the A D Ladder 164 8 6 Starting A D 74 164 8 7 ADC Setup Procedutes cce ee ARES SEU LEER CES M EPUM RE Legs 165 8 8 ADC Control Registets 2 3 ave sss E we Oe lee UrUEDUUDU QE DEDE 167 9 1 Time Out oet T gad bur bue 171 9 2 Lower Limit at which Watchdog Can Be 171 9 3 Initialization Program Example Setup that Initializes the Watchdog Timer 172 9 4 Program Main Routine Example Setup that Periodically Clears the Watchdog Timer 172 9 5 Setup of Interru
20. 2 14 1 6 2 Handling Unused Pins I ERE RE Meester REY 15 1 6 2 1 Handling Uniised 2 Ra re Rt eR P UR ess RECIEN 15 1 6 2 2 Handling Unused Pins Dedicated Output Pins 15 1 6 2 3 Handling Unused Pins Dedicated Input 15 1 6 2 4 Handling Unused Pins 8 16 1 6 3 Turning on Power e tees uper be badd Shue umapa ae rus 17 1 6 3 1 Power and Input Pin Voltage 17 1 6 3 2 Power and Reset Input 17 1 6 4 Power Circuit u y e pde ep depen eg 18 1 6 4 1 Design Considerations for the Power 18 1 6 4 2 Sample Power Circuit Emitter Follower Type 18 2 Basic CPU 19 2 1 Descriptions sev veb pipu pasu CEDE VI db Ies 19 2 2 pni ce EE 20 2 3 Block Functions ap pA epa e pre te e c ea ede teur i e etas 21 2 3 1 Block Diagram qaa ERR 21 2 3 2 Block Descriptio ERR Dag Helene 22 2 4 CPU Control Registe
21. ROM address Correction address udi match registers registers Correction Correction address data Match ROM correction detection MUX selector enable circuit registers Figure 12 3 ROM Correction Block Diagram 12 3 Programming Considerations At reset the ROM correction address match and data registers contain all 0s Since a reset also disables ROM correction in ROMCEN the ROM will still operate normally Only read from or write to the address match registers while ROM correction is disabled in ROMCEN Otherwise an error may occur in the match detection circuit Note that the address match and data registers only allow full register access eight bits You cannot write to individual bits The ROM correction function cannot be emulated in ICE mode MN101C46F LSI User Manual Panasonic Semiconductor Development Company 210 Panasonic ROM Correction ROM Correction Control Registers 12 4 ROM Correction Control Registers Table 12 1 shows the organization of the address match and data registers for ROM correction Write a ROM address to be corrected to an AMCHIHn AMCHIMn and AMCHILn register trio and write the corrected data to the asso ciated CHDATn register Enable ROM correction for the associated address in the ROMCEN register Table 12 1 ROM Correction Address Match and Data Registers Addre
22. 1 143 7 22 Line Shuttering Setup 143 7 23 Field Detection Circuit Block 144 7 24 Field Detection Timing a AAA RAG a UR E RA e e SAS ER a 144 8 1 Block Diagram o ET DUREE ER Mee eek e dep eps 160 8 2 The A D Conversion Operation e va bE WR bs ONE GASES OSM NN ES 162 8 3 Recommended ADC Connection 1 166 8 4 Recommended Circuit 166 9 1 Watchdog Timer Block 1 169 Panasonic Semiconductor Development Company MN101C46F LSI User Manual x Panasonic List of Figures 10 1 Closed Caption Decoder Block Diagram 174 10 2 Recommended ADC Configuration 1 1 175 10 3 External Connection with Both CCD0 and CCD1 175 10 4 External Connection with Only CCD0 175 10 5 u u cas upay baa CERERI EN p En A aa ohne c beds 176 10 6 Sync Separator Circuit Block 178
23. 100 ADIN4 4 101 ADINS PAS 110 ADIN6 PA6 111 ADIN7 PA7 ANCTR2 A D Control Register 2 x 03FB2 Bit 7 6 5 4 3 2 1 0 ANST Reserved Reset 0 0 0 0 0 0 0 R W R W R R R R R R R ANST A D Conversion Status 0 End or stopped 1 Start or converting Reserved Set to 0 8 4 2 A D Buffer ANBUF1 A D Conversion Data Storage Buffer x 03FB4 Bit 7 6 5 4 3 2 1 0 ANBUF ANBUF ANBUF ANBUF ANBUF 17 16 15 4 13 Reset X X X X X 0 0 0 RW R R R R R R R R This register stores the results of the A D conversion MN101C46F LSI User Manual Panasonic Semiconductor Development Company 168 Panasonic Watchdog Timer Description 9 Watchdog Timer NRST STOP Write WDCTR HALT fs SYSCLK 9 1 Description The MN101C46F contains a watchdog timer function The watchdog timer is used to detect software faults It is controlled by the watchdog timer control register WDTCR and generates a watchdog interrupt WDIRQ when the watchdog timer overflows Two consecutive watchdog interrupts indicate a software fault that cannot be recovered by software and requires a forcible reset by hardware 9 1 1 Watchdog Timer Block Diagram DLYCTR R R 1 2 1 214 1 215 1 220 I Internal reset release 15 2 5 26 fs 22 w
24. 2 203 11 6 Pin Edge D tection us uyapay e A eR e er e erg te 204 12 1 ROM Area Schematic 14 209 12 2 ROM Correction PIOW z RC eR q Sa GR REDE RR 209 12 3 ROM Correction Block 1 4 4 1 210 13 1 Example of IC Bus Applicaton zou Sua ae 213 13 2 Connection of Two Microcontrollers to C 214 13 3 IC Bus Interface Op tatiOll u Li us qasiq CREE EET Pee 215 13 4 Bus Controller Block Diagram ep eR ERR etes ee et dotes 216 13 5 Pin Control Circuit for the IC Bus Controller sees ene 218 13 6 SDA and SCLE Wavetorms s sie saysi ua Fae False Sande HEP ber 219 13 7 Waveform for Master Transmitter Transitioning to Master 221 13 8 Waveform for Slave Receiver Transitioning to Slave 223 14 1 14 Bit PWM Block Diagram eR ht C ce anu ec m rece d 227 14 2 14 Bit PWM Output 228 14 3 tgyg PWM Output Waveform 6 e 228 14 4 Added Pulse Waveform siret eb ie 229 14 5 Block Diagram
25. 5 TBNZ io8 bp d7 TBNZ io8 bp d11 6 OR Dn Dm 7 AND Dn Dm 8 BSET io8 bp BCLR io8 bp 9 JMP abs18 label JSR abs18 label XOR Dn Dm 8 Dm B ADDC Dn Dm C BSET abs16 bp BCLR abs16 bp D BTST abs16 bp cmp 8 abst6 mov 8 abs16 8 abs16 d7 11 bane 8 abs16 d7 11 E TBZ abs16 bp d7 TBZ abs16 bp d11 F TBNZ abs16 bp d7 TBNZ abs16 bp d11 Ver2 1 2001 03 26 Panasonic Semiconductor Development Company MNIOICA6F LSI User Manual 247 Panasonic MN101C46F Revision History Revision 2 00 to Revision 2 10 July 29 2001 Page Description of Revision Chapter 1General Description P1 Changed 42 pin SDIL to 42 pin SDIP P2 Corrected number of internal interrupts from 10 to 12 P3 Changed Package from 42 pin SDIL to 42 pin SDIP in table 1 2 P3 Added 64 pin LQFP to Package in table 1 2 P3 Added LQFP064 P 1414 to Package model number in table 1 2 P3 Added notes to list of description of hardware table 1 2 P4 Corrected OSC2 in figure 1 1 from input output to output P5 Added figure 1 2 Flat package version P6 Corrected OSC2 in pin description table from iuput output to output P9 Added Conversion relativity accuracy in table 1 6 P10 Revised figure 1 4 P11 Deleted description of HSYNC cycle and HSYNC hpase difference P12 Added notes of software setup example to ta
26. E POIN7 ADIN4 ADINS ADIN6 ADIN7 li Note 0 10 I Pll n 2 P12 Figure 4 6 PO7 ADINA Port 0 P10 ADIN5 P11 ADIN6 and P12 ADIN7 Port 1 MN101C46F LSI User Manual Panasonic Semiconductor Development Company 72 Panasonic I O Ports I O Port Circuit Diagrams 0 Pullup off 1 Pullup on P1PUP3 lo 0 P18 1 SYSCLK lt gt P1MD3 0 Port input 4 E 1 Port output 35 5 PIDIR3 0 Port low output 1 Port high output 0 P1OUT3 Pin Dot clock U 5 SYSCLK or X multiple of SYSCLK 1 P13 SYSCLK lt Figure 4 7 P13 SYSCLK Port 1 0 Pullup off 1 Pullup on 0 P14 1 PWMO rS 0 Port input 1 Port output 0 P1DIR4 M U 1 Pin PWMO output x 0 Port low output 1 Port high output i P1OUT4 P1IN4 Figure 4 8 P14 PWM0 Port 1 Panasonic Semiconductor Development Company MN101C46F LSI User Manual 73 Panasonic I O Ports 1 0 Port Circuit Diagrams 0 Pullup off 1 Pullup on P1PUPn 5 0 P15 P16 1 PWM1 PWM2 XS P1MDn 0 Port input 1 Port o
27. ER EU e eee b dee ede te gt edet 30 2 6 Memory Mode Settings obese EE UR px INE PUE UO VUE SINE DEED eh bea aps 31 2 7 Register Map 03 00 0 4 32 2 8 Controlling the Operating Mode and Generating Halting Clock Oscillation 38 2 9 Oscillation Stabilization 2 2 14 2 45 3 1 Interrupt Functions Sots RASA Ip rA RR ead La asad SSS ee RU 47 3 2 Interrupt Vector Addresses and Interrupt 50 3 3 Setting Interrupt canes CENTRI UR GE UNE De RE Ree SESS 58 3 4 Interrupt Control Registers cpu ERES VENUE RUE SUE P PEE nates RS 59 4 1 I O Port Bins ice I Mea de ae ebd qb dete tonat pb e bres 66 5 1 Peripheral Functions that Use Prescalar 93 5 2 Prescalar Control Registers sete beer eer cep e ee e ee esee edges 95 5 3 Timer 2 prescalarselect register ovde ette a RR RR et UR ERR UR E UR 95 5 4 Timer 3 Prescalar Select Register u phuyuy uqusqa uuu ly SUE EU EE Ce 96 5 5 Timer4 Prescalar Select Register oru S ENG EELS EEE SEES CE US OMS 96 5 6 Peripheral Functions that Can Use Prescalar 97 5 7 Procedures for Setting up a Coun
28. 0000 0011 134 8 5 1 gt 7 0 mem8 SP 2 PC bp15 8 mem8 SP 3 bp7 PC H memB SP 3 bp1 0 PC bp17 16 memB SP 4 HA mem8 SP 5 HA h SP 65SP Contorl instructions REP REP imm3 imm3 1 RPC 0010 0001 1 1 13 NOTE Pages for MN101C Series Instruction Manual 1 norepeat whn imm3 0 rep imm3 1 1 Other the instruction of MN101C Series the assembler of this Series has the following instructions as macro instructions The assembler will interpret the macro instructions below as the assembler instructions macro instructions replaced instructions remarks INC Dn ADD 1 Dn DEC Dn ADD 1 Dn INC An ADDW_1 An DEC An ADDW 1 An INC2 An ADDW 2 An DEC2 An ADDW 2 An CLR Dn SUB Dn Dm ASL D ADD Dn Dm ROL ADDC Dn Dm NEG NOT Dn ADD 1 NOPL MOVW DWn DWm MOV MOV 0 SP Dn MOV Dn 0 SP MOVW MOVW 0 SP DWn MOVW MOVW DWn 0 SP MOVW MOVW 0 5 MOVW MOVW An 0 SP Ver3 1 2001 03 26 Panasonic Semiconductor Development Company 245 Panasonic MN101C46F LSI User Manual MNI01C Series Instruction Map Appendix D MNI01C Series Instruction Map MN101C SERIES INSTRUCTION MAP 1stnibble2ndnibble MOV 46 08 RTI 8 abs8 abs12 P
29. Operating Frequency 12 MHz 14 MHz 14 32 MHz SLCNT2 x 16 x 1B SLCNTI x 1B x 1B x OF MN101C46F LSI User Manual Panasonic Semiconductor Development Company 198 Panasonic IR Remote Signal Receiver Description 11 IR Remote Signal Receiver 1 fsyscLK 3 58 MHz in all of the examples and descriptions in this section 11 1 Description The MN101C46F contains a remote signal receiver that processes signals in two formats Household Electrical Appliance Manufacturers Association HEAMA format and 5 6 bit format This chapter provides an overview of each block in the circuit and describes the operation of the receiver The remote signal is input through the RMIN pin Each time the edge detection circuit detects the active edge of the signal the 6 bit counter resets and the sampling clock Ts starts counting Ts is formed by dividing PWM2 by the value in the frequency division control register RMTC The clock status register RMCS which can be read at any time holds the current value of the 6 bit counter The remote signal contains a leader data and a trailer in that order The micro controller shifts received data into the LSB of the reception data shift register RMSR After it receives eight bits it loads the contents of RMSR to the reception data transfer register RMTR Panasonic Semiconductor Development Company MN101C46F LSI User Manual 199 Panasonic oruoseueq
30. fg 220 fg 218 MUX gt WDIRQ f 2 6 _ 7 Figure 9 1 Watchdog Block Diagram The watchdog timer is also used to count the oscillation stabilization wait It functions as a time out timer except when a reset is cleared or when returning from STOP mode For resets and in the STOP mode the watchdog timer is initialized and starts counting from its initial value x 0000 using the system clock fs as its clock source Set the oscillation stabilization wait in the oscillation stabilization wait control register DLYCTR After oscillation has stabilized it continues counting as a watchdog timer See section 2 14 Resets on page 43 Panasonic Semiconductor Development Company MN101C46F LSI User Manual 169 Panasonic Watchdog Timer Operation of the Watchdog Timer Once started the watchdog timer cannot be stopped 9 2 Operation of the Watchdog Timer 9 2 1 Watchdog Timer Function The watchdog timer counts using system clock fs as its clock source When the timer overflows it generates the watchdog interrupt WDIRQ as a nonmaskable interrupt NMI The watchdog timer stops at reset but once it is activated it cannot be stopped except by another reset Use the watchdog timer control register WDCTR to clear the timer and to set the time out period The watchdog timer can also detect software faults that repeatedly clear the watchdog timer in short per
31. 8 0 230 14 6 8 Bit PWM Output Waveform uu PS ec e 231 B 1 Memory Map for Internal Flash 237 B 2 PROM Writer Hardware Setup RR oth ew SU eae RR EE ERE 238 B 3 Pin Configuration for Socket 1 238 B 4 EEPROM Programming FlOW kA OES Le IE ROUEN a EOS e 239 MN101C46F LSI User Manual Panasonic Semiconductor Development Company xi Panasonic About This Manual Using This Manual About This Manual This manual is intended for assembly language programming engineers It describes the internal configuration and hardware functions of the MN101C46F and MN101CF46F microcontrollers Except where specified when this manual refers to MN101C46F it implies both products Using This Manual The chapters in this manual deal with the internal blocks of the MN101C46F Chapters 1 to 5 provide an overview of the MN101C46F s general specifications basic CPU functions interrupts I O ports and prescalar functions Chapters 6 to 10 describe the 8 bit timers on screen display analog to digital converter watchdog timer and closed caption decoder Chapter 11 describes the IR remote signal receiver Chapter 12 describes the ROM correction feature Chapter 13 describes the I C bus controller Chapter 14 describes the pulse width modulat
32. ANCHS2 EO ANBUF1 T ANLADE KS __ tz e ANBUET3 0 A D conversion ANSH1 ANST control f 7 7 ANBUF15 ANBUF16 ANBUF17 7 Y Vov 93 ADINO ADIN1 gt 5 ADIN2 Y_ A D conversion Sample hold S AD comparar 9218 ADINA ample hol bit A D comparato ADIN5 ADIN6 ADIN7 Vss g 2 i 5 4 15 8 MUX gt 1 2 gt fyx2 gt 16 MUX gt 118m7 Figure 8 1 ADC Block Diagram MN101C46F LSI User Manual Panasonic Semiconductor Development Company 160 Panasonic Analog Digital Converter Analog to Digital Conversion Operation 8 3 Analog to Digital Conversion Operation The operation of the analog to digital conversion circuit is described below 1 Setup the Analog Pins Use the port input mode register to set the pins that will be set up as analog input pins in step 2 as special function pins Complete the port input mode register setup before applying an analog voltage to the pins 2 Select the Analog Input Pin Select the analog input pin from among ADINT7 ADINO using the ANCHS 2 0 field of A D control register 1 ANCTR1 3 Select the A D Conversion Clock Select the A D conversion clock using the ANCK 1 0 field of A D control register 0 ANCTRO Set so that the oscillator you are using does not result in a conversion clock tap of 800 ns or below 4 Setthe
33. General Description Circuit Design Considerations P ch Input pin TI Current Through current Input 0 3 3 Input voltage at Vpp 3 3 V A Structure B Characteristics Figure 1 13 Input Inverter Structure and Characteristics 1 6 2 4 Handling Unused Pins I O Pins First check the reset value of any unused I O pins If the pin output is supposed to be high impedance after a reset output is off for both P channel and N channel transistors insert a resistor of at least 10 kO to pull the pin up or down so that input is not unstable If the pin output is on after a reset leave the pin open Output Output control Several control 10 kQ Output OFF Output OFF Data Data Severa Input Input 10kQ Output OFF Output OFF Several 10 kQ Data Severa 10 kQ Figure 1 14 Handling Unused Pins Output Is Hi Z at Reset MN101C46F LSI User Manual Panasonic Semiconductor Development Company 16 Panasonic General Description Circuit Design Considerations 1 6 3 Turning on Power 1 6 3 1 Power and Input Pin Voltage Design circuits so that voltage is supplied to input pins after the microcontroller has powered up Reversing this order may cause latch ups in the microcontroller which can lead to damaging high currents Input protection Input resistor Forward current produced P N supply Figure 1 15 Power and Input Pin Voltage 1 6 3 2 Power a
34. OSCM ACT DLY WD MEM CPUM x 03F00 D MD Gre CPU mode and memory control P4OU P3OU P20U PIOU POOU T O port output x O3F10 u M T 5 P4MD P3MD P2MD PIMD POMD PAIN P3IN P2IN POIN i x O3F20 I O port input 5 PADIR P3DIR P2DIR PIDIR PODIR x 03F30 CEN port I O mode control PCNT PCNT PAPL P3PL P2PL PIPL POPL x 03F40 0 U w I O port pullup resistor control o3pso C M CK2M TM3M TM2M TMSO TM2O TM3B TM2B x p p p p c c c c tol 03F60 PSCM CK4M TM4M TM4O TM4g mer contro x D D D 03 70 AMC AMC AMC AMC AMC AMC AMC AMC AMC AMC AMC AMC AMC AMC AMC x HIM7 HIM6 HIL6 HIMS HIL5 HIM4 HILA HIM3 HIM2 HIL2 HIMI HILI HMO HILO O3rgo AMC AMC AMC AMC AMC AMC AMC AMC AMC AMC AMC AMC AMC AMC AMC AMC hoy correction control 1 Correction address x HILF HIME HILE HIMD HILD HIMC HIMB HILB HIMA HILA HIM9 HIL9 HIM8 HIL8 correction contiol T feprrecion address 03Fo0 AMC AMC AMC AMC AMC AMC AMC AMC AMC AMC AMC AMC AMC AMC x HIHD HIH9 HIH8 HIH7 6 5 HIH4 HIH3 2 HIHO x 03FA0 Serial interface control AN AN AN AN x 03FBO DUET CTR2 CIRT CERO Analo
35. Panasonic MN101C46F LSI User Manual Closed Caption Decoder Closed Caption Decoder Registers Table 10 9 Closed Caption Decoder Registers CCD0 CCD1 Register Address Address R W Description NFSELH x 03E41 x 03E61 Noise filter select register high NFSEL 03 40 x 03E60 R W Noise filter select register FQSELH x 03E43 x 03E63 R W Frequency select register high FQSEL 03 42 03 62 Frequency select register SCMINGH x 03E45 x 03E65 R W Minimum sync level detection interval set reg ister high SCMING x 03E44 x 03E64 R W Minimum sync level detection interval set reg ister BPPSTH 03 47 x 03E67 R W Backporch position register high BPPST x 03E46 x 03E66 R W Backporch position register SYNCMIN x 03E48 x 03E68 R Minimum sync level register BPLV 03 49 x 03E69 R Pedestal level register SPLVH x 03E4B x 03E6B Sync separator level set register high SPLV x 03E4A x 03E6A R W Sync separator level set register CLAMPH x 03E4D x 03E6D R W Clamping control register high CLAMP x 03E4C x 03E6C R W Clamping control register HSEP1H x 03E4F x 03E6F R W HSYNC separator control register 1 high HSEP1 x 03E4E x 03E6E R W HSYNC separator control register 1 HSEP2H x O3EST x 03E71 R W
36. BSP4 BSP3 BSP2 BSP1 BSPO PSP5 PSP4 PSP3 PSP2 PSP1 PSPO Reset 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 RW R RW RA RW RW RW RW R RW RW RW RW RW The sync separator uses the value set in these registers to separate the com posite sync signal from the composite video signal Video signal Setting for sync P separator level Composite sync processing Figure 10 14 Sync Separator Level Panasonic Semiconductor Development Company MN101C46F LSI User Manual 193 Panasonic Closed Caption Decoder Closed Caption Decoder Registers Composite signal from ADG Compare Composite sync dc pus MUX CLMODE BSP Figure 10 15 BSP and PSP Multiplexing BSP 5 0 Sync separator level for pedestal clamping Sync separator level sync tip level 2 BSP 5 0 The valid range is x 00 tox IF PSP 5 0 Sync separator level for sync tip clamping Valid range x 00 to x 1F CLAMPH Clamping Control Register High x 03E4D CLAMPWH Clamping Control Register High x 03E6D CLAMP Clamping Control Register x 03E4C CLAMPW Clamping Control Register x 03E6C Bit 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 CL CL PCLV6 PCLV5 PCLV4 PCLV3 PCLV2 PCLVI PCLVO SAFE bn MODE MODE 1 0 Reset 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R RW RW RW RW RW RW RW R W R R R W R R R W R W
37. Changed bit numbers in table 12 3 1 12 10 Clarified that the ROM correction function cannot be emulated in ICE mode Revision 1 10 to Revision 1 20 July 19 1999 Page in Japanese Description of Revision Chapter 0 Abo ut This Manual 0 4 Changed example page from image taken from MN101C12G to one from 101 46 Chapter 10 Closed Caption Decoder 10 5 Changed 24 P25 25 to P26 VREFHS to VREFHO VREFLS to VREFHI 10 19 Added description of slice level calculation control register SLCNT 10 33 10 34 Added description of slice level calculation control register SLCNT 10 39 Added slice level calculation control register SLCNT Chapter 11 IR Remote Signal Receiver 11 3 In figure 11 1 1 added description of PWM input in SLOW mode 11 5 Added description of RMTC register setup in SLOW mode 11 16 Added description of RMTC register setup in SLOW mode Chapter 14 Pulse Width Modulator 14 1 Deleted 8 bit from chapter title 14 2 to 14 7 Described 14 bit PWMs 14 8 to 14 10 Described 8 bit PWMs 14 2 Added bus width in figure 14 1 1 14 4 Revised reset values for TDCHL and TDCCLL registers 14 6 Revised table 14 1 1 and figure 14 1 9 14 7 Changed 11 to b 11 and 00 to b 00 Panasonic
38. E e REY RERUM SUCEDE TRI 202 11 3 4 Identifying the Data 7 203 11 3 5 Generating Interr pts ees aqu uya eet SERIE er op dre 204 11 3 5 1 Leader Detection eie eee Lp RC p EUR RR E RR kusa 204 11 3 5 2 Trailer Detection ue eere FUMER EIN er NEUE 204 11 3 5 3 8 Bit Data Reception 204 11 3 5 4 Pin Edge Detection uuu eese eee HR eR MERE baw bee wide 204 11 4 IR Remote Signal Receiver Control 205 12 ROM Correction 209 12 1 Descriptions yku 209 12 2 Block Diagram abel ee XV Ib 210 12 3 Programming 0 7 210 124 ROM Correction Control 211 13 2C Bus Controller se Lat Qua kaqq aa cnet ae 213 13 1 Descriptions n S SIENTE e UB teu 213 MNI101C46F LSI User Manual Panasonic Semiconductor Development Company Panasonic Contents 13 2 Block Diagram au meneen Kua ee ee pao REPRE EIDEM AERE UT EE 216 13 3 Functional
39. P2MD5 P2MD4 P2MD3 P2MD2 P2MD1 P2MDO P27 function switch 0 P27 1 VREFHO P26 function switch 0 P26 1 CVBSO P25 function switch 0 P25 1 CVBS1 P24 function switch 0 P24 1 VREFHI P23 function switch 0 P23 1 CLH P22 function switch 0 P22 1 CLL P21 output switch 0 21 4 1 PWMS IRQ4 P20 output switch 0 P20 IRQ3 1 PWMA IRQ3 I O Ports I O Port Control Registers x 03F2A Panasonic Semiconductor Development Company 89 Panasonic MN101C46F LSI User Manual I O Ports I O Port Control Registers P3MD Port 3 Output Mode Register Bit F Reset 0 6 4 3 2 1 0 P3MD7 P3MD6 P3MD5 P3MD4 P3MD3 P3MD2 P3MDI P35MDO 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W P3MD is an 8 bit access register PSMDT PSMD6 PSMD5 PSMD4 PSMD3 PSMD2 P3MD1 PSMDO P37 function switch 0 P37 IRQ5 1 NSYNC IRQ5 This bit exists but contains no function P35 output switch 0 P35 1 YM P34 output switch 0 P34 1 ROUT P33 output switch 0 P33 1 GOUT P32 output switch 0 P32 1 BOUT P31 output switch 0 P31 1 YS P30 function switch 0 P30 1 NHSYNC x 03F2B MN101C46F LSI User Manual 90 Panasonic Panasonic Semiconductor Development Company I O Ports I O Port Control Registers PAMD Port 4 Output Mode Register x O3F2C Bit T 6 4 3 2 1 0
40. QN CO CO IRQ1 ADIN1 P03 lt gt 24 Vss re oOoO O0oooo Oo toot 22460 6 0 gt 2 2 S zzu xz 009 d aa eB ooo amp g gt 0 0 S oS 8 B c P01 P02 P14 P21 P41 and P42 are 5 V N channel open drain pins Vpp port in flash ROM mode Vpp port in mask ROM mode MMOD tied high sets test mode pin to normal mode FLASH tied low sets flash mode pin to normal mode Figure 1 2 MN101C46F Pin Configuration N C N C FLASH 4 N C P31 YS P32 BOUT P33 GOUT P34 ROUT P35 YM P36 NRST N C P37 NVSYNC IRQ5 N C P40 PWM N C N C Panasonic Semiconductor Development Company 5 Panasonic MN101C46F LSI User Manual General Description Pin Description 1 4 2 Pin Description Table 1 3 Pin Description Block Pin Name lO Pin Count Description Vpp I 1 Voltage supply Apply 3 0 to 3 6 V Vss I 1 Ground reference Connect directly to external ground Power Voltage supply Vpp in mask ROM version and Vpp in Vpp Vpp I 1 N EEPROM version SYSCLK O 1 System clock output Clocks OSCI I 1 Oscillator input connection OSC2 O 1 Oscillator output connection Reset NRST T O 1 Reset alt function P36 External interrupt request to microcontroller alt functions POO Interrupts external IRQ0 IRQ5 I 6 P03 P17 P20 P21 P37 NHSYNC I 1 Horizontal sync signal input NVSYNC I 1 Vertical syn
41. Reset 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W Reserved Always set to 0 MIE Maskable interrupt enable 0 Disables all maskable interrupts 1 Enables interrupts individually xxxLVn xxxIE IM 1 0 Interrupt mask level VF Overflow flag NF Negative flag CF Carry flag Control acceptance of maskable interrupts 0 No overflow occurred 1 An overflow occurred 0 The MSB of the operation result is a 0 1 The MSB of the operation result is a 1 0 The MSB did not produce a carry up or down 1 The MSB produced a carry up or down ZF 0 flag 0 The operation result is not all zeros 1 The operation result is all zeros Panasonic Semiconductor Development Company 27 Panasonic MN101C46F LSI User Manual Basic CPU Functions Operations Registers Maskable Interrupt Enable Flag MIE This flag enables maskable interrupts Maskable interrupts are accepted when MIE is 1 When MIE is 0 all maskable interrupts are disabled regardless of the interrupt mask level IM 1 0 within the PSW Interrupts do not change MIE Interrupt Mask Level Field IM 1 0 The interrupt mask level field IM 1 0 controls acceptance of maskable interrupts according to the interrupt level of the interrupt source The 2 bit field defines levels 0 through 3 Level 0 is the highest interrupt mask level Interrupt requests are accepted only when the level set in the interrupt level flag xxxLVn of the interrup
42. Table 6 5 Procedures for Setting up a Cascade Connection Procedure Description 1 Check that counters are stopped TM2MD x 03F5C bit 3 TM2EN 0 TM3MD x 03F5D bit 3 TM3EN 0 1 Set the TM2EN flag of the timer 2 mode register TM2MD and the TM3EN flag of the timer 3 mode register TM3MD to 0 to stop the count in both timers 2 Setup the cascade connection TM3MD x 03F5D bit 4 TM3CAS 1 2 Set the TM3CAS flag in the TM3MD regis ter to 1 to cascade timers 2 and 3 3 Select count clock source TM2MD x 03F5C bits 1 0 TM2CK 1 0 01 3 Use the TM2CK 1 0 flag of the TM2MD register to select prescalar output as the clock source 4 Select prescalar output and enable it CK2MD x 03F5E bits 2 1 TM2PSC 1 0 201 bit O TM2BAS 1 PSCMD 03 6 bit O PSCEN 1 4 Use the TM2PSC 1 0 field and the TM2BAS flag of the timer 2 prescalar select register CK2MD to select fg 4 as the prescalar output Also set the PSCEN flag in the prescalar control register PSCMD to 1 to enable the prescalar count 5 Set the period for generating the interrupts TMnOC x 03F5B x 03F5A x 09C3 5 Set a value for the interrupt generation period in the timer 1 compare register and timer 0 compare register TM3OC TM20C Since we are using 2500 divi sions set to x 09C3 2500 1 The timer 3 binary counter and timer 2 binary counter TM3BC 2 will be initialized
43. 0 Interrupt vector base 04000 1 Interrupt vector base x 00100 EXMEM Switches external memory expansion mode 0 Do not expand to external memory 1 Disabled EXWH Switches between fixed wait mode and handshake mode 0 Disabled 1 Fixed wait mode IRWE Sets software writing of interrupt request flag 0 Writing with software disabled The state of the interrupt request flag xxxIR does not change even if data is written to an interrupt con trol register xxxICR 1 Writing with software enabled EXW 1 0 Set fixed wait states 00 No waits 279 3 ns with 14 32 MHz bus cycle 01 Setting disabled 419 0 ns with 14 32 MHz bus cycle 10 Two waits 558 6 ns with 14 32 MHz bus cycle 11 Setting disabled 698 3 ns with 14 32 MHz bus cycle A The wait space for the EXW 1 0 applies to devices connected to the CSIC inter e face Three waits are inserted when the reset is cleared Be sure to set the start of the initialization routine to either no waits or two waits The wait space for IOW 1 0 is the special register area I O space at x 03F00 x 03FFF Three waits are inserted when the reset is cleared Be sure to set the start of the initialization routine to either no waits or two waits Select no waits for high performance system architectures Panasonic Semiconductor Development Company MN101C46F LSI User Manual 35 Panasonic Basic CPU Functions Standby Fun
44. 03F33 Bit 7 6 5 4 3 2 1 0 PnDIR7 PnDIR6 PnDIRS PnDIR4 PnDIR3 PnDIR2 PnDIRI PnDIRO Reset 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W P4DIR Port 4 I O Control Register x 03F34 Bit 6 5 4 3 2 1 0 0 0 0 0 0 P4DIR2 PADIRI PADIRO Reset 0 0 0 0 0 0 0 0 R W R R R R R R W R W R W The PnDIR registers control the I O direction of the ports The bit number corresponds to the associated pin number For instance PODIR7 applies to the P07 pin These 8 bit access registers 0 Input 1 Output MN101C46F LSI User Manual Panasonic Semiconductor Development Company 86 Panasonic POMD Port 0 Output Mode Register I O Ports I O Port Control Registers x 03F28 Reset 0 Bit 6 4 3 2 1 0 POMD7 POMD6 POMDS POMD4 POMD3 POMD2 POMDI POMDO 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W POMD is an 8 bit access register POMDT POMD6 POMDS POMD4 POMD3 POMD2 POMD1 POMDO P07 function switch 0 07 1 ADIN4 P06 function switch 0 06 1 ADIN3 P05 function switch 0 05 1 ADIN2 P04 function switch 0 P04 1 ADINI P03 function switch 0 1 1 ADINO IRQI P02 function switch 0 02 1 SCLI1 P01 function switch 0 POI 1 SDAI output switch 0 POO IRQO 1 RMIN IRQO Panasonic Semiconductor
45. 1 Noise filter POLSEL Input polarity 0 Positive edge triggered 1 Negative edge triggered LEADERE Interrupt enable for leader detection 0 Disable Enable TRAILRE Interrupt enable for trailer detection 0 Disable 1 Enable DAT8E Interrupt enable for 8 bit data reception detection 0 Disable 1 Enable EDMEE Interrupt enable for RMIN pin edge detection 0 Disable 1 Enable MN101C46F LSI User Manual Panasonic Semiconductor Development Company 206 Panasonic IR Remote Signal Receiver IR Remote Signal Receiver Control Registers RMIS Remote Signal Interrupt Status Register x 03EA0 Bit F 6 5 4 3 2 1 0 BG BC FMT DOMES MS6BIT TRAILR DAT8 EDGE RSTE EDGS MON D D D D D Reset 0 0 0 0 0 0 0 0 R W R W R W R R W R W R W R W indicates the detection operation status of remote signal inter rupts It is an 8 bit access register BCRSTE 8 bit data reception binary counter reset enable 0 Disable 1 Enable BCEDGS 8 bit data reception binary counter reset edge select 0 Reset at lst edge 1 Reset at 2nd edge FMTMON Format monitor 0 HEAMA format 1 5 6 bit format DOMESD Interrupt request on HEAMA leader detection 0 Norequest Request M56BITD Interrupt request on 5 6 bit leader detection 0 Norequest Request TRAILRD Interrupt request on trailer detection 0 Norequest Request DATS8D Interrupt request on 8 bit rece
46. 1 V shutters 0 and 1 on HSONO HSON1 1 H shutters 0 and 1 on VSPO 0 V shutter 0 shutters below VSP1 1 V shutter 1 shutters above HSP0 0 H shutter 0 shutters to the right HSP1 1 H shutter 1 shutters to the left SHTRAD 1 All shutters ORed VSONO VSON1 1 V shutters 0 and 1 on HSONO HSON1 1 H shutters 0 and 1 on VSPO 1 V shutter 0 shutters above VSP1 0 V shutter 1 shutters below HSPO 1 H shutter 0 shutters to the left 0 H shutter 1 shutters to the right SHTRAD 1 All shutters ORed VSONO 0 V shutter 0 off VSON1 1 V shutter 1 on HSONO HSON1 1 shutters 0 and 1 on 1 V shutter 0 shutters above VSP1 0 V shutter 1 shutters below 1 shutter 0 shutters to the left 0 H shutter 1 shutters to the right SHTRAD 1 All shutters ORed Figure 7 18 Shuttered Area Setup Examples MN101C46F LSI User Manual Panasonic Semiconductor Development Company 138 Panasonic On Screen Display Controlling the Shuttering Effect 7 10 2 Controlling Shutter Movement Enabling the shutter movement function in the registers allows the shuttered area to expand or contract over time producing a wipe in or wipe out effect This allows the OSD display to appear or disappear without an abrupt transition Table 7 9 shows the register settings required for this function and figure 7 19 shows four setup examples There is no repeat operation for shutter mo
47. 3 38 MODE 1014 4 37 A15 013 5 36 A14 1012 6 35 A13 Voti 7 34 A12 010 8 33 11 vo9 9 32 A10 vos 10 31 A9 ERASE 11 30 Vss 107 12 29 A8 13 28 A7 o5 14 27 A6 4 15 26 A5 1 03 16 25 A4 102 17 24 vo1 38 23 A2 VO0 19 22 A1 NOE 20 21 Figure B 3 Pin Configuration for Socket Adaptor MN101C46F LSI User Manual Panasonic Semiconductor Development Company 238 Panasonic MN101CF46F Flash EEPROM Version Reprogramming Flow B 4 Reprogramming Flow Figure B 4 shows the flow for reprogramming erasing and programming the flash memory Write Os to entire memory Erase routine Reverse Write user program Figure B 4 EEPROM Programming Flow As the figure shows the write occurs after the memory is completely erased The erase routine consists of three steps first writing all zeros to the entire memory space next erasing the memory and finally reversing B 5 Programming Times Table B 1 shows the time required for PROM reprogramming erasing and pro gramming Table B 1 Programming Times for PROM Writers Programming Time Reprogramming Writer User Program Only Time DATA I O LabSite DIP48 1 4 provisional Panasonic Semiconductor Development Company MN101C46F LSI User Manual 239 Panasonic MNIOIC Series Instruction Set Appendix C MNIOIC Series Instruction S
48. 3 4 1 Interrupt Handling Sequence 5 u sss s RE MES ME ENE 49 3 4 2 Interrupt Vector Addresses and Interrupt Groups 50 3 4 3 Interrupt Levels and Priorities u asa suwasqa sas III 51 3 4 4 How Interrupts Are Accepted 51 3 4 5 Interrupt Acceptance 53 3 4 6 Interrupt Return 212 54 3 4 7 Maskable Interr pts uu TH RES Er assqa e eem 55 3 4 8 Nested Interrupts us s a tu ane erg em EUR Rr RACHEL S E 56 3 5 Setting the Interrupt Flags l l pus aa us I e 58 3 5 1 Using Software to Rewrite Interrupt Request Flags 58 3 5 2 Setting the Interrupt Flags u asss usya ss IA lt 58 3 6 Interrupt Control Registers 14 0 4 59 4 ee ed ese ban tee RC res eu Cere Mae Ae 66 4 1 Description oov sien pete nue plates Fed ee Selb EN P LL Per PIENE PIER Slane 66 4 2 TO Port Circuit Diagrams oes sss iah ha pasu bu me ae 67 4 3 TO Port Control Registers i eee eer rr oer ee e ede S Eae cen ees 85 Panasonic Semiconductor Development Company MN101C46F LSI User Manual ii Panasonic Contents 5 Pre
49. ADIN3 P06 7 P40 PWM ADIN4 P07 8 P37 NVSYNC IRQ5 ADIN5 P10 9 P36 NRST ADIN6 P11 1 P35 YM ADIN7 P12 42 SDIP P34 ROUT 3 MMOD Top View P33 GOUT SYSCLK P13 P32 BOUT 1 PWMO P14 P31 YS PWM1 P15 FLASH 4 PWMe2 P16 P30 NHSYNC IRQ2 PWMS P17 P27 VREFHO IRQ3 PWM4 P20 26 50 1 04 PWMS P21 P25 CVBS1 Vpp P24 VREFH1 CLL P22 P23 CLH Notes 1 POI P02 P14 P21 P41 and P42 are 5 V N channel open drain pins 2 Vpp port in flash ROM mode Vpp port in mask ROM mode 3 MMOD tied high sets test mode pin to normal mode 4 FLASH tied low sets flash mode pin to normal mode Figure 1 1 MN101C46F Pin Configuration MNIOICA46F LSI User Manual Panasonic Semiconductor Development Company 4 Panasonic General Description Pin Description N C N C PWM1 P15 N C 1 PWM0 P14 SYSCLK P13 N C 3 MMOD ADIN7 P12 ADING P11 ADIN5 P10 N C ADIN4 P07 ADIN3 P06 N C N C Notes mom CN 1 GGG coe 9 a Trot See quien D z zzz x mr gt gt I gO0200 2 2 2 lt GN 0 0 0 vt GN OD O O O LO LO LO LO LO LO LO LO LO O st 1 O 48 2 47 3 46 4 45 5 44 6 43 7 42 8 64 Pin LQFP 41 9 Top View 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 000 O O Tov 0 GQ CM QN
50. Area Text ROM CROMEND 24x M 1 1 CROMEND GROMEND 6 lt N 1 1 Graphics ROM GROMEND Notes m 0 and up SO Y TS n 0 and up 7 GROMEND 6 lt N 1 1 7 6 ROM 7 6 1 ROM Organization Text ROM Addresses Each character requires 36 bytes Text character lt 16 bits e 1 Line 1 Line 2 Line 3 requires 108 bytes 8 color mode Code N 1 dot 3 bits ode 8 colors graphics data GROMEND 6cxN E 7 CROMEND 24x M 1 1 ae Line 18 oss Code M 4 CROMEND 24m _ text data Bit 15 Bit 0 CROMEND 23 Line tbits7t0o0 i CROMEND 22 Line 1 bits 15 to 8 CROMEND 24x m 1 H CROMEND 21 CROMEND 20 Line 2 bits 15 to 8 text data s Line 2 bits 15108 CROMEND Saum CROMEND 1F Line 3 bits 7 to 0 EN is CROMEND 47 Code 01 CROMEND 24 text data CROMEND 23 Code 00 CROMEND 1 Line 18bits 7toO _ _ 181 7 croweno Line 18 bits 15to8 1 byte y_ Graphics ROM Addresses Graphics tile lt 16 bits gt TS In 8 color mode each tile 1 116 eet eet 2 Sheet 1 Bit 15 Bit 0 eet 4J lt Line 2 3 Line 3 Line 18 8 color mode GROMEND 6 x n 41 4 GROMEND 6B eni Coden Line 1 data GROMEND 66 graphics data GROMEND 65 Line 2 data GROMEND 6 xn GROMEND 60 GROMEND SF Line 3 data Line 17 data GROMEND 06 108 bytes GR MEND 0
51. BGE label if VF NF 0 PC 5 d1 label HPC 5 2 3 1001 1000 lt fl 2 3 102 if VF NF 1 PC 5PC BCC label if CF 0 PC 4 d7 label H PC 4 12 3 1000 1100 d7 2 103 if CF 1 4 label if CF 0 PC 5 d11 label H gt PG 5 23 1001 1100 lt 911 3 103 if CF 1 PC452PC BCS label if CF 1 PC 4 07 label H gt PC 4 12 3 1000 1101 d7 H 2 104 if CF 0 4 BCS label if CF 1 PC 5 d11 label HPG 5 23 1001 1101 dii H 8 104 if CF 0 PC452PC BLT label if VF NF 1 PC 4 d7 label H gt PC 4 23 1000 1110 d7 2 105 0 4 BLT label if VF NF 1 PC 5 d1 1 label HsPC 5 2 8 1001 1110 dii 8 105 if VF NF 0 PC 5PC BLE label if VF NF ZF 1 PC 44 d7 label HPG 4 2 3 1000 1111 d7 H 2 106 if VF NF ZF 0 PC 4PC BLE label if VF NF ZF 1 PC 5 d1 1 label HPG 5 12 3 1001 1111 dii 3 106 if VFANF ZF 0 PC 5PC BGT label if VF NF ZF 0 PC 5 d7 label HPG 5 3 4 0010 0010 0001 d7 H 2 107 if VFANF ZF 1 PC 5PC NOTE Pages for MN101C Series Instruction Manual 4 04 sign extension 2 47 sign extension 3 11 MN101C46F LSI User Manual Panasonic Semicond
52. BLINK of the COL field causes all characters following that COL to blink To use this function you must enable blinking by writing a 1 to bit 5 BLINK of the OSD3 register x 03EBA In closed caption mode you can specify whether or not the underlines blink on underlined blinking characters Set bit 1 UNDP of the OSD3 register to 0 to disable underline blinking or set it to 1 to enable underline blinking The blink cycle lasts for 128 VSYNC pulses about 2 seconds The characters display for 96 VSYNCS about 1 5 seconds and turn off for 32 VSYNCS about 0 5 seconds Panasonic Semiconductor Development Company MN101C46F LSI User Manual 131 Panasonic On Screen Display Setting up the OSD 7 7 3 Display Sizes Graphic tile sizes x 1 x2 x3 x4 b 00 b 01 b 10 b 11 HSZ 1 0 gt b 00 1 b 01 x2 b 10 x4 b 11 T x6 HH H VSZ 1 0 Y The settings shown are for interlaced displays In progressive displays the vertical size settings VSZ 1 0 are as follows 01 10 2x and 11 3x The 00 setting is invalid Figure 7 1
53. BVC label if VF 0 PC 5 07 label H gt PC 5 34 0010 0010 0110 lt d7 H 2 114 if VF 1 PC 5 gt PC BVC label if VF 0 PC 6 d11 label H3PC 6 34 0010 0011 0110 lt fl 114 if VF 1 PC 6 gt PC BVS label if VF 1 PC 5 d7 label H gt PC 5 3 4 0010 0010 0111 lt d7 H 2 113 if VF 0 PC 53PC BVS label if VF 1 PC 6 d1 1 label H3PC 6 34 0010 0011 0111 dil iftVF 0 PC 6 PC BRA label PC 3 d4 label H PC 3 1110 111H lt d4 gt 114 BRA label PC 4 d7 label H PC 4 1000 1001 d7 H 2 114 BRA label PC 5 d11 label H PC 513 1001 1001 dii 3 119 CBEQ CBEQ imm8 Dm label if Dm imm8 PC 6 d7 labe H2OPC e e e 6 3 4 1100 10Dm 48 gt lt d 2 1114 if Dmzimm8 PC 62PC CBEQ imm8 Dm label if Om imm8 PC 8 d11 label H4PC e e e 8 45 0010 1100 10Dm 48 gt dii 119 if Dm imm8 PC 8 PC CBEQ imm8 abs8 label _ if mem8 abs8 imm8 PC 9 d7 label HPC e 9 6 7 0010 1101 1100 abs 8 gt 48 gt lt 07 2 1111 if mem8 abs8 zimm8 PC 92PC CBEQ imm8 abs8 label ifmem8 abs8 imm8 PC 10 d11 labe H gt PC e e 10 6 7 0010 1101 1101 abs 8 48 gt dii 8 117 if mem8 abs8 imm8 PC 10 PC CBEQ imm8 abs16 label if mem8 abs16 inm8 PC 11 d7 abel HPCl 6 11 7 8 0011 1101 1100 abs 16 gt lt 8 gt lt d7 2 118 if memB8
54. FIELD FIELD HSEP Sync separator 2 registers x 03E70 NDIW NDIW WH W TWW TWW CKL CKL WH W 2WH 2W H H VWH VW MN101C46F LSI User Manual Panasonic Semiconductor Development Company 32 Panasonic Basic CPU Functions Memory Space Table 2 7 Register Map x 03D00 x 03EFF Continued 16 4 LSBs MSBs F E D C B A 9 8 7 6 5 4 3 2 1 0 Description DC DC DC pc pc pc pc x 03E80 BSTS BRST CLK MYA DREC DREC DTRM DTRM C interface registers D H H TDCH TDCL TDCC PWM5 PWM4 PWM3 PWM2 PWMI PWMO x 03E90 R PWM registers 5 RMLD RMTR RMSR RMCS RMTC RMIR RMIS x 03EA0 Remote signal receiver registers EVOD EVOD HCOU HCOU OSD3 OSD2 OSDI RAME GRO CRO x 03EBO H NTH NT ND MEN D D x O3pgco APH IVPH IHPH SHTC HSHT HSHT HSHT HSHT VSHT VSHT VSHT VEHT IH 1 0 IH 0 n WBSH BBSH FRAM COLB isters x 03ED0 OSD control registers D D E x 03EE0 PLT 7 PLT16 PLT15 PLT14 PLT13 PLT12 PLTO PLT10 PLTO7 PLTO6 PLTO5 PLTO4 PLTOS PLTO2 PLTO PLTOO x oagpo PUT37 PLT36 PLT35 PT34 PTS PLT32 PLT31 PLT30 PLT27 PLT26 PLT25 PLT24 PLT23 PLT22 PLT21 PLT20 F OSCM ACT DLY WD MEM CPUM x 03F00 D MD em erel CPU mode and memory control
55. HDIST HDIST HDIST HDIST HDIST HDIST HDIST HDIST HDIST W8 WT W6 WS WA 2 wl wo Reset R W Bit 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 R R R R R R R R W RW RW RW RW RW RW RW HDISTW 8 0 HSYNC count setting the interval for sync separation detection In these registers set the interval during which sync separation occurs The valid range is x 000 to x 1FF commend value x 1007 Reset R W Bit Reset R W VCNTH VSYNC Separator Control Register High x 03E59 VCNTWH VSYNC Separator Control Register High x 03E79 VCNT VSYNC Separator Control Register x 03E58 VCNTW VSYNC Separator Control Register x 03E78 Jj 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 VSEP VSEP VSEP VSEP SEL LMT2 LMTI LMTO 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 R R R R R R R R W R R R R R RW RW RW VSEPSEL VSYNC signal select 0 OH to 127H VSYNC separation mask 1 No mask VSEPLMT 2 0 VSYNC separation detection threshold HVCOND Sync Separator Status Register x 03E5A HVCONDW Sync Separator Status Register x 03E7A 7 6 5 4 3 2 1 0 STPN ou VSEP HSEP HLOCK 0 0 0 1 1 0 0 0 R R R Use this register to monitor the status of the sync separator MN101C46F LSI User Manual Panasonic Semiconductor Development Company 196 Panasonic Cl
56. NFSELH Noise Filter Select Register High 03 41 NFSELWH Noise Filter Select Register High x 03E61 NFSEL Noise Filter Select Register x 03E40 NFSELW Noise Filter Select Register x 03E60 Bit 7 6 5 4 3 2 1 0 7 6 5 4 2 1 0 MING aus ion Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R R R R R R R R W R R R R R R R W R W These registers select the low pass filter which eliminates noise and high frequency signals that are unnecessary to the sync separator and the clamp ing controller The recommended settings for NFSELH and NFSEL are x 0 and x 00 MING Output select for noise filter detecting minimum sync tip 0 Low pass filter 1 1 Low pass filter 2 3 or 4 set in NFSW 1 0 NFSW 1 0 Noise filter switch for composite sync separator 00 Low pass filter 3 01 Low pass filter 4 10 Low pass filter 2 11 Low pass filter 1 The cutoff frequencies for low pass filters 1 to 4 are lower in ascending order so that low pass filter 4 eliminates the highest amount of noise FQSELH Frequency Select Register High x 03E43 FQSELWH Frequency Select Register High x 03E63 FQSEL Frequency Select Register x 03E42 FQSELW Frequency Select Register x 03E62 Bit 7 6 5 4 3 2 1 0 7 6 5 4 2 1 0 _ VFQ VFQ VFQ VFQ ES FQ FQ FQ FQ DIV5 DIV4 DIV3 DIV2 D
57. P4OU P3OU P2OU P1OU P0OU T O port output x 03F10 T T T T P4MD P3MD P2MD PIMD P0MD PAIN P3IN P2IN PON i x O3F20 T O port input F ROM ROM PADIR P3DIR P2DIR PLDIR PODIR x 03F30 CENH CEN I O port I O mode control R PCNT PCNT P4PL P3PL P2PL PIPL POPL x 03F40 2 0 U I O port pullup resistor control x O3pso CK9M CK2M TM3M TM2M TM3O TM2O TM3B TM2B D D D D PSCM CK4M TM4M TM4O TM4B x 03F60 5 D 5 x 03F70 AMC AMC AMC AMC AMC AMC AMC AMC AMC AMC AMC AMC AMC AMC AMC HIM7 HIM6 HIL6 HIMS HILS HIM4 HIL4 HIM3 HIL3 2 HIL2 HIMI HIL1 HIMO HILO x 03F80 AMC AMC AMC AMC AMC AMC AMC AMC AMC AMC AMC AMC AMC AMC AMC ROM correction control 1 correction address HIMF HILF HIME HILE HIMD HILD HIMC HIMB HIMA HILA HIM9 HIL9 HIM8 HIL8 x 03F90 AMC AMC AMC AMC AMC AMC AMC AMC AMC AMC AMC AMC AMC AMC AMC HIHD HIHC HIHB HIHA 9 HIH8 HIH7 6 5 HIH4 HIH3 HIH2 HIHO x 03FA0 Serial interface control AN AN AN x 03FB0 mE eigo eret kero Analog interface control x O3FCO CH CH CH CH CH CH ROM correction c
58. PWM 8 bit I O control PWMn Figure 14 5 Block Diagram of 8 Bit PWM Notes fpwm fsyscLk 2 Output pulse cycle 2 fpyyy 143 us when fsyscrk 3 58 MHz Minimum pulse width 1 fpwm 0 56 us tr ow PWMn 1 x 0 56 us de peut xe MN101C46F LSI User Manual Panasonic Semiconductor Development Company 230 Panasonic Pulse Width Modulator 8 Bit Pulse Width Modulators 14 2 2 8 Bit PWM Output Waveform Figure 14 3 shows the 8 bit PWM waveform It is assumed that fsyscrk 3 58 MHz The 8 bit PWM output pulse width changes relative to settings of data reg isters in units of 28 fpwm cycles When it changes between the data settings 00 01 however it changes at double B data Corresponding output waveform 00 High level 01 143 us 0 56 us Low level FF Figure 14 6 8 Bit PWM Output Waveform Panasonic Semiconductor Development Company MN101C46F LSI User Manual 231 Panasonic Pulse Width Modulator PWM Registers 14 3 PWM Registers Register Address R W Description TDCC x O3E9C R W 14 bit PWM control register TDCHR x 03E9F w 14 bit PWM data register high TDCHL x 03E9EFE w 14 bit PWM data register low TDCHL x 03E9F R 14 bit PWM data latch high TDCHR x 03E9E R 14 bit PWM data latch low PWMO x 03E90 R W 8 bit PWM data register 0 PWMI x 03E92 R W 8 bit PWM data register 1 PWM2 x 03E94 R W 8 bit PWM data register 2 PW
59. Panasonic Semiconductor Development Company Basic CPU Functions Pipeline Processing 2 6 Pipeline Processing Pipeline processing refers to the reading and decoding of instructions simul taneous with instruction execution so that the next instruction is ready for pro cessing as soon as execution of the first instruction ends Pipeline processing allows instructions to execute continuously increasing speed of execution It is performed by the instruction queue and instruction decoder The instruction queue is a two stage instruction pre fetch buffer It is controlled so that whenever the queue is empty during a cycle of instruction execution the next instruction is fetched The first word of the instruction to be executed operation code is stored in instruction register during the last cycle of instruction execution At this time the next operand or operation code is fetched to the instruction queue so execution can begin immediately if a direct address da or immediate data imm is in the first cycle of the next instruction to be executed In some instructions such as jump instructions the instruction queue may be empty when the operation code to be executed next is stored in the instruction register during the last cycle The queue may therefore produce a wait of one machine cycle if the instruction queue is empty and a direct address da or immediate data imm is needed in the first cycle of the instruction to be executed H
60. d16 Am Dn mem8 d16 Am 71 4 0010 0111 1aDn lt d16 gt 33 Dn d4 SP Dn mem8 d4 SP 312 0111 01Dn lt d4 gt 2 33 MOV Dn d8 SP Dn mem8 d8 SP eit sal tas 5 3 0010 0111 01Dn d8 gt 3 34 MOV Dn d16 SP Dn mem8 d16 SP 7 4 0010 0111 00Dn di6 ETT 34 MOV Dn io8 Dn mem8 IOTOP io8 4 2 0111 OODn lt 08 gt 35 MOV Dn abs8 Dn mem 8 abs8 4 2 0101 01Dn abs 8 gt 35 MOV Dn abs12 Dnmeme8 abs12 5 2 0101 00Dn abs 12 gt 36 Dn abs16 8 5516 7 4 0010 1101 00Dn abs 16 gt 36 MOV 108 8 gt 8 08 6 3 0000 0010 i8 gt 8 gt 37 MOV imm8 abs8 imm8 mem 8 abs8 6 3 0001 0100 abs 8 48 gt 37 MOV imm8 abs12 imm8 mem8 abs12 713 0001 0101 abs 12 gt lt 8 gt 38 MOV imm8 abs16 imm8 meme8 abs16 9 5 0011 1101 1001 abs 16 gt 48 gt 38 Dn HA Dn mem 8 HA 2 2 1101 00Dn 39 MOVW MOVW An DWm mem16 An DWm 213 1110 00Ad 40 MOVW An Am mem16 An 5Am 81 4 0010 1110 10Aa 4 40 MOVW d4 SP DWm mem16 d4 SP gt DWm 3 3 110 011d lt d4 gt 2 41 MOVW d4 SP Am mem16 d4 SP gt Am 3 3 110 010a lt d4 gt 2 41 MOVW d8 SP DWm mem16 d8 SP gt DWm 51 4 0010 1110 0114 d8 gt 3 42 MOVW d8 SP Am mem16 d8 SP gt Am 51 4 0010 1110 010a
61. each Instruction Register direct Immediate value Register indirect Register relative indirect Stack relative indirect Absolute RAM short I O short Handy addressing The MN101C46F provides the addressing modes most frequently used by C compilers Data transfer instructions can use any of the addressing modes Since relative values can be specified in half bytes 4 bits instruction code can be shortened Handy addressing reuses addresses that have accessed memory so it can only be used with store instructions It can be combined with absolute addressing to shorten code There are seven addressing modes that can be used to transfer data to memory register indirect register relative indirect stack relative indirect absolute RAM short I O short and handy Two addressing modes can be used with operation instructions register direct and immediate value See the MNIOIC series instruction manual for details The MN101C46F uses a basic 8 bit data access You can use either an odd address or an even address to specify addresses for a 16 bit data access Panasonic Semiconductor Development Company 29 Panasonic MN101C46F LSI User Manual Basic CPU Functions Addressing Modes Table 2 5 Address Space Address
62. lt 08 gt 3 42 MOVW d16 SP DWm 16 016 5 gt 7 5 0010 1110 001d di6 m 43 MOVW d16 SP Am mem16 d16 SP gt Am 715 0010 1110 000a di6 a Zum 43 MOVW abs8 DWm mem16 abs8 2DWm 48 100 0114 abs 8 44 MOVW abs8 Am mem16 abs8 Am 4 3 100 010a abs 8 gt 44 MOVW abs16 DWm memti6 abs16 2DWm 7 65 0010 1100 0114 abs 16 gt 45 MOVW abs16 Am mem16 abs16 Am 7 5 0010 1100 010a abs 16 gt 45 MOVW DWn Am DWn mem16 Am 21 3 1111 00aD 46 MOVW An Am gt 16 314 0010 1111 10 46 MOVW DWn d4 SP DWn mem16 d4 SP 3 3 111 011D lt d4 gt 2 47 MOVW An d4 SP An mem16 d4 SP 3 3 111 010 lt 04 gt 2 47 MOVW DWn d8 SP DWn mem16 d8 SP 51 4 0010 1111 0110 d8 gt 3 48 MOVW An d8 SP An mem16 d8 SP 5 4 0010 1111 010A d8 gt 3 48 MOVW DWn d16 SP DWn gt mem16 d16 SP 7 5 0010 1111 001D d 6 s 49 MOVW An d16 SP An mem16 d16 SP 715 0010 1111 000A d 6 PEE 49 MOVW DWn abs8 DWn gt mem16 abs8 4 3 101 011D lt abs 8 gt 50 MOVW An abs8 An mem16 abs8 4 3 101 010 lt abs 8 gt 50 MOVW DWn abs16 DWn gt mem16 abs16 71 5 0010 1101 0110 abs 16 gt 51 MOVW An abs16 An memt16 abs16 7 5 0010 1101 010A abs 16 gt 51 MOVW DWn HA DWn mem 16 HA s pese 283 1001 010D 52 MOVW
63. 0 ROMCENH ROM Correction Enable Register High x 03F3F ROMCEN ROM Correction Enable Register x 03F3E Bit 7 6 5 4 2 1 0 7 6 5 4 3 2 1 0 RCEN RCEN RCEN RCEN RCEN RCEN RCEN RCEN RCEN RCEN RCEN RCEN RCEN H7 H6 H5 H4 H3 H2 H1 7 6 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RW R W RA RW RW RW RW RW RW RW RW RW RW RW RW RCENHn Address n ROM correction enable n 15 8 0 Disable 1 Enable RCENn Address n ROM correction enable n 7 0 0 Disable 1 Enable Panasonic Semiconductor Development Company MN101C46F LSI User Manual 211 Panasonic ROM Correction ROM Correction Control Registers AMCHIHn ROM Correction Address Match Register n High x o3F90 to x 03F9F Bit 7 6 5 4 3 2 1 0 CHAn CHAn 17 16 Reset 0 0 0 0 0 0 0 0 R W R R R R R R R W R W AMCHIHn are 8 bit access registers n 2 0 F CHAn 17 16 Correction address bits A17 to A16 A17 MSB AMCHIMn ROM Correction Address Match Register n Middle x 03F71 to x 03F8F Bit 7 6 5 4 3 2 1 0 CHAn CHAn CHAn CHAn CHAn CHAn CHAn CHAn 15 14 13 12 10 9 8 Reset 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W AMCHIMn are 8 bit access registers n 0 F CHAn 15 8 Correction address bits A15 to A8 AMCHILn
64. 0 Specify the address of the text characters or graphic tile stored in ROM 512 types each COL Color Control Code Normal Mode ID Code 10 BSHAD 1 0 Specify shadowing of the character box for a 3D button effect 00 Disable 01 Disable 10 Upper left white and lower right black shadows 11 Upper left black and lower right white shadows CSHAD Specifies character shadowing for a 3D effect 0 Disable 1 Enable MN101C46F LSI User Manual Panasonic Semiconductor Development Company 118 Panasonic On Screen Display VRAM FRAME Specifies character outlining black 0 Disable 1 Enable BLINK Specifies character blinking 0 Disable Enable 2 0 Specify the background color 1 of 8 colors CCOL 2 0 Specify the foreground text color 1 of 8 colors COL Color Control Code Closed Caption Mode ID Code 10 CUNDL Specifies underlining 0 Disable 1 Enable ITALIC Specifies italicization 0 Disable 1 Enable FRAME Specifies character outlining black 0 Disable 1 Enable BLINK Specifies character blinking 0 Disable 1 Enable BCOL 3 0 Specifies the background color 1 of 16 colors CCOL 4 0 Specifies the foreground text color 1 of 16 colors CB Repeat Blank Character Code ID Code 01 BF Repeat blank repeat character select 0 Repeat blank 1 Repeat character CB 3 0 This field specifies the number of times up to 16 a blank space or charac ter is repeated T
65. 0 Push pull control 1 High impedance PLT17RH ROUT pin high impedance control 0 Push pull control 1 High impedance PLT17B Blue digital output push pull PLT17G Green digital output push pull PLT17R Red digital output push pull MN101C46F LSI User Manual Panasonic Semiconductor Development Company 156 Panasonic On Screen Display OSD Registers PLT20 27 Palette 2 Colors 0 7 Register x 03EF0 x 03EF7 Bit 7 6 9 4 3 2 1 0 PLT20 PLT20 PLT20 PLT20 PLT20 PLT20 PLT20 PLT20 YM YS BH GH RH B G R Reset 0 0 0 0 0 0 0 0 R W RW RW RW RW RW RW R W RW Color 0 of palette 2 PLT20YM YM output PLT20YS YS output PLT20BH BOUT pin high impedance control 0 Push pull control 1 High impedance PLT20GH GOUT pin high impedance control 0 Push pull control 1 High impedance PLT20RH ROUT pin high impedance control 0 Push pull control 1 High impedance PLT20B Blue digital output push pull PLT20G Green digital output push pull PLT20R Red digital output push pull Bit 7 6 3 4 3 2 1 0 PLT27 PLT27 PLT27 PLT27 PLT27 PLT27 PLT27 PLT27 YM YS BH GH RH B G R Reset 0 0 0 0 0 0 0 0 R W RW RW RW RW RW RW R W RW Color 7 of palette 2 PLT27YM YM output PLT27YS YS output PLT27BH BOUT pin high impedance control 0 Push pull control 1 High impedance PLT27GH GOUT pin high impedance control 0 Push pull control 1 High imped
66. 0 R W R R R R R R R prescalar control register enables or disables prescalar counting PSCEN Controls prescalar 0 and 1 counts 0 Disable 1 Enable The timer prescalar select registers select the count clocks for the 8 bit timers CK2MD Timer 2 prescalar select register x 03F5E Bit 7 6 5 4 3 2 1 0 TM2 TM2 TM2 PSCI PCSO BAS Reset 0 0 0 0 0 X X X R W R R R R R R W R W Table 5 3 Timer 2 prescalar select register TM2PSC1 TM2PSCO TM2BAS Clock selected 0 0 0 fosc 4 0 1 0 fosc 16 1 0 0 fosc 32 1 1 0 fosc 64 0 1 6 2 Em 1 1 4 Panasonic Semiconductor Development Company MN101C46F LSI User Manual 95 Panasonic Prescalar Prescalar Control Registers Bit Reset R W Bit Reset R W CK3MD Timer 3 prescalar select register F 6 4 3 2 1 0 TM3 TM3 TM3 PSCI PCSO BAS 0 0 0 0 0 X X X R R R R R R W R W R W Table 5 4 Timer 3 Prescalar Select Register TM3PSC1 TM3PSCO 5 Clock selected 0 0 0 fosc 4 0 1 0 16 1 0 0 fosc 64 1 1 0 fosc 128 0 1 fg 2 1 1 fs 8 CK4MD Timer 4 prescalar select register 7 6 5 4 3 2 1 0 TM4 TM4 TM4 PSC1 PCS0 BAS 0 0 0 0 0 x x x R R R W R W R W Table 5 5 Timer 4 Prescalar Select Register
67. 0 0 0 0 0 0 0 0 R W R W R W R R R R R W R W The closed caption decoder 0 interrupt control register VBIOICR con trols interrupt levels interrupt enables and interrupt requests for closed caption decoder 0 interrupts Use interrupt control registers with the maskable interrupt enable flag MIE of the PSW at 0 VBOLV 1 0 Interrupt level specification flag A 2 bit flag that sets the interrupt level Determines which of the CPU s levels 0 3 is assigned to the interrupt VBOIE Interrupt enable flag 0 Disable interrupt 1 Enable interrupt VBOIR Interrupt request flag 0 No interrupt request 1 Generate interrupt request Panasonic Semiconductor Development Company MN101C46F LSI User Manual 61 Panasonic Interrupts Interrupt Control Registers VBHICR Closed Caption Decoder 1 Interrupt Control Register x O3FF4 Bit 7 6 4 3 2 1 0 VBILVI VBILVO VBIIE VBIIR Reset 0 0 0 0 0 0 0 0 R W R W R W R R R R R W R W The closed caption decdoer 1 interrupt control register VBILICR con trols interrupt levels interrupt enables and interrupt requests for closed caption decoder 1 interrupts Use interrupt control registers with the maskable interrupt enable flag MIE of the PSW at 0 VB1LV 1 0 Interrupt level specification flag A 2 bit flag that sets the interrupt level Determines which of the CPU s levels 0 3 is assigned to the interrupt VB1IE Interrupt enable flag 0 Di
68. 0 and 1 VSHTO VSMPO 0 V shutter 0 moves downward SHTSPO SHTSP1 0 Shutter moves 1 HSYNC each VSYNC VSHT1 You must set OSDREGE x 1 or the shutters will not move PCNT2 register bit 2 VSHTO VSHT1 Vertical shutter 0 stops x 3FF HSYNC lines from the top of the screen VSHT1 VSHTO Figure 7 19 Shutter Movement Setup Examples MN101C46F LSI User Manual Panasonic Semiconductor Development Company 140 Panasonic On Screen Display Controlling the Shuttering Effect Do not allow the horizontal shutter ing boundaries to overlap any itali cized portion of a closed caption display This distorts the italicized characters 7 10 3 Controlling Shuttering Effects Through register settings you can independently control shuttering for text text background graphics and color background You can also output blanks to the shuttered area You cannot shutter the cursor layer Table 7 9 shows the register settings required for these effects There are three types of shuttering shuttering of text text background and graphics shuttering of the color background and shutter blanking The sections below describe how to control each of these Table 7 10 Bit Settings for Controlling Shuttering Effects Function Bit Name Description Text shuttering CCSHT 0 Shutter text layer characters 1 Don t shutter text layer characters Text background BCSHT 0 Shutter text layer bac
69. 0011 0000 1bp abs 8 dii 3 124 if mem8 abs8 bp 1 PC 82PC 1 d4sign extension 2 d7 sign extension 3 411 sign extensio Panasonic Semiconductor Development Company MN101C46F LSI User Manual 243 Panasonic MNI01C Series Instruction Set MN101C SERIES INSTRUCTION SET Group Mnemonic Operation Flag CodeCycle Re Exten Machine Code Notes Pag VFINF CF 2 Size peat sion 1 2 3 4 5 6 7 8 9 10 11 TBZ TBZ io8 bp label ifmem8 IOTOPsio8 bp 0 PC 7 d7 labelH4PC O O 7 67 0011 0100 lt 8 gt d7 1 23 if mem8 IOTOP sio8 bp 1 PC 7 9PC TBZ io8 bp label f mem8 OTOP io8 op 0 PC8 di tlabelsH 9PCG 0 6 8 67 0011 0100 16 lt o8 gt dil 72 123 8 08 1 8 TBZ abs16 bp label if mem amp abst6 bp 0 PC 9 d7 abe sHOPC 0 0 9 9 7 8 0011 1110 abs 16 gt lt d7 i 124 if mem8 abs16 bp 1 PC 9 PC TBZ abs16 bp label if mem8 abs16 op 0 PC 10 d11 label HsPC O amp e 10 7 8 0011 1110 1bp abs 16 dil 2 124 if mem8 abs16 bp 1 PC 10 PC TBNZ 2 abs8 bp label if mem8 abs8 bp 1 PC 7 d7 label H PC O e 0 7 6 7 0011 0001 abs 8 d7 1 125 if mem8 abs8 bp 0 PC 72PC TBNZ abs8 bp label I mem8 abs8 op 1 PC 8 d1 label H gt PC O 6 0 8 6 7 0011 0001 1bp abs 8 dii 2 125 if mem8 abs8 bp 0 PC 82PC TB
70. 10 7 HSYNC Securement and 180 10 8 VSYNC M sking nri umapa URGE PIS VEU RES 180 10 9 Data Shce Eevel Calculation ck e ase RR Ro q gS RU 181 10 10 Sampling Clock Timing 4 182 10 11 Caption Data Capture 2 182 10 12 SLSFand SLHD Multiplexing 1 44 186 10 13 Backporch Position 1 2 22 192 10 14 SynGSeparatopDevelx ee Rep Guss py 193 10 15 BSP and PSP 222 525 ei y eee 194 11 1 IR Remote Signal Receiver Block Diagram 200 11 2 IR Remote Signal Noise 1 1 1 7 201 11 3 Reception of 8 Bit Data with No 202 11 4 Reception of 8 Bit Data with 202 11 5 Conditions for Detecting Data
71. 12 or 14 32 MHz clock supplied through the OSC1 and OSC2 pins then synchronized internally to the HSYNC pulse MN101C46F LSI User Manual Panasonic Semiconductor Development Company 136 Panasonic On Screen Display Controlling the Shuttering Effect 7 10 Controlling the Shuttering Effect The MN101C46F OSD achieves a shuttering effect using four programmable shutters two vertical and two horizontal With this feature you can shutter any portion of the OSD display or you can combine shuttering with a wipe out effect to create a smooth appearing and disappearing effect To prevent flickering and shadows on the display only write to the registers during the VSYNC cycle 7 10 1 Controlling the Shuttered Area The register settings for the two vertical shutters VSHTO and VSHT1 and two horizontal shutters HSHTO and HSHT1 control which area of the screen is shuttered Table 7 8 shows the register settings required for this function and figure 7 18 shows four setup examples Table 7 8 Bit Settings for Controlling the Shuttered Area Function VSHTO Bit VSHT1 Bit HSHTO Bit HSHT1 Bit Description Shutter enable disable VSONO VSONI HSONO HSONI 0 Disable shutter Acts as though there are no shutter lines 1 Enable shutter Shutter position VSTO00 VST10 5700 5 10 For vertical shutters this is the number of H scan lines VSTO9 VST19 HST09 HST19 from the top of the screen
72. 16 bit units You can transfer with either odd or even addresses They are undefined at reset 15 0 Address register A0 Al 2 7 3 Stack Pointer SP This register specifies the top address of the stack area It is decremented during saves and Incremented when restored It is undefined at reset 15 0 Stack pointer SP MN101C46F LSI User Manual Panasonic Semiconductor Development Company 26 Panasonic 2 8 Operations Registers Basic CPU Functions Operations Registers The operations registers consist of four data registers D0 D1 D2 and D3 2 8 1 Data Registers D0 D1 D2 D3 The data registers are all 8 bit general purpose registers They can be used for arithmetic logical or shift operations or for transfers of data to memory DO and D1 can be paired and handled as a 16 bit registers as can D2 and D3 The data registers are undefined at reset 2 8 2 Processor Status Word Data registers 15 DI DO DWO D3 D2 DWI The processor status word PSW is an 8 bit register that stores an operation result flag an interrupt mask level and a maskable interrupt enable flag The PSW is automatically saved to the stack when an interrupt occurs and automat ically restored from the stack after the interrupt is recovered PSW Processor Status Word Bit 7 6 5 4 3 2 1 0 Reserved MIE IMI IMO VF NF CF ZF
73. 2 and 3 determine the color palette used for that pixel Graphics Tile ri mei Sheet 3 Line 2 Sheet 2 Hines eet Line 18 1dot 3 bits 8 colors this example line 18 of the code 00 Bit 15 5 graphics is set in 8 color mode 8 color mode Setup example 8 color mode GROMEND 5 _ Sheet 1 bits 7 to 0 0000 0000 GROMEND 4 Sheet 1 bits 15 to 8 1010 1010 GROMEND 3 Sheet 2 bits 7 to 0 0000 0000 GROMEND 2 Sheet 2 bits 15 to 8 1100 1100 GROMEND Sheet bits 7 to 0 1 0000 0000 8 GROMEND Sheet 3 bits 15 10 8 1 byte 1111 0000 noe Use graphics palette 7 r Use graphics palette 6 Use graphics palette 5 r Use graphics palette 4 Use graphics palette 3 Use graphics palette 2 Use graphics palette 1 Use graphics palette 0 Graphics tile Line 1 Line 2 Line 3 e 5 5 Line 18 n Bit 15 Bit 0 Figure 7 6 Graphics ROM Setup Example for a Single Line Panasonic Semiconductor Development Company MN101C46F LSI User Manual 123 Panasonic On Screen Display ROM ROMEND 90xN 1 ROMEND 1B0 ROMEND 18C ROMEND 168 ROMEND 144 ROMEND 120 ROMEND FC ROMEND D8 ROMEND B4 ROMEND 90 ROMEND 6C ROMEND 48 ROMEND 24 Gra
74. 4 MHz oscillator The Ts cycle is the contents of RMTC 1 in normal mode or the contents of RMTC 2 in slow mode so load a value from 1 to 255 to set a division ratio from 2 to 256 The microcontroller reads the value in the frequency division counter as a ones complement number each digit is complemented Set the RMTC value so that T 2 where T is the pulse width of the remote input signal Table 11 5 shows how to define T for the different formats Table 11 5 HEAMA and 5 6 Bit Data Pulse Widths H L HEAMA format Data 0 T Ea Data 1 T 3T Data 0 2T 2T 5 6 bit format Data 1 2T 6T RMTC is an 8 bit access register Panasonic Semiconductor Development Company 205 Panasonic MN101C46F LSI User Manual IR Remote Signal Receiver IR Remote Signal Receiver Control Registers Bit Reset R W RMIR Remote Signal Interrupt Control Register X OSEA2 7 6 5 4 3 2 1 0 MOD MOD FILTR POL LEADER TRAILR DAT8 EDME AUTO SEL E SEL E E E E 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W RMIR controls the operating modes and interrupt operations for the receiver circuit It is an 8 bit access register MODAUTO Automatic operating mode detection on off 0 Automatic detect 1 Fixed MODSEL Operating mode select 0 HEAMA format 1 5 6 bit format FILTRE Noise filter input multiplexer on off 0 Pin level
75. 8 7 6 5 4 Reset 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW A 11 4 hold the VRAM end address RAMEND The low order four bits 1 of the address are always x F and the high order four bits are always x 0 The available address range is x 040F to x OBFF with a programmable Do not set outside x 40 x BF The range from x 40 to x BFP microcontroller will not operate correctly MN101C46F LSI User Manual Panasonic Semiconductor Development Company 146 Panasonic On Screen Display OSD Registers A11 A4 0000 XXXX XXXX 1111 Fixed Programmable Fixed 040F 000010100 000011111 OBFF 000011011 111111111 Initial Horizontal Position Register High x 03ECB IHP Initial Horizontal Position Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 IHSZI 570 ISHT 9 IHP8 IHP7 IHP6 IHP5 4 IHP3 IHP2 IHPI IHPO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W RW RW RW RW R W RW RW RW RW RW RW RW IHSZ 1 0 Initial horizontal size 00 1 dot 1 VCLK period 01 1 dot 2 VCLK periods 10 1 dot 3 VCLK periods 11 1 dot 4 periods ISHT Initial shutter control 0 Shutter control on 1 Shutter control off IHP 9 0 Initial horizontal position IVPH Initial Vertical Position
76. 8 bits shi 1 TE Y s a PE MI maaan PONO Note Vpp 3 3 V Vos 0 V 25 Figure 1 5 Composite Video Signal Specification Composite Video Signal Specification 1 Signal input amplitude The phase difference is reference 720 2000 mV to the sync signal input to CVBS 2 Caption data amplitude 360 3 Sync signal amplitude 360 4 Maximum CVBS input potential Vpp V 5 Minimum CVBS input potential Vp Vss 1 5 1 PC Interface Timing i Ji 15V F IE se 41 lt gt x lt P S tHD STA tHD DAT tHIGH tSU DAT Si tSU STA tsU sTP P Figure 1 6 Interface Timing Panasonic Semiconductor Development Company MN101C46F LSI User Manual 11 Panasonic General Description Electrical Characteristics Table 1 7 2 Timing for Master Transmission SCL SDA Master Reception SCL and Slave Transmission SDA No Parameter Symbol Conditions Min Max Unit SCL clock frequency 7 fscL fosc 12 to 14 32 MHz 100 kHz Bus free time tBUF fsc 100 kHz 20 us SDA and SCL rise time t 1 SDA and SCL fall time tr 300 ns Notes 1 See section 13 for information on the C clock select All other parameters adhere to the specifications shown above 2 figure 1 7 shows the software method of attaining the bus free time indicated above The microcontroller requires 80 machin
77. Addressed as slave Set to 1 when the slave address on the bus matches the contents of the address register or matches the general address x 00 AAS resets after a read from the I2CDRECH register LAB Lost arbitration bit Set to 1 when the microcontroller loses a bus arbitration LAB resets when I2CDTRMH indicates a start condition STA 1 BB Bus busy bit A start condition on the bus sets this flag to 0 and a stop condition resets it to 1 The microcontroller considers the bus to be busy as long as BB 0 D 7 0 Received data The serial data received from the bus is shifted into this field MSB first I2CMYAD I C Self Address Register x 03E84 Bit 7 6 5 4 3 2 1 0 A6 A5 A4 A3 A2 Al A0 Reset 0 0 0 0 0 0 0 0 R W R R W R W R W R W R W R W R W A 6 0 Microcontroller address This register is formed from a 7 bit field address latch It holds the micro controller s own address used for a compare when the microcontroller is addressed as a slave When a match occurs AAS is set to 1 I2CCLK 2 Clock Control Register x O3E86 Bit 6 5 4 3 2 T 0 C7 C6 C5 C4 C3 C2 CO Reset 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W C 7 0 Output clock frequency select 1 This 8 bit field determines the SCL output With a 3 58 MHz system clock calculate the frequency as follows To conform to the specification the clock signal must be
78. External Connection with Figure 10 4 External Connection with Both CCD0 and CCD1 Unused Only CCD0 Unused Table 10 2 provides the register setting for caption terminals in cases of Figure 10 2 Figure 10 3 and figure 10 4 And always set both bits 6 and 7 of P2MD to 1 whether using two CCD s or only one CCD In not using any CCD always set these two bits to 0 Panasonic Semiconductor Development Company MN101C46F LSI User Manual 175 Panasonic Closed Caption Decoder Functional Description Table 10 2 Caption decoder register setting decoder VBI control ADC control Clamp control Use two caption caption 0 ON PCNTO bp0 0 ON PCNTO bp3 1 ON P2MD bp6 1 decoders caption 1 ON PCNTO bp1 0 ON PCNTO bp4 1 ON P2MD bp5 1 Use one caption caption 0 ON PCNTO bp0 0 ON PCNTO bp3 1 ON P2MD bp6 1 OFF PCNTO bp1 1 OFF PCNTO bp4 0 ON P2MD bp5 1 no caption 1 OFF PCNTO bp3 0 OFF PCNTO bp4 0 OFF P2MD bp6 0 OFF P2MD bp5 0 No use caption decoder OFF PCNTO bp0 1 OFF PCNTO bp1 1 no caption 0 no caption 1 10 3 2 Clamping Circuit This block clamps the input video signal CVBSO CVBS1 Control circuit ADDATA 7 0 Clamping Circuit r External I circuit 1 umm Data slice circuit Sync separato circuit Figure 10 5 Clamping Circuit The clamping circuit internal to the MN101C46F provides three current sources high medium a
79. HSYNC separator control register 2 high HSEP2 03 50 x 03E70 R W HSYNC separator control register 2 FIELDH x 03E53 x 03E73 R W Field detection control register high FIELD 03 52 x 03E72 Field detection control register HLOCKLVH x 03E55 03 75 R W Sync separator detection control register 1 high HLOCKLV x 03E54 x O3E74 R W Sync separator detection control register 1 HDISTWH 03 57 03 77 R W Sync separator detection control register 2 high HDISTW x 03E56 x 03E76 R W Sync separator detection control register 2 VCNTH 03 59 x 03E79 R W VSYNC separator control register high VCNT x 03E58 x 03E78 R W VSYNC separator control register HVCOND x OSESA x OGBE7A R Sync separator status register CLPCNDIH x 03ESD x OSE7D R Clamping control signal status register 1 high CLPCNDI x 03ESC x 03E7C R Clamping control signal status register 1 SLCNTI x 08D7A x 03DFA R W Sampling frequency control register 1 SLCNT2 x 03D7B x 03DFB R W Sampling frequency control register 2 MN101C46F LSI User Manual Panasonic Semiconductor Development Company 184 Panasonic Closed Caption Decoder Closed Caption Decoder Registers FC VBI Decoding Format Select Register x 03E00 FCW VBI Decoding Format Select Register x 03E20 Bit 7 6 5 4 3 2 1 0 SLPUL CRIC NCRIG CNT CNT CNT CNT CNT SEL SEL SEL STAP4 STAP3 STAP2 STAPI STAPO
80. High impedance FRAMERH ROUT pin high impedance control 0 Push pull control 1 High impedance FRAMEB Blue digital output push pull FRAMEG Green digital output push pull FRAMER Red digital output push pull Panasonic Semiconductor Development Company MN101C46F LSI User Manual 153 Panasonic On Screen Display OSD Registers BBSHD Black Box Shadowing Register x 03ED4 Bit 7 6 3 4 3 2 1 0 BBSHD BBSHD BBSHD BBSHD BBSHD BBSHD BBSHD BBSHD YM YS BH GH RH B G R Reset 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Sets color of black box shadowing BBSHDYM YM output BBSHDYS YS output BBSHDBH BOUT pin high impedance control 0 Push pull control 1 High impedance BBSHDGH GOUT pin high impedance control 0 Push pull control 1 High impedance BBSHDRH ROUT pin high impedance control 0 Push pull control 1 High impedance BBSHDB Blue digital output push pull BBSHDG Green digital output push pull BBSHDR Red digital output push pull WBSHD White Box Shadowing Register x OSED6 Bit 7 6 3 4 3 2 1 0 WBSHD WBSHD WBSHD WBSHD WBSHD WBSHD WBSHD WBSHD YM YS BH GH RH B G R Reset 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW Sets color of white box shadowing WBSHDYM YM output WBSHDYS YS output WBSHDBH BOUT pin high impedance control 0 Push pull control 1 High impedance WBSHDGH GOUT pin high im
81. High order HA SP45 Low order HA SP 4 3 PC bits 18 17 0 SP 3 PC bits 16 9 SP 2 PC bits 8 1 SP 1 4 PSW is saved to the stack PSW SP 5 Interrupt level xxxLVn IMn 6 Operation jumps to vector table address New SP after interrupt serviced OdSP y before interrupt serviced 7 0 GE E PSW PC 8 1 PC 16 9 PCO Reserved PC 18 17 HA 7 0 HA 15 8 7 754022 2 Program counter data PC top return address is saved to the stack The xxxLVn of the accepted interrupt is copied to the IMn of the PSW Lower Address Higher Figure 3 5 Stack Status during Interrupts Panasonic Semiconductor Development Company 53 Panasonic MN101C46F LSI User Manual Interrupts Operation 3 4 6 Interrupt Return Operation After the values of registers and the like that were saved by interrupt servicing have been restored by the program by a POP instruction operation returns to the program that was being executed when the interrupt was accepted via an RTI instruction The following shows the sequence of operation for the return from interrupt instruction RTI 1 The contents of the PSW saved to the stack SP are restored 2 data of the program counter PC Top return address saved to the stack Y SP 1 2 or 3 is restored Data and address registers are not 3 The handy address register HA
82. LL UDASDIG 201g J AI9994 PLUIS MI IR Remote Signal Receiver IR Remote Signal Receiver Operation 11 3 IR Remote Signal Receiver Operation 11 3 1 Operating Modes The IR remote signal receiver has three operating modes HEAMA 5 6 bit and HEAMA 5 6 bit automatic detect Set the mode in the MODAUTO and MODSEL bits of the interrupt control register RMIR The FMTMON bit of the interrupt status register RMIS monitors the operating mode In automatic detect mode the microcontroller checks the interval between remote signal edges If the interval is n 4Ts to n 3Tg where n is the leader value set in the LD 3 0 field of the RMLD register it processes the data in HEAMA format If the interval is 28 to 35 Ts cycles it processes the data in 5 6 bit format 11 3 2 Noise Filter The IR remote signal receiver contains a noise filter to eliminate noise from the remote signal To enable the noise filter set the FILTRE bit of the interrupt control register RMIR to 1 The noise filter samples the remote input signal every PWMS cycle 17 9 us or PWM7 cycle 71 5 us then outputs the value that it sampled at least three times during the last four sampling cycles This eliminates any noise occurring during one or two sampling cycles Select the sampling clock PWM5 or PWM7 with the SP bit of the RMLD register PWMS is selected at reset ww L i NE Noise filter x output Noi
83. LSI User Manual oruoseueq OLL IDnup W 42SN IST HOFOIOINIW juawudojaaaq AOJINPUOIIWAY 21uospupq Vertical position Field Horizontal position counter Shutter controller Color palettes PALETWE r o Marne 3 counter detector 8 EosEL HSYNC o 10 bit a HCOUNT OSC1 2 Y Clock Dot clock sync 1 2 circuit divider Y RW I OSD SYSCLK COL CCB HP VP attributes System cock OSD registers Y Font and tile RW qata read circuit IRQ Y DMA block addr Reads display code Data decoder RAM IHP IVP 8 Kbytes CRAMEND data Note 2 indicates the control bit or field 2 addr Text style and color controller UNDE CAPM BLINK RGB Shift register Text graphics and cursor MIX display controller YS YM ROM 96 Kbytes Figure 7 1 OSD Block Diagram uo1ljdiios q Ke dsrq 125 0 On Screen Display Power Saving Considerations in the OSD Block 7 2 Power Saving Considerations in the OSD Block Table 7 2 shows the two control bits that can decrease the power consumption of the OSD block This section explains h
84. O3E3D STAP Sampling Start Position Register Software Setting x 03E1C STAPW Sampling Start Position Register Software Setting x 03E3C Bit 7 6 9 4 3 2 1 0 7 6 5 4 3 2 1 0 SFT SFT SFT SFT SFT SFT SFT SFT SFT SFT SFT STAP STAP STAP STAP STAP STAP STAP STAP STAP STAP STAP 10 9 8 7 6 3 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R R R R R R W RW RW R W RW RW RW RW RW RW RW SFTSTAP 10 0 Software setting for sampling start position in clock units FCPNUMH Sampling Start Position Register Hardware Calculation High x 03E1F FCPNUMWH Sampling Start Position Register Hardware Calculation High x 03E3F FCPNUM Sampling Start Position Register Hardware Calculation x 03E1E FCPNUMW Sampling Start Position Register Hardware Calculation x 03E3E Bit 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 FCP FCP FCP FCP FCP FCP FCP FCP FCP FCP FCP NUM NUM NUM NUM NUM NUM NUM NUM NUM NUM NUM 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R R R R R R R R R R R R R R R R FCPNUM 10 0 Sampling start position calculated by the hardware MN101C46F LSI User Manual Panasonic Semiconductor Development Company 190 Panasonic Closed Caption Decoder Closed Caption Decoder Registers
85. OSCO XI XO Clock CPU NORMAL 0 0 0 0 Oscillates Oscillates OSCI Runs IDLE 0 0 0 1 Oscillates Oscillates XI Runs SLOW 0 0 1 1 Oscillates Oscillates XI Runs HALTO 0 1 0 0 Oscillates Oscillates OSCI Stopped HALTI 0 1 1 1 Oscillates Oscillates XI Stopped STOP0 1 0 0 0 Stopped Stopped Stopped Stopped STOPI 1 0 1 1 Stopped Stopped Stopped Stopped There are three steps to invoking HALT or STOP mode from NORMAL mode 1 Toreturn via a maskable interrupt on the PSW set MIE to 1 and set an IM value that allows the recovery source interrupt to be received 2 Check that the interrupt request flag xxxIR of the maskable interrupt con trol register xxxICR has been cleared then set the interrupt enable flag XXXIE for the recovery source 3 Setthe CPUM to invoke HALT or STOP mode To clear an interrupt request flag using software set the IRWE flag in the memory control register MEMCTR MN101C46F LSI User Manual Panasonic Semiconductor Development Company 38 Panasonic Basic CPU Functions Standby Function 2 12 3 Moving between SLOW and NORMAL Modes The MN101C46F has two CPU operating modes NORMAL and SLOW To move between SLOW and NORMAL modes you must transit an idle state The following is an example of a program that moves between NORMAL and SLOW modes Program 1 MOV x 3 DO Invokes SLOW mode MOV DO CPUM If the slow clock is running with sufficient stability you can invoke SLOW mode fro
86. P channel XPEDOWN Clamping control pulse for medium current source N channel PEDUP Clamping control pulse for low current source P channel PEDOWN Clamping control pulse for low current source N channel SLCNT2 Sampling Frequency Control Register 2 x 03D7B SLCNT2W Sampling Frequency Control Register 2 x 03DFB SLCNT1 Sampling Frequency Control Register 1 x 03D7A SLCNT1W Sampling Frequency Control Register 1 x 03DFA Bit 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 SL SL SL SL SL SL SL SL SL SL SL SL CNT2 CNT2 CNT2 CNT2 CNT2 CNT2 CNTI CNTI CNTI CNTI CNTI 5 4 3 2 1 0 5 4 3 2 1 0 Reset 0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 0 RW R RW RA RW RW RW RW R RW RW RW RW RW RW SLCNT2 5 0 SLCNT1 5 0 Select the sampling frequency when the operating frequency changes These registers allow you to keep the sampling frequency for closed cap tion data from changing when the operating frequency changes The table below shows how to set SLCNT2 and SLCNT1 for particular operating Panasonic Semiconductor Development Company MN101C46F LSI User Manual 197 Panasonic Closed Caption Decoder Closed Caption Decoder Registers frequencies Note that when you change the operating frequency you must align other registers besides the VBI Table 10 10 Sampling Frequency Control Register Settings
87. PIR WDIR Reserved Reset 0 0 0 0 0 0 0 R W R R R R R W R W Program interrupt request flag 0 No interrupt request 1 Generate interrupt request WDIR Watchdog interrupt request flag 0 No interrupt request 1 Generate interrupt request Reserved Always set to 0 The nonmaskable interrupt control register stores nonmaskable interrupt requests When a nonmaskable interrupt occurs it is accepted regardless of the interrupt mask level IMn in the PSW and operation jumps to the address written at x 04004 in the interrupt vector table The watchdog timer overflow interrupt request flag WDIR is set to 1 when the watchdog timer overflows The program interrupt request flag PIR is set to 1 when an undefined instruction is executed Forcibly generate a nonmaskable interrupt by setting either the PIR flag or the WDIR flag with an instruction IRQOICR External Interrupt O Control Register x 03FE2 to x 03FE71 Bit 7 6 5 4 2 1 IRQn IRQn LV1 Lyo REDGn IRQnIE IRQnIR Reset 0 0 0 0 0 0 0 RW RW RW R R RW RIW The external interrupt n control register IRQnICR is the register that con trols interrupt levels valid edges interrupt enables and interrupt requests for external interrupt n Use interrupt control registers with the maskable interrupt enable flag MIE of the PSW at 0 n 0 to 5 IRQnLV 1 0 External interrupt level specification f
88. Panasonic General Description Electrical Characteristics Table 1 6 Electrical Characteristics Continued Ta 20 to 70 C Vpp 3 3 V Vgg 0 V No Parameter Symbol Conditions Min Typ Max Unit MMOD and FLASH Input pin with CMOS input level C3 Input high voltage Vin Vpp 3 0 V to 3 6 V 0 7Vpp Vpp V C4 Input low voltage Vpp 3 0 V to 3 6 V 0 0 3Vpp C5 Input leakage current Hi 0 0 V to 3 6 V 5 HA P07 P10 P13 15 16 P22 P27 P31 P35 P40 I O pins with CMOS input level C6 Input high voltage Vin Vpp 3 3 V to 3 6 V 0 7Vpp Vpp V C7 Input low voltage Vit Vpp 3 3 V to 3 6 V 0 0 3Vpp C8 Output high voltage Von 1 mA Vpp 0 6 C9 Output low voltage VoL IoL 1 8 mA 0 4 C10 Output leakage current Iro Output Hi Z 5 uA Vin 0 0 V to 3 6 V C11 Pullup resistance Vin 0 0 V 10 30 90 P00 P03 P06 P17 P20 P30 P37 I O pins with CMOS input level and Schmidt trigger C12 Input high voltage Vin Vpp 3 3 V to 3 6 V 0 7Vpp Vpp V C13 Input low voltage Vpp 3 3 V to 3 6 V 0 0 3Vpp C14 Output high voltage 1 Vpp 0 6 C15 Output low voltage VoL Ip 1 8 mA 0 4 C16 Output leakage current Iro Output Hi Z 5 pA Vin 0 0 V to 3 6 V C17 Pullup resistance Vin 0 0 V 10 30 90 KQ P36 NRST I O pin with CMOS input level Schmidt trigger and N channel ope
89. RH OSD output Hi Z control 0 P32 P33 P34 P35 1 BOUT GOUT ROUT YM lt P3MDn Y y 0 Port inpu 1 Port output Ds lt gt e 1 0 Port low output 1 Port high output lt gt e P3OUTn BOUT GOUT ROUT YM 1 digital output X cz P3INn n 2 P32 n 3 P33 4 P34 n 5 P35 Note Figure 4 17 P32 BOUT P33 GOUT P34 ROUT and P35 YM Port 3 0 Pullup off 1 Pullup on eI lt P3PUP6 0 1 Port output gt P3DIR6 0 Port low output Pin 1 Port high output K P3OUT6 P36 NRST P3IN6 NRST lt fj Schmidt trigger Figure 4 18 P36 NRST Port 3 MN101C46F LSI User Manual Panasonic Semiconductor Development Company 82 Panasonic I O Ports I O Port Circuit Diagrams 0 Pullup off 1 Pullup on P3PUP7 i 0 P37 IRQ5 1 NVSYNC IRQ5 lt 07 0 Port inpu 1 Port outpi PSDIR7 t 0 Port low output Pin 1 Port high output P3OUT7 X P37 IRQ5 NVSYNC P3INN amp 1 IRQ5 s NVSYNC Schmidt trigger Figure 4 19
90. ROM Correction Address Match Register n Low x 03F70 to x 03F8E Bit 7 6 5 4 3 2 1 0 CHAn CHAn CHAn CHAn CHAn CHAn CHAn CHAn 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W are 8 bit access registers n 0 F CHAn 7 0 Correction address bits A7 to AO CHDATOn ROM Correction Data Register n x 03FD0 to x 03FDF Bit 7 6 4 3 2 1 0 CHn7 CHn6 CHn5 CHn4 CHn3 CHn2 CHnl CHnO Reset 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W CHDATn 8 bit access registers n 0 CHn7 Correction data D7 CHn6 Correction data D6 CHn5 Correction data D5 CHn4 Correction data D4 CHn3 Correction data D3 CHn2 Correction data D2 CHn1 Correction data D1 CHn0 Correction data DO MN101C46F LSI User Manual Panasonic Semiconductor Development Company 212 Panasonic I C Bus Controller Description 13 Bus Controller 13 1 Description The MN101C46F contains one C bus controller fully compliant with the PC specification that can control one of two bus connections An IC bus is a simple two wire bus for transferring data between ICs Since it requires only a serial data line SDA and a serial clock line SCL it minimizes interconnections so ICs have fewer pins and there are fewer PCB tracks The result is a smaller and less expensive PCB Figure 13 1 shows a typi
91. Register High x 03ECD IVP Initial Vertical Position Register x 03ECC Bit 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 TVSZ1 IVSZO IVP9 IVP8 IVP7 IVP6 5 IVP4 IVP3 IVP2 IVPO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W RW RW RW RW RW RW RW IVSZ 1 0 Initial vertical size IVSZ 1 0 1 Dot Size Setting Interlaced Displays Progressive Displays 00 1 H scan line Reserved 01 2 H scan lines 1 H scan line 10 4 H scan lines 2 H scan lines 11 6 H scan lines 3 H scan lines IVP 9 0 Initial vertical position IAPH Initial RAM Address Pointer Register High x 03ECF 1 IAP Initial RAM Address Pointer Register x O3ECE Bit 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Set APCNT bit 7 of x 03EB8 to IAP11 IAPIO IAPO IAPG IAPS IAP2 IAPI 1 to make this setting valid Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW RW RW RW RW RW IAP 11 0 Initial RAM address start of second line pointer Panasonic Semiconductor Development Company MN101C46F LSI User Manual 147 Panasonic On Screen Display OSD Registers a Bit Set APCNT bit 7 of x 03EB8 to 1 to make this setting valid Reset R W Bit Reset R W
92. Sample Hold Time Set the sample hold time using the ANSH 1 0 field of ANCTRO Select a value for the sample hold time that is appropriate to the impedance of the analog input 5 Setup the A D Ladder Resistors Set the ANLADE flag of ANCTRO to 1 to send current to the ladder resis tors and put A D conversion in standby Steps 2 through 5 do not need to be done in order Steps 3 4 and 5 may even be done simultaneously 6 Select the A D Conversion Start Source and Start A D Conversion Set the ANST flag of A D control register 2 ANCTR2 to 1 to start A D conversion 7 A D Conversion The ADC samples for the sample hold time set in step 3 and sequentially compares and determines the bits starting from the MSB 8 Endof A D Conversion When A D conversion is complete the ADC clears the ANST flag and sends the results to the A D buffer ANBUFI It also generates an A D end inter rupt request ADIRQ at this time Panasonic Semiconductor Development Company MN101C46F LSI User Manual 161 Panasonic Analog Digital Converter Analog to Digital Conversion Operation tAD 1107 8 9 12 A D conversion clock 4 ANST flag Start A D conversion A D conversion end L lt A D conversion time AM ES 4 Semping Hold MEE Comparebi4 Comparebi3 Corpaebi0 Ae e MN Bit4 Bit3 Bit 1 Bito i determined determined determined determined A D interru
93. Semiconductor Development Company MN101C46F Revision History Panasonic Revision 1 00 to Revision 1 10 July 12 1999 Page in Japanese Description of Revision Chapter 1General Description 1 6 Changed fixed polarity of MMOD pin from low to high Added description of P21 as n channel open drain 5 volt pin 1 7 Added list of pin functions figure 1 3 2 1 8 to 1 19 Added electrical specification Appendices 15 2 to 15 7 Added description of flash EEPROM version MNIOICA46F Revision History Panasonic Semiconductor Development Company Panasonic MN101C46F F46F LSI User s Manual Description Record of Changes Ver 2 1 to 2 11 Description of Changes Former version New version 21446 0211E October 2001 Ver2 11 Latest version 21446 021E August 2001 2nd Edition 1st Printing Sales office lt Definition gt A add D delete C modify change MN101C46F F46F LSI User s Manual October 2001 Ver2 11 Issued by Matsushita Electric Industrial Co Ltd Matsushita Electric Industrial Co Ltd Semiconductor Company Matsushita Electric Industrial Co Ltd Nagaokakyo Kyoto 617 8520 Japan Tel 075 951 8151 http www panasonic co jp semicon SALES OFFICES NORTH AMERICA U S A Sales Office Panasonic Industrial Company PIC New Jersey Office Two Pa
94. Specifies addresses using the stack pointer and a 16 SP d16 bit displacement Absolute abs8 7 0 Specifies addresses using operand values appended to abs8 instruction code You can specify the optimum oper abs12 7 length for the address specified abs16 15 0 abs16 abs18 17 0H Jump instructions only absi8 JI RAM short abs8 7 0 You can specify addresses with an 8 bit offset from abs8 address x 00000 I O short 108 15 0 You can specify addresses using 8 bit offset from io8 the top address x 03F00 of the special register area Handy HA This type of addressing reuses an address that has accessed memory It can only be used with MOV and MOVW instructions Combine it with absolute addressing to keep code size small Note Hybrid bit MN101C46F LSI User Manual Panasonic Semiconductor Development Company 30 Panasonic Basic CPU Functions Memory Space 2 10 Memory Space 2 10 1 Memory Modes Memory space includes the ROM area the program area for instructions the RAMarea where data can be read or written and a memory mapped special register area The MN101C46F supports a single chip mode Table 2 6 shows settings for this mode Table 2 6 Memory Mode Settings Memory Mode MMOD Pin EXMEM flag MEMCTR register Single chip mode L 0 Disabled L 1 Disabled H 2 10 2 Single Chip Mode Single chip mode is
95. Timing Control Register x 03E27 Bit 7 6 5 4 3 2 1 0 _ VBIIRQ VBIIRQ VBIIRQ VBIIRQ 4 3 2 1 0 Reset 0 0 0 1 1 1 1 1 R W R R R R W R W R W R W R W This register allows you to time the interrupt occurring after the line 21 data capture to a line other than line 21 VBIIRQ 4 0 VBI interrupt timing control In this field set the H line number from 0 to 25 for the VBI interrupt You must set this field to x 13 or higher ACQ1H ACQ Capture Timing Control Register 1 High x O3E09 ACQ1WH ACQ Capture Timing Control Register 1 High x 03E29 ACQ1 ACQ Capture Timing Control Register 1 x O3E08 ACQ1W ACQ Capture Timing Control Register 1 x 03E28 Bit 7 6 5 4 2 1 0 7 6 5 4 3 2 1 0 _ _ ACQI ACQI ACQ1 ACQI u hi _ ACQI ACQ1 ACQI ACQI E4 E3 E2 El EO S4 S3 S2 81 50 Reset 0 0 0 1 1 1 1 1 0 0 0 1 1 1 1 1 R W R R R RW RW RW RW RW R RW RW RW RW RW For designs using the closed caption decoder always tie these registers to a x 13 and x 12 z ACQ1E 4 0 Stop position for ACQ capture 1 Always tie the bits in ACQI to Valid range x 00 to x 25 fixed settings ACQ1S 4 0 Start position for ACQ capture 1 Valid range x 00 to x 25 Panasonic Semiconductor Development Company MN101C46F LSI User Manual 187 Panasonic Closed Caption Decoder Closed Caption Decoder Registers C
96. Use these registers to set the clamping mode sync tip or pedestal clamp ing PCLV 6 0 Pedestal clamping level setting Set the reference level for pedestal clamping in this field The valid range is x 00 to X IFP VBION VBI setting 0 VBI off 1 VBI SAFE Clamping current source select This bit is the capacitance switch for 5 and 6 in figure 10 5 on page 176 0 High current source 5 and 6 capacity high 1 High current source 5 and 6 capacity low CLMODE 1 0 Clamping mode setting 00 Automatic switching depends on the cycle state 01 Sync tip clamping only 10 Pedestal clamping only 11 Clamping off MN101C46F LSI User Manual Panasonic Semiconductor Development Company 194 Panasonic Closed Caption Decoder Closed Caption Decoder Registers HSEP1H HSYNC Separator Control Register 1 High x 03E4F HSEP1WH HSYNC Separator Control Register 1 High x 03E6F HSEP1 HSYNC Separator Control Register 1 x 03E4E HSEP1W HSYNC Separator Control Register 1 x 03E6E Bit 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Hs Hs HS us Hs us us B Hs Hs Hs FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 0 RW R RW RW RW RW RW RW RW RW RW RW RW HSFREQ 10 0 Correction HSYNC frequency Set the correction HS YNC cycle in this fiel
97. between 0 and f T 3 58 MHz 100 kHz To satisfy this require SCL 2x Register setting 6 ment always set I2ZCCLK to x 0C or higher Panasonic Semiconductor Development Company MN101C46F LSI User Manual 225 Panasonic I C Bus Controller Bus Interface Registers In this case the following C 7 0 settings apply X 0C 99 4kHz x 1E 49 7 kHz X OE 89 5kHz 27 39 8 kHz X10 81 4kHz x 036 29 8 kHz x 14 68 8kHz x 54 19 9 kHz X18 59 7kHz x AD 10 0 kHz I2CBRST IC Bus Reset Register x 03E88 Bit 7 6 5 4 3 2 1 0 BRST Reset 0 0 0 0 0 0 0 1 R W R R R R R R R R W BRST Bus reset When a serious bus error occurs this bit can be set to 0 forcing the clock line low and resetting the bus This function works in all C modes After a forced reset the microcontroller is in slave receiver mode This reset does not change the contents of the I2ZCMYAD and I2CCLK registers 0 Force bus to reset 1 Steady state I2CBSTS 2 Bus Status Register x 03E8A Bit 7 6 5 4 3 2 1 0 SDAS SCLS Reset 0 0 0 0 0 0 R W R R R R R R R R I2CBSTS is a two bit read only register that monitors the status of the Pc bus SDAS SDA data line status This bit monitors the state of the I C data line SDA SCLS SCL clock line status This bit monitors the state of the C clock line SCL MN101C46F LSI User Manual Panasonic Semiconductor Development Compa
98. cycle in this field in ADC clock units This is the interval used for detecting the sync tip level for sync tip clamping The valid range is x 000 to x 7FF Note that the HSYNC cycle set in this register is only used for detecting the minimum sync level You must also set the correc tion HSYNC cycle in HSEP1H and HSEPI For the NTSC format the settings for these registers are x 03 and x 8E calculated as follows A D sampling frequency x HSYNC cycle 14 32 MHz x 63 us x 03 and 8 BPPSTH Position Register High x 03E47 BPPSTWH Backporch Position Register High x 03E67 BPPST Position Register x 03E46 BPPSTW Backporch Position Register x 03E66 Bit 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 BP BP BP BP BP BP BP BP BP PST8 PST7 PST6 PST5 PST4 PST3 PST2 PST1 PSTO Reset 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 R W R R R R R R R R W RW RW RW RW RW RW RW BPPST 8 0 Backporch start position for the leading edge of HSYNC Use these registers to specify the position for capturing the pedestal level value used during pedestal clamping Specify a number of ADC clocks after the leading edge of HSYNC The valid range is x 000 to x IFF and the recommended settings are x 00 and x 47 Video signal HSYNC Set this interval in BPPSTH and BPPST Pedestal level for BPLV r
99. electronic equipment Its simple efficient Instruction set helps make it both economical and fast It offers the following features A 4 bit instruction word length minimizing instruction code size Code is compressed by adopting a basic instruction word length of 1 byte and allowing instruction length to vary in 4 bit units This prevents code expansion even though the simple instruction set is limited to load stores of data transfers to memory A minimum instruction execution time of 1 cycle 279 3 ns C compatible register set minimized for the simplest architecture The instruction set analyzes code generated by the C compiler and code from assembler programming The set represents a trade off of hardware size against performance The instruction set is thus the smallest C oriented set available and is notable for its simplicity See the MN101C Series LSI User Manual for more information Panasonic Semiconductor Development Company MN101C46F LSI User Manual 19 Panasonic Basic CPU Functions Features 2 2 Table 2 1 Basic CPU Features Features Parameter Description Architecture Load store architecture Six registers Four 8 bit data registers and two 16 bit address registers Miscellaneous 19 bit PC 8 bit PSW and 16 bit SP Instructions Number of instructions 97 Addressing modes 9 Instruction word length Basic part 1 byte minimum Extensions 0 5 bytes xn 0 lt n lt 9
100. hias te ete dente reet 175 10 3 1 Analog to Digital Conyvertet ics n Lr Re RES VERS HERE E 175 10 3 2 Clamping Circuit lt t cake bees Oba ue EAR ev ubere tue all ERE 176 10 3 3 Sync Separator cer see E DETUR UO OR BAAR Bt 177 10 3 3 1 HSYNC Separator ica el pes kuy yuana e nei as 180 10 3 3 2 VSYNG S patatotsc ieee note Ooh Ss Hh e en Neq 180 10 3 3 3 Field Detection Circuit XP ee e ucapnya E DUE 180 10 3 4 Data Slicer iiie ae iu ua k huy Ahead eee ncn ae ees 181 10 3 5 Controller and Sampling 181 10 3 5 1 CRI Detection for Sampling Clock 182 10 3 5 2 Data Capt re Control su RP EUER 182 10 4 Closed Caption Decoder Registers 183 11 IR Remote Signal Receiver 199 11 1 Description sse eR erm Deb y eS EH PUE EE 199 11 2 Block Diagram oe eg abo gr ace hu neg Addere eg h et ttg 200 11 3 IR Remote Signal Receiver 201 11 3 1 Operating Modes BE MN angle Feb te ent 201 11 3 2 oras cc IE 201 11 3 3 8 Bit Data Reception gt
101. in two separate opera tions 2 13 Setting the Clock Switch Register Always set the MN101C46F s CPU mode control register CPUM flags and oscillation frequency control register OSCMD flags OSCND Oscillation frequency control register x 03F0D Bit 7 6 5 4 3 2 1 0 Reserved Reserved Reset 0 0 0 0 0 0 0 0 R W R R R R R R R W Reserved Always set to 0 CPUM CPU mode control register x 03F00 Bit 7 6 3 4 3 2 1 0 OSC OSC OSC SELI SELO DBL STOP HALT OSCI OSCO Reset 0 0 0 0 0 0 0 0 R W R R W R W R W R W R W R W R W OSCSEL 1 0 Clock division NORMAL mode 00 1 01 Do not set 10 Do not set 11 Do not set OSCDBL Always set to 0 MN101C46F LSI User Manual Panasonic Semiconductor Development Company 42 Panasonic Basic CPU Functions Resets Use a circuit that provides a pulse with a sufficiently long low level for an instant shut off if you are connecting a supply voltage lower ing circuit to the NRST pin A reset might also be produced if the oscil lation clock has a pulse with a low level time of four clocks or less so pay attention to noise 2 14 Resets 2 14 1 Reset Operation The CPU is internally reset and all registers initialize when the NRST pin P36 is driven low 2 14 1 1Invoking the Reset Mode There are two ways to invoke the reset mode 1 Drive the NRST pin low Drive the NRST pin l
102. interrupts When the program writes a 0 to MIE in the PSW When reset is input The MIE flag is set to 1 in the following cases enabling interrupts When a program writes a 1 to the MIE in the PSW The value in the interrupt mask level field IM 1 0 is changed in the following cases When new values are written by a program in the IM 1 0 field of the PSW IM 1 0 become 00 when a reset is input IM 1 0 change to the corresponding interrupt level value when a maskable interrupt is accepted When an RTI instruction is executed at the very end of the interrupt service routine program IM 1 0 is restored to the mask level value prevailing before the interrupt was accepted If a nonmaskable interrupt and a maskable interrupt occur at the same time the nonmaskable interrupt takes priority MN101C46F LSI User Manual Panasonic Semiconductor Development Company 52 Panasonic 3 4 5 Interrupt Acceptance Operation Interrupts Operation The MN101C46F uses hardware to save the program s return address PSW and the like to the stack when an interrupt is accepted It then jumps to the start address of the interrupt program specified in the interrupt vector table The fol lowing shows the sequence of hardware processing when an interrupt is accepted 1 The stack pointer SP value is updated SP 6 SP 2 handy address register is saved to the stack
103. lt 10 Off On Off On Off Notes 1 compare level reference level 2 The numbers 1 to 6 correspond to the numbers in figure 10 5 Table 10 5 provides the registers used to control and monitor the clamping circuit See the page number indicated for register and bit descriptions Table 10 5 Control Registers for Clamping Circuit CCDO CCD1 Register Address Address Description Register for selecting the low pass filter NFSELH 191 x O3EAl x 03E61 Noise filter select register high NFSEL 191 x 03E40 x 03E60 Noise filter select register Registers for controlling clamping SCMINGH 192 x 03E45 x 03E65 Minimum sync level detection interval set register high SCMING 192 x 03E44 x 03E64 Minimum sync level detection interval set register SYNCMIN 193 x OSEAS x 03E68 Minimum sync level register BPPSTH 192 03 47 03 67 Backporch position register high BPPST 192 x 03E46 x 03E66 Backporch position register BPLV 193 03 49 x 03E69 Pedestal level register CLAMPH 194 x OSE4D x 03E6D Clamping control register high CLAMP 194 x 03E4C x 03E6C Clamping control register CLPCND1 197 x 03E5C x 03E7C Clamping control signal status register 1 10 3 3 Sync Separator Circuit A low pass filter and a sync separator comprise this block The sync s
104. lt 8 gt 72 SUBC SUBC Dn Dm Dm Dn CF Dm e eee 3 2 O 0010 1011 DnDm 73 SUBW SUBW DWn DWm DWm DWn gt DWm 3 0010 0100 00Dd 1 74 SUBW DWn Am Am DWn Am eees3 3 0010 0100 10Da 74 SUBW imm16 DWm DWm imm16 DWm ojoo 4 0010 0100 0104 H6 gt 75 SUBW imm16 Am 16 gt 1 0010 0100 011a lt 16 gt 75 MULU MULU Dn Dm Dm Dn2DWk 016 8 0010 1111 1110 4 76 DIVU DIVU Dn DWm DWm Dn2DWm4 DWmh 3 9 0010 1110 111d 5 77 CMP Dn Dm Dm Dn PSW 2 0011 0010 DnDm 78 CMP imm8 Dm Dm imm8 PSW 2 1100 00Dm lt 8 gt 78 imm8 abs8 mem8 abs8 imm8 PSW 63 0000 0100 abs 8 lt 8 gt 79 CMP imm8 abs12 mem8 abs12 imm8 PSW e eee 3 0000 0101 abs 12 gt 8 gt 79 CMP imm8 abs16 mem8 abs16 imm8 PSW 4 5 0011 1101 1000 abs 16 gt B gt 80 CMPW CMPW DWn DWm DWm DWn PSW eeee 3 3 0010 1000 01Dd 81 CMPW DWn Am Am DWn PSW eeee 3 0010 0101 11Da 81 CMPW An Am Am An PSW eeee 3 0010 0000 01Aa 2 82 CMPW immi6 DWm DWm imm16 PSW 3 1100 110d lt 16 gt 82 CMPW imm16 Am Am imm16 PSW eeees6 3 1101 110a 4H6 gt 83 Logical manipulation instructions AND AND Dn Dm Dm amp Dn gt Dm 090063 2 0011 0111 DnDm 84 AND imm8 Dm Dm amp imm8 Dm 4 2 0001 11Dm lt 8 gt 84 AND imm8 PSW PSW amp imm8 PSW 5 3 0010 1
105. mem8 abs16 amp bpdata PSW 0 7 6 0011 1100 abs 16 gt 94 1 mem8 abs16 bp BCLR BCLR io8 bp mem8 lOTOP io8 amp bpdata PSW 0e 0O e 5 5 0011 1000 1bp i8 gt 95 0 mem8 OTOP i08 bp BCLR abs8 bp mem8 abs8 amp bpdata PSW 4 4 1011 1bp abs 8 95 0 memB8 abs8 bp BCLR abs16 bp mem8 abs16 amp bpdata PSW e 7 6 0011 1100 1bp abs 16 gt 96 0 mem8 abs16 bp BTST BTST imm8 Dm Dm amp imme PSW 01 0 5 3 0010 0000 11Dm 48 gt 97 BTST abs16 bp mem8 abs16 amp bpdata PSW 016 0 7 5 0011 1101 abs 16 gt 97 Branch instructions Bcc BEQ label if ZF 1 PC 3 d4 label H PC 3 23 1001 000H lt d4 gt 1 98 if ZF 0 PC 32PC BEQ label if ZF 1 4 17 1 4 2 8 1000 1010 d7 2 98 if ZF 0 PC 4 gt PC BEQ label if ZF 1 PC 5 d11 label H PC 5 23 1001 1010 lt di1 WH 3 99 if ZF 0 5 BNE label if ZF 0 PC 3 d4 label H PC 3 23 1001 001H lt d4 gt 1 100 if ZF 1 PC 32PC BNE label if ZF 0 PC 4 d7 label H PC 4 23 1000 1011 d7 H 2 100 if ZF 1 PC 4 gt PC BNE label if ZF 0 PC 5 d11 label H PC 5 23 1001 1011 lt fl H 3 101 if ZF 1 PC 5PC BGE label if VF NF 0 PC 4 d7 label H gt PC 4 12 3 1000 1000 d7 H 2 102 if VF NF 1 PC 4PC
106. output pins either match output to an external level or control the direction from the input side For input pins fix the level externally The MN101C46F has one system clock generating circuit set It then produces two clocks OSC and XI by dividing the system clock internally OSC is the fast clock for NORMAL mode and XI is the slow clock for SLOW mode Use the CPU mode control register CPUM to move between NORMAL and SLOW mode or to invoke standby modes The normal reset operations and interrupts are available as sources to return from standby modes Waits for oscillation to sta bilize are inserted during reset operations and when returning from STOP mode they are not inserted when returning from HALT mode The CPU automatically returns the system clock s oscillation mode to the mode it was in prior to invoking standby mode Panasonic Semiconductor Development Company MN101C46F LSI User Manual 37 Panasonic Basic CPU Functions Standby Function 2 12 2 CPU Mode Control Register Use the settings of flags in the CPU mode control register CPUM to change modes CPUM CPU Mode Control Register x 03F00 Bit 7 6 5 4 2 1 0 oe or Eu STOP HALT OSCI OSCO Rest 0 0 0 0 0 0 0 R W RW RW RW RW RW RW RW Table 2 8 Controlling the Operating Mode and Generating Halting Clock Oscillation Modes Operating OSCI CPU Input Mode STOP HALT OSC1 OSCO
107. sets to 0 indicating an asynchronous state This allows the device to determine the quality of the signal 10 3 3 2VSYNC Separator The VSYNC separator extracts the VS YNC signal from the composite signal Like the HSYNC separator it contains programmable methods for eliminating noise The VCNTH and VCNT registers contain these settings Masking the OH to 127H range by setting the VSEPSEL bit of VCNTH to 0 prevents VSYNC errors due to noise See figure 10 8 VSYNC 127H signal Figure 10 8 VSYNC Masking 10 3 3 3Field Detection Circuit The field detection circuit detects the phase difference between VSYNC and HSYNC based on the setting in the VPHASE 9 0 field of the FIELDH and FIELD registers This setting is in units of the sampling clock for the HS YNC separator The results of the field detection are stored in the ODDEVEN bit of FIELDH MN101C46F LSI User Manual Panasonic Semiconductor Development Company 180 Panasonic Closed Caption Decoder Functional Description 10 3 4 Data Slicer The data slicer contains the maximum and minimum detection circuits the slice level calculator and the slicer The circuit compares the 8 bit digital values output from the ADC to the slice level which can be calculated by the hardware or set in the software It then outputs the results in serial Os and 1s The data slicer calculates the slice level the level above which
108. soft ware Set the interrupt levels This operation sets interrupt levels using the xxxLV 1 0 flag of the interrupt control register xxx ICR Set the IM 1 0 flag of the PSW if you need to change the interrupt acceptance level of the CPU Enable interrupts This operation sets the xxxIE flag of the interrupt control register xxxICR to enable interrupts Enable all maskable interrupts This operation sets the MIE flag of the PSW and enables maskable interrupts MN101C46F LSI User Manual Panasonic Semiconductor Development Company 58 Panasonic Interrupts Interrupt Control Registers 3 6 Interrupt Control Registers The interrupt control registers are comprised of the nonmaskable interrupt control register NMICR external interrupt control registers IRQnICR and internal interrupt control registers xxxICR Table 3 4 Interrupt Control Registers Disable all maskable interrupts with the MIE flag of the PSW register before writing to the interrupt con trol register Register Address R W Register name NMICR x O3FEI R W Nonmaskable interrupt control register IRQOICR x 03FE2 R W External interrupt 0 control register IRQIICR x 03FE3 External interrupt 1 control register IRQ2ICR x 03FE4 R W External interrupt 2 control register IRQ3ICR x 03FES External interrupt 3 c
109. the maskable interrupt enable flag MIE flag of the PSW is set to 1 Vector numbers are preset for maskable interrupts in the hardware but you can give interrupts priorities with a user program by setting the interrupt level flag field LV 1 0 There are three levels of interrupt priorities when multiple interrupts have the same priority level the one with the lowest vector number has the highest priority A maskable interrupt is accepted if the level set for it in the interrupt level field LV 1 0 is higher than the level in the interrupt mask level field IM 1 0 of the PSW No level is specified for nonmaskable interrupts they are always accepted with top priority MN101C46F LSI User Manual Panasonic Semiconductor Development Company 46 Panasonic Interrupts Functions 3 2 Table 3 1 Interrupt Functions Functions interrupts Interrupt Types Reset Interrupt Nonmaskable Interrupt Maskable Interrupts Vector No 0 1 2 27 Table address x 04000 x 04004 x 04008 x 0406C Start address Specify with the vector table Interrupt level Levels 0 2 programmed Interrupt source External RST pin input Software fault detection PI Interrupts from external pin input or internal periph eral functions Interrupt generation Input directly to CPU core Input to CPU core from the nonmaskable interrupt control register NMICR The interrupt request level set in the interrupt level fla
110. 0 PC 6 d16 label H gt PC JSR label SP 3 9SP PC 7 bp7 0 mem8 SP 7 8 0011 1001 1aaH abs 18b 15 0 gt 55 130 PC 7 bp15 8 mem8 SP 1 PC 7 H gt mem8 SP 2 bp7 0 mem8 SP 2 bp6 2 PC 7 bp17 16 smem8 SP 2 bp1 0 abs18 label H PC JSRV tbl4 SP 3 9SP PC 3 bp7 0 mem amp SP 3 9 1111 1110 lt t4 gt 131 PC 3 bp15 8 mem8 SP 1 PC 3 H mem8 SP 2 bp7 0 mem8 SP 2 bp6 2 PC 3 bp17 16 mem8 SP 2 bp1 0 mem8 x004080 tbl4 2 2PC bp7 0 mem8 x 004080 tbl4 lt lt 2 1 gt PC bp15 8 mem8 x 004080 tbl4 lt lt 2 2 bb7 PC H mem8 x 004080 tbl4 lt lt 2 2 bp1 0 gt PC bp17 16 NOP NOP PC 2 gt PC O 0000 0000 132 NOTE Pages for MN101C00 Series Instruction Manual 1 d7sign extension 2 411 sign extension 8 412 sign extension 4 16 sign extension 5 aa abs18 17 16 MN101C46F LSI User Manual Panasonic Semiconductor Development Company 244 Panasonic MN101C SERIES INSTRUCTION SET MNI01C Series Instruction Set Group Mnemonic Operation Flag Cod Re Exten Machine Code Notes Paga VF NF CF ZF Size peat sion 1 3 4 6 7 9 10 11 RTS RTS mem8 SP PC bp7 0 0000 0001 133 mem8 SP 1 PC bp15 8 mem8 SP 2 bp7 PC H mem8 SP 2 bp1 0 gt PC bp17 16 SP 3 SP RTI RTI 8 5 gt 5
111. 00 5 Set the interrupt level TM2ICR x 03FEB bits 7 6 21 1 0 10 x Set the interrupt level using the TM2LV 1 0 field in the timer 2 interrupt control register TM2ICR If the interrupt request flag might have already been set clear the request flag See section 3 5 Setting the Interrupt Flags 6 Enable interrupts 2 x 03FEB bit 1 TM2IE 1 Enable interrupts by setting the TM2IE flag of the TM2ICR register to 1 7 Start the timer TM2MD x 03F5C bit 3 TM2EN 1 S Set the TM2EN flag of the TM2MD regis ter to 1 to start timer 2 TM2BC starts counting from x 00 When TM2BC matches the value set in the TM2CC register the timer 0 interrupt request flag is set at the next count clock and TM2BC starts counting up again from x 00 You can switch between binary counters in the count up by changing the TMnEN flag of the TMnMD register at the same time as another bit MN101C46F LSI User Manual Panasonic Semiconductor Development Company 102 Panasonic 8 Bit Timers Operation of the 8 Bit Timer Cascade Connection 6 3 Operation of the 8 Bit Timer Cascade Connection The cascade connection links timers 2 and 3 so they can be used together as a single 16 bit timer The cascaded timer runs on the clock source of timer 2 which corresponds to the eight low order bits Table 6 4 Functions of Cascaded Timers Timer 2 Timer 3 16 bits
112. 001 0010 48 gt 85 OR OR Dn Dm DmIDn Dm 0 oe 3 2 0011 0110 DnDm 86 OR imm8 Dm Dmlimm8 Dm 01 oe 4 2 0001 10Dm lt 8 gt 86 OR imm8 PSW PSWlimm8 gt PSW ee9925 3 0010 1001 0011 48 gt 87 XOR Dn Dm Dm Dn2Dm 0 e 0 e 3 2 0011 1010 DnDm 9 88 XOR imm8 Dm Dm imm82Dm 0 e oe 5 3 0011 1010DmDm lt 8 gt 88 NOTE Pages for MN101C Series Instruction Manual 4 D DWn d DWm D DWm 9 m n 2 A An a Am 6 4 sign extension 53 d DWm 7 8 sign extension 54 D DWk 8 Dn zero extension Panasonic Semiconductor Development Company MN101C46F LSI User Manual 241 Panasonic MNIOIC Series Instruction Set MN101C SERIES INSTRUCTION SET Group Mnemonic Operation Flag E UE Re Exten Machine Code Notes Pag CF ZF Size peat sion 1 2 3 4 5 6 7 8 9 10 11 NOT NOT Dn Dn Dn 0 0 0083 0010 0010 10Dn 89 ASR ASR Dn Dn msbtemp Dn Isb CF 2 0010 0011 10Dn 90 Dn gt gt 1 Dn temp Dn msb LSR LSR Dn Dn lsb2CF Dn 1 Dn 0 0 2 O 10010 0011 11Dn 91 0 Dn msb ROR ROR Dn Dn Isb temp Dn gt gt 1 Dn 2 O 0010 0010 11Dn 92 CF Dn msb temp gt CF Bit manipulation instructions BSET io8 bp mem8 IOTOP io8 amp bpdata PSW 1000 1 mem8 IOTOP io8 bp BSET abs8 bp mem8 abs8 amp bpdata PSW 214 1011 abs 8 93 1 mem8 abs8 bp BSET abs16 bp
113. 00c IDnup W 42SN IST HOFOIOINIW AOJINPUOIIWAY 21 Remote input signal RMTC x 03E04 7 6 5 4 3 2 1 0 division 3 58 MHz 0 28 us RMIN gt x Noise filter Normal PWM5 Slow PWM3 17 9 us Normal PWM7 Slow PWM5 71 5 us fu ej 5 4 s a 1 0 x 03EAC CK 4 Polarity select Sampling counter x Write instruction Ts Sampling CK Edge R detection circuit 6 bit counter A Overflow counter value Normal PWM2 C S l Slow PWM0 447 5 kHz 2 2 us Clock supply stops upon overflow 7 6 5 4 3 2 1 0 RMIR x 03EA2 6 Counter value bs e Ep PESE nc 2 e 2 T 5 6 bit C CK CK Short leader leader Data format Short long Long N detection detection detection detection pi Reset g Q s RMSR x 03EA8 7 6 41312 110 LU _ Loading of 8 bit 6 bit counter overflow R eceived data Remgte signal edge detection gt ck oa counter 7 6 5 413 211 0 CK CK Y Y R a T Reset 7 RMTR ea ECX RMIS x 03EA0 Figure 11 1 IR Remote Signal Receiver Block Diagram RMCICR x 03FFB RMCIR bit 0 weibeig Z
114. 1 MEMCTR R W Memory control register x 03FOD OSCMD R W Oscillation frequency control register x 03FE0 Reserved R W For debugging x OSFEI NMICR R W Nonmaskable interrupt control register See section 3 Inter rupts on page 59 x O3FE2 xxxICR R W Maskable interrupt control registers See section 3 Inter x 03FFE rupts on page 59 x 03FFF Reserved Use to read interrupt vector information in hardware servicing of interrupts Note Some CPUM bits are read only Panasonic Semiconductor Development Company MN101C46F LSI User Manual 23 Panasonic Basic CPU Functions Organization of Instruction Execution Controller 2 5 Organization of Instruction Execution Controller The instruction execution controller is comprised of four blocks memory the instruction queue the instruction register and the instruction decoder Instructions are fetched in bytes and temporarily stored in the 2 byte instruction queue They are transferred from the instruction queue in bytes or half bytes to the instruction register where they are decoded by the instruction decoder Memory Instruction queue Instruction register Instruction decoder Fetch 15 0 C 1 or 0 5 bytes Instruction decoding CPU control signal Figure 2 2 Organization of the Instruction Execution Controller MN101C46F LSI User Manual 24 Panasonic
115. 1 OR mode GSHT Graphics shutter control 0 Disable 1 Enable BCSHT Text background shutter control 0 Disable 1 Enable CCSHT Character shutter control 0 Disable 1 Enable MN101C46F LSI User Manual Panasonic Semiconductor Development Company 152 Panasonic On Screen Display OSD Registers COLB Color Background Register x 03ED0 Bit 7 6 5 4 3 2 1 0 COLB COLB COLB COLB COLB COLB COLB COLB YM YS BH GH RH B G R Reset 0 0 0 0 0 0 0 0 R W RW R W RW RW RW RW R W RW Sets color when background is colored COLBYM YM output COLBYS YS output COLBBH BOUT pin high impedance control 0 Push pull control 1 High impedance COLBGH GOUT pin high impedance control 0 Push pull control 1 High impedance COLBRH ROUT pin high impedance control 0 Push pull control 1 High impedance COLBB Blue digital output push pull COLBG Green digital output push pull COLBR Red digital output push pull FRAME Outlining and Character Shadowing Color Register x 03ED2 Bit 7 6 3 4 3 2 1 0 FRAME FRAME FRAME FRAME FRAME FRAME FRAME YM YS BH GH RH B G R Reset 0 0 0 0 0 0 0 0 R W RW R W RW RW RW RW R W RW Sets color of outlines and shading FRAMEYM YM output FRAMEYS YS output FRAMEBH BOUT pin high impedance control 0 Push pull control 1 High impedance FRAMEGH GOUT pin high impedance control 0 Push pull control 1
116. 13 7 3 7 Conditions for Writes 113 7 4 Display Setup Examples 114 74 1 Setting Up the Display without 114 74 2 Setting Up the Display with 116 7 5 ST Lee dee ROO dnd u ae 118 7 5 1 VRAM Bit Assignments in Internal 118 7 5 2 VRAM Operation sinc fs cnp phi UPS DIEN PEE UP bt ba bb ue P RESP E Rp 118 7 5 3 VRAM 522 dd CPP DRE 121 7 6 ROM iade Re ORC ee S QA TA like ERN Y TG 122 7 6 1 ROM Organization erede d eR pce eed RP 122 MN101C46F LSI User Manual Panasonic Semiconductor Development Company iii Panasonic Contents 7 6 2 Graphics ROM Organization in Different Color 123 77 Setting up the OSD sida uy apu iue e Re e ELE 126 77 1 Setting OSD Display Colors 77 126 7 7 2 Text ayer Bunctions v RERO RR RO C tr e UN BUR EUR 129 7 1 3 Display S1ze8 es x ARRIANUS ege 132 77 4 Setting Up OSD Disp
117. 2 14 Bit PWM Output Waveforms Figure 14 2 shows 14 bit output waveform This example assumes fsyscr Kk 3 58 MHz PWM output modulated by the 14 bit PWM s high order 7 bits TDCHR data whose cycle is tsup 71 5 us is overlapped with an added pulse whose minimum pulse is at the 128 types of positions set by the 14 bit PWM low order bits TDCLR data and then output PO P1 P2 P3 Pn P127 Added pulses BETA 71 5 us tsuB tstp Figure 14 2 14 Bit PWM Output Waveform Figure 14 4 shows the relationship of the tsup 71 5 us cycle to the PWM output of the high order 7 bit TDCHR data Table 14 1 shows the relationship of the position of the added pulse overlapped by the TDCLR data low order 7 bits of the 14 bit PWM data Figure 14 4 shows the output waveform diagram TDCHR data tsup 71 5 us fsvscu 3 58 MHz 7F 7E 70 1 i 00 Minimum pulse width 0 56 us Figure 14 3 tsyg PWM Output Waveform Table 14 1 Added Pulse Overlapping Position TDCLR Data Pn on which Added Pulse Is overlapped n 0 to 127 TF 127 TE 63 127 7D 31 95 127 7 31 63 95 127 7B 15 47 79 111 127 7 15 47 63 79 111 127 01 0 to 127 except 63 00 0 to 127 MN101C46F LSI User Manual Panasonic Semiconductor Development Company 228 Panasonic Pulse Width Modulator 14 Bit Pulse Width Modulator tsrp 9 152 ms 3 58 MHz 31 63 95 1
118. 2 Timer 3 Timer 4 DAC fosc 2 fosc 4 Y Y Y fosc 16 fosc 32 Y fosc 64 Y fosc 128 6 2 Y Y Y fs 4 Y E fs 8 4 Panasonic Semiconductor Development Company MN101C46F LSI User Manual 93 Panasonic Prescalar Description 5 1 2 Prescalar Block Diagram PSCMD 3 bit prescalar TM3PSCO ess seal 1 L TM4BAS TM4PSC0 TM4PSC1 r l BBN Qo RS aan 539 DR 2 8 BLD 2 08 69 9 0 Figure 5 1 Prescalar Block Diagram MN101C46F LSI User Manual Panasonic Semiconductor Development Company 94 Panasonic 5 2 Prescalar Prescalar Control Registers Prescalar Control Registers 5 2 1 Prescalar Control Registers There are four prescalar control registers Table 5 2 Prescalar Control Registers Register Address R W Description PSCMD x 03F6F R W Prescalar control register CK2MD x 03F5E R W Timer 2 prescalar select register CK3MD x O3F5F Timer 3 prescalar select register CK4MD x 03F66 R W Timer 4 prescalar select register Use the prescalar control register PSCMD the timer prescalar select registers CKnMD and the serial transfer clocks select registers SCnCKS to control prescalar operation and select prescalar output PSCMD Prescalar control register x 03F6F Bit 7 6 5 4 3 2 1 0 PSCEN Reset 0 0 0 0 0 0 0
119. 27 TDCLR data 01 ILL Overlapping pulse tsug PWM waveform determined by high order 7 bits suB 71 5 us Figure 14 4 Added Pulse Waveform 14 1 3 Data Transfers from Registers to Latches When TDCC is set to 11 14 bit data is transferred from a 14 bit PWM data register to a 14 bit PWM data latch during the repeat cycle of the high order 7 bits of the next PWM This is to prevent the PWM waveform from being dis rupted by changes in the data that may occur partway through the PWM waveform If TDCC is set to 00 the 14 bit PWM output waveform does not change even when the 14 bit PWM data register value is rewritten Panasonic Semiconductor Development Company MN101C46F LSI User Manual 229 Panasonic Pulse Width Modulator 8 Bit Pulse Width Modulators 14 2 8 Bit Pulse Width Modulators The MN101C46F has six 8 bit PWMs These PWMs have resolutions of eight bits minimum pulse widths of 2 and cycles of 2 14 2 1 8 Bit PWM Description The MN101C46F has six 8 bit PWM blocks The 8 bit registers PWMn are used to write pulse width modulation data concerning the PWM blocks The 8 bit PWM output waveform or repeat cycle is 143 us and the minimum pulse width is 0 56 us Figure 14 5 shows a block diagram of the 8 bit PWMs Data Bus S MSB PWMO PWM5 7 5l4 la 2l1 x 03E90 xOSE9A PwM DAC output Dx
120. 5 CRI2SWH CRI Capture Start Timing Control Register 2 High x 03E35 CRI28 CRI Capture Start Timing Control Register 2 x O3E14 CRI2SW CRI Capture Start Timing Control Register 2 x 03E34 Bi 7 6 5 4 3 2 1 0 7 6 5 4 2 1 0 CRDS CRI2S CRDS CRI2S CRDS CRDS CRDS CRI2S CRDS CRI2S CRDS 10 9 8 7 6 5 4 2 1 0 Reset 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 R RW RW RW RW RW RW RW RW RW RW RW CRI2S 10 0 Start position for CRI capture 2 Valid range x 000 to x 7FF CRI2EH CRI Capture Stop Timing Control Register 2 High x 03E17 CRI2EWH CRI Capture Stop Timing Control Register 2 High x 03E37 CRI2E CRI Capture Stop Timing Control Register 2 x 03E16 CRI2EW CRI Capture Stop Timing Control Register 2 x 03E36 Bit 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 CRDE CRDE CRDE CRDE CRDE CRDE CRDE 2 2 10 9 8 7 6 4 3 2 1 0 Reset 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 R W R R R R R RW RW RW R W RW RW RW RW RW RW RW CRI2E 10 0 Stop position for CRI capture 2 Set this field so that the last CRI rising edge is included The valid range is x 000 to x 7FF Panasonic Semiconductor Development Company MN101C46F LSI User Manual 189 Panasonic Closed Caption Decoder Closed Caption Decoder Registers DATASH Data Capture Start Timing Control Register High 03 19 DATASWH Data Capture Start Timin
121. 5 j cRoMENp Line 18 data GROMEND 5A GROMEND 59 GROMEND 07 Code 01 graphics data GROMEND 6c GROMEND 68 GROMEND 1C Code 00 graphics data GROMEND All addresses are expressed in hex notation Other values are decimal GROMEND Graphics ROM end address register programmable to any address CROMEND Text ROM end address register programmable to any address M Number of text fonts 1 N Number of graphic fonts 1 8 color mode Figure 7 5 ROM Organization 6 bytes 8 color mode GROMEND 7 She GROMEND 6 1 GROMEND 5 She GROMEND 4 GROMEND 3 She GROMEND 2 i j GROMEND 1 She et 1 bits 7 to 0 Sheet 1 bits 15 to 8 et 2 bits 7 to 0 Sheet 2 bits 15 to 8 et 3 bits 7 to 0 Sheet 3 bits 15 to 8 et 4 bits 7 to 0 Sheet 4 bits 15 to 8 MN101C46F LSI User Manual 122 Panasonic Panasonic Semiconductor Development Company On Screen Display ROM Z 6 2 Graphics ROM Organization in Different Color Modes The graphics layer supports up to eight colors in the 8 color mode It also supports a 4 color mode The smaller the number of colors the less ROM area required per tile The figures in this section illustrate the ROM organization for each color mode The example in figure 7 6 demonstrates the graphics ROM setup for line 18 of the code 00 data when the graphics layer is in 8 color mode The three bits of data for each pixel in sheets 1
122. 5 Graphic Size Combinations MN101C46F LSI User Manual Panasonic Semiconductor Development Company 132 Panasonic On Screen Display Setting up the OSD Character sizes x1 x2 x3 x4 b 00 b 01 b 10 b11 HSZ 1 0 t t t t gt b 00 T x1 b 01 x2 10 4 72 b 11 T x6 108 VSZ 1 0 Y The settings shown are for interlaced displays In progressive displays the vertical size settings VSZ 1 0 are as follows 01 1x 10 2x and 11 2 3x The 00 setting is invalid Figure 7 16 Character Size Combinations Panasonic Semiconductor Development Company MN101C46F LSI User Manual 133 Panasonic On Screen Display Setting up the OSD 1 When you write new values to the m GIVP and CIVP fields the settings take effect on the next VSYNC pulse This means that changes are reflected in the next display screen rather than the current one 7 7 4 Setting Up the OSD Display Position This section describes how to control the positioning of the OSD To set the horizonta
123. 6 KB Reserved area x 0x1FFFF Note The shaded region is write protected in this mode Figure B 1 Memory Map for Internal Flash EEPROM B 2 Benefits Because you can maintain and upgrade the program in the MN101CF46F up to and immediately following product release this version of the device shortens time to market by as much as one month This device is ideal for applications in quickly changing markets since it allows you to revise the microcontroller program in an existing product Panasonic Semiconductor Development Company MN101C46F LSI User Manual 237 Panasonic MN101CF46F Flash EEPROM Version Using the PROM Writer Mode B 3 Using the PROM Writer Mode In this mode the MN101CF46F allows a PROM writer to program the internal flash memory as if it was a standalone memory chip The microcontroller is inserted into a dedicated adaptor socket which connects to DATA I O s LabSite PROM writer When the microcontroller connects to the adaptor socket it auto matically enters PROM writer mode The adaptor socket ties the microcontroller pin states to PROM writer mode and programming occurs without any reference to the microcontroller pin states MN101CF46F Adaptor socket for MN101CF46F Third party PROM writer Figure B 2 PROM Writer Hardware Setup NS Vep 1 40 VoD NCE 2 39 NWE 015
124. 66 Panasonic I O Ports I O Port Circuit Diagrams 4 2 1 0 Port Circuit Diagrams 0 Pullup off 1 Pullup on POPUPO 0 1 RMIN IRQO 5b ax o 0 Port input 1 Port output PODIRO 0 Port low output 1 Port high output POOUTO 173 E POINO 1 Schmidt trigger RMIN IRQ0 Figure 4 1 P00 RMIN IRQ0 Port 0 Panasonic Semiconductor Development Company MN101C46F LSI User Manual 67 Panasonic I O Ports 1 0 Port Circuit Diagrams 0 Pullup off 1 Pullup on c POPUP1 0 P01 1 SDA1 lt POMD1 0 Port input 1 Port output lt gt PODIR1 0 Port low output Pin 1 Port high output 0 c POOUT1 M LJ P01 974 SDA1 X 1 SDA output POIN1 f Schmidt trigger SDA input 5 I CSEL1 e I2CSEL0 0 Pullup off 1 Pullup on lt gt P4PUP1 0 P41 1 SDA0 lt PAMDi ee 0 Port input 1 Port output lt gt P4DIR1 J gt 0 Port low output Pin 1 Port high output 0 lt g
125. 7 12 Bus Interface Registers I2CDTRMH 2 Transmission Data Register High x 03E81 I2CDTRM 2 Transmission Data Register X 03E80 Bit 7 6 4 3 2 1 0 7 6 5 4 9 2 1 0 STA STP ACK DT7 DT6 DTS DT4 DT3 DT2 DTI DTO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R RW RW RW RW RW RW RW RW RW RW RW STA 12 start control 1 STP stop control z Writing to the STA and STP bits allows you to change the state of the SCL is held low during interrupt transmission or reception operation Table 13 6 shows the settings for dif servicing and is cleared high by a ferent start and stop conditions write to I2CDTRM Table 13 6 STA and STP Settings STA STP Mode Function Description 0 0 All NOP No state change 1 1 All NOP No state change 1 0 Slave receiver Start Change to mode indicated by R W bit Master transmitter Repeat start R W 0 Change to master transmitter R W 1 Change to master receiver 0 1 Slave receiver Stop read Change to slave receiver after stop condi Master transmitter Stop write tion ACK Acknowledge signal output control The acknowledge signal is output after every byte transfer on the ninth clock pulse ACK is normally 1 and transitions to 0 to output an acknowl edge for instance if the master or slave receiver has received a data byte DT 7 0 Data to be tra
126. 8 bus reset register I2CBSTS 226 x 03E8A bus status register Arbitration and bus busy control The bus controller allows software control but implements communication timing and bus arbitration completely in the hardware Arbitration Controlled by the software but implemented completely in the hardware MN101C46F LSI User Manual Panasonic Semiconductor Development Company 216 Panasonic I C Bus Controller Functional Description Bus busy Checked by the hardware This eliminates the need for the software to check whether the bus is busy The program can request a transfer to the bus at any time Conversion of register settings to 12 protocol The bus controller converts the data in the IDDCCDTRM register to the PC protocol Changes of transfer mode A write to the I2CDTRMH register indicates the transfer mode master trans mitter receiver or slave transmitter receiver for a new transfer To minimize software control the hardware generates an interrupt each time a transfer ends During interrupt servicing the SCL line stays low then clears to high on a write to I2CDTRMH When the microcontroller is a slave transmitter and the transfer ends SCL goes high on a read to the I2CDRECH register after ACK 1 negative acknowledge interrupt B Multimaster support The hardware performs bus arbitration for a multimaster system When it loses an arbitration
127. APDATAH Caption Data Capture Register High x 03E0B CAPDATAWH Caption Data Capture Register High x 03E2B CAPDATA Caption Data Capture Register x 03E0A CAPDATAW Caption Data Capture Register x 03E2A Bit 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP DA15 DA14 DAI3 DA12 DA10 DA9 DA7 DA6 DAS DA4 DA3 DA2 DAI DAO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R R R R R R R R R R R R R R R R CAPDA 15 0 Caption data These registers stores the 16 bit captured caption data CRI2FQW CRI Frequency Width Register A High x 03E0D CRI2ZFQWW CRI Frequency Width Register A High x 03E2D CRHFQW CRI Frequency Width Register x 03E0C CRHFQWW CRI Frequency Width Register x 03E2C Bit 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 CRD CRI2 CRI2 CRD CRI2 CRD FQW7 FQW6 5 FQW4 FQW3 FQW2 FQW1 FQWO FQW7 6 FQWS FQW4 FQW3 FQW2 FQW FQWO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R R R R R R R R R R R R R R R The 2 and CRIIFQW registers store the CRI cycles from rising edge to rising edge for monitoring whether the CRIs were detected cor rect
128. An HA gt 16 2 39 001 011A 52 MOVW imm8 DWm sign imm8 DWm 4 2 0000 110d lt 8 gt 5 53 MOVW imm8 Am zero imm8 Am 4 2 0000 111a lt 8 gt 53 MOVW imm16 DWm imm16 DWm 6 3 1100 111d lt 16 Veios DR 54 NOTE Pages for the MN101C Series Instruction Manual i d8sign extension 4 A An a Am 2 d4zero extension 5 8 sign extension 3 d8 zero extension 6 8 zero extension MN101C46F LSI User Manual Panasonic Semiconductor Development Company 240 Panasonic MNIOIC Series Instruction Set MN101C SERIES INSTRUCTION SET Group Mnemonic Operation Flag Coddcycid Re jexten Machine Code Notes Pag VF NF CF ZF Size peat son 2 3 4 5 6 7 8 9 10 11 MOVW imm16 Am imm16 Am 6 3 1101 111 4H6 gt 54 MOVW SP Am SP Am 3139 0010 0000 100a 55 MOVW An SP An SP 3 3 0010 0000 101A 55 MOVW DWn DWm DWn DWm 3 3 0010 1000 00Dd 1 956 MOVW DWn Am DWnAm 3 3 0010 0100 11Da 56 MOVW An DWm An gt DWm 3 3 0010 1100 11Ad 57 MOVW An gt Am 813 0010 0000 00Aa 2 57 PUSH PUSH Dn SP 1 SP Dn mem8 SP 03 1111 10Dn 58 PUSH An SP 2SP An gt mem16 SP 2 5 0001 011A 58
129. C B A 9 8 7 6 5 4 3 2 1 0 x 03D00 x 03D10 x 03D20 x 03D30 x 03D40 x 03D50 x 03D60 F SLCN SLCN x 03D70 VBI 1 x 03D80 x 03D90 x 03DAO x 03DBO x 03DCO x 03DDO x 03DE0 SLCN SLCN x 03DFO TW TW VBI 2 Table A 2 Register Map x 03E00 x 03EFF 12 4 LSBs n Description MSBs F E D C B AJ 9 8 7 6 5 4 3 2 1 0 CRM CRIB CRI2 CAP ACQI ACQI VBI HNU SLsF SLHD MAX MIN SL FC x 03E00 FQW FQW FQW FQW DATA DATA H IRQ M CNT H VBI 1 registers FCP FCP STAP STAP DATA DATA DATA DATA CRDE CRDE CRDS 128 5 5 x 03E10 NUM NUM EH E SH S H H H H H CAP CAP ACQ1 ACQI VBI HNU SLSF SLHD MAX MINW SLCN FCW x 03E20 QWW QWW QWW QWW DATA DATA WH W IRQW MW w w w TW WES MP VBI 2 registers FCP FCP STAP STAP DATA DATA DATA DATA CRDE CRDE CRDS CRDS 5 5 x 03E30 NUM WH W EWH EW SWH SW WH W H w WH W WH WH w gt 03 40 CLAM CLAM SPLV SPLV BPLV SYNC BPP BPPS SCMI SCMI FQSE FOSE NFSE NFSE X IH 1 PH P H MIN STH T NGH NG LH L LH L CLPC CLPC HVCO VCNT VCNT HDIS HDIS HLO HLO FIELD FIELD HSEP HSEP Sync separator 1 registers x 03E50 NDIH ND1 ND H TWH TW CKLV CKLV H 2H 2 H HSEP HSEP CLAM CLAM SPLV SPLV BP
130. Converter ADC Control Registers 8 4 ADC Control Registers A D conversion employs control registers ANCTRn and a data storage buffer 1 8 41 ADC Control Registers The following registers control A D conversion Table 8 8 ADC Control Registers Register Address R W Description ANCTRO x O3FBO R W A D control register 0 ANCTRI x 03FB1 R W A D control register 1 ANCTR2 x 03FB2 R W A D control register 2 ANBUFI x 03FB4 R A D conversion data storage buffer 1 ADICR x 03FFA R W A D conversion interrupt control register ANCTRO A D Control Register 0 x O3FBO Bit 7 6 5 4 3 2 1 0 ANSHI ANSHO ANCK1 ANCKO uM Rest 0 0 0 0 0 0 0 0 R W R W R W R W R W R W ANSH 1 0 Sample hold time 00 tap X 2 Ol tap X6 11 tap x 18 11 Do not use 0 A D conversion clock fap 1 tap 00 fg 2 01 fg 4 10 fg 8 ll fy x2 ANLADE A D ladder resistor control 0 A D ladder resistor OFF 1 A D ladder resistor ON Panasonic Semiconductor Development Company MN101C46F LSI User Manual 167 Panasonic Analog Digital Converter ADC Control Registers ANCTR1 A D Control Register 1 x O3FB1 Bit F 6 9 4 3 2 1 0 ANCHS ANCHS ANCSH 2 0 Reserved 1 Reserved Set to 0 ANSH 2 0 Analog input channel 000 ADINO 001 ADINI 010 ADIN2 PA2 011 ADIN3
131. D Timer 2 Mode Register x O3F5C Bit 7 6 5 4 3 2 T 0 TM2 TM2 Reset 0 0 0 0 0 0 0 0 R W R R R R R W R R W R W 2 Timer 2 count control 0 Stop count 1 Count TM2CK 1 0 Clock source select 01 tm2spc prescalar output 11 Disabled TM3MD Timer Mode Register x O3F5D Bit 7 6 5 4 3 2 1 0 TM3 TM3 TM3 CAS 225 Reset 0 0 0 0 0 0 0 0 R W R R R R W R W R R W R W TMSCAS Timer 3 operating mode select 0 Normal counting 1 Cascade connection TMSEN Timer 3 count control 0 Stop count 1 Count TM3CK 1 0 Clock source select 00 fosc 10 fx 01 tm3spc prescalar output 11 Disabled TM4MD Timer 4 Mode Register x O3F64 Bit 7 6 5 4 3 2 1 0 4 TM4 TMN CK0 Reset 0 0 0 0 0 0 0 0 R W R R R R R W R R W R W TM4EN Timer 4 count control 0 Stop count 1 Count TM4CK 1 0 Clock source select 00 fosc 10 fx 01 tm4spc prescalar output 11 Disabled MN101C46F LSI User Manual Panasonic Semiconductor Development Company 108 Panasonic On Screen Display Description 7 On Screen Display 7 1 Description Table 7 1 shows the OSD functions of the MN101C46F OSD allows you to display on screen text characters and graphic tiles of the same size 16 dots x 18 lines on the same line in any order You can also modify the ROM space that contains the text characters and t
132. DCIE DCIR Reset 0 0 0 0 0 0 0 0 R W R W R W R R R R R W R W The PC interrupt control register I2CICR is the register that controls interrupt levels interrupt enables and interrupt requests for Pc interrupts Use interrupt control registers with the maskable interrupt enable flag MIE of the PSW at 0 I2CLV 1 0 Interrupt level specification flag A 2 bit flag that sets the interrupt level Determines which of the CPU s levels 0 3 is assigned to the interrupt I2CIE Interrupt enable flag 0 Disable interrupt 1 Enable interrupt I2CIR Interrupt request flag 0 No interrupt request 1 Generate interrupt request NEW ADICR A D Conversion Interrupt Control Register x OSFFA Bit 7 6 4 3 2 1 0 ADLVI ADLVO ADIE ADIR Reset 0 0 0 0 0 0 0 0 R W R W R W R R R R R W R W The A D conversion interrupt control register ADICR is the register that controls interrupt levels interrupt enables and interrupt requests for A D conversion interrupts Use interrupt control registers with the maskable interrupt enable flag MIE of the PSW at 0 ADLV 1 0 Interrupt level specification flag A 2 bit flag that sets the interrupt level Determines which of the CPU s levels 0 3 is assigned to the interrupt ADIE Interrupt enable flag 0 Disable interrupt 1 Enable interrupt ADIR Interrupt request flag 0 No interrupt request 1 Generate interrupt request MN101C46F LSI User Manual Pa
133. DREGE OSD registers read write enable 0 Disable 1 Enable SCLKF 1 0 SYSCLK frequency select 00 SYSCLK x 4096 01 Dot clock 10 S YSCLK x 2 11 SYSCLK MN101C46F LSI User Manual Panasonic Semiconductor Development Company 92 Panasonic 5 Prescalar Prescalar Description 5 1 Description The MN101C46F has two prescalars that can be used simultaneously and shared between different peripheral functions They use the fosc and fs as their base clocks for counting Their hardware is structured as follows Prescalar fosc based 7 bit prescalar Prescalar 1 fs based 3 bit prescalar Prescalar 0 outputs divided clocks of fosc 2 fosc 4 fosc 16 fosc 32 fosc 64 and fosc 128 Prescalar 1 outputs divided clocks of fs 2 fs 4 and fs 8 Use pres calars when you are employing divided clocks based on fosc or fs in the fol lowing peripheral functions Timer 2 8 bit timer counter Timer 3 8 bit timer counter Timer 4 8 bit timer counter D A conversion function See section 2 10 3 Special Function Registers on page 32 for more infor mation on fosc and fs 5 1 1 Peripheral Functions that Use Prescalar Output The table below lists the clocks that are selectable for each of the peripheral functions that use the prescalar block Table 5 1 Peripheral Functions that Use Prescalar Output Selectable Peripheral Function Divided Clocks Timer
134. Development Company 87 Panasonic MN101C46F LSI User Manual I O Ports I O Port Control Registers P1MD Port 1 Output Mode Register Bit 6 4 3 2 1 0 PIMD7 PIMD6 PIMD5 PIMD4 PIMD3 PIMD2 PIMDI PIMDO Reset 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W 1 is an 8 bit access register P1MD7 P1MD6 P1MD5 P1MD4 P1MD3 P1MD2 P1MD1 P1MDO P17 output switch 0 17 2 1 PWM3 IRQ2 P16 output switch 0 P16 1 PWM2 P15 output switch 0 P15 1 PWMI P14 output switch 0 P14 1 PWMO P13 output switch 0 P13 1 SYSCLK or clock divided from SYSCLK P12 function switch 0 2 1 ADIN7 11 function switch 0 1 ADIN6 P10 function switch 0 P10 1 ADIN5 x 03F29 MN101C46F LSI User Manual Panasonic Semiconductor Development Company 88 Panasonic a Driving P2MD5 and P2MD6 high switches the functions of P22 and P23 to CLH and CLL Always set P2MD5 and P2MD6 to lor 0 simultaneously When one is set to 1 and the other is set to 0 closed caption decoders don t work correctly P2MD Port 2 Output Mode Register Bit 7 6 4 3 2 1 P2MD7 P2MD6 2 5 P2MD4 P2MD3 P2MD2 P2MDI P2MDO Reset 0 R W R W R W 0 0 0 0 R W R W R W 0 R W P2MD is an 8 bit access register P2MDT P2MD6
135. Field Detection Circuit Block Diagram 7 11 2 Description The 7 bit field counter in this block resets every HSYNC interval to count the system clock At each VSYNC interval the four MSBs of the 7 bit counter are alternately loaded made readable to bits 7 to 4 N2 and 3 to 0 N1 of the EVOD register x 03EBE The comparator compares the N1 and values and outputs the results to the EOMON bit of EVODH x 03EBF The OSD identifies the field that sets EOMON to 1 as the display start field Table 7 11 shows the criteria that the comparator uses By reading the FRMON bit of EVODH the OSD can determine which register the four MSBs will load to on the next VSYNC input To ensure that the display starts at the right field you must also set the EOSEL bit of EVODH so that EOMON becomes 1 at the display start field 774 FT Field counter value i QU Nu Load value to FREG2 Load value to 1 FRMON _ 00M Figure 7 24 Field Detection Timing MN101C46F LSI User Manual Panasonic Semiconductor Development Company 144 Panasonic On Screen Display Field Detection Circuit Table 7 11 EOMON Output Criteria EOMON Output FRMON N1 N2 Relationship EOSEL 0 EOSEL 1 0 N1 gt N2 0 1 Load to N2 next NI lt N2 1 0 Complement previous Complement previous 1 N1 gt N2 1 0 Load to N1 next NI lt N2 0 1 Complement previous Comple
136. For designs using the closed caption decoder always tie it to 0 HONTSEL 1 0 HSYNC count value select When this field is unused tie it to b 00 00 When odd add 1 to the HSYNC count value 01 When even add 1 to the HSYNC count value 10 No change to the HSYNC count value 11 Reserved SLICESEL Hard soft slice level select 0 Select hardware calculation 1 Select software setting Panasonic Semiconductor Development Company MN101C46F LSI User Manual 185 Panasonic Closed Caption Decoder Closed Caption Decoder Registers SLICELD 2 0 Slice level load timing sele ct When this field is unused tie it to b 000 000 1H100 1 field 001 2H101 2 fields 010 4H110 4 fields 011 8H111 8 fields MAX CRI Interval Maximum Register x 03E03 MAXW CRI Interval Maximum Register x 03E23 MIN CRI Interval Minimum Register x 03E02 MINW CRI Interval Minimum Register x 03E22 Bit 7 6 2 4 3 2 1 0 7 6 5 4 3 2 1 0 MAX7 MAX6 MAXS 2 MIN7 MIN6 MINS MIN3 MIN2 MINI MINO Reset 0 0 0 0 0 1 1 1 1 1 1 1 1 R W R R R R R R R R R R R R R R R R MAX 7 0 Maximum value during the CRI interval Valid range x 00 to x FF MIN 7 0 Minimum value during the CRI interval Valid range x 00 to x FF S
137. For horizontal shutters it is the number of pixels from the left of the screen Shuttering direction VSPO VSPI HSPO 0 Shutter below vertical shutters or to the right zontal shutters 1 Shutter above vertical shutters or to the left hori zontal shutters Shuttering mode control SHTRAD 0 AND the shuttered areas of all the shutters shared bit 1 OR the shuttered areas of all the shutters Determining the vertical shutter positions VSTO and VST1 The top edge of the television screen is x 000 Each integer higher brings the shutter position down one H scan line Determining the horizontal shutter positions HSTO and HST1 The left edge of the television screen is x 000 Each integer higher brings the shutter position right one pixel One pixel or one dot is the smallest display unit in the OSD Panasonic Semiconductor Development Company MN101C46F LSI User Manual 137 Panasonic On Screen Display Controlling the Shuttering Effect VSHTO Television screen HSHT1 VSHTO VSHT1 Television screen HSHTO HSHT1 VSHT1 HSHT1 Television screen VSHT1 VSONO VSON1 1 V shutters 0 and 1 on HSONO HSON1 1 H shutters 0 and 1 on VSPO 0 V shutter 0 shutters below VSP1 1 V shutter 1 shutters above 0 shutter 0 shutters to the right 1 H shutter 1 shutters to the left SHTRAD 0 All shutters ANDed Shuttered region VSONO VSON1
138. HADI BSHADO CSHAD FRAME BLINK BCOL2 BCOLI BCOLO CCOL2 CCOLI CCOLO Character color control code ID code Box shadow nd Outline Blink Background color select Text color select COL closed caption mode 1 0 CUNDL ITALIC BLINK BCOL3 BCOL2 BCOLI BCOLO CCOL3 CCOL2 CCOLI CCOLO Character color control code ID code Underline Italics Outline Blink Background color select Character color select CB 0 8 3 BF CB3 CB2 CB CBO Repeat character blank code Blank Number of blank char repetitions ID code A char 4 bits HP 1 571 HSZO SHT HP9 HP8 HP7 HP6 HP5 HP4 HP3 HP2 HP HPO H position control ID code H text size Shutter H display start position 1 dot resolution 1024 steps start position set in register IHP VP 1 LAST VSZI VSZO INT VP9 8 7 VP6 5 4 VP3 VP2 VP VPO V position control ID code Last line V text size Interrupt V display start position 1H scan line resolution 1024 steps start position set in register IVP AP 1 11 APIO AP9 AP8 AP7 AP6 5 4 2 RAM address pointer ID cod VRAM start code address position for next line 9906 lt 00100 x 00BFF Specify intemal RAM address Set initial address in the register t Don t care bits 7 5 2 VRAM Operation CC Character Code ID Code 00 CGSEL Selects text or graphic 0 Text 1 Graphic PLT 1 0 Select the palette PLTOx PLT3x CCH 8
139. I 1 x 03D80 x 03D90 x 03DAO x 03DBO x 03DCO x 03DDO x 03DEO R SLCN SLCN x 03DFO DW TIN VBI 2 CRI4 CRIB CRI2 ACQI ACQI VBI HNU SLSF SLHD MAX MIN SL FC x 03EO00 FQW FQW FQW DATA H IRQ M CNT H VBI 1 registers FCP FCP STAP STAP DATA DATA DATA DATA CRDE CRDE CRDS CRDS 5 5 x 03E10 H SH S H H H H H CAP ACQ1 ACQI VBI HNU SLSF SLHD MAX MINW SLCN FCW x O3E20 Qww QWW QWW QWW DATA DATA WH W IRQW MW W w w TW WH w VBI 2 registers FCP FCP STAP STAP DATA DATA DATA DATA CRDE CRDE CRDS CRDS 5 CRI1S x 03E30 WH W EWH EW S WH sw W WH W WH W WH w WH w 03EA40 HSEP HSEP CLAM CLAM SPLV SPLV BPLV SYNC BPP BPPS SCMI SCMI FQSE NFSE NFSE IH 1 PH P H MIN STH T NGH NG LH L LH L CLPC CLPC HVCO VCNT VCNT HDIS HDIS HLO HLO FIELD FIELD HSEP HSEP Sync separator 1 registers 03 50 NDIH ND1 ND H TW CKLV CKLV H 2H 2 H HSEP HSEP CLAM CLAM SPLV SPLV BPLV SYNC BPPS BPPS SCMI SCMI FQSE FOSE NFSE NFSE x 03E60 1WH IW PVH PW WH W W MINW TWH TW NGW NGW LWH LW LWH LW H CLPC CLPC HVCO VCNT VCNT HDIS HDIS HLO HLO
140. I C Bus Controller PC Interface Setup Examples 13 6 1 3 Setting up the Second Interrupt When the microcontroller receives the data x 85 from the slave device it returns an ACK 0 signal and the bus controller generates an interrupt At this point implement the following settings To set up the interrupt Set the I2CICR register x 03FF6 to x 02 This enables PC interrupts and clears the previous interrupt request setup the C registers 1 Read the I2CDREC register x 03E82 and the I2CDRECH register x 03E83 to determine the bus controller status 2 Sincethe communication will end when the microcontroller receives the next data byte set the IDCDTRMH register x 03E81 to x 01 This sets STA to 0 STP to 0 ACK to 1 and the transmission data to x 00 With this setting the microcontroller returns an ACK 1 signal on the ninth clock 13 6 1 4Setting up the Third Interrupt When the microcontroller receives the data x 033 from the slave device it returns an ACK 1 signal and the bus controller generates an interrupt At this point implement the following settings To set up the interrupt Set the I2CICR register x 03FF6 to x 02 This enables re interrupts and clears the previous interrupt request setup the C registers 1 Read the I2ZCDREC register x 03E82 and the I2CDRECH register x 03E83 to determine the bus controll
141. IV 1 interrupt Chapter 7 On Screen Display 7 4 In note 1 added example of maximum horizontal display characters during NTSC interlacing 7 5 Changed bit positions in OSDREGE register 7 6 Adjusted values for new 14 32 MHz maximum frequency 7 10 to 7 13 Added display examples Panasonic Semiconductor Development Company MN101C46F Revision History Panasonic Page in Japanese Description of Revision 7 14 Changed VRAM bit allocation CB code and bit width for blanks repeti tions 7 17 Changed CRAMEND to RAMEND 7 36 to 7 37 Added to and modified DMA and interrupt timing description 7 42 Changed OSDREGE bit positions in shutter movement diagram 7 54 Changed register name Chapter 8 Analog to Digital Converter 8 2 to 8 11 Adjusted values for new 14 32 MHz maximum frequency 8 15 Corrected unit symbol for capacitor values Chapter 10 Closed Caption Decoder 10 1 Changed settings for sampling frequency control registers 10 2 Changed settings for sampling frequency control registers 10 18 10 33 Adjusted values for new 14 32 MHz maximum frequency Appendices 15 10 Added VBIVOICR and VBIVIICR interrupts to register map Revision 1 20 to Revision 1 30 July 26 1999 Page in Japanese Description of Revision Chapter 3 Interrupts 3 2 Chan
142. IVI DIV0 DIV3 DIV2 DIVI DIVO Reset 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 1 RW R RW RW RW RW RW RW R R R RW RW RW RW In these registers set the sampling cycle for separating the HSYNC and VSYNC signals from the composite sync signal The recommended set tings are x IF and VFQDIV 5 0 Sampling frequency setting for VSYNC separator In this field set the ratio by which to divide the sampling frequency for the HSYNC separator FQDIV 3 0 Sampling frequency setting for HSYNC separator In this field set the ratio by which to divide the A D sampling frequency Panasonic Semiconductor Development Company MN101C46F LSI User Manual 191 Panasonic Closed Caption Decoder Closed Caption Decoder Registers SCMINGH Minimum Sync Level Detection Interval Set Register High x 03E45 SCMINGWH Minimum Sync Level Detection Interval Set Register High x 03E65 SCMING Minimum Sync Level Detection Interval Set Register x 03E44 SCMINGW Minimum Sync Level Detection Interval Set Register x 03E64 Bit 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 sc SC SC SC SC SC SC SC SC SC MING MING MING MING MING MING MING MING MING MING 9 8 7 6 2 4 3 2 1 0 Reset 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 RW R R R R R RW RW RW RW RW RW RW RW RW RW SCMING 9 0 Interval setting for the minimum sync level detection Set the HSYNC
143. Interrupt source TM3IRQ Timer operation Clock sources fosc 4 fosc 16 fosc 32 fosc 64 fogc 128 fg 2 fg 4 fs 8 fx fosc Machine clock oscillation for fast operation fx Machine clock oscillation for slow operation fs System clock See section 2 13 Setting the Clock Switch Register When timers are cascaded both the binary counter and the compare register function as 16 bit registers Set the TMnEN flags of the mode registers to 1 for both the high order 8 bit timer and the low order 8 bit timer Use the low order 8 bit timer to select the clock source All other settings and count timing are the same as when the 8 bit timers are used independently When timers 2 and 3 are cascaded use the interrupt request flag of timer 3 Tie the timer pulse output of timer 2 low Disable timer 2 interrupts even though no timer 2 interrupt requests will occur Panasonic Semiconductor Development Company MN101C46F LSI User Manual 103 Panasonic 8 Bit Timers Operation of the 8 Bit Timer Cascade Connection 6 3 1 Example of Cascade Connection Setup Cascading timers 2 and 3 In the following setup example a clock function is implemented by cascading timers 2 and 3 as a 16 bit timer and generating interrupts at set intervals The selected clock source is fs 4 fosc 20 MHz It generates an interrupt every 2500 divisions 1 ms The setup procedures are described below
144. LSF VBI Data Slice Level Register Software x 03E05 SLSFW VBI Data Slice Level Register Software x 03E25 SLHD VBI Data Slice Level Register Hardware x 03E04 SLHDW VBI Data Slice Level Register Hardware x 03E24 Bit 7 6 5 4 3 2 1 0 T 6 5 4 9 2 1 0 SLSF SLSF SLSF SLSF SLSF SLSF SLSF SLSF SLHD SLHD SLHD SLHD SLHD SLHD SLHD SLHD 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Reset RW RW RW RA RW RW RW RW R R R R R R R R SLSF 7 0 VBI data slice level software setting Valid range x 00 to x FF SLHD 7 0 VBI data slice level hardware calculation Valid range x 00 to x FF Composite signal from ADC Compare 0 1 data MUX SLSF L Figure 10 12 SLSF and SLHD Multiplexing MN101C46F LSI User Manual Panasonic Semiconductor Development Company 186 Panasonic Closed Caption Decoder Closed Caption Decoder Registers HNUM HSYNC Count Register x 03E06 HNUMW HSYNC Count Register x 03E26 Bit 7 6 3 4 3 2 1 0 tud HNUM4 HNUM3 HNUM 2 HNUMI HNUMO Reset 0 0 0 0 0 0 0 0 R W R R R R R R R R SBFLAG Start bit detection flag 0 No start bit detected 1 Start bit detected HNUM 4 0 HSYNC count during the VBI interval This field indicates the H line number from 0 to 25 VBIIRQ VBI Interrupt Timing Control Register x 03E07 VBIIRQW VBI Interrupt
145. LSI User Manual 215 Panasonic Bus Controller Block Diagram 13 2 Block Diagram SDA Digital filter D 14 0 Bus buffer Parallel to serial uM Dn lt converter 9 Transmission data register LSB Data bus controller Seri m erial to parallel gt convener MSBH Reception data register LSB E 7 Address comparator SCL Digital filter Address register gt Clock register Clock controller Control register 5 8 Status register MODE lsrs LAB BB n Y Y Bus busy logic Register control Arbitration logic sequence controller Clock prescaler q Figure 13 4 PC Bus Controller Block Diagram 13 3 Functional Description The bus controller contains the registers shown in table 13 3 See the page number indicated for register and bit descriptions Table 13 3 Control Registers for Clamping Circuit Register Page Address Description I2CDTRM 224 x 03E80 FC transmission data register I2CDTRMH 224 x 03ES81 transfer control register I2CDREC 224 x 03E82 rc reception data register I2CDRECH 224 x 03E83 PC mode register I2CMYAD 225 x 03E84 self address register I2CCLK 225 x 03E86 clock control register I2CBRST 226 x 03E8
146. LV SYNC BPPS BPPS SCMI SCMI FQSE FOSE NFSE NFSE x 03E60 1wH IW PWH PW WH w W MINW TW NGW NGW LWH LW LWH LW H Sync separator 2 registers CLPC CLPC HVCO VCNT VCNT HDIS HDIS HLO HLO FIELD FIELD HSEP HSEP x 03E70 NDIWINDIW NDW WH W TWW TWW CKL WH W 2WH 2W H H VWH VW DC Dc pc pc pc pc pc x 03E80 BSTS BRST CLK MYA DREC DREC DTRM DTRM C interface registers D H H TDCH TDCL TDCC PWMS PWM4 PWM3 PWM2 PWMI PWMO 03 90 p E PWM registers Panasonic Semiconductor Development Company MN101C46F LSI User Manual 235 Panasonic Register Map Table A 2 Register Map x 03E00 x 03EFF Continued RMLD RMTR RMSR RMCS RMTC RMIR RMIS x 03EA0 Remote signal receiver registers EVOD EVOD HCOU HCOU OSD3 OSD2 OSDI RAME GRO CRO x 03EBO H NTH NT ND ME MEN D D JAPH men uie SHTC HSHT HSHT HSHT HSHT VSHT VSHT VSHT VSHT xX 1H OH o IH 0 E WBSH BBSH FRAM COLB isters x OSEDO OSD control registers D D E 03EE0 porre poris ecria erri PLT12 erri PLT10 PLTO7 PLTO6 PLTOS PLTO4 PLTO3 erro2 PLT00 xO3EFo 71137 36 PLT35 PLT34 PLT33 PLT32 PLT31 PUT30 PLT27 PLT26 PUT25 PUT24 PUT23 PLT22 PLT21 20
147. M3 03 96 8 bit PWM data register 3 PWM4 03 98 R W 8 bit PWM data register 4 5 x 03E9A R W 8 bit PWM data register 5 14 3 1 14 Bit PWM Control Registers Data must be set in the following three types of registers for 14 bit PWM control TDCC 14 bit PWM Control Register x 03E9C Bit 4 6 5 4 3 2 1 0 Reserved TDCCI TDCCO Reset 0 0 0 0 0 0 0 0 R W R R R R R R W R W R W TDCC is a 2 bit register that controls 14 bit PWM operation Reserved Always set to 0 TDCC 1 0 Data latch transfer bits 00 Do not transfer 01 TDCLR TDCLL 10 TDCHR TDCHL 11 TDCHR TDCHL and TDCLR TDCLL TDCHR 14 bit PWM Data Register High x OSE9F Bit 7 6 5 4 3 2 1 0 TDCHR TDCHR TDCHR TDCHR TDCHR TDCHR TDCHR Reserved 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 R W w w w w w w w w TDCHRn 14 bit PWM high order data Indicates 14 bit PWM output waveform modulation data 6 0 MN101C46F LSI User Manual Panasonic Semiconductor Development Company 232 Panasonic Pulse Width Modulator PWM Registers TDCLR 14 bit PWM Data Register Low x 03E9E Bit T 6 4 3 2 1 0 Reserved TDCLR6 TDCLRS TDCLRA TDCLR3 TDCLR2 TDCLRI TDCLRO Reset 0 0 0 0 0 0 0 0 R W w w w w w w w w TDCLRn 14 bit PWM low order data Indicates overlapping position of pulse added to 14
148. MDn py 0 Port input 1 Port output gies 0 Port low output Pin 1 Port high output 4 P2INn lt 2 CVBS1 CVBS0 lt AAN Note n 5 P25 n 6 P26 Figure 4 14 P25 CVBS1 and P26 CVBSO Port 2 Panasonic Semiconductor Development Company MN101C46F LSI User Manual 79 Panasonic I O Ports 1 0 Port Circuit Diagrams 0 Pullup off 1 Pullup on o E 0 P30 1 NHSYNC zac P3MDO D 0 Port input 1 Port output e 0 Port low output Pin 1 Port high output P3OUTO t x P30 NHSYNC P3INO lt 1 NHSYNC A Schmidt trigger Figure 4 15 P30 NHSYNC Port 3 MN101C46F LSI User Manual Panasonic Semiconductor Development Company 80 Panasonic I O Ports I O Port Circuit Diagrams 0 Pullup off 1 Pullup on P3PUP1 0 P31 1 YS lt gt e 01 0 Port inpu 1 Port output rae P3DIRi D 0 Port low output 1 Port high output P3OUT1 Pin rx 1 P31 YS x c YSoUT gt P3IN1 Figure 4 16 P31 YS Port 3 Panasonic Semiconductor Development Company MN101C46F LSI User Manual 81 Panasonic I O Ports 1 0 Port Circuit Diagrams 0 Pullup off 1 Pullup on P3PUPn BH GH
149. Modulator PWM Registers PWNM 2 8 bit PWM Data Register 2 x 03E94 Bit F 6 5 4 3 2 1 0 PWM2 PWM2 PWM2 PWM2 PWM2 PWM2 PWM2 2 DT7 DT6 DT5 DT4 DT3 DT2 DTI DTO Reset 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W PWM3 8 bit PWM Data Register 3 x O3E96 Bit 7 6 5 4 3 2 1 0 PWM3 PWM3 PWM3 PWM3 PWM3 PWM3 PWM3 PWM3 DT7 DT6 DT5 DT4 DT3 DT2 DTI DTO Reset 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W 8 bit PWM Data Register 4 x 03E98 Bit 7 6 5 4 3 2 1 0 PWM4 PWM4 PWM4 PWM4 PWM4 PWM4 PWM4 DT7 DT6 DT5 DT4 DT3 DT2 DTI DTO Reset 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W PWMS5 8 bit PWM Data Register 5 x 03E9A Bit 7 6 5 4 3 2 1 0 PWM5 PWM5 PWM5 PWM5 PWM5 PWM5 PWM5 PWM5 DT7 DT6 DT5 DT4 DT3 DT2 DTI DTO Reset 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W MN101C46F LSI User Manual Panasonic Semiconductor Development Company 234 Panasonic Register Map Appendix A Register Map Table A 1 Register Map x 03D00 x 03DFF 12 4 LSBs Description MSBs F E D
150. NZ io8 bp label if mem8io bp 1 PC 7 d7 label H 3PC O 0 7 67 0011 0101 lt io8 gt d7 4 26 if mem8 io bpz0 PC 72PC 2 i08 bp label f mem8 io op 1 PC 8 d1 label sH3PC 0 0 0 e 8 67 0011 0101 16 lt o8 gt dii 2 126 if mem8 io bpz0 PC 82PC TBNZ abs16 bp label if mem8 abs16 bp 1 PC 9 d7 label H PC O e 0 e 9 7 8 0011 1111 abs 16 gt d7 H 12 if mem8 abs16 bp 0 PC 92 PC TBNZ abs16 bp label if mem8 abs16 bp 1 PC 10 d1 label H PC O 0 0 10 7 8 0011 1111 1bp abs 16 gt dii 2 127 if mem8 abs16 bp 0 PC 102PC JMP JMP An 02PC 17 16 An3PC 15 0 02PC H 0010 0001 00A0 128 JMP label absi8 label H2PC et See 0011 1001 OaaH abs 18b 15 0 gt 5 128 JSR JSR An SP 3 9SP PC 3 bp7 0 mem8 SP 3 7 0010 0001 00A1 129 PC 3 bp15 8mem8 SP 1 PC 3 H mem8 SP 2 bp7 0 mem8 SP 2 bp6 2 PC 3 bp17 16 smem8 SP 2 bp1 0 0 gt PC bp17 16 An PC bp15 0 02 PC H JSR label SP 32SP PC45 bp7 02mem8 SP 5 6 0001 OOOH lt d12 gt 3 129 PC 5 bp15 8 mem8 SP 1 PC 5 H mem8 SP 2 bp7 0 mem8 SP 2 bp6 2 PC 5 bp17 16 smem8 SP 2 bp1 0 PC 5 d12 label H gt PC JSR label SP 35SP PC 6 bp7 D2memB SP 6 7 0001 001H d16 _ Qus 4 130 PC 6 bp15 8 mem8 SP 1 PC 6 H mem8 SP 2 bp7 0 gt mem8 SP 2 bp6 2 PC 6 bp17 16 mem8 SP 2 bp1
151. OMEND 40 ROMEND 3F ROMEND 3C ROMEND 3B 72 bytes ROMEND 08 ROMEND 07 ROMEND 04 ROMEND 03 ROMEND Line 1 data Line 2 data Line 3 data Line 17 data Line 18 data ROMEND 3 ROMEND 2 ROMEND 1 ROMEND Graphics tile 4 color mode 1 dot 2 bits 4 colors Sheet 1 bits 7 to 0 Sheet 1 bits 15108 Sheet 2 bits 7 to 0 1 Sheet 2 bits 15108 1 by lt 16bits I 1 Line 1 Sheet 214 Line 2 Line 3 eet Line 18 4 Bit 15 Bit 0 Figure 7 9 Graphics ROM Organization in 4 Color Mode 16W x 18H Tiles Panasonic Semiconductor Development Company 125 Panasonic MN101C46F LSI User Manual On Screen Display Setting up the OSD 7 7 7 7 1 Setting up the OSD Setting OSD Display Colors This section describes how to set up the display colors for the OSD Setting up the color palette Table 7 7 Color Palettes Palette Name Address Applications PLTOO PLT37 03 0 Text foreground and background colors COLB x 03EDO Color background FRAME x 03ED2 Outlining and character shadowing colors BBSHD x 03ED4 Box shadowing color black WBSHD x 03ED6 Box shadowing color white Setting up the graphics display colors The following settings determine the graphics display colors GCOL x 03EB8 bit 1 sets the number of colors of the mode 4 or 8 CH 8 0 CC bits 8 to 0
152. OP D E F ADD 8 Dm MOVW 8 DWm MOVW 8 Am JSR d12 label JSR d16 label MOV 8 abs8 abs12 PUSH An OR 8 Dm AND 8 Dm When the exension code is b oo10 When the extension code is b 001 1 MOV abs12 Dm MOV abs8 Dm MOV An Dm MOV Dn abs12 MOV Dn abs8 MOV Dn Am MOV io8 Dm MOV d4 SP Dm MOV d8 An Dm MOV Dn io8 MOV Dn d4 SP MOV Dn d8 Am ADD 4 Dm SUB Dn Dn d7 BRA d7 BEQ d7 BNE d7 d7 BCS 47 BLT d7 BLE d7 BEQ d4 BNE d4 MOVW DWn HA MOVW BGE 011 BRA d11 BEQ d11 BNE 011 d11 BCS d11 BLT d11 BLEd11 MOV Dn Dm MOV 8 Dm BSET abs8 bp BCLR abs8 bp CMP 8 Dm MOVW abs8 Am MOVW abs8 DWm CBEQ 8 Dm d7 CMPW 16 DWm MOVW 16 DWm MOV Dn HA MOVW abs8 MOVW DWn abs8 CBNE 8 Dm d7 CMPW 16 Am MOVW 16 Am MOVW An DWm MOVW d4 SP Am MOVW d4 SP DWm POP Dn ADDW 4 Am BRA d4 MOVW Dwn Am Extension code b 0010 2ndnible 3rd nibble 0 1 0 MOVW An Am MOVW An d4 SP 4 5 CMPW An Am MOVW DWn 04 5 PUSH Dn 8 9 A B MOVW SP Am MOVW An SP ADDW 8SP ADDW 4 SP BTST 8 Dm JSRV ibl JMP 0 JSR A0 JMP A1 JSR A1 MOV PSW Dm REP BGT d7 BHI d7 BLS d7 BNC
153. P27 VREFHO 2 78 4 14 25 51 and P26 CVBSO 2 2 2 4 79 4 15 P30 NHSYNOC Port 3 45e eL usaha od atta en upas IUE Pep nones 80 4516 PSI YS Port 3 coesustie ine Bees eee EE Meio apas eee Oi EE E 81 4 7 P32 BOUT P33 GOUT P34 ROUT and P35 YM 3 82 4 18 P36 NRST Port 3 82 419 P37 NVSYXNC ARQS Port 3 u s sas repe et e et AREE 83 4 20 PAO PWM Port A ote be RE pu ee gear SERRA a ia deeb iue ed 84 5 1 Piescalar Block Diagram oeni ennnen r E aM Rusia nie usus SERA RS 94 6 1 Block Diagram of Timers 2 iayy ee 99 6 2 Block Diagram of Timer4 masasun ter Dee v er gus nen eee ees 99 6 3 Count Timing for Timer Operation Timers 2 3 and 4 100 7 1 OSD Block Diagram 110 7 2 Display Example without APh MESE n AREE PEE CEP 115 7 3 Display Example with suut E Re ERU PEE EUIS SEE 117 7 4 VRAM Orp nz tion eorr Pr ede PENA NER 121 7 5 ROM Organization e a al rU ARE Ree ere eget uy 122 7 6 Graphics ROM Setup Example fora Single 123 7 7 Graphic
154. P37 NVSYNC IRQ5 Port 3 Panasonic Semiconductor Development Company MN101C46F LSI User Manual 83 Panasonic I O Ports 1 0 Port Circuit Diagrams 0 Pullup off 1 Pullup on 9 P4PUP0 P 0 P40 1 PWM P4MD0 0 Port input 1 Port output 0 P4DIRO M U X PWM output gt 1 0 Port low output 1 Port high output 0 P4OUTO Pin X U X 1 Low output P4INo lt Figure 4 20 P40 PWM Port 4 MN101C46F LSI User Manual Panasonic Semiconductor Development Company 84 Panasonic I O Ports I O Port Control Registers 4 3 1 Port Control Registers POPLU P3PLU Ports 0 3 Pullup Resistor Control Registers x 03F40 x 03F43 Bit F 6 4 3 2 1 0 PnPLU7 PnPLU6 PnPLUS PnPLU4 PnPLU3 PnPLU2 PnPLU1 PnPLUO Reset 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W PAPLU Port 4 Pullup Resistor Control Register x 03F44 Bit 7 6 5 4 3 2 1 0 0 0 0 0 0 P4PLU2 PAPLUI PAPLUO Reset 0 0 0 0 0 0 0 0 R W R R R R R R W R W R W The PnPLU registers control the port pullup resistors The bit number cor responds to the associated pin number For instance POPLU applies to the P07 pin These are 8 bit access registers 0 Pullup resistor off 1 Pullup resistor on POOUT P3OUT Ports 0 3 Output Control Regist
155. P4MD2 PAMDI PAMDO Reset 0 0 0 0 0 0 0 0 R W R R R R R R W R W R W P4MD is an 8 bit access register PAMD2 P42 function switch 0 P42 1 SCLO P4MD1 P41 function switch 0 P41 1 SDAO PAMDO P40 output switch 0 40 1 PWM PCNTO Port Control Register 0 x 03F4A Bit 7 6 5 4 3 2 1 0 RC Dc OSD ADCI ADCO RMC VBIO SEL1 SELO POFF ON ON OFF OFF OFF Reset 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W PCNTO is an 8 bit access register I2CSEL1 SDA1 SCL1 enable 0 Disable 1 Enable I2CSELO SDAO SCLO enable 0 Disable 1 Enable OSDPOFF OSD enable 0 Disable 1 Enable ADC1ON ADC enable for closed caption decoder 1 0 Disable 1 Enable ADCOON ADC enable for closed caption decoder 0 0 Disable 1 Enable RMCOFF IR remote signal receiver enable 0 Enable 1 Disable Panasonic Semiconductor Development Company MN101C46F LSI User Manual 91 Panasonic I O Ports I O Port Control Registers VBI1OFF Closed caption decoder 1 enable 0 Enable 1 Disable VBIOOFF Closed caption decoder 0 enable 0 Enable 1 Disable 2 Port Control Register 2 x 03F4E Bit 7 6 5 4 3 2 1 0 Dc PWM OSD OFF OFF REGE SCLKF1 SCLKF0 Reset 0 0 0 0 0 0 0 0 R W R R R R W R W R W R W R W I2COFF 2 function enable 0 Enable 1 Disable PWMOFF PWM function enable 0 Enable 1 Disable OS
156. PIKL Kukje Center Bldg 11th Fl 191 Hangangro 2ga Youngsan ku Seoul 140 702 KOREA Tel 82 2 795 9600 Fax 82 2 795 1542 280901 Printed in JAPAN
157. POP POP Dn mem8 SP Dn SP 1 SP 213 1110 10Dn 59 memi6 SP JOAnSP422SP 2 4 0000 011A 59 EXT Dn DWm sign Dn gt DWm 313 1001 000d Arithmetic manupulation instructions ADD ADD Dn Dm Dm Dn Dm eeee 2 0011 0011 DnDm 61 ADD imm4 Dm Dm sign imm4 Dm eeee 2 1000 00Dm lt 4 gt 6 61 ADD imm8 Dm Dm imm8 Dm eeee 1 2 0000 100 lt 8 gt 62 ADDC ADDC Dn Dm Dm Dn CF Dm e eee 3 2 0011 1011 DnDm 63 ADDW ADDW DWn DWm DWm DWn DWm e eee 3 O 0010 0101 1 64 ADDW DWn Am Am DWn Am ee ee 3 3 0010 0101 10Da 64 ADDW imm4 Am Am sign imm4 gt Am ee ee 3 2 1110 110a lt 4 gt 6 65 ADDW imm8 Am Am sign imm8 Am 3 0010 1110 110a lt 8 gt 77 65 ADDW imm16 Am 16 gt 4 0010 0101 011a H6 gt 66 ADDW imm4 SP SP sign imm4 SP 3 2 1111 1101 lt 4 gt 6 66 ADDW imm8 SP SP sign imm8 gt SP 41 2 1111 1100 48 gt 7 67 ADDW imm16 SP SP imm16 SP 7 4 0010 1111 1100 lt 16 gt 67 ADDW imm16 DWm DWm imm16 DWm 1 0010 0101 0104 lt 16 gt 68 ADDUW ADDUW Dn Am Am zero Dn 2Am ee ee 3 3 O 0010 1000 1aDn 8 69 ADDSW ADDSW gt 3 0 0010 1001 1aDn 70 SUB SUB Dn Dm when Dm Dn Dm e eee 3 2 0010 1010 71 SUB Dn Dn Dn Dn2Dn 121 1000 01Dn 71 SUB imm8 Dm Dm imm8 Dm 3 0010 1010DmDm
158. Pana NSeries TheOnetoWatch for Constant Innovation Making theFuture ComeAlive MICROCOMPUTER MN101C MN101C46F F46F LSI User s Manual Pub No 21446 0211E Panasonic PanaXSeries is a trademark of Matsushita Electric Inustrial Co Ltd The other corporation names logotype and product names written in this book are trademarks or registered trademarks of theri corresponding corporations Request for your special attention and precautions in using the technical informaition and semiconductors described in this book 1 An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this book and controlled under the Foreign Exchange and Foreign Trade Law is to be exported or taken out of Japan 2 The contents of this book are subject to change without notice in matters of improved function When finalizing your design therefore ask for the most up to date version in advance in order to check for any changes 3 We are not liable for any damage arising out of the use of the contents of this book or for any infringement of patents or any other rights owned by a third party 4 No part of this book may be reprinted or reproduced by any means without written permission from our company 5 This book deals with standard specification Ask for the latest individual Product Standards or Specifications in advance for more detai
159. R W Timer 2 interrupt control register Timer 3 TM3BC x 03F51 R Timer 3 binary counter TM30C x 03F53 R W Timer 3 compare register TM3MD x 03F55 R W Timer 3 mode register CK3MD x 03F57 Timer 3 prescalar select register PSCMD x 03F6F R W Prescalar control register TM3ICR x 03FEA R W Timer 3 interrupt control register Timer 4 TM4BC 03 58 R Timer 4 binary counter TM4OC x 03F5A R W Timer 4 compare register TM4MD x 03FSC R W Timer 4 mode register CK4MD x 03F5E R W Timer 4 prescalar select register PSCMD x 03F6F R W Prescalar control register TM4ICR x 03FEB R W Timer 4 interrupt control register MN101C46F LSI User Manual Panasonic Semiconductor Development Company 106 Panasonic 6 4 2 Programmable Timer Registers Timers 0 through 4 all have 8 bit programmable timer registers The pro 8 Bit Timers 8 Bit Timer Control Registers grammable timer registers are composed of compare registers and binary counters The compare registers are 8 bit registers that hold values to be compared to the binary counter The binary counters are 8 bit up counters Binary counters are cleared to 00 when compare registers are written to during counting TM2OC Timer 2 Compare Register
160. SDPOFF and OSDREGE Settings OSDPOFF OSDREGE OSD Register R W Power Dissipation 0 Don t care Off Disabled Less 1 0 Disabled 1 1 On Enabled Greater Panasonic Semiconductor Development Company MN101C46F LSI User Manual 111 Panasonic On Screen Display OSD Operation See section 7 9 Selecting OSD Dot Clock on page 136 for more information on setting the operating clock frequency Do not include graphic tiles in italic display lines in the closed caption load Graphic tiles will be shifted by a pixel 7 3 OSD Operation This section describes the basic operation of the OSD block Also see the descriptions of register assignments and VRAM assignments for details Figure 7 1 shows a block diagram of the OSD circuit 7 3 1 Operating Clock The source clocks for OSD operation are the external oscillator pins OSC1 and OSC2 The frequency range is 12 to 14 32 MHz 7 3 2 External Input Synchronization Signal Input a horizontal synchronization signal HSYNC and a vertical synchronization signal VSYNC Use software to select whether there are any pull up resistors and to select polarity For VS YNC assign an IRQ so the microcontroller can detect the start of the field Note that REDGS selects the interrupt edge and VPOL selects the OSD input 7 3 3 Display Control System The OSD is able to display text fonts and graphic tiles in the same line 7 3 3 1 Tex
161. SI User Manual Panasonic Semiconductor Development Company 182 Panasonic Closed Caption Decoder Closed Caption Decoder Registers 10 4 Closed Caption Decoder Registers Table 10 9 Closed Caption Decoder Registers CCD0 CCD1 Register Address Address R W Description FC x 03E00 x 03E20 VBI decoding format select register SLCNT x 03E01 x 03E21 R W Slice level calculation control register MAX x 03E03 x 03E23 R CRI interval maximum register MIN x 03E02 x 03E22 R CRI interval minimum register SLSF x 03E05 x 03E25 R W VBI data slice level register software SLHD x 03E04 x 03E24 R W VBI data slice level register hardware HNUM x 03E06 x 03E26 R HSYNC count register VBIIRQ x 03E07 03 27 R W interrupt timing control register ACQIH x 03E09 x 03E29 R W ACQ capture timing control register 1 high ACQI x 03E08 x 03E28 R W ACQ capture timing control register 1 CAPDATAH x 03E0B x 03E2B R Caption data capture register high CAPDATA x 03E0A x 03E2A R Caption data capture register CRDFQW x 03E0D x 03E2D R CRI frequency width register A high CRIIFQW x 03E0C x OS3E2C R CRI frequency width register low CRI4FQW x 03E0F x OS3E2F R CRI frequency width register B high x OSEOE
162. TU Leos Gene Ee eei pp E Spi 35 2 12 Standby Funcion 34 029 heb Oh EISE UE IUe ri epu CEPR e E db us 36 2 12 1 OVEGIVIEW xen Sean am NOSE RUE T pes u XII 36 2 122 CPU Mode Control Register 38 2 123 Moving between SLOW and NORMAL 39 2 12 4 Invoking the Standby 40 2 13 Setting the Clock Switch 2 42 2 14 a SLE ERE ID I RUE EE RUE T T NUR eas 43 2 14 1 Reset Operation ov olent UPS s b Lb pe RE das 43 2 14 1 1 Invokmng the Reset Mode i ur EE FE gD BUTE usapu 43 2 14 1 2 Operation Sequence During Resets 43 2 14 2 Oscillation Stabilization 44 2 14 2 1 Controlling the Oscillation Stabilization 45 3 oe ne ee elu es ee edd 46 3 1 Descriptions 3224 0 ee et SER EI SE a A le ES 46 3 2 Functions i debe dh HB aes cle eee det ated eb iss 47 3 3 Block Diagram x oco Sas REUNIR RC nct RENE URP RR ERR UR ss IS 48 3 4 Cub ET 49
163. TXx7 bit 6 controls the YS pin output Translucency PLTx0 PLTXx7 bit 7 controls the YM pin output See figure 7 10 Palette PLTnm n 0 3 m 0 7 Bit 7 6 5 4 3 2 1 0 PLTnm PLTnm PLTnm PLTnm PLTnm PLTnm PLTnm PLTnm YM YS BH GH RH B G R Hi Z V 0 Push pull 1 HiZ Hi Z x 0 Push pull 1 Hi Z Hi Z control 0 Push pull 1 Hi Z YM YS BOUT GOUT ROUT Figure 7 10 OSD Signal Output Control MN101C46F LSI User Manual Panasonic Semiconductor Development Company 128 Panasonic On Screen Display Setting up the OSD 7 7 2 Text Layer Functions This section describes the character enhancement functions available in the text layer Outlining In both normal and closed caption modes writing a 1 to bit 9 FRAME of the VRAM s COL field causes outlines to appear around all characters following that COL You can specify the color of the outline in the color palette s FRAME x OSED2 Figure 7 11 shows an example of character outlining As shown in the figure if a character contains dots in the left or right borders of its field the outlining for those dots appear in the adjacent character field 16 dots 16 dots 16 dots gt Figur
164. Table 1 4 Absolute Maximum Ratings Vss 0 V No Parameter Symbol Rating Unit A1 Power supply voltage 0 3 to 4 6 2 Input pin voltage normal pins Vi 0 3 to Vpp 0 3 5 V pins Vis 0 3 to 6 0 A3 Output pin voltage normal pins Vo 0 3 to Vpp 0 3 N ch open drain pins when Vpp 1 4 V Vosi 0 3 to 46 0 N ch open drain pins when Vpp 1 4 V Vosa 0 3 to 4 6 4 Power dissipation Pp 1000 mW A5 Operating ambient temperature Topr 20 to 70 Storage temperature MN101C46F T 55 to 125 MN101CF46F 55 to 95 Note 1 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device These are stress ratings only and functional operation of the device under these or any conditions other than those indi cated in the operational sections of this specification is not implied Precautions 1 All of the and pins are external Connect them directly to the power source and ground 2 Thoroughly test your crystal oscillator in this device s oscillator cell before using 3 If you install the product close to high field emissions under a cathode ray tube for example shield the package surface to ensure normal performance 4 improve noise and latch up tolerance connect bypass capacitors between Vpp and pins with a thick line by the shortest possible distance Use electrolytic capacitors of at least 22 uF 6 3 V tolerance 5 ensure normal performance
165. Table 11 3 Leader Detection Conditions Format Edge Interval HEAMA data leader n 4 lt interval lt n 4 Tg 0 5 6 bit data leader 28 6 lt interval lt 36Ts Note 1 n the leader value set in LD 3 0 of register 11 3 5 2Trailer Detection An interrupt occurs when the 6 bit counter overflows 11 3 5 36 Bit Data Reception Detection An interrupt occurs when the microcontroller loads 8 bit received data to the reception data transfer register RMTR 11 3 5 4 Edge Detection An interrupt occurs when the remote signal input pin RMIN is asserted The POLSEL bit of RMIR sets the polarity of RMIN RMIN input positive edge triggered POLSEL 0 RMIN input negative edge triggered POLSEL 1 Edge detection output l fsvscLK 1 5 5 Note l fsyscLk 1 3 58 MHz 0 28 Us Figure 11 6 Pin Edge Detection The detection output for all four interrupt vectors is an active high pulse asserted at intervals of 1 fsyscrk Bits 3 to 0 of the RMIR register control the interrupt vectors individually A 0 disables the interrupt vector and a enables it A remote signal interrupt sets the RMCIR flag of the RMCICL interrupt register x 00FC76 MN101C46F LSI User Manual Panasonic Semiconductor Development Company 204 Panasonic IR Remote Signal Receiver IR Remote Signal Receiver Control Registers The edge detection circu
166. VBIVIICR x 03FF8 VSYNC VBIV1 inter rupt 25 x 04064 Reserved 26 x 04068 A D conversion interrupt ADIRQ ADICR x 03FFA 27 x 0406C Remote control interrupt RMIRQ RMICR x 03FFB 28 x 04070 Reserved 29 04074 Reserved 30 x 04078 Reserved MN101C46F LSI User Manual Panasonic Semiconductor Development Company 50 Panasonic Interrupts Operation 3 4 3 Interrupt Levels and Priorities The MN101C46F assigns vector numbers and interrupt control registers for each interrupt except reset interrupts It sets interrupt levels by interrupt groups except for the reset and nonmaskable interrupts using programming There are three levels of interrupt priority when multiple interrupts have the same priority level the one with the lowest vector number has the highest priority When a vector 3 interrupt set at level 1 occurs at the same time as a vector 4 interrupt set at level 2 the vector 3 interrupt is accepted Vector 1 nonmaskable interrupt Priority Interrupt vector No 1 Vector 1 3 Level 0 Vectors 2 5 and 6 2 Vector 2 p 3 Vector 5 8 Level 1 Vector 3 4 Vector 6 5 Vector 3 s Level 2 Vectors 4 and 8 6 Vector 4 7 Vector 8 Figure 3 3 Example of Interrupt Levels 3 4 4 How Interrupts Are Accepted After an interrupt source occurs it goes through the following sequence until it is accepted 1 The interru
167. You must also select the C function in the port mode registers For bus connection 0 set bits 0 and 1 of the PAMD register x 03F2C For bus connection 1 set bits 1 and 2 of the POMD register x 03F28 Table 13 4 shows the register settings required to use either SDAO SCLO or SDAT SCL I alone figure 13 5 shows the control circuit for this pin setup Table 13 4 Registers Settings for SDAO SCLO or SDA1 SCL1 Ports Register Bit SDAO SCLO Only SDA1 SCL1 Only POMD x 03F28 1 0 selects P01 1 selects SDA1 2 0 selects P02 1 selects SCL1 P4MD x 03F2C 0 1 selects SDAO 0 selects P60 1 1 selects SCLO 0 selects P61 PCNTO x 03F4A 8 1 enables SDAO SCLO 0 disables SDAO SCLO 9 0 disables SDA1 SCL1 1 enables SDA1 SCL1 Port control register 0 x 03F4A bits 7 6 l2CSELO 1 on d y j SDA 0 I2CSEL1 SDA IN uu spat SDA OUT q be Port control register 0 X O3F4A bits 7 6 12C I2CSEL0 Circuit 5 SCL0 I2CSEL1 san C Figure 13 5 Pin Control Circuit for the IZC Bus Controller MN101C46F LSI User Manual Panasonic Semiconductor Development Company 218 Panasonic I C Bus Controller SDA and SCL Waveform Characteristics 13 5 SDA and SCL Waveform Characteristics Figure 13 6 and table 13 5 provide the timing definitions and specificat
168. a memory mode in which the system is constructed entirely of internal memory It is an optimized memory model that allows you to build the highest performance system architecture In single chip mode both ROM and RAM are internal memory The MN101C46F has 3 Kbytes of RAM space and 96 Kbytes of ROM space x 00000 256b abs8 addressing ytes access area Internal 3 Kbytes RAM x 00100 Data space x 00C00 x 03D00 768 bytes Special register area Y x i 128 byles x 04000 Interrupt vector table 04080 Subroutine SAEVIS vector table A 040 Instruction code Internal 48 Kbytes table data ROM 96 Kbytes space Y x 10000 Instruction code 48 Kbytes OSD fonts Y y x1BFFF Y Note MMOD L Figure 2 3 Single Chip Mode Panasonic Semiconductor Development Company MN101C46F LSI User Manual 31 Panasonic Basic CPU Functions Memory Space 2 10 3 Special Function Registers The MN101C46F assigns x 03D00 x 03FFF in memory space as a special function register area I O space Its special registers are placed as follows Table 2 7 Register Map x 03D00 x 03EFF 16 4 LSBs MSBs F E 1 918171615141312 11110 Description x 03D00 x 03DI10 x 03D20 x 03D30 x 03D40 x 03D50 x 03D60 SLCN SLCN x 03D70 VB
169. a signal is 1 and below which it is 0 from the maximum and minimum clock run in CRI pulses occurring in the interval between the settings in the CRILSH CRIIS and CRIIEH CRIIE registers CRI HSYNC CRHSH CRITS lt CRI1EH CRI1E gt l lt gt Data i max min 2 of this interval slice level computed in the hardware Figure 10 9 Data Slice Level Calculation Table 10 7 provides the registers used to control and monitor the data slicer Table 10 7 Control Registers for Data Slicer CCDO CCD1 Register Page Address Address Description CRIISH 189 x OSEII x 03E31 CRI capture start timing control register 1 high CRIIS 189 x O3EIO x 03E30 CRI capture start timing control register 1 CRIIEH 189 x O3EI3 x 03E33 CRI capture stop timing control register 1 high 189 x OBEI x 03E32 CRI capture stop timing control register 1 MAX 186 x 03E03 x 03E23 CRI interval maximum register MIN 186 x 03E02 x 03E22 CRI interval minimum register SLSF 186 x O3E05 x 03E25 VBI data slice level register software set ting SLHD 186 x O3E04 x 03E24 VBI data slice level register hardware calculated SLCNT 185 03 01 0 21 Slice level calculation control register 10 3 5 Controller and Sampling Circuit The control circuit contains the CRI window gen
170. abs16 4imm8 PC 112PC CBEQ imm8 abs16 label _ if mem8 abs16 imm8 PC 12sd11 label s HPC e e 12 7 8 0011 1101 1101 abs 16 gt 8 gt dii 3 118 if mem8 abs16 4imm8 PC 12 PC CBNE CBNEimm8 Dmjabel __ if Om imm8 PC 6 d7 label HPCl 6 e e 5 3 4 1101 10Dm 48 gt lt 07 H 2 119 if Dm imm8 PC 62PC CBNE imm8 Dm label if Dm4imm8 PC 8 dtt label H2PC e e e 8 45 0010 1101 100 48 gt dil 3 114 8 8 CBNE imm8 abs8 label iflmem8 abs8 imm8 9 17 0 e 9 6 7 0010 1101 1110 abs 8 8 gt lt d7 2 124 if mem8 abs8 imm8 PC 92PC CBNE imm8 abs8 abel iflmem8 abs8 imm8 PC tG dif abeHHPC e 6 e 10 6 7 0010 1101 1111 abs 8 48 gt dii 3 124 if mem8 abs8 imm8 PC 10 PC CBNE imm8 abs16 label if mem8 abs16 4imm8 PC 11sd7 label sH9PC e 11 7 8 0011 1101 1110 abs 16 gt 8 gt lt d7 2 121 if mem8 abs16 imm8 PC 112PC CBNE imme abs16 label ifimem8 abs16 imm8 2 211 e e 12 7 8 0011 1101 1111 abs 16 gt 48 gt dii 121 if mem8 abs16 imm8 PC 122PC TBZ TBZ abs8 bp label if mem8 abs8 op 0 PC 7 d7 label H4PC 0 0 7 67 0011 0000 abs 8 d7 2 124 if mem8 abs8 bp 1 PC 7 PC TBZ abs8 bp label if mem8 abs8 bp 0 PC 8 d1 1 label H PC 0 0 8 6 7
171. al Panasonic Semiconductor Development Company 134 Panasonic On Screen Display DMA and Interrupt Timing To prevent error program data to meet the restrictions for the number of characters used outlined in section 7 1 Description on page 109 If an unexpected VSYNC or too many HSYNCS come in during a DMA transfer the DMA transfer address may move to a different line and the microcontroller may shut down If this occurs add a dummy line to the VRAM area and set HP and VP 7 8 DMA and Interrupt Timing This section describes how the MN101C46F handles the timing of direct memory access DMA transfers of OSD data and OSD interrupts Direct Memory Access The microcontroller reads the line 1 data from the RAM as it scans line 1 onto the display For line 2 and following lines it reads the data as it scans the display start for the preceding line The RAM read starts 13 system clock cycles 13Ts after the leading edge of the HSYNC pulse The DMA transfer takes 4Ts for each display data word Ifa DMA transfer occurs at the same time as the leading edge of a VS YNC pulse the screen flickers To avoid this do not set a display position in the last line Interrupts The microcontroller processes the INT interrupt request bit of the display data s VP field during the DMA transfer If INT is set to 1 when the associated VP transfer ends the OSD generates an interrupt request Note that if the interrupt
172. al Panasonic India Ltd NPI E Block 510 International Trade Tower Nehru Place New Delhi_110019 INDIA Tel 91 11 629 2870 91 11 629 2877 Indonesia Sales Office P T MET amp Gobel M amp G JL Dewi Sartika Cawang 2 Jakarta 13630 INDONESIA Tel 62 21 801 5666 Fax 62 21 801 5675 e Taiwan Sales Office Panasonic Industrial Sales Taiwan Co Ltd PIST Head Office 6F 550 Sec 4 Chung Hsiao E RD Taipei 110 TAIWAN Tel 886 2 2757 1900 886 2 2757 1906 Kaohsiung Office 6th Floor Hsin Kong Bldg No 251 Chi Hsien 1st Road Kaohsiung 800 TAIWAN Tel 886 7 346 3815 886 7 236 8362 Sales Office Panasonic Industrial Shanghai Co Ltd PI SH Floor 6 Zhong Bao Mansion 166 East Road Lujian Zui PU Dong New District Shanghai 200120 CHINA Tel 86 21 5866 6114 86 21 5866 8000 Panasonic Industrial Tianjin Co Ltd PI TJ Room No 1001 Tianjin International Building 75 Nanjin Road Tianjin 300050 CHINA Tel 86 22 2313 9771 Fax 86 22 2313 9770 Panasonic SH Industrial Sales Shenzhen Co Ltd PSI SZ 74 107 International Bussiness amp Exhibition Centre Futian Free Trade Zone Shenzhen 518048 CHINA Tel 86 755 359 8500 86 755 359 8516 Panasonic Shun Hing Industrial Sales Hong Kong Co Ltd PSI HK 11th Floor Great Eagle Center 23 Harbour Road Wanchai HONG KONG Tel 852 2529 7322 Fax 852 2865 3697 Korea Sales Office Panasonic Industrial Korea Co Ltd
173. ample Graphics VRAM Settings graphics output Line No RAM Addr RAM Data Data Type Description 1 2802 CG 1 PLT 1 CH x 002 OBFC 1801 CC CG 0 PLT 3 CH x 001 OBFA C004 HP HSZ x 0 SHT 0 HP x 04 OBF8 C040 VP LAST 0 VSZ x 0 INT 0 VP x 40 2 OBAE 0810 CC CG 0 PLT 1 010 OBAC 2813 CC CG 1 PLT 1 CH x 013 OBAA 4003 CB BF 1 CB x 3 1014 CC CG 0 PLT 2 CH x 014 OBA6 4002 CB BF 1 CB x 2 OBA4 3016 CC CG 1 PLT 2 CH x 016 OBA2 D810 HP HSZ x 3 SHT 0 10 OBAO C858 VP LAST 0 VSZ x 1 INT 0 VP x 58 3 0 5 2981 CC CG 1 PLT 1 CH x 181 0 5 3182 CC CG 1 PLT 2 182 0B5A C044 HP HSZ x 0 SHT 0 HP x 44 0B58 E020 VP LAST 1 VSZ x 0 0 VP x 20 Notes 1 Always specify HP and VP in that order at the end of each line 2 SetINT to 1 in the VP setting to generate an OSD interrupt 3 Set LAST to 1 in the VP setting for the last line in the display Also set the VP value to a smaller value than the position of the current line In the example in table 7 4 VP x 20 is smaller than VP x 58 MN101C46F LSI User Manual Panasonic Semiconductor Development Company 114 Panasonic On Screen Display Display Setup Examples A A E VP HP x 22 HSZ
174. an ACK 0 signal so the microcontroller must send the next data byte Set up the transmission data as follows To set up the interrupt Set the I2CICR register x 03FF6 to x 02 This enables PC interrupts and clears the previous interrupt request setup the C registers 1 Read the I2CDREC register 03 827 and the I2CDRECH register x 03E83 to determine the bus controller status The previous read from I2CDREC cleared the AAS so AAS should be 0 2 Set the DDCDTRM register x 03E80 to and the 2CDTRMH regis ter x 03E81 to x 01 This sets STA to 0 STP to 0 ACK to 1 and the transmission data to x AA The microcontroller does not need to issue an ACK signal in this transfer so the ACK bit should be 1 3 Begin transmitting data in sync with the clock from the master 13 6 2 4Setting up the Third Interrupt The master send an ACK 1 signal then issues a stop condition ending the communication Data slave address ACK 01 0 T Jol I h Note circled areas are signals output from the MN101C46F Figure 13 8 Waveform for Slave Receiver Transitioning to Slave Transmitter Panasonic Semiconductor Development Company MN101C46F LSI User Manual 223 Panasonic I C Bus Controller Bus Interface Registers 13
175. ance PLT27RH ROUT pin high impedance control 0 Push pull control 1 High impedance PLT27B Blue digital output push pull PLT27G Green digital output push pull PLT27R Red digital output push pull Panasonic Semiconductor Development Company MN101C46F LSI User Manual 157 Panasonic On Screen Display OSD Registers PLT30 37 Palette 3Colors 0 7 Register X OSEF8 x OSGEFF Bit 7 6 2 4 3 2 1 0 PLT30 PLT30 PLT30 PLT30 PLT30 PLT30 PLT30 PLT30 YM YS BH GH RH B G R Reset 0 0 0 0 0 0 0 0 R W RW RW RW RW RW RW RW Color 0 of palette 3 PLT30YM YM output PLT30YS YS output PLT30BH BOUT pin high impedance control 0 Push pull control 1 High impedance PLT30GH GOUT pin high impedance control 0 Push pull control 1 High impedance PLT30RH ROUT pin high impedance control 0 Push pull control 1 High impedance PLT30B Blue digital output push pull PLT30G Green digital output push pull PLT30R Red digital output push pull Bit 7 6 5 4 3 2 1 0 PLT37 PLT37 PLT37 PLT37 PLT37 PLT37 PLT37 PLT37 YM YS BH GH RH B G R Reset 0 0 0 0 0 0 0 0 R W RW RW RW RW RW RW RW Color 7 of palette 3 PLT37YM YM output PLT37YS YS output PLT37BH BOUT pin high impedance control 0 Push pull control 1 High impedance PLT37GH GOUT pin high impedance control 0 Push pull control 1 High impedance PLT37RH ROUT pi
176. ardware automatically controls the instruction queue so you do not need to pay any particular attention to it when writing a program When you are calculating instruction execution time however be aware of how the instruction queue operates The instruction decoder will generate control signals in each instruction execution cycle according to microprogram control The instruction decoder decodes the contents of the instruction queue in the cycle before the control signal is required Panasonic Semiconductor Development Company MN101C46F LSI User Manual 25 Panasonic Basic CPU Functions Address Registers 2 7 Address Registers The address registers consist of the program counter PC the address registers AT and the stack pointer SP 2 7 1 Program Counter PC This register indicates the address of the instruction being executed Instructions are separated by half bytes 4 bits so the program counter requires 19 bits to express the 256 Kbyte instruction space The LSB of the program counter indicates the half byte The program counter resets to the value stored in the vector table at address x 04000 18 0 Program counter PC 2 7 2 Address Registers A0 AI These registers are used as address pointers They can be used for operation instructions that calculate addresses addition subtraction or compare The address registers contain pointers 2 bytes of data so transfers to memory are normally in
177. art timing control register DATAEH 190 x OSEIB x 03E3B Data capture stop timing control register high DATAE 190 x O3EIA Data capture stop timing control register CAPDATAH 188 x O3EOB x 03E2B Caption data capture register high CAPDATA 188 x 03E0A x 03E2A Caption data capture register HNUM 187 x O3E06 x 03E26 HSYNC count register VBIIRQ 187 x O3E07 03 27 interrupt timing control register 10 3 5 I CRI Detection for Sampling Clock Generation The decoder captures the caption data on the rising edge of the CRI pulse To achieve this it contains a circuit to accurately detect the CRI pulse rises and to generate a data sampling clock CRI Data 21 HSYNC X X X T CRI2SH CRI2S CRI2EH CRI2E gt l CRI detec ion VVWTTHhis interval determines the sampling clock timing Figure 10 10 Sampling Clock Timing Determination 10 3 5 2Data Capture Control The DATASH DATAS and DATAEH DATAE registers control the data capture timing and the CAPDATAH CAPDATA registers store the caption data captured on the sampling clock generated through CRI detection CRI 21 HSYNC 4 4 4 4 DATASH DATAS CRI2SH CRI28 Data 50 Sampling clock DATAEH DATAE gt l Figure 10 11 Caption Data Capture Timing MN101C46F L
178. asis total 16 types Display functions Shutter effect Outlining Blinking Shadowing foreground and background In closed caption mode Italics Underlining Repeated tile or blank 6 Notes 1 Maximum 61 characters per line with the default colors Each color assignment including outlining and blinking decreases this total by one The maximum is about 44 characters in NTSC interlacing when HSYNC 63 5 us 2 8 color mode 108 bytes per tile 7 KB 64 tile types 4 color mode 72 bytes per tile 4 5 KB 64 tile types Multiple modes cannot be used simultaneously the color mode applies to the entire display 3 R G and B can each be set in three levels giving a total of 27 available display colors 3 X 3 X 3 Selects any eight of these color combinations for one color palette Intermediate grades for R G and B will cause Hi Z output Implement intermediate voltages using external resistors 4 The OSD dot clock frequency controls the horizontal position and size For details see section 7 7 4 Setting Up the OSD Display Position on page 134 and section 7 9 Selecting the OSD Dot Clock on page 136 5 This function can be used for a wallpapering effect or to insert spaces for continuous blanking One tile code can be repeated up to 16 times Repeating tiles allows you to use more than 62 tiles per line Panasonic Semiconductor Development Company 109 Panasonic MN101C46F
179. ave address of the microcontroller 2 Set the 2 register x 03E81 to x 00 This sets STA STP ACK and the transmission data to Os With this setting the microcontroller returns an ACK 0 signal when an address match occurs The master sends data the slave address to the slave microcontroller in sync with the master clock When the R W bit 1 the microcontroller changes from a slave receiver to a slave transmitter 13 6 2 2Setting up the First Interrupt Once the microcontroller becomes a slave transmitter set up the transmission data To set up the interrupt Set the I2CICR register x 03FF6 to x 02 This enables PC interrupts and clears the previous interrupt request To set up the registers 1 Read the I2ZCDREC register x 03E82 and the I2CDRECH register x 03E83 to determine the 2 bus controller status AAS should be 1 2 Set the I2CDTRM register x 03E80 to x 55 and the DCDTRMH register x 03E81 to x OI This sets STA to 0 STP to 0 ACK to 1 and the trans mission data to x 55 The microcontroller does not need to issue an ACK signal in this transfer so the ACK bit should be 1 3 Begin transmitting data in sync with the clock from the master MN101C46F LSI User Manual Panasonic Semiconductor Development Company 222 Panasonic I C Bus Controller PC Interface Setup Examples 13 6 2 3Setting up the Second Interrupt The master sends
180. bit PWM output waveform 6 0 TDCHL 14 bit PWM Data Latch High x OSE9F Bit 7 6 5 4 3 2 1 0 Reserved TPCHL TDCHL TDCHL TDCHL TDCHL TDCHL TDCHL reer 6 5 4 3 2 1 0 Reset x x x x X x x x RW R R R R R R R R TDCHLn 14 bit PWM high order data latch Latches TDCHR register data n 6 0 TDCLL PWM Data Latch Low x OSE9E Bit ef 6 4 3 2 1 0 Reserved TDCLL6 TDCLL5 TDCLLA TDCLL3 TDCLL2 TDCLL TDCLLO Reset X X X X X X X X R W R R R R R R R R TDCLLn 14 bit PWM low order data latch Latches TDCLR register data 6 0 14 3 2 8 Bit PWM Control Registers PWMO PWMS5 are 8 bit registers They are used for writing 8 bit PWM output waveform modulation data within one repeat cycle They are set to 0 upon reset and 8 bit PWM output is set to H PWM0 8 bit PWM Data Register 0 x 03E90 Bit 5 4 3 2 1 0 PWMO PWMO PWMO PWMO PWMO PWMO DT7 DT6 DT5 DT4 DT3 DT2 DTI DTO Reset 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W PWM1 8 bit PWM Data Register 1 x 03E92 Bit 7 6 5 4 3 2 1 0 PWMI PWMI PWMI PWMI PWMI PWMI PWMI PWMI DT7 DT6 DT5 DT4 DT3 DT2 DTI DTO Reset 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Panasonic Semiconductor Development Company MN101C46F LSI User Manual 233 Panasonic Pulse Width
181. bit is set to 1 in the line display data the interrupt occurs at the first scan line If the interrupt bit is set to 1 in the line 2 display data the interrupt occurs at the first display line IVP write timing The IVP register determines the vertical positions of the L1 line shown in figure 7 17 Mistimed writes to this register can cause the OSD display to flicker If for instance the write to IVP occurs above line L1 the display jumps immediately to the new L1 setting If it occurs below line L1 however the new display position line L1 does not display until the next screen or field To prevent flickering Panasonic Semiconductor Development Company MN101C46F LSI User Manual 135 Panasonic On Screen Display Selecting the OSD Dot Clock always write to the IVP register at a point after L1 has displayed 13Ts 4nTs i i Display screen Y Line 1 Display code DMA i OSD interrupt Line L1 Display code DMA Text Graphics Text Line L2 OSD interrupt display display display Graphics Text display display 4 HSYNC pulse Figure 7 17 DMA and Interrupt Timing for the OSD 7 9 Selecting the OSD Dot Clock This section describes how to set up the OSD dot clock The source for the OSD dot clock is programmable to either the
182. ble 1 7 Chapter 2 Basic CPU Functions P31 Corrected special register area from 256bytes to 768bytes P32 Deleted HVCONDH and HVCONDWH sync separater to registor map P41 Added notes of invoking the Standby mode Chapter 4 I O Ports P89 Added notes of closed caption decoder contral bit setup for P2MD Chapter 8 Analog Digital Converter P167 Corrected addres of ADICR register from x 03FFB to x 03FFA Chapter 10 Closed Caption Decoder P181 P182 and P183 P175 Revised figure 10 2 10 3 and 10 4 P175 Added description of register setup rule to text P176 Revised figure 10 5 P176 Added description of CCD1 to table 10 3 P177 P179 Added CCD1 Address to table 10 5 10 6 10 7 10 8 and 10 9 P185 to P197 Added names and address of CCD1 P185 Added description of SLCNT register setup to text P191 Corrected description of FQSEL register P196 Added commend value of HDISTW register Appendix A Register Map P235 Deleted HVCONDH and HVCONDWH sync separater MNIOICA46F Revision History Panasonic Semiconductor Development Company Panasonic Page Description of Revision Appendix C Instruction Set P240 to P245 Revised Instruction Set to Latest version Appendix D Instruction Map P246 to P247 Revised Instruct
183. ble 9 2 Lower Limit at which Watchdog Can Be Cleared Lower Limit Value at which WDTC2 WDTC1 WDTCO Watchdog Can Be Cleared 0 None 0 1 21 system clocks 0 0 22 system clocks 1 1 21 system clocks 0 213 system clocks 0 1 215 system clocks 1 0 217 system clocks 1 1 219 system clocks 9 2 1 6 Relationship between Watchdog Timer and CPU Mode The watchdog timer has the following relationship to the CPU mode 1l In NORMAL IDLE and SLOW modes the watchdog timer counts the sys tem clock 2 The watchdog timer count continues regardless of switching between the NORMAL IDLE and SLOW modes 3 HALT mode stops the watchdog timer Panasonic Semiconductor Development Company MN101C46F LSI User Manual 171 Panasonic Watchdog Timer Operation of the Watchdog Timer Place the command that sets the WDEN flag to 1 at the end of the initialization If the WDCTR regis ter is changed after operation begins a watchdog interrupt will be generated by the setting for lower limit of clearability 4 In STOP mode the watchdog timer clears automatically 5 No watchdog interrupts are generated in STOP mode 6 Aftera reset is cleared and after returning from STOP mode the count con tinues only for the oscillation stabilization wait In systems that use STOP mode the program will usually branch depending on whether STOP is invoked or not When this happens the count value of t
184. c signal input OSD YS YM 2 Video signal control ROUT GOUT O 3 RGB screen output BOUT SDA0 SDA1 IO 2 PC data PC interfaces 2 SCLO SCL1 T O 2 PC clock IR remote signal receiver RMIN I 1 Remote signal input PWM 8 bit 6 channel PWM0 PWM5 6 8 bit pulse width modulator output PWM 14 bit 1 channel PWM 1 14 bit pulse width modulator output 00 07 8 General purpose port 0 I O P10 P17 I O 8 General purpose port 1 I O I O ports 20 27 I O 8 General purpose port 2 I O P30 P37 I O 8 General purpose port 3 I O 40 42 3 General purpose port 4 I O CVBSO CBVS1 I 2 Composite video signal input CLH I 1 Clamp level high input Closed caption decoders 2 CLL I 1 Clamp level low input VREFHS I 1 CCD reference voltage input VREFLS I 1 CCD reference voltage input ADC 5 bit 8 channel ADIN0 ADIN7 I 8 Analog signal input Flash FLASH I 1 Dedicated flash mode input Connect to Vss Test MMOD I 1 Test pin Connect to Vpp MN101C46F LSI User Manual Panasonic Semiconductor Development Company 6 Panasonic General Description Electrical Characteristics 1 5 Electrical Characteristics Type CMOS integrated circuit Function 16 bit microcontroller with graphic display circuit Application Television Connection See Figure 1 9 Correct Connection Technique for the Vpp and Vss Pins on page 14 Packaging See Figure 1 1 MN101C46F Pin Configuration on page 4
185. cal PC bus application Data line SDA Clock line SCL Figure 13 1 Example of I C Bus Application In an C bus system devices are considered masters or slaves when performing data transfers A master is a device that initiates a data transfer on the bus and gen erates the clock signals to permit that transfer At that time all devices addressed are considered slaves Table 13 1 defines some 1 bus terminology Table 13 1 2 Bus Terminology Term Description Transmitter A device that sends data to a bus Receiver A device that receives data from a bus Master A device that initiates a transfer generates clock signals and terminates a transfer Slave A device addressed by a master Multimaster More than one device capable of controlling the bus can be connected to the bus and more than one master can attempt to control the bus at the same time without corrupting the message The system is not dependent on any single master Arbitration A procedure to ensure that if more than one master simultaneously tries to control the bus only one is allowed to do so and the message is not corrupted The device that loses arbitration becomes the slave of the device that wins Synchronization A procedure to synchronize the clock signals of two or more devices Panasonic Semiconductor Development Company MN101C46F LSI User Manual 213 Panasonic Bus Controller Description Figur
186. can be cleared by writing in the WDCTR The timer is cleared regardless of the value written We recommend that you use the bit set BSET instruction which does not change the value MN101C46F LSI User Manual Panasonic Semiconductor Development Company 170 Panasonic Watchdog Timer Operation of the Watchdog Timer 9 2 1 4 Time Out Period The time out period is determined by the system clock fs and bits 2 and 1 WDTS 1 0 of the WDCTR If the watchdog timer cannot be cleared before this value is reached it is considered a software fault and the watchdog interrupt WDIRQ is generated as nonmaskable interrupt NMI Table 9 1 Time Out Periods WDTS1 WDTSO Time Out Period 0 0 216 system clocks 0 1 218 system clocks 1 X 220 system clocks Note The system clock is determined by the CPU mode control register CPUM See section 2 13 Setting the Clock Switch Register on page 42 The time out period is generally determined by the run time of the program s main routine Set a time out period that is longer than the main routine s run time divided by a given natural number 1 2 Insert watchdog timer clear commands in the main routine such that their number makes it an equivalent period 9 2 1 5 Lower Limit at which Watchdog Can Be Cleared The lower limit value at which the watchdog timer can be cleared is determined by bits 5 4 and 3 WDTC2 WDTC1 and WDTCO of the WDCTR register Ta
187. color palette This function is unavailable in the closed caption mode BSHADJ 1 0 COL bits 12 to 11 in the RAM data enable character box shadowing when BSHADI is 1 This function is unavailable in the closed caption mode 00 and 01 No box shadowing 10 Upper left white and lower right black shadows 11 Upper left black and lower right white shadows PLTOx x O3EEO x 03EE7 PLT1x x O3EES x O3EEF PLT2x x OSEFO x 03EF7 or PLT3x x 03EFO x O3EFF specify the palette color for the font data stored in ROM BBSHD x 03ED4 specifies the black color for box shadowing WBSHD x 03ED6 specifies the white color for box shadowing B Setting up the text display colors closed caption display The following settings determine the text display colors in closed caption mode CAPM x 03EBA bit 0 sets closed caption display mode when 1 CH 8 0 CC bits 8 to 0 in the RAM data set the code of the font to be displayed PLT I1 CC bit 12 in the RAM data selects the color palette 0 selects the 16 colors of PLTOO PLT17 while 1 selects the 16 colors of PLT20 37 CGSEL CC bit 13 in the RAM data selects text font display when 0 CCOL 3 0 COL bits 3 to 0 in the RAM data set the color of the charac ter 16 colors This value is in reference to the selected color palette PLTOO PLT17 or PLT20 PLT37 BCOL 3 0 COL bits 7 to 4 in the RAM data set the back
188. conditions for iden tifying the data format When the microcontroller detects a data trailer the hardware automatically shuts off the supply to sampling clock Ts which the 6 bit counter counts The counter resets and the clock supply restarts at the next edge detection 0 2 4 6 8 10 12 16 20 24 28 32 36 40 64Ts Pe el 4 o tg Leader EN Leader 24 Ts wx i When RMLD 3 0 6 x Data Data 0 2 4 Ts format T ir lt detection Data 1 8 Ts I Short long Short detection Long o 8 Leader i Leader 32 Ts E i Data Data 0 8 Ts Q format T T detection Data 1 16 Ts H Shortlong Short detection Long 0 4 8 12 16 20 24 28 32 36 40 Figure 11 5 Conditions for Detecting Data Formats Panasonic Semiconductor Development Company MN101C46F LSI User Manual 203 Panasonic IR Remote Signal Receiver IR Remote Signal Receiver Operation 11 3 5 Generating Interrupts The IR remote signal receiver has four interrupt vectors leader detection trailer detection 8 bit data reception detection and pin edge detection This section describes the operation for each of them 11 3 5 I Leader Detection An interrupt occurs when the circuit detects a data leader It detects leaders by testing the interval between remote signal edges Table 11 3 shows the con ditions
189. ction 2 12 Standby Function 2 12 1 Overview The MN101C46F has two sets of oscillation pins for the system clock high and low oscillation It has two CPU operating modes NORMAL and SLOW and two standby modes HALT and STOP You can decrease power consumption by making effective use of these modes CPU operating mode Standby mode Interrupt E NORMAL mode E STOPO 4 E CPU input clock Off 3 NORMAL Program 5 E System clock Off i CPU input clock fosc d UN System clock fosc 2 Interrupt Qf s D HALT 0 CPU input clock fosc Program 3 Program 4 E System clock Off STOP mode Idle CPU input clock switch fxi gt fosc i Program 1 HALT mode Program 2 Interrupt E 4 STOP1 1 Y E CPU input clock Off J bE System clock Off 3 2 5 input clock fxI Reset System clock fx 2 Interrupt E NC E E HALT 1 E CPU input clock fx SLOW mode E Program 4 System clock Off 1 Notes 1 CPU off 2 Add oscillator stabilization wait 3 fosc High speed operating clock external oscillation 2 4 Low speed operating cl
190. ction 2 13 Setting the Clock Switch Register on page 42 for more infor mation on the system clock fs Panasonic Semiconductor Development Company 163 Panasonic MN101C46F LSI User Manual Analog Digital Converter Analog to Digital Conversion Operation 6 3 1 3 Setting up the A D Conversion Sampling Time Setup the A D conversion sampling time with the ANSH 1 0 field of the ANCTRO register Set the sampling time to an appropriate value for the analog input impedance since it is changed by external circuits Table 8 4 A D Conversion Sampling Time and Conversion Time A D Conversion Time Sampling Time ANSH1 ANSHO ts tap 1 12 us tap 8 96 us 0 0 tap x2 13 4 us 107 5 us 1 tap X6 17 9 us 143 3 us 1 0 tap X 18 31 3 us 250 8 us 1 Reserved 6 3 1 4 Controlling the Internal Ladder Resistors Set the ANLADE flag in the ANCTRO register to 1 to send current to the ladder resistor and put the ADC in standby When the ADC is stopped set ANLADE to 0 to reduce power consumption Table 8 5 Controlling the A D Ladder Resistors ANLADE A D Ladder Resistor Control 0 ladder resistors OFF A D conversion stopped 1 A D ladder resistors ON A D conversion on standby 6 3 1 5 Setting the Start of A D Conversion Set the ANST flag of ANCTR2 to 1 to start A D conversion The ANST flag stays at 1 throughout A D conversion and is cleared to 0 whe
191. ctions To enable IC interrupts Set the C interrupt control register 2 x 03FF6 to x 02 To set up the registers 1 Set the I2CCLK register x 03E86 to selecting a clock frequency of 10 kHz 2 Set the I2CDTRM register x 03E80 to x FD and I2CDTRMH x 03E81 to x 05 This sets STA to 1 STP to 0 and ACK to 1 Bits 7 to 1 of the trans mission data setting x FD indicate the address b 11111107 of the slave device from which the microcontroller will request the data and bit 0 indi cates the read write setting bit 0 1 read 13 6 1 2Setting up the First Interrupt When an ACK 0 signal returns from the slave device the IC bus controller generates an interrupt At this point implement the following settings To set up the interrupt Set the I2CICR register x 03FF6 to x 02 This enables PC interrupts and clears the previous interrupt request To set the registers 1 Read the IZ2CDREC register x 03E82 and the I2CDRECH register x 03E83 to determine the bus controller status 2 Sincethe microcontroller will become a receiver on the next operation set the I2CDTRMH register x O3E81 to x 00 This sets STA STP ACK and the transmission data to Os With this setting the microcontroller returns an ACK 0 signal on the ninth clock MN101C46F LSI User Manual Panasonic Semiconductor Development Company 220 Panasonic
192. d in HSYNC separator sam pling clock units The valid range is 000 to x 7FF HSEP2H HSYNC Separator Control Register 2 High x 03E51 HSEP2WH HSYNC Separator Control Register 2 High x 03E71 HSEP2 HSYNC Separator Control Register 2 x 03E50 HSEP2W HSYNC Separator Control Register 2 x 03E70 Bit 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 H H H H H H H H H H CLOSE CLOSE CLOSE CLOSE CLOSE CLOSE CLOSE CLOSE CLOSE CLOSE 9 8 E7 E6 5 4 2 1 Reset 0 0 0 0 0 0 0 0 1 1 1 0 0 1 0 0 R W R R R R R R R W R W RW RW RW RW RW RW RW HCLOSEE 9 0 Start position for HSYNC detection Set the position in HSYNC separator sampling clock units The valid range is x 000 to x 3FF FIELDH Field Detection Control Register High x 03E53 FIELDWH Field Detection Control Register High x 03E73 FIELD Field Detection Control Register 03 52 FIELDW Field Detection Control Register x 03E72 Bit 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 ODD V EVEN PHASE PHASE PHASE PHASE PHASE PHASE PHASE PHASE PHASE PHASE 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 RW R R RW RW RW RW RW RW RW RW RW RW ODDEVEN Field detection signal 0 Odd field 1 Even field VPHASE 9 0 Phase difference setting for VSYNC and HSYNC Set the pha
193. d7 5 d7 BVC d7 BVS d7 NOT Dn ROR Dn BGT d11 BHI d11 BLS d11 BNC d11 BNS d11 BVC d11 BVS 011 ASR Dn LSR Dn SUBW DWn DWm SUBW 16 DWm SUBW 16 SUBW DWn Am MOVW DWn Am ADDW DWn DWm ADDW 16 DWm ADDW 16 Am ADDW DWn Am CMPW DWn Am MOV d16 SP Dm MOV d8 SP Dm MOV d16 An Dm MOV Dn d16 SP MOV Dn d8 SP MOV Dn d16 Am MOVW DWn DWm NOPL n m CMPW DWn DWm ADDUW Dn Am EXT Dn DWm 8 PSW 0R 8PSW MOV Dn PSW ADDSW Dn Am SUB Dn Dm SUB 8 Dm SUBC Dn Dm MOV abs16 Dm MOVW abs16 Am MOVW abs16 DWm 8 Dm d12 MOVW An DWm MOV Dn abs16 MOVW An abs16 MOVW DWn abs16 CBNE 8 Dm d12 CBEQ 8 abs8 d7 d11 CBNE 8 abs8 d7 d1 1 MOVW d16 SP Am MOVW d16 SP DWm MOVW d8 SP Am MOVW d8 SP DWm MOVW An Am ADDW 8 Am DIVU MOVW An d16 SP MOVW DWn d16 SP MOVW An d8 SP MOVW DWn d amp SP MOVW An Am MULU MN101C46F LSI User Manual 246 Panasonic Semiconductor Development Company Panasonic MNIOIC Series Instruction Map Extension code b 0011 2nd nibble 3rd nibble 0 1 2 3 4 5 6 7 8 9 A B D E F TBZ abs8 bp d7 TBZ abs8 bp d11 1 TBNZ abs8 bp d7 TBNZ abs8 bp d11 2 CMP Dn Dm 3 ADD Dn Dm 4 2 io8 bp d7 TBZ io8 bp d11
194. dance control 0 Push pull control 1 High impedance PLTO7RH ROUT pin high impedance control 0 Push pull control 1 High impedance PLTO7B Blue digital output push pull PLT07G Green digital output push pull PLTO7R Red digital output push pull Panasonic Semiconductor Development Company MN101C46F LSI User Manual 155 Panasonic On Screen Display OSD Registers PLT10 17 Palette 1 Colors 0 7 Register X OSEE8 x OSEEF Bit 7 6 3 4 3 2 1 0 PLT10 PLT10 PLT10 PLT10 PLT10 PLT10 PLTIO PLTIO YM YS BH GH RH B G R Reset 0 0 0 0 0 0 0 0 R W RW RW RW RW RW RW RW Color 0 of palette 1 PLT10YM YM output PLT10YS YS output PLT10BH BOUT pin high impedance control 0 Push pull control 1 High impedance PLT10GH GOUT pin high impedance control 0 Push pull control 1 High impedance PLT10RH ROUT pin high impedance control 0 Push pull control 1 High impedance PLT10B Blue digital output push pull PLT10G Green digital output push pull PLT10R Red digital output push pull Bit 7 6 5 4 3 2 1 0 PLT17 PLT17 PLT17 PLT17 PLT17 PLT17 PLT17 PLT17 YM YS BH GH RH B G R Reset 0 0 0 0 0 0 0 0 R W RW RW RW RW RW RW RW Color 7 of palette 1 PLT17YM YM output PLT17YS YS output PLT17BH BOUT pin high impedance control 0 Push pull control 1 High impedance PLT17GH GOUT pin high impedance control
195. data in the following order at the end of a line APCNT 0 Horizontal position HP vertical position VP APCNT 1 Horizontal position HP vertical position VP address pointer AP Insert the color control code COL before the character code CC A character code CC must immediately precede a repeat character blank code CB and a color control code COL or character code CC must fol low it To indicate the last line of a display make the VP value for the last line smaller than that in the currently displayed line In addition write a 1 to the VP s last line flag LAST Lines cannot overlap If the horizontal sync signal is asserted while the microcontroller is access ing HP and VP no more lines will be displayed Panasonic Semiconductor Development Company MN101C46F LSI User Manual 113 Panasonic On Screen Display Display Setup Examples 7 4 Display Setup Examples Z 4 1 Setting Up the Display without AP This section shows how to set up the display data in the VRAM without AP Register settings RAMEND x 003EB4 x BF end address IHPH x 003ECB x O8 IHP x 22 IHSZ IHP x 003ECA x 22 IHP x 22 IHSZ IVPH x 003ECD x 18 IVP x 03 IVSZ x3 IVP x 003ECC x 03 IVP x 03 IVSZ x 3 OSD2 x 003EB8 x 00 APCNT 0 8 color graphics mode no Table 7 4 Ex
196. e Internal ROM Internal RAM Internal peripheral functions CSIC expansion bus c bo Z Figure 2 1 Block Structure and Functions Panasonic Semiconductor Development Company MN101C46F LSI User Manual 21 Panasonic Basic CPU Functions Block Functions 2 3 2 Block Description Table 2 2 Block Description Block Description Clock Generator An oscillation circuit connected to a quartz or ceramic oscillator supplies the clock to all blocks within the CPU Program counter The program counter generates addresses for queued instructions Nor mally it increments based on the sequencer indications but for branch instructions it is set to the branch head address For interrupt servicing it is set to the result of the ALU operation Instruction queue This block contains up to two bytes of prefetched instructions Instruction decoder The instruction decoder decodes the contents of the instruction queue generates in the proper sequence the control signals necessary for exe cuting the instruction and controls every chip block involved in instruc tion execution Instruction execu tion controller This block controls the operation of all blocks within the CPU using the results from the instruction decoder and interrupt requests ALU Arithmetic and logic unit This block calculates operand addresses for data arithmetic operations logic ope
197. e the right hand border of the shadow box appears in the character field to the right of the shadowed text 16 dots 16 dots gt 18 dots Box shadowing black Box shadowing white Specify the color in BBSHD Specify the color in WBSHD Figure 7 13 Box Shadowing Example MN101C46F LSI User Manual Panasonic Semiconductor Development Company 130 Panasonic On Screen Display Setting up the OSD Italicizing In closed caption mode writing a 1 to bit 10 ITALIC of the VRAM s COL field italicizes all characters following that COL Figure 7 14 shows an example of an italicized character Underlining In closed caption mode writing a 1 to bit 11 CUNDL of the VRAM s COL field underlines all characters following that COL Figure 7 14 shows an example of an underlined character 4 g 8 Italics HE o o N Y EE Caption mode Figure 7 14 Italicizing and Underlining Example B Blinking In both normal and closed caption modes writing a 1 to bit 8
198. e 13 2 shows an example of an PC bus configuration using two microcon trollers Both C bus lines SDA and SCL are bidirectional and connected to a positive supply voltage via a pullup resistor The open drain output pins of the microcontrollers perform the wired AND function on the bus Software controls whether a microcontroller operates as a transmitter or receiver and whether it is in master or slave mode VDD Pullup resistors Data line SDA Clock line SCL 1 Clock output Data output Data output Data input Device 1 Device 2 Clock input Figure 13 2 Connection of Two Microcontrollers to the IC Bus Table 13 2 describes the four operating modes for devices on the PC bus Table 13 2 Operating Modes for Devices on an 2 Bus Operating Mode Description Master transmitter The device that generates the serial transfer clock SCL signal and trans mits serial data to a slave device in sync with SCL Master receiver The device that generates the SCL signal and receives serial data from a slave device in sync with SCL Slave transmitter A device that transmits data in sync with the SCL signal from the master Slave receiver A device that receives data in sync with the SCL signal from the master MN101C46F LSI User Manual Panasonic Semiconductor Development Company 214 Panasonic I C Bus Controller Description Figure 13 3 shows the MN101C46F
199. e 7 11 Character Outlining Example Character shadowing In normal mode writing a 1 to bit 10 CSHAD of the VRAM s COL field causes shadows to appear behind all characters following that COL You can specify the color of the shadow in the color palette s FRAME register x 03ED2 Figure 7 12 shows an example of character shadowing As shown in the figure if a character contains dots in the right border of its field the shadowing for those dots appear in the character field to the right ra 16 dots a 16 dots 16 dots gt Figure 7 12 Character Shadowing Example Panasonic Semiconductor Development Company MN101C46F LSI User Manual 129 Panasonic On Screen Display Setting up the OSD Box shadowing In normal mode writing a 1 to bit 12 BSHAD1 of the VRAM s COL field causes boxes to appear around all characters following that COL If COL bit 11 BSHADO is 0 the color specified in the WBSHD register x 03ED6 appears on the top and left sides of the box and the color specified in the BBSHD register x 03ED4 appears on the bottom and right sides of the box These positions are reversed if BSHADO is 1 Figure 7 13 shows an example of box shadowing As shown in the figur
200. e cycles from the time the stop condition occurs to the time the next start condition occurs gt _80 machine cycles at 14 32MHz Stop Condition Start Condition Figure 1 7 Start and Stop Conditions Table 1 8 Timing for Slave Reception SCL SDA Slave Transmission SCL and Master Reception SDA No Parameter Symbol Conditions Min Max Unit SCL clock frequency fscL fosc 12 to 14 32 MHz 100 kHz Bus free time tBUF 77 us Hold time to start condition tHD STA 4 7 Clock low pulse width tow 4 7 Clock high pulse width tHIGH 4 Setup time for start condition tsU STA 4 7 Data hold time tHD DAT 0 Data setup time tSU DAT 250 ns SDA and SCL rise time t 1 us SDA and SCL fall time tr 300 ns Setup time for stop condition tSU STP 4 7 us Noise sampling time tNOISE 1 MN101C46F LSI User Manual Panasonic Semiconductor Development Company 12 Panasonic General Description Electrical Characteristics 1 5 22 HSYNC and VSYNC Input Conditions Use the flyback H and V for onscreen displays and to identify onscreen fields Adhere to the input conditions described below in your design to ensure accurate displays Figure 1 8 HSYNC and VSYNC Input Conditions Table 1 9 HSYNC and VSYNC Input Conditions Symbol Description Min Typ Max Unit t Gap between VSYNC leading edge and 0 4 Tysync 0 4 us leading edge of
201. egister Figure 10 13 Backporch Position Setting MN101C46F LSI User Manual Panasonic Semiconductor Development Company 192 Panasonic Closed Caption Decoder Closed Caption Decoder Registers SYNCMIN Minimum Sync Level Register x 03E48 SYNCMINW Minimum Sync Level Register x 03E68 Bit 7 6 5 4 3 2 1 0 SYNC SYNC SYNC SYNC SYNC SYNC SYNC MIN6 MINS MIN4 MIN3 MIN2 MINI MINO Reset 0 0 0 0 0 0 0 0 R W R R R R R R R R SYNOMIN 6 0 Minimum sync level This field stores the minimum level the sync tip level detected during the interval set in the SCMING register For sync tip clamping you should control clamping so as to make this value 16 dec BPLV Pedestal Level Register 03 49 BPLVW Pedestal Level Register x 03E69 Bit 7 6 5 4 3 2 1 0 BPLV6 BPLV5 BPLV4 BPLV3 BPLV2 BPLVI BPLVO Reset 0 0 0 0 0 0 0 0 R W R R R R R R R R BPLV 6 0 Pedestal level This register stores the pedestal level captured from the position specified in BPPSTH and BPPST SPLVH 5 Separator Level Set Register High x 03E4B SPLVWH Sync Separator Level Set Register High x 03E6B _ Sync Separator Level Set Register x 03E4A SPLVW Sync Separator Level Set Register x 03E6A Bit 7 6 5 4 3 2 1 0 7 6 S 4 3 2 1 0 BSP5
202. elephones home automation devices pagers air conditioners palmtop computers remote controllers fax machines and electronic musical instruments The MN101C46F has a flexible and optimized hardware architecture and a simple efficient instruction set It has 96 Kbytes of ROM and 3 Kbytes of RAM on chip It provides six external interrupts ten internal interrupts including the NMI three timer counters an analog to digital converter a watchdog timer an on screen display function a closed caption decoder an interface pulse width modulators and an IR remote signal receiver This structure makes it optimum for controlling a television tuner The machine cycle minimum instruction execution time in standard mode is 279 33 ns when the raw oscillation fosc is 14 32 MHz The ICs use 42 SDIP packages 1 2 Series Products This manual describes the following MN101C46F derivatives These two chips have the same functions Table 1 1 MN101C46F Derivatives Product ROM size RAM size Chip type MN101C46F 96 Kbytes 3 Kbytes Mask ROM MN101CF46F 96 Kbytes 3 Kbytes Flash ROM Panasonic Semiconductor Development Company MN101C46F LSI User Manual 1 Panasonic General Description OHardware Functions 1 3 OHardware Functions Table 1 2 Description of Hardware Function Description CPU core MN101C Core Load store architecture three stage pipeline Half byte instruction set hand
203. eparator extracts HSYNC and VSYNC from the composite video signal Figure 10 6 shows a block diagram of the circuit and table 10 6 provides the registers used to control and monitor it See the page number indicated for register and bit descriptions Panasonic Semiconductor Development Company MN101C46F LSI User Manual 177 Panasonic Closed Caption Decoder Functional Description weibeig 101e1edeg ou S 9 01 4 TASSEAD 0 8 A1MOO1H pubis asind Ionuoo 13808 10 ou g Jejo1uoo 7 0 81 6444 o 01 o3u84SH dHOOd3SH Sdd8 o 6133s0 19H Jeng JO 99 9D Jojejedes ONASH I A Iels p q 0 08 L1NO loislasa o 9 NINONAS ASdWNOO ae Joyersedas ou s 2 10 99 p N3A3ado E Jojoejep p 3 dn ouAs _ lo elaiao 10 91 0 LIMSAN Jojeredes ou S Io risa Jojejeue asind peo d ou s T3Sd3SA 2 d3SA dAVSd3SA o vivqav Jojejedes ONASA 10 91 013 1 Panasonic Semiconductor Development Company MN101C46F LSI User Manual 178 Panasonic Closed Caption Decoder Functional Description Table 10 6 Control Registers for Sync Separator Circuit CCD0 CCD1 Register Page Address Address Description Register for set
204. er status 2 Since the transfer has ended set the IZCDTRMH register x 03E81 to x 03 This sets STA to 0 STP to 1 ACK to 1 and the transmission data to 00 With this setting the microcontroller issues a stop condition and frees the bus slave address R W ACK i 1 0 0 1 0 1 0 1 1 0 0 1 Li Ri ai Note circled areas are signals output from the MN101C46F Figure 13 7 Waveform for Master Transmitter Transitioning to Master Receiver Panasonic Semiconductor Development Company MN101C46F LSI User Manual 221 Panasonic I C Bus Controller PC Interface Setup Examples 13 6 2 Setting up a Transition from Slave Receiver to Slave Transmitter This example demonstrates how to set up a data transfer when changing from slave receiver to slave transmitter Figure 13 8 shows an example waveform 13 6 2 1 Pre configuring To set up the I O port Set port control register 0 PCNTO x 03F4A to x 80 enabling the SDA1 and pins and set the port 0 output mode register POMD x FFFC to x 06 selecting the SDA1 and SCL 1 functions To enable IC interrupts Set the I2CICR register x 03FF6 to x 02 To set up the registers 1 Set the I2CMYAD register 03 847 to x 24 This sets the sl
205. erator and the caption data window generator The sampling circuit extracts the 16 bit caption data 503 kHz from the serial data output from the data slicer at the 14 32 MHz ADC sampling rate Table 10 8 provides the registers used to control and monitor these two blocks Panasonic Semiconductor Development Company 181 Panasonic MN101C46F LSI User Manual Closed Caption Decoder Functional Description Table 10 8 Control Registers for Controller and Sampling Circuit Register Page CCD0 Address CCD1 Address Description Registers for Detecting CRI and Generating Sampling Clock CRDSH 189 x OSEIS x 03E35 CRI capture start timing control register 2 high CRI2S 189 x 03E14 x 03E34 CRI capture start timing control register 2 CRDEH 189 x03E17 03 37 capture stop timing control register 2 high CRDE 189 0 16 x 03E36 CRI capture stop timing control register 2 CRDFQW 188 x O3EO0D x 03E2D CRI frequency width register A high CRIIFQW 188 x 03EOC x OS3E2C CRI frequency width register low CRI4FQW 188 x O3EOF x OS3E2F CRI frequency width register B high CRBFQW 188 x O3EOE x OS3E2E CRI frequency width register B low Registers for Controlling Data Capture DATASH 190 x O3EI9 x 03E39 Data capture start timing control register high DATAS 190 x 03E18 x O3E38 Data capture st
206. errupt Functions MN101C46F LSI User Manual Panasonic Semiconductor Development Company 48 Panasonic Interrupts Operation 3 4 Operation 3 4 1 Interrupt Handling Sequence The operation of normal interrupts other than the reset follows a sequence con sisting of an interrupt request acceptance of the interrupt and hardware pro cessing The hardware processing of interrupts consists of saving the program counter PC processor status word PSW and handy addressing information HA to the stack and jumping to the address specified by the vector After the interrupt service routine quits the register values saved when the interrupt was accepted are restored using an RTI instruction and operation returns to the program that was running when that interrupt was accepted Interrupt service routine Main program Reset interrupt source at beginning Hardware processing PC PSW save etc Interrupt occurs 12 machine cycles max 11 machine cycles Restart PSW PC return etc RTI instruction Figure 3 2 Interrupt Handling Sequence Maskable Interrupts Panasonic Semiconductor Development Company MN101C46F LSI User Manual 49 Panasonic Interrupts Operation 3 4 2 Interrupt Vector Addresses and Interrupt Groups The table below shows the relation
207. ers X O3F10 x O3F13 Bit F 6 4 3 2 1 0 PnOUT7 PnOUT6 PnOUTS PnOUT4 PnOUT3 PnOUT 2 PnOUT 1 PnOUTO Reset 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W L P4OUT Port 4 Output Control Register x 03F14 Bit 7 6 5 4 3 2 1 0 Writing a 1 to P3DIR6 and a 0 to P3OUT6 causes a reset 0 0 0 0 0 P4OUT2 P4OUTI P4OUTO Reset 0 0 0 0 0 0 0 0 R W R R R R R R W R W The PnOUT registers contain the port output data The bit number corre sponds to the associated pin number For instance POOUTT applies to the P07 pin These are 8 bit access registers Panasonic Semiconductor Development Company MN101C46F LSI User Manual 85 Panasonic I O Ports I O Port Control Registers POIN P3IN Ports 0 3 Input Registers x 0O3F20 x O3F23 Bit 7 6 5 4 3 2 1 0 PnIN7 PnIN6 PnIN5 PnIN4 PnIN3 PnIN2 PnINI PnINO Reset Pin Pin Pin Pin Pin Pin Pin Pin R W R R R R R R R R PAIN Port 4 Input Register x O3F24 Bit 7 6 5 4 3 2 1 0 0 0 0 0 0 P4IN2 P4INO Reset 0 0 0 0 0 Pin Pin Pin R W R R R R R R R R The PnIN registers contain the port input data The bit number corresponds to the associated pin number For instance POIN7 applies to the PO7 pin These are 8 bit access registers PODIR P3DIR Ports 0 3 I O Control Registers x 03F30 x
208. es Instruction 240 Appendix MN101C Series Instruction 246 Panasonic Semiconductor Development Company MN101C46F LSI User Manual vi Panasonic List of Tables List of Tables 1 1 MNIOICA6F Derivatives eser ee e RR EE 1 1 2 Description of Hardware ocaeca RR ere Rn se RED rd RS ERR RC RR RERO 2 1 3 Pin Description usu 6 1 4 Absolute Maximum 1 1 2 7 7 1 5 Recommended Operating 1 8 1 6 Electrical Characteristics 2 2 eb pi EPA SEE 8 1 7 PC Timing for Master Transmission SCL SDA Master Reception SCL and Slave Transmission SDA 12 1 8 Timing for Slave Reception SCL SDA Slave Transmission SCL and Master Reception SDA 12 1 9 HSYNC and VSYNC Input Conditions 13 2 1 Basic CPU Features a uh tig bol De A ele Be ee oe ek ele a Ok 20 2 2 Block Description 5 520 3 E Se oe ESA VS TREE Re Sua 22 2 3 CPU Control Registers 1 x Vx a ANA e EORR RUND Ma Sh esha 23 2 4 Interrupt Mask Levels and Interrupt Acceptance 28 2 5 Address Space l
209. et MN101C SERIES INSTRUCTION SET Group Mnemonic Operation Code Cycld Re 5002 Data Move Instructions MOV MOV Dn Dm Dn Dm 2 1 1010 DnDm 25 MOV imm8 Dm imm8 Dm 412 1010DmDm lt 8 gt 25 MOV Dn PSW Dn PSW 3 3 0010 1001 01Dn 26 PSW Dm PSW5Dm 3 2 0010 0001 01Dm 26 MOV An Dm mem8 An gt Dm 212 0100 1ADm 27 MOV d8 An Dm mem8 d8 An gt Dm 41 2 0110 1ADm lt 08 gt 4 27 MOV d16 An Dm mem8 d16 An gt Dm 7 4 0010 0110 1ADm d16 28 MOV d4 SP Dm mem8 d4 SP gt Dm 3 2 0110 01Dm lt d4 gt 72 28 MOV d8 SP Dm mem8 d8 SP gt Dm 5 3 0010 0110 01Dm lt d8 gt 3 29 MOV d16 Dm mem8 d16 SP gt Dm aa gt 7 4 0010 0110 00Dm d16 29 MOV 108 0 mem8 IOTOP io8 Dm 4 2 0110 00Dm lt 08 gt 30 MOV aaa Dm mem8 abs8 gt Dm 412 0100 01Dm abs 8 gt 30 MOV abs12 Dm 8 12 5 2 0100 00Dm abs 12 gt 31 MOV abs16 Dm mem8 abs16 Dm 71 4 0010 1100 00Dm abs 16 gt 31 MOV Dn Am 8 s ss 212 0101 1aDn 32 MOV Dn d8 Am Dn mem8 d8 Am 4 2 0111 laDn lt d8 gt 1 32 MOV Dn
210. g xxxLVn of the maskable interrupt control regis ter xxxICR is input to the CPU core Acceptance Always accepted Always accepted Acceptance determined by the interrupt mask level IM of the PSW and interrupt control of the register xxxICR Machine cycles needed for accep tance 12 PSW status after acceptance All flags cleared to 0 Interrupt mask level flag of PSW cleared to 00 The interrupt mask level of the PSW is set to the interrupt level flag xxxLVn setting Interrupt requests whose level is the same or lower than the accepted level are masked Panasonic Semiconductor Development Company 47 Panasonic MN101C46F LSI User Manual Interrupts Block Diagram 3 3 Biock Diagram Level detect gt Interrupt CPU core Vector 1 IRQNMI IRQLVL 2 0 WDOG 7 IRQICR poxLV 1 0 Peripheral functions VO xxxLV Interrupt Level xxxIE Interrupt Enable xxxIR Interrupt Request XXXICR xxxLV 1 0 Peripheral functions yo xxxLV Interrupt Level xxxIE Interrupt Enable xxxIR Interrupt Request Figure 3 1 Block Diagram for Int
211. g Control Register High x 03E39 DATAS Data Capture Start Timing Control Register x 03E18 DATASW Data Capture Start Timing Control Register x 03E38 Bit 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA S S S S S S S S S S S 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 RW R R R R RW RW RW RW RW RW RW RW RW RW RW DATAS 10 0 Start position for data capture Set this field to the same start position as that for CRI detection set in CRD2S The valid range is x 000 to x 7FF DATAEH Data Capture Stop Timing Control Register High X O3E1B DATAEWH Data Capture Stop Timing Control Register High x 03E3B DATAE Data Capture Stop Timing Control Register x 03E1A DATAEW Data Capture Stop Timing Control Register x 03E3A Bit 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA E E E E E E E E E E E 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 R W R R R R R RW RW RW R W RW RW RW RW RW RW RW DATAE 10 0 Stop position for data capture Set this value high enough to allow the last data to be captured The valid range is x 000 to x 7FF STAPH Sampling Start Position Register Software Setting High x 03E1D STAPWH Sampling Start Position Register Software Setting High X
212. g interface control x 03FCO cH CH CH CH ROM correction control 2 correc X 03FDO DATF DATE DATD DATC DATB DATA DATO DATS 7 DAT6 DATS DAT3 DAT2 DATI DATO tion data x O3FEO TM3I TM2I IRQSI IRQ4I IRQ3I IRQ2I IRQII IRQOI NMIC CR CR CR CR CR CR CR R Int RMC AD VBIV VBIV DC OSD VBIO EE ICR ICR OICR ICR ICR ICR ICR MN101C46F LSI User Manual Panasonic Semiconductor Development Company 236 Panasonic MN101CF46F Flash EEPROM Version Description Appendix B MN101CF46F Flash EEPROM Version B 1 Description The MN101CF46F is an electrically programmable 96 kilobyte flash ROM versions of the MN101CF46F It is programmed in PROM writer mode which uses a dedicated writer The 96 kilobyte flash memory is divided into two main areas Fixed user program area 96 kilobytes x 0x04000 to x Ox1BFFF This area stores the user program It is overwritten in PROM writer mode User program area 32 kilobytes x 0x00000 to x Ox03FFF and x 0x1C000 to x 0x 1FFFF This area cannot be used When using the writer fill this area with FF Normal operation is guaranteed with up to ten programmings x 0x00000 16 KB Reserved area 0 04000 96 Fixed user program area x 0x1C000 1
213. ged number of internal interrupts from 10 to 9 Chapter 4 I O Ports 4 5 Changed notes for P3OUT 4 12 Changed notes for P2MD 4 14 Changed description of PCNT2 bits 1 to 0 4 21 Revised figure 4 3 7 4 31 Revised figure 4 3 17 Chapter 6 8 Bit Timers 6 10 Revised setup example 2 6 13 Revised setup example 3 Chapter 7 On Screen Display 7 26 Changed hi z control description in figure 7 5 1 Chapter 8 Analog to Digital Converter 8 2 Changed names of ADC input pins in text and table 8 1 1 8 3 Changed names of ADC input pins in figure 8 2 2 8 6 In figure 8 2 2 changed names of analog input channels for A D control register 1 8 8 Changed names of ADC input pins in setup procedures MNIOICA46F Revision History Panasonic Semiconductor Development Company Panasonic Page in Japanese Description of Revision 8 10 Changed names of ADC input pins in table 8 3 1 8 12 Changed names of ADC input pins in text Changed pin setup registers in 1 of setup example Changed names of ADC input pins in 2 of setup example In figure 8 3 3 changed names of ADC input pins and deleted VREF and VREF pin names Deleted note on ANBUFO register from 9 of setup example Chapter 12 ROM Correction 12 5 Added AMCHIM to text
214. ground color 16 colors As with CCOL this value is in reference to the selected color palette PLTOO PLT17 or PLT20 PLT37 ITALIC COL bit 10 in the RAM data enables character italicization when set to 1 CUNDL COL bit 11 in the RAM data enable character underlining when set to 1 PLTOx x OSEEO x OGBEE7 and PLT1x x O3EES8 x O3EEF or PLT2x x O3EFO0 x O3EF7 PLT3x x 03EFO x O3EFF spec ify the palette color for the font data stored in ROM Panasonic Semiconductor Development Company MN101C46F LSI User Manual 127 Panasonic On Screen Display Setting up the OSD Setting up functions for all text This section describes settings for text display that are used for both normal display and closed caption display BLINK COL bit 8 in the RAM data enables character blinking when set to 1 FRAME COL bit 9 in the RAM data enables character outlining when set to 1 Set the outline color using FRAME in the color palette FRAME x 03ED2 specifies the outline color or character shading Setting up functions for all the display colors Color background function The color background function allows you to fill the television screen areas that are not covered by the OSD display text or graphics with any color COLB x O3EDS bit 0 enables the color background function when set to 1 COLB x OSEDO specifies the color of the background Transparency PLTx0 PL
215. he watchdog timer will vary so consider the danger of triggering a watchdog interrupt when you are setting the lower limit at which the watchdog timer can be cleared 9 2 2 Setup Examples for the Watchdog Timer In this example the watchdog timer is used to detect software faults The detection period is 21 system clocks and the lower limit for clearability is 2 system clocks The procedure is described below Table 9 3 Initialization Program Example Setup that Initializes the Watchdog Timer Procedure Description 1 Set time out period WDCTR x0 3F02 bits 2 1 WDTS 1 0 01 1 Set the WDTS 1 0 field of the WDCTR to 01 to select 218 system clocks as the time out period 2 Set lower limit of clearability WDCTR x 03F02 bits 5 3 WDTC 2 0 010 2 Set the WDTC 2 0 field of the WDCTR to 010 to select 2 system clocks as the lower limit for clearability 3 Start watchdog timer running WDCTR x 03F02 bit O WDEN 1 3 Setthe WDEN flag in the WDCTR to 1 to start the watchdog timer running Table 9 4 Program Main Routine Example Setup that Periodically Clears the Watchdog Timer Procedure Description 1 Periodically clear the watchdog timer Write to WDCTR x 03F02 1 Clears the watchdog timer with a period of at least 2 system clocks and no more than 218 system clocks c f BSET WDCTR WDEN bit O WDEN 1 Insert watchdog timer clears wit
216. he graphic tiles using register settings This allows you to adjust the memory space to fit your application Table 7 1 OSD Functions and Features Function Feature Text Characters Graphics Tiles Characters or tiles per line single screen Maximum total number of text characters graphic screen 61 codes tiles on the line holding the most characters on the 60 characters per line maximum 61 tiles per line In closed caption mode 16 of 27 colors two 16 color palettes RAM usage 128 bytes per line maximum 128 bytes per line maximum Line by line basis 2048 bytes 16 lines vertically Line by line basis 2048 bytes 16 lines vertically Maximum 64 lines Maximum 64 lines ROM usage 36 bytes per character 9 KB 256 character types 8 colors 108 bytes per tile 7 KB 64 tile types Resolution 16 wide X 18 high pixels 16 wide X 18 high pixels In closed caption mode 16 X 26 underlining is in the hardware Color depth 8 of 27 colors four 8 color palettes 8 of 27 colors four 8 color palettes Up to 27 colors in one display Display position H 1 dot resolution 1024 steps 1 H scan line resolution 1024 steps H 1 dot resolution 1024 steps V 1 H scan line resolution 1024 steps Display size Four vertical types and four horizontal types on a line by line basis total 16 types Four vertical types and four horizontal types on a line by line b
217. he sync separator status HVCOND 196 x O3ESA x O3E7A Sync separator status register Panasonic Semiconductor Development Company MN101C46F LSI User Manual 179 Panasonic Closed Caption Decoder Functional Description 10 3 3 1HSYNC Separator The HSYNC separator extracts the HS YNC signal from the composite sync signal using the sampling clock generated by the sync separator clock pulse gen erator This circuit also secures and interpolates the HS YNC signal T Error HSYNC Missed Detected HSYNC resulting from HSYNC noise Window for securing and interpolating HSYNC h 1 Window open Gane HSEP2H HSEP setting l O O Q Interpolated Secured and HSYNC interpolated HSYNC HSEPTH HSEP1 setting gt Figure 10 7 HSYNC Securement and Interpolation As shown in figure 10 7 noise can cause the HSYNC detection circuit to both miss HSYNC pulses and add erroneous ones The HSYNC separator contains a window circuit to correct these errors The open and close timing for this window is set in HSEP1H HSEP1 HSEP2H and HSEP2 registers The unit used for the setting is the sampling clock for the HSYNC separator The circuit counts a corrected and interpolated HSYNC signal If the count within the interval set in the HDISTWH and HDISTW registers is greater than that set in HLOCKLVH and HLOCKLV registers the HLOCK bit of HVCOND
218. hin the main routine so periods are equal and the set period is achieved We recommend an instruction that does not change the value such as a bit set BSET for the clear Table 9 5 Setup of Interrupt Service Routine Procedure Description 1 Watchdog interrupt service 1 A nonmaskable interrupt is generated when NMICR x 03FE1 the watchdog timer overflows Check that TBNZ NMICR WDIR WDPRO the WDIR flag in the nonmaskable inter T rupt control register NMICR is set to 1 with the interrupt service routine and per form service appropriate to the system MN101C46F LSI User Manual Panasonic Semiconductor Development Company 172 Panasonic Watchdog Timer Watchdog Timer Control Register a Operation just prior to when a watchdog interrupt is engaged can not be guaranteed When a watch dog interrupt occurs run a program that initializes the system 9 3 Watchdog Timer Control Register The watchdog timer is controlled by the watchdog timer control register WDCTR Address x 03F02 R W R W Register Description WDTCR The watchdog timer control register WDTCR Watchdog TImer Control Register x 03F02 Bit 6 5 4 3 2 1 0 WDTC2 WDTCI WDTCO WDTSI WDTSO WDEN Reset 0 0 0 0 0 1 1 0 R W R R R W R W R W R W R W WDTC 2 0 Watchdog Timer Counter This field sets the lower limit va
219. his function saves RAM space by preventing the VRAM address from incrementing The program redisplays the preceding charac ter code the specified number of times This increases the limit beyond 61 characters per line Panasonic Semiconductor Development Company MN101C46F LSI User Manual 119 Panasonic On Screen Display VRAM HP Horizontal Position Control Code ID Code 11 HSZ 1 0 This field specifies the H size of the display code on the next line 00 1 dot 1 VCLK period 01 1 dot 2 VCLK periods 10 1 dot 3 VCLK periods 11 1 dot 4 VCLK periods SHT Specifies shutter operation for the next line Setting this bit to 1 disables the shuttering function You can disable and enable shuttering on a line by line basis 0 Enable 1 Disable HP 9 0 This field specifies a VCLK indicating the horizontal start position for the next line 1024 steps are available VP Vertical Position Control Code ID Code 11 LAST Specifies the last line in the display This resets the line pointer for charac ter reads from the internal RAM to the first line 0 Disable Enable VSZ 1 0 This field specifies the V size of the display code on the next line 00 1 dot 1 H scan line 01 1 dot 2 H scan lines 10 1 dot 4 H scan lines 11 1 dot 6 H scan lines INT Specifies an OSD interrupt 0 Disable Enable VP 9 0 Specifies an H scan line indicating the vertical start position for the next line 1024 steps are availab
220. iagram lt ta sepes tae er repe RANG ee eae das 160 8 3 Analog to Digital Conversion Operation 161 8 3 1 Setting Up A D 163 8 3 1 1 Setting up the A D Conversion Input 163 8 3 1 2 Setting up the A D Conversion 163 8 3 1 3 Setting up the A D Conversion Sampling 164 8 3 1 4 Controlling the Internal Ladder Resistors 164 8 3 1 5 Setting the Start of A D 164 8 3 2 Setup Example of A D Conversion 2 165 8 3 2 1 Operating the ADC with Register Settings 165 8 3 3 Cautions on A D 2 71 166 8 3 3 1 Noise Prevention ccce Rr C RU GER ea P RC eb 166 8 4 ADC Control Registers sv eee ees pee ban ETE eue dab v tu EQ bh a 167 8 4 1 ADC Gontrol Registers cech DEEP EN VI FRE UE ERU ERAS EUROS ES 167 8 4 2 AVD Butter s S UE 168 9 Watchdog Tier uy oleo REV E Re Er xe Rx Re RE AR 169 9 1 Description os Seve Bo
221. iation auto reception 5 6 bit detection 1 bit interrupts PC Two multimaster circuits 1 internal PWM Six 8 bit channels one 14 bit channel MN101C46F LSI User Manual Panasonic Semiconductor Development Company 2 Panasonic General Description OHardware Functions Table 1 2 Description of Hardware Continued Function Description SYSCLK output Clock output uses a period of fs or fs 4096 Closed caption decoders Two channels with a built in sync separator Handles 12 0 14 0 or 14 32 MHz OSD functions 16 x 18 pixel H x V graphic tiles 16 character tile sizes 8 out of 27 colors displayable per tile on the graphics layer 27 text colors and 27 text background colors displayable Port functions 35 I O ports Six 5 V N channel open drain ports Four input ports Low power modes STOP HALT and SLOW modes Operating voltages 3 0 to 3 6 V Package 42 pin SDIP 64 pin LQFP 0 Package model number SDIP042 P 0600 LQFPO064 P 1414 0 Notes 1 In case of flst package Panasonic Semiconductor Development Company MN101C46F LSI User Manual 3 Panasonic General Description Pin Description 1 4 Pin Description 1 4 1 Pin Configuration IRQO RMIN 1 Vss 1 SDA1 P01 2 OSC2 1 SCL1 P02 3 OSC1 IRQ1 ADIN0 P03 4 Vpp Vpp 2 ADIN1 P04 5 P42 SCLO 1 ADIN2 P05 6 P41 SDAO 1
222. ilization Wait The oscillation stabilization wait is the time required for a stopped oscillation circuit to reach stable oscillation An oscillation stabilization wait is inserted automatically when a reset is cleared or when returning from the STOP mode You can select the oscillation stabilization wait when returning from the STOP mode by setting the oscillation stabilization wait control register DLYCTR The oscillation stabilization wait is fixed for reset clearing The timer that counts the oscillation stabilization wait is also used as a watchdog timer It also functions as an override detection timer if not clearing a reset or returning from STOP mode When resetting from the STOP mode the watchdog timer is initialized and counting begins from an initial value x 0000 using the system clock fs as the clock source After the oscillation stabilization wait ends the timer continues counting as a watchdog timer See section 9 Watchdog Timer on page 169 NRST STOP 3 write WDCTR R R i HALT D 1 2 1 214 1 215 1 220 Internal 5 5 reset sysclk release s 214 210_ MUX DLYCTR MU 0 fs 22 Hase 7 fg 229 15 218 MUX wb IRQ WDCTR 15 219 WDEN 0 worso 1 _WDTS1_ WDTCO WDTC1 WDTC2 REESE 7 Figure 2 10 Function Block Diagram of the Oscillator Stabil
223. in the RAM data set the code of the tile to be displayed PLT 1 0 CC bits 12 to 11 in the RAM data select color palette 0 1 2 or 3 CGSEL CC bit 13 in the RAM data selects graphic tile display when 1 PLT0x x 03EE0 x 03EE7 PLT1x x 03EE8 x 03EEF PLT2x x 03EFO x 03EF7 or PLT3x x 03EFO x 03EFF specify the palette color for the tile data stored in ROM B Setting up the text display colors normal display The following settings determine the text display colors in normal mode CAPM bit 1 sets normal display mode when 0 CH 8 0 CC bits 8 to 0 in the RAM data set the code of the font to be displayed PLT 1 0 CC bits 12 to 11 in the RAM data select color palette 0 1 2 or 3 CGSEL CC bit 13 in the RAM data selects text font display when 0 CCOL 2 0 COL bits 2 to 0 in the RAM data set the color of the character 8 colors This value is in reference to the selected color palette PLTxO PLTx7 MN101C46F LSI User Manual Panasonic Semiconductor Development Company 126 Panasonic On Screen Display Setting up the OSD BCOL 2 0 COL bits to 4 in the RAM data set the background color 8 colors As with CCOL this value is in reference to the selected color pal ette PLTx0 PLTx7 CSHAD COL bit 10 in the RAM data enables character shadowing when set to 1 Set the shadowing color in the FRAME of the
224. ing Mode Valid Addresses Description Register Dn DWn Specifies the register directly Only internal registers direct An SP can be specified PSW Immediate imm4 imm8 Directly specifies an operand value mask value or values imm16 the like to be appended to an instruction code Register An 15 0 Specifies addresses using address registers indirect An Register rela d8 An 15 0 Specifies addresses using address registers and an 8 tive indirect An d8 bit displacement d16 An 15 0 Specifies addresses using address registers and a 16 An 416 bit displacement d4 PO 17 0H Specifies addresses using the program counter a 4 bit Jump instructions only PC d4 displacement and the H bit d7 PC 17 0H Specifies addresses using the program counter a 7 bit Jump instructions only PC d7 displacement and the H bit d11 PC 17 0H Specifies addresses using the program counter a 11 Jump instructions only PC d11 bit displacement and the H bit d12 PC 17 0H Specifies addresses using the program counter a 12 Jump instructions only PC d12 bit displacement and the H bit d16 PO 17 0H Specifies addresses using the program counter a 16 Jump instructions only PC 916 bit displacement and the H bit Stack relative d4 SP 15 0 Specifies addresses using the stack pointer and a 4 bit indirect SP d4 displacement d8 SP 15 0 Specifies addresses using the stack pointer and an 8 SP d8 bit displacement d16 SP 15 0
225. inter rupts Use interrupt control registers with the maskable interrupt enable flag MIE of the PSW at 0 VBV1LV 1 0 Interrupt level specification flag A 2 bit flag that sets the interrupt level Determines which of the CPU s levels 0 3 is assigned to the interrupt VBV1IE Interrupt enable flag 0 Disable interrupt 1 Enable interrupt VBV1IR Interrupt request flag 0 No interrupt request 1 Generate interrupt request OSDICR OSD Interrupt Control Register x O3FF5 Bit 7 6 5 4 3 2 1 0 OSDLVI OSDLVO OSDIE OSDIR Reset 0 0 0 0 0 0 0 0 R W R W R W R R R R R W R W The OSD interrupt control register OSDICR is the register that controls interrupt levels interrupt enables and interrupt requests for OSD inter rupts Use interrupt control registers with the maskable interrupt enable flag MIE of the PSW at 0 OSDLV 1 0 Interrupt level specification flag A 2 bit flag that sets the interrupt level Determines which of the CPU s levels 0 3 is assigned to the interrupt OSDIE Interrupt enable flag 0 Disable interrupt 1 Enable interrupt OSDIR Interrupt request flag 0 No interrupt request 1 Generate interrupt request Panasonic Semiconductor Development Company MN101C46F LSI User Manual 63 Panasonic Interrupts Interrupt Control Registers I2CICR I C Interrupt Control Register x 03FF6 Bit F 6 5 4 3 2 1 0 DCLVI DCLVO
226. interrupt request flag is set at the next count clock and TM3BC and TM2BC start counting up again from x 0000 Use 16 bit access instructions when working with the settings for the combined register and 2 Start the high order timer before the low order timer Panasonic Semiconductor Development Company 105 Panasonic MN101C46F LSI User Manual 8 Bit Timers 8 Bit Timer Control Registers 6 4 8 Bit Timer Control Registers Timers 0 through 4 are each composed of a binary counter TMnBC and a compare register TMnOC They are controlled by mode registers TMnMD If you are selecting the count clock sources for timers 0 through 4 by selecting a prescalar output you must use the prescalar control register PSCMD and a prescalar select register CKnMD for control Control the IR remote signal receiver with the IR remote signal receiver carrier output control register RMCTR 6 4 1 Control Registers Table 6 6 lists the registers that control timers 2 through 4 Table 6 6 8 Bit Timer Control Registers Register Address R W Description Timer 2 TM2BC 03 50 R Timer 2 binary counter TM2OC x 03F52 R W Timer 2 compare register TM2MD x 03F54 R W Timer 2 mode register CK2MD x 03F56 R W Timer 2 prescalar select register PSCMD x 03F6F R W Prescalar control register TM2ICR x 03FE9
227. iods When the watchdog timer is cleared in a period shorter than the set time the lower limit at which the watchdog timer can be cleared it is considered a software fault and a watchdog interrupt WDIRQ is generated Two consecutive watchdog interrupts will be interpreted as a software fault that cannot be recovered by software and requires a forcible reset by hardware 9 2 1 1 Using Watchdog Timer Functions Periodically clear the watchdog timer during your program to avoid timer overflows when you are using the watchdog timer function When the microcon troller experiences a software fault for any reason the program will not be able to execute correctly the watchdog timer will overflow and a software fault will be detected Programming of watchdog timer functions should generally be performed at the last stage of program debugging 9 2 1 2 Methods of Software Fault Detection When the program is running correctly it is expected that the watchdog timer function is cleared at set intervals The MN101C46F s watchdog timer has two ways it detects software faults 1 When the watchdog timer overflows 2 When the watchdog timer clears at an interval shorter than the value set in the WDCTR register for the lower limit at which the timer can be cleared When a software fault is detected a watchdog interrupt WDIRQ is generated as a nonmaskable interrupt NMI 9 2 1 3 Clearing the Watchdog Timer The watchdog timer
228. ion Map to Latest version Revision 1 30 to Revision 2 00 July 19 2000 Page in Japanese Description of Revision Chapter 1General Description 1 2 Changed original frequency to 14 32 MHz and minimum instruction execution time to 273 3 ns 1 3 Corrected machine cycle and system clock frequency values Added description of CCD VSYNC interrupt 1 4 Revised CCD frequencies 1 6 Changed input ports on pin configuration to I O ports 1 7 Changed input ports in pin description table to I O ports 1 8 to 1 18 Corrected electrical specs adjusting them for new 14 32 MHz maximum fre quency 1 19 Added HSYNC and VSYNC input conditions Chapter 2 Basic CPU Functions 2 1 Changed internal operating frequency to 14 32 MHz and minimum instruction execution time to 273 3 ns 2 16 Added VBIVOICR and VBIV 1ICR interrupts to register map 2 18 Adjusted values for new 14 32 MHz maximum frequency 2 23 Adjusted values for new 14 32 MHz maximum frequency 2 27 Adjusted values for new 14 32 MHz maximum frequency Chapter 3 Interrupts 3 3 Added table with list of interrupt functions 3 6 3 15 Added VBIVO and VBIV I interrupt vectors vector numbers 23 and 24 3 26 Changed VBIO interrupt to CCDO interrupt 3 27 Changed VBII interrupt to CCD1 interrupt 3 30 Added CCD0 VSYNC VBIVO interrupt 3 31 Added CCD1 VSYNC VB
229. ions for the MN101C46F I C bus interface SDA 3 X I lI LAT 1 d tsu ste tsu ste nm re FA I j tk Figure 13 6 SDA and SCL Waveforms Table 13 5 SDA and SCL Waveform Characteristics Parameter Symbol Min Max Unit SCL clock frequency 0 100 kHz Bus free time between a stop and start condition tBUF 20 us Hold time repeated start condition tHD STA 4 0 Low period of the SCL clock tLow 4 7 High period of the SCL clock tHIGH 4 0 Setup time for a repeated start condition tSU STA 300 Data hold time tHD DAT 250 ns Data setup time teU DAT SDA and SCL rise time tg 1000 SDA and SCL fall time tp 300 Stop condition setup time tsu sTP 4 0 us Panasonic Semiconductor Development Company MN101C46F LSI User Manual 219 Panasonic I C Bus Controller PC Interface Setup Examples 13 6 1 C Interface Setup Examples 13 6 1 Setting up a Transition from Master Transmitter to Mas ter Receiver This example demonstrates how to set up a data transfer when changing from master transmitter to master receiver Figure 13 7 shows an example waveform 13 6 1 1 Pre configuring To set up the I O port Set port control register 0 x 03F4A to x 40 enabling the SDAO and SCLO pins and set the port 4 output mode register PAMD x 03F2C to x 06 selecting the SDAO and SCLO fun
230. is restored from the stack SP 4 or 5 saved so put a PUSH instruction in the program if you need to save 4 SP value is updated SP 6 SP them to the stack The handy address register is an internal register saved so that handy addressing Bits 6 2 of the address where the is not affected by interrupts program counter bits 18 17 and 0 5 Operation jumps to the address indicated by the PC is saved are reserved Do not have the program change them MN101C46F LSI User Manual Panasonic Semiconductor Development Company 54 Panasonic Interrupts Operation 3 4 7 Maskable Interrupts The sequence of operation when an interrupt with a low mask level occurs during interrupt servicing is shown below interrupt 1 xxxLV 1 0 00 interrupt 2 xxxLV 1 0 2 10 jC Ree IM 1 0 b 00 Mainprogram Set MIE IM 1 0 b 11 Interrupt 1 occurs z L IM and MIE 1 so accepted xxxLV 1 0 b 00 Interrupt IM 1 0 servicing cycle C Interrupt service routine 1 1 Interrupt 2 occurs xxxLV 1 0 b 10 2 9 bir Interrupt 0 servicing cycle Cinterrupt service RT Interrupt occurs 7 IM IL so not accepted xxxLV 1 0 b 11 Y Notes 1 Interrupts that occur during interrupt service routi
231. it Pulse Width 212 1 227 14 1 1 14 Bit PWM 1 227 14 1 2 14 Bit PWM Output Waveforms 1 228 14 1 3 Data Transfers from Registers to Latches 229 14 2 8 Bit Pulse Width 230 14 2 1 8 Bit PWM Description a Ime Ire 230 14 2 2 8 Bit PWM Output Waveform chs cR hee Rv OR abe eee 231 14 3 PWM Registers cioe oo bI eek Beis E ES Pn ES eben inc d EE 232 14 3 1 14 Bit PWM Control Registers 2 232 14 3 2 8 Bit PWM Control 1 233 Appendix A Register 235 Appendix MN101CF46F Flash EEPROM 237 B 1 Description ioco o er PES ees Cu eee ea aia ew Sa 237 2 Benefits ahua haba ep hh es e a ub etg 237 B 3 Using the PROM Writer 4 4 238 B 4 Reproeramrmne FOW aqu P ERPPRERE PEE REO NEUE 239 B 5 Programming TIMES issues RR RA a DR re RE Ma ps d 239 Appendix MN101C Seri
232. it samples the remote signal with fsysc Set the frequency divide by ratio to meet this condition If you do not the microcontroller may interpret the data 1s and Os incorrectly After the program sets the divide by ratio for the frequency in RMTC the read values may be incorrect until the circuit detects the next active edge of the remote signal Bit Reset R W 11 4 IR Remote Signal Receiver Control Registers Table 11 4 IR Remote Signal Receiver Registers Register Address R W Function RMTC 0 4 Remote signal frequency division control register RMIR x 03EA2 R W Remote signal interrupt control register RMIS 0 0 R W Remote signal interrupt status register RMLD x 03EAC R W Remote signal leader value set register RMCS x 03EA6 Remote signal clock status register RMSR x 03EA8 Remote signal reception data shift register RMTR x OGBGEAA Remote signal reception data transfer register Z 6 5 4 3 2 RMTC Remote Signal Frequency Division Control Register 1 X O3EA4 0 RMTC7 RMTC6 5 RMTC4 RMTC3 RMTC2 RMTCO 0 0 0 0 0 R W R W R W R W R W 0 R W To identify the remote signal the IR signal receiver generates a sampling clock Ts by dividing the PWM2 pulse by the value set in RMTC 7 0 fpwm2 18 fsyscrk divided by 2 2 447 5 kHz and 2 2 us with a
233. ization Wait MN101C46F LSI User Manual Panasonic Semiconductor Development Company 44 Panasonic Basic CPU Functions Resets DLYCTR Oscillation Stabilization Wait Control Register x O3F03 Bit F 6 5 4 3 2 0 DLYSI DLYS0 Reset 0 0 0 0 0 0 R W R R R R R W R W R DLYS 1 0 Oscillation stabilization wait period select The oscillation stabilization wait period after a reset is f 214 00 214 01 210 10 26 1 22 2 14 2 1 Controlling the Oscillation Stabilization Wait When returning from the STOP mode you can select an oscillation stabilization wait of 214 210 26 or 2 system clocks by setting bits 3 2 DLYS1 and DLYSO of DLYCTR When clearing a reset the oscillation stabilization wait is fixed at 214 system clocks Select the system clocks in the CPU mode control register CPUM Table 2 9 Oscillation Stabilization Wait DLYS1 DLYS2 Oscillation Stabilization Wait 0 0 215 system clocks 0 1 210 system clocks 1 0 26 system clocks 1 1 22 system clocks Panasonic Semiconductor Development Company MN101C46F LSI User Manual 45 Panasonic Interrupts Description 3 Interrupts 3 1 Description For faster response the MN101C46F uses a vector system that jumps directly to an interrupt service routine The MN101C4A6F s interrupt vectors include a reset a nonmaskable interrupt NMJ six external interrupts and nine internal inter
234. kground shuttering 1 Don t shutter text layer background Graphics shuttering GSHT 0 Shutter graphics layer 1 Don t shutter graphics layer Color background COLBSHT 0 Shutter color background shuttering 1 Don t shutter color background Shutter blanking SHTBLK 0 Don t output blanks to the shuttered area 1 Output blanks to the shuttered area To shutter text layer characters text layer background and graphics layer Text Set the text shutter control bit CCSHT of the shutter control register SHTC x 03EC8 to 1 Text background Set the text background shutter control bit BCSHT of SHTC to 1 Graphics Set the text background shutter control bit GSHT of SHTC to 1 Figure 7 20 shows three setup examples of text layer shuttering Panasonic Semiconductor Development Company MN101C46F LSI User Manual 141 Panasonic On Screen Display Controlling the Shuttering Effect HSHT0 HSHT1 CCSHT 0 Shuttering of text foreground disabled BCSHT 0 Shuttering of text background disabled VSHTO VSHT1 Television screen Shuttered region HSHTO HSHT1 H CCSHT 1 Shuttering of text foreground enabled DE PO NATU SE Rod VSHTO BCSHT 0 Shuttering of text background disabled VSHT1 Television screen HSHT0 HSHT1 H CCSHT 0 Shuttering of text foreground disabled E AENEA VSHT0 BCSHT 1 Shuttering of text background enabled LJ B Shri iQ ICI MES VSHT te
235. l position of the display Write the position of the first line in the display to the IHP field x OS3ECA and x 03ECB bits 9 to 0 Write the position of the second and all following lines in the HP 9 0 field within the text display RAM data of the preceding line Permissible ranges IHP gt x 0C and HP gt x 0C About the horizontal start position on the screen The horizontal position or HP settings determine where the left side of the display starts on the screen You can set this value in 1 pixel units To set the vertical position of the display Write the position of the first line in the display to the IVP 9 0 field x OSECC and x 03ECD Write the position of the second and all following lines in the VP 9 0 field within the text display RAM data of the preceding line Permissible range x 3F0 no of H scan lines gt IVP or VP gt x 03 Sample VP range calculation The base graphics line height is 18 dots or H scan lines If the graphics line you are positioning displays at 2x the base height the number of H scan lines is 18 x 2 36 x 24 H scan lines The permissible range of settings for VP is x 3F0 24 x 3CC gt VP gt x 03 About the vertical start position on the screen The vertical position VP settings determine where the upper edge of the display starts on the screen You can set this value in H scan line units MN101C46F LSI User Manu
236. lag Sets a CPU level between 0 3 for the interrupt REDGn External interrupt enable edge specification flag 0 Negative edge 1 Positive edge IRQnIE External interrupt enable flag 0 Disable interrupt 1 Enable interrupt IRQnIR External interrupt request flag 0 No interrupt request 1 Generate interrupt request MN101C46F LSI User Manual 60 Panasonic Panasonic Semiconductor Development Company Interrupts Interrupt Control Registers TMnICR Timer n Interrupt Control Register x 03FEB to x 03FED Bit 6 5 4 3 2 1 0 TMn TMn LVO TMnIE TMnIR Reset 0 0 0 0 0 0 0 0 RW RW R R R R RW RW The timer n interrupt control register TMnICR is the register that controls interrupt levels valid edges interrupt enables and interrupt requests for timer n interrupts Use interrupt control registers with the maskable inter rupt enable flag MIE of the PSW at 0 n 2 2 to 4 TMnLV 1 0 Interrupt level specification flag A 2 bit flag that sets the interrupt level Determines which of the CPU s levels 0 3 is assigned to the interrupt TMnIE Interrupt enable flag 0 Disable interrupt 1 Enable interrupt TMnIR Interrupt request flag 0 No interrupt request 1 Generate interrupt request VBIOICR Closed Caption Decoder 0 Interrupt Control Register x OSFF3 Bit 6 5 4 3 2 1 0 VBOLVI VBOLVO VBOIE VBOIR Reset
237. lamping current for input high Vpp 3 3 V 5 25 uA C32 Medium clamping current for input high IcLH2 1 6 V 50 180 C33 Very high clamping current for input high IcLH3 With the following connections 415 615 C34 High clamping current for input high Toy 33 KQ between CLH and GND 185 335 C35 Low clamping current for input low 6 8 between CLL and 18 3 C36 Medium clamping current for input low IcLL2 70 20 C37 Very high clamping current for input low Icr13 345 145 C38 High clamping current for input low IcLL4 205 55 Note 2 See figure 1 4 for the recommended pin connections 3 See figure 1 5 for the input waveform specification for the composite video signal 50 1 560 pF l Le Low pass filter CLL Note constants shown in this diagram are recommended values only Operation at these values is not guaranteed Figure 1 4 External Connection Example for Closed Caption Decoder Pins MN101C46F LSI User Manual Panasonic Semiconductor Development Company 10 Panasonic General Description Electrical Characteristics Table 1 6 Electrical Characteristics Continued Ta 20 to 70 C Vpp 3 3 V Vas 0 V No Parameter Symbol Conditions Min Typ Max Unit 8 bits
238. lay Position 134 7 8 DMA and Interrupt 2 2 1 135 7 9 Selecting the OSD Dot Clock 4 136 7 10 Controlling tbe Shuttering Effect i e IRR CROIRE 137 7 10 1 Controlling the Shuttered Area 137 7 10 2 Controlling Shutter Movement 1 139 7 10 3 Controlling Shuttering 1 141 7 10 4 Controlling Line Shutferimng sina y eR pL Red a ES ap CS S sss RUN BRE 143 7 11 Detection ge waste Gaga Phe USC a da ie 144 7 11 1 Block Dias tam 2 2 ons a De oer Be vale Rede 144 7 11 2 D seription RICE hs RR ee 144 7 11 3 Considerations for Interlaced Displays 145 7 12 OSD ee e UR RE C e E c OR beh eg 146 8 Analog Digital 159 8 1 Descriptions iso b his b EP ESE P Juba MENO dr yy sha wala 159 8 1 1 Eunctions eise ER RU bE RR RES a ES RAS SS ER EO EON ESR EP ON ED 159 8 2 ADC Block D
239. le AP RAM Address Pointer ID Code 11 AP 11 0 Specifies the VRAM start code address position of the next line Specifies an on chip RAM address within the 3KB x 0100 x OBFF The starting line is specified in the IAP register This is valid only when APCNT 1 MN101C46F LSI User Manual Panasonic Semiconductor Development Company 120 Panasonic On Screen Display VRAM Z 5 3 VRAM Organization Program Data and i Stack RAMEND 50xn 1 RAMEND 50x n 1 RAMEND 50xN 1 RAMEND 9F RAMEND Program Data and Stack Area RAMEND 50xN 1 RAMEND 2N RAMEND 2N 1 RAMEND RAMEND Notes 1 Line N data Line 2 data Line 1 data Line N data Line 2 data Line 1 data Any number RAMEND 1 APCNT 0 RAMEND 4F RAMEND 4E RAMEND 4D RAMEND 4C RAMEND 4B RAMEND 4A Code 39 Low order 8 bits of text code High order 8 bits of text code APCNT 1 RAMEND 2N 1 RAMEND 2N 2 RAMEND 2N 3 RAMEND 2N 4 RAMEND 2N 5 RAMEND 2N 6 RAMEND 2N 7 RAMEND 2N 8 RAMEND 3 RAMEND 2 Low order 8 bits of text code High order 8 bits of text code RAMEND All addresses are expressed in hex notation Other values are decimal 2 RAMEND RAM end address register programmable to any address Figure 7 4 VRAM Organization Panasonic Semiconductor Development Company 121 Panasonic MN101C46F LSI User Manual On Screen Display ROM x 080000 Program Data
240. lor graphics mode no graphics output Line No RAM Addr RAM Data Data Description 1 OBFE 2802 CC CG 1 PLT 1 CH x 002 OBFC 1801 CC CG 0 PLT 3 CH x 001 004 HSZ x 0 SHT 0 04 8 C040 VP LAST 0 VSZ x 0 INT 0 VP x 40 OBF6 CBF4 AP AP x BF4 2 OBF4 0810 CC CG 0 PLT 1 CH x 010 OBF2 2813 CC CG 1 PLT 1 CH x 013 OBFO 4003 CB BF 1 CB x 3 1014 CC CG 0 PLT 2 CH x 014 OBEC 4002 CB BF 0 CB x 2 OBEA 3016 CC CG 1 PLT 2 CH x 016 OBE8 D810 HP HSZ x 3 SHT 0 10 OBE6 C858 VP LAST 0 VSZ x l INT 0 VP x 58 OBE4 CBE2 AP AP x BE2 3 OBE2 2981 CC CG 1 PLT 1 CH2x 181 OBEO 3182 CC CG 1 PLT 2 182 OBDE C044 HP HSZ x 0 SHT 0 HP x 44 OBDC E020 VP LAST 1 VSZ x 0 INT 0 VP x 20 OBDA CBFE AP AP X BFE Notes 1 Always specify HP VP and AP in that order at the end of each line 2 Set INT to 1 in the VP setting to generate an OSD interrupt 3 Set LAST to 1 in the VP setting for the last line in the display Also set the VP value to a smaller value than the position of the current line In the example in table 7 4 VP x 20 is smaller than VP x 58 MN101C46F LSI User Manual 116 Panasonic Panasonic Semiconductor Development Company On Screen Display Display Setup Examples
241. lsd infomation required for your design purchasing and applications If you have any inquiries or questions about this book or our semiconductors please contact one of our sales offices listed at the back of this book Contents Contents 1 General 1 1 1 OVCIVIEW Loses ERO e tC cate e ibe e Sa sua y 1 1 2 Series Products cive bU EU P eel SS ee deb uw sha ut 1 1 3 OHardware Punctions d eR ai Soke SESS BA REAR RSS 2 1 4 Pin Descriptions se eR EOM ee uu ORC s de te Le et RET 4 1 4 1 Pin Configuration isis eLpbuIee ERR ROO uqaqa yaka UE epe Eee 4 1 4 2 Pin Description ess a ses S Ree aL e RU e EE RUN RR e EUR 6 1 5 Electrical Characteristics ir ere UELLE hen ie eg ie nate i 7 1 5 1 I C Interface Timi aea ses dede ecce de re UC e oaa ynin aa pa 11 1 5 2 HSYNC VSYNC Input 1 13 1 6 Circuit Design 2 1 4 2 14 1 6 1 Considerations when Using the 14 1 6 1 1 Connecting the VDD and VSS 14 1 6 1 2 Operation
242. lue at which the watchdog timer can be cleared 000 None 001 27 system clocks 010 2 system clocks 21 system clocks 100 21 system clocks 101 21 system clocks 110 217 system clocks 111 21 system clocks WDTS 1 0 Time out Period Setting 00 2 6 system clocks 01 218 system clocks 1 220 system clocks WDEN Watchdog Timer Enable 0 Disable 1 Enable Panasonic Semiconductor Development Company MN101C46F LSI User Manual 173 Panasonic Closed Caption Decoder Description 10 Closed Caption Decoder 10 1 Description The MN101C46F contains two identical closed caption decoder circuits CCD0 and CCD1 The decoders extract encoded captions from composite video signals Figure 10 1 provides a block diagram of the decoders and section 10 3 Func tional Description on page 175 describes the circuit s main blocks Note that this section describes CCDO but all descriptions also apply to CCD1 Table 10 1 provides the pin names for each decoder Table 10 1 Pins Used for CCDO and CCD1 Closed Caption Decoder Pin Name CCDO CVBSO VREFHO CLHO CLLO CCD1 CVBS1 VREFHI CLHO CLLO 10 2 Block Diagram Controller CRI Data extraction frequency detector ond ERI Slicing circuit Slice level detector Max min detector HSYNC separator Data extractor sampling circuit VSYNC separator RAM _ Clamping CPU Fig
243. ly during this period CRI2FQW 7 0 CRI frequency width 2 This field indicates the width in clock units from the second from last to the third from last detected CRI rising edge CRI1FQW 7 0 CRI frequency width 1 This field indicates the width in clock units from the last to the second from last detected CRI rising edge CRMFQW CRI Frequency Width Register B High x O3EOF CRIAFQWW CRI Frequency Width Register B High x OSE2F CRISFQW CRI Frequency Width Register B x 03E0E CRISFQWW CRI Frequency Width Register B x 03E2E Bit 7 6 5 4 3 2 1 0 T 6 5 4 3 2 1 0 CRI4 CRB CRB CRB CRB CRB FQW7 FQW6 5 FQW4 FQW3 FQW2 FQW1 FQWO FQW7 FQW6 5 FQW4 FQW3 FQW2 FQW1 FQWO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R R R R R R R R R R R R R R R CRI4FQW 7 0 CRI frequency width 4 This field indicates the width in clock units from the fourth from last to the fifth from last detected CRI rising edge CRISFQW 7 0 CRI frequency width 3 This field indicates the width in clock units from the third from last to the fourth from last detected CRI rising edge MN101C46F LSI User Manual Panasonic Semiconductor Development Company 188 Panasonic Closed Caption Decoder Closed Caption Decoder Registers
244. m NORMAL mode with a simple write to the CPU mode control register This does not require that you transit the idle state To switch from SLOW mode back to NORMAL mode start the fast clock oscil lating and hold the program in idle until the clock becomes sufficiently stable During idle the CPU runs at the slow clock Oscillation stabilization requires the same length of time as a reset Unlike the reset however you do not need to count with a program We recommend that you discuss the oscillation stabilization time with the oscillator manufacturer The following are examples of programs that move from SLOW back to NORMAL mode Program 2 MOV x 504 Y DO Invokes IDLE mode MOV DO CPUM Program 3 MOV x OB DO Loop for waiting 10 100 Hs LOOP ADD 1 D0 when at 3 58 MHz and BNE LOOP moving from slow 3 58 MHz SUB DO DO to fast 14 32 MHz clocks MOV DO Sets NORMAL mode Panasonic Semiconductor Development Company MN101C46F LSI User Manual 39 Panasonic Basic CPU Functions Standby Function 2 12 4 Invoking the Standby Mode Use programming to invoke standby modes from CPU operating modes use interrupts to return from standby modes to CPU operating modes Set the following to invoke standby modes 1 Clearthe interrupt enable flag MIE in the processor status word PSW and the interrupt enable flag xxxIE in the maskable interrupt control register xxxICR to disable all in
245. many Sales Office Panasonic Industrial Europe GmbH PIEG Hans Pinsel Strasse 2 85540 Haar GERMANY Tel 49 89 46159 119 49 89 46159 195 ASIA e Singapore Sales Office Panasonic Semiconductor of South Asia PSSA 300 Beach Road 16 01 The Concourse Singapore 199555 THE REPUBLIC OF SINGAPORE Tel 65 390 3688 Fax 65 390 3689 e Malaysia Sales Office Panasonic Industrial Company M Sdn Bhd Head Office Tingkat 16B Menara PKNS Petaling Jaya No 17 Jalan Yong Shook Lin 46050 Petaling Jaya Selangor Darul Ehsan MALAYSIA Tel 60 3 7951 6601 60 3 7954 5968 Fax 52 3 671 1256 Matsushita Electric Industrial Co Ltd 2001 Penang Office Suite 20 07 20th Floor MWE Plaza No 8 Lebuh Farquhar 10200 Penang Malaysia Tel 60 4 201 5113 Fax 60 4 261 9989 Johore Sales Office Menara Pelangi Suite8 3A Level8 No 2 Jalan Kuning Taman Pelangi 80400 Johor Bahru Johor MALAYSIA Tel 60 7 331 3822 Fax 60 7 355 3996 Oe Thailand Sales Office Panasonic Industrial THAILAND Ltd PICT 252 133 Muang Thai Phatra Complex Building 31st FI Rachadaphisek Rd Huaykwang Bangkok 10320 THAILAND Tel 66 2 693 3428 Fax 66 2 693 3422 Philippines Sales Office PISP Panasonic Indsutrial Sales Philippines Division of Matsushita Electric Philippines Corporation 102 Laguna Boulevard Bo Don Jose Laguna Technopark Santa Rosa Laguna 4026 PHILIPPINES Tel 63 2 520 8615 Fax 63 2 520 8629 lndia Sales Office Nation
246. ment previous 7 11 3 Considerations for Interlaced Displays B Switching the display start field The OSD is constructed so the display start position is the field field 1 where the EOMON bit is 1 however interlaced displays may require that the start position be a field field 2 where the EOMON bit is 0 In this case merely com plementing the EOSEL bit will not result in a correct display You must set the following two bits to have the display start at field 2 CANH 0 bit 4 Set to 1 0 Normal display 1 Slide the field 1 display position down 1 line EOSEL x 03EBP bit 2 Complement the value EOSEL has for field 1 in a normal display Scrolling in the closed caption mode To implement text layer scrolling in the closed caption mode the program must constantly switch the text display fields This can cause the text lines to display incorrectly To prevent this set the following bits to fix the text lines to the even or odd field characters while scrolling BFLD x OSEBA bit 2 Set to 1 to enable scrolling 0 Normal display 1 Display the same characters in fields 1 and 2 EONL bit 3 Set to or 1 0 Fix to characters in field 1 1 Fix to characters in field 2 Panasonic Semiconductor Development Company MN101C46F LSI User Manual 145 Panasonic On Screen Display OSD Registers 7 12 OSD Registers CROMEND Text ROM End Addres
247. n drain C18 Input high voltage Vpp 3 3 V to 3 6 V 0 7Vpp VDD V C19 Input low voltage Vpp 3 3 V to 3 6 V 0 0 3Vpp C21 Output leakage current lio Output Hi Z 5 uA Vin 3 6V C22 Pullup resistance Rig Vin 0 0 V 10 30 90 kQ P01 P02 P14 P21 P41 42 1 0 pins with TTL input level Schmidt trigger and N channel open drain C23 Input high voltage Vpp 3 3 V 2 2 C24 Input low voltage Vpp 3 3 V 0 0 6 C25 Output low voltage VoL Io 4 mA 0 4 C26 Output leakage current Iro Output Hi Z 10 pA Vin 0 0 V to 5 25 V A D Converter Characteristics C27 Resolution RES 5 bits C28 Conversion time tap fosc 14 32 MHz 13 4 us C29 Analog input voltage VIA Vss Conversion relativity accuracy LE 2 LSB Panasonic Semiconductor Development Company MN101C46F LSI User Manual 9 Panasonic General Description Electrical Characteristics Table 1 6 Electrical Characteristics Continued Ta 20 to 70 C Vpp 3 3 V Vgg 0 V No Parameter Symbol Conditions Min Typ Max Unit Closed Caption Decoder Characteristics 8 These pins also function as port pins The characteristics below apply when the port function is disabled CVBS0 CVBS1 C31 Low c
248. n high impedance control 0 Push pull control 1 High impedance PLT37B Blue digital output push pull PLT37G Green digital output push pull PLT37R Red digital output push pull MN101C46F LSI User Manual Panasonic Semiconductor Development Company 158 Panasonic Analog Digital Converter Description 8 Analog Digital Converter 8 1 Description The MN101C46F contains an analog digital converter ADC pair with a 5 bit resolution It contains a sample hold circuit and can be programmed to switch among eight channels ADIN7 ADINO of analog input When the ADC is inactive you can reduce power consumption by turning the internal ladder resistors off 8 1 1 ADC Functions The table below shows the A D conversion functions Table 8 1 A D Conversion Functions A D input pins Eight Pin names ADIN7 ADINO Interrupt ADIRQ Resolution 5 bits Conversion time minimum 13 4 us when tap 1 12 us Power down function Internal ladder resistors can be turned on and off Panasonic Semiconductor Development Company 159 Panasonic MN101C46F LSI User Manual Analog Digital Converter ADC Block Diagram 8 2 ADC Block Diagram ANCTR1 ANCTRO ANCTR2 0 ANCHSO 9 ANCHS1
249. n the A D con version end interrupt is generated Table 8 6 Starting A D Conversion ANST Starting A D Conversion 0 Start A D conversion or conversion underway 1 Stop A D conversion or conversion halted MN101C46F LSI User Manual Panasonic Semiconductor Development Company 164 Panasonic Analog Digital Converter Analog to Digital Conversion Operation 8 3 2 Setup Example of A D Conversion 8 3 2 1 Operating the ADC with Register Settings You can start A D conversion with register settings In the following example of setup procedures the analog input pin is ADINO the conversion clock is 4 and the sample hold time is tap x 6 Conversion ends with an interrupt Table 8 7 ADC Setup Procedures Procedure Description 1 Set up analog input pins POMD 03 28 bit POMD0 1 POPLU x0 3F40 bit 0O POPLUO 0 1 Use the port input mode register to set the analog input pins to be set in step 2 as spe cial function pins Use the port pullup pull down resistor control register to set up pins without pullup or pulldown resistors 2 Select analog input pin ANCTRI x 03FB1 bits 2 0 ANCHS 2 0 000 2 Select the analog input pins from among ADINT 0 using the ANCHS 2 0 field of A D control register 1 ANCTRI ANCTRO x 03FB0 bits 5 4 ANCK 1 0 01 3 Select the A D conversion clock 3 Select the A D conversion clock with
250. nasonic Semiconductor Development Company 64 Panasonic Interrupts Interrupt Control Registers RMCICR Remote Control Interrupt Control Register x 03FFB Bit P 6 5 4 3 2 1 0 RMC RMC LVO RMCIE RMCIR Reset 0 0 0 0 0 0 0 0 RW RW RW R R R R RW RW The remote control interrupt control register RMCICR is the register that controls interrupt levels interrupt enables and interrupt requests for remote control interrupts Use interrupt control registers with the maskable interrupt enable flag MIE of the PSW at 0 RMCLV 1 0 Interrupt level specification flag A 2 bit flag that sets the interrupt level Determines which of the CPU s levels 0 3 is assigned to the interrupt RMCIE Interrupt enable flag 0 Disable interrupt 1 Enable interrupt RMCDIR Interrupt request flag 0 No interrupt request 1 Generate interrupt request Panasonic Semiconductor Development Company MN101C46F LSI User Manual 65 Panasonic Ports Description 4 Ports 4 1 Description The MN101C46F contains 35 pins that form general purpose I O ports Ports 0 1 2 and 3 are 8 bit ports and port 4 is a 3 bit port All of these pins have alternate functions Table 4 1 I O Port Pins Port Associated Pins Port 0 07 00 Port 1 P17 P10 Port 2 27 20 Port 3 P37 P30 Port 4 42 40 MN101C46F LSI User Manual Panasonic Semiconductor Development Company
251. nasonic Way Secaucus New Jersey 07094 U S A Tel 1 201 348 5257 1 201 392 4652 Chicago Office 1707 N Randall Road Elgin Illinois 60123 7847 U S A Tel 1 847 468 5720 1 847 468 5725 Milpitas Office 1600 McCandless Drive Milpitas California 95035 U S A Tel 1 408 942 2912 1 408 946 9063 Atlanta Office 1225 Northbrook Parkway Suite 1 151 Suwanee GA 30024 U S A Tel 1 770 338 6953 1 770 338 6849 San Diego Office 9444 Balboa Avenue Suite 185 San Diego California 92123 U S A Tel 1 619 503 2903 1 858 715 5545 e Canada Sales Office Panasonic Canada Inc PCI 5770 Ambler Drive 27 Mississauga Ontario LAW 2T3 CANADA Tel 1 905 238 2101 1 905 238 2414 E LATIN AMERICA e Mexico Sales Office Panasonic de Mexico S A de C V PANAMEX Amores 1120 Col Del Valle Delegacion Benito Juarez C P 03100 Mexico D F MEXICO Tel 52 5 488 1000 Fax 52 5 488 1073 Guadalajara Office SUCURSAL GUADALAJARA Av Lazaro Cardenas 2305 Local G 102 Plaza Comercial Abastos Col Las Torres Guadalajara Jal 44920 MEXICO Tel 52 3 671 1205 OG Brazil Sales Office Panasonic do Brasil Ltda PANABRAS Caixa Postal 1641 Sao Jose dos Campos Estado de Sao Paulo Tel 55 12 335 9000 55 12 331 3789 B EUROPE U K Sales Office Panasonic Industrial Europe Ltd PIEL Willoughby Road Bracknell Berks RG12 8FP THE UNITED KINGDOM Tel 44 1344 85 3671 44 1344 85 3853 Ge Ger
252. nd Reset Input Voltage Design in sufficient time after the supply voltage powers up for the microcon troller to recognize the reset pin voltage as a reset signal Supply voltage Reset pin at low level input voltage or lower Time required to recognize as reset Figure 1 16 Power and Reset Input Voltage Panasonic Semiconductor Development Company MN101C46F LSI User Manual 17 Panasonic General Description Circuit Design Considerations 1 6 4 Power Circuit 1 6 4 1 Design Considerations for the Power Circuit MOS logic devices such as microcontrollers use fast large scale integration designs so use a power circuit that provides a sufficient margin Consider a power system like that shown in Figure 1 18 making sure you first evaluate AC line noise and check the ripple when driving LEDs and the like Vpp Figure 1 17 Design Considerations for the Power Circuit 1 6 4 2 Sample Power Circuit Emitter Follower Type Place noise eliminating capacitors as close to the microcontroller supply pins as possible Vpp Microcontroller Vss For eliminating noise Figure 1 18 Sample Power Circuit Emitter Follower Type MN101C46F LSI User Manual Panasonic Semiconductor Development Company 18 Panasonic Basic CPU Functions Description 2 Basic CPU Functions 2 1 Description The MN101C series of microcontrollers are designed with a flexible optimized hardware architecture for embedded applications in
253. nd low You can modify these current sources using external resistors R1 and R2 Within the clamping circuit you can turn each of the current sources on and off in steps The control bits for these currents are the same for sync tip and pedestal clamping but the reference and compare levels are different Table 10 3 provides these values for the two types of clamping and table 10 4 shows how to control the three current levels so that the video signal matches the reference level Table 10 3 Clamping Reference and Compare Levels Reference Level Compare Level Clamping Type CCD0 CCD1 CCD0 CCD1 Sync tip 16 dec 16 dec Output from minimum detection circuit Output from minimum detection circuit clamping value in SYNCMIN x 03E48 value in SYNCMIN x 03E68 Pedestal Value in PCLV Value in PCLV Value in BPLV x 03E49 Value BPLV 03 69 clamping x 03E4D x 03E6D MN101C46F LSI User Manual Panasonic Semiconductor Development Company 176 Panasonic Closed Caption Decoder Functional Description Table 10 4 Current Level Control Current Source Control Low Current Medium Current High Current Conditions 1 2 3 4 5 6 10 lt Off On Off On Off On 4 lt lt 9 Off On Off On Off Off 1 lt A lt 3 Off On Off Off Off Off 0 Off Off Off Off Off Off 3 lt lt 1 Off Off Off Off Off 9 lt lt 4 Off On Off Off Off
254. ne 1 are accepted as nested interrupts if IL IM If IL IM they are not accepted 2 Ifinterrupt 2 which occurs during interrupt service routine 1 is not accepted because IL 21M it is accepted when interrupt service routine 1 ends 3 Operations in parentheses are performed by hardware Figure 3 6 Processing Sequence for Maskable Interrupts Panasonic Semiconductor Development Company MN101C46F LSI User Manual 55 Panasonic Interrupts Operation 3 4 8 Nested Interrupts Once an interrupt is received the MN101C46F automatically disables acceptance of interrupts with lower levels When an interrupt is received its xxxLV 1 0 is copied to the processor status word s IM 1 0 Thus after interrupt is received interrupts with levels lower than that of the received interrupt are automatically disabled but interrupts with levels higher than the received interrupt are accepted as nested interrupts In general priority is assigned by levels even during interrupt handling however you can still control nested interrupts through the following procedures 1 disable nested interrupts do either of the following Clear MIE in the PSW to 0 Rewrite IM 1 0 in the PSW to raise the mask level 2 enable interrupts with levels lower than the received interrupt Rewrite IM 1 0 in the PSW to lower the mask level Interrupt nesting can only be enabled for those interrupts whose level is higher than the inter
255. nking Setup Examples 7 10 4 Controlling Line Shuttering It is possible to cancel shuttering of individual lines on the text and graphics layers so that they will be displayed on both shuttered and non shuttered regions To disable shuttering on the next line Set the SHT bit bit 10 of HP in the RAM data to 1 To disable shuttering on the first line Set the ISHT bit of the IHPH register x 03ECB to 1 Figure 7 22 shows a setup example for the text layer Line 1 ISHT 1 an ABCDEFG DRUG Line 2 SHT 0 EFG Line 3 SHT 0 d Line 4 SHT 1 ABCDEFG b P Television screen Figure 7 22 Line Shuttering Setup Example Panasonic Semiconductor Development Company MN101C46F LSI User Manual 143 Panasonic On Screen Display Field Detection Circuit 7 11 Field Detection Circuit 7 11 1 Block Diagram HSYNC Database Siete Divide y R Upper4bits 4 R by3 7 bit counter x 003EBE EVOD FREG 13 10 VSYNC De Y leading p LOADN1 4 edge detection D FF x 4 N1 RI Y x 003EBE EVOD FREG 23 20 y D FF x 4 N2 4 4 4 N2CNT N1CNT Vertical display Y Y controller EOMON gt Comparator EOSEL OS FRMON Figure 7 23
256. nsmitted The parallel data in this field is converted to serial data for transmission to the 2 bus It is shifted out MSB first to the interface I2CDRECH 12 Reception Data Register High x O3E83 I2CDREC 12 Reception Data Register x 03E82 Bit 7 6 5 4 3 2 1 0 z 6 5 4 3 2 1 0 MODEMODE stc trp aas LAB BB DT7 Dre prs DT3 DTI pro Reset 0 0 0 0 0 0 0 1 0 0 0 0 0 R W R R R R R R R R R R R R R R R R The I2CDRECH register contains the status bits for monitoring the device The IZCDREC register contains the reception data I2CDRECH and 12 are read only registers MODE 1 0 I C device mode This field indicates which PC mode the microcontroller is MODEI indicates slave or master and MODEO indicates receiver or transmitter If the microcontroller loses an arbitration or if a stop condition occurs the hardware clears MODE 1 0 to b 00 00 Slave receiver 10 Master receiver 01 Slave transmitter 11 Master transmitter MN101C46F LSI User Manual Panasonic Semiconductor Development Company 224 Panasonic I C Bus Controller Bus Interface Registers STS Stop condition at slave receiver Set to 1 when a stop condition is detected while the microcontroller is in slave receiver mode LRB Last received bit Stores the last serial data bit received LRB normally indicates the ACK cycle data AAS
257. nterrupt Flags 3 5 Setting the Interrupt Flags 3 5 1 Using Software to Rewrite Interrupt Request Flags Interrupt request flags are operated by hardware and are set to 1 when an interrupt source event occurs When the interrupt is accepted they are cleared to 0 To rewrite an interrupt request flag by software you must set the IRWE flag in the MEMCTR register 3 5 2 Setting the Interrupt Flags The table below shows how interrupt flags are set and describes the flags including changing interrupt request flags using software Procedure Description Disable all maskable interrupts Clear the MIE flag in the PSW to disable all maskable interrupts Be sure to do this if you are changing the interrupt control register Set up interrupt sources This procedure makes selections for interrupt sources such as choosing the interrupt edges chang ing the interrupt periods of timers and the like Write enable interrupt request flags This operation sets the IRWE flag of the memory control register MEMCTR and enables writes to interrupt request flags using software You only need to do this if you change the interrupt request flag with software Rewrite the interrupt request flags This operation rewrites interrupt request flags xxxIR in the interrupt control register xxxICR Write disable interrupt request flags This operation clears the IRWE flag and disables writing to the interrupt request flags using
258. ny 226 Panasonic Pulse Width Modulator 14 Bit Pulse Width Modulator 14 Pulse Width Modulator 14 1 14 Bit Pulse Width Modulator The MN101C46F has a 14 bit pulse width modulator PWM The PWM has a resolution of 14 bits a minimum pulse width of 2 f syscuk and a cycle of 2 BM 14 1 1 14 Bit PWM Description The following description assumes an internal oscillation frequency fsyscrk 3 58 MHz Figure 14 1 shows a block diagram of the 14 bit PWM Transfer the 14 bit waveform data written in 14 bit PWM data registers TDCHR and TDCLR to 14 bit PWM data latches TDCHL and TDCLL respectively by setting bit 11 in 14 bit PWM control register TDCC Since the clock divided by PWM is used as the clock for remote control PWM must be engaged when using the remote signal receiver DATA BUS 7 v PWM PWM control register TDCLR x 03E9E data register TDCHR x 03E9F TDCC x 03E9C 7 y7 lt v vt PWM TDCLL x 03E9E data latch TDCHL x 03E9F 7 gt 7 Pulse adder PWM output circuit gt gt X PWM A 7 gt PWM 14 bit counter fowm foysoux 2 Notes 1 Minimum pulse width 2 fsyscy k 0 56 us 2 Repeat cycle 2 71 5 us Figure 14 1 14 Bit PWM Block Diagram Panasonic Semiconductor Development Company MN101C46F LSI User Manual 227 Panasonic Pulse Width Modulator 14 Bit Pulse Width Modulator 14 1
259. o Digital Conversion Operation 8 3 3 Cautions on A D Conversion conversion is susceptible to noise so take preventative measures 6 3 3 1 Noise Prevention Place capacitors near the microcontroller s Vgg pins for the A D input analog input pins Vpp Vss Vss ADINQ D 4 Power to supply ADIN Place near Vss pin Figure 8 3 Recommended ADC Connection To ensure A D conversion precision observe the following precautions when using the ADC 1 Keep the input impedance R of the A D input pins to 500 or less and connect an external capacitor of between 1000 pF and 1 2 Keep the time constants R C in mind when setting the conversion interval 3 When running A D conversion A D precision cannot always be guaranteed if the output levels of the microcontroller are changed or peripheral added circuits are turned on and off since these actions cause fluctuations in analog input pins and current pins When evaluating a set check the waveform of the analog input pins Equivalent circuit block that outputs analog signal Microcontroller R NW input pin Da 777 1 Vss 1 uF gt gt 1000 but R lt 500 kQ Note Asterisked figures are reference values Figure 8 4 Recommended Circuit for ADC MN101C46F LSI User Manual Panasonic Semiconductor Development Company 166 Panasonic Analog Digital
260. ock external oscillation 8 Figure 2 5 Transitions between Operating Modes CPU KZ fosc m Divide by 2 t Divide by 2 System oscillation oscillation input Divide by 4 4 S 12 16MHz odo X Divide by 2 Slow oscillation Figure 2 6 Clock Switching Circuit MN101C46F LSI User Manual Panasonic Semiconductor Development Company 36 Panasonic Basic CPU Functions Standby Function The HALT States HALTO and HALT1 B Inthe HALT states the CPU is halted but the oscillator continues to run You can return immediately to the operating state with an interrupt In HALTO both the fast and slow oscillators run An interrupt returns operation to NORMAL mode The STOP States STOPO and 5 1 In these states both the CPU and the oscillators stop Use an interrupt to restart the oscillators and then return to operating mode after oscillation has stabilized From STOPO an interrupt returns operation to NORMAL mode From STOPI an interrupt returns operation to SLOW mode Slow Operation SLOW In this mode programs run at the slow operating clock This reduces power con sumption idling IDLE Idling is used to make the program wait for the fast operating clock to stabilize when going between SLOW mode and NORMAL mode Pay particular attention when reducing power supply by invoking STOP or HALT mode that the current flowing to or from pins and input pin levels are not unstable For
261. of the 8 Bit Timers 6 2 2 Example of 8 Bit Timer Operation Setup Timer operation timers 2 3 and 4 In the following example a clock function is implemented by using timer 0 to generate interrupts at set intervals fg 4 is used as the clock source fosc 20 MHz and interrupts are generated at every 250 divisions 100 us The pro cedures are described below Table 6 3 Procedure for Setting up an 8 Bit Timer Procedure Description 1 Check that counter is stopped TM2MD x 03F5C bit 3 TMOEN 0 1 Set the TM2EN flag of the timer 2 mode register TM2MD to 0 to stop the count 2 Select count clock source TM2MD x 03F5C bits 1 0 TM2CK 1 0 01 Use the TM2CK 1 0 flag of the TM2MD register to select prescalar output as the clock source 3 Select prescalar output and enable it CK2MD x 03F5E bits 2 1 TMOPSC 1 0 01 bit O TMOBAS 1 PSCMD x 03F6F bit O PSCEN 1 Use the TM2PSC 1 0 field and the TM2BAS flag of the timer 2 prescalar select register CK2MD to select fs 4 as the prescalar output Also set the PSCEN flag in the prescalar control register PSCMD to to enable the prescalar count 4 Set period for generating interrupts TM20C x 03F5A x F9 Set a value for the interrupt generation period in the timer 2 compare register TM2OC Since we are using 250 divi sions set to 249 x F9 The timer 2 binary counter TM2BC will be initialized to
262. olor background control 0 Don toutput 1 Output Panasonic Semiconductor Development Company MN101C46F LSI User Manual 149 Panasonic On Screen Display OSD Registers Bit Reset R W OSD3 OSD Register 3 0 Bit T 6 5 4 3 2 1 0 EONL BFLD UNDF CAPM Reset 0 0 0 0 0 0 0 0 R W RW RW RW RW RW BLINK Character blinking control Controls blinking for characters with BLINK set in the COL code 0 Don t blink 1 Blink CANH Vertical alignment control for closed captions Active when interlacing is selected 0 Normal position 1 Add 1 to V position of even fields EONL and BFLD Closed caption scrolling control Use when required for smoother scrolling 00 Normal display 01 Fix to font of odd field during scrolling 10 Fix to font of even field during scrolling 11 Normal display UNDF Underline blinking control 0 Don t blink 1 Blink CAPM Closed caption mode setting 0 Normal display mode 1 Closed caption mode VSHTOH Vertical Shutter 0 Register High x 03EC1 VSHTO Vertical Shutter 0 Register x O3ECO 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 VSP0 VSMO x d x EM Ew 27 P 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W RW RW RW RW RW RW RW RW RW RW RW RW RW VSONO Vertical shutter 0 on off 0 Off 1 On VSPO Vertical shutter 0 shuttering direction 0 Shutter below 1 Shu
263. ontrol 2 correc x 03FD0 DATE DATD DATC DATB DATA DAT DATS DAT7 DAT6 DATS DAT3 DAT2 DATI DATO tion data O3FEO TM4I TM3I 21 IRQ5I IRQ4I IRQ3I IRQ2I IRQII IRQOI NMIC x CR CR CR CR CR CR CR CR R Int 03FF0 RMC AD VBIV VBIV DC osp VBI0 i DOD gt OICR ICR ICR ICR ICR Panasonic Semiconductor Development Company MN101C46F LSI User Manual 33 Panasonic Basic CPU Functions Bus Interface 2 11 Bus Interface 2 11 1 Bus Controller The MNIOIC series limits the effects of bus line loads and speeds up operation by separating the buses to which internal memory and internal peripheral functions are connected Bus control uses four types of buses a ROM bus a RAM bus a peripheral expansion bus I O bus and an external expansion bus These buses are con nected respectively to internal ROM internal RAM internal peripheral functions and the external interface The functions of the bus controller include parallel instruction supply and data access handling slow devices when accessing external space and arbitrating bus usage when an external bus master device is connected A block diagram of the bus controller is shown below Instruction Interrupt queue Program address Operand address control Bus controller Interrupt bus Memory control register Memory mode setting bus access wait cont
264. ontrol register IRQ4ICR x 03FE6 R W External interrupt 4 control register IRQSICR x 03FE7 External interrupt 5 control register TM2ICR x 03FEB R W Timer 2 interrupt control register timer 2 compare match TM3ICR x 03FEC R W Timer 3 interrupt control register timer 3 compare match TM4ICR x 03FED R W Timer 4 interrupt control register timer 4 compare match VBIOICR x 03FF3 R W Closed caption decoder 0 interrupt control register VBILICR x 03FF4 Closed caption decoder 1 interrupt control register OSDICR x 03FF5 R W OSD interrupt control register I2CICR x 03FF6 R W PC interrupt control register VBIVOICR x 03FF7 Closed caption decoder 0 VSYNC VBIVO interrupt con trol register VBIVIICR x 03FF8 Closed caption decoder 1 VSYNC VBIV 1 interrupt con trol register ADICR x 03FFA A D conversion interrupt control register RMCICR x 03FFB Remote control interrupt control register Setting the interrupt level specification flag xxxLVn to level 3 disables that vec tor s interrupts regardless of the interrupt enable flag and interrupt request flag Panasonic Semiconductor Development Company 59 Panasonic MN101C46F LSI User Manual Interrupts Interrupt Control Registers NMICR Nonmaskable Interrupt Control Register x OSEF1 Bit 6 5 4 2 1 0
265. operation sequence in each of these modes In all modes the C bus controller generates an interrupt after each data byte transfer The software then loads the next data byte Interrupt Interrupt Interrup MN102H51K RW 0 h Address Master wi PW Data 8 bits Data 8 bits P Slave ACK ACK ACK Z Normally ACK 0 A Master Transmitter ACK 1 signals transfer end to slave transmitter Interrupt Interrupt Interrupt MN102H51K R W 1 Address CMaster Sue u ACK ack P Slave Data 8 bits Data 8 bits B Master Receiver RW 1 X Ack 0 Ack 1 Address Master s 7 bits R W ACK ACK P Clave gt ACK Data 8 bits Data 8 bits MN102H51K T M Interrupt Interrupt Interrupt When the microcontroller is addressed ACK 1 signals transfer it outputs ACK 0 and sets the AAS bit end to slave transmitter of the IPCDREC register to 1 C Slave Transmitter R W 0 Master s Address pyw Data 8 bits Data 8 bits P 7 bits Clave gt MN102H51K T T Interrupt Interrupt Interrupt When the microcontroller is addressed it outputs ACK 0 and sets the AAS bit Interrupt of the I2CDREC register to 1 STS sets to 1 D Slave Receiver Figure 13 3 lC Bus Interface Operation Panasonic Semiconductor Development Company MN101C46F
266. or The appendices provide register and instruction maps instruction sets and describe the flash EEPROM version Text Conventions Where applicable this manual provides special notes and warnings Helpful or supplementary comments appear in the sidebar In addition the following symbols indicate key information and warnings Key information These notes summarize key points relating to an operation Warning 1 Please read follow these instructions to prevent damage reduced performance Register Conventions This manual presents 8 bit registers in the following format REGISTER 8 Bit Register Name 00000 Bit 7 6 5 4 3 2 1 0 Bit Bit Bit Bit Bit m Name Name Name Name Name Reset 0 0 0 0 0 0 0 0 R W R R R R W R W R W R W R W The hexadecimal value 00000 indicates the register address The top row of the register diagram holds the bit numbers Bit 7 is the most significant bit MSB The second row holds the bit or field names A dash indicates a reserved bit The third row shows the reset values and the fourth row shows the accessibility R read only W write only and R W readable writable Panasonic Semiconductor Development Company MN101C46F LSI User Manual xii Panasonic About This Manual Related Documents Related Documents MN101C Series LSI User Manual Describes the device architecture MN101C Series Instruction Manual De
267. or selecting the fosc 16 output by prescalar 0 as the count clock for timer 2 Table 5 7 Procedures for Setting up a Count Clock for Timer 2 Procedure Description 1 Select prescalar output 1 Selects fosc 16 as the prescalar output CK2MD x 03F5D using TM2PSC 1 0 and TM2BAS in the Bits 2 1 TM2PSC 1 0 01 timer 2 prescalar select register CK2MD Bit O TM2BAS 0 2 Enable prescalar output 2 Enables prescalar counting by setting the PSCMD x 03F6F PSCEN flag in the prescalar control register Bit O PSCEN 1 PSCMD to 1 Enable prescalar counting by setting the PSCEN flag in the prescalar control register PSCMD The prescalar starts counting when it is enabled Start the timer counting after the prescalar is set up You must also select the prescalar output at the timer using the timer mode register Panasonic Semiconductor Development Company MN101C46F LSI User Manual 97 Panasonic 8 Bit Timers Introduction to the 8 Bit Timers 6 8 Bit Timers 6 1 Introduction to the 8 Bit Timers The MN101C46F has three 8 bit timers timers 2 3 and 4 Timers 2 and 3 can be cascaded and used as a 16 bit timer You cannot cascade timer 4 You can select divided clocks based on fosc and fs for the clock sources of the timers by using the output of the prescalars An IR remote signal receiver output circuit is built in 6 1 1 8 Bit Timer Function The table below describes the functions that can use these
268. osed Caption Decoder Closed Caption Decoder Registers STPN Status of clamping control pulse signal during STOP COMPSY Composite sync signal status VSEP VSYNC signal status HSEP HSYNC signal status HLOCK Sync detection 0 Asynchronous 1 Synchronous Clamping Control Signal Status Register 1 High x 03E5D CLPCND1WH Clamping Control Signal Status Register 1 High x 03E7D CLPCND1 Clamping Control Signal Status Register 1 x 03E5C CLPCND1W Clamping Control Signal Status Register 1 x 03E7C Bit 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 XPED XPE PED PE UP DOWN UP DOWN SAFP SAFN CLPP CLPN Reset 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 R W R R R R R R R R R R R R R R W R W RW These registers are for monitoring the status of the clamping current source switch shown in figure 10 5 on page 176 An N channel transistor is on when the associated bit PEDOWN XPEDOWN CLPN or SAFEN is 1 A P channel transistor is on when the associated bit PEDUP XPEDUP CLPP or SAFEP is 0 SAFP Clamping control pulse for large high current source P channel SAFN Clamping control pulse for large high current source N channel CLPP Clamping control pulse for small high current source P channel CLPN Clamping control pulse for small high current source N channel XPEDUP Clamping control pulse for medium current source
269. ow for at least four cycles of the slow clock fy NRST pin 4 oscillation clocks 2 2 us at 1 79 MHz Figure 2 8 Minimum Reset Pulse Width You can also invoke the reset mode through programming a software reset by outputting low to pin P36 NRST by setting the PSOUTS flag in the P3OUT register to 0 When a reset within the MN101CAGF initializes the registers the PSOUTS flag is set to 1 and the reset is cleared See section 4 3 I O Port Control Registers on page 85 clock The MN101C46F starts up in SLOW mode if a slow oscillation is used as the base 2 14 1 2Operation Sequence During Resets 1 When the reset pin changes from L to H the internal 14 bit counter also used as the watchdog timer starts counting the system clocks The length of time required from the start of counting to overflow is called the oscillation stabilization wait Internal registers and special registers are initialized during the reset period Internal resets are cleared when the oscillation stabilization wait ends and program execution begins for the address written in the vector table at address x 04000 Panasonic Semiconductor Development Company MN101C46F LSI User Manual 43 Panasonic Basic CPU Functions Resets VDD NRST 1 Oscillator Stabilization wait Internal RST Figure 2 9 Reset Clearing Sequence 2 14 2 Oscillation Stab
270. ow to use these bits Table 7 2 Power Saving Control Bits for the OSD Bit Name Register Address Bit Description Reset OSDPOFF PCNT0 x 03F4A 7 0 System clock off to OSD 0 1 System clock on to OSD OSDREGE PCNT2 x 03F4E 2 0 R W disabled for OSD registers 0 1 R W enabled for OSD registers Using OSDPOFF to control the system clock supply to the OSD The OSDPOFF bit enables or disables the system clock supply to the OSD block When the OSD is unused setting this bit to 0 stops the clock supply to the OSD reducing power dissipation Setting OSDPOFF to 0 not only disables the OSD display it disables reads from and writes to the OSD registers To operate the OSD set this bit to 1 then set up the OSD registers Using OSDREGE to control read write access to the OSD registers The OSDREGE bit enables or disables read write operations to the OSD reg isters See section 7 12 OSD Registers on page 146 Once you have set the OSD registers you can write a O to this bit to disable furthers reads and writes to them reducing power dissipation This bit resets to 0 Note that when OSDPOFF is 0 you cannot set the OSD registers even if OSDREGE is 1 Table 7 3 shows the combinations of OSDPOFF and OSDREGE settings Note also that when OSDREGE is 0 the OSD display runs but the shutter cannot be moved If your application requires shutter movement you must enable OSDREGE Table 7 3 O
271. pedance control 0 Push pull control 1 High impedance WBSHDRH ROUT pin high impedance control 0 Push pull control 1 High impedance WBSHDB Blue digital output push pull WBSHDG Green digital output push pull WBSHDR Red digital output push pull MN101C46F LSI User Manual Panasonic Semiconductor Development Company 154 Panasonic On Screen Display OSD Registers PLT00 07 Palette 0 Colors 0 7 Register 0 0 0 7 7 6 2 4 3 2 1 0 PLT00 PLT00 PLT00 PLT00 PLT00 PLT00 PLT00 PLT00 YM YS BH GH RH B G R Reset 0 0 0 0 0 0 0 0 R W RW RW RW RW RW RW RW Color 0 of palette 0 PLT00YM YM output PLTOOYS YS output PLTOOBH BOUT pin high impedance control 0 Push pull control 1 High impedance PLTOOGH GOUT pin high impedance control 0 Push pull control 1 High impedance PLTOORH ROUT pin high impedance control 0 Push pull control 1 High impedance PLTOOB Blue digital output push pull PLT00G Green digital output push pull PLTOOR Red digital output push pull Bit 7 6 5 4 3 2 1 0 PLTO7 PLTO7 PLTO7 PLTO7 PLTO7 PLTO7 PLTO7 PLTO7 YM YS BH GH RH B G R Reset 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW Color 7 of palette 0 PLTO7YM YM output PLTO7YS YS output PLTO7BH BOUT pin high impedance control 0 Push pull control 1 High impedance PLTO7GH GOUT pin high impe
272. phic Tile Codes ROMEND Required bytes per tile 4 colors 8 colors N x 4 8 1 Nisa Nx2 1 multiple of 3 04 m 06 ees s 05 EEEE 03 poc 04 Ll din 02 p 03 p S s S P 02 Wade dm eie tsa a mmm a 01 gt 01 LO a 108 bytes 72 bytes 00 4224 00 72 bytes 108 bytes See fig 7 9 See fig 7 8 Figure 7 7 Graphics ROM in the Two Color Modes MN101C46F LSI User Manual 124 Panasonic Panasonic Semiconductor Development Company On Screen Display ROM ROMEND 6B Line 1 data ROMEND 65 fine zdat Graphics tile r 16 bits T d Line 1 ROMEND 60 a 8 color mode Sheet Line 2 ROMEND 5F Line 3 data Line 3 ROMEND 5A Sheet 2 ROMEND 59 Sheet gt 2 8 ROMEND 5 Sheet 1 bits 7 to 0 NA 12 ROMEND 4 Sheet 1 bits 15 to 8 Ends LE insta ROMEND 1C 8 ROMEND 3 Sheet 2 bits 7 to 0 dicun Line 17 data i ROMEND 2 Sheet 2 bits 15 to 8 ROMEND 08 7 7 ROMEND 1 Sheet 3bits 7100 P un i Line 18 data 6 bytes pomenn Sheet 3bits 1518 1 byte it it Figure 7 8 Graphics ROM Organization in 8 Color Mode 16W x 18H Tiles ROMEND 47 ROMEND 44 ROMEND 43 R
273. previous HSYNC t Gap between VSYNC leading edge and 0 4 Tysync 0 4 leading edge of following HSYNC ty VSYNC pulse width 4 0 ty HSYNC pulse width 4 0 Tusync 4 0 Panasonic Semiconductor Development Company MN101C46F LSI User Manual 13 Panasonic General Description Circuit Design Considerations 1 6 Circuit Design Considerations 1 6 1 Considerations when Using the IC 1 6 1 1 Connecting the Vpp and Vss Pins Directly connect all Vpp and Vss pins separately to an external power source and GND Thoroughly double check the pin positions of the IC package and install it on a PCB The figures below show examples of correct and incorrect connection techniques Incorrect connection runs the risk of damaging the device by melting the metallization with large currents Output Input Figure 1 9 Correct Connection Technique for the Vpp and Vss Pins Output Input High current Figure 1 10 Incorrect Connection Technique for the Vpp and Vss Pins 1 6 1 2 Operation Considerations 1 Toensure that operation is correct shield the surface of the package if you are using it where it will be subject to strong electrical fields such as under a CRT MN101C46F LSI User Manual Panasonic Semiconductor Development Company 14 Panasonic General Description Circuit Design Considerations 2 Double check the operating temperatures before use Different products have different operating temperature ranges If for example you a
274. pt ADIRQ Figure 8 2 The A D Conversion Operation To read A D conversion values either run multiple A D conversions and check that levels match in the program or find average values and remove noise MN101C46F LSI User Manual Panasonic Semiconductor Development Company 162 Panasonic Analog Digital Converter Analog to Digital Conversion Operation 6 3 1 Setting Up A D Conversion 6 3 1 1 Setting up the A D Conversion Input Pins Select the pins to be used for A D conversion input using the ANCHS 2 0 flag of ANCTRI Table 8 2 Setting up the A D Conversion Input Pins ANCHS2 ANCHS1 ANCHSO A D Pin 0 0 0 ADINO pin 1 ADINI pin 1 0 ADIN2 pin 1 ADING pin 1 0 0 ADIN4 pin 1 ADINS pin 1 0 ADIN6 pin 1 pin 6 3 1 2 Setting up the A D Conversion Clock Set up the A D conversion clock with the ANCK 1 0 field of the ANCTRI register Set the field so the A D conversion clock tap does not fall below 800 ns The table below illustrates the relationship between the machine clocks fosc fs and fx and the A D conversion clock tap Calculated with fs fosc 2 and fy 2 Table 8 3 A D Conversion Clocks and Cycles A D Conversion Cycles tap A D Conversion ANCK1 ANCKO Clock fosc 7 16 MHz fx 1 79 MHz 0 0 fs 2 559 ns not settable 2 24 us 1 fg 4 1 12 us 4 48 us 1 0 fs 8 2 24 us 8 96 us 1 fxx2 Reserved Reserved See se
275. pt Service Routine 1 172 10 1 Pins Used for CCDO and o IPSI ERO NEG EG RERUM EIS 174 10 2 Caption decoder register setting 176 10 3 Clamping Reference and Compare Levels 176 10 4 Current Level Control s pene a cota Woh ose Et EAS Se eT eR us 177 10 5 Control Registers for Clamping Circuit 2 0 2 0 ec ccc eee eens 177 10 6 Control Registers for Sync Separator 1 179 10 7 Control Registers for Data 5 04 181 10 8 Control Registers for Controller and Sampling 182 10 9 Closed Caption Decoder 183 10 10 Sampling Frequency Control Register 198 11 1 Logic Level Conditions for Data 1 203 11 2 Long and Short Data 1 0 4 203 11 3 Leader Detection 0 1 2 204 11 4 IR Remote Signal Receiver
276. pt request flags xxxIR of the external interrupt control register IRQnICR and internal interrupt control register xxxICR corresponding to the interrupt source are set to 1 2 Ifthe interrupt enable flag xxxIE for that interrupt request flag is 1 an interrupt request signal is output to the CPU 3 The interrupt request signal is the interrupt level information set for the indi vidual interrupt The level set in the interrupt level flag xxxLV 1 0 is out put to the CPU 4 Ifthe level of the interrupt request of the output interrupt request signal is higher than the level set in the interrupt mask level field IM 1 0 of the PSW and the PSW s interrupt enable flag MIE is 1 enabled the interrupt is accepted 5 After the interrupt is accepted the interrupt request flag xxxIR is cleared Panasonic Semiconductor Development Company MN101C46F LSI User Manual 51 Panasonic Interrupts Operation The interrupt enable flag xxxIE is not cleared after the interrupt is accepted The MIE in the PSW is not cleared to 0 when an interrupt is accepted Current interrupt mask level IM Y PSW VF NF OF ZF Level detection Interrupts serviced if IL lt IM __ xxxICR xxx E xxxIR Level of interrupt that occurred IL Figure 3 4 Interrupt Acceptance Process The mask interrupt enable flag MIE is set to 0 in the following cases disabling
277. ption detection 0 Norequest Request EDGED Interrupt request on RMIN pin edge detection 0 Norequest Request Panasonic Semiconductor Development Company MN101C46F LSI User Manual 207 Panasonic IR Remote Signal Receiver IR Remote Signal Receiver Control Registers RMLD Remote Signal Leader Value Set Register Bit F 6 5 4 3 2 1 0 SP LD3 LD2 LD1 LDO Reset 0 0 0 0 0 1 1 0 R W R W R R R R W R W R W R W RML D is an 8 bit access register SP Noise filter sampling cycle 0 PWMS 17 9 us fpwms fsyscik 29 1 PWM7 71 5 us fpwM7 Do not set the leader value too LD 3 0 HEAMA qata leader value small Leader detection and data Set the four MSBs of the 6 bit leader value for HEAMA data in LD 3 0 detecti simulta M AE C ES This 4 bit setting must be between 0 and 63 Ts cycles The default value is neously x 6 The two LSBs of the leader are always 0 RMCS Remote Signal Clock Status Register X O3EA6 Bit 7 6 5 4 3 2 1 0 LONG SHORT DF DF TSCNT5 TSCNT4 TSCNT3 TSCNT2 TSCNTI TSCNTO Reset 0 0 0 0 0 0 0 0 R W R W R W R R R R R R RMCS indicates the result of the short long data detection It is an 8 bit access register LONGDF Long data format detection Set to 1 when long data is detected SHORTDF Short data fo
278. rations shift operations and relative indirect register addressing Internal ROM These memory blocks contain the program data and stack areas RAM Address registers The address registers store the memory addresses that will be accessed during data transfers In relative indirect register addressing mode they store the base address Data registers These registers store data used for operation You can link two 8 bit data registers and use them as a 16 bit register Interrupt controller This block detects interrupt requests from peripheral function blocks and requests that the CPU service the interrupt Bus controller This block controls the connection between the CPU s internal and exter nal buses It also contains a bus arbitration function Internal peripheral functions MNIOIC series devices contain a wide range of internal peripheral devices such as timers and ADCs MN101C46F LSI User Manual Panasonic Semiconductor Development Company 22 Panasonic Basic CPU Functions CPU Control Registers 2 4 CPU Control Registers The MN101C46F uses memory mapped I Os The registers of its peripheral circuits are placed in memory space x 03D00 x 03FFF The CPU s control registers are also mapped to this memory space Table 2 3 CPU Control Registers Address Register R W Description x 03F00 CPUM R W CPU mode control register x 03F0
279. re generated at intervals that are preset using the clock source selection and the compare register TMnOC setting When the binary counter TMnBC matches the compare register setting an interrupt request is generated at the next count clock the binary counter is cleared and up counting begins again from x 00 Select from among the following clock sources for different timers Table 6 2 Clock Sources with Timers Running Timers 2 3 and 4 Timer 2 Timer 3 Timer 4 Clock Source Count Period 8 Bits 8 Bits 8 Bits fosc 125 ns fosc 4 500 ns Y Y Y fosc 16 2 Y fosc 32 4 us fosc 64 8 us Y Y Y fosc 128 16 us Y fs 2 500 ns V fs 4 lus 4 fs 8 2 us fx 500 ns fosc 8 MHz fx 2 MHz f fosc 2 4 MHz Count timing for timer operation timers 2 3 and 4 The binary counter counts up using the selected clock source as the count clock The operation shown below is the basic sequence for all 8 bit timers Count clock TMnEN flag Compare register t Ds counter A B C E Interrupt request flag Figure 6 3 Count Timing for Timer Operation Timers 2 3 and 4 MN101C46F LSI User Manual Panasonic Semiconductor Development Company 100 Panasonic 8 Bit Timers Operation of the 8 Bit Timers a When a value is written to a compare register while the TMnEN flag indicate
280. re using a prod uct guaranteed for 70 C at temperatures higher than this it may malfunc tion because it has no operating margin 3 Double check the operating voltages before use Different products have dif ferent operating voltage ranges Panasonic cannot guarantee reliability at voltages higher than the guar anteed voltage Service life of transistors for example may vary with age Using a product at a voltage below the guaranteed voltage may cause malfunction since there is no operating margin 1 6 2 Handling Unused Pins 1 6 2 1 Handling Unused Functions If you are not using a function set it so its operation is halted 1 6 2 2 Handling Unused Pins Dedicated Output Pins Leave any unused pins that are dedicated for output open Output Figure 1 11 Handling Unused Pins Dedicated for Output 1 6 2 3 Handling Unused Pins Dedicated Input Pins Pull unused pins that are dedicated for input either up or down by inserting a resistor of at least 10 If an unstable input causes both the P channel and N channel transistors of the input inverter to engage a through current will flow into the input circuit causing an increase in current consumption or noise in the chip s internal power supply Several Input pin Joko pul 4 Input p Severa 10 Input pin Figure 1 12 Handling Unused Pins Dedicated for Input Panasonic Semiconductor Development Company MN101C46F LSI User Manual 15 Panasonic
281. rmat detection Set to 1 when short data is detected TSCNT 5 0 6 bit counter value RMSR Remote Signal Reception Data Shift Register 8 Bit 7 6 5 4 3 2 1 0 RMSR7 RMSR6 RMSR5 RMSR4 RMSR3 RMSR2 RMSRI RMSRO Reset 0 0 0 0 0 0 0 0 R W R R R R R R R R RMTR Remote Signal Reception Data Transfer Register x 03EAA Bit 7 6 5 4 3 2 1 0 RMTR7 RMTR6 RMTRS RMTR4 RMTR3 RMTR2 RMTRI RMTRO Reset 0 0 0 0 0 0 0 0 R W The microcontroller shifts received data into RMSR converting it to paral lel data After it shifts in 8 bits it loads the data byte to RMTR The CPU reads the data from RMTR The data shifts from LSB to MSB RMSR and RMTR are 8 bit access registers MN101C46F LSI User Manual Panasonic Semiconductor Development Company 208 Panasonic ROM Correction Description 12 ROM Correction 12 1 Description The ROM correction function can correct the program data in any address within the 96 kilobyte ROM It cannot correct OSD ROM data A maximum of sixteen addresses can be corrected Addresses are set as address match interrupts This function shortens time to market for large scale designs since changes can be implemented in the software after the mask ROM is complete The ROM correction function has numerous other applications For instance you can insert keywords into the functional routines then use the function to send internal status information to an external location This enable
282. rol Address decoding 1 Bus arbiter Peripheral RAM bus expansion bus b i zl Internal peripheral Internal RAM BR BG functions CSIC interface Internal ROM CSIC expansion bus A D Figure 2 4 Function Block Diagram of the Bus Controller The CSIC expansion bus accesses the OSD closed caption PWM and remote signal receiver registers Accesses of the CSIC expansion bus always have one wait and are set up in the memory control register MEMCTR You can set the number of waits for the peripheral expansion bus I O bus connected to the internal peripheral functions MN101C46F LSI User Manual Panasonic Semiconductor Development Company 34 Panasonic Basic CPU Functions Bus Interface 2 11 2 Control Registers Two registers control bus interface functions the memory control register MEMCTR and the expansion address control register EXADV MEMCTR Memory Control Register x 03F01 Bit 7 6 5 4 3 2 1 0 IOW1 IOWO IVBM EXMEM EXWH IRWE EXWI EXWO Reset 1 1 0 0 1 0 1 1 R W R W R W R W R W R W R W R W R W IOW 1 0 Set number of waits when accessing special register area 00 No waits 279 3 ns with 14 32 MHz bus cycle 01 Setting disabled 419 0 ns with 14 32 MHz bus cycle 10 Two waits 558 6 ns with 14 32 MHz bus cycle 11 Setting disabled 698 3 ns with 14 32 MHz bus cycle IVBM Sets base address for interrupt vector table
283. rs Ree OU ip RAD E e deg e abus val ee a 23 2 5 Organization of Instruction Execution 1 24 2 6 Pipeline Processing Uer eR REED Ue ale au Phu yqa asw 25 2 7 Address Registers a u may he ee ree vare re es 26 2 7 1 Program Counter PG s us PVT debited ERE PEN REN SES 26 2 7 2 Address Registers A0 erasa sua pupu ene nee 26 2 7 3 stack Pointer SP uyu ss duum SEU eT PIG S NU AL A TOR Y 26 2 8 Op rations Registers 2 us eoe ue de tea e deg e es 27 2 8 1 Data Registers 00 D1 D2 and D3 27 2 8 2 Processor Status Words ER RR xU TRU E UN 27 MNI101C46F LSI User Manual Panasonic Semiconductor Development Company Panasonic Contents 2 9 Addressing Modes uc n Beak 29 2 10 Memory Spaces sc see puse ecu eg eee Ua TO ee e IURE m MN ELM UN 31 2 10 1 Memory 5 esee y sk pu A een HERE Y reed y yes y RUE 31 2 10 2 Single CHP ModE l RR e UR IR RR cage alsa a Css 31 2 10 3 Special Function Registers secs e ese eve emer OE Tene a ve es 32 2 11 Bus Interface se eve ei ep aha etu a e ea e uera e ph eS 34 2 11 1 Bus Controller a E ML epe su 34 2 11 2 Control Registers a cre pre
284. rt 2 MN101C46F LSI User Manual Panasonic Semiconductor Development Company 76 Panasonic I O Ports I O Port Circuit Diagrams 0 Pullup off 1 Pullup on P2PUPn P2MDn e 0 P22 P23 1 CLL CLH RE 0 Port input 1 Port output P2DIRn 0 Port low output 1 Port high output Pin P2OUTn P2INn amp CLL CLH amp Note n 2 P22 n 3 P23 Figure 4 12 P22 CLL and P23 CLH Port 2 Panasonic Semiconductor Development Company 77 Panasonic MN101C46F LSI User Manual I O Ports 1 0 Port Circuit Diagrams 0 Pullup off 1 Pullup on amp 5 5 P2PUPn 0 24 27 1 VREFH1 VREFHO 0 Port input 1 Port output 5 5 P2DIRn 0 Port low output 1 Port high output Pin P2OUTn X P2INn lt Clerc VREFH1 VREFHO lt AAN Note n 4 P24 n 7 P27 Figure 4 13 P24 VREFH1 and P27 VREFHO Port 2 MN101C46F LSI User Manual Panasonic Semiconductor Development Company 78 Panasonic I O Ports I O Port Circuit Diagrams 0 Pullup off 1 Pullup on E P2PUPn i 0 P25 P26 1 CVBS1 CVBSO P2
285. rted 3 times By these commands transi tion to STOP HALT mode is always executed during NOP instructions and in programming the state of pipeline need not to be mind Invoking the HALT Mode Invoke HALTO from the NORMAL mode and HALT from the SLOW mode Only the CPU halts the oscillation state is maintained Return from HALT mode with an interrupt or reset A reset will cause an ordinary reset operation an interrupt will return to the mode prevailing before HALT was invoked If you invoke HALT mode with the watchdog timer enabled the watchdog timer will stop counting It will resume counting once you return to a CPU operating mode Program 4 MOV x 4 DO Invokes HALT mode MOV DO CPUM NOP Executes up to 3 instructions NOP depending on pipeline state NOP after writing to CPUM Invoking STOP Mode Invoke STOPO from NORMAL mode and STOP1 from SLOW mode Oscil lation and the CPU halt for both cases Return from STOPO and STOPI with interrupt or a reset Program 5 MOV x 8 DO Invokes STOP mode MOV DO CPUM NOP Executes up to 3 instructions NOP depending on pipeline state NOP after writing to CPUM Panasonic Semiconductor Development Company MN101C46F LSI User Manual 41 Panasonic Basic CPU Functions Setting the Clock Switch Register When switching clocks set the OSCDBL OSCSEL and OSC0 flags separately Even flags that are mapped to the same special register must be set
286. rupt mask level IM of the PSW You can accept an interrupt with priority below that of the interrupt currently being processed by forcibly re writing its IM but be sure the nested interrupts do not overflow the stack The operating sequence for nested interrupts is shown below Interrupt 1 xxxLV 1 0 10 Interrupt 2 xxxLV 1 0 00 Do not perform operations in the maskable interrupt control register xxxICR when interrupt nesting is enabled If you need to do an opera tion first clear the MIE flag of the PSW to disable interrupts MN101C46F LSI User Manual Panasonic Semiconductor Development Company 56 Panasonic Interrupts Operation Main program IM 1 0 b 11 Interrupt occurs 2 IL IM so accepted xxxLV 1 0 b 10 Interrupt 0 b 10 servicing cycle C Interrupt service routine 1 5 Interrupt occurs z IL lt IM so accepted xxxLV 1 0 b 00 Interrupt wit 0 0 servicing cycle C Interrupt service routine 2 Restart interrupt service routine 1 RTI M1 0 b 10 RTI iw1 0 611 Note Operations in parentheses are performed by hardware Figure 3 7 Processing Sequence for Nested Interrupts Panasonic Semiconductor Development Company MN101C46F LSI User Manual 57 Panasonic Interrupts Setting the Interrupt Flags Table 3 3 Setting I
287. rupts peripheral function interrupts The operation of normal interrupts other than the reset follows a sequence con sisting of an interrupt request acceptance of the interrupt and hardware pro cessing The hardware processing of interrupts consists of saving the program counter PC processor status word PSW and handy addressing information HA to the stack and jumping to the address specified by the vector After the interrupt service routine quits the saved data can be restored using an RTI instruction After an interrupt occurs jumping to the interrupt service routine takes a maximum of 12 machine cycles the return takes a maximum of 11 machine cycles Interrupt control registers set up for each interrupt are used to control the interrupt function Interrupt control registers each have an interrupt request flag IR and interrupt enable flag TE and an interrupt level flag field LV 1 0 The interrupt request flag IR is set to 1 when an event that is an interrupt source occurs It is cleared to O when the interrupt is accepted The interrupt request flag is hardware operated but it can also be written to using software The interrupt enable flag IE enables the specified interrupt The nonmaskable interrupt NMI has no interrupt enable flag if its interrupt request flag is set it is accepted unconditionally Maskable interrupts have interrupt enable flags The interrupt enable flags of maskable interrupts are valid if
288. s ROM in the Two Color 124 7 8 Graphics ROM Organization in 8 Color Mode 16W x 18H Tiles 125 7 9 Graphics ROM Organization in 4 Color Mode 16W x 18H Tiles 125 7 10 OSD Signal Output 21 128 7 11 Character Outlining Example 2 2 129 7 12 Character Shadowing 1 1 4 129 7 13 Box Shadowing Example asus ee pere bp eee o ehe ene eyes 130 7 14 Italicizing and Underlining 12 131 7 15 Graphic Size 22 132 7 16 Character Size Combinations zx oti ns as ae EU ED 133 7 17 DMA and Interrupt Timing for the 5 136 7 18 Shuttered Area Setup Examples 2 1 138 7 19 Shutter Movement Setup 22 1 140 7 20 Text Layer Shuttering Setup 1 142 7 21 Shutter Blanking Setup
289. s Register x 03EB0 Bit 7 6 5 4 3 2 1 0 15 14 AI3 12 All AIO A9 8 Reset 0 0 0 0 0 0 0 0 R W R W R W R W R W R W RW R W R W A 15 8 hold the programmable portion of the text ROM end address The 1 low order eight bits of the address always and the MSB is always b 1 The available address range is x 1_OOFF to x 1 BFFF with a pro ROM data will be displayed incor grammable range from x 00 to rectly if CROMEND is set to x CO A15 AB or higher 1 XXXX XXXX 1111 1111 Fixed Programmable Fixed 100FF 1 0000 000011111 1111 1BFFF 1 1111 1111 1111 1111 GROMEND Graphics ROM End Address Register x 03EB2 Bit 7 6 5 4 3 2 1 0 15 14 AI3 12 All AIO A9 8 Reset 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW A 15 8 hold the programmable portion of the graphics ROM end address 1 The low order eight bits of the address are always x FF and the MSB is always b 1 The available address range is x 1 OOFF to x 1 BFFF with ROM data will be displayed incor a programmable range from x 00 to x BF rectly if GROMEND is set to x CO A15 AB or higher 1 XXXX XXXX 1111 1111 1 Fixed Programmable Fixed i 1 100FF 1 10000 000011111 1111 1BFFF 1 1111 111141111 1111 RAMEND VRAM Address Register x 03EB4 Bit 7 6 5 4 3 2 1 0 All AIO A9
290. s a stop 0 the binary counter is cleared to 00 during that write cycle b The binary counters starts counting when the TMnEN flag indicates operation 1 Negative edges of the count clock are counted c When the binary counter matches the compare register value the inter rupt request flag is set at the next count clock the binary counter is cleared to x 00 and up counting begins again d Rewriting the compare register while the TMnEN flag indicates opera tion 1 does not change the binary counter e The binary counter stops running when the TMnEN flag indicates a stop 0 When the binary counter matches the compare register value the interrupt request e flag is set at the next count clock and the binary counter is cleared so observe the following relationship Compare register setting Clocks till interrupt request is generated 1 Setting a compare register value that is smaller than the binary counter value dur ing a count will cause the binary counter to count up till one end overflows When processing by means of interrupts clear the timer interrupt request flag prior to starting the timer The timing pattern when a timer n interrupt request is generated with a setting of TMnOC x 00 is the same as when the setting is x 01 Panasonic Semiconductor Development Company MN101C46F LSI User Manual 101 Panasonic 8 Bit Timers Operation
291. s system level examination of the internal status even with the mask ROM version To use the ROM correction function embed a routine such as that shown in figure 12 2 in the ROM I I I 1 ROM 9 is ROM correction required 1 Yes Necessary I RH ROM software settings 1 1 address c rrection Set up the correction data 1 1 I Instruction Instruction 3 counter fetch correction function I CPU E T pay PETENTE Figure 12 1 ROM Area Schematic Diagram Figure 12 2 ROM Correction Flow As figure 12 1 shows the function lies between the microcontroller and ROM blocks First set the correction data for any sixteen non OSD addresses in the ROM correction address match and data registers Follow the flow shown in figure 12 2 Once this is done the circuit will correct the ROM output for the designated addresses Panasonic Semiconductor Development Company MN101C46F LSI User Manual 209 Panasonic ROM Correction Block Diagram 12 2 Block Diagram Figure 12 3 is a block diagram of the ROM correction circuit A match detection circuit constantly monitors the ROM address specified by the CPU instruction pointer IP When the value matches a correction address the circuit replaces the data output from the ROM with the data in the appropriate correction data register It then sends the corrected data to the CPU Data bus
292. sable interrupt 1 Enable interrupt VB1IR Interrupt request flag 0 No interrupt request 1 Generate interrupt request VBIVOICR Closed Caption Decoder 0 VSYNC Interrupt Control Register x 03FF7 Bit 7 6 5 4 3 2 1 0 VBVO VBVO LVO VBVOIE VBVOIR Reset 0 0 0 0 0 0 0 R W R W R R R R R W R W The closed caption decoder 0 interrupt control register V BIVOICR con trols interrupt levels interrupt enables and interrupt requests for VBIVO interrupts Use interrupt control registers with the maskable interrupt enable flag MIE of the PSW at 0 VBVOLV 1 0 Interrupt level specification flag A 2 bit flag that sets the interrupt level Determines which of the CPU s levels 0 3 is assigned to the interrupt VBVOIE Interrupt enable flag 0 Disable interrupt 1 Enable interrupt VBVOIR Interrupt request flag 0 No interrupt request 1 Generate interrupt request MN101C46F LSI User Manual Panasonic Semiconductor Development Company 62 Panasonic Interrupts Interrupt Control Registers VBIV1ICR Closed Caption Decoder 1 VSYNC Interrupt Control Register x 03FF8 Bit 7 6 5 4 3 2 1 0 VBVI VBVI INVI LVO VBVIIE VBVIIR Reset 0 0 0 0 0 0 0 0 R W R R R R R W R W The closed caption decoder interrupt control register VBIV controls interrupt levels interrupt enables and interrupt requests for VBIV 1
293. scalar aaa on 93 5 1 IDESCIPU ON u CRECEN Pu 93 5 1 1 Peripheral Functions that Use Prescalar 93 5 1 2 Prescalar Block Diagram ee peg E 94 5 2 Prescalar Control Registers 1 2 sasana Rep EUR eer reed 95 5 2 1 Prescalar Control Registers au a a cece bt e RR EE bene sabes Meee ES 95 5 3 Operation of the Prescalar Function 97 5 3 1 PrescalarOperauion c uoo Res ees See Se A CEST EQUOS AT ea EUR 97 5 3 2 Example of Prescalar Operation Setup 0 0 97 6 8 Bit TIMES a i ea eR aerate ed ae ee eae ex 98 6 1 Introduction to the 8 Bit Timers 98 6 1 1 8 Timer Eunction sya agua y eR AS Les bos wR as RSS ER 98 6 1 2 8 Bit Timer Block Diagrams 99 6 2 Operation of the 8 Bit Timers 1 7 100 6 2 1 Operation of the 8 Bit Timers 1 100 6 2 2 Example of 8 Bit Timer Operation Setup 102 6 3 Operation of the 8 Bit Timer Cascade
294. scribes the instruction set MNIOIC Series Cross Assembler User Manual Describes the assembler syntax and notation MNIOIC Series C Compiler User Manual Usage Guide Describes the installation commands and options for the C compiler MNIOIC Series C Compiler User Manual Language Description Describes the syntax for the C compiler MNIOIC Series C Compiler User Manual Library Reference Describes the standard libraries for the C compiler MNIOIC Series C Source Code Debugger User Manual Describes the use of the C source code debugger MNIOIC Series PanaX Series Installation Manual Describes the installation of the C compiler cross assembler and C source code debugger and the procedures for using the in circuit emulator Questions and Comments We welcome your questions comments and suggestions Please contact the semiconductor design center closest to you See the last page of this manual for a list of addresses and telephone numbers You can also find contact and product information on the World Wide Web at http www psdc com MN101C46F LSI User Manual Panasonic Semiconductor Development Company xiii Panasonic General Description Overview General Description 1 1 Overview The MN101C series of 8 bit single chip microcontrollers can be used in embedded applications that incorporate a wide array of peripheral features such as cameras VCRs minidisc players TVs CD players laser disc players printers t
295. se difference in HSYNC separator sampling clock units The valid range is x 000 to x 3FF Panasonic Semiconductor Development Company MN101C46F LSI User Manual 195 Panasonic Closed Caption Decoder Closed Caption Decoder Registers Bit HLOCKLVH Sync Separator Detection Control Register 1 High x 03E55 HLOCKLVWH Sync Separator Detection Control Register 1 High x 03E75 Sync Separator Detection Control Register 1 x 03E54 HLOCKLVW Sync Separator Detection Control Register 1 x 03E74 7 6 5 4 3 2 1 0 7 6 5 4 2 1 0 H H H H H H H H H LOCK LOCK LOCK LOCK LOCK LOCK LOCK LOCK LOCK LV8 LV7 LV6 LV5 LV4 LV3 LV2 LVI LVO Reset R W Bit 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 R R R R R R R R W R W RW RW RW RW RW RW RW HLOCKLV 8 0 Sync separator detection threshold This value is compared to the count of the corrected HSYNC Its valid range is x 000 to x IFF and recommended settings are x 00 and x 08 HLOCKLV lt HSYNC count asynchronous HLOCKLV gt HSYNC count synchronous HDISTWH Sync Separator Detection Control Register 2 High X 03E57 HDISTWWH Sync Separator Detection Control Register 2 High x 03E77 HDISTW Sync Separator Detection Control Register 2 x O3E56 HDISTWW Sync Separator Detection Control Register 2 x 03E76 7 6 5 4 3 2 1 0 7 6 5 4 9 2 1 0
296. se eliminated Figure 11 2 IR Remote Signal Noise Filtering Panasonic Semiconductor Development Company MN101C46F LSI User Manual 201 Panasonic IR Remote Signal Receiver IR Remote Signal Receiver Operation 11 3 3 8 Bit Data Reception Resetting the 8 bit data reception counter allows the microcontroller to receive 8 bit data either with or without a leader The software can reset the counter using the BCRSTE and BCEDGS bits of the interrupt status register RMIS You can also reset the counter with an external reset or a hardware reset at leader detection Set BCRSTE to enable resets to the 8 bit data reception counter When the BCEDGS bit is 0 the counter resets at the first remote signal edge after each trailer detection This mode is for data containing no leader See figure 11 3 8 bit data Trailer 8 bit data Remote signal input Edge detection i 8 bit data 8 bit data reception detection Trailer detection reception 5 6 7 0 0 1 2 counter X X X Counter reset Figure 11 3 Reception of 8 Bit Data with No Leader When BCEDGS is 1 the counter resets at the second remote signal edge after each trailer detection By ignoring the leader this mode allows the microcon troller to receive 8 bit data that contains a leader See figure 11 4
297. ser Manual Panasonic Semiconductor Development Company 112 Panasonic 1 After reset clears the system clock supply to the OSD stops To operate the OSD you must first set OSDPOFF bit 7 of PCNTO x 03F4A to 1 You do not need to meet condition 3 in the closed caption mode since COL carries over On Screen Display OSD Operation 7 3 6 Basic VRAM Operation Display data stored in the VRAM transfers automatically through a DMA transfer from the internal RAM to the OSD as the display approaches the position specified by the microcontroller Since the OSD will have the internal bus during this transfer the microcontroller stops See section 7 8 and Interrupt Timing on page 135 for more information The two MSBs identify the transferred data with the following ID codes Qv Display code CC Color control code normal mode COL Color control code closed caption mode COL Repeat character blank code CB Horizontal position code HP Vertical position code VP Z 3 7 Conditions for VRAM Writes 1 The lead data for each line must be the color control code COL or the char acter code CC Never place the horizontal position HP vertical position VP RAM address pointer AP or repeat CB codes at the beginning of a line If the lead data is CC the character will be palette color 1 and the background will be color 2 Always place
298. ship between interrupt vector addresses and interrupt groups Table 3 2 Interrupt Vector Addresses and Interrupt Groups Vector Control Register No Address Interrupt Group Source Address 0 x 04000 Reset 1 x 04004 Nonmaskable interrupt NMI NMICR x OSFEI 2 x 04008 External interrupt 0 IRQO IRQOICR x 03FE2Z 3 x 0400C External interrupt 1 IRQI IRQIICR x O3FE3 4 x 04010 External interrupt 2 IRQ2 IRQ2ICR x 03FE4 5 x 04014 External interrupt 3 IRQ3 x 03FES 6 x 04018 External interrupt 4 4 IRQ4ICR x 03FE6 7 x 0401C External interrupt 5 5 IRQSICR x O3FE7 8 x 04020 Reserved 9 040247 Reserved 10 x 04028 Reserved 11 x 0402C Timer 2 interrupt TM2IRQ TM2ICR x 03FEB 12 x 04030 Timer 3 interrupt TM3IRQ TM3ICR x 03FEC 13 x 04034 Timer 4 interrupt TM4IRQ TM4ICR x 03FED 14 x 04038 Reserved 15 x 0403C Reserved 16 x 04040 Reserved 17 x 04044 Reserved 18 x 04048 Reserved 19 x 0404C Closed caption decoder 0 VBIOIRQ VBIOICR x 03FF3 interrupt 20 x 04050 Closed caption decoder 1 VBIIIRQ VBILICR x 03FF4 interrupt 21 x 04054 OSD interrupt OSDIRQ OSDICR x 03FF5 22 x 04058 interrupt DCIRQ DCICR x 03FF6 23 x 0405C Closed caption decoder O VBIVOIRQ VBIVOICR x 03FF7 VSYNC VBIVO inter rupt 24 x 04060 Closed caption decoder 1 VBIVIIRQ
299. ss Match Register ROM Address Data Register High Middle Low Address 0 AMCHIHO x 03F90 AMCHIMO x 03F71 AMCHILO x 03F70 CHDATO x 03FDO Address 1 AMCHIHI x 03F91 AMCHIMI x 03F73 AMCHILI x 03F72 CHDATI x 03FD1 Address 2 AMCHIH2 x 03F92 2 x 03F75 AMCHIL2 x 03F74 2 x 03FD2 Address 3 x 03F93 x 03F77 AMCHIL3 x 03F76 CHDAT3 x 03FD3 Address 4 x 03F94 AMCHIM4 x 03F79 AMCHIL4 x 03F78 CHDAT4 x 03FD4 Address 5 AMCHIHS x 03F95 AMCHIMS x 03F7B AMCHILS x 03F7A CHDATS x 03FD5 Address 6 AMCHIH6 x 03F96 AMCHIM6 x 03F7D 6 x 03F7C CHDAT6 x 03FD6 Address 7 AMCHIH7 x 03F97 AMCHIM7 x 03F7F AMCHIL7 x 03F7E CHDAT7 x 03FD7 Address 8 AMCHIHS x 03F98 AMCHIMS x 03F81 AMCHILS8 x 03F80 CHDATS x 03FD8 Address 9 AMCHIHO x 03F99 AMCHIMO x 03F83 AMCHIL x 03F82 CHDATO x 03FD9 Address 10 AMCHIHA x 03F9A AMCHIMA x 03F85 AMCHILA x 03F84 CHDATA x 03FDA Address 11 AMCHIHB x 03F9B AMCHIMB x 03F87 AMCHILB x 03F86 CHDATB x 03FDB Address 12 x 03F9C AMCHIMC x 03F89 AMCHILC x 03F88 CHDATC x 03FDC Address 13 AMCHIHD x 03F9D AMCHIMD x 03F8B AMCHILD x 03F8A CHDATD x 03FDD Address 14 x 03F9E AMCHIME x 03F8D AMCHILE x 03F8C CHDATE x 03FDE Address 15 x 03F9F AMCHIMF x 03F8F AMCHILF x 03F8E CHDATF x 03FDF Note All registers reset to
300. t P4OUT1 P41 M u JH SDAO X 1 TH PAIN1 lt Gl ec Schmidt trigger Figure 4 2 P01 SDA1 and P41 SDAO Dual Use Pins MN101C46F LSI User Manual Panasonic Semiconductor Development Company 68 Panasonic I O Ports I O Port Circuit Diagrams 0 Pullup off 1 Pullup on c POPUP2 0 P02 1 SDA1 lt gt POMD2 0 1 Port output lt gt PODIR2 0 Port low output Pin 1 Port high output 0 lt gt POOUT2 2 U 954 SDA1 X 1 SDA output s POIN1 lt q lt Schmidt trigger SDA input 2d 95 I CSEL1 I2CSEL0 0 Pullup off 1 Pullup on lt gt P4PUP2 0 P42 1 SDA0 lt gt P4MD2 0 Port input 1 Port output lt gt P4DIR2 J gt 0 Port low output Pin 1 Port high output 0 lt gt P4OUT2 M 42 U e SDAO 1 x TT P4IN2 lt 2 lt Schmidt trigger Figure 4 3 P02 SCL1 and P42 SCLO Dual Use I C Pins Panasonic Semiconductor Development Company MN101C46F LSI User Manual 69 Panasonic I O Ports 1 0 Port Circuit Diagrams
301. t Clock for Timer 2 97 6 1 Timer Function EN RA ove beg ee eR t eet 98 6 2 Clock Sources with Timers Running Timers 2 3 and 4 100 6 3 Procedure for Setting up an 8 Bit 102 6 4 Functions of Cascaded 2 22 103 6 5 Procedures for Setting up a Cascade Connection 104 6 6 Bit imer Control Registers iiie ox RR Re SAS RRS o Road et ce Rut Re 106 7 1 OSD Functions and 4 109 7 2 Power Saving Control Bits for 5 111 7 3 OSDPOFF and OSDREGE 5 111 7 4 Example Graphics VRAM 5 1 114 7 5 Example Text Settings 1 211 2 42 116 7 6 VRAM Bit Assignment oce aaa dau y u uu ei eee ete ee wee 118 7 7 Color Palettes au Cd te RR E ER RN RE 126 MN101C46F LSI User Manual Panasonic Semiconductor Development Company vii Panasonic List of Tables 7 8 Bit Settings for Controlling the Shuttered Area
302. t Fonts These are used to display text Each individual character has a text color and a background color for its display Colors for outlines and shading are set sepa rately There is a special closed caption mode for displaying closed captions You cannot use normal character display while you are using closed caption mode Also in using closed caption mode characters can be lined up with graphic tiles but graphic tiles on characters displayed as italics will be shifted by a pixel 7 3 3 2 Graphic Layer The graphic layer is used primarily for graphics Eight colors can be displayed in pixel units for one tile 8 color mode There are four sets of color palettes so a single tile can be displayed with 4 different colors on one screen by switching the color palette for individual tiles There is also a 4 color mode The color mode must be switched per screen so all tiles displayed on a single screen must be the same mode 8 color mode tiles and 4 color mode tiles cannot be displayed on the same screen The resolution of graphic tiles is 16 dots x 18 dots 7 3 4 Output Pin Setup Select OSD or port for the output pins RGB YS and YM are digital outputs Set the YS polarity 7 3 5 Microcontroller Interface The microcontroller writes display data to be sent to the OSD in the control register and the VRAM which is assigned to internal RAM space Assign the VRAM by setting its end address in the control register RAMEND MN101C46F LSI U
303. t control register XxxICR is higher than the interrupt mask level set here when the setting is smaller When an interrupt is accepted its interrupt level is set in and IMO so interrupts of that level or lower are not accepted until servicing of the received interrupt is completed Table 2 4 Interrupt Mask Levels and Interrupt Acceptance Interrupt Mask Level IM1 IMO Mask Priority Interrupt Levels Accepted Mask level 0 0 0 High Only the non maskable interrupt NMI Mask level 1 0 1 NMIs level 0 Mask level 2 1 0 U NMIs and levels 0 1 Mask level 3 1 1 L NMIs and level 0 2 ow Overflow Flag VF VF is set to 1 when the result of an arithmetic operation causes an overflow of a signed number If there is no overflow VF is 0 Use VF when working with signed data Negative Flag NF NF is set to 1 when the MSB of an operation result is 11 when the MSB is 0 NF is 0 also Use NF when working with signed data Carry Flag CF CF is set to 1 when the MSB produces a carry up or down as a result of an operation if there is no carry CF is 0 Zero Flag ZF ZF is set to 1 when all bits of the operation result are 0 otherwise ZF is 0 MN101C46F LSI User Manual Panasonic Semiconductor Development Company 28 Panasonic Basic CPU Functions Addressing Modes 2 9 Addressing Modes The MN101C46F has nine addressing modes The usable modes are preset for
304. ter left side 5 Horizontal shutter 0 movement direction 0 Right to left Left to right HSMO Horizontal shutter 0 movement control 0 Don t move 1 Move HSTO 9 0 Horizontal shutter O position Panasonic Semiconductor Development Company MN101C46F LSI User Manual 151 Panasonic On Screen Display OSD Registers HSHT1H Horizontal Shutter 1 Register High x 03EC7 HSHT1 Horizontal Shutter 1 Register x O3EC6 Bit 7 6 4 3 2 1 0 7 6 5 4 2 2 1 0 een xd HSMI m bs 15 i S i Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W RW RW RW RW RW RW RW RW RW RW RW RW RW RW HSON Horizontal shutter 1 on off 0 Off 1 On HSP1 Horizontal shutter 1 shuttering direction 0 Shutter right side 1 Shutter left side HSMP1 Horizontal shutter 1 movement direction 0 Right to left Left to right HSM1 Horizontal shutter 1 movement control 0 Don t move 1 Move HST1 9 0 Horizontal shutter 1 position SHTC Shutter Control Register x 03EC8 Bi 7 6 5 4 3 2 1 0 BLK sur ser seo C9 T sur sur Reset 0 0 0 0 0 0 0 0 R W RW RW RW RW RW RW R W RW SHTBLK Shutter blank function control 0 Shutter blank off 1 Shutter blank on COLBSHT Color background shutter control 0 Disable 1 Enable SHTSP 1 0 Shutter speed control Four speeds SHTRAD Shutter mode control 0 AND mode
305. terrupts temporarily 2 Specify the interrupt source that will return the standby mode to a CPU oper ating mode and set the xxxIE in the maskable interrupt control register for only that return Also set the MIE flag in the PSW NORMAL SLOW mode J Clear PSW s MIE flag and interrupt enable flags xxxIE Disable all interrupts of all maskable interrupt control registers Enable interrupt Set xxxIE which causes return that causes return Set MIE flag in PSW Invoke STOP HALT STOP mode Count stops STOP Reset returning from STOP io uad wait for oscillation to stabilize x Interrupt that causes return generated Watchdog timer NORMAL HALT Counts restarts SLOW mode STOP Disabled Interrupt acceptance cycle Y Note Operations in parentheses are performed by hardware Figure 2 7 Sequence for Invoking and Exiting Standby Modes MN101C46F LSI User Manual Panasonic Semiconductor Development Company 40 Panasonic Basic CPU Functions Standby Function You cannot return to a CPU operat ing mode with a maskable interrupt unless the interrupt has been enabled and the level is equal to or higher than the mask level set in the PSW for the priority of the interrupt to be used before invoking HALT or STOP mode Right after the instruction of the transition to HALT STOP mode NOP instruction should be inse
306. the ANCK 1 0 field of the ANCTRO register 4 Set the sample hold time ANCTRO x 03FBO bits 7 6 ANSH 1 0 01 4 Set the sample hold time using the ANSH 1 0 field of ANCTRO 5 Set the interrupt level ADICR 0 bits 7 6 ADLV 1 0 00 5 Set the interrupt level with the ADLV 1 0 field of the A D conversion end interrupt control register ADICR If the interrupt request flag may already be set clear it See section 3 5 2 Setting the Interrupt Flags on page 58 6 Enable interrupts ADICR x 03FFA bit I ADIE 1 6 Set the ADIE flag in the ADICR register to 1 to enable interrupts 7 Set the A D ladder resistor ANCTRO x 03FB0 bit 3 ANLADE 1 7 Set ANLADE flag of ANCTRO to 1 to send current to the ladder resistors and put conversion in standby 8 Start A D conversion ANCTR2 x 03FB2 bit 7 ANST 1 8 Set the ANST flag of A D control register 2 ANCTR2 to 1 to start A D conversion 9 End A D conversion ANBUFI x 03FB4 9 When A D conversion is complete the ADC generates an A D conversion end interrupt and clears the ANST flag in ADCTR2 The results are stored in the A D buffer ANBUF1 Note Steps 3 and 4 can be done simultaneously Panasonic Semiconductor Development Company 165 Panasonic MN101C46F LSI User Manual Analog Digital Converter Analog t
307. the hardware immediately stops the data transfer and generates an interrupt Address decoding The 2 bus controller decodes the microcontroller s address set in the I2CMYAD register when the microcontroller is a slave device It also decodes the general code address 0 M Forced bus reset Through software control by a write to the DDCBRST register the bus con troller can force the SCL line to reset to low when a bus error occurs This resets the entire 2 bus controller circuit leaving the microcontroller in slave receiver mode It does not change the contents of the IDCM YAD and I2CCLK registers Clock frequency adjustment The I2CCLK register sets the serial clock frequency allowing synchronization with low speed devices With a 3 58 MHz oscillator the maximum setting is 100 kHz and the minimum setting is 10 kHz Bus state monitoring With the I2CBSTS register the bus controller determines the logic levels of the SCL and SDA lines Panasonic Semiconductor Development Company MN101C46F LSI User Manual 217 Panasonic I C Bus Controller Setting up the Bus Connection 13 4 Setting up the I C Bus Connection Set the IC connection in the I2CSELO and I2CSELI bits of the PCNTO register x O3F4 A Since SCLO SDAO SCL1 and SDA1 pins also serve as general purpose port pins and reset to the general purpose function you must set these bits every time the program uses the function
308. timers Table 6 1 Timer Function Timer 2 8 bits Timer 3 8 bits Timer 4 8 bits Interrupt sources TM2IRQ TM3IRQ TM4IRQ Timer operation Cascade connection No Clock sources fosc fosc fosc fosc 32 fosc 64 fosc 32 fosc 64 fosc 128 fosc 64 fs 2 fs 2 fs 2 fs 4 fs 8 fs 4 fx fx fx fosc Machine clock oscillation for fast operation fx Machine clock oscillation for slow operation fs System clock See section 2 13 Setting the Clock Switch Register MN101C46F LSI User Manual Panasonic Semiconductor Development Company 98 Panasonic 8 Bit Timers Introduction to the 8 Bit Timers 6 1 2 8 Bit Timer Block Diagrams Prescaler Read Write block fose im3psc Compare register Match detected TM3IRQ TM2IRQ 8 bit counter ove 2 _ rst TM2MD 5 TM2CKO TM2CK1 p TM2EN Figure 6 1 Block Diagram of Timers 2 and 3 Read Write Compare register TM40C Match detected 8 bit counter TM4BC RST TM4IRQ 4 0 TM4CK1 Figure 6 2 Block Diagram of Timer 4 Panasonic Semiconductor Development Company MN101C46F LSI User Manual 99 Panasonic 8 Bit Timers Operation of the 8 Bit Timers 6 2 Operation of the 8 Bit Timers 6 2 1 Operation of the 8 Bit Timers Timer functions are able to generate interrupts repeatedly at set intervals Operation of 8 bit timers 2 3 and 4 Timer interrupts a
309. ting the sync separator level SPLVH 193 x 03E4B x 03E6B Sync separator level set register high SPLV 193 x OS3EAN x 03E6A Sync separator level set register Register for controlling the sync separator clock FQSELH 191 x O3E43 x 03E63 Frequency select register high FQSEL 191 x 03E42 x 03E62 Frequency select register Registers for controlling the HSYNC separator HSEPIH 195 x 03E4F x 03E6F HSYNC separator control register 1 high HSEPI 195 x 03E4E x 03E6E HSYNC separator control register 1 HSEP2H 195 x O3ESI x 03E71 HSYNC separator control register 2 high HSEP2 195 x OSE50 x 03E70 HSYNC separator control register 2 HLOCKLVH 196 x 03E55 03 75 Sync separator detection control register 1 high HLOCKLV 196 x OSE54 03 74 separator detection control register 1 HDISTWH 196 x OSEST x OSE7T Sync separator detection control register 2 high HDISTW 196 x O3E56 x 03E76 Sync separator detection control register 2 Register for controlling the VSYNC separator VCNTH 196 x O3E59 x 03E79 VSYNC separator control register high VCNT 196 03 58 03 78 VSYNC separator control register Register for controlling the field detection FIELDH 195 x O3E53 x 03E73 Field detection control register high FIELD 195 x O3E52 x O3E7Z Field detection control register Register for monitoring t
310. to x 0000 6 Set the low order timer interrupt level TM2ICR x 03FEB bit I TMOIE 0 6 Set the TM2IE flag in the timer 2 interrupt control register TM2ICR to 0 to disable interrupts 7 Set the high order timer interrupt level x 03FEC bits 7 6 TM2LV 1 0 10 7 Set the interrupt level using the TM3LV 1 0 field in the timer 3 interrupt control register TM3ICR If the interrupt request flag might have already been set clear the request flag See section 3 5 Set ting the Interrupt Flags 8 Enable high order timer interrupts x 03FEC bit I TM3IE 1 8 Enable interrupts by setting the flag of the TM3ICR register to 1 9 Start the high order timer TM3MD x 03F5D bit 3 TM3EN 1 9 s Set the TM3EN flag of the TM3MD regis ter to 1 to start timer 3 MN101C46F LSI User Manual Panasonic Semiconductor Development Company 104 Panasonic 8 Bit Timers Operation of the 8 Bit Timer Cascade Connection Table 6 5 Procedures for Setting up a Cascade Connection Continued Procedure Description 10 Start the low order timer TM2MD x 03F5C bit 3 TM2EN 1 10 Set the TM2EN flag of the TM2MD regis ter to 1 to start timer 2 TM3BC and TM2BC start counting from x 0000 as a 16 bit timer When TM3BC and TM2BC match the value set in the TM3OC and TM2OC registers the timer 1
311. tter above Vertical shutter 0 movement direction 0 Bottom to top 1 Top to bottom VSMO Vertical shutter 0 movement control 0 Don t move 1 Move VSTO 9 0 Vertical shutter O position MN101C46F LSI User Manual Panasonic Semiconductor Development Company 150 Panasonic On Screen Display OSD Registers VSHT1H Vertical Shutter 1 Register High x 03EC3 VSHT1 Vertical Shutter 1 Register x 03EC2 Bit 7 6 5 4 3 2 1 0 7 6 5 4 2 1 0 VSPI T VSMI bu T iu EM n a M Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R W RW RW RW RW RW RW RW RW RW RW RW RW RW VSON1 Vertical shutter 1 on off 0 Off On VSP1 Vertical shutter 1 shuttering direction 0 Shutter below 1 Shutter above VSMP1 Vertical shutter 1 movement direction 0 Bottom to top 1 to bottom VSM1 Vertical shutter 1 movement control 0 Don t move 1 Move VST1 9 0 Vertical shutter 1 position HSHTOH Horizontal Shutter 0 Register High x O3EC5 HSHTO Horizontal Shutter 0 Register 0 4 Bit 7 6 5 4 3 2 1 0 7 6 5 4 9 2 1 0 a HSPO iw HSMO ow 557 in a Pd ida i ow o Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R W RW RW RW RW RW RW RW RW RW RW RW RW RW HSON Horizontal shutter 0 on off 0 Off 1 On HSP0 Horizontal shutter 0 shuttering direction 0 Shutter right side 1 Shut
312. uctor Development Company 242 Panasonic MNIOIC Series Instruction Set MN101C SERIES INSTRUCTION SET Mnemonic Operation 6 Re Machine Code 6 7 8 Bcc BGT label if VF NF ZF 0 PC 6 d1 1 label H PC 6 3 4 0010 0011 0001 dii 8 107 if VFANF ZF 1 PC 6 3PC BHI label if CFIZF 0 PC 5 d7 label HPC 5 3 4 0010 0010 0010 d7 2 108 if CFIZF 1 5 BHI label 7 0 11 6 34 0010 0011 0010 44 2 3 108 if CFIZF 1 PC 6 gt PC BLS label if CFIZF 1 PC 5 d7 label HPC 5 34 0010 0010 0011 d7 109 if CFIZF 0 5 BLS label CFIZF 1 PC 6 d11 label H gt PC 6 3 4 0010 0011 0011 dil 3 109 if CFIZF 0 PC 62PC BNC label if NF 0 PC 5 07 label H gt PC 5 3 4 0010 0010 0100 d7 2 110 1 5 BNC label HINF 0 PC 6 d11 labe H PC 6 3 4 0010 0011 0100 dil 1110 1 6 BNS label i NF 1 PC 5 d7 label H gt PC 5 3 4 0010 0010 0101 d7 2 111 0 5 BNS label if NF 1 PC 6 d11 label H4PC 6 34 0010 0011 0101 dil 111 if NF 0 PC 6 gt PC
313. ure 10 1 Closed Caption Decoder Block Diagram MN101C46F LSI User Manual Panasonic Semiconductor Development Company 174 Panasonic The constants shown in figures 10 2 to 10 4 are recommended values only Operation at these values is not guaranteed Always set the same value to bits 6 and 7 of P2MD Otherwise CCD s don t work correctly Closed Caption Decoder Functional Description 10 3 Functional Description 10 3 1 Analog to Digital Converter The analog to digital converter ADC converts the clamped video signal to 8 bit digital data using a 14 32 MHz sampling clock Figure 10 2 shows an example con figuration using the recommended external pin connections In this example both caption decoders are used Figure 10 3 shows the recommended connection when neither decoder is used and figure 10 4 shows that when only CCDO is used XO3F4A bit 4 ADDATA 7 0 VIDEO IN bit 0 Low pass filler Clam circ CVBS1 X03F4A bit 5 VIDEO IN 1 VREFH1 IN Po VREFH ZZ ADC VREFL ADDATA 7 0 feyscux 1432 MHz vREFHO VREFHO Used as P27 T Used as 33V m cveso 6 8 kQ Used as P26 Ed Used as P22 VIDEO N enema or CVBSO CVBS1 Q Men Q Please OPEN Used as P23 Q CVBS1 CLH Used as P25 33 kQ L VREFH1 VREFH1 gt Used as 24 Used as P24 Figure 10 3
314. utput 0 P1DIRn M U PWM1 PWM2 x o 0 Port low output 1 Port high output 0 P10UTn Pin M u rb x 1 Low output P1INn lt Note 5 15 6 P16 Figure 4 9 P15 PWM1 P16 PWM2 Port 1 MN101C46F LSI User Manual Panasonic Semiconductor Development Company 74 Panasonic 0 Pullup off 1 Pullup on P1PUP7 I O Ports I O Port Circuit Diagrams P2PUPO i 0 P17 IRQ2 P20 IRQ3 1 PWM3 PWM4 PIMD7 P2MD0 0 Port input 1 Port output P1DIR7 P2DIR0 PWM3 PWM4 4 x c 0 Port low output 1 Port high output P1OUT7 P2OUTO Pin gt x c Low output P1IN7 2 0 1 IRQ2 IRQ3 Schmidt trigger Figure 4 10 P17 PWM3 IRQ2 Port 1 and P20 PWM4 IRQ3 Port 2 Panasonic Semiconductor Development Company 75 Panasonic MN101C46F LSI User Manual I O Ports 1 0 Port Circuit Diagrams 0 Pullup off 1 Pullup on e PUPI 0 P21 IRQ4 1 PWM5 lt gt e 2 01 0 Port input 1 Port output P2DIR1 PWMS output gt x 0 Port low output 1 Port high output mp P20UT1 PIN 1 IRQ4 T Schmidt trigger Figure 4 11 P21 PWM5 IRQ4 Po
315. vement so you must reset the bits each time Table 7 9 Bit Settings for Controlling Shutter Movement Function VSHTO Bit VSHT1 Bit HSHTO Bit HSHT1 Bit Description Shutter movement enable VSMO VSMI 5 0 HSMI 0 Move shutter disable 1 Don t move shutter Shuttering movement VSMPO VSMPI HSMPO 0 Move from top to bottom vertical shutters from direction left to right horizontal shutters 1 Move from bottom to top vertical shutters or from right to left horizontal shutters Shuttering movement SHSPO SHTSP1 00 Move every VSYNC speed control shared bits 01 Move every 2 VSYNCs 10 Move every 3 VSYNCs 11 Move every 4 VSYNCs Panasonic Semiconductor Development Company MN101C46F LSI User Manual 139 Panasonic On Screen Display Controlling the Shuttering Effect HSHT0 HSHT1 VSONO VSON1 1 V shutters 0 and 1 on HSONO HSON1 1 H shutters 0 and 1 on VSPO 1 V shutter 0 shutters above VSHT0 VSP1 0 V shutter 1 shutters below HSP0 1 H shutter 0 shutters to the left HSP1 0 H shutter 1 shutters to the right SHTRAD 1 All shutters ORed VSHT1 Television screen Shuttered region This example shows V shutter 0 moving downward It shutters both the text and the background color in the text layer HSHTO HSHT1 VSMO 1 V shutter 0 movement enabled VSM1 0 V shutter 1 movement disabled 5 0 HSM1 1 Movement enabled for H shutters
316. x OSE2E R CRI frequency width register B low CRIISH x 03E11 x 03E31 R W CRI capture start timing control register 1 high CRIIS x 03E10 x 03E30 R W CRI capture start timing control register 1 CRIIEH x O3EI3 x 03E33 R W CRI capture stop timing control register 1 high 03 12 x 03E32 R W CRI capture stop timing control register 1 25 x 03E15 x 03E35 R W CRI capture start timing control register 2 high 125 x 03E14 x 03E34 R W CRI capture start timing control register 2 CRDEH x 03E17 03 37 R W capture stop timing control register 2 high CRDE x 03E16 x 03E36 capture stop timing control register 2 DATASH x 03E19 x 03E39 R W Data capture start timing control register high DATAS x 03E18 03 38 R W Data capture start timing control register DATAEH x 03E1B x 03E3B R W Data capture stop timing control register high DATAE x 03E1A x 03E3A R W Data capture stop timing control register STAPH x 03E1D x 03E3D R W Sampling start position register software set ting high STAP x 03E1C x 03E3C R W Sampling start position register software set ting FCPNUMH x OSEIF R Sampling start position register hardware cal culation high FCPNUM x OSEIE x OSE3E R Sampling start position register hardware cal culation Panasonic Semiconductor Development Company 183
317. xt background disappears leaving only the characters visible Television screen Figure 7 20 Text Layer Shuttering Setup Examples To shutter the color background Set the color background shutter control bit COLBSHT of the shutter control register x 03EC8 to 1 This function exists only when the program enables a color background It allows you to limit the area covered by the color background blank out the shuttered area Set the shutter blanking control bit SHTBLK of SHTC to 1 Shutter blanking outputs black to the entire shuttered area To output blanking to a display that uses a color background enable the color background shutter COLBSHT 1 so that the color background will also be blanked in the shuttered area Figure 7 21 shows two setup examples MN101C46F LSI User Manual Panasonic Semiconductor Development Company 142 Panasonic On Screen Display Controlling the Shuttering Effect HSHT0 HSHT1 CCSHT 0 Shuttering of text disabled BCSHT 0 Shuttering of text background disabled VSHTO SHTBLK 1 Shuttered area is blank VSHT1 Television screen Shuttered area Shuttered area is blank black HSHTO HSHT1 Color background CCSHT 0 Shuttering of text disabled BCSHT 0 Shuttering of text background disabled SHTBLK 1 Shuttered area is blank COLBSHT 1 Color background is shuttered VSHTO VSHT1 Television screen Figure 7 21 Shutter Bla
318. y addressing 256 Kbytes of memory space shared by instructions and data Machine cycle NORMAL mode 279 3 to 333 3 ns 3 0 to 3 58 MHz 3 0 to 3 6 V SLOW mode 1 12 to 1 33 us 0 75 to 0 895 MHz 3 0 to 3 6 V Operating modes NORMAL SLOW HALT and STOP ROM correction Programming can be changed in up to 16 locations Internal memory 96 Kbyte ROM 3 Kbyte RAM Interrupt functions Twelve internal interrupts Software fault interrupt nonmaskable interrupt NMI Timer interrupts Timers 2 interrupt Timer 3 interrupt Timer 4 interrupt ADC interrupt Pc interrupt OSD interrupt Closed caption decoder interrupts Closed caption 0 interrupt Closed caption 1 interrupt Closed caption 0 VSYNC interrupt Closed caption 1 VSYNC interrupt IR remote receiver interrupt Six external interrupts IRQO 5 Edge selectable Timer counters Three 8 bit timers Timer 2 e Clock sources fosc fosc 4 fosc 16 fosc 32 fosc 64 fs 2 fg 4 fx Timer 3 16 bit cascading function connecting to timer 2 e Clock sources fosc fosc 4 fosc 16 fosc 64 fos 0 128 fs 2 fs 8 fx Timer 4 e Clock sources fosc fosc 4 fosc 16 fosc 32 fosc 64 fs 2 fg 4 fx Watchdog timer Timeout period selectable to 216 ne or 220 Forced hardware reset within the IC when timeout period detected A D converter 5 bits and 8 channels Remote signal Household Electrical Appliance Manufacturers Assoc
319. you must connect V pp power supply pins 20 and 39 to external sources of the same voltage 3 3 V This ensures that no other element can supply power externally to either of the pins 6 POI PO2 P14 P21 P41 and P42 are N channel open drain pins Panasonic Semiconductor Development Company MN101C46F LSI User Manual 7 Panasonic General Description Electrical Characteristics Table 1 5 Recommended Operating Conditions C11 12 to 14 32 MH C12 TIT TIT Figure 1 3 OSC1 and 5 2 Oscillator Circuits Vss 0V No Parameter Symbol Conditions Min Typ Max Unit B1 Power supply voltage 1 Vpp fosc 12 to 14 32 MHz 3 0 3 3 3 6 V B2 Ambient temperature T Vpp 3 0 V to 3 6 V 20 70 C B3 Instruction execution speed tc Vpp 3 0 V to 3 6 V 279 3 333 3 ns B4 Oscillator frequency See figure 1 3 fosci Vpp 3 0 V to 3 6 V 12 00 14 32 MHz OSC1 OSC2 Table 1 6 Electrical Characteristics Ta 20 to 70 C Vpp 8 3 V Vas 0 V No Parameter Symbol Conditions Min Typ Max Unit Power supply current C1 Operating supply current Ippo fosc 14 32 MHz 10 50 mA Input pins tied to Vpp or Vss Output pins open OSD operating OSC2 Oscillator circuit C2 Internal feedback resistance R posc2 OSCI Vpp or OSCI Vss 313 940 2820 MN101C46F LSI User Manual Panasonic Semiconductor Development Company 8

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