interoperability report
Contents
1. specification FEATURE DESCRIPTION VALUE RECEIVER TRANSMITTER LINE RATE Low END FPGA ASIC 3 GBPs X X Mib END FPGA ASIC 6 GBPS X X Mib END FPGA ASIC 10 GBPs x x HIGH END FPGA ASIC 12 5 GBPS x x L NUMBER OF LANES 1 8 RANGE X X M NUMBER OF CONVERTERS 1 8 RANGE X X F NUMBER OF OCTETS 1 2 4 8 AND 16 X X N SAMPLE RESOLUTION 7 16 BITS RANGE X X N SAMPLE ENVELOPE 8 12 16 20 x x HD HIGH DENSITY MODE 1 0 FORN 8 16 X X 1 FOR N 12 20 SCR SCRAMBLING 1 0 X X CF CONTROL BITS PER FRAME 0 X X cS CONTROL BITS PER SAMPLE 0 3 BITS RANGE X X PROGRAMMABLE SuBcLass 0 BACKWARD COMPATIBLE SYNC_B X X SUBCLASS 1 DETERMINISTIC LATENCY SYSREF x x SUBCLASS 2 DETERMINISTIC LATENCY SYSCLK LINE CODING 8B10B X X Test MODES BUILT IN K 28 5 X X BUILT IN ILA X X CODE GROUP SYNC X X LANE SYNC X X LANE CONFIG X X Table 1 Features of the Receiver and Transmitter modules Maximum rates on FPGA ASIC depends on actual family speed grade technology process respectively Standard Deliverables Item Description Receiver Transmitter Deliverables RTL Code encrypted X X Regression Test Bench X O X O Test Cases X O X O Timing Constraint File X X Documentation Datasheet X X User Manual X X Release Note X X Regression Test Report X X Simulation IOT Reports X X Hardware IOT Reports X X Logs Synthesis Report X X Test Log X X Table 2 Standard Deliverables IDT 2014 All rights reserv2. Interoperability report Test number 9 10 11 12 13 14 15 16 17 18 19 20 21 Test Data phase Character replacement Framing Framing Framing Framing Scrambling 3 125Gbps data rate 6 375Gbps data rate 10Gbps Subclass 1 Subclass 1 Subclass 2 Description Test that the expected waveform is obtain at the DAC outputs Check that the DAC still outputs correct data if character replacement is disabled at TX LMF 421 LMF 422 LMF 222 LMF 124 Enable scrambler and check data at the output Check data contents at the output of the DAC Check that latency is constant from start up to start up Check data contents at Interoperable Yes Yes Yes No Yes Yes Yes Yes Yes Yes Yes Yes No Notes Check with a spectrum analyzer for a clean sine wave at output Check for a clean sine wave at output No K28 3 or K28 7 detected by DAC Check for a clean sine wave at output S 2 not supported by TX design Check for a clean sine wave at output Check for a clean sine wave at output Performed using a constant data and SBER testing mode inside the DAC Check for a clean sine wave at DAC output Check for a clean sine wave at DAC output Check for a clean sine wave at DAC output Tested LMF 222 as Arria V GT kit features 2 TRX up to 10Gps on FMC connector Check for a clean
3. speed serial JESD204B DAC with four lanes input Populated device can be DAC1658D1G5NLGA8 or DAC1653D1G5NLGA8 e One SAMTEC FMC high density connector to interface with compatible carrier board e One USB to SPI master device It can be bypassed and the demo board can be controlled from the carrier through the FMC connector e On board voltage regulators for all devices on the board e Clock divider by 1 2 4 8 or 16 to drive carrier board clock input The DAC1653D and the DAC1658D are high speed high performance 16 bit dual channel Digital to Analog Converters DACs The devices provide sample rates up to 2 Gsps with selectable 2X 4X and 8X interpolation filters optimized for multi carrier and broadband wireless transmitters The DAC165xD integrates a JEDEC JESD204B compatible high speed serial input data interface running up to 10 Gbps allowing dual channel input sampling at up to 1 Gsps over four differential lanes There are two versions of the DAC165xD e Low common mode output voltage part identification DAC1653D1G5NLGA8 e High common mode output voltage part identification DAC1658D1G5NLGA8 An optional on chip digital modulator converts the complex I Q pattern from baseband to IF The mixer frequency is set by writing to the Serial Peripheral Interface SPI control registers associated with the on chip 40 bit Numerically Controlled Oscillator NCO This accurately places the IF carrier in the frequency domain The 16 bit pha
4. HDL 93 and it supports any FPGA ASSP or ASIC technologies The MTI s IPC JESD204 B offers the following competitive advantages Support of rates up to 12 5 Gbps with each Transmitter or Receiver core Support for FPGA ASSP and ASIC silicon target either Data Converter or DSP 32 bits internal data processing with clock frequency 1 40 of baud rate in use enable usage in low end and mid end FPGAs MCDA ML Multiple Converter Device Alignment Multiple Lanes o Disabling of features mandatory to a class MCDA ML module if connected to a device pertaining to a class that does not support these features JESD204 standard Support run time programmable configuration for key parameters o L M F N HD SCR CS o Support for deterministic latency subclass 1 o Support for backward compatibility to JESD204A subclass 0 O Insertion of tail bits are performed based on register settings Both constant and low DC content tail bits are supported o Support for built in test modes Support for error handling Includes 8b10b coding block Separate CPU interface for control and monitoring IDT 2014 All rights reserved Rev 1 0 01 06 2014 5 of 13 IDT INTEROPERABILITY REPORT Features The JESD204B Receiver and Transmitter modules are fully compliant to the JESD204B 01 2012 standard with the following feature IDT integrated Device Technology set as a subset of the entire
5. INTEROPERABILITY REPORT Interoperability report between Altera FPGA and IDT DAC Rev 1 0 01 06 2014 IDT Integrated Device Technology Info Content Keywords JESD204B DAC1658D 1653D DAC1658Q 53Q Altera ARRIA V Stratix V Cyclone V Abstract This document describes the tests that have been performed between IDT JESD204B DAC and Altera FPGA development kit supplied with MTI s IPC JESD204 B IP solution IDT Integrated Device Technology IDT INTEROPERABILITY REPORT Revision history Rev Date Description Author 1 0 2014 01 06 Initial revision with Arria V GT dev kit P Lieutaud IDT HSC DAC Application Engineer Contact information For additional information please visit http www idt com IDT 2014 All rights reserved Rev 1 0 01 06 2014 2 of 13 IDT IDT integrated Device Technology INTEROPERABILITY REPORT 1 1 1 2 1 3 1 3 1 Introduction The goal of this document is to detail tests performed between silicon devices As result one can claim that they are compatible from the perspective of the implementation of the JESD204B standard Scope Interoperability testing shall be limited to existing DAC and FPGA dev kit hardware Hardware setup IDT DAC165xD demo board The board used is referenced as DAC1658D1G5 DB or DAC1658D1G5 DB Board schematic and layout are available from http www idt com Its main characteristics are e One dual high
6. all devices on the board e Clock divider by 1 2 4 8 or 16 to drive carrier board clock input The DAC1653Q1G5NAGA and the DAC1658Q1G5NAGA are high speed high performance 16 bit Quad channel Digital to Analog Converters with similar feature sets as DAC1653D and the DAC1658D devices ref to 1 3 1 The DAC165xQ includes a very low noise bypass able integrated Phase Locked Loop PLL This PLL is fully integrated and does not need any external passive components 1 3 3 Altera Arria V GT development kit The hardware used is referenced as Arria V GT FPGA Development Board The main features are e Two Arria V GT FPGA 5AGTD7K3F40I8N in the 1517 pin FineLine BGA FBGA package e FPGA configuration circuitry e Clocking circuitry e Two high speed mezzanine card HSMC connectors e One FMC port e DDR3 SDRAM e For a full list of features please visit the Arria V GT Development Kit web page at http Awww altera com products devkits altera kit arria v gt html IDT 2014 All rights reserved Rev 1 0 01 06 2014 4 of 13 IDT IDT integrated Device Technology INTEROPERABILITY REPORT 1 3 4 MTI s IPC JESD204 B Applications and Benefits The applications for MTI s IPC JESD204 B IP are related to Data Converters or DSP Digital Signal Processing environments required for radar medical imaging wireless and cellular military and aerospace just to mention a few The IP implementation is made in RTL V
7. ed Rev 1 0 01 06 2014 6 of 13 IDT integrated Device Technology IDT INTEROPERABILITY REPORT The JESD204B IP FPGA is provided from MTI and is accessible from following web pages http Awww mti mobile com products ipc interfacing ipc jesd204 b Demo version can be requested here http Awww mti mobile com products ipc interfacing ipc jesd204b altera IDT 2014 All rights reserved Rev 1 0 01 06 2014 7 of 13 IDT integrated Device Technology IDT INTEROPERABILITY REPORT 1 4 1 5 Hardware setup The picture below gives an overview of the used configuration 1 Fig 1 ArriaV GT dev kit with DAC1658D1G5 DB As FMC connector is connected only to FPGA2 the FPGA design is targeting that device The frequency generator is connected to DAC board DAC_CK SMA connector Reference clock to FPGA is supplied from the DAC board via FMC connector To supply the correct frequency SO S1 and S2 jumpers have to be properly set to divide down by 4 For example if the DAC clock frequency is 1 2GHz the FPGA reference clock is 300MHz and the data rate on the lanes will be 6Gbps DAC must be set to operate in by 2 interpolation and use all the 4 lanes IDT 2014 All rights reserved Rev 1 0 01 06 2014 8 of 13 IDT INTEROPERABILITY REPORT IDT integrated Device Technology 2 Test results Interoperability report Table 1 2 1 Setup 1 Setu
8. nty of merchantability or non infringement of the intellectual property rights of others This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties IDT s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users Anyone using an IDT product in such a manner does so at their own risk absent an express written agreement by IDT Integrated Device Technology IDT and the IDT logo are registered trademarks of IDT Other trademarks and service marks used herein including protected names logos and designs are the property of IDT or their respective third party owners Copyright 2014 All rights reserved IDT 2014 All rights reserved Rev 1 0 01 06 2014 13 of 13
9. p 1 is built around an ArriaV GT dev Kit using MTI s IPC JESD204 B IP and DAC1658D demonstration board The following table details the tests carried out and the results Tests performed using setup 1 Unless otherwise specified tests are conducted at bitrate of 6Gbps Test number 1 Test Sync request K28 5 Code group synchronization Inter Lane Alignment Inter Lane Alignment Inter Lane Alignment Inter Lane Alignment Configuration data Description DAC asserts SYNC low DAC detects K28 5 transmitted by TX DAC has properly received more than 4 K28 5 Check that the DAC has received at least 4 multi frames Subclass0 only check that more than 4 multi frames is supported Check that the DAC has achieved ILA Check that the DAC has achieved ILA when K 32 Check that the DAC has received the correct expected configuration data Interoperable Yes Yes Yes Yes Yes Yes Yes Notes SYNC state is reported using a LED on the FPGA carrier board DAC reports that it has received K28 5 DAC synchronization state machine has entered CS_DATA state DAC has also de asserted SYNC signal Check ILA flag inside the DAC Not supported in TX IP DAC ila_rcv_flag is high DAC ila_rcv_flag is high Check DAC received configuration data IDT 2014 All rights reserved Rev 1 0 01 06 2014 9 of 13 IDT INTEROPERABILITY REPORT IDT
10. report 3 Contents 1 TASK noeneen Error Bookmark not defined 1 4 8 1 1 Introduction oo eseseseseseseteeseseseseseeetetseseseseeetevens 3 15 Hardware Setup 0 eect teense 8 1 2 SCOPE ea era a NEE EAEE EEIE a 2 Test results ansssnssensesennsennnnnnnunnnnnnnnnnnnnnnnnnnennnnn nnn 9 1 3 Hardware SCtUp scsessssesesseessennetnsenenein 2 1 E csests Siac iccasiatasedilenathaests 9 1 3 1 IDT DAC165xD demo board f 2 2 SGtUp A aa EOE 11 1 3 2 IDT DAC165xQ demo board sseeseeeeeteees 3 CONLGINS wis iis csccccctecstccstccecscecceetice sees cecesneseeccececesss 13 1 3 3 Altera Arria V GT development kit 4 1 3 4 MTI s IPC JESD204 B eccecceeceeeeeeeeeteeeeteees 5 DISCLAIMER Integrated Device Technology Inc IDT and its subsidiaries reserve the right to modify the products and or specifications described herein at any time and at IDT s sole discretion All information in this document including descriptions of product features and performance is subject to change without notice Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products The information contained herein is provided without representation or warranty of any kind whether express or implied including but not limited to the suitability of IDT s products for any particular purpose an implied warra
11. se adjustment feature the 12 bit digital gain and the 16 bit digital offset enable full control of the analog output signals The DAC165xD is compatible with device subclass 0 and 1 of the JEDEC JESD204B standard guaranteeing deterministic and repeatable interface latency using the differential SYSREF signal The device also supports harmonic clocking to reduce system level clock synthesis and distribution challenges IDT 2014 All rights reserved Rev 1 0 01 06 2014 3 of 13 IDT IDT integrated Device Technology INTEROPERABILITY REPORT 1 3 2 Multiple Device Synchronization MDS enables multiple DAC channels to be sample synchronous and phase coherent to within one DAC clock period MDS is ideal for LTE and LTE A MIMO transceiver applications The DAC165xD includes a 2 4 or 8 divider to achieve the best possible noise performance at the analog outputs allowing harmonic clocking through the system IDT DAC165xQ demo board The board used is referenced as DAC1658Q1G5 DB or DAC1653Q1G5 DB Board schematic and layout are available from http www idt com Its main characteristics are e One quad output high speed serial JESD204B DAC with 8 lanes input e One SAMTEC FMC high density connector to interface with compatible carrier board e One USB to SPI master device It can be bypassed and the evaluation board can be controlled from the carrier through the FMC connector e On board voltage regulators for
12. sine wave at output Check that overall system latency uncertainty is with 1 DAC clock period DAC and TX IP do not IDT 2014 All rights reserved Rev 1 0 01 06 2014 10 of 13 integrated Device Technology IDT INTEROPERABILITY REPORT S22 Interoperability report Test number Test Description Interoperable Notes the output of the DAC support subclass 2 22 Test STLTP Test short transport Yes Scrambler and de layer test pattern scrambler enabled at both side of the link F 1 23 Test LTLTP Test long transport No Not supported by DAC layer test pattern 24 Test JTSPAT Check error free No Not supported by TX channel IP 2 2 Setup 2 Setup 2 is built around an Arria V GT dev Kit and DAC1658Q1G5 DB demonstration board s z s Qi IDT 2014 All rights reserved Rev 1 0 01 06 2014 11 of 13 DT INTEROPERABILITY REPORT SBi Interoperability report The following table details the tests carried out and the results Table 2 Tests performed using setup 2 Table description Test number Test Description Interoperable Notes 1 Framing LMF 841 Yes Check for a clean sine wave at DAC output 2 3 125Gbps data rate Yes Check for a clean sine wave at DAC output 3 6 375Gbps data rate Yes Check for a clean sine wave at DAC output IDT 2014 All rights reserved Rev 1 0 01 06 2014 12 of 13 IDT INTEROPERABILITY REPORT Pio Interoperability
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