User Manual for Daughter Card
Contents
1. RYCCLK_FWL nc gays ee TXC_BUFR_FROM_FPGA 35 Mhz Xt xN N TX _CLKGEN_TO_FPGA U3 CDCU87 L____ty _ CLKGED SCLk e33 E oie ae m RY CLK FWL nc gays z TXC_N_BYPASS_CLk Sil178 25 Mhz Xte xM N TXC_CLKGEN_TO_FPGA TXC E BYPASS CLK i u3 U UE TX _CLKGEN_SCLk Saye TAC BUFR TC_ FPGA TX _BUFR_FROM_FPGA y DV TX _BUFR_TC_FPGA Xl CDCU87 200MHz 07 Tx _BUFR_TC_FPGA DIM _OSCc_OUT _4 OSC 34 poo Tx _h _BUFR_CLk FPGA TX _ _BYPASS CLK DIMN_FPGA_FE gt TX _ BYPASS_CLK Sil178 UE U J OPTIONAL H gt TX _TXC See Schematic DV 1 OPTIONAL HE gt TX S See Schematic GT DIVIDER NOT AVAILABLE ON ALL CHIPS tte CDCU87 DDF 2 L_DIMW_PLI_CKIh p CABLE _CIN l ne SODIMN Se a oe p 2 WBMhzwe 1884302 a i U44 MGTCG1_CLK1 gt MGTCG _ CLk p DIMN_FPGA_FE 250MHz OSC L 45 f MGTOSCI CLK H MICTOF_E CLK Mictor MICTOR_C_CLK gt 11 250MHz OSC L28 t MGTOSC2_CLK GT DVE Ree MGTCG _SCLK 16 4 1 Block Diagram of the DNDVI_DC clocks DIMM_FPGA_FB EXPCOh_CLKIN 20C Pir EXPCON CCLK gt Daughtercarc EXPCON_DCLK Header F4 EXPCON_ECLK 4 DVIC Si 163B RY J LRX0_RXCHI Ue Rx CLK _ RX0_CLK_FWE DVE Si 1638 TX0_CLKGEN_SCLK2. RJA al z Haii L RX1_CLK_FWE TX1_CLKGEN_SCLK RXO_CLK_FWE agg yge XVIN TXC_CLKGEN_TO_FPGA _ U31 CDCL877 TX0_CLKGEN_SCLK L 32 TX0_BUFR_FRON_FPGA y 2 Mhz Xta t TX0_BUFR_TC_FPGA t TX0_W S_BUFR_CLK RX4_CLK_FWL ngage Fuxe XVN TXC_CLKGEN_TO_ FPGA BI cs Si 178 U32 U6 UE TX1_CLKGEN_SCLK _ TX0 TXC PERE eal gt Tx1_BUFR_FROV_FPGA y DVIC TX1_BUFR_TC_FPGA y TX Jz CDCL877 20CMHz L2 L TX1_BUFR_TC_FPGA m DIMM_OSC_ OUT OSC U34 DOR L TX1_N S_BUFR_CLK FPGA TX1_lv_BYPASS_CLK DIMM_FPGA_FB gt TX1_ BYPASS_CLK Si 178 UEU OPTIONAL H gt TX1_TXC See Schematic DVI OPTIONAL He l gt See Schematic m C D VIDER NOT AVAILABLE ON ALL CHIP SiO CDCL877 DDR2 DIMM_PLL_CKIN CABLE1_ CIN L5 SODIMM eee gt a 21 4 Mhz Xta ICS84302C M ai f U44 MGTCG _CLK gt D DIMM FPGA FE 25CMHz OSC U45 MGTOSC_CLK gt MICTOR_E_CLK gt Mictor MICTOR_O CLK lt 11 25CMHz 7 OSC U28 MGTOSC2_CLK gt a C T D V D E Fm MGTCG1_SCLK 17
3. 4 2 List of Input Clocks When shipped the DNDVI board has several clock sources available DIFFERENTIAL e 200 Mhz Oscillator U34 H17 J17 e 250 Mhz Oscillator U45 M34 N34 for MGT use only e 250 Mhz Oscillator U28 J1 K1 for MGT use only e 1CS8442 Clock Generator U31 J16 J15 e ICS8442 Clock Generator U32 J14 K14 e 1CS843020 Clock Generator U44 AP29 AP28 AP3 AP4 for MGT use only e Note Pins 2 3 on H5 can be configured as an input clock at the expense of two LEDs See Schematic page PO9_CLOCKS for details H19 H18 e Note Pins 2 3 on H8 can be configured as an input clock at the expense of two LEDs See Schematic page PO9_CLOCKS for details AF18 AG18 DIFFERENTIAL FEEDBACK CLOCKS e TX0 PLL CDCU877 U33 K18 K17 e TX1 PLL CDCU877 U27 K19 J19 e DDR PLL CDCU877 U53 L15 L14 SINGLE ENDED CLOCKS e RXO U9 AD21 e RX1 U12 AE18 e EXPCON_CCLK P4 AF16 e EXPCON_DCLK P4 AG17 e EXPCON_ECLK P4 AE21 18 4 3 List of Output Clocks SINGLE ENDED CLOCKS e EXPCON_CLKIN P4 AF20 e GP_I2C_SCL AE17 Note that this is the general I2C clock for the board and attaches to both the FPGA temperature sensor and the DDR2 connector e RX0 CLK FWD U31 U7 Note By default this clock is ignored on the ICS8442 see schematic for details e RX1_CLK_FWD U32 U6 Note By default this clock is ignored on the ICS8442 see schematic for details e RX0_I2C_SCL U
4. DO is RX _QO_ 23 0 NOTE QO is bit reversed in dual link mode Master ODCK is RX _CLK HSYNC VSYNC are also passed into the FPGA Receive Debug Headers H3 H VSYNC 3 4RX_DE 5 6 H1 H4 Slave Clock Debug Header 4 27 I2C Bypass If so desired the I2C channel can be directly connected to the DVI transmitter To do this one needs to remove the DDC EEPROM U13 U20 Default Removed and use jumpers to short the RX I2C to the TX I2C H2 H6 2C ByPass E o 200 oe sa u RX DDC_SDA 3 H ATX _DDC_SDA ad E F qi 6 ig i 6 OROROORO 5 MORO ORM OP OROR ORO ON Please see the schematic for specific connection issues 5 2 Transmitters Sil178 Note that the Sil 178 reference manual should be considered the authority concerning the Sil 178 The manual is available on the DNDVI CD as Sil178 DS 0086 pdf and also from the Sil website http www siliconimage com docs SiI DS 0086 pdf ISEL RST EDGE HTPLG DSEL SDA BSEL SCL Configuration Logic Block EXT_SWING TXC PREi PanelLink VSYNC Data TMDS TXO Digital IDCK Capture Cora TX14 e Et e T D 23 0 control signals Block Figure 2 Functional Block Diagram The DNDVI_DC board has two Sil 178 chips per transmitter channel One Sil 178 is designated as the MASTER and one as the SLAVE When a single link signal is applied to the transmitter the MASTER
5. above discussed N and M inputs T configures the TEST output a pattern of 1 1 will set TEST to FOUT Note that the SDATA and SLOAD are the same for all the ICS8442s ICS843020 01 on the DNDVI board and that each IC component can be programmed separately by control of the individual S CLOCK signals Please see the schematic for specific ICS843020 01s The maximum frequency allowable for S CLOCK is 50MHZ LVCMOS When editing the constraints file for a design make sure the ICS843020 01 inputs are set to LVDSEXT_25 And that DIFF_TERM is used on the input buffer See note on Schematic PO9_CLOCKS Example FOUT Verilog VHDL UCFE settings UCF NET FOUT LOC IOSTANDARD LVDSEXT_25 Verilog IBUFGDS Verilog DIFF_TERM TRUE Verilog IGDS_FOUT Verilog I FOUT_P IB FOUT_N O ROUT_IGDS 24 VHDL VHDL VHDL VHDL VHDL VHDL IGDS_FOUT IBUFGDS generic map DIFF_TERM gt TRUE port map I gt FOUT_P IB gt FOUT_LN O gt FOUT_IGDS 5 DVI Interfaces Receivers and Transmitters 5 1 Receivers Sil163B Note that the Sil 163B reference manual should be considered the authority concerning the Sil 163B The manual is available on the DNDVI CD as Sil163b DS 0055 pdf and also from the Sil website http www stimage com docs Sil DS 0055 pdf PIXS M_S SD OCK_INV EXT_RES Termination Control Data oe SYNC2 RX2 RX1 Data Recovery ODCK SYNC1 CH1 DE Panel C
6. deselect the Copy the input design to the project directory option Select the U1_fpea ucf file as the constraint file Select the appropriate FPGA properties 31 6 3 on the next screen then finish creating the project Right click on Translate and select properties Make sure the Allow Unmatched LOC Constraints option is enabled Generate the programming file by double clicking on Generate Programming File At this point a bit file should be created load it into the DNDVI_DC board following the steps outlined in section 1 4 Horizontal Mirroring After recompiling the bitfile including the H_MIRROR option the following demonstration can be performed DNDVI_DC HORIZONTAL MIRROR TEST SETUP DVI IMAGE SOURCE DUAL LINK SINGLE LINK CAMERA COMPUTER ETC DISPLAY DUAL LINK SINGLE LINK DNDV _DC DISPLAY DUAL LINK SINGLE LINK DVI IMAGE SOURCE DUAL LINK SINGLE LINK CAMERA COMPUTER ETC 32 With the following results SDINI GROUP Note that dip switch S2 leaver 4 can be used in this mode to switch between mirrored output and non mirrored output Also note that a different bitfile will be needed for single link and dual link applications Important If for some reason noise exists on the screen or the clock is dysynched press the RESET button S1 33
7. 21 AH9 RX1_12C_SCL U22 V3 e TX0_I2C_SCL U6 U3 AF13 Note This attaches to both the SIL178 and J2 output e TX1_I2C_SCL U4 U8 AM10 Note This attaches to both the SIL178 and J3 output e TX0_CLKGEN_SCLK U31 L31 e TX1_CLKGEN_SCIK U32 L30 e MGTCG1_SCLK U44 J32 e TX0O_M_BYPASS_CLK AB5 Note Ignored by default see schematic for details e TX0_S_BYPASS_CLK AD5 Note Ignored by default see schematic for details e TX1_M_BYPASS_CLK AG8 Note Ignored by default see schematic for details e TX1_S_BYPASS_CLK AG7 Note Ignored by default see schematic for details e MICTOR_E_CLEK J11 F29 19 e MICTOR_O_CLKJJ11 E29 DIFFERENTIAL CLOCKS e DIMM_PLL_CKIN U53 AD7 AD6 e TX0_BUFR_FROM_FPGA U33 AB3 AA3 e TX1_BUFR_FROM_FPGA U27 AM3 AL3 4 4 Configuring the ICS8442s U31 U32 Note that the ICS8442 reference manual should be considered the authority concerning any of the ICS8442s The manual is available on the DNDVI CD as 1CS8442 pdf and also from the ICS website http www icst com datasheets ics8442 pdf VCO_SEL XTAL_SEL TEST_CLK XTAL_IN XTAL_OUT PHASE DETECTOR MR i nFOUTO nFOUT 1 Payer CONFIGURATION INTERFACE TEST S CLOCK nP_LOAD LOGIC Mo Ms NO N1 Note a ICS8442 simulation only Verilog model is included in the reference design The ICS8442 has two modes of operation Input from TEST_CLK or input from XTAL_IN OUT de
8. HDL DIFF_TERM gt TRUE VHDL port map VHDL I gt FOUT_P IB gt FOUT_LN VHDL O gt FOUT_IGDS 4 5 Configuring the CDCU877 U27 U33 U53 Note that the CDCU877 reference manual should be considered the authority concerning any of the CDCU877s The manual is available on the DNDVI CD as CDCU877 pdf and also from the Texas Instrument website http focus ti com docs prod folders print cdcu877 html http www s ti com sc ds cdcu877 pdf The CDCU877 can either be set in BYPASS mode where the input clock is sent directly to the outputs or in PLL mode PLL mode is set by holding AVDD to VDD 1 8V BYPASS mode is set by grounding AVDD Please see the schematic for details about which components to add and remove Removing a Ferrite bead and adding 0 Ohm resistors When editing the constraints file for a design make sure the CDCU877 inputs are set to LVDSEXT_25 And that DIFF_TERM is used on the input buffer See note on Schematic PO9_CLOCKS Example FOUT Verilog VHDL UCE settings UCF NET POUT LOC IOSTANDARD LVDSEXT_25 Verilog IBUFGDS Verilog DIFF_TERM TRUBE Verilog IGDS_FOUT Verilog 1GFOUT_P IBGFOUT_N O FOUT_IGDS VHDL IGDS_FOUT IBUFGDS VHDL generic map VHDL DIFF_TERM gt TRUE VHDL port map VHDL I gt FOUT_P IB gt FOUT_N VHDL O gt FOUT_IGDS NOTE By default the DDR PLL U53 is in BYPASS MODE and only used as a voltage le
9. I channel When not defined nothing happens to the transmitter define TXO_PATTERN_2560x1600 define TXO_PATTERN_1600x1200 define TXO_PATTERN_1280x1024 define TXO_PATTERN_640x480 Only one of the above should be defined at a time When defined they specify the test pattern resolution displayed on TXO if RX0O_PASSTHROUGH is not defined define H_MIRROR This turns on the MIRROR output option for the RX_PASSTHROUGH defines above The output will be the horizontal mirror of the input See later parts of this section for demonstration On S2 DIPSW4 is used to enable or disable output mirroring 6 2 Synthesizing the Reference Design Synthesis of the Dini Group reference design requires Synplicity s Synplify software If you don t have this software you should get Synplicity s 30 day evaluation softwate The reference design can be compiled using Xilinx s XST synthesis tool built in to ISE but may need to be modified Using Simplify Pro open the dn123_synp pryj synplify file included on the CD Make sure in the implementation options tab the correct Xilinx Part Speed settings have been selected Verify that the Verilog tab inside Implementation Options and change any Paths that have been defined to point to appropriate locations on the host system Run Synplify Create a new project in Xilinx ISE project navigator specify EDIF has the top level source Select the Synplify output as the Input design Make sure to
10. MPACT Choose Prepare a PROM File as the project action Target Xilinx PROM MCS file format and give it a filename Select an xcf32p as the PROM Device and add it to the list When it brings up the GUI and asks for a bit file give it your bit file generated by the ISE tools Don t add a second bit file because there is only 1 FPGA on the board Now generate the mcs output file by double clicking on Generate File Go check to make sure that the mcs file was created To program that mcs file into the Prom a Switch iMPACT to boundary scan mode b Initialize the JTAG chain It should find the xcf32p and the xc4vfx60 100 devices c Assign the mcs file as the programming file for the xcf32p d Bypass the programming file for the xc4vfx60 100 e Double click Program while the xcf32p is selected Make sure to select Verify Erase Before Programming and Load FPGA from the options given in the programming window Hit OR and wait for about 2 minutes until the programming has completed DNDVILDC User Guide Www dinigroup com 8 DNDVI_DC 10 Now when the board is power cycled it will automatically have the mcs file loaded into the FPGA 1 9 Check LED status lights The DNDVI_DC has many status LEDs to help the user confirm the status of the configuration process 1 Che
11. Sil 178 will handle all 24 bits of output When a dual link signal is applied the Master Sil 178 will handle the lower 12 bits and the Slave Sil178 will handle the upper 12 bits of each pixel Note while the Sil 178 is capable of both 24 bit and 12 bit input modes only the 12 bit input mode is available in dual link configurations Master D 11 0 l For frequencies less than or equal to 165MHz For frequencies greater than 165MHz the Multimedia Controller is sending both EVEN Multimedia Controller is sending only the and ODD data to Master device only EVEN data to the Master device l pI11 0 For frequencies greater than 165MHz the Multimedia Controller is not sending any data Multimedia Controller is sending only the ODD to the slave It is powered down i data to the Slave device It takes the Slave out l of power down mode l l l wr COO OS oe a Edge OR l l IDCK Dual Clock I IDCK Slave PD bit must be set to 1 by this period Slave PD bit Figure 15 Single Dual Link Timing Diagram The I2C address of the Master Si1178 is 0x70 and the address of the Slave Sil178 is 0x72 Only after writing to 0x70 register PD set to 0 this must be done after every reset see Sil178 manual for explanation 6 Reference Design This section will discuss the options available in the reference design along with the steps needed to generate bit files from the referenc
12. THE DINI GROUP DVI DAUGHTER CARD User Guide DNDVI DC LOGIC EMULATION SOURCE DNDVI DC User Manual Version 1 1 The Dini Group 1010 Pearl Street Suite 6 La Jolla CA92037 Phone 858 454 3419 Fax 858 454 1279 support dinigroup com www dinigroup com Last Modified 8 3 2007 11 12 51 Last saved by jthurkettle Welcome to DNDVI DC Daughter Card Congratulations on your purchase of the DNDV1I_DC Daughter Card l User LED s l To confi g debug Virtex4 FPGA FX60 FX100 j NI Sa a ie te ee ee a i l Oo O i log DNSODOKIO o OS eN JE 125 abis 100 DN7000K10 Rocket I O 1 JTAG l DN8000K1 OPCI l Fey O E SIL178 DVI Output l i Dual Link I I I I Ga i es FPGA Configuration FF1152 DVI Input Switching 3 44 yy 200MHz i Dual Link SIL163B Regulator f x DDR2 SODIMM Switching Regulator ii up to 1GB addressing Logic 32 Analyzer Mictor Switching 1 2V Regulator f I i z RS232 L Switching 43 3V l 2 Channels Regulator l E ns N High 1 4 with FX100 l l 5V Switching y s i i 1 8 ee Regulator j Era l differential i er External Power Cable 4Ch Butter Zn feon i 12V Connector l annes I i QSE DP 6 with FX100 l l l QUICK START GUIDE 1 Quick Start Guide The Dini Group DNDVI_DC is the user friendhest board available with a Virtex 4 FPGA and two DVI interface 1 1 What s provide
13. ck the power voltage indication LEDs to confirm that all voltage rails of the DNDVI_DC are present The LEDs indicate the presence of 12V 5V 3 3V 2 5V and 1 8V 2 Check the Configuration status LED When the FPGA has been successfully configured the FPGA_DONE LED will iluminate You should also verify the fan mounted above the Virtex 4 FPGA is spinning 1 10 Finished Quick Start At this point either a reference design is loaded or a user supplied design is loaded in the DN_DVI board If you wish to verify the reference design move on to chapter 2 DNDVILDC User Guide Wwww dinigroup com 9 DNDVI_ DC 2 Testing the Reference design using the Included software To test the reference design on the daughter card the DNDVI_DC provides tests for the following options out of the box e DVIRXO RX1 TXO TX1 e 200 pin SODIMM socket e RS232 Loopback e Rocket IO The 4 DVI connectors allow single link and dual link digital video to be received and transmitted The RS232 interface allows low speed data transfers to and from the User design A DDR2 SDRAM SODIMM can be installed in the 200 pin SODIMM socket or one of our other cards SSRAM FLASH Mictor can be installed instead The 200 pin header can be used to connect the DNDVI_DC to many of the DiniGroup FPGA emulation boatds check http www dinigroup com for the compatibility list This section will get you started and show you how to operate the provided s
14. d First let s examine the contents of your DNDVI_DC kit It should contain e DNDVLDC board e RS 232 IDC header cable to female DBI e CD ROM containing O Virtex 4 Reference Design o User manual PDF o Board Schematic PDF o DNDVL_DC firmware DNDVI_DC User Guide Www dinigroup com DNDVI_DC The Dini Group can optionally provide the following accessories e Memory modules for use in the DNDVI_DC DDR2 SODIMM socket QDRII SRAM 64x1 Mb 300Mhz Flash memory 32x4Mb 2x4Mb serial flash Reduced Latency DRAM RLDRAM 64x8Mb 300Mhz Standard SRAM 64x2M Select ZBT sync burst Pipelined Flow through Test connection module with two Mictor38 You may also want to obtain from a third party vendor e Xilinx Parallel Cable IV or Xilinx Platform Cable USB e 200 pin DDR2 SODIMM e Synplicity Identify or Xilinx Chipscope for embedded logic analyzer functionality e LCD monitor with DVI input Any DVI 1 0 compliant monitor should suffice e Video card with DVI output e Video camera with DVI output 1 2 Precaution The DNDVI_DC is sensitive to static electricity so treat the PCB accordingly The target markets for this product are engineers that are familiar with FPGAs and circuit boards However if needed the following web page has an excellent tutorial on the Fundamentals of ESD for those of you who are new to ESD sensitive products http www esda org basics partl cfm There are four ground test points on th
15. e DNDVI_DC The DNDVI_DC has been factory tested and pre programmed to ensure correct operation You do not need to alter any jumpers or program anything to see the board work A reference design is included on the provided CD The 200 pin connector is not 5V tolerant According to the Virtex 4 datasheets the maximum applied voltage to these signals is VECO 0 5V 3 0V while powered on These connections are not buffered and the Virtex 4 part is sensitive to ESD Take care when handling the board to avoid touching the daughter card connectors DNDVILDC User Guide Wwww dinigroup com 4 DNDVI_DC 1 3 Power On Instructions The image below represents your DNDVI_DC You will need to know the location of the following parts referenced in this chapter in Bc FS Fi a FEE ees a EN i o nuntem 4 SC ya pes oe PUGET iin amp LALE rages DS1 10 LEDS REV SEL 2 TTET mime mmm seo LI s gt g ST amp 2 lt epu esl 9 To begin working with the DNDVI_DC follow the steps below 1 4 Verify Switch Settings The DNDVI_DC uses a DIP switch to program the FPGA configuration circuitry The function of these DIP switches is listed in Table 2 Verify that the switch settings on your board match the default settings DNDVILDC User Guide Wwww dinigroup com 5 DNDVI_DC Table 1 Switch Description Switch Default Signal Name On setting Of
16. e design using standard development tools The reference design provides an example interface to the RS232 port DVI ports and DDR2 module port The provided design files can also be used to test the process of generating FPGA programming files and loading them into the FPGA 6 1 Reference Design Verilog Files Included on the CD are the Verilog files for the reference design The top level file U1_fpega v has several defines which determine the behavior of the design define SETUP 8442 When defined the 8442s are configured define EXPCONIO_TEST When defined the 200 pin header is active and will respond to the daughter card header test This is used internally in the Dini group to verify functionality of the header If one desires to use this test one will need a host card such as the 8000k10pci configured with the matching end of this test define INCLUDE_DDR2_LOGIC When defined the DDR2 test is enabled define DDR2_ LEDS When defined the LEDS are used to indicate states of the DDR2 test define DDR2 MICTOR _ DEBUG When defined the mictor connector will hold the data returned from a invalid ddr2 read if one exists This is used internally 30 define RXO_ PASSTHROUGH When defined the RXO DVI channel will be shunted to the TXO DVI channel When not defined TXO will generate a basic test image define RX1_ PASSTHROUGH When defined RX1 DVI channel will be shunted to the TX1 DV
17. f setting Position CFG_REVO When CFG_REVSEL is ON CFG_REVO CFG REV1 and CFG_REV1 are used to select the design revision to be enabled overriding the internal aa oe CFG_REVSEL programmable revision selection control bits S14 Jof DIPSW4 Configurable Configurable p i 3 3 gt 3 o E Mi if H ia 7 sie 1 5 Memory and heat sinks There should be an active heat sink installed on the FPGA on the DNDVI_DC Virtex 4 FPGAs are capable of dissipating 15W or more so you should always run the board with the heat sink installed The DNDVI_DC comes packaged without memory installed If you want the Dini Group reference design to test your memory module you can install it now in the 1 8V DDR2 DIMM socket DNDVILDC User Guide Wwww dinigroup com 6 DNDVI_DC The socket DDR2_SODIMM can accept any capacity DDR2 SODIMM Note that DDR1 modules will not work in these slots since they are supplied with 1 8V power and DDR1 requires 2 5V power and a completely different pin out Note that the Dini Group has a DDR2 module that provides a DDR1 socket even so changing all the voltages would still be required 1 6 Power Up Procedure 1 Plug the four pin hard drive power connector from the power supply into P2 Make sure your work area is clear and there are no metal wrenches under the board Turn on the power supply When the DNDVI_DC powers on it automatically loads Xilinx FPGA design bit file
18. hannel SYNC Decoder Interface ee HSYNC Data a SYNCO 0 VSYNC SCDT CTL 3 1 pom Figure 1 Functional Block Diagram QE 23 0 QO 23 0 a D Rg amp ys Z O O PDO STAG_OUT ISYNC ST The DNDVI_DC board has two Sil 163B chips per receiver channel One Sil 163B is designated as the MASTER and one as the SLAVE When a single link signal is applied to the receiver the MASTER Sil 163B will handle all 48 bits of output When a dual link signal is applied the Master Sil 163B will handle the even 24 bits and the Slave Sil163B will handle the odd 24 bits NOTE The slave is bit reversed Master is in Single Link a i Two Pixels Clock Mode Master is in Dual Link One Pixel Clock Mode M ster is outsuttin i Master is outputting Even pixels Master has Tri P J Stated its Odd pixel bus to allow Slave to output both Even and Odd i Odd pixel data pixels Panel DO 23 0 DO 23 0 DO 23 0 DO 23 0 DO 23 0 DO 23 0 DO 23 0 Slave is not Active Slave is in Dual Link One Pixel Clock Mode Master ODCK Outputs are Tri Stated Slave is outputing Odd pixels 2 pixeliclock rd rT LTr Mode System is sending Data only to the Master Only System is sending the Even pixel data to the clock is sent to the i Master and the Odd pixel data to the Slave Slave i Slave SCDT a es Master S_D Figure 14 Single Dual Link Timing Diagram In the above diagram DE is RX _QE_ 23 0
19. ide of R325 This is not reflected in the schematic 3 2 Multiplexed Serial Port a3338 iii a i _ aak The DNDVI_DC has one serial port P3 for user use No configuration is required to enable the first serial port This can be extended to two serial ports by use of a breakout serial cable LED5 and LED6 are tied to the second serial ports TX and RX respectively Serial port 1 uses pins 2 and 3 Serial port 2 uses pins 6 and 7 of port P3 To enable the second RS232 Port Add the following 0 Ohm resistors R350 R352 R362 R360 This will enable the second serial port on pins 6 and 7 on P3 For more details see page 07 in the Schematic P07 MISC PERIPHERALS 15 4 Clocking Overview This chapter discusses the various clocks available on the DNDVI_DC and any user settable options available DIMV_FPGA_FE EXPCO_CLKIN 4 900 Pin EXPCON_CCLK gt l Daughtercarc EXPCON_DCLK y Header Pz EXPCON_ECLK _9 DV Si 163B RX 1 EERO ye RXC_CLK RIC CLk FWE DV 1 Si163B TXC_CLKGEN_SCLK l Rx RPAH y Re _CLk px clk FW Tx _CLKGEN_SCLk
20. oftwate 2 1 DVI reference design The FPGA is initially programmed with a reference design that will recetve DVI video on RX0O and send it back out on TXO The RST switch may need to be applied after changing input frequencies The same is true for RX1 and TX1 DNDVL DC User Guide Www dinigroup com 10 ON_DVI SELF LOOPBACK DVI PASSTHROUGH EXAMPLE There is also sample code that can be un commented in the reference design that will generate a simple video output pattern without requiring a DVI input cable connected to RX0 11 DVI MONITOR iat D DVLRXI ZN NOTE If you are using a dual link signaling you MUST use dual link DVI cables Dual link DVI cables can be identified by the pin out on the connector DVI I Single Link DVI I Dual Link DVI D Single Link 2 2 Communicating to the User Design over the Serial Port You may want to communicate with your design over the user serial port P3 Connect a RS232 cable to P3 the FPGA RS232 The reference design is programmed to digitally loop back the input to the output No hardware flow control is supported If on the terminal you see a local echo then the 12 reference design was able to capture the RS232 signal and generate an RS232 signal that your computer could capture com1_19200_n81_noflow HyperTerminal rs DB xj File Edit View Call Transfer Help Dle al 3 ala l loopback test echo echo_ OT C
21. onnected 00 00 36 autodetect t92008 N 1 SCROLL CAPS uum Capture Print echo The provided test design automatically runs a DDR2 memory test with status indicated by the LEDs After reset LED 5 will go high for approximately 20 seconds followed by LED indicators of the memory test LED10 9 indicate test stage 00 indicates initial stage 01 indicates write read test 10 indicates read back test 11 indicates successful completion of tests If an error occurs the LEDS will indicate which test failed and indicate the LSB of error in the memory 13 2 4 RocketiO TEST On the CD accompanying the DNDVI board in the bit file directory one can find the RocketlO MCS file Load the MCS file into the PROM following the steps outlined in section 2 5 Connect SMA cables in loop back configuration on all eight of the RocketIO pairs That is to say connect TXP to RXP and TXN to RXNJ Reset or power on the board after all the connections have been made If test passes all 10 LEDS should flash on and off The image above shows the loopback configuration for pair 3 The following is an explicit list of pair matching 012 J13 23 714 24 J34 J25 J35 J36 J38 37 39 J26 J15 J27 J16 28 J40 J29 J41 17 742 18 J43 30 J19 31 J20 32 J21 33 J22 14 3 DNDVI_DC Hardware 3 1 ERRATA Please note On the Revision 1 0 boards a jumper wire has been added to the bottom of the board between R244 and the non power s
22. pending on the setting of XTAL_SEL By default XTAL_SEL is set to 1 XTAL_IN OUT to switch the input into the 8442s see the Schematic one will need to move a configurable resistor going into XTAL_SEL The FOUT frequency is governed by FOUT F_LIN M 24N Where M is an integer and N is a power of two FOUT is a LVDS differential signal and must be treated as such when being incorporated into the Verilog VHDL design Only serial configuration is supported on the DN_DVI board which means the 8442 needs to be configured each time the board is reset SERIAL LOADING l l In addition to the above discussed N and M inputs T configures the TEST output a pattern of 1 1 will set TEST to FOUT Note that the SDATA and SLOAD are the same for all the ICS8442s on the DNDVI board and that each ICS8442 can be programmed separately by control of the individual S_CLOCK signals Please see the schematic for specific ICS8442s The maximum frequency allowable for S_CLOCK is 50MHZ LVCMOS When editing the constraints file for a design make sure the ICS8442 inputs are set to LVDSEXT_25 And that DIFF_TERM is used on the input buffer See note on Schematic PO9_CLOCKS Example FOUT Verilog VHDL UCFE settings UCF NET FOUT LOC IOSTANDARD LVDSEXT 25 Verilog IBUFGDS Verilog DIFF_TERM TRUE Verilog IGDS_FOUT Verilog I FOUT_P IB FOUT_N O ROUT_IGDS VHDL IGDS_FOUT IBUFGDS VHDL generic map 21 V
23. stored in the PROM if the load FPGA option was selected during PROM programming To load a different Xilinx bit program file into the DNDVI_DC follow the steps outlined in section 2 4 1 7 Loading FPGA configuration once The DNDVI_DC reads FPGA configuration data from the JTAG chain To program the FPGA on the DNDVI_DC FPGA design file with a bit file extension are uploaded through the JTAG chain This can be accomplished using the Xilinx ISE iMPACT tool Step by step instructions for loading bit file into the FPGA via iMPACT 1 Attach the Xilinx JTAG cable to J8 on the DNDVI_DC 2 Start iMPACT DNDVILDC User Guide Wwww dinigroup com 7 DNDVI_DC 3 Create a new project in iMPACT file gt new gt create new project 4 Choose Configure devices using Boundary Scan JTAG as the project action 5 Bypass the first Assign New Configuration File pop up menu 6 Select the FPGA design bit file in the second Assign New Configuration File pop up menu 7 Right click on the FPGA in the JTAG chain display select program and then OK at the Programming Properties menu 1 8 Loading FPGA bitfile into the PROM There is an XCF32P Xilinx FLASH PROM on the board to allow the FPGA to automatically be programmed when the board is powered on To use this feature the ISE tools must be version 7 1sp3 or newer 1 2 Attach a Xilinx JTAG cable to J8 on the DNDVI_DC Start IMPACT Create a new project in i
24. vel shifter 4 6 Configuring the ICS843020 01 U44 Note that the I1CS843020 01 reference manual should be considered the authority concerning the ICS843020 01 The manual is available on the DNDVICD as ICS843020 01 pdf and also from the ICS website http www icst com datasheets ics843020 01 pdf BLock DIAGRAM VCO_SEL XTAL_SEL TEST_CLK XTAL_IN c XTAL_OUT P_DIV Float 1 default 1 4 PHASE DETECTOR 2 MR veo pFOUTO nFOUTO FOUT1 nFOUT 1 S LOAD S DATA _ tm CONFIGURATION s_cLock gt INTERFACE gt TEST nP LOAD __ i LOGIC ig MO M8 NO N1 The ICS843020 01 has two modes of operation Input from TEST_CLK or input from XTAL IN OUT depending on the setting of XTAL_SEL By default XTAL SEL is set to 1 XTAL_IN OUT to switch the input into the ICS843020 01 see the Schematic one will need to move a configurable resistor going into XTAL_SEL The FOUT frequency is governed by FOUT F_IN M 24N P_DIV Where M is an integer and N is a power of two and P_DIV is 1 4 or 8 FOUT is a LVDS differential signal and must be treated as such when being incorporated into the Verilog VHDL design Note that by default P_DIV is floating to change the value of P_DIV see the schematic for which resistor to remove Only serial configuration is supported on the DN_DVI board which means the 1CS843020 01 needs to be configured each time the board is reset SERIAL LOADING l l In addition to the
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