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CHAPTER 1 - HARMAN Luxury Audio Group

Contents

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3. E DRAFTER NOE REV DESCRIPTION 1 CHANGED PER DCR 021030 00 CW 11 20 02 11 26 02 CLC 1 25 02 6 11 26 02 CHANGED PER DCR 030317 00 RWH 5 21 03 CW 5 22 03 CLC 5 22 03 MAG 5 22 03 3 ADD LUGI DETAIL PER DCR RWH 7 1 04 CW 7 1 04 040624 00 CLC 7 1 04 MAG 7 2 04 41701 09640 KEYSTONE MOUNTS ON BACK WITH SHORT SIDE OF BRACKET ON PCB SCRW 4 40X1 4 PNH PH BLK NOIES 640 0231 1 LEXICON BOM NUMBER 023 15621 SUPER SEDES ANY INFORMATION ON THIS DRAWING 2 ALL COMPONENTS TO BE INSTALLED FROM TOP SIDE OF PCB 3 LEAD PROTRUSIONS 100 MAXIMUM FROM BOTTOM SIDE OF PCB 4
4. gt X I r 812 gt 72 8 R232 1612 2612 rteu 2512 0512 0184 6712 9512 315X 092 183
5. 8 7 6 5 4 3 2 1 REVISIONS REV DESCRIPTION DRAFTER QC ANALOG BOARD CONNECTORS ow 5VD 1 1 CHANGED PER DCR 020913 00 _ CAM MAG RS 232 TRANSCEIVER RS 232 11706 02 12 20 02 RWH CW MAX202E FEMALE RESET oey 2 2 CHANGED PER DCR 030307 00 eee eu A 2 1 4 7K 47 9 82 LATCH 4 MAG cis V DE9F 9 B2 SCLK 5 5 14 03 5 20 03 See s 6 CHANGED U52 PER DCR 030307 00 A ud ON D AST 16 11 25 ADA SDATA OUT 5 5 22 03 5 22 03 772 elyce ci i 9 B2 7 L C31 9 9 82 5 22 03 5 22 03 1 25 W2 9 AB RWH ECM 15 4 10 4 CHANGED PER DCR 030626 00 GND C2 1 9 2903 10 9 03 Tead 165 11 TUN RDS CLK 2 TXD_A 12 TUN RDS DAT 9 02 CAM MAG 12T 5 1 12 LRDS DAT mw 19 62 10 2 03 10 9 03 v C2 Wi 4 RWH CW RE
6. 7 6 5 4 2 1 REVISIONS REV DESCRIPTION DRAFTER Q C 3 3V CHECKER AUTH 3 3VD RWH CW i 1 CHANGED PER DCR 020913 00 11 08 02 12 20 02 CAM MAG 11 06 02 12 20 02 4 RWH CW A 2 CHANGED PER DCR 030307 00 5 2 03 5 20 03 C33 C35 C37 C57 C63 C64 C68 C80 C124 C136 C145 C150 CAM MAG 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 5 14 03 5 20 03 RWH ECM D i i i 1 4 3 CHANGED PER DCR 030626 00 9 29 03 10 9 03 4 CAM MAG C32 C36 C56 C61 C62 C70 C79 C103 C107 C135 C154 C164 10 2 03 10 9 03 01 25 01 25 01 25 01 25 01 25 01 25 01 25 01 25 01 25 01 25 01 25 01 25 RWH CW 4 CHANGED 39 134 PER ECO 040422 00 42704 429 04 4 29 04 5 2 04 C34 C38 C58 C69 C81 C106 C137 C146 C147 001 50 001 50 T 001 50 T 001 50 T 001 50 001 50 T 001 50 T 001 50 T 001 50 pe 4 4 4 4 4 4 4 tL c78 C139 470 16 T 470 16 pyn c39 d C1
7. 8 7 6 5 4 2 1 REVISIONS DESSEN DRAFTER BET PRO CHECKER AUTH RWH CW 1 CHANGED PER DCR 020913 00 PN MAG 11 06 02 12 20 02 RWH CW 2 CHANGED PER DCR 030307 00 8 MAG 514003 5 20 03 RWH 3 CHANGED PER DCR 030626 00 0 10 2 03 10 9 03 3 3VD BEF EE VDDQ VDD paq 23 DSPA A14 N K4 C15 DSPA D31 56 Bao 22 ADDR23 DATA47 5i DSPA D30 54 0031 24 DSPA AD10 NC L3 ADDR22 DATA46 C14 DSPA 029 53 0030 10 66 AO K3 ADDR21I DATA45 D15 DSPA_D28 51 0029 9 65 8 NC Li 20020 DATA44 E14 DSPA D27 50 0028 64 DSPA A7 200819 DATA43 DSPA D26 48 0027 63 DSPA NC L2 ADDRI8 DATA42 15 DSPA D25 47 0026 62 DSPA 5 ADDR17 DATA41 S 0025 5 z 3 3VD NC MI F13 DSPA D24 45 61 DSPA A4 A NC ADDR 16 40 E73 023 42 0024 4 60 ADDR15 DATA39 0023 Ai4 Ni F14 D22 40 27 DSPA A2 DSPA A13 ADDR14 DA
8. 8 7 5 4 3 2 1 CLOCK BUFFERS REVISIONS u91 MAIN FS256 9 8 R396 REV DESCRIPTION DRAFTER Q C CONNECTORS TO AMPS DIGITAL CONNECTOR u ILONA dud 3 3VD CHECKER RW FROM MAIN BOARD 1 1 CHANGED PER DCR 02110700 11 4 02 11 20 02 __ FRONT FB24 gt U91 CBV MAG 10 B2 e 18 3 3VD 11 2 R395 MAIN 11 20 02 11 21 02 R2957 40 1 Y p AMI RWH CW RA en 1 39 MAIN FS256 74LCX14 68 1 2 CHANGED PER DCR 030407 00 Baris cecus SS 3 38 095 R409 L 1 CBV MAG f 1 4 37 2 4 15 83 5 23 08 5 23 03 12 82 L SIDE FB22 5 35 741 1004 6841 091 3 CHANGED PER DCR 030729 00 AWE 8294 6 3 1 NE RIGS lesu 9 29 03 10 7 03 129 B20 AA FB23 ES suit iso gt ADE 5 A4 CBV MAG ATE 10 C7 15 C3 74LCX14 68 1 10 6 08 10 7 08 2 74K 32 MAIN 125 OUT2 11 C7 15 C3 43 3VD 1 RWH ECM vo 4 31 MAIN 25 OUT3 10715051 091 4 CHANGED PER DCR 031125 00 082 _
9. TORQUE 6 8 IN LBS NOTES 1 PART NUMBER LISTING IS FOR REFERENCE ONLY AND DOES NOT SUPERSEDE THE BOM 2 REFERENCE DRAWING 680 16422 FOR WIRE HARNESS DETAILS a 8 RING TERMINALS ATTACH TO SCREW TERMINALS ON PCB lt b 10 RING TERMINALS ATTACH TO BINDING POSTS 3 SOLDER TO 3 DEVICE LEADS 20 640 01710 SCRW 6 32 X 1 4 PNH PH ZN 6 19 680 16418 WIRE 16G 6 RINGX2 PC 170 150MM REF 18 680 16417 WIRE 16G 6 RINGX2 PC 80 150MM REF 17 023 15890 PL SPKR EMI FILTER BD ASSY 16 644 03668 WSHR LOCK EXT STAR 6 SS 4 15 680 16422 HARNESS AMP 3CH 1 14 641 16288 SCRW TAP 6 32 X 312 PNH TORX ZN 20 13 643 16290 NUT 6 32 KEP CONICAL WSHR ZN 12 630 16283 WSHR SHLDR 312 SHNK 6CL NYL 4 11 023 15824 PL AMP BD ASSY 3CH 1 10 630 16284 SPCR 6CL X 090 25 RD NYL 4 TORQUE 6 8 IN LBS 9 702 16427 PLATE AMP 3CH 1 8 640 16298 SCRW 6 32 X 25 PH ZN 2 7 490 16280 CONN POSTX2G 10 32 RED BLK 3 6 022 16448 PL HS ASSY DBL POS m 5 022 16449 PL HS ASSY
10. 5 DRAFTER Dv of REV DESCR AUTH 701 09640 5 RWE W MOUNTS ON BACK WITH EIS i E B D 2 2 D E F B R A C 1 1 6 2 1 6 Q 2 RWH CW CHANGED PER DCR 5 2 09 5 20 03 G 3 _ 4 40 1 4 PNH ZN 2 530307 00 ane uic m 5 19 03 5 20 03 640 01701 SFF NOTE 8 RWA CW CHANGED PER DCR 5 22 03 5 22 03 030307 00 ale AG US _ um RWH ECM 1 CHANGED PER DCR 9 30 03 10 9 03 030626 00 CLC AG T 10 6 03 10 9 03 id idi p J3 15 J6 J7 5 i 5 CHANGED PER ECO 4 21 04 4 29 04 cg 040422 00 CLC 05 06 09 c 2 c Ti c pes R26 s 7 214592144 03 850 52 O 02 ADDED LUGI DETAIL 7 7 04 T T E SERRER PETET DCR 040624 00 CLC MAG u aS 1 1 04 1 2 04 C26 C37 5 R19 RI6 R19 R20 C38 A 06 c l U8 U9 C39 um S Rl TE I SEE C33 1 m ei Es n CAO OSCA O B D F H K M P C
11. 8 6 5 4 3 2 1 5VD eub REVISIONS 4 REV DESCRIPTI DRAFTER ON Q C TAVECT245 CHECKER AUTH CPU WRDCLK MON VCC 1 AWE cw UA CPU WRDCLK vee le CHANGED PER 020913 00 1 B8 lt 2 2 3 NG LVKYBDIRQ xd CAM MAG CPU DSPABIRQ B3 11 06 02 12 20 02 1 88 15 B4 A4LS LVDSPABIRQ 2 CHANGED PER DCR i RWH cw 1 08 4 CPU VIDTUNIRO 1485 As LVCRYIRQ 5 2 03 5 20 03 1 08 lt B6 67 LVVIDTUNIRQ 2g x NE xe ume 88 nom CHANGED P RWH G DIS GED PER 030626 09 10603 D DIR MAG GND HO 10 2 03 10 9 03 U37 777 MAINS_RLY SOFT RLY PE 5VD 74VHCT245 CPUDATAT 15 20 1 D3 7 A5 15 0 CPUDATAO LVDATA0 LVDATA 15 0 60 1589 AST LVDATAS CPUDATA4 14 84 M g LVDATA4 CPUDATAS 13 85 LVDATA5 CPUDATA6 12 86 6 LVDATA6 CPUDATA7 11 82 7 LVDATA7 AB ig apy 1 RES BUFDIR 036 777 1 83 9 C8 m CPUCS2 3 3VD 74VHC273 C 20 vec CPUDATAO 3 2 CPUDATAG 102 DSPARESET CPUDATA2 726 205 DSEBR
12. n m m m gt m gt w o uw pm 52 elo es S us i Y RY1 2 2 D 20 D D D 9 w Ww w Aj App gru 118 eeu le oul gzuJ 2 o w reu 2 C65 VL 982 268
13. REV FSCRIPTION DRAFTER CHECKER Q C AUTH 4 RWH 9 19 03 CW 11 17 03 1 CHANGED PER DCR 030821 00 Sear 9 26 03 LED MOUNTING DETAIL SEE DETAIL 37 PLCS TOP OF 7 SIDE VIEW NOTES prd ANODE Nu Lo ER 14 OK BOTTOM VIEW LEXICON BOM NUMBER 023 15616 SUPERSEDES INFORMATION ddl xd cL MEL ON THIS DRAWING 2 COMPONENTS TO BE INSTALLED ON BOTH SIDES OF PCB T E i i 3 LEAD PROTRUSIONS 100 MAXIMUM FROM CIRCUIT SIDE C R3 R4 i R23 sl EH OF PCB 4 UNLESS OTHERWISE SPECIFIED MOUNT ALL COMPONENTS FLUSH AND PERPENDICULAR 90 1 TO PCB Ky 55 e UR gt NR 5 PCB ASSEMBLY TO BE PACKAGED IN STATIC SHIELDING us ES 2104 EE FARADAY CAGE BAG THAT HAS AN ANTI STATIC NON CONDUCTIVE INNER LAYER ALSO THE ASSEMBLY IS TO BE S PROPERLY PACKAGED TO PREVENT ANY DAMAGE DURING SHIPMENT m m 22 6 SOLDER PASTE MASK PER LEXICON DOC NO 030 15567 Ps 22 7 BREAK AND CUT 55 FLUSH WITH EDGES THROW OUT BLANK MATERIAL AFTER SOLDERING AND P
14. 8 7 6 5 4 2 1 REVISIONS 5VV 5 DRAFTER 3 3VD Bom SY D amp REV DESCRIPTION CHEGKEE VIDR B C8 MAX4310 R144 RWH Cw ief 74HC4051 y 2 3 1 CHANGED PER DCR 030106 00 1308 13 SHDN VCC 15K ECM MAG 1 A6 3 D8 4 D8 OSD Y IN 5 C8 7 D8 7102 050 SY OUT 4 iNo 13 ALONE 3 D8 RWH 1 A6 3 D8 4 D8 As m ND our s SY_MAIN1 2 CHANGED PER DCR 030421 00 2003 IN1 75 0 ECM MAG 1 A6 3 D8 4 D8 5VV 5VV 1 5 20 03 5 22 03 FB A0 VEE i RWH Cw 5 Uis 3 CHANGED PER DCR 030623 00 10 8 03 ort ejas 7 1 6 ECM MAG 9 03 MVID SEL0 1K 024 10 9 03 MVID_SEL1 10 9 C3 SEL2 9 R206 R138 9 C3 100K d 3 3K 2N3906 0 03 6 9 83 m AW BW C129 7 1229 MEM SC MAINI D 10 16 1 196 5 MAX4310 8141 5VV U28 Sonn 5VV 5VV T SHDN VCC e 3 3VD A 7 C2 OSD_C_OU ji 15y R205 R14 gt ourl8 R142 SC I 4 3 11 0K 750 1 25 2 13 R208 150 Vs Q7 1 8207 1 1 C3 3 C8 4 C8 5 4 14 780 36K R18 1 C3 3 C8 A CB PR U15 9 09 SY1 1 5VV 1 gt 1 23 3 28 4 28 NC 5 OUT IN R16 817 5VV
15. 8 7 5 4 3 2 1 REVISIONS REV DESCRIPTION DRAFTER Q C M CHECKER AUTH 15V 15V LEFT ANALOG INPUTS 1 OdBFS 4 0Vrms m Hd 1 CHANGED PER DCR 021107 00 11 14 02 11 20 02 11 CBV MAG 18 1473 11 20 02 11 21 02 R15 C59 MAIN SOURCE SELECT LEFT RWH OW 1 R77 47 GND V 2 CHANGED PER DCR 030407 00 4 RCA 100 D15 10 25 AUR 5151 CBV MAG J15 8 1 4W 99 56 8 52 5 23 03 5 23 03 J 5153 RWH CW 4 y gt a 17 154 018 LEFT MAIN IN 3034081 3 CHANGED PER 090729 00 9 29 03 10 7 03 11195 g CBV MAG 1 56 10 6 03 10 7 03 9 57 RWH ECM L EE 9137 4 CHANGED Sh 6 10 13 15 PER DCR 031125 00 4514 04 4 80 04 li 15V A0 Ai A2 EN CBV MAG i Ubi 1 30 04 2 2104 R13 1 76 15 2 5 CHANGED SH 10 13 amp 15 PER ECOS Po 2 R73 2 D5 14 D3 SELO CBV KAB turpem js Dips 14 D3 MAIN ANLG 040408 00 amp 040421 00 004 mE B 14W 56 2 05 14 03 SEL2 RWH CW J14 6 CHANGED SHTS 10 13 PER ECO 040526 00 6 14 04 6 16 04 627 MAIN_ANLG_EN SURE 2 05 14 03 CBV MAG 6 1404 6 21 04 15V 15V n 13 14 3 06408 V GND V REC SOURCE SELECT LEFT em 3 R69 6153 100 N 7
16. p 1 OO gt 2 Front L R Direct Analog Path 3 oo d gt 5 4 gt sw Front L R _ gt 2 gt oo MOYO O gt 5 DAC gt sw 1f WY A K gs E gt gt un AD Ctr Sub Mux QO 7 MUX Level main clks eee COs cH papas P 22 MOO gt Tuner DAC gt sw 4 1 gt Phono 5 sw to from Side L R Mux gt Phono _ Sw Main Bd Side L R 75u Mic1 2 sw DAC T sw g e w BA Side Rear Mux 1 2 sw AD hono T Level Rear UR bo NA EN ESEA y data gt DAC d gt sw q w Mc 4 Y Pr eamp 1 2 gt 67 gt 3 0 145 Amps Tuner gt sw 67 Module ________ Headphone dI HRS HDP pros In addition a 5 1 channel source can be selected for the Main audio path There are two possible methods of getting a 5 1 source into the box Refer to the Main Audio Paths 5 1 Channel Input block diagram on the next page 6 4 Lexicon 1 An S PDIF signal may be encoded in Dolby Digital DTS format and pass through a decoder that outputs the 5 1 channels These channels are then passed along to the DSP and sent to the analog board 2 Two sets of three
17. 7 6 5 2 1 REVISIONS REV DESCRIPTION DRAFTER CHECKER AUTH 1 CHANGED PER DCR 020913 00 PN MAG 11 06 02 12 20 02 2 CHANGED PER 030307 00 uM pecus CAM MAG 3 3VD 5 14 03 5 20 03 3 CHANGED PER DCR 030626 00 0 10 2 03 10 9 03 R73 10K DSPASEL A4 2 775 enun es B9 DSPABLDATA7 DSPASPICLK DSPABLDATA6 o a g DSPARXD D10 DSPABLDATAS DSPATXD D4 A9 DSPABLDATA4 8 28 9 22 MISO LODATO4 A BEDAE ATAS LODATO3 SPORT CLK A D9 1 DSPABLDATA2 gt SPORT FS A PS DSPABLDATA1 Pye DSPASPSFPGA DSPABLDATAO D3B 510 45 LOCLK ADSP 21161N DSPA2DSPB FS2 LOACK 3 3VD DSPB2DSPA 87 02 SPLBLOGK DSPBALDATA7 D2B A12 DSPBALDATAG NC B6 D12 DSPBALDATAS NC rra BATA B12 DSPBALDATA4 NC C6 C12 DSPBALDATA3 R74 R140 NC De 14 DSPBALDATA2 10K 10K D1B LIDATO2 L1DATO1 DS scu DSPBALDATA0 FS0 DSPASPOFPGA E4 C DOB B13 L1ACK 016 DSPBSEL A4 22 B9 DSPBALDATA7 DSPBALDATA 7 0 9 C2 SPIDS LODATO7 E9 B4 SPICLK LODATOG 510 D
18. 8 7 6 5 4 2 1 REVISIONS REV DESCRIPTION DRAFTER QC CHECKER AUTH 1 CHANGED PER DCR 021107 00 BUM CBV MAG 11 20 02 11 21 02 2 CHANGED PER DCR 030407 00 ESOS CBV MAG 3 3VD 3 3VD 5 23 03 5 23 03 RWH CW XC9572XL 3 CHANGED PER 030729 00 26 VOCIO1 VOCINTI 5 MAG 38 VCCIO2 VOCINT2 57 10 6 08 10 7 03 51 VCCIOS VCCINT3 5 3 VCCIOA MAIN ANLG SELO i fpa MAIN ANLG D eod 9 91 MAIN ANLG SEL2 ad 03 5 MAINZ ANEG SEN 1 D5 2 D5 0 04 10 MAIN PHONO SEL SO x Loss MAIN TUNER SEU 22 05 12 MAIN 75 SEU 4 10 04 11 D3 12 D4 14 03 gt MAIN DACOUT SEL L SE MAIN DIRECT SEU 2 13 MAIN_MIC_SEL i 15 M 74VHC04 Ne 7 o 10114 REC ANLG SELO 1 C5 2 C5 NC 19 010715 ANLG NC 24 2 9 1 1 16 SEL2 E NC NC 4 747 ANLG EN sO s des NC 43 ae EE REC PHONO SEU Ss NC 46 14 20 SEU 46 INC 6 15 3 B5 B D4 14 63 SEL REC DIRECT SEU NO 73 7 07128125 REC AD DAC SEU EU 74VHC04 NC 0 17 LAMP 15 A8 29 ZONE ANLG SELO m 30 ZONE ANLG SELI BOE 021732 Z
19. 8 7 6 5 4 3 2 1 REVISIONS REV DESCRIPTION DRAFTER CHECKER AUTH RWH CW 1 CHANGED PER DCR 030106 00 1415 08 3 3VD 1 21 03 43 RWH CW 2 CHANGED PER DCR 030421 00 250705 FB8 3 3V REGULATOR 5 20 03 5 22 03 is RWH CW 3 3VD_E D6 E vssx E48 3 CHANGED PER DCR 030623 00 En eis VDDI VSSI 05 5VV 3 3VD 10 9 03 VDDE E VSSL ETFEZ 1 VSSE E 4 D5 VDDA EO 12 Fre 1N4002 LMS1585A SAA 7109E vssA 88 4 CASEEVOUT VIN VOUT N13 TO 220 VDDA _ st N12 C96 GND C97 VDDA D1 VSSA 4 VDDA 02 POWER BLOCK GND NI 1 25 i U24 10 10 298 9 VSSA VSSA D4 VSSA ps M H4 VDDE DO VSSE VDDE D1 VSSE D1 m 3 3V 3 3VD C143 __ 147 LC148 149 17 po VSSE 8216 135 115 19 VSSE ps 13 1 11 i D DO veer Les C49 53 Lceo 1061 1062 cea 1 4 opps 4 1 25 1 25 7 tr VDDI_Da VDDI_D5 Lus VDDX D vssx pLE5 4 v 15V G BYPASS CAPACITORS 9 GND6 C126 C135 5V REGULATOR GND2 1 25 1 25 1 GND1 6 GND4 1 I 7 023 10128
20. 8 7 6 5 4 3 2 1 REVISIONS DRAFTER Q C 2 B4 CHANGED DCR 021028 00 MAG D20 SWITCHCOL 1 gt 1N914 D31 SWITCHCOL 0 D 1N914 STDBY MAIN DVD1 Z2 DVD1 Z3 DVD1 TUNER 1 TUNER 3 1 2 SROW 0 1 2 SROW 8 1 2 SROW 0 1 2 SROW 8 1 2 SROW 0 1 2 SROW 8 I L I L JF io sowo Ale sowa LIE Hrs a Hla snows alt Hla sowo a Hla SW45 SW34 SW16 SW3 SW1 LEFT MODE MAIN SAT Z3 SAT TUNER 4 TUNER 6 1 2 SROW 1 1 2 SROW 9 1 2 SROW 1 4 1 2 SROW 9 1 2 SROW 1 1 2 SROW 9 M 1 SROW 1 all dd SROW 9 SROW 1 al 9 2713 sROW 9 M d SROW 1 5 SROW 9 SW44 SW36 ane SW18 SW6 SW4 RIGHT MODE MAIN TV Z3 TV TUNER 7 TUNER 9 1 2 SROW 2 m 1 2 SROW 10 1 2 SROW 10 1 2 SROW 10 4 3_SROW 2 tle 10 snow 10 4 T3 snow 10 SW43 SW38 SW20 SW7 C MUTE MAIN TUNER 23 TUNER SAVE 1 2 _ SROW 3 1 2 SROW 11 1 2 SROW 11 3 1 2 SROW 11 LLL EI LI ues DE Hc _ Lese D mes DE SW42 SW40 SW22 SW10 Z2 DVD2 MAIN DVD2 Z3 OFF TUNER 2 LEFT SEEK 1 2 SROW 4 1 2 SROW 12 1 2 SROW 12 1 2 SROW 12 sama 09 sasa LS 4 4 Etik sons alt snow 12 4 mi 3 SROW 12 SW24 SW33 SW23 SW14 23 DVD2 MAIN VCR 23 VCR TUNER 5 RIGHT SEEK 1 2 SROW 5 1 2 SROW 13 1 2 SROW 5 4 1 2 SROW 13 1 2 SROW 5 1
21. 8 7 6 5 4 3 2 1 REVISIONS 15V REV DESCRIPTION DRAFTER Q C CHECKER AUTH OdBFS 2 0Vrms MAIN INPUT LEVEL CONTROL 1 CHANGED PER DCR 021107 00 LEFT MAIN IN 1 03 3 03 LEFT_MAIN 8254 CBV MAG __ RIGHT MAIN AC V 11 20 02 11 21 02 2 D3 3 D3 gt 1 00K 55 RWH CW lt R256 U57 2 CHANGED PER DCR 030407 00 15V 5VD lt 100K 4 lt R255 C343 5 21 03 5 23 03 y gt 1 00K CBV MAG A L 1 5 23 03 5 23 03 13 1 ae 3 CHANGED PER DCR 030729 00 Seas tonne D VCC VDD 5VA CBV MAG 3 C6 7 D8 LEFT_PHONO75_IN 36 p 2 1 10 6 08 10 7 08 15N 1 25 MAL VEE GND 15V 5VD 15 12 PGA2311 5 noe i AGNDL VA PHONO 75U INPUT 4 5 050 A 16 14 LEFT MAIN IN LVL dl 13 12 SANL AOUTL MAININ 4 B8 10 D5 15V vec VDD 5 D5 6 D4 7 B7 8 B6 9 B6 1 0 C7 11 C7 12 C7 13 C7 14 B5 15 C5 ADA_SCLK SCLK vp 4 3 06 7 D8 RIGHT_PHONO75_IN 14 15 3 16 qN 8 C7 10 C7 11 C7 12 C7 13 C7 14 B5 15 A5 15 C5 ADA SDATA OUT ____ 4 15V 5VD VEE GND ADA VC SEL 2 e 5 5 D5 6 C4 7 A7 8 87 9 C7 9 87 14 85 15 C5 EVEN DGND 5 A 4 s EM 13 12 5 C5 6 C4 7 A7 9 C7 14 83 VC ZCEN 1 zcEN MAR vec VDD 15V 5 C5 6 C4 7 A7 8 B7 9 C7 9 B7 14 B3 V
22. CO 5 is DESCRIPTION DRAFTER CHECKER Q C AUTH W W 1 CHANGED PER DCR 030821 00 52 e 534 5925 5924 5W16 5W15 SW3 swe 51 536 VELIE SW27 SW26 5W18 SW17 SW6 SWS 5 4 538 5s 5929 5928 5920 519 SW9 58 SW7 SW40 SW31 SW30 SW22 SW21 SW12 SW11 SW10 SW32 SW23 SW14 SW13 en an Jt UNLESS OTHERWISE SPECIFIED DIMENSIONS ARE IN INCHES CONTRACT NO TOLERANCES ARE FRACTIONS DECIMALS ANGLES ol APPROVALS DATE BD SW L LED wu 2009 DRAWN IM SUM gore SoS EME Y DRAWING 710 15560 7 9 02 FINISH FSCM NO DWG REV NEXT ASSY USED ON RWH 7 10 02 080 15568 1 APPLICATION DO NO SCALE DRAWING 55UED MAG 1 8 02 LE 1 1 SHEET 2 OF 2 22 2 D
23. 8 7 6 5 4 3 2 1 REVISIONS REV DESCRIPTION AUI 15V LEFT FRONT DI DONNE OdBFS 1 98Vrms 112dB OdBFS 7 2Vrms 1 CHANGED PER DCR 021107 00 CBV MAG 5VD 5VA 5VR R232 C256 R193 11 20 02 11 21 02 il ll il VANS fox vA 1553 15V 5VD RWH CW 316 33063 R194 681 5 154 2 CHANGED PER DCR 030407 00 Pu 552908 FB19 3 1 115K lt 1902131 741 U48 wl ud CBV MAG C309 C305 C302 C258 1 1200PF T 4 ADG451 5 23 03 5 23 03 200 pe 820 ihe s A LFRONT DACOUT oy 3 CHANGED PER DCR 030729 00 osos 47 47 330 6 3 Aba C257 Cote CBV MAG C308 C304 C303 by zt e P ui ed 10603 10763 m 316 330 6 3 68 1 1200PF U29 4 CHANGED PER DCR 031125 00 1 14 04 1 30 04 1 25 1 25 1 25 1 1 191 4 5 CBV MAG pe Y 1 30 04 2 2 04 22K 8190 RWH CW AK4395 AA 15 n 5 CHANGED 45 48 999 100 PER 4 27104 4 29 04 gt oo 18 121K y 5 0 040408 00 Ks 15 03 FRONT_DAC_MCKI 3 17 h 6 CHANGED U29 PER ECO 040526 00 RWH m al 13 32 ADG451 6 14 04 6 16 04 __ MAIN DAC RST 455 23 CBV MAG 11 07 12 07 13 07 14 83 JPD AOUTL po 4 88 LEFT MAIN IN 3 MC33078 on 4 A4 5 A4 6 A4 11 D7 12 D7 13 D7 15 B3 15 D5 MA
24. 8 7 5 4 3 2 1 REVISIONS REV DESCRIPTION DRAFTER Qc CHECKER AUTH RWH CW 1 CHANGED PER DCR 020913 00 1465 02 1220102 CAM MAG 11 06 02 12 20 02 RWH CW 2 CHANGED PER DCR 030307 00 515103 CAM MAG 15V 5VD 5 14 08 5 20 03 RWH ECM 3 CHANGED PER DCR 030626 00 MAG 10 2 03 10 9 08 D23 D22 1N4002 1N4002 78L05 VIN VOUT 2 L 50 2367 018 T 1 25 L C52 M 10 10 77 5V_A VCOA 5V 5 3 FB9 Ie FB7 FB8 3 C 2208 016 C20 C44 1 25 1 25 T T 1 25 1 914 cae ee 1 50 R40 AAF xl U17 D19 1 2K 4716 MAIN PUMP UP 1 2 UPA 74 04 BAR35 12 8 177 P 4 4 6N 011 SUP 7 i 37 149 017 BAR35 R45 100 20 MAIN_PLL_PUMP DN 4 P DOWNA 4 TLO72 3 ol MODULE 74 04 1 2K Y T 1 25 018 iu PLL OUTA SPARES P_DNA j 777 U17 MER OSCA BAR35 R44 9 2 MAIN LOCK s gt 6 2 1 DOWNA 1 C46 U10 U10 R43 U17 pij 499 OSCA 1 3 gt 1 2 MAIN PLL_MCKO amp 13 D 12 NC 1 4 25 74HCU04 74HCU04 47 74 04 B LK_DNA D21 R41 R38 47K 47K Ut 1N914 C48 4 99K cag NC R49 R47 E pi T 1 5 74ACT04 2 2M 15V 1 25 2 2M LC45 R39 d U10 U17 p2 T 47 16 2 7045 L 28 utt 49K 5 06 1 74HCU04
25. 2008 2283 1883 Toru 0078 CD 993 CO DESCRIPTION DRAFTER CHECKER Q C AUTH 1 gt m 2 o ER DCR 021107 00 RWH 11 14 02 CLC 11 21 02 Hija CW 11 21 02 MAG 11 21 02 ER DCR 030407 00 RWH 5 21 03 CLC 5 23 03 CW 5 23 03 MAG 5 23 03 ER DCR 030729 00 RWH 9 29 03 CLC 10 6 03 CW 10 7 03 MAG 10 7 03 ER DCR 031125 00 RWH 1 14 04 CBV 1 15 04 ECM 1 30 04 MAG 1 30 04 NOT ES C 1 LEXICON BOM NUMBER 023 15617 SU ON THIS DRAWING OF PCB U TESTING ALL COMPONENTS OF PCB UNLESS 01 3 LEAD PROTRUSIONS LESS OTHERWISE SPECI FLUSH AND PERPENDICULA PCB ASSEMBLY TO BE PAC FARADAY CAGE CONDUCTIVE PROPERLY PACKAGED TO P SOLDER PASTE MASK PER BREAK PCB AT V GROOVES MATERIAL AF INNER LAYER REVENT TO BE THERWISE 2100 50 FIED INSTALLED INDICATED MAXIMUM AGED ALSO MOU PERSEDES ANY FROM TOP SIDE FROM BOTTO T ALL COM R 90 1 TO IN A STATIC S BAG THAT HAS AN ANTI STATIC THE ASSEMB ANY DAMAGE D LEXICON DOC NO 03 AN
26. 8 7 6 3 2 1 REVISIONS REV DESCRIPTION DRAFTER CHECKER AUTH RWH CW or 1 CHANGED PER DCR 020913 00 10502 1220102 4 R56 11 06 02 12 20 02 RWH CW 2 CHANGED PER DCR 030307 00 rM a CAM MAG spicik 5 5 10K 10K 210K RP6 210K 51408 SER CRST R10 3 3K 23 3K 23 3 10K RP5 RP5 RP5 RP7 10K RP7 3 3VD 3 CHANGED PER DCR 030626 00 9 29 03 10 9 03 3 3K 2 RP9 2 RP1 RP7 4 2 1 3 3 4 4 74VHC139 MAG CINTR SCS 10 2 08 10 9 03 e vcc HS CRY 19 2 CRY FLCS e FLCS e NVCS ORY BESET ds me CRY BC cry ea TTT a scs p e 9 C2 CRY TXD 8102779 140 SCDIN U13 9 C2 4 SCDOUT SCDIO SDCLKI SEUD CRY_INTREQ 8 SDCLKO 9 C2 1299 INTREQ ABOOT CS494001 CL DOMO A CS GPIO9 DOMI 141 HINBSY GPIO8 SD CAS 12 74VHCT32 DSPASPICLK R104 120 11 DELWE 6 D6 9 C2 4 WR DS GPIO10 SD RAS 18 DEL WE 6 D6 9 C2 DSPARXD R101 21 W GPIO11 SDWE 6 D6 9 C2 DSPATXD R103 0 4 130 GPIO13 R50 L 21 07 139 49 CRY_NVCS 825 68PF 6 At GPIOT2 NVCSN GPIO14 1 115 GPIO0 NV0EN GPIO15 M SEY NVWES NVOE 9 A8 tis GPIO1 NVWEN GPIO16 e NVWE f 105 HDATA2 GPIO2 HDATA3 GPIO3 SDADDRO EXTAO CRY 777 R51
27. 9 9 9212 612H ozzy 2 5 6 J7 J8 20 i ar 9 A Co e oF a Jes RET SEES R21 R 2 4 R25 D id C39 C39 R101 e C 3 5 R102 R94 22 42 105 8106 RY1 RY4 J17 Sle 10 SWHT em oi 5 ENCH e R97 E 7 50 R99 51 C41 2 021 02 2 2 2 Q22 2 2 14 5 BST Tel uis 14 21 75 13 Slo 024 ET uni Cag C61 0 R172 02 5 C105 ctos C10 5 B E lt e R178 8170 gt E SINE C98 99 a G 100 E1 HT E R173 1 012 9112 C174 x U 9 GND2 9 Oy w oO 022 5
28. 8122 1222 22 C18 C226 9112 1412 0024 S N LABEL 740 11287 OR EQUIVALENT 6612 1022 0022 206 9222 52 6222 5028 eozu J17 a 5 R207 Bs2u 6625 UT 025 reed ZIZH ered w w 2 LEED 2 ga
29. 5 8 Functional Diagnostic Descriptions 5 11 Disassemibly 5 19 CHAPTER 6 THEORY OF 6 1 RV 8 Amplifier Theory 6 1 RV 8 Analog Board 6 4 RV 8 Main Board Theory eerie ipee tete ed inier ER 6 9 RV 8 Phono Microphone Input Board 6 47 RV 8 Turnier Board THEON ien Se dn ird e dit o dS 6 48 RV 8 Video System Theory n n 6 50 CHAPTER Z PARTS EIS Wi ioe ace nace arts RR Main Board Assembly uu u u a ennt nnn A ntn nennen nnns 7 1 VCO Masterclock Board Assembly nennen enne entren 7 8 Microphone Preamplifier Board 7 4 Tuner Board Assembly cierre enitn a TSAKA enne eo ni en nne ae 7 4 IR Encoder 7 5 Switch LED Board Assembly 7 5 Headphone Board 7 6 Analog Input Output Board Assembly pp 7 6 3 Channel Amplifier Board Assembly pp 7 9 4 Channel Amplifier Board Assembly
30. NO_ERROR 0x0 ADDR_FAILURE 0 1 DATA FAILURE 0 2 TIMEOUT_FAILURE 0x3 COUNTER_FAILURE 0 4 NON VOL DATA FAILURE 0 5 OPCODE FAILURE 0x6 FPGA ID NO MATCH Ox7 DAR FPGA ID NO MATCH 0x8 AUDIO FPGA 0 NO MATCH 0x9 ANALOG_FPGA_ID_NO_MATCH OxA VFD_TIME_OUT OxB 5 3 VFD_RAM_ERROR OxC TEST INCOMPLETE oxD RS232_WRAP_FAILURE OxE SRAM_PREBURNIN_FAILURE 0x13 SRAM_BURN_IN_FAILURE 0 14 EPROM_CHKSUM_FROM_FLASH 0 15 DRAM_FAILURE 0x16 FIFO_ERROR_OVERRUN 17 PIC_SN_INVALID 0x18 FLASH BURN FAIL 0x19 FLASH BURN NO ROOM LEFT FLASH_BURN_NOT_FLASH_PART Ox1B SHARC_TIMEOUT_REBOOT DSP FPGA ID MATCH 1 DEC FPGA ID MATCH 1 TEST NOT EXIST 0x20 THERMOSTAT FAILURE 0x21 EXPANSION_BRD_FAILURE 0x22 ERROR ID BAD VALUE 0x40 ERROR PARAM SEMA CREATE 0x60 CS49400 NO START MESSAGE 0x100 549400 NO BOOT SUCCESS MESSAGE 0x101 CS49400_INIT_ERROR 0x102 CS49400 ERR WRITE TIMEOUT 0x103 CS49400 ERR READ TIMEOUT 0 104 549400 TIMEOUT 0x105 CS49400_AUTO_BOOT_FAILURE 0 106 549400 MSG FAILURE 0 107 CSs49400_DEQ_MSG_FAILURE 0x108 CS49400_FINTREQ_TIMEOUT 0 109 549400 APP START MESSAGE 0x110 CS49400_AB_SPI_TIMEOUT 0x11
31. v 3 El 96 06 2018 5072 8012 1012 8012 6019 012 zo 8 8 8j TIT 20 862 662 eO 112 8112 2212 Er 5112 x 13 GND 2817 C188 5812 2812 6112 R130 1 TSTU 3512 2718 ej 1512 Ez R132 x 1112 ems hi hi C225
32. C175 R245 681 gt 2818 2614 C176 26912 C172 R246 U39 011 R247 2812 C177 1412 1524 BEZY 1912 042 R249 c178 R248 R250 9919 6912 0112 2412 7523 5528 40 11287 I DRAFTER Q C R ESCRIPTION CHECKER AUTH RWH CW p DCR 1 13 03 1 14 03 CLC MAG Z14263 114703 RWH CW SA DCR 5 20 03 5 22 03 CLC MAG 5492J83 5499 93 u RWH CW FD HEATSINK ON 10 8 03 10 16 03 FR 030623 00 CLC MAG 10 16 03 10 16 03 RWH CW FD PER DCR 12 23 03 12 30 03 031218 00 MJD MAG 18720703 NOTES T AJ 59 5 TO BE INSTALLED BOM NUMBER 023 15618 SUPER ANY INFORMATION ON THIS T FROM C ED OF PCB UNLESS OTHERWISE OT TOU SIDE OF PG C UJ 00
33. 8 7 6 5 4 3 2 1 REVISIONS 3 3VD 3 3VD REV DESCRIPTION LECKER RWH CW 1 CHANGED PER DCR 020913 00 an MAG 1 f E VDDEXT2 GND1 S 2 CHANGED PER DCR 030307 00 NN mo eS SE see sat BERTA GND3 1 E7 VDDEXT5 GND4 FE8 4 5 14 03 5 20 03 5 17 vbpexre GND5 F RWH D 4 5 VODEXTS 05 5 4 Eo PETS 3 PER DCR 030626 00 VDDEXT7 GND6 G6 1 19 VDDEXT8 GND7 S 4 CAM MAG 18 VDDEXT8 GND7 S6 4 8 G7 8 7 M8 vpDEXT9 97 4 10 2 03 10 9 03 VDDEXT9 GND8 1 Ell vDDEXT10 GNDe S8 4 RWH CW VDDEXT10 28 ____ 61 G9 4 CHANGED C73 75 130 133 PER D37 Git G9 D47 4011 vDDEXT11 GND10 S9 4 4 27 04 4 29 04 P PSA VDDEXTH GND10 esi0 1 vDDEXT12 510 ___ 1A VDDEXT12 1A L11 H6 ECO 040422 00 11 H6 VDDEXT13 GND12 H8 4 4 29 04 5 2 04 VDDEXT13 GND12 86 4 H7 18V ADSP 21161N GND13 j D8 ADSP 21161N GND1I3 p 1 8 POWERBLOCK GND14 E5 4 1 THES DD I T VDDINT2 Hig 1 vDDINT3 GND16 1 8V A VDDINT3 GND16 J6 E10 VDDINT4 GND17 26 Fs VDDINT4 GND17 J7 1 vDDINT5 GND18 57 ____ VDDINTS GND18 7
34. 0dBFS 1 98Vrms ba OdBFS 7 2Vrms CHECKER AUTH i p RWH CW 5VD 5VA 5VR R228 C250 R183 CHANGED DER 97107200 11 4 02 11 20 02 li th AA t 15V 5VD MAG b 316 330 6 3 R184 68 1 AN FB18 3 196 gt 19 2 CHANGED DCR 030407 00 2 145K C207 L 13 12 5 21 03 5 23 03 C301 C297 C294 1 C252 1 1200 T ADG451 CBV MAG 1 8200PF L VCC VDD 5 23 03 5 23 03 47 47 330 6 3 m x i Eu cnn 35 p GENTER DACOUT 11 87 3 CHANGED PER DCR 030729 00 Spee doces C300 C296 C295 ze JIN CBV MAG v Slike VEE GND 1 1 R181 4 5 4 CHANGED PER DCR 031125 00 AOA 156 04 SK V CBV MAG AK4395 R180 15V 1 80 04 2 2 04 VN 18 pepa 5 CHANGED R41 44 R96 97 PER 45754 2109704 f 15 C3 CSUB_DAC_MCkI 3 VREFH 17 n A 4 TM nas ial lt a gt RWH CW 10 07 12 D7 13 D7 14 83 MAIN DAC RST 4 23 ADG451 6 CHANGED U27 PER ECO 040526 00 SAGA MAIN FS64 5 22 5 23 5 88 MAG u u E T 4 4 5 4 6 4 10 7 12 07 13 07 15 3 15 05 BICK AOUTL 8 D 6 14 04 6 21 04 GIN 15 C3 15 D5 MAIN 128 OUT 6 pzFR 28 C161 VEE GND ___ _ 5 7 27 y Ub7 4 A4 5 A4 6 A4 10 C7 12 C7 13 C7 15 C3 15 C5 LRCK CAD1 8150 8148 18PF 4 5 __ MAIN DAC LATCH 1 8 26 Y 14 83 JTS DZFL Ey Marre pig 25
35. 2 Scroll through the MAIN MENU using the Menu arrows and highlight SETUP Press the Menu y arrow to enter SETUP In the SETUP menu highlight INPUTS Press the Menu arrow to enter INPUT SETUP Highlight DVD1 and press the Menu arrow button to select the DVD1 INPUT SETUP menu Scroll down through the DVD1 menu options and highlight DIGITAL IN Press the Menu arrow to enter DVD1 DIGITAL IN 6 Scroll through the DVD1 DIGITAL IN input options and highlight COAX 1 Press the Menu arrow to assign the input to DVD1 Press the Menu arrow button five times to exit the setup menus Insert a disc into the DVD or CD player and press Play Slowly increase the volume on the RV 8 to a comfortable listening level 9 Verify that clean undistorted audio can be heard 10 Once complete repeat steps 1 to 9 to test the remaining digital inputs 2 to 4 Change the DVD1 DIGITAL IN selected in step 6 to the next appropriate input 11 Now test the optical inputs using steps 1 to 10 Be sure to use the appropriate digital cable AUDIO I O TESTS In order to properly test the RV 8 as described in this procedure the RV 8 must be in Diagnostics mode Perform the following procedure to enter the Diagnostics mode To enter Diagnostics mode 1 Connect the video monitor to the main composite output of the RV 8 and turn the monitor on This will allow full viewing of the RV 8 s Diagnostics menus Turn on the RV 8 using the
36. j E P ____ j j J DE IN8 TO DIG ZONE2 OPT OUT 44K GAIN 1 4 00 Vrms 4 00 Vrms 997 eve i 10 Fs 2 n a 8 Interna 44100 Analog DE IN8 TO DIG ZONE2 OPT OUT 44K FREQ 2 00 Vrms 2 00 Vrms 10 20k 10 Fs 2 n a Interna 30 Fs2 Noe wa 8 2 44100 DE IN8 TO DIG ZONE2 OUT 44K DYNRNG 1 4 00 mVrms 14 00 mvrms 997 n a lt 10Hz gt 20kHz LP Narrow n a n a 20 Internal 44100 Analog DE MIC IN1 amp 2 TO DIG ZONE2 OPT OUT 96K GAIN 1 10 00 mVrms 10 00 mVrms 997 lt 10 Fs 2 None n a n a 21 Internal 96000 Analog THD N Ampl gt 0 25 oso ________ 0005 lt 10 2 gt 20 21 Noe wa 9 21 9600 Analog Page 2 of 6 TEST 8 RV8 AUDIO TEST SUMMARY 010 15834 D A Tests Digital Generator Analog Analyzer Switcher Module See Bal Gnd Typical Upper Lower Clock Sample Audio Test Name Note Left Right Freq Hz EQ Curve Z out Unbal Float Level Measure Reading Limit Limit Imp _ Bandwidth Filter Aln B In A Out B Out Source Rate Source DIG_ZONE2_COAX1_IN_96K_TO_ANLG_ZONE2_FIX_OUT DIG ZONE2 COAX1 IN 96K ANLG ZONE2 FIXOUTGAN 1 rooodeFS j ooodBrs 97 Noe UC CC RN poco hm f se f na ma 9800 PIC_ZONE2_COAX1_I
37. 1 284 83 REV DESCRIPTION DRAFTER CHECKER Q C AUTH 1 CHANGED PER DCR 021029 00 CW 11 4 02 CLC 11 14 02 RWH 11 14 02 MAG 11 14 02 CHANGED PER DCR 030515 00 RWH 5 22 03 CLC 5 23 03 CW 5 23 03 RWH 5 22 03 VOTES ON THIS DRAWING 1 LEXICON BOM NO 023 15622 SUPERSEDES INFORMATION PCB ASSEMBLY TO BE PACKAGED IN STATIC SHIELDING FARADAY CAGE BAG THAT HAS AN ANTI STATIC CONDUCTIVE INNER LAYER ALSO THE ASSEMBLY IS TO BE PROPERLY PACKAGED TO PREVENT ANY DAMAGE DURING SHIPMENT 3 SOLDER PASTE MASK PER LEXICON DOC NO 030 15537 NON JUL 22 2005 D COPY UNLESS OTHERWISE SPECIFIED DIMENSIONS ARE IN INCHES TOLERANCES ARE FRACTIONS DECIMALS ANGLES 01 005 CONTRACT NO exicon APPROVALS DATE DRAWN CW 8 14 02 ASSEMBLY DRAWING PC BD HEADPHONE BD RV8 710 15530 MATERIAL CHECKED 8 20 02 sIZE FSCM NO DWG NO REV NEXT ASSY USED ON FINISH Q C RWH 8 16 02 B 080 15538 2 APPLICATION DO NO SCALE DRAWING ISSUED 8 16 02 SCALE 1 1 SHEET 1 OF 1 2 M 701 09640 KEYSTONE gt MOUNTS ON BACK WITH SHORT SIDE OF BRACKET ON PCB SCRW 4 40X1 4 PNH PH
38. VIDEO INPUTS 6 D7 6 C2 6 C5 3 8VA m R98 120PF 2 49K L6 L5 1 SPARES INPUT 1 INPUT 2 DAC PB orm 5 R97 2 7UH 2 7UH 6 R100 C33 C29 R95 U3 75 0 75 0 75 0 4 1 dc 390PF 560PF 10 6 D7 6 C5 R96 R99 750 1 07K 196 PB BLU R25 BLU R21 6 D7 6 C2 6 C5 B 5VV 15K 15K R91 2 49K 4 NC 6 DAC PR 1 3 4 NC 5 C3 NC J8 J5 Nc RY5 PR 1 PR IN1 1 2 RED R23 PR RED R20 ae 15K ae 15K VIDEO OUTPUTS 1 07K 1 1 NC 6 lt 4 NC INPUT 3 6 RY1 Y J10 6 Ow o4 PY IN SEL Ow 4 PY INI3 8 o Y 2 Y IN3 86 RY4 GRN R28 RY6 l 15K J6 CNV PB 11 1 13 PB OUT J9 11 18 PB IN SEL 95 13 PB IN13 2 PB IN3 9 RY4 BLU R26 RY6 15K CNV PR 11 11 J8 11 13 PR_IN_SEL 9 PR 13 PR IN13 9 PR 2 PR_IN3 9 RY2 RED R24 RY5 15K 5VR 45VR 04 03 1N4002 1N4002 CONTRACT xi n NOE RY5 NO RY2 e CO BEDFORD MA 01730 TITLE APPROVALS DATE 9 C3 9 83 9 C3 DBAWN SCHEM VIDEO BD RV8 BW Nem COMPONENT VIDEO CHECKED Ecw 8 28 02 SKE CODE NUMBER REV 060 15589 3 cw 8 28 02 ISSUED MAG 8 28 02 15589 3 6 sHEET 6 10 8 7 6 5 4 3 2 1 D gt 10 16 2003_16 28 REVISIONS REV DE
39. mia 5 R193 R927 R277 E a Riza o a 8 E 8 3 m nj2 5 2 2 n LIT TIT y Ps y E io 5 LOLOT 2 20 2 51 o n n la g E n 4 R154 2 Rise 892 R235 5117058 049 Q Z 8 52 gt 27 225 S L 121 5 27 25 8 E Em 273 872 18 16 EN ui 12 Cas pil _ _ 044 025 52 R178 C138 297 8168 uig m 8263 014 5123 266 TE sz ma pub ET D51 R188 22 2265 998 74 5 C T 065 RS R88 2 a n 2 8 gt E 181 12 Q Dun n g ki ard 8 8 Y no 2l 15118 2 o HH 2 5 012 245 3 g E d 2 o lll 18181 n i 2 5 n a 8 5 a ETE n ul 2n HE 9 n ls tes 144 OD T 5 c9 E 8 8 ET 2 i D 2 S D 8 8 cis3 o E 151 181 O g o s jr n D all zl 8 gt 5 peer
40. Sheets 5 6 and 7 cover the C Sub Side and Rec A D channels They are similar to the main zone except for various analog source differences and separate clock sources and data outputs Rec amp Zone D A converter sheet 8 The AK4395 24 bit delta sigma stereo D A converter operates up to 192kHz The DAC is configured through its serial control port pins 8 10 11 with a separate Reset pin 6 6 Lexicon The output of the DAC passes through a second order low pass filter with its 3dB frequency at 187kHz The filter topology is a compromise between the flat pass band Butterworth filter and the Bessel filter with its superb transient response The filter is flat out to 20kHz It has an overall gain of 6 7dB when measured at the test points This means a 0 dBFS signal at the D A converter will be 4 Vrms going into the analog switches 09411 analog switches select either the output of the Rec Zone DAC or the Rec analog input source directly The selected signal goes to the dual op amp 032 which buffers a 6dB voltage divider that feeds the level control The PGA2311 output level control is buffered by a 6dB gain driver A direct path around the level control provides a fixed output Rec analog output has a maximum output level of 4 Vrms The signal passes through a muting relay on the way to the output jacks The relays are controlled by the ZONE MUTE RLY signal Zone Level Control sheet 9 U63 serves as a direct bypass level contr
41. es m Goa 121 aa E 5 2 181 AE TN s 1 rm Asse 331 2 c B H j K L D 7 SEE NOTE 7 NOTES 1 HSG BOM NUMBER 23 15824 SUPERSEDES ANY INFORMATION ON THIS DRAWING 2 COMPONENTS TO BE INSTALLED ON TOP SIDE OF PCB UNLESS OTHERWISE NOTED B AN ASTERISK 3 ALL LEADS TO BE TRIMMED TO 8 083 OR LESS CROWN DOCUMENT INFORMATION 4 UNLESS OTHERWISE SPECIFIED MOUNT ALL COMPONENTS FLUSH AND PERPENDICULAR 30 DEG 7 1 DEG TO PCB WAS CROWN PART NUMBER 135266 2 5 PCB ASSEMBLY TO BE PACKAGED IN A STATIC SHIELDING FARADAY CAGE FOR SCHEMATIC SEE 16 16159 HAS ANTI STATIC INNER LAYER THE ASSEMBLY IS TO BE PROPERLY PACKAGED TO PREVENT ANY DAMAGE DURING SHIPMENT SOLDER PASTE MASK PER HSG DOC NO 38 16177 Lorem ves e 26 03 7 HOLE ON TOP OF RELAYS K2 4 MUST BE OPENED AFTER THE UU E sau 5 1 CLEANING PROCESS BY EITHER REMOVING THE SEALING TAPE OR CUTTING INTERNATIONAL INE WWW CROWNINTL OFF THE CIRCULAR TAB WITH AN EXACTO KNIFE OR SIMILAR CUTTING TOOL MES 6 26 03 WARNING THIS STEP MUST BE DONE AFTER THE CLEANING PROCESS NOT E ME BEFORE WATER OR CLEANING SOLVENTS ENTERING THE RELAY VENT HOLE ARE FOR REFERENCE ONLY VE
42. 114 DSPA DO 2091 2 2 ma BRST DATA16 000 NS spato M10 vssa vss 0 5 DOM EiS ye BMS CAS ORS SDWE N10 177 SDCKE SDCLK0 Pe p SDCLK1 d dE U16 B DSPASDRAMCS DSPABWR lt DSPABRD lt BRST 22 DSPABC CONTRACT 7 A 9 lexicon BEDFORD MA 01730 TITLE APPROVAL DATE DERW OVALS SCHEM MAIN BD RV8 RWH 4 26 02 DSP A SDRAM AND FLASH CHECKED 4 30 02 CODE NUMBER REV 9 QC 060 15559 3 Cw 5 1 02 ISSUED JV 4 30 02 15559 6 4 4 19 8 8 7 6 5 4 2 1 8 7 6 5 4 2 1 REVISIONS DESSEN DRAFTER BET PRO CHECKER AUTH 1 CHANGED PER DCR 020913 00 PN MAG 11 06 02 12 20 02 2 CHANGED PER 030307 00 uM pecus CAM MAG 514003 5 20 03 3 CHANGED PER DCR 030626 00 0 10 2 03 10 9 03 DSPB A 14 0 3 3VD 3 3VD TE Tafele RP12 RP12 s RP12 VDDQ VDD 23 DSPB
43. 4 00 Vrms 3 40 lt 10 gt 500 13 Interna 7 2 00 Vrms 2 00 Vrms 10 20k 20k 40k 20 Level lt 0 10 0 10 0 25 0 75 100k _ lt 10 gt 500k 17 1 13 Internal 3 80 Vrms 3 80 Vrms 20 1k 5 40k 20 Unbal THD N lt 003 005 0005 00k _ lt 10 gt 22 None 17 1 13 Internal 4 00 Vrms 4 00 Vrms 15k 20 Unbal Level gt 95 00 75 00 50 00 00 lt 10 gt 22k None 17 1 13 Interna OFF OFF 997 20 Unbal Leve lt 110 00 105 00 140 00 100k _ lt 10 gt 22k None 17 1 13 Internal 4 00 Vrms ___ 4 00 Vrms 20 Level 3 80 3 40 100 lt 10 gt 500k None 5 7 2 14 Interna 2 00 Vrms 10 20k 20k 40k 20 Unbal Leve lt 0 10 0 10 0 25 0 75 100k lt 10 gt 500k None 17 14 Internal 3 80 Vrms 20 1k 5 40k 20 Unbal THD N lt 003 005 00005 100k _ lt 10 gt 22k 17 14 Internal 4 00 Vrms 15k 20 Unbal Level gt 95 00 75 00 150 00 100k lt 10 gt 22 None 17 14 Interna OFF OFF Leve lt 110 00 105 00 140 00 k lt 10 gt 22 None 14 Internal 4 00 Vrms Level 3 80 3 40 100k lt 10 gt 500 17 14 Internal 2 00 Vrms 2 00 Vrms 10 20 20 40 0 25 0 75 lt 10 gt 500k 5 7 3 Interna 3 80 Vrms 3 80 Vrms 20 1k 5 40k THD N lt 003 00005 100k lt 10 gt 22 None 4 14 Internal 4 00 Vrms 4 00 Vrms 15k Level gt 95 00 75 00 150 00 100k lt 10 gt 22 None 5 17 14 Interna OFF OFF 9 dBr Leve lt 110 00 105
44. port 89 of the CPU As the heatsink temperature increases beyond each heat category this PWM signal shrinks in duty cycle in order to increase the fan speed This methodology was embraced to keep fan noise to a minimum while the unit is in operation MON is a provision for monitoring the transformer secondary voltage from the amplifier power supply via the AN7 A D Converter port 99 It is currently not used Front Panel Boot Level Monitoring and Control Signals OVLED SYSLED IR FPSWITCH 3 1 The user has the option of starting the RV 8 into three modes e Normal start up default e AMON e Diagnostics The processor monitors PE port bits 1 through 3 during the earliest stages of boot which are connected to signals FPSWITCH 3 1 The following button map applies e FPSWITCH1 Right Mode e FPSWITCH2 Zone 2 DVD2 e FPSWITCHGS Zone DVD2 When a high is read on any of these port pins it indicates that a button is being pressed and held The table on the next page illustrates the button combinations and their associated modes These combinations must be pressed and held during power up 6 12 Lexicon Buttons and Associated Modes START UP MODES Zone 3 Mode Description DVD 2 ma Boot Process executes uninterrupted d AMON Allows the loading of new code without re flashing storage RAM Places unit into diag mode allowing individual testing of functionality Behind the display wi
45. 6 5 RV 8 Service Manual SCHEMATIC WALKTHROUGH Analog Audio Inputs sheets 1 2 amp 3 Sheets 1 and 2 are identical The Left input jacks and associated circuitry are on sheet 1 while sheet 2 includes the Right input jacks and circuitry Each input pair is buffered by a dual TL072 op amp Each buffer connects to three DG408 8x1 CMOS switches There are separate switches for the Main and Zone2 3 analog source selection with independent switches for left and right channels for a total of six DG408s At the bottom right hand corner of each sheet is a quad switch These switches are used when routing a 5 1 analog source One routes the Center and Subwoofer signals from Inputs 4 or 7 while the other buffers the Surround L R signals from Input 5 or 8 Sheet 3 hold buffering and switches for tuner and phono and buffering for phono75 and mic1 2 Three sets of switches are used to select inputs for each zone separately These switches work in parallel with the muxes on sheets 1 and 2 to provide a 1 of 10 analog input mux function for each zone Main Inputs C Sub and Side Inputs sheets 4 5 6 amp 7 The outputs of the Main source selectors feed the Main Input Level control on sheet 4 A dual op amp on sheet 4 buffers a 6dB voltage divider that feeds the level control The output of the level control is used for the direct analog path to the Front L R outputs and feeds the A D converter Two microphone inputs are provided from the micr
46. 87 1 4W 56 mj 8 LEFT ty os gra 11 10 96 8157 gt 58 t A0 Ai A2 EN V 7 15V T 1 16 15 2 020 REC_ANLG_SEL0 2 C5 14D3 REC ANLG 5 1 NOTES R9 C47 C5 14 C3 gt REC ANLG SEL2 4 1 _ AA 865 2 05 14 03 1 UNLESS OTHERWISE INDICATED RESISTORS ARE 1 10W Pu RCA 100 10 25 pes 2 05 14 03 2 UNLESS OTHERWISE INDICATED RESISTORS ARE 5 L C23 Y lt R66 15V 15V 3 UNLESS OTHERWISE INDICATED CAPACITORS ARE T 150 100K Y 4 dev 15V 13 4 DIGITAL ANALOG CHASSIS POWER 4 ZONE SOURCE SELECT LEFT GROUND GROUND GROUND GROUND 7 15V GND 5 XX XX DENOTES SHEET NUMBER SECTOR i 18V 5 6 LAST REFERENCE DESIGNATORS USED C475 D36 E1 FB38 J27 Q3 Bis 4 6 ss R421 RY8 U96 5 1 A Ret E pL8 LEFT ZONE IN 3 83 9 041 7 COMPONENTS MARKED WITH ON BOM 11 100 7 10 25 Ys 0186 8 5 14W BAV99 56 10 87 C21 Re2 58 T 150 100K y A0 Al A2 EN 15V 15V il 16 15 2 U19 SHEET REV CONTROL BLOCK 060 15579 415V 2 B5 14 C3 ZONE_ANLG_SELO 10F17 6 LEFT ANALOG INPUT MUXES i olas 14 63 ZONE_ANLG 2OFi7 3 RIGHT ANALOG INPUT MUXES 4 15V Bs 14 63 ZONE ANLG SEL2 SOFi7 3 MORE ANALOG INPUT MUXES 4 I 40217 3 INPUTS amp MAIN A D CONVERTER pd R5 2851463 gt ZONE ANLG
47. COMPONENTS FL DICULAR 90 1 RUSIONS 100 MAXIMUM FROM PECIFIED MOUNT SH AND PERPEN 8 HERWISE S J FMBLY BE PACKAGED IN A AJ PASTE MASK PE 0 15587 PIC SHIELDING FARADAY CAGE HAS AN ANTI STATIC INNER LAYER ALSO THE PROPERLY PACKAGED ENT ANY DAMAGE DURING SHIP EFXICON DOC AJ b AND GUT EXCESS FLUSA NIIB HROW OUT BLANK PCB MATERIAL FR WAVE SOLDERING AND PRIOR 10 JUL 22 2005 RELEASED COPY UNLESS OTHERWISE SPECIFIED DIMENSIONS ARE IN INCHES TOLERANCES ARE FRACTIONS DECIMALS ANGLES 01 005 CONTRACT NO con APPROVALS MATERIAL DRAWN RWH BD VIDEO NEXT ASSY FINISH CHECKED CLE MBLY DRAWING Q C CW FSCM NO DWG NO REV APPLICATION DO NO SCALE DRAWING ISSUED MAG SHEET o 1 7002 AVIN Ad03 0 7 6 5 4 5 2 1 DESCRPTON LL LI 9 D FOAM TOP 7 730 15822 4
48. 12 9 02 15549 1 1 SHEET 1 OF 1 8 7 6 5 4 3 2 1 5 12 2003_14 46 8 7 6 5 4 3 2 1 CPUADDR 20 0 eee 7 B5 9 C7 REV DESCRIPTION DRAFTER Q C CPUDATA 59 CHECKER AUTH PT EST RWH CW p CHANGED PER DCR 020913 00 PUN NEC 10K 45VD AT49C1024
49. 2 GPIO26 AUDATAO DEC SDOT 9 88 3 3VD 3 3VD SDATAN3 GPIO27 AUDATA1 DEC SDO gt 9 88 AUDATA2 9 B8 FB13 127 CLKIN AUDATA3 XMT958A I DEG 9 88 139 NC 126 16 100 5 LPD SCLK1 14 A 5 12 Ne 123 CRY Di CRY 18 LP NC 4763 124 2 LRCLK1 NG B jog FILT1 AUDATA4 GPIO28 1253 12538 25 12SB SCLK1SC 852 15 NC 152 CLKSEL AUDATAS GPIO29 3 CRY A0 ER 306 PLLVSS AUDATA6 GPIO30 899 148 7 XMT958B GPIO31 2 5VD CRY D1 U13 5 UHS2 C8 OUT GPIO17 47 5K UHS1 GPIO19 TEST 1 UHSO GPIO18 DBCK R54 3 3VD 1 C98 GPIO20 Lany 2 7 10K CRY AT 74VHCT32 3300PF 777 GPIO21 RP8 3 610 0 8 NC C99 anseo 20900090 9200 FDBDA 4 C 5 10K 74VHCT32 AT29LV040A 22299 090009099 909099 FDBCK y 3 R53 FL A0 m vccl U7 82PF 00 0 FL_A1 A1 777 3 3VD GS S sN Oto 77 07 CRY A2 AD _ 45 CRY_A4 777 TC Ree 5 ae ioo 21 CRY 00 NC 1 8 NC _ t C109 CRY AG 22 CRY Dt 10K 0 CRY_A7 23 CRY_D2 R10812288MHZ 4 gt x CRY 8 103 25 CRY D3 Nc 21767 2 CRY 9 A9 104126 CRY 04 NG 10K VDD 1 CRY A10 AIO 105127 CRY 05 10K our 3 CRY ios 28 CRY 06 A12 Ado 197129 CRY D7 GND A13 4 CRY A14 5 2 CRY A15 11 ae CONTRACT 7
50. 4 C74 UB i vopinte GND19 58 1 H2 vDDINT7 GND20 J9 4 VDDINT7 GND20 x 49 vDDINT8 2 910 VDDINT8 GND21 I 33 10 H11 K6 gr VDDINT9 GND22 c2 1 vDDINT9 GND22 K6 K5 K7 C73 K5 vDDINT10 GND23 VDDINTIO GND23 kg I a E 9 6800 6 3 a VDDINT12 25 2 18 K10 45VD 8 vDDINT13 GND26 4 VDDINTI3 GND26 1 77 L10 VDDINT14 VDDINT14 R76 N14 P14 js DSPAAVDD Ni4 pp AGND P14 AVDD AGND LM1117 10 Al ci 3 vour 24 1 4 NC A15 NC1 27 NG NC2 NC2 NC 15 NC 15 BIS 877 AEBS NC Nos TERM ADJ 1 00K Ae NCA NC Ri5 NCZ C U22 1 NC RIS Neg 4 1 U34 R78 016 72 71 dd oss ah age 2 1 25 T 01 25 T 4 7 6 3 330 6 3 1 8V B 1 8V 1 8V B C131 33 10 C130 c 6800 6 3 5VD 77 8142 4 DSPBAVDD 45VD LM1117 10 voUT2 1 4W Bias GAL16V8R 15 TERM 1 00 9 02 e BISP_CTRL 2 vcc H B 1 62 31 4 1 CPUWRL 4 12 CPUCLKI 1 B3 9 C8 1 8 4 w CPUWRH s ES RESREGDECL gt 08 R144 C129 C128 CPURD 6 1054 RESREGDECH e 1 B3 9 C8 gt 2 A7 1 25 01 25 CPUADDR3 7 15 DISP_RS 242 CPUADDR2 al 2 Ong DISP RW P 12 86 L C127 C133 196 CPUADDR 20 0 GP UADDRI 9 10 2 DISP E 12 86 T 4 7 6 330 6 3 1 D3 9 C
51. MAG 1 3 5 20 03 5 22 03 1 3 CHANGED DCR 030623 00 m ON R72 019 Reg 1 25 R66 018 Reg C25 ev 10 8 08 10 16 03 2 88 3 88 4 88 lt 75 0 1 1 75 0 2 C8 3 C8 4 C8 2 na 1 2 88 3 88 5 d 196 Re 2 476 R74 10 9 03 10 16 03 3 3K 1 3 3K 470K Y 15V 15V 5VV 5VV 2N3904 2N3904 2 016 R59 C21 2 B8 3 B8 4 B8 SC2 1 SY 2 C8 3 C8 4 C8 2 B8 3 B8 L R58 22 47 6 R65 3 3K 470K 15V 15V 5VV 5VV 2N3904 C16 J13 3 3 s R55 Q15 R51 1 25 R48 ava 2 88 3 88 4 88 223 5 75 0 1 75 0 2 C8 3 C8 4 C8 22 196 2 B8 3 B8 5 1 856 3 3K 470K Y 15V 15V 5VV 5VV 2433904 12 2N3904 D D 4 I T R46 013 R42 1 25 R39 012 R41 C15 sva 2 88 3 88 4 88 lt 75 0 1 1 75 0 2 C8 3 C8 4 C8 22 pas 196 5 L 1 RO 2 4 6 R47 NOTES 3 3K 3 3K 470K 1 UNLESS OTHERWISE INDICATED RESISTORS ARE 1 10W ty 2 UNLESS OTHERWISE INDICATED RESISTORS ARE 5 5VV 5VV 3 UNLESS OTHERWISE INDICATED CAPACITORS ARE UF V 2N3904 2N3904 5 C10 4 DIGITAL lt gt ANALOG CHASSIS POWER GROUND GROUND GROUND GROUND sc5 R36 011 R32 1 25 010 R31 C11 sys 5 XX XX DENOTES SHEET NUMBER SECTOR 8 1 750 1 s 2108 32848 6 LAST REFERENCE DESIGNATORS USED C183 011 E3 FB11 J20 L7 22 Ags 196 2 88 3 88 RO 2 476 837 SSK 470K Q26 R255 RP1 RY6 U42 Y1 7 COMP
52. 1 25 7 4 7 GNDR 8357 C365 R339 2 8 MC33078 spata 15 MAIN T25 INT 15 B5 15 D6 11 55 1 1 25 17 47 MAIN FS 100PF 2 00K 25 LRCK 5 A4 6 A4 10 C7 11 C7 12 C7 13 C7 15 C3 15 C5 1 34 4 51 4 AINR p see 80 28 18 MAIN RSE 5 A4 6 A4 10 C7 11 D7 12 D7 13 D7 15 83 15 D5 ui y 3 AGND 24 MCKI F 2200 13 Ret 12 MAIN RST 5 A4 G A4 14 83 CONTRACT A U84 NO ex CO n 3 OAK PARK C347 R277 BEDFORD MA 01730 RIGHT MAIN IN LVL Yu R293 4746 5 62K we APPROVALS DATE 1 51 SCHEM ANALOG I O BD RV8 14w DRAWN nwH 8 27 02 u INPUTS amp MAIN A D CONVERTER CBV 8 28 02 SIZE CODE NUMBER REV 060 15579 3 5VA CW 8 29 02 FIENANME S ISSUED 8 29 02 15579 6 4 SHEET 4 OF 17 8 7 6 5 4 3 2 1 e 8 7 6 5 4 3 2 1 REVISIONS REV DESCRIPTION DRAFTER Q C CHECKER AUTH RWH CW C SUB INPUT LEVEL CONTROL 1 CHANGED PER DCR 021107 00 11 14 02 11 20 02 CBV MAG 5VA 11 20 02 11 21 02 RWH CW s 2 CHANGED PER DCR 030407 00 Ets MEM ES CBV MAG 5 23 03 5 23 03 5 RWH CW Lu 3 CHANGED PER DCR 030729 00
53. 6 19 RV 8 Service Manual Proprietary DSP A U16 The Memory interface and control block for U16 is shown on this page The on chip memory controller provides all the necessary interface to the SDRAM The DSP accesses the memory data bus 32 bits at one time eliminating the more conventional four data mask controls These have been replaced by one control signal DQM P13 which acts like an output enable during read accesses This device also allows for four banks of memory and provides four chip select signals As this application uses only one memory device 50 6 is the only chip select used The WR M9 RD R8 BRST 9 and ACK M12 pins are valid only in topologies where there is a bus master and a bus slave As there is no host connection to the DSPs through the Address and Data busses and both DSPs are independent of each other these signals serve no function They are connected to their analogous pins on DSP B and are pulled up by internal resistors Boot Mode Configuration The ADSP21161N supports a multitude of boot up options These options are chosen by hardwiring the EBOOT 5 LBOOT and 5 pins to the appropriate values This application utilizes the SPI boot option therefore these pins are hardwired to a value of 010 via RP4 and R69 R71 Proprietary Algorithm DSP B SDRAM and Flash Sheet 5 This sheet shows the interconnection between DSP B and its SDRAM It also illustrates the boot co
54. OUT 96K DYNRNG 1 4 00 mVrms 14 00 mvrms 997 None 20 Unbal Float dBFS THD N 108 00 104 00 130 00 n a lt 10Hz gt 20kHz LP Narrow n a n a 8 20 Internal 96000 Analog eem ______ ___ ANLG FRONT IN1 TO DIG ZONE2 OPT OUT 48K GAIN 1 4 00 Vrms 4 00 Vrms 997 None 20 Float dBFS Level 0 40 0 00 1 10 n a lt 10 Fs 2 None n a n a 1 13 Internal 48000 Analog nb LG TO DIG ZONE2 OUT 48K DYNRNG 1 4 00 mVrms 14 00 mvrms 997 None 20 Narrow n a n a 1 13 Internal 48000 Analog ANLG FRONT IN1 TO DIG ZONE2 OUT 44K THD 3 80 Vrms 3 80 Vrms LG N1 TO DIG ZONE2 OPT OUT 44K DYNRNG 1 4 00 mVrms 14 00 mvrms 997 None 20 Float dBFS THD N 107 00 104 00 130 00 n a lt 10Hz gt 20kHz LP Narrow n a n a 1 13 Internal 44100 Analog 4 70 mVrms 50 00 mVrms None 20 16 00 mVrms 16 00 mVrms FRONT 75 IN TO DIG ZONE2 OUT 44K THD 1 16 00 mVrms 16 00 mVrms 20 20k RIAA PRE 20 n a 100 Fs 2 None n a n a 11 23 Internal 96000 Analog ANLG_FRONT_PHONO75_IN_TO_DIG_ZONE2_OPT_OUT_44K_XTALK 16 00 mVrms_ 16 00 mVrms RIAA PRE 20 lt 10 Fs 2 None G_FRONT_PHONO75_IN_TO_DIG_ZONE2_OPT_OUT_44K_DYNRNG 1 4 70 mVrms 16 00 uVrms 997 20 THD N 106 00 100 00 a 100Hz gt 20kHz LP Narrow n a n a 11 23 Internal 96000 Analog LG FRONT MIC IN1 amp 2 TO DIG ZONE2 OPT OUT 96K GAIN 1 10 00 mVrms 10 00 mVrms 997 None 40 Level 26 25 25 75 75 lt 10 Fs 2 None n a n a 21 Internal 96000 Analog LG FRONT MIC IN1 amp 2 TO DIG ZONE
55. TUNER BD ASSY 023 15627 MIC PREAMP BD ASSY 023 15621 SPCR M3X25MM 6MM HEX 635 15337 BRACKET TUNER B 701 15814 NOTES DRESS NUT D S SUPPLIED WITH 9 3 5MM PHONE JACK 1 PART NUMBER LISTING IS FOR REFERENCE 2 PLCS ONLY AND DOES NOT SUPERSEDE THE BOM SCRW M3X6MM PNH PH BZ SCRW AB 4 3 8 FH PH BZ 640 10498 2 PLCS 641 13116 3 PLCS TORQUE 4 6 IN LBS TORQUE 2 4 IN LBS SCRW 4 40X1 4 FH PH RELEASED COPY 640 02715 TORQUE 4 6 IN LBS DEC 18 2003 UNLESS OTHERWISE SPECIFIED ACAD 2002 FILE NAME ANCES ARE i pd 15848 0 0 ASSY DWG A LR ERO RC 712708 TUNER PREAMP RV 8 G P RR es SIZE JFSCM NO DWG NO REV C 080 15848 0 APPLICATION 00 NOT SCALE DRAWING 85080 sowe REVISION HISTORY APPRDVED E C N ZONE REV DESCRIPTION DATE DWN EM 1 INITIAL RELEASE 6 26 03 ME5 _ MES 2 SYN LABEL amp NOTES PER ECO 040404 0 4 23 04 wes 5 RELEASED COPY SIDE S N LABEL 740 11287 OR EQUIVALENT us 7 R167 6 ese T 4 EN m 25 m N E e E o 5 Ba 2 2 gut 4 T o E 9 g
56. 7 RES 99999999999 lt CPUADDR4 22144 00742 CPUDATA6 88 s 933 CPUADDR 242 DOS 33 4 8117 __25 DQ4 35 10K 4 0 DQ3 RP13 33 __ 2 14 DQ2 31 11 WE 2 CPUDATAO 5VD 27 Sub 28 RESET NC2 5VD d 46 VSS1 1MX16 Wii R84 27 552 120 5 R81 10k U26 REFERENCE COPY 4 5 2 27 1 1 1 1 8110 C114 RP11 oj BOOT LOCK 111 1 2K TL7705B 1 25 5 DEBUG_RXD 2004 HSG pee vcc R113 777 DEBUG TXD 12 08 CONTRA A 1 2K USER RXD 12 08 er 1 1 25 au 7 12 C8 NO XI 3 OAK PARK L 2dRESIN SENSE USER TXD 12 C8 C112 t i RESET gt 2 C7 BEDFORD 01730 6 Y CT RESET RESET gt 12 D4 APPROVALS pate f TITLE 1 25 E 4 5 SCHEM MAIN BD RV8 GND RESETp R112 CPU WRD DRAWN WRDCLK MON 4 26 02 U31 EPSWITCH2 A CHECKED 4 30 02 SKE CODE NUMBER REV 2 gt 81000 FPSWITCH3 QC CW 5 1 02 060 15559 6 1 3 5 ISSUED FILE NAME E JV 4 30 02 15559 6 1 1 OF 19 S 7 6 5 4 3 2 1
57. 75 777 5VD e 4 y 8 sot soto SPDIF COAX IN3 GND TACT 284 74HCU04 74HCU04 5 vec 20 77 ula ALS No 4 13 Y2 7 15 5 NC 17148 NC AS YA 1048 GND 5VD 77 U2 74 244 5 vec 8 J8 9 82 DIG REC OUT 2A Yi R29 U3 A2 Y2 5 6 NC 6 14 NC 301 R30 P L C19 XS o 8 12 NC 1 25 74HCU04 SM YA 1 295 3 47PF BLK RCA 2 1 m U3 B 10 D gt NC U2 74HCU04 U4 5 6 NC TORX173 J7 E 352 CVID ZON3 1 12 84 IN 4 1 E SPDIF 9 07 NC 624 74HCU04 CP1 TORX173 zb __ 5 3 b 1 SPDIF_OPTO_IN2 6 2 4 CP2 TORX173 _ 5 3 h 1 SPDIF IN3 6 2 4 TORX173 n SOA PAGE A P 1 SPDIF IN4 NO 44 BEDFORD 01730 6 2 4 TITLE CP4 APEROVALS DATE _ SCHEM MAIN BD RV8 DRAWN RWH 4 26 02 SPDIF vo z CHECKED CAM 4 30 02 SEE CODE NUMBER Q C 5 1 02 HLERAWE 060 15559 8 ISSUED JV 4 30 02 15559 6 13 SHEET 13 19 7 6 5 4 3 2 1 7 6 4 2 1 REVISIONS REV DESCRIP
58. 8 6 5 4 3 2 1 REVISIONS REV DESCRIPTION DRAFTER Q C CHECKER AUTH RWH CW 2 5V REGULATOR 1 CHANGED PER DCR 020913 00 11 05 02 12 20 02 CAM MAG bans 11 06 02 12 20 02 2 RWH CW 2 CHANGED PER DCR 030307 00 203 szos 2 5VD 5 14 03 5 20 03 RWH ECM 3 CHANGED PER DCR 030626 00 40 9 03 D LM2937 2 MAG VIN vout 3 10 2 08 10 9 03 TERM GND T 2 U12 POWER CONNECTOR L C54 E T 4 7 6 3 AN ane 5VD C169 L C168 1 C167 7100 25 7 22 50 TT 150PF 231 5VD 3 3V REGULATOR 370 1 1 DGND1 D48 2 DGND2 i lt i 3 3 DGND3 1N4002 DGND4 W6 DGND5 3 3V n 15VP 1 DGND6 LMS1585A DGND7 CASE VOUT 2 1 DGND8 em 1 V ule C 173 Lan DGND9 GND 7100 25 7 22 50 T 150PF i 1 038 LUG1 1 777 15V 4 ko 15VN FAN CONNECTORS 15V R182 R183 8184 R185 R186 51 51 51 51 51 L3 14W 14W P1 AW 1 4 gt 1 4W Con gt 1 220UH 2 100 25 22 50 L 150PF ou M 76 177 C175 TC174 r 470 16 924 1 4 4 1 423 R188 B D49 N 1N4002 tL 178 T 470 16 L2 4 1 e 2 220UH J32 2 4 1 3NF06 _ 2 01 02 J21 8178 047 2 Q2 FAN DRV 9 8 R177 Z 2N4401 3 1 88 5o 74HCU04 47K Q1 n 10K CONTRACT ex CO n NO BEDFORD MA
59. ma 8 2 9600 Analog j j l M j p p D j G ZONE2 OPT OUT 48K GAIN 1 4 00 Vrms 4 00 Vrms 997 None 20 Float dBFS Level 0 40 0 00 1 10 n a lt 10 Fs 2 None n a n a 1 13 Internal 48000 Analog G_ZONE2_OPT_OUT_48K_THD 3 80 Vrms 3 80 Vrms 997 None 20 Unbal dBFS THD N lt 99 00 88 00 120 00 lt 10 Fs 2 None 48000 Analog ANLG ZONE2 IN1 TO DIG ZONE2 OUT 48K DYNRNG ANLG ZONEZ IN1 TO DIG ZONE2 OPT OUT 44K C j j jj 4 j j j 7 c r lt 10Hz gt 20kHzLP 2 2 PHONO75 IN TO DIG ZONE2 OUT MK T T 1 ree e S jr sj j j j jp j None 20 16 00 mVrms 16 00 mVrms ZONE2 75 DIG ZONE2 OUT 44K THD 1 16 00 mVrms 16 00 mVrms 20 20k RIAA PRE 20 Unba THD N 0 01 0 02 002 n a 100 Fs 2 None n a n a 11 23 Internal 96000 Analog LG_ZONE2_PHONO75_IN_TO_DIG_ZONE2_OPT_OUT_44K_XTALK 16 00 mVrms_ 16 00 mVrms RIAA PRE 20 Unbal Leve lt 75 00 70 00 lt 10 Fs 2 None 96000 Analog 4 70 mVrms 16 00 uVrms LG ZONE2 MIC 1 182 TO DIG ZONE2 OUT 96K LG ZONE2 MIC IN1 amp 2 TO DIG ZONE2 OPT OUT 96K GAIN 1 10 00 mVrms 10 00 mVrms 997 Bal Float dBFS 10 Fs 2 Internal LG ZONE2 MIC IN1 amp 2 TO DIG ZONE2 OPT OUT 96K FREQ 1 10 00 mVrms 10 00 mVrms 20 20k Bal Float dBr 10 Fs 2 Interna LG ZONE2 MIC 1 182 TO DIG ZONE2 OUT 96K THD 1 10 00 mVrms 10 00 mVrms 997 Bal Float dBFS lt
60. 080 16438 APPLICATION 00 NOT SCALE DRAWING SSUED uc nzwe sar see 1961 2 1 4 3 J 14157411416 D DEC 05 2003 CN N 1 REVISIONS DESCRIPTION DWR CHKD Q C AUTH SEE BOM FOR P N p APPLY HEATSINK COMPOUND TO BOTTOM SURFACE OF TRANSISTOR NOTES C 1 PART NUMBER LISTING IS FOR REFERENCE ONLY amp DOES NOT SUPERSEDE THE BOMS gt lt s 00 1759 X ja _ sme exe 2 SCRW TAP 6 32 X 1 4 PNH TORK ZN TEM ASSY DWG A DRAWN 10 28 03 HS DBL RV 8 E DWG NO ka ow 080 16439 APPLICATION DO NOT SCALE DRAWING 5907 2 1 NN gt gt 77 NN M EV LATAS 1 TUN N FO Yuq u ANS OSES s s 4 i ANN 22527 1 gt OWN 9 26 7 7 e 452 4 27 EA B 2002 SO 4 3 DEC 05 2003 2 1 REVISIONS REV DESCRIPTION DRAFTER Q C CHECKER AUTH RWH CW 1 CHANGED PER DCR 000327 00 4 10 00 4 10
61. 1 CVID ZON22 2 YEL 1 VIDEO BOARD CONNECTOR CVID ZON 1 2 YEL 1 1 CVID_MAIN2 2 YEL l J4 CVID_MAIN1 REVISIONS DESCRIPTION DRAFTER CHECKER AUTH NOTES 1 LAST REFERENCE DESIGNATORS USED J5 REFERENCE COPY 2002 Lexicon Inc CONTRACT 3 OAK PARK lexicon BEDFORD MA 01730 _ SCHEM VIDEO OUT BD RV8 CW 8 7 02 RCA OUTPUTS CHECKED ECM 8 13 02 SEE CODE NUMBER ju RWH 8 14 02 ISSUED MAG 8 15 02 15519 0 1 me 1 OF 1 002 11 25 oo Co _ 9 3 2 8 7 6 5 4 3 2 1 REVISIONS REV DESCRIPTION DRAFTER CHECKER AUTH 1 CHANGED PER DCR 021030 00 V Um CBV MAG 112002 RWH CW LUGI 2 CHANGED PER DCR 030317 00 OUS R42 MAG 75US R 1 B3 1 B5 5 22 03 5 22 03 5 x 2505 1 B5 1 B3 100 R33 15VA VABUA 7505 LRET C35 100 i i Y J3 1 25 R45 1 25 RIAA R R26 8 1 3 1 B5 1 5 NE5532A R35 C38 100 100 7 NE5532A R47 RCA 6 7 RIAA L 1 1 4W 04 2 21K 10 25 1 C3 1 B5 RE A 1 100 C29 2475 BAR35 C37 2 21K R48 RIAA 120PF 91 5 068 63 1 C3 l D10 pu
62. 1 C3 2 1K MAINMORPH1 1 83 Y7 NN MAIN eds 5VV R194 S VIDEO Q8 Q9 15K OUT 2N3904 2N3904 2 5 NS AD8072 INH R15 7 R195 SY_MAIN2 VSS VEE 1 00K 6 75 0 1 41027 1 9 C3 R196 sVV 475 R197 5VV 5VV 1 11 0K T SC MAIN2 1 C5 3 C8 196 1 Q4 1 C5 3 B8 K 4 R12 1 05 3 88 I 5VV 2N3906 9 09K SC3B c5 2 1 05 gt 1 25 R10 1 85 5056 4 75K e BYPASS 1 MAINMORPH2 o 2 Q6 RI 1 25 23904 2N3904 215 5VV VSS VEE R9 1 00K MAX4310 196 V R216 MORPHEN SHDN VCC 15k 9 83 zcal 080 Y C OUT 4 No Ss S MAINT a IN1 75 0 196 9 211 118 Ao VEE T 15 t R212 038 OSD gt 502 C127 5VV 7 L 8 LT1229 8215 561 5VV MAIN 1 D7 3 B8 4 B8 7 R217 1000PF COMPOSITE VIDEO 1 C7 803 U28 R239 319 3 1 87 R203 4 1K 13 1 OUT 100K R238 NN v 15V R200 3 3K 2N3906 vs 9 03 MTHRU mel R202 1 R237 R214 50 36K 8 25K 10K 1 1 U22 v 7 sw BYPASS R127 MSVID_SEL0 145K R126 9 83 3 9 B3 P MSVID SEL2 1 15 CVID_MAIN2 CONTRACT 7 9 83 1 1 4 ex CO n 3 OAK PARK OSD IN BEDFORD MA 01730 TITLE APPROVALS DATE SCHEM VIDEO BD RV8 RWH 8 9 02 MAIN R125 CHECKED 8 28 02 SIZE CODE NUMBER REV p B 060 15589 3 CW 8 2802 ISSUED MAG 8 28 02 15589 3 2 sHEET
63. 16 PLCS FANS TORQUE TORQUE 10 14 IN LBS 8 10 IN LBS B lt N 07 2 4 20 2 XY TORQUE 8 12 IN LBS SEE 080 15647 FOR FRONT PANEL ASSY DETAIL A v lt S 2 2 Y T REF AC INPUT WIRING 4 PLCS MAIN BD TORQUE 4 6 IN LBS 16 PLCS 2 PLCS OPT PANEL TORQUE 4 6 IN LBS D 4 PLCS d lt gt lt lt Cr ts eos Sy lt CN OX lt 2 PLCS r PISA 22 72 SEE ASSY DWG e 2 080 15848 lt lt 16 PLCS i 6 PLCS CENTER PLATE NOTE AIR FLOW 4 PLCS HANDLE TORQUE 4 6 IN LBS DIRECTION gt lt ORG e So Sac AS Q Q lt 1 5 TORQUE 8 12 IN LBS ee 2 4 1 SEE SHT 3 FOR PARTS LIST DRESS NUT 2 SUPPLIED WITH 2 PLCS TUNER 3 5MM PHONE JACK 13 TORQUE 4 6 IN LBS TORQUE 4 6 IN LBS ed amp RCA CONN 4 PLCS 16 TORQUE 2 4 IN LBS ICES ARE CHASSIS 8 TORQUE 4 6 IN LBS 8 poer m 1 6 04 SIZE FSCM NO 046 NO RI 080 15646 NEXT ASSY USED APPLICATION 5 13 04 SCALE 1 1 SHEET 2 OF 3 n gt IN gt PART 022 15610 022 15611 022 15612 022 15624 023 15615 023 15617 270 16120 454 13124 470 15213 490 13144 490 15843 527 12974 530 02488 540 14303
64. 187 QDC LUG 8 187RA 250 QDC SLV 7 5 QTY MERLO s gt gt Too o N CN gt WHERE USED TUNER CABLE D CONN TO REAR CABLES TO CHASSIS CHASSIS CHASSIS REAR PANEL FANS TO CHASSIS FANS TO CHASSIS PS TO PS MTG PLATE HANDLES TO REAR PNL MAIN BD TO REAR PNL CTR PLATE TO CHAS 6 MAIN BD TO CTR PLATE 4 ANLG BD TO CTR PLATE 5 VIDEO ASSY TO REAR PNL 4 TUNER PREAMP TO REAR PNL 2 OPTION PNL TO REAR PNL 2 PLATE TO FP 2 FANS TO CHAS COVER TO CHAS FEET TO CHAS FP TO CHAS 4 AMPS TO CHAS amp REAR PNL 14 PS MTG PLATE TO CHAS 2 TUNER PREAMP TO REAR PNL PS amp TOROID ASSY TO CHAS 6 XFRMR TO BRKT 4 PLATE TO CHAS RCA amp OPTO CONN TO REAR PNL D CONN TO REAR PNL CHASSIS GND CHASSIS GND HANDLES TO REAR PNL AC CONN TO PWR SW AC CONN TO CHASSIS GND HEADPHONE BD TO ANLG BD TUNER TO ANLG BD VIDEO BD TO MAIN BD PREAMP BD TO ANLG BD ANLG BD TO MAIN BD FP TO MAIN BD 3 CHAN AMP TO MAIN BD 4 CHAN AMP TO MAIN BD PART 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 680 15642 680 15643 680 15698 700 15809 700 15810 700 15811 700 15812 702 15803 702 15806 702 15807 702 15808 720 15425 720 16123 740 08556 740 09538 740 1
65. 2128 5262 928 T928 e928 0128 9928 2928 D E bred Lezy 5522 0922 8224 2824 9824 2 sei 2628 1969 Loew peed 612 Teeu soe 0168 peu 9268 6228 Peed LECH ozen 112 gee 1662 even Cy 50 2 2162 w p w zu 18e5 w B pn 6 2 CD Ol 55 2 4 p rm BA w 5155
66. 30 MAIN 125 00 4 120715051 Mi 3m 8 SIDE 280 a 2 sI 4 A4 15 B5 gt MAIN S INZ 27 204 ne REO Mo 8 D7 15 83 ae 5 5 CHANGED R391 405 PER ECO 040421 00 RWE W in 2 B A4 15 B5 74LVC1G04 68 1 N 4 27 04 4 29 04 274K 5 gt MAN 125 INS 26 4 CBV KAB 1 4 22 NUN EO 77 U76 4 28 04 5 2 04 12 2 P SIDE 5 1 4 4 5 4 6 4 10 7 11 07 12 07 13 07 15 83 ince 3309 FRONT DAC 10007 2 R207 22 REC DAC 125 OUT 74LCX14 68 1 21 ADC FS64 8 07 15 031 B 1 ce 3 7 A2 15 83 1 MAIN 123 IN4 19 AS AS gt 18 REC DAC FS64 __ U76 R308 11 82 CENTER AMP 2834 cr J27 17 8 D7 15 B3 3 24 E CSUB DAC 11 07 1 18 7 AIA4 5IA4 6 A4 10 C7 11 C7 12 C7 13 C7 15 03 TOMS e 274 3 14 DACFS 5 R307 DAC M 3 4 AA 12 D7 TUN RDS DAT 12 74LCX14 68 1 15 84 AMP 3 OUT FB36 3 TUN CLK 11 076 1 8422 10 R306 MET FB35 4 1 1908 REAR DAC 2 74K 14 83 ADA SDATA IN 8 74LCX14 68 1 1 v i SDATA OUT 4 D5 8 C7 10 C7 11 C7 12 C7 13 C7 14 B5 15 A5 TA _ 7 OUT 15 B4 R399 J21 5 4 D5 5 D5 6 D4 7 B7 8 B6 9 B6 10 C7 11 C7 12 C7 13 C7 14 B5 SA 1 x 14 85 nem 2 3 4 D5 5 D5 6 C4 7 A7 8 B7 9 C7 9 B7 14
67. 4 16 mtema 96000 Anal ZONE2 IN4 TO DIG ZONE2 COAX OUT 96K DYNRNG 1 4 00 mVrms 14 00 mvrms 997 None 20 Unbal Float dBFS THD N 107 00 104 00 130 00 n a lt 10Hz gt 20kHz LP Narrow n a n a 4 16 Internal 96000 Analog LG ZONE2 IN5 TO DIG ZONE2 COAX OUT 96K GAIN 1 4 00 Vrms 4 00 Vrms 997 None 20 Unbal dBFS 0 40 0 00 0 a lt 10 Fs 2 None n a n a 5 17 Internal 96000 Analog LG_ZONE2_IN5_TO_DIG_ZONE2_COAX_OUT_96K_FREQ 2 00 Vrms 2 00 Vrms 10 20 20 40k None 20 Unbal dBr Level 0 20 0 00 0 10 lt 10 Fs 2 None 17 Internal 96000 Analog LG ZONE2 IN5 TO DIG ZONE2 COAX OUT 96K THD 1 3 80 Vrms 3 80 Vrms 20 1k 5k 40k None 20 Unba dBFS THD N lt 98 00 86 00 88 00 75 00 120 00 n a lt 10 Fs 2 None n a n a 5 17 Internal 96000 Analog ANLG ZONE2 IN5 TO DIG ZONE2 COAX OUT 96K 1 oovms 4oovms 85 20 Unbai Float 48 Level 86 00 LG ZONE2 IN5 TO DIG ZONE2 COAX OUT 96K DYNRNG 1 4 00 mVrms 14 00 mVrms 997 None 20 Unbal Float dBFS THD N 107 00 104 00 130 00 n a lt 10Hz gt 20kHz LP Narrow n a n a 5 17 Internal 96000 Analog 22 2 LG ZONE2 IN6 TO DIG ZONE2 COAX OUT 96K GAIN 1 4 00 Vrms 4 00 Vrms 997 None 20 Unbal Float dBFS Level 0 40 0 00 1 10 n a lt 10 Fs 2 None n a n a 6 18 Internal 96000 Analog 30 Fs2 Noe ma 6 18 96000 Anal LG ZONE2 IN6 TO DIG ZONE2 COAX OUT 96K THD 1 3 80 Vrms 3 80 Vrms 20 1k 5k 40k None 20 Unba Float dBFS THD N 98 00 86 00 8
68. 5OFi7 3 NPUTS amp C SUB A D CONVERTER 6 ya ay R57 i i 60217 4 INPUTS amp SIDE A D CONVERTER pud 7O0F17 3 REC A D CONVERTER a ROA E E 8 17 3 REC DAC amp OUT LEVELS J10 15V 5VD 9 OF 17 3 ZONE OUT LEVELS v C19 100217 6 L R FRONT DACS EE TUBE 17 6 CENTER AND SUB DACS 13 12 CENTER UNITY GAIN PASS THRU 6 CENTER AND 5 1 VDD I3OF17 6 L R REAR DACS 35 D CENTER IN I4OF17 3 CONTROL REGISTERS 18 5 08 150 17 5 MAIN AUX CONNS 160217 3 POWER SUPPLY amp HEADPHONE VEE GND 15V 5VD 170217 3 BYPASS CAPACITORS 7 N 4 R3 4 5 U18 d R53 E Bi xm J9 14W 56 15V VDD 5 D LC17 aJ iN T 150 15V 5VD VEE GND 5 018 13 12 DG411 LEFT SIDE UNITY GAIN PASS THRU VDD A p15 LEFT SIDE IN 6 08 R1 C31 8 8 3 1072 849 GND 15V 5VD lt RCA 100 D1 10 25 h VA U18 2004 HSG B BASS 2 56 13 12 CONTRACT C1 850 DG411 NO 3 OAK PARK 1 15 ii T 150PF aiu 100K Y 15V j i 10 BEDFORD MA 01730 15V 9 APPROVALS pate TITLE GND SCHEM ANALOG BD RV8 2 A5 14 C3 ANLG 4 5 DIR SEL DRAWN 8 27 02 _ U18 LEFT ANALOG INPUT MUXES _ ANLG 7 8 DIR _SEL 4 5 CHECKED 2 A5 14 C3 i 8 28 02 SIZE CODE NUMBER REV y ac B 060 15579 6 15V CW 8 29 02 ILE NAME ISSUED MAG 8 29 02 15579
69. Es ASSEMBLY IS TO BE PROPERLY PACKAGED ks La PREVENT ANY DAMAGE DURING SHIP RES z mm C114 033 R143 E i DEl E rcc 2 4 Cs EOS 5 2 6 SOLDER PASTE MASK PER LEXICON DOC ND 5 gt R120 im rt 2 C139 U35 R147 E O e Jos 036 037 ZEE EET EE LM 7 BREAK PCB AND CUT EXCESS FLUSH WITH 28 MN J14 T EDGES THROW OUT BLANK MATERIAL gs jS e AFTER WAVE SOLDERING PRIOR TO E 22 ICT e ie Bg 2 L 8 NUTS SUPPLIED WITH 5 OR 6 zs CONNECTORS IF INSTALLED MUST BE oewos 8 142 Y U47 4 v L E 5 BAGGED AND KEPT WITH PCB ASSY FOR C147 144 F gt C151 C155 13 ES 048 Es DURI MECHANICAL ASSEMBI TU Riss O iis mu U45 2817 w 1 R156 208 53 5157 R158 40 1 an EM _ JU 5 2004 szad 2512 1418 FERE 8 14 aA 1 52 J20 C172 C115 FB16 pz Km 02 171 165 R172 R174 C173 C176 7 RELE
70. i CBV MAG CENTER IN 1 B3 242 OdBFS 2 0Vrms 1 25 4 10 6 03 10 7 03 15 12 PGA2311 nog 1 R243 AGNDL VA 210 y S 16 AINL AourL 14 CENTER IN LVL 5 B8 11 D5 45V 4 D5 6 D4 7 B7 8 B6 9 B6 10 C7 11 C7 12 C7 13 C7 14 B5 15 C5 ADA_SCLK 6 4 CENTER SUB DIRECT INPUT 4 C3 VC 0 3 _ C329 C330 125 5 47 4 D5 6 C4 7 A7 8 B7 9 C7 9 B7 14 85 15 C5 ADA_VC_SEL 2 65 DGND 5 415V SUBA 4 C5 6 C4 7 A7 9 C7 14 B3 MAIN_VC_ZCEN 1 7 8 A C5 6 C4 7 A7 8 B7 9 C7 9 B7 14 B3 sbour VOCI Z teca SUB IN 5 MC33078 2 83 gt t 7 R245 9 11 SUB_IN_LVL AOUTR LIN 5 A8 11 B5 1 00K R246 055 1 8247 AGNDR VA D lt 1 00 10 13 065 R268 1 100K 45V C325 LIEN 4 25 6324 47 5VA C380 paso C SUB A D CONVERTER 100PF R321 3 3VD 2 00K 1 298 5VA OdBFS 0 884Vrms 8i C422 C417 6 8322 2 00K 5 gt EU 47 47 2 y 978 423 C418 0dBFS 2 0Vrms 5VA L C412 1 25 1125 2200PF PCM1804 TI 22 v p 4 4 o 8347 CENTER IN LVL C328 R266 4 21 NC 5 D3 11 D5 E NE 8282 21 Ne 4716 9 62K AINL OVFR 1 51 C415 12 5VR VREFL 47 10414 5 R346 d DNE GNDL 7 n318 C416 6 lt 10 0 100 3 VCOML 1 R324
71. 122 825 120 15 i 2 825 BAV99 8200 203 R205 R_FRONT_AMP 15 08 Y R101 422 2 21 3 12 ADG451 A FRONT 16 A8 1 1 VCC VDD 15 120 14 15 16 p OdBFS 7Vrms J7 VEE GND 4 R45 PT AA LEFT OUT 4 s 2 100 RCA gt L 45VD H Eu 100 C76 15V 13 150 10 2 DACOUT T 9 825 825 47 25 15 8VD es 024 9 1 TN 1 P 3 127 ADGA451 c 16 mag FB14 VDD p 2 D26 TH72 WA e 5 RIGHT FRONT OUT 11 A6 12 A7 13 A6 14 C3 V AIN MUTE 1N4002 6 o iW Gia ROS CONTRACT VEE GND 4 931 AE h NO exicon 3 OAK PARK U28 V 1 BEDFORD MA 01730 tl MAIN CNTL i L REY 64 47 12 7 13 A7 APPROVALS DATE MILE 15V R82 A DRAWN SCHEM ANALOG BD RV8 14 03 MAIN MUTE RLY 2N4401 8 2702 FRONT DACS 42K CHECKED 8 28 02 SIZE CODE NUMBER REV Q2 9 060 15579 6 b CW 8 2902 FILE NAME ISSUED MAG 8 29 02 15579 6 10 SHEET 10 OF 17 8 7 6 5 4 3 2 1 6 21 2004_14 22 REVISIONS REV DESCRIPTION DRAFTER Q C CENTER
72. 162 GND C164 GND3 i 1 25 1 25 1 25 1 25 VIN VOUT CASE VIN L C163 GNDS Y a 10 10 V 15V N 5V 1N4002 5VV C12 C19 C22 C36 C40 C42 C44 C66 C68 Te 125 1 25 T 1235 1 235 1 25 T 1 25 ene 15 15V 3 3 4 45VR ET C72 C74 C76 C98 C101 C102 Tew Jes 1 25 125 7 1 25 125 T3125 T 1 25 FB4 M 6 5VR ere C118 C124 C157 C158 C159 C160 Jag a Te 125 1 25 T 1235 125 T1325 T 1 25 5VV CONNECTOR am 100 25 VIDEO RST VIDEO 987 C52 C70 J18 15V 9 28 1 25 1 25 A25 T A25 T 4A25 1 25 Te VIDEO SCLK 15V OSD CS 908 L C139 C90 pee VIDEO w 9 D8 us CONTRACT x 15 06 VID_I2C_SCLK 4 cor exicon 3 OAK PARK ads 508 BEDFORD 01730 m 45V 8 C2 SYNC DETECT Tes 125 T 25 1 25 1 25 1 25 1 25 APPROVALS DATE Vibes oy CVID ZON2 M i 2 j gt 4 DRAWN RWH 8 9 02 i S C140 4 C3 POWER INTERFACE CONNS 1 420 CHECKED 8 28 02 SEE CODE NUMBER REV 15V NN 060 15589 3 Js CW 8 2802 ISSUED 8 28 02 15589 3 10 SHEET 10 10 8 7 6 5 4 3 2 1 D gt 10 16 2003_16 29 2 1 J 1 25 FB1 2 3 VCC VCCO TANK OUT VREF AGC GND1 GND2 C1 REVISIONS REV DESCRIPTION DRAFTER CHECKER AUTH NOTES 1 UNLESS OTHER
73. 8 EGRE RP21 6 3 47 REC ADC FS64 E aci EXP10 201 S64 19 6 3 47 REC ADC MCKI E oci EXP11 202 RP23 6 47 REC DAC FS Eb EXP12 203 EXP12 REC DAC FS64 N 21 RP22 7 2 47 REC DAC FS64 gt 12 D4 1 204 12 CDAC 19 5 4 47 REC DAC MCKI e 212 EXP14 205 EXP14 AMP1 SER IN 180 RP16 6 3 47 CTRL DATA 12 88 SPARES 15 206 AMI SEN QUI S8 RP16 7 V2 47 STAT DATA 1258 AN SEN CT RICE RP16 57774 47 eed 16 149 16 8 1 47 17 0 17 150 Exp AMP SER IN 48 CTRL_DATB a HOM 174 547 NC 27 3 647 STAT NC RP18 5 4 47 8 8 p HINBSY 152 AM ree RP27 2 V7 47 SER CLKB ir NC RPi88 71 47 12154 ADA TUN CE 27 UNER CE N po eee red RP27 4 47 DATA LATCHB eee NC 22 5 4 47 NC RP23 5 V4 47 NC ZONE2 MCKO 80 NC 24 5 V4 47 16 82 P ZONES 168 MAIN PLL PUMP UP Eod NC RP26 7 2 47 MAIN PLL MCKO 185 173 MAIN LOCK DN NC RP2684 1 47 15 82 MINER EE NPL DOWN SLOW 172 MAIN_PLL_PUMP_DN See NC 278 147 AUDIO OSC 182 DOWN FAST 174 ZONE2 PUMP UP 10 83 OSC 14 112MHZ PIN ZONE2 UP 16 C8 3 3VD ZONE2_PLL_DOWN_SLOW 17 ZONES ELE LOCK DN 16 B8 2 PLL DOWN 175 ZONE2_P
74. APTE ECS 1 7 GPIO4 SDADDRI EXTA1 CRY HDATAS GPIOS SDADDR2 EXTA2 CRY AS 0 1 5 HDATA6 GPIO6 SDADDR3 EXTA3 PRIM gt HDATA7 GPIO7 SDADDRAEXTA4 CRY AS SDADDRS EXTA5 FINTREQ i 169 FiNTREQ SDADDR6 EXTA6 9 C2 met i ECS SDADDR7 EXTA7 CRY A0 RYA 6l CRY_A8 0 4 FA0 FSCCLK SDADDR8 EXTA8 mn CRY AS 7 FA1 FSCDIN SDADDR9 EXTA9 CRY A10 CRYA1 T gt FHS2 FSCDIO FSCDOUT SDADR10 EXTA10 14 FHS0 FWR FDS SDDAT8 EXTA11 CRY A12 29 FHS1 FRD FR_W SDDAT9 EXTA12 CRYCATS 1 S FDATO SDDATIQOEXTA13 BEN FDATI SDDAT11 EXTA14 CRY ATS 1 55 2 SDDAT12EXTA15 CRY ATG 1 18 EDAT3 SDDATI3EXTA16 CRY ATT 19 SDDAT14EXTA17 z 1281 DEGES DECCLK 1 3 4 FDATS SDDAT15EXTA18 CRY CRY A 19 0 e 6 SD 19 CRY_D0 SDDATO EXTDO 9 88 119 FLROLKN1 SDDAT1 EXTD1 cRy Di 9 B8 gt See SDi 131 FSCLKN1 STCCLK2 SDDAT2 EXTD2 CRY DS 9 88 FSDATAN1 SDDAT3 EXTD3 eT SDDAT4 EXTD4 CRY DS 9 11 CMPREQ FLRCLKN2 SDDAT5 EXTD5 CRY D CMPCLK FSCLKN2 SDDAT6 EXTD6 CRY D7 CRY D 7 0 4 75 FSDATAN2 SDDAT7 EXTD7 al 12500 82 LRCLKN GPIO23 MCLK 9 A2 50 SCLKN GPIO22 R106 82 SDATANO 1024 SCLK0 DEC OUT SCKI 9 A2 SPARES 2 5VD 81 DEC OUT FSI 0 SDATAN1 GPIO25 LRCLKO 5800 9 A2 1 15190
75. Disconnect power Wait ten minutes Remove the top cover of the RV 8 With the RV 8 facing you locate the switching power supply mounted vertically on the left side of the chassis Power on the unit 4 5 DoD 200 ID 70 RV 8 Service Manual Locate the wire connection at the top of the switching supply With the DMM measure the voltages on the connector using the black probe to chassis Yellow is 15 volt rail measure for a voltage range of 14 75V to 15 250V Blue is 15 volt rail measure for a voltage range of 14 75V to 15 250V Red is 5 volt rail measure for a voltage range of 4 75V to 5 25V Locate the two black six wire connectors that run from the main power supply board in the middle of the RV 8 to the two amp channels left and right of the chassis With the black lead of the DMM connected to the chassis carefully probe the inside of each black wire with the red probe Some pins contain 65V Some pins contain 65V AM FM Tuner amp Headphone Output Tests These tests confirm that the tuner and the headphone output in the RV 8 are functioning normally Test ou N 4 6 Attach both the AM and FM antennas to the back of the RV 8 Connect the RCA front left and right outputs of the RV 8 to the external amplifier left and right inputs Connect the outputs of the external amplifier to the pair of speakers Power on the RV 8 Press the remote control MAIN soft button Pres
76. E MAG 15V 5 D IN MAIN SOURCE SELECT Eu GND 15 83 RIAA T aad RIGHT PHONO IN 4 M 40K R373 e a T Y 4 402 13 12 15V R PHONO INPUT 1 4 06411 15 RIGHT MAIN IN R371 15 370 14 5 2 D3 4 D8 I 15 83 RRET te 16 S 4 02K 4 02K VEE GND 15V 5VD 1 1 a 15V 4 5 ih 1 Y 3 12 R365 8 15 VDD 7508 L A 5 11 10 15 83 7505 MC39078 LEFT PHONO75 N 4087 08 815 R364 d i Se 14 D3 MAIN SEL VEE GND L PHONO 75U INPUT 1 4 14 03 MAIN_TUNER_SEL P 5 8363 asy R362 15V 5VD 15 83 75US_LRET A min 4 02K 4 02 13 12 196 196 DG411 15V VDD 38 p LEFT 14 3 8 D4 US R eu 32 MC33078 T T ha 15 43 7999 AP RIGHT PHONO75 IN VEE GND Hex EN 4 02 J R361 2 4 5 U42 ih a 2402 A U86 1 13 12 DG411 R PHONO 75U INPUT 1 Y VCC R358 asy R359 75US_RRET on a 8 5 15 3 DM l 4 02K MN VEE Bhp REC SOURCE SELECT 1 15V 15V 4 5 042 R381 8 13 12 DG411 15V MIC_OUT1 ACA 5 MC33078 15 B3 A 15 83 402k 6 Mil 4 MIC1_IN 4 C8 6 D8 7 D8 ii oe LA iE RIGHT REC IN pos rca 196 S 16 2 4 02K U88 L MIC INPUT 1 71 GND 15V 5VD Y U2 RET DA ie 12 4 02K 4 0
77. MANUFACTURER MODEL VX XX c 200X OPTIONS At this point the normal operating software takes over the functioning of the RV 8 Debug Terminal Monitor Test optional If the unit is not powering up correctly monitor the boot sequence using a debug terminal monitor Test 1 Power off the unit 2 Connect a debug terminal monitor to the RV 8 RS232 serial port 2 3 Power the unit and monitor the boot sequence Note In order to see data on the debug port use the following serial protocol 19200bps 8 1 8 data bits 1 Stop Bit 5 7 RV 8 Service Manual EXTENDED DIAGNOSTIC TESTS The extended diagnostic tests are accessible by pressing and holding the ZONE2 DVD2 amp ZONE3 DVD2 front panel buttons when powering on a RV 8 The audio outputs analog and digital are muted When the VFD on the unit displays LEXICON the front panel buttons can be released After the model banner is briefly displayed on the VFD the display will indicate DIAGS MENU FUNCTIONAL TESTS The extended diagnostics can also be entered via the serial debug port by first entering the debug program Typing debug when connected to the serial port accesses the debug program The debug program is case sensitive In addition the extended diagnostics can be entered by sending ed which stands for extended diagnostics to the unit via the serial debug port during the first ten seconds after powering on the unit Af
78. 11 12 15 16 17 18 20 21 22 RV 8 Service Manual Press the Menu arrow The DVD1 INPUT SETUP menu will now be displayed Using the Menu arrow scroll to the VIDEO IN parameter and select it by pressing the Menu gt arrow The DVD1 VIDEO IN menu will be displayed Using the Menu arrow scroll to the COMPOSITE 1 parameter and select it by pressing the Menu arrow Press the Menu lt arrow to exit the DVD1 VIDEO IN menu Using the Menu arrow scroll to the COMPONENT IN parameter Select it by pressing the Menu gt arrow The DVD1 COMPONENT IN menu will be displayed Using the Menu arrow highlight the VIDEO parameter and press the Menu arrow to select it This will set the RV 8 to up convert composite and S video inputs to component video Press the Menu 4 arrow three times to exit to the SETUP menu Using the Menu arrow scroll down to the DISPLAYS parameter and select it by pressing the Menu gt arrow The DISPLAY SETUP menu will open with the ON SCREEN DISPLAY parameter highlighted Select it by pressing the Menu arrow The ON SCREEN DISPLAY menu will open with the STATUS parameter highlighted Select the STATUS parameter by pressing the Menu arrow and change the value of the parameter to ALWAYS OFF Press the Menu arrow to exit the menu structure The video path is now set for testing Test 1 2 Load a disc into the DVD player and press Play
79. 18 2 t HEADP_PRES er GNDIS 44 79 13 12 yaad ong M 3 GND9 GND19 5 VDD i 5VD 4 e GND10 GND20 10 84 p 10 ge was CIN 4 14 09 ZONE SEU GND gt 117 930 E HEADP_REC_SEL lt 100K D27 14 03 FRONT_SEL 4 5 016 15V 16 14 C3 1N4002 1 15V RY8 R83 CONTRACT xi n 3 OAK PARK ___ HEADP_MUTE_RLY 183 2N4401 NO 14 B3 33k en e CO BEDFORD MA 01730 TITLE i APPROVAL DATE v OVALS SCHEM ANALOG I O BD RV8 DRAWN _ nwH 8 27 02 CHECKED POWER SUPPLY amp HEADPHONE 8 28 02 SIZE CODE NUMBER REV ac B 060 15579 3 CW 8 29 02 FIENANME ISSUED MAG 8 29 02 15579 6 16 SHEET 16 OF 17 8 7 5 4 3 2 1 10 7 2003 11 05 7 6 5 4 2 1 REVISIONS REV DESCRIPTION DRAFTER Q C CHECKER AUTH 1 CHANGED PER DCR 021107 00 11 20 02 11 21 02 2 CHANGED PER DCR 030407 00 EUR 15V CBV MAG 15V
80. 196 y 13 12 ADG451 16 2 FB12 VDD 15 F R44 of gt 15 p 10 RY xA O SUB OUT CONTRACT 10 A6 12 A7 13 A6 14 C3 MUTE i SIN 6 Ed d RCA gt NO exicon 3 OAK PARK GND BEDFORD MA 01730 U28 PET TITLE 4 5 APPROVALS DATE y Tp 7 DRAWN SCHEM ANALOG BD RV8 ANN RWH 8 2702 CENTER AND SUB DACS _ MAIN RLY CNTL 8 28 02 SIZE CODE NUMBER REV 10 A5 12 A7 13 A7 Gc B 060 15579 6 CW 8 29 02 FILE NAME ISSUED MAG 8 29 02 15579 6 11 SHEET 11 17 8 7 6 5 4 3 2 1 6 21 2004 14 23 8 7 6 5 4 3 2 1 REVISIONS LEFT amp RIGHT SIDE D A CONVERSION OdBFS 1 98Vrms aude 15V OdBFS 7 2Vrms REV DESCRIPTION AUT 5VD 5VA 5VR T des an 1 CHANGED PER 021107 00 lE GW 024 Tm 11 14 02 11 20 02 36 mim EE 68 1 s 1121 02 17 1 i lt 1 RWH cw asa 115K gt 02011 13 12 ADG451 2 CHANGED PER DCR 030407 00 eius gt 8200PF igi ONE T s L_SIDE_DACOUT 5 23 03 5230 47 47 330 6 3 15 D 12 87 RWH CW C292 C288 C287 R225 8172 Tue m 0
81. 22 4 A4 15 D6 125 IND tio 12 7505 L E 45 A5V NDD SR 5 A4 15 D6 MAIN 125 1 2 13 7503 38816188 ae 14 8 pL 6 A4 15 D6 gt 125 143 14 7505 R 8 B3 16 58 gt 16 N 7 A2 15 C6 125 15 7505 RRET _ 508 415V 5VD VEE GND J22 x 16 Uii 12V 25 4 s U14 5VD 11 5010 NC 3 1 DG41 74LCX14 VDD 45V 9 83 16 C8 2 _ 65 p 7 U96 U96 5 U91 8 IN ADA TUN CE 9 8 516 6833 5 1 FB28 TUN TUNED 13 12 NC es po 552 2 FB29 TUN 8 14 85 1 i VEE GND 74 14 74 14 1 2K t 14 85 74LCX14 Ufy tits To LEFT amp RIGHT ZONE 4 5 A 4 4 TUNER Ley 3 A8 a 3 A8 3 A8 13 12 6 TUNER R i 15V DG411 U96 U96 7 3 8 CONTRACT vec VDD SDATA OUT 11 10 4 pA 8 NO exicon 3 OAK PARK 9 83 16 88 s P ZONE 11 5 D 10 4 D5 8 C7 10 C7 11 C7 12 C7 13 C7 14 B5 15 C5 ADA x E UA B BEDFORD MA DIAO 9 FN 74VHCT14 74VHCT14 1 2K 10 FB30 FA TUN SDATA OUT __ 14 85 TITLE GND 11 APPROVALS DATE 1403 REAR_AMP_SEL lt R390 sik EO R410 12 FB31 gt TUN RDS CLK DRAWN SCHEM ANALOG I O BD RV8 14 03 REC AMP 4 5 014 400K 14 A3 TUN A 13 2832 TUN_RDS DAT 8 27 02 j 14 C3 15 6 MAIN AUX CONNS ZONE SEU 74VHCT14 1
82. 4 EDGES SIEP 4 SOLDER BOX SEAMS 0 07 1 8MM MIN LENGTH OF PIN IO BE FREE OF SOLDER VCO BD ASSY 023 14837 010 AEF 2 SOLDER 2 PINS TO HOUSING UNLESS OTHERWISE SPECIFIED ACAD 2000 FILE NAME OR DIMENSIONS ARE IN INCHES 14834 2 TOLERANCES ARE 023 16129 DECIMALS ANGLES 2 1 REVISIONS 1 ADD ASSEMBLY SEQUENCE CHG CW 1 17 01 2 ADD 023 16129 VCO ASSY AN 5 5 03 CW 5 9 03 D PER ECO 030314 00 CLC 5 8 03 5 12 03 TYPICAL 4 CORNERS LEASED COPY MAY 15 2003 NOTES 1 PART NO S SHOWN FOR REFERENCE ONLY SEE BOM 022 14458 2 STEPS 4 amp 5 ALL HOUSING SEAMS amp SEAMS BETWEEN THE COVER amp HOUSING ARE TO BE SOLDERED PER PCB WORKMANSHIP STANDARDS JOINTS SHOULD BE SMOOTH AND NEAT WITH NO EXCESS BUILDUP 55 DWG n z VCO MCLK _________ 12 8 SIZE FSGM NO DWG NO REV B 080 14834 2 KB APPLICATION DO NOT SCALE DRAWING SSUED 2 d 1 2 DRAFTER Q C Je J4 J5 9 Ee 32 EE en 3 J6 14 S N LABEL 740 11287 OR EQUI
83. 909 19 TO PCB 4 PCB ASSEMBLY TO BE PACKAGED IN A STATIC SHIELDING FARADAY CAGE BAG THAT HAS AN ANTI STATIC NON CONDUCTIVE INNER LAYER THE ASSEMBLY IS TO BE PROPERLY PACKAGED TO PREVENT ANY DAMAGE DURING SHIPMENT 5 SOLDER PASTE MASK PER LEXICON DOC 030 16187 6 BREAK AND CUT EXCESS FLUSH WITH EDGES HR ANK RIAL O e THROW OUT BL PCB MATERIAL JUL 22 2005 0 COPY UNLESS OTHERWISE SPECIFIED 3 TOLERANCES ARE FRACTIONS 5 ANGLES APPROVALS DATE pw DRAWN RWH 5 1 03 2 72 710 16180 MATERIAL CHECKED CLC 5 6 03 SIZE TFSCM NO DWG NO REV NEXT ASSY USED ON FINISH 0 CW 5 8 03 080 16188 0 APPLICATION DO NO SCALE DRAWING ISSUED MAG 5 8 03 SCALE 1 1 SHEET 1 OF 1 7 8 7 6 5 4 3 2 1 REVISIONS DESCRIPTION DWR CHKD Q C AUTH REV Dr qp s TORQUE amp 19 PER ECO 040512 00 CLC 5 20 04 KB 5 20 04 TORQUE 8 10 IN LBS 10 PER ECO 040625 00 CLC 6 29 04 MAG 6 30 04 TYPICAL WIRE B BLACK 3 DISCARD PLASTIC INSULATOR REPLACED WIRE A BROWN P W PCB ITEM 17 WIRE D BLACK a WIRE oe 2 9 FACE CAPS AWAY FROM PLATE PART IS SYMMETRICAL a WIRE E ORANGE mu WIRE F BLACK TORQUE 6 8 IN LBS
84. G0 TORQUE 8 10 IN LBS SEE DWG 080 15648 FOR VIDEO ASSY 5S 62 8 PLCS 4 CHAN AMP TORQUE 8 10 IN LBS 37 4 D 2 p Z 25 Do Z lt 4 lt 2 PLCS TORQUE i e SS BRUN gt S 8 10 IN LBS TNS lt i AY Q S S 1 SEE SHT 3 FOR PARTS LIST 72 gt 2 LOOP TUNER FFC ITEM 44 1 TURNS Sg TORQUE THRU FERRITE ITEM 9 CENTER p 8 10 IN LBS ITEM 70 ON SIDE OF FERRITE AND MOUNT TO FOLD OF CENTER PANEL 4 PLCS VIDEO g DOCUMENT CONTROL BLOCK TORQUE 4 6 IN LBS 15 PLCS RCA CONN 35 i p DESCRIPTION REV TORQUE 2 4 IN LBS 080 15646 SHT 1 OF 3 080 15646 SHT 2 OF 3 2 080 15646 SHT 3 OF 3 ane oo APRONS pam ASSY DWG DR CHASSIS RV 8 asta neo were usos e sa 6 080 15646 APPLICATION 00 NOT SCALE DRAWING SUED syisyoe scae 1 1 emio 8 7 6 5 4 5 2 1 JULY 05 2005 6 PLCS 3 CHAN AMP 50 74 5 TORQUE 8 10 IN LBS SEE DETAIL 14 11 ON SHT 2 FOR AC INPUT WIRING Ad09 GAC VITAY 9002 so AINE 1 REVISIONS 7 6 9 4 PER DCR 040624 01 CLC 7 13 04 MAG 7 13 04 PER ECO 040803 00 CLC 8 16 04 MAG 8 26 04 P d 8 PLCS TORQUE 4 6 IN LBS TO MAIN BD COME 26 2 PLCS TORQUE 4 6 IN LBS 4 PLCS N
85. Rv 8 DWG NO REV 8 assy 8E sz 080 15647 0 APPLICATION DO NOT SCALE DRAWING ISSUED 6 24 03 SCALE 1 2 SHEET 1 1 BRACKET HEADPHONE BD Jn 701 15816 E SCRW M3X12MM PNH PH ZN M3X6MM PNH PH BZ pd 640 10498 2 PLCS EN gt TORQUE 4 6 IN LBS PLACE THIS EDGE FLUSH TO WALL CENTER VERTICALLY SW LED BD ASSY 023 15616 HEADPHONE ASSY Pod 11023 15622 PANEL FRONT 702 15800 SCRW M3X6MM PNH BZ d 14640 10498 11 PLCS 640 10495 TORQUE 4 6 IN LBS 8 7 6 5 A 4 3 2 LEXICON INC 2 1 641 13116 15 TORQUE 2 4 IN LBS SCRW TAP AB 4X3 8 FH PH BZ 64 PLCS P VIDEO OUT BD ASSY 023 15620 SCRW M3X6MM PNH BZ 640 10498 4 PLCS TORQUE 4 6 IN LBS CABLE FFC 14C X 1 680 16146 REF VIDEO BD ASSY 14023 15618 BRACKET VIDEO BD 701 15815 VIDEO IN BD ASSY 023 15619 CABLE 14C X 1 680 15684 REF UNLESS OTHERWISE SPECIFIED DIMENSIONS ARE IN INCHES TOLERAN APPLICATION REVISIONS REV DESCRIPTION DWR CHKD Q C AUTH NOTES 1 PART NUMBER LISTING IS FOR REFERENCE ONLY AND DOES NOT SUPERSEDE BOM RELEASED COPY JAN
86. 2 18 n l D EER o 2 c163 1 8367 D 2Yj8 a jlo 2 A S 2 81 8 Bi a 5 n LB R363 2 Isl E Lgs i DD ISISI oN 8256 cize a 5 2 18 ro 5 o o EZ g 8 2 a k 6275 mme 2 F364 147 R378 2 5 9395 b D E COVE are 5 22 224 59418 582 a P8 1 ps pee P7 5 5 1 paz euo b R257 NUR Dog 1047 094 4 3 L i m eum m om m 8218 1812 18 igi Js 181 esee IBIR Y cree ae 2 181 ete HH pes ilv ES naz pss 054 g 077 e ee 8 gt E E M 1 5 E oe gu Wb ur 5 8 m d as HHH c HEH 5 445 2 N o N Ir gi m P12 RRR GE g 2 22417 em not dL 563 Go n gt OL Luz QL 0 ms Ee pns 982 007 a SES
87. 2 Etr ver 0275 TZ 1072 2 5 2 5 g 5 2 g amp v2 1172 675 1972 BA 9072 8172 gccu oer ESEN ZT E 0572 0 617 1572 752 TIT GND 2192 5288 2965 iL 5928 1 9958 retu sceu oseu sseu 6283 eer 9572
88. 5VA C385 4 SIDE A D CONVERTER 100PF R329 NA 45VA 3 3VD 2 00K 1 dB OdBFS 0 884Vrms R352 C359 R328 Bl esau C434 C429 S R330 100 200K 5 7 55 47 47 R287 Va U79 435 430 24 T pu spes 196 5VA C424 1 25 MS OdBFS 2 0Vrms 45VA 2200PF PCM1804 C336 25 dd R270 MC33078 6 D2 12 D5 LEFT_SIDE_IN_LVL 8286 amp OVFL A NG 47 16 5 62 gt AINL OVFR 1 51 1 4W C427 1 BYPAS 12 yt VREFL 5VR 47 10426 R350 h GRO ae GNDL 7 lt R326 5 E gt 10 0K 3 vcoML PEN 71 R332 dps C433 5 8 6 VCOMR 200K C431 A OSR2 15 192K EN C362 0384 R327 196 3 8 VREFR OSR1 4 MAIN ADC Sex EN 4 A4 5 B4 14 B3 1046 1 25 519 45VA 47 C432 OSRO LADO SOR 4 A4 5 B4 14 B3 6 1 25 27 A GNDR R353 C360 R331 8 103307 SDATA 15 126 IN3 15 A5 15 D6 2 8 MC33078 mer lice cai R333 lt 25 AINR 17 47 MAIN FS 100PF 00K L ww 25 LRCK WA4 5 A4 10 C7 11 C7 12 C7 13 C7 15 C3 15 C5 1 51 4 AINR R288 079 174W d 16 MAIN FS64 4 A4 5 A4 10 C7 11 D7 12 D7 13 D7 15 B3 15 D5 3 AGND 2 49K TTE SIDE ADC MCKI a sis gt T 2200 5VA 13 Ret 18 MAINT ADC 4 A4 5 A4 14 B3 es RIGHT_SIDE_IN_LVL C339 R273 6 8 MC33078 U83 NO exicon 3 OAK PARK 6 22 12 85 AN A See
89. 9 83 Neh M5 NC 056 p MS NC 056 50 C155 TRST TDI DNE NC 056 50 Ne 5 2 N TESTA JT TESTa 33 NE NC TEST2 AOUT TESTI BIO NG TESTO 13 XTALOUT DESNE XTALO Ne 034 10 07 MG TRASI 3 PARK NO R225 24 576MHz exICOn BEDFORD MA 01730 TITLE APPROVAL DATE OVALS SCHEM VIDEO BD RV8 DRAWN RWH 8 9 02 m VIDEO CONVERSION CHECKED Ecw 8 28 02 SEE CODE NUMBER REV 9 8 cw 8 28 02 060 15589 ISSUED MAG 8 28 02 15589 35 SHEET 5 or 10 9 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 REVISIONS COMPONENT ENCODER FILTERS REV DESCRIPTION DRAFTER C38 5VV AUTH 1 CHANGED PER DCR 030106 00 Bm 48 3 VD 1 13 03 1 23 03 MAX4310 ECM MAG aa vs E 1 21 03 RWH CW 2 CHANGED PER DCR 030421 00 6 C2 6 C5 5 20 03 5 22 03 i 7 RWH CW 3 CHANGED PER DCR 030623 00 10 8 62 10 16 03 1 25 1 25 1 25 A VEE ECM MAG 0 10 9 03 74 00 1 6 9 C6 m 5VV R105 750 196 1N914 1K DEC VS 9 R84 5 B5 9 C6 5 C5 m EC XHH 10 74HCO0 3 9 83 YNC 5VV gt 30
90. CS0 NOTES wi 10K T UNLESS OTHERWISE INDICATED RESISTORS ARE 1 10W FB1 1m B j H 2 RP1 RP1 lt RP1 RP2 RP2 2 se Siok 10K Siok 10 2 UNLESS OTHERWISE INDICATED RESISTORS ARE 5 C H EXPANSION 1 p 11 qe s 3 UNLESS OTHERWISE INDICATED CAPACITORS ARE UF V NO 74VHCT541 4 2 DIGITAL ANALOG CHASSIS POWER EXPIO EXPI 7 0 EXPIO T GROUND GROUND GROUND GROUND 22 ei 5 LAST REFERENCE DESIGNATORS USED C2 FB1 J3 R1 RP2 U2 W1 27 5 15 Il EXPOS v H 6 COMPONENTS MARKED WITH BOM EXP a VA Y8pg EXPOS 24 EXPI6 8 12 EXPO6 Eus Y im L 8 5VD 6 B 4 w 02 EXP RESET ahha af NC7WZU04 J3 ay RESET 5VD SPARE GND T 18 6 NC7WZU04 C1 C2 1 25 1 25 2003 Lexicon Inc CONTRACT D A NO exico n 3 OAK PARK BEDFORD MA 01730 TITLE APPROVALS DATE DEAWN SCHEM EXP TEST BD RV8 Di PP ID IE 4 29 03 PY CHECKED CAM 4 29 03 SZE CODE NUMBER FEV B 060 15379 0 CW 4 29 03 FILE NAME 1 3 5 ISSUED KAB 5 2 03 15379 0 1 sHEET 1 OF 1 S 8 7 6 5 4 3 2 1 5 6 3 2 1 REVISIONS CHECKER AUTH COM
91. DBL 1 lt A 4 022 16446 PL HS ASSY SGL POS 1 te 3 022 16447 PL HS ASSY SGL NEG 1 WIRE F BLACK 15 i 2 703 16429 INSULATOR AMP 3CH 1 no N WIRE E ORANGE 15 BE 4 Je 1 6 PLCS 1 701 16424 BRACKET AMP 3CH 1 e TORQUE 6 8 IN LBS Ql Tq soul Te I liu ITEM PART NO DESCRIPTION QTY UNLESS OTHERWISE SPECIFIED ACAD 2002 FILE NAME 9 15 WIRE A BROWN DIMENSIONS ARE IN INCHES lexicon DECIMALS ANGLES ET APPROVALS DATE ASSY DWG D LEAS D 0 PY MATERIAL DRAWN 1072805 AMP 3CH RV 8 D 15 wiRE b BLACK 15 WIRE e BLACK x ws ov 080 16434 2 APPLICATION DO NOT SCALE DRAWING ISSUED MAG 11 24 05 SCALE SHEET 1 1 JUL 09 7 6 4 5 2 1 v00c 60 8 7 6 5 4 2 1 _____________ 5 6__ _____ __ DWR CH o c Aum 16 SHOW INSTALLATION ITEMS 16 AN 5 19 04 5 20 04 REF 4 17 PER ECO 040512 00 cic 5 20 04 KB 5 20 04 ADD ITEM 18 CHG THKNS ITEM AN 6 29 04 CW 6 30 04 8 PER ECO 040625 00 6 29 04 MAG 6 30 04 13 WIRE VIOLET TORQUE 13 WIRE D BLACK 6 8 IN LBS TORQUE 6 8 IN LBS 8 5 Pues TORQUE 6 8 IN LBS 2 y gt p di WIRE H BLACK 13 Da 13 WIRE E YELLOW 2 WIRE G WHITE 13 13 WI
92. OUT 96K DYNRNG 1 4 00 mVrms_ 4 00 997 None 20 Float dBFS THD N 40800 4040 ______ 13000 ma t0Hz20kHziP Narrow 6 148 9600 Anaog ANLG FRONT IN7 TO DIG ZONE2 OPT OUT 96K loat oat 4 Leve _____ 0 2050 00 020 ______ 0 50 025 3 80Vrms ___ 3 80 Vrms 1 4 00 4oovms jk 1 None 20 Float jap 11500 000 43540 na lt 10 2 7 19 mtema 96000 Anaig T IN7 TO DIG ZONE2 OPT OUT 96K DYNRNG 1 4 00 mVrms 14 00 mvrms 997 None 20 Unbal Float dBFS THD N 108 00 104 00 130 00 n a lt 10Hz gt 20kHz LP Narrow n a n a 7 19 Internal 96000 Analog _IN8_TO_DIG_ZONE2_OPT_OUT_96K_GAIN 1 4 00 Vrms 4 00 Vrms 997 None 20 Unbal oat dBFS 0 38 0 00 0 a lt 10 Fs 2 None n a n a 8 20 Internal 96000 Analog _IN8_TO_DIG_ZONE2_OPT_OUT_96K_FREQ 2 00 Vrms 2 00 Vrms None 20 Unba oat dBr Level 0 20 0 00 0 10 10 Fs 2 None 96000 Analog G FRONT IN8 TO DIG ZONE2 OPT OUT 96K THD 1 3 80 Vrms 3 80 Vrms 20 1k 5k 40k None 20 Unba oat dBFS THD N 98 00 86 00 88 00 75 00 120 00 n a 10 Fs 2 None n a n a 8 20 Internal 96000 Analog JANLG_FRONT_IN8_TO_DIG_ZONE2 OPT_OUT_96K_XTALK 1 4 00 Vrms 4oovms 15k None 20 Float dB level lt 1500 8000_ 13000 510 2592 None 8 2 96000 Analog _IN8 TO DIG ZONE2
93. R40 smoothes out the transient response of the feedback loop When MAIN PLL MCKO has reached equilibrium with the reference clock the pump up down signals are inactive The FPGA delivers a series of active low pulses to the error amplifier via MAIN The average duty cycle of these pulses is approximately 1 128 Instabilities such as jitter in the reference will appear as variations in pulse width but the instantaneous variation gets averaged by the action of the loop filter The result is a steady control voltage to the VCO that produces a high stability frequency based on the average frequency of the reference When lock down pulse forward biases 020 current flows through R48 which is integrated by C48 R49 provides a constant current of opposite polarity which also gets integrated The two integrals oppose each other and when the net current into the summing node is zero the voltage at U11 pin 1 remains constant If the duty cycle of the pulse is too small the voltage is driven progressively lower If the duty cycle is too high the voltage is driven progressively higher The resultant voltage is applied to R47 which sinks current from the summing node of the loop integrator which raises the VCO control voltage This gets counter acted by current pulses through D17 and R44 When the integral of these two currents balance the control voltage remains constant so the VCO output frequency remains constant and the loop is s
94. This signal is shared between both SHARC devices DSPARXD receives control status information from the SHARCs in serial form This data is stored within the SPI Control Status RAM and is polled by the system software This signal is shared between both SHARC devices DSPASPICLK is the shift clock used by the SPI protocol to serially shift data into and out of SHARCs DSPASEL is the chip select for the SPI port on SHARC1 018 This signal enables SPI communications with U18 Setting bit 4 in the SPI Chip Select Register high enables it Once this bit is set then control data is written to the SPI Control RAM then the number of bytes to be shifted out on DSPATXD is written 6 33 RV 8 Service Manual to the SPI DMA Block Size Register Once this register is written then a SPI transfer occurs to the SHARC When the transfer is done the host CPU is interrupted by DSPABIRQ The system software must then clear bit 4 in the SPI Chip Select Register to zero DSPBSEL is the chip select for the SPI port on SHARC2 037 This chip select is enabled by writing a one to bit 5 in the SPI Chip Select Register Transfers to SHARC2 are implemented in the same fashion as described under DSPASEL DSPASP3FPGA is DOWNMIX audio return signal from SHARC1 in SPORT format The data present in this stream is converted to S PDIF and 126 formats and mapped Look Up Table to the output ports SPORT A is the serial shift clock for the data present
95. VIDEO SCLK VIDEO DATA and VIDEO REG comprise the remainder of the SPI interface to the On Screen Display controller and the video board control logic Instructions are sent from either the OSD control RAM or the Video control RAM inside the FPGA The OSD control RAM is used to store the two byte commands that are sent to the OSD controller on the video board The contents of the entire RAM are shifted out of VIDEO DATA synchronous with VIDEO SCLK when a byte is written to the lower order byte RAM A status bit is set in the Serial Interface Status Register while the OSD RAM contents are being shifted out VIDEO REG acts as a latch enable for the parallel register devices on the video board The Video Control RAM stores the instructions for the video logic The entire contents of this RAM are transmitted when a byte is written to address 6 within this RAM block VID 12 SDATA and VID 12 SCLK comprise the 1 control interface to the video CODEC The host CPU writes data to storage registers within the FPGA which in turn is transmitted to the CODEC using the 12C protocol 6 34 Lexicon Tuner Board Control Interface Signals ADA TUN CE TUN RDS CLK TUN RDS DAT ADA TUN is select that enables SPI transfers to the Tuner Board The rest of the SPI port is comprised of ADA SDATA IN ADA SDATA OUT and ADA LATCH from the Analog Board Control Interface Currently the tuner board does not utilize a SPI interface so the chip s
96. When a cart is used use caution when moving the cart apparatus combination to avoid injury from tip over Unplug this apparatus during lightning storms or when unused for long periods of time Refer all servicing to qualified service personnel Servicing is required when the apparatus has been damaged in any way such as when a power supply cord or plug is damaged liquid has been spilled or objects have fallen into the apparatus the apparatus has been exposed to rain or moisture does not operate normally or has been dropped Refer to the operating instructions for power requirements Be advised that different operating voltages may require the use of different line cord and or attachment plug Do not install the unit in an unventilated rack or directly above heat producing equipment such as power amplifiers Observe the maximum ambient operating temperature listed in the product specification Never attach audio power amplifier outputs directly to any of the unit s connectors To reduce the risk of fire or electric shock do not expose this apparatus to rain or moisture This equipment has been tested and found to comply with the limits for a Class B digital device pursuant to Part 15 of FCC Rules These limits are designed to provide reasonable protection against harmful interference in a residential installation This equipment generates uses and radiates radio frequency energy and if not installed and used in accordance with the
97. ZN 640 01701 Ji Eu yu 22 C10 y2 52 ES d 173 8 2 92154 12194 33 912 918 183 AE J2 ENT P N 740 11287 DRAFTER Q C REV DESCRIPTION CHECKER AUTHOR RWH 4 15 03 CW 4 17 03 1 CHANGED PER DCR 030410 00 CLC 4 17 03 KAB 4 29 03 NOTES LEXICON BOM NUMBER 023 15627 SU ANY INFORMATION ON THIS ALL COMPONENTS TO BE BOTTOM SIDE OF UNLESS OTHERWISE SPECIFIED MOU MAXIMUM DRAWING INSTALLED SIDE OF PCB UNLESS OTHERWISE SP LEAD PROTRUSIONS 100 PERSEDES FROM TOP ECIFIED FROM T ALL COMPONENTS FLUSH AND PERPENDICULAR 909 19 TO PCB PCB ASSEMBLY TO BE PACKAGED IN SHIELDING FARADAY CAGE BAG T ANTI STATIC NON CONDUCTIVE I LY S THE ASSEMBLY IS TO BE PROPER TO PREVENT ANY DAMAGE DURING SOLDER PASTE MASK PER LEXICON D 030 15547 STATIC NER LAYER PACKAGED HIPMENT OC NO BREAK PCB AND CUT EXCESS FLUSH WITH EDGE
98. _ TEMBRA 10 1 87 7 100K 210 0 9 B2 VIDEO REG 8 1 88 1 TEMPI n ENCA IN 9 ue 1 VID_I2C_SCLK 10 1 TEMP2 12 9 C2 EPENCS IN E 9 82 gt 120 10 8 11 1 uns VID SDATA 12 1 B a EP_SDATA IN 12 R172 J R174 13 BGO EP SDATA OUT 13 100 100 a SYNC DETECT 14 J18 FP SDATA 14 1 1 15 9 C2 FP SDATA LTCH 15 CVID_ZON3 16 9 C2 13 83 9 A2 SER_CLKB 1 16 C165 LC170 J29 I 2 7788 DISP RS 17 01 50 T 01 50 9 A2 3 NC 18 4 7 83 DISP RW 19 STAT DATB 5 ge DISP 20 LATCHB M FP D 7 0 FP DO gt 1 8 2 gt 8 FP D1 23 284 AMP_RESET 1179 02 24 10 03 25 AMP POWER SUPPLY CONNECTOR SPARE AD 11 D4 26 TEMPS 12 FP D5 27 45VD TEMP6 13 D6 28 TEMP7 14 D7 29 FLEX 4 30 J27 FPSWITCH1 81 J22 EPSwITCH2 32 2 03 SO FT_RLY 1 i FPSWITCH3 33 1 A3 2 03 MAINS RLY 3 3 35 4 me 1 08 a BROWN OUT 5 5 37 38 ABT16244 39 x 728 SYSLED 30 19 40 1 87 1 87 OVLED 29 v2 20 777 A 2 lexicon BEDFORD 01730 124 oE TITLE APPROVALS DATE U15 DRAWN SCHEM MAIN BD RV8 777 RWH 4 26 02 BOARD INTERCONN DEBUG CHECKED 4 30 02 SEE CODE NUMBER REV lt ac 060 15559 5 ISSUED Cw 5 1 02 JV 4 3
99. approvas ome ASSY DWG ACCESS DRAN 8712703 RV 8 8 12 05 CHECKED 1 6 04 SIZE FSCM NO DWG NO sis 080 15645 1 serie D BRACKET MTG RACK 701 15813 2 CLEAR BAG 5X8 730 02823 2 RACK MT KIT IS OPTIONAL ROUTE RACK MOUNT HARDWARE M 14750 15828 SEE BO 1 REMOVE AAA BATTERIES FROM REMOTE PLACE IN CLEAR BAG CLEAR BAG 2X3 SEN 730 15829 B B TRAY ACCESSORY EX 730 15823 22 LS ANTENNA ADAPTOR a SEE BOM S 55 PUT LITERATURE IN PLACE APPROPRIATE PLACE HERE ES POWER CORD HERE SEE BOM FOR LITERATURE BOM CLEAR 12 12 WEE CERNE DEED 730 06760 TOLERANCES ARE RV 8 RS sm lt 8 7 6 5 4 3 DO NOT SCALE DRAWING SSUED s ix o 1 2 12 15 04 ____________ nv nemen bwvcwo acum ADD LOCTITE TO HANDLES AN 7 12 04 DMC 7 13 04 PER DCR 040624 01 7 13 04 WAG 7 13 04 ADD WSHRS ITEM 36 amp 39 AN 8 13 04 CW 8 26 04 PER 4040803 00 CLC 8 16 04 8 26 04 COVER SCRW ITEM 28 AN 9 21 04 CW 9 30 04 D PER ECO 040831 00 CLO 9 23 04 10 1 04 PER 050503 00 CLO 5 27 05 MAG 7 5 05 SEE 080 15647 FOR FRONT PANEL ASSY TORQUE 10 14 IN LBS 4 PLCS 52 13 PLCS COVER TORQU 8 10 IN LBS SEE NOTE 2 2 PLCS
100. left right analog input pair the phono preamplifier microphone 1 microphone 2 or tuner MAIN 128 IN2 is the serial data stream sourced from the C SUB A D Converter on the Analog Board to the AVRX FPGA This 125 stream is the 24 bit left and right channel data encoded from the number four left right analog input pair MAIN 125 ING is the serial data stream sourced from the SIDE A D Converter on the Analog Board to the AVRX FPGA This 1 stream is the 24 bit left and right channel data encoded from the number five left right analog input pair MAIN 125 IN4 is the serial data stream sourced from the REC A D Converter on the Analog Board to the AVRX FPGA This 125 stream is the 24 bit left and right channel data encoded from a selected left right analog input pair the phono preamplifier microphone 1 microphone 2 or tuner These analog sources are level controlled prior to conversion Note that in all cases the analog sources are level controlled prior to conversion REC ADC FS is the Left Right framing signal for MAIN 125 IN4 sourced from the AVRX FPGA to the REC A D Converter on the Analog Board REC ADC FS64 is the serial clock for the MAIN 128 1 4 data streams This is sourced from the AVRX FPGA to the REC A D Converter on the Analog Board 6 35 RV 8 Service Manual _125_ is the 24 bit serial data stream sourced from the AVRX FPGA to the LEFT RIGHT FRONT D A Converter on the Analog Board MAIN I2S OUT2 is the 2
101. pp 7 12 Speaker EMI Filter Board Assembly nennen nnne 7 14 Video Board Assembly tien E bii Ee E E al m 7 15 Video In Board ASS mbly uu ce eite Rape Ce usia ee ee engi 7 17 Video Out Board 7 17 Power Supply Board Subassembly pp 7 17 Chassis Assermibly edd ae eddie re dente EG ui sai dus 7 18 Mechanical uuu uuu ette pep terne nde acera ade reed ng 7 20 Video Mechanical 7 20 Tuner Preamp Mechanical 7 20 Assembly ette tete tite AY a as tb yasa 7 21 Power Supply Mechanical Assembly pp 7 21 Bridge Rectifier L EAEE NA entree nnns nennen 7 21 VCO Mechanical 7 21 3 Channel Amp Bd Mechanical Assembly pp 7 21 4 Channel Amp Bd Mechanical 4 eene 7 21 Single Positive Heatsink Assembly 0000 nnne nnne 7 22 Single Negative Heatsink Assembly pp 7 22 Double Positive Heatsink 7 22 Double Negative Heatsink 7 22 Mounting Bracket Assembly Option a 7 22 Power Cord Opltioris 1
102. 01730 TITLE 5H DATE SCHEM MAIN BD RV8 RWH 4 26 02 POWER SUPPLY CHECKED 4 30 02 555 CODE NUMBER REV 8 ac 060 15559 CW 5 1 02 FILE NAME 5 ISSUED Jv 4 30 02 15559 6 17 17 or 19 8 6 5 4 3 2 1 is 7 4 3 2 1 REVISIONS DRAFTER Q C REV DESCRIPTION AUTH RWH CW 1 CHANGED PER DCR 020913 00 11 05 02 12 20 02 CAM MAG 11 06 02 12 20 02 RWH CW 2 CHANGED PER DCR 030307 00 5 2 03 5 20 03 CAM MAG 5 14 03 5 20 03 RWH ECM 8 CHANGED PER DCR 030626 00 9 29 03 10 9 03 D CAM MAG 10 2 03 10 9 03 C 45VD REAR PANEL IR INPUT R2 8 b 1K GPIU281 J6 VCC 07 A 2 OUT IR_IN2 9 C8 BAV99 xl SHIELD GND 8 Ui P 1 99 777 y 77 77 t T y po Y R26 77 FP_IR_BLINK gt 12 86 1K 45 05 825 1 2 2K BAV99 B 3 FP IR BLINK RET gt 12 86 777 99 V 777 pe Y v 777 CONTRACT 7 A exicon BEDFORD MA 01730 TITLE DATE SCHEM MAIN BD RV8 RWH 4 26 02 REMOTE CONNECTOR E CHECKED 4 30 02 SEE CODE NUMBER REV Qc 060 15559 3 cw 51 02 FILE NAME S ISSUED JV 4 30 02 15559 6 18 SHEET 18 or 19 2
103. 1 149 1 4 D5 5 D5 6 D4 7 B7 8 B6 9 86 10 C7 12 C7 13 C7 14 B5 15 C5 ADA_SCLK 10 24 4 D5 8 C7 10 C7 12 7 13 C7 14 B5 15 A5 15 C5 gt SDATA OUT 11 AOUTR 21 0 64 12 04 14 07 14 031 E MAIN DIREOT SELL 1 ies f i 10 C4 12 C5 14 D6 12 piro AOUTR 20 415V 13 19 C299 DIF1 AGND 44 16 R230 C253 R188 58 DIF2 VREFL 47 pe A 4 NES532A V 45VD 1 15 ca 316 33063 Rigg 58 1 p DGND BGND 98 1 1145 lt 1 2414 1 C254 1 1200 T 13 42 U61 1 25 T GAP ADG451 42700 as SUB DACOUT R231 C255 R187 16 18 D e 11 A7 AAT Y 316 330 6 3 68 1 1200PF ONB 196 1 166 4 5 027 22K Y 7 8185 15V N 1 21K Tal Hed 15 5 13 12 8 ADG451 5 23 5 8 SUB IN LVL 5 MC33078 vcc VDD s 7 11 S D 10 GND 8153 45V R151 18PF 1 50 57 6K 45V 1 R152 71 3 15V 432K n 196 C470 CENTER DAcoUT 896 E 11 02 CENTER DACOUT gooopr R416 R419 825 47 25 15V 5VD R42 021 x 15 C8 196 n S 825 BAV99 422 2 21K 1 R415 1 13 12 ADG451 RA VDD 715 120 5 s p _7 RELAY OdBFS 7Vrms 35 ee GND 6 FB phis 15V gtt 4 APER 1 2 CENTER OUT 4 5 028 100 RCA gt 4570 44 1 4W Ct 897 C74 15V 13 150 T A 11 C2 SUB DACOUT AA 9 12 825 47 25 15V 5VD 1 2825 2
104. 1 25 1 25 1 25 1 25 1 25 1 25 72 25 72 25 1 25 7425 2 25 T 45 4 25 T 1 25 15V 5V ANALOG BYPASS CAPACITORS 5VA C348 C353 C358 C364 C377 C382 C387 C392 4 25 1 25 T 4 25 T 4 25 1 25 1 25 1 25 1 25 C351 C356 C361 C366 C373 C378 C383 C388 4 25 1 25 T 1 25 T 4 25 1 25 1 25 1 25 1 25 5VA 45V DIGITAL BYPASS CAPACITORS 5VD C78 C92 C98 C103 C128 C130 C132 C135 C137 C140 4 25 1 25 1 25 4 25 T 125 T 4 25 1 25 1 25 1 25 T 4 25 C169 C181 C184 C187 C189 C192 C220 C223 C226 C480 1 25 1 25 1 25 425 T 125 1 25 1 25 T A25 TA25 1 25 3 3V DIGITAL BYPASS CAPACITORS 3 3VD C172 C173 1 C174 1 C175 1 C176 C177 1 178 237 1 372 C472 C478 C479 4 25 p 4 25 p 4 95 1 25 T 4 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 CONTRACT n AGAR PARI NO BEDFORD MA 01730 TITLE APPROVALS DATE SCHEM ANALOG I O BD RV8 DRAWN RWH 8 27 02 CHECKED BYPASS CAPACITORS CBV 8 28 02 SIZE CODE NUMBER REV 060 15579 3 a CW 8 29 02 FILE NAME ISSUED MAG 8 29 02 15579 6 17 r 17 OF 17 7 6 5 4 2 1 10 7 2003 11 05 7 6 4 3 2 1 REVISIONS REV DESCRIPTION DRAFTER CHECKER AUTH RWH CW 1 CHANGED PER DCR 030106 00 PM ECM S VIDEO INPUTS 5VV 5VV 1 21 03 1 23 03 2 CHANGED PER DCR 030421 00 E 2N3904 15 2N3904
105. 1 74 100k lt 10 gt 500k 11 23 12 24 Interna FRONT TUNER FM98 TO ANLG FRONT DIR HEADPHONE OUT FREQ LG FRONT TUNER FM98 TO ANLG FRONT DIR HEADPHONE OUT THD 100 mVrms 100 mVrms 150 mVrms 50 2k 2k 16k None None 25 25 Float dBr Level 0 00 1 75 0 50 0 50 2 00 100k lt 10 gt 500k lt 10 gt 500k 11 23 42 24 Internal Internal LG FRONT TUNER FM98 TO ANLG FRONT DIR HEADPHONE OUT SNR OFF 50 16k 997 None 25 Float THD N Float dBr Leve 2 25 0 10 100k 50 00 60 0 100k 22 gt 22k 23 12 24 23 12 Internal Analog Analyzer Typical Reading Bandwidth ANLG_FRONT TUNER 1050 TO ANLG FRONT DIR HEADPHONE OUT See Bal Gnd Note Left Right Freq Hz EQ Curve Z out Unbal Float Level Measure ANLG FRONT TUNER AM1050 ANLG FRONT DIR HEADPHONE OUT GAIN OFF 150 mVrms Level 1 285 lt 10 gt 500 11 23 ANLG_FRONT_ TUNER AM1050 TO ANLG FRONT DIR HEADPHONE OUT FREQ 1 _ 150mvims 150mVrms 50 1 1 2 3 2 3 5 25 Float dBr Level 0 04 0 25 0 _ 1 0 2 01 21 0 1 5 6 0 35 0 __ 100 lt 10 gt 500k None 11 23 12 24 Internal Analog FRONT TUNER 1050 TO ANLG FRONT DIR HEADPHONE OUT THD 1 _ 400 400mVrms 1 None 25 Unbal Float THD N gt 0 46 3 16 0 10 100k lt 10 gt 500 1
106. 10 22 19 External 44100 Digital DIG ZONE2 COAX3 IN 44K TO ANLG ZONE2 VAR OUT 1 0 00 dBFS 0 00 dBFS None Vrms 4 20 4 50 3 590 a lt 10 gt 500k None 19 n a n a Externa 44100 Digital DIG ZONE2 COAX3 IN 44K TO ANLG ZONE2 VAR OUT THD fe ros 967 is DIG ZONE2 4 IN 44K ANLG ZONE2 VAR OUT DIG ZONE2 4 IN 44K TO ANLG ZONE2 VAR OUT THD 1 2 00dBFS 12 00 dBFS na THD N lt 002 005 0002 100k 22k None External 44100 Digital DIG_ZONE2_OPT1_IN ANLG ZONE2 VAR OUT T j J re s G_ZONE2_OPT1_IN_44K_TO_ANLG_ZONE2_VAR_OUT_GAIN 0 00 dBFS 0 0 dBFS n a na Vrms Level 4 20 4 50 3 590 100k de gt 500k None n a n a External 44100 Digital G_ZONE2_OPT1_IN_44K_TO_ANLG_ZONE2_VAR_OUT_THD 12 00dBFS _ 12 00 dBFS None n a na THD N lt 002 lt 10 22k None n a n a External ZONE2 IN 44K TO ANLG ZONEZ plz cuj HE sh Se DIG ZONE2 OPT2 IN 44K TO ANLG ZONE2 VAR_OUT_GAIN ma vms Level 420 _____ 450 ______ 3 590 lt 10 gt 600 __ 7 9 ma na Exema 44100 DIG ZONE2 OPT2 IN 44K TO ANLG ZONE2 VAR OUT THD 1 12 00dBFS 12 00 dBFS 997 n a n a na THD N lt 002 005 0002 100k lt 10 22k None 7 19 n a n a External 44100 DIG ZONE2 OPT
107. 10 9 03 x 047 5 046 47 2 RWH CW R161 y R58 4 CHANGED PER DCR 031124 00 ine 12 12 0 03 12 30 03 R9 44 5 CAM MAG 74Hauo4 74LCX14 56 RIS er CLKOUT Ya 6 680 NC 1 159 LC160 5 TIMEXPHAL NC _ oE R59 FT 22PF CFGO 22PFT 1 15 CFG1 Ne 015 680 FLAG10 E 16 W180 01 Ji FLAG9 E3 R60 2528 t FLAGS ES 1 MODULATION 3 75 21527 MESI FLAG Ee 680 3 e IRQ0 FLAG6 GND VDD 3 3VD F1 41585 LAGS Gg R61 RBPA FLAG4 GS 5 MODULATION 1 25 U48 875 eR G2 N 680 10K 5 cs FLAG1 6 R62 m FLAGO PA ADSP 21161N py PI No 3 oA M7 RP1 SRP1 RPi RP NS prs HOST BLOCK ONG 10K 10K 10K 2RP4 HEA BRA 18 45 45 4 DSPAB FLASH RST tee BRS NG SPARES Q BR2 2 2 777 SR ABT16244 T pe BRI _ 15 41 8 DMAGI OMIS y M14 NC 40 9 047 J3 DMAG2p 3g 2 R63 13 12 NC CLKDIVBINT 3 38 3 H2 SAL 680 1 74HCU04 4RP2 JRpz R64 047 2 3 DSPARESET E2 RESET 10K 10K U15 5 p08 Cd EMU 2 5 980 74HCU04 Ci 872 pos R65 U46 BIO TRST 680 9 2 TDI
108. 10Hz gt 20kHz LP Internal LG FRONT IN1 TO DIG ZONE2 OUT 96K LG FRONT 1 TO DIG ZONE2 OPT OUT 96K GAIN N1 TO DIG ZONE2 OPT OUT 96K FREQ N1 TO DIG ZONE2 OPT OUT 96K THD N1 TO DIG ZONE2 OPT OUT 96K XTALK J 1 TO DIG ZONE2 OPT OUT 96K DYNRNG LG F IN2 TO DIG ZONE2 OPT OUT 96K LG FRONT IN2 TO DIG ZONE2 OPT OUT 96K GAIN 4 00 Vrms 4 00 Vrms 997 20 oat Leve 0 38 10 40k 20 oat 3 80 Vrms 3 80 Vrms 20 1k 5k 40k 20 Unbal THD N lt 98 00 86 00 n a lt 10 Fs 2 None n a n a 13 Internal 96000 Analog 4 00 Vrms 4 00 Vrms 15k 20 Leve lt 115 00 lt 10 Fs 2 None 13 Interna 96000 4 00 mVrms 4 00 mVrms 997 20 lt 10 Fs 2 None ma 2 14 Interna 96000 4 00 Vrms 4 00 Vrms 9 0 20 0 00 0 10 0 0 25 n a 10 Fs 2 None n a n a 14 Internal 96000 Analog lt 98 00 86 00 88 00 75 00 120 00 n a 10 Fs 2 None n a n a 14 Internal 96000 Analog LG N2 TO DIG ZONE2 OUT 96K FREQ 2 00 Vrms 2 00 Vrms 10 40k 20 Leve LG N2 TO DIG ZONE2 OPT OUT 96K THD 3 80 Vrms 3 80 Vrms 20 1k 5k 40k 20 oat D N 20 oat Leve ____ 115 00 80 00 ______ 13000 4052 None 2 4 9600 Anaog 9 20 D N 108 00 10Hz 20kHzLP Narrow 2 4 9600 Analog ANLG FRONT DIG ZONE2 OUT LG N3 TO DIG ZONE2 OPT OUT 96K GAIN 1 4 00 Vrms 4 00 Vrms 997 20 Unba oat Level 0 38 0 00 1 10 n a lt 10 Fs
109. 12 00 8 00 10 00 4 00 7 00 238 00 16 00 C123 273 275 277 281 C283 285 289 291 293 C297 299 301 305 307 C309 311 312 315 316 C319 322 324 327 330 C332 335 338 340 343 C346 403 405 407 410 C415 417 419 422 427 C429 431 434 439 441 C446 C349 350 354 355 C359 360 363 365 C375 376 380 381 C385 386 390 391 C1 30 448 450 451 C453 454 456 C86 89 93 96 153 156 C157 160 161 164 165 C168 C400 401 412 413 C424 425 436 437 C229 236 240 242 246 C248 252 254 258 260 C230 231 234 235 C227 228 368 370 C470 471 475 C33 34 37 38 41 42 C45 46 49 50 53 54 C57 58 61 62 77 85 C87 88 90 92 94 95 C97 111 114 116 119 C122 124 127 140 143 C144 147 152 154 155 C158 159 162 163 166 C167 169 193 196 197 C202 203 208 209 214 C215 218 226 232 233 C237 262 269 271 272 C274 276 279 280 282 C284 287 288 290 292 C295 296 298 300 303 C304 306 308 310 313 C314 317 318 321 325 C326 329 333 334 337 341 342 345 348 351 353 356 358 361 364 366 369 371 374 377 379 382 384 387 389 392 394 395 397 402 404 406 408 409 411 414 416 418 420 421 423 426 428 430 432 433 435 438 440 442 444 445 C447 457 460 469 C472 474 476 480 C194 195 198 201 C204 207 210 213 PART DESCRIPTION QTY EFFECT INACT REFERENCE INFO C216 217 270 00779 FERRITE BEAD 15 00 FB1 14 33 270 06671 FERRITE CHOKE 2 5 TURN 3 00 FB25 27 270 09799 FERRITESM CHIP 600 OHM 1206 20 00 FB15 24 28 32 34 38 300 10563 DIODESM DUAL SERIES GP SOT23 26 0
110. 14 10K lt 10 10kK 22 8 v4 6 EBOOT LBOOT BMS STATE NC ADDR23 215 DSPB D31 56 DQ31 DHT K2 ADDR Spe 914 DSPB D30 Ai0 24 DSPB_AD10 0 4 HOST BOOT NA 4 NG eens DSPB 029 042 10 66 DSPB A9 M P L1 ADDR2O DATA44 218 DSPE D27 500028 DEPE A7 0 1 1 LINK PORT BOOT Ne 19 DATA43 ET DSPE 50_ 27 T 63 DSPB AG C 8136 ADDRIS DATA42 Ei DSPB D25 47 0026 6 62 DSPB RO Ne 17 Ets DSPB_D24 45 0025 AST 67 A4 1 1 X RESERVED T 1 NC 1 ADDR16 5558021 45 450 DSPE AS DSPB_AT4 ADDRIS 9 DSPB 022 40 ARE ASL27 DSPB A2 DSPB A13 ADDR14 DATAS DSPB 021 390022 A 26 DSPB Ai BMS BECOMES AN OUTPUT A13 C ME 1 DATA37 056 65 39 ns F5 DSPE AO CHIP SELECT FOR EEPROM NC 2 ADDR12 DATA36 EI Bene Dio 37 0020 0 N3 ADDR11 DATA35 612 DSPB D18 0019 100MHZ 59 E DSPB A9 p2 ADDR10 DATA34 DSPB D17 0018 Rene 9 ER ADDR9 ADSP 21161N 014 Bees 33 0017 Dawe 771 E x DSPB A7 R3 ADDR8 DATA32 H15 DSPB_D15 85 Te DSFR 7 7 MEMORY DATA31HH1S 5558 015 870015 DSPB 5 N 0088 H12 DSPB D13 82 5519 DSPB A4 DDRS DATAZ HTS DSPB D12 DSPB_A3 R4 4 DSPB D11 79 SAS P17
111. 2 D29 j 1 o DEUM 02 us m m QO O w J15 ie O 5 RT1 042 E E i 9 5 02381 Do m D27 ui INI D wo Isl allel occ 125024 L JL J D26 THK m ut ace SEE NOTE 7 0 N D22 D23 e B 3o CROWN DOCUMENT INFORMATION NOTES _ 1 HSG BOM NUMBER 23 15826 SUPERSEDES ANY INFORMATION ON THIS DRAWING PART MEMBE 1 45 484255 2 COMPONENTS TO BE INSTALLED ON SIDE OF UNLESS OTHERWISE FOR SCHEMATIC SEE 8680 16179 NOTED BY AN ASTERISK 3 ALL LEADS TO BE TRIMMED TO 0 093 OR LESS 4 UNLESS OTHERWISE SPECIFIED MOUNT COMPONENTS FLUSH AND PERPENDICULAR DEG 1 DEG TO PCB 5 PEB ASSEMBLY TO BE PACKAGED IN A STATIC SHIELDING FARADAY CAGE BAG THAT HAS AN ANTI STATIC NON CONDUCTIVE INNER LAYER THE ASSEMBLY IS TO BE PROPERLY PACKAGED TO PREVENT ANY DAMAGE DURING ae in 1718 W MISHAWAKA RD SHIPMENT WWI gent SOLDER PASTE MASK PER HSG DOC NO 08308 18177 INTERNATIONAL INC WWW CROWNINTL 7 THE VENT HOLE ON TOP OF RELAYS K2 3 MU
112. 2 10 8 7 6 5 4 2 1 D gt 10 16 2003_16 28 8 7 6 4 3 2 1 REVISIONS 3 3VD REV DESCRIPTION DRAFTER CHECKER _ AUTH 74HC4051 RAWH 46 1 CHANGED PER DCR 030106 00 3305 tiM 210 AN R150 1 21 03 1 23 03 1 A6 2 D8 4 D8 Y2 CW COB NC 12 45W 45W 6 8K 2 CHANGED PER DCR 030421 00 250705 5 22 03 ECM MAG 1 A6 2 D8 4 D8 pa NCS Ma 8151 52003 5 22 03 RWH CW 4176 gt 2 MAX4310 Y 8 CHANGED PER DCR 030623 00 E U SHDN ECM 7 RECVID SELO ula 1 10 9 03 10 16 03 9 C3 SEL INO 9 C3 RECVID SELZ e 08072 8 p _________ x 9 C3 OUT RECCVID EN 6 2 i n169 41019 VEE 100K R149 U17 7 5VV 1 75 0 R163 M 5VV 1 5VV R148 750 R164 gu Q25 6 8K 750 NC13 1 36K R110 4 14 3 3K 2N3906 1 C3 2 C8 4 C8 1 C3 2 C8 4 C8 S Y2 9 03 BECSVID YOFF 1 03 2 C8 4 C8 w 1104 R103 R146 NC 5 5 10K R119 SY3 2 1 1 03 573 Y6 1 83 Y7 ms 11 C4 8 SC 1 6 1 25 INH R7 d L L VSS 45VV 45VV 9 09 4 R2 5VV T C1 3 3VD SC_REC2 1 4 3 SYREC2 1 25 2 1 1
113. 2 SROW 13 M SROW 5 M 3 snow 13 Pur SROW 5 4 9 92713 sROW 13 M uc SROW 5 SROW 13 SW15 SW35 SW26 SW17 SW5 SW13 MAIN CD 23 CD TUNER 8 1 2 SROW 14 1 2 SROW 14 1 2 SROW 6 B alt le snow 14 J Hla alt Hla snows SW37 SW19 SW8 MAIN OFF MAIN AUX Z3 AUX TUNER 0 1 2 SROW 7 1 2 SROW 15 1 2 SROW 15 all 3 SROW 7 RPM all ub tla SROW 7 4 113 SROW 15 all 2920 SROW 7 SW41 SW39 SW30 SW21 SW11 SROW 15 0 1 85 2 84 15 SROW 0 4RP15 SROW 4 RP1 SROW 8 4RP4 SROW 12 10 10K 10 10 4RP25 SROW 1 1RF18 SROW 5 3RP26 SROW 9 45 SROW 13 10 10K 10 10 1 2 SROW 2 2 SROW 6 4RP35 SROW 10 2RF47 SROW 14 10 10K 10 10 2RP37 SROW 3 3RP36 SROW 7 RPS SROW 11 1 4 SROW 15 10 10K 10 10 ex CO n 3 OAK PARK BEDFORD MA 01730 APPROVALS 18 SCHEM SW LED BD RV8 DRAWN 7 10 02 FRONT PANEL SWITCH MATRIX CHECKED 7 8 02 SIZE CODE NUMBER REV Q C ECM MAG 7 0 02 7 8 02 060 15569 1 FILE NAME 15569 3 3 0 2003 17 07 SHEET 3 OF 4 M Co 11 2 REVISIONS REV DESCRIPTION DRAFTER CHECKER AUTH LEDCOL2 CW RWH pee B 2 C2 um 1 CHANGED PER DCR 021028 00 MAS 2 2 CAM 2 C2 m EDCOLO 11 5 02 CW RWH 2 CHANGED LED COLOR SCHEME 3 24 03_ 3 26 03 MDVD1 Z2DVD1 Z3DVD
114. 245 12524 CAPSM CER 68pF 50V COG 5 1 00 C21 245 14588 CAPSM CER 01uF 25V X7R 10 06 21 00 C32 36 56 61 62 65 C70 71 77 79 102 103 C107 108 125 128 135 C138 148 154 164 245 14764 CAPSM CER 82pF 50V COG 5 1 00 C99 270 00779 FERRITE BEAD 4 00 FB1 2 16 18 270 11545 FERRITESM CHIP 600 OHM 0805 12 00 FB3 13 15 270 12323 FERRITESM CHIP 750 OHM 0805 1 00 FB14 270 15670 INDUCTORSM 220u0H 2096 1 2A 1 00 L2 300 10509 DIODESM 1N914 SOT23 4 00 D16 21 38 43 300 10563 DIODESM DUAL SERIES GP SOT23 6 00 D1 6 300 10564 DIODESM SCHOTTKY LOW VF SOT23 8 00 D17 20 39 42 300 11599 DIODESM GP 1N4002 MELF 6 00 D22 23 44 45 48 49 300 14286 DIODESM SCHOTTKY 1A SMB 3 00 D24 37 47 310 10566 TRANSISTORSM 2N4401 SOT23 1 00 Q1 310 15669 TRANSISTORSM MOSFET 2A 55V SOT 1 00 Q2 330 09889 ICSM DIGITAL 74ACTO4 SOIC 2 00 U17 28 330 10523 IC HEX INVERTER 74HCU04 SOP 6 00 U3 4 10 23 35 47 330 12143 ICSM DIGITAL 74ACT244 SSOP 1 00 U45 330 12451 ICSM DIGITAL 74VHCT32 SOIC 1 00 U7 330 12452 ICSM DIGITAL 74VHCT244 SOIC 1 00 U2 330 13865 ICSM DIGITAL 74VHC04 SOIC 1 00 U14 330 13876 ICSM DIGITAL 74VHC273 SOIC 2 00 U20 21 330 13882 ICSM DIGITAL 74LCX14 SOIC 1 00 U46 330 14247 ICSM DIGITAL 74VHCT245 SOIC 3 00 U36 37 43 330 15085 ICSM DIGITAL 74ABT16244 TSSOP 1 00 U15 330 15735 ICSM DIGITAL 74VHC139 SOIC 1 00 013 340 09244 ICSM LINEAR 78LS05 5V REG SOIC 2 00 U18 29 340 11597 ICSM LIN TLO72 DUAL OPAMP SOIC 2 00 U11 24 7 2 DESCRIPTIO
115. 272 273 282 283 203 16252 RESSM THIN 1 1 10W 5 11K OHM 16 00 R49 50 64 65 133 134 R148 149 217 218 232 R233 301 302 316 317 203 16253 RESSM THIN 1 1 4W 4 99K OHM 12 00 R11 80 82 95 164 R166 179 248 250 R263 332 334 203 16254 RES MF 1 1W 49 9K OHM VERT 8 00 R10 18 94 102 178 R186 262 270 203 16256 RESSM RO 1 1 4W 107 OHM 4 00 R58 142 226 310 203 16415 RESSM THIN 1 1 10W 825 0 OHM 16 00 R15 16 19 29 99 100 R103 113 183 184 187 R197 267 268 271 281 240 16257 CAP ELEC 2 2uF 160V RAD 20 8 00 C19 22 58 61 97 100 C136 139 240 16260 CAPSM ELEC 2 2uF 50V 20 2 00 C82 121 240 16261 CAPSM ELEC 10uF 50V 20 4 00 C25 64 103 142 240 16262 CAPSM ELEC 4 7uF 16V NPOL 20 8 00 C157 158 161 162 C165 166 169 170 240 16263 CAPSM ELEC 33uF 16V NPOL 20 4 00 C2 41 80 119 244 16265 CAP MYL 0047uF 250V RAD 5 4 00 C29 68 107 146 244 16266 CAP MYL 01uF 250V RAD 5 8 00 C26 28 65 67 104 C106 143 145 244 16267 CAP MYL 33uF 63V RAD 10 4 00 C27 66 105 144 245 10416 CAPSM CER 1000pF 50V COG 5 8 00 C177 184 245 10544 CAPSM CER 220pF 50V COG 5 16 00 C12 13 16 17 51 52 C55 56 90 91 94 95 C129 130 133 134 245 10561 CAPSM CER 100pF 50V COG 5 8 00 C159 160 163 164 C167 168 171 172 245 10973 CAPSM CER 22pF 50V COG 5 8 00 C1 3 40 42 79 81 C118 120 245 16269 CAPSM CER 22pF 200V COG 5 20 00 C5 8 11 44 47 50 83 C86 89 122 125 128 245 16270 CAPSM CER 100pF 200V COG 5 8 00 C14 18 53 57 92 96 C131 135 245 16293 CAPSM CER 1uF 50V X7R 10 48 00 C4 6
116. 34 202 10570 RESSM RO 5 1 10W 120 OHM 12 00 R1 9 28 43 50 202 10599 RESSM RO 5 1 10W 3K OHM 1 00 R30 202 11041 RESSM RO 5 1 10W 680 OHM 19 00 R10 14 16 18 20 27 R29 44 49 202 14584 RESSM RO 5 1 10W 10K OHM 0603 3 00 R15 17 19 202 14792 RESSM RO 5 1 10W 56 OHM 9 00 R35 42 51 205 14586 RESSM NET 5 ISOL 10KX4 4 00 RP1 4 240 09786 CAP ELEC 100uF 25V RAD LOW ESR 1 00 C6 240 13217 CAPSM ELEC 47uF 16V 20 4 00 C1 13 15 245 12485 CAPSM CER 1uF 25V Z5U 20 7 00 C2 5 7 9 12 245 14588 CAPSM CER 01uF 25V X7R 10 06 3 00 C8 10 11 300 10509 DIODESM 1N914 SOT23 3 00 D1 20 31 310 10422 TRANSISTORSM 2N4403 SOT23 3 00 Q1 3 310 10510 TRANSISTORSM 2N3904 SOT23 1 00 Q4 330 15085 ICSM DIGITAL 74ABT 16244 TSSOP 1 00 U1 350 15517 ICSM CPLD RV8 FP V1 00 1 00 U2 4380 13639 LEDSM BLU 30MCB AX ZBEND 2 5MM 16 00 D11 22 30 33 D35 38 40 7 5 DESCRIPTION QTY EFFECT INACT REFERENCE INFO 430 13888 LEDSM RED 60MCD AX ZBEND 2 5MM 12 00 D2 10 21 32 39 430 14527 LEDSM SYEL 250MCD AX ZBEND 2 5 9 00 D12 19 34 453 13899 SWSM PBM 1P1T 6 2MMSQ 200GF 45 00 SW1 45 510 13145 CONN POST 100 HDR 2X7MCG LP 2 00 J1 2 510 15690 CONN FFC 1 25MM 40 POS VERT 1 00 J5 710 15560 PC BD SW LED RV8 1 00 PICK REV 1 PC BOARD 740 11287 LABEL S N PCB PRINTED 1 00 Headhone Board Assembly 245 10562 CAPSM CER 150pF 50V COG 10 2 00 C1 2 270 00779 FERRITE BEAD 3 00 FB1 3 510 11583 1 4 PH JACK PCRA 3C SW TR G PT 1 00 J1 510 15696 CONN FFC 1 25MM 4
117. 5 ACCESSORY ASSY SEE BOM 3 UNIT IN BAG 730 14150 FOAM 730 15821 5 1 PART NUMBERS SHOWN ARE FOR REFERENCE ONLY amp DO NOT SUPERSEDE BOM S 2 PLACE BOTTOM FOAM INSERT IN BOTTOM OF BOX 3 PLACE UNIT IN FOLD WITH CREASES ON BOTTOM SIDE OF UNIT USE CLEAR TAPE SET UNIT IN BOTTOM INSERT B 4 PLACE TOP FOAM INSERT AROUND UNIT 5 PLACE ACCESSORY KIT OF UNIT BETWEEN NOTCHED FOAM BLOCKS 6 CLOSE INNER BOX FLAPS INNER BOX 730 15819 7 ADD ID LABEL TO INNER BOX SPACE PROVIDED SLIP INNER BOX INTO OUTER SHIPPING BOX CLOSE FLAPS AND TAPE 9 PLACE SECOND ID LABEL ON OUTER SHIPPING BOX 7 OUTER BOX ru 8 730 15818 ID LABEL 8 730 15845 2 PLCS 14 2004 84 mas ASSEMBLY DWG m a ass SHIPMENT RV 8 _____ RV 8 l m DWG NO eras uso e sz 8 080 15644 0 APPLICATION __ 00 NOT SCALE DRAWING SSUED N A serio 1 3 2 1 2 1 CHG CALLOUT AN 11 8 04 12 14 04 PER ECO 041013 00 11 18 04 WG 12 14 04 PART NUMBERS SHOWN ARE FOR REFERENCE ONLY AND DO NOT SUPERSEDE BOM S PLACE ITEMS IN TRAY CAVITIES AS SHOWN CLOSE COVER OF COMPLETED KIT AND TAPE n
118. 5885 D 7 0 BES 5985 24 DO RWH 9 9 9 0 Bo 7 B3 2 CHANGED PER DCR 030421 00 5 20 03 5 22 03 955 gt 555 30 pz 10 A5 IDEO DATA 92 spATI psf 28 08 __ 5 20 03 5 22 03 VIDEO SCLK 22 OxA2 28 D4 RWH CW 10 A5 SDATCLK GCK1 D4 3 CHANGED PER DCR 030623 00 UU UN D6 ECM 10 A5 950 68 OSD CS 7 07 2007 10 9 03 10 16 03 10 A5 qREG CS 18 A 15 0 Mone 7783 A 12 4 JTAG PROGRAMMING PORT 3390 3100 avo OM SUV A6 15 Ar R81 883 4882 5 Ao a 47K 16 BLK 2 ATS FLASH INTERFACE NC XC95144XL 97 YEL JTAG TCK 48 TCK ai s 6 JTAG 83 96 15 WES 7 JTAG TDI 45 100 29 18 035 74VHCTOB 8 NC 90 OSD TSC 11 OSD TSC5 OSD TSCp 7 88 GRN 9 JTAG TMS 47 VROM WRD WH gt 77 MVID SELO 2 81 MVID_SEL1 ee 79 MVID_SEL2 78 gt s OxAS 82 MSVID_YOFF ISVID 4 P 7 02 MORPHEN ip gt 2 C6 MTHRUP 35 NC 2 A5 31 DEC HS 2 5 B5 DEC HS 5 85 6 D7 DEC_VS 19 VS 34 93 RECVID SELO 3 08 PAN 3 D8 He cene RECCVID EN RECCVD EN 5 05 PLAYSPEED ol orn 37 RECSVIDYOFFS 1306 60 PAL_EN 3 94 SECAM EN gt j assasi U 10 A5 VIDEO RST 99 RESETN GSR 39 SEL OxA7 36 MORPHEN jc 4 5 C
119. 6 CW 8 29 02 FILE NAME ISSUED MAG 8 29 02 15579 6 12 SHEET 12 OF 17 8 7 6 5 4 3 2 1 6 21 2004_ 14 23 8 7 6 5 4 3 2 1 REVISIONS LEFT amp RIGHT REAR D A CONVERSION OdBFS 1 98Vrms 15V REV DESCRIPTION DRAFTER ch 411 2dB 0dBFS 7 2Vrms CHECKER AUTH 5VD 45VR 4 RWH CW AN R220 C238 R163 CHANGEDPER DCR 02110700 11 14 02 11 20 02 112002 112102 5 330 6 3 8164 n FB16 3 1 214 4 RWH CW 2 1415K5 701951 2 CHANGED PER DCR 030407 00 C285 C281 C278 C240 1 1200PF T 13 12 ADG451 5 21 03 5 23 03 VE 1 sates CBV MAG VDD 5 23 08 5 23 03 47 47 330 6 3 15V 35 p 2 LREAR_DACOUT ng EE DER RWH CW C284 C280 C279 R221 C239 R162 C194 mgs 0729 00 9 29 03 10 7 03 4h m nt IC mde tlie GND CBV MAG 316 330 6 3 68 1 1200PF 10 6 03 10 7 03 1 25 1 25 1 25 1 1 161 4 5 U24 RWH ECM l P i 4 CHANGED PER DCR 031125 00 3 14 64 22K j CBV MAG AK4395 R160 15V 130 04 2 2 04 2 18 RWH CW 2 vp 18 121k 15V 5VD 5 CHANGED R33 36 R92 93 PER ECO 040408 00 90 15 c3 _ _ 17 CHANGED R1
120. 6 1 SHEET 1 OF 17 8 7 5 4 3 2 1 6 21 2004 14 22 8 7 5 4 3 2 1 REVISIONS REV DESCRIPTION DRAFTER Q C 15V CHECKER amt RIGHT ANALOG INPUTS OdBFS 4 0VI 15V 15V rms ELT 1 CHANGED PER DCR 021107 00 91008 j 4 CBV MAG Rie C60 a 14 v 3 MAIN SOURCE SELECT RIGHT 5005 _ RWH CW 1 O E 1 jj 57 TLO72 R80 GND v 2 CHANGED PER DCR 030407 00 RCA 100 816 1025 A 5 51 CBV MAG J15 3 1 4W 4 UB 56 5152 5 23 03 5 23 03 v 1630 y gt R79 7 3 CHANGED PER DCR 030729 00 CW IEE 400K Y 15184 8 RIGHT MAIN IN 8 03 4 08 9 29 03 10 7 03 15V 11155 CBV MAG 10 56 10 6 03 10 7 03 15V 9 15V AO Al A2 EN U12 1 16 15 2 2 R4 5 8 MAIN_ANLG_SEL0 2 C e pe 1072 R76 1 D5 14 D3 MAIN ANLG SEL 1 lt RCA 100 10 25 gt VA 1 D5 14 D3 3 1 4W BAV99 6 U7 56 05 14 03 MAIN ANLG SEL2 4 578 Ae y 1 D5 14 D3 MAIN_ANLG_EN 15V 15V 15V 15V 57 15V don 3 14 3 REC SOURCE SELECT RIGHT GND v N R12 C52 5151 3 mE CU R72 6 92 __ lt RCA 100 4 012 6 2t 1 zi 8 RIGHT REC 8 14W BAV
121. 7 24 32 39 43 C45 46 63 71 78 84 C85 102 110 117 123 C124 141 149 156 C327 328 245 16295 CAPSM CER 4700pF 50V COG 5 1 00 C148 245 16296 CAPSM CER 27pF 50V COG 10 4 00 C30 69 108 147 245 16297 CAPSM CER 47pF 50V COG 10 4 00 C15 54 93 132 245 16411 CAPSM CER 01uF 100V X7R 5 8 00 C20 21 59 60 98 99 C137 138 245 16412 CAPSM CER 47uF 50V Z5U 5 4 00 C23 62 101 140 270 16272 COIL 1 5uH 5 RAD 375LS 4 00 L1 4 7 13 PART DESCRIPTION QTY EFFECT INACT REFERENCE INFO 300 10509 DIODESM 1N914 SOT23 64 00 D1 4 6 9 11 13 16 18 D24 27 29 32 34 36 D39 41 47 50 52 55 D57 59 62 64 70 73 D75 78 80 82 85 87 D97 98 104 300 16200 DIODESM ZENER 5 1V 225mW SOT23 8 00 D20 21 43 44 66 67 D89 90 300 16201 DIODESM ZENER 17V 225mW SOT23 8 00 D19 42 65 88 93 96 300 16202 DIODESM ZENER 16V 500mW SOD123 8 00 D22 23 45 46 68 69 D91 92 300 16203 DIODESM RECT 400V 50A 50NS SMB 8 00 D14 15 37 38 60 61 D83 84 300 16205 DIODESM SW 250V 625mA MELF 8 00 D5 10 28 33 51 56 D74 79 310 10510 TRANSISTORSM 2N3904 SOT23 12 00 Q8 16 27 35 46 54 65 Q73 80 84 88 92 310 10565 TRANSISTORSM 2N3906 SOT23 8 00 Q15 34 53 72 79 83 Q87 91 310 16206 TRANSISTORSM NPN 25V 225mW SOT 4 00 Q77 81 85 89 310 16207 TRANSISTORSM NPN 300V 1W SOT 4 00 Q3 22 41 60 310 16208 TRANSISTORSM PNP 50V 350mW SOT 4 00 Q78 82 86 90 310 16209 TRANSISTORSM PNP 300V 1W SOT 4 00 04 23 42 61 310 16210 TRANSISTOR NPN 300V 1W TO92 12 00 Q9 10 18 28 29 37 47 Q48 56 66 67 75 310 162
122. 702 15803 PANEL REAR RV8 1 00 7 19 PART DESCRIPTION QTY EFFECT INACT REFERENCE INFO 702 15806 PLATE BOTTOM RV8 1 00 CHASSIS BOTTOM 702 15807 PLATE MTG PS RV8 1 00 702 15808 PANEL OPTION BLANK RV8 1 00 REAR PANEL 720 15425 PAD FOOT 1 438OD 563IDX 06THK 4 00 720 16123 TAPE FOAM DBL STK 1 75X 4X 025 1 00 FERRITE TO TUNER CBL 740 08556 LABEL GROUND SYMBOL 0 5 DIA 1 00 740 09538 LABEL S N CHASSIS PRINTED 1 00 REAR PANEL 740 14888 LABEL LIC PAT WARN MC 12 1 00 CHASSIS BOTTOM 740 16015 LABEL 100 120V 50 60Hz 1300W 1 00 For 100 120V REAR PANEL ABOVE AC CONN 740 16017 LABEL 220 240V 50 60Hz 1300W 1 00 For 220 240V REAR PANEL ABOVE AC CONN 750 15827 PWR SUP 5V 15V 65W U BRKT 1 00 750 15828 REMOTE CONTROL RV8 1 00 FP Mechanical Assembly 023 14068 PL IR ENC BD ASSY MC12 B 1 00 023 15616 PL SW LED BD ASSY RV8 1 00 023 15622 PL HEADPHONE BD ASSY RV8 1 00 430 13143 DISPLAY 20 2 CHAR 5X8DOT 1 00 550 13633 BUTTON 276X 572 BLK 16 00 550 13634 BUTTON 276X 572 BLK W LTPIPE 29 00 550 14090 KNOB 2 00X 95H 6MM ALUM PEWTER 1 00 ENCODER 635 14526 SPCR M3CLX6MM 6MMRD 1 00 IR ENC BD 640 01841 SCRW 2 56X1 4 PNH PH ZN 4 00 DISPLAY TO FP 640 10495 SCRW M3X12MM PNH PH ZN 1 00 IR ENC BD 640 10498 SCRW M3X6MM PNH PH BZ 10 00 SHIELD TO FP 640 10498 SCRW M3X6MM PNH PH BZ 11 00 SW LED BD TO FP 640 10498 SCRW M3X6MM PNH PH BZ 2 00 HEADPHONE BRKT 640 15476 SCRW M4X8MM PNH PH ZN 6 00 SPT BRKTS TO FP 680 14693 CABLE 1
123. 74acTo4 BAR35 18 2K 77 177 1 072 U10 9 gt NC T 74HCU04 U10 11 10 74HCU04 U10 13 D 12 NC 74HCU04 44 1K AND 48K 512FS ZZ 88 2K AND 96K 256 FS A CONTRACT ex CO n NO BEDFORD MA 01730 TITLE APPROVAL DATE mn OVALS SCHEM MAIN BD RV8 RWH 4 26 02 VCOA CHECKED 4 30 02 SEE CODE NUMBER REV 8 Qc 060 15559 3 2 Cw 5 1 02 ISSUED Jv 4 30 02 15559 6 15 SHEET 15 19 8 7 5 4 3 2 1 8 7 3 2 1 REVISIONS REV DESCRIPTION DRAFTER Q C CHECKER AUTH 1 CHANGED PER DCR 020913 00 MAG 11 06 02 12 20 02 2 CHANGED PER DCR 030307 00 Dua pecus CAM MAG 15V 5VD 5 14 03 5 20 03 3 CHANGED PER DCR 030626 00 10 2 03 10 9 03 D45 D44 1N4002 1N4002 78L05 VIN VOUT COMMON 4 c92 2367 T 1 25 94 I 10 10 77 5V_B 4 5 VCOB 5V FB12 FB10 FB113 L 693 D38 T 1 25 ee c coe 77 1N914 1 50 C84 R89 C83 3 028 041 Ros 1 2K 47 16 ZONE2_PLL_PUMP_UP 2 415V 74ACT04 BAR
124. 8 User Guide Lexicon P N 070 15838 Required Equipment The following is a minimum suggested equipment list required to perform the proof of performance tests High quality amplifier with RCA input connectors and volume control capabilities A pair of high quality speakers High quality video monitor with composite RCA S video and component RCA input connections High quality DVD player with RCA analog L R outputs digital coaxial and optical outputs and composite S video and component outputs CD disc for a test audio source DVD disc for a test video source DAT recorder with digital coaxial and optical record inputs for testing the digital output of the RV 8 A pair of stereo headphones Variac variable AC power supply 2 amp minimum 0 220 VAC Digital multimeter 3 5 digits 0 5 or better accuracy Low Distortion Audio Oscillator with single ended or balanced analog outputs switchable 2 low pass filter or band pass 20 20 2 filter and output THD N lt 001 Distortion Analyzer with switchable 30Hz high pass filter or band pass 20 20kHz filter Digital Distortion Analyzer RS232 089 wrap around plugs These are created by connecting pins 2 4 3 of a female 089 connector Debug terminal monitor optional Required Cables Shielded audio cable with an RCA connector and an appropriate connector on the opposite end for connection to a Low Distortion Audio Oscillator Shielded audio cable with an RCA connecto
125. 8130 1 25 15V gt 1 00K 15 12 pGa2311 2814 5VD 196 AGNDL VA n mw rms 16 AoOUTL 14 S MC33078 C67 eas 4 D5 5 D5 6 D4 7 87 8 B6 10 C7 11 C7 12 7 13 C7 14 B5 15 C5 gt SCLK 6 4 2 Ut5 4725 R27 FBS 4 5 gt 4 Ent Z SS VC 5 3 EDI Y 8 L ZONE3 LEFT OUT Me i 18PF 330 RCA gt 4 D5 5 D5 6 C4 7 A7 8 87 9 C7 14 B5 15 C5 ADA VG 2 DGND ROI sei RSS v 11 14W 14 B3 ZONE 2 1 402K 15 4 02K 2 113 150 T 4 C5 5 C5 6 C4 7 A7 8 87 9 C7 14 83 spout 2 9 ANR 5 MC33078 C68 2 gt 16 J3 AGNDR VA 6 m R31 FB6 9 C3 R ZONE DACOUT R134 C126 10 Ge U23 96 1 A NEM 2 ZONE3 RIGHT OUT S 1 RY3 330 1 00K 10 25 R91 18PF C6 gt R135 1 1 25 150PF T 100K R133 6120 4 02K 2 1 00K Lae 1 po 1 B li 47 5VA 8 A4 ZONE RLY CNTL CONTRACT 3 OAK PARK NO exICOn BEDFORD MA 01730 TITLE APPROVALS DATE DRAWN SCHEM ANALOG I O BD RV8 SEED RWH 8 770 ZONE OUT LEVELS CBV 8 28 02 SIZE CODE NUMBER REV 060 15579 3 a CW 8 29 02 FILE NAME ISSUED MAG 8 29 02 15579 6 9 9 OF 17 8 7 6 5 4 3 2 1 10 7 2003_11 05
126. AVRX FPGA The optical sources require no additional conditioning and so are routed directly to the AVRX from the TORX connectors The AVRX determines the word clock from incoming S PDIF samples via phase comparison with the system word clock from the on board PLL circuitry The PLL is adjusted until the system word clock is the same as the S PDIF word clock The S PDIF inputs are sampled with a clock that is 1024 times the sample rate in 96 88 2 KHz mode and 2048 times the sample rate in 48 44 1 kHz mode to compensate for sources that display a significant amount of jitter This oversample scheme eliminates the need for a two stage PLL The S PDIF channel status bits from all channels may be read through the host interface DIG REC OUT is sourced from the AVRX FPGA SPORT data from the downmix port of the SHARCs or digital audio data from the Record Zone DAC is converted to a Bi phase mark signal with parity added by the AVRX Format Decoder Interface Signals CRY CLKSEL CRY TXD CRY_RXD CRY SPICLK CRY FCS CRY SCS CRY_INTREQ CRY FINTREQ HINBSY DEC IN FSI DEC IN 5 DEC SDI DEC MCKI DEC OUT SCKI DEC OUT FSI DEC_SDO 3 0 CRY CLKSEL is a programmable bit within the MUTE IR control register that sets the internal operating speed of the Format Decoder When this bit is high the internal logic of the Format Decoder runs at the input clock rate When low the Format Decoder runs at the higher frequency of its internal PLL The
127. After the RV 8 has passed the VFD Test for the rest of the power on diagnostics the VFD displays DIAGNOSTIC TESTS The dots increment in number from both sides simultaneously as the rest of the power on diagnostic tests are completed This keeps you informed as to the functioning of the RV 8 If a failure occurs the test will attempt to enter a loop to exercise signal lines to aid in debugging Display for the Remaining Tests If any of the following tests fail the VFD display and LED matrix will display the test and error fault as previously discussed The VFD will display the test number and the error code In the event that VFD is not operable the same information will be written to the LED matrix The test number will be read out as in the top row The error number can be read out in the second row Most Significant Byte and third row Least Significant Byte AVRX FPGA Test The AVRX FPGA test verifies the ID register can be read from the XC2S200 on the main board If a failure occurs the test will attempt to write the test number and the error number to the VFD CS49400 Test This test verifies that the Crystal 49400 Decoder can communicate with the Host Hitachi processor through the AVRX FPGA If a failure occurs the test will attempt to write the test number and the error number to the VFD Power On Diagnostics Completed After the power on diagnostics are completed the VFD will display the appropriate power up message
128. B N 18 7 247 3 05 26 4 5 47 VIDEO SCLK VID 8 42 RP26 3 V 47 VIDEO DATA 3 88 a DEC 8000 ise dis VID DATA 36 25 2 V7 47 VIDEO REG E li 8 B3 DEC SDOT 123 128 IN2 VID_I2C 29 VID 120 gt 12 83 8 83 DEC 802 125 128 IN3 126 VID 120 gt 12 84 8 83 5003 127 123 IN4 1 50 24 7 2 47 12 03 8 87 EC SD 136 128 OUT ADA_SDATA_OUT 22 RE24 47 OUT 12 04 887 DEC IN FSI 7 2 47 RP24 6 47 SCLK 8 8 DEC IN 8 47 DEC OER ADA LATCH 34 25 4 Y Y5 47 ADA LATCH SEL VG gt 1204 101 17 1 8 47 DIG_REC_OUT MAIN Dar our RP20 8 1 47 MAIN 125 1 gt 13 88 B EXP0 187 9 MASS T E RP20 6 3 47 MAIN 125 OUT2 1 188 1252 OUT 7 RP20 7 V2 47 MAIN 125 0073 MAN 1 EXP2 189 MAE EDU S RP20 5 74 47 MAIN 125 OUT4 125 OUT 4 1 Bes EXP3 191 EXP OUT BE 21 5 V4 47 REC DAC 128 OU E EXP4 192 EXPS AN ise RP22 8275147 MAIN 125 IN4 a EXP5 193 25 1923 23 8 1 47 MAIN FS EXP6 194 EXPS UNES RP21 8 1 47 MAIN 25647 E 1064 EXP7 195 EXPS 564 RP19 8 47 MAIN 5256 EI 199 EXP 26 01022 RP22 6 3 47 REC ADC FS E EXP9 200
129. B5 74 2 14 85 R398 1 A gt J26 1 MAIN 128 OUT1 2 74K R397 5 MAINCI2S OUT 10 C7 15 D5 1 AA 125 11 C7 15 D5 3 MAIN 125 OUT3 2 74K 12 C7 15 D5 4 MAIN 125 4 Q 5 REC DAC 126 OUT 5 MAINZES 4 A4 5 A4 6 4 10 C7 11 C7 12 C7 13 C7 15 C5 7 REC_DAC_FS ee 8 REC ADC FS 9 MAIN FS64 IAS 15V 5VD INPUT SEL AMP 7 AND 3 10 REC DAC FS64 vno ce eae asia REC ADC FS64 15 05 15V Ui LADO 7 A2 15 D5 jal ua 12 MAIN FS256 BUF DG411 C475 13 DAC MCKI Fm VCC VDD 8 ER 14 REC ADC 7 A2 15 D4 13 82 L REAR 35 D 2 3 TLO72 8404 8403 R402 x 1 IN 4 200 AA AMP_7_OUT 15 C8 J20 L 120 422 2 21K VEE GND 15V 5VD lt R406 LA U93 1 1 LEFT amp RIGHT REAR 4 5 U16 100K Y 13 12 15 8407 R_REAR_AMP x dae Se PP las J 221 na 16 5 D 2 R405 1 CONNECTOR FROM SPARES 15V 50 epe ND T eim AUX PHONO BOARD al s ib A 3 13 12 TLO72 3 1 BAT 8200 ae R420 3 ngog 4 OUT1 8 88 2 d 5 MICT RET E 8 83 16 88 L BEC AMP 35 D 2 2 090 120 422 221 6 OUT2 ET NC id 4 1 15V 7 MIC2 RET 3 88 n C2 3 88 VEE GND j 8 RIAA L B 15V 5VD 15V R392 9 RIAALRET 24 993 LEFT RIGHT REC 4 5 U14 j 10 RIAA R 3 D8 1 11 RRET 13 12
130. BYPASS CAPACITORS 5 23 03 5 23 03 3 CHANGED PER DCR 030729 00 ous toos 2 290 070 C33 C37 C41 C45 C49 C53 C57 C61 C77 C81 C83 C85 C87 C90 C94 C99 C100 C102 C106 C108 C110 C133 C138 C143 C147 C149 C151 C154 C158 C162 C166 10 6 03 10 7 03 425 1 25 1 25 1 25 1 25 425 T 425 25 1 25 1 25 T 4 55 1 25 1 25 1 25 1 25 1 25 1 25 425 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 C170 C180 C183 C186 C188 C191 C196 C202 C208 C214 C219 C222 C225 C232 C262 C264 C266 C268 C371 C462 C464 C466 C476 C460 C469 425 1 25 125 125 1 25 1 25 1 25 r 95 7125 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 4 25 1 05 1 25 1 25 4 25 125 1 25 T 4 25 15V BYPASS CAPACITORS C34 C38 C42 C46 C50 C54 C58 C62 C79 C80 C82 C84 C88 C91 C95 C97 C101 C104 C105 C107 C109 C127 C129 C131 C134 C136 C139 C144 C148 C150 C152 425 1 25 1 25 1 25 1 25 4 25 4 25 T 45 25 1 25 T 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 T 1 25 1 25 1 25 C155 C159 C163 C167 C171 C179 C182 C185 C190 C193 C197 C203 C209 C215 C218 C221 C224 C233 C263 C265 C267 C269 C369 C461 C463 C465 C467 C468 C477 425 1 05 125 71 25 1 25 1 25 r 25 125 T 45 r 1 25 1 25 1 25 1 25 1 25 1 25
131. Board Analog IO Board and Amplifier Modules This page also contains the Debug and User Access RS 232 terminal ports RS 232 Transceiver U5 05 is a Maxim MAX202E dual RS 232 Transceiver that runs on 5V whereas most transceivers need 12 V to accommodate the 10V swing intrinsic to RS 232 This device uses charge pump voltage conversion to accomplish this C28 doubles the 5V present in the circuit to 10V storing it on C27 The second charge pump inverts the 10V to 10V storing it on C30 Using this technology the output drive capability on pins 9 and 12 is 8 when loaded with a nominal 5K Ohm RS 232 receiver This conforms to the EIA TIA 232E and V28 specifications for RS 232 The debug transmit signal DEBUG_TXD from the CPU drives pin 11 of 05 This driver is output as TXDA on pin 14 and is ferrite bead de coupled to remove spurious high frequency noise before being output on J4 Signals received from the debug terminal enter the system via J4 pin A3 This signal is ferrite bead de coupled to remove spurious high frequency noise which drives U5 pin 13 as the signal RXDA The output of this driver provides the receive signal to the Host CPU as DEBUG RXD from U5 pin 12 The user transmit signal USER TXD from the CPU drives pin 10 of U5 This driver is output as TXDB on pin 7 and is ferrite bead de coupled to remove spurious high frequency noise before being output on J4 6 40 Lexicon Signals received from the user
132. C9 11 245 15692 CAPSM CER 1uF 25V X7R 10 06 3 00 C3 8 10 245 15736 CAPSM CER 22uF 16V X7R 10 1 00 C5 270 00779 FERRITE BEAD 1 00 FB1 270 15728 INDUCTORSM 6 8uH 10 1 00 L1 340 15088 ICSM LIN LM1117 ADJ 800mA SOT 2 00 U1 3 340 15659 ICSM LIN CRISP TEF6892H QFP44 1 00 U2 510 15729 CONN FFC 1 25MM 13 POS PCRA 1 00 J2 510 16141 CONN MOD RF F W SCRW TERM 1 00 J1 640 01701 SCRW 4 40X1 4 PNH PH ZN 1 00 701 09640 BRACKET KEYSTONE 621 4 40X2 1 00 710 15540 PC BD TUNER RV8 1 00 PICK REV 1 PC BOARD 740 11287 LABEL S N PCB PRINTED 1 00 750 15685 TUNER AM FM 1384 HORIZ PC MNT 1 00 04 IR Encoder Board Assembly 202 00528 RES CF 5 1 4W 820 OHM 1 00 R1 202 00530 RES CF 5 1 4W 1 2K OHM 1 00 R2 202 00531 RES CF 5 1 4W 1 5K OHM 1 00 R3 245 03609 CAP CER 1uF 50V Z5U AX 80 2096 2 00 C1 2 345 14780 IC INTER GP1U28 38kHz IR DET 1 00 U1B 430 10594 LED T1 3 4 IR 1 00 D1 430 14487 LED T1 BLU 430NM 1 00 SYSTEM ON D4 430 14787 LED T1 RED 700NM 1 00 OVERLOAD D2 430 14788 LED T1 YEL 585NM 1 00 IR ACK D3 452 13640 SW RTY ENC 24POS INC B 25L VRT 1 00 SW1 630 14778 SPCR LED T1 375 H 3 00 D2 4 680 14082 CABLE 100 PLUG SCKT 2X7C 3 L 1 00 IR ENC BD J1 TO SW LED BD 710 13690 PC BD IR ENC MC12 1 00 PICK REV 2 PC BOARD 740 11287 LABEL S N PCB PRINTED 1 00 Switch LED Board Assembly 202 09871 RESSM RO 5 1 10W 1K OHM 3 00 R11 13 202 09899 RESSM RO 5 1 10W 47 OHM 1 00 R31 202 10557 RESSM RO 5 1 10W 4 7K OHM 3 00 R32
133. CLK 57 8 47 eA 12 B6 2 B4 N FP SENG EF_ENGAIN 1588 2 03 WRDCLKMON 154 WORDCLK SH7014 2 00 ed 12 86 IN lt a 6 06 8 8 IR_IN2 90 IN 129 APIS 4 5 47 DSPARXD 18 C3 MAIN BS Serr elk 132 RP15 3 V 6 47 DSPASPICLK DIE docs 125 IN 3 1 MAIN 125 IN3 Sen DS Nols 15 2777 47 DSPASEL ED MAIN 125 IN2 io 128 1 3 08 CRY_CLKSEL C MAINPI2S INT 14 MAIN 128 IN1 RDSDAT 38 TUN 12 D3 599 SPDIF IN 4 1 SPDIF COAX IN1 166 gone COAX IN R152 47 DSPBSEU zt HORE SPDIF IN2 CRY_OUT 8 08 SPDIF COAX IN3 167 SbDIE COAX INS QUI 188 RP14 4 5 47 CRY_SPICLK ED B IN 4 1 SPDIF IN1 168 SDI GRY RP14 3 47 CRY FCS E c SEDIE INS 162 OPTO IN2 565 120 565 8 07 SPDIF IN4 160 13 YPP CRY_INTREQ 6 06 m SPASPSFPGA 89 SHRC1 SPORT CRY FINTREQ ND 21 GHYSEINTREQ C 6 C7 RP177 2 47 rog SHRC1 SPORT OUTI WCLKDIV8INT 6 D7 a SPORT WCLKDIVBINT N 3 C8 907 2e SPORT FS N RP18 6 3 47 87 SPORT CK E 907 2t SPORT CLK RP17 6 3 47 RP25 3 6 47 SYNC_DETECT PET 6 87 SP BSPSFPGA 86 SuRC2 SPORT IN1 VID CS 537 25 1 8 47 OSD CSI 12 B4 gt gt SPORT FS
134. CW 1 CHANGED PER DCR 020913 00 S MEN CAM MAG FPGA PROGRAMMING PORT 1106021 12 20 02 5VD 3 3VD 3 3VD 2 CHANGED PER DCR 030307 00 2005 J15 4 CAM MAG 5 14 03 5 20 03 RED vcc o 4 RWH ECM BLK GND 2 2 23 41 44 14 22 32 42 3 CHANGED PER 030626 00 9 29 03 10 9 03 D CCLK 013 5 Noe CAM MAG ME NO 21 ee 10 2 03 10 9 03 I 19 OE RESET BLU D P o GRN DIN 017 Doy XFLASH DIN 9 2 ORG PROG o 6 1 35 9 NC 7 NC D24 gt Ne 8 Nc XC18V02 Da Nc 17156 4 NC 17 31 NC NC 17 ING 05 31 Ne 9 D2 XFLASH CCLK _ 18 NC pe 20 9 22 w FPGA DONE 26 25 NC 1 B8 9 D2 ASH_INIT 1 NC 28 NC 07 9 08 29 JTAG PROGRAMMING PORT Ne se 5VD CNC 38 NO A 9 J16 NC 40 NC XFLASH CF mw ypgj RED VCC 66 NC 43 NC NC BLK GND 072 NC No OTE 52013901 014 JTAGTOK 13 ofS Ne 9 TDI 6 JTAG TDO 11 37 CST ee JTAG TDI GND NC 3 12 24 34 U40 GRN 019 JTAG TMS C 77 77 3 3VD FPGA DONE LED 4 Se R146 046 crap FBIS 74HCUO4 150 et YEL 27 1 25 035 Z U35 3 gt t AUDIO OSC 9 A8 SPARES 74HCU04 74HCU04 47 EXPANSION SLOTS Rigs OPE 4 M Y if U35 C141 L 14 112MHz C140 9 8 NC 5VD 5VD 18PF T T 18PF es 4 4 77 77 34 34 ae 33 33 NC 32 NC 32 010
135. DSPB_A2 T4 ADDRS DATA27 2 DSPB D10 77 0011 WE P29 DSPB A1 ADDR DATA26 J14 DSPB_D9 76 0010 csp T ADDR1 DATA25 bag DSPB A0 M5 DSPB D8 74 DQ K DEEP DATADS 15 DSPB 13 pay 88 P54 22 12 DSPB_D6 NC _ MS2 211 14 DSPB D5 10 005 Nce 13 NC DSPB D4 898 6 70 NC Mso0 DATA19 K13 DSPB D3 7 NC4 69 DSPABWR WA DATAT DSPB 02 NGA 57 4 B7 gt 55PABRD Req WR M13 DSPB D 4 30 NC 4 87 RD DATA17 2 NC2 30 4 87 BRST S BRST DATA16 14 DSPB DO NE 4 87 sbAio M10 VSSQ vss NCO 5 P13 U27 BMS _CAS SDWEPRIS SDCKEL SDCLKO SS NC SDCLK1 uM U34 SPARES P1 DSPBSDRAMCS no PIA 10K CONTRACT x A 9 lexicon BEDFORD MA 01730 TITLE APPROVAL DATE DERW OVALS SCHEM MAIN BD RV8 RWH 4 26 02 DSP B EXTERNAL MEMORY CHECKED 4 30 02 See CODE NUMBER REV o ac 060 15559 3 amp CW 5 1 02 FILE NAME ISSUED JV 4 30 02 15559 6 5 sHEET 5 or 19 8 8 7 6 5 4 2 1 i
136. DTS ES Matrix 6 1TM e DTS Digital SurroundTM e DTS Virtual 5 1TM e Surround 6 1 C O S 6 1 TM e THX Surround EXTM e THX Ultra2 CinemaTM The 125 audio streams coming in to the Format Processor are interrogated via the DSPAB SPI port and its status is reported back to the CPU The SPI port for DSPAB is selected by asserting CRY FCS low CRY FINTREQ is an open drain output that is asserted low when DSPAB has control data that requires the host CPU attention This signal is pulled up to 2 5V by a 3 3K resistor Provision is made to utilize the SPI signals for SHARC U16 DSPASPICLK DSPARXD and DSPATXD This provision would be selected by installing R101 R103 and R104 and de installing R100 R102 and R105 This provision is not implemented in this application HINBSY is an output signal the status of which is latched into a control register within the FPGA The CPU polls this register bit If this bit is high it indicates that either DSPAB or DSPC has not read data written via SPI No other data may be written until this bit is cleared to 0 internally All SPI signals are broken out to test points for ease of monitoring Unused Pins Pins CS WR RD AO 1 HDATA 7 0 FAO FA1 FDATA 7 0 CMPREQ CMPCLK LRCLKN SCLKN SDATAN 3 0 All above listed pins function either as parallel host interface pins or as unused audio channel inputs As such they are unused in this application and therefore are pulled up to
137. HALF 2 18 07 02 11 20 02 aa 9 D7 CBV MAG 11 20 02 11 21 02 RWH CW SIDE INPUT LEVEL CONTROL 2 CHANGED PER DCR 030407 00 5 21 03 5 23 03 CBV MAG LEFT_SIDE_IN 45VA 5 23 03 5 23 03 RWH CW RIGHT SIDE 3 CHANGED PER DCR 030729 00 C335 CBV MAG 15V 5VD 10 6 03 10 7 03 C354 4 CHANGED PER DCR 031125 00 Pid n 13 12 peat 5VA CBV MAG ET CO 5 i OdBFS 2 0V 1 25 4 1 30 04 2 2 04 e MC33078 2 0Vrms 3 B6 4 C8 7 D8 1 D 3 R248 15 12 PGA2311 lt R271 A VEE GND Bey 909 aie AGNDL gt 10 Y 16 14 LEFT SIDE __ 4 5 U51 P S ook ANL AOUTL 6 B8 12 D5 y 1 4 D5 5 D5 7 B7 8 B6 9 B6 10 C7 11 C7 12 C7 13 C7 14 B5 15 C5 5 6 vp 4 A5V L MIC INPUT a 337 Case 15V 5VD d 4 D5 5 D5 7 A7 8 87 9 C7 9 87 14 B5 15 C5 ADA_VC_SEL 2368 DGND 5 13 2 4 C5 5 C5 7 A7 9 C7 14 B3 MAIN VC 2 1 zcEN 77 SAR e VDD 8 4 C5 5 C5 7 A7 8 87 9 C7 9 87 14 B3 8 MUTE 7 VC 2 17 87 3 86 4 C8 7 c8 MIC2 IN ig S p 15 E t 5 7 R251 9 11 RIGHT SIDE IN LVL PE 5 SIDE IN 6 As 12 B5 VEE GND 909 14 c3 e SIDE SEU lt R252 1 R253 AGNDR VA 4 5 U51 100K 1 00K 10 13 U66 R272 V 71 gt 100K 15V C333 1 25 C332 47
138. LEVEL CONTROL 5 21 03 5 23 03 I CBV MAG VEE GND 5 23 03 5 23 03 5VA 4 5 1044 3 CHANGED PER DCR 030729 00 oues Y CBV MAG C312 10 6 03 10 7 08 EL 415V 5VD 47 4 4 C313 VA LLLA 13 12 1 25 J LEFT_ZONE_IN 6 SOE 7 15 12 PGA2311 gt R260 1 83 3 83 8 5 D gt 10 AGNDL VA Veri LEFT SIDE IN HALF i aL LEFT REAR IN LVL cut J SI 6 VD 4 14 07 14 C3 ZONE_DACOUT_SEL y __ ZONE DIRECT SEL VC 4 3 L C314 C315 14 06 15V B B5 VC _ SDIN puer 14 66 1 15Y 5VD 4 D5 5 D5 6 C4 7 A7 8 B7 9 B7 14 B5 15 C5 ADA_VC_SEL 2 5 A 13 12 4 C5 5 C5 6 C4 7 A7 14 B3 MAIN ZCEN 1 zcEN 77 90411 4 C5 5 C5 6 C4 7 A7 8 B7 9 B7 14 B3 SDOUT 9 87 18 41 R REC s D SECZONE 9 A7 VC MUTE 8 7 5 REC DAC 88 15 R ZONE DACOUT RIGHT SIDE HALF B RIGHT_REAR_IN_LVL ree ON AGNDR VA 4 s U44 10 13 U63 5 C310 gt AU 215 15V 5VD 1 25 5 6311 1 i 3 12 47 VDD 2 63 3 A3 RIGHT ZONE IN ls 110 11 5VA GND al 5 U44 ZONE OUTPUT 15V LEVEL CONTROL 5VA 15V li R28 252 LZONEAMP gt HAsielcal 120 Baci 9 D3 L ZONE DACOUT 3 MC33078 R131 C125 47 R32 lt R132 2 Y Took gne Y 5 AA R_ZONE_AMP 15 A8 16 B8 100K 0 120 b
139. NUMBER LISTING IS FOR REFERENCE ONLY AND DOES NOT SUPERSEDE THE BOM 022 15609 CHASSIS ASSY ACAD 2002 FILE NAME 15646 43 ANGLES TITLE a Fas CHASSIS 080 15646 4 2 _______ 1 REVISIONS REV DESCRIPTION DWR CHKD Q C AUTH SCRW M4X8MM PNH PH ZN 640 15476 2 PLCS TORQUE 8 10 IN LBS BRACKET SUPPORT COVER D 701 15454 BRACKET L 701 15847 2 PLCS NUT amp WASHER SUPPLIED WITH ENCODER P N 452 13640 KNOB 2 00 X 95H SCRW M4X8MM PNH PH ZN TORQUE 5 7 IN LBS 550 14090 640 15476 4 PLCS TORQUE 8 10 IN LBS BUTTON BLK 550 13633 16 PLCS a P d p SPCR M3 CL X 6MM 6MM RD a 635 14526 dd NUT SUPPLIED IR ENC BD ASSY P d WITH 1 4 JACK 023 14068 B TORQUE 4 6 IN LBS ROUTE DISPLAY CABLE OUTSIDE THE SHIELD BUTTON BLK W LT 550 13634 29 PLCS CABLE 100 PLUG SCKT 2X7C 43 2 680 14082 REF FROM IR ENC BD 7 2 LED VERT 720 15849 MAY 20 2004 CABLE 100 PLUG SCKT 2X7C 7 PLCS eae 680 14693 NOTE PIN 1 OF CABLE MOUNTS TO SHED PIN 13 ON DISPLAY NOTES 701 14858 1 PART NUMBER LISTING IS FOR REFERENCE ZN ONLY AND DOES NOT SUPERSEDE BOM TORQUE 4 6 IN LBS A UNLESS OTHERWISE SPECIFIED ACAD 2000 FILE p s Bi e ETT TITLE TORQUE 4 6 IN LBS Rix 1 Z ASSY DWG MECH aii FP RV 8
140. Ne B 1 1 74H 4 EXPA 17 0 3 EXPB 17 0 b SR 11 044 30 ua EXPBO 30 EXPA1 29 EXPB1 29 28 28 035 2 27 1 2 27 M 13 12 NC 26 EXPB3 26 1 o 25 4 25 4 24 24 5 23 5 23 22 22 EXPA6 21 1 EXPB6 21 M EXPA7 20 EXPB7 20 19 19 18 1 EXPB8 18 7 9 17 EXPB9 17 16 16 EXPA10 15 1 EXPB10 15 M EXPA11 14 EXPB11 14 18 13 12 12 7 12 12 EXPA13 11 EXPB13 11 10 10 EXPA14 9 1 14 9 M EXPA15 8 EXPB15 8 7 7 EXPA16 6 T EXPB16 6 EXPA17 5 EXPB17 5 4 4 2 C3 RESET 3 1 2 C3 RESET 3 1 2 2 CONTRACT 7 A 1 NO 25 J30 BEDFORD MA 01730 APPROVALS pate 77 07 BD RV8 DRAWN 4 26 02 FPGA FLASH 3 CHECKED 4 30 02 SEE CODE NUMBER REV 060 15559 3 ISSUED Cw 5 1 02 880 JV 4 30 02 15559 6 10 sHEET 10 or 19 8 7 6 5 4 3 2 1 8 2 1 REVISIONS REV DESCRIPTION LECKER UE 1 CHANGED PER DCR 020913 00 y ret 10 88 2 CHANGED PER DCR 030307 00 CW 47 RP32 EXPB0 EXPB 17 0 10 86 i 5 20 03 EXP1 47 RP32 EXPA1 51403 52003 4
141. SOFT RLY signal is made inactive BROWN OUT is a monitoring signal from the amp power supply that will trigger an NMI if the power supply rails drop by more than 10 of their nominal voltage This will place the RV 8 into a standby mode with the amplifiers shut off until the supplies have stabilized 6 43 RV 8 Service Manual S PDIF IO Sheet 13 The AVRX FPGA receives eight S PDIF streams from the back panel Four are from coaxial sources requiring signal conditioning and amplification The remaining four are from optical sources that go directly to the FPGA Record S PDIF outputs are available as a single coax and a single optical signal This page also illustrates the Zone 3 video output Coax S PDIF Inputs J1 and J2 are dual stacked RCA connectors Each input is protected by a spark gap providing a path for ESD discharges made to the connectors C1 R1 C3 R2 C5 R3 and C7 R4 present a standard impedance to the incoming S PDIF signals C2 C4 C6 and C8 provide AC de coupling for each of the signals as they enter the amplifier stage D1 D4 provide diode clamp protection of the amplifiers by ensuring that the input stages are never subjected to voltages greater than 5V nor lower than DGND U3 and U4 are configured as amplifiers by R5 R12 by forcing the gates to run in a semi linear region The effective result is that each input gate acts as an amplifier with a gain of 10 increasing the amplitude of the input stream from 0 5V to 5V
142. THD L Y O F LG MAIN DIR IN345 TO AN AMP1 OUT PWR VS THD 30 75 100 0 75 1 00 a o CC ag 0 75 1 00 THD N lt 0 010 020 5 0001 00 gt gt 22k None 1 0 2 0 Internal LG_MAIN_DIR_IN345_TO_AN N_AMP2_OUT_PWR_VS_THD 0 75 1 00 gt 140 50 22 gt 22 0 Internal Anal H 0010 Ho 22 22 _2 _ 6 0 memi Analo LG MAIN DIR IN345 AMP3 OUT PWR VS THD 2 22k 3 o 6 0 na Anao 30 75 41 00 lt 0 010 gt gt 22k 3 0 6 0 Internal Anal LG_MAIN_DIR_IN345_TO_AN N_AMP4_OUT_PWR_VS_THD 0 75 1 00 gt 140 50 22 gt 22k None E Analog 30 75 1 00 0 75 41 00 600 lt 0 010 22 gt 22k None 4 0 3 0 Internal Analog LG MAIN DIR IN345 TO AN N AMP5 OUT PWR VS THD 0 75 1 00 0 75 1 00 600 gt 140 50 i 22 gt 22k None k c Analog 0 75 1 00 600 Unbal lt 0 010 0 020 k 22 gt 22k None 5 0 1 0 Internal Analog 0010 IR NDERIT LG MAIN DIR 14345 AMP7 OUT PWR VS THD puso ence m ks piss pisos 1 u 2 7 e 2 0 75 1 00 30 75 41 00 lt 0 010 020 0001 100 e gt 22k None 5 0 Internal nsi ANLG MAIN DIR 1 345 ANLG MAIN OUT VS TH LG MAIN DIR IN345 TO ANLG MAIN AM
143. Ta NJM2229 15 vs C175 ve T 2 74HC02 Us VIDEO IN VSYNC OUT VSYNC 7 C8 7 14 R249 cim SYNCDETOUTD im 680K SyNcpETouT 13 5VAS T CSYNC OUT SYNC DETECT 10 A6 R253 R250 30 1K C176 R247 Bs 10K 1 AFC IN 32 MM INT 19K 5 74HC02 7 4 GMHSYN MM TC AFC OUT F 6 gt 7 C8 SYNC U42 E 018 GND INTEGR AFC FILT VCO FILT VCO OUT Y m 5 3 5 R246 58254 6255 212 22K 22 V 7 R252 C173 390 R251 M 5VV 5VV p 1 5K 503KHZ 5VV R248 C177 180 C179 C181 100K 2 1000PF T 1 507 T 3300 74HCO2 10 v 4 R243 ORT U42 74HC02 11 10K V 12 X 8242 7 475 1N914 172 1 3 3VD 74HC4053 16 R241 1K BPCOR CONTRACT con NO lexicon BEDFORD MA 01730 TITLE DC RESTORER AEE ROVERS DALE SCHEM VIDEO BD RV8 DRAWN RwH 8 9 02 5 SYNC STRIPPER CHECKED 8 28 02 SIZE CODE NUMBER in Q C cw 8 28 02 FLENAWE 060 15589 ISSUED MAG 8 28 02 15589 3 8 sHEET 8 or 10 6 5 4 3 2 1 gt 10 16 2003_16 28 8 7 6 5 4 3 2 1 REVISIONS 3 3VD REV DESCRIPTION DRAFTER CHECKER RWH CW 1 CHANGED PER DCR 030106 00 ee mud 210 LEL 1 21 03 1 23 03
144. Verify a clean undistorted picture appears on the monitor S video Input to Component Video Output Test This test will verify the Video Up Conversion functionality of the RV 8 Setup oO N Connect the S video output from the DVD player to the RV 8 s S video input 1 Connect the RV 8 main component video output to the component video input of the video monitor Turn on the DVD player monitor and the RV 8 The monitor should display a blue screen On the RV 8 remote control press the MAIN button then press the DVD1 button to select DVD1 as the input for testing the video paths Press the remote control Menu arrow to display the Main Menu Using the Menu arrow scroll down to SETUP Press the Menu arrow to select the SETUP menu The SETUP Menu will appear with INPUTS highlighted Press the Menu arrow again to open the INPUT SETUP menu 4 26 Lexicon 10 DVD1 will be highlighted 11 Press the Menu arrow The DVD1 INPUT SETUP menu will now be displayed 12 Using the Menu arrow scroll to the VIDEO IN parameter and select it by pressing the menu arrow 13 The DVD1 VIDEO IN menu will be displayed Using the Menu arrow scroll to the S VIDEO 1 parameter and select it by pressing the Menu arrow 14 Press the Menu 4 arrow to exit the DVD1 VIDEO IN menu 15 Using the Menu arrow scroll the COMPONENT IN parameter Select it by pressing the Menu gt arrow 16 The DVD1 COMPONEN
145. all of the analog audio inputs and outputs level controls and A D and D A converters This board is located below the RV 8 Video Board There are three separate signal paths Main Zone2 and Zone3 Each of the eight analog stereo inputs the tuner the phono or any of eight digital inputs can be routed to any of the three paths The schematics refer to Main Rec and Zone Rec is named for Zone2 and Zone is named for Zone3 on the back panel Main Audio Paths One of the eight analog stereo inputs the tuner or the phono can be routed to the main path and to the A D convertor s In addition one of the eight digital inputs can be routed from the main board The A D digitizes the analog signal if selected and passes it to the DSP on the main board Digital signals from the main board pass directly to the DSP Refer to the Main Audio Paths 2 Input block diagram below The DSP creates eight different output signals from the 2 channel input D A converter IC s convert each of the eight signals from the DSP to analog and then send them to their respective RCA connectors The outputs are also sent to the seven channels of amplification with channels 6 and 7 having the ability to be redirected A direct analog path is provided which passes a 2 channel analog input signal directly to the Left and Right Front outputs via the level controls bypassing the DSP and converters Main Audio Paths 2 Channel Input
146. amplifier outputs Power on the RV 8 and repeat steps 5 to 7 Repeat steps 5 to 9 to test the RV 8 amplifier outputs for the rear left rear right and center channel outputs RV 8 Service Manual Phono Input To Main Zone Outputs Test This test will verify the audio path between the Phono inputs labeled left and right to all Main Zone Outputs Test 1 Connect the low distortion oscillator output to the Phono left and right inputs on the rear panel of the RV 8 2 Connect the RCA front left and front right outputs of the RV 8 to the external amplifier left and right inputs Connect the outputs of the external amplifier to the pair of speakers Using the Menu arrows scroll through the Diagnostics Menu and select the AUDIO I O TESTS In the AUDIO I O TESTS menu highlight AUDIO PHONO TEST Press the remote control Menu gt arrow to engage the test The RV 8 is now set to route audio from the Phono left and right inputs to all Main Zone outputs 5 Power on the external amplifier Slowly increase the volume on the external amplifier to a comfortable listening level 6 Sweep the oscillator from 20Hz to 20kHz Verify that clean undistorted audio can be heard throughout the frequency sweep Power down the external amplifier Repeat steps 5 through 7 for the remaining paired RCA outputs center sub side L R and rear L R Digital Inputs to Main Zone Outputs Test This test will verify the audio path between the S PDIF coax
147. circuit 6 50 Lexicon S video inputs Video board schematic sheet 1 Specific references are to input 1 other inputs are similar S video luminance inputs pin 3 of the mini din jacks are terminated and buffered the same as composite inputs AC coupling is applied after buffering C25 couples s video 1 luminance Chrominance input 1 pin 4 of mini din jack J15 is first ac coupled by C24 and then buffered by emitter follower Q19 The dc level at the chroma input pin is direct coupled to subsequent sense circuitry through the voltage divider formed by R70 and 71 Main Monitor Composite S video Video board schematic sheet 2 Composite and S video luminance connect to multiplexers 020 021 and S video chrominance connects to 022 The composite multiplexer is addressed by the MVID_SELn bits and the S video multiplexers addressed by MSVID_SELn bits When MCVID_EW is asserted low 018 is enabled and all MSVID_SELn bits are forced to 0 by logic in CPLD 014 sheet 9 Composite multiplexer 020 selects one composite source With MSVID SELn set to 0 the s video path is disabled because 021 is selecting disconnected input and U22 is selecting a grounded input to feed the chrominance channel When MCVID EN is high U20 is disabled disconnecting the composite inputs and U14 passes addresses to the MSVID_SELn bits allowing 021 and 022 to select one of the S video sources The composite luminance MY signal from U20 U21 i
148. coupled to the CRISP processor U2 via C3 C5 and C2 respectively R2 and C4 form a de emphasis filter for the FM MPX signal but as we are decoding this from the combined FM RDS stream this option is left unused R1 provides the FM RDS signal to both the RDS and FM inputs of U2 Signal Processor U2 The signals provided by tuner module 04 are processed by 02 a Philips TEF6892H device This is a signal processor with on board DSP that is intended for use in car audio systems Although signal paths for Cellphone CD player and Cassette Tape are provided they are unused in this application All radio signal de multiplexing and enhancements are made via this device The AM signal is processed to remove noise caused by external sources such as AC line disturbances and path loss and gain controlled based upon the signal strength as provided via the LEVEL signal pin 1 AM is introduced into the device via pin 7 and the FM RDS via pin 6 The AFSAMP and AFHOLD pins 10 and 9 respectively are provided with the sample and hold control signals from the tuner block and in conjunction with the LEVEL pin are used to provide an average voltage of the radio signal levels which in turn determines signal strength The FREF signal from the tuner is introduced by pin 11 and is internally divided down to provide the de multiplexing pilot signals for FM and for the RDS Volume and Equalization are controlled within U2 via the bus pins SDA and SCL pins 4
149. instructions may cause harmful interference to radio or television reception which can be determined by turning the equipment off and on The user is encouraged to try to correct the interference by one or more of the following measures Re orient or relocate the receiving antenna Increase the separation between the equipment and the receiver Connect the equipment into an outlet on a circuit different from that to which the receiver is connected Consult the dealer or an experienced radio television technician for help SUMMARY The following general safety precautions must observed during all phases of operation service and repair of this unit Failure to comply with these precautions or with specific warnings elsewhere in these instructions violates manufacturer safety standards and intended use of this unit Harman Specialty Group assumes liability for failure to comply with these requirements GROUND THE INSTRUMENT To minimize shock hazard the unit chassis and cabinet must be connected to an electrical ground The unit is equipped with a three wire grounding type plug It will only fit into a grounding type power outlet This is a safety feature If you are unable to insert the plug into the outlet contact your electrician to replace your obsolete outlet Do not defeat the safety purpose of the grounding type plug DO NOT OPERATE IN AN EXPLOSIVE ATMOSPHERE Do not operate the unit in the presence of flammabl
150. low pass filtering and pull up networks for these quadrature signals See page 6 30 for further information regarding these signals FP SDATA IN is the signal by which the AVRX FPGA receives data back from the CPLD on the Front Panel Board with regards to the status of the pushbutton array FP SDATA OUT is the signal by which the AVRX FPGA transmits data to the CPLD on the Front Panel Board in order to write to the LED array SDATA CLK is the clock signal that controls the serial shift of data up and back from the FPGA front panel FP SDATA LTCH is a signal that marks the beginning of an eight bit sample being transmitted to the front panel All four of these signals comprise the SPI interface to the front panel DISP RS is an address decoded bank select for the VFD DISP RW is an address decoded read write strobe for the VFD When this signal is high the VFD registers are in read mode When low the registers are in write mode DISP E is an address decoded global enable of the VFD FP D 7 0 is an eight bit data bus to the VFD register accesses to the VFD are made via this bus FPSWITCH 3 1 are breakout signals from the RIGHT MODE MAIN DVD2 and ZONE 2 DVD2 buttons on the front panel The Host CPU monitors these signals The boot up state of these switches determines the operational mode RV8 will enter once boot up is complete See page 6 8 for further details Supply voltages 3 3VD and 5VD are both needed to power the Front
151. migrated to the DRAM for execution The data bus from the CPU is one word wide as mandated by the fact that all instructions are word length As all accesses are word wide the address bus to the DRAM is oriented on word boundaries hence the 10 bit address beginning at CPUADDR1 instead of CPUADDRO Boot Mode Jumper Selection The RV 8 supports multiple booting options to aid in software development In the final product only one of these modes is available booting from FLASH as described on page 6 15 For development booting may be accomplished from either the EEPROM or the ROMulator by proper jumper selection as 6 13 RV 8 Service Manual implemented in W3 W4 and W5 The following table illustrates the various modes available to the developer Boot Mode Jumper Configuration Uninstalled Default Boot and Program Run from FLASH Boot from EEPROM FLASH Program Run Boot and Program Run from ROMulator 23 Boot from ROMulator Program Run from FLASH FLASH U26 The FLASH RAM used in this product is a 1Mx16 120nS device There is a sector of memory of 16Kwords available at the bottom of the memory array This is intended for use as a boot sector and can be write protected to prevent erasure when updates to the system or algorithm software are being programmed This write protect is enforced or disabled by the state of the WP pin 14 This pin is under software control by the CPU When this pin is low protection is en
152. on DSPASP3FPGA DSPASPOFPGA SPORT FS A Nis the frame sync signal for DSPASP3FPGA and DSPASPOFPGA DSPASPOFPGA is an input data stream in SPORT format to SHARC1 Samples from the outputs of the Format Decoder and from the various system inputs are multiplexed and mapped through the Input Source Look Up Table to this data signal DSPBSP3FPGA is the MAIN audio return signal from SHARC2 in SPORT format The data present in this stream is converted to S PDIF and 125 formats and mapped via Look Up Table to the output ports SPORT B is the serial shift clock for the data present on DSPBSP3FPGA SPORT FS B Nis the frame sync signal for Video Interface Signals SYNC DETECT OSD CS VIDEO SCLK VIDEO DATA VIDEO REG VID I2C DATA VID SCLK SYNC DETECT is a signal that indicates the presence or absence of video synchronization from the Video Board This signal is stored in the Interrupt Status Register at bit 7 There is no interrupt assigned to this signal so the host processor simply polls this bit for its status 050 CS is the chip select for the Fujitsu MB90092 OSD Controller device located on the Video Board This signal becomes active when transfers are initiated via the Video OSD SPI interface Transfer initiation takes place when the two byte commands for the MB90092 have been written to the OSD Controller RAM While the transfer is in progress bit 6 is set in the Serial Interface Status Register
153. or it can be derived from the fixed crystal reference signal AUDIO OSC When the incoming master clock is too low compared to the reference a series of active high pulses are sent to the VCO forcing it to increase the output frequency until a phase match occurs between the reference and the master clock When the incoming master clock frequency is too high compared to the reference a series of active low pulses are sent to the VCO forcing it to throttle back on the output frequency until phase match occurs When the two are matched a series of low going pulses to the VCO that sustains oscillation at a stable point Further discussion as to the theory of VCO operation will be made later in this document MAIN PLL PUMP UP is an active low signal that forces the master clock to increase in frequency when the master clock rate is lower than the reference frequency MAIN PUMP is an active low signal that forces the master clock from the VCO to decrease in frequency when the master clock rate is higher than the reference frequency MAIN LOCK is an active low signal that keeps the master clock from the VCO at a stable rate of oscillation when the master clock is equal to the reference frequency MAIN PLL FPGA MCKO is the master clock output from the VCO for the Main Zone A set of analogous signals exists for the Zone 2 PLL circuitry Their function is exactly the same as their Main Zone counterparts so further discussion would be
154. power up mode of this pin is low CRY TXD transmits control data to the Format Decoder utilizing a modified SPI Serial to Parallel Interface protocol Control data is written to the internal Format Decoder SPI Control RAM by the system software and serially shifted out via this pin CRY RXD receives control status information from the Format decoder in serial form This data is stored within the Format Decoder SPI Status RAM and is polled by the system software CRY SPICLK is the shift clock used by the SPI protocol to serially shift data into and out of the Format Decoder The speed of this clock is controlled by CRY CLKSEL This clock must be in slow mode when programming the Format Decoder FLASH RAM during boot up CRY FCS is the chip select for the DSPAB section of the Format Decoder This chip select is enabled when bit in the SPI Chip Select Register is set high This register bit must be set before data is written to the Format Decoder SPI Control RAM The DSPAB section of the Format Decoder is responsible for all algorithm decoding as listed on page 6 27 SPI transfers are initiated when the Format Decoder SPI DMA Block Size Register is loaded with the number of bytes to be transferred When a transaction has been completed the host processor must reset the chip select bit low CRY 5 5 is the chip select for the DSPC section of the Format Decoder This chip select is enabled when bit 1 in the SPI chip select register is set high T
155. protocol is 19200bps 8 O 1 8 data bits Odd Parity 1 Stop Bit Serial Debug Cable The cable required to connect the RS232 serial debug port to the computer is a straight through serial interface cable A null modem adapter or cable should not be used The RV 8 RS232 connector on the rear panel is a D9 female so one end of the serial cable must be a D9 male The other connector on the cable depends upon the RS232 connector used on the computer The computer may have a D9 or a D25 male connector Typically computers have a D9 for COM 1 and a D25 for COM 2 However some newer computers use a D9 for both COM 1 and COM 2 The COM port used on the computer does not matter however you must ensure that whatever serial communications program is being used has the correct computer COM port selected Serial Debug Program The serial debug program controls the communication from an RV 8 to a computer This program allows a user to view activity of the unit and to control and configure the unit for testing The debug program is used extensively to perform audio and video testing of a unit in the audio and video ATE programs Error Codes The error codes for the diagnostic tests that report additional failure information consist of six parts as described below E tXX aYYYYYY wZZZZZZ rQQQQQQ E Failure Number The E stands for error and the hexadecimal number after the E indicates test number from the list below tXX Error Codes List
156. read together If a time out occurs then B2 or B1 will indicate what operation caused the fault BO will indicate which processor failed Processor A or B Bit B3 is used to indicate whether the SHARC was able to run the code If this bit is zero the code was not able to run a 1 indicates the SHARC was able to run Bit B4 indicates whether the test passed or failed This bit is only valid if B3 is a 1 Bit B5 indicates that the read back register failed There is a fault in the read back register circuitry if this bit is a 1 Bit B6 indicates whether the circuitry around the SHARC LEDS failed A 1 indicates a failure When the SHARC passes these tests it will return a value of 0x0300 aYYYYYY Failing address location The address in hexadecimal where the failure occurred wZZ Value Written The target value in hexadecimal that was written to the address where the failure occurred 5 5 RV 8 Service Manual rQQ Value Read The actual value in hexadecimal that was read from the address where the failure occurred POWER ON DIAGNOSTICS As described earlier there are two power on modes in the RV 8 You can power on via the rear panel power switch or by bringing the RV 8 out of standby mode Power on diagnostics are executed every time the rear panel power switch is switched on Diagnostics are not run when the unit is brought out of standby The power on diagnostics take approximately fifty seconds to complete The powe
157. rear panel main power switch 3 When LEXICON appears on the display press and hold the Zone2 DVD2 and Zone3 DVD2 buttons on the front panel within twenty seconds 4 Continue to hold down the buttons until the RV 8 display reads DIAGS MENU FUNCTIONAL TESTS Analog Inputs To Main Zone Outputs Test This test will verify the audio path between the paired analog inputs 1 to 8 and all Main outputs Test 1 Connect the low distortion oscillator output to the left and right analog audio inputs labeled 1 on the rear panel of the RV 8 2 Connect the RCA front left and front right outputs of the RV 8 to the external amplifier left and right inputs Connect the outputs of the external amplifier to the pair of speakers 4 14 Lexicon Using the Menu arrow scroll down through the Diagnostics Menu and select AUDIO I O TESTS In the AUDIO I O TEST menu highlight AUDIO INPUT 1 TEST Press the Menu arrow to engage the test The RV 8 is now set to route audio from the left and right analog inputs labeled 1 to all Main Zone outputs Power on the external amplifier Slowly increase the volume on the external amplifier to a comfortable listening level Sweep the oscillator from 20Hz to 20kHz Verify that clean undistorted audio can be heard throughout the frequency sweep Power down the external amplifier Once complete repeat steps 5 through 7 to test the remaining paired RCA outputs Center Sub Side L R and R
158. same pin The module also provides a field strength signal in the form of a proportional DC voltage at pin 15 Incoming signal strength and quality are further represented by the AF_SAMP and AF_HOLD signals pins 20 and 19 respectively These signals are used to control an off module sample and hold that will store the average value of the analog signals output by the module The processor chip U2 contains the sample and hold function A reference signal of 75 4kHz is available for external processing via the FREF pin pin 21 This signal is typically divided down to 38kHz and 19kHz to provide demultiplexing of the RDS signal information and the left and right audio samples of the FM program material respectively CPU command and control to the module is provided an C bus comprised of a serial data stream SDA pin 11 and a serial shift clock SCL pin 10 Station selection via the on board PLL synthesizer as well as selection of AM or FM programming is accomplished this 1 bus Two voltage supply rails are present on this module VCC5 pin 5 is a standard 5V supply input that powers the digital logic inside the module while all of the analog functionality such as the PLL synthesizer signal strength and signal quality control is powered by VCC8P5 pin 6 This is an 8 5V DC supply The five volt rail is de coupled by C10 and C11 while the 8 5V rail is de coupled by C8 and C9 The AM AF signal FM MPX and the FM RDS signals are AC
159. several seconds and the test will attempt to enter a loop to exercise signal lines to aid in debugging SH Flash Checksum Test The SH Flash Checksum test verifies U26 on the Main Board has the correct program by adding up all the values in memory and checking it against the value stored The checksum is reported to the Serial Debug Port The test verifies that the calculated checksum matches the checksum value stored in the flash If an error occurs an attempt will be made to blink the standby LED using a rate of a two blinks per several seconds and the test will attempt to enter a loop to exercise signal lines to aid in debugging SH DRAM Test The SH DRAM test performs write and read testing on the DRAM The test uses patterns 0 00 OxFFFF 0x5555 and OxAAAA Once each location in the DRAM is verified a walking 1s check is done to test address buss integrity If an error occurs an attempt will be made to blink the STANDBY LED using a rate of three blinks per several seconds and the test will attempt to enter a loop to exercise signal lines to aid in debugging 5 6 Lexicon VFD Test The VFD vacuum fluorescent display performs a busy test and a memory test The busy test sends information to the VFD and verifies that the VFD asserts then de asserts its busy status The VFD memory test consists of writing 55h AAh a walking 1 and finally a 0 to the character generator memory and display memory space of the VFD and reading them back
160. signal is used to reset the state machines controlling the LED matrix and the switch status SYSTEM ON LED is a buffered equivalent of the SYSLED signal which is driven directly by the Host CPU The SYSTEM ON LED is one of three LEDs located behind the VFD lens on the front panel 6 41 RV 8 Service Manual OVLD LED is a buffered equivalent of the OVLED signal which is driven directly by the Host CPU The OVERLOAD LEDis one of three LEDs located behind the VFD lens on the front panel U15 provides the buffered signals from the CPU to the Front Panel Board FP IR BLINK is a repeater signal from the ZONE 2 remote control detector plugged into the back of the RV8 This signal causes an infrared LED to blink which in turn is sensed by the front panel IR detector FP IR BLINK RET is the return current path from the front panel infra red LED FP IR IN1 is the output signal from the infra red detector on the front panel Whenever a signal from a hand held remote control is detected the IR detector outputs a Hamming Code signal to the AVRX FPGA which then decodes the command The Host CPU then reads and processes the code accordingly FP IR ACK is a signal driven directly from the Host CPU to a front panel LED indicator This LED flashes whenever a hand held remote control access has been made It serves as a visual verification that the remote signal is being received FP ENC A B IN are rotary encoder output signals R172 R175 C165 and C170 are
161. the CS0 memory space the memory boot space is 16 bits wide and that the on chip PLL is operating in 4X mode The processor runs from a 6 25MHz clock supplied by a CPLD device see schematic sheet 7 into the EXTAL pin 74 With 4X PLL operation the internal bus of the processor runs at 25MHz This clock is sourced to the rest of the system via the PA15 CK pin 83 The PLL is biased and noise filtered by an external network comprised of R125 R126 C120 and C121 Serial Ports Signals DEBUG RXD DEBUG TXD USER RXD USEH TXD The CPU provides two asynchronous serial ports which are used as a debug port and as a user port The debug port is implemented by RXDO 51 and PA1 50 Connecting a hyperterminal to this port grants the user access to the debugging and register editing tools built into the boot code During the boot phase each step of the process is echoed to the terminal via this debug port as well as any initialization failures that may occur The debugger allows the user to manually change register values within the CPU and each of the peripheral devices attached to the host It will also allow the running of configuration scripts to test various functions and features included in the RV 8 Re programming the system FLASH is also called into service via the debugger 6 10 Lexicon The user port is implemented by PA3_RXD1 48 and PA4_TXD1 47 Connecting an HDI emulated hyperterminal to this port allows access to
162. the system software at the code level This port is also used to download new code to the FLASH device Serial Port Settings Each serial port must be set to the following protocols in order to work properly with hyperterminal connections 19200 Bits Per Second 8Bits e Odd Parity e 1 Stop Bit e Flow Control set to None Interrupts Signals BROWN_OUT CPU_CRYIRQ CPU_DSPABIRQ CPU_KYBDIRQ CPU_VIDTUNIRQ The CPU has provisions for six interrupt sources of which five are used The highest priority interrupt is the Non Maskable Interrupt NMI 76 This interrupt monitors the status of the amplifier power supply If the voltage rails should drop by more than 10 as would happen during brown out conditions the interrupt is triggered and the unit goes into standby mode This is the BROWN_OUT interrupt Ferrite bead FB14 suppresses spurious signals that may falsely trigger an NMI The next level of interrupt is implemented within the IRQO 49 domain This interrupt is dedicated to monitoring the status for the front panel pushbutton array An interrupt is generated when the button is pressed and a second one when it is released This is CPU_KYBDIRQ IRQ1 46 is currently unused It may be used as an interrupt source monitor or a general purpose in the future IRQ2 43 monitors the status of the SPI port transfers to and from the algorithm DSPs Currently this interrupt is masked off by the system software but it remai
163. to ON Press the remote control MAIN button then press the remote control DVD1 button to select DVD1 as the input for the Main Zone 7 Onthe RV 8 rear panel locate the Trigger Outputs block Connect the DMM s red probe to positive and connect the black probe to negative Measure the PWR and the 1 trigger outputs for 12 Volts DC RS232 Test This test will verify that the RS232 port 1 on the back of the RV 8 is functioning normally by comparing the transmitted signal at pin 2 to the received signal at pin 3 Test 1 Qo E or Connect the video monitor to the main composite video output of the RV 8 and turn the monitor on This will allow full viewing of the RV 8 s Diagnostics menus Power on the RV 8 using the main power switch on the rear panel When LEXICON appears on the display press and hold the Zone2 DVD2 and Zone3 DVD2 buttons on the front panel within eight seconds Continue to hold down the buttons until the RV 8 display reads DIAGS MENU FUNCTIONAL TESTS Turn the volume knob until REPAIR TESTS is displayed on the front panel Press the Mode button on the front panel to enter the REPAIR TEST menu Turn the volume knob to the right until 85232 WRAP TEST appears on the display Press the front panel Mode button until the display reads INSERT WRAP PLUGS Connect the wraparound plugs to pins 2 and of the female DB9 connector labeled 15232 1 on the back of
164. to a brown out reduction in AC Line Voltage Setup 1 The RV 8 should be powered on normally through the Variac 2 Wait for the RV 8 to complete its power up initialization 3 Verify that all seven of the Amp Status LEDs at the bottom of the front panel are lit Test 1 Slowly turn the Variac voltage down until the RV 8 display indicates PP BROWN OUT CYCLE POWER Verify that all seven of the Amp Status LEDs at the bottom of the front panel are OFF Set the Digital Multi Meter DMM to measure AC Volts reading on the highest range Disconnect the AC Line cord from the rear of the RV 8 Verify the voltage at the AC Line cord is between 80 and 90 VAC N 4 3 RV 8 Service Manual Power Supplies The following tests and information will verify the voltages and handling issues of the RV 8 Lethal voltages are present on the RV 8 heat sinks DO NOT come into contact with the Amplifier Output Transistors or the heat sinks Power Supply Discharge time is more than ten minutes unless manually discharged Whenever the RV 8 covers are removed the amplifier channels carry a lethal voltage Stay clear of them when testing the inside of the RV 8 When replacing the channels it is important to discharge them before removing them from the chassis Follow the safety and handling procedures below when service is required inside the RV 8 Discharging The Power Supply 1 The unit must be disconnected from
165. wiring harness into the connector J15 120 on the Power Supply Board to the left of the transformer Set the Digital Multi Meter DMM for a DC resistance reading on the highest range Set the rear panel power switch of the RV 8 to the 1 ON position Test 1 Verify the resistance between the Line Brown pin and chassis ground is an open circuit 2 Verify the resistance between the Neutral Blue pin and chassis ground is an open circuit 3 Install the top cover P N 700 15809 4 2 Lexicon Power On Complete Supply Test This test will verify that there are no shorts from the transformer secondary winding to ground Lethal voltage will be present during this test DO NOT come into contact with the Amplifier Output Transistors or the Heat Sinks Power Supply Discharge time is more than ten minutes unless discharged using a discharge box Setup 1 5 rear panel power switch of the RV 8 to the 0 OFF position 2 Connect one end of the AC power cord to the RV 8 and the other end to the Variac 3 Power on the 4 Setthe Variac voltage to 120VAC Test Test 1 Setthe rear panel power switch of the RV 8 to the 1 ON position 2 While monitoring the current draw on the Variac after approximately sixty seconds verify that the current draw is less than 1 0A 0 85A typical and all seven amplifier channel LEDs are lit Brown Out Test This test verifies that the unit responds
166. 0 02 15559 6 12 SHEET 12 OF 19 3 8 7 6 5 4 3 2 1 7 6 5 4 3 2 1 REVISIONS REV DESCRIPTION DRAFTER CHECKER AUTH 5VD 1 CHANGED PER DCR 020913 00 N MAG 11 06 02 12 20 02 RWH CW c4 D2 R7 R8 2 CHANGED PER DCR 030307 00 515103 BAV99 MAG BLK 01 50 MAS 2 2K 5 14 08 5 20 03 l R2 gt 3 CHANGED DCR 030626 00 Saw ZZ us MAG the 13 012 SPDIF COAX IN SPDIF_COAX_IN 4 1 wee 10 2 03 10 9 03 SVS 74HCU04 74HCU04 A 0 R9 R10 BAV99 BLK 00150 47K 2 2K J 3 1 m 1 4 27 5 U4 U4 010 COAX IN4 45VD 74HCU04 74HCU04 4 D R11 R12 BAvee X 3 BLK 0150 MAS J2 L 75 27 1 4W 777 U4 04 2 SEDIE GONGIN S PDIF RECORD OUTPUTS 74HCU04 74HCU04 C 45VD Di R5 R6 t 9 99 GP1F55T SPARES BLK py 0150 47K 2 2K VEG J1 3 l L
167. 0 D1 24 28 29 300 11599 DIODESM GP 1N4002 MELF 10 00 D25 27 30 36 310 10566 TRANSISTORSM 2N4401 SOT23 3 00 Q1 3 330 13865 ICSM DIGITAL 74VHC04 SOIC 1 00 U53 330 13882 ICSM DIGITAL 74LCX14 SOIC 2 00 U76 91 330 14642 ICSM DIGITAL 74VHCT14 SOIC 1 00 U96 330 15878 ICSM DIGITAL 74LVC1G04 SC70 2 00 U94 95 340 01525 IC LINEAR 7905 5V REG 1 00 073 340 10552 ICSM LIN MC33078 DU OPAMP SOIC 25 00 U13 15 32 37 52 U54 57 68 71 U77 80 86 89 340 10877 ICSM LIN 4556 DUAL OP AMP SOIC 1 00 030 340 11559 ICSM LIN LM317M ADJ REG DPAK 3 00 U74 75 92 340 11597 ICSM LIN TLO72 DUAL OPAMP SOIC 13 00 01 8 17 31 72 90 93 340 12062 ICSM LIN LM3940 5 3V REG TO263 1 00 U85 340 15493 ICSM LIN PGA2311 VOL 5V SOIC 7 00 U22 23 63 67 340 15699 ICSM LIN NE5532A DUALOPAMP SOI 4 00 U45 48 346 10549 ICSM SS SWITCH DG408 SOIC 6 00 U10 12 19 21 346 14451 ICSM SS SW DG411QUAD 1P1T SOIC 13 00 U9 14 16 18 38U40 44 49 51 346 14583 ICSM SS SW ADG451QUAD 1P1T SOI 6 00 U24 29 350 16126 ICSM CPLD RV8 ANALOG V1 00 1 00 U39 355 14761 ICSM DAC AK4395 24BIT VSOP 5 00 U58 62 355 15677 ICSM ADC PCM1804 24b 192kHz SO 4 00 U81 84 410 11639 RELAY 2P2T DIP 5V HI SENS 8 00 RY1 8 510 03961 CONN POST 100X025 HDR 2MCG 1 00 W1 510 13149 CONN RCA PCRA 1FCGX2V WH RED G 15 00 J1 15 510 14079 CONN POST 156X045 HDR 4MC LOK 1 00 J19 510 15687 CONN FFC 1 25MM 13 POS VERT 1 00 J24 510 15688 CONN FFC 1 25MM 16 POS VERT 1 00 J23 510 15690 CONN FFC 1 25MM 40 POS VERT 1 00 J26 510 1
168. 0 mE 150 11 5 02 11 6 02 CW RWH 2 CHANGED SHEET 4 PER DCR 030320 00 32403 CAM MAG D 3 25 03 3 27 03 RWH CW CHANGED SHEETS 2 amp 4 PER DCR 030821 00 4749 03 11 17 03 D 220 9 23 03 9 26 03 IR ENCODER BOARD CONNNECTOR 5VD J2 4 1 2 3 4 5 FP_IR_IN1 6 7 8 LED 9 MAIN BD CONNECTORS 1 EE ENGR N 2 3904 12 13 3 3VD 3 3VD K 14 5VD 5VD 3K Qs JA Q4 777 1 2 RESET C 3 SYSTEM ON LED 2 88 C 4 FP IR BLINK 5 FP IR BLINK RET NOTES 5 AK 1 UNLESS OTHERWISE INDICATED RESISTORS ARE 1 10W 8 OVLD LED VFD CONNECTOR 9 FP ENCA IN 2 UNLESS OTHERWISE INDICATED RESISTORS ARE 5 10 FP ENGB IN Ji 3 UNLESS OTHERWISE INDICATED CAPACITORS ARE UF V 15 u 2 C8 5 07 5 4 gt DIGITAL lt ANALOG CHASSIS _ POWER i4 FP SDATA CIK 2 C8 Ds 1 GROUND GROUND GROUND GROUND 2 C8 15 FP SDATA LTCH gt 2 C8 02 5 5 XX XX DENOTES SHEET NUMBER SECTOR 16 D3 6 TZ DISP RS EP D 3 6 LAST REFERENCE DESIGNATORS USED C15 040 15 Q4 R51 RP4 18 NC SWA45 U2 19 DISP RW 9 20 DISP EN 7 COMPONENTS MARKED WITH amp 11 NC 12 18 FE LC6 DOCUMENT CONTROL BLOCK 060 15569 FP D 7 0 1090F SHEET REVISION TITLE 2 10F4 FRONT PANEL CONNECTORS 2 OF 4 FRONT PANEL CPLD 1 FRONT PANEL SWITCH MATRIX B S L Row SROW 15 0 40 4 3 FRONT PANEL LED MATRIX 34 NC 2 84 3 87 35 36 37 38 39 40 L RIBB
169. 00 630 12533 WSHR FL 120IDX 250DX 062 RUB 16 00 FANS TO CHASSIS 7 18 DESCRIPTION QTY EFFECT INACT REFERENCE INFO 635 15322 SPCR M3X8MM RD HEXHD BLIND ZN 16 00 FANS TO CHASSIS 640 01711 SCRW 6 32X1 4 FH PH ZN 4 00 PS TO PS MTG PLATE 640 01721 SCRW 8 32X3 8 PNH PH ZN 4 00 HANDLES TO R PANEL 640 02377 SCRW 4 40X1 4 PNH PH BLK 1 00 MAIN BD TO R PANEL 640 10498 SCRW M3X6MM PNH PH BZ 6 00 CTR PLT TO CHAS L amp R 640 10498 SCRW M3X6MM PNH PH BZ 2 00 OPT PNL TO REAR PNL 640 10498 SCRW M3X6MM PNH PH BZ 4 00 MAIN BD TO CTR PLATE 640 10498 SCRW M3X6MM PNH PH BZ 5 00 ANLG BD TO CTR PLATE 640 10498 SCRW M3X6MM PNH PH BZ 4 00 VIDEO DBs TO R PNL 640 10498 SCRW M3X6MM PNH PH BZ 2 00 TUNER ASSY TO R PNL 640 10498 SCRW M3X6MM PNH PH BZ 2 00 BTM PLATE TO FP 640 11284 SCRW M3X8MM FH PH BZ 16 00 FANS TO CHASSIS 640 13645 SCRW M4X10MM FH SCKT BZ 13 00 COVER TO CHASSIS 640 15346 SCRW M5X16MM PNH PH ZN 4 00 FEET TO CHASSIS 640 15476 SCRW M4X8MM PNH PH ZN 4 00 XFRMR TO BRKT 640 15476 SCRW M4X8MM PNH PH ZN 6 00 PS amp TORROID ASSY TO CHASSIS 640 15476 SCRW M4X8MM PNH PH ZN 6 00 3CH AMP TO CHASSIS AND R PANEL 640 15476 SCRW M4X8MM PNH PH ZN 2 00 PS MTG PLATE TO CHAS 640 15476 SCRW M4X8MM PNH PH ZN 8 00 AMP TO CHASSIS AND R PANEL 640 15476 SCRW M4X8MM PNH PH ZN 4 00 F PANEL TO CHASSIS 640 16140 SCRW 4 40X5 16 THMB RH SS 1 00 TUNER PREAMP TO RP 641 01703 SCRW TAP AB 4X1 4 PNH PH ZN 8 00 ACCESS PLATE TO CHAS 641 11466 SCRW TAP 4X3 8 PN
170. 00 140 00 100k _ lt 10 gt 22k 5 17 Internal 9 9 pue E E x i 9 9 e A z z z 2 5 N N N lt 3 a lt 5 ZONE2 TO ZONE2 DIR FIX OUT RELAY MUTE LG ZONE2 PHONO IN TO ANLG ZONE2 DIR FIX OUT N LG ZONE2 PHONO TO ANLG ZONE2 DIR FIX OUT XTALK ANLG ZONE2 PHONO IN ZONE2 DIR FIX OUT SNR ZONE3 TO ANLG ZONE3 DIR VAR OUT LG 2 IN1 TO ANLG ZONE3 DIR VAR OUT GAIN LG 2 1 TO ZONE3 DIR VAR OUT LG 2 IN1 TO ZONE3 DIR VAR OUT LG 2 1 TO ZONE3 DIR VAR OUT XTALK LG ZONE3 IN1 TO ANLG ZONE3 DIR VAR OUT SNR LG ZONE3 IN2 TO ANLG ZONE3 VAR OUT LG ZONE3 IN2 ANLG ZONE3 DIR VAR OUT GAIN LG 2 IN2 TO ZONE3 DIR VAR OUT FREQ LG ZONE3 IN2 TO ANLG ZONE3 DIR VAR OUT THD LG ZONE3 IN2 TO ANLG ZONE3 DIR VAR OUT XTALK LG 2 IN2 TO ANLG ZONE3 DIR VAR OUT S LG ZONE3 IN3 TO ANLG ZONE3 DIR VAR OUT LG 2 IN3 TO ANLG 2 DIR VAR OUT GAIN LG 2 IN3 TO ANLG ZONE3 DIR VAR OUT THD LG 2 IN3 TO ZONE3 DIR VAR OUT X LG ZONE3 IN3 TO ANLG ZONE3 DIR VAR OUT S LG ZONE3 4 TO ANLG ZONE3 DIR VAR OUT LG ZONE3 4 TO ZONE3 DIR VAR OUT LG 2 IN4 TO ANLG ZONE3 DIR VAR OUT LG ZONE3 4 TO ZONE3 DIR VAR OUT XTALK LG 2 4 ANLG Z
171. 00 RWH 2 CHANGED PER DCR 000925 01 KB 10 20 00 10 20 00 CHANGED FROM 24K TO 1 5 2 Ron 010130 00 oo USO KB KB 1 30 01 1 80 01 45VD 4 IRM 8755 H2 3 SEE NOTE 4 VCC SEE NOTE 4 IR FLASHER SYSTEMON OVERLOAD IR ACK SHIELD GN 45VD 45VD 45VD D2 id D3 id RED YEL IR AUXRET R2 im 28 SEE NOTE 4 DATA 5 5 5 SYSTEM ON LED OVLD LED LED NOTES 1 UNLESS OTHERWISE INDICATED CAPACITORS ARE UF V ENCODER A 2 DIGITAL ANALOG 1 CHASSIS POWER ENCODER B 777 GROUND V GROUND GROUND GROUND 3 LAST REFERENCE DESIGNATORS USED C2 D4 J1 SW1 U1 4 INSTALL ONE ONLY OF B C SW1 1 1 1 CONTRACT 277 lexicon BEDFORD 01730 5 pare TITLE DRAWN cw 10 27 99 SCHEM IR ENC BD MC12 CHECKED 10 27 99 CODE NUMBER REV Gc 060 13699 3 10 27 09 FILENAME ISSUED 10 27 99 13699 3 1 sHEET 1 OF 1 7 6 5 4 3 2 1 1 30 2001 15 17 8 7 6 5 4 3 2 1 REVISIONS REV DESCRIPTION DRAFTER CHECKER AUTH RWH CW 1 CHANGED PER DCR 020913 00 pum 6 11 06 02 12 20 02 RWH CW 2 CHANGED PER DCR 030307 00 4 29 03 5 2 03 D NC 1 EXPO0 2 3 EXPO2 4 5 4 6 EXPOS 7 EXPO6 8 7 9 5VD CS1
172. 00 PLUG SCKT 2X7C 10 5 1 00 SOLDER TO DSPLY DSPLY TO SW LED BD 701 14858 SHIELD 6 7X1 8X 4 H 1 00 701 15454 BRACKET SUPPORT COVER MC8 1 00 701 15816 BRACKET HEADPHONE BD RV8 1 00 701 15847 BRACKET L SUPPORT COVER RV8 2 00 FP TO COVER 702 15800 PANEL FRONT RV8 1 00 703 14098 LENS 6 36X1 55 MC12 1 00 720 15849 LIGHT PIPE LED VERT 13D 7 00 Video Mechanical Assembly 023 15618 PL VIDEO BD ASSY RV8 1 00 023 15619 PL VIDEO IN BD ASSY RV8 1 00 023 15620 PL VIDEO OUT BD ASSY RV8 1 00 640 10498 SCRW M3X6MM PNH PH BZ 4 00 VIDEO BD TO BRKT 641 13116 SCRW TAP AB 4X3 8 FH PH BZ 15 00 VIDEO BD TO BRKT 701 15815 BRACKET VIDEO BD RV8 1 00 Tuner Preamp Mechanical Assembly 023 15621 PL MIC PREAMP BD ASSY RV8 1 00 023 15627 PL TUNER BD ASSY RV8 1 00 635 15337 SPCR M3X25MM 6MM HEX 1 00 TUNER BD TO BRKT 640 02715 SCRW 4 40X1 4 FH PH ZN 1 00 TUNER BD KEYSTONE TO BRKT 640 10498 SCRW M3X6MM PNH PH BZ 1 00 SPCR TO BRKT 640 10498 SCRW M3X6MM PNH PH BZ 2 00 MIC PREAMP TO BRKT 640 10498 SCRW M3X6MM PNH PH BZ 1 00 TUNER BD TO SPCR 7 20 DESCRIPTION QTY EFFECT INACT REFERENCE INFO 641 13116 SCRW TAP AB 4X3 8 FH PH BZ 1 00 RCA CONN TO BRKT 641 13116 SCRW TAP AB 4X3 8 FH PH BZ 2 00 TUNER BD TO BRKT 701 15814 BRACKET TUNER RV8 1 00 Fan Assembly 410 15839 FAN 60X60X10MM 12VDC 10CFM 1 00 525 12536 CONN CONT CRIMP 22 26AWG AMP 2 00 527 12537 CONN HSG CRIMP 100X2 POL LK 1 00 Power Supply Mechanical Assembly 023 15826 PL
173. 0000 This strobe acts as a clock signal for register device U21 on sheet 2 The table the next page illustrates the register control 6 22 Lexicon Address 0x00C00000 T 3055 9s sone AMPMRLY EXPBRST EXPARST ETRGEN1 ETRGENO DSPCRST DSPBRST DSPARST e AMPMRLY Amp Mains Relay CTRL 0 Relay is open 1 Relay is closed e EXPBRST Expansion Slot 1 Reset 0 Expansion Slot 1 is reset 1 Expansion Slot 1 is out of reset EXPARST Expansion Slot 0 Reset 0 Expansion Slot 0 is reset 1 Expansion Slot 0 is out of reset External Trigger 1 Enable 0 External Trigger 1 is inactive 1 External Trigger 1 is active e ETRGENO External Trigger 0 Enable 0 External Trigger 0 is inactive 1 External Trigger 0 is active e DSPCRST Format DSP Reset 0 CS494001 is in reset 1 CS494001 is out of reset e DSPBRST SHARC U33 Reset 0 033 is in reset 1 U33 is out of reset e DSPARST SHARC 016 Reset 0 U16 is in reset 1 U16 is out of reset 6 23 RV 8 Service Manual External Register U21 bit map RESREGDECH is decoded from chip select CPUCS3 write strobe CPUWRH and the condition CPUADDR 3 1 000 The result is an active high strobe when a write operation is performed at CPU address 0 00 00000 This strobe acts as a clock signal for register device 020 on sheet 2 The following table illustrates the register con
174. 02 105 PER ECO 040421 00 b 13 12 ADG451 RWH CW ___MAIN_DAC_RST 4 55 23 10 D7 11 D7 12 D7 14 B3 PD AOUTL gps LEFT IN LVL 3 e 6 CHANGED 024 PER ECO 040526 00 S404 __ MAIN FS64 5 _ 22 6 7 CBV MAG 4 A4 5 A4 6 A4 10 C7 11 D7 12 D7 15 B3 15 D5 1 BICK AOUTL 5 88 D Se aide 15 C3 15 D5 128 OUT4 6 DZER 28 C153 VEE GND MAIN FS 7 27 y M 24 4 A4 5 A4 6 A4 10 C7 11 C7 12 C7 15 C3 15 C5 LRCK 8138 R136 18PF 4 5 U MAIN DAC LATCH 3 8 26 NC A l y 14 83 Ife DZFL 15K Br 19 pig 25 1 8137 1 4 05 5 05 6 04 7 87 8 86 9 86 10 7 11 7 12 7 14 85 15 5 10 CLK 24 AK REAR DACOUT SEL 4 D5 8 C7 10 C7 11 C7 12 C7 14 85 15 A5 15 C8 OUT 11 AOUTR 21 CO REAR DIRECT SEL i 12 20 1 AOUTR 15 13 19 283 13 pie AGND y R222 C241 R168 8 14 pire vREFL 16 47 A e e 5 NEB582A TEN i 15 1 BGND 15 C282 de 33063 R169 GS 6 1 77 5 145K lt 199 L A U45 4 _ C242 1 1200 T 13 12 059 1 25 SE g20DPE Y ADG451 VCC VDD 15V 14 5 p 15 R_REAR DACOUT amp R223 C243 R167 C198 1618 e 13 A7 EE A LE 9 316 330 6 3 68 1 1200PF GND 1 1 R166 4 5 U24 22K Y R165 15V 1 21K Al EY 5 5VD 8 13 12 5 9 C5 RIGHT REAR 5 MC33078 VCC VDD gt 1 u s 10 24 034 C156 T 4 GND T U24 R141 15V
175. 022 16448 PL HS ASSY DBL POS RV8 2 00 022 16449 PL HS ASSY DBL NEG RV8 2 00 023 15825 PL AMP BD ASSY 4CH RV8 1 00 023 15890 PL SPKR EMI FILTER BD ASSY RV8 4 00 7 21 DESCRIPTION QTY EFFECT INACT REFERENCE INFO 490 16280 CONN BDGPOSTX2G 10 32 RED BLK 4 00 630 16283 WSHR SHLDR 312SHNK 6CL NYL 4 00 630 16284 SPCR 6CLX 090 25RD NYL 4 00 640 01710 SCRW 6 32X1 4 PNH PH ZN 8 00 P3 10 640 16298 SCRW 6 32X 25 UFH PH ZN 2 00 641 16288 SCRW TAP 6 32X 312 PNH TORX ZN 24 00 643 16290 NUT 6 32 KEP CONICAL WSHR ZN 4 00 644 03668 WSHR LOCK EXT STAR 6 SS 4 00 680 16423 HARNESS AMP 4CH RV8 1 00 701 16425 BRACKET AMP 4CH RV8 1 00 702 16428 PLATE AMP 4CH RV8 1 00 703 16430 INSUL AMP 4CH RV8 1 00 Single Positive Heatsink Assembly 100 01759 CHEM HEATSINK COMP SILICONE 0 003 oz 310 16276 TRANSISTOR MJ21194 NPN TO3 2 00 630 16421 INSUL SIL RUB 94X 66 1 00 641 16289 SCRW TAP 6 32X 25 PNH TORX ZN 4 00 704 16431 HEATSINK AMP SGL RV8 1 00 Single Negative Heatsink Assembly 100 01759 CHEM HEATSINK COMP SILICONE 0 003 oz 310 16277 TRANSISTOR MJ21193 PNP TO3 2 00 630 16421 INSUL SIL RUB 94X 66 1 00 641 16289 SCRW TAP 6 32X 25 PNH TORX ZN 4 00 704 16431 HEATSINK AMP SGL RV8 1 00 Double Positive Heatsink Assembly 100 01759 CHEM HEATSINK COMP SILICONE 0 003 oz 310 16276 TRANSISTOR MJ21194 NPN TO3 4 00 630 16421 INSUL SIL RUB 94X 66 2 00 641 16289 SCRW TAP 6 32X 25 PNH TORX ZN 8 00 704 16432 HEATSINK AMP DBL RV8 1 00 Double
176. 0421 00 sear vi eR 52003 5 22 03 16 RWH CW sL 2 3 CHANGED PER DCR 030623 00 UU UN 1 46 2 08 3 08 10 9 03 10 16 03 1 A6 2 D8 3 D8 o 5 Gar 8 AD8072 1 A6 2 D8 3 D8 CVID OUT IN um SYZON2 1 A6 1 A6 Z2VID_SELO EZNVID m Z2VID SEL2 9 83 220 10 07 5VV 3 3VD 16 74HC4051 VCC 1 C3 2 C8 3 C8 Y1 1 3 2 C8 3 C8 svi 3 R129 1 D3 2 C8 3 C8 p Y4 OUT IN SY3 YS 1 15 8114 1 C3 Y6 1 1 83 Y7 15K R128 RHS CVID_ZON2 ZONES IBS 10 A6 COMPOSITE VIDEO 594 OUT U8 R122 750 1 16 74HC4051 yo VCC 3C 5VV 1 C7 2 B8 3 B8 Y1 1 C7 2 B8 3 B8 Ye 45 1 D7 2 B8 3 B8 OUT IN SCZON2 8134 1 87 100K R38 750 U9 1 Z28VID_SELO W2Z2SVID 22SVID SEL2 CONTRACT z NO exICOn 3 OAK PARK BEDFORD MA 01730 TITLE APPROVALS DATE DRAWN SCHEM VIDEO BD RV8 RWH 8 9 02 ZONE 3 CHECKED Ecw 8 28 02 SEE CODE NUMBER iu Q C 060 15589 cw 8 2802 ee ISSUED 8 28 02 15589 3 4 sHEET 4 10 8 6 5 4 3 2 1 D gt 10 16 2003_16 28 REVISIONS REV DESCRIPTION ARAR TER AU RWH Cw o a 1 CHANGED PER DCR 030106 00 7 08 vests VIDEO DECODER VIDEO EN
177. 07 2004 edeon DECIMALS ANGLES XX 000 ASSEMBLY DWG 005 ase VIDEO RV 8 ______ _6 _ DWG NO REV assy USED a s B 080 15648 15648 0 DO NOT SCALE DRAWING ISSUED 6 24 03 SCALE 1 2 SHEET 1 OF 1 2 1 LEXICON INC 4 5 2 REVISIONS REV DESCRIPTION DWR CHKD Q C AUTH D C FAN 60MM 410 15839 HOUSING 2P 527 12537 OR EQUIVALENT CRIMP CONTACTS 2 525 12536 OR EQUIVALENT RED fF BLK 0 25 5 00 NOTES 1 PART NUMBER LISTING IS FOR REFERENCE ONLY amp DOES NOT SUPERSEDE BOM NOTE LEXICON P N S 527 12537 amp 525 12536 REFER TO AMP P N S EQUIVALENT PARTITS FROM OTHER VENDORS ARE ALLOWED PROVIDED BOTH THE HOUSING amp THE CONTACT ARE MADE BY THE SAME VENDOR UNLESS OTHERWISE SPECIFIED ACAD 2000 FILE NAME TOLERANCES AEN NC 15649 0 eicon A Stag ns ASSY DWG i APR 2 2004 FAN 60MM 12VDC SIZE FSCW NO DWG NO REV ELEASED COPY were S el 080 15649 APPLICATION 00 NOT SCALE DRAWING JSSUED MA 4 2 1 gt LEXICON INC 4 2 1 REVISIONS DESCRIPTION DWR CHKD Q C AUTH ___ SCRW M3X6MM PNH PH BZ 640 10498 2 PLCS TORQUE 4 6 IN LBS
178. 1 CS49400_C_SPI_TIMEOUT CS49400 HOST BOOT FAILURE 0x113 549400 FLASH WRITE TIMEOUT 0 114 CS49400_BAD_FLASH_DATA 0x115 549400 BAD RESP OPCODE 0 116 CS49400_FLASH_READ_TIMEOUT 0 117 CS49400_MASTER_BOOT_FAILURE 0x118 CS49400 BAD FLASH VERSION 0 119 CS49400 ERASED FLASH 0 11 5 4 RV 8 Service Manual Lexicon 549400 CHECKSUM FAIL 0 11 CS8420_INIT_ERROR 0x200 CS8420_ISC_WR_TIMEOUT 0x201 CS8420_ISC_RD_TIMEOUT 0x202 CS8420 WRONG VERSION 0x203 CS8420_WRONG_ID 0x204 These codes are used to interpret the diagnostic results from the Extended Diagnostic Repair Menu The Error code is 16 bits with the most significant byte always being 0x03 The least significant byte is broken into bits as shown below MSBit B7 B6 B5 B4 B3 B2 B1 LSBit B7 not used Should always 0 B6 GPIO LED failure 1 indicates that neither LED lit up from the test B5 Read Back Register Fail 1 indicates the Read back register failed B4 Test Fail 1 indicates the test failed 0 indicates success B3 SHARC Test Completed 1 indicates that the SHARC was able to finish executing the test B2 READ Time out 1 means that Hitachi could not read back from the SHARC 1 indicates time out B1 WRITE Time out 1 is means there was a time out BO SHARC processor id 0 is for Processor A and 1 for Processor B Bits B2 B1 and BO are
179. 1 06 02 12 20 02 A Se Ec Cc Ks Ls Kee dada ai i i 2 CHANGED PER DCR 030307 00 oM VCCO 33V VCGINT 2 5V R148 FPGA CCLK 1 A6 CAM MAG pus 52 Mg 155 84966 XFLASH CCLK 10 D8 5 14 03 5 20 03 DC 9134 5 8157 F M1 DONE 04 DONE 1 B8 10 D8 RWH ECM D ex Nig j R128 27 54 M2 XC2S200 DIN 0 193 Eoo 10 D3 3 CHANGED PER DCR 030626 00 9 29 03 10 9 03 LBS b 777 018 147 10208 gt DUE 130 106 HOST_DATA7H108 LVDATA 2 D4 FPGA PROG 115 LVDATA6 BB 1 CPUADDR9 96 HOST DATA6 115 LVDATAS 8135 HOST _ADR09 HOST DATA5 10 03 XFLASH_CF 1135 CPUADDR8 HOST DATAS 126 LVDATA4 CPUADDR7 oe Host alla Ee LVDATA3 CPUADDRG 73 1981 EC LVDATA2 CPUADDRS LVDATA1 CPUADDR4 70 HOST ADR04 HOST DATA B2 LVDATAO CPUADDR3 LVKYBDIRQ DS FORME GPUADDRT 57 HOST ADR02 1801 Hi LVDSPABIRGI 203 1 03 7 85 2 63 HOST ADR00 IRQ3 RAG 2031 IRO7_N 2 D3 CPUCS2 EP 1 B3 2 C7 CPUWRL N 62 FP IR IN1 1 83 7 85 WR N IR1_IN lt 12 86 7 65 me CPURD see 59 RP28 1 847 SDATA IN aloes 2 RP28 2777 47 FP SDATA OUT CPUCLKOUT 77 SER_OUT 57 RP28 3776 47 FP SDATA CLK 1 08 phost PIN SER
180. 1 23 12 24 Internal Analog Page 5 of 6 TEST PROC RV8 RV8 AUDIO ATE TEST SUMMARY 010 15834 A A Amplifier Tests Analog Generator Analog Analyzer Switcher Module See Bal Gnd Typical Upper Lower Clock Sample Audio Test Name Note Left Right Freq Hz EQ Curve Z out Unbal Float Level Measure Reading Limit Limit Imp Bandwidth Filter Aln B In A Out B Out Source Rate Source SIDE 5 TO ANLG REAR DIR AMP3 amp 7 OUT ANLG SIDE IN5 TO ANLG REAR DIR AMP387 OUT GAIN 100Vms ___ 1 00 5 ik LG SIDE IN5 TO ANLG REAR DIR AMP3 amp 7 OUT THD I ANLG SIDE 5 TO REAR DIR AMP387 OUT FREQ 1 00 Vrms 1 00 Vrms 10 20 20k 40k 100k 1 00 Vrms 0 0010 None n a Analog Level 0307 02725 5227 5130 Hoc 10 gt 500k None E E313 13 memi s A Analog LG SIDE IN5 REAR DIR AMP3 amp 7 OUT XTALK SIDE IN5 ANLG REAR DIR AMP387 OUT SNR 1 00 Vrms OFF Float THD N Float dB Leve Float dBr 20 20k None 20 20k None 997 None 65 00 0 05 50 00 0 0001 00 10 gt 22k 150 00 100k lt 10 gt 22 F N5 E DIR j OUT 1 10 20 ANLG ZONE2 IN5 ANLG ZONE2 DIR AMP387 OUT 1 00 Vrms 1 00 Vrms 20 20k ANLG ZONE2 5 ANLG ZONE2 DIR AMP387 OUT XTALK 1 00 Vrms 1 00 Vrms 20 20k 2 IN5 TO AN ZONE3 IN5 TO ANLG 20 DIR AMP387 OUT GAIN 1 00 Vr
181. 1 7 OUT SNR 1 20 Vrms OFF 7k 60 None 0 0018 30 10 0 030 5 3 0 100k lt 10 gt 500k 0001 100 n a None 1 2 3 5 6 5 6 0 Internal 0 Internal 0 Internal n a Analog n a n a LG MAIN D LG MAIN D LG MAIN D IN345 TO AN IN345 TO AN IN345 TO AN N AMP1 OUT XTALK N AMP2 OUT XTALK AMP3 OUT XTALK 00 Vrms 1 00 Vrms 1 00 Vrms 1 00 Vrms 1 00 Vrms Tk 20k 1k 20k 5 Leve lt 58 00 7150 00 00 10 gt 22k Internal Interna Analog ia Anas LG MAIN D IN345 TO AN AMP4 OUT XTALK 1 00 Vrms 1 00 Vrms 1k 20k Level lt 58 00 150 00 100k lt 10 gt 22 LG MAIN D LG MAIN D MAIN D R IN345 TO AN R IN345 TO AN R IN345 TO AN LG MAI AMP5 OUT XTALK N AMP6 OUT XTALK N AMP7 OUT XTALK 1 00 Vrms 00 Vrms 1 00 Vrms 1 00 Vrms 1 00 Vrms 1 00 Vrms 1k 20k 1k 20k 1k 20k Unbal Leser E Level Level 58 00 Level lt 5800 58 00 150 00 100 10 gt 22k 00 10 gt 22k None None Interna Interna Interna n a Analog 2 2 2 2 2 ipapa 2 2 2 2 2 LG MAIN DIR IN345 TO ANLG MAIN AMP1 7 OUT PWR VS
182. 1 PER DCR 030320 00 CAM MAG YEL R21 RED R2 3 25 03 3 27 03 LEDO LEDO 3 CHANGED RESISTORS PER DCR 030821 00 anaes mo D D13 680 D3 120 CAM KH Z2DVD2 Z3DVD2 9 23 03 YEL RED LED1 R20 LED1 Rl 012 680 D2 120 Z2SAT Z3SAT YEL RED LED2 R23 LED2 ne 015 680 05 120 Z2NCR Z3VCR YEL RED LED3 n2 LED3 014 680 04 120 Z2TV Z3TV YEL RED LED4 R25 LED4 R6 D17 680 D7 120 Z2CD Z3CD YEL RED LEDS 24 LED5 RS 016 680 D6 120 Z2TUNER Z3TUNER C YEL RED LED6 Rar LED6 8 019 680 D9 120 Z2AUX Z3AUX YEL RED LED7 R26 LED7 Ae 018 680 D8 120 72 7 RED RED LED8 R28 LED8 R9 021 120 010 120 AMP2 AMP5 BU BU LED9 8 LED9 5 D37 680 D33 680 BLU BLU LED10 na LED10 R29 B D36 680 D22 680 AMP4 AMP7 BU BU LED11 6 LED11 0 D35 680 011 680 LED 12 0 2 3 BYPASS CAPACITORS 3 3VD 5VD LC1 1013 t C15 47 16 47 16 T 47 16 T T CONTRACT ex CO n aso Ta lexicon BEDFORD MA 01730 4 25 T 1 25 T 1 25 T 1 25 TITLE APPROVALS DATE SCHEM SW LED BD RV8 DRAWN 7 10 02 FRONT PANEL LED MATRIX CHECKED 7 8 02 SIZE CODE NUMBER REV 060 15569 3 ECM 7 10 02 FILE NAME ISSUED MagG 7 8 02 15569 3 4 SHEET 4 OF 4 0 2003_17 07 UJ 11 2
183. 105 6421 26 8 EET 6 T 0357 0379 gt 9319 E Sp lyne osa 0 MAIN ADC_192K EN 4 A4 6 A4 14 B3 mtoe aps lt 10 MAIN ADC 96K EN 4 A4 6 A4 1 45VA 47 16420 OSRO 4 A4 6 A4 14 B3 T 15 7 4 27 cNDR R349 C355 R323 2 8 MC33078 15 VA MAIN 125 IN2 15 85 15 06 E fossa cel Od R325 25 AINR 17 Hi MAIN FS n 100PF 2 00K 3 25 LRCK 4 A4 6 A4 10 C7 11 C7 12 C7 13 C7 15 3 15 C5 51 4 AINR feet 5078 E 16 MAIN FS64 4 A4 6 A4 10 C7 11 D7 12 D7 13 D7 15 83 15 D5 d Y 3 AGND 2 49K ads CSUB ADC 145 59 Ms 26 2200PF 13 5119 MAIN RST 5VA ee RST TM 4 A4 6 A4 14 B3 0331 R269 E Z U82 5 C3 11 85 SUB IN LVL 3 6 8285 47 16 5 62 1 Paw CONTRACT 7 NO ex CO n 3 OAK PARK BEDFORD MA 01730 TITLE APPROVALS DATE SCHEM ANALOG BD RV8 DRAWN nwH 8 27 02 u INPUTS amp C SUB A D CONVERTER CBV 8 28 02 SIZE CODE NUMBER REV 060 15579 3 CW 8 29 02 FILE NAME ISSUED MAG 8 29 02 15579 6 5 SHEET 5 OF 17 8 7 6 5 4 3 2 1 10 7 2003 11 05 8 7 5 4 3 2 1 REVISIONS REV DESCRIPTION DRAFTER Q C CHECKER AUTH RIGHT SIDE IN HALF 1 CHANGED PER DCR 021107 00 BD ow LEFT_SIDE iN
184. 10W 150 OHM 7 00 R31 36 146 202 11041 RESSM RO 5 1 10W 680 OHM 12 00 R57 68 202 11071 RESSM RO 5 1 4W 75 OHM 4 00 R1 4 202 11496 RESSM RO 0 OHM 1206 8 00 R121 127 188 202 12894 RESSM RO 5 1 10W 1 3M OHM 1 00 R165 202 12933 RESSM RO 5 1 4W 10 OHM 2 00 R76 142 202 14584 RESSM RO 5 1 10W 10K OHM 0603 17 00 R73 75 79 81 84 108 R114 116 132 140 R141 171 179 187 202 14585 RESSM RO 0 OHM 0603 20 00 R53 55 70 72 100 102 R105 107 128 130 R137 139 148 150 R158 160 166 202 14792 RESSM RO 5 1 10W 56 OHM 5 00 R161 164 167 202 15681 RESSM RO 5 1 10W 47 OHM 0603 1 00 R152 203 10424 RESSM RO 1 1 10W 4 99K OHM 4 00 R38 39 87 88 203 10896 RESSM RO 1 1 10W 1 00K OHM 4 00 R15 19 77 143 203 11075 RESSM RO 1 1 10W 95 3 OHM 1 00 R30 203 11726 RESSM RO 1 1 10W 301 OHM 1 00 R29 203 11741 RESSM RO 1 1 10W 18 2K OHM 2 00 R48 97 203 11980 RESSM THIN 1 1 10W 10 0K OHM 2 00 R173 175 203 12471 RESSM RO 1 1 10W 442 OHM 2 00 R78 144 203 12491 RESSM RO 1 1 10W 205 OHM 1 00 R118 203 12722 RESSM THIN 1 1 10W 49 9K OHM 2 00 R44 93 203 12797 RESSM RO 1 1 10W 100 OHM 2 00 R172 174 203 12898 RESSM RO 1 1 10W 47 5K OHM 1 00 R99 203 12934 RESSM RO 1 1 10W 82 5 OHM 1 00 R50 203 13131 RESSM RO 1 1 10W 8 45K OHM 2 00 R16 20 205 14586 RESSM NET 5 ISOL 10KX4 11 00 RP1 8 11 13 205 15083 RESSM NET 5 ISOL 47X4 24 00 RP14 37 205 15737 RESSM NET 5 ISOL 3 3KX4 2 00 RP9 10 240 09786 CAP ELEC 100uF 25V RAD LOW ESR 3 00 C169 173 176 240 10758 CAPSM
185. 11 TRANSISTOR PNP 300V 1W TO92 12 00 Q5 6 19 24 25 38 43 Q44 57 62 63 76 310 16274 TRANSISTOR MJE15032 NPN TO220 4 00 Q7 26 45 64 310 16275 TRANSISTOR MJE15033 PNP TO220 4 00 Q11 14 330 15667 ICSM DIGITAL 74HCT594 SOIC 1 00 030 330 16215 ICSM DIGITAL 74HCT597 SOIC 1 00 U50 340 10552 ICSM LIN MC33078 DU OPAMP SOIC 4 00 U1 5 9 13 340 11045 ICSM LIN LM393 DUAL COMP SOIC 4 00 U3 7 11 15 340 11948 ICSM LIN LM339 QUAD COMP SOIC 4 00 U4 8 12 16 340 16219 ICSM LIN TLE2037 OPAMP SOIC 4 00 U2 6 10 14 410 16222 RELAY 1P2T 24V SEALED 4 00 K1 4 430 16223 LEDSM GRN 10MCD 1206 4 00 E1 4 440 15874 FUSE 5X20MM SLO BLO 12 5A 250V 2 00 F1 2 480 16225 THERMISTORSM NTC 20K OHM 0805 4 00 RT1 4 510 15694 CONN FFC 1 25MM 6 POS VERT 2 00 P1 2 510 15695 CONN FFC 1 25MM 14 POS VERT 1 00 J1 510 16278 CONN 163 HDR 2X3MC SHR POL LK 1 00 J6 510 16279 CONNSM TEST POINT 1206 8 00 TP1 8 525 16229 TERM SCRW PC SNAP VERT 6 32 8 00 P3 10 600 16416 FUSE CLIP 5X20MM PC 217 LS 4 00 HW4 7 600 16420 BUS BAR CU 4CH RV8 1 00 W1 680 16417 WIRE 16G 6RINGX2 PC 80 150MM 1 00 W7 680 16418 WIRE 16G 6RINGX2 PC 170 150MM 1 00 W8 710 16160 PC BD AMP MOD 4CH RV8 1 00 PICK REV 2 PC BOARD 740 11287 LABEL S N PCB PRINTED 1 00 PLACE NEXT TO TP8 Speaker EMI Filter Board Assembly 245 16182 CAPSM CER 470pF 100V X7R 1096 2 00 C1 2 710 16180 PC BD SPKR EMI FILTER RV8 1 00 PICK REV 0 PC BOARD 7 14 DESCRIPTION QTY EFFECT INACT REFERENCE INFO Video Boar
186. 13 Internal 96000 Analog ANLG ZONE2 IN2 TO DIG ZONE2 COAX OUT 96K FREQ 2 00 Vrms 12 00 Vrms 10 20 20 40 Level 0 20 0 00 ANLG ZONE2 IN2 TO DIG ZONE2 COAX OUT 96K 1 Hoovms 4oovms sk None 20 Float 9 level ____ 86 00 800 3000 510 2592 None 2 14 mtma 9600 Analog lt 10Hz gt 20kHz LP__ Narrow ANLG_ZONE2_IN3TO_DIG_ZONEZCOAXOUT96K rr O T ___ T T T T T J Jj ANLG_ZONE2_IN3_TO_DIG_ZONE2_COAX_OUT_96K_GAIN 1 4 00 Vrms 4 00 Vrms 997 None 20 Unbal Float dBFS Level 0 40 0 00 1 10 n a lt 10 Fs 2 None n a n a 3 15 Internal 96000 Analog LG ZONE2 IN3 TO DIG ZONE2 COAX OUT 96K FREQ 2 00 Vrms 2 00 Vrms 10 20 20 40k None 20 Unba dBr Level 0 20 0 00 0 10 lt 10 Fs 2 None 3 15 Internal 96000 ANLG ZONE2 IN3 TO DIG ZONE2 COAX OUT 96K XTALK oat 48 Leve 86 00 ANLG ZONEZ IN4 TO DIG ZONE2 COAX OUT 96K Erw rdum l Ex j j ANLG ZONE2 IN4 TO DIG ZONE2 COAX OUT 96K FREQ oat 4 _____ 0 2050 00 ___ 040 0507025 lt 10 62 wa 4 16 96000 Analog ANLG ZONE2 IN4 TO DIG ZONE2 COAX OUT 96K THD 3 80Vrms 3 80 Vrms THD N lt 98 00 86 00 _ 88 00 75 00 ____ 120 00 lt 10 8 2 mwa ma 4 16 96000 Anaog ANLG ZONE2 IN4 TO DIG ZONE2 COAX OUT 96K XTALK 1 400 400Vmms jk 1 Noe 20 Float dB eve 4600 800 4920 na lt 10 2
187. 145 149 151 R152 155 195 198 218 203 10579 RESSM RO 1 1 10W 2 49K OHM 2 00 R91 98 203 10837 RESSM RO 1 1 10W 475 OHM 6 00 R156 196 199 204 R209 242 203 10840 RESSM RO 1 1 10W 750 OHM 23 00 R38 93 96 105 R122 125 130 132 157 R158 161 165 177 180 R200 201 205 208 203 10895 RESSM RO 1 1 10W 681 OHM 2 00 R174 182 203 10896 RESSM RO 196 1 10W 1 00K OHM 4 00 R1 9 15 229 203 11080 RESSM RO 196 1 10W 1 15K OHM 12 00 R126 129 159 160 176 R178 179 183 211 212 203 11697 RESSM RO 1 1 10W 909 OHM 1 00 R102 203 11705 RESSM RO 196 1 10W 11 0K OHM 6 00 R2 6 8 13 14 19 203 11723 RESSM RO 196 1 10W 4 75K OHM 8 00 R5 10 16 171 184 R187 190 192 203 11726 RESSM RO 1 1 10W 301 OHM 2 00 R215 217 203 11734 RESSM RO 1 1 10W 4 32K OHM 1 00 R103 7 15 DESCRIPTION QTY EFFECT INACT REFERENCE INFO 203 11740 RESSM RO 1 1 10W 9 09K OHM 4 00 R3 7 12 18 203 11743 RESSM RO 1 1 10W 100K OHM 5 00 R34 44 53 62 71 203 11889 RESSM RO 1 1 10W 110 OHM 4 00 R233 236 203 12198 RESSM RO 1 1 10W 2 15K OHM 5 00 R172 185 186 188 189 203 12298 RESSM RO 1 1 10W 30 1K OHM 1 00 R253 203 12491 RESSM RO 1 1 10W 205 OHM 4 00 R140 143 210 213 203 12497 RESSM RO 1 1 10W 8 25K OHM 4 00 R86 109 137 237 203 12841 RESSM RO 1 1 10W 39 2K OHM 5 00 R33 43 52 61 70 203 12897 RESSM RO 1 1 10W 976 OHM 2 00 R175 181 203 16145 RESSM RO 1 1 10W 1 07K OHM 2 00 R90 99 205 15737 RESSM NET 5 ISOL 3 3KX4 1 00 1 240 09786 CAP ELEC 100uF 25V RAD LOW E
188. 166 245 14764 CAPSM CER 82pF 50V COG 5 1 00 C114 270 00779 FERRITE BEAD 4 00 FB4 7 270 11289 INDUCTORSM 10UH 10 1 00 L7 270 11545 FERRITESM CHIP 600 OHM 0805 7 00 FB1 3 8 11 270 15693 INDUCTORSM 2 7uH 10 6 00 L1 6 300 10509 DIODESM 1N914 SOT23 2 00 D1 11 300 10563 DIODESM DUAL SERIES GP SOT23 1 00 D10 300 11599 DIODESM GP 1N4002 MELF 8 00 D2 9 310 10510 TRANSISTORSM 2N3904 SOT23 16 00 Q2 3 5 6 8 19 310 10565 TRANSISTORSM 2N3906 SOT23 7 00 Q1 4 7 20 24 26 310 10566 TRANSISTORSM 2N4401 SOT23 3 00 Q21 23 330 10417 ICSM DIGITAL 74HC00 SOIC 1 00 U2 7 16 DESCRIPTION QTY EFFECT INACT REFERENCE INFO 330 10505 ICSM DIGITAL 74HC02 SOIC 1 00 U42 330 12321 ICSM DIGITAL 74VHCT08 TSSOP 1 00 U35 340 01525 IC LINEAR 7905 5V REG 1 00 U32 340 09244 ICSM LINEAR 78LS05 5V REG SOIC 1 00 U29 340 10502 ICSM LIN LF353 DUAL OPAMP SOIC 2 00 U31 41 340 11495 ICSM LIN LT1229 VID OPAMP SOIC 3 00 U18 28 30 340 13445 ICSM LIN TLC2933 PLL TSOP 1 00 U1 340 14535 IC LIN 1585A 3 3V REG TO220 1 00 U24 340 15586 ICSM LIN MAX4310 VIDAMP W MUX 5 00 04 15 17 38 340 15683 ICSM LIN AD8072 VIDAMPX2 SOIC 5 00 U3 5 6 19 27 345 10503 ICSM INTER NJM2229 SYNSEP SOIC 1 00 U39 346 10507 15 55 SWITCH 74HC4051 SOIC 11 00 U7 13 20 23 346 10508 ICSM SS SWITCH 74HC4053 SOIC 1 00 U40 350 15672 ICSM FLASH 128KX8 5V 90NS PLCC 1 00 U25 350 16147 ICSM CPLD RV8 VIDEO V1 00 1 00 U14 355 15678 ICSM CODEC SAA7109E VIDEO BGA 1 00 U34 365 13288 ICSM uPROC M
189. 17537 Rev 0
190. 182 185 R266 269 203 16175 RESSM RO 1 1 4W 365K OHM 6 00 R239 240 242 245 R253 257 203 16235 RESSM THIN 1 1 10W 100 OHM 9 00 R118 119 121 147 159 R212 213 243 327 203 16236 RESSM THIN 1 1 10W 100K OHM 21 00 R136 152 153 157 160 R220 236 237 241 244 R304 320 321 325 328 R368 369 379 380 R390 391 203 16237 RESSM THIN 1 1 10W 12 1K OHM 3 00 R373 384 395 203 16239 RESSM THIN 1 1 10W 1 82K OHM 9 00 R107 167 191 251 275 R335 367 378 389 203 16241 RESSM THIN 1 1 10W 23 2K OHM 12 00 R365 366 371 376 377 R382 387 388 393 R405 407 203 16243 RESSM THIN 1 1 10W 280K OHM 3 00 R130 214 298 203 16244 RESSM THIN 1 1 10W 33 2K OHM 9 00 R132 135 146 216 219 R230 300 303 314 203 16245 RESSM THIN 1 1 10W 47 5 OHM 3 00 R96 180 264 203 16249 RESSM THIN 1 1 10W 750 0 OHM 9 00 R97 108 139 181 192 R223 265 276 307 203 16250 RESSM THIN 1 1 10W 75 0 OHM 3 00 R106 190 274 203 16251 RESSM THIN 1 1 10W 95 3 OHM 12 00 R104 105 114 115 188 R189 198 199 272 273 R282 283 203 16252 RESSM THIN 1 1 10W 5 11K OHM 12 00 R133 134 148 149 217 R218 232 233 301 302 R316 317 203 16253 RESSM THIN 1 1 4W 4 99K OHM 9 00 R95 164 166 179 248 R250 263 332 334 203 16254 RES MF 1 1W 49 9K OHM VERT 6 00 R94 102 178 186 R262 270 203 16256 RESSM RO 1 1 4W 107 OHM 3 00 R142 226 310 203 16415 RESSM THIN 1 1 10W 825 0 OHM 12 00 R99 100 103 113 183 R184 187 197 267 R268 271 281 240 16257 CAP ELEC 2 2uF 160V RAD 20 6 00 C58 61 97 100 136 C139 240 16260 CAPSM
191. 2 5 8 7 6 5 4 3 2 1 15VA 4 R11 10 0K 1 11 1 15 47 15VA C14 1 25 MC33078 1 25 2 MC33078 C12 15VA 812 47 FB1 C5 R7 10 16 10 0 jm 196 150PF C2 150PF C7 R8 po 10 16 10 0K FB2 1 15VA C8 R9 10 16 10 0K 196 C10 R10 1046 100K MICROPHONE BIAS VOLTAGE SUPPLY 15VA D8 1N4002 CASE VOUT 9V VOUT LM317M D7 1N4002 1 js R15 C17 1K 22 16 1 25 1 R19 our 100 REVISIONS DESCRIPTION CHANGED PER DCR 021030 00 CHANGED PER DCR 030317 00 C 11 26 02 11 26 02 Cw 5 22 03 MAG 5 22 03 AUTH M C16 814 47PF 10 0K 1 13 M R20 100 R24 100 R23 wico 100 3 OAK PARK BEDFORD MA 01730 TITLE SCHEM MIC PREAMP BD RV8 MIC INPUTS FILE NAME 15529 2 2 OF 5 23 2003 9 16 HEADPHONE OUTPUT REVISIONS RWH 5 22 03 ECM 5 22 03 CHANGED PER DCR 030515 00 MAG 5 23 03 CW RWH CHANGED PER DCR 021029 00 11 4 02 11 12 02 11 14 02 5 23 03 DESCRIPTION DRAFTER CHECKER AUTH G NOTES 1 UNLESS
192. 2 5V by a section of RP7 6 26 Lexicon Audio Input Port Signals DEC IN FSI DEC 5 DEC _ SDI This port takes as input 125 audio data DEC 80 synchronous with DEC SCKI A frame start pulse is also utilized DEC IN FSI These signals are sourced from the AVRX FPGA This data is multiplexed into the Format Decoder from one of two sources 125 data may come from the Main zone S PDIF input block or from one of six ADCs on the Analog I O Board Chip Clock Signals CLK12500C XTALO PLLVDD FILT1 FILT2 CLKSEL PLLVSS There are two possible methodologies of providing a global clock signal to the Format Decoder The default topology consists of U30 a 12 288MHz 3 3V oscillator R107 places the output of U30 into the path of the CLKIN pin R108 ties the oscillator enable high causing it to generate the clock The second clock source is from the system clock signal CLK12500C R106 would pass this clock signal along to the Format Decoder in this option Naturally the other two options would have to be disabled and taken out of the path This topology has been determined to be not practical due to the differences in internal topologies between the Format Decoder and the SHARCs As a result this option is not implemented FB13 provides a high frequency filtered version of the 2 5VA supply which in turn is a high frequency filtered version of the digital 2 5V supply This double filtered supply voltage drives the internal Phase L
193. 2 OPT OUT 96K FREQ 10 00 mVrms 10 00 mVrms None 40 Level 0 00 10 Fs 2 None F 10 00 mvrms 10 00 mVrms THD N Ampl gt 0 25 lt 10Hz gt 20kHzLP_ None ma 9 2 intema 96000 Analog ANLG CENTER LFE N4 TO DIG ZONE2 j T ji qi rhe J LG_CENTER_LFE_IN4_TO_DIG_ZONE2_OPT_OUT_96K_GAIN 1 4 00 Vrms 4 00 Vrms 997 None 20 Unbal Float dBFS Level 0 38 0 00 1 10 n a lt 10 Fs 2 None n a n a 4 16 Internal 96000 Analog LG CENTER LFE 4 TO DIG ZONE2 OUT 96K FREQ 2 00 Vrms 2 00 Vrms 10 40k None 20 Float dBr Leve 0 20 0 00 0 10 lt 10 Fs 2 None n a n a 16 Internal Analog 4 00 Vrms ___ 4 00 Vrms Float level 11500 8000 13000 40 422 None 4 16 mtema 96000 Anal lt 10Hz gt 20kHzLP ANLG CENTER LFE IN TO DIG ZONE OPT out MK j ___ J PENSA Ps ss i 3 80Vrms 3 80 Vrms 4 00 mVrms 4 00 mVrms None 20 SIDE IN5 TO DIG ZONE2 OUT 96K DE IN5 TO DIG ZONE2 OPT OUT 96K GAIN 997 DE IN5 TO DIG ZONE2 OPT OUT 96K FREQ 1 i 2 00 Vrms 10 40k 0 20 0 00 0 10 Internal DE IN5 TO DIG ZONE2 OPT OUT 96K THD 1 I 3 80 Vrms 20 1k 5k 40k 98 00 86 00 88 00 75 00 Internal DE IN5 TO DIG ZONE2 OPT OUT 96K XTALK 1 i 4 00 Vrms lt 115 00 Internal DE IN5 TO DIG ZONE2 OPT OUT 96K DYNRNG 1 4 00 mVrms 108 00 lt 10Hz gt 20kHz LP Internal f s ip j j h j
194. 2 and 43 respectively This is the same bus that provides control of the tuner module A gated equivalent of this bus is provided via SCLG and SDAG pins 3 and 4 respectively and are provided a path to the tuner module by R4 and R7 This was to accommodate using a single register set to control all functionality on the board but as it was determined to not be necessary this option remains unused R5 and R6 pass the 1 bus along to the tuner block The bus provides CPU control of the radio signal AGC and indication of stereo signal detection as well as capabilities to provide overall signal level and equalization control at this level of implementation Left and Right audio signals are presented to the rest of the RV 8 system via LFOUT and RFOUT pins 27 and 28 respectively C12 and C13 provide an AC couple path to the output of the board while R8 and R9 ensure equal path impedance for these signals R16 further balances the common return path for the output signals C14 and C15 provide a high frequency roll off for noise in conjunction with R8 and R9 C20 provides storage of a reference voltage used by the internal D A converters in the control path of U2 6 49 RV 8 Service Manual C18 and C19 provide de coupling for the 8 5V supply voltage that powers U2 Output Connector J2 J2 is the only system wide interface to the tuner module A bulk supply of 12VDC is provided to the PCB via pin 3 of J2 This bulk voltage is noise filte
195. 2 n a n a 3 15 Internal 96000 Analog NLG FI N3 TO DIG ZONE2 OPT OUT 96K FREQ 1 2 00 Vrms 2 00 Vrms 10 40k 20 oat dBr Leve 0 20 0 00 10 Fs 2 96000 Analog 3 80 Vrms t NLG FI F G 3 80 Vrms 20 1k 5k 40k 20 ANLG_I N3 TO DIG ZONE2 OPT OUT 96K XTALK 96000 Analog G 96000 Analog lt 10 Fs 2 None wa ma 1 13 Interna 96000 212 FIF ol a gt 2 212 5 5 0 d 1 4 00 Vrms 4 00 Vrms 15k 20 Unbal dB Level lt 115 00 80 00 130 00 n a lt 10 Fs 2 None n a n a Internal N3_TO_DIG_ZONE2_OPT_OUT_96K_DYNRNG 1 4 00 mVrms 4 00 5 997 20 Unbal dBFS THD N 108 00 104 00 130 00 n a lt 10Hz gt 20kHz LP Narrow n a Interna z o 3 o Page 1 of 6 AUG 25 2004 TEST 8 RV8 AUDIO TEST SUMMARY 010 15834 A D Tests Analog Generator Digital Analyzer Switcher Module See Bal Gnd Typical Upper Lower Clock Sample Audio Test Name Note Left Right Freq Hz EQ Curve Z out Unbal Float Level Measure
196. 2 through 4 as well as the optical inputs labeled 1 to 4 Change the INPUT TEST selected in step 4 of setup procedure to the next appropriate input Move the output of the DVD player to the appropriate RV 8 input When testing the optical inputs be sure to use the appropriate digital cable Digital Inputs To Zone 2 Outputs Test This test will verify the audio path between the RV 8 S PDIF coaxial and optical digital inputs and the Zone 2 RCA Fixed and Variable outputs Note This test requires the use of a CD player as a source The tests to follow will be run using a PCM signal at a 44 1kHz sample rate Test 1 S PDIF coaxial digital output of the CD player to the S PDIF coaxial digital input 1 on the RV 8 rear panel 2 Connect the Zone 2 RCA left and right Fixed outputs of the RV 8 to the external amplifier left and right inputs Using the Menu arrows scroll through the Diagnostics Menu and select the AUDIO I O TESTS In the AUDIO I O TEST menu highlight S PDIF INPUT CX 1 TEST Press the remote control Menu arrow to engage the test The RV 8 is now set to route digital audio from the S PDIF coaxial digital input labeled 1 to all the RCA analog outputs gt Power on the external amplifier Press play on the CD player Slowly increase the volume on the external amplifier to a comfortable listening level Verify that clean undistorted audio can be heard Stop the CD player and power down the external
197. 20425 00 9 29 03 10 7 03 ecu Xe CBV MAG 1 E c 1 p 330 6 3 Ri71 1200PF 7 5 125 10 6 03 10 7 03 4 CHANGED PER DCR 031125 00 22K 45V CBV MAG 95 RA i usoa 22204 15V 4 VD 121K 5 CHANGED R37 40 R94 95 PER apod eod 153 SIDE DAC MCKI acie a7 040408 00 Ks ADG451 10 07 11 07 13 07 14 83 MAIN DAC RST 4 PD AOUTL 23 6 D2 6 pe LEFT_SIDE IN LVL e VCC 6 CHANGED U25 PER ECO 040526 00 A M 5 A4 6 A4 10 C7 11 D7 13 D7 15 83 15 D5 MAIN FS64 5 AOUTL 22 t 815i D n 15 C3 15 D5 MAIN 128 OUTS 6 lt 28 741 C157 VEE GND 4 A4 5 A4 6 A4 10 C7 11 C7 13 C7 15 C3 15 05 MAIN_FS 7 capt 27 8144 asy 142 18PF S Des 14 83 s MAIN DAC LATCH 2 8 cs pzrL pd me 9 35 1 8143 1 CADO P S A 4 32K 4 D5 5 D5 6 D4 7 B7 8 B6 9 B6 10 C7 11 C7 13 C7 14 B5 15 C5 gt SCLK 10 24 1 ADA SDATA OUT 11 21 10 04 11 D3 14 D7 14 C3 MAIN DIRECTES SELJA 4 D5 8 C7 10 C7 11 C7 13 C7 14 B5 15 A5 15 C5 ADA AOUTR 10 C4 11 C5 14 D6 2 4 12 piro AourR 20 13 pig AGND 19 C291 x 8226 C247 R178 DIF2 VREFL 47 s 15V 5VD 15 290 1 38063 179 7 L 1 1 15 5 C205 L 13 32 060 1 C248 1 1200PF T ADG451 Md R_SIDE_DACOUT 5 BESIDE 12 7 R22
198. 261 37 NC 2 UNLESS OTHERWISE INDICATED RESISTORS ARE 5 MPX C5 CM NC 10 25 3 2 RFGND2 LEVEL NC 32 RDDALS8 NC 4 Nc 112 39 NC 5VD 12V 3 UNLESS OTHERWISE INDICATED CAPACITORS FM2 TEST des RDCL R8 R9 J1 A 18 AF ADDR 44 100 100 4 gt DIGITAL ANALOG CHASSIS POWER 11 HOLD 20 R1 6 1 1 GROUND GROUND GROUND GROUND Ho SPA 5 TEES 9 5 ia Nc Ls FREF 01 25 LEVEL CREF 5 LAST REFERENCE DESIGNATORS USED C21 FB1 J2 L1 R16 U4 SFO R15 3814 SHDI s 2 8 RIS FB1 6 COMPONENTS MARKED WITH ON 1 7 GND4 SHD2 2 NE 196 196 NC 1 Ha GND7 SHD3Fs FREF HANC NC 2 GND14 SHD4 3 NC4 15 n 45018 NC5 H3 NC TUNER L 4 25 SDA NC7 We TUNER R 6 SCL NC8 x R7 04 41 NC9 55 1 2200 2 DGND 14 15 RDSGND nci ee 150PF 150PF R4 0 17 AGND Nc12L40 J 0 TUN_RDS_CLK R5 4 R6 U2 TUN RDS DAT diu MH1 C7 LC6 p T 47PF 57 r5 G G 0 E D 1 1 1 1 2003 Lexicon Inc CONTRACT GXICO n 3 OAK PARK BEDFORD MA 01730 APPROVALS pate DRAWN 12 3 00 SCHEM TUNER BD RV8 CHECKED 12 4 02 SEE CODE NUMBER REV ac 060 15549 1 cw 12 9 02 TENAME ISSUED
199. 2K is DG411 1 1 A5V VDD 11 10 15V 93 D zi 14 03 REC_PHONO_SEL WEE NB 15 83 MIC_OUT2 Cyaan _MC33078 14 03 REC_TUNER_SEL U42 d 4 02K d MIC2 4 C8 6 C8 7 C8 ix O R377 2 15V 5VD y 2402K 71 U88 15V R MIC INPUT 2 1 4 13 12 MIC2 RET 1874 15 8375 v VDD 15 83 MIG2_I V 2 LEFT ZONE 4 02K 4 02K 3 D ZONE IN 1 83 9 04 196 196 gt IN VEE GND 15V 5VD 15V 4 5 U40 h 3 12 TUNER L 15V VDD 15 2 TUNER LEFT TUNER IN 65 7 8 ZONE SOURCE SELECT NER INPUT VEE GND LTU 15V 5VD 4 5 U40 8 A8 15 A2 NERO Y 4 02K 4 02K 13 12 15v 1 1 VDD 415V 14 p 15 RIGHT ZONE IN 2 B3 9 c4 N 4 16 iN NER_R R384 VEE GND 15V 5VD d 15 42 TUNER_ RIGHT_TUNER_IN 4 5 U40 4 8 poen 577 lexicon due BEDFORD MA 01730 R TUNER INPUT 1 d 11 YCC VPD ag TTE 5 D TUNER_RET 2 ZONE_PHONO_SEL n UMS PATE SCHEM ANALOG BD RV8 8 A8 15 A2 1 14 C3 pom GND RWH 8 27 02 MORE ANALOG INPUT MUXES 1 14 03 ZONE TUNER S 4 5 U40 CHECKED 8 2602 NUMBER REY Y CW 8 29 02 FILE NAME HS ISSUED MAG 8 29 02 15579 6 3 SHEET 3 OF 17 1 8 7 6 5 4 3 2 10 7 2003 11 05
200. 2K CHECKED 14 C3 CBV 8 28 02 SIZE CODE NUMBER REV 15V J24 CONNECTOR FROM Gc B 060 15579 5 TUNER MODULE CW 8 29 02 gie NAME ISSUED MAG 8 29 02 15579 6 15 SHEET 15 OF 17 8 7 5 4 3 2 1 5 4 2004 8 43 8 7 5 4 3 2 1 REVISIONS REV DESCRIPTION DRAFTER Q C CHECKER AUTH RWH CW 12V FOR TUNER MODULE 5VD 5VA CHANGEDPER DCR 02110300 11 4 02 11 20 02 415V CBV MAG 45VD 412V Wi 11 20 02 11 21 02 036 A 5 2 CHANGED PER DCR 030407 00 EUR 5VD SOURCE 9 CBV MAG FB25 5VD 1N4002 12V 5 23 03 5 23 03 45V en i CASE VOUT 8 CHANGED PER DCR 030729 00 ous toos 2 5TURN vouT 2 4 CBV MAG 1 C448 100 25 L 450 LM317M 10 6 03 10 7 03 T 150PF C449 T 150PF 1 0457 92 5 FROM POWER SUPPLY sisi J19 15VSOURCE 6 1 5 2 15V 3 GND 4 15 6451 5TURN 00 25 C453 T 150 C452 150PF SVD 5VA REGULATOR 4 3 3VD D35 n 031 1N4002 4 134002 GND 33VD 1 U73 09 P 15V SOURCE GND C394 T LM3940 2 3 t t vour VIN VOUT C454 100 25 C456 CASESVIN T EY 1N4002 T 150PF FB27 C455 T 150 TERM GND 7905 2 485 C4
201. 3 4 6 202 09871 RESSM RO 5 1 10W 1K OHM 1 00 R15 202 10559 RESSM RO 5 1 10W 100 OHM 12 00 R19 20 23 24 33 R41 43 45 48 52 54 202 10586 RESSM RO 5 1 4W 100 OHM 2 00 R26 29 202 10598 RESSM RO 5 6 1 10W 330 OHM 2 00 R2 5 203 10578 RESSM RO 196 1 10W 2 21K OHM 4 00 R35 39 44 50 203 11077 RESSM RO 196 1 10W 237 OHM 1 00 R16 203 11723 RESSM RO 1 1 10W 4 75K OHM 2 00 R32 38 203 11980 RESSM THIN 1926 1 10W 10 0K OHM 8 00 R7 14 203 12481 RESSM RO 1 1 10W 1 50K OHM 1 00 R25 2038 12494 RESSM RO 1 1 10W 2 37K OHM 2 00 R49 55 203 12719 RESSM THIN 1 1 10W 2 00K OHM 2 00 R18 22 2038 12723 RESSM THIN 1 1 10W 102 OHM 2 00 R17 21 203 12898 RESSM RO 1 1 10W 47 5K OHM 4 00 R27 28 31 37 203 13135 RESSM THIN 1 1 10W 432 OHM 2 00 R30 36 2038 14566 RESSM THIN 1 1 10W 20 0K OHM 2 00 R46 51 240 09367 CAPSM ELEC 10uF 25V NONPOL 20 4 00 C38 40 45 46 240 11111 CAPSM ELEC 47uF 6V NONPOL 20 2 00 C31 32 240 11827 CAPSM ELEC 10uF 16V 20 7 00 C5 10 24 240 13216 CAPSM ELEC 22uF 16V 20 1 00 C18 241 09366 CAPSM TANT 10uF 25V 20 2 00 C26 28 244 11589 CAP MYL 068uF 63V RAD 5 BOX 4 00 C33 36 37 39 245 10562 CAPSM CER 150pF 50V COG 10 6 00 C1 4 25 27 245 10974 CAPSM CER 4 7pF 50V COG 5 2 00 C41 44 245 10976 CAPSM CER 47pF 50V COG 5 6 00 C11 12 15 16 19 22 245 12485 CAPSM CER 1uF 25V Z5U 20 10 00 C13 14 17 20 21 C23 34 35 42 43 245 12522 CAPSM CER 120pF 50V COG 10 2 00 C29 30 270 11545 FERRITESM CHIP 600 OHM 0805 8 00 FB1 8 300 10
202. 3 IN 44K TO ANLG ZONE2 VAR OUT GAIN ms gt T L n ma DIG ZONE2 OPT3 IN 44K ZONE2 VAR OUT THD 1 1200 12004 5 97 None _ lt 10 22k 7 19 ma Exema 400 DIG ZONE2 4 IN 44K ANLG ZONE2 VAR OUT DIG ZONE2 4 IN 44K TO ANLG ZONE2 VAR OUT THD i 2 00 dBFS 12 00 dBFS 997 lt 002 1005 0002 100k lt 10 22k None External 44100 Digital DIG_ZONE2_OPT1_IN_96K_TO_ANLG_ZONE3_VAR_OUT 0 1010 0 30 25 875 ion Fo k qwe 9 2 na ma Externa 96000 ZONE2 OPT1 IN 96K TO ANLG ZONE3 VAR OUT XTALK 1 1 00 dBFS 1 00 dBFS 15k None dB gt 98 00 775 00 7150 00 100k lt 10 22k None External 96000 E ZONE2 OPT1 IN 96K TO ANLG 2 VAR OUT DYNRNG 60 00 dBFS 60 00 dBFS a a on gt 112 00 lt 10 22k None T Y OT T k AG CRM ma wma Level 357 353 39 7 100 lt 10 gt 600 None 16 138 ma Exema 96000 d ma 002 105 002 0 00 2k home 16 1348 Exema 900 DIG MAIN OPT1 IN 96K TO ANLG MAIN OUT XTALK dB 8500 oo ______ 150 00 100 40 2 None 16 138 Exema 96000 Digital DIS MAIN OPT1 IN 96K ANLG MAIN OU
203. 34 C149 330 6 3 47 16 330 6 3 D 47 16 5VD 5V C9 C16 C26 C55 C105 C110 C113 C115 C116 C119 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 C120 C121 C143 C155 C156 C157 C162 C163 C166 1 25 4 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 La 2 C17 M 470 16 4 27 2 5V 2 5VD A 1 8V A 1 8V B 4 C95 C101 C104 C153 1 8V B 1 25 1 25 1 25 1 25 B 415V 15V 4 4 5 7 C102 C108 C148 pod oe 1 01 25 T 01 25 T 01 25 85 11 1 25 1 25 z 4 ph 34 4 C97 C151 C152 C65 C77 C125 C138 ee 01 25 T 01 25 01 25 7 01 25 1001 5025 2001 50 001 50 C47 C89 1 1 14 t 1 25 1 25 C76 C132 96 144 med 7100 10 T 100 10 001 50 001 50 15V 15 LERRA 77 77 7 A Lexicon BEDFORD MA 01730 TITLE APPROVALS DATE SEER SCHEM MAIN BD RV8 RWH 4 26 02 BYPASS CAPACITORS CHECKED 4 30 02 CODE NUMBER REV QC 060 15559 4 CW 5 1 02 FILE NAME JV 4 30 02 15559 6 19 19 OF 19 8 7 6 5 4 2 1 8 7 6 5 4 3 2 1 REVISIONS REV DESCRIPTION DRAFTER CHECKER _AUTH CW RWH 1 CHANGED PER DCR 021028 0
204. 35 1 2K 8 _ 4 BIN 024 is Super 7 188 VCOVB 1 B BAR35 R94 100 20 9 A2 ZONE2 PLL PUMP DN Sq 4 4 TLO72 3 VCO MODULE 74ACT04 1 2K 040 55 PLL OUTB SPARES P_DNB m gt NCO oscB U28 BAR 2 2 LOCK s gt 9 ios C88 U23 023 R92 13 75 912 RNC 2057 OscB t gt ZONE2 Ag 74ACT04 D39 1 4 25 74HCU04 74HCU04 47 LK DNB D43 R91 028 11 10 R87 47K 1N914 C90 4 99K 1 C01 74 4 R96 F 1025 2 2M 15V 1 25 2 2M 7 R88 023 U28 D42 47 16 4 99K 13 02 9 8 024 74HCU04 74ACT04 BAR35 18 2 77 1 TLO72 U23 4 9 gt cB Y 74HCU04 15V U23 1 010 74HCU04 44 1K AND 48K 512FS U23 5 gt 88 2K AND 96K 256 FS 74HCU04 77 ex CO n NO BEDFORD MA 01730 TITLE APPROVAL OVALS SCHEM MAIN BD RV8 RWE VCOB CHECKED SIZE CODE NUMBER REV ac Bu B 060 15559 3 FILE NAME ISSUED JV 15559 6 16 sHEET 16 OF 19 8 7 3 2 1 4 27 2004 9 56
205. 4 00 Vrms 4 00 Vrms 20 Unba oat Vrms Leve gt 110 00 Internal 97 97 LG_ZONE3_IN1_TO_ANLG_ZONE3_DIR_VAR_OUT_RELAY_MUTE LG ZONE3 IN1 TO ANLG ZONES3 DIR VAR OUT RELAY MUTE 1 4 00 Vrms 4 00 Vrms 9 None at Vrms d OO0k lt 10 22k None 5 Interna Analog None 20 Vms 0 260 k 16 00 mVrms 16 00 mVrms 20 50 50 20k RIAA PRE 20 Level lt 0 10 0 50 0 50 100k lt 10 gt 500 None 17 11 23 Internal n a Analog Level gt 80 00 70 00 150 00 lt 10 gt 22k None 23 Internal LG FRONT IN1 TO ANLG MAIN OUT LG FRONT IN1 TO MAIN OUT GAIN Float Vrms 3 40 3 70 3 10 100k 10 gt 500k 14 13 16 13 Internal Analog 10 500k 14 1346 1 3 Analog LG FRONT IN1 ANLG MAIN OUT THD 2 00Vrms 2 00 Vrms None 20 Unba THD N 004 10 gt 22k None 14 13 16 18 Internal LG FRONT IN1 TO ANLG MAIN OUT XTALK 1 4 00 Vrms 4 00 Vrms 15k None 20 Unba Float Leve gt 85 00 10 gt 22k 1 4 13 16 13 Internal LG_FRONT_IN1_TO_ANLG_MAIN_OUT_SNR 1 OFF 997 None 20 Unbal Float dBr Leve 106 00 102 00 140 00 00k lt 10 gt 22 1 4 13 16 13 Internal LG FRONT IN1 TO ANLG MAIN OUT VC MUTE 1 4 00 Vrms 4 00 Vrms 997 20 Unb Float Vrms Leve gt 34 00 30 00 45 00 100k lt 10 22k None 1 4 13 16 1 13 Internal ANLG FRONT IN TO MAIN OUT RELAY MUTE J T 1 rr rp pr am eras 4 v LG
206. 4 bit serial data stream sourced from the AVRX FPGA to the CENTER SUB D A Converter on the Analog Board MAIN 128 OUTS is the 24 bit serial data stream sourced from the AVRX FPGA to the LEFT RIGHT SIDE D A Converter on the Analog Board MAIN I2S OUTA is the 24 bit serial data stream sourced from the AVRX FPGA to the LEFT RIGHT REAR D A Converter on the Analog Board MAIN is the Left Right framing signal for the MAIN 126 IN 3 1 and the MAIN 125 OUT 4 1 data streams sourced from the AVRX FPGA to the MAIN C SUB and SIDE A D and D A Converters on the Analog Board MAIN FS64 is the serial clock for the MAIN 125 IN 3 1 and the MAIN 128 OUT 4 1 data streams This is sourced from the AVRX FPGA to the MAIN C SUB and SIDE A D and D A Converters on the Analog Board REC DAC 125 OUT is the 24 bit data stream sourced from the AVRX FPGA to the Record Zone D A converter on the Analog Board REC DAC FS is the Left Right framing signal for REC DAC 125 OUT It is sourced from the AVRX to the Record Zone D A converter REC DAC FS64 is the serial clock for REC DAC 125 OUT The Zone 2 left right VAR and FIX outputs are sourced by the Record Zone D A converter Power Amplifier SPI Control Signals CTRL DATA STAT DATA SER CLKA DATA LATCHA CTRL DATB STAT DATB SER CLKB DATA LATCHB STAT DATA is the receive path from the four channel power amplifier Data from this signal is stored in a 2x8 bit RAM internal to the AVRX from which the
207. 4888 740 16015 740 16017 022 16444 022 16445 022 16442 750 15827 3 amp 4 CH BD PS amp ASSY TO MAIN BD 3 CH amp 4 CH AMP TO ANLG BD DESCRIPTION CABLE HSGX2 10C 4C X 3 16 5 CABLE HSG QDC 18 14AWG 22 5 CABLE HSG HSG 6C 12 COVER 4U CHASSIS LEFT CHASSIS RIGHT PLATE CENTER CHASSIS PANEL REAR PLATE BOTTOM PANEL MTG PS PANEL OPTION BLANK PAD FOOT TAPE FOAM DBL STK 1 75X 4X 025 LABEL GROUND SYMBOL 0 5 DIA LABEL S N CHASSIS LABEL LIC PAT WARN LABEL 100 120V LABEL 220 240V MECH ASSY AMP 3 CHAN MECH ASSY AMP 4 CHAN MECH ASSY PS PWR SUP 5V 15V 65W APPLICATION NI SE SSIES ee NONE 5 UNLESS OTHERWISE SPECIFIED DIMENSIONS ARE IN INCHES TOLERANCES ARE DESCRIPTION CEA LI LOCTITE TO HANDLES AN 7 12 04 DuC 7 13 04 PER DCR CLO 7 13 04 MAG 7 13 04 DELETE LOCTITE ITEM 10 AN 8 13 04 8 28 04 ADD WSHRS mui amp 39 PER ECO 040 CLC 8 16 04 MAG 8 26 04 SCRW 28 WAS 640 16121 AN 9 21 04 cw 9 30 04 PER ECO 040831 01 9 23 04 MAG 10 1 04 4 SOR S 32 WERE 30 AN 5 26 05 cw 6 22 05 PER ECO 4050503 00 CLC 5 27 05 MAG 7 5 05 WHERE USED PWR SUP TO MAIN ANLG amp VIDEO BDS PWR SW TO PWR SUPPLIES PWR SUP TO AMPS REAR PANEL FOOT FERRITE TO CTR PLATE CHASSIS REAR PANEL BOTTOM PLATE REAR PANEL 1 PART
208. 5 m CLE 7 DEC27M 35 3i edi i 63 ZOVID ling i Need 64 Z2VID_SEL2 SPARE1 59 Z2CVID 46 SPARE OxA8 86 DEC_RES ee 49 6 C7 Ie FB2 ie FB1 5 53 MSVID SELO gt 2 A8 C59 C58 54 MSVID SELI e I T 55 MSVID SEL2 26 33 MSTHRU 1 25 gt T 1 25 2 D5 56 RECSVID SELO TLC2933 R77 BE eye RECSVID_SEL1 XRH 1 14 2 2K RECSVID SEL2 SEL 65 Z2SVID_SEL0 C57 Z28VID SELO ec ZVD SEH 4 A8 DEC_XRH 4 1 25 Z2SVID_SEL1 57 SEL 8 5 5 T Z28VID_SEL2 gt 4 A8 R79 47 15 2 Sein B v OUT 3 23 54 GCK2 ENC27M I2 ENG 27MHZ 5 B4 47 50 R78 ENC15K P_OUT 12 AK 876 ospscukL 9 VCO_IN 2 8 mH 5 ose GNDL GNDV 4 2577 1 50 4716 U14 Uil 1 T 1 2 74 OSD 3 OSD_SCLK5 Ds Ny 035 ENCODER CLOCK CONTRACT z SOM EMEC NO lexicon OSD CS 8 OSD CS5 BEDFORD MA 01730 TITLE U35 APPROVALS DATE DEAWN SCHEM VIDEO BD RV8 74VHCTO8 RWH 8 9 02 4 CPLD CONTROL REGISTERS PLL VIDEO 5 VIDEO DATAS y 7 88 CHECKED Ecu gogo SIZE CODE NUMBER REV U35 060 15589 3 us cw 8 28 02 FILE NAME ISSUED 8 28 02 15589 3 9 sHEET 9 or 10 8 7 6 5 4 3 2 1 D gt 10 16 2003_16 28
209. 5 0 and D 7 0 buses see below Character dot clock is fixed at about 15 MHz based on the external LC circuit formed by L7 C99 C100 A crystal clock is supplied by oscillator 037 PAL or U36 NTSC The active oscillator is determined by a high level on either NTSC_EN or PAL EN enabling the respective oscillator 6 53 RV 8 Service Manual In overlay mode composite or s video luminance from the input amplifier is applied to YIN and similarly s video chrominance if applicable is applied to CIN The video applied to YIN is shifted to have a back porch dc level of about 1 57Vdc by U31 and associated circuitry C123 C73 passively couple the ac content of the luminance signal with the op amp providing the dc response The chroma channel is biased to the same 1 57V level by R171 R172 The OSD video is related to program video by the separate H and V syncs GMHSYN VSYNC derived by the sync stripper sheet 8 The full screen mode is independent of video and sync inputs Raster generation is based on the appropriate crystal clock The OSD luminance output is dc shifted back to OV back porch level by U31 and associated circuitry C121 C122 passively couple the ac content with the op amp providing the dc response Chroma is simply ac coupled by C107 C108 The shifted OSD video is buffered and filtered by U30 to produce OSD SY OUT and OSD C OUT Switch U40 permits the S video luminance to be turned off when MSVID_YOFF is asserted high OSD_Y
210. 5 00 75 00 150 00 100k lt 10 gt 22 None 5 17 17 Interna 2 exis Ade j eve 50 7 Ho lt 10 gt 600 5 17 6 18 mea eve 0 00 02505 100 40 0 5 7 6 18 mena THD N lt 03 05 7 0005 ook lt 10 gt 2 5 17 6 148 mtma eve 940 750 4500 ok lt 10 gt 22 None 5 7 6 148 mh 10500 4400 40 2 None 5 17 6 18 7 Leve 3 80 lt 10 gt 600 Noe 5 17 7 149 lt 0 10 X 0 100k _ lt 10 gt 500k 17 19 Internal 4 00 Vrms 20 Leve gt 95 00 1 7 Internal N o D I 20 1k 6 40k 00 Vrms 4 00 Vrms 2 00 Vrms 2 00 Vrms 10 20K 20k 40k lt 010 ____ 0251075 100k lt 10 gt 500 None 17 Interna 2 00 Vrms 2 00 Vrms 10 20k 20k 40k 20 Unbal Unbal i lt 10 gt 500 Internal 2 00 Vrms 10 20k 20k 40k Unbal A lt 10 gt 500k Interna 3 80 Vrms 3 80 Vrms 20 1k 5 40k 20 THD N 4 00 Vrms 4 00 Vrms 20 Unbal Float dB Leve gt 95 00 100k lt 10 gt 22 Internal LG ZONE3 IN8 TO ANLG ZONE3 DIR VAR OUT SNR OFF OFF 997 20 Unbal Float Leve 110 00 100k 10 gt 22k Internal LG ZONE3 IN1 TO ANLG ZONE3 DIR VAR OUT VC MUTE Sea aS ae LG_ZONE3_IN1_TO_ANLG_ZONE3_DIR_VAR_OUT_VC_MUTE 1 1
211. 5 6 C4 7 A7 8 B7 9 C7 9 B7 15 C5 ADA VC 3 vo NC vo M C5 5 C5 6 C4 7 A7 9 C7 1 62 78 076 076 15 C5 _ 99 lO GSR O 6 3 5 xc 8 87 _ _ 11 10 13 12 94 64 82 ZONE ZCEN T 16 A3 TUN TUNED 95 10 96555 MAIN RST 7 74LCX14 74LCX14 15 A2 TUN 95 1 0 665 MANADE EN A A4 5 A4 6 A4 15 A2 TUN STEREO 96 2 0 67 96K 4 A4 5 84 6 A4 87 MAIN 192 EN 9 7 0 ADC RST STREN TDI 158 71 90 ADC 96K EN Wee TCK 48 ae REC 192K EN TMS 47 S TMS 1 2 R200 ADA SDATA IN JTAG PROGRAMMING PORT 00 74 02 200 86 15 C6 84 GND7 o 75 15 45 5VD R123 gt 75 Laia 5 1535 e Z GND6 Je 63 5 p 44 GNDS 88 Ed 44 GNp3 wu Ez NC 21 74 YEL 05 039 o 109 TDO WHT TDI GRN TMS o TMS D NO exICOn 3 OAK PARK BEDFORD MA 01730 TITLE APPROVALS DATE SCHEM ANALOG I O BD RV8 DRAWN RWH 8 27 02 CONTROL REGISTERS CHECKED 8 28 02 SEE CODE NUMBER REV QC 7 3 CW 8 29 02 FILE NAME ISSUED MAG 8 29 02 15579 6 14 14 17 8 7 6 5 4 2 1 10 7 2003_14 56
212. 5 TR 3 CHANGED PER DCR 030626 00 2 47 RP31 2 10 2 03 10 9 03 47 RP31 EXPB2 EXP3 47 RP31 EXPA3 47 RP31 EXP4 47 RP30 EXPA4 47 RP30 EXPB4 EXP5 47 RP30 EXPA5 47 RP30 EXPB5 EXP6 47 RP29 6 47 RP29 EXPB6 7 47 RP29 7 47 RP29 EXPB7 EXP8 47 RP37 47 RP37 C EXP9 47 RP37 EXPA9 47 RP37 EXPB9 EXP10 47 RP36 EXPA10 47 RP36 EXPB10 EXP11 47 RP36 11 47 RP36 EXPB11 EXP12 47 RP35 12 47 RP35 EXPB12 EXP13 47 RP35 EXPA13 47 RP35 EXPB13 EXP14 47 RP34_EXPA14 47 RP34 EXPB14 EXP15 47 RP34 EXPA15 47 RP34 15 16 47 RP33 16 B 47 RP33 16 9 A7 EXP17 47 RP33 17 47 RP33 EXPB17 NO lexicon 3 OAK PARK BEDFORD MA 01730 TITLE APPROVAL DATE DERW OVALS SCHEM MAIN BD RV8 RWH 4 26 02 EXPANSION PORT SERIES TERMINATIONS CHECKED 4 30 02 See CODE NUMBER REV 3 Qc cw 5102 bee 060 15559 ISSUED JV 4 30 02 15559 6 11 SHEET 11 OF 19 8 2 1 10 10 2003_11 04
213. 52 275 Ne 395r Br CRY 6 gt 417 BEDFORD 01730 TITLE 5 DATE CRY_CLKSEL SCHEM MAIN BD RV8 9 C2 DRAWN LI CE RWH 4 26 02 924 CRYSTAL DSP CHECKED SIZE CODE NUMBER REV GND 200NS CAM 4 30 02 060 15559 3 U19 CW 5 1 02 FILE NAME JV 4 30 02 15559 6 8 sHEET 8 or 19 8 7 6 3 2 1 10 10 2003 11 04 8 7 6 5 3 2 1 REVISIONS REV DESCRIPTION DRAFTER QC 3 3VD 2 5VD CHECKER AUTH 5VD RWH CW 3 3VD 1 CHANGED PER DCR 020913 00 a aes 43 3VD PESO PERS PA mm 1
214. 541 15576 550 15844 630 12533 635 15322 640 01711 640 01721 640 02377 640 10498 640 11284 640 13645 640 15346 640 15476 640 16140 640 17394 641 01703 641 11466 644 01747 643 10492 644 10494 644 01741 680 15697 680 15630 680 15631 680 15632 680 15633 680 15634 680 15636 680 15637 680 16122 680 15639 680 15640 680 15641 DESCRIPTION PL MECH ASSY FP PL MECH ASSY VIDEO PL MECH ASSY TUNER PREAMP PL FAN ASSY PL MAIN BD ASSY PL ANLG 1 0 BD ASSY FERRITE FLAT CABLE 1 8 X 1 1 SWITCH ROCKER 2P1T XFORMER PWR TOR CONN PLUG 200 4FC RA CONN AC 3C SNAP IEC CONN DSUB JSCKT 4 40 TIE CABLE NYL GROMMET STRIP SER NYL FOOT BLK HANDLE U BLK WSHR FL 12 ID 25 OD RUB SPCR M3X8MM RD HEX HD SCRW 6 32X1 4 FH PH ZN SCRW 8 32 3 8 PNH PH ZN SCRW 4 40 1 4 PNH PH SCRW M3X6MM PNH PH SCRW SCRW SCRW SCRW M3X8MM FH PH M4X10MM FH SCKT BZ MSX16MM PNH PH M4X8MM PNH PH SCRW 4 40X5 16 THUMB RH SS SCR M4X8MM PNH PH ZN IT SCRW TAP AB 4X1 4 PNH PH SCRW TAP 4X3 8 PNH PH TRI WSHR INT STAR 4 NUT M4X 7MM KEP WSHR FL M4 CL X 9 OD X 8MM THK WSHR INT STAR 8 CABLE PWR WIRE 14G G Y 3 5 CABLE FFC 4C 14 CABLE FFC 13C 15 CABLE FFC 16C 10 CABLE FFC 16C 14 CABLE FFC 40C 6 CABLE FFC 40C 12 CABLE FFC 14C 4 FOLD CABLE FFC 14C 4 CABLE FFC 6C 4 CABLE FFC 6C 6
215. 55 irum m So s o d 14 E NOI L _ D25 R57 fi gt cas L 5 a deum 016 7 N 3 cs 2 ue 553 m E SERIAL NUMBER LABE 1 LEXICON BOM NUMBER 023 15615 SUPER CAT 013 014 028 60 ess e 3 T CDE iS udun 54 J 924 _ 7140 11287 OR EQUIVALENT SEDES ANY INFORMATION ON THIS wes 034 R62 017218019 220 E Gom ux D31 R63 saa E O DRAWING gt TEU 534 8 sim m E 2 ALL COMPONENTS TO BE INSTALLED FROM mE t s SIDE PCB UNLESS OTHERWISE Wo D36 R68 glo 222 Te 4 D 5 S ECIFIED 5 B DA gm E CO 8 020 021 E 3 LEAD PROTRUSIONS 100 MAXIMUM FROM gt C69 _ J11 COR BOTTOM SIDE OF PCB e m U21 4 UNLESS OTHERWISE SPECIFIED MOUNT rey m 025 E ET ALL COMPONENTS FLUSH AND PERPEN VCOVB BI og DGND7 p 4 NES MR 023 026 DICULAR 90 1 TO PCB E k 20 e 5 R84 4 4 tens vel mi og SP s mI 5 PCB ASSEMBLY TO BE PACKAGED IN A e mo Es STATIC SHIELDING FARADAY CAGE BAG IREN DE QUEE EE EE El pu ux U34 THAT HAS AN ANTI STATIC NON CON p m U DUCTIVE INNER LAYER ALSO THE ye d 3 5 Zu s T
216. 563 DIODESM DUAL SERIES GP SOT23 8 00 D1 6 13 14 300 10564 DIODESM SCHOTTKY LOW VF SOT23 4 00 D9 12 300 11599 DIODESM GP 1N4002 MELF 2 00 D7 8 340 10552 ICSM LIN MC33078 DU OPAMP SOIC 2 00 U1 2 340 11559 ICSM LIN LM317M ADJ REG DPAK 1 00 U3 340 15699 ICSM LIN NE5532A DUALOPAMP SOI 2 00 U4 5 510 10595 PHONE JACK 3 5MM PCRA 3C STER 2 00 J1 2 510 10986 CONN RCA PCRA 1FCGX2V RED WH G 1 00 J3 510 15688 CONN FFC 1 25MM 16 POS VERT 1 00 4 640 02377 SCRW 4 40X1 4 PNH PH BLK 1 00 KEYSTONE BRKT 701 09640 BRACKET KEYSTONE 621 4 40X2 1 00 LUG1 710 15520 PC BD MIC PREAMP RV8 1 00 PICK REV 2 PC BOARD 740 11287 LABEL S N PCB PRINTED 1 00 Tuner Board Assembly 202 09794 RESSM RO 0 0805 4 00 R1 3 5 6 202 10585 RESSM RO 5 1 4W 51 OHM 1 00 R16 203 10576 RESSM RO 1 1 10W 1 87K OHM 1 00 R12 203 10583 RESSM RO 1 1 10W 10 0K OHM 3 00 R13 15 2038 11723 RESSM RO 1 1 10W 4 75K OHM 1 00 R11 203 11731 RESSM RO 1 1 10W 1 62K OHM 1 00 R10 203 12797 RESSM RO 1 1 10W 100 OHM 2 00 R8 9 240 09367 CAPSM ELEC 10uF 25V NONPOL 20 2 00 C12 13 240 13217 CAPSM ELEC 47uF 16V 20 3 00 C18 20 21 241 15206 CAPSM TANT 33uF 10V 20 2 00 C16 17 7 4 DESCRIPTION QTY EFFECT INACT REFERENCE INFO 245 10562 CAPSM CER 150pF 50V COG 10 2 00 C14 15 245 10588 CAPSM CER 33pF 50V COG 10 1 00 C1 245 10976 CAPSM CER 47pF 50V COG 5 2 00 C6 7 245 14588 CAPSM CER 01uF 25V X7R 10 06 2 00 C2 19 245 15691 CAPSM CER 001uF 25V X7R 10 06 2 00
217. 5694 CONN FFC 1 25MM 6 POS VERT 4 00 J17 18 21 27 510 15696 CONN FFC 1 25MM 4 POS VERT 1 00 J25 640 01701 SCRW 4 40X1 4 PNH PH ZN 1 00 U73 704 14452 HEATSINK TO220 MTTAB NUT 1 45H 1 00 U73 710 15570 PC BD ANALOG 8 1 00 PICK REV 4 PC BOARD 740 11287 LABEL S N PCB PRINTED 1 00 3 Channel Amplifier Board Assembly 201 16214 RES TRM 1T PC 1K OHM SA TOP 1 00 R168 201 16271 RES TRM 1T PC 1K OHM SA SIDE 2 00 R252 336 202 09794 RESSM RO 0 OHM 0805 5 00 R74 77 126 169 173 202 16231 RESSM RO 5 1 4W 2 2M OHM 3 00 R131 215 299 202 16232 RES CF 5 1W 10 OHM VERT 12 00 R140 141 143 145 224 R225 227 229 308 309 R311 313 202 16234 RES MO 5 2W 68 OHM VERT 24 00 R37 38 40 41 43 44 R110 111 194 195 R200 211 278 279 202 16255 RESSM RO 5 1W 30 OHM 6 00 R36 39 42 109 R193 277 203 11082 RESSM RO 1 1 10W 15 0K OHM 6 00 R87 90 171 174 R255 258 203 11732 RESSM RO 1 1 10W 1 82K OHM 3 00 R370 381 392 203 11980 RESSM THIN 1 1 10W 10 0K OHM 9 00 137 162 163 221 246 7 9 DESCRIPTION QTY EFFECT INACT REFERENCE INFO R247 305 330 331 203 12722 RESSM THIN 1 1 10W 49 9K OHM 3 00 R138 222 306 203 13134 RESSM THIN 1 1 10W 1 00K OHM 9 00 R144 155 165 228 231 R249 312 315 333 203 13638 RESSM THIN 1 1 10W 2 49K OHM 15 00 R86 88 91 93 150 R170 172 175 177 R234 254 256 259 R261 318 203 14566 RESSM THIN 1 1 10W 20 0K OHM 9 00 R151 154 235 238 319 R322 372 383 394 203 14891 RESSM THIN 1 1 10W 9 09K OHM 6 00 R98 101
218. 59 458 Da ETUR 3340 7 10 10 15V 1N4002 5VA 15V 5VA 15V 5VD 15V 13 12 VDD 5VR 9 83 15 A8 b ZONE_AMP 35 p 15V 5VR REGULATOR OIN gt GND 15V 5VD D33 1N4002 LEFT amp RIGHT ZONE WEEDS E 1N4002 D32 VDD CASE VOUT eoe 15V 9 B3 15 A8 R ZONE AMP 5 15 3jvIN vour 2 C397 CASE VOUT 5 1 6395 LM317M R304 C398 VIN VOUT 4 TT 1 25 15V 5VD GND R118 ADJ lt 357 10 16 LM317M R302 4 1 4 5 038 A 1 075 51 ADS gt 102 074 51 13 12 Y 1 00K VDD Et 15 1 15V E B3 15 B8 L REC AMP 6 5 DZ C399 2227 8 N 4 10 16 R303 5VD is EA LEFT amp RIGHT REC 4 5 038 g 12 s D gt A Y DG411 RC4556 47 25 D29 51 TEST POINTS VDD 4 2 R109 B V9o B B3 15 A8 P REC AMP 15V b 10 R120 U30 C146 10K 1 100 Y GND1 GND11 15 5VD GND 47 25 k 15 G GND2 GND12 h N a 5 88 G GND3 GND13 13 12 W R115 R116 0142 R106 3 3VD GND4 e GND14 VDD 15V ay peg St BELAY 4 G GND5 GND15 10 84 L FRONT HDP 5 5 D if 195 1 5 S R107 99 1 4W 6 ama GND6 GND16 IN 10 4 GND 15V 5VD 15V E J25 lt 100K GND7 GND17 LEFT amp RIGHT FRONT ue 47125
219. 65 R228 231 312 315 333 203 13638 RESSM THIN 196 1 10W 2 49K OHM 20 00 R2 4 7 9 66 86 88 R91 93 150 170 172 R175 177 234 254 R256 259 261 318 203 14566 RESSM THIN 196 1 10W 20 0K OHM 12 00 R67 70 151 154 235 R238 319 322 361 372 R383 394 203 14891 RESSM THIN 196 1 10W 9 09K OHM 8 00 R14 17 98 101 182 R185 266 269 203 16175 RESSM RO 196 1 4W 365K OHM 8 00 R129 161 239 240 R242 245 253 257 203 16235 RESSM THIN 196 1 10W 100 OHM 12 00 R75 112 116 118 119 R121 147 159 212 R213 243 327 203 16236 RESSM THIN 1 1 10W 100K OHM 28 00 R52 68 69 73 76 136 R152 153 157 160 220 R236 237 241 244 304 R320 321 325 328 345 R358 368 369 379 380 R390 391 203 16237 RESSM THIN 196 1 10W 12 1K OHM 4 00 R362 373 384 395 203 16239 RESSM THIN 1 1 10W 1 82K OHM 11 00 R23 83 107 167 191 R275 335 344 367 R378 389 203 16241 RESSM THIN 1 1 10W 23 2K OHM 16 00 R342 343 360 365 366 7 12 R371 376 377 382 387 R388 393 404 407 DESCRIPTION QTY EFFECT INACT REFERENCE INFO 203 16243 RESSM THIN 1 1 10W 280K OHM 4 00 R46 130 214 298 203 16244 RESSM THIN 1 1 10W 33 2K OHM 12 00 R48 51 62 132 135 R146 216 219 230 300 R303 314 203 16245 RESSM THIN 1 1 10W 47 5 OHM 4 00 R12 96 180 264 203 16249 RESSM THIN 1 1 10W 750 0 OHM 12 00 R13 24 55 97 108 139 R181 192 223 265 276 R307 203 16250 RESSM THIN 1 1 10W 75 0 OHM 4 00 R22 106 190 274 203 16251 RESSM THIN 1 1 10W 95 3 OHM 16 00 R20 21 30 31 104 105 R114 115 188 189 198 R199
220. 7 1 gt 12 B6 19 177 177 177 100 3 04 CLK12500B ek 10 GND 27 044 5VD CPUDATA 15 0 1 03 2 07 74VHCT245 20 2 FP D 7 0 m 2 41422 16 FP D2 CPUDATA3 Blas Bili5 FP D3 CPUDATA4 6142 5 7146 13 5 CONTRACT SS aci 7 lexicon 15 48 B8 BEDFORD MA 01730 198 DIR APPROVALS pate HTLE 10 DRAWN SCHEM MAIN BD RV8 TE RWH 4 26 02 DSP FPGA POWER CONN CHECKED 4 30 02 SEE CODE NUMBER REV 9 ac 060 15559 4 6 CW 5 1 02 FILE NAME al JV 4 30 02 15559 6 7 sHEET 7 OF 19 S 8 7 6 5 4 3 2 1 gt
221. 7 THE VENT HOLE ON TOP OF RELAYS K1 4 MUST BE OPENED AFTER THE Bo nl ut QE s gt ns ram OFF THE CIRCULAR TAB WITH AN EXACTO KNIFE OR SIMILAR CUTTING TOOL CM PHONE 574 294 8008 WARNING THIS STEP MUST BE DONE AFTER THE CLEANING PROCESS NOT UNCONTROLLED FILENAME ee ass PAE EONAR S 2 ee BEFORE WATER OR CLEANING SOLVENTS ENTERING THE RELAY VENT HOLE See Pops KOR ccce PAS aao rere eee __ 3E N N A AT TRON REPR T N WILL DAMAG THE RELAY INCLUDING ASSOCIATED ELECTRONIC REPRODUCTIONS ASSY DWG MOD 4CH RV8 ARE FOR REFERENCE ONLY VERIFY LATEST TOLERANCE UNLESS REVISION PRIOR TO USE OTHERWISE SPECIFIED THESE DRAWINGS AND SPECIFICATIONS ARE THE PROPERTY OF CROWN INTERNATIONAL INC AND SHALL NOT BE REPRODUCED COPIED OR USED AS THE BASIS FOR THE MANUFACTURE OR SALE OF APPARATUS OR DEVICES WITHOUT PERMISSION B BOO DRILLS 02 1 DO NOT SCALE DRAWING SCALE NDNE PROJ NO 5 SHEET 1 OF 1 2 REVISION HISTORY APPRDVED E C N ZONE REV DESCRIPTION DATE DWN CM PE 2 jam s n NOTES PER ECO es COMPONENT MAP D TOP SIDE S N LABEL P N 7480 11287 OR EQUIVALENT SEE NOTE 7 PLACE OVER HW4 AS SHOWN J12 m Jr wo 01 9 2 D
222. 7 13 C7 14 B5 15 A5 15 C5 ADA x CDTI AOUTR 8200PF 4 1143 L jay PAREC 9 C4 12 piro AOUTR 20 R214 R217 C234 Y 1 1 A A 15V Dri 19 E 316 33 idee 15 5VD 2 ore Dus a 13 12 1 Bend 15 s 681 Wc vip DG411 058 gin 2 c3 3 83 RIGHT REC IN s p 10 VEE GND al s U43 5VA v C113 7 C8 8 D3 L REC DACOUT 3 MC33078 R125 C117 V EE 1 M io M REC OUTPUT A 1 00K 10 2 d R18 R126 032 1 0 25 C114 LEVEL CONTROL UA 15 88 16 88 5 100K 2 R124 120 lt 1 00K 4 25 15V 15V 1 15 12 PGA2311 gt R22 RRES adi AGNDL VA 196 a 15 A8 16 B8 L16 AoOUTL 14 C63 M RELAY OdBFS 4Vrms 4 05 5 05 6 04 7 87 9 86 10 07 11 07 12 07 13 07 14 85 15 5 ADA SCLK 6 VD 4 U13 47 25 6 Ji 90 S ens C116 C115 SE vc 4 Ri FBI 7 A6 4 25 747 8 VACUA pe 4 ZONE2 LEFT 4 D5 5 D5 6 C4 7 A7 9 C7 9 B7 14 B5 15 C5 ADA VC SEL 2555 DGND 5 p sv R84 45VD n RCA OUT VAR bos 1 14 B3 ZCEN 1 ZCEN we AER Kw 402K 4 al 150PF T 4 C5 5 C5 6 C4 7 A7 9 C7 9 B7 14 B3 spour VC 4 L 1 15V ANR 5 MC33078 C64 1 AGNDR VA 6 1 1 025 16 lt J1 REC DACOUT 5 8 10 13 022 s R113 4 uig C89 R201N4002 R21 FB2 7 C8 8 C3 4 33078 412
223. 7 C249 8177 165 iN MSS 2 5 6 Ner GND 6 1200PF 1 53055 8176 1200 4 5 025 22K M R175 15V 121K 15V 5VD 1 196 13 1 ADG451 _RIGHT SIDE _ 5 MC33078 VDD 0 C160 6 GND Y 2 R147 asy R145 4 5 1925 AV d 4 AA 1 50K 57 6 ET 1 R146 196 is 15 432 C368 8200PF_R296 Ra 1 145 09 894 C71 415V C227 422 2 24K 12 02 L SIDE DACOUT 197 122 a 1 R202 R204 8200PF 22 4725 18V 5VD 838 Dio A R SIDE 15 D8 d lt 825 R300 422 2 21K 13 12 1 pe 1 1 ADG451 x VDD ee 422 S D 15 RELAY OdBFS 7Vrms OIN 6 FB VEE GND 4 R37 U26 1 LEFT SIDE OUT 4 5 100 gt Z y 45VD 11 1 4W C9 E 3 R95 C72 45V 4 A T 13 150PF T 122 R_SIDE DACOUT i De ce 9 li 3 ES 47 25 15V 5VD R39 BUS 1 825 415V 196 y 3 1 ADG451 6 7 gt VCC VDD 15V 8 10 P D2 E 3 gt 072 R110 AL en 2 RIGHT SIDE OUT __ MAIN_MUTE 1 gt S 100 BOR 10 6 11 6 13 6 14 3 S 2 U31 42 4 4W C10 78 NO exicon 3 OAK PARK Xx 150 T BEDFORD MA 01730 SE T T APPROVALS Y 15V DRAWN SCHEM ANALOG I O BD RV8 15V RWH 8 2702 SIDE DACS 10 A5 11 A7 13 A7 REY CHECKED 8 28 02 SIZE CODE NUMBER REV ac B 060 15579
224. 73 5 R38 RTA 7 8395 3 PIE EHE 88 eve o i 2 M 8181 18 ET I8 fee 18181 18 gt OW DIS 5 D38 Es D51 s m is 294 E m HHH c ra ER s dai ESI 50 HH A oe me a _ 7 iggi E PO gms m E gu 2 B z 18 ar rar c149 roar sel ens Lus PZ a iO 1071 294 541 OL quii bes be 915 zz m THRE 2 294 SEE NOTE 7 E Tl IPI212181 c Sag LEI I I 2s BISIBI8I2I 1 HARCANAN NP 1 R245 SEE NOTE 7 SEE NOTE 7 SEE NOTE 7 NOTES 1 HSG BOM NUMBER 23 15825 SUPERSEDES ANY INFORMATION ON THIS DRAWING 2 COMPONENTS TO BE INSTALLED ON TOP SIDE OF PCB UNLESS OTHERWISE NOTED BY AN ASTERISK 3 Al EADS TO BE TRIMMED TO 8 093 OR LESS 4 UNLESS OTHERWISE SPECIFIED MOUNT ALL COMPONENTS FLUSH AND PERPENDICULAR 98 DEG 1 DEG TO PCB ERES ERU NDS 5 PCB ASSEMBLY TO BE PACKAGED IN STATIC SHIELDING FARADAY CAGE WAS CROWN PART BER 35264 3 BAG THAT HAS AN ANTI STATIC NON CONDUCTIVE INNER LAYER THE 3 ASSEMBLY IS TO BE PROPERLY PACKAGED TO PREVENT ANY DAMAGE DURING SCHEMATIC SEE SUISSES SHIPMENT 6 SOLDER PASTE MASK PER HSG DOC NO 80308 18177
225. 74HC4051 2N3906 R3 4 4 TE 16 C405 5VV am R121 9 09K 5 Yo R5 R4 SC4B 14 6 8K gt 1 C5 2 C8 y 475K 1K t C5 2 B8 1 3 ZONE2 D5 2 88 SB Te 7 S VIDEO NE 5 5 1 25 1 5 SESB 21 6 41 25 Q2 Q3 m dk OUT 1 85 Y7 l 2N3904 2N3904 211 11 R1 101 1 00K 316 1 6 VSS VEE U13 5VV 5VV 1 C7 2 B8 4 B8 weet 1 C7 2 B8 4 B8 SC1 5 R153 1 07 2 88 4 88 7 5 6 Sc3 1 7 8167 1 87 100K 4019 R160 L n 145K CVID_REC1 TS R162 42 RISS ZONE2 1 1 15K COMPOSITE VIDEO R161 R166 1 750 36K OUT 1 R155 REC2 75 0 RECSVID SELO 1 9 83 P R154 CONTRACT 1 b RECSVID_SEL2 R158 e ex CO n FORS PARK 9 B3 150 15 BEDFORD 01730 TITLE APPROVALS DATE SAWN SCHEM VIDEO BD RV8 RwH 8 9 02 ZONE 2 CHECKED ECM 8 28 02 SEE CODE NUMBER REV 060 15589 3 cw 8 2802 mE 8 28 02 15589 3 3 sHEET 3 10 2 1 D gt 10 16 2003_16 28 8 6 5 4 3 2 1 REVISIONS REV DESCRIPTION DRAFTER CHECKER AUTH RWH CW 1 CHANGED PER DCR 030106 00 ee 1 21 03 RWH CW ah 2 CHANGED PER DCR 03
226. 74LCX14 TDO R66 U46 3 3VD 016 680 11 R67 74LCX14 ABT16244 36 Yi 680 777 2 33 16 Res U46 5 BCKO 32 T 3 ot R162 P12 220 OE 680 741 1456 R13 CLKOUTH89 U15 XTAL 163 N13 1 CLK 8 45 3 Bal Stile 2 CLK CFG1 FLAG11E 20 CLKDBL FLAG 10 30 P FLAG9LES Ho FLAG8 HES elo FLAG7 IRQ0 FLAG6 1 2 03 DSPBRESET 3 3VD FLAG5 GS 4 83 FLAG4L SI NO 4 R141 HBR FLAG3L 1 2 3 4 FLAG2 SI Ne RP3 RP3 lt RP3 10K E cs FLAGI NC it 10K PA ADSP 21161N aie n REDY PIL NC BRE HOST BLOCK E 5 po BRS BMsTR A2 W7 A Wo pad BR2 DMAR2p O O 520 BR1 J17 3 3VD DSPBTDO L_P MAGTPM A DMAG2pMi4 1 W104 L slo 2 L 2 Di NC 3 4 8159 NG 5 E2 7 EMU C2 Ewo 1 10 TRST TEST CONTRACT NC 11 B29 12 TDI Di NO ex CO n 3 OAK PARK 4 13 TDO BEDFORD 01730 QR160 us APPROVALS pate gt b DRAWN SCHEM MAIN BD RV8 RWH 4 26 02 DSP HOST 1 2 CHECKED 4 30 02 CODE NUMBER REV Qc 060 15559 3 Cw 51 02 Ssu JV 4 30 02 15559 6 3 sHEET 3 or 19 8 5 4 3 2 1 5 6 2004 9 30
227. 8 118 C111 Tm 10K ZONE2 RIGHT gt A 4 18PF 4 330 RCA gt 8129 8 1 00 10 25 52 15 Hee Vv 1 4W 62 OUT VAR 21 E hi27 eit E 4 02 150PF T 2 1 00K c SE 45V 2 y RELAY OdBFS 4Vrms J2 5VA FB3 4 R23 C65 8 DADA a O ZONE2 LEFT PN ee 330 RCA gt 47 25 5VD 1 OUT FIX lt R24 Mot 18 gt 5 9 150 T EA C66 18 5 2 CONTRACT 47 25 R25 4 Rog FB4 sp NO ex CO n 3 OAK PARK lt 10K A CO e ZONE2 RIGHT BEDFORD MA 01730 fs 330 RCA QUT FIX THE ZONE RLY W 4 3 APPROVALS DATE E SCHEM ANALOG BD RV8 R81 150PF DRAWN 8 27 02 14 83 ZONE RLY Ey I 2N4401 DAC amp OUT LEVELS 12K CHECKED 8 28 02 SIZE CODE NUMBER REV Y Q1 B 060 15579 3 Qc 8 29 02 FILE NAME ISSUED MAG 8 29 02 15579 6 8 SHEET 8 OF 17 8 7 6 5 4 3 2 1 10 7 2003 11 05 REVISIONS DRAFTER QC 5VD REV DESCRIPTION DRAFTER 222 ho 3 RWH CW OdBFS 4 3Vrms 18 de GHANGED BER DCR 02110700 11 14 09 11 20 02 DG411 CBV MAG VDD 11 20 02 11 21 02 OUTPU B D4 L REC 36 2 1 20 DACOUT 9 B7 2 CHANGED PER DCR 030407 00 OW
228. 8 00 75 00 120 00 n a 10 Fs 2 None n a n a 18 Internal 96000 Analog THD N 107 00 104 00 ______ 130 00 wa lt 10Hz gt 20kHzLP ma 6 18 96000 Analog ANLG ZONEZ TO DIG ZONE2 COAX OUT 96K BH E j j j ZONE2 COAX OUT 96K GAIN 1 4 00 Vrms 4 00 Vrms 997 None 20 at Level 0 40 0 00 1 10 n a lt 10 Fs 2 None n a n a 7 19 Internal 96000 Analog ZONE2 COAX OUT 96K FREQ 2 00 Vrms 2 00 Vrms 10 20 20 40k None 20 at Level 0 20 0 00 lt 10 Fs 2 19 Internal 96000 Analog 3 80Vrms 3 80 Vrms THD N lt 98 00 86 00 Float 48 48600 400 4500 0 52 7 19 96000 Anal ZONE2 OUT 96K DYNRNG 1 4 00 mVrms 14 00 mVrms 997 None 20 Unbal Float dBFS THD N 107 00 104 00 130 00 n a lt 10Hz gt 20kHz LP Narrow n a n a 7 19 Internal 96000 Analog DIG_ZONE2_COAX_OUT_96K_GAIN 1 4 00 Vrms 4 00 Vrms 997 None 20 Unbal Float dBFS Level 0 40 0 00 10 Fs 2 None n a n a 8 20 Internal 96000 Analog DIG ZONE2 COAX OUT 96K FREQ 2 00 Vrms 2 00 Vrms 10 20 20 40k None 20 Level 0 20 0 00 0 10 a lt 10 Fs 2 None 20 Internal DIG ZONE2 COAX OUT 96K THD 1 3 80 Vrms 3 80 Vrms 20 1k 5k 40k None 20 Unbal Float dBFS THD N lt 98 00 86 00 8 75 00 lt 10 Fs 2 n a n a 8 20 Internal 96000 Analog ANLG ZONE2 IN8 TO DIG ZONE2 COAX OUT 96K DYNRNG 1 4 00 mVrms 4 00 mvrms THD N 107 00 lt 10Hz gt 20kHzLP Narrow
229. 8 RESSM THIN 1 1 10W 2 49K OHM 8 00 R279 280 283 284 287 R288 291 292 203 15237 RESSM THIN 1 1 10W 681 OHM 4 00 R208 211 216 219 203 15479 RESSM THIN 1 1 10W 1 21K OHM 8 00 R160 165 170 175 R180 185 190 195 203 15674 RESSM RO 1 1 10W 57 6K OHM 8 00 R136 139 142 145 R148 151 154 157 240 09367 CAPSM ELEC 10uF 25V NONPOL 20 20 00 C31 32 35 36 39 40 C43 44 47 48 51 52 C55 56 59 60 117 C118 125 126 240 09786 CAP ELEC 100uF 25V RAD LOW ESR 3 00 C449 452 455 240 11827 CAPSM ELEC 10uF 16V 20 7 00 C352 357 362 367 C398 399 473 240 12136 CAPSM ELEC 33uF 10V 20 1 00 C459 240 13217 CAPSM ELEC 47uF 16V 20 8 00 C320 323 328 331 C336 339 344 347 240 13642 CAP ELEC 47uF 25V RAD NPOL 6D 18 00 C63 76 141 142 C145 146 240 15668 CAPSM ELEC 330uF 6 3V 20 105C 22 00 C238 239 241 243 245 C247 249 251 253 C255 257 259 261 270 C278 286 294 302 396 241 09798 CAPSM TANT 10uF 10V 20 2 00 C393 458 241 11799 CAPSM TANT 4 7uF 6 3V 20 52 00 C112 113 115 120 121 7 7 DESCRIPTION QTY EFFECT INACT REFERENCE INFO 245 10561 245 10562 245 10587 245 11594 245 11598 245 11949 245 12316 245 12485 245 13810 7 8 CAPSM CER 100pF 50V COG 5 CAPSM CER 150pF 50V COG 10 CAPSM CER 18pF 50V COG 10 CAPSM CER 2200pF 50V COG 5 CAPSM CER 8200pF 50V COG 5 CAPSM CER 1500pF 50V COG 5 CAPSM CER 0082uF 50V X7R 10 CAPSM CER 1uF 25V Z5U 20 CAPSM CER 1200pF 50V COG 5 08 16 00 36 00
230. 8 is uninstalled and R157 is installed This places the FPGA in master serial mode This is appropriate for loading from a serial EPROM In this mode of operation the FPGA provides a shift clock out of the CCLK pin to the programming EPROM which in turn shifts programming data into the DIN DATAO pin synchronous with this clock Resistors R128 through R131 R133 through R135 and R148 through R151 configure the source of programming The default condition routes the serial data and shift clock from the host CPU In addition the INIT PROGRAM and DONE pins of the FPGA are routed to the host The following table illustrates the configuration for this mode 6 29 RV 8 Service Manual FPGA Programming Source Configuration Table FPGA PROGRAMMING CONFIGURATION R128 R129 R130 R131 R133 R134 R135 R148 R149 R150 R157 R158 1 IN IN IN IN OUT OUT OUT IN OUT IN OUT OUT IN Host Programming Default OUT OUT OUT OUT IN IN IN OUT IN OUT IN IN OUT EPROM Programming Development Host Bus Interface Signals CPUADDR 9 0 LVDATA 7 0 CPUCSZ CPUWRL CPURD BUFDIR CPUCLKOUT RESET The AVRX FPGA internal registers are contained entirely within the CS2 memory space of the host CPU Therefore the memory space that these registers occupy begins at a base address of 0x00800000 Register accesses are implemented over a byte wide data bus LVDATA T 0 with 1Kbytes of addressing implemented over a 10 bit wide address bus CPUADDR 9 0 Write acce
231. 99 U6 56 i 12 55 DE 3 B3 8 C4 026 Y R71 4 4 11156 T 150 100K 0157 15V dos 9 fsg 1 AO 1 A2 M 1 16 15 2 U11 415V ycs 14Dal REC_ANLG SELO 5 14 9 REG ANLG SEL 4 2 ERR R68 1 C5 14 C3 S A JI2 ia aw 1925 T 1 08 14 C3 s PEC ANLG 4 C24 lt R67 15V 15V T 150PF gt 100K 15V 1 15V 8 14 Y 3 CONS TUS ZONE SOURCE SELECT RIGHT ih 531 C44 65 5 2 cL EA R64 E 12 85 p RIGHT_ZONE_IN 3 A3 9 C4 lt RCA 100 D8 100 Ps 11155 BA 1 4W BAvgg 1025 56 10 187 1 22 y lt R63 58 150PF i lt 100K AO 1 A2 1 16 15 2 U10 7 15V ZONE ANLG SELO Ws Ge 14 03 ZONE SELI 4 1 85 14 63 ZONE ANLG SEL2 86 C40 8 1 85 14 03 ZONE_ANLG_EN 6 m um 5 11972 860 lt 100 10 25 pL DADA 8 14W 56 15V 5VD 4 C20 y lt R59 n T 150PF T 100K Y T SUB UNITY GAIN PASS THRU 5 13 12 15V AS DG411 7 3 CC VDD V 15 s D SUB_IN 5 C8 4 15V m o GND 15V 5VD R4 C36 _8 4 5 09 7 je A 5 TLO72 856 13 lt RCA 100 og 10 25 J9 3 1 4W BAV99 U2 56 15V e ycc VDD e 4 S D T T 9 UK 415V 5VD 8 IN dd 45V VEE GND ih 5 U9 RIGHT SIDE UNITY GAIN PASS THRU L 13 12 15V VDD BV 14g 15 15 RIGHT SIDE I
232. A7 2059 bs ne Roni VDD 2747 088 20 D6 i DO 44 DATAO ADR18 ZS NC 3 lour NTSC EN 2 9 63 26 9 207 Br 45 DATA1 ADR19 78 0 _ 23 A10 D2 46 ADR20 2 4FS GND 25 03 47 4 R136 036 2 12 10K D4 48 DATA4 18 NC 28 13 05 49 DATAS 17 4 291174 D6 50 DATAS ae 8l 5VV 3 M5 7 DI 51 7 2353 2 16 20909099 4 17 73448MHZ 1 30 a A o A O 00 0 0 o 12808 NC1 90NS 026 E1 3 oUT IN LL PAL EN 9 C3 9 C3 m VROM_WR E WR L7 GND E U37 al 16 99 o100 025 SD 15PF 4XFSC OSCILLATORS 3 PARK ON SCREEN DISPLAY AI15 0 BEDFORD MA 01730 i TITLE APPROVAL DATE SCHEM VIDEO RV8 DI7 DRAWN RWH 8 9 02 m 7 0 ON SCREEN DISPLAY CHECKED EcM 8 28 02 SKE CODE NUMBER REV 9 cw 8 28 02 060 15589 ISSUED MAG 8 28 02 15589 37 SHEET 7 oF 10 9 8 7 6 5 4 3 2 1 6 5 4 3 2 1 REVISIONS REV DESCRIPTION ARAR TER 1 CHANGED PER DCR 030106 00 ao MAG 5 2 CHANGED DCR 030421 00 E CM MAG 5 20 03 5 22 03 15V Sepia CHANGED PER DCR 030623 00 ee ee 1N4002 MAG D 1N4002 4 10 9 03 78L05 vN 1 COMMON U29 C136 L C137 D n SYNC STRIPPER leg
233. ASED COPY J18 frezalar adiera S J22 RPISIRP2O 21 22 23 P24 C168 R187 ks N sd 1 5 1 24 ti FB18 14 J2 1 DIMENSIONS ARE IN INCHES O 49 1 J28 18 1 TOLERANCES J23 224 J26 rsi J29 231 je FRACTIONS DECIMALS ANGLES 4 1 01 APPROVALS DATE PC BD MAIN BD RV8 005 id 4 26 02 T ASSEMBLY DRAWING dup SIZE FSCM DWG NO REV APPLICATION DO NO SCALE DRAWING ISSUED 4 30 02 1 5 SHEET 1 2 D
234. B PE14 DACKON AHN i FLBY 7B5j 20 1 4 DSPHOSTIANDE US E AHN lt 1 83 i l 1 E EP dra 3 OF 19 4 DSP HOST 1 AND 2 mel TEE E u svo T TEMP6 8127 O 98 87 CPUADDR20 9 NAL MEMORY TEMP5 8126 0 96 EF ANE 2 CPUADDRIS 16 an 6 OF 19 3 DSP SPI SERIAL AND LINK PORTS p SPARE AD m Q PF5 ANS TIOCOD DRAK1 5 CPUADDRI8 171418 37 132 7 19 4 DSP FPGA POWER CONN TEMP4 8124 0 94 EA ANS PE15 CPUADDRi7 48 ids dk 8 OF 19 3 CRYSTAL DSP TEMP3 R123 O 93 AN2 PAO RxDol 5 CPUADDRi6 1416 BYTEDA 9 OF 19 3 MAIN FPGA 2 8122 0 92 a 50 CPUADDR15 2 15 FLBY 10 OF 19 3 EPGA FLASH Wege p R121 O ILE ANO 48 CPUADDRI4 _ 21414 RYBY gt 1 85 Een 3 EXPANSION PORT SERIES TERMINATIONS B M 19 BOARD SDATA 115 PA4 TXD1 7 CPUADDRI2 5 rais 725 452 CBUBATATI 13 OF 19 3 HAAS OVLED 111 2818 73 CPUADDRII 614 PAISAI CPUDATAI3 14 OF 19 3 TRIGGER OUTPUTS 12 8 SYSLED n 110 03 751 CPUADDRIO 7 3 39 CPUDATA12 15 OE 19 3 VCOA PET MD2 CPUADD A9 0012 16 19 VCOB 12 86 lt a ao PE 0 78 4 Dans 17 19 3 POWER SUPPLY NC 106 MD0 CPUADDR7 1947 001032 CPUDATAS 18 OF 19 IR REMOTE CONNECTOR D s CP ADDRS 20 As DQ9 30 19 OF 19 4 BYPASS CAPACITORS UADDRS 21 44 __
235. B90092 0SDC PQFP 1 00 U26 390 10516 RESONATOR CER 503KHz 1 00 Y1 390 13857 CRYSTAL OSCSM 14 31818MHz TRI 1 00 U36 390 13858 CRYSTAL OSCSM 17 73448MHz TRI 1 00 U37 390 14544 CRYSTAL OSCSM 24 576MHz TRI 3V 1 00 U33 410 11639 RELAY 2P2T DIP 5V HI SENS 6 00 RY1 6 510 13128 CONN MINIDIN 4FC PCRA GND 9 00 J1 4 11 15 510 14079 CONN POST 156X045 HDR 4MC LOK 1 00 J18 510 15471 CONN RCA PCRA 1FCGX2V GRN GND 2 00 J7 10 510 15472 CONN RCA PCRA 1FCGX2V RED GND 2 00 J5 8 510 15473 CONN RCA PCRA 1FCGX2V BLU GND 2 00 J6 9 510 15688 CONN FFC 1 25MM 16 POS VERT 1 00 J20 640 01701 SCRW 4 40X1 4 PNH PH ZN 1 00 032 704 06165 HEATSINK TO220 75X 5X 5 TAB 1 00 U24 704 09508 HEATSINK TO220 MTTAB W 4 40NUT 1 00 U32 710 15580 PC BD VIDEO RV8 1 00 PICK REV 4 PC BOARD 740 11287 LABEL S N PCB PRINTED 1 00 Video In Board Assembly 202 10946 RESSM RO 5 1 10W 3 3K OHM 5 00 R1 4 7 10 13 202 13579 RESSM RO 5 1 10W 22 OHM 5 00 R2 5 8 11 14 203 10560 RESSM RO 1 1 10W 75 0 OHM 5 00 R3 6 9 12 15 240 11827 CAPSM ELEC 10uF 16V 20 2 00 C11 12 245 12485 CAPSM CER 1uF 25V Z5U 20 10 00 C1 10 310 10510 TRANSISTORSM 2N3904 SOT23 5 00 Q1 5 510 13147 CONN RCA PCRA 1FCG YEL GND 5 00 J1 5 680 15684 CABLE FFC 14CX 1 CRMPST RA 2 5 1 00 J6 710 15500 PC BD VIDEO IN RV8 1 00 PICK REV 0 PC BOARD 740 11287 LABEL S N PCB PRINTED 1 00 Video Out Board Assembly 510 13147 CONN RCA PCRA 1FCG YEL GND 4 00 J1 4 680 16146 CABLE FFC 14CX 1 CRMPST RA 1 5 1 00 J5 710 15510 PC BD VIDEO OUT RV8 1 00 PICK R
236. C DAC FS 14 5 CHANGED PER DCR 031124 00 FB5 9 B2 FS E 12 0 03 12 30 03 is 9 82 ADC CAM MAG 1 A3 m DEBUG TXD u gt IXDA m 9 82 MAIN FS 16 12 8 03 12 30 03 s 9 82 p REC_DAC FS64 18 1 MAIN 125 IN4 19 lt DEBUG 12 13 rm p 20 FS64 21 Es 1 E dee DAC 125 OUT 22 23 USER TXD 10 7 TXDB AA 47K 47K FS64 24 25 26 MAIN 125 MAIN_I2S_IN 3 1 Ta FB4 27 MAIN 128 yc VAS a USER 9 A 8 rmm RXD B 28 MAIN 12S IN 29 12 14 TXD B J4 bi MAIN 125 OUT 4 1 ain 125 OUT4 30 1 U5 13 T 150PF T 150PF 9 83 MAIN 125 OUTS 31 150PF E MAIN 125 OUT 32 MAIN 125 OUT1 33 34 _ _ 35 1 9 B2 36 C REC_ADC_MOKV 37 38 MAIN FS256 39 1 9 82 39 1 AMP BOARD 5 d 45VD 5VD 45VD 5 0 3 3VD A A A VIDEO BOARD CONNECTOR 8187 lt 171 FLEX FRONT PANEL CONNECTOR 10K 10K FB16 FB18 3 3VD 45VD R181 4 R180 9 A2 SER CLKA 1 jan 47K 4 7 9 82 CTRL_DATA 3 1 Pu s VIDEO DATA STAT DATA 5 m FP_RESET 2 lt 5 9 A2 a n SYSTEM ON LED 3 VIDEO SCLK 4 9 2 LATCHA 18 83 FF IR_BLINK RET 5 7 OSD CS 1 8 18 83 lt a 2 9 B2 5 9 9 C2
237. CAM MAG RP CPUADDR1 24 Ag voc 4 11 06 02 12 20 02 2 CPUADDR19 DRAN CPUADDR2 25 40 21 CPUDATAO 2 CHANGED PER DCR 030307 00 s 10 CPUADDR1 17 21 CPUADDR3 26 101 22 CPUDATA1 S 2 03 5 20 03 IPIE csE abis CPUADDR2 18 49 acl 6 _ 2 102 19 _CPUDATA2 8040 CPUADDR3 19 1 U R5 28 103 18 14 03 5 20 03 1 CFUADDRI 29 A2 CPUADDRS 29 104 17 CPUDATAR 8 CHANGED SHT 12 PER DCR 030307 00 A ere sma a D 2 07 CEUADDRS 3 A4 CPUADDRS 31 A 128 15 CPUDATA6 CAM MAG 9 C8 CPUADDR7 25 5 CPUADDRS 32 196 14 CPUDATAT 52203 5 22 03 UADDRIO 35 117 CPUDATA8 FOM PUADDR 4 CHANGED PE SVD SVD GPUADDRS 2917 2 CPUDATAI CPUADDRII 36 40 log 10 CPUDATAS ibo TUN 9 29 03 10 9 03 CPUADDRIO __28 48 014 2 CPUADDRI2 3 Aq 1019 NC 16149 D2 CPUADDR13 38 8 CPUDATA11 10 2 03 10 9 03 NC 16 No 085 CPUDATA3 CE ARBBI 3 12 1011 m cw NG 15 NC D3 7 GpUDATAE CPUADDR OI Z CPUDATA12 5 CHANGED SHTS 1 3 12 PER DCR 031124 00 R118 Jg 52 8 UADDRIS __40 A14 1013 6 CPUDATATS SES 123008 205 usare 13 wr 9 CPUADDR16 411445 10145 CPUDATA14 AG 1 R120 144 06510 CPUDATA7 CPUDATA15 12803 123003 6 5 43 1 N R119 ______80 88888 9 35 5 __________ 29 6 33 CPUDATA8 W
238. CAPACITORS ARE UF V D8 A3 U D8 A9 CPUDATA7 62 6 CPUADDR2 11 30 4 DIGITAL D7 U GNDi GND2 ANALOG CHASSIS POWER 5207 ME ESTE w3 CPUDATAT 12 98 GND2 29 CPUADDRS 77 GROUND V GROUND 7 GROUND GROUND CPUDATA5 64 55 4 CPUADDRO CPUDATA6 13 06 7 28 CPUADDR8 CPUDATA4 66 D2 A0 10K 10K 9 CPUDATAS 14 52 27 CPUADDR7 5 XX XX DENOTES SHEET NUMBER SECTOR are 68 CPUDATA4 15 26 CPUADDRG 6 LAST REFERENCE D CPUDATAS Hos CPUDATAS T D4 As 2S CPUADDRS A diss 2 USED C178 049 2818 J32 13 02 CPUDATA1 69 40 PROGCS CPUDATA2 17 24 CPUADDR4 RP37 U48 W10 Y2 D1 CS1N D2 A3 u 40 PROGOS 18 23 CPUADDRS 7 COMPONENTS MARKED WITH AR eer FBI4 CSON CPUDATAO 19 01 42 22 CPUADDR2 a 20100 2071 s CPU CRYIRQ 1 S 42 RDN 0 21 CPUADDRI PA9 TCLKD IRQ3N WRHN 77 PU DSPA 77 2 07 _ 43 TCLKC IRQ2N WRLN 538 a PA5_IRQ1N SCK1 CPU KYBDIR _ 2 07 m PU Cy 39 RQON SCK0 5 IRQSN RDwR 24 4 CPUCSY 7 85 is 2 RASN Z2 CPUCS2 5 I C git DOCUMENT CONTROL BLOCK 44060 15559 ze FPGA INIT 102 4_ PB4_IRQ2N 55 CPURDWR 9 8 SHEET REVISION TITLE 9008 102 PES PB3 IRQ1N CASL CPUWRL gt 1 OF 19 6 HOST PROCESSOR Irpa lobe FPGA DONE 105 TIOCP
239. CATION __ DO NOT SCALE DRAWING SUED we 1 1 JUL 09 2004 4 3 2 1 TORQUE 8 10 IN LBS TYP WIRE G WHITE WIRE H BLACK WIRE E YELLOW WIRE F BLACK WIRE C VIOLET WIRE D BLACK TORQUE 6 8 IN LBS 2 5 12 14 IN LBS 1 PART NUMBER LISTING IS FOR REFERENCE ONLY AND DOES NOT SUPERSEDE THE BOM UJ TORQUE 10 12 IN LBS 2002 SO emez scm 6 32 x VA SS Z so tez 6 32 x 1 4 PAH TORK 82 2 3 P sume __________ ss tezs sem 6 32 x REX AIM 2 seres 7111 UNLESS OTHERWISE SPECIFIED ACAD 2002 FILE NAME 10 12 NALES TOLERANCES waq 16436 0 XX 00 ayz amas pam 55 DWG ee MECH PS RV 8 ZE FSC NO 0 NO ke m 080 16436 0 APPLICATION DO NOT SCALE DRAWING SSUED n zvos sene ser DEC 05 2003 REVISIONS DESCRIPTION DWR CHKD Q C AUTH APPLY HEATSINK COMPOUND TO BOTTOM SURFACE OF TRANSISTOR 1 PART NUMBER LISTING IS FOR REFERENCE ONLY amp DOES NOT SUPERSEDE THE BOMS Lors SL AUB wxswe PART NO ACAD 2002 FILE NAME 16438 0 lexicon ASSY DWG a pops HS SOL RV 8 e B
240. CODER 1 21 03 1 23 03 RWH CW Rosi 2 CHANGED PER DCR 030421 00 wot 10K 10K ECM MAG 52003 5 22 03 10 A6 lt VID 120 SDATA 3 CHANGED PER DCR 030623 00 VID I2C SCLK ECM MAG 10 A6 10 908 10 16 03 R210 C156 2 D5 7 D8 SD Y IN 11 PLAYSPEED 4 9 C6 205 056 50 XRV o R226 47 1 DEC XRH amp 6 7 9 87 1 8213 57 C153 2 A5 7 C8 m SD 9 86 205 R234 056 50 ER J dus 110 SDA E 1 SCL_E R CR C 6 C6 PDS G VBS CVBS 6 06 C Jv R232 SAA 7109E BTI NC PD11 B CB CVBS 6 C6 ks HPDOLATI NC PD10 DECODER PD9 E14 NC PD8 07 NC PD7 IPDSLC14 NC PD6 sv R143 P11 IPDA EIS NC Pa 2 03 Al12 PD3 VSOUT 18 235 05650 ID C18 NC PD2 110 IPpoLB13 PD1 SAA 7109E 1 PD0 ENCODER G14 NC 914 NC sc p R140 x VSVGG RSET 2 03 Al22 FSVGC 52 8233 056 50 NC CBO DUMPA 110 12 NC DUMPB 1 CLK ATANG TTX SRES MARNE TTXRQ XCLKO2 Y J12 NC PIXCLKO NC PIXCLKI K14 NC ASCLK STS NE NC D3 mus E Al23 AMCLKHSL2 NC ET E AA _ Al24 DEC_HS 9 C6 DIE Arey DEC 6 NC D 6 D7 9 C6 B L14 9 83 ENC_RES D2JRES LLc NC A6 ENC 27MHZ AB XTALO RES p 2 9 83 27 C151 RES a
241. COMR esi R311 1 25 28 10 4 REC ADC 192K EN __ 4 C5 5 C5 6 C4 8 B7 9 C7 9 B7 14 B3 _VC_MUTE spout 4 VC 3 S ADC 96K EN lt 14 83 gt 106 47 C408 OSR0 14 83 7103 RIGHT_REC IN HALF 9 n 1 25 27 m C350 t GNDR 5 345 MAIN 125 ina AGNDR VA E R315 SDATA VA 15 A5 15 C6 47 10 13 mm Boni M 25 REC ADC FS a Lis see R264 R2 1 51 AINR C317 ZAGOK je EM 14w 16 REC 864 15 83 15 D5 i AGND SUE 22 LC401 MCLK 18 MOKI 15 B3 15 D4 1 25 RAR 6 5VA 2200 CONTRACT H C316 5VA 13 19 REC ADC RST 14 B3 NO lexico n 3 OAK PARK t CF Y BEDFORD MA 01730 47 C323 R265 8 MC33078 ME TITLE 6 R281 APPROVALS DATE 62K i ENS SCHEM ANALOG BD RV8 4716 5 62 DRAWN nwH 8 27 02 5VA 1 Du REC A D CONVERTER CHECKED 8 28 02 SIZE CODE NUMBER REV ac B 060 15579 3 CW 8 29 02 FILE NAME ISSUED MAG 8 29 02 15579 6 7 SHEET 7 OF 17 8 7 6 5 4 3 2 1 10 7 2003 11 05 8 7 6 5 4 3 2 1 15V 5VD REVISIONS 4 4 DESCRIPTION DRAFTER QC mS REC D A CONV
242. C_MUTE 8 spour 7 VC 0 5 D5 3 86 6 08 7 08 MIC1_IN 5 9 11 RIGHT MAIN 8 IN MAIN IN 4 A8 10 B5 GND 15V 5VD RONDE VA MIC INPUT 4 5 U50 TM 10 U67 276 Y 13 12 medii i 100K 15V VDD C341 L 3 B6 6 C8 7 C8 2 IN 1 8 pHo 1 MC33078 257 gt VA 1 25 6 j VEE GND 4 1 00K C340 5 258 057 R259 G 4 s U50 gt 100K ii 1 00K oA 47 14 03 MAIN PHONO75_SEL Y 45 1 14 03 MIC SEL 515 5VA C390 MAIN A D CONVERTER 100 8337 A 5VA 3 3VD 2 00K li 1 de 5VA OdBFS 0 884Vtms 2555 C363 R336 8 MC33078 C446 C441 AUR s gt gt R338 100PF 2 00K H 47 47 R291 w U80 1M4W C447 C442 2 49K T Ts OdBFS 2 0Vrms 15 C436 25 4 4 06 B 5VA 1804 22 vp 14 355 344 R274 8 MC33078 4 02 10 05 LEFT_MAIN_IN_LVL 2 pil R290 amp ovr 4716 5 62 gt AINL OVER HE 1 1 24 071 439 BYPAS 12 5VR W 3 1 vREFL 5VA 47 C438 23 354 iid THS GNDL FMT1 7 lt R334 lila C440 lt n 100PF 3 VCOML 4 Q R340 1 25 26 SM I RENE s 6 4 lt R335 2 00K 1 25 OSR2 lt 5 210 06 19 4 5 28 VREFR OSRI H MAIN 5 B4 6 A4 14 B3 21 45VA 47 6444 OSRO LADC 96K EN 5 84 6 A4 14 B3
243. C_OUT is formed as half the sum of the buffer outputs These OSD output signals feed the output amplifiers as described earlier In order to produce usable overlays in the SECAM system the OSD switching action is bypassed at high frequency through U35 and R146 preserving an attenuated version of the fm color carriers On Screen Display Serial Control Video board schematic sheet 7 The internal registers of the OSD are programmed serially from the main board in multiple 8 bit packets on VIDEO DATA accompanied by VIDEO SCLK operating at 1 MHz During routine OSD updating OSD_CS is level shifted by 035 becoming OSD_CS5 the OSD chip select The CPLD generates OSD SCLKG from the VIDEO SCLK and U35 drives OSD SCLKS to clock the data into the OSD chip Each logical transfer to the OSD chip consists of a pair of single byte transfers Sync Stripper DC Restorer Video board schematic sheet 7 Video from input amplifier U28 is fed through R204 to U41 which drives sync stripper U39 and the dc restorer formed by switch U40 and op amp U41 Sync stripper U39 accepts analog video and extracts vertical and horizontal sync producing logic level VSYNC OUT and AFC OUT pulses respectively A phase locked loop based on ceramic resonator Y 1 provides robust horizontal sync extraction even from noisy video sources Pull down resistors on the outputs improve the pulse waveshapes Sections of U42 buffer and shape the pulses from 039 AFC OUT is stretched
244. D THROW OUT BLAN LDERING AND PRIOR TO IN CIRCUIT INFORMATION SIDE PONENTS HIELDING NON IS TO BE URING SHIPMENT 0 15577 JUL 22 2005 RELEASED COPY UNLESS OTHERWISE SPECIFIED DIMENSIONS ARE IN INCHES TOLERANCES ARE FRACTIONS DECIMALS ANGLES CONTRACT NO PC I O RV8 DRAWN 21 02 gt _ MATERIAL ASSEMBLY DRAWING CHECKED 8 z29702 rere SIZE FSCM NO DWG NO REV Q C 4567 ag eee Gn cw 8 29 02 D 080 15578 4 APPLICATION NO SCALE DRAWING ISSUED wag 8 29 02 SCALE 1 1 SHEET 109801 J14 SGHESY yGuccH 854 9 S tule ru 074 o ogu 7942994 cc gy 194 2
245. DE Right RIGHT MODE Mute MUTE MODE The MAIN switches MAIN Switch Name where Switch Name is the name of the Switch that is labeled on the front panel The Zone 2 switches ZONE 2 Switch Name where Switch Name is the name of the Switch that is labeled on the front panel The Zone 3 switches ZONE 3 Switch Name where Switch Name is the name of the Switch that is labeled on the front panel The Tuner switches TUNER Switch Name where Switch Name is the name of the Switch that is labeled on the front panel When all twenty two switches have been pressed the display will indicate SWITCH TEST All Switches Done 2 Press the Mode button to proceed to the next test Encoder Test This test verifies the operation of the encoder knob Setup The front panel display should indicate ENCODER TEST ENCODER Test Test 1 Turn the encoder knob clockwise until the display indicates ENCODER TEST Encoder Test CCW 24 Turn the encoder knob counter clockwise until the display indicates ENCODER TEST ENCODER Test Passed 3 Press the Mode lt button to proceed to the next test LED Test This test verifies the operation of each of the twenty three front panel LEDs Setup The front panel display should indicate LED TEST LED Test 11 STBYRed RV 8 Service Manual Test 1 the encoder knob clockwise and verify that each LED lights individually and is the correct color See the color code ta
246. E NC1 5 Ne 6 CHANGED SHTS 7 amp 19 PER ECO 040422 00 4 27104 429 04 81 gt gt gt gt gt lt NC 305 UCAS D9 34 CPUDATA9 OE NC2 CAM C118 C117 PLLVSS 32 pio 35 GPUDATATO ncs 13 Ne 1 3K 117 824 pri vss PB9 IRQ7N A21 PUD 33 9 04 5 2 04 470 1 25 PB8_IRQGN_A20_WAITN 34 20 NO bl BH CPUDATAT 12lyss1 NCSLA2 NG a PB7 A19 30 GRUADDRI9 NC 12 NG 018 39 CPUDATAIS 34 552 23 10K ADDR20 ADDR19 CPUCLKI 74 PB6_A18 0 40 CPUDATA14 7 83 EXTAL 17 22 GPUADDR17 22 01441 CPUDATA15 032 NAE ie Qt G U 37 32 NC 15 18 GPUADDR14 142 45VD CPUADDR20 A14 717 CPUADDRI3 60NS EMULATOR CPUADDR19 A13 1MX16 5VD 1 106 SH7014 A12 18 CFUADDRI2 A17 veo NN R114 12 15 CPUADDRIT gt U42 ROMUCS 2 wr 39 CEUADDR18 CPUDATA15 52 pig 11144 CPUADDR10 5 3 D15 A16 38 CPUADDR17 CPUDATAT4 53 019 13 CPUADDR9 JUMPER SELECT t D14 Ats 32 6 NOTES UDATA13 54 12 PUAD PIPER 135 36 CPUADDRI5 EPUDATATS ota CPUADDRS 1 2 BOOT FLASH hi R85 CPUDATAT2 013 A14 35 CPUADDRI4 TUNLESS OTHERWISE INDICATED RESISTORS 1 10W CPUDATATT 57 11 AS 10 CPUADDRG 3 ROMULATOR WS 10K 7 D11 12 34 GPUADDRIS 2 UNLESS OTHERWISE INDICATED RESISTORS ARE 5 C D10 A5 U D D10 11 CPUDATAS 59 D9 Ad 8 CPUADDRA 5VD CUB ATAS m D9 A10 32 CPUADDRIT 3 UNLESS OTHERWISE INDICATED
247. E RIGHT Channel 2 channel on the four channel module Features Full complementary output topology e High performance error amplifier to provide extremely low THD e Ultra high 140V rails to maximize dynamics e Critical protection circuits local to each amp channel Input Stage Op amp U1 A MC33078 is used to set up a conventional balanced to single ended conversion stage The overall gain of this stage is approximately 6 15 6dB which is set by R2 2 49k R4 2 49k R3 15k and R5 15k C1 22pF provides high frequency feedback Power Amplifier Overall Gain For this portion of the theory consider the power amplifier as one large op amp The output of U1 A MC33078 feeds a single ended audio signal into the power amplifier The power amplifier is set up as a conventional inverting amplifier The gain of this stage is approximately 10 20dB which is set by R7 2 49k R9 2 49k and R10 49 9k Bias Bias is set by R14 9 09k R17 9 09k R15 825 and R16 825 This causes a small equal current to flow through R19 825 and R29 825 via steering diodes D4 1N914 and D7 1N914 R19 drives Q5 MPSW92 and MPSW 92 while R29 drives Q9 MPSW42 and 010 MPSW42 These four transistors also serve as voltage translators Emitter resistors R20 95 3 R21 95 3 R30 95 3 and R31 95 3 set a current used to bias Q8 MMBT3904 R84 1k potentiometer is then used to precisely tune the bias level to
248. EADPHONE OUT THD 3 80 Vrms 20 40k None 600 10 gt 500 40kHz LP Analog LG ZONE2 IN1 TO ANLG ZONE2 HEADPHONE OUT XTALK 4 00 Vrms 15k None 1 2 00 Vrms 1 3 80 Vrms 1 4 00 Vrms Leve lt 0 45 0 0 0 40 0 10 0 8 0 25 0 8 THD N lt 002 009 00005 Level gt 73 00 70 00 150 00 600 lt 10 gt 22k None 1 13 Internal 1 13 Internal 1 13 Internal n a n a n a Analog ZONE3 ANLG ZONE3 HEADPHONE OUT FREQ LG 2 IN1 TO ANLG ZONE3 HEADPHONE OUT THD 2 00 Vrms 2 00 Vrms 10 20 20 20k 20k 40k 20 3 80 Vrms Unbal Level 0 45 0 0 0 4 0 8 0 25 0 8 lt 10 gt 500 40kHz LP Level 448 ______ 4 60 444 7 600 lt 10 gt 500 11 23 15 Interna 11 23 Internal 600 lt 10 gt 500 None 11 23 15 Internal LG ZONE3 IN1 TO ANLG ZONE3 HEADPHONE OUT XTALK 4 00 Vrms 20 10 gt 22k None 3 11 23 3 Interna 3 LG ZONE3 IN1 TO ANLG ZONE3 HEADPHONE OUT SNR OFF 20 10 gt 22k None 11 23 Interna LG 2 IN1 ANLG ZONE3 HEADPHONE OUT RELAY LG 2 IN1 TO ANLG ZONE3 HEADPHONE OUT RELAY MUTE Interna A A FM Tuner Tests See Test Name Note Left ZONE2 TUNER FM98 TO ANLG ZONE2 DIR HEADPHONE OUT Analog Generator Right Bal EQ Curve Z out Unbal Analog Analyzer Gnd Float Level Measure Typ
249. ELEC 1uF 50V 20 5 5mmH 2 00 C42 84 240 12983 CAPSM ELEC 100uF 10V 20 2 00 C96 144 240 13217 CAPSM ELEC 47uF 16V 20 9 00 C22 24 41 45 53 C60 83 87 149 240 13913 CAPSM ELEC 470uF 16V 20 5 00 C17 78 139 177 178 7 1 DESCRIPTION QTY EFFECT INACT REFERENCE INFO 240 15668 CAPSM ELEC 330uF 6 3V 20 105C 4 00 C39 75 133 134 240 20028 CAP ELEC 6800uF 6 3V RAD 20 2 00 C73 130 241 09798 CAPSM TANT 10uF 10V 20 3 00 C52 94 122 241 11799 CAPSM TANT 4 7uF 6 3V 20 4 00 C54 67 100 127 241 15206 CAPSM TANT 33uF 10V 20 2 00 C74 131 244 10423 CAP MYL 22uF 50V RAD 5 BOX 3 00 C168 172 175 245 09291 CAPSM CER 470pF 50V COG 5 1 00 C118 245 09869 CAPSM CER 001uF 50V Z5U 20 14 00 C34 38 58 69 76 81 C97 106 132 137 146 C147 151 152 245 09876 CAPSM CER 01uF 50V Z5U 20 4 00 C2 4 6 8 245 10562 CAPSM CER 150pF 50V COG 1096 9 00 C10 15 167 171 174 245 10587 CAPSM CER 18pF 50V COG 10 2 00 C140 141 245 10588 CAPSM CER 33pF 50V COG 10 4 00 C1 3 5 7 245 10973 CAPSM CER 22pF 50V COG 5 2 00 C159 160 245 10975 CAPSM CER 3300pF 50V X7R 10 1 00 C98 245 10976 CAPSM CER 47pF 50V COG 5 1 00 C19 245 11595 CAPSM CER 01uF 50V COG 5 2 00 C165 170 245 11645 CAPSM CER 47UF 50V Z5U 20 2 00 C23 25 245 12485 CAPSM CER 1uF 25V Z5U 20 72 00 C9 16 18 20 26 31 33 C35 37 40 43 44 C46 51 55 57 59 63 C64 66 68 72 80 82 C85 86 88 93 95 101 C104 105 109 117 C119 121 124 126 129 136 142 143 145 150 153 155 158 162 163 166
250. ELEC 2 2uF 50V 20 2 00 C82 121 240 16261 CAPSM ELEC 10uF 50V 20 3 00 C64 103 142 240 16262 CAPSM ELEC 4 7uF 16V NPOL 20 6 00 C161 162 165 166 C169 170 240 16263 CAPSM ELEC 33uF 16V NPOL 20 3 00 C41 80 119 244 16265 CAP MYL 0047uF 250V RAD 5 3 00 C68 107 146 244 16266 CAP MYL 01uF 250V RAD 5 6 00 C65 67 104 106 C143 145 7 10 DESCRIPTION QTY EFFECT INACT REFERENCE INFO 244 16267 CAP MYL 33uF 63V RAD 10 3 00 C66 105 144 245 10416 CAPSM CER 1000pF 50V COG 5 6 00 C179 184 245 10544 CAPSM CER 220pF 50V COG 5 12 00 C51 52 55 56 90 91 C94 95 129 130 C133 134 245 10561 CAPSM CER 100pF 50V COG 5 6 00 C163 164 167 168 C171 172 245 10973 CAPSM CER 22pF 50V COG 5 6 00 C40 42 79 81 118 120 245 16269 CAPSM CER 22pF 200V COG 5 15 00 C44 47 50 83 86 89 C122 125 128 245 16270 CAPSM CER 100pF 200V COG 5 6 00 C53 57 92 96 131 135 245 16293 CAPSM CER 1uF 50V X7R 10 37 00 C4 43 45 46 63 71 78 C84 85 102 110 117 C123 124 141 149 156 C327 328 245 16295 CAPSM CER 4700pF 50V COG 5 1 00 C148 245 16296 CAPSM CER 27pF 50V COG 10 3 00 C69 108 147 245 16297 CAPSM CER 47pF 50V COG 10 3 00 C54 93 132 245 16411 CAPSM CER 01uF 100V X7R 5 6 00 C59 60 98 99 137 138 245 16412 CAPSM CER 47uF 50V Z5U 5 3 00 C62 101 140 270 16272 COIL 1 5uH 5 RAD 375LS 3 00 L2 4 300 10509 DIODESM 1N914 SOT23 48 00 D16 24 27 29 32 D34 36 39 41 47 50 D52 55 57 62 64 D70 73 75 78 80 82 D85 87 97 99 104 300 16200 DIODESM ZENER 5 1
251. ERSION baa CHECKER AUTH N je 34 RWH CW 1 CHANGED DCR 021107 00 3 2 L REC DACOUT __ CBV MAG FB15 3 46 7dB 15 7 C8 8 C7 Ao P Yad 62 3 OdBFS 1 98Vrm y OdBFS 4 3Vrm 2 CHANGED PER DCR 030407 00 OW l 1 98Vrms N 4 3Vrms VEE GND 5 21 03 5 23 03 47 47 330 6 3 8213 8210 5 8 4 5 043 os Eod uds uis T Fes Y 8 CHANGED PER DCR 030729 00 Cw wd 3e 2 AN 9 29 03 10 7 03 1 25 1 25 1 25 68815 052 15V 5VD CBV MAG C2291 1 4 i BEG PAG 10 6 08 10 7 03 8200PF F y REC gt 9 D4 4395 5V i3 12 DG411 2 18 R212 R209 230 VDD 22 VA es AA i LEFT_REC_IN 6 5 v E 15 83 15 D4 3 17 3 1500 SIN A VEE GND 14 83 EC DAC RST 45 AOUTL 23 E Wwe 8 _ REC DACOUT 4 5 15 83 15 05 PEC DAC FS64 5 xcu 22 1 14 66 REC 15 C3 15 D5 EC DAC 125 OUT 6 SDATA pzrR 28 15V 15V 5VD 15 C3 15 C5 REC_DAC_FS 7 LRCK 27 15V 14 83 REG_DAG_LATCH 8 05 26 T A 13 12 olean ME P 4 52 MC33078 VDD cR BEDS CADO 5 Rd 316 33 LAE 14 1 R REC DACOUT 7 28 8 87 3i ty R219 16 8 24 6812 235 ADA SDATA OUT 11 21 236 1 1500 T Mess AD 4 D5 10 C7 11 C7 12 C
252. ESETA gt 3 88 CPUDATAS 8130 RESET gt CPUDATA4 13 4D 4012 1422 5915 EXPA RESET ENI 1760 gt 10 A8 EXPB RESET CPUDATAT 18 p IAMP_MAINS RLY RES 10 A6 7 83 RESET CLK 1 A3 CLR GND 021 5VD 74ACT244 E SPARES 2 18 AMP RESET FP RESET 12 88 836 D15 214 VIDEO RESET CPU TEST LED1 8 FPGA RESET 150 B 099 YEL 5VD 419 GND R35 D14 T CPU TEST LED2 74 244 27 150 20 11 9 NC EAS CPU TEST LED3 3 rs 15 va NC 150 lt HAM v GRN ma CPUTESTLEDS LED4 1 U45 150 lt Z 3 3VD YEL 74VHC273 CPU TEST LED5 R32 EN 20 lt bs 2 IAMP_SOET RLY 139 RD 7120 206 CPU TEST LED1 R31 D10 CPU TEST LED CPUDATAII opu CPU TEST LED2 CPUDATATS 450 5015 CPU TEST LED4 PS GRN CPUDATA14 1760 696 CPU TEST LEDS RESREGDECH 15 18 42 19 CPU TEST LED6 77 7 83 CLK 09 NC 1 GND CPU TEST LED 6 1 CPU TEST 20 27 020 CPU TEST LED2 3 1 43 BOOT_LOCK CPU TEST LED3 40 NO exicon 3 OAK PARK CPU TEST LED4 5 BEDFORD MA 01730 CPU TEST LEDS 60 EHE THLE CPU TEST LED6 7 DATE NS 510 DRAWN SCHEM MAIN BD RV8 99 4 26 02 BUFFERS LEVEL SHIFTERS m a CHECKED 4 30 02 SE CODE
253. ET FHS 2 0 sets the host interface mode for DSPAB to SPI serial mode by hardwiring these pins to a binary value of 101 UHS 2 0 performs the same function for DSPC and is hardwired to a binary value of 101 again selecting SPI serial mode 6 25 RV 8 Service Manual SPI Interface Signals CRY_SCS CRY_SPICLK CRY_RXD CHY TXD CRY_INTREQ DSPASPICLK DSPARXD DSPATXD CRY FCS CRY FINTREQ HINBSY During the boot phase of RV 8 algorithm code is loaded into the format FLASH and then into the on board SRAM All external memory is accessed through DSPC via its SPI port As demonstrated with the SHARC devices the two SPI ports for DSPAB and DSPC are shared with each one selected by independent chip select signals Host instructions to DSPC are transmitted from the FPGA via CRY RXD Status from DSPC is transmitted back to the FPGA Host via CRY TXD Data on both ports is synchronous with CRY SPICLK All transfers to and from DSPC take place when CRY SCS is asserted low DSPC only serves to interface to external memory The available post processing of audio data is not utilized in this application CRY_INTREQ is an open drain output that is asserted low when DSPC has control data that requires host CPU attention This signal is pulled up to 2 5V via a section of RP10 DSPAB implements the following audio algorithms e Dolby Digital EXTM e Dolby Pro Logic e DTS ES 96 24TM e DTS 96 24TM DTS ES e Discrete 6 1TM
254. EV 0 PC BOARD Power Supply Board Subssembly 022 16443 PL ASSY BRIDGE RECT RV8 1 00 D26 202 09794 RESSM RO 0 OHM 0805 1 00 R238 202 16233 RES CF 5 2W 27K OHM VERT 10 00 R2 11 203 11980 RESSM THIN 1 1 10W 10 0K OHM 8 00 R207 210 215 218 220 R223 225 203 13134 RESSM THIN 1 1 10W 1 00K OHM 3 00 R221 227 228 7 17 DESCRIPTION QTY EFFECT INACT REFERENCE INFO 203 14566 RESSM THIN 1 1 10W 20 0K OHM 4 00 R211 213 214 216 203 16235 RESSM THIN 1 1 10W 100 OHM 2 00 R222 226 203 16238 RESSM THIN 1 1 10W 14 7K OHM 1 00 R212 203 16246 RESSM THIN 1 1 10W 6 19K OHM 2 00 R217 219 203 16247 RESSM THIN 1 1 10W 61 9K OHM 2 00 R208 209 240 16258 CAP ELEC 5600uF 35V SNAP 20 2 00 C81 82 240 16259 CAP ELEC 27000uF 80V SNAP 20 4 00 C40 77 78 79 240 16264 CAPSM ELEC 10uF 50V NPOL 20 1 00 C70 244 16268 CAP MYL 1uF 250V X2 RAD 2096 1 00 C80 245 16292 CAPSM CER 01uF 50V X7R 10 2 00 C65 66 245 16293 CAPSM CER 1uF 50V X7R 10 6 00 C67 69 71 75 83 245 16410 CAPSM CER 33uF 50V X7R 5 2 00 C74 76 300 10509 DIODESM 1N914 SOT23 4 00 D22 25 3800 16204 DIODESM RECT 100V 3A 20NS SMC 4 00 D27 30 310 10566 TRANSISTORSM 2N4401 SOT23 3 00 Q23 25 340 11045 ICSM LIN LM393 DUAL COMP SOIC 1 00 U42 340 16216 ICSM LIN 7815 15V REG D2PAK 1 00 U1 340 16217 ICSM LIN 7915 15V REG D2PAK 1 00 U2 340 16218 ICSM LIN LM324 4OPAMP SOIC 1 00 U41 410 16220 RELAY 1PNO 5V SEALED 1 00 K3 410 16221 RELAY 1PNO 24V SEALED 1 00 K2 480 16224 THE
255. FAN DRV This voltage will vary between 3V and 11V The environment fans are driven from the 15V supply with this control voltage present on the other side of the fan windings Therefore the fans will run on voltages from 4V to 12V dependent upon the duty cycle of FAN Connectors J21 J23 J24 and J32 are connected in parallel so that all four fans are controlled by the same signal L3 is a provision to keep brush noise from the fan from getting into the 15V supply It has been determined that this protection is unnecessary and so it is not installed R182 R186 Provide a total resistance between 15V and the fans of approximately 10 Ohms capable of dissipating 1 25W This resistance suffices to suppress back EMF from the fans C177 provides local bulk capacitance for the circuit 6 46 Lexicon IR Remote Connector Sheet 18 This page contains the IR detector input for ZONE 2 ZONE 2 Remote Input Remote control of the RV 8 is made possible via an infra red detector behind the front panel lens Control from the Main Zone is made by pointing the remote at the front panel and activating functionality on the remote control surface panel Remote control for a second zone is made possible by connecting an IR detector to J5 When commands from the remote strobe this external detector the resultant signal is passed along to an infra red LED located in close proximity to the main zone detector This LED is also located behind the front panel le
256. G FRONT DI LG FRONT PHONO IN TO ANLG FRONT DI R OUT GAIN R OUT FREQ lt 10 gt 500 LG FRONT PHONO IN TO ANLG FRONT DI FRONT PHONO TO FRONT DIR OUT XTALK LG FRONT PHONO IN TO ANLG FRONT DIR OUT SNR R OUT THD 20 16 00 mVrms 16 00 mVrms 20 50 50 20 RIAA PRE 20 20 20k RIAA PRE 20 4 70 mVrms 4 70 mVrms 16 00 mVrms 16 00 mVrms RIAA PRE 20 OFF 0 00 100k 100 gt 22 None 1 13 11 23 Interna 1 13 11 23 Interna Leve gt 80 00 70 00 150 00 lt 10 gt 22k None 23 Internal Leve gt 76 00 72 00 140 00 100k 100 gt 500k 23 Internal FRONT IN3 TO FRONT HEADPHONE OUT FRONT IN3 FRONT HEADPHONE OUT XTALK 4 00 Vrms 4 00 Vrms 5k FRONT IN3 TO FRONT HEADPHONE OUT GAIN FRONT IN3 TO FRONT HEADPHONE OUT FREQ FRONT IN3 TO FRONT HEADPHONE OUT THD 4 00 Vrms 4 00 Vrms 97 2 2 00 Vrms 0 20 20 20k 20k 40k 3 3 80 Vrms 0 40 THD N lt 005 09 00005 600 lt 10 gt 500k AOkHz LP 11 23 oat dB Level gt 73 00 70 00 150 00 600 lt 10 gt 22k 11 23 15 Internal LG ZONE2 TO ANLG ZONE2 HEADPHONE OUT FREQ 2 00 Vrms 10 20 20 20k 20k 40k 600 lt 10 gt 500k None level ____ 4 36 460 600 lt 10 gt 600 None 11 23 13 Interna Analog LG ZONE2 IN1 TO ANLG ZONE2 H
257. G ZONE2 DIR VAR OUT GAIN na ANLG ZONE2 IN1 TO ANLG ZONE2 DIR VAR OUT FREQ 2 00 Vrms 2 00 Vrms 0 20k 20k 40k None 20 0 25 0 75 lt 10 gt 600 _7 A 1 13 j ma Anaog LG ZONE2 IN1 ANLG ZONE2 DIR VAR OUT THD 1 3 80 Vrms 3 80 Vrms 20 1k 5 40k None 20 Float THD N lt 003 005 00005 100k lt 10 gt 22 None 7 19 1 13 Interna n a LG ZONE2 IN1 TO ANLG ZONE2 DIR VAR OUT XTALK 1 4 00 Vrms 4 00 Vrms 15k Unb Float dB Level gt 85 00 75 00 0 00 k lt 10 gt 22 None 7 19 1 13 Interna n a LG ZONE2 IN1 20 2 VAR OUT SNR OFF OFF Leve 2110 00 105 00 Analog i 3 4 00 Vrms 4 00 Vrms 9 z 5 LG_ZONE2_IN1_TO_ANLG ZONE2 DIR VAR OUT VC ene 150 i080 100100 LG ZONEZ IN1 TO ANLG ZONEZ DIR VAR OUT RELAY MUTE IE F 5 one 007 00 internal E eer J ene 20 Lever 380 90 Analog ANLG ZONEZ INT TO LG ZONE2 TO ANLG ZONE2 DIR OUT RELAY MUTE up 21 U PERIERE p rer 12 OR ENTIER 70mVrms 4 70 mVrms None 20 220 6 00 mVrms 16 00 mVrms RIAA PRE 1 50 0 50 70mVrms 4 70 mVrms _ 20 20 RIAA PRE 001 6 00 mVrms 16 00 mVrms RIAA PRE 20 150 00 70mVrms 4 70 mVrms None 20 140 00 M jJ re j J 00
258. H PH BZ TRI 20 00 RCA CONN TO R PNL ALIGN HOLES W CONNS BEFORE TORQUING SCREWS 643 10492 NUT M4X 7MM KEP ZN 1 00 CHASSIS GND 644 01741 WSHR INT STAR 8 ZN 4 00 REAR HANDLES 644 01747 WSHR INT STAR 4 ZN 4 00 DSUB JSCKT 644 10494 WSHR FL M4CLX9ODX 8MM THK 1 00 CHASSIS GND 680 15630 WIRE 14G G Y 3 5 187QDCRA LUG8 1 00 AC IN TO CHASSIS GND 680 15631 CABLE FFC 4CX1 25MM 15 L COS 1 00 HEADPHONE TO ANLG BD 680 15632 CABLE FFC 13CX1 25MM 15 L COS 1 00 TUNER TO ANLG BD 680 15633 CABLE FFC 16CX1 25MM 10 L COS 1 00 VIDEO BD TO MAIN BD 680 15634 CABLE FFC 16CX1 25MM 14 L COS 1 00 PHONO PREAMP TO ANLG 680 15636 CABLE FFC 40CX1 25MM 6 L COS 1 00 ANLG BD TO MAIN BD 680 15637 CABLE FFC 40CX1 25MM 12 L COS 1 00 FP TO MAIN BD 680 15639 CABLE FFC 14CX1 25MM 4 L COS 1 00 4CH AMP TO MAIN BD 680 15640 CABLE FFC 6CX1 25MM 4 L COS 3 00 AMPS ANLG BD 2 CROWN PS TO MN BD 1 680 15641 CABLE FFC 6CX1 25MM 6 L COS 1 00 AMP TO ANLG BD 680 15641 CABLE FFC 6CX1 25MM 6 L COS 1 00 4CH AMP TO ANLG BD 680 15642 CABLE HSGX2 10C 4CX3 16 5 1 00 PS TO MAIN ANLG amp VIDEO BDs 680 15643 CABLE HSG QDC 18 14AWG 22 5 1 00 PWR SW TO PWR SUP 680 15697 CABLE PWR 187RA 250QDC SLV 7 5 1 00 AC CONN TO PWR SW 680 15698 CABLE HSG HSG 16G 6C 12 2 00 3 amp 4CH AMPS TO PS 680 16122 CABLE FFC 14CX1 25MM 4 L FOLD 1 00 AMP TO MAIN BD 700 15809 COVER 4U RV8 1 00 700 15810 CHASSIS LEFT RV8 1 00 700 1581 1 CHASSIS RIGHT RV8 1 00 700 15812 PLATE CENTER CHASSIS RV8 1 00
259. IN_FS64 5 AOUTL 22 2 7 ish 1 815 15 C3 15 D5 125 OUTT 6 SDATA pzrR 28 Le GND 18 029 4 A4 5 A4 6 A4 11 C7 12 C7 13 C7 15 C3 15 C5 MAIN FS 7 RCK capi 27 R156 asy PIA 4 5 __ MAIN DAC LATCH 0 26 NC 1 50K 57 6K 14 83 DAC I tS DZFL beo R155 14 9 capo pis 25 AK 1 4 D5 5 D5 6 D4 7 B7 8 B6 9 B6 1 1 C7 12 C7 13 C7 14 B5 15 C5 ADA_SCLK 10 2 11 03 12 04 14 07 14 3 MAIN DACOUT SDATA OUT 11 21 121041407 MAIN_DIRECT_SEL 4 D5 8 C7 11 C7 12 C7 13 C7 14 B5 15 A5 15 C5 CDTI AOUTR 11 C5 12 C5 14 D6 12 pio AOUTR 20 1 259 13 19 C307 R234 C25 R198 DIF1 AGND lm VAL g NESS32A 15V 5VD pire VREFL 16 47 118 33063 R199 681 6 bd 4 15 2 145K 5 C217 L U48 13 12 DGND BGND C306 C260 1 1200 4 ADG451 8200PF VCC VDD U62 1 25 45V 14g p 15 DACOUT __ 10 A7 v R235 C261 8197 C216 16 A a 1 GND 330 6 3 5 029 N Rigs 22 15V 1 21K 15V 1 iu YD 8 13 12 ADG451 4 C2 4 A8 RIGHT_MAIN_IN_LVL 5 MC33078 VCC VDD 6 T 9 9 D OIN C168 GND 029 8159 8157 18PF VE 1 50K 57 6K aay 1 R158 1 15V AA C370 1 499K 200 298 299 FRONT __ L _ 899 Sm R98 L_FRONT_HDP C228 2 21K 10 02 thee I mc A 16 88
260. J15 may be used as an In Circuit Programming port that will directly configure the FPGA bypassing the EPROM Typically during development the EPROM is socketed for easy removal and insertion and the EPROM is programmed in a standard PROM programmer Audio Reference Clock U35 AUDIO OSC is a reference signal that is used by the PLL phase comparators within the AVRX device It is used as a reference when no sample clock is derived from the S PDIF inputs 035 is a standard Unbuffered Hex Inverter of which one stage is configured as a Colpitts Oscillator comprised of Y1 R145 C140 and C141 This circuit generates a 14 112MHz square wave R145 provides hysteresis for the gate initiating and sustaining a reliable switching characteristic while C140 and C141 provide the proper AC load to the reactive element of Y1 The second stage of this circuit is another gate from the hex package that simply buffers the output of the oscillator presenting a minimal load to it while providing drive capability R147 provides source impedance matching to the characteristic impedance of the PCB 6 39 RV 8 Service Manual FB15 provides a cleaner 3 3V supply to the oscillator minimizing contamination of the output clock signal by the switching characteristics of other devices connected to the 3 3VD plane C142 is a standard high frequency de coupling capacitor for U35 Expansion Slot Connectors J25 J30 J25 and J30 are connectors that will provide system in
261. K CK 40 LED ROW10 33 Ma 16 LED10 R18 Q3 NC 41 LED ROW11 32 NC 0415 LROW11 S LED ROWIS SA 680 2N4403 Ne 0417 LROW12 220 NC One 9 LED COLUMNO U1 LEDcOLE 4 D8 NC LOLO 50 LED COLUMNI ABT16244 4 D8 NC ds 52 LED COLUMN AT C Ea LED12 4 D8 NC 025 A2 2120 NC 53 27 22 5 WE woim iw NC 97 SWITCHCOL 0 AX 037 SWCOLO Sweor 1 SWITCHCOL 1 NC ois SWGOLS SWITCHCOL 2 U1 0317 NC 0318 swRowo 20 SROw 0 ne 0310 SWROW1 Ne 0312 SWROW2 0313 SWROWS SWROWA C4 BESE 9 hEsETNGsSR SWROWS SWROWG NG 0316 SWROW7 SWITCHCOL 2 0 NC O41 SWROWS 3 D8 JTAG PROGRAMMING PORT NC 67 949 SWROWS 3 3VD NG g 1042 SWROW10 NS 045 SWROW11 048 SWROW12 NC 043 SWROW13 NC 044 SWROW14 0411 SWROW15 1 85 3 87 RED VCC BLK GND TDO NC4 YEL TCK JTAGSTON TCK NC5 TDO JTAG TE NG WHT TDI Ng nei 888388858 GRN TMS 0 0 5 0 50505 834 4JK CONTRACT n 3 OAK PARK NO eXICO BEDFORD MA 01730 APPROVALS DATE sCHEM SW LED BD RV8 DRAWN 7 10 02 FRONT PANEL CPLD CHECKED CAM 7 8 02 SIZE CODE NUMBER REV Q C ISSUED 060 15569 2 7 10 02 TENANE MAG 7 8 02 15569 3 2 SHEET 2 4 UJ 112 0 2003 17 07
262. LL_PUMP_DN A 158 7 2 PLL2 DOWN FAST 16 88 2160 RP23 7 2 47 DEC OUT FSI gt Lupo NO exicon 3 OAK PARK 207 5 58 RP217 2 47 DEC OUT SCKI gt BEDFORD 01730 8156 GND RP19 7 2 47 DEC TITUE 4 7K Lola of st 00 0 o 041 8 83 APPROVALS DATE 1 FPGA TDI hz c e o o o s uo DBAWN YE 5 BD RV8 e 2 FPGA TDO NC 26 0 MAIN FPGA 5 FPGA TMS i NC CHECKED 4 30 02 SIZE CODE NUMBER REV oj4 FPGA ac CW san E 060 15559 3 J19 ISSUED FILE NAME JV 4 30 02 15559 6 9 SHEET 9 19 8 7 6 5 3 2 1 8 7 6 5 4 3 2 1 REVISIONS REV DESCRIPTION DRAFTER Qc FPGA FLASH PROM for development only CHECKER AUTH RWH
263. N egi R2 C32 16 In 8 2 5 1072 R52 GND 15 45VD NC od 100 D2 AA mc RCA 10 25 2 4 5 09 ih U1 Y 13 12 CONTRACT z L 16 R51 4 00411 NO le xicon 3 OAK PARK 150PF 100K j 15V T er BEDFORD MA 01730 15V 9 IN APPROVALS E i VEE GND SCHEM ANALOG I O BD RV8 1 A5 14 C3 ANLG_ 4 5 SEL DRAWN 8 27 02 ANLG 7 8 DIR SEU 4 s 09 RIGHT ANALOG INPUT MUXES 1 5 14 23 L CHECKED 8 28 02 SIZE CODE NUMBER REV y B 060 15579 3 15V CW 8 29 02 ISSUED 8 29 02 15579 6 2 nex 2 OF 17 8 7 5 4 3 2 1 10 7 2003 11 05 8 7 6 5 4 3 2 1 REVISIONS 15V 15 5VD DRAFTER QC i ih pa CHECKER AUTH i W R368 ae 13 12 1 CHANGED PER DCR 021107 00 S 13 0d 15 83 A M 33078 LEFT_PHONO_IN VDD CBV MAG T 402K 2 3 s pi LEFT MAIN IN 1 03 4 081 11 20 02 1 S 1 24 02 087 GIN 2 CHANGED PER DCR 030407 00 i 1 4 GND 15V 5VD 32 03 Eus JL 5 23 03 5 23 03 5560 m 15 1867 478 RWH CW 9 15 83 e 13 12 3 CHANGED PER DCR 030729 00 4 02K 4 02K 00411 9 29 03 10 7 03 1 1 15V vec
264. N QTY EFFECT INACT REFERENCE INFO 340 12119 ICSM LIN TL7705 5V MON SOIC 1 00 U31 340 13137 IC LINEAR LM2941CT ADJ TO 220 2 00 U8 9 340 13883 ICSM LIN LM2937 2 5V REG TO263 1 00 U12 340 14535 IC LIN 1585A 3 3V REG TO220 1 00 038 340 15088 ICSM LIN LM1117 ADJ 800mA SOT 2 00 U22 39 345 13140 ICSM INTER RS232 XCVR 5V SOIC 1 00 U5 350 13879 ICSM SDRAM 512KX32X4 3 3V TSOP 2 00 U6 27 350 15096 ICSM FPGA XC2S200 6 28X42 PQFP 1 00 U41 350 15209 ICSM DRAM 1MX16 60NS SOJ 1 00 042 350 15249 ICSM GAL 16V8 RV8 V1 00 1 00 U44 350 15491 ICSM FLASH 512KX8 3V 200NS TSO 1 00 U19 350 16195 ICSM FLASH 16M RV8 MAIN V1 03 1 00 U26 365 15490 ICSM uPROC DSP CS49400 LQFP 1 00 U25 365 15660 ICSM uPROC ADSP21161 32BIT BGA 2 00 U16 34 365 15661 ICSM uPROC SH7014 28 7MHz QFP 1 00 U33 390 12076 CRYSTAL OSCSM 12 288MHz 1 00 U30 390 12458 CRYSTALSM 12 500MHz PAR HC49 1 00 Y2 390 13832 CRYSTALSM 14 112MHz PAR HC49 1 00 Y1 430 10419 LEDSM INNER LENS RED 6 00 D11 14 25 26 31 32 430 10420 LEDSM INNER LENS YEL 7 00 D12 15 27 28 D33 34 46 430 10421 LEDSM INNER LENS GRN 6 00 D10 13 29 30 35 36 510 10595 PHONE JACK 3 5MM PCRA 3C STER 1 00 J5 510 10745 CONN POST 100X025 HDR 2MC POL 4 00 J21 23 24 32 510 12319 CONN D SUB 9FCX2 STACKED PCRA 1 00 J4 510 13146 CONN HDR 200 4MC PCRA 1 00 TRIGGERS J3 510 13147 CONN RCA PCRA 1FCG YEL GND 1 00 J7 510 13148 CONN RCA PCRA 1FCGX2V BLK GND 2 00 J1 2 510 13538 CONN RCA PCRA 1FCG BLK GND 1 00 J8 510 13840 CONN O
265. N1 is a signal from the front panel remote control infra red detector The data from this detector is a serial bit stream that represents commands that change operative modes of the RV8 When a low to high transition has been detected from the IR receiver the internal state machine checks to make sure the incoming signal is a valid command stream by checking the period of the low to high and high to low transitions If it is not then the state machine waits for another low to high transition in the detector stream If the incoming stream is a valid command stream then the data extracted is compared to a look up table of valid code values This value is then stored in a RAM buffer that is polled by the host CPU FP SDATA is part of a four wire interface that controls the front panel LED display and pushbutton matrix This signal is a return stream of data reporting front panel button status to the host CPU Changes in button status are serially transmitted to the AVRX FPGA where current status is XOR ed with the previous status of the last scan A retriggerable timer is armed whenever the XOR gate is activated indicating a change in any of the buttons This timer sends a host interrupt after button activity has stabilized for three milliseconds This three millisecond period filters any switch bounce SDATA OUT is the transmitting stream from the main board to the front panel that controls the LED illumination that is part of the user interfac
266. NPUT SETUP menu Scroll down through the DVD1 menu options and highlight ANALOG IN Press the Menu arrow to enter DVD1 ANALOG IN 6 Scroll through the DVD1 ANALOG IN input options and highlight ANALOG 1 Press the Menu arrow to assign the input to DVD1 Press the Menu lt arrow once to return to the DVD1 INPUT SETUP menu Scroll down through the menu and highlight ZONE2 IN Press the Menu arrow to select the ZONE2 IN parameter 9 Press the Menu arrows until ANLG is listed 10 Press the Menu arrow once to confirm 11 Analog should now be selected as the Zone 2 source 12 Press the Menu arrow four times to exit the setup menus 13 Connect the oscillator output to the left and right audio inputs labeled 1 on the RV 8 rear panel 14 Confirm DVD 1 is selected in the Main Zone as well as the Zone 2 section of the front panel 15 Slowly increase the volume on the amplifier to a comfortable listening level for the speakers 16 Sweep the oscillator from 20Hz to 20kHz 17 Verify that you hear clean clear audio coming from the speakers 4 8 Lexicon 18 19 20 Power down the amplifier and move the cables from RCA left and right outputs from Fix to Var in Zone 2 Repeat the procedure above to test the Zone 2 variable output Once complete repeat steps 1 19 to test Analog Inputs 2 through 8 Change the DVD1 ANALOG IN selected in step 6 to the next appropriate input Analog Inputs to Zone 3 Outp
267. NUMBER REV S cw 5 1 02 060 15559 3 ISSUED FILE NAME s JV 4 30 02 15559 6 2 SHEET 2 or 19 S 2 1 8 5 4 3 2 1 REVISIONS 13 1 CLK12500C__ REV DESCRIPTION DRAFTER QC Y2 SUP AC CHECKER AUTH 1 CHANGED PER DCR 020913 00 EH ow 047 Ries 11 05 02 12 20 02 12 500MHZ 41 Poll CLK125008 amp CAM MAG 1 5 11 06 02 12 20 02 43 3VD 2 CHANGED PER DCR 030307 00 Dua pecus 1 3M 4 5 14 03 5 20 03 45VD S RWH ECM 857 3 CHANGED PER DCR 030626 00 leases ABT16244 10 2 03
268. N_96K_TO_ANLC_ZONE2 FIX OUT FREA frooasrs __ 1 5 102042 408 None paors fook 40 0 8 na f ma Exema 96000 Dg 5 ZONE2 COAX1 IN 96K ANLG ZONE2 FIX OUT THD 12 00dBFS 12 00 dBFS 207 1k 1k 40k None THD N lt 0025 004 005 010 0002 10 22k None 6 18 Externa 96000 Digital DIG ZONE2 COAX1 IN 96K TO ANLG ZONE2 FIX OUT DYNRNG 60 00 dBFS 60 00 dBFS dBr THD N gt 112 00 105 00 1000 00 lt 10 22k None 6 External 96000 FIC QUE EIN i tcs oL ZONE2 1 IN 48K TO ANLG ZONE2 FIX OUT 1 jhooodeFS 004 97 None Vrms Leve ____ 420 jh45 js50 100 lt 10 gt 60 None 6 18 ma mwa Exema 48000 DIG ZONE2 COAX IN 48K ANLG ZONE2 1 f 1200dBrS 200dBFS 97 THD N 02 05 02 lt 10 2 6 48 na Exema 48000 ZONE2 1 IN 48K TO ANLG ZONE2 FIX OUT DYNRNG feooodBrs 60 00 97 THD N 11200 ___ 105 00 ______ 1000 00 00 40 2 None 6 48 ma mwa 96000 DIG ZONE2 1 44 TO ANLG ZONE2 FIX OUT j E r Mur ZONE2 1 IN 44K TO ANLG ZONE2 1 hooodeFS 0 0 5 97 lt 10 gt 600 Noe 6 18 ma E
269. Negative Heatsink Assembly 100 01759 CHEM HEATSINK COMP SILICONE 0 003 oz 310 16277 TRANSISTOR MJ21193 PNP TO3 4 00 630 16421 INSUL SIL RUB 94X 66 2 00 641 16289 SCRW TAP 6 32X 25 PNH TORX ZN 8 00 704 16432 HEATSINK AMP DBL RV8 1 00 Mounting Bracket Assembly Option 630 08670 WSHR FIN 10 NYL BLK 4 00 640 08671 SCRW 10 32X3 4 FH PH BLK 4 00 640 14680 SCRW M4X14MM FH SCKT SS 4 00 701 15813 BRACKET MTG RACK 4U RV8 2 00 Power Cord Options 680 15223 CORD POWER IEC 15A 14G 2M NA 1 00 680 15217 CORD POWER IEC 10A 1MM 2M EURO 1 00 Europe 680 15202 CORD POWER IEC 10A 1MM 2M UK 1 00 United Kingdom Packaging Miscellaneous 070 15838 GUIDE USER RV8 1 00 070 1601 1 NOTES RELEASE RV8 1 00 7 22 DESCRIPTION QTY EFFECT INACT REFERENCE INFO 460 08452 BAT ALK AAA 4 00 480 15840 ANTENNA AM LOOP 75X168MM 1 00 480 15841 ANTENNA FM F 1 5M L 1 00 480 15842 ANTENNA FM PAL 1 5M L 1 00 560 16125 ADPTR RF CONN F MALE gt PAL MALE 1 00 730 15818 BOX 26 75X23 375X15 25 BLANK 1 00 OUTER BOX 730 15819 BOX 25 875X22 5X14 LEXICON 1 00 INNER BOX 730 15821 INSERT FOAM BASE 4UX19 1 00 730 15822 INSERT FOAM TOP 4UX19 1 00 730 15823 BOX 18 75X12 625X2 5 1 00 730 15829 TRAY ACCESSORY RV8 1 00 7 23 STET INSTALL COVER 700 14839 ONIO HOUSING 1 SOLDER BD 55 TO HOUSING 700 14838 AT TAB LEXICON INC EP o SOLDER SEAM BETWEEN COVER amp HOUSING TYPICAL
270. OHM 9 00 R112 310 311 318 319 R326 327 334 335 203 10838 RESSM RO 1 1 10W 68 1 OHM 26 00 R162 163 167 168 172 7 6 R173 177 178 182 183 R187 188 192 193 197 DESCRIPTION QTY EFFECT INACT REFERENCE INFO R198 306 309 393 396 R408 409 203 10896 RESSM RO 1 1 10W 1 00K OHM 24 00 R116 118 124 125 127 R128 130 131 133 134 R236 237 239 241 243 R245 247 249 253 255 R257 259 203 11078 RESSM RO 1 1 10W 422 OHM 9 00 R110 202 203 296 298 R300 403 416 418 203 11697 RESSM RO 1 1 10W 909 OHM 2 00 R248 251 203 11726 RESSM RO 1 1 10W 301 OHM 2 00 R303 401 203 11734 RESSM RO 1 1 10W 4 32K OHM 8 00 R137 140 143 146 149 R152 155 158 203 11993 RESSM RO 1 1 10W 357 OHM 1 00 R304 203 11995 RESSM RO 1 1 10W 2 55K OHM 2 00 R305 400 203 12371 RESSM THIN 1 1 10W 2 74K OHM 9 00 R206 207 294 295 R397 399 421 422 203 12476 RESSM RO 1 1 10W 4 02K OHM 42 00 R84 91 115 119 R358 389 203 12481 RESSM RO 1 1 10W 1 50K OHM 8 00 R138 141 144 147 R150 153 156 159 203 12719 RESSM THIN 1 1 10W 2 00K OHM 16 00 R312 313 315 316 R320 321 323 324 R328 329 331 332 R336 337 339 340 203 12723 RESSM THIN 1 1 10W 102 OHM 1 00 R302 203 12799 RESSM RO 1 1 10W 825 OHM 16 00 R34 35 38 39 42 43 R46 47 92 97 99 100 203 12969 RESSM THIN 1 1 10W 316 OHM 20 00 R212 215 220 235 203 13133 RESSM THIN 1 1 10W 1 15K OHM 8 00 R164 169 174 179 R184 189 194 199 203 13537 RESSM THIN 1 1 10W 5 62K OHM 8 00 R262 265 266 269 R270 273 274 277 203 1363
271. ON 2003 HSG A CONTRACT 7 NO exico n 3 OAK PARK BEDFORD MA 01730 TITLE APPROVALS DATE SCHEM SW LED BD RV8 DRAWN RWH 7 10 02 FRONT PANEL CONNECTORS CHECKED 7 8 02 SEE CODE NUMBER REV 060 15569 3 7 10 02 8 ISSUED 7 8 02 15569 3 1 sHEET 1 o 4 N 8 7 6 5 4 3 2 1 8 6 3 2 1 REVISIONS DESCRIPTION DRAFTER CHECKER _ AUTH CW RWH CHANGED PER DCR 021028 00 160 11 5 02 11 6 02 RWH CW 2 ADDED JTAG RES PER DCR 030821 00 Basa KB 9 23 03 9 26 03 LED 12 0 4 87 3 3VD ABT16244 2 LEDO 5VD Ae LEDT T 5 LED2 6 LED3 lt lt 1 mca FP I 7 6 222 8888 SDATA OUT Rai 555 U1 I 1 4 SPATO 699 59999 ABT16244 NC edi LROWO 27 LED ROWO LED4 28 ROW LEDS EA 1 04 LTCH eh LROW2 29 TED ROW2 LED6 Q1 XC9572XL LRows 30 LED ROW3 as Ya mE 680 2N4403 NC 0412 LROW4 32 ROWA NC 0413 LROW5 D ROWS R16 gt NC Ut 02 0416 LROW6 NC ABT16244 021 37 LED ROW8 3f v3 LED8 680 NS 2N4403 FP SDATA CLK 39 LED_ROWS 35 14 LEDS gt gt gt 5555 gt gt 5555 5 5 5 55 5 555 5 1 04 SDATCE
272. ONE ANLG SEL2 See SBI 0 3 38 ZONE ANLG See see 3 35 ZONE SEU O 24 3 3 A5 9 C4 14 63 ZONE DACOUT SEU 56 ZONE DIRECT SEU 025 36 ZONE TUNER SEU Es 74VHC04 O 2 6 35 ZONE SEL 15 A8 0 27 15 A8 40 HEADP FRONT SEL m LIE HEADP REC SEL pm e e 42 2 SEU 32 49 ANLG 4 5 DIR SEU O 33 1 A5 2 A5 13 C5 14 83 REAR_DACOUT_SEL 1 10 REAR DIRECT SEU 13 65 O 34 50 ANLG 7 8 SEU SD ARES 74VHC04 O 35 ADS 7 C8 er eS SIDE SEU SN 0 36 MAIN 37 10 A6 11 A6 12 A7 13 A6 40 53 ee a 10 C4 11 D3 12 D4 14 D7 ZONE DACOUT SEU a Belen SPARES 614 58 MAIN RLY O 760 HEADP RLY Wa 6 REAR_DACOUT_SEL teeter REC AD SEL CS 0 74 7 65 MAIN DAC RST H0 D7 11 D7 12 D7 13 D7 522 3 3VD 65 REC DAC RST 80 66 ZONE MUTE RLY er 67 MAIN 0 d 0 52 MAIN 1 en 053 5 3170 MAIN LATCH 2 13 12 NC 8122 O 54 12 C7 lt d G8 71 MAIN LATCH 3 ace LATCH E 14 05 5 05 6 04 7 87 8 86 9 86 10 7 11 07 12 07 13 07 15105 ADA SEATA OUT 22 o 57 4 52 4 D8 8 C7 10 C7 11 C7 12 C7 13 C7 15 A5 15 C5 23 luo GCK T jene 15 05 SEU 7 GCK3 o 60 E UC ZGEN 4 C5 5 C5 6 C4 7 A7 8 B7 9 C7 9 B7 4 D5 5 D
273. ONE3 DIR VAR OUT SNR LG ZONE3 5 ANLG ZONE3 DIR VAR OUT LG 7 IN5 TO ANLG 2 DIR VAR OUT GAIN LG ZONE3 5 TO ZONE3 DIR VAR OUT FREQ LG ZONE3 5 ANLG ZONE3 DIR VAR OUT X LG ZONE3 5 TO ZONE3 DIR VAR OUT S LG 7 IN6 TO ZONE3 DIR VAR OUT GAIN ZONE3 IN7 ANLG ZONE3 DIR VAR OUT LG 7 IN7 ANLG ZONE3 DIR VAR OUT GAIN ZONE3 IN7 TO ZONE3 DIR VAR OUT FREQ LG 2 IN7 TO ZONE3 DIR VAR OUT LG 2 IN7 TO ZONE3 DIR VAR OUT XTALK LG 2 7 TO ZONE3 DIR VAR OUT SNR LG ZONE3 IN8 TO ANLG ZONE3 DIR VAR OUT LG ZONE3 IN8 TO ANLG 2 DIR VAR OUT GAIN LG ZONE3 8 TO ZONE3 DIR VAR OUT FREQ LG 2 IN8 TO ZONE3 DIR VAR OUT LG ZONE3 8 TO ZONE3 DIR VAR OUT XTALK NIN 5 7 B 4 00 Vrms 4 00 Vrms Vrms 3 40 lt 10 gt 500k None 16 Interna 2 00 Vrms 2 00 Vrms 10 20k 20k 40k Float dBr Leve 0 10 0 10 100k _ lt 10 gt 500k 16 Interna 3 80 Vrms 3 80 Vrms 20 1k 5 40k Float THD N lt 003 005 00k lt 10 gt 22 None 5 Interna 4 00 Vrms 4 00 Vrms 15k Leve gt 95 00 75 00 Ok lt 10 gt 22 None 5 17 Interna OFF OFF 997 dBr Leve 110 00 105 00 00k 10 gt 22k None 5 16 Interna 7 7 7 N e N a o e e a ae ale 3 THD N lt 003 4 00 Vrms 15k Unbal Level gt 9
274. ONENTS MARKED WITH NOT INSTALLED 15V 15V Notation CVID composite video SVID s video PVID component video COMPOSITE VIDEOTNPUTS COMPOSITE VIDEO OUTPUTS VIDEO INPUT BOARD CONNECTOR C130 C131 C133 CVIDS s 2 D8 3 D8 4 D8 CVID4 s 12 08 3 08 4 08 2 D8 3 D8 4 D8 CVID2 2134 2 D8 3 D8 4 D8 CVID1 R223 2 R222 2 R221 2 R220 2 R219 470K 470K 470K 470K 470K 2 D8 3 D8 4 D8 VIDEO OUTPUT BOARD CONNECTOR 1 CVID REC2 2 gt 3 43 5 4 g CVID_REC1 5 3 7 9 2 A3 we CVID MAIN2 10 1 11 12 CVID MAIN1 13 2 83 i J16 57 DOCUMENT CONTROL BLOCK 060 15589 SHEET REVISION TITLE 10 3 S VIDEO IN COMPOSITE IN OUT 2 OF 10 3 MAIN 3 OF 10 3 ZONE2 4 OF 10 3 ZONE3 10 3 VIDEO CONVERSION 6 OF 10 3 COMPONENT VIDEO 7 OF 10 3 ON SCREEN DISPLAY 8 OF 10 3 SYNC STRIPPER 9 OF 10 3 CPLD CONTROL REGISTERS PLL 10 OF 10 3 INTERFACE CONNS 2003 HSG CONTRACT z NO exICOn 3 OAK PARK BEDFORD MA 01730 TITLE APPROVALS DATE SCHEM VIDEO BD RV8 DRAWN RWH 8 9 02 S VIDEO IN COMPOSITE IN OUT CHECKED ECM 8 28 02 SIZE CODE NUMBER REV QC 060 15589 3 cw 8 2802 rENAME ISSUED MAG 8 28 02 15589 3 1 sHEET 1 10 2 1 D gt 10 16 2003_16 26
275. ONN FFC 1 25MM 14 POS VERT 1 00 J1 510 16278 CONN 163 HDR 2X3MC SHR POL LK 1 00 J6 510 16279 CONNSM TEST 1206 6 00 8 525 16229 TERM SCRW PC SNAP VERT 6 32 6 00 P5 10 DESCRIPTION QTY EFFECT INACT REFERENCE INFO 600 16416 FUSE CLIP 5X20MM PC 217 LS 4 00 HW4 7 600 16419 BUS BAR CU 3CH RV8 1 00 W1 680 16417 WIRE 16G 6RINGX2 PC 80 150MM 1 00 W7 680 16418 WIRE 16G 6RINGX2 PC 170 150MM 1 00 W8 710 16150 PC BD AMP MOD 3CH RV8 1 00 PICK REV 2 PC BOARD 740 11287 LABEL S N PCB PRINTED 1 00 PLACE NEXT TO TP8 4 Channel Amplifier Board Assembly 201 16214 RES TRM 1T PC 1K OHM SA TOP 1 00 R168 201 16271 RES TRM 1T PC 1K OHM SA SIDE 3 00 R84 252 336 202 09794 RESSM RO 0 OHM 0805 6 00 R72 74 77 126 R249 251 202 16231 RESSM RO 5 1 4W 2 2M OHM 4 00 R47 131 215 299 202 16232 RES CF 5 1W 10 OHM VERT 16 00 R56 57 59 61 140 141 R143 145 224 225 227 R229 308 309 311 313 202 16234 RES MO 5 2W 68 OHM VERT 32 00 R26 27 34 35 37 38 R40 41 43 44 110 111 R169 173 176 194 196 R200 211 278 279 202 16255 RESSM RO 5 1W 30 OHM 8 00 R25 33 36 39 42 109 R193 277 203 11082 RESSM RO 1 1 10W 15 0K OHM 8 00 R3 6 87 90 171 174 R255 258 203 11732 RESSM RO 1 1 10W 1 82K OHM 4 00 R359 370 381 392 203 11980 RESSM THIN 1 1 10W 10 0K OHM 12 00 R53 78 79 137 162 R163 221 246 247 R305 330 331 203 12722 RESSM THIN 196 1 10W 49 9K OHM 4 00 R54 138 222 306 203 13134 RESSM THIN 196 1 10W 1 00K OHM 11 00 R8 32 81 144 155 1
276. ORT data format is comprised of a serial bit stream of eight 32 bit samples a serial shift clock and a frame start signal The audio data entering U16 on DSPASPOFPGA is comprised of samples from either the system S PDIF inputs the outputs of the A D Converters from the Analog IO Board or the S streams output from the Format Decoder DSP The selection of which stream is sent along to the SHARC is done via data multiplexing within the AVRX FPGA The data is clocked into the input buffers on the SHARC by SPORT CLK A while the beginning of the data frame is marked by SPORT FS A N SPORT data for the Main Zone is returned to the FPGA via DSPAPSFPGA This data is synchronous with SPORT CLK with each frame start marked by SPORT FS This data is re converted back to the S format via a look up table operation within the AVRX FPGA DSPA2DSPB is a data path from U16 to 034 synchronous with SPORT CLK A and frame start marked by SPORT FS A N while DSPB2DSPA is a data path from U34 to U16 synchronous with SPORT CLK B and frame marked by SPORT FS B N U34 provides a downmix data to the Analog IO Board via DSPBP3FPGA on SPORT port 3 This data is converted back to 125 data via look up table operation within the FPGA This data is synchronous with SPORT CLK B and frame start marked by SPORT FS B N SPORT port 0 on U34 is a full duplex communication channel to 016 and performs the same function as port 2 U16 The data ports are open drain therefo
277. OTHERWISE INDICATED CAPACITORS ARE UF V 2 DIGITAL ANALOG 1 CHASSIS POWER GROUND GROUND GROUND GROUND 3 LAST REFERENCE DESIGNATORS USED C2 FB3 J2 4 COMPONENTS MARKED WITH ON BOM REFERENCE COPY 2003 Lexicon Inc 3 OAK PARK BEDFORD MA 01730 DATE 8 26 02 CBV 8 26 02 SCHEM HEADPHONE BD RV8 NUMBER 060 15539 Q C 8 27 02 NAME MAG 8 27 02 15539 2 1 sHEET 1 OF 1 2 1 6 3 2003 12 14 8 7 6 5 4 3 2 1 REVISIONS REV DESCRIPTION DRAFTER CHECKER AUTH 1 CHANGED PER DCRS 030314 00 amp 030410 00 Eu pom 4 15 03 4 29 08 412V LM1117 5VD VOUT 3 16 R11 4 75K 1 LM1117 8P5V 2 vour vn ADJ TERM U1 L C17 1 C18 33 10 812 47 16 41021 1 4716 C19 R13 01 25 10 0K i C10 C8 196 57 1 25 a TEF6892H Gii vccaps NC 20 C13 001 25 cpRa 001 25 UT1384 NC 21 LEoUT ZZ NG _ 22 CDL RFOUT 28 NOTES ANTENNA L1 5 vcos VGGBPS NC 23 LRGUT 29 10 25 p 1 REIN 3 ANTENNA OUT 17 NC 24 TAPEL 30 NC C12 T UNLESS OTHERWISE INDICATED RESISTORS ARE 1 10W 6 8UH FM MPX OUT 1 25 1 RFGND1 RDS MPX BUT 18 R2 NC
278. P1 7 OUT POWER VS THD 1k 212 975 100 075 100 tk D A Amplifier Tests Digital Generator fftgen Switcher Module Typical Test Name Reading A In B In DIG_MAIN_COAX _IN_44K_T0_ANLG_WAIN_AWPS67_OUTNOBE hh T remeras eim ese DUT j S a EZ ro m ha k j L s L E sz jr jr jk None wma wa na dBV AD 9100 8500 oz 2 2 js2 6 o 0 0 Ei 44100 Di e wa na AD Leve 9200 90 10700 22 gt 22k __ 5572 7 0 0 Extema 4400 Digiti NOTES AMPLIFIER CONFIGURATION FM SIGNAL GENERATOR CONFIGURATION Ext Mod Input Modulation Program Frequency Pre Emph Amplitude 1 Tests are performed using the Audio Precision System Two Cascade Main DIR IN3 Left Front Left 5 Left Right FM AM FM kHz Pilot kHz AM 90 Display Mod Pilot Mono Address MHz 75uS dBu 2 Tests are performed using the Audio Precision System One Main DIR IN3 Right Front Right 1 n a EXT OFF ON n a 30 0 ON 1 050 n a 60 0 Main DIR IN5 Left Side Left 6 Main DIR IN5 Right Side Right 2 Main DIR IN5 Left Rear Left 7 Main DIR IN5 Right Rear Right 3 Page 6 of 6 Lexicon CHAPTER 5 TROUBLESHOOTING This chapter contains a complete description of the diagnostic tests for the RV 8 The diagnostics in
279. PACKAGED TO PREVENT ANY DAMAGE DURING SHIPMENT JUL 22 2005 UNLESS OTHERWISE SPECIFIED DIMENSIONS ARE IN INCHES TOLERANCES ARE FRACTIONS DECIMALS ANGLES CONTRACT NO exicon 201 APPROVALS DATE PC BD VIDEO OUT BD Rv8 005 DRAWN CW 8 6 02 ASSEMBLY DRAWING 710 15510 MATERIAL CHECKED CLC 8 14 02 SIZE FSCM NO NO m REV NEXT ASSY USED ON FINISH 36 RWH 8 14 02 980 15518 0 APPLICATION DO NO SCALE DRAWING SUED 8 15 02 SCALE 1 1 SHEET 1 OF 1 2
280. POS VERT 1 00 J2 710 15530 PC BD HEADPHONE RV8 1 00 PICK REV 2 PC BOARD Analog Input Output Board Assembly 202 09872 RESSM RO 5 1 10W 33 OHM 4 00 R209 210 217 218 202 09873 RESSM RO 5 1 10W 10K OHM 8 00 R19 20 24 25 29 30 R107 109 202 09899 RESSM RO 5 1 10W 47 OHM 4 00 R345 349 353 357 202 10557 RESSM RO 5 1 10W 4 7K OHM 3 00 R121 123 202 10569 RESSM RO 5 1 10W 10 OHM 6 00 R114 260 263 267 R271 275 202 10570 RESSM RO 5 1 10W 120 OHM 11 00 R18 22 28 32 98 101 8111 301 404 415 417 202 10571 RESSM RO 5 1 10W 100K OHM 40 00 R50 51 54 55 58 59 R62 63 66 67 70 71 R74 75 78 79 113 117 R120 126 129 132 135 R238 240 244 246 250 R252 256 258 261 264 R268 272 276 390 406 R413 414 202 10585 RESSM RO 5 1 4W 51 OHM 18 00 R106 108 278 281 282 R285 286 289 290 293 R314 317 322 325 330 R333 338 341 202 10586 RESSM RO 5 1 4W 100 OHM 24 00 R1 16 33 36 37 40 41 R44 45 48 202 10943 RESSM RO 5 1 10W 22K OHM 8 00 R161 166 171 176 R181 186 191 196 202 10946 RESSM RO 5 1 10W 3 3K OHM 1 00 R83 202 10949 RESSM RO 5 1 10W 1 2K OHM 5 00 R81 82 410 412 202 11496 RESSM RO 0 OHM 1206 4 00 R344 348 352 356 202 12191 RESSM RO 5 1 4W 330 OHM 6 00 R17 21 23 26 27 31 202 14585 RESSM RO 0 OHM 0603 4 00 R342 346 350 354 202 14792 RESSM RO 5 1 10W 56 OHM 20 00 R49 52 53 56 57 R60 61 64 65 R68 69 72 73 R76 77 80 103 104 R200 201 203 10578 RESSM RO 1 1 10W 2 21K OHM 9 00 R204 205 297 299 392 R402 407 419 420 203 10583 RESSM RO 1 1 10W 10 0K
281. POSITE VIDEO INPUTS 5VV C10 CVID J5 i125 longo VIDEO BOARD CONNECTOR 1 1 7 815 CVID 5 1 1 2 YEL RCA 75 0 CVID1 CVID5 2 1 R13 22 CVID4 3 3 3K 5 c9 CVID3 6 CVID2 8 1 25 5 SW 15V CVID1 10 C11 11 T 10 16 12 13 5VV 14 C8 J6 L C12 J4 5 T 10 16 125 __ 2 3904 1 i 1 R12 Q4 R11 Y 2 YEL RCA o CVID2 15V i 22 R10 C7 3 3K 1 25 15V 5VV C6 NOTES J3 4 25 2N3904 1 UNLESS OTHERWISE INDICATED RESISTORS ARE 1 10W 3 1 2 UNLESS OTHERWISE INDICATED RESISTORS ARE 596 aT VEL HOR t HA Q3 R8 CVID3 3 UNLESS OTHERWISE INDICATED CAPACITORS ARE UF V 196 22 4 DIGITAL ANALOG 1 CHASSIS POWER ae 77 GROUND Y GROUND GROUND GROUND C5 5 LAST REFERENCE DESIGNATORS USED C12 J6 Q5 R15 1 25 15V 5VV C4 J2 125 2 3904 i 9 R6 EL 750 Q2 R5 7 22 R4 3K 33 1 25 15V 5VV C2 1 25 2N3904 5 a D D D R3 Q1 R2 75 0 CVID5 2 YEL RCA 1 R1 C1 3 3K 1 25 15V 22 2002 Lexicon Inc CONTRACT 3 lexicon BEDFORD MA 01730 DEM SALE SCHEM VIDEO IN BD RV8 8 7 02 RCA INPUTS CHECKED 8 13 02 SEE CODE NUMBER P RWH 8 4 02 mLEWAME ISSUED MAG 8 15 02 15509 0 1 me 1 or 1 002 11 12 N 9 3 2 ZONE2 COMPOSITE VIDEO OUT 2 MAIN COMPOSITE VIDEO OUT 1 OSD
282. PS BD SUBASSY RV8 1 00 440 16212 FUSE 5X20MM SLO BLO 6 3A 250V 1 00 For 220 240V HW1 2 440 16213 FUSE 3AG FAST 15A 250V 1 00 For 120V HW1 2 635 16285 SPCR 6 32X1 25 25HEX ALUM 2 00 640 16291 SCRW 6 32X 25 PNH TORX SEMS BZ 2 00 641 16299 SCRW TAP 6 32X 25 PNH TX SMS Z 4 00 701 16426 BRACKET TOROID PS RV8 1 00 Bridge Rectifier Assembly 300 16273 DIODE RECT 200V 50A W HS 1 00 635 16286 SPCR 8 32X 5 375HEX ALUM 1 00 640 16287 SCRW 8 32X 75 PNH TORX SEMS BZ 1 00 704 16433 HEATSINK BRIDGE RECT RV8 1 00 VCO Mechanical Assembly 023 16129 PL VCO BD ASSY MCLK 1 00 700 14838 HOUSING 12 1 00 700 14839 COVER VCO MC12 1 00 3 Channel Amp Bd Mechanical Assembly 022 16446 PL HS ASSY SGL POS RV8 1 00 022 16447 PL HS ASSY SGL NEG RV8 1 00 022 16448 PL HS ASSY DBL POS RV8 1 00 022 16449 PL HS ASSY DBL NEG RV8 1 00 023 15824 PL AMP BD ASSY 3CH RV8 1 00 023 15890 PL SPKR EMI FILTER BD ASSY RV8 3 00 490 16280 CONN BDGPOSTX2G 10 32 RED BLK 3 00 630 16283 WSHR SHLDR 312SHNK 6CL NYL 4 00 630 16284 SPCR 6CLX 090 25RD NYL 4 00 640 01710 SCRW 6 32X1 4 PNH PH ZN 6 00 P5 10 640 16298 SCRW 6 32X 25 UFH PH ZN 2 00 641 16288 SCRW TAP 6 32X 312 PNH TORX ZN 20 00 643 16290 NUT 6 32 KEP CONICAL WSHR ZN 4 00 644 03668 WSHR LOCK EXT STAR 6 SS 4 00 680 16422 HARNESS AMP 3CH RV8 1 00 701 16424 BRACKET AMP 3CH RV8 1 00 702 16427 PLATE AMP 3CH RV8 1 00 703 16429 INSUL AMP 3CH RV8 1 00 4 Channel Amp Bd Mechanical Assembly
283. PTO PCRA TORX173 6Mbps 4 00 CP1 4 510 14079 CONN POST 156X045 HDR 4MC LOK 1 00 J31 510 14833 CONN OPTO PCRA XMTR 13 2Mbps 1 00 12 13 04 CP5 510 15688 CONN FFC 1 25MM 16 POS VERT 1 00 VIDEO BD J29 510 15689 CONN FFC 1 25MM 34 POS VERT 2 00 OPT BDS J25 30 510 15690 CONN FFC 1 25MM 40 POS VERT 2 00 ANLG FP BDS J20 26 510 15694 CONN FFC 1 25MM 6 POS VERT 1 00 AMP PWR SUP J27 510 15695 CONN FFC 1 25MM 14 POS VERT 2 00 PWR AMPS J18 22 510 16389 CONN OPTO RA XMT 13 2Mbps SHTR 1 00 12 13 04 CP5 640 01701 SCRW 4 40X1 4 PNH PH ZN 2 00 U38 LUG 1 670 01974 WIRE JMP 22AWG 0 1 NON INSUL 1 00 W6 701 09640 BRACKET KEYSTONE 621 4 40X2 1 00 LUG1 704 06165 HEATSINK TO220 75X 5X 5 TAB 2 00 08 9 704 09508 HEATSINK TO220 MTTAB W 4 40NUT 1 00 U38 710 15550 PC BD MAIN RV8 1 00 PICK REV 5 PC BOARD 740 11287 LABEL S N PCB PRINTED 1 00 VCO Masterclock Board Assembly 202 09899 RESSM RO 5 1 10W 47 OHM 1 00 R1 245 09895 CAPSM CER 10pF 50V COG 10 1 00 C3 245 12485 CAPSM CER 1uF 25V Z5U 2096 4 00 C1 2 4 5 270 11545 FERRITESM CHIP 600 OHM 0805 1 00 FB1 270 14359 COILSM VAR 1UH 5 5 6X6 2X6MM 1 00 L1 300 13881 DIODESM VARACTOR BB132 1 00 D1 340 16132 ICSM LIN MC100EL1648 VCO TSSOP 1 00 U1 510 14836 CONN POST 100X025 HDR 5MC RA 1 00 J1 710 16130 PC BD VCO MCLK 1 00 PICK REV 0 PC BOARD 7 3 DESCRIPTION QTY EFFECT INACT REFERENCE INFO Microphone Preamplifier Board Assembly 202 09795 RESSM RO 5 1 10W 2 2K OHM 4 00 R1
284. Panel Board The IR ENCODER Board VFD and LED matrix are powered by 5VD while the CPLD is powered by 3 3VD 6 42 Lexicon Video Board Connector J29 J29 is a 16 position FFC connector that conveys all the signals necessary for Host CPU access to the on board FPGA and the Video Decoder Encoder components VIDEO RESET is a buffered equivalent of the active low reset signal generated by 031 It provides an initiating signal to the state machines within the FPGA on the Video Board SYNC DETECT is a signal that indicates the presence or absence of video synchronization from the Video Board OSD_CS is the chip select for the Fujitsu MB90092 OSD Controller device located on the Video Board VIDEO SCLK is the serial data shift clock that comprises the SPI interface to the OSD and control logic VIDEO DATA is the serial data that is part of the SPI interface to the Video Board VIDEO REG comprise the remainder of the SPI interface to the On Screen Display controller and the video board control logic VID I2C SDATA is a serial data stream that communicates to the Video Codec using C protocol Provision is made for a pull up resistor R180 for compliance with the C specification The equivalent resistor is already populated on the Video Board and hence is not needed here VID 12 SCLK is the serial data stream shift clock that communicates to the Video Codec using protocol Provision is made for a pull up resistor R181 for compli
285. R139 18PF HOS o N 1 50 57 6K 45V 1 R140 1 4 32K 415V 196 R104 _ __ R92 C69 15V 15 88 43 02 s _L REAR_DACOUT ps 1 56 82 SR103 28109 _ P 47 25 15V 5VD R34 Dios al 20 2 825 6 56 2 8102 71 7 2 13 12 ADG451 1 57 gt 0 11 10 4 072 BFS 7V S D RELAY i OdBFS 7Vrms 9 JIN 15V R33 FB7 GND m 18V 4 i 1 LEFT OUT 4 5 6 li 100 RCA gt 5VD 44 1 4W 893 C70 15V 13 150PF T 4 13 C2 DACOUT A 9 x 22 47 25 15V 5VD R85 1 2825 1 13 12 40045 1 16 FB vii VDD M 439 Rao FB8 2 CONTRACT 6 7 VA RIGHT OUT 5 10 A6 11 A6 12 A7 14 C3 MAIN_MUTE l 8 IN RY4 100 RCA gt NO n 3 OAK PARK 12 7 TEE 1 4W 8 BEDFORD 01730 150 T 4 TITLE U26 APPROVALS DATE 4 5 o DRAWN SCHEM ANALOG I O BD RV8 RWH 8 27 02 8 CHECKED L R REAR DACS CBV 8 28 02 SIZE CODE NUMBER REV 10 A5 11 A7 12 A7 MAIN_RLY_CNTL B 060 15579 6 CW 8 29 02 FILE NAME ISSUED 8 29 02 15579 6 13 SHEET 13 OF 17 8 7 6 5 4 3 2 1 6 21 2004_ 14 23
286. R289 BEDFORD MA 01730 47 16 5 62 TITLE APPROVALS DATE ae M Ed SCHEM ANALOG BD RV8 8 27 02 u INPUTS amp SIDE A D CONVERTER CBV 8 28 02 SIZE CODE NUMBER REV 060 15579 4 CW 8 29 02 FILE NAME ISSUED MAG 8 29 02 15579 6 6 SHEET 6 OF 17 8 7 5 4 3 2 1 2 2 2004_11 13 8 7 6 4 3 2 1 REVISIONS REV DESCRIPTION DRAFTER Q C 415V 5VD CHECKER AUTH i 04 RWH CW EY 1 CHANGED PER DCR 021107 00 NOM NISL 13 12 nian CBV MAG 11 20 02 11 21 02 VDD 8 __ LEFT 5 3 2 RWH CW 8 C6 4 D8 15 3 633078 236 HAE T 2 CHANGED FER DCR 090407700 5 21 03 5 23 03 214 gt REC_IN 7 B7 CBV MAG GND 415V 45VD Y 2 54 es 5 23 03 5 23 03 A J RWH CW PHONO 75U INPUT 4 5 U49 100K Bo S CHANGED PER BOR 0307 2900 9 29 03 10 7 03 DG411 15V 1 TA 1 A5V VCC VDD 8 C6 4 D8 RIGHT PHONOTS IN 14 p15 16 IN 415V 15V 5VD VEE GND lh 4 5 049 5 8 MC3307 4 N 8 13 12 Fx RIGHT REC IN HALF IAT MIC1 IN Ds x 1 00K 3 86 4 C8 6 D8 55 R240 1 R241 gt 100K y 2 1 00K GND 15V 5VD ASV 1 MIC INP
287. RD THEORY The Phono Microphone Input Board contains the circuitry for the phono and mic input preamplifiers This board is located in a metal tray with the Tuner Board attached to the back panel The outputs from the preamps are sent to the Analog Board via a flat flex cable and eventually to differential buffers on that board unbalanced signals are sent with a local ground reference as a to form a differential pair Phono Inputs The phono is designed as a two stage RIAA filter circuit The first operational amplifier takes care of the 50Hz and 500Hz breakpoints while the 2122Hz rolloff is accomplished by the passive network R35 R44 and C37 The second amplifier supplies an additional 19 5 dB of gain Using two amplifiers results in accurate conformance to the RIAA curve as well as lower distortion due to the fact that each amplifier is operating at a lower gain than would be the case in a single amplifier design 6 47 RV 8 Service Manual D10 and D13 diode networks prevent the large signals that come from phonograph needle dropping to get into the mux circuitry on the analog board C31 C38 and C45 for a third order high pass circuit at around 8Hz to block the low frequency rumble sounds A tap is provided after the first opamp section This output is labeled 75uS_R L because it does not include the 2122Hz 75uS time constant rolloff filter which is useful to provide high frequency rich signals for click and pop dete
288. RE F BLACK 22 7 m P 8 WIRE B BLACK 13 m od C 3 a NOTES pe 3 3 1 PART NUMBER LISTING IS FOR REFERENCE ONLY AND DOES NOT SUPERSEDE THE BOM 2 REFERENCE DRAWING 680 16423 FOR WIRE HARNESS DETAILS 9 q 8 RING TERMINALS ATTACH TO SCREW TERMINALS ON PCB b 10 RING TERMINALS ATTACH TO BINDING POSTS 3 SOLDER TO 3 DEVICE LEADS TO eooo 6 32 N 8_ se teerr WE 166 48 wer ss 023 185800 PL sun num m es _______ B su oswes wem LOOK Ex sue je s 715 so wes ws o U O e r tezse Som TAP 6 32 x 312 TORK 24 wu 6 32 KEP CONCAL WOH ZN s 1ez5 sum 312 pec mb 4 s ws wes TL asan _ 1 x om 28 7 PATE 1 so teme Som 6 32 x 7s 490 1620 posmas 10 82 4 em wes PL ns ass Ps U 3 PL ges om 2 FROM gea 979 M S f PART IS SYMMETRICAL INSULATOR REPLACED oe ae oe m APPROVALS iE ASSY DWG 4CH 8 RV8 ZE NO DWG NO REV umo P e D 080 16435 2 APPLI
289. RIFY LATEST ES PC ASSY DWG AMP MOD REVISION PRIOR TO USE LERANCE UNL WILL DAMAGE THE RELAY OTHERWISE SPECIFIED THESE DRAWINGS AND SPECIFICATIONS ARE THE 2 SIZEIDWG NO REV PROPERTY OF CROWN INTERNATIONAL INC AND BBB 2010 16158 NOT BE REPRODUCED COPIED OR USED DRILLS 883 E 2 AS THE BASIS FOR THE MANUFACTURE OR SALE OF APPARATUS OR DEVICES WITHOUT PERMISSION DO NOT SCALE DRAWING SCALE NDNE PROJ NO 5 SHEET 1 OF 1 4 3 2 ONENT MAP TOP SIDE REVISION HISTORY APPROVED E C N ZONE REV DESCRIPTION DATE DWN EM PE 1 INITIAL RELEASE 6 26 03 5 5 2 SYN LABEL amp NOTES PER ECO 040404 0 4 23 04 wes 5 COPY ASED R S N LABEL P N 7486 11287 OR EQUIVALENT 5 5 Bow idi d cus 4 Ja dss amz H ses cie7 mus d NA H 078 a 085 HI 067 m mE Mm 5 R3
290. RIOR TO SIN N AQ 0 EQUIVALEN N LA 740 11287 JIVALENT 52 010 D21 D3a 034 o a pag ma 21 8 o I foo C8 ad X Em 28 5 Mc ale go v2 cis er E 4 5 d Bal L 40 2 es Bia 2 x Ug 75 agg 40 1 J5 Dit 02 033 035 036 37 038 RIO 29 gas m R46 R47 R48 1 Rag C D D D C2 UJ JUL 22 2005 A RELEASED COPY UNLESS OTHERWISE SPECIFIED DIMENSIONS ARE IN INCHES CONTRACT NO E X C O TOLERANCES ARE FRACTIONS DECIMALS ANGLES ol APPROVALS DATE PC BD SWZLED D RVB LR AWN CW 7 5 02 MATERTAL 0 ASSEMBLY DRAWING 110 15560 CLC 7 9 02 _ _ aN TEA SIZEIFSCM NO DWG NO E REV DOCUMENT CONTROL BLOCK NEXT ASSY USED ON RWH 7 10 04 D 080 15568 SHEET 1 REV 1 ao SHEET 2 REV 1 APPLICATION DO NO SCALE DRAWING 7 8 02 SCALE 1 1 SHEET OF 2 8 CO 5045 544 5042 39 J4 40 40 5
291. RMISTOR PTC 6 OHM 265V 2 00 RT1 2 510 15694 CONN FFC 1 25MM 6 POS VERT 1 00 P1 510 16227 CONN 163 HDR 2MC SHR POL LK 1 00 J21 510 16228 CONN 250 HDR 2X3MCG SHR POL 3 00 J4 14 15 510 16278 CONN 163 HDR 2X3MC SHR POL L 2 00 J2 5 525 16281 TERM QDC 250 PC 2LS LK 1 00 J12 525 16282 TERM QDC 250 PCRA 2LS 2 00 J6 7 600 16230 FUSE CLIP 3AG 5X20MM PC 2 00 HW1 2 710 16170 PC BD PS RV8 1 00 PICK REV 2 PC BOARD 740 11287 LABEL S N PCB PRINTED 1 00 PLACE OVER HW4 Chassis Assembly 022 15610 PL MECH ASSY FP RV8 1 00 022 15611 PL MECH ASSY VIDEO RV8 1 00 022 15612 PL MECH ASSY TUNER PREAMP RV8 1 00 022 15624 PL FAN ASSY RV8 4 00 CONNECT TO MAIN BD J21 23 24 32 022 16444 PL MECH ASSY AMP 3CH RV8 1 00 022 16445 PL MECH ASSY AMP 4CH RV8 1 00 023 15615 PL MAIN BD ASSY RV8 1 00 023 15617 PL ANLG I O BD ASSY RV8 1 00 270 16120 FERRITE FLAT CABLE 1 8X1 1 1 00 TUNER CABLE 454 13124 SW ROCKER 2P1T 16A 250 BLK VER 1 00 470 15213 XFORMER PWR TOR RV8 CX AMP 1 00 For 100 120V WIRE TO 100V 120V CONN ON PS BD For 220 240V WIRE TO 220V 230V 240V CONN ON PS BD 490 13144 CONN PLUG 200 4FC RA 12 30G 1 00 REAR PANEL 490 15843 CONN AC 3MC SNAP 06TH IEC 10A 1 00 527 12974 CONN DSUB JSCKT 4 40 187X 25 4 00 DCONN TO R PANEL 530 02488 TIE CABLE NYL 14 X5 5 8 8 00 CABLES TO CHASSIS 540 14303 GROMMET STRIP SER 037 GAP NYL 15 50 2 7 75 PCS 541 15576 FOOT 50MM DX25MM H ABS BLK 4 00 CHASSIS 550 15844 HANDLE U 5X2H 3 8 D BLK 2
292. Reading Limit Limit Imp _ Bandwidth Filter B In A Out B Out Source Rate Source ANLG_FRONT_IN4_TO_DIG_ZONE2_OPT_OUT_96K 200Vrms _ 200 Vrms N4 TO DIG ZONE2 OUT 96K THD 1 3 80 Vrms 3 80 Vrms 20 1k 5k 40k None 20 Unba Float dBFS THD N 98 00 86 00 88 00 75 00 120 00 n a 10 Fs 2 None n a n a 4 16 Internal 96000 Analog LG _IN4_TO_DIG_ZONE2_OPT_OUT_96K_DYNRNG 1 4 00 mVrms 14 00 mvrms 997 None 20 Unbal Float dBFS THD N 108 00 104 00 130 00 lt 10Hz gt 20kHz LP n a n a 4 16 Internal 96000 Analog 200Vrms 2 00 Vrms Level 0 20 0 00 ANLG FRONT IN5 TO DIG ZONE2 OUT 96K 1 Hoovms 4oovms 15k 20 Float dB ev lt 1500 8000 4300 lt 10 2 None 5 17 mtema 96000 Analog lt 10Hz gt 20kHzLP ZONE2 OP OUT 95K T T T T psc wipe oq cmo opm Re ANLG FRONT IN6 TO DIG ZONE2 OPT OUT 96K GAIN 1 4 00 Vrms 4 00 Vrms 997 None 20 Unbal Float dBFS Level 0 38 0 00 1 10 n a lt 10 Fs 2 None n a n a 18 Internal 96000 Analog ANLG FRONT 6 DIG ZONE2 OUT 96K THD 1 sovms 3 80 __ 201 4 None 20 Float jdeFS THD N ____ 98 00 86 00 88 00 7500 4220 lt 10 5 2 wa 6 18 9600 Anal Level lt 115 00 8000 4500 lt 0 52 jhoe 6 18 Itema 9600 Analog ANLG FRONT 6 TO DIG ZONE2
293. Regulator U38 041 is a fixed output voltage regulator that provides a 3 3V supply to most of the logic on this board It is derived from 5VD C158 provides local high frequency de coupling to the input while C122 provides local bulk capacitance to the output L1 and C123 form a low pass filter to provide a cleaner supply to the 3 3V It has been determined that this precaution is not needed in this design and so these components are not used W6 provides a zero ohm path from the 5VD supply to the input of 038 Diode D48 ensures that the output voltage never assumes a level higher than 5VD which could cause destruction to 038 Fan Control Circuitry U47 inverts the pulses supplied by one of the PWM timer circuits inside the Host CPU R179 acts asa default pull down for Q1 in the event that there is no signal source connected to U47 and the output achieves an indeterminate state as a result This prevents the fans from turning on in the absence of a control voltage R177 provides current limiting to the base of Q1 When positive current flows into the base of Q1 the transistor saturates effectively pulling the gate of Q2 low When a logic zero is applied to the base of Q1 the transistor appears as an open circuit to the gate of Q2 causing it to conduct from the drain to the source The drain of Q2 follows the input signal FAN DRV D49 L2 and C178 act as a full wave rectifier and filter that produces a DC voltage proportional to the duty cycle of
294. S THROW OUT BLANK PCB MATERIAL AFTER WAVE SOLDERING JUL 22 2005 UNLESS OTHERWISE SPECIFIED DIMENSIONS ARE IN MM TOLERANCES ARE FRACTIONS DECIMALS ANGLES E KX f 1 5 ex DRAWN RWH 12 03 02 710 15540 MATERIAL CHECKED CLC 12 03 02 ASSEMBLY DRAWI BD TUNER G NEXT ASSY USED ON FINISH Q C CW 12 09 02 SIZE FSCM APPL CATION DO NO SCALE DRAWING ISSUE D MAG DWG NO REV 080 1553548 1 12 09 02 SCALE Tel SHEET 1 OF 1 ry 4 4 2
295. SCRIPTION DRAFTER CHECKER BGN 1 CHANGED PER DCR 030106 00 210 R190 5VV 12303 2 CHANGED PER DCR 030421 00 siot 2 05 5 8 m 050 IN 5 20 03 5 22 03 RWH CW R189 3 CHANGED PER DCR 030623 00 E 050 10 9 03 10 16 03 8192 4 75K 1 3 3VD R182 3 3VD R183 es 16 10 16 681 t t 15 OSD SY OUT 1 145K SY 2 D5 L C166 MSVID_YOFF R209 T 12PF 9 C3 475 196 SECAM EN a 9 C3 57 47PF R179 1 15K SK OSD Y C OUTS 5VV B Bet C 145K C108 1 C115 T 68PF 1 25 Y C107 2 A5 5 C8 m 230 C IN NC OSD C OUT vkour 39 Ne _ 016 14 OSD CSYNC GMHSYN 15 OSD VSYNC B C2 m VSYNC 8 2 m S YNO VBLNK S NE _ 2 NC voc 3 NG MB90092 vos NC US ohe PLS az Ne A 15 0 Fsco 2 9 D3 22 pos 22 NC 0 8 OSD_TSC5 77 J D 7 0 9 3 we VIDEO DATAS pee 55 A2 9 D3 9 3 950 ADR3 6 FONT MEMORY DAS 050 557 8250 a7 4 qe ADRS 58 A5 apoE 59 A6 60 AZ 5VV 5VV B ADR7 NC 19 NC1 ADR8 61 A8 29F010 5VV NC 25 46 ADR9 63 A9 A0 12 A0 32 A NC 26 ADR10 64 A10 NC 27 NC4 pate T A nas 19 500 T NC 28 67 A12 9 14 Di R170 Ne 28 NC5 ADR12 5VV 001 10K ADR13 99 8 A4 15 02 READ ADR14 59 14 las pos Ds ADR15 2 EXE 4 14 31818MHZ ela 0041804 78 TEST ADR16 21 5
296. SPBALDATA5 D4 MSS LOBATA A9 DSPBALDATA4 DTT DSPBALDATA3 SPORT B Do Aii DSPBALDATA2 gt SPORT N C9 3 B11 DSPBALDATA1 DSPBSP3FPGA Doa DSPBALDATAO D3B ae Ne LOCLK NC scLke ADSP 21161N ado Ne 8 LOACK NC B7 D2A SPI BLOCK c11 DSPABLDATA7 DSPABLDATA 7 0 028 12 DSPABLDATA6 NC B6 012 DSPABLDATA5 NC p7 SCLK1 L1DATOS B45 DSPABLDATA4 NC C6 FS1 4 615 DSPABLDATA3 NC 06 01 LTDATOS Aya DSPABLDATA2 DIB AAE DSPABLDATAT DS BTA DSPABLDATAO FSO E4 Doa LicLk 418 B 65 Bi L1ACK 034 CONTRACT 7 A 9 lexicon BEDFORD MA 01730 TITLE APPROVALS DATE SCHEM MAIN BD RV8 DRAWN 4 26 02 DSP SPI SERIAL AND LINK PORTS CHECKED 4 30 02 BER CODE NUMBER REV 9 060 15559 3 565 CW 5 1 02 FILE NAME 4 30 02 15559 6 6 SHEET 6 or 19 7 6 5 2 1 9
297. SR 3 00 C138 140 240 10758 CAPSM ELEC 1uF 50V 20 5 5mmH 2 00 C56 179 240 11111 CAPSM ELEC 47uF 6V NONPOL 20 10 00 C11 15 17 21 25 C130 134 240 11827 CAPSM ELEC 10uF 16V 20 5 00 106 107 122 129 183 240 13217 CAPSM ELEC 47uF 16V 20 4 00 C47 54 73 79 241 09798 5 10 10 20 3 00 97 137 163 245 09876 CAPSM CER 01uF 50V Z5U 20 6 1 00 C120 245 09895 CAPSM CER 10pF 50V COG 10 1 00 C99 245 10416 CAPSM CER 1000pF 50V COG 5 3 00 C127 177 178 245 10452 CAPSM CER 390pF 50V COG 5 3 00 C32 33 39 245 10544 CAPSM CER 220pF 50V COG 5 2 00 C172 176 245 10561 CAPSM CER 100pF 50V COG 5 3 00 C64 169 174 245 10972 CAPSM CER 068uF 50V X7R 20 1 00 C180 245 10975 CAPSM CER 3300pF 50V X7R 10 1 00 C181 245 10976 CAPSM CER 47pF 50V COG 5 1 00 C117 245 10977 CAPSM CER 330pF 50V COG 5 1 00 C173 245 11591 CAPSM CER 560pF 50V COG 5 3 00 C27 29 34 245 11625 CAPSM CER 33pF 50V COG 5 1 00 C109 245 12070 CAPSM CER 15pF 50V COG 10 1 00 C100 245 12460 CAPSM CER 056uF 50V X7R 20 6 00 C151 156 245 12485 CAPSM CER 1uF 25V Z5U 20 119 00 C1 10 12 14 16 18 20 C22 24 28 31 35 37 C40 46 48 53 55 C57 63 65 72 74 78 C80 96 98 101 105 C108 112 116 118 119 C121 123 126 128 135 C136 141 150 157 162 C164 165 167 168 170 C171 175 182 245 12522 CAPSM CER 120pF 50V COG 10 3 00 C26 30 38 245 12524 CAPSM CER 68pF 50V COG 5 1 00 C115 245 14762 CAPSM CER 6 8pF 50V COG 5 1 00 C110 245 14763 CAPSM CER 12pF 50V COG 5 2 00 C113
298. ST BE OPENED AFTER THE ee ae Ee EE FILENAME PE MES 4 21 03 CLEANING PROCESS BY EITHER REMOVING THE SEALING OR CUTTING COPY COPIES OF THESE DOCUMENTS 161786 2 OFF THE CIRCULAR TAB WITH KNIFE SIMILAR CUTTING TOOL INCLUDING ASSOCIATED ELECTRONIC REPRODUCTIONS WARNING THIS STEP MUST BE DONE AFTER THE CLEANING PROCESS NOT ARE FOR REFERENCE ONLY VERIFY LATEST ASSY DWG PS REVISION PRIOR USE BEFORE WATER CLEANING SOLVENTS THE RELAY VENT OTHERWISE SPECIFIED WILL DAMAGE THE RELAY THESE DRAWINGS AND SPECIFICATIONS ARE THE B 202 d DWG NO REV PROPERTY OF CROWN INTERNATIONAL INC AND 888 818 48 p j 1 7 8 SHALL NOT BE REPRODUCED COPIED OR USED DRILLS 083 AS THE BASIS FOR THE MANUFACTURE OR SALE OF APPARATUS DR DEVICES WITHOUT PERMISSION DO NOT SCALE DRAWING MEE SCALE NONE PROJ NO MD588D8 SHEET OF 1 4 3 2 C D e DRAFTER Q C REV DESCRIPTION CUECKER 2 NOTES 1 LEXICON BOM NUMBER 023 15890 SUPERSEDES ANY INFORMATION ON THIS DRAWING 2 ALL COMPONENTS TO BE INSTALLED FROM TOP SIDE OF PCB 3 UNLESS OTHERWISE SPECIFIED MOUNT ALL COMPONENTS FLUSH AND PERPENDICULAR
299. T DYNRNG na 4 THD N ____ 109 00 _____ 105 00 ______ 1000 00 ook 40 2 None 16 138 ma Exema 96000 wa THD N 10000 00 4500 00 0 2 1 Exemal 95000 97000 DiG MAIN OPH IN ASK TO ANLE MAIN OUT DI NAR OPTEN AEK TO AN WAN OUT HD sr s 4800 Digital D MAIN OPTI N 48K TO ANLG MAIN OUT DYNRNG 61 20 dBFS 10 22k Externa igi DIG MAIN OPT1 IN 44K TO ANLG MAIN OUT DIG MAIN OPT1 IN 44K TO ANLG MAIN OUT GAIN j 0 00 dBFS lt 10 gt 500 External DIG MAIN OPT1 IN 44K TO ANLG MAIN OUT THD 10 00 dBFS 10 22k Externa 44100 Digita D MA IN 44K TO LG MAIN OUT CLKRNG 1 10 00 dBFS 10 00 dBFS 997 7 HD N gt 96 00 86 00 130 00 100 lt 10 22k n a u Externa 43650 44550 Digital Page 3 of 6 TEST 8 RV8 AUDIO TEST SUMMARY 010 15834 A A Tests Analog Generator Analog Analyzer Switcher Module See Bal Gnd Typical Upper Lower Clock Sample Audio Test Name Note Left Right Freq Hz EQ Curve Z out Unbal Float Level Measure Reading Limit Limit Imp _ Filter B In A Out B Out Source Rate Source ANLG_ZONE2_IN1_TO_ANLG ZONE2 DIR VAR OUT None 20 100k lt 10 gt 500k None 13 Internal ZONE2 1 TO ANL
300. T IN menu will be displayed 17 Using the Menu gt arrow highlight the VIDEO parameter and press the Menu arrow to select it This will set the RV 8 to up convert composite and S video inputs to component video 18 Press the Menu 4 arrow three times to exit to the SETUP menu 19 Using the Menu arrow scroll down to the DISPLAYS parameter and select it by pressing the Menu gt arrow 20 The DISPLAY SETUP menu will open with the ON SCREEN DISPLAY parameter highlighted Select it by pressing the Menu arrow 21 The ON SCREEN DISPLAY menu will open with the STATUS parameter highlighted Select the STATUS parameter by pressing the Menu arrow and change the value of the parameter to ALWAYS OFF 22 Press the Menu arrow to exit the menu structure 23 The video path is now set for testing Test 1 Load a disc into the DVD player and press play 2 Verify a clean undistorted picture appears on the monitor Making The Bias Voltage Adjustment Dangerous voltages capable of causing death are present in this unit Use extreme caution when handling testing or adjusting The bias voltage adjustment should only be performed while the amplifier module is at room temperature 25 C The amplifier module must have power applied for at least one minute before the bias adjustment is performed If the amplifier is hot from prior testing it should be set aside until it has cooled before continuing Use caution and foll
301. TAS8 E45 021 39 0022 2 26 DSPA NC ADDRIS 7 F15 DSPA_D20 37 0021 1 725 DSPA 0 1 2 3 Ne M2 ADDR12 DATA36 Ci LE 37 DQ20 2MX32 AO RP4 s 4 RP4 NG ADDR11 DATA35 D18 34 0019 100MHZ 59 C 10K S10K 10 DSPA ps ADDRtO DATA34 012 PSEA DIE 34 pais pams 2 EBOOT LBOOT BMS STATE 8 7 6 AR 52 ADDS ADSP 21161N DATA33 IS DEPA DTE 3 45 W M 1 0 1 HOST BOOT 83 7 MEMORY DATAS 15 Rene DH 83 0015 Damo S 0 1 O SPI BOOT DEFAULT R70 M4 appns H14 D14 52 0014 mM 0 11 LINK PORT BOOT DSPA_A4 ADDRS DATA29 HT5 D12 80 0013 RASP18 R69 ADDR4 28 45 DSPA 79 0012 1 o EEPROM BOOT BA R4 DATA27 512 7 wEp 3 X RESERVED 1 DSPA_At N5 ADDR2 DATA26 DSPA D9 76 0010 csp R71 x ADDR1 DATA25 DQ9 0 M5 J13 DSPA_D8 74 ee ADDRO 24 15 DSPA_D7 068 ais NC 5 DATA23 x BMS BECOMES AN OUTPUT 777 Ne Riomsa PATAS KI DSPA 06 SELECT N 2 MS 14 05 10 73 NC 4 82 DATA21 205 C6 Ne NC 13 DSPA_D4 8 6 70 MS1 DATA20 004 Ne SO 13 D3 ae hee DATATSUT 15 DSPA D2 5 003 57 NC Req WR DSPA Di 41002 N6 RD
302. TEST menu highlight S PDIF INPUT CX 1 TEST Press the remote control Menu y arrow to engage the test The RV 8 is now set to route digital audio from the S PDIF COAX digital input labeled 1 to all the RCA analog outputs 5 Power on the external amplifier Press Play on the CD player 6 Slowly increase the volume on the external amplifier to a comfortable listening level 7 Verify that clean undistorted audio can be heard 8 Stop the CD player and power down the external amplifier 9 The above procedure should be repeated to test S PDIF coaxial digital inputs 2 through 4 as well as the optical inputs 1 to 4 To do this repeat the procedure changing the Input Test selected in step 4 to the next appropriate input Move the output of the CD player to the appropriate RV 8 input that corresponds to the input selected in the AUDIO I O TEST menu When testing the optical inputs be sure to use the appropriate digital cable 4 18 Lexicon AUDIO PERFORMANCE VERIFICATION Performing these tests assures that the audio signal paths in the RV 8 meet published specifications These tests will verify the performance specifications of the gain frequency response THD N and S N ratio of each channel Analog Audio Inputs To Main Zone RCA Outputs Test This test will verify the specifications of the Main Zone RCA outputs Setup 1 Connect an audio cable between the output of the Low Distortion Oscillator and the RV 8 left RCA input 1 2 C
303. TION DRAFTER Q C CHECKER AUTH RWH CW 1 CHANGED PER DCR 020913 00 10502 550 05 11 06 02 12 20 02 RWH CW 2 CHANGED PER DCR 030307 00 rM CAM MAG 5 14 03 5 20 08 RWH ECM 3 CHANGED PER DCR 030626 00 10 2 08 10 9 03 REMOTE POWER CONTROL DRIVERS 3 3VD U14 2 03 REMOTE PWREN1 2 74VHC04 CASE GND 12V J3 ON OFF FB1 1 5 t i LM2941CT R16 4 L c25 GND ADJ 8 45K c22 nis n c E T 47UF 3 1U8 1 47 16 1 4W 1 4W S77 R15 277 1 00 LTZ 1 U14 2 03 REMOTE PWRENO 3 4 74VHC04 15V CASE GND ON OFF 12y FB2 vout Ne LM2941CT R20 LC23 GND 8 45K tl C24 ni RIS Lew T 47UF 3 109 1 T 47 16 1 4W T 150PF SPARES R19 U14 n 5 6 NC b 74VHC04 U14 gt 8 NC B 74VHC04 U14 L u 10 NC 74VHC04 U14 13 12 NC 74VHC04 277 CO n NO BEDFORD MA 01730 TITLE APPROVAL DATE OVALS SCHEM MAIN BD RV8 DRAWN 4 26 02 TRIGGER OUTPUTS CHECKED 4 30 02 SEE CODE NUMBER REV 060 15559 3 CW 5 1 02 FILE NAME 880 JV 4 30 02 15559 6 14 sHEET 14 Or 19 7 6 4 2 1
304. The second gate in the signal chain acts as a simple buffer providing a minimal load to the amplifier stage thereby preserving stability Optical S PDIF Inputs CP1 CP4 are standard TORX style optical receivers No additional signal conditioning is required for these signals and as such they are presented to the AVRX FPGA right from these inputs Record Zone S PDIF Outputs A digital audio output for the Record Zone is sourced from the AVRX FPGA to a 74VHCT244 Octal Buffer U2 Two out of the available eight buffers are actually used The first output drives a TORX style optical output connector The second buffer output drives a voltage divider that reduces the CMOS level of the signal to one of approximately 1 2V in amplitude C18 and C19 provide wave shaping and impedance compensation to the signal before being output through RCA coax connector J8 This output network conditions the CMOS signal to standard S PDIF specifications J8 is protected from ESD by a spark gap Zone 3 Composite Video Output J7 accepts a composite video signal from the Video Board and passes it to the outside world J7 is spark gap protected Trigger Outputs Sheet 14 The RV 8 provides two 12V voltage sources for remote powering external accessories in the user s home theater Each trigger output can provide up to 1 Amp to an external load U8 is a low drop out adjustable regulator It is powered by 15V while it s output voltage is set by R15 and R16 follow
305. Three Channel Status RAM Table CTRL DATB is the transmit path to the three channel power amplifier Control data from the Host CPU is loaded into an internal 2x8 bit RAM that is in turn serially shifted out to the three channel amplifier board The only control data currently being transmitted is in the form of three ready acknowledge bits each of which activates a relay that places the speaker terminals into circuit with the amplifier outputs The following table illustrates the mapping of the internal RAM uem me s _ _ Ready control for channels 7 5 RDY CON 7 5 Three Channel Control RAM Table SER CLKB is the serial shift clock with which the control and status data are synchronous DATA LATCHB is the signal that latches control and status data into registers when a full byte of data has been transmitted or received 6 37 RV 8 Service Manual VCO Clock Control Signals MAIN PUMP UP MAIN PUMP DN MAIN LOCK MAIN PLL FPGA MCKO ZONE2 PLL PUMP UP ZONE2 PLL PUMP DN ZONE2 LOCK REC DAC SEL 1 0 ZONE2 FPGA MCKO AUDIO OSC The AVRX FPGA uses the output frequency of each VCO implemented on RV 8 as a 512FS master clock at 44 1 48kHz and a 256FS master clock at 88 96kHz Within the AVRX the incoming clock frequencies are divided by 512 or 256 and is phase compared to a corresponding frequency derived from the reference clock source This clock reference is derived from the S PDIF sample rate
306. UNLESS OTHERWISE SPECIFIED MOUNT ALL COMPONENTS FLUSH AND PERPEN 2 7 DICULAR 90 1 TO PCB 5 PCB ASSEMBLY TO BE PACKAGED IN A SFE REBEBEEE Su GIG STATIC SHIELDING FARADAY CAGE BAG GIGGGE can 62 THAT HAS AN ANTI STATIC NON CON mm ml for DUCTIVE INNER LAYER ALSO THE us DE ASSEMBLY IS TO BE PROPERLY PACKAGED En SIE TO PREVENT ANY DAMAGE DURING SHIP m pu E qm pres ENT ve RRs Cm 6 SOLDER LEXICON DOC JE Cel me xA us mm 030 1552T P Mi 435 7 BREAK PCB AND CUT EXCESS FLUSH WITH EB Ra RSS O EDGES THROW OUT BLANK MATE RIAL AFTER WAVE SOLDERING 45 C46 ge OL Jen 8 NUTS SUPPLIED WITH CONNECTORS MUST T m i BE BAGGED AND KEPT WITH PCB ASSY FOR USE DURING MECHANICAL ASSEMBLY u AN LABEL On EQUIVALENIT JUL 09 2004 UNLESS OTHERWISE SPECIFIED DIMENSIONS ARE IN INCHES CONTRACT NO C X C a TOLERANCES ARE FRACTIONS DECIMALS ANGLES 01 APPROVALS DATE PC BD MIC PREAMP RV8 005 7 i DRAWN MATERIAL meee ASSEMBLY DRAWING CHECKED che a 19 02 f10 15520 FINISH SIZE FSCM NO DWG NO REV NEXT ASSY USED ON ibi CW 8 26 02 D 80 15528 3 APPLICATION DO No SCALE DRAWING EP 8 16 02 SCALE 1 5 SHEET or Go 12 22 183
307. UT 4 5 U51 A A y 13 12 DG41 A5V VCC VDD 3 86 4 C8 6 C8 2 IN 1 p10 15V 5VD GND 4 5 05 13 12 peat y VCC VDD 45V L REC DACOUT 6 S4IN VEE GND 15V 5VD REC_DAC_OUT 4 5 U49 4 18002 DG411 15V VCC VDD 8 67 8 63 P REC DACOUT 16 pic 14 03 AD 75 GND 14 83 SEL 45 14 03 REC AD_DAC_SEL Y C375 100 REC A D CONVERTER R313 45VA 3 3VD 2 00K 1 7dB 5VA OdBFS 0 884Vrms soo REC INPUT LEVEL CONTROL a R312 8 033078 Es 5VA 100PF Ed 5 gt p 4 7 4 7 5 gt id R279 A U77 174W C411 C406 yp RAL 2 49K k Ai 2 1 5VA L C400 1 25 MES C318 5VA 2006 1804 ti N due se 4 ELI vp M 8343 BFS 2 0VI 1 25 MC33078 15 12 20263 ds EK 2 8 5 ANL OVEL AGNDL VA 47 16 197 i AINL OVFR 174 12 HALF 16 ju C403 il cest BYPAS 4 D5 5 D5 6 D4 8 B6 9 B6 10 C7 11 C7 12 C7 13 C7 14 B5 15 C5 SCLK 6 VD A o oe 5VA 47 0402 1942 VC 2 3 C321 C322 9376 2 dip FMT1 7 ze 6 C3 SDIN F 47 R310 C404 FMTO 4 D5 5 D5 6 C4 8 B7 9 C7 9 B7 14 B5 15 C5 gt SEU 2 68 DOND 5 1008 1 C409 8 1 25 6 4 05 5 05 6 04 9 07 14 83 MAIN_VG_ZCEN 1 ZCEN caor ii V
308. V 225mW SOT23 6 00 D43 44 66 67 89 90 300 16201 DIODESM ZENER 17V 225mW SOT23 6 00 D42 65 88 93 95 300 16202 DIODESM ZENER 16V 500mW SOD12 36 00 D45 46 68 69 91 92 300 16203 DIODESM RECT 400V 50A 50NS SMB 6 00 D37 38 60 61 83 84 300 16205 DIODESM SW 250V 625mA MELF 6 00 D28 33 51 56 74 79 310 10510 TRANSISTORSM 2N3904 SOT23 9 00 Q27 35 46 54 65 73 Q84 88 92 310 10565 TRANSISTORSM 2N3906 SOT23 6 00 Q34 53 72 83 87 91 310 16206 TRANSISTORSM NPN 25V 225mW SOT 3 00 Q81 85 89 310 16207 TRANSISTORSM NPN 300V 1W SOT 3 00 Q22 41 60 310 16208 TRANSISTORSM PNP 50V 350mW SOT 3 00 Q82 86 90 310 16209 TRANSISTORSM PNP 300V 1W SOT 3 00 Q23 42 61 310 16210 TRANSISTOR NPN 300V 1W TO92 9 00 Q28 29 37 47 48 56 Q66 67 75 310 16211 TRANSISTOR PNP 300V 1W TO92 9 00 Q24 25 38 43 44 57 Q62 63 76 310 16274 TRANSISTOR MJE15032 NPN TO220 3 00 Q26 45 64 310 16275 TRANSISTOR MJE15033 PNP TO220 3 00 Q12 14 330 15667 ICSM DIGITAL 74HCT594 SOIC 1 00 030 330 16215 ICSM DIGITAL 74HCT597 SOIC 1 00 U50 340 10552 ICSM LIN MC33078 DU OPAMP SOIC 3 00 U5 9 13 340 11045 ICSM LIN LM393 DUAL COMP SOIC 3 00 U7 11 15 340 11948 ICSM LIN LM339 QUAD COMP SOIC 3 00 U8 12 16 340 16219 ICSM LIN TLE2037 OPAMP SOIC 3 00 U6 10 14 410 16222 RELAY 1P2T 24V SEALED 3 00 K2 4 430 16223 LEDSM GRN 10MCD 1206 3 00 E2 4 440 15874 FUSE 5X20MM SLO BLO 12 5A 250V 2 00 F1 2 480 16225 THERMISTORSM NTC 20K OHM 0805 3 00 RT2 4 510 15694 CONN FFC 1 25MM 6 POS VERT 2 00 P1 2 510 15695 C
309. V 8 rear panel Test 1 Press the Mode button to run the test Verify the display indicates SERIAL PORT 1 PASSED SERIAL PORT 2 PASSED Press the Mode lt button Remove the two 2 RS 232 wrap around plugs when prompted by the RV 8 display Press the Mode 4 button to proceed to the next test 5 12 Lexicon IR Remote Test This test verifies that the unit can respond to infrared commands from the infrared remote Remote Setup 1 Setthe remote control to its default menu by pressing the HOME button The LCD display on the remote control should appear as in Figure A below 2 Press the top left MAIN button once to open the MAIN menu The LCD display on the remote control should appear as in Figure B below Figure A HOME MENU HOME MAIN ZONE2 ZONE3 TV DVD1 cD DVD2 PHONO MAIN Figure B MAIN MENU MAIN STAT M OFF TUNER TV DVD1 cD DVD2 PHONO PAGEL Note The RV 8 will NOT respond to the PAGE HOME FAV M1 M2 and M3 buttons 3 RV 8 Setup The front panel display should indicate IR REMOTE TEST Remote Test 5 13 RV 8 Service Manual Test 1 Press and hold the DVD2 button on the remote Verify the yellow IR ACK LED is blinking on the RV 8 front panel Verify the display indicates IR REMOTE TEST Remote Test 21 IR 4 Press Mode button to proceed to the next test Display Character Test This test verifies that the display on the unit can display the s
310. VALENT BOTTOM SIDE DESCRIPTION CHECKER AUTH 5 LEXICON BOM NO 023 15619 SUPERSEDES ANY INFORMATION ON THIS DRAWING PCB ASSEMBLY TO BE PACKAGED IN STATIC SHIELDING FARADAY CAGE BAG THAT HAS AN ANTI STATIC NON CONDUCTIVE INNER LAYER ALSO THE ASSEMBLY IS TO BE PROPERLY PACKAGED TO PREVENT ANY DAMAGE DURING SHIPMENT SOLDER PASTE MASK TOP SIDE PER LEXICON DOC NO 030 15507 JUL 22 2005 RELEASED COPY UNLESS OTHERWISE SPECIFIED DIMENSIONS ARE IN INCHES TOLERANCES ARE FRACTIONS DECIMALS ANGLES CONTRACT NO CX C O n APPROVALS DATE pC BD VIDEO IN BD RV8 201 005 DRAWN CW 8 6 02 ASSEMBLY DRAWING 710 15500 MATERIAL CHECKED CLC 8 14 02 sIZE FSCM NO NO REV USED ON FINISH RWH 8 14 02 B 080 155308 0 DO NO SCALE DRAWING SUED 8 15 02 SCALE 1 1 SHEET 1 OF 1 APPLICATION 2 Je J3 J4 5 REV DESCRIPTION DARE TER mm CHECKER AUTH NOTES LEXICON BOM 023 15620 SUPERSEDES ANY INFORMATION ON THIS DRAWING PCB ASSEMBLY TO BE PACKAGED IN A STATIC SHIELDING FARADAY CAGE BAG THAT HAS AN ANTI STATIC CONDUCTIVE INNER LAYER ALSO THE ASSEMBLY IS TO BE PROPERLY
311. VFD display light RED AMBER and BLUE In approximately three seconds verify the display indicates LEXICON When the LEXICON display appears within eight seconds press and hold the Zone 2 DVD2 and Zone 3 DVD2 buttons 4 The display indicates a display similar to the following Note that the BOOTROM revision date XX XX and time XX XX will contain valid digits LEXICON RV 8 BOOTROM 200X XX XX XX XX 5 Continue to hold the buttons for another seven seconds until the display indicates DIAGS MENU FUNCTIONAL TESTS RV 8 Service Manual FUNCTIONAL TESTS The automated Functional Tests will execute the suite of tests This takes approximately forty five seconds to complete When the automated Functional Tests have completed you will be prompted to perform certain tasks to complete the rest of the functional tests Setup Press the Mode button The display should indicate FUNCTIONAL TESTS START ALL TESTS Test Press the Mode button again to start the tests When the test has completed the front panel display should indicate RS232 WRAP TEST Insert Wrap Plugs RS232 Wrap Test This test verifies that the unit can communicate with the rear panel serial communication connectors Setup 1 Create two 2 RS 232 wrap around plugs by connecting pins 2 amp 3 of a female DB9 connector 2 Install the two RS 232 wrap around plugs onto the RS 232 1 and 2 ports located on the R
312. WISE INDICATED RESISTORS ARE 1 10W 2 UNLESS OTHERWISE INDICATED RESISTORS ARE 5 3 UNLESS OTHERWISE INDICATED CAPACITORS ARE UF V 4 DIGITAL ANALOG _L CHASSIS POWER 7 GROUND Y GROUND GROUND GROUND 5 LAST REFERENCE DESIGNATORS USED C5 D1 FB1 J1 L1 R1 Ut ENCE COPY 2003 Lexicon Inc CONTRACT Xi n NO e CO BEDFORD MA 01730 APPROVALS pate DRAWN 3 3 03 SCHEM VCO BD MCLK CHECKED 3 5 03 SEE CODE NUMBER REV Q C 060 16139 0 cw 3 7 03 FILENAME ISSUED KAB 3 11 03 16139 0 1 SHEET 1 OF 1 2 1 3 18 2003_9 15 BINDING POST FILTER BP1 ic P BP2 C1 C2 470 10077 T 470PF 100 REVISIONS DESCRIPTION DRAFTER CHECKER AUTH NOTES 1 DIGITAL ANALOG _L_ CHASSIS POWER 7 GROUND v GROUND 7 GROUND GROUND 2 LAST REFERENCE DESIGNATORS USED BP2 C2 3 COMPONENTS MARKED WITH ARE NOT INSTALLED REFERENCE COPY 2003 Lexicon Inc A 3 OAK PARK BEDFORD MA 01730 TITLE SCHEM SPKR EMI FILTER BD RV8 9 5 1 03 5 5 1 03 8 Q C 060 16189 e CW 5805 lEIENAME a 5 8 03 16189 0 1 sHEET 1 5 2 1 exicon Harman Specialty Group 3 Oak Park Bedford MA 01730 1413 USA Customer Service Telephone 781 280 0300 Service Fax 781 280 0499 www lexicon com Part No 070
313. When the writing is complete the corruption ceases and the image is stable Power and Control Interface Video board schematic sheet 10 J20 is the control and status interface to the host J18 supplies power from a connector on the main board The main video 5 volt rail is 5VV a filtered version of system 5VD which also supplies relay coils through FB4 The negative rail is 5VV derived from the main board 15VA by regulator U32 The video codec U34 and CPLD U14 are powered by 3 3V from regulator U24 6 55 CHAPTER 7 PARTS LIST PART NO DESCRIPTION QTY EFFECT INACT REFERENCE INFO Main Board Assembly 022 14458 PL MECH ASSY VCO MC12 B 2 00 J9 11 202 09794 RESSM RO 0 OHM 0805 1 00 R82 202 09795 RESSM RO 5 1 10W 2 2K OHM 5 00 R6 8 10 12 25 202 09871 RESSM RO 5 1 10W 1K OHM 1 00 R26 202 09874 RESSM RO 5 1 10W 2 2M OHM 4 00 R47 49 96 98 202 09894 RESSM RO 5 1 10W 1M OHM 1 00 R145 202 09899 RESSM RO 5 1 10W 47 OHM 4 00 R43 92 120 147 202 10557 RESSM RO 5 1 10W 4 7K OHM 10 00 R21 24 129 131 R154 156 177 202 10558 RESSM RO 5 1 10W 47K OHM 8 00 R5 7 9 11 41 42 R90 91 202 10559 RESSM RO 5 1 10W 100 OHM 2 00 R37 86 202 10585 RESSM RO 596 1 4W 51 OHM 6 00 R178 182 186 202 10599 RESSM RO 5 1 10W 3K OHM 1 00 R119 202 10836 RESSM RO 596 1 4W 1K OHM 5 00 R13 14 17 18 176 202 10946 RESSM RO 5 1 10W 3 3K OHM 1 00 R109 202 10949 RESSM RO 596 1 10W 1 2K OHM 10 00 R40 45 46 89 R94 95 110 113 202 11040 RESSM RO 5 1
314. X FPGA VERIFY 85232 WRAP TEST SHARC TESTS SHARC BOOT PAIR 0 1 SHARC SDRAM PAIR 0 1 SHARC WCLK PAIR 0 1 CS49400 TESTS BOOT TEST SHOW FLASH VERSION FLASH CHECKSUM TEST LOAD FLASH IR REMOTE VFD MEMORY TEST VFD CHAR TEST VFD BLOCK TEST 5 9 OSD TEST PAGE 0 11 SWITCH TEST LED TEST ENCODER TEST SET TRIGGERS TRIGGER 0 TRIGGER OFF ON TRIGGER 1 TRIGGER OFF ON AMP RELAY TESTS MAIN RELAY RELAY OFF ON CHANNEL 1 RELAY OFF ON CHANNEL 2 RELAY OFF ON CHANNEL 3 RELAY OFF ON CHANNEL 4 RELAY OFF ON CHANNEL 5 RELAY OFF ON CHANNEL 6 RELAY OFF ON CHANNEL 7 RELAY OFF ON ALL RELAYS RELAY OFF ON SET FAN TEST FAN SPEED 0 3 THERMOSTAT TEST AMP 1 7 HEADPHN INSERTION EXPANSION BRD TEST DIG RCVR LOCK TEST SHUT OFF HV AMP PWR SET CONSTANT CYCLE NORMAL OPERATION RV 8 Service Manual The repair diagnostic tests that are the same as in the power on diagnostic tests and functional diagnostic tests are not described here 5 10 Lexicon FUNCTIONAL DIAGNOSTICS DESCRIPTIONS Diagnostic Tests This section describes the RV 8 power on and diagnostics process Setup 1 Connect the RV 8 to 120VAC 220VAC for European model power source 2 Setthe rear panel power switch of the RV 8 to the 1 ON position AMBER LED Remote Command received RED LED A D Overload lexicon BLUE LED Powered on and activated Test 1 Verify the three LEDS at the right side of the
315. ZONE3 PHONO TO ANLG ZONE3 DIR VAR OUT FREQ LG ZONE3 PHONO IN TO ANLG ZONE3 DIR VAR OUT THD v lt i o Page 4 of 6 TEST PROC RV8 RV8 AUDIO ATE TEST SUMMARY 010 15834 A A Tests Analog Generator Analog Analyzer Switcher Module See Bal Gnd Typical Upper Lower Clock Sample Audio Test Name Note Left Right Freq Hz EQ Curve Z out Unbal Float Level Measure Reading Limit Limit Imp _ Bandwidth Filter B In A Out B Out Source Rate Source ANLG_MAIN_IN345_TO_ANLG_MAIN_DIR_OUT 4 00 Vrms 2 00 Vrms LG MAIN IN345 TO ANLG MAIN DIR OUT 3 80 Vrms 20 40k None 20 Unba Float 96 006 5 40kHz LP 1 2 3 4 13 14 15 16 3 4 5 5 13 14 15 15 Internal n a Analog LG MAIN IN345 TO ANLG MAIN DIR OUT S OFF None 20 gt 108 00 1 2 3 4 13 14 15 16 13 14 15 15 Internal Analog LG_MAIN_IN678_TO_ANLG_MAIN_DIR_OUT LG_MAIN_IN678_TO_ANLG_MAIN_DIR_OUT F 1 2 00 Vrms 2 00 Vrms 10 20 20 20k 20k 40k 20 Unbal dBr Leve lt 0 05 0 0 0 25 0 10 1 2 3 4 Internal n a LG MAIN 678 ANLG MAIN DIR OUT 3 80 Vrms 20 40k None 20 oat 40kHz LP 1 2 3 4 Internal ANLG MAIN 678 TO ANLG MAIN DIR OUT SNR 1 OFF OFF 997 None 20 Unba Float dBr Level gt 108 00 105 00 140 00 100k lt 10 gt 22 1 2 3 4 13 14 15 16 19 20 21 21 Internal n a Analog LG FRONT PHONO IN TO ANLG FRONT DI R OUT LG FRONT PHONO IN TO ANL
316. a jack on the Main Board via cable J20 sheet 10 Video Converter Video board schematic sheet 5 Composite or S video inputs can be decoded and converted to component analog video output in the Y Pb Pr format by video codec U34 U34 combines the functionality of a video decoder and encoder codec U34 accepts the selected main composite or s video source on two analog input pairs Al1 and Al2 is taken after the input amplifiers but before the OSD while AI2 is subject to the OSD Within 034 the inputs are dc restored and converted to digital form for decoding The decoded digital video is passed via the PDn bus to the encoder portion of the codec to be re encoded The encoder incorporates 3 d a converters for producing Y Pb Pr component analog video The analog outputs from the encoder are filtered and buffered by U4 and U3 sheet 6 The dc level of the Y component is biased to place the back porch around OVdc and the dc level of the Pb and Pr components is biased to place the 0 color 6 52 Lexicon difference level around 0Vdc The converted input video is introduced into the component video relay tree and is a selectable output just as any Y Pb Pr component input The encoder within U34 produces the complete video waveform for normal NTSC or PAL video inputs However during trick modes of VCR playback pause shuttle the sync portion of the video is derived from a logic signal HVSYNC CPLD U14 detects trick modes based on anomalie
317. a point where output devices are just out of conduction This provides the AB B mode of operation for the output stage Bias voltage is measured across R25 30 and is set to 0 350Vdc 0 01 25 degrees ambient 6 1 RV 8 Service Manual Amplifier Operation At the heart of the amplifier is a high performance error amplifier 02 TLE2037 From the error amp audio signals move through the voltage translators and on to Q7 MJE15032 and Q11 MJE15033 Q7 and Q11 form current gain cells which feed the paralleled main output devices MJ21194 NPN MJ21193 PNP The main output devices are connected in an emitter follower configuration The devices are mounted directly to the heatsinks with no insulator which means the heatsinks are at rail potential 70Vdc Frequency Response The frequency response of the amp module is set by several components The dominant pole of the amplifier is set by R10 and C5 at approximately 145kHz All of the stages prior to the power amplifier stage also contribute to the high frequency roll off of the amplifier Amplifier Feedback Resistor R12 47 5 and capacitor C8 22pF provide a local high frequency roll off for the error amp The error amp also receives split feedback signals from two points at the output C23 0 33uF provides high frequency feedback through the output inductor L1 1 5uH while R58 107 provides low frequency feedback which negates the DC resistance effects of the output inductor R10
318. address decoded signal provided by the CPLD on sheet seven of the schematic Refer to the Programmers Guide Revision 6 for further details regarding address decoding and bit field definition The test LED signals are also broken out to a row of test pads represented by J10 RESET Buffer U45 U48 provides a buffered equivalent of the RESET signal to the FPGA and to off board components on the Front Panel PCB the Amplifiers and the Video PCB All reside within the 5 Volt domain Proprietary Algorithm DSP 1 and 2 Host Interface Sheet 3 This sheet contains the system clock generator spread spectrum generator and the host interface and configuration blocks of both SHARC engines Clock Generator and Buffers U46 and U47 U47 is a standard Hex Inverter of which one stage is configured as a Colpitts Oscillator comprised of Y2 R165 C159 and C160 This circuit generates a 12 500MHz square wave at CMOS levels R165 provides hysteresis for the gate initiating and sustaining a reliable switching characteristic while C159 and C160 provide the proper AC load to the reactive element of Y2 The second stage of this circuit is another gate from the hex package that simply buffers the output of the oscillator presenting a minimal load to it while providing drive capability Final buffering to the remainder of the 5V domain of this board is provided by yet another gate from U47 while buffering to the 3 3V domain is provided by U46 Spread Spectr
319. al S PDIF Record Zone output e One Composite Video Zone 3 output Two remote power outputs Two Phase Locked Voltage Controlled Oscillators for master audio clock generation Rremote control sensing and discrimination from the front panel and Zone Two e Canned Algorithm Surround Processing via a single Crystal Semiconductors DSP engine e Lexicon specific supplemental DSP via two Analog Devices SHARC DSP engines START UP CONDITIONS Power On and Boot Procedure Once the unit is powered up the reset generator U31 provides both active low and active high reset signals of approximately 3ms duration During this interval the CPU processor U33 is held in an inactive state as well as the three DSP engines and the FPGA This reset is also passed along to all of the remaining boards in the system Once this reset interval has passed the processor and FPGA are ready for further instruction The DSP engines remain in reset however and are not released from this state until commanded by the system software The CPU then begins booting from the on board 1Mx16 Flash 026 Diagnostic testing is run on the on board DRAM 042 If the test passes test LED D10 will light it will flash if the test fails The bulk of the boot and application software is then loaded from the Flash into this DRAM and a checksum test is performed If this test passes test LED D11 will light flash if the test fails Internal registers of the processor device are the
320. al amplifier to a pair of speakers 3 Power on the external amplifier Slowly increase the volume on the external amplifier to a comfortable listening level 4 Sweep the oscillator from 20Hz to 20kHz Verify that clean undistorted audio can be heard throughout the frequency sweep 5 Power down the external amplifier 4 12 Lexicon Phono Input to Digital Outputs This test will verify the audio path between the left and right Phono inputs and the Zone 2 S PDIF coaxial and optical digital outputs Setup 1 Connect the video monitor to the main composite output of the RV 8 and turn the monitor on This will allow full viewing of the RV 8 s menus Connect the S PDIF coaxial digital output on the RV 8 rear panel to the digital record input jack of the DAT machine Connect the left and right analog outputs of the DAT machine to the analog left and right inputs of an external amplifier Connect the outputs of the external amplifier to a pair of speakers Turn on the RV 8 using the main power switch on the rear panel Once the unit is in standby mode press the front panel standby button or the remote control POWER button to enter normal operation Test 1 Connect the low distortion oscillator output to the left and right phono inputs on the rear panel of the RV 8 Connect the S PDIF coaxial digital output on the RV 8 rear panel to the digital record input jack of the DAT machine Connect the left and right analog
321. ame character on every pixel Test 1 Verify the display indicates 2 Turn the encoder knob clockwise until the display indicates BBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBP 3 Turn the encoder knob counter clockwise until the display indicates 00022222222222222222 5 Press the Mode button to proceed to the next test Display Block Test This test verifies that the unit can display all the pixels in one block at a time Test 1 Verify the display has one block lit with no missing pixels in the top left corner of the display 2 Turn the encoder knob clockwise until all forty blocks have been displayed Note The blocks along the top row will be lit first followed by the blocks on the bottom row If the knob is continuously turned clockwise the block lighting pattern will repeat 3 Press the Mode lt button to proceed to the next test Switch Test This test verifies the operation of each of the twenty two front panel switches During the test the LED associated for each switch pressed will light and remain lit until another switch is pressed Setup The front panel display should indicate SWITCH TEST SwTst None pressed 5 14 Lexicon Test 1 Press each switch and that front panel display indicates the correct for the switch Standby STANDBY Mode Left LEFT MO
322. amplifier Switch the RCA cables from the Zone 2 RCA Fixed output to the Zone 2 RCA Variable outputs and repeat steps 5 through 8 10 The above procedure should be repeated to test S PDIF coaxial digital inputs 2 through 4 as well as the optical inputs 1 to 4 To do this repeat the procedure changing the Input Test selected in step 4 to the next appropriate input Move the output of the CD player to the appropriate RV 8 input that corresponds to the input selected in the AUDIO I O TEST menu When testing the optical inputs be sure to use the appropriate digital cable RV 8 Service Manual Digital Inputs To Zone 3 Outputs Test This test will verify the audio path between the RV 8 S PDIF coaxial digital input 1 to the Zone 3 RCA analog outputs Note This test requires the use of a CD player as a source The tests to follow will be run using a PCM signal at a 44 1kHz sample rate Test 1 Connect the S PDIF coaxial digital output of the CD player to the S PDIF coaxial digital input 1 on the RV 8 rear panel Connect the S PDIF optical digital output of the CD player to the S PDIF optical digital input 1 on the RV 8 rear panel 2 Connectthe Zone 3 RCA left and right Fixed outputs of the RV 8 to the external amplifier left and right inputs Connect the outputs of the external amplifier to a pair of speakers Using the Menu arrows scroll through the Diagnostics Menu and select the AUDIO I O TESTS 4 Inthe AUDIO I O
323. ance Use a soft lint free cloth slightly dampened with warm water and a mild detergent to clean the exterior surfaces of the unit Do not use alcohol benzene or acetone based cleaners or any strong commercial cleaners Avoid using abrasive materials such as steel wool or metal polish It the unit is exposed to a dusty environment a vacuum may be used to remove dust from the unit s exterior Ordering Parts When ordering parts identify each part by type board assembly location component location price and HSG Lexicon Part Number Replacement parts can be ordered from Harman Specialty Group 3 Oak Park Drive Bedford MA 01730 1441 Telephone 781 280 0300 Fax 781 280 0499 email csupport harmanspecialtygroup com ATTN Customer Service Returning Units to HSG Lexicon for Service Before returning a unit for warranty or non warranty service consult with HSG Lexicon Customer Service to determine the extent of the problem and to obtain Return Authorization No equipment will be accepted without Return Authorization from HSG Lexicon If HSG Lexicon recommends that a RV 8 be returned for repair and you choose to return the unit to HSG Lexicon for service HSG Lexicon assumes no responsibility for the unit in shipment from the customer to the factory whether the unit is in or out of warranty All shipments must be well packed using the original packing materials if possible properly insured and consigned prepaid to a reliable
324. ance with the specification The equivalent resistor is already populated on the Video Board and hence is not needed here CVID ZONS is a composite video analog signal that is sourced from a video selector that selects between one of five composite inputs or one of five S VIDEO inputs on the rear panel Amp Power Supply Connector J27 J27 is a 6 position FFC connector that provides enable controls for the Amplifier Power Supply Board Relays that activate the power amplifiers This connector also provides a BROWN OUT signal to the Host CPU where it is monitored as a Non Maskable Interrupt NMI Provision is made to use conventional ribbon cable for board interconnect via J28 but to date is not used in this design SOFT RLY is a signal that is activated from the external registers on sheet 2 This signal enables a current limited supply voltage to the power amplifiers during the final stages of boot up During this phase of the boot process readiness status is queried of each of the amp channels by the Host This relay signal returns to the inactive state if a problem is found within the amplifier blocks and also when the power supply has stabilized and current limiting on the supply rails is no longer necessary MAINS RLY is a signal that is also activated from the external registers on sheet 2 This signal enables the full supply to the amplifiers once the state of the amplifier channels are known to be good This relay activates before the
325. and C5 provide overall feedback for the amplifier Time Dependent VI Limiting For simplicity the positive side current limit is described below The negative side current limit operates in a similar fashion Current Limiting The output current of the amplifier is sensed across emitter resistors R26 0 68 R27 0 68 R169 0 68 and R173 0 68 This information is summed via R342 23 2k and R343 23 2k then divided down by R344 1 82k and R345 100k The divided voltage information is fed into the base of Q77 KST5089 Once the voltage across R344 and R345 reaches approximately 0 65Vdc Q77 turns on which causes Q79 MMBT3906 to turn as well This redirects current coming from Q5 and through 012 13914 and Q79 to the output thus limiting the amount of current driven into the base of Q7 Time Dependency C157 4 7uF provides time dependency to the current limit When no current is flowing through the emitter resistors C157 has no charge When current suddenly flows through the emitter resistors C157 is seen basically as a short which essentially eliminates R345 from the limiting circuitry As C157 charges the current is limited more and more until it reaches a steady state Voltage Information D1 1N914 and R129 365k provide the voltage information to the circuitry As the output voltage of the amplifier increases more current is pulled through R342 R343 R344 and R345 causing the voltage differential across pin
326. ble below and on the next page 2 When all LEDs have been lit press the Mode 4 button to proceed to the next test LED Color BLUE YELLOW Main DVD1 BLUE BLUE BLUE BLUE BLUE BLUE BLUE BLUE Main Sat Main TV Main Tuner Main DVD2 Main VCR Main CD Main Phono Main OFF EET Zone2 DVD1 YELLOW Zone2 SAT Zone2 TV Zone2 Tuner Zone2 DVD2 Zone2 VCR Zone2 CD Zone2 Phono Zone2 OFF N I N G a 2 zx co olo 5 16 Lexicon Zone3 CD Zone3 Phono Headphone Insert Test This test verifies that the RV 8 can detect the presence of headphones plugged in to the front panel Phones jack Setup The front panel display should indicate HEADPHN INSERT TEST HDPhones OUT Test 1 Inserta 1 4 inch headphone plug into the Phones jack on the RV 8 front panel and verify that the display indicates HEADPHN INSERT TEST HDPhones IN 2 Remove the 1 4 inch headphone plug from RV 8 front panel Phones jack 3 Press the Mode lt button to proceed to the next test RV 8 Service Manual Temperature Test This test verifies the temperature measurement circuits in the RV 8 Test 1 Verify the display indicates the temperature of Amp1 xx approximately 30 40 C TEMP TEST AMP1 xx degC 2 Rotate the encoder knob slowly clockwise and verify that the temperature measurements for Amp2 through Amp7 are within 30 40 C Note The
327. by R244 C173 before buffering in order to meet the minimum width necessary for the OSD chip Sections of U42 and the network formed by R243 R242 D11 and C172 form pulses that are aligned with video back porch These pulses switch U40 which in combination with integrator U41 forms a sample and hold circuit that closes the feedback loop around the input video amplifier during back porch time This acts to maintain the back porch level at OV D10 limits the negative going output of U41 in order to minimize the undesirable effects of unusual sync patterns inherent in the macrovision video copy protection scheme Additional logic within 039 detects the presence of a valid video input SYNC DETECT is fed to the main board for use in OSD management The sync stripper 039 is susceptible to small variations on its power supply and so it is specially powered from a dedicated 5V regulator U29 With video input absent OUT free runs at around 15kHz 6 54 Lexicon Video Control Registers Video board schematic sheet 8 Control registers are implemented within CPLD U14 through a serial interface The serial clock and data are VIDEO_SCLK and VIDEO_DATA shared in common with the OSD A transfer is initiated by a pulse on VIDEO REG followed by a burst of clock and data that update all 56 control register bits within the CPLD in approximately 4 5 sec All control bits are initialized to 0 at power up by VIDEO RST Logic within the CPLD der
328. cation via the front panel e Radio Data Stream decoding RDS e I nter station noise muting Overall Design Theory The entire design of the Tuner Board fits on one schematic sheet Each functional block is discussed separately Antenna Input J1 The antenna connectors comprise separate inputs for AM and FM The AM terminals are standard thumbscrew types that will accept twin lead cabling such as found on the antenna included as an accessory shipped with the RV 8 FM is brought into the tuner via a 75 ohm F type connector FM signals may be provided to the tuner via cable television service or with the use of a 75 300 ohm Balun transformer and a Y style twin lead antenna The signals are mixed down to a single path into the UT1384 tuner module by inductor L1 which provides a low impedance path for AM signals and C1 which provides a low impedance path for FM signals The entry point into the tuner module acts as a 6 48 Lexicon voltage summing node The common side of each antenna terminal is tied directly to the rear panel chassis via LUG1 Tuner Module U4 The heart of the design is the Microtune UT1384 Tuner module This device provides all RF descrimination and provides as outputs AM program material in analog audio format multiplexed FM program material in the form of an analog signal and Radio Data Stream RDS material in the form of an analog signal The RDS output provides both RDS data and multiplexed FM material on the
329. ch sector is erased automatically prior to writing Writing occurs when the WE and CE pins are low and OE is high Main FPGA Sheet 9 This page contains the AVRX FPGA which performs many salient functions to the main board It is packaged in a 208 pin QFP package The AVRX FPGA converts and routes various digital audio formats among the system I O connectors and DSP processors and has Serial Peripheral Interface SPI ports that provide the means for the host processor to communicate to the system peripherals It also has an 12C interface for host communication to the video codec and it has interfaces for the IR remote control and rotary encoder AVRX U41 Functionality is implemented within a Xilinx 25200 device This device contains 200 000 logic gates 75 264 bits of distributed RAM and 56K bits of block RAM 2 5V for core operation and 3 3V for IO operation powers it The FPGA may be configured either by the system software during the boot phase or by a 128K serial FLASH PROM during development Configuration Resistors R157 and R158 select the programming mode of the FPGA The default condition with R158 installed and R157 uninstalled configures the device as a slave operating in serial mode In this operating mode the programming data is loaded into the device via the DIN DATAO pin 153 with the rising edge of the signal appearing at the CCLK pin 155 The host processor provides both signals In the alternative scheme R15
330. ction algorithms Microphone Inputs The circuitry here supplies power 9 volts to an external microphone capsule and performs balanced to unbalanced conversion and amplification The input op amp is protected from the common mode phantom power by 10uF input capacitors and an inductor capacitor RFI filter network This op amp is unity gain and rejects common mode noise from a differential microphone signal The second op amp amplifies the signal by 25 5dB A diode network prevents microphone accidents from creating a large signal that could clip the muxes on the analog board A 100 ohm resistor pair isolates the output from reactive loads Microphone Phantom Power Supply Power is pulled from the 15V supply and regulated down to 9 volts by a voltage regulator Diode D8 prevents back biasing the regulator when 15V is removed An RC filter is created by 330 ohms and 10uF The 2 2K resistors provide current limiting and define the input impedance that the microphone sees at the input of the amplifier RV 8 TUNER BOARD THEORY This section provides a detailed description of the design theory embodied in the RV 8 Tuner Board Each section of this document will discuss the theory of each functional subset of this board and will reference a schematic sheet for each block The schematic set being referenced is at a minimum revision level of 1 The RV 8 Tuner Board incorporates the following features e AM Stereo decoding Station identifi
331. d Assembly 202 09795 RESSM RO 5 1 10W 2 2K OHM 1 00 R77 202 09871 RESSM RO 5 1 10W 1K OHM 13 00 R4 11 17 85 88 108 R111 113 139 239 R241 244 202 09873 RESSM RO 5 1 10W 10K OHM 13 00 R84 107 136 146 170 R214 225 230 231 243 R247 249 250 202 09874 RESSM RO 5 1 10W 2 2M OHM 1 00 R240 202 09894 RESSM RO 5 1 10W 1M OHM 2 00 R75 232 202 09899 RESSM RO 5 1 10W 47 OHM 4 00 R79 80 224 226 202 10426 RESSM RO 5 1 10W 15K OHM 18 00 R20 28 114 117 R141 144 153 154 R194 197 216 202 10557 RESSM RO 5 1 10W 4 7K OHM 4 00 R81 83 147 202 10558 RESSM RO 5 1 10W 47K OHM 1 00 R78 202 10571 RESSM RO 5 1 10W 100K OHM 9 00 R134 135 167 168 173 R193 203 206 248 202 10573 RESSM RO 5926 1 10W 470K OHM 11 00 R37 47 56 65 74 191 219 223 202 10943 RESSM RO 5 1 10W 22K OHM 3 00 R246 254 255 202 10945 RESSM RO 5 1 10W 1 5K OHM 1 00 R251 202 10946 RESSM RO 596 1 10W 3 3X OHM 15 00 R30 35 40 45 49 54 R58 63 67 73 87 R110 138 227 238 202 10947 RESSM RO 5 1 10W 680K OHM 1 00 R245 202 10948 RESSM RO 5 1 10W 390 OHM 1 00 R252 202 10949 RESSM RO 5 1 10W 1 2K OHM 1 00 R76 202 11042 RESSM RO 5 1 10W 6 8K OHM 4 00 R119 121 148 150 202 12369 RESSM RO 5 1 10W 36K OHM 6 00 R131 133 166 169 R202 207 202 13579 RESSM RO 5 1 10W 22 OHM 10 00 R31 36 41 46 50 R55 59 64 68 72 202 16144 RESSM RO 5 1 10W 12 OHM 1 00 R228 203 10560 RESSM RO 196 1 10W 75 0 OHM 32 00 R29 32 39 42 48 51 R57 60 66 69 89 92 R94 95 97 100 101 R104 106 115 116 118 R120 142
332. d convertors Heat generated by the 5V regulator is dissipated by a heatsink Two voltage regulators create the 5VR supply from the 15V rail The first regulator regulates to about 10V and the second regulates to 5V 5 is an alternative clean 5 volt supply used by the A D and D A converters Six DG411 switches select either front L R or either of the two zones as a source for the headphones A high current op amp with 12dB of gain drives the headphone output at J25 A high impedance headphone presence detector is shunted to relay ground or the 10K output impedance by a normalling switch in the socket and is pulled high when a jack is inserted 6 8 Lexicon RV 8 MAIN BOARD THEORY This section provides a detailed description of the design theory embodied in the RV 8 Main Board Each section of this document will discuss the theory of each functional subset of this board and will reference a schematic sheet for each block The schematic set being referenced is at a minimum revision level of 6 The RV 8 Main Board incorporates the following features e Command and control of the entire RV 8 system e Digital audio inter system routing FPGA e Front Panel display control button monitoring and LED display control Two expansion ports Amplifier environmental and power monitoring and control e User and debug access via two RS 232 serial ports e Four coaxial and four optical S PDIF input ports e One coaxial and one optic
333. dB typical 520 to 1720kHz lt 8uV typ 4uV 0 5696 0 32 typical 1kHz 60dBmV 30 mod gt 80dBmV Lexicon Phono Performance MM Frequency Response 50Hz to 20kHz 0 5dB rumble filter 4dB at 10Hz THD Noise Below 0 02 20Hz to 20kHz 4 7mV input Signal to Noise Ratio 72dB minimum Compatible Amplifier Connectors Banana Plugs Standard 0 75 inch plugs Spade Connectors Size 10 12 gauge Bare Wire Up to 10 gauge bare wire Specifications are subject to change without notice 3 5 3 6 RV 8 Service Manual Lexicon CHAPTER 4 FUNCTIONAL VERIFICATION PERFORMANCE VERIFICATION This section describes a quick verification of the operation of the RV 8 and the integrity of its analog and digital audio signal paths Dangerous voltages capable of causing death are present in this unit Use extreme caution when handling testing or adjusting INITIAL INSPECTION Inspect the RV 8 for obvious signs of misuse abuse or neglect With the power off verify that all switches operate smoothly With the power off and AC cord disconnected remove the RV 8 top cover Verify that all cables are correctly installed and are securely fastened Check for burnt or obviously damaged components ou p ON Check the voltage select connector for the primary windings of the power transformer for the analog power supply J14 220VAC J15 120VAC Put the cover back on N Connect the AC cord Using the main power switch
334. dBr 20 2 20 2 and 0 10dBr to 0 8dBr 20 2 40 2 of reference level over the entire sweep Note these levels 4 19 RV 8 Service Manual Signal to Noise Test SNR 1 Using the signal level from step 5 of the Frequency Response Test above turn off the oscillator and verify a noise level measurement lt 102dBr 2 This procedure should be repeated to test Analog Inputs 2 through 8 To do this move the cable from the output of the Low Distortion Oscillator to the next pair of inputs and repeat the tests above to test the remaining Main Zone RCA outputs Analog Audio Inputs to Amplifier Outputs Tests This test will verify the specifications of the Analog RCA inputs to the amplifier outputs Setup 1 Connect an audio cable between the output of the Low Distortion Oscillator and the RV 8 Left RCA input 1 2 Connect audio cable between the front left amplifier output of the RV 8 and the input of the Distortion Analyzer Using the Menu arrows scroll through the Diagnostic Menu and select the AUDIO I O TESTS In the AUDIO I O TEST menu highlight AUDIO INPUT 1 TEST Press the Menu arrow on the RV 8 remote control to engage the test The RV 8 is now set to route audio from the left and right RCA inputs labeled 1 to all amplifier outputs Gain Test GAIN 1 Apply a 1kHz signal 1Vrms to the RV 8 Left RCA analog input 1 2 Setthe scale on the Distortion Analyzer to measure 8Vrms signal level 3 Tur
335. ds Each successive 256 word page is accessed by bank switching The memory device itself is non linear as access is defined by row column address multiplexing The SDRAM addressing scheme is implemented via a 10 bit wide address bus The mapping is defined as Column Address A 7 0 Row Address A 10 0 Each 256 word page is accessed across four banks with each bank selected by two bits BA 1 0 The SHARC devices contain a memory interface controller which multiplexes an array of internal address bits into the row column scheme illustrated above An integral part of the address muxing is the 6 18 Lexicon incorporation of the bank bits within the address space The following table illustrates the internal to external address multiplexing SHARC DSP Internal to External Address bit mapping Row Address Bank Bits Column Address Memory access is contiguous with this scheme The following diagram illustrates how each 256 word page is interleaved in relation to the internal address Memory Interleave Diagram 0 000000 OxOOOOFF 0x000100 0x0001 FF 0 000200 OxOOO2FF 0 000300 0x0003FF 0 000400 OxOOOAFF Ox000500 OxOOO5FF 0 000600 OxOOOGFF 0x000700 Ox0007FF I4 1024 Words M 1024 Words gt Ox1FFCOO OxiFFCFF Ox1FFDOO OxiFFDFF Ox1FFEOO0 OxiFFEFF Ox1FFFOO OxiFFFFF Bank O Bank 2 Bank 3 4 1024 Words
336. e LED data is written to a RAM buffer internal to the FPGA and is transmitted up to the front panel at a bit rate of 1MHz SDATA CLK is the clock signal that controls the serial shift of data up and back from the front panel FP SDATA LTCH is a signal that marks the beginning of an eight bit sample being transmitted to the front panel This four wire interface works in conjunction with an FPGA on the front panel PCB Refer to the theory of operation for this board for further details FP ENCA IN and FP ENCB comprise a two wire quadrature signal from the rotary encoder on the front panel The direction of rotation of the encoder is determined by the relative position of a rising edge on FP compared to FP ENCA IN When the encoder is rotated clockwise the rising edge of FP ENCB occurs during a high cycle of FP ENCA IN When the encoder is rotated counter clockwise the edge occurs during a low cycle The AVRX FPGA debounces the signals from the rotary encoder and uses the debounced signals to control a four position Gray Code counter This counter can be read by software to determine the position of the encoder 6 31 RV 8 Service Manual Digital Audio Signals SPDIF_COAX_IN 4 1 SPDIF_OPTO IN 4 1 DIG REC OUT Provision is made within the RV 8 for eight S PDIF inputs four from coaxial sources and four from optical fiber sources The coax sources are signal conditioned and buffered prior to being routed to the
337. e packaged in a 255 position Ball Grid Array The IO pins on these devices are not 5 volt tolerant necessitating the level shifters on sheet 2 of this schematic set These DSP devices are responsible for proprietary signal processing such as Bass Management Room Equalization and LOGIC7 Surround Decoding These blocks represent the sections of the Proprietary Algorithm DSPs that configure their default operation Clock and Configuration Device Pins CLKIN P12 XTAL R13 CLKOUT R9 CFG 1 0 N12 13 CLKDBL R12 The DSP devices each have a clock input of 12 500 MHz as provided by buffer gates U46 The clock input pins CLKIN are impedance matched by R161 and R162 Since this topology uses an external oscillator rather than a crystal the XTAL pins on each device are left floating and unused The core clock frequency is derived from this input clock by internal PLL circuits The PLLs are configured for X4 operation by the CFG 1 0 pins by hardwiring them to a binary value of 10 setting the core frequency to 50MHz This core frequency is then further multiplied by two by hardwiring the CLKDBL pin to a logic 0 This makes the final core frequency 100MHz The CLKOUT pin on each device connects to a test point ACKO or BCKO depending upon which DSP device is of interest The clock signals appearing here are 2X the input clock or 25 00 MHz Interrupt Requests Device Pins IRQ2 J1 IRQ1 IRQ0 H2 The ADSP21161N has
338. e as well as the Zone 3 section of the front panel 10 Slowly increase the volume on the amplifier to a comfortable listening level for the speakers 11 Sweep the oscillator from 20Hz to 20kHz 12 Verify that clean undistorted audio can be heard from the Zone 3 audio outputs of the RV 8 13 Once complete repeat steps 1 12 to test Analog Inputs 2 through 8 to the audio output of Zone3 Change the DVD1 ANALOG IN selected in step 6 to the next appropriate input 4 9 RV 8 Service Manual Analog Inputs to Digital Outputs Test This test will verify the audio path between the paired analog inputs 1 to 8 to Zone 2 digital outputs Setup 1 Connect the video monitor to the main composite output of the RV 8 and turn the monitor on This will allow full viewing of the of the RV 8 s menus 2 Connect the S PDIF coaxial digital output of Zone 2 the RV 8 rear panel to the digital record input jack of the DAT machine 3 Connect left and right analog outputs of the DAT machine to the analog left and right inputs of an external amplifier Connect the outputs of the external amplifier to a pair of speakers Turn on the RV 8 using the main power switch on the rear panel Once the unit is in standby mode press the front panel standby button or the remote control POWER button to enter normal operation Test 1 To enter the MAIN MENU press the remote control Menu arrow 2 Scroll through the MAIN MENU using the Menu arrow
339. e gasses or fumes Operation of any electrical instrument in such an environment constitutes a definite safety hazard KEEP AWAY FROM LIVE CIRCUITS Operating personnel must not remove unit covers Qualified maintenance personnel must make component replacements and internal adjustments Do not replace components with the power cord connected Under certain conditions dangerous voltages may exist even with the power cord removed To avoid personal injuries always disconnect power and discharge circuits before touching them DO NOT SERVICE OR ADJUST ALONE Do not attempt internal service or adjustment unless another person capable of rendering first aid resuscitation is present DO NOT SUBSTITUTE PARTS OR MODIFY INSTRUMENT Because of the danger of introducing additional hazards do not install substitute parts or perform any unauthorized modification to the unit DANGEROUS PROCEDURE WARNINGS Warnings such as the example shown below precede potentially dangerous procedures throughout this document Instructions contained in warnings must be followed Dangerous voltages capable of causing death are present in this unit Use extreme caution when handling testing or adjusting Atos ELECTROSTATIC DISCHARGE ESD PRECAUTIONS The following practices minimize possible damage to circuit boards resulting from electrostatic discharge or improper insertion Keep circuit boards in their original packaging until ready for use Avoid havi
340. e remote control POWER button will bring the RV 8 out of standby mode No diagnostics are run when the unit is brought out of standby DIAGNOSTICS USER INTERFACE Various combinations of button pushes are used to control diagnostic activity The table below summarizes the options available followed by more detailed descriptions Action Buttons to be Held Enter Diagnostics ZONE2 DVD2 amp ZONE3 DVD2 Restore Defaults MODE RIGHT Waiting For Download MODE RIGHT amp ZONE2 DVD2 amp ZONE3 DVD2 To enter extended diagnostics via front panel 1 Press and hold the front panel ZONE2 DVD2 and ZONE3 DVD2 buttons when powering on a RV 8 2 Continue to hold both buttons until the DIAGS MENU appears on the front panel display This operation normally takes approximately thirty seconds to complete To enter extended diagnostics via serial debug port Type debug when connected to the serial port to access the debug program The debug program is case sensitive In addition the extended diagnostics can also be entered by sending stands for extended diagnostics to the unit via the serial debug port during the first ten seconds after powering on the unit For more information see the section on the Serial Debug program 5 1 RV 8 Service Manual To restore factory default settings 1 Press and hold the front panel Mode button while powering on the RV 8 to restore the factory default setti
341. e scale on the Distortion Analyzer to measure 1Vrms signal level Using the output level from step 4 of the Gain Test set the Distortion Analyzer for a 0dB reference to check frequency response of the RV 8 Turn the filter on the Analyzer off Sweep the oscillator frequency from 10Hz to 100kHz Verify the signal levels are 0 10dBr to 0 5dBr 10 20Hz 20kHz 0 10dBr to 0 2dBr 20Hz 20kHz 0 10dBr to 0 5dBr 40kHz and 0 10dBr to 3 0dBr 100kHz of reference level over the entire sweep 4 21 RV 8 Service Manual Signal to Noise Test SNR 1 Using the signal levels from step 5 of the Frequency Response Test turn off the oscillator and verify a noise level measurement lt 105dBr This procedure should be repeated to test Analog Inputs labeled 2 through 8 To do this move the cable from the output of the Low Distortion Oscillator to the next pair of inputs and repeat the tests above to test the remaining Main Zone RCA outputs Repeat the above tests for the remaining Main Zone amplifier outputs VIDEO INPUT OUTPUT TESTS These tests will verify that all thirteen video inputs and ten video outputs pass video There are three different video paths to be tested in the RV 8 composite S video and component Composite paths have five inputs and five outputs S video paths have five inputs and four outputs Component paths have three inputs and one output The following tests will verify that the RV 8 is passing clea
342. ear L R Repeat steps 5 through 7 to test Analog Inputs 2 through 8 Change the INPUT TEST selected in step 4 to the next appropriate input Switch the Oscillator outputs to the RV 8 input that corresponds to the input selected in the AUDIO TEST menu Analog Inputs to Amplifier Outputs Test This test will verify the audio path between the paired analog inputs labeled 1 to 8 and all analog amp output channels Test 1 10 11 Connect the low distortion oscillator output to the left and right analog audio inputs labeled 1 on the rear panel of the RV 8 With the RV 8 powered off connect the RV 8 amplifier front left and front right outputs to the pair of speakers Power on the RV 8 Using the Menu arrows scroll through the Diagnostics Menu and select the AUDIO I O TESTS In the AUDIO I O TESTS menu highlight the AMP TEST Press the remote control Menu arrow to engage the test The RV 8 is now set to route audio from the left and right analog inputs labeled 1 to all amplifier outputs Using the volume knob on the front panel of the RV 8 slowly increase the volume to a comfortable listening level Sweep the oscillator from 20Hz to 20kHz Verify that clean undistorted audio can be heard throughout the frequency sweep Lower the volume of the RV 8 Power off the RV 8 and carefully disconnect the front left and front right speaker wires from the RV 8 amplifier outputs and connect them to the side left and side right
343. ect it by pressing the Menu arrow The ON SCREEN DISPLAY menu will open with the STATUS parameter highlighted Select the STATUS parameter by pressing the Menu arrow and change the value of the parameter to ALWAYS OFF Press the Menu 4 arrow to exit the menu structure The video path is now set for testing Test 1 2 3 4 Load disc into the DVD player and press play Verify a clean undistorted picture appears on the monitor Pause the DVD player To test the three remaining S video outputs other Main Zone output and the Zone 2 outputs switch the S video monitor output cable on the back of the RV 8 to the next main S video output connector and press play on the DVD player Repeat the above procedure for the two Zone 2 S video outputs To test the remaining S video inputs 2 through 5 reconnect the S video output cable to the first main S video output In steps 13 and 14 of the above Setup procedure change the VIDEO IN parameter from S VIDEO 1 to S VIDEO 2 Repeat steps 1 to 3 of this test procedure Repeat Step 7 above to test the remaining RV 8 S video inputs 3 through 5 Component Video Input to Component Video Output Test This test will verify the component video switching function of the RV 8 Setup c Connect the component video output from the DVD player to the RV 8 component video input 1 Connect the RV 8 main component video output to the component video input of t
344. ector J19 Looking down on to the board locate the three black screws that hold the board to the center chassis On the rear panel remove the fifteen black screws along the row of analog RCA connectors Carefully pull the board inward then up and out of the RV 8 Store it in a static free area To remove the Main Power Supply Assembly Note To remove the center main power supply first remove the amp channels 1 On top of the main supply assembly disconnect the following cables J2 5 6 7 21 and P1 Turn the RV 8 over and remove the ribbon cable J20 that runs to the front panel Remove the six screws that hold the assembly in place three on each amp channel side Carefully grab on to the assembly and pull up removing it out the bottom of the RV 8 chassis Store it in a static free area To remove the Tuner Phono Board Place the RV 8 upside down with the rear panel facing you Locate the Ground Lug and remove it from the rear panel Grab the Tuner Phono board assembly and remove the two rear panel screws Carefully lift the assembly out and disconnect the two ribbon cables at J2 and J4 Lift the assembly out and store it in a static free area Removing the Main Processor Board Note The Tuner Phono assembly should be removed prior to removing the Main Processor board 1 2 3 4 Place the RV 8 upside down with the rear panel facing you Locate and disconnect the following po
345. edge of CRY effectively delaying it by approximately 5nS This signal is OR ed with the original CRY NVWEJ to better align the rising edge of DELWE with the address bus so that the hold time will not be violated An additional 5nS is picked up 6 27 RV 8 Service Manual from the propagation delay of a gate within U7 The resultant signal DELWE is the write enable 019 Software requirements dictate that the FLASH address space begin at 0x80000 U13 decodes out the start address with chip select When CRY_A19 is high and CRY_NVCS is low pin 4 of U13 goes low This signal is used as the chip select for the FLASH CRY FLCS Due to another bug within the CS49400 writing the FLASH must be accomplished by using GPIO20 and GPIO21 as address pins At the beginning of a write cycle to the FLASH erase commands are sent to specific addresses within the device GPIO 21 20 take the place of CRY A 1 0 during this phase of the operation During normal read operations the GPIO pins are programmed to be always low and CRY A 1 0 are passed along to U19 via OR gates U7 During read cycles DELWE is driven high while the output enable signal CRY NVOE is driven low enabling the read buffers on 019 All data transfers are eight bits wide and are accomplished via data bus CRY D 7 0 In future revisions of the CS49400 silicon all delay and logic steering circuitry will be designed out Provision to remove the delay elements from the circ
346. elect signal is not used TUN RDS DAT is a bi directional signal that comprises part of an 1 interface to the Tuner Board Control register addresses and data are serially shifted up to the tuner board synchronous with the rising edge of TUN RDS CLK Analog Board Control Interface Signals ADA SDATA OUT ADA SDATA IN ADA SCLK ADA LATCH ADA VC SEL TUN TUN 5 TUN RDS DAT These signals comprise the SPI interface to the Analog Board Control data to the CODECs is transmitted from the FPGA SDATA OUT and status information is received via SDATA Both signals are synchronous with serial shift clock Control data is latched into an eight bit register on the Analog Board when ADA LATCH is in a high state this occurs at the end of every sample byte transmitted ADA SEL is a chip select that enables SPI transfers to the volume controller devices on the Analog Board ADA TUN CE is a chip select that enables SPI transfers to the Tuner Board Currently the Tuner Board does not use SPI control so this signal is unused Analog Board Audio Interface Signals REC FS REC ADC FS64 REC DAC FS REC DAC FS64 MAIN FSy MAIN FS64 MAIN 125 OUT 4 1 REC DAC 125 OUT MAIN 125 IN 4 1 MAIN 125 IN1 is the serial data stream sourced from the MAIN A D Converter on the Analog Board to the AVRX FPGA This 125 stream is the 24 bit left and right channel data encoded from a selected
347. embly consists of three boards the Video In Board schematic 060 15509 the Video Out Board schematic 060 15519 and the Video Board schematic 060 15589 The RCA input and output boards connect to the main board via flexible ribbon connectors with most of the active circuitry contained on the Video Board Video input and output connectors are mounted directly on the boards which attach to the rear panel of the RV 8 Separate cables supply power and control signals to the video assembly Control from the main board is implemented via a serial interface Composite video inputs Video In board schematic sheet 1 Specific references are to input 1 other inputs are similar Standard video levels applied to RCA jack J5 develop 1Vp p is across 75 ohm termination resistor R15 Emitter follower Q5 is located close to the connector and buffers the input with a gain slightly less than unity Transistor bias is supplied through R13 Buffered video is fed to pin 10 of ribbon cable J6 through low value series resistor R14 which reduces high frequency peaking in the transmission path to the video board Composite video outputs Video Out board schematic sheet 1 Composite video outputs originating on the video board are fed through individual pins of J5 to the corresponding output RCA jacks The on board traces are controlled impedance and form part of a 75 ohm wideband transmission system and output level is 1Vp p when terminated in 75 ohms 2Vp p open
348. entially with each transfer of a data byte 6 20 Lexicon Link Ports Signals DSPABLDATA 7 0 DSPBALDATA 7 0 LOCLK LOACK L1CLK The link port is a full duplex pathway that allows 100MHz bit rate transfers of audio data between the SHARCs The LODAT 07 00 ports on each device are configured as transmitters while the L1DAT 07 00 ports are configured as receivers Data is transmitted from U16 to U34 on DSPABLDATA 7 0 synchronous with the clock sourced from the LOCLK pin 016 034 receives this data on the rising edge of this clock When a transfer is complete U34 transmits an acknowledge signal to U16 via the LOACK signal Transfers in the opposite direction are handled the same way except that the clock source is U34 while the acknowledge source is U16 Currently this application is not using the link ports and as such this interconnection is only a provision for future enhancements of capability SPORT Data Ports Signals SPORT A SPOHT FS DSPASP3FPGA DSPASPOFPGA B SPORT FS N DSPBSP3FPGA Each SHARC has four SPORT data ports comprised of a frame sync signal a serial clock and two bi directional data ports U16 utilizes three of these ports Port 0 is used as the receive data port while Port 2 is used as a full duplex channel between U16 and U34 Port 3 is the return port for the Main Zone data Port 1 is unused Timing is shared among all three used ports The SP
349. enu down arrow scroll down to the DISPLAYS parameter and select it by pressing the Menu arrow The DISPLAY SETUP menu will open with the ON SCREEN DISPLAY parameter highlighted Select it by pressing the Menu arrow The ON SCREEN DISPLAY menu will open with the STATUS parameter highlighted 4 22 Lexicon 18 Select the STATUS parameter by pressing the Menu arrow and change the value of the parameter to ALWAYS OFF 19 Press the Menu lt arrow to exit the menu structure 20 The video path is now set for testing Test 1 2 3 4 Load disc into the player and press play Verify a clean undistorted picture appears on the monitor Pause the DVD player To test the four remaining composite outputs the other Main Zone output the Zone 2 outputs and the Zone 3 output switch the composite output cable on the back of the RV 8 to the next main composite video output connector and press Play on the DVD player Repeat the above procedure for the two Zone 2 composite video outputs To test the remaining composite inputs 2 through 5 reconnect the composite output cable to the first main composite output In steps 13 and 14 of the above Setup procedure change the VIDEO IN parameter from COMPOSITE 1 to COMPOSITE 2 Repeat steps 1 to 3 of this test procedure Repeat step 7 above to test the remaining RV 8 composite inputs 3 through 5 S video Inputs to S video Outputs Test This test w
350. er by pressing the Menu arrow and change the value of the parameter to ALWAYS OFF Press the Menu 4 arrow to exit the menu structure The video path is now set for testing Test 1 2 3 4 Load a disc into the DVD player and press play Verify a clean undistorted picture appears on the monitor Pause the DVD player In steps 13 and 14 of the above Setup procedure change the COMPONENT IN parameter from COMPONENT 1 to COMPONENT 2 Repeat steps 1 to 3 of this test procedure Repeat step 4 above to test the remaining RV 8 component inputs Composite Video Input to Component Video Output Test This test will verify the Video Up Conversion functionality of the RV 8 Setup 1 Connect the composite video output from the DVD player to the RV 8 s composite video input 1 2 Connect the RV 8 main component video output to the component video input of the video monitor 3 Turn on the DVD player monitor and the RV 8 4 The monitor should display a blue screen 5 Onthe RV 8 remote control press the MAIN button then press the DVD1 button to select DVD1 as 8 9 10 the input for testing the video paths Press the remote control Menu arrow to display the Main Menu Using the Menu arrow scroll down to SETUP Press the Menu right arrow to select the SETUP menu The SETUP menu will appear with INPUTS highlighted Press the Menu arrow again to open the INPUT SETUP menu DVD1 will be highlighted 4 25
351. ers set the output voltages for these devices R77 R78 for 022 and R143 R144 for 039 The voltage is set by the following equation Veer 1 R77 R78 1 R78 REF Where V 1 25V 1 60UA 1 ADJ Substitute R143 for R77 R144 for R78 for U42 programming C67 and C127 provide local filtering of the 5V supply feeding the regulators C75 and C133 provide local bulk capacitance to the 1 8V planes for each SHARC At least one device from each of these pairs must be a low ESR tantalum type or the regulators will oscillate Pins 2 and 4 of the regulators are electrically the same pins but they are shown connected together at the schematic level R76 and R142 provide a de coupled 1 8V to the analog PLL supply pin on each SHARC while C73 C74 and C130 C131 provide local high frequency de coupling of this voltage The 1 8V planes for each device break out to test points 1 8 and 1 8V B for ease of measurement Glue Logic CPLD U44 This device provides address decoded strobes for the external registers the CPU clock and the address decoded control interface to the VFD CPUCLKI is a 6 25MHz clock signal that is derived by dividing the input clock CLK12500B by 2 This clock is the system clock for the CPU on sheet 1 RESREGDECL is decoded from chip select CPUCS3 write strobe CPUWRL and the condition CPUADDR 3 1 000 The result is an active high strobe when write operation is performed at CPU address 0 00 0
352. etc ha ipte e Eo e gr etre n e eripe 7 22 7 22 ASSEMBLY DRAWINGS 080 14834 PC ASSY DWG MECH VCO 080 15508 PC ASSY DWG VIDEO IN BD 080 15518 PC ASSY DWG VIDEO OUT BD 080 15528 PC ASSY DWG MIC PREAMP BD 080 15538 PC ASSY DWG HEADPHONE BD 080 15548 PC ASSY DWG TUNER BD 080 15558 PC ASSY DWG MAIN BD 080 15568 PC ASSY DWG SW LED BD 080 15578 PC ASSY DWG ANLG BD 080 15588 PC ASSY DWG VIDEO BD 080 16158 PC ASSY DWG AMP MOD 3CH 080 16168 PC ASSY DWG AMP MOD 4CH 080 16178 PC ASSY DWG PS BD 080 16188 PC ASSY DWG SPKR EMI FILT 080 15644 ASSY DWG SHIPMENT 080 15645 ASSY DWG ACCESS 080 15646 ASSY DWG CHASSIS 080 15647 ASSY DWG MECH FP 080 15648 ASSY DWG MECH VIDEO 080 15649 ASSY DWG FAN 60MM 080 15848 ASSY DWG MECH TUNER PREAMP 080 16434 ASSY DWG AMP 3CH 080 16435 ASSY DWG AMP 4CH 080 16436 ASSY DWG MECH PS 080 16437 ASSY DWG BRIDGE RECT 080 16438 ASSY DWG HS SGL 080 16439 ASSY DWG HS DBL SCHEMATICS 060 13699 SCHEM IR ENC BD 060 15509 SCHEM VIDEO IN BD 060 15519 SCHEM VIDEO OUT BD 060 15529 SCHEM MIC PREAMP BD 060 15539 SCHEM HEADPHONE BD 060 15549 SCHEM TUNER BD 060 15559 SCHEM MAIN BD 060 15569 SCHEM SW LED BD 060 15579 SCHEM ANLG BD 060 15589 SCHEM VIDEO BD 060 16139 SCHEM VCO BD MCLK 060 16169 SCHEM AMP MOD 4CH 3CH 060 16179 SCHEM PS BD Lexicon CHAPTER 1 REFERENCE DOCUMENT amp EQUIPMENT LISTS Reference Document Refer to the RV
353. every time it successfully completes the test If the test fails it will attempt to loop to keep the signal lines active for debugging purposes In addition test progress and failure information is available via the serial debug port Specific failure information will depend on the test 5 8 Lexicon being executed Pressing and holding the Mode button returns the user to the top level diagnostic menu Repair Diagnostics Suite The repair tests suite is the section where every diagnostic test can be executed individually Additionally the repair test suite allows you to run any single diagnostic test infinitely The encoder knob is used to scroll through each diagnostic test To run any particular test or to move into a sub menu use the Mode button To back out of a sub menu or to return out of a test use the Mode button Sub menus can be used to partition off groups of tests that deal with a portion of the board For example the SHARC tests and the Trigger tests can be placed in sub menus In the repair suite the SHARC tests will also include tests as outlined below SHARC WCLK SHARC BOOT PAIR 0 PAIR 1 SHARC SDRAM PAIR 0 PAIR 1 SHARC WCLK PAIR 0 PAIR 1 In the repair suite the ability to set each trigger on and off will be available SET TRIGGERS Trigger 0 ON Trigger 1 ON Trigger 0 OFF Trigger 1 OFF The following diagnostic selections are available in the repair tests suite SH FLASH CHECKSUM SH DRAM AVR
354. exico RV 8 Receiver Service Manual Harman Specialty Group 3 Oak Park Bedford MA 01730 1413 USA Customer Service Telephone 781 280 0300 Service Fax 781 280 0499 www lexicon com Part No 070 17537 Rev 0 IMPORTANT SAFETY INSTRUCTIONS 99 ADOOS SO QP gt D 11 12 13 14 15 16 17 18 19 Read and keep these instructions Heed all warnings Follow all operation instructions Do not use this apparatus near water Clean only with a dry cloth Do not block any ventilation openings Install in accordance with the manufacturer s instructions Do not install near any heat sources such as radiators heat registers stoves or another apparatus including amplifiers that produces heat Do not defeat the safety purpose of the polarized or grounding type plug A polarized plug has two blades with one wider than the other A grounding type plug has two blades and a third grounding prong The wide blade or the third prong are provided for your safety If the provided plug does not fit into your outlet consult an electrician for replacement of the obsolete outlet Protect the power cord from being walked on or pinched particularly at plugs convenience receptacles and the point where they exit from the apparatus Only use attachments accessories specified by the manufacturer Use only with the cart stand tripod bracket or table specified by the manufacturer or sold with the apparatus
355. forced When high the boot sector may be erased and re programmed The RYBY pin 15 is an output flag of the internal status of the device When this pin is low it indicates that the Flash is in the middle of an erase or programming cycle busy When this pin returns to a high state it indicates that the operation at hand has been completed and the device contents may be read in the same manner as an EEPROM The WE 11 CE 26 and OE 28 have the same function as those on an EEPROM Erasure or in circuit programming is accomplished by executing the erase or program command sequence These sequences initiate the proper embedded algorithm that ensures proper execution of the desired command The RESET pin 12 is tied to the system level power on reset When this pin is low it suspends any operation that is in progress and resets the internal state machines to reading array data During power up the internal state machines are set up in this manner The BYTE pin 47 is pulled high to configure the Flash as a word mode device The CPU fetches its start up instructions from the boot sector of this device Once boot up is complete all system control and DSP algorithm code is accessed from here as well Under normal operating circumstances 50 from the CPU controls the CE pin of this device This signal is labeled BOOTCS and it is routed to the FLASH device by jumpering pins 1 and 2 on W4 During code development cycles CS1 f
356. formats 8 Unbalanced RCA connectors for Front L R Center Sub Side L R and Rear L R 1 Unbalanced RCA variable output level stereo connector 1 Unbalanced RCA fixed output level stereo connector 1 S PDIF coaxial RCA connector and 1 optical connector 1 Stereo RCA variable output level connector 1 Stereo 1 4 inch phone connector 7 Channels 2 channels assignable to Zone 2 or Zone 3 Main Zone Audio Performance A D Conversion D A Conversion Frequency Response THD Noise Dynamic Range Signal to Noise Ratio Input Sensitivity Input Impedance 24 bit 96kHz multi bit AX architecture 24 bit 44 1 to 192kHz multi bit AX architecture 20Hz to 20kHz 0 1dB 0 1dB 0 25dB at 10Hz 0 5dB at 40kHz reference 1kHz Below 0 0296 20Hz to 20kHz 140Wrms all channels driven 105dB minimum 22kHz bandwidth A weighted 102dB minimum 22kHz bandwidth unweighted 105dB minimum 22kHz bandwidth A weighted 102dB minimum 22kHz bandwidth unweighted 200mVrms 2Vrms for maximum output level at OdB input gain 100kQ in parallel with 150pF Combined measurements of preamplifier and power amplifier sections 3 1 RV 8 Service Manual Preamp Output Level 150mVrms typical 6Vrms maximum RCA connectors Maximum value with full scale input signal and volume at 12dB Preamp Output Impedance 5000 in parallel with 150pF RCA connectors Combined measurements of preamplifier and power ampl
357. he video monitor Turn on the DVD player monitor and the RV 8 The monitor should display a blue screen On the RV 8 remote control press the MAIN button then press the DVD1 button to select DVD1 as the input for testing the video paths Press the Menu arrow on the RV 8 remote control to display the Main Menu Using the Menu arrow on the remote scroll down to SETUP Press the Menu gt arrow to select the SETUP menu The SETUP Menu will appear with INPUTS highlighted Press the Menu arrow again to open the INPUT SETUP menu 4 24 Lexicon 10 11 12 13 14 15 16 17 18 19 DVD1 will be highlighted Press the Menu arrow The DVD1 INPUT SETUP menu will now be displayed Using the Menu arrow scroll to the COMPONENT IN parameter Select it by pressing the Menu arrow The DVD1 COMPONENT IN menu will be displayed with the COMPONENT 1 parameter highlighted Press the Menu arrow to select this video input This will assign the RV 8 component 1 video input to the main component video output Press Menu lt arrow three times to exit to the SETUP menu Using the Menu arrow scroll down to the DISPLAYS parameter and select it by pressing the Menu y right arrow The DISPLAY SETUP menu will open with the ON SCREEN DISPLAY parameter highlighted Select it by pressing the Menu arrow The ON SCREEN DISPLAY menu will open with the STATUS parameter highlighted Select the STATUS paramet
358. his document should not be construed as a commitment on the part of Harman Specialty Group The information it contains is subject to change without notice Harman Specialty Group assumes no responsibility for errors that may appear within this document TABLE CONTENTS CHAPTER 1 REFERENCE DOCUMENT 4 EQUIPMENT LISTS 1 1 CHAPTER 2 GENERAL INFORMATION pp 2 1 CHAPTER 3 SPECIFICATIONS 3 1 CHAPTER 4 FUNCTIONAL VERIFICATION 4 1 Performance 4 1 IMSPOCON m 4 1 FUNCTIONAL Tests a an aaa asa saa stub 4 1 Functional Audio Tests 4 8 Audio Performance Verification pe 4 19 Video Input Output Tests 4 22 Lexicon Audio Precision ATE Summary pt 4 29 CHAPTER 5 TROUBLESHOOTING 5 1 Diagnostic Categories tend ete e rg ie qr e ede Re die 5 1 Power Oni E 5 1 Diagnostic User Interface ence tdg testet ter 5 1 Diagnostic 5 2 Power On Diagnostics 2o te tn te ete pe tutes 5 6 Extended Diagnostics
359. his register bit must be set before data is written to the Format Decoder SPI Control RAM The DSPC section of the Format Decoder is responsible only for accessing the FLASH device attached to the Format Decoder SPI transactions are handled in the same manner as for CRY FCS 6 32 Lexicon CRY INTREQ is an interrupt line that indicates that DSPC has out going control data and should be serviced by the host CPU When this interrupt occurs bit 2 in the Interrupt Status Register is set This bit is then cleared after the host CPU polls this register This interrupt is active low CRY_FINTREQ is an interrupt line that indicates that DSPAB has out going control data and should be serviced by the host CPU When this interrupt occurs bit 3 in the Interrupt Status Register is set This bit is then cleared after the host CPU polls this register This interrupt is active low HINBSY is a status signal from the Format Decoder that indicates that control data written via the SPI port has not yet been read by the decoder This signal serves as a hold off for the host CPU preventing it from over writing control data before it has a chance to be implemented by the Format Decoder The state of this signal is stored within the Serial Interface Status Register at bit 7 which is continuously polled by the host processor When this bit is set high the host will not write any further instructions via the SPI port until the system software sees this bit UN set to
360. host may determine the ready status and clip status of each channel The following table illustrates the mapping of the internal RAM ame me om Control bits 7 0 from the previous SPI cycle Clip Indicator for Channels 4 1 CLIP 4 1 Ready monitor for channels 4 1 RDY MON 4 1 Four Channel Status RAM Table CTRL DATA is the transmit path to the four channel power amplifier Control data from the Host CPU is loaded into an internal 2x8 bit RAM that is in turn serially shifted out to the four channel amplifier board The only control data currently being transmitted is in the form of four ready acknowledge bits each of which activates a relay that places the speaker terminals into circuit with the amplifier outputs The table on the next page illustrates the mapping of the internal RAM 6 36 Lexicon aee me fom Ready control for channels 4 1 RDY 4 1 Four Channel Control RAM Table SER CLKA is the serial shift clock with which the control and status data are synchronous DATA LATCHA is the signal that latches control and status data into registers when a full byte of data has been transmitted or received STAT DATB is the receive path from the three channel power amplifier Data from this signal is stored in a 2x8 bit RAM internal to the AVRX from which the host may determine the ready status and clip status of each channel The following table illustrates the mapping of the internal RAM ame Ei
361. ial and optical digital audio inputs labeled 1 to 4 and all Main Zone analog outputs Note This test requires the use of a CD player as a source The tests to follow will be run using a PCM signal at a 44 1kHz sample rate Test 1 Connect the S PDIF coaxial digital output of the CD player to the S PDIF coaxial digital input 1 on the RV 8 rear panel Connect the S PDIF optical digital output of the CD player to the S PDIF optical digital input 1 on the RV 8 rear panel 2 Connect the RCA front left and front right outputs of the RV 8 to the external amplifier left and right inputs Connect the outputs of the external amplifier to a pair of speakers Using the Menu arrows scroll through the Diagnostic Menu and select the AUDIO I O TESTS 4 Inthe AUDIO TEST Menu highlight S PDIF INPUT CX1 TEST Press the Menu arrow to engage the test The RV 8 is now set to route digital audio from the S PDIF coaxial digital input labeled 1 to all the RCA analog outputs 5 Power on the external amplifier Press Play on the CD player 6 Slowly increase the volume on the external amplifier to a comfortable listening level 7 Verify that clean undistorted audio can be heard 8 Stop the CD player and power down the external amplifier 9 Repeat steps 2 through 8 for the remaining paired RCA outputs Center Sub Side L R Rear L R 4 16 Lexicon 10 The above procedure should be repeated to test digital 5 COAX inputs labeled
362. ical Reading Upper Limit Switcher Module Clock Sample Bandwidth Filter B Out Source Rate q 50 100k _ lt 10 gt 500k 11 23 24 Internal ZONE2 TUNER FM98 TO ANLG ZONE2 DIR HEADPHONE OUT GAIN 25 Unba ZONE2 TUNER 98 TO ZONE2 DIR HEADPHONE OUT THD 1 150 150mvrms 50 16k 75US PRE 25 Float THD N gt 0 80 225 0 10 100k lt 10 gt 500k None 11 23 12 24 Internal n a ANLG ZONE2 TUNER FM98 TO ANLG ZONE2 DIR HEADPHONE OUT SNR 1 OFF OFF 997 None 25 Float dBr Level 55 00 50 00 60 00 100k 22 gt 22k A Wig 11 23 12 24 Interna 25 25 ANLG 98 ANLG ZONE3 DIR HEADPHONE OUT ee ZONE3 TUNER FM98 TO ZONE3 DIR HEADPHONE OUT GAIN 150mVms i50mvms 97 INone 25 ANLG ZONE3 TUNER FM98 TO ANLG ZONE3 DIR HEADPHONE OUT FREQ 100 mVrms 100 mvrms 50 2k 2k 16k 5 97 None C ule j F S 1 94 152 100 10 500k None 11 23 24 Interna Leve 0 00 1 75 0 50 7 050 200 100k lt 10 gt 500k None 11 23 24 Internal Float THD N gt 0 80 2325 _______ 010 joo 10 500k None 11 23 24 Interna ANLG_FRONT TUNER FM98 ANLG FRONT DIR HEADPHONE OUT FRONT TUNER FM98 TO ANLG FRONT DIR HEADPHONE OUT GAIN 150 mVrms 997 None 25 Float Vrms Level 1 55
363. ifier sections Zone 2 and Zone 3 Audio Performance A D Conversion 24 bit 44 1 to 96kHz multi bit AX architecture Zone 2 only D A Conversion 24 bit 44 1 to 192 2 multi bit AX architecture Frequency Response 10Hz to 20kHz 0 1dB 0 25dB 0 75dB at 40kHz reference 1kHz THD Noise Below 0 005 at 1kHz 1Vrms output level Dynamic Range 101dB minimum 22kHz bandwidth Signal to Noise Ratio 101dB minimum 22kHz bandwidth Input Sensitivity 200mVrms 4Vrms for maximum output level Input Impedance 100kQ in parallel with 150pF Preamp Output Level 200mVrms typical 4Vrms maximum maximum value with full scale input signal and volume at 088 Preamp Output Impedance 3000 in parallel with 150pF Video Input and Output Connectors Video Inputs 5 composite RCA 5 S video and 3 component video RCA Video Outputs 5 composite RCA 2 monitor 2 Zone2 1 Zone3 4 S video 2 monitor 2 Zone2 and 1 component RCA Composite and S video Performance Compatibility NTSC PAL and SECAM Switching Active Output Level 1 0V peak to peak Impedance 750 3 2 Lexicon Input Return Loss Differential Gain Differential Phase Bandwidth K Factor Gain Signal to Noise Ratio Frequency Response gt 40dB lt 0 5 lt 0 5 gt 25MHz lt 0 3 0 15dB gt 65dB 10Hz to 10MHz 0 1 0 3dB Component Video Performance Compatibility Switching Impedance Bandwidth Insertion Loss Video Converter Other Trigger Output
364. ill verify the S video switching function of the RV 8 Setup 1 c RON 10 11 Connect the S video output from the DVD player to the RV 8 S video input 1 Connect the first main S video output of the RV 8 to the S video input of the video monitor Turn on the DVD player monitor and the RV 8 The monitor should display a blue screen On the RV 8 remote control press the MAIN button then press the DVD1 button to select DVD1 as the input for testing the video paths Press the remote Menu arrow to display the Main Menu Using the Menu arrow scroll down to SETUP Press the Menu arrow to select the SETUP menu The SETUP menu will appear with INPUTS highlighted Press the Menu right arrow again to open the INPUT SETUP menu DVD1 will be highlighted Press the Menu arrow The DVD1 INPUT SETUP menu will now be displayed 12 13 Using the Menu arrow scroll to the VIDEO IN parameter Select it by pressing the Menu arrow Using the Menu arrow scroll to S VIDEO 1 4 23 15 16 19 RV 8 Service Manual Press the Menu arrow to select S VIDEO 1 This will assign the S video 1 video input to the Main S video output of the RV 8 Press the Menu arrow three times to exit to the SETUP menu Using the Menu arrow scroll down to the DISPLAYS parameter and select it by pressing the Menu gt arrow The DISPLAY SETUP menu will open with the ON SCREEN DISPLAY parameter highlighted Sel
365. in processor board 3 Remove the seven screws that hold the channel in place There are three on the back panel two on the front end holding it to the main chassis one in the top and one on the bottom main chassis Carefully pull the amp channel to the front panel and lift it free Store the module in a static free area For the right 4 channel amp locate and disconnect the black 6 wire connector and two thin white ribbon cables that run to the main analog board at J1 and J27 Also remove one large thin white ribbon cable on the underside of the amp channel connecting to J18 of the main processor board 7 Remove the nine screws that hold the channel in place There are three on the back panel two on the front end holding it to the main chassis one in the top and three on the bottom main chassis 8 Carefully pull to the front panel the amp channel and lift it free 5 19 9 RV 8 Service Manual Store the module in a static free area To remove the video board Qv Rp om First rotate the RV 8 so the rear panel is facing you Disconnect the following cables J18 the 4 wire power cable and J20 the thin white ribbon cable On the back rear panel remove the four black screws that hold the board in place Carefully pull the board inward then up and out of the RV 8 Store it in a static free area To remove the analog board OY de CO dS c Disconnect the following cable on the analog board and power supply conn
366. in step 6 to the next appropriate input 19 Now perform the setup and test steps 1 to 18 to test the digital optical outputs Be sure to use the appropriate digital cable 4 10 Lexicon Digital Input to Digital Outputs Test This test will verify the audio path between the S PDIF coaxial and optical inputs 1 to 4 and the Zone 2 S PDIF coaxial and optical digital outputs Setup 1 video monitor to the main composite output of the RV 8 and turn the monitor on This will allow full viewing of the RV 8 s menus 2 Connect a S PDIF coaxial digital output from a DVD or CD player to the S PDIF coaxial digital input labeled 1 on the rear panel of the RV 8 3 Connect the S PDIF coaxial digital output on the RV 8 rear panel to the digital record input jack of the DAT machine 4 Connect the left and right analog outputs of the DAT machine to the analog left and right inputs of an external amplifier Connect the outputs of the external amplifier to a pair of speakers Power on the RV 8 using the main power switch on the rear panel Once the unit is in standby mode press the front panel standby button or the remote control POWER button to enter normal operation Test 1 To enter the MAIN MENU press the remote control Menu arrow 2 Scroll through the MAIN MENU using the Menu arrows and highlight SETUP Press the Menu y arrow to enter SETUP In the SETUP menu highlight INPUTS Press the Menu arrow
367. ing the RV 8 when removal of components is necessary The amplifier channels may still be charged Be sure to discharge for safety See page 4 4 for instructions on discharging amplifier channels To remove the top cover 1 Remove the thirteen screws that hold the top cover of the unit 2 Carefully slide the cover to the back of the RV 8 and remove Reverse the above procedure when reinstalling the cover To remove the bottom cover 1 Carefully rotate the RV 8 onto its side 2 Loosen the eight screws four on each side of the bottom cover 3 Push the cover towards the front panel and remove from the bottom of the RV 8 To remove the Power Supply Board 1 With the RV 8 front panel facing you locate the power supply module mounted to the inside chassis on the left hand side of the RV 8 Remove the two wire connectors on the top and bottom of the supply module Hold the supply with one hand and remove the two screws that hold the supply to the inside chassis Carefully remove the supply from the RV 8 chassis Store the module in static free area To remove the amp channels 1 For ease of removal of the left 3 channel amp remove the switching power module first 2 Locate and disconnect the black 6 wire connector and two thin white ribbon cables that run to the main analog board at J18 and J21 Also remove one large thin white ribbon cable on the underside of the amp channel connecting to J22 of the ma
368. ing the equation V 1 275 R15 R16 R15 C25 provides local bulk capacitance for the voltage input C22 is a low ESR type capacitor which provides stability for the regulator and bulk capacitance for the output voltage R13 and R14 provide a current path for any load that would source current when shut off as U8 cannot sink current FB1 and C10 provide suppression of high frequencies preventing EMI effects J3 is the output connector which is protected by a spark gap 6 44 Lexicon The regulator provides the external 12VDC when the ON OFF pin is brought to a logic 0 This pin is software controlled via the external registers on sheet 2 See page 6 23 for further information Inverter U14 permits us to use positive logic in the software register This circuit is duplicated exactly with U9 and all associated components VCO A Sheet 15 The purpose of the VCO is to provide clean stable clock that matches the average properties of a potentially unstable reference such as jitter At the heart of the circuit is the metal encased VCO module which provides an output clock at 22 579MHz or 24 576MHz depending on the control voltage The control voltage should fall between 5V and 6V The 700mVpp output of the VCO is amplified by one gate of U10 to a 5V logic level This gate is self biased in the middle of its inverting characteristic by R41 R42 and C49 Another gate of U10 is used to invert and buffer the output signal of the conditi
369. ions This function is used only in development and as such is not used in the standard build of this product Note that R159 and R160 must be removed before using JTAG as they provide default termination of the TRST and TCK pins during normal operation RV 8 Service Manual J17 Series Connection Diagram w 4 cE m we Mx U18 JTAG ENABLED U37 JTAG ENABLED U37 U18 JTAG ENABLED General Purpose Device Pins FLAG 9 4 F3 ES F2 F4 F1 G3 Each flag pin may be configured as input or an output In this application the flag pins listed above are configured by software as outputs An internal register controls each flag output They are used as test bits that activate status LEDs for each device U15 provides increased drive capability for each flag pin to light the LEDs while resistor networks RP1 through RP3 provide a default pull down state for these pins when the DSPs are being configured during the boot phase When the devices are unconfigured these flag pins default to input mode Note that FLAGO is no longer used in this application Its function is non descriptor Proprietary DSP SDRAM and Flash Sheet 4 This sheet shows the interconnection between DSP A and its SDRAM It also illustrates the boot configuration for DSP A SDRAM U6 Each SHARC is supported by a 2 Mbit x 32 100MHz SDRAM The memory interface is implemented as four banks of 256 wor
370. ives additional control bits from the values in the registers For example the MSVID_SELn bits are formed by gating the MVID SELn bits with MCVID such that the MSVID_SELn bits are forced to 0 when MCVID is low The CPLD can be programmed in circuit through the JTAG port J17 Font Flash Programming Interface Video board schematic sheet 9 The CPLD 014 also controls the in system programming of flash memory U25 which holds the bitmapped OSD font pattern The CPLD is interfaced to the memory D 7 0 and A 15 0 buses In normal operation this interface is tri stated outputs and does not drive the buses and the only bus activity is the fetching of font patterns from U25 over the A 15 0 D 7 0 buses under the control of OSD U26 When necessary the host processor on the main board manages the programming of the font flash memory A large white box on the OSD is a symptom of an un programmed memory A control register transfer with bit 47 set initiates a font flash write cycle based on a state machine in the CPLD The CPLD address and data buses are enabled the OSD releases control of the bus OSD TSC high and VROM WhY is asserted to write to the flash memory The host performs a series of transfers with updated address and data to program subsequent bytes into the flash During programming the OSD continues to operate but the write operations interfere with the normal bitmap fetching which temporarily corrupts the OSD image
371. l input of the DAT player Repeat steps 1 18 to test S PDIF optical Inputs 1 through 4 Change the DVD1 DIGITAL IN selected in step 6 from COAX to Optical and use the appropriate digital cable Phono Input to Zone 2 Outputs Test This test will verify the audio path between the left and right phono inputs and the Zone 2 Fixed and Variable outputs Test 1 Connect the Low Distortion Oscillator output to the phono left and right audio inputs on the rear panel of the RV 8 2 Connectthe Zone 2 RCA left and right Fixed outputs of the RV 8 to the external amplifier left and right inputs Connect the outputs of the external amplifier to a pair of speakers 3 Power on the external amplifier Slowly increase the volume on the external amplifier to a comfortable listening level 4 Sweep the oscillator from 20Hz to 20kHz Verify that clean undistorted audio can be heard throughout the frequency sweep Power down the external amplifier Switch from the Zone 2 Fixed outputs to the Zone 2 Variable outputs and repeat steps 3 to 5 above Phono Input to Zone 3 Output Test This test will verify the audio path between the left and right phono inputs and the RCA Zone 3 outputs Test 1 Connect the Low Distortion Oscillator output to the phono left and right audio inputs on the rear panel of the RV 8 2 Connect the RCA left and right Zone outputs of the RV 8 to the external amplifier left and right inputs Connect the outputs of the extern
372. ls are address decoded signals from CPLD U44 When write cycles are performed to the VFD Display Control Register CPU Address 0x00C00003 or the VFD Data Register CPU Address 0x00C00005 the tri state buffer is enabled and data flow is from the CPU to the VFD When read cycles are performed at these register locations The buffer is enabled and data flow is from the VFD to the CPU When these register locations are not addressed for access the tristate buffer is disabled and the IO pins float Format DSP Sheet 8 This sheet contains the format DSP associated FLASH RAM algorithm memory timing circuitry and delay components necessary for proper interfacing between the DSP and RAM Format DSP U25 This device decodes all the canned algorithm information from the input data streams provided by the FPGA This device is a Crystal Semiconductor 5494001 Multi Standard Audio Decoder It is packaged in a 144 pin LQFP In truth this decoder is actually two DSP engines one package DSPAB and DSPC Each engine has it s own SPI port for host communication Power Up State Signals CRY RESET FHS 2 0 UHS 2 0 When the RV8 is first powered up the Format DSP is placed in a reset state by the signal CRY RESET going low This signal is controlled by external register U21 which will hold U25 in reset until released by the system software When this reset is asserted high pins FHS 2 0 and UHS 2 0 are sampled on the rising edge of CRY RES
373. mply the composite video With S video input the result is the composite version of the S video the sum of Y C The internal U38 multiplexer selects whether the OSD is in the path or whether the input is fed straight through controlled by MTHRU Output impedance is structured as with the main luma output Main composite video CVID_MAIN2 is driven by U5 Luma and chroma from the input amplifiers are summed by R126 and R127 scaled by 1 2 and the result is amplified by U5 which has a gain of two MAIN is not subject to the OSD Standard 1Vp p video input levels produce 1Vp p output on the composite and luminance channels when terminated in 75 ohms or 2Vp p open circuit The composite main outputs are fed to the output rca jacks on the Video Out board via ribbon cable J16 Zone2 Composite S video Video board schematic sheet 3 Zone2 functionality in the RV 8 corresponds to Record functionality in previous products and the nomenclature reflects this legacy In many places the record nomenclature has been retained to correspond with the software base but from the user perspective this circuitry drives Zone2 Zone2 video circuitry is structured similarly to main video but without OSD capability Refer to the previous section for additional description Multiplexers U10 and U11 U12 are addressed by the RECVID SELn and RECSVID SELn bits respectively to select an independent zone 2 record source but otherwise operate like their coun
374. mps the core voltage supply pins to the I O supply pins This ensures that the I O pins will track the core voltage at power up Destruction of the chip could result if the I O voltage rises faster than the core voltage With this topology the 3 3VD supply will be pulled along with the 2 5VD supply if the 3 3V supply is slow in 6 28 Lexicon coming up This is a likely scenario given the fact that the 3 3V rail is more heavily loaded than the 2 5V rail There are seven ground pins associated with the core supply and four associated with the I O supply In addition there are five no connect pins that are recommended by the manufacturer to be tied to GND All sixteen pins are tied to the DGND system plane Algorithm Storage FLASH RAM U19 The FLASH is an ATMEL AT29LV040A 4Mbit device organized as 512Kx8 3 3 volts power this device It operates much like an EEPROM Read cycles are identical to PROM operation with data output on CRY 0 7 0 when chip select and output enable are both low The output buffers enter a high impedance state when either of these signals is high This device uses software data protection programming Prior to writing data to this device a series of three programming commands must be presented at specific addresses Data will not be written without this sequence The FLASH is organized as 2048 sectors of 256 bytes each If any data within a sector is to be changed then the entire sector must be programmed Ea
375. ms _ 1 00 Vrms LG ZONE3 DIR 387 OUT 2 IN5 TO ZONES IN5 TO 20 IN5 20 IN5 LG ZONE3 D LG ZONE3 D LG ZONE3 D LG ZONE3 D R AMP3 amp 7 OUT FREQ R AMP3 amp 7 OUT THD AMP3 amp 7 OUT XTALK AMP3 amp 7 OUT SNR 1 00 Vrms 1 00 Vrms 10 20 20k 40k 100k NLG MAIN DIR IN345 TO ANLG MAIN AMP1 7 OUT LG MAIN D LG MAIN D IN345 TO AN IN345 TO AN LG MA AMP1 7 OUT GAIN N AMP1 7 OUT FREQ nad Vrms 1 00 Vrms 1 00 Vrms 1 00 Vrms ee 20k 40k 100k Float dBr Leve 107 00 105 00 24000 22 gt 22k TTR R T BIUUCHU NECI gt 22k None 7 3 5 6 __ _ Float dBr Leve 210370702725 527 5730 lt 10 gt 500 Nn 7 3 5 6 Analog Float THD N lt 0 0010 0 0001 lt 10 gt 22k None 7 3 5 6 memi ma Anaog Float 48 Leve lt 65 00 50 00 150 00 lt 10 gt 22k Nn 7 3 5 6 Analog Float 48 Level 107 00 105 00 140 00 22 gt 22k A Wig rn lucc i eee I I s ji pe Se ee lt 10 gt 22k None 5 1 4 6 2 7 3 0 1 2 3 5 6 5 6 7 95 03 0 02 2 5 pcm None 1 2 3 5 6 5 6 LG MAIN D LG MAIN D IN345 TO AN IN345 TO AN AMP1 7 OUT SMPTE IMD N ANLG MAIN AMP
376. n all the filters off on the Analyzer Filter not required for Gain Test 4 Verify that the output level measurement from the RV 8 is between the range of 7 55Vrms and 8 35Vrms Note this level Total Harmonic Distortion Test THD 1 Adjust the scale on the Distortion Analyzer to measure 0 01 THD N and turn off the low pass audio band pass filter 2 Verify that the THD N measured on the Analyzer is less than 0 05 Frequency Response Test FREQ 1 Setthe scale on the Distortion Analyzer to measure 1Vrms signal level 2 Using the output level from step 4 of the Gain Test set the Distortion Analyzer for a OdB reference to check frequency response of the RV 8 Turn the filter on the Analyzer off Sweep the oscillator frequency from 10Hz to 100kHz Verify the signal levels are 0 10dBr to 0 5dBr 10 20 2 20 2 0 10dBr to 0 2dBr 20Hz 20 2 0 10dBr to 0 5dBr 40kHz and 0 10dBr to 3 0dBr 100 2 of reference level over the entire sweep Note these levels 4 20 Lexicon Signal to Noise Test SNR 1 Using the signal levels from step 5 of the Frequency Response Test turn off the oscillator and a noise level measurement lt 105dBr This procedure should be repeated to test analog inputs labeled 2 through 8 To do this move the cable from the output of the Low Distortion Oscillator to the next pair of inputs and repeat the tests above to test the remaining Main Zone RCA o
377. n configured These include the following e Bus State Controller e Wait State Controller e DRAM Configuration the default conditions are now replaced with optimized settings e Serial Communication Ports 1 and 2 e Pin Function Control e General Purpose I O The processor then checks the status of PE 3 1 88 86 to determine which start up configuration has been chosen by the user If these port pins read as all low then the processor continues with the normal boot procedure 6 9 RV 8 Service Manual The Serial port UARTs are now tested and if the test passes LED D12 will light flash if the test fails The FPGA U41 is now programmed If the operation is successful LED D13 will light flash if the operation fails If all of these steps are completed successfully LED 010 will dimly glow This is due to the LED being driven with a 4mS square wave All through these tests progress may be monitored via a hyperterminal monitor connected to serial port O If a problem exists with this serial connection LED D11 will light Diagnostics continue by testing the Character RAM on the front panel Vacuum Fluorescent Display Connection integrity to the Video Board Analog I O Board AM FM Tuner Module and Amplifier SPI ports is tested as well The FPGA status is checked by polling it s internal ID register The Format DSP U25 is now taken out of reset and its associated Flash device U19 is tested The algorithm DSP devices U16 and U34 a
378. ndow are three LEDs that are driven directly from the processor These LEDs are driven via the PE 10 12 port 108 110 111 When these port pins are high the associated LED lights The following table illustrates their functionality DISPLAY LED INDICATORS PORT BIT SIGNAL NAME FUNCTION PE10 FP_IR_ACK Yellow LED indicating infra red remote access PE11 SYSLED Blue LED indicating unit is on and functional PE12 OVLED Red LED indicating clipping on an audio input Miscellaneous Peripheral Control Signals CPU WRD CLK MON FLBY Timer Channel 0 is used as an interval counter that monitors the period of FSCLK from both the Main Zone and Zone 2 The FPGA Multiplexes each clock signal into the TIOCOA port 85 as signal CPU WRD CLK MON With each rising edge of FSCLK the event timer is restarted and the period is verified by count value FLBY is output from the storage FLASHRAM 026 to indicate that the device is busy either during an erase or re programming operation The processor device monitors this signal via the PE14 port 1 When the signal is low the FLASHRAM is not ready for read accesses When high the device may be accessed as normal DRAM U42 The DRAM used in this product is a standard 70nS 1Mx16 Fast Page Mode device U42 The processor executes all software instructions from this device except for the earliest phases of boot up After DRAM testing has passed all of the system code that resides in the FLASHRAM is
379. nfiguration for DSP B The functionality of this page is identical to that of Sheet 4 Further discussion would be redundant DSP SPI Serial and Link Ports Sheet 6 This sheet shows the interconnection between DSP A and DSP B as well as the SPI host interface as well as the audio data path into and out of the SHARCs SPI Interface Signals DSPASEL DSPASPICLK DSPARXD DSPATXD DSPBSEL SPI is a serial interface protocol consisting of a four wire interface a chip select two data pins and clock pin This interface runs in full duplex mode allowing the SHARC to simultaneously receive and transmit data on the same port The SHARCs are configured as slave devices to a master boot device The interface between the CPU and the SPI port on each SHARC is implemented in the FPGA The receive and transmit wires as well as the SPI clock are shared between the two DSPs while selection of the devices is accomplished with their individual chip select signals The SPI interface is essentially a shift register that serially transmits and receives data synchronously with DSPASPICLK When a SPI transfer occurs data is shifted out of one end of the shift register on DSPATXD and into the other end of the shift register on DSPARXD SPI transfers to U16 are accomplished by asserting DSPASEL and beginning the transfer SPI transfers to U34 are accomplished by asserting DSPBSEL and beginning the transfer The internal registers of the SHARCs are accessed sequ
380. ng from the 3 3V domain are given a shift in level making them compatible with the CMOS 5 volt threshold of the CPU input pins Five of the interrupt sources discussed in the previous section are sourced from the FPGA directly to the processor after undergoing level shifting U36 performs a similar function with a byte wide data bus between the FPGA and the CPU It should be noted that the FPGA is 5 volt tolerant on all of it s I O and therefore needs not to have any 5V level signals attenuated to 3 3V When a memory access is made to the CS2 space of the CPU 036 is taken out of tristate and becomes active The BUFDIR signal as generated by the FPGA controls the direction flow of this device that is to say signal flow is from the CPU to the FPGA during write cycles and from the FPGA to the CPU during read cycles RV 8 Service Manual External Registers U20 and U21 U20 and U21 are octal D flops that provide software control for the following e Resets to the DSP engines e Resets to the expansion ports e Control of external trigger voltages e Amplifier Soft Start and Main Relays e Status LEDs for debugging and boot monitoring e FLASH Write Protect When the unit is powered up these D flops are cleared to zero placing all DSPs and expansion ports into a reset state In addition the external triggers amp relays and status LEDs are held in an inactive state The Flash boot sector write protect is active These flops are strobed by an
381. ng plastic vinyl or Styrofoam in the work area Wear an anti static wrist strap Discharge personal static before handling circuit boards Remove and insert circuit boards with care When removing circuit boards handle only by non conductive surfaces Never touch open edge connectors except at a static free workstation Minimize handling of circuit boards Handle each circuit board by its edges Do not slide circuit boards over any surface Insert circuit boards with the proper orientation Use static shielded containers for storing and transporting circuit boards exicon 3 Oak Park Bedford MA 01730 1413 USA Telephone 781 280 0300 Fax 781 280 0490 www lexicon com Customer Service Telephone 781 280 0300 Sales Fax 781 280 0495 Service Fax 781 280 0499 Product Shipments 16 Progress Road Billerica MA 01821 5730 USA Harman International Company No 070 17537 Rev 0 07 05 These service instructions are only intended for use by qualified personnel Do not perform any servicing other than that contained in these instructions unless qualified to do so Refer to the Safety Summary on the previous page prior to performing any service Lexicon and the Lexicon logo are registered trademarks of Harman International Industries Incorporated U S patent numbers and other worldwide patents issued and pending 2005 Harman International Industries Inc All rights reserved T
382. ngs 2 Continue to hold both buttons until the unit has restarted and the amplifier status LEDs have turned on This operation normally takes approximately forty five seconds to complete To enter the Download mode 1 Press and hold the front panel Mode ZONE2 DVD2 and ZONE3 DVD2 buttons when powering a RV 8 to put the unit into the mode used for downloading the software application 2 Continue to hold both buttons until WAITING FOR DOWNLOAD appears on the front panel display This operation normally takes approximately twenty five seconds to complete DIAGNOSTIC REPORTING diagnostic functionality is reported to the Vacuum Fluorescent Display VFD They report on what test is being executed and if the test passed or failed Diagnostic status and data is also available on an external PC or a terminal via the serial debug port located at the D9 connector labeled RS 232 on the rear panel of the RV 8 In the event a diagnostic failure occurs for those diagnostic tests that report additional failure information such as data sent data received address location etc can be viewed on the VFD display or it can be sent to the serial debug port Vacuum Fluorescent Display VFD The VFD is the primary source of information during diagnostics The exact display information will depend on the test s being executed When an individual diagnostic test is executed the VFD will display the name of that test Groups of te
383. ns The result is that the serial commands made by the remote control from ZONE 2 are repeated by the front panel IR LED which in turn are received by the front panel detector J5 is spark gap protected and diode clamped by D5 and D6 R25 and R26 form a voltage divider to properly bias the IR LED Provision is made for a third zone of remote control but this has not been implemented in this product In this case signals passed along from the external detector via J6 activate IR LED D8 which are then received by IR detector U1 Both components are located in close proximity inside the unit chassis The output from the detector is passed along to the AVRX FPGA for further processing and signal conditioning Bypass Capacitors Sheet 19 This page illustrates the distribution of capacitive de coupling for each of the supply voltage zones Of the six voltage planes used in this project the 3 3VD supply is larger because a far larger percentage of the design uses 3 3V logic This plane therefore has more in the way of high frequency de coupling as well as evenly distributed bulk capacitance The 5VD plane area is the next largest It primarily supplies the Host CPU and its support memory The 1 8V planes are for the core voltages used by the Hammerhead SHARCs The 2 5V plane area supplies the core voltages for the AVRX as well as the Format Decoder The 15V supplies are used exclusively by the two PLL circuits RV 8 PHONO MICROPHONE INPUT BOA
384. ns as a provision This is CPU DSPABIRQ IRQ3 42 monitors the status of INTREQ or ed with FINTREQ from the output steering DSP U25 Each indicates out going data from the DSP sub modules within this chip that must be read by the host processor This is CPU CRYIRQ IRQ 4 5 are internal interrupts They are not utilized outside of the CPU IRQ6 31 is a shared resource with the CPU address bit 20 As such it is not available for use IRQ7 32 monitors interrupts from the Video Board and from the Tuner Module This is CPU VIDTUNIRQ FPGA Configuration Signals FPGA INIT FPGA PROG FPGA DONE FPGA SDATA FPGA CCLK The FPGA is programmed during the boot phase This is accomplished by serially loading the device with the appropriate code The process begins when the CPU asserts FPGA PROG low on port PE6 104 In response the FPGA asserts FPGA INIT low the CPU monitors PE5 102 for status of this signal The configuration memory inside the FPGA is automatically cleared Once this is done the FPGA asserts FPGA INIT high Once the CPU receives this response the loading of configuration data begins RV 8 Service Manual Configuration data FPGA_SDATA is sourced from the PB13 112 port of the CPU along with the serial clock FPGA_CCLK from the PE15 2 port Data is clocked into the FPGA on the rising edge of this clock When this process is complete the FPGA asserts the signal FPGA_DONE to a high state monitored by the CPU on p
385. o run particular tests for troubleshooting User Interface The user interface consists of a set of menus The top menu is the DIAGS MENU and is shown in the top line of the VFD display To view the available menu items turn the encoder knob in either direction and the menu choices will appear in the second row When the desired menu item is shown press the Mode button This selects the menu item If the item is another menu the menu s title now appears in the top line of the VFD and its menu items are in the second row If a test is selected the test name will appear in the top line and the results or information to run the test will be on the second row Once a test is finished or to get out of a menu press the Mode button The group tests are the diagnostics in which if a test passes the diagnostics automatically execute the next test Group tests are the Power On Diagnostics and the Functional Test suite If one of the group tests is selected each test in the group is automatically run if the current test passes Upon successful completion of the group tests the VFD will either display Pass or Fail and come out of the test group to the menu or it will continuously loop If a test fails the VFD and front panel LEDs will attempt to indicate the failed test The test will attempt to loop to keep the signal lines active for debugging purposes If an individual test is selected it will continuously run and report if it passes
386. ock Loop of the Format Decoder at the PLLVDD pin C100 provides local bulk capacitance for this supply rail through the FILT1 pin The internal PLL circuitry requires external band pass filtering which is provided via the FILT2 pin by 899 C98 and C99 CLKSEL selects the source clock for all internal logic in the Format Decoder and is controlled by software When this signal is low the internal clock source is the internal PLL When high then all internal logic is driven by the CLKIN pin directly This signal is significant during the boot phase of RV 8 when the algorithm FLASH U19 is being loaded Writing to this FLASH can only happen reliably when CLKSEL is high PLLVSS is connected to digital ground This is the ground return pin for the internal PLL SDRAM Interface Signals SD CS SDCKE SDCLKI SDCLKO DQM0 DQM1 SD CAS SD 5 SDWE SDRAM is not implemented for the Format Processor As such these pins are all pulled high by RP5 RP6 and RP7 FLASH Interface Signals CRY NVCS CHY NVWE CHY FLCS CRY NVOE DELWE NVCS CRY_A 19 0 CRY D 7 0 GPIO20 GPIO21 The format processor utilizes a 512Kx8 FLASH RAM U19 for algorithm storage The algorithms are loaded into the FLASH during the boot phase Due to a bug in the silicon for the CS49400 the write enable for the FLASH must be delayed approximately 1015 in relation to the address bus CRY 19 0 This is accomplished by R50 C21 which slows down the falling
387. og Input Analog Output s 3 or 6 left channel Left Front 3 or 6 right channel Right Front 4 or 7 left channel Center 4 or 7 right channel Sub 5 or 8 left channel Left Side and Left Rear 5 or 8 right channel Right Side and Right Rear Two different pairs of control bits are used to select the DSP DAC signals or analog input signals for the Main outputs MAIN DACOUT SEL selects the respective DAC outputs for all of the Main outputs Front 6 7 RV 8 Service Manual L R Center Sub L R Side L R Rear whereas MAIN DIRECT SEL selects the 5 1 analog inputs directly The rear channels are switched with separate controls REAR_DACOUT_SEL and REAR DIRECT SEL The output from the analog switch goes to a 6dB level shifter and ADG451 output mute switch The outputs pass through DC blocking caps and relays before going to the RCA connectors The relays mute the Main outputs during a power cycle and whenever the unit is in Standby or powered off The relays are controlled by the MAIN MUTE RL Y signal Control Registers sheet 14 A Xilinx CPLD hold the control registers for the board The main board writes to them via a SPI data bus ADA SCLK ADA SDATA OUT ADA LATCH Their function is loosely related to the function and numbering of the MC 12 registers The control register output bits provide relay control 5 1 direct mux selection analog source selection A D control DAC reset control output selection independent zero cr
388. ol for the rear channels The input comes from the side channels in the 5 1 direct bypass path The rest of the circuitry U44 U33 U23 and U15 are similar to the Rec path page 8 Zone analog output has a maximum output level of 4 Vrms Main D A Converters sheets 10 13 There are eight outputs for the Main Audio Path The D A circuitry is shown for two outputs on each sheet The circuitry is identical for all eight outputs The AK4395 is the same 24 bit D A converter that operates Zone2 The AK4395 DACs are configured through their serial ports pins 8 10 11 MAIN DAC RST puts the pairs of DACs into reset The DACs are followed by 2nd order low pass filter The filter topology is a flat pass band Butterworth filter with the 3 dB point at 127kHz and a pass band flat to 20kHz The filter amplifies the 1 7Vrms differential signal to 7Vrms 11 2 dB and converts it to single ended for the level controls Note these values assume a 0 dBFS digital input signal to the DAC ADGA51 analog switches are used to select either the DAC output or analog input for the respective output These direct analog signal paths have been designed to support two modes 2 channel analog direct or bypass mode Any analog input can be routed directly to the L R Front outputs e 5 1 channel analog direct or bypass mode When this mode is enabled specific analog input signals are routed to specific analog outputs according to the table below Anal
389. oma output The purpose of the dc amplifiers is to transfer the dc voltage at the input to the output to accommodate different S video aspect ratio switching schemes that rely on different dc voltages Main S video at J4 is driven by gain of one amplifiers U16 Iuma and U15 chroma Internal multiplexers in these amplifiers determine whether the s video is taken from the OSD path MSTHRU hi or straight through from the input amplifiers MSTHRU low MSTHRU follows MTHRU unless MSVID YOFF is asserted by logic in CPLD 014 sheet 9 MSVID_YOFF allows main s video luminance to be shut off by 040 sheet 7 when a composite source is in use Amplifier outputs fed through 75 ohm series resistors R145 R142 forming a matched transmission line driver system R144 and R141 compensate for slight impedance errors due to the resistance of the on board connecting traces The chroma output is ac coupled by C80 with a dc level introduced through R18 according to the action of the associated dc amplifier Main S video at J3 is driven by gain of one amplifiers U27 S video at J3 is not subject to the OSD and is not selectively disabled when composite video is in use 6 51 RV 8 Service Manual Main composite video CVID_MAIN1 is driven by U38 Luma and chroma from the input amplifiers are summed by R211 and R212 scaled and the result is amplified by 038 which has a gain of two With composite input there is no chroma and the result is si
390. on the back of the RV 8 verify that the unit runs through its Power On Diagnostics 9 Check each of the front panel switches for smooth mechanical operation Verify each LED turns on and off when the associated switch is depressed and that the display acknowledges each switch function 10 Press each button on the remote and verify that the RV 8 responds to all the remote commands FUNCTIONAL TESTS The following tests verify the basic functions of the RV 8 Power Supply Tests The main power supply in the RV 8 has an operational range of 120 230 VAC 50 60Hz 1300W The following test is for North American line voltage of 120VAC Test 1 Set Variac to the voltage the unit is configured for 0 220 Verify that the RV 8 is powered off at its rear panel power switch Connect the AC power cord to the RV 8 AC power connector Check for power supply shorts to ground 4 1 RV 8 Service Manual Turn on the RV 8 using the rear main power switch Power on the Variac at 220VAC or 120VAC Monitor the current draw During the boot the current draw should be 175mA At the end of the boot when the power amp is on the current should be 375mA Safety Complete Supply Test These tests will verify that the High Current Power Supply operates properly Setup 1 5 rear panel power switch of the RV 8 to the 0 OFF position Disconnect the AC Line cord from the unit Plug the transformer primary
391. oning circuit R43 provides source impedance termination to reduce overshoot The output of the VCO is sent to the AVRX FPGA via MAIN PLL MCKO This is used as a 512FS master clock in 44kHz or 48kHz mode and a 256FS master clock at 96KHz The FPGA divides this clock down to 44 48 96kHz and the result is phase and frequency compared to a corresponding frequency from a selected reference such as the derived clock from an S PDIF stream or the local crystal oscillator When MAIN PLL MCKO is too low relative to this reference the FPGA generates a series of active low pulses to the PLL Error Amplifier U11 via MAIN PLL PUMP DN If MAIN PLL MCKO is too high relative to the reference the FPGA generates a series of active high pulses to the PLL Error Amplifier via MAIN PLL PUMP UP The PLL Error Amplifier U11 is biased at 2 5V via the voltage divider comprised of R38 and R39 The pump up down pulses from the FPGA are buffered by U19 and connected to schottky diodes D18 and D19 When no pulses are asserted the diodes are reverse biased and no current is injected into the summing node of U11 When the VCO frequency is too low D16 will be forward biased by the UPA pulses asserted low by U19 The resulting current through R46 will be integrated by feedback capacitors C41 and C42 This will cause a progressively higher voltage at test point VCOVA This is the control voltage to the VCO module as this voltage rises it causes the VCO output frequency to increase
392. onnect an audio cable between the front left RCA output of the RV 8 and the input of the Distortion Analyzer Using the Menu arrows scroll through the Diagnostic Menu and select the AUDIO I O TESTS In the AUDIO I O TEST menu highlight AUDIO INPUT 1 TEST Press the remote control Menu gt arrow to engage the test The RV 8 is now set to route audio from the left and right RCA inputs labeled 1 to all RCA analog outputs Gain Test GAIN 1 Apply a 997Hz signal 4Vrms to the RV 8 left RCA analog input 1 2 Setthe scale on the Distortion Analyzer to measure 8Vrms signal level 3 Turn all the filters off on the Analyzer Filter not required for this test 4 Verify that the output level measurement from the RV 8 is between the range of 3 10Vrms and 3 70Vrms Note this level Total Harmonic Distortion Test THD 1 Adjust the scale on the Distortion Analyzer to measure 0 01 THD N and turn off the low pass or audio band pass filter 2 Verify that the THD N measured on the Analyzer is less than 0 09 Frequency Response Test FREQ 1 Setthe scale on the Distortion Analyzer to measure a 4Vrms signal level 2 Using the output level from step 4 of the Gain Test set the Distortion Analyzer for a OdB reference to check frequency response of the RV 8 Turn the filter on the Analyzer off Sweep the oscillator frequency from 10Hz to 40kHz Verify the signal levels are 0 10dBr to 0 8dBr 10 2 20 2 0 10dBr to 0 25
393. ophone preamplifiers 06411 analog switch can select Mic inputs 1 and 2 or the phono75 to be passed to the Main Input level control and A D converter These switches work in parallel with the muxes on sheets 1 and 2 to provide a 1 of 12 analog input function When the Mic input is selected the Analog inputs are disabled by bringing MAIN_ANLG_EN low on sheets 1 and 2 The Main Input level control is the PGA2311 which has a range from 31 5 to 95 5 dB in 0 5 dB steps The PGA2311 operates on 5 volt rails and cannot handle signal levels greater than 7 5 Two dual op amps provide the left and right differential audio signals to the A D converter The op amp circuits bias the signals at 2 5 V and attenuate it by 7dB This means a 2 Vrms signal at the output of the level control will be equivalent to 0 dBFS after the A D conversion The PCM1804 stereo A D converter incorporates a multi bit delta sigma architecture It outputs 24 bits at a 96kHz sample rate under normal operation The serial audio data from the A D converter goes directly to the Main board Control signals are used for reset MAIN_ADC_RST and to place the converter in 88 2k 96k or 192k sample rate mode MAIN ADC 96K EN and MAIN ADC 192K EN The main board provides three clocks MAIN ADC which is 256xFS for 44 1k and 48k sample rates 128xFS for 88 2k and 96k sample rates and 64xFS for 192k MAIN FS64 which is 64xFS and MAIN FS which is 1xFS where FS sample
394. or eight digital audio inputs can also be selected as the source for the Zone2 and Zone3 audio paths Refer to the Zone2 and Zone3 Audio Paths block diagram below An analog source can be passed directly to the analog outputs Likewise a digital source can be routed to a D A converter for the analog outputs In addition a 5 1 Dolby Digital or DTS encoded 5 1 digital source may also be selected and passed through a decoder which will output a 2 channel downmix for the Zone2 outputs Zone2 and Zone3 Audio Paths 6 7 Mux to Amps gt sw gt 67 Zone out gt sw b Zone2 dili Ser _ co m lt zone2 N Headphone gt Phono _ 4 sw clks sw A gt 75u Amp 0 gt Mict 2 3 sw sw to from gt gt Phono gt 1 Main Bd 4 81 Phono Zone2 Mux Anlg TM 6 Preamp 7 MUX main zone2 DAC gt ge 7 Output 5 sw gt gt gt _ OVO Mic Tuner y sw Level Ps QAO Pream V 22 i Phono sw sw A zones ed E Zone2 out lt 00 gt Tuner gt 1 54 00 8 1 ome Zone3 Mux Anlg E Qupd gt Zone3 L R 2 2 80 2x v WAS Tuner gt SW __ sw
395. ort PE7 105 It should be noted that LED D46 lights when this signal goes high The CPU may continue with the remainder of the boot phase upon receipt of the FPGA DONE signal Amplifier Environment Monitor and Control Signals FAN DRV 7 1 AC MON The CPU incorporates eight 10 bit A D Converters of which seven are used to monitor the temperature of the amplifier heatsinks This is accomplished by monitoring the analog voltages present on the 7 1 signal lines connected to the AN 6 0 ports of the CPU 98 91 These voltages are provided via thermistors placed in direct contact with the heatsink metal Each thermistor is part of a voltage divider the output of which is converted to a 10 bit value by each converter The output value of the converters are directly proportional to this voltage and hence to the temperature of the heatsink The entire spectrum of voltages is separated into four heat categories From these temperature values the software determines how fast or slow the heatsink fans are to run Under extreme heating conditions the CPU protects the amplifiers from thermal runaway by placing the entire system into standby mode The processor incorporates four Multi Function Timer Units that may be used to generate timing oriented waveforms or as interval event counters Two are used in this implementation Timer 1 generates PWM signal that is used to control environment fans The DRV signal is sourced from the
396. ossing enable and mute for inputs and outputs Three bits of data are returned to the main board through the SPI port HEADP PRES TUN TUNED TUN STEREO A serial stream from the tuner for status and RDS data is also available TUN SDATA OUT Amp Select and I O Connectors sheet 15 The Main Board Digital connector is the source for the clocks and data for the A D and D A converters The MCLK is at 256x the sample rate FS Each converter gets MCLK through a separate buffer and Source resistor The SCLK 64xFS and LRCK 1xFS are distributed directly to the DACs All of the D A converters operate 125 mode J20 and J22 provide a row of test points for quick access to all the clocks J23 and J24 are ribbon connectors from the Mic Phono Board and Tuner board respectively The left and right signal pairs are buffered differentially and presented to the input muxes through these connectors The tuner is controlled through the SPI port signals ADA TUNER CE ADA SDATA OUT and TUN SCLK Power Supply Connections and Regulators sheet 16 There is a separate feed from the switching power supply to the Analog board The Analog board has a 4 pin connector that accepts 15 volts 5 volts and a ground connection to the supply The 15 supply is a shared daisy chain connection from the supply to the analog and video boards Three regulators generate 12 for the tuner 3 3VD for the convertors and CPLD and 5VA for the volume controls an
397. outputs of the DAT machine to the analog left and right inputs of the external amplifier Connect the outputs of the external amplifier to a pair of speakers Place the DAT machine into Record mode Power on the external amplifier Slowly increase the volume on the external amplifier to a comfortable listening level Sweep the oscillator from 20Hz to 20 2 Verify that clean undistorted audio can be heard throughout the frequency sweep Power down the external amplifier Repeat steps 2 through 7 for the S PDIF optical output Use the appropriate digital cable Digital Input to Amplifier Output This test will verify the audio path between the S PDIF coaxial and optical inputs labeled 1 to 4 and the amplifier outputs Setup 1 Connect the video monitor to the main composite output of the RV 8 and turn the monitor on This will allow full viewing of the RV 8 s menus Connect a S PDIF coaxial digital output from a DVD or CD player to the S PDIF coaxial digital input labeled 1 on the rear panel of the RV 8 Connect the outputs of the front left and front right channels channels 1 and 5 of the RV 8 amplifier to a pair of speakers Turn on the RV 8 using the main power switch on the rear panel 4 13 RV 8 Service Manual 5 Once the unit is in standby mode press the front panel standby button or the remote control POWER button to enter normal operation Test 1 To enter the MAIN MENU press the remote control Menu
398. ow checkout procedures carefully to ensure correct results Note It is recommended to use test clips when measuring voltages across pins 4 27 RV 8 Service Manual Note During this procedure all tests are performed with NO INPUT SIGNAL applied to the amplifier inputs and with NO RESISTIVE LOAD connected to the amplifier outputs Bias Adjustment On The 4 Channel Module Channel 1 1 Measure the DC voltage across pins 1 amp 2 of P11 2 Adjust R84 until the voltage measured is 350mV 12mV 338mV 362mYV Channel 2 1 Measure the DC voltage across pins 5 8 6 of P11 2 Adjust R168 until the voltage measured is 350mV 12mV 338mV 362mv Channel 3 1 Measure the DC voltage across pins 1 amp 2 of P12 2 Adjust R252 until the voltage measured is 350mV 12mV 338mV 362mv Channel 4 1 Measure the DC voltage across pins 5 8 6 of P11 2 Adjust R336 until the voltage measured is 350mV 12mV 338mV 362mv Bias Adjustment On The 3 Channel Module Note The reference designators on the 3 Channel Module are identical to the 4 Channel Module except Channel 1 is eliminated Channel 2 1 Measure the DC voltage across pins 5 amp 6 of P11 2 Adjust R168 until the voltage measured is 350mV 12mV 338mV 362mv Channel 3 1 Measure the DC voltage across pins 1 amp 2 of P12 2 Adjust R252 until the voltage measured is 350mV 12mV 338mV 362mv Channel 4 1 Measure the DC voltage ac
399. provision for three interrupt sources In this application only one is used IRQO with the unused IRQ lines pulled to an inactive high state IRQO monitors an active low interrupt provided by the FPGA which is generated coincident with the rising edge of the word clock divided by eight i e 14 112MHz 8 1 764 2 Therefore for every eight audio samples an interrupt is generated to the DSPs Bus Arbitration Device Pins RBPA B3 HBR R10 HBG R11 CS N11 PA R6 BR6 BR1 7 N7 P7 R7 8 P8 SBTS P6 ID2 J3 ID1 J2 IDO J4 These DSP devices operate independent of each other therefore the bus arbitration capabilities of these devices go unused and are wired to their inactive states Since these devices share no resources each DSP has an ID code of 000 as hardwired to the ID 2 0 pins JTAG Interface Device Pins EMU C2 TMS C1 TCK D2 TRST B1 TDI B2 TDO D1 The DSPs support JTAG debugger access to the internal registers Development code may also be loaded via the JTAG port using the Analog Devices ICE development toolkit The principle departure from standard JTAG is the presence of the EMU signal This is a status line that is read by the ICE tools The JTAG signals break out to JTAG connector J17 Jumpers W7 through W10 implement device selection for JTAG By selective jumpering one may talk to U16 U34 or U34 in series with U16 The following diagrams illustrate the various configurat
400. r undistorted video It is not necessary to enter the Extended Diagnostics as was done in the Audio tests Composite Video Input to Composite Video Outputs Test This test will verify the composite video switching function of the RV 8 Setup 1 oO 10 11 12 13 14 15 16 Connect the composite video output from the DVD player to the RV 8 s composite video input 1 Connect the first main composite output of the RV 8 to the composite input of the video monitor Turn on the DVD player monitor and the RV 8 The monitor should display a blue screen Press the remote control MAIN button then press the DVD1 button to select DVD1 as the input for testing the video paths Press the Menu arrow to display the Main Menu Using the Menu arrow button scroll down to SETUP Press the Menu arrow to select the SETUP menu The SETUP Menu will appear with INPUTS highlighted Press the Menu arrow again to open the INPUT SETUP menu DVD1 will be highlighted Press the Menu arrow The DVD1 INPUT SETUP menu will now be displayed Using the Menu arrow scroll to the VIDEO IN parameter Select it by pressing the Menu arrow The DVD1 VIDEO IN menu will open and COMPOSITE 1 will be highlighted Press the Menu arrow to select COMPOSITE 1 This will assign the composite 1 video input to the main composite output of the RV 8 Press the Menu arrow three times to exit to the SETUP menu Using the M
401. r on diagnostics are intended to verify basic hardware functionality of an RV 8 Additional diagnostic tests are available to completely test the hardware and for debugging failures Initially an attempt is made to illuminate the VFD and front panel LEDs for approximately five seconds However during the first four tests the VFD will not be considered functional due to it not being tested During these tests Trap Op Code SH Flash Checksum SH DRAM and VFD RAM the unit will attempt to use the standby LED to indicate if a failure occurs As soon as these tests are completed the VFD will display DIAGNOSTIC TESTS The dots increment in number from both sides simultaneously as the rest of the power on diagnostic tests are completed This informs you that the unit is still functioning The audio outputs digital and analog will be muted during this sequence The following is a list of test explanations The front panel display is shown only for the first test that can use the VFD The reference designators used are from Revision 5 Main Board 710 15550 used on BOM 023 15615 The schematics for the main board are 060 15559 Trap Opcode The Trap Opcode error occurs if during the initial boot sequence an undefined Opcode is fetched The INT TRAP Control register can be used to determine the starting address of the undefined instruction If the trap error occurs an attempt will be made to blink the standby LED using a rate of a single blink per
402. r on one end and an appropriate connector on the opposite end for connection to a Low Distortion Audio Analyzer Shielded audio cable balanced and an XLR female connector on one end and an appropriate connector on the opposite end for connection to a Low Distortion Analyzer 4 Shielded audio cables with RCA connectors on both ends 2 Shielded AES audio cables with XLR male on one end and XLR female on the other 1 1 RV 8 Service Manual Digital S PDIF audio cable with RCA connectors on both ends Digital S PDIF audio cable with optical connectors on both ends 2 Video cables with RCA connectors on both ends 2 Video cables with S Video connectors on both ends 2 Video cables with 3 wire component RCA connectors on both ends RV 8 AC power cord RV 8 remote control Required Tools 1 2 Clean antistatic well lit work area with grounding wrist strap Number 1 Phillips tip screwdriver magnetic tip preferred Number 2 Phillips tip screwdriver magnetic tip preferred 1 4 hex nut driver full hollow 7 16 hex nut driver full hollow 9 32 hex nut driver full hollow 8 slotted mini phone jack driver Slim needle nose pliers 9 32 7 16 1 4 and 3 16 sockets 1 8 drive type 1 8 Ratchet wrench Magnification glasses and lamp Surface Mount Technology SMT Soldering De soldering bench top repair station Lexicon CHAPTER 2 GENERAL INFORMATION Periodic Maintenance Under normal conditions the RV 8 requires minimal mainten
403. re need pull up resistors R73 R74 and R140 DSP FPGA Power Conn Sheet 7 This sheet shows the power and ground pin distribution within the SHARC devices and the regulator scheme for the SHARC inner core power supply This sheet also shows the glue logic CPLD and interface to the VFD on the front panel 6 21 RV 8 Service Manual Power and Ground Distribution U16 and U34 The SHARC devices require two supply voltages One voltage powers the 3 3V IO while the inner core of the device runs off of 1 8V There are 13 pins on each device that require 3 3V 14 pins that require 1 8V and one pin that requires a separate 1 8V to power the internal PLL circuitry There are twenty six digital logic ground pins and one analog ground pin for the PLL When the SHARCs are first powered up care must be taken to ensure that the IO supply voltage does not come up faster than the core voltage supply as destruction to the silicon would result D37 and 047 fast Schottky diodes rated at a forward current of 1 amp These diodes effectively clamp the 3 3V rail to the 1 8V rail ensuring that the two sets of supply pins will track each other during power up to a level of 1 8V thereby ensuring a stable core voltage being present before the IO voltage climbs to its stability point The AGND pin is tied to digital ground in this implementation 1 8V Regulator Circuitry U22 and U39 U22 and U39 are Adjustable Low Dropout Voltage Regulators Resistive divid
404. re taken out of reset and loaded with algorithm code Status is monitored by polling the internal registers of the DSP devices Connection to the amplifiers is tested by serially shifting a single bit up to the amplifiers via the SPI ports and then monitoring its return Power is then briefly applied via the Soft Start Relay which applies a current limited full scale voltage to the amp rails If a problem exists with the amplifier power supply as indicated by either the status read back from the SPI ports or by the Brown Out Interrupt power is immediately removed and status is indicated on the hyperterminal monitor If everything checks out then the Mains Relay is activated and the Soft Start Relay is de activated The hyperterminal will indicate that the unit is now ready Host Processor Sheet 1 This page contains the embedded CPU and its associated DRAM and flash memory for storage of the boot mode and system control software In addition provisions are in place for a separate boot flash memory and emulator support during software development Processor U33 The processor is a Hitachi SH7014 single chip RISC This device implements all system control via a 16 bit wide data bus over 8Mwords of address space This address map is split into four chip select areas CS 3 0 of 2Mwords each The processor is pre configured by four mode pins MD 3 0 which are hard coded via zero ohm resistors to a value of 1001 binary This establishes that
405. re the temp signal usually reads in the range of approximately 0 5 to 0 6Vdc DCLF The card is also protected from DC signals and Low Frequency LF signals The output is monitored and will open the relay if either of these conditions exists The relay will stay off for a few seconds and will try to turn back on If a DC or LF signal still appears at the output the relay will either turn off again or not turn on at all This cycle will repeat until a DC or LF signal is no longer present at the output The output of the amplifier is fed into a low pass filter set up by R46 200k C23 0 47uF R47 2 2k and C24 0 1uF The output of the filter is sent into a window comparator set up by U3 A LM393D and U3 B When the window comparator is triggered it turns on Q15 MMBT3906 which then turns off Q16 MMBT3904 and consequently turns of the output relay K1 RDY CON This is an input signal to each amp channel that is used to turn on and off the output relay A input or no input will keep the relay off A 5Vdc input signal will turn the output relay on if a DC or LF signal is not present at the output of the amplifier RDY MON This is an output signal of the amp card The only function of the RDY MON signal is to report the status of the output relay A OVdc signal means the relay is open and a 5Vdc signal means the relay is closed 6 3 RV 8 Service Manual RV 8 ANALOG BOARD THEORY The analog board of the RV 8 encompasses
406. red by FB1 Pins 4 and 6 provide the LEFT and RIGHT stereo signals from the tuner to the rest of RV 8 while the common return path for both of these is provided by pin 5 Pins 12 and 13 provide the I C bus that controls the tuner system RDS data is fed back to the system CPU on these lines as well R14 R15 and C7 provide standard 12 pull up and edge control as described in the Philips specification for C MH1 is a plated through hole that connects to Chassis Ground at the opposite end of the PCB from LUG1 The RV 8 system provides a ground path on this pin and by keeping it independent from the Tuner functionality and tying it to Chassis Ground here we ensure minimal radiated EMI from the unit Rail Supplies U1 and U3 U1 provides the analog supply voltage to the tuner module and the CRISP processor R12 and R13 program the low drop out regulator U1 to derive 8 5Vdc from the bulk 12Vdc provided C17 provides bulk de coupling capacitance of this output supply voltage U3 provides the digital supply voltage to the tuner module R10 and R11 program the low drop out regulator 03 to derive 5Vdc from the bulk 12Vdc provided C16 provides bulk de coupling capacitance of this output supply voltage C21 bulk de couples the 12Vdc driving both regulator circuits RV 8 VIDEO SYSTEM THEORY The RV 8 video section consists of three major functional blocks video switcher video converter and on Screen display generator OSD The video ass
407. redundant The signals in question are ZONE2 PLL PUMP UP ZONE2 PLL PUMP DN ZONE2 PLL LOCK and ZONE2 PLL FPGA MCKO The Zone 2 D A and A D converter master clocks may be sourced from either the Main or Zone 2 VCOs Two control register bits within the Clock Source Select 2 register make the source selection The following table further illustrates the selection conditions Master Clock Source Select Table Master Clock Source Select REC MCKI REC DAC MCKI ZONE 2 PLL ZONE 2 PLL MAIN ZONE PLL ZONE 2 PLL MAIN ZONE PLL Default MAIN ZONE PLL Default pce ZONE 2 PLL MAIN ZONE PLL oo j 6 38 Lexicon Expansion Slots Signals EXP 17 0 The RV 8 has built in capacity for future expansion capabilities general purpose 18 bit bus is shared between two expansion ports To date the only use for this expansion bus is for a test fixture that may be plugged into either port to test continuity of the signals to the FPGA Beyond this there are no clear definitions of signal function for this bus FPGA Flash Sheet 10 This page contains the configuration FLASH EPROM for the AVRX FPGA FPGA configuration indicator the audio reference clock generator and the Expansion slot connectors Configuration FLASH EPROM U40 This device is a Xilinx XC18V02 2Mbit 3 3V EPROM that is used to store programming algorithms for the AVRX FPGA It is packaged in 44 pin PLCC package This device is used only during de
408. rom the CPU is routed to the CE pin by jumpering pins 2 and 3 on W4 In this case the chip select signal is labeled PROGCS code outside of low level booting may be executed from the memory space occupied by CS1 R88 acts as a pull up for the FLASH pin EEPROM U32 The EEPROM is a 64Kx16 1Mbit device that serves as the primary boot code source during software development The WE pin 43 is pulled high by R160 to prevent inadvertent write cycles to the device that would corrupt the resident code The BOOTCS signal is routed to the CE pin 3 by placing jumper plug between pins 1 and 2 on W5 R187 serves as a default pull up resistor This device is not 6 14 Lexicon used in the released version of this product and therefore is installed during software development cycles only Emulator Support J14 The Emulator socket is designed to accept a 40 position emulator pod for boot code development When the pod is in place it acts exactly like the EEPROM mentioned above The BOOTCS signal is routed to the chip enable pin by placing a jumper plug between pins 2 and 3 on W5 This device is not used in the released version of this product and therefore is installed during software development cycles only Reset Generator U31 The Reset Generator provides reliable one shot pulses of both polarities to various components on the Main Board and to all off board peripheral devices that are required to initialize to a known sta
409. ross pins 5 8 6 of P11 2 Adjust R336 until the voltage measured is 350mV 12mV 338mV 362mv 4 28 Lexicon LEXICON AUDIO PRECISION ATE SUMMARY This chart represents a summary of Audio Precision test settings and parameters used by Lexicon in production testing of all RV 8 products The ATE chart and ATE summary are provided as a reference and supplement of bench test settings found in the rest of the Performance Verification chapter The Audio ATE Test Chart is located on the next page 4 29 TEST PROC RV8 RV8 AUDIO ATE TEST SUMMARY 010 15834 A D Tests Analog Generator Digital Analyzer Switcher Module See Bal Gnd Typical Upper Lower Clock Sample Audio Test Name Note Left Right Freq Hz EQ Curve Z out Unbal Float Level Measure Reading Limit Limit Imp _ Bandwidth Filter Aln B In A Out B Out Source Rate Source ANLG_ZONE2_IN1_TO_DIG_ZONE2_COAX_OUT_96K 200Vrms _ 200Vrms LG ZONE2 IN1 TO DIG ZONE2 COAX OUT 96K THD 1 3 80 Vrms 3 80 Vrms 20 1k 5k 40k None 20 Unba Float dBFS THD N 98 00 86 00 88 00 75 00 120 00 n a 10 Fs 2 None n a n a 1 13 Internal 96000 Analog LG_ZONE2_IN1_TO_DIG_ZONE2_COAX_OUT_96K_DYNRNG 1 4 00 mVrms 14 00 mVrms 997 None 20 Unbal Float dBFS THD N 107 00 104 00 130 00 a lt 10Hz gt 20kHz LP Narrow n a n a 1
410. s RS 232 Serial Input Output Power Requirements Dimensions amp Weight 3 Channel Y Pb Pr format independent Passive 750 gt 150MHz lt 3dB NTSC PAL SECAM to Y Pb Pr 1 Power on off and 1 programmable connector on detachable screw terminals 12 VDC 0 5 amps each 2 9 D sub connectors 120 230 VAC 50 60Hz 1300W universal line input detachable power cord Height with feet 7 76 inches 197 1mm Width 17 3 inches 440mm Depth 21 2 inches 538 48mm Weight 650 29 48kg 3 3 Rack Mounting Environment Remote Control FM Tuner Performance Tuning Range Usable Sensitivity Selectivity Frequency Response THD Noise Signal to Noise Ratio Image Rejection AM Suppression AM Tuner Performance Tuning Range Usable Sensitivity THD Noise Wideband AGC 3 4 RV 8 Service Manual Optional brackets are available for installation in a standard 19 inch equipment rack 4 rack units required Operating Temp 0 to 35 C 32 to 95 F Storage Temp 30 to 75 C 22 to 167 F Relative Humidity 95 maximum without condensation Hand held backlit infrared remote control unit preprogrammed amp learning Requires 4 AAA batteries alkaline batteries recommended 64MHz to 108MHz 4uV 1 6uV typical gt 87dbmV 93dbmV typical 50Hz to 16kHz 0 1dB 1 0dB Below 0 4 at 1 kHz stereo 50dB minimum at 60dBmvV stereo A Wtg gt 50dB gt 60dB typical gt 45dB gt 55
411. s 1 and 2 of Q77 to decrease At the same time D1 and R129 also pull charge out of C157 which stretches the time dependency of the limiter Other Protection D14 ES2GTR and D15 ES2GTR are fly back diodes that steer reactive energy returned from the load around the current gain cells and back into the power supply D5 RLS245 and D10 RLS245 limit collector voltages on the MPSW42 s and MPSW92 s thus reducing cross conduction currents under high current high frequency conditions 6 2 Lexicon Clip The clip signal is derived from the output signal of the error amp This signal is called V_ERR on the schematic V_ERR is fed into a window comparator set up by U4 A LM339D and U4 B When the signal coming out of the error amp exceeds 12 5 it triggers the window comparator The output of this stage is sent into another comparator stage set up by U4 C The output of U4 C feeds a RC circuit R75 R76 and C31 that can be used to change the point at which a clip signal is indicated in this case the C is not populated so it is not being used The output of the RC circuit feeds a fourth comparator stage set up by U4 D This comparator drives the clip signal The clip signal is normally at OVdc and goes to 5Vdc when a clip occurs Temperature Sensing An NTC is thermally coupled to the negative heatsink for every amp channel As the temperature of the heatsink increases so does the value of the temperature signal At room temperatu
412. s BAV99 eR 196 AA 15VA CONNECTOR TO ANALOG BOARD 15VA 4 FB8 C R30 068 63 C27 28 10 25 150PF 10 25 C31 47 6 Y 2 03 2 C3 2 C3 2 B3 1 85 1 05 1 C5 R43 1 D5 1 B5 75US L 1 B5 NOTES mv DSL 183 105 1 85 1 D8 100 1 UNLESS OTHERWISE INDICATED RESISTORS ARE 1 10W R40 1 05 n 4 308 R 1 D5 1 83 2 UNLESS OTHERWISE INDICATED RESISTORS ARE 5 100 R41 3 UNLESS OTHERWISE INDICATED CAPACITORS ARE UF V ye psl C25 241925 FB6 4 DIGITAL ANALOG _L CHASSIS POWER HISYA 100 isopr C26 77 GROUND Y GROUND 7 GROUND GROUND v R52 RAAL 1 C3 UDS l 5 XX XX DENOTES SHEET NUMBER SECTOR R39 C40 100 mn 6 LAST REFERENCE DESIGNATORS USED C46 014 FB8 J4 LUG1 R55 US No Es 1 R53 nA 1 D5 1 03 7 COMPONENTS MARKED WITH NOT ON BOM INSTALLED ONLY 100 FOR WHITE OVER RED nr C39 R54 miAA 1 BAR35 Dia 068 63 mwv 183 DOCUMENT CONTROL BLOCK 060 15529 n SHEET REVISION TITLE v 1 OF 2 2 PHONO PREAMP 2 OF 2 2 MIC INPUTS R37 47 5K 196 C36 475K R36 068 63 432 1 10 25 L C32 T 47 6 COPY 57 1 1 1 1 2003 Lexicon Inc CONTRACT ex CO n BEDFORD MA 01730 TITLE APPROVALS DATE DRAWN SCHEM MIC PREAMP BD RV8 RWH 8 15 02 PREAMP CHECKED cBv 8 15 02 SEE CODE NUMBER REV 2 060 15529 219 CW 8 26 02 FILE NAME 2 ISSUED MaG 8 16 02 15529 2 1 1 oF
413. s amplified by non inverting stage 028 R207 makes the gain be slightly greater than the desired factor of two in order to make up for slight losses in other stages The signal from U28 1 is fed through R204 to the sync stripper and dc restorer sheet 8 The dc correction signal BPCOR returns through R206 to close the dc feedback loop and maintain the video back porch near OVdc The signal OSD Y IN is distributed to output amplifiers 016 027 038 and also feeds the on screen display sheet 7 Chroma selected by U22 MC is ac coupled by C127 and amplified by U28 also with gain slightly greater than two With a composite source selected U22 is forced to input 0 grounding the chroma channel The signal OSD C is distributed to output amplifiers 015 027 038 and U5 and also feeds the on screen display sheet 7 The dc level on the chroma channel of the selected source is fed to two dc amplifiers through multiplexer U23 filtered by C5 The overall gain of the dc path from the chroma input is unity such that the dc voltage on the chroma input is buffered and can be applied to the chroma output The amplifier formed by Q5 Q6 and Q4 applies dc to the chroma of the S video 2 output and Q8 Q9 and Q7 applies dc to the chroma of the S video 1 output Each dc path can be selectively enabled by the MORPHEN 1 logic levels A high logic level disables the amplifier and no dc voltage is added to the corresponding chr
414. s and highlight SETUP Press the Menu arrow to enter SETUP In the SETUP menu highlight INPUTS Press the Menu arrow to enter INPUT SETUP Highlight DVD1 and Press the Menu arrow to select the DVD1 INPUT SETUP menu Scroll down through the DVD1 menu options and highlight ANALOG IN Press the Menu arrow to enter DVD1 ANALOG IN 6 Scroll through the DVD1 ANALOG IN input options and highlight ANALOG 1 Press the Menu arrow to assign the input to DVD1 Press the Menu arrow once to return to the DVD1 INPUT SETUP menu Scroll down through the menu and highlight ZONE2 IN Press the Menu arrow to select the ZONE2 IN parameter 9 Press the Menu arrows until ANLG is displayed 10 Press the Menu arrow once to confirm Analog should now be selected as the Zone 2 source 11 Press the Menu arrow four times to exit the setup menus 12 Connect the oscillator output to the left and right audio inputs labeled 1 on the rear panel of the RV 8 13 Confirm DVD 1 is selected in the Main Zone as well as the Zone 2 section of the front panel 14 Place the DAT machine into Record mode 15 Slowly increase the volume on the amplifier to a comfortable listening level for the speakers 16 Sweep the oscillator from 20Hz to 20kHz 17 Verify that clean undistorted audio can be heard from the Zone 2 digital outputs of the RV 8 18 Once complete repeat steps 1 17 to test Analog Inputs 2 through 8 Change the DVD1 ANALOG IN selected
415. s generated each time a button on the front panel is pressed A second interrupt is generated when the key is released This carries a host interrupt priority of level 0 This interrupt is level shifted to 5V prior to being presented to the CPU LVDSPABIRQJ is an interrupt to the host CPU that is generated whenever a read or write transaction via the SHARC SPI ports has been completed This carries a host interrupt priority of level 2 This signal is level shifted to 5V prior to being presented to the CPU At present this interrupt is masked off and unused by system software 6 30 Lexicon LVCRYIRQ is an interrupt to the host CPU that is generated whenever a read or write transaction the Format Decoder SPI ports has been completed This carries a host interrupt priority of level 3 This signal is level shifted to 5V prior to being presented to the CPU At present this interrupt is masked off and unused by system software LVVIDTUNIRQ is an interrupt to the host CPU that generated whenever RDS data from the tuner module is ready to be read by the CPU This interrupt is a shared resource with the video board It carries an interrupt priority of level 7 This signal is level shifted to 5V prior to being presented to the CPU At present this interrupt is masked off and unused by system software Front Panel Interface Signals FP IR IN1 FP SDATA IN FP SDATA OUT FP SDATA CLK FP SDATA LTCH ENCA IN ENCB IN FP IR I
416. s in the decoded video sync timing With normal video the PLAYSPEED signal is asserted high In trick modes PLAYSPEED is not asserted and system software in the host asserts SYNC_EN U2 Q20 and associated circuitry switch U4 during sync time to construct a video waveform with sync derived from HVSYNC There is time base instability inherent with a VCR even in normal playback To improve the stability of the converted video output a phase locked loop U1 sheet 9 is used to reduce abrupt frequency shifts of the encoder clock ENC_27MHZ A multiplexer within U14 determines whether ENC_27MHZ comes from the PLL or directly from XCLK according to a multiplexer within U14 The preferred clock is dependent on the particular display device 034 is clocked at 24 576MHz by 033 Proper operation of the codec depends on the settings of an extensive set of internal registers of both the decoder and encoder These registers are read and written via the 2 ports connected to the host processor on the Main Board J20 sheet 10 Component Video Switcher Video board schematic sheet 3 Component video switching is performed by means of relays to maximize signal fidelity and format compatibility There is no active circuitry in the video path of external component sources Three sets of component input rca jacks component inputs 1 2 3 feed a 3 wide two tier tree of double throw relays Each tier is comprised of a pair of dpdt relays The tree selec
417. s the remote TUNER soft button The RV 8 s display will display Tuner in the upper left and the AM or FM radio station it is tuned to in the upper right Raise the RV 8 volume to a comfortable level Randomly scan to different radio stations by pushing the TUNE SEEK buttons on the front panel or remote control stopping at each station to listen for clarity Switch between the AM and FM bands by pressing the AM FM button on the front panel or remote control checking stations for clarity Power down the external amplifier Remove the cables from the outputs of the amplifier and connect them to the RV 8 s front left and right amplifier outputs Repeat steps 7 and 8 above adjusting the volume on the front panel of the RV 8 to a comfortable listening level Lower the volume on the RV 8 and plug a pair of headphones into the Phones jack on the front panel Repeat steps 7 and 8 above adjusting the volume on the front panel of the RV 8 to a comfortable listening level Lexicon Trigger Test This test will verify the trigger circuits of the RV 8 For this test you will need the RV 8 remote control and a Digital Multimeter DMM Test oa Power on the RV 8 Turn on the DMM and set it to read DC voltage for a 12V level Using the remote control Menu arrow select SETUP from the Main Menu Scroll down through the SETUP menu and select TRIGGERS Scroll to DVD1 and change the trigger from OFF
418. separate analog input pairs can be routed directly to the outputs bypassing the DSP and converters This mode is available for DVD Audio and multi channel SACD players with 5 1 analog outputs In the first case Input 3 would pass to the Left and Right Front outputs Input 4 would pass to the Center and Subwoofer outputs Input 5 would pass to the Left and Right Side and Rear outputs A duplicate set uses inputs 6 7 and 8 in a similar manner Main Audio Paths 5 1 Channel Input Front L R Direct Analog Path Front L R Mux Main Mux I Sw Front L R AA 1 DAC gt sw y 8 1 Front S 9 3 Ani UR b AID 2 l 952 PL main ciks Ctr Sub Mux T gt 6 man MUX Level C Sub Direct Center Sub sw gt C Sub Direc 1 D gt DAC b sw 4 C Sub 4 C Sub gt sw gt caval A D F Side L R Mux Side Direct Side L R 7 C Sub gt sw to from sw ide Side Direct i gt Main Bd DAC du J gt OIO 1 l 4 Side 5 Side gt sw gt 12 A D Rear Mux Level Rear Direct 8 Side sw sw I DAC gt sw Rear 2 4 evel Rear Direct 1 isi 1 1 6 7 sw Zone2 and Zone3 Audio Paths Any of the ten analog
419. shipping agent When returning a unit for service please include the following information Name e Company e Street Address e City State Zip Code Country e Telephone number including area code and country code where applicable e Serial Number of the unit e Description of the problem e Preferred method of return shipment e Return Authorization number on both the inside and outside of the package 2 1 RV 8 Service Manual Please enclose a brief note describing any conversations with HSG Lexicon personnel indicate the name of the person at HSG Lexicon and give the name and daytime telephone number of the person directly responsible for maintaining the unit Do not include accessories such as manuals cables remote control etc with the unit unless specifically requested to do so by HSG Lexicon Customer Service personnel 2 2 Lexicon CHAPTER 3 SPECIFICATIONS Audio Input and Output Connectors Analog Audio Inputs Digital Audio Inputs Sample Rates Accepts Main Audio Outputs Zone 2 Audio Outputs Zone 3 Audio Output Headphone Output Amplifier Outputs 8 stereo RCA or 5 stereo and one 5 1 channel or 2 stereo and two 5 1 channel connectors 4 S PDIF coaxial RCA and 4 S PDIF optical connectors coaxial and optical input connectors conform to IEC 958 S PDIF standards 44 1 48 88 2 96kHz 16 24 bits PCM audio Dolby Digital DTS DTS ES and DTS 96k discrete data
420. sses are made when the host CPU asserts CPUWRL and CPUCS2 to low states Read accesses are made when the host CPU asserts CPURD and CPUCS2 to a low state The FPGA has 5 volt tolerant IO so the address chip select read and write control lines come directly from the CPU During read cycles the FPGA places data on the bus at 3 3V logic levels This must be level shifted into the 5V domain to be reliably read by the CPU The bi directional ports on sheet two of this schematic provides this level translation to and from the CPU The direction of these level shifting transceivers is controlled by BUFDIR This signal is low during write cycles to the FPGA and high during read cycles from the FPGA CPU accesses to and from the FPGA are synchronous with the core frequency of the host processor 25MHz This clock is provided by the host to the FPGA as CPUCLKOUT RESET is a power up reset signal that clears the state of the internal registers to zero This signal serves little more purpose than to be a fail safe mechanism to ensure proper resetting of the FPGA as this device is cleared whenever the power to the unit is removed The FPGA is re configured at each power up and boot phase Interrupt Sources Signals WCLKDIV8INT LVKYBDIRQ LVDSPABIRQ LVCRYIRQ LVVIDTUNIRQ WCLKDIVSINT is an interrupt to the SHARC DSPs that occurs once every eight audio samples being presented to the SPORT IO LVKYBDIRQ is an interrupt to the host CPU that i
421. sts such as the power on diagnostics have a generic message on the top line of the VFD For example DIAGNOSTIC TESTS is on the VFD while the power on diagnostics are being run An E followed by a number that indicates which test failed displays failure messages Front Panel LEDs The front panel LEDs for the Main input select buttons are also used to display the diagnostic test number The LEDs are used in binary format with the Main Tuner LED as the LSB and the Main DVD2 LED as the MSB as shown in the table below Test Number Main LED Phono Tuner CD TV VCR Sat DVD2 DVD1 BIT 0 1 2 3 4 5 6 7 Running test number 1 would illuminate the Main Phono LED only with all the others off Running test number 3 would illuminate the Main Phono LED and Main Tuner LEDs only with all others off etc If a failure occurs the front panel LEDs indicating the test number that was running when the failure occurred will also continue to be illuminated The diagnostics will attempt to continuously execute the failed test a test loop to keep the signal lines active as an aid in debugging the failure 5 2 Lexicon Serial Debug Port The Serial Debug Port is available to provide diagnostic status to be viewed on an external PC from the D9 connector labeled RS232 Using a terminal or a PC running a terminal program the progress of the diagnostics can be monitored and test failure information is reported The serial
422. tabilized and locked 6 45 RV 8 Service Manual D16 prevents the control voltage from going much below 2V ensuring that the VCO is never driven to a non oscillating state D21 prevents the duty cycle integrator from being driven to the wrong polarity when the loop is out of lock VCO B Sheet 16 Sheet 16 replicates the VCO and PLL circuitry on sheet 15 for Zone 2 Further enhancement of details will not be made here Power Supply Sheet 17 Power Entry Connector J31 Power is brought onto the PCB via J31 a Molex style connector rated for high current C167 C169 provide de coupling of the 5VD supply at a wider range of frequencies than could be achieved with a single high value capacitor All of the logic supply voltages are derived from 5VD The 15V rails are de coupled by C171 C176 in the same manner as the 5VD rail These supply voltages are used to derive power for both VCO circuits output triggers and environment fans Chassis Ground is picked up by LUG1 which provides mechanical contact with the chassis via the rear panel 2 5V Regulator U12 This regulator provides a supply voltage for the AVRX FPGA core and for the Decoder DSP core It is derived from 5VD an LM2937 This device is a fixed output voltage regulator specified at 2 5V It is rated for 500mA current which is far less than the required current C54 provides local bulk capacitance to the regulator input while C53 provides it for the output 3 3V
423. te when power is first applied These pulses are approximately 3mS in duration from the time that power is first applied The time constant is set by the value of C116 and is determined by the equation T 2 6 x 10 x C112 Where T is in seconds C112 is in Farads Resistor R111 serves to eliminate false triggering of the output pulse by limiting the current flowing into the CT pin 3 This impacts the value minimally by slowing the rise time of the output pulse Generally this is not critical and therefore can be ignored R110 provides a default pull up of the RESIN pin 2 thereby enabling the reset circuit to work as intended A test point E6 has been provided so that manual triggering of the reset may be accomplished by connecting the test point to ground momentarily This saves the trouble of having to power cycle the entire unit C111 provides high frequency filtering of the internal voltage reference at the REF pin 1 R113 provides a default pull up for the RESET pin 5 while R112 provides a default pull down of the RESET pin 7 C114 is a standard power supply decoupling capacitor Buffers Level Shifters Sheet 2 This sheet contains a set of external registers for software control of certain external resources as well as level shifters interfacing the 5V and 3 3V domains Level Shifters U36 and U37 037 is a bidirectional transceiver hardwired for signal flow from the A ports to the B ports Signals originati
424. temperature is affected by the environment around the RV 8 under test In a warmer location the temperature readings will be higher Fan Test This test checks the operation of the internal fans using the encoder knob to select the fan speed and verifies that the speed of the fans increases with each increment of the fan speed indicator The fans are located at the bottom of the RV 8 chassis Two fans are on the left side and two are on the right side of the unit Setup The front panel display should indicate FAN TEST FAN Speed 0 Test 1 Turn the encoder knob slowly clockwise until the display indicates FAN Speed 1 Verify that the fans have started turning Turn the encoder knob slowly clockwise until the display indicates FAN Speed 2 Verify that the speed of the fan speed has increased from previous step Turn the encoder knob slowly clockwise until the display indicates FAN Speed 3 gt that the speed of the fan speed has increased from previous step To verify all four fans are working 1 Place your fingers under the chassis on the sides and feel for the draw of the fans 2 Press the Mode 4 button to proceed to the next test Diagnostic Tests Completion When the Diagnostic Tests are complete the unit will display the test results Verify the display indicates FUNCTIONAL TESTS Passed 5 18 Lexicon DISASSEMBLY INSTRUCTIONS The following are instructions for disassembl
425. ter connectivity for accessory boards that will enhance product capabilities An eighteen bit wide bus from the FPGA is source impedance split into two different paths to the connectors These signals are currently bi directional in nature and have no clearly defined function as of yet J25 and J30 are 34 position Flat Flex Cable Connectors FFC that provide a 5VD supply to the expansion card via four pins The contact impedance of the connector pins to FFC cable is such that future expansion cards should not draw more than one amp of current from the 5VD supply Ground and signal return path is provided via ten pins on each connector J25 3 is an active low reset signal EXPA_RESET while J30 3 has a separate active low reset signal EXPB RESET Both resets are Host Processor controlled and allows each expansion slot to be reset independently Expansion Port Series Terminations Sheet 11 This page further illustrates the source impedance splitting of the expansion bus mentioned in the preceding section RP29 RP37 provide source impedance matching for each of the eighteen bus signals originating from the AVRX FPGA Each signal connects to two resistors the opposite ends of which connect to J25 and J30 The effect is that the bus is shared between both connectors but each slot has it s own impedance path back to the FPGA pins Board Interconn Debug Sheet 12 This page contains all of the off board interconnections to the Front Panel Board Video
426. ter extended diagnostics are entered use the front panel encoder Mode and Mode 4 buttons to navigate through the diagnostics The front panel encoder is rotated to display the desired tests The Mode button is pressed to move down through the menu selections and to execute the desired diagnostic test The Mode button is used to move back through menu selections similar to an escape button Esc on a computer keyboard Types of Diagnostic Tests The extended diagnostic tests fall into two categories The first category is for tests required to functionally verify the RV 8 These tests are performed on every unit These will be referred to as Functional Diagnostic tests The second category is for troubleshooting defective units These tests are only utilized if there is a failure The troubleshooting tests can be used to help isolate the source of failures so that units can be cost effectively fixed These tests are referred to as Repair diagnostics Two groups of tests are executed for every RV 8 These are the Loop Tests and the Functional Test Suite The Loop Tests and the Functional suite comprise the automated sets of tests used to verify proper operation of every unit Each of the tests in these suites are run in order unless there is a failure The failing test will loop to allow the electrical signals to be active for troubleshooting You can optionally continue to run the other diagnostic tests in the suite The Repair suite allows you t
427. terminal enter the system via J4 pin B3 This signal is ferrite bead de coupled to remove spurious high frequency noise which drives U5 pin 8 as the signal RXDB The output of this driver provides the receive signal to the Host CPU as USER_RXD from U5 pin 9 W1 and W2 test points for ease of debug C12 C13 provides a high frequency path to ground for noise entering the system from the outside world DSR and RLSD signals from the terminals are not used and so they are pulled up to 5VD via R21 R24 J4 is a dual stacked DB9 F connector DB9 is the standard profile for RS 232 Analog Board Connector J26 J26 is a 40 position Flat Flex Cable FFC connector All digital audio streams and their associated clocks are either sourced from the FPGA to the Analog Board or they return to the FPGA from the Analog Board Detailed description of these signals may be found on page 6 37 Signals not previously discussed or bearing special consideration are as follows RESET is an active high signal generated by Reset Generator 031 It provides power up reset to the Analog Board and is the only positive going reset signal in use in the RV 8 system Amp Board Connectors J18 and J22 J18 is a 14 position FFC connector that provides interconnection with the Crown Four Channel Amplifier Module A ferrite bead de coupled 5V is supplied to the module to power the SPI control logic The ferrite is necessary for the suppression of parasitic frequencies that
428. terparts in the main path There is no dc restorer in the zone2 path so back porch dc level varies with average picture level due to input ac coupling The multiplexer internal to output amplifier U17 allows the zone2 S video luminance to be shut off when a composite source is in use Multiplexer 013 feeds the input dc voltage to the dc amplifier formed by Q2 Q3 and Q1 to transfer dc voltage on the chroma input to the chroma output for S video switching purposes The Zone2 composite output from U18 feeds two 75 ohm outputs connecting to rca jacks on the Video Out board via ribbon cable J16 Zone3 Composite video Video board schematic sheet 4 Zone3 is an additional video path in the RV 8 which provides one composite video output Zone 3 video functionality corresponds to zone2 audio functionality in previous products and the signal naming nomenclature reflects this legacy Signals on the schematic refer to zone2 but this is zone 3 from the user perspective and rear panel labeling Multiplexers U9 and U7 U8 are addressed by the Z2VID_SELn and Z2SVID SELn bits respectively to select an independent zone source but otherwise operate like their counterparts in the main path There is no dc restorer in the zone3 path so back porch dc level varies with average picture level due to input ac coupling Refer to the composite video description in the previous sections for additional information The zone3 composite output from U5 feeds the Zone 3 VIDEO rc
429. the RV 8 are used to verify functionality of the unit and to aid in troubleshooting defective units Familiarity is assumed with the RV 8 structure all applicable assembly drawings FAT process and Audio ATE processes DIAGNOSTIC CATEGORIES There are two types of diagnostics in the RV 8 power on and extended The entire set of power on diagnostics is executed every time a unit is powered on using the rear panel power switch The power on diagnostic tests can be run individually in the extended diagnostics The extended diagnostics contain the tests that are used to verify functionality and to aid in troubleshooting The extended diagnostics also contain additional tests used to verify all the front panel controls infrared communications audio and video performance etc The troubleshooting or repair diagnostics are utilized to troubleshoot an RV 8 if any test fails POWER ON MODES There are two power on modes available power on via the rear panel power switch and by bringing the RV 8 out of standby mode The power on diagnostics are executed every time the rear panel power Switch is switched on When an RV 8 is in normal operating mode pressing the front panel standby button or the remote control SYSTEM OFF button will put the unit into a low power standby mode When the RV 8 is in standby mode pressing any of the front panel or remote control Main Zone 2 or Zone 3 input select buttons and or pressing the front panel standby button or th
430. the AC Power before it is discharged 2 Waitten minutes 3 Remove the top cover and measure the voltage from positive to negative See figure 1 below Figure 1 Measure the Voltage from Positive to Negative Lexicon Changing the Voltage This procedure gives instructions for changing an RV 8 from 120V to 220 240 VAC fF G Disconnect the RV 8 from AC Power Wait ten minutes Remove the cover of the RV 8 Measure the voltage on the output devices Replace the fuse with the proper value see table below for part number listing Move the Transformer primary wire harness to the proper connector see table below for connector information Replace the rear panel Voltage label with the appropriate label for the configured voltage Part number 740 16015 LABEL 100 120V 50 60Hz Part number 740 16017 LABEL 220 240V 50 60Hz 1 AC Fuse on Power Supply PCB 440 16213 440 16212 15A 6 3A Transformer primary wire harness Plug to 100V 120V Plug to 220V 230V 240V connector J15 connector J14 Measuring Power Supply Voltages AN In this procedure testing of the supplies will be performed with the top cover removed and the unit turned on Due to risk of shock do not remove the cover with the unit powered on The Amp channels on both sides of the RV 8 heat sinks are Live Voltage Great must be taken to avoid touching these areas when testing for voltages inside the unit gt
431. the RV 8 10 Press the Mode button to engage the test 11 The display should read SERIAL PORT 1 PASSED and SERIAL PORT 2 FAILED 4 7 RV 8 Service Manual FUNCTIONAL AUDIO TESTS Note The DVD1 input will be used throughout the functional audio I O tests Any other input may be substituted as desired You will need the RV 8 remote control throughout to configure the Setup menus Analog Inputs to Zone2 Outputs Test This test will verify the audio path between the paired inputs labeled 1 to 8 and the fixed and variable RCA Zone 2 output Setup 1 Connect the video monitor to the main composite output of the RV 8 and turn the monitor on This will allow full viewing of the of the RV 8 s menus 2 Connect the RCA left and right outputs labeled Fix from Zone 2 to an external amplifier 3 Connect the outputs of the external amplifier to the pair of speakers 4 Ifthe RV 8 is powered off turn on using the main power switch on the rear panel 5 Once the unit is in standby mode press the front panel standby button or the remote control POWER button to enter normal operation Test 1 To enter the MAIN MENU press the remote control Menu arrow 2 Scroll to the MAIN MENU using the Menu arrows and highlight SETUP Press the Menu gt arrow to enter SETUP In the SETUP menu highlight INPUTS Press the Menu arrow to enter INPUT SETUP Highlight DVD1 and press the Menu gt arrow button to select the DVD1 I
432. to enter INPUT SETUP Highlight DVD1 and press the Menu arrow to select the DVD1 INPUT SETUP menu Scroll down through the DVD1 menu options and highlight DIGITAL IN Press the Menu arrow to enter DVD1 DIGITAL IN 6 Scroll through the DVD1 DIGITAL IN input options and highlight COAX 1 Press the Menu arrow to assign the input to DVD1 Press the Menu lt arrow once to return to the DVD1 INPUT SETUP menu Scroll down through the menu and highlight ZONE2 IN Press the Menu arrow to select the ZONE2 IN parameter 9 Press the Menu arrows on the remote until DIGITAL is listed 10 Press the Menu arrow once to confirm Digital should now be selected as the Zone 2 source 11 Press the Menu lt arrow four times to exit the setup menus 12 Confirm DVD 1 is selected in the Main Zone and Zone 2 section of the front panel 13 Place the DAT machine into Record mode 14 Power on the external amplifier 15 Insert a disc into the DVD or CD player and press Play Slowly increase the volume on the RV 8 to a comfortable listening level 16 Verify that clean undistorted audio can be heard 17 Press Stop on the DVD or CD player and power down the external amplifier RV 8 Service Manual 18 Repeat steps 1 17 to test S PDIF coaxial Inputs 2 through 4 Change the DVD1 DIGITAL IN selected in step 6 to the next appropriate input 19 To test the S PDIF Optical I O use the S PDIF optical output on the RV 8 to the S PDIF optica
433. trol Address 0x00C00000 pop4 ts BOOTLOCK SOFTRLY e CPULED6 Test LED 010 0 D10 is off 1 D10 is lit e CPULED5 Test LED 011 0 D11 is off 1 D11 is lit e CPULEDA Test LED 012 0 D12 is off 1 D12 is lit e CPULED3 Test LED 013 0 D13 is off 1 013 is lit e CPULED2 Test LED 014 0 D14 is off 1 D14 is lit e CPULED1 Test LED 015 0 015 is off 1 D15 is lit e BOOTLOCK Program Flash Boot Sector Lock 0 Boot sector is write protected 1 Boot sector is write enabled e SOFTRLY Amplifier Soft Relay 0 Soft Relay is open 1 Soft Relay is closed External Register U20 bit map Note that the U20 and U21 are word accesses to the same CPU address and that they are write only 6 24 Lexicon DISP RS is a decode of CPUCS3 and the condition CPUADDR 3 1 001 This is an active low signal and is a function bank select signal for the VFD DISP RW is a read write strobe for the VFD When this signal is high the VFD registers are in read mode When low the registers are in write mode This signal is a decode of CPURD CPUCS3 and the condition CPUADDR 3 1 001 or 010 DISP E is a global enable of the VFD and is a decode of CPUCS3 and CPUADDR 3 1 001 or 010 This is an active high signal VFD Data Bus Transceiver U43 This device is a byte wide bi directional tristate buffer interface for the VFD data bus The buffer s direction and tristate contro
434. ts one of the input sets and presents it to the bank of final output relays The final tier of relays RYS RY1 connects the output RCA jacks either to the selected component input or to the video converter One transistor driver is associated with each pair of relays Relays are actuated when the associated PSELn bit is asserted high switching from the normally closed to the normally open circuits Component OSD in the RV 8 is implemented through the video converter which decodes the S video OSD and produces the Y Pb Pr component OSD One normally open pole of RY2 disconnects the luminance component CNV Y in order to effectively disable component output The signals generated by the RV 8 OSD are compatible only with the 480i Y Pb Pr component format When incompatible formats are in use the component OSD is inapplicable and is not accessed by the operating system software On Screen Display Signals Video board schematic sheet 5 OSD chip U26 produces a character based video display that can be overlaid on program video or that can occupy a full screen based on an independent internal video generator OSD modes and parameters are controlled by an extensive set of internal registers accessed via serial interface The character strings to be displayed are loaded serially into the screen memory within the chip The bitmapped patterns that define the shapes of individual characters are stored in external font memory interfaced through the A 1
435. uit is provided by R51 R52 R54 and R56 Audio Output Port Signals DEC DEC OUT SCKI DEC OUT FSI DEC SDO 3 0 The Format Decoder outputs four 125 audio data streams to the AVRX FPGA DEC SDO 3 0 These are multiplexed to an eight channel serial interface that is in the Analog Devices SPORT mode This eight channel interface drives the SPORT inputs of the SHARCs The serial bits are synchronous with DEC OUT SCKI which is equal to 64 FS DEC OUT FSI is the audio output sample rate clock Output Port Map Table 110 AUDATAO DEC SDOO Left Right 109 AUDATA1 DEC 8001 Center Sub 107 AUDATA2 DEC SDO2 Left Surround Right Surround 106 AUDATAS DEC SDOS Downmix OR Left Back Right Back DEC is the master serial bit clock for the Format Decoder and is provided by the AVRX FPGA are DEC OUT SCKI and DEC OUT FSI Test Pins Signals TEST DBCK DBDA FDBDA FDBCK These pins are pulled up to 2 5 via RP8 for normal operation with the exception of TEST which is pulled down These pins are for internal testing by the manufacturer and serve no useful function to this application Power Supply and Ground Signals 2 5VD 43 3VD DGND The CS49400 operates with 3 3V I O and a core voltage of 2 5V There are seven core voltage pins tied to 2 5VD by mini plane on the PCB and four I O voltage pins tied to the system wide 3 3VD plane Diode D24 is a fast SCHOTTKY device rated with a forward current of 1A The diode cla
436. um Generator U48 U48 is a device that deliberately introduces a certain amount of clock jitter to any clock provided to the CKI pin 1 The purpose of this is to provide a quick solution to EMI emissions By introducing a small amount of jitter to the system the overall emission level is averaged out over a very wide band of frequencies rather than isolated spikes of RF being emitted from a relatively low baseband of noise The effect is an instantaneous change in duty cycle of the output clock at any given time The amount of modulation is dependent on the state of the SS input pin 4 When this pin is high the instantaneous duty cycle of the clock at the CKO pin 5 may have increased or decreased by as much as 3 75 When the SS pin is low the duty cycle variation is limited to 1 25 The FS2 and FS1 pins 8 and 7 select the frequency range that the input clock falls within FB17 provides a cleaner equivalent of the 5V digital supply rail to the Spread Spectrum device while C161 acts as a standard de coupling capacitor As of this date the Spread Spectrum operation has not been selected for use in this system Resistors R166 and R170 select between straight unmodified system clocking or spread spectrum clocking The default operation of this unit is with R166 in place straight unmodified clocking 6 16 Lexicon DSP 1 and 2 Configuration U16 and U34 DSP 1 and DSP 2 are Analog Devices ADSP21161N 32 bit SHARC Microcomputers They com
437. ut Test This test will verify the audio path between the paired inputs 1 to 8 and the RCA Zone 3 output Setup 1 Connect the video monitor to the main composite output of the RV 8 and turn the monitor on This will allow full viewing of the RV 8 s menus 2 Connect the Zone RCA left and right audio outputs to an external amplifier 3 Connect the outputs of the external amplifier to the pair of speakers 4 Ifthe RV 8 is powered down turn it on using the main power switch on the rear panel 5 Once the unit is in standby mode press the front panel standby button or the remote control POWER button to enter normal operation Test 1 To enter the MAIN MENU press the remote control Menu arrow 2 Scroll through the MAIN MENU using the 4 arrows and highlight SETUP Press the Menu gt arrow to enter SETUP In the SETUP menu highlight INPUTS Press the Menu arrow to enter INPUT SETUP Highlight DVD1 and press the Menu arrow to select the DVD1 INPUT SETUP menu Scroll down through the DVD1 menu options and highlight ANALOG IN Press the Menu arrow to enter DVD1 ANALOG IN 6 Scroll through the DVD1 ANALOG IN input options and highlight ANALOG 1 Press the Menu arrow to assign the input to DVD1 7 Press the Menu arrow button four times to exit the setup menus 8 Connect the oscillator output to the left and right audio inputs labeled 1 on the rear panel of the RV 8 9 Confirm DVD 1 is selected in the Main Zon
438. utputs Repeat the above tests for the remaining Main Zone amplifier outputs Digital Optical Input to Analog Output Test This test will verify the specifications of the digital input and analog output circuitry Setup 1 Connect a digital audio cable from the output of the Digital Function Generator to the S PDIF optical input 1 on the RV 8 rear panel Connect analog audio cable between the front left RCA output of the RV 8 and the input of the Distortion Analyzer Using the Menu arrows scroll through the Diagnostic Menu and select the AUDIO I O TESTS In the AUDIO I O TEST menu highlight S PDIF INPUT OP1 TEST Press the Menu gt arrow to engage the test The RV 8 is now set to route audio from the left and right RCA inputs labeled 1 to all RCA analog outputs Gain Test GAIN gt N Apply a 997Hz signal 0dBFS to the S PDIF coaxial 1 input of the RV 8 Set the scale on the Distortion Analyzer to measure 8Vrms signal level Turn all the filters off on the Analyzer Filter not required for Gain Test Verify that the output level measurement from the RV 8 is between the range of 3 28Vrms and 3 63Vrms Note this level Total Harmonic Distortion Test THD 1 2 Adjust the scale on the Distortion Analyzer to measure 0 01 THD N and turn off the low pass audio band pass filter Verify that the THD N measured on the Analyzer is less than 0 05 Frequency Response Test FREQ 1 2 Set th
439. velopment cycles and as such is not installed on the Main Board under normal circumstances In order to use the FLASH as illustrated the AVRX FPGA must be placed in Master Serial Mode see the Configuration section on page 6 30 for further details as to how to implement this operational mode In Master Serial Mode the FPGA provides an active low reset signal to the EPROM via XFLASH which resets the internal address counter of the EPROM to zero The FPGA then asserts this reset signal high Once the reset signal is high the FPGA asserts the EPROM chip select low via FPGA DONE The FPGA then provides a clock signal to the EPROM via XFLASH CCLK which causes serial data to be shifted out of the DO data pin into the FPGA DIN pin this signal is called XFLASH DIN on the schematic When configuration has completed the FPGA re asserts FPGA DONE high This signal is inverted by a single gate inside U38 causing D46 to illuminate upon completion of the configuration operation This provides a visual cue as to when the FPGA is done XFLASH CF is output pin from the EPROM that allows the programming port connected to the EPROM to configure the FPGA Programming Ports Signals JTAG TCK JTAG TDO JTAG TDI JTAG TMS The EPROM supports boundary scan testing as well as In Circuit Programming via a fully compliant IEEE 1149 1 JTAG Port J16 is a 1x9 row of pins that can accept a Xilinx download cable By configuring the FPGA in Slave Serial Mode
440. wer and ribbon cables J20 2 23 24 26 27 29 31 and 32 Locate and remove the four screws that hold the Main board to the chassis On the rear panel of the RV 8 locate the screws and other fasteners that hold the Main board to the rear panel 5 20 Lexicon 5 6 Carefully slide the Main board to the front of the RV 8 and up and out of the chassis Store it in a static free area To remove the front panel Belge 19275 Place the RV 8 upside down with the front panel facing you Locate and remove the two screws and ribbon cable J20 and disconnect it from the Main board Turn the RV 8 over Locate and remove the two screws holding the front panel to the chassis Carefully pull the front panel away from the chassis and store it in a static free area 5 21 Lexicon CHAPTER 6 THEORY OF OPERATION RV 8 ANPLIFIER THEORY The RV 8 amplifier sections are designed using the most advanced linear power technology available Using this technology allows maximum amplifier performance under the most demanding and extreme conditions In the RV 8 there are two amplifier modules One module consists of three amplifier channels and the other consists of four amplifier channels Each individual channel is identical schematically but not identical in the way they are laid out For this portion of the theory only one channel will be referenced since all channels are the same schematically All references correspond to the SID
441. would compromise the RFI integrity of the amplifiers The SPI port signals SER CLKA CTRL DATA STAT DATA and DATA LATCHA discussed in greater depth on page 6 38 and will not be expanded upon here Each channel amplifier contains a thermistor that monitors heat sink temperatures local to each channel s output transistors This information is provided to the A D inputs of the Host CPU in the form of a voltage that increases proportionally with temperature TEMP 4 1 are the voltages for the four channel module See page 6 12 for more information J22 is the same form factor as J18 and performs the same function The only difference is that this component provides interconnectivity with the Crown Three Channel Amplifier Module TEMP 7 5 provides temperature monitoring to the Host CPU in the same manner as on the four channel module AMP_RESET is a buffered equivalent active low reset signal as provided by Reset Generator 031 This is used to clear the SPI logic on the modules to zero SPARE AD is intended as a monitoring signal for the amplifier power supply To date this has not been implemented in the design Front Panel Connector J20 J20 is a 40 position FFC connector that conveys all the signals necessary to control and report status of the front panel LED array the pushbutton array the rotary encoder and the Vacuum Fluorescent Display RESET is a buffered equivalent of the active low reset signal generated by 031 This
442. xema 44100 Digta DIG ZONE2 COAX1 IN 44K TO ANLG ZONE2 FIX OUT THD 12 00dBFS 12 00 dBFS _ 997 n a TOEN lt 002 005 0002 0 lt 10 22k 6 18 n a n a Externa 44100 Digital DIG ZONE2 COAX1 IN 44K TO ANLG ZONE2 FIX OUT CLKRNG 1 moors 100dBFS 9 jhoe THD N gt 94 50 rooo ______ 12000 _ lt 10 22k 6 18 na mna External 4365044550 Digital DIG ZONE2 COAX1_IN 44K TO ANLG ZONE2 VAR OUT s S sS s 4 50 aso he 7 19 ma ma Digtal Level 010 19 oro 925075 _ 100k_ lt 10 gt 500k None 19 ma nla External 4400 Dig fe ros 0025004 070 is ns L ZONE2 COAX1 IN 44K ANLG ZONE2 VAR OUT XTALK BE em s h Rene s Ps s P es a ss DIG ZONE2 1 IN 44K TO ANLG ZONE2 VAR OUT DYNRNG 48 THD N 11200 4050 ______ 1000 00 _____ 1 10 2k 6 18 na 96000 DIG ZONE2 1 IN 44K TO ANLG ZONE2 VAR OUT CLKRNG Se EE 50007000 DIG ZONE2 COAX2 IN 44K TO ANLG ZONE2 VAR OUT DIG ZONE2 2 IN 44K TO ANLG ZONE2 VAR OUT GAIN 0 DIG ZONE2 COAX2 IN 44K ANLG ZONE2 VAR OUT THD 1 2 00 dBFS 12 00 dBFS 997 lt 002 1005 002 00 lt
443. zero again DEC IN FSI is the word clock output to the Format Decoder that operates at 44 1kHz or 48kHz dependent upon the sampling rate of the source material multiplexed on the DEC SDI signal DEC 5 is the sample clock 64FS output to the Format Decoder DEC 01 is synchronous with this clock DEC_SDI is the 125 formatted audio data input to the Format Decoder Audio data from the system S PDIF inputs or from the signal MAIN 125 IN1 is multiplexed down to this one signal DEC is the bit clock of the DEC SDI stream and equivalent to 256FS DEC OUT SCKI is the sample clock 64FS output from the Format Decoder Signals DEC SDO 3 1 are synchronous with this clock DEC OUT FSI is the word clock output from the Format Decoder that marks the sample frames on the DEC SDO outputs DEC SDO 3 0 are the four data output streams from the Format Decoder These streams carry the 5 1 decoded audio data This data is further format for compliance to the Analog Devices SPORT specification and routed to the SHARC devices SHARC Interface Signals DSPATXD DSPARXD DSPASPICLK DSPASEL DSPBSEL DSPASP3FPGA DSPBSPS3FPGA DSPASPOFPGA SPORT CLKA A SPOHT FS A SPOHT B SPORT FS B N DSPATXD transmits control data to the SHARCs utilizing the Analog Devices SPI Serial to Parallel Interface protocol Control data is written to the internal SPI Control RAM by the system software and serially shifted out via this pin

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