出原 寿紘 - 大阪大学X線天文グループ
Contents
1. 6 a A Hy A Lf Floating Level Signal Level Hip 2 12 21 26 CCD CCD X X CCD X CCD XX CCD2. 4 SOI ASIC VHDL
3. CCD X CCD 15 CCD CCD CCD COD CCD
4. ODS 1 B 7 c CDS CDS ASIO B 3 3 AD B 6 2 ADO Analog to Digital Converter NZNO ADC
5. spurious charge spurious charge Janesick SCH 1997 spurious charge 10 2000 11 2 7 4 FDA EET 12 HOC TH a TO SE HOC x 77 HOC
6. A SOI CMOS XX CCD LYF ASIC IEEE 89 3
7. 1 74keV 2 3 CCD 2 CCD CCD XX CCD COCD
8. W n mathematica AD W n 19 3 4 ASTRO H ASTRO H 550km WEER 30 Low Earth Orbit LEO 24 ASTRO H SXI ASIC 3 4 1 Total Ionizing Dose TID Total Ionizing Dose TID TID LSI TTD 3 7 ote
9. 2010 2 H EE AM 90 1 D Matsuura H Ozawa E Miyata H Tsunemi H Ikeda Development of an analog LSI for readout of X ray CCDs Nucl Instr amp Meth A 570 2007 140 2 X http www astro isas jaxa jp asca outline 3 Astro E2 XIS 2004 4 Astro E2 X CCD XIS OAK X 2004 5 E Miyata amp K Tamura Novel Photon Counting Detector for 0 12013100 keV X Ray Imag ing Possessing High Spatial Resolution Japanese Journal Applied Physics 42 2003 L1201 6 CCD X 2004 7 H Brauninger R Danner D Hauff et al First results with the pn CCD detector system for the XMM satellite mission Nucl Instr amp Meth A 326 1993 129 8 McLean I S Electronic Imaging in Astronomy Paraxis Publishing Ltd 1997 State Im ager
10. TID SEE SEU Single Event Upset SEL Single Event Latchup 2 SEU SEU 3 9 3 9 5 V 0V PMOS a TRAIL TEMEL RKECERL KE ETAL SCORES 5V CAL 0V GND 5V CMOS
11. 2 VOC 2 22 2 7 3 VOC HOC VOC HOC VOC HOC W spurious charge spurious charge Janesick 9 TO CCD CCD x 2 23 25 MEAZICIEFLASb AY SNA ZUY BAATZ CCD
12. 49 BABRI AS 6 1 78 1 kHz 10 5 bit DAC 0 3 2 5 bit DAC 0 10 mV 18 mV 5 bit DAC 3 14 mV 14 mV 4 3 BO SFY TIS 4 3 60 kHz 78 1 10 5 bit DAC 0 3 mV 10 18 5 bit DAC 0 14 14 5 bit DAC 3 e 1 20krad 1 3 33 krad hr 6 20 krad ch mVl INL
13. 6 2 6 1 CCD CCD 2 13 CCD Fe 10 CCD CHSENKAROA X Y CC ASE CCD 24umx24um M 512x512 CCD 600x600 2 13 OCCD VOO Vertical Over Clock HOO Horizontal Over Clock
14. 4 8 0 19 ASIC 0 09 cm 4 33 4 35 4 8 ID chip 7 chip 12 chip 13 particle sec 3 0 x 107 388 sec 3 0 x 10 414 sec 3 0 x 10 4 350 sec 3 0 x 10 393 sec 3 0 x 10 3 376 sec 6 1 x 10 337 sec 3 0 x 10 4 1198 sec 3 0 x 10 1206 sec particle cm 7 7 x 107 7 9 x 107 il 9 0 krad 22 2 14 14 15 mA 119 120 mA SEL SELA LET BHE 1 68 MeV cm2 mg SEL SEL 3 SEL
15. 13 SEL z pu P z u e P x 4 5 w 3 SEL 1 P 0 P 0 e 0 05 4 6 SEL 3 carr 95 3 ASIC SC 4 en gt O particle cm co 5 7 x 10 cm particle ASIC 95 confidence level 4 8 61 8x107 6x107 4x107 N x Irradiation level particle cm2 Transit time minute 4 33 ASIO chip7 8x107 6x107 4x107 2x107 Irradiation level particle cm2 Transit time minute 4 34 ASIC chip12 4x108 2x108 Irradiation level particle cm Transit time minute 4 35 ASIC chip13 62 800
16. 2 7 1 CCD E eV X N a 2 14 W N W an vN 2 15 AN VNF Fo 2 16 F 0 12 AE FWHM 2 35 x W x AN 2 eV 2 17 CCD 6keV X 6000 eV AE FW HM 2 35 x 3 65 eV x 0 12 x ae 3 65 eV 120 eV 2 18 CCD AE FWHM 4 1202 FWHM noi
17. 4 9 60 60 2 OW 60 4 9 60 1 173 MeV 1 332 MeV 2 ASIC 4 10 680 mm 4 11 60 10 mm 30 cm CHS M 4 12 44 X 4 10 mm 30mm 50mm LO EWIL ZNSE 5 6
18. i L 10 S109 metal Si p acceptor ion EF P x Qm 0 xq N Qs Qm Qs 0 Qm Qs 0 Qm Qn Qb 0 a wa FEA RE b c 2 2 MOS Ey a b c 27 11 Er E a 2 1 y EEY r U7 REL Ey M 2 2 a Pp Ni exp ae Be
19. 54 gain ch mV gauss sigma of scatter plot ch 0 50 100 150 200 100 150 absorbed dose krd absorbed dose krd 0 8 gt g 0 6 5 J lt 0 4 Oo oO 0 2 0 50 100 150 200 absorbed dose krd absorbed dose krd X 4 25 5 bit DAC 1E 3 3 4 2 2 2009 7 7 8 HIMAC 4 26 HMAC 60 ASIC 150 MeV 400 MeV 2 7 mm 4 9 mm 3 mm 2 3 3 1
20. X CCD IC X CCD Application Specific Integrated Circuits ASIC X CCD ASIC XMM Newton PN CCD ASIC AD Analog to Digital AD AD ASIC ASIC
21. 122 120 gain ch mV 118 116 0 5 10 15 20 absorbed dose krd Xi 4 19 5 bit DAC fH 0 0 gauss sigma of scatter plot ch 0 5 10 15 20 absorbed dose krd X 4 20 5 bit DAC 0 ol equivalent input noise uV 4 21 5 bit DAC 0 W INL 4 22 5 bit DAC 0 5 10 15 20 absorbed dose Krd Sees A JA W IN A yh 2 Als fe UK ANAT WI te 0 ia Vv As P 5 10 15 20 absorbed dose krd 52 124 122 120 gain ch mV 118 gauss sigma of scatter plot ch 116 0 5 10 15 20 0 5 10 15 20 absorbed dose krd absorbed dose krd INL eM ANA OMW VAN NA AN KTM aN equivalent input noise uV 0 5 10 15 20 absorbed dose krd abso
22. LST OPEN IP 16 XX CCD ASIC Noqsi Aerospace John P Doty 1 4 ASIC X ASTRO H 2 1 1 ASIC ASIC ASIC
23. 1 Vps lt Ves Vin Vps gt Vas Vin Ip W 1 Ip 7 Cog Ves Viha Vos Vps 3 1 gp W LL M 3 2 29 Cor 1 W Ip OL Lb Cox Vas Vin 1 a AVps 3 2 ye EW 2 ar Was Vin 3 3 Vp 1
24. ODS sont a Aude Pcie La aan ae damien me RBA AT Y 7 OPREARIC re ne piety width 79 Filtered Signal i EVEN 0 15 0 04 E b Preamplifier output i 2 2 0 02 Sp a i peranna ote gt 0 02 ah it h t _ 0 04 Filtered signal differential outputs 4 0 03 E 0 01 j w0 o o0 oov 2 Time usec Time usec B 7 a CCD B 8 a
25. 2300 3000mm X 4 11 45 4 12 60 4 13 2009 6 2 0 9 2008 Heavy Ion Medical Accelerator in Chiba HIMAO 200 MeV amu SXI ASIC 1 MD01 28 I20 16 krad 1 20 krad 2 200 krad
26. 2 CH mac 5
27. MiKE 30 MiK DAC iCDS DE FPGA 10ns DAOCO fal CCD DAO 12 V 100mV iCDS ADC F COD AD ADO 5 V 12 bit DE iCDS X
28. Er EE IEE np Ep Er 2 9 a EFL Me 2 c 10 100A it a ee Ee Leh Erich KERODI l TRO BZADA ZC ES 2 1 2 CCD CCD MOS CCD CCD Da channel CCD CCD Buried channel CCD CCD 2 CCD 2 3 CCD V
29. kHz 78 1 10 5 bit DAC 3 mV 24 14 0 2 56 4 28 FO YOS4k 9 THC HOO IRL TM SZNBEAY OGH 4 29 2 7 150 a Absorbed dose krad 0 20 40 60 80 Transit time min 4 30 60 SXI ASIO TID 2008 HIMAO SXI ASIC MDO 200 MeV amu vee ome 2 00 x 10 particle sec 15 1 11 x 10 particle sec 63 ASIC
30. Oe IC Bie CBM et RA LET 1 68 MeV cm mg Integral flux ASIC 4 9 K 4 9 LET 1 68 MeV cm mg Integral flux particle cm str sec 4 6 x 10 7 9 x 1074 6 2 x 107 6 2 x 107 particle cm str sec lk ASIC ASIC 2r CH SOC Integral flux 3 9 x 107 particle cm sec CB Oy LEPIK 6 1 x 10 6 1x105 39x102 4 11 Cie De B 819 pixel x 155 bit pixel x 1 6 x 107 4 1 x 10 bit 4 12 SEBU sku 1 SEU 10 ie OSEU A B B SRR EAO LET LET SEU
31. 4 99 994 SEU 1 SEU 819 10 MF SEU ASIC 155 bit 1 bit SEU 120 ADU SEU ASIC A ADOC LET 1 68 MeV cm mg SEU zssu 1 10 5 ASIC 0 09 cm A A 6 1 x 10 particle sec x 0 19 0 09 cm x 0 0105 sec 1 4 x 10 particle em 4 9 1 4 x 10 particle cm2 ASIC HUT Z bit
32. SXI ASIC 0 35 pm CMOS LSI krad 4 13 1 6 20 krad ASIC 144 cm 2 7 200 krad ASIC 45 3 cm 1 4 15 ASIC 144 cm ASIC IC 15 cm FOZ U Yy 7 lk 1 25 MeV 4 5 x 107 4 16 2 ASIC 45 3 cm ASIO 2
33. 1 Vcs V 2 Ves 14 15 03 3 3 3 ASIO SKID CCD CCD ASIC 4 ASIC SXLASIC SXI ASIC MD0O1 MNDO1 MD02 MND02 MND02 4 2 2 MDOT SXI ASIC X CCD 4 3 3 V 5 bit DAC Digital to Analog Converter 2 AD ADC Analog to Digital Converter TSM
34. 10 0 63 fF CHA ZO 5 bit DAC 5 bit DAC 32 AX ADC 1 155 3 5 AM ADC 3 5 CCD Reset Deint Int Post SXI ASIO 2 AX ADC even ADC odd ADC CCD 1 Reset ADCO e477 In CCD 77
35. X CCD SXI SXI CCD X CCD X CCD XX X P CCD 20 keV X 10 AME SXI ASTRO H COD 4
36. 2 3 1 2 3 1 3 CCD 2 CCD 3 CCD 2 4 2 CCD 2 5 2 C
37. AL ADC 28 5 0 3 31 4 0 3 pV 4 8 200 180 160 Power consumption mW 140 120 10 100 1000 Readout speed kHz ASIC1 43 60 27C0 2 505 4 9 60 1 1 173 MeV y 2 1 332 MeV 4 2 4 2 1 60 2009 6 1 2 60 SXI ASIC TID 4 60 2 4 2 2 R 4 2 2 TBq 279 4mx4mx3 1m rad hr 0 1 50 60 5 3
38. 2 24 26 S35 ASIC ASIC X ASTRO H lk ET ASTRO H ASIC X ASIC CMOS ASIC ASTRO H 3 1 X ASTRO H X ASTRO H X 3 1 2013 2 X X ata HEX PA 3 X XX X RR ait 0 3 600keV 3 1 1 X Ra SXI X Soft X ray Imager SXI lk 0 3 20 keV ORK X
39. ASIC CCD COCD K CCD CCD CCD 10 Torr CCD 56 C Fe B 3 CCD B 15 Fe 0 4pF 50 EL T EVEN 5 9 keV 6 5 keV 2 5 9 keV 6 5 keV 5 9 keV 6 5 keV
40. 30 charged particle PMOS V O Vout Vout NMOS GND Time 3 9 PMOS Baa Cross section osEE cm LET Bafa LET MeV cm mg 3 10 Weibull curve 36 4 SXI ASIC 4 1 ASIC 4 2 4 3 ASIC 4 1 ASIC SKXLASIC ASIC CCD ASIC 4 1 1 4 1 NI6703 NI6534 NI 4 2 CCD
41. CCD 1 2 3 2 3 6 22 1 2 3 2 13 X 10 HOC VOC AU CHA HBAS X 2 x2 23 2 7 CCD
42. X 2500 86 1000 100 Counts 10 0 2 4 6 8 10 Energy keV XI B 15 X CCD Fe ASIC B 16 Fe XX XX 67 B 6 3 OKI 0 2 um FD SOI CMOS XX CCD ASIC CCD ASIC Cr 0 8 pF 28 uV SXLASIC 2 33 pV XX CCD Fe 5 9 keV 305 eV X CCD 5 5 uV e7 Pch 2k 4k
43. CCD lk CCD p S Co ORE RRO Hime Bh Si SiO Si SiO CCD p Si n Si CCD CCD SiO Poly 51 Poly Si X 2 3 CCD E CCD A 2 2 X CCD Si 1 X wa Si phe CCD
44. ISV IG1V IG2V ISH IGIH IG2H ISV ISH RD channel stop ISV _ _ IG1V IG2V 1 pixel ISV IGLV IG2V ape IG1H 1G2H Z GeD GND t Z A Lit 1 arc 7A tT LU lt fir 1 A o SG P1H P2H IG2H IG1H 2 6 CCD 2 4 FDA Bete MOS FET rye CCD FDA Floating Diffusion ae 2 7 FDA FET MOS FET1 FET MOS FET2 FEBT RG Reset Gate RD Reset Drain FET OD Drain OG Output Gate HEIR 3 FET OS Output Source
45. 2 7 e HOC HEK HOC HOC CCD e VOC VO VOC HOC o CCD X X X VOC 2 13 XX 1 CCD 1
46. LET Erer BHW Sr cm 1 ELET ST I particle sec FAA D amp I KNEX Gy J kg 100 rad 4 3 ELET S n I Gy sec 4 4 150 MeV LET Erer 4 38 x 107 MeV cm mg 3 mm ASIC 0 09 cm2 0 56 CH t 2 00 x 10 particle sec 1 11 x 10 particle sec 2 9 krad hr 158 krad hr 1 MeV 1 6 x 10 7 J CHS Ml 4 30 169 krad 4 31 4 32 ch mV MNDO2 MDO1 channel 0 4 7 MND02 ADC MND02 169 krad Ilch mV
47. 5 9keV XX 1600 XX X 1 8 keV K 2 X 10 keV W 3 65 eV CHS 14 KIA K 1 83keV Si X 1 74 keV X MO Si 20m D CCD X CCD Si
48. 10 5 bit DAC 0 5 bit DAC COD 5 bit DAC 5 bit DAC 0 0 V DAC 4 1 Ze 4 1 HAT WIE kHz 19 5 39 1 78 1 156 312 625 5 bit DAC 0 10 ImVI 18 16 37 T Q Z A 4 1 Ac NTI 5 bit DAC setup Test board CCD clock analog signals simulato divider FIFO 1 FIFO 2 control signals NT6534 bitstreams clock frequency setup 4 2 38 Pixel number T T FTF eS a OOOO O A ee SS PETTEE EET os SS ees Eo RT 530 channel0 even avian S OO HH uae SN J channel0 odd s y e s i
49. 4 53 2 mV 85 2 mV 117 mV 147 mV mV ch mV ch 84 4 C 0 4 pF C 0 8 pF e C 1 6pF z Model O O Q O lt 9 5 5 8 pe 0 100 200 300 Input voltage difference mV B 13 Equivalent input noise uV 30 40 50 20 0 5 1 1 5 Feedback capacitance C pF B 14 CCD 85 2 mV 8 B 3 X CCD CCD V PV 6 27 SG 7 6 PH 7 6 RD 11 RG 6 3 OG 3 OD 22 kHz 97 CCD FC 56 Torr 107 B 6 X CCD B 6 1 ASIC
50. Weible curve 3 4 1 LET SEE 3 8 x 107 cm particle bit 4 13 64 Integral flux particle cm7 sr sec 1000 100 10 0 1 0 01 10 1074 10 gt 10 107 10 8 107 10 10 10 1 10 2 10 23 GCRs only GCRs 90 worse case solar activity GCRs singly ionized anomalous 1 LET MeV cm2 mg 4 37 ASTRO H LET 65 43 ASIC ASIC 10 C 30 YC 10 C 0 C 40 C 4 3 1 4 38 ASIC NI 7 5 cm 5 cm 2 5 cm ROFL D 25
51. 10 2 SXT ASIC 22 krad TID 60 33 p y ray 3 7 NMOS Mei ic Ba EILNE BS 10 10 104 amp 1000 Oo 100 10 Trapped electron 1 Bremsstrahlung 0 1 lt Trapped proton 0 01 Total 10 0 1 1 10 Depth mm 3 8 ASTRO H 3 34 Sigle Event Effect SEE Sigle Event Effect SEE
52. 4 1 18 mV 2 16 mV o 78 1 kHz INL 0 2 XIS 33 4 6 TINL 156 kHz AD ADC INL 0 10 3 2 41 INL 0 10 100 1000 Readout speed kHz M46 AX ADC INL 156 kHz AX ADC INL 0 1 0 3 4 1 3 4 4 4 5 ch mV 4 7 ADC 78 1 kHz AD ADC part 28 5 31 4 uV 8 AY ADC 29
53. CCD CCD CCD CCD LRT ORAS BEBO EL XX CCD X CCD CCD CCD MOS
54. ASIC X ASTRO H 3 1 1 X SXI CMOS 2 3 2 1 CMOS 3 2 2 CMOS 10 10 10 13 13 14 15 16 16 17 20 20 21 2 22 22 24 24 24 25 26 3 3 3 4 4 4 1 4 2 4 3 5 A A 1 A 2 B B 1 B 2 B 3 B 4 B 5 B 6 PSC Ape cas Gar Ge Gh hs tas Es Ate ahh Eh ee a ee es a be ed 30 3 3 1 SXLASIC X CCD 31 0 1 IINRNRTF Bord TI hh 31 ASTRO H 33 3 4 1 33 3 42 ee 35 SXI ASIC 37 ASIC a 37 4 1 1 me ge toe sch ik God Axo Ged II 37 4 1 2 4 wow GA eS See ee eee REE we E ES 41 4 1 3 sc a 42 4 1 4 42 JI a 44 4 2 1 60 oo a 44 4 2 2 RRF YORAR oaa 55 a a 66 4 3 1 a say hich ge che i GE ads Be Rh Re 66 43 2
55. 66 0 4 A a A normal cable 30 f L A A J A A fabricated cable J x o 0 3 A 2 L 4 gt 2 20 A 0 2 o Z A g normal cable A 5 A fabricated cable E 10 0 1 Z A aa sad emdi even ana AR ot dao oi evenO evenl even2 even3 odd0 oddl odd2 odd3 i l 0 0 4 39 NI normal cable fabricated cable ADC IINL 4 40 pt1000 pt1000 R OQ Mee TPC 4 40 NI6703 NI6534
56. 6 2 6 2 5 bit DAC 2 0 6 C 4 42 36 ch mV XI 4 42 4 12 ch mV ch mV W Val Gane Valnin 100 4 15 V alt 20degcC Val ch mV 0 40 C KEZ Valmas Valmin 20 ch mV Valr_2oqegc 4 43 W 5 bit DAC 0
57. 58 MD01 16 krad even odd TID MOS 20 MD01 3 60 MND02 TID MD01 MND02 QFP MD01 QFP E aa MNDO2 MDOT
58. ROMER 1 SG RG MOS FET1 2 7 1 Floating diffusion RD Floating diffusion RD 17 OG Output Gate voltage RG Reset Gate clock 2 ine P1H SG RG RD Reset Drain voltage High 6V OD Output Drain voltage Low 8V RG OD 20V MOS FET 1 OG 3V MOS FET 2 S a Sh SRE Pa 1 RG Floating diffusion WARS YY ye IV iY f Aa i RD Ate E F SG High RG High PIH Low RD 12V RG MOS FET 1 P1H OG 3V 2RG ae a floating level floating level SG High P1H Low RG Low RD 12V OD 20V RG MOS FET 1 a Sean MOS FET 2 Hes 3 SG SG signal level Yh SER HI signal level P1H High SG Low RG Low 27 FDA 18 2 RG MOS FET1 2 7 2 RD
59. 4 5 HTMAC LET 4 5 LET 21 Ay Selden 4 5 HIMAC TR MeV amul 150 400 mm one 4 9 0 56 0 19 lparticle secl lt 2x 10 lt 2 10 LET MeV cm2 mg 4 38 x 10 1 68 4 26 Heavy Ion Medical Accelerator in Chiba HIMAC 4 27 K 4 28 ASIC MEL ASIC 3 1 mm 150 MeV
60. CCD 12 electrode electrode electrode e e e Oxide Semiconductor Transfer direction Potential X 2 1 CCD 1 2 2 CCD CH4 CCD GiO gt poly Si SiO Py 2 1 1 CCD MOS OCD 3 2 2 27 a
61. 4 4 19 ch mV 4 20 4 21 4 22 INL 5 bit DAC 0 4 23 5 bit DAC ff 3 ch mV AEDS ZA INL 5 bit DAC 0 3 R 4 4 4 19 XI 4 25 ADC channel 0 even channel 1 even x channel 2 even channel 3 even channel 0 odd O channel 1 odd channel 2 odd channel 3 odd 50 124
62. ASIC ASTRO H XX FFAST 1 1 1 12 1 3 1 4 2 2al ZZ 2 3 2 4 2 0 2 0 20 3 3 1 9 2 X X CCD X CCD Charge Coupled Device CCD 21 1 CCD 2 1 2 CCD CCD X 2 2 1 XX 2 3 1 2 3 2 3 2 FDA 2 5 1 252 os gt 2 5 3 awe ath oh at CCD 2 6 1 CCD 2 7 1 KRIOS 2 7 2 WR aaa 2 7 3 20 27 4
63. 1 24 um x 24 um 512 x 512 2 33 uV e7 i D 3 CCD TEG TEST BOARD Vi sO51 ort 305 0 3905h 0 Oi Oi B 9 CCD ASIC B 4 B 4 1 NN ee RA X CCD ASIC CCD OS NN i 24 gm 512 x 512 2 33 uV CHS CCD B 2 OCOCD QFP ASIC COD 1 ASIC 7 1 Sl B 4 2 MiKE MiKE X CCD B 10 MiKEY AF LENT KFS ld 130 mmx160 mm x160 mm MiKE
64. 68 73 X CCD 74 PCCDN ES 0 we een ARERR OE ESS EGS 74 I S A E a AO ee ee 74 SOI CMOS XX CCD ASIC 76 E ws ose ee Dae a eee eee Gee eee eee ee 76 OC ae ey oe Ge a we A a ee a 76 78 Beg eye oa ar a BS ee A a a ee 78 B32 awe bE RR EEE SEEDS ED 79 Bo ADA ng ae ba eae be ee oe a OO reo RO eR 79 IE eF zomea eaae a a ea e a E i ao i 81 B 4 1 81 BAD MiKE 82 BA CE ke a ew a a a a aA 82 B44 oo a 82 ASIC 5 4 4 8 bee 40a 6 ek Oe a ee II 84 X CCD ee 86 B 6 1 X ck ee tei Anh ee ahh ee ot els ee Se in B 6 2 X B 6 3 2 1 Zo 2 3 2 4 2 9 2 0 A 2 8 2 9 2 10 2 11 Zale 2 13 3 1 3 2 3 3 3 4 3 0 3 6 3 7 3 8 3 9 3 10 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 CCD 2 MOS WOT ZIL HEM l BATE CCD CCD SHA ate COD OMe ceo gaara E ea a a e i E a E A 2 CCD 2 CCD
65. 305 eV 287 eV 48 2 pV ODD EVEN 5 9 keV 425 eV MiKE HBS OCD 5 9 keV 6 5 keV 201 eV 197 eV B 6 2 XRT XXY X 10 mm 0 45 mm CCD 1 4 mm CCD 19 25 mm Fe CCD 1 14 3 B 16 X
66. 2 57 430 en 58 4 31 aa 60 4 32 60 4 33 ASIC chip7 ee 62 4 34 ASIC chip12 62 4 35 ASIC chip13 62 4 36 channel 0 even 63 4 37 ASTRO H LET 65 4 38 66 4 39 NI 67 4 40 67 4 41 69 442 ny ee oh wR eS 09 EER RES ES 70 AART AS O E a a ee a ee Be aa Ee AS ha BY 70 4 44 0 40 C 71 4 45 72 AD P
67. Xk CCD 13 Fe Mn Ko 5 9 keV Mn K8 6 5 keV 5 9 keV 144 eV 7 1 XIS CCD 33 Pch 2k4k CCD A 2 A 1 Pch 2k4k CCD 74 A 1 Pch 2k4k CCD BI2 24 4k 1 15 um x 15 wm 2048 x 4096 4 FT FFT WV e7 5 5 1000 100 8 QO 10 0 2 4 6 8 10 Energy keV A 2 Fe 1 R A 2 Pch 2k4k CCD CI 70 kHz 33 5 e7 7 07 0 10 eV 144 6 5 9 keV 19 B SOI CMOS FJOVAZAWVEXR CCD LYE ASIC ASTRO H SXI ASIC
68. X CCD SIS 5 6 a o I la mt L EA f Ale A YA tet 4 oh E PA 2 10 20 2 5 2 Hloating signal level 1 ADC OCOCD SOC 6 TH Nt Sampling Nt Sampling XY 2 11 2 5 3 Hoating signal level
69. 18 Weibull curve So 1 exp F 3 6 osss 50 L LET Li LET RME L gt Lin W curve width JAXA SEE SEU LBT BED 25 MeV cm mg SEL LET BMAD 75MeV cm me LET Bae LET SEE SEE LET 3 4 2 ASTRO H 10 C 30 C NT ASIC CMOS 10 0 C lt 40 C SXI ASIO
70. 3 1 mm 5 21 4 29 2 2 SEL 0 2 A SEL 5 PD 3 3 V 0 1 9 4 6 4 6
71. 4 2 Full Frame Transfer FFT Frame Transfer FT 5 5 pV e CHS Pch 2k4k CCD A 1 A 2 Pch 2k4k CCD 70 C CCD Diese BC 10 Torr CCD 4 x 4 33 5 kHz Pch 2k4k CCD 4 SXI ASIC 4 A 2 Pch 2k4k CCD Fe channel 1 even X 1 1 OCCD XX 1
72. DIE X CCD X CCD XX 4keV XX X Ohandra XMM Newton BM X X CCD X CCD XX X 1 2 X CCD X CCD XX CCD
73. Application Specific Integrated Circuits ASIC ASIC CCD 0 2 15 mV 4 TSMC Taiwan Semiconductor Manufacturing Company 0 35 um CMOS 15 mm 168 mW IC CCD ASTIO COD ASIC 0 2 X CCD 5 5 V e 5 4 ASIC 2013 X ASTRO H ASTRO H 550
74. DE B 4 3 CCD 30 CPU Armadillo 9 PO 104 FPGA Field Programmable Gate Array B 11 Armadillo 9 90mmx96mm 75 CCD B 4 4 B 12 77 7 iCDS ADC
75. PRC B 4 PRC NMOS PMOS NAK om 180 PSRR power supply rejection ratio ce VL VSS negative supply voltage VH VDD positive supply voltage MOS M2 M7 OKI 0 2 am EFD SOI MOS 1 8V 1 O 3 3V B 4
76. CCD ASIC 39 counts Counts Counts Counts 200 150 100 50 200 150 100 50 200 150 100 50 a Ct Ce a channel0 even 500 520 540 560 Pulse height ch 480 channell even 320 340 360 Pulse height ch 280 300 channel2 even 260 280 300 Pulse height ch 220 240 200 150 100 50 channel3 even 360 320 340 Pulse height ch 280 300 channel0 odd 200 150 Counts 100 50 640 660 680 Pulse height ch 600 620 200 150 Counts 100 50 320 340 360 380 Pulse height ch 300 200 150 Counts 100 50 540 500 520 Pulse height ch 460 480 channel3 odd 200 150 Counts 100 50 480 500 520 Pulse height ch 440 460 4 4 40 Decimal value Residual 20 15 10 5 0 5 10 15 20 Voltage difference mV 4 5 a 78 1 kHz 0 even ADC ADC CCD 12 bit
77. 22 000 FDA oaa ee ee CCD 2 a CCD 26 60 De JG be ox te apna hed ecg ah dhe ce ese Sp GG ts Co th 2 A a Po I FW ID Jp bh devk dads amp amp Och IAs Bids bd Ss ho HR Sao od Soke we A Sock wD EO Mh wg GOO Kk 4H GH We Oe A CODD Y wc 6 encase Rc as be 4 cers LES er ARR DE ASTRO H Qhttp astro h isas jaxa jp NMOS NMOS PMOS Pa PAI 4 eae a obo aA TID 1 a ASTRO H SEEC RAF OT Oli ne che ke cote th TI Weibull curve NI 2 a II AAYY OT AS ega me SS SS a ak E ee es ee ee SS channel 0 even INL 22 4 06 amp eee Sh Be BE Ew we EMO SR INL ww aa 2 a 60 4 10 x x Stocks Se Pee BL EE we ee gh a he el ee Awe ee A we ee 45 ER e O E E E E SS 45 4 12
78. 5 cm D 25 4 11 4 39 2 INL 4 38 4 10 5 bitDAC 0 mV 18 16 kHz 78 1 10 ASIC 4 40 pt1000
79. 8 Ea E x T expl arr ce kg VOC X Hee ee yp Het FEY CSA ey eC 2 21 W A NAS ERS BBG R MS LDS Sa fl S LS VOC VOC eV Si 1
80. ADO even odd ADC O channel 0 even channel 0 odd 30 krad O channel 0 even channel 0 odd 200 krad 5 gt 6 36 uV 38 uV TINL channel 0 odd 180 krad 200krad 0 4 4 25 5 bit DAC 3 5 bit DAC 0 PA
81. Linux 0 1 OQ V 0 1 OQ ET ROL 67 4 3 2 ASIC 0 40 C 10 C 20 625 kHz 6 4 11 Ze 4 11 ID 36 35 20 CI 0 10 20 30 40 kHz 19 5 39 1 78 1 156 312 625 5 bit DAC 0 3 10 ImV 18 16 4 41
82. X CCD ASIC 2 XX X XX X CCD X CCD IC CCD X i CCD
83. X Si ae 2 COD X 13 2 2 1 X X 3 1 photoabsorption 2 Compton scattering 3 pair creation CCD 100 eV 10keV HRO X X 10keV 10keV COD X Aa an i eae
84. b Feo INL 0 2 4 1 2 Integral Non linearity INL ADC ADC 78 1 kHz 2 mV CCD 4 3 ASIO 2 AD ADC EVEN ADC ODD ADC 4 8 ADC 4 44 18 mV 25 16 mV 18 ADC 4 5 0 even ADC ADC TINL 2 ADC
85. T T T T T T 790 channel0 even Ne NN PuN IN Ne channel0 even NM Ni Ni un cy eae ho ee ee ee DE n ce pend ree rel mamas PD FR a Ne aa MM oes MM ee ar j oe eg a aa ie an ie oy alee 76D fn nnn tf a 2 750 es 11 SS SR i a i oes sae 740 2 740 Mo I PTE ea 3 Z 730 3 3 ak E r RARS ee 720 PTA TREA 8 T a NE iR ecuador pg one A 710 5 foe oa A 710 pee oe co os io ee aa ent maces ee eT eee fe en ie cen ore ni at are 620s me ne re oa eae eons picket aaa ae 1 iti ess perkins cua on Po ae ane ean ln 9 mw 670 es Ro MGS SS Se ess ee le a E A ARS eae a a Io 660 i j i i i 1 j 1 i 1 i j 0 100 200 300 400 500 600 700 800 8 900 0 100 200 300 400 500 600 700 800 900 Pixel number Pixel number 4 36 channel 0 even 18 mV 4 BEA AY 3 krad channel 0 even 18 mV 4 36 channel 0 even 18 mV 3 kad 20 80 ADU
86. Post AD SXI ASIC 2 ADC AD 155 bit DAQ 12 bit 3 3 2 SXLASICD AD ADC 155 bit 12 bit 3 6 l 1 pixel readout time CCD signal Deints lt Int __ Post ___ odd ADC 35clocks 35clocks 85clocks Rese clocks even ADC oe ee eles Reset 5clocks 3 5 AX ADC AD S cc D O O 3 0 20 40 60 80 100 120 140 160 Sample number clock Ml 3 6 32 bit We Y n n 1 155 155 1 if Y n 1 2 Yn WAN Ere si 3 4 12 bit W n
87. 0 2 an FD Fully Depleted SOI CMOS XX CCD ASIC ORA B 2 ASIO ASIC OKI 0 2 um FD SOI CMOS ASIC 2 5mm 7 IFD SOI SOL 16 a Gate Gate Source Drain Source Drain Source Drain b Gate Gate Source Drain Source Drain Source Drain p SOI layer B 1 a CMOS b SOI CMOS SOI Correlated Double Sampling CDS ADC 1 65 V 33 mW CHS B 2 ASIC B 1 B 1 ASIC OKI 0 2 um FD SOI CMOS gt 2 5mm x 2 5 mm FRU AVE 7 1 65 V 33 mW B 2 ASIC 77 X
88. 2 2 b p ps eNa 2 2 Qs eM4z 2 3 Na zg d o eNA 2 4 dx z 0 d T LO 2 5 fs x 0 2 6 2 4 2 5 2 6 ane r Ay s 2 7 2 zZ zg 0 z 2e Td eN a 2 8
89. CMOS SOI CMOS SOI CMOS CMOS 190 2 B 1 SOI CMOS PNPN 31 LSI Ch SDS SOI SOI CMOS OKI
90. 170 mW IC e ASIC CCD ASIC 0 2 Pch 2k4k CCD 5 5 pV e 5 4 TID ASTRO H 200 SEE LET 1 68 MeV cm mg SEL SEL LET BHO PIR 1 68 MeV cm2 mg SEU SEE
91. CCD X CCD X CCD X 2 COCD 1 1 1 10 CCD 1 3 ASIC CCD
92. Ip Vin I 3 2 NMOS n p n HO PMOS go NMOS NMOS PMOS NMOS 2 MOSFET CMOS Complementary MOS MOSFET Vas VBE Vin
93. 50 4 19 X 4 25 ADC 50 HIMACQ A JOa Bn oO we SR ee BH OO ID BR EERO 55 56 4 31 4 32 MND02 ADC Py ae ok Be ae ee 2 60 PAA Ve He See hoe Peo 2 2 2 een eee Bae eS 61 LET 1 68 MeV cm mg Integral flux particle em str sec 64 ee 66 68 4 42 70 Pch 2k4k CCD 75 Pch 2k4k CCD o oaa 75 CM he wed E sa eich A ewe eh See ee eee Tr XO ODA S beac ee ek 4 Reh a oe oe RR AS 81 X CCD We 86 Eh I 1 F 1 1 X X CCD X CCD 1993 XX CCD SIS Solid State Imaging Spectrometer X X
94. M2 M3 M6 M7 3 3 V source tie 1 O M1 M4 M5 1 8 V source tie core 1 65 V 78 G C filter 2m order low pass filter CDS circuit Signal Filtered Signal Hodie PH AEE ii i B 5 B 3 2 B 5 Low Pass Filter LPF Correlated Double Sampling CDS 4 2 3 CDS CCD CCD
95. MOS FET2 OD OG Hoating level 8SG SG 3 SG 2 7 3 SG ee PR diffusion MOS FET2 floating diffusion signal level 1 3 CCD 2 8 2 9 CCD CCD 26 Hloating level signal level Reset Floating Signal Level Level k 2 8 CCD Reading Floppy Disk Drive EA eee Pee LLPW oor Loy l pe Signal leve i Sps 0 50 a LOPPEO 2 9 C
96. NMOS 2 EH L TEPEL Z RU EFL be L SEARO A AE TTD 1 joule kg 1 Gy 100 rad 3 5 3 8 SHIELDOSE 2 25 oo 3 1 mm 1 1 1 krad
97. 60 ee 46 4 13 60 47 4 14 JI 47 4 15 1 he bx GOSS s SORRY RY Ae 48 AIG WA Ore PIT OF Bs ook we wow XO ME ee Ee ee G 48 4 17 2 a 49 4 18 2 6 isn tae eee owe ee RAR RA 49 4 19 20 krad 5 bit DAC 0 2 51 4 20 20 krad 5 bit DC 51 4 21 20 krad 5 bit DAC 0 52 4 22 20 krad 5 bit DAC 0 52 4 23 20 krad 5 bit DAC 3 53 4 24 200 krad 5 bit DAC 0 54 4 25 200 krad 5 bit DAC 3 55 4 26 HIMAC IEST TIT ISS ohh Whe a 56 ADT HIMAG OC 23 hee ee Se Be ee ee ee E ee i 57 4 28 57 4 29
98. RODO 208 3 0 5O 556 88hea v ofa a ADE in JAPAN Fig 6 Picture of the X ray CCD and ASIC mounted on the test board MiKE system CCD z MiKE control signals D clock and bias trigger AC LVDS OD 22 V ET LVDS 2SC3735 width test pulse signal i Download PRAM bus X ray CCD clk ena 220pF ASIC Sequencer ASIC L control signals lt iCDS ADC 5 control signals PE LE z MiKE iCDS ADC Fig 7 Configuration of the performance measurements 5 L Str der et al Astron Astrophysics 365 2001 L18 6 W Buttler G Lutz H Bergmann H Dietl D Hauff P Holl and P F Manfredi Nucl Instrum and Meth A 273 1988 778 7 H Ikeda et al Nucl Instrum and Meth A 579 2007 701 8 E Miyata C Natsukari T Kamazuka H Kouno H Tsunemi M Matsuoka H Tomida S Ueno K Hamaguchi I Tanaka Nucl Instrum and Meth A 488 2002 184 9 T Kishishita et al Nucl Instrum and Meth A Development of an SOI Analog Front end ASIC for X ray Charge Coupled Devices in press 10 T Tsuboyama et al Nucl Instrum and Meth A 582 2007 861 00000000000000 LU Function CCD frame data generator A FPGA on PC 104 a MEEUUUUOUUOUUUUUUUU Data Processor armadillo 9 Address Data 16bit Register Transmit command Write PRAM Ethernet a b HOLDA HOLDB
99. 27 3 1 ASTRO H Ohttp astro h isas jaxa jp 3 2 CMOS 3 2 1 CMOS CMOS LSI LSI CMOS CMOS 14 CMOS LSI 28 3 2 2 CMOS G b D S B Ged B gate insulator S D NMOS PMOS p type substrate 3 2 NM
100. 5 1 Ryo 1 W L W L 23 MD01 W 75 um 04 pm 1 iMND02 W L 25 um 1 um 16 W W L TID 4 31 4 32 MD
101. CCD OCOCD AC 220 pF ASIC ASIC width LVDS Low Voltage Differential Signaling PC 104 LO FPGA 12 bit 4 bit PCODE 16 bit armadillo 9 armadillo 9 30 CCD B 12 test pulse DAC 82 96 mm armadillo 9 B 11 CY B 10 MiKE MiKE system CCD MiKE control signals ani Data Processor clock and bias trigger C J LVDS CCD frame data Function m E FPGA on PC 104 interface board sete Veet eeeeeeew eee Address Data 16bit Register ge
102. CCD X Ennoton CCD Photoelectron gectron Eeron photon 7 Eiyinding 2 10 CG Oi as Ole Evinding bi Oe 4 a a mc Aen E N electron 2 11 Netectron COCW Si 2 E indin Nanger 2 12 Nauger N Felecton Ebinding photon e 2 13 X
103. EVEN b c CDS b ODD c width faa width CCD DAC 16 B 8 CCD EVEN ODD width 0V 2 width ASIC AD PC104 FPGA width 12 bit 80 KR B 2 X CCD CCD HA P4 6 5B1P 2 HPK N
104. JAXA Open IP LSI SO1 Silicon On Insulator XX CCD ASIC ISAS SOIT ASIC CCD Readout ASIC with SOI technology for X ray CCDs IEEE Transactions on Nuclear Science B 1 SOI SOI Silicon On Insulator Buried Oxide BOX 35 SOI CMOS CMOS LSI B 1 SOI CMOS Complementary Metal Oxide Semiconductor CMOS CMOS SOI CMOS
105. Torr in a vacuum chamber to keep water off the CCD The readout speed of the CCD was 97 kHz Figure 8 shows an X ray image obtained by the CCD processed with the ASIC Each white dot represents an X ray interaction point The shadow image of the heart shaped mask is clearly seen on the image which indicates that the ASIC properly processed the output signals of the CCD An exposure time of each frame image is 14 sec with readout time of 3 sec We summed up 2500 frames for the image We calculated the readout noises from the standard deviation of the horizontal over clocked region The readout noise was 53 7 uV with Ce 0 4 pF In the current experimental setup we cannot avoid the excess noise from a refrigerator and vacuum chamber system Since the readout noise of the ASIC was 35 8 uV measured in the unit test before tuning on the compressor of the vacuum chamber we expect better performances by designing an optimum test board with shielding the external noises B X ray spectrum Figure 9 shows the X ray spectrum of Fe of the EVEN chain The 5 9 keV and 6 5 keV emission lines are clearly separated in the figure We fitted the spectrum around 5 9 keV with two Gaussian functions The energy resolution was 305 eV and 287 eV at 5 9 keV and 6 5 keV full width at half maximum respectively We found that the energy resolution of the ODD chain was worse than that of the EVEN chain a Test pulse 0 1 0 05 E 0
106. 300 mV 2 33 UV CCD A a CE ey 2 1 20 2 33 uV e 23 5 keV XX 3 65 eV e C 1 6 pF 200 mV Cp 0 8 pF 0 4 pF B 13 INL 2 Xi B 14 85 2 mV B 14 26000
107. ASIC 2 X CCD 3 ASIC 4 ASIC 5 ASIC X CCD B ASIC X CCD ASIC eK 2 X CCD Charge Coupled Device 2 1 CCD CCD 1970 AT amp T Boyle Smith CCD 1 CCD MOS Metal Oxide Semiconductor 2 1
108. LET SEU SEL SEE LET SEE 0 C 40 C 10 C 0 C 40 C ASIC lt XIS ASIC 13 A XX CCD ASTRO H Pch 2k4k CCD SXI ASIC 26 A 1 Pch 2k4k CCD A 1 CCD Pch 2k4k CCD Pch 2k4k CCD P CCD 15 wm 2048 x 4196 4
109. 3 625 kHz ch mV 39 kHz 0 2 312 kHz 0 6 Ich mV 0 2 OCOD 6 4 keV Ka 13 eV X X ray Imaging Spectrometer XIS IC CCD 0 40 C ch mV 0 2 33 kHz 34 ch mV SXI ASIC ASIC 68 150 150 100 100 lt lt
110. 6 47 PCB RE OD BV ASIC 144cm X 4 15 1 AA i 4 16 7c ASIC 37 cm 4 15 28 1 cm gt _ O 48 PCB 40cm ASIC 45 3cm 4 17 2 4 18 ASIC 2 5 cm 12 5 cm HS Ai ASIC 30 cm 4 17 24 cm
111. 9 5 H z 50 z 50 1 1 rA 1 a 1 9 9 2 0 5 2 10 5 0 z 10 05 95 oO oO 1 9 AS 0 10 20 30 40 2 transit time minute transit time minute 150 150 100 100 lt lt S 8 50 E 50 S 21 O 3 9 205 8 30 5 a 20 z 30 g 195 S 29 5 o 8 19 T 29 0 10 20 30 40 transit time minute transit time minute 150 100 lt 9 5 5 50 4 40 5 5 40 B S 39 5 oO 39 2 0 10 20 30 40 transit time minute 4 41 69 gain ch mV 100 120 110 90 R 4 12 4 42 O 19 5 kHz 39 1 kHz 78 1 kHz QO 156 kHz x 312 kHz A 625 kHz 120 Pe ES lt 4 AA i i gt SF gt f 2 5 Ss CD 100 am 0 10 20 30 40 0 10 20 30 40 Temperature degC Temperature degC 4 42 ch mV 5 bit DAC 0 5 bit DAC 3 Gain ch mV e 5 bit DAC 0 A 5 bit DAC 3 W Val 10 100 1000 Readout speed kHz 4 43 312 kHz 0 6
112. B 4 37 CREME 25 36 ASTRO H LET LET LET Galactic Cosmic Rays GCR LET 80 LET B 819 pixel x 155 bit pixel x 4 10 63 11 1972 1989 10 90 ote 10 MeV
113. E 5 Dl be 2 a 8 S ar PPT td we 4 i oe fe edo eo a aes e Ogee q 2 z z BON Re Ras i 5 3 IRT Row Pg Binh er 8 3o aotar EA i Rar oe O A A lx ee 4 e o 1 fo i i i i i i i i i i i i i i 0 100 200 300 400 500 600 700 800 900 0 100 200 300 400 500 600 700 800 900 Pixel number Pixel number 340 330 oO o Ss gt gt D 9 Q Q go p GR Ee Ee Gl Ed i Ei 0 100 200 300 400 500 600 700 800 900 0 100 200 300 400 500 600 700 800 900 Pixel number Pixel number channel2 even me eee ee a aman 7 es a ae Te ae T oe eo 2 eo x b e D eo 3 2 2 afrce y lt e e eo 270 ee GAO in hee eae fd E KO Nee ON e o oe oe ad 4 Sa eee ere het ete SAP Lee eae eee 8 A pe er o e A 240 0 100 200 300 400 500 600 700 800 900 0 100 200 300 400 500 600 700 800 900 Pixel number Pixel number channel3 even ae eae man Ge aed Ge Gk ee eer 3 330 Petes re sta rae Ra 3 5 a PR seo e 5 e Cea g E e eo s Ne Mee We z F 320 Heres aa ae eee NA a N 3 A e eS 0 A gipse sas ew a et san aa aes saih OPA ee a a a 300 EE O a A A D A AAN D D 0 100 200 300 400 500 600 700 800 900 Pixel number 4 3 819
114. LSI 17 LST ON B oe ee SEL LSI Linear Energy Transfer LET LET MeV cm2 mg CHS LSI LET LET SEE LET o RED SEE SEE LET SEE LET 3 10 Weibull curve
115. P Doty CCD ASIC MND02 2009 20 Development of ASICs for multi readout X ray CCDs 2008 21 NIST PSTAR http physics nist gov PhysRefData Star Text contents html 22 NIST XCOM http physics nist gov PhysRefData Xcom Text XCOM html 23 i Electronics for Particle Measurements KEK Report 2002 8 2002 124 T Takahashi et al The NeXT x ray mission to exlore nonthermal universe in Proc SPIE 7011 2008 701100 25 Dell SEES http seesproxy tksc jaxa jp fw dfw SEES 26 ASTRO H P X CCD 2010 27 S M RA R 1987 28 H Nakajima D Matsuura N Anabuki E miyata H Tsunemi J P Doty H Ikeda T Takashima H Katayama Performance of an Analog ASIC Developed for X ray CCD Camera Readout System Onboad Astronomical Satellite IEEE Trans Nucl Sci 56 2009 29 H Nakajima D Matsuura T Idehara N Anabuki H Tsunemi J P Doty H Ikeda T Takashima H Katayama Development of high spe
116. used an X ray CCD whose conversion rate was 2 33 V e Since the conversion gain is much lower than that of the existing CCDs for high resolution applications e g 5 uV e7 we expect better analog performances by combining with optimum devices for practical use Another version of the ASIC is now under fabrication in which the non overlapping logic gates are employed for switching EVEN and ODD signal chains The ASIC proves that the FD SOI process can be a practically usable option for front end applications ACKNOWLEDGMENT The authors would like to express their sincere gratitude for the financial support of JAXA with regards to the Steering Committee of Space Engineering TK is supported by research fellowships of the Japan Society for the Promotion of Science for Young Scientists REFERENCES 1 Y Tanaka H Inoue and S S Holt Publ Astron Soc Japan 46 1994 L37 2 M L J Turner et al Astron Astrophysics 365 2001 L27 3 K Koyama et al Publ Astron Soc Japan 59 2007 S23 4 D Matsuura H Ozawa E Miyata H Tsunemi and H Ikeda Nucl Instrum and Meth A 570 2007 140 al d TE FIP PEJ RE g ae rr 1 TTT spirits ie w oo gt 8 g a 2008008 D pE J 4 4 3 p BDDBBBHODODOHDDU c oo J DODOODNDODNDOO0UDHND pi uid gt 3 sp ra HHHOUOUH mm 2T LA T gt D GRD
117. 0 06 0 04 E b Preamplifier output 0 02 Voltage V Voltage V 0 02 0 04 Eo Filtered signal differential ec 4 me 0 02 0 01 Foo py oi 10 0 10 20 30 Time usec P signal EVEN b RAMP signal ODD c width signal 20 10 0 10 20 Time usec Fig 3 Measured waveform traces Left from an upper panel input test pulse pseudo CCD signal preamplifier output and filtered signals Right ramp and width signals Gm C filter 2m order low pass filter Signal CDS circuit Filtered Signal Hate oer Fig 4 Configuration of the LPF and CDS circuit This phenomenon was common In varying degrees to other six channels The energy resolution of the ODD chain for 5 9 keV iron line was 425 eV FWHM We discuss the origin of the phenomenon in the following section For comparison we obtained an X ray spectrum with the Mik E iCDS ADC board The energy resolution processed with the MiK E system was 201 eV and 197 eV FWHM at 5 9 keV and 6 5 keV respectively Since the ASIC achieved the comparable noise level with the Mi KE DAQ system in the unit tests we speculate the external noise coming from the interference with the refrigerator and vacuum chamber system degrades the en
118. 70 Gauss sigma of scatter plot Equivalent input noise e 5 bit DACO e 5 bit DACO A 5 bit DAC 3 A 5 bit DAC3 meee 9 9 3 q z Z 0 0 10 100 1000 10 100 1000 Readout speed kHz Readout speed kHz INL e S bit DAC 0 A 5 bit DAC 3 W Val 6 10 100 1000 Readout speed kHz 4 44 0 40 Ci BUY 4 Aa INL 4 44 SXI 68 kHz 78 1 kHz 8 INL 312 kHz 40 71 Gain ch mV INL 119 118 5 E S a 118 Z os 117 5 e chip 36 e chip 36 A chip 35 A chip 35 chip 20 chip 20 Re 117 0 10 20 30 40 0 10 20 30 40 Temperature degC Temperature degC Sigma of scatter plot Equivalent input noise Sigma of scatter plot ch Equivalent input noise uV e chip 36 e chip 36 A chip 3
119. 8 0 1 pV CHS CCD CCD WV pV e SXI Pch 2k4k CCD 5 5 u V e 5 4 e 4 2 4 1 4 Re 4 8 EYES ASIC 1 156 kHz 168 mW CHS ASIC flee ASIC IC 3 3V 8 ASIC LVDS 3 5 mA 100 OCHA ASIC 168 mW 3 5mA x 3 3 V x 8 92 4 mW ASIC SXI 68kHz CHS 42 Equvalent input noise LV 0 10 100 1000 Readout speed kHz 4 7 APADC
120. ASIC in the following tests B DAQ system Figure 7 shows the DAQ configuration for the performance measurements The control signals for the CCD and ASIC were supplied from the MiK E system 8 which is a flexible CCD operating system developed at Osaka University The MiKE system consists of flexibly configured multiple VME 3U boards In the measurements we combinatorially employes a DAC and sequencer boards to generate analog signals for the CCD control and digital signals for the ASIC readout The DAC was employed to generate each clock for the CCD driver with adjustable output voltages and is controlled by a field programmable gate array FPGA on board the sequencer board The output of the ASIC is directly fed into a data processor which consists of a PC 104 and armadillo9 boards AtmarkTechno The data processor acquires frame data via LVDS lines and transmit data to PC through Ethernet The width signals are converted to binary counts with a scaler driven by a 200 MHz clock frequency in the data processor The MiK E system also supports a stand alone data acquisi tion DAQ capability as is shown with the dashed lines in Fig 7 In this case the output of the emitter follower is fed into the Fig 1 Photograph of the ASIC X ray CCD signal of 1 pixel floating level signal level CCD Signal Test Pulse 1 O pF Fig 2 follower MiK E integrated CDS CDS and ADC board and then the volt
121. HOLDC Voltage V 4 050 4 055 4 060 Time us Fig 10 a Schematic of the non overlapping logic gates b Timing diagram simulated with SPICE
122. of the preamplifier circuit PRC denotes a folded cascode transcon ductance amplifier with a PMOS input transistor The gain of the preamplifier is adjustable from 12 5 to 100 in eight steps by changing negative feedback capacitance Cr with a binary weighted configuration and CMOS switches The measured waveform trace of the preamplifier output 1s shown in Figure 3 Left The feedback capacitance was set at Cs 0 2 pF 2 Band pass filter stage Figure 4 shows the configuration of a low pass filter LPF and correlated double sampling CDS circuit The CDS technique is traditionally employed for CCD readout circuits in order to measure the voltage difference between the floating and signal levels with elimi nating the noise coming from CCDs We employed differential transconductor circuits as a component of the LPF and CDS circuit which are shown as trapezoidal symbols in Fig 4 The CDS circuit samples the floating and signal levels for the LPF outputs and then determine the signal pulse height by subtracting the floating level from the signal level The measured waveform traces of the filtered signal are shown in Figure 3 Left Since the CDS circuit functions as a high pass filter the entire LPF and CDS circuit eventually works as a band pass filter By employing the differential network chain we aimed to expand the dynamic range and mitigate external noises 3 Analog to Digital conversion stage Figure 5 shows the config
123. 01 even odd gt 59 4 7 4 31 4 32 MNDO2 ADC channel 0 even channel 1 even x channel 2 even channel 3 even channel 0 odd O channel 1 odd channel 2 odd channel 3 odd gain ch mV 0 50 100 150 0 5 10 15 20 25 absorbed dose krd absorbed dose krd 4 31 MND02 4 AD ADC oK A MDO channel 0 3 N N Q 3 gt 150 g 150 2 G c 5 5 Q Q 100 100 S J 50 in 50 esaseeaee aes ae agngagaggease ee 0 0 0 50 100 150 0 5 10 15 20 absorbed dose krd Absorbed dose krd 4 32 MNDO02 AX ADC MD01 channel 0 3 60 GAT AY 2 3
124. 5 4 chip 35 chip 20 chip 20 iii 0 10 20 30 40 0 10 20 30 40 Temperature degC Temperature degC 4 45 4 45 78 1 kHz 5 bit DAC 0 3 ch mV 3 20 C 3 INL 72 5 X CCD X CCD ASIC ASIC X CCD 4 TSMC 0 35 pm CMOS 15 mm
125. 5 cm 12 5 cm M418 2 5 cm 12 5 cm HORT UY ZO 1 25 MeV 0 19 2 4 x 10 25 C 4 14 6 46 1Gy 100rad 1 E 06 BEE t us THUS T 200krad ed J 1 E 04 cm 4 13 60 Si 0 9 4 14
126. C Taiwan Semiconductor Manufacuturing Company 0 35 um CMOS 3 mm 15 mm QFP Quad Flat Package QFP 3 3 3 1 SXI ASIO MULE UTU NT i a S A SOA Le SD SIF MPOW 0 0 30 R 3 1 SXLASIC TSMC 0 35 pm CMOS 3 mm x 3mm 15mm x 15 mm 4 3 3 V X ray CCD signal 1 pixel each modulator output 1 pixel 0011010110101 1 00011010100010 0100010001 1010 00100100010001 0100100001 decimation filter floating level 2 xVin 1 xh n h 1 h 2 h 3 V n n th output h n filter coefficient 155 bit stream decimal value 3 4 SXI ASIC 3 3 1 SXILASIC XX CCD 3 4 SXI ASIC ASIO XX CCD
127. CCD EVEN ODD FD SOI CMOS 88 3 3 4 1
128. CD 26 60 3 V Q C V Q C 19 2 5 CCD 1 2 8 floatinglevel signal level floating signal level 2 5 1 2 SARI A D floating signal level f COCD X
129. CD 2 EES Ptype S ilicon A a T P type Silicon pt 1 P1 P 3 lt P 2 GS le we 2 P1 lt P 3 P 2 1 P1 lt P2 en aa nee 3 P1 P 2 lt P 3 g 2 P1 gt P2 4 P1 P 3 lt P 2 ee 8 8 se ST ee aye ee ee gt 2 4 3 CCD 2 5 2 CCD 2 3 2 2 6 CCD P1V P2V 2 TG Transfer Gate TG P2V 16 P1H P2H A 2 SG Summing Gate S8G TG P2H 1
130. HE ASIC Fabrication process OKI 0 2 um FD SOI CMOS Chip size 2 5 mmx2 5 mm Number of channels 7 Power rails 1 65 V Power consumption 33 mW Max readout speed 200 kHz threshold voltage was set to 0 V in the measurement Finally the width signals of EVEN and ODD chains are merged in a multiplexer to be delivered to an external pin of the ASIC The A to D conversion is established by running a scaler during the interval of the pulse width with an appropriate clock frequency III EXPERIMENTAL SETUP A Test board In order to evaluate the performance of the ASIC we combined a chip with an X ray CCD Figure 6 shows a picture of the CCD and ASIC mounted on a test board We inserted an emitter follower circuit and capacitor of 220pF between X ray CCDs and the ASIC In the left side of the picture an X ray CCD is placed in a PGA socket We used an N channel FFT full frame transfer type CCD with a pixel size of 24 um x 24 um and imaging size of 512 x 512 pixels provided by Hamamatsu Photonics K K HPK The specifications of the X ray CCD is summarized in Table II The conversion gain of the CCD is 2 33 uV e which is defined as a ratio of the CCD output voltage per electron generated by photoelectric absorption The ASIC is shown in the right side of the CCD which is placed in a ceramic package and mounted on the test board with a QFP socket Since there exists only one readout node in the CCD we evaluated a typical channel of the
131. OS OREX a lk NMOS b PMOS p nm MOSFET Metal Oxide Semiconductor Field Effect Transistor 3 2 NMOS Ee a b NMOS p MOSFET PMOS NMOS MOSFET NMOS p n DRAIN GOURCE SiO D G B 4
132. age difference between the floating and signal levels are sampled by a 12 bit analog to digital converter The maximum ADC channel and output voltage in the MiKE system are 4096 ch and 5 V respectively The control signals for the iCDS ADC board are generated by the sequencer board Before measuring the ASIC performance we determined the CCD conversion gain S with the MiKE DAQ system We combined the CCD with the Mik amp 1CDS ADC board and obtained an X ray spectrum of Fe Since we know the total gain Aicps apc of the Mik E iCDS ADC board in advance 20 x 13 6 the output ADC difference between 5 9 keV and 6 5 keV lines equals to 6 5 keV 5 9 keV 4096 ch _ _ _ S AioDS TADO EG 5 V where esi 3 65 eV e We calculated the conversion gain at 2 33 wV e for the X ray CCD 1 IV PERFORMANCE EVALUATION COMBINED WITH AN X RAY CCD A Imaging capability We performed X ray irradiation tests with an image mask to demonstrate the imaging capability for the CCD ASIC system A mask of plastic plated with nickel is placed above the CCD by 1 4 mm It has a length of 10 mm and thickness of 0 45 mm A radioisotope Fe is located above the detector by 19 25 mm We operated the CCD at 56 C to reduce the dark Configuration of the preamplifier circuit PRC denotes a transconductance amplifier with a PMOS input transistor and SF denotes a source current and at a pressure of several x10
133. ch 2k4k CCD tetawetecdwhesebeheeadebae thee 74 A 2 X LL ee 75 Bel AZ CMOS SOM MOS a 2 te eae ee be ee ae ee Bare ee eed 77 B2 A CO Ses oa Bee ok a OEE TT Bee EE 78 B 4 78 B 5 79 BG 2 ADC sos Soe ew Se ew a 80 Ber tS Oi das amp ey eae se ee amp Bebe RY Bare AS Eee G 80 Be Fe aD 4 wk SR ewe PAK owe we BS hoe be dk 80 B9 CCD ASIC 2 VU i ee SS 6 ow eh Re we Re 81 BIO NMGKE VAD 666k ee eben OHA RYDGES RAR ORES 83 PITIS AZAT IE A Cb Ee ee SEES 83 B12 Sa AO UIZ Neee oe hee Re ek ee Shee 83 BLUZAT SII VSS Cee CTA AO LTE O yrei pya 85 B 14 cas ah Rb Gh Re aR EEA DEY 85 Belo TAAA II 87 BG KA ORY bn ee kee ee hehe haw eee een 87 3 1 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 4 10 4 11 4 12 A l A 2 B 1 B 2 B 3 Se OPO We be bes ob Oe wt es ee ed ee eee ae eS 31 37 By HGR en so oie ewe A RR eae eA REDE aa 44 60
134. ed multi channel readout X ray CCD camera with analog ASIC Nucl Instr amp Meth A 2010 submitted 30 X 2005 31 T Kishishita G Sato H Ikeda M Kokubun T Takahashi T Idehara H Tsunemi Y Arai Development of an SOI Analog Front end ASIC for X ray Charge Coupled Devices Proc Seventh International Hiroshima Symposium on the Development and Application of Semiconductor Tracking Detectors 32 T Kishishita T Idehara H Ikeda H Tsunemi Y Arai G Sato T Takahashi Readout ASIC with SOI technology for X ray CCDs IEEE Trans Nucl Sci 2010 submitted 33 K Koyama et al X ray Imaging Spectrometer XIS on Board Suzaku Publ Astron Soc Japan 59 2007 23 34 JAXA Astro E2 2 2005 35 E USOT Pixel Pixel 2009 92 36 Allan J et al CREAM96 A Revision of the Cosmic Ray Effects on Micro Erectronics Code IEEE Trans Nucl Sci 44 1997 93 Readout ASIC with SOI technology for X ray CCDs Tetsuichi Kis
135. ed the signal timing with SPICE The result is shown in Fig 10 b As shown in the figure the timing of the signals Filtered Signal DAC DAC Fig 5 Configuration of the ADC stage Fig 8 X ray image of a heart shaped mask placed between the CCD and the 5Fe source Each white dot represents an X ray interaction point 1000 500 100 Counts 0 2 4 6 8 10 Energy keV Fig 9 X ray spectrum of Fe obtained with the CCD and readout ASIC The CCD was operated at 56 C The readout speed of the CCD was 97 kHz is not overlapped By using the non overlapping logic gates we can reduce the interference between EVEN ODD chains and expect further low noise performances TABLE II SPECIFICATIONS OF THE X RAY CCD P4 6 5B1P 2 HPK N channel CCD Full frame transfer Model number Device type Transfer method Readout nodes 1 Pixel size 24 um x 24 um Number of pixels 512 x 512 Conversion gain 2 33 uVle VI SUMMARY We developed a readout ASIC for X ray CCDs by utilizing a recent technology of FD SOI The ASIC includes a pream plifier correlated double sampling circuit ramp circuit and comparators We evaluated the performance of the ASIC by combining with an X ray CCD and irradiating a radioisotope 55Fe When the X ray CCD is operated at 56 C the energy resolution of the X ray spectrum achieved 305 eV FWHM for the 5 9 keV line In the performance measurements we
136. ergy resolution of the spectrum V DISCUSSION As is described above the spectral performances are slightly different between EVEN ODD chains This is due to the small difference of time jitters exists in width outputs of two signal chains Since the noise level inside the ASIC is common between the two chains we speculate that the origin of the additional jitter difference comes from the interference between the EVEN ODD chains and is specifically located at the digital circuits for switching EVEN ODD chains In the current design we employed two CMOS switches which consist of pairs of NMOS and PMOS transistors to move from EVEN to ODD and vice versa The switching signal for the EVEN and ODD switches are provided in opposite phase each other e g ON signal for the EVEN switch and OFF for the ODD switch by a simple circuit structure using only inverters However this simple logic gates generate a timing overlap in output switching signals As a result the small difference is generated in time jitters between EVEN ODD chains In order to remove possible overlaps between EVEN ODD timings we are now designing a modified version of the ASIC in which non overlapping logic gates are employed for the switching circuits Figure 10 a shows a schematic of the non overlapping logic gates The signals HOLDA and HOLDB are supplied to a CMOS switch for the EVEN chain and HOLDC and HOLDD is for that of the ODD one We simulat
137. frst in first out memory FIFO 1 FIFO 2 ASIC National Instrumemts NT6703 NI6534 NI6703 NI6534 PCI CCD NI6703 CCD FIFO 1 NI6534 ASIC ASIC 1 5625 MHz 100 MHz ASIO FIFO 2 ASIO CCD He 819 1 18 mV 16 mV 2 mV 18
138. hishita Toshihiro Idehara Hirokazu Ikeda Hiroshi Tsunemi Yasuo Arai Goro Sato and Tadayuki Takahashi Abstract We developed an analog front end application spe cific integrated circuit ASIC with a fully depleted FD silicon on insulator SOI technology for readout of X ray CCDs The ASIC contains seven readout channels each of which is equipped with the correlated double sampling circuit followed by an amplitude to pulse width conversion circuit We combined the ASIC with an X ray CCD for performance evaluation tests We succeeded in processing analog signals from the CCD and confirmed an X ray imaging and photon counting capabilities by irradiating a radioisotope Fe The energy resolution was 305 eV at 5 9 keV full width at half maximum and the readout noise was 48 2 uV for power consumption of 33 mW per chip The ASIC proves that the FD SOI process can be a practically usable option for front end applications Index Terms SOI silicon on insulator ASIC VLSI analog front end low noise CCD X ray I INTRODUCTION E experimentally designed a new analog readout ASIC for X ray CCDs utilizing a recent SOI CMOS technol ogy X ray CCDs have been successfully employed as focal plane detectors of X ray astronomical satellites 1 2 3 The X ray CCD in combination with an X ray mirror enables to simultaneously acquire an object image as well as an energy spectrum in the soft X ray band below 10 keV A disadvantage
139. km 30 ASIC 200 10 C 0 C 40 C ASIC X CCD ASIC
140. nerator OD 22 V LVDS armadillo 9 width test pulse signal 2SC3735 DownloadIPRAM bus X ray CCD clk ena i a 220pF ASIC Sequencer command ASIC Write PRAM L sa control signals iCDS ADC Ethernet T a control signals ee MIKE B 12 83 B 5 ASIC ASIC CCD ASIC CCD ASIO B 7 B 8 COD CDS width signal 0 2 pF ICR ASIC ASIC ADC CCD CCD
141. of the X ray CCD exists in its poor timing resolution e g a few seconds The practical readout speed is about 100 kHz to achieve the low noise level while higher readout speed is required to readout electronics for the next generation CCD systems One solution to improve the time resolution is to increase the number of readout nodes by integrating readout electronics to an LSI which meets with the demands of space and power limitations Actually such readout ASICs have been widely designed with bulk CMOS technologies 4 5 The distinct features of SOI devices i e small parasitic capacitance and low junction leakage current are just suit able for switched capacitor circuits which are often used in CCD readout circuits e g CAMEX 64 6 on account of low power and high speed capabilities These characteristics mitigate substrate coupling noise and reduce the silicon area T Kishishita H Ikeda G Sato and T Takahashi are with the Institute of Space and Astronautical Science Japan Aerospace Exploration Agency Sagamihara Kanagawa 229 8510 e mail kisisita astro isas jaxa jp T Idehara and H Tsunemi are with the Department of Earth and Space Science Graduate School of Science Osaka University Machikaneyama cho Toyonaka shi Osaka 560 0043 Japan Y Arai is with the Institute of Particle and Nuclear Studies National High Energy Accelerator Research Organization 1 1 Oho Tsukuba Japan in comparison with bulk CMOS proces
142. r formances The details of the CMOS based circuit description and ASIC performance of the unit tests are found elsewhere 9 II OVERVIEW OF THE ASIC A Specifications of the ASIC The CCD readout ASIC is designed on the basis of the Open IP LSI project led by JAXA Figure 1 shows a photo graph of the bare chip The circuit design was submitted to OKI Semiconductor Co Ltd via the multi chip project oper ated as a part of the SOI pixel detector R amp D program in KEK 10 The fabrication process was a 0 2 um FD SOI CMOS provided by the Miyagi factory of OKI Semiconductor Co Ltd The ASIC contains seven readout channels Each channel consists of a preamplifier low pass filter correlated double sampling CDS circuit ramp circuit and comparators The total power consumption is 33 mW for power rails of 1 65 V The maximum pixel readout speed is 200 kHz which is limited by the ramp rate for an analog to digital conversion ADC The specifications of the ASIC are summarized in Table I B Detailed description of the signal processing 1 Preamplifier stage As shown in the inset panel of Figure 2 a CCD signal of one pixel consists of a floating and signal levels The voltage difference of the two levels corresponds to charge amounts generated by an incident X ray in the CCD through photoelectric absorption The input CCD signal is fed to the ASIC and then amplified in the preamplifier circuit Fig 2 shows the configuration
143. ray CCD signal of 1 pixel floating level CCD Signal Test Pulse O B 3 PRC TI PRO SE B 3 B 3 1 ASIC CCD B 3 B 3 CCD 20 pF AC PRC B 3 SEF CMOS CC IRKI 12 5 100 8 B 7 CCD Test pulse Preamplifier output B 3 D EG i DI AE E BEM a D N meet CCD 5 5
144. rbed dose krd X 4 23 5 bit DAC 3 gain ch mV equivalent input noise LV y Po099696666996 ET 0 oe 6 eas im potto Ta gauss sigma of scatter plot ch 0 50 100 150 200 0 50 100 150 200 absorbed dose krd absorbed dose krd INL 0 50 100 150 200 0 50 100 150 200 absorbed dose krd absorbed dose krd X 4 24 5 bit DAC 1E 0 0 2 200 krad 20 krad 200 krad lch mV INL 1 20 krad 4 24 4 25 5 bit DAC 0 3 4 24 5 bit DAC 0 ch mV 30 krad
145. s for Astronomy 1981 9 Janesick J R Hyneek J and Blouke M M Solid State Imagers for Astronomy Proc SPIE 290 1981 10 X CCD 1997 11 MAXI CCD 2000 12 13 All X NeXT CCD 2007 14 Behzad Razavi CMOS 2004 15 CMOS CQ 2006 16 X CCD LSI 2005 17 NEC ELECTRONICS http www necel com 91 18 R Rando A Bangert D Bisello A Candelori P Giubilato M Hirayama R Johonson H F W Sadrozinski M Sugizaki J Wyss M Ziegler Radiation Testing of GLAST LAT Tracker ASICs IEEE Trans Nucl Sci 51 2004 842 847 19 HEE John
146. se eV 2 19 FWHMnoise 3 Mint hi 6S UNOK RAS DT 2 7 2 EEN CCD 1 e pixel 1 24 2 Si SiO 3 2 2 1 1 MPP 3
147. ses Moreover SOI devices intrinsically immune to single event latch ups since SOI transistors are free from parasitic PNPN structure SOI technologies are thus more fascinating LSI fabrication pro cesses than bulk CMOS devices for front end applications in radiation harsh environments such as space Over the past few years we have recognized a fully depleted FD SOI process could be a useful technology to be applied for analog front end circuits on board space satellites We also identified possible issues concerning front end circuits in small circuit designs with FD SOI 7 Compared with a partially depleted PD SOI the FD SOI employs a thinner silicon layer and then the silicon layer underneath the gate electrode is completely depleted As a result the kink effect which is revealed in the PD SOI is moderated in the FD SOI In addition an improvement in the threshold slope parameter assists us in employing low threshold voltage transistors when designing circuits Since the FD SOI is still a relatively new technology the FD SOI processes are not yet widely employed in commercial use while several applications to digital circuits have been exploited for space environments In order to demonstrate the attractive features of the FD SOI we have designed an analog front end application specific integrated circuit ASIC for readout of X ray CCDs In this paper we report on the first result of the FD SOI readout ASIC with practical pe
148. uration of the ADC stage The entire circuit consists of two ADCs and a multiplexer Each ADC consists of a hold capacitor operational amplifier current generator and comparator The outputs of the CDS circuit are alternatively steered into the two separate hold capacitors of 1 pF by the CMOS switches the signal channel is separated into two parts 1 e one is named EVEN and the other named ODD By the action of the CMOS switches the hold capacitor moves to a position of a feedback component of the opera tional amplifier see Fig 5 An output voltage level of the op erational amplifier is set from a baseline to the corresponding voltage of charge amounts accumulated in the hold capacitor and then the output voltage level of the operational amplifier is ramped up linearly by feeding charges into the feedback capacitor from a current generator The ramp signal is then fed into the comparator The comparator delivers a width signal when the hold capacitor switches to a feedback capacitor of the operational amplifier and then negates the width signal when the voltage level reaches to a threshold voltage As a result the time width of the width signal corresponds to the pulse height of the CCD signals The slope of the ramp signal and threshold voltages for comparators are adjustable in 16 steps with a binary weighted configuration Fig 3 Right shows the measured waveforms of the ramp and width signals The TABLE I SPECIFICATIONS OF T
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