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XSA Board V1.1, V1.2 User Manual

1. 000 XC9572XL CPLD Spartan II FPGA 8 2 7 3 6 6 7 2 1 8 4 5 4 5 4 4 5 5 4 2 4 5 6 7 8 9 XSA BOARD V1 1 V1 2 USER MANUAL 24 Seven Segment LED The XSA Board has 7 segment LED digit for use by the FPGA or the CPLD segments of this LED are active high meaning that a segment will glow when a logic high is applied to it The LED shares the same pins as the eight bits of the Flash RAM data bus Four Position DIP Switch The XSA Board has a bank of four DIP switches accessible from the CPLD and FPGA When closed or ON each switch pulls the connected pin of the FPGA and CPLD to ground Otherwise the pin is pulled high through a resistor when the switch is open or OFF When not being used the DIP switches should be left in the open or OFF configuration so the pins of the FPGA and CPLD are not tied to ground and can freely move between logic low and high levels The DIP switches also share the same pins as the uppermost four bits of the Flash RAM address bus If the Flash RAM is programmed with several FPGA bitstreams then the DIP switches can be used to select a particular bitstreams which will be loaded into the FPGA by the CPLD on power up However this featu
2. FPGA CPLD RAM Flash EEPROM High Address Low Address Upload Format XSA BOARD V1 1 V1 2 USER MANUAL 13 After setting the board type and parallel port you can download BIT or SVF files to the Spartan Il FPGA XC9572XL CPLD on your XSA Board simply by dragging them to the FPGA CPLD area of the GXSLOAD window as shown below X gxsload Once you release the left mouse button and drop the file the highlighted file name appears the FPGA CPLD area and the Load button in the GXSLOAD window is enabled Clicking on the Load button will begin sending the highlighted file to the XSA Board through the parallel port connection BIT files contain configuration bitstreams that are loaded into the FPGA while SVF files will go to the CPLD GXSLOAD will reject any non downloadable files ones with a suffix other than BIT or SVF During the downloading process GXSLOAD will display the name of the file and the progress of the current download X gxsload XSA BOARD V1 1 V1 2 USER MANUAL 14 You drag amp drop multiple files into the FPGA CPLD area Clicking your mouse filename will highlight the name and select it for downloading Only one file at a time can be selected for downloading X gxsload ram100 bit dwnldpar svf Double clicking the highlighted file will deselect it so no file will be downloaded Doin
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5. 4 0 1 4 A 22 A subset of the 144 pins on the FPGA s TQFP package connects to the prototyping header The number of the FPGA pin connected to a given header pin is printed next to the header pin on the board This makes it easier to find a given FPGA pin when you want to connect it to an external system While most of the FPGA pins are already used to support functions of the XSA Board they can also be used to interface to external systems through the prototyping header The FPGA pins can be grouped into the various categories shown below Pins denoted with are useable as general purpose pins denoted with can be used as general purpose I O only if the CPLD interface is XSA BOARD V1 1 V1 2 USER MANUAL 29 reprogrammed with the alternate parallel port interface stored in the dwnldpa2 svf file pins with no marking cannot be used as general purpose 1 at all Configuration Pins 30 31 37 38 39 44 46 49 57 60 62 67 68 69 72 106 109 111 These pins are used to load the Spartanll FPGA with a configuration bitstream Some of these pins are dedicated to the configuration process and cannot be used as general purpose 37 69 72 106 109 111 The rest can be used as general purpose after the FPGA is configured If external logic is connected to these pins you may hav
6. You can use your XSA Board in three ways distinguished by the method you use to apply power to the board Using a 9VDC wall mount power supply You can use your XSA Board all by itself to experiment with logic designs Just place the XSA Board on a non conducting surface as shown in Figure 1 Then apply power to jack J5 of the XSA Board from a 9V DC wall mount power supply with a 2 1 mm female center positive plug See Figure 2 the location of jack J5 on your XSA Board The on board voltage regulation circuitry will create the voltages required by the rest of the XSA Board circuitry Be careful The voltage regulators the XSA Board will become hot Attach a heat sink to them if necessary Powering Through the PS 2 Connector You can use your XSA Board with a laptop PC by connecting a PS 2 male to male cable from the PS 2 port of the laptop to the J4 connector You must also have a shunt across pins 1 and 2 of jumper J7 The on board voltage regulation circuitry will create the voltages required by the rest of the XSA Board circuitry Many PS 2 ports cannot supply more than 0 5A so large fast FPGA designs may not work when using this power source Solderless Protoboard Installation The two rows of pins from your XSA Board can be plugged into a solderless protoboard with holes spaced at 0 1 intervals One of the A C E protoboards from 3M is a good choice Once plugged in many of the pins of the FPGA are accessible to other c
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8. 9 ESS Corporation XSA Board V1 1 V1 2 User Manual How to install test and use your new XSA Board RELEASE DATE 12 22 2003 Copyright 2001 2003 by X Engineering Software Systems Corporation All XS prefix product designations are trademarks of XESS Corp All XC prefix product designations are trademarks of Xilinx All rights reserved No part of this publication may be reproduced stored a retrieval system or transmitted in any form or by any means electronic mechanical photocopying recording or otherwise without the prior written permission of the publisher Printed in the United States of America XSA BOARD V1 1 V1 2 USER MANUAL 1 Table of Contents XSA BOARD V1 1 V1 2 USER MANUAL 2 XSA BOARD V1 1 1 2 USER MANUAL Preliminaries Here are some places to get help if you encounter problems If you can t get the XSA Board hardware to work send an e mail message describing our problem to help xess com or submit a problem report at http www xess com help html Our web site also has m answers to frequently asked questions m example designs application notes and tutorials for the XS Boards m a place to sign up for our email forum where you can post questions to other XS Board users If you can t get your Xilinx WebPACK software tools installed properly send an e mail message describing your problem to hotline xilinx com or check their web site at http www xilinx com suppor
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10. Board Control line goes directly to the 051075 oscillator and is used for setting the divisor as described previously and status line S6 connects directly to the FPGA for use as a communication line from the FPGA back to the PC The CPLD handles the fifteen remaining active lines of the parallel port as follows Three of the parallel port control lines 1 connect to the JTAG pins through which the CPLD is programmed The C1 control line clocks configuration data presented on the C3 line into the CPLD while the C2 signal steers the actions of the CPLD programming state machine Meanwhile information from the CPLD returns to the PC through status line S7 The eight data lines 00 07 and the remaining three status lines 53 55 connect to general purpose pins of the CPLD The CPLD can be programmed to act as an interface between the FPGA and the parallel port the dwnldpar svf file is an example of such an interface Schmitt trigger inverters are inserted into the D1 line so it can carry a clean clock edge for use by any state machine programmed into the CPLD The CPLD connects to the configuration pins of the Spartan Il FPGA so it can pass bitstreams from the parallel port to the FPGA The actual configuration data is presented to the FPGA on the same 8 bit bus that also connects to the Flash RAM and seven segment LED The CPLD also drives the configuration pins CCLK PROGRAM CS and WR of the FPGA XSA BOARD V1 1 V1 2 USER MAN
11. Setting Purpose On A shunt should be installed if the 2 5V supply voltage is derived from the 3 3V supply default Off The shunt should be removed if the 2 5V supply voltage is applied from an external source through pin 22 of the XSA Board labeled 2 5V at the lower right hand corner of the board 1 2 shunt should be installed on pins 1 and 2 set when setting the frequency of the programmable oscillator 2 3 osc shunt should be installed on pins 2 and 3 osc during normal operations when the programmable default oscillator is generating a clock signal 1 2 The shunt should be installed on pins 1 and 2 if the 3 3V supply voltage is derived from the 5V default supply 2 3 The shunt should be installed on pins 2 and if the 3 3V supply voltage is derived from the 9VDC supply applied through jack J5 1 2 xi The shunt should be installed on pins 1 and 2 xi if the XSA Board is to be downloaded using the Xilinx IMPACT software 2 3 xs The shunt should be installed on pins 2 and 3 xs if the XSA Board is to be downloaded using the default XESS GXSLOAD software N A This is a header that provides access to the 5V GND references on the board No shunt should be placed on this header Testing Your XSA Board Once your XSA Board is installed and the jumpers are in their default configuration you can test the board using the GUI based GXSTEST utility as follows You start GXSTEST
12. by clicking on the icon placed on the desktop during the XSTOOLS installation This brings up the window shown below X gxstest Biel x Board Type 54 100 Port Next you select the parallel port that your XSA Board is connected to from the Port pulldown list GXSTEST starts with parallel port LPT1 as the default but you can also select LPT2 or LPT3 depending upon the configuration of your PC After selecting the parallel port you select either the XSA 50 or XSA 100 item in the Board Type pulldown list Then click on the TEST button to start the testing procedure GXSTEST will configure the FPGA to perform a test procedure on your XSA Board XSA BOARD V1 1 V1 2 USER MANUAL 10 Within thirty seconds you will see displayed on the LED digit if the test completes successfully Otherwise an E will be displayed if the test fails A status window will also appear on your PC screen informing you of the success or failure of the test If your XSA Board fails the test you will be shown a checklist of common causes for failure If none of these causes applies to your situation then test the XSA Board using another PC In our experience 99 996 of all problems are due to the parallel port If you cannot get your board to pass the test even after taking these steps then contact XESS Corp for further assistance As a result of testing the XSA Board the CPLD is programmed with the standard parallel port interface fo
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14. 78 59 3 E87 BUS040 40 3 xcausnai 7 RUSD4 42 VREF2_1 VREF5_1 5 5 BuSn4 45 96 yeausnan 4 BuS04 47 VREF2_2 59 BUS050 50 VREFS_2 391 enus n 4 RUSO 51 102 xcBus102 4 Ellen 54 XC2S TQFP144 VREF5_3 103 03 4 815056 56 12 xcBusu2 4 R7 5 1 113 xcBusns 4 CBUS088 88 CCLKO L4 2 BUSOG 18 166182 VREF6_I Taig XCBUSH6 4 Lion BLSA 18 180152 vrere_2 Ply xcausiiz Z XCR 39 120 xCBUS120 4 BUS044 44 DN 00 121 xcBust21 A XCRUSD4 46 0 122 XCRUSI22 4 XCBUS Dd 49 02 VREF63 1253 XCBUISI23 4 3 3V XCR 57 05 124 12472 XC 50 08 126 26 4 RBF 4 XC 82 129 xcBusi28 4 BAA 67 06 130 XCBUS130 4 15038 58 131 4 XCR 0001 132 2 4 gRBH 4 7K 30 WRITE VREF7 1 122 132 BUSO68 A 5068 68 134 xcBusi34 R8G 44 XCBUSO 2 DONE 136 XCBUSI38 4 ra 37 PROGRAM VREF7 2 138 1 CCLK vrer7 139 4 7 xcausi09 109 o 3 140 xcausi4n 1 XCRUSIM 141 XCBuS141 4 RSH 4 7 06 06 106 M2 500 2 XCBUS142 142 TMS XCBUSD 92 TDI nco HOS TDO 5822225222292929 WRITE 9 C5 C5 C5 CO C5 CO C5 Co C5 Co C5 Co
15. C5 Co C5 BUSY DOUT 3 3V 2 5V COMPANY XESS Corporation TITLE XSA Board Spartan FPGA RELEASED XCBUSL001 144 0 01uF xsal_2 sch 2 Mon Feb 11 08 37 19 2002 N D5 XCBUSO60 8 5 OE K xcRus043 12 o TCK Kk xcRuson2 06 XCB 06 D7 XCBUSO6 CE XCBUSO4 CS TDI BUSO BSY BUSO CCL BUSO WRITE TDO XCB 19 U2 As es PS s XC9572XL vQ64 M A7 XCBUSO66 Kk xcRus076 A4 Kk xcRus074 A3 Kk xcRus027 A2 Kk xcRusn2R A1 xcausn20 0 Kk xcRusn4n DO Kk xcRusnig 1 01 Kk xcRus044 D2 03 K xcRusn4o D4 xcRus057 C17 C18 C19 0 01uF 0 01uF 0 01uF COMPANY XESS Corporation XSA Board CPLD Interface RELEASED DATED SHEET OF PROGRAM DONE XCBUS 001 144 C20 0 01uF xsal_2 sch 3 Mon Feb 11 08 37 19 2002 U3 AT49F002 D 4O 01 4 C42 SODTPUMN XCBUS054 XCB 4 5063 Kk O XCBUS056 Kk xcausns amp 6 XCBUS 001 144 XESS Corporation XSA Board Flash RAM RELEASED DATED SHEET xsal_2 sch 4 Mon Feb 11 08 37 19 2002 04 SDRAM 256MB XCBUSL001 144 COMPANY XESS Corporation XSA Board Sync DRAM DRAWN DATED RELEASED DATED SHEET xsal_2 sch 5 Mo
16. O or MCS file are downloaded into the Flash through the parallel port 4 The CPLD is reprogrammed to create a circuit that configures the FPGA with the contents of the Flash when power is applied to the XSA Board This configuration loader is stored in the fcnfg svf bitstream file located within the XSTOOLS XSA folder Multiple files can be stored in the Flash device just by dragging them into the Flash EEPROM area highlighting the files to be downloaded and clicking the Load button Note that anything previously stored in the Flash will be erased by each new download This is useful if you need to store information in the Flash in addition to the FPGA bitstream Files are selected and de selected for downloading just by clicking on their names in the Flash EEPROM area The address ranges of the data in each file should not overlap or this will corrupt the data stored in the Flash device XSA BOARD V1 1 V1 2 USER MANUAL 16 You can also examine the contents of the Flash device by uploading it to the PC upload data from an address range in the Flash type the upper and lower bounds of the range into the High Address and Low Address fields below the Flash EEPROM area and select the format in which you would like to store the data using the Upload Format pulldown list Then click on the file icon and drag amp drop it into any folder This activates the following sequence of steps 1 The CPLD on the XSA Board is reprogrammed to creat
17. UAL 26 that control the loading of a bitstream The CPLD uses the MO input of the FPGA to select either the slave serial or master select configuration mode M1 and M2 are already hard wired to VCC and GND respectively The CPLD can monitor the status of the bitstream download through the INIT DONE and BSY DOUT pins of the FPGA The CPLD also has access to the FPGA s JTAG pins TCK TMS TDI TDO The TMS TDI and TDO pins share the connections with the BSY DOUT CS and WR pins With these connections the CPLD can be programmed with an interface that allows configuration of the Spartan Il FPGA through the Xilinx IMPACT software Jumper J9 allows the connection of status pin S7 to the general purpose CPLD pin that also drives status pin S5 This is required by the iMPACT software so it can check for the presence of the downloading cable FLASH RAM EO XC9572XL Spartan ll FPGA Parallel Port 07 00 2 3 gt o gt 4 PPD2 CCLK 5 PPD3 PROGRAM 6 PPD4 NNIT 7 PPD5 MO 8 PPD6 AN M1 9 PPD7 TDI Ws 16 2 TMS AUR 14 PPC1 gt gt TOK BSY DOUT 11 PPS7 lt TDO DONE 12 PPS5 4 5 13 PPS4 4 TMS 15 PPS3 4 VVV p Osc MN TO m pepe 10 PPS6 4 After the Spartanll FPGA is configured with a bitstream and the DONE pin goes high the CPLD switches into
18. US111 5046 41 40 XCBUS142 1 11 21 XEBUS047 1 91 39 L 91 17 XCBUS048 L J 4599 XCB S039 91 60 I XCBUS050 O 11 38 Ji 42 censor 31 78 4 91 43 XCBUSGER 91 79 i 31 44 NEBUSUSE O 31 82 i 31 46 XCHISUET O 1 83 5 47 XEHUSHER O 31 35 il 31 48 91 62 31 49 XOH SGED 41 66 i 31 63 XCBUSD62 41 80 OO 4 72 Ji 81 i Ji 74 i Ji 75 i Ji 76 XCBUS 001 144 COMPANY XESS Corporation XSA Board Prototyping Header RELEASED
19. a mode that connects the parallel port data and status pins to the FPGA This lets you pass data to the FPGA over the parallel port data lines while XSA BOARD V1 1 V1 2 USER MANUAL 27 receiving data from the FPGA over the status lines The connections between the FPGA and the parallel port are shown below 256 KByte Flash RAM z net CN COSI LO SO P CN CO STELO DE 2S m oe M ES OS OS 11111 11111 1111 a H DO 33 4 ses ULU r 01 32 44 D2 31 x 42 03 27 i E 47 4 25 LO 56 P 65 2 Q x VOONSNOOIPRN The FPGA sends data back to the PC by driving logic levels onto pins 40 29 and 28 which pass through the CPLD and onto the parallel port status lines S3 S4 and S5 respectively Conversely the PC sends data to the FPGA on parallel port data lines DO D7 and the data passes through the CPLD and ends up on FPGA pins 50 48 42 47 65 51 58 and 43 respe
20. al of up to 50 MHz through pin 64 of the prototyping header This external clock takes the place of the internal 100 MHz clock source in the DS1075 oscillator You must use the GXSSETCLK software utility to enable the external clock input of the DS1075 Clock signals can also be directly applied to two of the dedicated clock inputs of the FPGA through the pins of the prototyping header 5V A PP CO 11 96 Pin 64 081075 29 3 17 42 88 18 Pin 1 5 XC9572XL Spartan Il g Osc 3 CPLD FPGA 15 Pin 31 XSA BOARD V1 1 V1 2 USER MANUAL 22 Synchronous DRAM The various SDRAM organizations and manufacturers used on the XSA Boards are given in the following table SDRAM Board Organization Manufacturer amp Part No 4 16 HY57V641620HGT XSA 50 4 x 16 Samsung K4S641632F TC75000 8M x 16 HY57V281620HCT 8M x 16 Samsung K4S281632E TC75000 XSA 100 The SDRAM is connected to the FPGA as shown below Currently FPGA pin 133 drives a no connect pin of the SDRAM but this could be used in the future as the thirteenth row column address bit of a larger SDRAM Also the SDRAM clock signal is re routed back to a dedicated clock input of the FPGA to allow synchronization of the FPGA s internal operations with the SDRAM operations 000 00 S
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22. circuitry PS 2 Pins 93 94 When not used to access the PS 2 keyboard mouse port these pins can be used as general purpose I O through the prototyping header Global Clock Pins 15 18 These pins can be used as global clock inputs or general purpose inputs They cannot be used as outputs Free Pins 77 787 79 80 83 84 85 86 877 These pins are not connected to any other devices on the XSA Board so they can be used without restrictions as general purpose I O through the prototyping header JTAG Pins 2 32 34 142 These pins are used to access the JTAG features of the FPGA They cannot be used as general purpose 1 pins XSA BOARD V1 1 V1 2 USER MANUAL 30 XSA Pin Connections The following tables list the pin numbers the Spartan Il FPGA the XC9572XL CPLD along with the pins of the other chips that they connect to on the XSA Board columns of the table are arranged as follows Column 1 lists the Spartan Il FPGA pin It is left blank if there is no connection to the FPGA for this function Pins marked with are useable as general purpose through the prototyping header pins denoted with can be used as general purpose only if the CPLD interface is reprogrammed with the alternate parallel port interface stored in the dwnldpa2 svf file pins with no marking cannot be used as general purpose at all Column 2 lists the XC9572XL CPLD pin It is left blank if there is no con
23. ctively The FPGA should never drive these pins unless it is accessing the Flash RAM otherwise the CPLD and or the FPGA could be damaged The CPLD can sense when the FPGA lowers the Flash RAM chip enable and it will release the data lines so the FPGA can drive the address output enable and write enable pins of the Flash RAM without contention The CPLD also drives the decimal point of the LED display to indicate when the FPGA is configured with a valid bitstream Unless it is accessing the Flash RAM the FPGA should never drive pin 44 to a low logic level or it may damage itself or the CPLD But when the XSA BOARD V1 1 V1 2 USER MANUAL 28 FPGA lowers the Flash RAM chip enable the CPLD will stop driving the LED decimal point to allow the FPGA access to data pin D1 of the Flash RAM For more details on how the CPLD manages the interface between the parallel port and the Spartanll FPGA both before and after device configuration see the KSA Parallel Port meer terface application note Prototyping Header The pins of the FPGA are accessible through the 84 pin prototyping header on the underside of the XSA Board Pin 1 of the header denoted by a square pad is located in the middle of the left hand edge of the board and the remaining 83 pins are arranged counter clockwise around the periphery The physical dimensions of the prototyping header and the pin arrangement are shown below 1 75 _ o 64
24. e an interface between the Flash device and the PC parallel port 2 The Flash data between the high and low addresses inclusive is uploaded through the parallel port 3 The uploaded data is stored in a file named FLSHUPLD with an extension that reflects the file format X gxsload Board Type ksa 00 Load FPGA CPLD Flash EEPROM u T 00 High Address 0x3FFFF Low Address m Upload Format The uploaded data can be stored in the following formats MCS Intel hexadecimal file format This is the same format generated by the promgen utility with the p mcs option HEX Identical to MCS format EXO 16 Motorola S record format with 16 bit addresses suitable for 64 KByte uploads only EXO 24 Motorola S record format with 24 bit addresses This is the same format generated by the promgen utility with the p exo option EXO 32 Motorola S record format with 32 bit addresses XESS 16 XESS hexadecimal format with 16 bit addresses This is a simplified file format that does not use checksums XESS 24 XESS hexadecimal format with 24 bit addresses XSA BOARD V1 1 V1 2 USER MANUAL 17 XESS 32 XESS hexadecimal format with 32 bit addresses After the data is uploaded from the Flash the CPLD on the XSA Board is left with the Flash interface programmed into it You will need to reprogram the CPLD with either the parallel port or Flash configuration circ
25. e mapped into the eight bit data format of the HEX MCS EXO and XES files using a Big Endian style That is the 16 bit word at address N in the SDRAM is stored in the eight bit file with the upper eight bits at location 2N and the lower eight bits at location 2N 1 This byte ordering applies for both RAM uploads and downloads XSA BOARD V1 1 V1 2 USER MANUAL 19 Programmer s Models This section describes the various sections of the XSA Board and shows how the 1 of the FPGA and CPLD are connected to the rest of the circuitry The schematics which follow are less detailed so as to simplify the descriptions Please refer to the complete schematics at the end of this document if you need more details The XSA Board contains the following components XSA Board Organization 2550 or XC28100 Spartan Ill FPGA This is the main repository of programmable logic on the XSA Board XC9572XL CPLD This CPLD manages the interface between the PC parallel port and the rest of the XSA Board Osc A programmable oscillator generates the master clock for the XSA Board Flash A 128 or 256 KByte Flash device provides non volatile storage for data and configuration bitstreams SDRAM An 8 or 16 MByte SDRAM provides volatile data storage accessible by the FPGA LED A seven segment LED allows visible feedback as the XSA Board operates DIP switch A four position DIP switch passes settings to the XSA Board or controls the upper add
26. e to disable it during the configuration process The DONE pin 72 can be used for this purpose since it goes to a logic high only after the configuration process is completed Flash RAM Pins 27 28 29 39 40 41 4277 43 44 46 47 4877 49 50 5177 54 56 57 58 59 60 62 63 64 65 66 67 74 75 76 These pins are used by the FPGA to access the Flash RAM They can be used for general purpose under the following conditions When the FPGA is configured from the Flash the CPLD drives all these pins so any external logic should be disabled using the DONE pin Also after the configuration the Flash chip enable 41 should be driven high to disable the Flash RAM so it doesn t drive the data bus pins In addition the standard parallel port interface loaded into the CPLD dwnldpar svf will drive eight of the Flash RAM pins 42 43 47 48 50 51 58 65 with the logic values found on the eight data lines of the parallel port If this is not desired then use the alternate parallel port interface dwnldpa2 svf which does not drive these pins VGA Pins 127 13 19 20 21 22 23 26 When not used to drive a VGA monitor these pins can be used for general purpose I O through the prototyping header When used as I O the REDO RED1 12 13 GREENO GREEN 1 19 20 and BLUEO BLUE1 21 22 pairs have an impedance of approximately 1 KO between them due to the presence of the resistor ladder DAC
27. g this disables the Load button X gxsload XSA BOARD V1 1 V1 2 USER MANUAL 15 Storing Non Volatile Designs in Your XSA Board The Spartan ll FPGA on the XSA Board stores its configuration in an on chip SRAM which is erased whenever power is removed Once your design is finished you may want to store the bitstream in the 256 KByte Flash device on the XSA Board which configures the FPGA for operation as soon as power is applied Before downloading to the Flash the FPGA file must be converted into MCS format using one of the following commands promgen u 0 file bit p exo 5 256 promgen u 0 file bit p mcs s 256 In the commands shown above the bitstream in the file bit file is transformed into an EXO or MCS file format starting at address zero and proceeding upward until an upper limit of 256 KBytes is reached Before attempting to program the Flash you must place all four DIP switches into the OFF position After the EXO or MCS file is generated it is loaded into the Flash device by dragging it into the Flash EEPROM area and clicking on the Load button This activates the following sequence of steps 1 The entire Flash device is erased 2 The CPLD on the XSA Board is reprogrammed to create an interface between the Flash device and the PC parallel port This interface is stored in the fintf100 svf bitstream file located within the XSTOOLS XSA folder 3 The contents of the EX
28. gt T p gt BERT J8 16 D 741514 741514 48 4 PP C2 48 17 gt PP D2 J8 5 gt gt PP C3 48 18 gt mi gt PP D3 48 6 gt 04 48 7 gt PP D5 48 8 gt PP D6 pn 48 9 D PP D7 48 10 XCBUS078 48 23 USF NO 12 13 48 11 gt Pt O 57 48 24 9 EN 74LS14 22 SH PP S4 J8 13 gt J8 27 D Er 1 13 2 48 26 gt C30 JE COMPANY XESS Corporation XSA Board Parallel Port Interface RELEASED DATED SHEET xsal_2 sch 9 Mon Feb 11 08 37 20 2002 XCBUS002 05065 XCBUSO12 L J s16 XCBUSO64 21 94 5013 41 27 5065 3 XCBUSO15 41 28 5066 0 4 XCBUSO18 H 1 5 XCBUS067 1 4 5 XCBUSO19 s 5068 21 41 10 5020 H J1 29 XCBUS069 L J XCBUS021 1 41 32 XCBUS072 H 41 55 XCBUS022 ann XCBUSO74 1 41 53 5023 1 41 34 XCBUS075 EJ 4 79 5026 J1 36 XCBUSO76 1 41 77 XCBUS027 L J ee XCBUS077 41 6 XCBUS028 L J 41 50 XCBUS078 O s 9 XCBUS029 1 01 51 XCBUSO79 41 67 XCBUS030 1 41 56 XCBUSO80 4 7 XCBUSO31 21 69 XCBUS083 XCBUS032 L J1 68 XCBUSO84 XCBUSO34 XCBUS085 01 19 XCBUS037 L J i739 5086 5038 H eds XCBUS087 1 41 25 XCBUS039 E ass XCBUSO88 41 24 XCBUSO40 en XCBUS093 E 1 5 XCBUSO41 41 57 5094 41 25 XCBUS042 1 41 65 XCBUS106 41 26 XCBUS043 ES 41 58 XCBUS109 J 7 XCBUSO44 1 61 XCB
29. ilinx XC9572XL CPLD is used to manage the configuration of the FPGA via the parallel port The CPLD also controls the programming of the Flash RAM on the XSA Board 100 MHz Programmable Oscillator A Dallas 051075 programmable oscillator provides a clock signal to both the FPGA and the CPLD The DS1075 has a maximum frequency of 100 MHz that is divided to provide frequencies of 100 MHz 50 MHz 33 3 MHz 25 MHz 48 7 KHz The clock signal from the DS1075 is connected to a dedicated clock input of the CPLD The CPLD passes the clock signal on to the FPGA This allows the CPLD to control the clock source for the FPGA XSA BOARD V1 1 V1 2 USER MANUAL 21 set the divisor value the DS1075 must be placed its programming mode This is done by pulling the clock output to 5V on power up with a shunt across pins 1 and 2 of jumper J6 Then programming commands to set the divisor are sent to the 051075 through control pin CO of the parallel port The divisor is stored in EEPROM in the 051075 so it will be retained even when power is removed from the XSA Board The shunt on jumper J6 must be across pins 2 and 3 to make the oscillator output a clock signal upon power up The clock signal enters a dedicated clock input of the CPLD Then the CPLD can output a clock signal to a dedicated clock input of the FPGA To get a precise frequency value or to sync the 5 circuitry with an external system you can insert an external clock sign
30. ircuits on the protoboard The numbers printed next to the rows of pins on your XSA Board XSA BOARD V1 1 V1 2 USER MANUAL 6 correspond to the pin numbers of the FPGA Power can still be supplied to your XSA Board though jack J5 or power can be applied directly through several pins on the underside of the board Just connect 5V 3 3V 2 5V and ground to the pins of your XSA Board listed in Table 1 Power supply pins for the XSA Board Voltage Pin Note 5V 2 3 3V 22 Remove the shunt from jumper J7 if you wish to use your own 3 3V supply Leave the shunt on jumper J7 to generate the 3 3V supply from the 5V supply 2 5V 54 Remove the shunt from jumper J2 if you wish to use your own 2 5V supply Leave the shunt on jumper J2 to generate the 2 5V supply from the 3 3V supply GND 52 Parallel Port e Figure 1 External connections to the XSA Board XSA BOARD V1 1 V1 2 USER MANUAL PC Parallel Port Clock Input 100 MHz Osc Pushbutton Flash RAM 5V Spartan II FPGA SDRAM Pushbutton 2 5V PS 2 Mouse Monitor or Keyboard Figure 2 Arrangement of components on the XSA Board Connecting a PC to Your XSA Board The 6 DB25 male to male cable included with your XSA Board connects it to a PC One end of the cable attaches to the parallel port on the PC and the other co
31. n Feb 11 08 37 19 2002 R2C RED1 XCBUS013 3 AAN 6 550 REDO 05012 6 NU 3 680 R2B GREEN 5020 2 AAN 7 330 R1B GREENO 05019 7 A AP 680 R2A BLUE1 05022 1 2 8 530 RIA BLUEO 05021 8 AAA 680 HSYNC XCBUS023 VSYNC XCBUSO26 R3E 4 7K R3D NG 4 7K 12 R2D 330 XCBUS094 4 PS2 CLK RID Ann 4 XCBUS093 PS2 DATA 680 02 54 XCBUSO46 6 SW PUSH NO 542 43 13 03 56 XCBUS049 5 D4 S5 XCBUS057 4 ANNE EPA 05 53 XCBUSO60 3 14 06 52 XCBUS062 2 ANNE 07 50 XCBUS067 1 ANNE 10 00 51 XCBUS039 8 AAN 9 D1 DP XCBUSO44 7 10 XCBUSL001 144 COMPANY XESS Corporation mE Board PS 2 Port VGA Port LED DRAWN DATED REV V1 2 RELEASED DATED SHEET OF xsal_2 sch 6 Mon Feb 11 08 37 19 2002 0 41 64 PROG OSC 0 01uF 0 01uF Ll XSA Board Programmable Oscillator xsal_2 sch 7 Mon Feb 11 08 37 20 2002 PWRPLUG 45 3 SWITCH 1 4148 1 4148 XESS Corporation XSA Board Regulated Power Supplies xsal_2 sch 8 Mon Feb 11 08 37 20 2002 U9C U9D 3 89 o8 PP CO 741514 741514 U9B HEINE 3 gt pp ct J8 14 gt 74LS14 48 2 gt PP DO J8 15 5 PP S3 U9A U9E J8 3 D 1
32. nection to the CPLD for this function Column 3 lists the pins of other devices on the XSA Board that are connected to the associated FPGA and or CPLD pin Column 4 lists the pin of the XSA prototyping header that is connected to the associated FPGA and or CPLD pin Columns 5 7 list the pins of devices on the Xstend Board that will connect to the FPGA and or CPLD when the XSA Board is inserted into an Xstend Board The first table lists the connections for the XST 2 Board while the second table lists the connections for the older XST 1 3 Board XSA BOARD V1 1 V1 2 USER MANUAL 31 1 850 080 79 9309084 0401 0149 6 14 4 68 SS LUOdUVd SE vS lHOdHVd 02 S 1HOdHVd 2 1 22 9 Z r0 LUOdUVd 82 q IHOduvd 2 16 1Q LYOdUVd 26 0 1 IGL d1d9 O LYOduVd 82 SWL AIIIZI LUOIUUVd 62 0 0 1 06 m SALNVLINHVdS _ 8 Zul 0 05 Wi 8v INvS
33. ng and restoring power during the oscillator programming process At the completion of the process the new frequency will be programmed into the DS1075 An external clock signal can be substituted for the internal 100 MHz oscillator of the DS1075 Checking the External Clock checkbox will enable this feature in the XSA BOARD V1 1 V1 2 USER MANUAL 11 programmable oscillator chip If this option is selected you are then responsible for providing the external clock to the XSA Board through pin 64 labeled CLK at the upper left hand corner of the board XSA BOARD V1 1 V1 2 USER MANUAL 12 Programming This section will show you how to download a logic designs into the FPGA and CPLD of your XSA Board and how to download and upload data to and from the SDRAM and Flash devices on the board Downloading Designs into the FPGA and CPLD of Your XSA Board During the development and testing phases you will usually connect the XSA Board to the parallel port of a and download your circuit each time you make changes to it You can download a FPGA design into your XSA Board using the GXSLOAD utility as follows You start GXSLOAD by clicking on the icon placed on the desktop during the XSTOOLS installation This brings up the window shown below Then select the type of XS Board you are using and the parallel port to which it is connected as follows X gxsload 54 100 Load Port
34. nnects to the female DB 25 connector J8 at the top of the XSA Board as shown in Connecting a VGA Monitor to Your XSA Board You can display images on a VGA monitor by connecting it to the 15 pin J3 connector at the bottom of your XSA Board see Figure 1 You will have to create a VGA driver circuit for your XSA Board to actually display an image You can find an example VGA driver at http www xess com ho03000 html XSA BOARD V1 1 V1 2 USER MANUAL 8 Connecting Mouse or Keyboard to Your XSA Board You can accept inputs from a keyboard or mouse by connecting it to the J4 PS 2 connector at the bottom of your XSA Board see Figure 1 You can find an example keyboard driver at nttp www xess com ho03000 html Inserting the XSA Board into an XStend Board If you purchased the optional XST 2 x Board then the XSA Board is inserted as shown below Refer to the XST 2 x Board Manual for more details Setting the Jumpers on Your XSA Board The default jumper settings shown in Table 2 your XSA Board for use a logic design environment You will need to change the jumper settings only if you are m downloading FPGA bitstreams to your XSA Board using the Xilinx IMPACT software XSA BOARD V1 1 V1 2 USER MANUAL 9 Jumper J10 m reprogramming the clock frequency on your XSA Board see page 11 m changing the power sources for the XSA supply voltages Table 2 Jumper settings for XSA Boards
35. older 2 The contents of the EXO MCS HEX or XES files are downloaded into the SDRAM through the parallel port The data in the files will overwrite each other if their address ranges overlap 3 If any file is highlighted in the FPGA CPLD area then this bitstream is loaded into the FPGA or CPLD on the XSA Board Otherwise the FPGA remains configured as an interface between the PC and the SDRAM You can also examine the contents of the SDRAM device by uploading it to the PC To upload data from an address range in the SDRAM type the upper and lower bounds of the range into the High Address and Low Address fields below the RAM area and select the format in which you would like to store the data using the Upload Format pulldown list Then click on the file icon and drag amp drop it into any folder This activates the following sequence of steps 1 The FPGA on the XSA Board is reprogrammed to create an interface between the RAM device and the PC parallel port This interface is stored in the ram100 bit or ram50 bit bitstream file located within the XSTOOLS XSA folder 2 The SDRAM data between the high and low addresses inclusive is uploaded through the parallel port XSA BOARD V1 1 V1 2 USER MANUAL 18 3 The uploaded data is stored in a file named RAMUPLD with extension that reflects the file format X gxsload 5 100 LPT1 gt 16 bit data words the SDRAM ar
36. partan ll FPGA 8M X 16 SDRAM XSA 100 4 X 16 SDRAM XSA 50 sON gt CO CO C2 Co A 3 3 5 7 0 1 8 6 4 2 2 0 6 1 4 6 0 1 7 5 3 0 8 9 6 3 4 7 3 2 0 6 4 2 1 9 1 XSA BOARD 1 1 1 2 USER MANUAL 23 The Flash RAM organizations and manufacturer used on the XSA Boards are given the following table Flash RAM Board Organization Manufacturer amp Part No XSA 50 128K x 8 Atmel AT49F001 Flash RA XSA 100 256K x8 Atmel AT49F002 Flash The Flash RAM is connected so both the FPGA and CPLD have access Typically the CPLD will program the Flash with data passed through the parallel port If the data is an FPGA configuration bitstream then the CPLD can be configured to program the FPGA with the bitstream from Flash whenever the XSA Board is powered up See the application note Flash Proqratrining ead Canfigaralitl or more retis n this After power up the FPGA can read and or write the Flash Of course the CPLD and FPGA have to be programmed such that they do not conflict if both are trying to access the Flash The Flash is disabled by raising the CE pin to a logic 1 thus making the I O lines connected to the Flash available for general purpose communication between the FPGA and the CPLD 128K x 8 Flash RAM XSA 50 256K x 8 Flash RAM XSA 100 IL OC ams T eL e tC
37. re is not currently supported by the CPLD configuration that loads the FPGA from the Flash RAM XSTOOLS XSA fcnfg svf PS 2 Port The XSA Board provides a PS 2 style interface mini DIN connector J4 to either a keyboard or a mouse The FPGA receives two signals from the PS 2 interface a clock signal and a serial data stream that is synchronized with the falling edge of the clock 5V A ck PS 2 data Connector FPGA 44 Spartan ll o Pushbutton o SW2 XSA BOARD V1 1 V1 2 USER MANUAL 25 The XSA Board has a single pushbutton that shares the FPGA pin connected to the data line ofthe PS 2 port The pushbutton applies a low level to the FPGA pin when pressed and a resistor pulls the pin to a high level when the pushbutton is not pressed VGA Monitor Interface The FPGA can generate a video signal for display VGA monitor When the FPGA is generating VGA signals the FPGA outputs two bits each of red green and blue color information to a simple resistor ladder DAC The outputs of the DAC are sent to the RGB inputs of a VGA monitor along with the horizontal and vertical sync pulses HSYNC from the FPGA vsync gt hsync REDO AAA Sr AAA gt red i FPGA WW onnector GREEN 4 gt green J3 BLUEO AN BLUE1 ANA Parallel Port Interface The parallel port is the main interface for communicating with the XSA
38. ress bits of the Flash device Pushbutton A single pushbutton sends momentary contact information to the FPGA Parallel Port This is the main interface for passing configuration bitstreams and data to and from the XSA Board PS 2 Port A keyboard or mouse can interface to the XSA Board through this port VGA Port The XSA Board can send signals to display graphics on a VGA monitor through this port XSA BOARD V1 1 V1 2 USER MANUAL 20 Prototyping Header ofthe FPGA pins connected to the 84 pins on the bottom of the XSA Board that are meant to mate with solderless breadboards Parallel Port 2 PPDO XC9572XL 25100 015 00 07 00 1 0 12 0 RAS CAS CS WE DQML CKE 5 2 Port 3 PPD1 4 PPD2 5 PPD3 6 PPD4 7 5 8 PPD6 9 PPD7 17 PPC3 14 PPCT PPS7 12 PPS5 13 PPS4 15 PPS3 our 1 10 PPS6 4 Figure 3 XSA Board programmer s model VGA Connector Programmable logic FPGA and XC9572XL CPLD The XSA Board contains two programmable logic chips m A50 Kgate XC2S50 or 100 Kgate Xilinx 25100 FPGA in a 144 pin PQFP package The FPGA is the main repository of programmable logic on the XSA Board m A X
39. t support htm If you need help using the WebPACK software to create designs for your XSA Board then check out this futorial Take notice The XSA Board requires an external power supply to operate It does not draw power through the downloading cable from the PC parallel port If you are connecting a 9VDC power supply to your XSA Board please make sure the center terminal of the plug is positive and the outer sleeve is negative Do not power your XSA Board with a battery This will not provide enough current to insure reliable operation of the XSA Board XSA BOARD V1 1 V1 2 USER MANUAL 4 Packing List Here is what you should have received in your package m XSA Board m cable with a 25 pin male connector on each end m anXSTOOLS CDROM with software utilities and documentation for using the XSA Board XSA BOARD V1 1 V1 2 USER MANUAL 5 Installation Installing the XSTOOLS Utilities and Documentation Xilinx currently provides the WebPACK tools for programming their CPLDs and Spartan ll FPGAs The XESS CDROM contains a version of WebPACK that will generate bitstream configuration files compatible with your XSA Board You can also the most current version of the WebPACK tools from the Xilinx website In addition XESS Corp provides the XSTOOLS utilities for interfacing a PC to your XSA Board Run the SETUP EXE program on the XSTOOLS CDROM to install these utilities Applying Power to Your XSA Board
40. uit before the board will function again The CPLD configuration bitstreams are stored in the following files XSTOOLS XSA dwnidpar svf Drag amp drop this file into the FPGA CPLD area and click on the Load button to put the XSA in a mode where it will configure the FPGA through the parallel port XSTOOLS XSA fenfg svf Drag amp drop this file into the FPGA CPLD area and click on the Load button to put the XSA in a mode where it will configure the FPGA with the contents of the Flash device upon power up Downloading and Uploading Data to the SDRAM in Your XSA Board The XSA 100 Board contains a 16 MByte synchronous DRAM 8M x 16 SDRAM whose contents can be downloaded and uploaded by GXSLOAD The 5 50 has an 8 MByte SDRAM organized as 4M x 16 This is useful for initializing the SDRAM with data for use by the FPGA and then reading the SDRAM contents after the FPGA has operated upon it The SDRAM is loaded with data by dragging amp dropping one or more EXO MCS HEX and or XES files into the RAM area of the GXSLOAD window and then clicking on the Load button This activates the following sequence of steps 1 The Spartan II FPGA on the XSA Board is reprogrammed to create an interface between the RAM device and the PC parallel port This interface is stored in the ram100 bit or ram50 bit bitstream file located within the XSTOOLS XSA folder The CPLD must have previously been loaded with the dwnldpar svf file found in the same f
41. und in the dwnldpar svf bitstream file located within the XSTOOLS XSA folder This is the standard interface that should be loaded into the CPLD when you want to use it with the GXSLOAD utility Setting the XSA Board Clock Oscillator Frequency The XSA Board has 100 MHz programmable oscillator a Dallas Semiconductor DS1075Z 100 The 100 MHz master frequency can be divided by factors of 1 2 up to 2052 to get clock frequencies of 100 MHz 50 MHz down to 48 7 KHz respectively The divided frequency is sent to the rest of the XSA Board circuitry as a clock signal The divisor is stored in non volatile memory in the oscillator chip so it will resume operation at its programmed frequency whenever power is applied to the XSA Board You can store a particular divisor into the oscillator chip by using the GUI based GXSSETCLK as follows You start GXSSETCLK by clicking on the icon placed on the desktop during the XSTOOLS installation This brings up the window shown below Board XS4 100 gt SET Port et 21 Exit Divisor External Clock EE Your next step is to select the parallel port that your XSA Board is connected to from the Port pulldown list Then select either XSA 50 or XSA 100 in the Board Type pulldown list Next you enter a divisor between 1 and 2052 into the Divisor text box and then click on the SET button Then follow the sequence of instructions given by XSSETCLK for moving shunts and removi

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