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MCF5307 ColdFire® Integrated Microprocessor User's Manual

1. MBAR Offset 31 24 23 16 15 8 7 0 0x000 Reset status register System protection Software watchdog Software watchdog RSR p 6 5 control register interrupt vector register service register SWSR SYPCR p 6 8 SWIVR p 6 9 p 6 9 0x004 Pin assignment register PAR p 6 10 Interrupt port Reserved assignment register IRQPAR p 9 7 0x008 PLL control PLLCR Reserved p 7 3 0 00 Default bus master park Reserved register MPARK p 6 11 0x010 Reserved 0x03C Table A 2 Interrupt Controller Registers MBAR 1 Offset 31 24 23 16 15 8 7 0 Interrupt Registers p 9 3 0x040 Interrupt pending register IPR p 9 6 0x044 Interrupt mask register IMR p 9 6 0x048 Reserved Autovector register AVR p 9 5 Interrupt Control Registers ICRs p 9 3 0x04C Software watchdog TimerO ICR1 p 9 2 Timer1 ICR2 p 9 3 p 9 3 timer ICRO p 6 6 0x050 UARTO ICR4 p 9 3 UART1 ICR5 9 3 DMAO ICR6 p 9 3 ICR7 p 9 3 0x054 DMA2 ICR8 p 9 3 ICR9 p 9 3 Reserved M MOTOROLA Appendix A List of Memory Maps A 1 Table A 3 Chip Select Registers MBAR Offset 31 24 23 16 15 8 7 0 0x080 Chip select address register bank 0 CSARO Reserve
2. iu AY LY AS MEL LL ALL ae 31 0 X X X X X X RAW N SIZ 1 0 X X X X K D 31 0 i PUMA V 018 Precharge SRAS V SCAS U Read Write CPU Figure 12 12 Dual Address Peripheral to SDRAM Lower Priority DMA Transfer Figure 12 13 shows a single address DMA transfer in which the peripheral is reading from memory Note that TM2 is high indicating a single address transfer Note that DREQ is negated in clock 4 before the assertion of TS in clock 6 12 16 MCF5307 User s Manual M woronoLA DMA Controller Module Functional Description CLKIN DREQO TMO yoy NX LL O O TS A 81 0 SIZ 1 0 X TIP Kt FY PF RW TM2 TTO Figure 12 13 Single Address Transfer 12 5 4 2 Auto Alignment Auto alignment allows block transfers to occur at the optimal size based on the address byte count and programmed size To use this feature DCR AA must be set The source is auto aligned if SSIZE indicates a transfer size larger than DSIZE Source alignment takes precedence over the destination when the source and destination sizes are equal Otherwise th
3. Bits Value Command Description 6 4 MISC Field This field selects a single command 000 NO COMMAND 001 RESET MODE Causes the mode register pointer to point to UMR1n REGISTER POINTER 010 RESET RECEIVER Immediately disables the receiver clears USRn FFULL RxRDY and reinitializes the receiver FIFO pointer No other registers are altered Because it places the receiver in a known state use this command instead of RECEIVER DISABLE when reconfiguring the receiver 011 RESET disables the transmitter and clears USRn TxEMP TxRDY No other registers TRANSMITTER are altered Because it places the transmitter in a known state use this command instead of TRANSMITTER DISABLE when reconfiguring the transmitter 100 RESET ERROR lears USRn RB FE PE OE Also used in block mode to clear all error bits after a STATUS data block is received 101 RESET BREAK Clears the delta break bit UISRn DB CHANGE INTERRUPT 110 START BREAK Forces TxD low If the transmitter is empty the break may be delayed up to one bit time If the transmitter is active the break starts when character transmission completes The break is delayed until any character in the transmitter shift register is sent Any character in the transmitter holding register is sent after the break The transmitter must be enabled for the command to be accepted This command ignores the state of CTS 111 STOP BREAK Causes TxD to go hi
4. 15 14 13 12 10 9 8 7 6 5 4 3 2 1 0 Byte Command 0 1 0 0 0 0 0 0 Result X XX X X D 7 0 Word Command 0 1 0 0 0 4 0 0 Result D 15 0 Longword Command 0 1 0 0 0 8 0 0 Result D 31 16 D 15 0 Figure 5 26 DUMP Command Result Formats MOTOROLA Chapter 5 Debug Support 5 29 Background Debug Mode BDM Command Sequence READ DUMP B W gt MEMORY Cus NOT READY NEXT CMD RESULT XXX NEXT CMD XXX NEXT CMD gt J READY BERR gt CNOT READY READ P a MEMOR 25 WOTRERDY LOCATION NEXTCMD Y NEXT CMD MS RESULT LS RESULT NEXT CMD XXX NEXT CMD ILLEGAL J READY BERR gt CNOT READY Figure 5 27 DuMP Command Sequence Operand Data None Result Data Requested data is returned as either a word or longword Byte data is returned in the least significant byte of a word result Word results return 16 bits of significant data longword results return 32 bits A value of 0x0001 with S set is returned if a bus error occurs 5 30 MCF5307 User s Manual M woronoLA Background Debug Mode BDM 5 5 3 3 6 Fill Memory Block FILL A FILL command is used with the WRITE command to access large blocks of memory An initial WRITE is executed to set up the starting address of the block and to supply the first operand The FILL command writes subsequent operands The initial ad
5. 18 28 Three Wire Implicit and Explicit Bus Mastership sese 18 30 Three Wire Bus Arbitration 18 31 Three Wire Bus Arbitration Protocol State Diagram sess 18 32 Master oTi bip 18 34 Software Watchdog Reset 18 36 JTAG Test Logic Block 19 2 JTAG TAP Controller State 1 19 4 Disabling JTAG in seems 19 11 Disabling JTAG in Debug 19 11 je diti M 20 3 PSTCEK ces e eene eer RUNE 20 3 AC Timings Normal Read and Write Bus Cycles sse 20 5 SDRAM Read Cycle with EDGESEL Tied to Buffered BCLKO 20 6 SDRAM Write Cycle with EDGESEL Tied to Buffered BCLKO 20 7 SDRAM Read Cycle with EDGESEL Tied High sse 20 8 SDRAM Write Cycle with EDGESEL Tied High eene 20 9 SDRAM Read Cycle with EDGESEL Tied Low ee 20 10 SDRAM Write Cycle with EDGESEL Tied Low eese 20 11 AC Output Timing High 20 11 Reset TIMIN 20 12 Real Time Trace rennen nenne 20 13 BDM Serial Port AC Timing cossssssssssessssossescosssssonsesdes
6. Abbreviation Signal Name Function VO Page SRAS Synchronous row address strobe DRAM 17 17 Transfer acknowledge Bus VO 17 9 TCK Test clock JTAG 17 23 TDI DSI Test data input Development serial input JTAG 17 22 TDO DSO Test data output Development serial output JTAG 17 22 TIN 1 0 Timer input Timer 17 19 Transfer in progress Bus 17 10 TMS BKPT Test mode select Breakpoint JTAG 17 22 TM 2 0 Transfer modifier Bus 17 10 0 Timer outputs Timer 17 19 TRST DSCLK Test reset Development serial clock JTAG 17 21 TS Transfer start Bus VO 17 9 TT 1 0 Transfer type Bus 17 10 TxD 1 0 Transmit data Serial module 17 18 17 2 MCF5307 Bus Signals The bus signals provide the external bus interface to the MCF5307 17 2 4 Address Bus The address bus provides the address of the byte or most significant byte MSB of the word or longword being transferred The address lines also serve as the DRAM addressing providing multiplexed row and column address signals When an external device has ownership of the MCF5307 bus the device must drive the address bus and assert TS or AS to indicate the start of a bus cycle During an interrupt acknowledge access A 4 2 indicate the interrupt level being acknowledged 17 2 1 1 Address Bus A 23 0 The lower 24 bits of the address bus become valid when TS is asserted A 4 2 indicate the interrupt level durin
7. H 18 1 Bus and Control Signals sse 18 1 Bus CharacteristiCs ceste ote ee ten tee ten teme ee ten tene ee ea ete ea ee ehe 18 2 Data Transfer Operation 1 18 3 Bus Cycle 18 4 Data Transfer Cycle States 18 5 CY Cle e n 18 7 Wile 18 8 Fast Termimation 18 9 Back to Back Bus 18 10 eet 18 11 18 12 Line Read Bus Cycle u eet tenete eret ee ones 18 12 Line Write Bus Cycles sese 18 14 Transfers Using Mixed Port Sizes sss 18 15 Misaligned Operands 18 16 6 crane te te 18 17 Interrupt 5 18 17 Level 7 Interrupts iie e ee etm 18 18 Interrupt Acknowledge Cycle sse 18 19 Bus Arbitration eot eee erret 18 20 Bus Arbitration Signals 18 21 General Operation of External Master Transfers 18 21 Two Device Bus Arbitration Protocol Two Wire Mode 18 25 Multiple External Bus Device Arbitration Protocol Three Wire Mode 18 29 Reset Operation 18 33 Master RRA E AR EARE 18 34 Software Watchdog Reset essent 18 35 C
8. ao Tr Ta Note Input and output AC timing specifications are measured to BCLKO with 50 pF load capacitance not including pin capacitance Figure 20 1 Clock Timing Figure 20 2 shows PSTCLK timings for parameters listed in Table 20 4 gt m A Figure 20 2 PSTCLK Timing 20 3 Input Output AC Timing Specifications Table 20 5 lists specifications for parameters shown in Figure 20 3 and Figure 20 4 Note that inputs IRQ 7 5 3 1 BKPT and AS are synchronized internally that is the logic level is validated if the value does not change for two consecutive rising BCLKO edges Setup and hold times must be met only if recognition on a particular clock edge is required Table 20 5 Input AC Timing Specification 66 MHz 90 MHz Num Characteristic Units Min Max Min Max B1 Valid to BCLKO rising setup 7 5 5 5 ns B2 BCLKO rising to invalid hold 3 2 nS B3 Valid to BCLKO falling setup 7 5 5 5 nS B4 BCLKO falling to invalid hold 3 2 nS M MOTOROLA Chapter 20 Electrical Specifications 20 3 Input Output AC Timing Specifications Table 20 5 Input AC Timing Specification 66 MHz 90 MHz Num Characteristic Units Min Max Min Max B5 BCLKO to input high impedance 2 2 Bus clock B6 BCLKO to EDGESEL delay 0 7
9. Rating Symbol Value Units Supply voltage 0 3 to 44 0 V Maximum operating voltage Voc 3 6 V Minimum operating voltage 3 0 V Input voltage Vin 0 5 to 45 5 V Storage temperature range 55 to 150 C Table 20 2 lists junction and ambient operating temperatures Table 20 2 Operating Temperatures Characteristic Symbol Value Units Maximum operating junction temperature Tj 105 oc Maximum operating ambient temperature TAmax 70 oc Minimum operating ambient temperature TAmin 0 1 This published maximum operating ambient temperature should be used only as a system design guideline All device operating parameters are guaranteed only when the junction temperature lies within the specified range Table 20 3 lists DC electrical operating temperatures This table is based on an operating M Chapter 20 Electrical Specifications 20 1 Clock Timing Specifications voltage of 3 3 Vdc 0 3 Vdc Table 20 3 DC Electrical Specifications Characteristic Symbol Min Max Units Operation voltage range Voc 3 0 3 6 Input high voltage 2 0 3 6 V Input low voltage 0 5 0 8 V Input signal undershoot 0 8 V Input signal overshoot 0 8 V Input leakage current 0 5 2 4 V during normal operation lin 20 High impedance three state leakage current 0 5 2 4 V durin
10. on 31 24 23 16 15 8 7 0 0x080 Chip select address register bank 0 CSARO p 10 6 Reserved 0x084 Chip select mask register bank 0 CSMR0O p 10 6 0x088 Reserved Chip select control register bank 0 CSCRO 10 8 0x08C Chip select address register bank 1 1 p 10 6 Reserved 0x090 Chip select mask register bank 1 CSMR1 p 10 6 0x094 Reserved Chip select control register bank 1 CSCR1 p 10 8 0x098 Chip select address register bank 2 CSAR2 p 10 6 Reserved 0x09C Chip select mask register bank 2 CSMR2 p 10 6 0x0A0 Reserved Chip select control register bank 2 CSCR2 p 10 8 0 0 4 Chip select address register bank 3 CSAR3 10 6 Reserved 0x0A8 Chip select mask register bank 3 CSMR3 p 10 6 Ox0AC Reserved Chip select control register bank 3 CSCR3 p 10 8 0x0BO Chip select address register bank 4 p 10 6 Reserved 0x0B4 Chip select mask register bank 4 CSMR4 p 10 6 0x0B8 Reserved Chip select control register bank 4 CSCRA p 10 8 OxOBC Chip select address register bank 5 CSAR5 p 10 6 Reserved 0x0CO Chip select mask register bank 5 CSMR5 p 10 6 0x0C4 Reserved Chip select control register bank 5 CSCR5 p 10 8 0x0C8 Chip select address register bank 6 CSAR6 10 6 Reserved 0x0CC Chip select mask register bank 6 CSMR6 p 10 6 OxODO Reserved Chip sele
11. 15 3 16 1 Pins 1 52 Left 1 1 16 1 16 2 Pins 53 104 Bottom Left to Right esee 16 3 16 3 Pins 105 156 Right Bottom to Top eene 16 4 16 4 Pins 157 208 Top 16 6 16 5 DIMENSIONS 16 11 17 1 MCE5307 Signal MEERE noe ettet tette ene 17 3 17 2 Data Pin Config ratiOn noter irren 17 6 17 3 Bus Cycle Siz Encoding oerte irte rer tr entire enero Ree eroe entia aida 17 7 17 4 Bus Cycle Transfer Type Encoding 17 9 17 5 TM 2 0 Encodings for TT 00 Normal Access eene 17 9 17 6 Encoding for DMA as Master TT 01 enne 17 9 17 7 TM 2 1 Encoding for DMA as Master 01 seen 17 10 17 8 TM 2 0 Encodings for TT 10 Emulator Access eene 17 10 17 9 TM 2 0 Encodings for TT 11 Interrupt 17 10 xxviii MCF5307 User s Manual M MOTOROLA TABLES Table Number 17 10 Data Pin Configuration wisecssccscciectsecssccsencsscssesesenessccieccdoncsvestecssencsuccsentsendsvecdesesencsees 17 12 17 11 D7 Selection of CSO Automatic Acknowledge sene 17 13 17 12 D6 and D5 Selection of CSO Port 517 17 13 17 13 D4 ADDR_CONFIG
12. 2 z z z z z z GRRORREIORRRISTPTPOPTu8BOBAS OSSRPRSSOOORSBOUSCEOOREOS e N vec 1 N T im GND A0 HZ A1 L1 BKPT GND 1 081 2 5 VCC 5 DSO vce A4 DSCLK A5 9 1 GND GND L 1 DO 9 01 A7 VCC vec 02 A8 9 L 1 03 A9 tL 04 10 9 GND GND 1 105 Ail 06 A12 1 D7 A13 9 31 VCC CTF LL 08 14 L 1 09 A15 010 16 1 GND GND 9 3 DT 17 Lt 012 A18 L 013 19 L 014 20 9 Ly 915 21 L 016 22 1 GND GND DAT 23 1 018 PP8 019 PP9 VCG 1 020 PP10 1 021 PP11 D22 PPSI 57 GND GND 4 1 023 PP13 1 024 PPIE 1 025 PPS VCC vec 026 120 027 5121 9 tL 028 GND 1 1 GND _OE 1 029 cso 3 030 cst 031 vec m 3 G8SERSSEESSs zo a u VAJA 2000 C5 02 CD IF FFZ0Z E uoa 9762882 8882 28206 52008 ien 55 EF Figure 16 1 Mechanical Diagram 16 4 Case Drawing Figure 16 2 and Figure 16 3 show the MCF5307 case drawings M woronoLA Chapter 16 Mechanical Data 16 9 Case Drawing VIEN INDEX 4x 52 TIPS 4x ca 0 2 C 4 B D o 2 H B D Figure 16 2 MCF5307 Case Dra
13. 11 13 Continuous Page Mode Operation essen 11 14 Write Hit in Continuous Page Mode sese 11 15 EDO Read Operation 3 2 2 2 EE E 11 15 DRAM Access Delayed by Refresh essesssreseserecseresereesestseseeseserereesesesesersereseressesese 11 16 MCE5307 SDRAM Interface wicccicisccsccsconsssesseescostsvessecscoscsvesteesconesvecseetsendsvesteussenssees 11 18 Using EDGESEL to Change Signal Timing sss 11 19 M MOTOROLA Illustrations xxi Figure Number 11 15 11 16 11 17 11 18 11 19 11 20 11 21 11 22 11 23 11 24 11 25 11 26 11 27 11 28 11 29 12 1 12 2 12 3 12 4 12 5 12 6 12 7 12 8 12 9 12 10 12 11 12 12 12 13 13 1 13 2 13 3 13 4 13 5 13 6 14 1 14 2 14 3 14 4 14 5 14 6 14 7 14 8 14 9 xxii ILLUSTRATIONS Mus Number DRAM Control Register DCR Synchronous Mode eese 11 19 DACRO and DACRI Registers Synchronous Mode sese 11 20 DRAM Controller Mask Registers DMRO and 11 22 Burst Read SDRAM Access enne nnne nnne enne tenere nennt 11 28 Burst Write SDRAM Access 11 29 Synchronous Continuous Page Mode Access Consecutive Reads 11 30 Synchronous Continuous Page Mode Access Read after 11 31 Auto
14. BCLKO A 31 0 x how Jeter Jaen Gaunt Gom Es gt SCAS vj tip SENE c t TASI3 0 NOP NOP Figure 11 18 Burst Read SDRAM Access PALL Figure 11 19 shows the burst write operation In this example DACR CASL 01 which creates an SRAS to SCAS delay of 2 BCLKO cycles Note that data is available upon SCAS assertion and a burst write cycle completes two cycles sooner than a burst read cycle with the same tpcp The next bus cycle is initiated sooner but cannot begin an SDRAM cycle until the precharge to ACTV delay completes 11 28 MCF5307 User s Manual M woronoLA A 31 0 om Y count Y cour X Cm i X lt NP Er RAS 0 or 1 ns SIS a PE UEM N mul qul 0 del dese d 5 3 0 Synchronous Operation NEN ACTV NOP WRITE NOP PALL Figure 11 19 Burst Write SDRAM Access Accesses in synchronous burst page mode always cause the following sequence l 2 4 5 6 ACTV command NOP commands to assure SRAS to SCAS delay if CAS latency is 1 there are no NO
15. General Operation of External Master Transfers Both normal terminations and terminations due to bus errors generate an end of cycle Bus cycles resulting from a burst inhibited transfer are considered part of that original transfer 2 A means asserted N means negated EM means external master 18 9 2 Multiple External Bus Device Arbitration Protocol Three Wire Mode Three wire mode lets the MCF5307 share the external bus with multiple external devices This mode requires an external arbiter to assign priorities to each potential master and to determine which device accesses the external bus The arbiter uses the MCF5307 bus arbitration signals BR BD and BG to control use of the external bus by the MCF5307 The MCF5307 requests the bus from the external bus arbiter by asserting BR when the core requests an access It continues to assert BR until after the transfer starts It can negate BR at any time regardless of the BG status If the MCF5307 is granted the bus when an internal bus request is generated it asserts BD and the access begins immediately The MCF5307 always drives BR and BD which cannot be directly wire ORed with other devices The external arbiter asserts BG to grant the bus to MCF5307 which can begin a bus cycle after the next rising edge of BCLKO If BG is negated during a bus cycle the MCF5307 releases the bus when the cycle completes To guarantee that the bus is released BG must be negated before
16. 15 2 Code Example eed e m etre dela 15 3 MCF5307 User s Manual M woronoLA CONTENTS Paragraph Title Page Number Number Part IV Hardware Interface Chapter 16 Mechanical Data 16 1 IAM CL M 16 1 16 2 etudes ict deii ER 16 1 16 3 Mechanical 1 16 8 16 4 boum 16 9 Chapter 17 Signal Descriptions 17 1 ud RR CE eren eco 17 1 17 2 MGE5307 Bus Signals e e e ed s 17 7 17 2 1 Address Busses asd hasaeneaeateen et baa hb eee e 17 7 17 2 1 1 Address Bus A 23 0 sese 17 7 17 2 1 2 Address Bus A 31 24 PP 15 8 essere 17 7 17 2 2 Data Bus 4 tette te e ee eee ieds 17 8 17 2 3 Read Write 17 8 17 2 4 ee 17 8 17 2 5 Transfer Start CES ces erede bia A 17 9 17 2 6 Address StFObe CA Si Dites rane aS Ae p ee ege ee viae neci e eu 17 9 17 2 7 Transfer Acknowledge 17 9 17 2 8 Transfer In Progress TIPIPP oenen enen en n Enu EEEE 17 10 17 2 9 Transfer Type TT 1 0 PP 1 0 eren 17 10 17 2 10 Transfer Modifier TM 2 0 PP 4 2 esee 17 10 17 3 Interrupt Control Signals ccccisccsccscesesscssscscoscsscssnescostevesststcesdsscsarsteenddecssesssonsse 17 12 17 3 1 Interrupt Request IRQI IRQ2 IRQ3 IRQ6 IRQS IRQ4 and IRQ 17 12 17 4 Bus Arbitration Sig
17. 4 0 Reserved should be cleared 6 2 4 Software Watchdog Timer The software watchdog timer prevents system lockup should the software become trapped in loops with no controlled exit The software watchdog timer can be enabled or disabled through SYPCR SWE If enabled the watchdog timer requires the periodic execution of a software watchdog servicing sequence If this periodic servicing action does not occur the timer times out resulting in a watchdog timer IRQ or hardware reset with RSTO driven low as programmed by SYPCR SWRI If the timer times out and the software watchdog transfer acknowledge enable bit SYPCR SWTA is set a watchdog timer IRQ is asserted Note that the software watchdog timer IACK cycle cannot be autovectored If a software watchdog timer IACK cycle has not occurred after another timeout SWT TA is asserted in an attempt to terminate the bus cycle and allow the IACK cycle to proceed The setting of SYPCR SWTAVAL indicates that the watchdog timer TA was asserted Figure 6 4 shows termination of a locked bus 6 6 MCF5307 User s Manual M Programming Model Code in the watchdog timer interrupt Cod bl it int tand handler polls SYPCR SWTAVAL to ode enables software watchdog timer interrupt an TA SWTA functionality by writing SYPCR determine if SWETA was needed If s0 ae execute code to identify bad address z Problem 1 Watchdog timer time
18. Encodings not shown are reserved for future use The breakpoint status is also posted in CSR Note that CSR BSTAT is cleared by a CSR read when either a level 2 breakpoint is triggered or a level 1 breakpoint is triggered and a level 2 breakpoint is not enabled Status is also cleared by writing to TDR BDM instructions use the appropriate registers to load and configure breakpoints As the system operates a breakpoint trigger generates the response defined in TDR PC breakpoints are treated in a precise manner exception recognition and processing are initiated before the excepting instruction is executed All other breakpoint events are recognized on the processor s local bus but are made pending to the processor and sampled like other interrupt conditions As a result these interrupts are imprecise In systems that tolerate the processor being halted a BDM entry can be used With TDR TRC 01 a breakpoint trigger causes the core to halt PST OxF If the processor core cannot be halted the debug interrupt can be used With this configuration TDR TRC 10 the breakpoint trigger becomes a debug interrupt to the processor which is treated higher than the nonmaskable level 7 interrupt request As with all interrupts it is made pending until the processor reaches a sample point which occurs once per instruction Again the hardware forces the PC breakpoint to occur before the targeted instruction executes This is poss
19. The DBR supports both aligned and misaligned references Table 5 11 shows relationships between processor address access size and location within the 32 bit data bus Table 5 11 Access Size and Operand Data Location A 1 0 Access Size Operand Location 00 Byte D 31 24 01 Byte D 23 16 10 Byte D 15 8 11 Byte D 7 0 Ox Word D 31 16 1x Word D 15 0 XX Longword D 31 0 5 4 6 Program Counter Breakpoint Mask Registers PBR PBMR The PC breakpoint register PBR defines an instruction address for use as part of the trigger This register s contents are compared with the processor s program counter register when TDR is configured appropriately PBR bits are masked by clearing corresponding PBMR bits Results are compared with the processor s program counter register as defined in TDR Figure 5 10 shows the PC breakpoint register M MOTOROLA Chapter 5 Debug Support 5 13 Programming Model 31 1 0 Field Program Counter Reset R W Write PC breakpoint register is accessible in supervisor mode using the WDEBUG instruction and through the port using the RDMREG and WDMREG commands using values shown in Section 5 5 3 3 Command Set Descriptions DRc 4 0 0x08 Figure 5 10 Program Counter Breakpoint Register PBR Table 5 12 describes PBR fields Table 5 12 PBR Field Descriptions Bits Name Description 31 0 Address PC breakpo
20. esee 2 43 2 7 3 Execution Timings Two Operand Instructions eee 2 43 2 7 4 Miscellaneous Instruction Execution Times eene 2 45 vi MCF5307 User s Manual M woronoLA Paragraph Number 2 1 5 2 8 2 8 1 2 8 2 3 1 3 1 1 3 1 2 3 1 3 3 1 4 3 2 4 1 4 2 4 3 4 4 4 4 1 4 5 4 5 1 4 6 4 7 4 8 4 8 1 4 8 2 4 9 4 9 1 4 9 1 1 4 9 1 2 4 9 1 3 4 9 2 4 9 3 4 9 3 1 4 9 3 2 4 9 3 3 4 9 3 4 4 9 4 CONTENTS Page Hie Number Branch Instruction Execution Times eene 2 46 Exception Processing Overview 2 47 Exception Stack Frame Definition sessssseeeeeeee 2 49 Processor Exceptions esee eee teen heo ae eee Eben tipa o 2 50 Chapter 3 Hardware Multiply Accumulate MAC Unit M 3 1 MAC Programming Model esee 3 2 General Operation snn is nion Seiad nie 3 3 MAC Instruction Set Summary sess 3 4 Data 3 4 MAC Instruction Execution 11155 3 5 Chapter 4 Local Memory Interactions between Local Memory Modules eene 4 1 SRAM O VEO dq C 4 1 SRAM Operation 4 2 SRAM Programming Model seen 4 3 SRAM Base Address Register RAMBAR eene 4 3 SRAM Imntiahization
21. 81 18 17 16 15 14 13 12 11 109 8 7 6 54 3 2 10 Field BA RE CASL CBM PS IP PM Reset Uninitialized 0 Uninitialized 0 Uninitialized R W R W Addr MBAR 0x108 DACRO 0x110 DACR1 Figure 11 16 DACRO and DACR1 Registers Synchronous Mode 11 20 MCF5307 User s Manual M woronoLA Synchronous Operation Table 11 13 describes DACRz fields Table 11 13 DACRO DACR1 Field Descriptions Synchronous Mode Bit Name Description 31 18 BA Base address register With DCMR BAM determines the address range in which the associated DRAM block is located Each BA bit is compared with the corresponding address of the current bus cycle If all unmasked bits match the address hits in the associated DRAM block BA functions the same as in asynchronous operation 17 16 Reserved should be cleared 15 RE Refresh enable Determines when the DRAM controller generates a refresh cycle to the DRAM block 0 Do not refresh associated DRAM block 1 Refresh associated DRAM block 14 Reserved should be cleared 13 12 CASL CAS latency Affects the following SDRAM timing specifications Timing nomenclature varies with manufacturers Refer to the SDRAM specification for the appropriate timing nomenclature Number of Bus Clocks Parameter CASL 00 CASL 01 CASL 10 CASL 11 tacp SRAS assertion to SCAS asser
22. Buffer URBO 4 Registers UART Receive 2 Receiver Holding Register 2 Receiver Holding Register 3 Receiver Shift Register UARTO UART Command Register UCRO Ww UART Mode Register 1 UMR1 R W UART Mode Register 2 UMR2 R W UART Status Register USRO R External UART i Interf Transmitter Buffer Transmitter Holding Register nterface UTBO gt TXD 2 Registers Transmitter Shift Register R FIFO Figure 14 20 Transmitter and Receiver Functional Diagram 14 20 MCF5307 User s Manual M MOTOROLA Operation 14 5 2 1 Transmitting The transmitter is enabled through the UART command register UCRz When it is ready to accept a character the UART sets USRn TxRDY The transmitter converts parallel data from the CPU to a serial bit stream on TxD It automatically sends a start bit followed by the programmed number of data bits an optional parity bit and the programmed number of stop bits The Isb is sent first Data is shifted from the transmitter output on the falling edge of the clock source After the stop bits are sent if no new character is in the transmitter holding register the TxD output remains high mark condition and the transmitter empty bit USRn TxEMP is set Transmission resumes and TxEMP is cleared when the CPU loads a new character into the UART transmitter buffer UTBz If the transmitter receives disable
23. sese 2 27 2 2 1 1 Data Registers DO D7 y erret teeth te eis 2 27 2 2 1 2 Address Registers 2 27 2 2 1 3 StackiPointer A T ettet te etre ette tenet 2 28 2 2 1 4 Program Counter PG 2 28 2 2 1 5 Condition Code Register CCR esee 2 28 222 Supervisor Programming Model sese 2 29 2 2 2 1 Status Register SR oae n Uri i tege etus 2 29 2 2 2 2 Vector Base Register VBR eese 2 30 2 2 2 3 Cache Control Register CACR eene 2 30 2 2 2 4 Access Control Registers ACRO ACRI eere 2 31 2 2 23 5 RAM Base Address Register RAMBAR eene 2 31 2 2 2 6 Module Base Address Register MBAR eene 2 31 2 3 Integer Data Formats eerta rire tte te ben ape eee elena pee terea aped 2 31 24 Organization of Data in Registers 2 31 2 4 1 Organization of Integer Data Formats in Registers sss 2 31 2 4 2 Organization of Integer Data Formats in Memory sees 2 32 2 5 Addressing Mode Summary sse 2 33 2 6 Instruction Set Summary 2 34 2 6 1 Instruction Set Summary 2 37 2 7 Instr ction TMS se ote RR IE eS E A a ossi n id 2 40 2 7 1 MOVE Instruction Execution Times essere 2 41 2 12 Execution Timings One Operand Instructions
24. A 6 5 4 3 2 0 PARK IARBCTRL EARBCTRL SHOWDATA BCR24BIT 0000_0000 R W MBAR 0x0C Figure 6 9 Default Bus Master Register MPARK Table 6 6 describes MPARK bits Table 6 6 MPARK Field Descriptions Bits Name Description 7 6 PARK Park Indicates the arbitration priority of internal transfers among MCF5307 resources 00 Round robin between DMA and ColdFire core 01 Park on master ColdFire core 10 Park on master DMA module 11 Park on current master Use of this field is described in detail in Section 6 2 10 1 1 Arbitration for Internally Generated Transfers MPARK PARK 5 IARBCTRL Internal bus arbitration control Controls external device access to the MCF5307 internal bus 0 Arbitration disabled single master system 1 Arbitration enabled IARBCTRL must be set if external masters are using internal resources like the DRAM controller or chip selects Use of this bit depends on whether the system has single or multiple masters as follows In a single master system IARBCTRL should stay cleared disabling internal arbitration by external masters In this scenario MPARK PARK applies only to priority of internal masters over one another Note that the internal DMA master 3 has priority over the ColdFire core master 2 if internal DMA bandwidth is at its maximum BWC 000 In multiple master systems that expect to use internal resources like the DRAM controller or chip selects internal
25. Figure 11 22 Auto Refresh Operation 11 4 4 6 Self Refresh Operation Self refresh is a method of allowing the SDRAM to enter into a low power state while at the same time to perform an internal refresh operation and to maintain the integrity of the data stored in the SDRAM The DRAM controller supports self refresh with DCR IS When IS is set the SELF command is sent to the SDRAM When IS is cleared the SELFX command is sent to the DRAM controller Figure 11 23 shows the self refresh operation BCLKO Y ME N E git SCKE DCR COC 0 i S i First i 1 SELFX NOP Possible ACTV Self Refresh Active Figure 11 23 Self Refresh Operation PALL NOP SELF 11 32 MCF5307 User s Manual M woronoLA Synchronous Operation 11 4 5 Initialization Sequence Synchronous DRAMs have a prescribed initialization sequence The DRAM controller supports this sequence with the following procedure 1 SDRAM control signals are reset to idle state Wait the prescribed period after reset before any action is taken on the SDRAMs This is normally around 100 us 2 Initialize the DCR DACR and DMR in their operational configuration Do not yet enable PALL or REF commands 3 Issue PALL command to the SDRAMs by setting DCR IP and accessing SDRAM location Wait the time determined by tgp befor
26. 11 5 2 DCR Initialization At power up the DCR has the following configuration if synchronous operation and SDRAM address multiplexing is desired 15 14 13 12 1 10 9 8 0 Field SO res NAM COC IS RTIM RC Setting 1 X 0 0 0 0 0 0 0 0 1 0 0 1 1 0 8 0 2 6 Figure 11 25 Initialization Values for DCR This configuration results in a value of 0x8026 for DCR as shown in Table 11 34 Table 11 34 DCR Initialization Values Bits Name Setting Description 15 SO 1 Indicating synchronous operation 14 X Don t care reserved 13 NAM 0 Indicating SDRAM controller multiplexes address lines internally 12 COC 0 SCKE is used as clock enable instead of command bit because user is not multiplexing address lines externally and requires external command feed 11 IS 0 At power up allowing power self refresh state is not appropriate because registers are being set up 10 9 00 Because tpc value is 70 nS indicating a 3 clock refresh to ACTV timing 8 0 RC 0x26 Specification indicates auto refresh period for 4096 rows to be 64 mS or refresh every 15 625 us for each row or 625 bus clocks at 40 MHz Because DCR RC is incremented by 1 and multiplied by 16 RC 625 bus clocks 16 1 38 06 0x38 11 5 3 DACR Initialization As shown in Figure 11 26 in this example the SDRAM is programmed to access only the second 512
27. A 31 0 Y i X i Column ees oO 3 5 DRAMW teas gt icASL 25 D 31 0 Log ACTV NOP READ NOP READ NOP PALL Figure 11 20 Synchronous Continuous Page Mode Access Consecutive Reads Figure 11 21 shows a write followed by a read in continuous page mode Because the bus cycle is terminated with a WRITE command the second cycle begins sooner after the write than after the read A read requires data to be returned before the bus cycle can terminate Note that in continuous page mode secondary accesses output the column address only 11 30 MCF5307 User s Manual M woronoLA Synchronous Operation BCLKO A 31 0 X Row Y CUBE Tm tgp i f D 31 0 IEEE i 100 DN ACTV i N P WRITE NOP READ NOP NOP NOP PALL Figure 11 21 Synchronous Continuous Page Mode Access Read after Write 11 4 4 5 Auto Refresh Operation The DRAM controller is equipped with a refresh counter and control This logic is responsible for providing timing and control to refresh the SDRAM Once the refresh counter is set and refresh is enabled the counter counts to zero At this time a
28. ON Figure 8 2 IC Standard Communication Protocol 2 Slave address transmission The master sends the slave address in the first byte after the START signal B After the seven bit calling address it sends the R W bit C which tells the slave data transfer direction Each slave must have a unique address An master must not transmit an address that is the same as its slave address it cannot be master and slave at the same time M MOTOROLA Chapter 8 Module 8 3 12 Protocol The slave whose address matches that sent by the master pulls SDA low at the ninth clock D to return an acknowledge bit 3 Data transfer When successful slave addressing is achieved the data transfer can proceed E on a byte by byte basis in the direction specified by the R W bit sent by the calling master Data can be changed only while SCL is low and must be held stable while SCL is high as Figure 8 2 shows SCL is pulsed once for each data bit with the msb being sent first The receiving device must acknowledge each byte by pulling SDA low at the ninth clock therefore a data byte transfer takes nine clock pulses If it does not acknowledge the master the slave receiver must leave SDA high The master can then generate a STOP signal to abort the data transfer or generate a START signal repeated start shown in Figure 8 3 to start a new calling sequence If the master receiver does not acknowledge the slave tran
29. eese nennen 8 6 PC Frequency Divider Register IFDR esee 8 7 PC Control Register ZOCR 8 8 Status Register IDSR i i ie ene ee te 8 9 PC Data I O Resister O A B E O 4 eerte eese 8 10 PC Programming Examples essen 8 10 Initialization Sequence 8 10 Generation of 8 10 Post Transfer Software Response 8 11 Generation OF SLOP eie tete e a e ee 8 12 Generation of Repeated 5 sese 8 12 Slave Mode c E EER 8 13 Arbitration 8 13 MCF5307 User s Manual M CONTENTS Paragraph Number ie Chapter 9 Interrupt Controller 9 1 n 9 2 Interrupt Controller Registers 9 2 1 Interrupt Control Registers ICRO ICRO 9 2 2 Autovector Register 9 2 3 Interrupt Pending and Mask Registers IPR and IMR 9 2 4 Interrupt Port Assignment Register Chapter 10 Chip Select Module 10 1 10 2 Chip Select Module Signals sss 10 3 Chip Select Oper amp tion ee ene meten em ten tee tie tein ene ete tees cens 10 3 1 General Chip Select 10 3 1 1 8 16 and 32 Bit Port Sizing eee ee esee 10 3 1 2 Global Chip Select
30. 20 20 MCF5307 User s Manual M ILLUSTRATIONS Figure Number Ju Number 1 1 MGF5307 Block Diagram onte te reiten auo in Lane Eo EAE 1 2 1 2 UART Module Block Diagram seen enne eene 1 9 1 3 PEE Module ni rettet ope rer ee ete oer d 1 12 1 4 ColdFire MCF5307 Programming Model sse 1 13 2 1 ColdFire Enhanced Pipeline eret ttt rtt tetti etel ostia nis 2 23 2 2 ColdFire Multiply Accumulate Functionality Diagram sees 2 25 2 3 ColdFire Programming Model sse 2 27 2 5 Status Register SR ROPA IRR MEHR 2 30 2 6 Vector Base Register VBR 2 30 2 7 Organization of Integer Data Formats in Data 15 15 2 32 2 8 Organization of Integer Data Formats in Address Registers 2 32 2 0 Memory Operand Addressing esses 2 33 2 10 Exception Stack Frame Form sese 2 49 3 1 ColdFire MAC Multiplication and Accumulation see 3 2 3 2 MAC Programming Model seen 3 2 4 1 SRAM Base Address Register RAMBAR eese 4 3 4 2 7 4 7 4 3 Cache Organization and Line Format esee 4 8 4 4 Cache
31. Table 18 4 Bus Cycle States State Cycle BCLKO Description S0 All High The read or write cycle is initiated On the rising edge of BCLKO the MCF5307 places a valid address on the address bus asserts TIP and drives R W high for a read and low for a write if these signals are not already in the appropriate state The MCF5307 asserts TT 1 0 TM 2 0 SIZ 1 0 and TS on the rising edge of BCLKO 1 All Low AS asserts on the falling edge of BCLKO indicating that the address and attributes are stable The appropriate CSx BE BWE and OE signals assert on the BCLKO falling edge Fast termination TA must be asserted during S1 Data is made available by the external device and is sampled on the rising edge of BCLKO with TA asserted 2 Read write High TS is negated on the rising edge of BCLKO skipped for fast termination Write The data bus is driven out of high impedance as data is placed on the bus on the rising edge of BCLKO S3 Read write Low The MCF5307 waits for TA assertion If T is not sampled as asserted before skipped for fast the rising edge of BCLKO at the end of the first clock cycle the MCF5307 termination inserts wait states full clock cycles until TA is sampled as asserted Read Data is made available by the external device on the falling edge of BCLKO and is sampled on the rising edge of BCLKO with TA asserted S4 All High The external device
32. 0 eee 10 4 ChipsSelect 10 4 1 Chip Select Module Registers esee 10 4 1 1 Chip Select Address Registers 7 10 4 1 2 Chip Select Mask Registers 10 4 1 3 Chip Select Control Registers CSCRO CSCR7 10 4 1 4 Code Example esee Chapter 11 Synchronous Asynchronous DRAM Controller Module 11 1 QVELVICW 11 1 1 MR 11 1 2 Block Diagram and Major Components sese 11 2 DRAM Controller Operation 1 11 2 1 DRAM Controller Registers eee 11 3 Asynchronous Operation 11 3 1 DRAM Controller Signals in Asynchronous 11 3 2 Asynchronous Register 11 3 2 1 DRAM Control Register DCR in Asynchronous Mode 11 3 2 2 DRAM Address and Control Registers DACRO DACRI 11 3 2 3 DRAM Controller Mask Registers DMRO DMRI 11 3 3 General Asynchronous Operation Guidelines 11 3 3 1 Non Page Mode Operation sese M MOTOROLA Contents Page Number xi Paragraph Number 11 3 3 2 11 3 3 3 11 3 3 4 11 3 3 5 11 4 11 4 1 11 4 2 11 4 3 11 4 3 1 11 4 3 2 11 4 3 3 11 4 4 11 4 4
33. a 4 18 Push and Store B fferS cie aane e emt tienes 4 18 Push and Store Buffer Bus Operation sse 4 18 Cache Locking ote ten mim tenuere Dres eec testers 4 19 Cache udutis cd 4 21 Cache Control Register CACR eese 4 21 Access Control Registers ACRO ACRI eere 4 22 Cache Management eet ettet eno itae eee cui See 4 24 Cache Operation 4 25 Cache State Transitions nennen 4 25 Cache Initialization Code eese nennen nnns 4 29 Chapter 5 Debug Support COVEIVIEW MEE Signal Description neieiet nennen enemies Real Time Trace Support Begin Execution of Taken Branch PST 0x5 see 5 4 Programming 5 5 Address Attribute Trigger Register 5 7 Address Breakpoint Registers ABLR ABHR eene 5 8 BDM Address Attribute Register BAAR eere 5 9 Configuration Status Register CSR sess 5 10 Data Breakpoint Mask Registers DBR DBMRB eee 5 12 Program Counter Breakpoint Mask Registers PBR 5 13 Trigger Definition Register 5 14 Background Debug Mode 5 16 CPU Halt emet e tede 5 16 BDM Serial Ini
34. s USRh TxRDY Ko x A internal v M ld module w w select i C1 C2 C3 Start C4 Stop C5 C6 break break not i transmitte CTS N RTS4 Manually asserted Manually by BIT SET command asserted 1 transmit characters W write 3 UMR2n TxCTS 1 UMR2n TxRTS 1 Figure 14 21 Transmitter Timing Diagram 14 5 2 2 Receiver The receiver is enabled through its UCRn as described in Section 14 3 5 UART Command Registers UCRn Figure 14 22 shows receiver functional timing 14 22 MCF5307 User s Manual M woronoLA Operation T T TxD C1 C2 C4 C5 C6 C7 C8 C6 C7 and C8 will be lost Receiver Enabled USRn RxRDY USRn FFULL internal y module select Status Status Status Status Data C5 will Data Data Data C1 be lost C2 C3 C4 Ld Overrun Reset by USRn OE command Manually asserted first time Automatically asserted RTS automatically negated if overrun occurs when ready to receive UOPO RTS 1 Figure 14 22 Receiver Timing When the receiver detects a high to low mark to space
35. 17 10 MCF5307 User s Manual M woronoLA MCF5307 Bus Signals Table 17 6 TM 2 0 Encodings for TT 00 Normal Access Continued TM 2 0 Transfer Modifier 110 Supervisor code access 111 Reserved As shown in Table 17 7 if the DMA is bus master TT 01 TM 2 0 indicate the type of access and provide the DMA acknowledgement information for channels 0 and 1 NOTE When 01 the encoding is independent from TM 2 1 encoding Table 17 7 Encoding for DMA as Master 01 TMO Transfer Modifier Encoding 0 Single address access negated 1 Single address access Table 17 8 TM 2 1 Encoding for DMA as Master TT 01 TM 2 1 Transfer Modifier Encoding 00 DMA acknowledges negated 01 DMA acknowledge channel 0 10 DMA acknowledge channel 1 11 Reserved Table 17 9 shows TM 2 0 encodings for emulator mode accesses Table 17 9 TM 2 0 Encodings for TT 10 Emulator Access TM 2 0 Transfer Modifier 000 100 Reserved 101 Emulator mode data access 110 Emulator mode code access 111 Reserved The TM signals indicate user or data transfer types during emulation transfers while for interrupt acknowledge transfers the TM signals carry the interrupt level being acknowledged see Table 17 10 Table 17 10 TM 2 0 Encodings for TT z 11 Interrupt Level TM 2 0 Transfer Modifi
36. 2 0 Register Contains the register number in commands that operate on processor registers 5 5 3 1 1 Extension Words as Required Some commands require extension words for addresses and or immediate data Addresses require two extension words because only absolute long addressing is permitted Longword accesses are forcibly longword aligned and word accesses are forcibly word aligned Immediate data can be 1 or 2 words long Byte and word data each requires a single extension word and longword data requires two extension words Operands and addresses are transferred most significant word first In the following descriptions of the BDM command set the optional set of extension words is defined as address data or operand data 5 5 3 2 Command Sequence Diagrams The command sequence diagram in Figure 5 17 shows serial bus traffic for commands Each bubble represents a 17 bit bus transfer The top half of each bubble indicates the data the development system sends to the debug module the bottom half indicates the debug module s response to the previous development system commands Command and result transactions overlap to minimize latency M MOTOROLA Chapter 5 Debug Support 5 21 Background Debug Mode BDM COMMANDS TRANSMITTED TO THE DEBUG MODULE COMMAND CODE TRANSMITTED DURING THIS CYCLE HIGH ORDER 16 BITS OF MEMORY ADDRESS LOW ORDER 16 BITS OF MEMORY ADDRESS NONSERIAL RELATED ACTIVITY SEQUENCE TA
37. enne 5 40 5 6 1 1 Emulator Mode st aes utm tnn oe sade 5 41 5 6 2 Concurrent BDM and Processor Operation 5 41 5 7 Motorola Recommended BDM Pinout seen 5 42 5 8 Processor Status DDATA 5 42 5 8 1 IJser Instr ctionr56t EAS teste sates 5 43 5 8 2 Supervisor Instruction Set sess 5 46 Part Il System Integration Module SIM Chapter 6 SIM Overview 6 1 6 2 Programming 6 2 1 SIM Register Memory Map sess ene eren 6 2 2 Module Base Address Register MBAR eee 6 2 3 Reset Status Register RSR eese 6 2 4 Software Watchdog Timer esee eene 6 2 5 System Protection Control Register SYPCR 6 2 6 Software Watchdog Interrupt Vector Register 6 9 6 2 7 Software Watchdog Service Register SWSR sese 6 9 6 2 8 PLL Clock Control for CPU STOP Instruction esee 6 10 6 2 9 Pin Assignment Register 6 10 6 2 10 Bus Arbitration Control e 6 11 6 2 10 1 Default Bus Master Park Register 6 11 6 2 10 1 1 Arbitration for Internally Generated Transfers MPARK PAREK 6 12
38. 12 17 Timer Block Diagram 13 1 Timer Mode Registers 1 eee 13 3 Timer Reference Registers TRRO TRR1 eene 13 4 Timer Capture Register 1 sese 13 5 Tuner Counters CDONO TGNT 5 tete tree dank P s 13 5 Timer Event Registers TERO TERI esee nnne nne 13 5 Simplified Block Diagram 1 14 1 UART Mode Registers 1 10 14 5 UART Mode Register 2 UMR2n 14 6 UART Status Register USRn 14 7 UART Clock Select Register UCSRn eese nnne 14 8 UART Command Register UCRn eese nennen nnne nnns 14 9 UART Receiver Buffer URBOJ nire a a 14 11 UART Transmitter Buffer enne 14 12 UART Input Port Change Register UIPCRn see 14 12 MCF5307 User s Manual M woronoLA Figure Number 14 10 14 11 14 12 14 13 14 14 14 15 14 17 14 16 14 18 14 19 14 20 14 21 14 22 14 23 14 24 14 25 14 26 14 27 15 1 15 2 15 3 16 1 16 2 16 3 17 1 18 1 18 2 18 3 18 4 18 5 18 6 18 7 18 8 18 9 18 10 18 11 18 12 18 13 18 14 18 15 18 16 18 17 18 18 ILLUSTRATIONS Page Jie Number UART Auxiliary Control Register UACRn eee 14 13 UART Interrupt Status Mask Registers UISRn UIMR
39. 14 1 Serial Module OvVerVIeW n 14 2 R gister DeSCEIDUOnDS uer embed Pe DEBER 14 2 UART Mode Registers 1 UMRn eere 14 4 UART Mode Register 2 UMR2n eee 14 6 UART Status Registers USRn esee 14 7 Contents xiii Paragraph Number 14 3 4 14 3 5 14 3 6 14 3 7 14 3 8 14 3 9 14 3 10 14 3 11 14 3 12 14 3 13 14 3 14 14 4 14 5 14 5 1 14 5 1 1 14 5 1 2 14 5 1 2 1 14 5 1 2 2 14 5 2 14 5 2 1 14 5 2 2 14 5 2 3 14 5 3 14 5 3 1 14 5 3 2 14 5 3 3 14 5 4 14 5 5 14 5 5 1 14 5 5 2 14 5 5 3 14 5 6 14 5 6 1 15 1 15 1 1 15 1 2 15 1 3 15 1 4 xiv CONTENTS Page We Number UART Clock Select Registers UCSRn eere 14 8 UART Command Registers UCRn eene 14 9 UART Receiver Buffers 14 11 UART Transmitter Buffers 14 11 UART Input Port Change Registers UIPCRn eee 14 12 UART Auxiliary Control Register UACRnD see 14 12 UART Interrupt Status Mask Registers UISRn UIMR q 14 13 UART Divider Upper Lower Registers UDUn UDLx 14 14 UART Interrupt Vector Register UIVRn eee 14 15 UART Input Port Register UIPn seseeeeeeee 14 15 UART Output Port Command Registers UOP1n UOPOn
40. DRAMW 0 31 0 RAS 1 or 0 Figure 11 24 Mode Register Se 11 5 SDRAM Example MRS x t MRS Command This example interfaces a 2M x 32 bit x 4 bank SDRAM component to a MCF5307 operating at 40 MHz Table 11 32 lists design specifications for this example Table 11 32 SDRAM Example Specifications Parameter Specification Speed grade 8E 40 MHz 25 nS period 10 rows 8 columns Two bank select lines to access four internal banks ACTV to read write delay tacp 20 nS min Period between auto refresh and ACTV command tnc 70 nS ACTV command to precharge command tras 48 nS min Precharge command to ACTV command trp 20 nS min Last data input to PALL command tgw 1 bus clock 25 nS Auto refresh period for 4096 rows tper 64 mS 11 34 MCF5307 User s Manual M MOTOROLA SDRAM Example 11 5 1 SDRAM Interface Configuration To interface this component to the MCF5307 DRAM controller use the connection table that corresponds to a 32 bit port size with 8 columns Table 11 26 Two pins select one of four banks when the part is functional Table 11 33 shows the proper hardware hook up Table 11 33 SDRAM Hardware Connections MCF5307 A15 A14 A13 A12 A11 A10 A9 A17 A18 A19 A20 A21 A22 Pins SDRAM A0 A1 A2 A3 A4 A5 A6 7 8 AQ A102 BAO 1
41. 5 o nonae anie aee e n ERR Tee avs 4 4 SRAM Initialization Code eese nennen nennen nnne 4 5 Power Management 4 6 Cache OVeEVIe Wo vue tute ne mer 4 6 Cache 4 7 Cache Line States Invalid Valid Unmodified and Valid Modified 4 8 The Cache at Start Up svicissccsccsisiscsccsscscosecsecsacucostsvcsvacveostsvesensseviessesceutconsssestes 4 9 Cache Op ration iieri e i re Pere E O eei Eee ER even esed 4 11 Caching 4 13 Cacheable 4 13 Write Through Mode 4 14 Copyback Mode 4 14 Cache Inhibited 3 nnne 4 14 Cache PHOLOCOL dite E P REFIERE 4 15 I SERBIEN 4 15 MIS sim tumet 4 16 Read Elit idend Ier 4 16 Write Hte reete dee tore M M m NUMOS 4 16 Cache Coher rgcy 5 o oe ee eet ene 4 17 M Contents vii Paragraph Number 4 9 5 4 9 5 1 4 9 5 2 4 9 5 2 1 4 9 5 2 2 4 9 6 4 10 4 10 1 4 10 2 4 11 4 12 4 12 1 4 13 5 1 52 5 3 5 3 1 5 4 5 4 1 5 4 2 5 4 3 5 4 4 5 4 5 5 4 6 5 4 7 5 5 5 5 1 5 9 2 5 5 2 1 9 5 2 2 9 9 3 5 5 3 1 5 5 3 1 1 5 5 32 5 5 3 3 5 5 3 3 1 3 5 3 32 5 5 3 3 3 viii CONTENTS Page Ae Number Memory Accesses for Cache Maintenance 4 17 Cache Fillmg dh HEP eire 4 17 Cache Pushes ate a E en AM
42. CAS 3 0 DACRn CAS 01 DRAMW DIST Figure 11 5 Basic Non Page Mode Operation RCD 0 RNCN 1 4 4 4 4 M MOTOROLA Chapter 11 Synchronous Asynchronous DRAM Controller Module 11 11 Asynchronous Operation Figure 11 6 shows a variation of the basic cycle In this case RCD is 1 so there are two clocks between RAS and CAS Note that the address is multiplexed on the rising clock immediately before CAS is asserted Because RNCN 0 RAS and CAS are negated together The next bus cycle is initiated but because DACRn RP requires RAS to be precharged for two clocks RAS is delayed for a clock in the bus cycle Note that this does not delay the address signals only RAS BCLKO RAS 1 or 0 CAS 3 0 me J psig D se A Figure 11 6 Basic Non Page Mode Operation RCD 1 RNCN 0 5 5 5 5 11 3 3 2 Burst Page Mode Operation Burst page mode operation DACRn PM 01 optimizes memory accesses in page mode by allowing a row address to remain registered in the DRAM while accessing data in different columns This eliminates the setup and hold times associated with the need to precharge and assert RAS Therefore only the first bus cycle in the page takes the full access ti
43. E trapf w 1 0 0 trapf l 1 0 0 unlk AX 3 1 0 wddata lt ea gt 7 1 0 7 1 0 7 1 0 7 1 0 8 1 0 7 1 0 wdebug l ea 10 2 0 10 2 0 a Ro N If a MOVE W imm SR instruction is executed and imm 13 1 the execution time is 1 0 0 n is the number of registers moved by the MOVEM opcode PEA execution times are the same for d16 PC PEA execution times are the same for d8 PC Xi SF The execution time for STOP is the time required until the processor begins sampling continuously for interrupts 2 7 5 Branch Instruction Execution Times Table 2 16 shows general branch instruction timing Table 2 16 General Branch Instruction Execution Times Effective Address Opcode ea Rn An An An d16 An d8 An Xi SF xxx wl lt xxx gt bra 1 0 1 bsr 1 0 1 jmp ea 5 0 0 5 0 0 6 0 0 1 0 0 jsr lt ea gt 5 0 1 5 0 1 6 0 1 1 0 1 rte 14 2 0 rts m 8 1 0 m 2a 1 Assumes branch acceleration Depending on the pipeline status execution times may vary from 1 to 3 cycles For the conditional branch opcodes bcc a static algorithm is used to determine the prediction state of the branch This algorithm is
44. Figure 7 2 PLL Control Register PLLCR Table 7 1 describes PLLCR bits Table 7 1 PLLCR Field Descriptions Bit Name Description 7 ENBSTOP Enable CPU STOP instruction Must be set for the ColdFire CPU STOP instruction to be acknowledged Cleared at reset and must be subsequently set for the processor to enter low power modes Only clocks to the core are turned off because of the CPU STOP instruction Internal modules remain clocked and can generate interrupts to restart the ColdFire core 0 Disable CPU STOP 1 Enable CPU STOP STOP instruction turns off clocks to the ColdFire core 6 4 PLLIPL PLL interrupt priority level to wake up from CPU STOP Determines the minimum level an interrupt decoded as an interrupt priority level must be to waken the PLL The PLL then turns clocks back on to the core processor and interrupt exception processing occurs 000 Any interrupts can wake core 001 Interrupts 2 7 010 Interrupts 3 7 011 Interrupts 4 7 100 Interrupts 5 7 101 Interrupts 6 7 110 Interrupt 7 only 111 No interrupts can wake core Any reset including a watchdog reset can wake the core No PLL phase lock time is required 3 0 Reserved should be cleared 7 3 PLL Port List Table 7 2 describes PLL module inputs Table 7 2 PLL Module Input Signals Signal Description CLKIN Input clock to the PLL Input frequency must not be changed during operation Changes are recognized only at re
45. NOT READY DEON NOT READY XXX NEXT CMD NEXT CMD ILEGAL READY COMPLETE NEXT CMD Gorin Figure 5 29 FILL Command Sequence Operand Data A single operand is data to be written to the memory location Byte data is sent as a 16 bit word justified in the least significant byte 16 and 32 bit operands are sent as 16 and 32 bits respectively Result Data Command complete status OXFFFF is returned when the register write is complete A value of 0x0001 with S set is returned if a bus error occurs 5 32 MCF5307 User s Manual M woronoLA Background Debug Mode BDM 5 5 3 3 7 Resume Execution Go The pipeline is flushed and refilled before normal instruction execution resumes Prefetching begins at the current address in the PC and at the current privilege level If any register such as the PC or SR is altered by a BDM command while the processor is halted the updated value is used when prefetching resumes If a GO command is issued and the CPU is not halted the command is ignored 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 OxC 0x0 0 0 Figure 5 30 Command Format Command Sequence 60 NEXT CMD Figure 5 31 Go Command Sequence Operand Data None Result Data The command complete response OxFFFF is returned during the next shift operation M MOTOROLA Chapter 5 Debug Support 5 33 Background Debug Mode BDM 5 5 3 3 8 No Ope
46. sse 11 8 11 7 DRAM Addressing for Byte Wide 11 10 11 8 DRAM Addressing for 16 Bit Wide Memories sess 11 10 11 9 DRAM Addressing for 32 Bit Wide Memories sss 11 11 TO SDRAM Commands ie obe oer ee eue ESPERE EE ERE Ge 11 17 11 11 Synchronous DRAM Signal Connections sess 11 17 11 12 DCR Field Descriptions Synchronous Mode eee 11 19 11 13 DACRO DACRI Field Descriptions Synchronous Mode sss 11 21 11 14 DMRO0 DMRI Field Descriptions 11 15 5307 to SDRAM Interface 8 Bit Port 9 Column Address Lines 11 24 11 16 5307 to SDRAM Interface 8 Bit Port 10 Column Address Lines 11 24 11 17 5307 to SDRAM Interface 8 Bit Port 11 Column Address Lines 11 24 11 18 5307 to SDRAM Interface 8 Bit Port 12 Column Address Lines 11 24 11 19 5307 to SDRAM Interface 8 Bit Port 13 Column Address Lines 11 25 11 20 5307 to SDRAM Interface 16 Bit Port 8 Column Address Lines 11 25 11 21 5307 to SDRAM Interface 16 Bit Port 9 Column Address Lines 11 25 11 22 5307 to SDRAM Interface 16 Bit Port 10 Column Address Lines 11 25 11 23 5307 to SDRAM Interface 16 Bit Port 11 Column Address Lines 11 25 11 24 5307 to SDRA
47. 17 4 2 Bus Grant BG An external arbiter asserts the BG input to indicate that the MCF5307 can take control of the bus on the next rising edge of BCLKO When the arbiter negates BG the MCF5307 will release the bus as soon as the current transfer completes The external arbiter must not grant the bus to any other master until both BD and BG are negated 17 12 MCF5307 User s Manual M woronoLA Clock and Reset Signals 17 4 3 Bus Driven BD The MCF5307 asserts BD to indicate that it is the current master and is driving the bus The MCF5307 behaves as follows f the MCF5307 is the bus master but is not using the bus BD is asserted If the MCF5307 loses mastership during a transfer it completes the last transfer of the access negates BD and three states all bus signals on the rising edge of BCLKO If the MCF5307 loses bus mastership during an idle clock cycle it three states all bus signals on the rising edge of BCLKO BDcannot be negated unless BG is negated 17 5 Clock and Reset Signals The clock and reset signals configure the MCF5307 and provide interface signals to the external system 17 5 1 Reset In RSTI Asserting RSTI causes the MCF5307 to enter reset exception processing When RSTI is recognized BR and BD are negated and the address bus data bus TT SIZ R W AS and TS are three stated RSTO is asserted automatically when RSTI is asserted 17 5 2 Clock Input CLKIN CLKIN is the MC
48. Byte 0x0000 0000 Byte 0x0000 0001 Byte 0x0000 0002 Byte 0x0000 0003 Longword 0x0000 0004 Word 0x0000 0004 Word 0x0000 0006 Byte 0x0000 0004 Byte 0x0000 0005 Byte 0x0000 0006 Byte 0x0000 0007 Longword OxFFFF FFFC BIOS e el e Word OxFFFF_FFFE Byte OXFFFF FFFC Byte OXFFFF FFFD Byte OxFFFF_FFFE Byte OxFFFF_FFFF Figure 2 9 Memory Operand Addressing 2 5 Addressing Mode Summary Addressing modes are categorized by how they are used Data addressing modes refer to data operands Memory addressing modes refer to memory operands Alterable addressing modes refer to alterable writable data operands Control addressing modes refer to memory operands without an associated size These categories sometimes combine to form more restrictive categories Two combined classifications are alterable memory both alterable and memory and data alterable both alterable and data Twelve of the most commonly used effective addressing modes from the M68000 Family are available on ColdFire microprocessors Table 2 5 summarizes these modes and their categories M MOTOROLA Chapter 2 ColdFire Core 2 33 Instruction Set Summary Table 2 5 ColdFire Effective Addressing Modes Category Addressing Modes Syntax bi meg 8 Data Memory Control Alterable Register direct Data Dn 000 reg no X X Address An 001 reg no X Register indirect Address An 010 reg no
49. includes general descriptions of the modules and features incorporated in the MCF5307 focussing in particular on new features e Part I is intended for system designers who need to understand the operation of the MCF5307 ColdFire core Chapter 2 ColdFire Core provides an overview of the microprocessor core of the MCF5307 The chapter begins with a description of enhancements from the V2 ColdFire core and then fully describes the V3 programming model as it is implemented on the MCF5307 It also includes a full description of exception handling data formats an instruction set summary and a table of instruction timings Chapter 3 Hardware Multiply Accumulate MAC Unit describes the MCF5307 multiply accumulate unit which executes integer multiply multiply accumulate and miscellaneous register instructions The MAC is integrated into the operand execution pipeline OEP M MOTOROLA AboutThis Book Organization xxxii Chapter 4 Local Memory This chapter describes the MCF5307 implementation of the ColdFire V3 local memory specification It consists of the two following major sections Section 4 2 SRAM Overview describes the MCF5307 on chip static RAM SRAM implementation It covers general operations configuration and initialization It also provides information and examples showing how to minimize power consumption when using the SRAM Section 4 7 Cache Overview
50. Bus clocks T2 TIN valid to BCLKO input setup 7 5 5 5 nS T3 BCLKO to TIN invalid input hold 3 2 nS T4 BCLKO to TOUT valid output valid 15 11 nS T5 BCLKO to TOUT invalid output hold 1 5 1 5 nS T6 TIN pulse width 1 1 Bus clocks T7 TOUT pulse width 1 1 Bus clocks ET AQ gt gt Em TIN N m TOUT Figure 20 14 Timer Module AC Timing 20 14 MCF5307 User s Manual M woronoLA Input Output Timing Specifications 20 7 12 Input Output Timing Specifications Table 20 10 lists specifications for the input timing parameters shown in Figure 20 8 Table 20 10 12 Input Timing Specifications between SCL and SDA 66 MHz 90 MHz Num Characteristic Units Min Max Min Max Start condition hold time 2 2 Bus clocks 12 Clock low period 8 m 8 Bus clocks I3 SCL SDA rise time Vi 0 5 V to 2 4 V 1 1 mS l4 Data hold time 0 0 ns 15 SCL SDA fall time 2 4 V to Vi 0 5 V 1 1 mS l6 Clock high time 4 4 Bus clocks 17 Data setup time 0 0 nS 18 Start condition setup time for repeated start condition only 2 2 Bus clocks I9 Stop condition setup time 2 2 Bus clocks Table 20 11 lists specifications for the PC output timing parameters shown in Figure 20 8 Table 20 11 I2C Output Timing Specifications between SCL
51. TMR PS TMR CLK 10 System Bus Clock 16 TMR CLK 01 System Bus Clock 1 Decimal Hex 45 MHz 30 MHz 22 5 MHz 45 MHz 30 MHz 22 5 MHz 246 F6 5 75552 8 63328 11 51103 0 35972 0 53958 0 71944 247 F7 5 77882 8 66823 11 55764 0 36118 0 54176 0 72235 248 F8 5 80212 8 70318 11 60424 0 36263 0 54395 0 72527 249 F9 5 82542 8 73813 11 65084 0 36409 0 54613 0 72818 250 FA 5 84872 8 77309 11 69745 0 36555 0 54832 0 73109 251 FB 5 87203 8 80804 11 74405 0 367 0 5505 0 734 252 FC 5 89533 8 84299 11 79065 0 36846 0 55269 0 73692 253 FD 5 91863 8 87794 11 83726 0 36991 0 55487 0 73983 254 FE 5 94193 8 9129 11 88386 0 37137 0 55706 0 74274 255 FF 5 96523 8 94785 11 93046 0 37283 0 55924 0 74565 13 14 MCF5307 User s Manual M woronoLA Chapter 14 UART Modules This chapter describes the use of the universal asynchronous synchronous receiver transmitters UARTs implemented on the MCF5307 and includes programming examples All references to UART refer to one of these modules 14 1 Overview The MCF5307 contains two independent UARTs Each UART can be clocked by BCLKO eliminating the need for an external crystal As Figure 14 1 shows each UART module interfaces directly to the CPU and consists of the following Serial communication channel Programmable transmitter and receiver clock generation Internal channel control logic e Interrupt control logic UART CTS Internal Channel Serial RIS Control Logie Communications Channel RxD TxD
52. Write UART command registers UCRn p 14 9 0 1 0 20 UART Read UART receiver buffers URBn p 14 11 UART Write UART transmitter buffers UTBn p 14 11 0 100 0 210 Read UART input port change registers UIPCRn p 14 12 Write UART auxiliary control registers UACRn p 14 12 0 104 Ox214 Read UART interrupt status registers UISRn p 14 13 Write UART interrupt mask registers UIMRn p 14 13 Ox1D8 0 218 UART divider upper registers UDUn p 14 14 Ox1DC 0x21C UART divider lower registers UDLn p 14 14 M MOTOROLA Chapter 14 UART Modules 14 3 Register Descriptions Table 14 1 UART Module Programming Model Continued MBAR Offset 31 24 23 16 15 8 7 0 UARTO UART1 0x1E0 0x220 Do not access Ox1EC 0x22C Ox1FO 0x230 UART interrupt vector register UIVRn p 14 15 Ox1F4 0 234 Read UART input port registers UIPn p 14 15 Write Do not access 0 1 8 0x238 Read Do not access Write UART output port bit set command registers UOP n p 14 15 OxiFC Ox23C Read Do not access Write UART output port bit reset command registers UOPOn p 14 15 1 UMRin UMR2n and UCSRn should b
53. if bcc is a forward branch amp amp CCR 7 then the bcc is predicted as not taken 2 46 MCF5307 User s Manual M MOTOROLA Exception Processing Overview if bcc is a forward branch amp amp CCR 7 then the bcc is predicted as taken else if bcc is a backward branch then the bcc is predicted as taken Table 2 17 shows timing for Bcc instructions Table 2 17 Bcc Instruction Execution Times Predicted Predicted Correctly as Not Predicted Correctly as Taken Taken Incorrectly bcc 1 0 0 1 0 0 5 0 0 2 8 Exception Processing Overview Exception processing for ColdFire processors is streamlined for performance Differences from previous M68000 Family processors include the following Asimplified exception vector table e Reduced relocation capabilities using the vector base register Asingle exception stack frame format Use ofa single self aligning system stack pointer ColdFire processors use an instruction restart exception model but require more software support to recover from certain access errors See Table 2 18 for details Exception processing can be defined as the time from the detection of the fault condition until the fetch of the first handler instruction has been initiated It is comprised of the following four major steps 1 The processor makes an internal copy of the SR and then enters supervisor mode by setting SR S and disabling trace mode by clearin
54. 0 SC SD UC and UD are ignored in the chip select decode on external master or DMA access 0 V Valid bit Indicates whether the corresponding CSAR CSMR and CSCR contents are valid Programmed chip selects do not assert until V is set except for CSO which acts as the global chip select Reset clears each CSMRn V 0 Chip select invalid 1 Chip select valid M MOTOROLA Chapter 10 Chip Select Module 10 7 Chip Select Registers 10 4 1 3 Chip Select Control Registers CSCRO CSCR7 Each chip select control register Figure 10 4 controls the auto acknowledge external master support port size burst capability and activation of each chip select Note that to support the global chip select CSO the CSCRO reset values differ from the other CSCRs CS0 allows address decoding for boot ROM before system initialization 15 14 18 10 9 8 7 6 5 4 3 2 0 Field WS PS1 PS0 BEM BSTR BSTW Reset CSCRO 11_11 D7 D6 D5 Reset Other CSCRs Unitialized R W R W Address 0x08A CSCRO 0x096 CSCR1 0x0A2 CSCR2 CSCR3 0 CSCR4 0x0C6 CSCR5 0x0D2 CSCR6 0x0DE CSCR7 Figure 10 4 Chip Select Control Registers CSCRO CSCR7 Table 10 9 describes CSCRn fields Table 10 9 CSCRn Field Descriptions Bits Name Description 15 44 Reserved should be cleared 13 10 WS Wait states The numb
55. A Address and Data Timing with EDGESEL Tied High B Address and Data Timing with EDGESEL Tied Low Buffer Delay BCLKO net ed Buffered IA i ain BCLKO E Adde VALID X VALID x VALID X VALID C Address and Data Timing with EDGESEL Tied to Buffered Clock Figure 11 14 Using EDGESEL to Change Signal Timing 11 4 3 Synchronous Register Set The memory map in Table 11 1 is the same for both synchronous and asynchronous operation However some bits are different as noted in the following sections 11 4 3 1 DRAM Control Register DCR in Synchronous Mode The DRAM control register DCR Figure 11 15 controls refresh logic 15 14 18 12 11 10 9 8 7 6 5 4 3 2 1 0 Field SO NAM COC IS RTIM RC Reset 0 Uninitialized R W R W Addr MBAR 0x100 Figure 11 15 DRAM Control Register DCR Synchronous Mode Table 11 12 describes DCR fields Table 11 12 DCR Field Descriptions Synchronous Mode Bits Name Description 15 SO Synchronous operation Selects synchronous or asynchronous mode When in synchronous mode the DRAM controller can be switched to ADRAM mode only by resetting the MCF5307 0 Asynchronous DRAMs Default at reset 1 Synchronous DRAMs 14 Reserved should be cleared 13 NAM No address multiplexing Some implementations require external multiplexing For example when lin
56. BDM State Machine Current State X Next State Figure 5 13 BDM Serial Interface Timing DSO Past Current T T t T T DSCLK and DSI are synchronized inputs DSCLK acts as a pseudo clock enable and is sampled on the rising edge of the processor CLK as well as the DSI DSO is delayed from the DSCLK enabled CLK rising edge registered after a BDM state machine state change All events in the debug module s serial state machine are based on the processor clock rising edge DSCLK must also be sampled low on a positive edge of CLK between each bit exchange The MSB is transferred first Because DSO changes state based on an internally recognized rising edge of DSCLK DSDO cannot be used to indicate the start of a serial transfer The development system must count clock cycles in a given transfer C1 C4 are described as follows e Cl First synchronization cycle for DSI DSCLK is high e C2 Second synchronization cycle for DSI DSCLK is high e C3 BDM state machine changes state depending upon DSI and whether the entire input data transfer has been transmitted e C4 DSO changes to next value NOTE A not ready response can be ignored except during a memory referencing cycle Otherwise the debug module can accept a new serial transfer after 32 processor clock periods 5 18 MCF5307 User s Manual M woronoLA Background Debug Mode BDM 5 5 2 1 Receive Packet Format T
57. EM D i BEIBWEx N B D 31 0 Read SS Write _E _ Figure 18 11 Back to Back Bus Cycles Basic read and write cycles are used to show a back to back cycle but there is no restriction as to the type of operations to be placed back to back The initiation of a back to back cycle is not user definable 18 4 7 Burst Cycles The MCF5307 can be programmed to initiate burst cycles if its transfer size exceeds the size of the port it is transferring to For example with bursting enabled a word transfer to an 8 bit port would take a 2 byte burst cycle for which SIZ 1 0 10 throughout A line transfer to a 32 bit port would take a 4 longword burst cycle for which SIZ 1 0 11 throughout The MCF5307 bus can support 2 1 1 1 burst cycles to maximize cache performance and optimize DMA transfers A user can add wait states by delaying termination of the cycle The initiation of a burst cycle is encoded on the size pins For burst transfers to smaller port sizes SIZ 1 0 indicates the size of the entire transfer For example if the MCF5307 writes a longword to an 8 bit port SIZ 1 0 00 for the first byte transfer and does not change CSCRs are used to enable bursting for reads writes or both MCF5307 memory space can be declared burst inhibited for reads and writes by clearing the appropriate CSCRx BSTR BSTW A line access to a burst inhibited region is broken int
58. Generate Dummy Read Dummy Read STOP Signal from I2DR from I2DR Figure 8 10 Flow Chart of Typical 2 Interrupt Routine 8 14 MCF5307 User s Manual M woronoLA Chapter 9 Interrupt Controller This chapter describes the operation of the interrupt controller portion of the system integration module SIM It includes descriptions of the registers in the interrupt controller memory map and the interrupt priority scheme 9 1 Overview The SIM provides a centralized interrupt controller for all MCF5307 interrupt sources which consist of the following External interrupts Software watchdog timer Timer modules module UART modules DMA module Figure 9 1 is a block diagram of the interrupt controller System Integration Module SIM DMA Four Channels Software Interrupt Controller Watchdog 12 ICR IRQPAR 2 5 I C Module Two General 4 Purpose PE Timers IRQ 1 3 5 7 Figure 9 1 Interrupt Controller Block Diagram M woronoLA Chapter 9 Interrupt Controller 9 1 Interrupt Controller Registers The SIM provides the following registers for managing interrupts Each potential interrupt source is assigned one of the 10 interrupt control registers ICRO ICR9 which are used to prioritize the interrupt sources The interrupt mask register IMR provides bits for masking individual interrupt sources The interrupt pending register IPR provides bits for indicating when an interrupt reque
59. Odd even no parity or force parity One one and a half or two stop bits Each channel programmable to normal full duplex automatic echo local loop back or remote loop back mode e Automatic wake up mode for multidrop applications e Four maskable interrupt conditions e UARTO and UART have interrupt capability to DMA channels 2 and 3 respectively when either the RXRDY or FFULL bit is set in the USR e Parity framing and overrun error detection e False start bit detection e Line break detection and generation Detection of breaks originating in the middle of a character e Start end break interrupt status 14 3 Register Descriptions This section contains a detailed description of each register and its specific function Flowcharts in Section 14 5 6 Programming describe basic UART module programming The operation of the UART module is controlled by writing control bytes into the appropriate registers Table 14 1 is a memory map for UART module registers 14 2 MCF5307 User s Manual M woronoLA Register Descriptions Table 14 1 UART Module Programming Model MBAR Offset 31 24 23 16 15 8 7 0 UARTO UART1 0 1 0 0x200 UART mode registers UMR1n p 14 4 UMR2n p 14 6 0 1 4 0x204 Read UART status registers USRn p 14 7 Write UART clock select register UCSRn p 14 8 0 1 8 0x208 Read Do not access
60. Parallel port bit Address bus bit 8 36 PP9 A25 lO Parallel port bit Address bus bit 8 37 VCC Power input 38 PP10 A26 lO Parallel port bit Address bus bit 8 39 PP11 A27 lO Parallel port bit Address bus bit 8 40 PP12 A28 lO Parallel port bit Address bus bit 8 41 GND Ground pin 42 PP13 A29 lO Parallel port bit Address bus bit 8 43 PP14 A30 lO Parallel port bit Address bus bit 8 44 PP15 A31 lO Parallel port bit Address bus bit 8 45 VCC Power input 46 SIZO VO Size attribute 8 47 8121 lO Size attribute 8 MCF5307 User s Manual M MOTOROLA Table 16 1 Pins 1 52 Left Top to Bottom Continued M MOTOROLA Pin i Ne Wane Description mA 48 GND Ground pin 49 OE Output enable for chip selects 8 50 CSO Chip select 8 51 CS1 Chip select 8 52 VCC Power input Table 16 2 Pins 53 104 Bottom Left to Right Pin i Name vo Description IA 53 GND Ground pin 54 CS2 Chip select 8 55 CS3 Chip select 8 56 54 Chip select 8 57 Power input 58 CS5 Chip select 8 59 CS6 Chip select 8 60 CS7 Chip select 8 61 GND Ground pin 62 AS Address str
61. The cache does not support snooping that is cache coherency is not supported while external or DMA masters are using the bus Therefore on chip DMAs of the MCF5307 cannot access local memory and do not maintain coherency with the unified cache 4 9 5 Memory Accesses for Cache Maintenance The cache controller performs all maintenance activities that supply data from the cache to the core including requests to the SIM for reading new cache lines and writing modified lines to memory The following sections describe memory accesses resulting from cache fill and push operations Chapter 18 Bus Operation describes required bus cycles in detail 4 9 5 1 Cache Filling When a new cache line is required a line read is requested from the SIM which generates a burst read transfer by indicating a line access with the size signals SIZ 1 0 The responding device supplies 4 consecutive longwords of data Burst operations can be inhibited or enabled through the burst read write enable bits BSTR BSTW in the chip select control registers CSCRO CSCR7 SIM line accesses implicitly request burst mode operations from memory For more information regarding external bus burst mode accesses see Chapter 18 Bus Operation The first cycle of a cache line read loads the longword entry corresponding to the requested address Subsequent transfers load the remaining longword entries A burst operation is aborted by an a write protection fault
62. UMR1n p 14 4 UMR2n p 14 6 0x1C4 Read UART status registers USRn p 14 7 Write UART clock select register UCSRn p 14 8 0x1C8 Read Do not access m Write UART command registers UCRn p 14 9 0 1 UART Read UART receiver buffers URBn p 14 11 UART Write UART transmitter buffers UTBn p 14 11 Ox1DO Read UART input port change registers UIPCRn p 14 12 A 4 MCF5307 User s Manual M woronoLA Table A 6 UARTO Module Programming Model Continued MBAR Offset 31 24 23 16 15 8 7 0 Write UART auxiliary control registers UACRn p 14 12 Ox1D4 Read UART interrupt status registers UISRn p 14 13 Write UART interrupt mask registers UIMRn p 14 13 0x1D8 UART divider upper E registers UDUn p 14 14 Ox1DC UART divider lower registers UDLn p 14 14 0 1 0 Do not access Ox1EC Ox1FO UART interrupt vector register UIVRn p 14 15 Ox1F4 Read UART input port registers UIPn p 14 15 Write Do not access 0x1F8 Read Do not access Write UART output port bit set command registers UOP 1n p 14 15 0 1 Read Do not access Write UART output port bit reset command registers UOPO0n p 14 15 UMRin UMR2n and
63. 0x0001 S 1 is returned if a bus error occurs 5 26 MCF5307 User s Manual M woronoLA Background Debug Mode BDM 5 5 3 3 4 Write Memory Location WRITE Write data to the memory location specified by the longword address The address space is defined by BAAR TT TM Hardware forces low order address bits to zeros for word and longword accesses to ensure that word addresses are word aligned and longword addresses are longword aligned Command Formats Byte 0 1 0 8 0 0 0x0 31 16 15 0 D 7 0 Word 0 1 0 8 0 4 0 0 31 16 15 0 D 15 0 Longword 0 1 0 8 0 8 0 0 31 16 15 0 D 31 16 D 15 0 Figure 5 24 WRITE Command Format M MOTOROLA Chapter 5 Debug Support 5 27 Background Debug Mode BDM Command Sequence WRITE WRITE B W ADDR ADDR S 22 READY READY READY READY C CMD NCMD COMPLETE XXX N BERR NEXT CMD READY WRITE LONG MS ADDR LS ADDR T MS DATA 22 READY NOT READY READY S Emm eem H READY LOCATION NOT READY CMD COMPLETE N BERR NEXT CMD READY Figure 5 25 WRITE Command Sequence Operand Data This two operand instruction requires a longword absolute address that specifies a location to w
64. 0xB DD destination subx l Dy Dx PST 0 1 swap Dx PST 0x1 trap imm PST 0x1 trapf PST 0x1 tst b ea x PST 0x1 PST 0x8 DD source operand tst l ea x PST 0 1 PST DD source operand tst w ea x PST 0x1 PST 0x9 DD source operand M MOTOROLA Chapter 5 Debug Support 5 45 Processor Status DDATA Definition Table 5 22 PST DDATA Specification for User Mode Instructions Continued Instruction Operand Syntax PST DDATA unlk Ax PST 0x1 PST DD destination operand wddata b lt ea gt y PST 0x4 PST 0x8 DD source operand wddata lt ea gt y PST 0x4 PST 0xB DD source operand wddata w lt ea gt y PST 0x4 PST 0x9 DD source operand 1 For JMP and JSR instructions the optional target instruction address is displayed only for those effective address fields defining variant addressing modes This includes the following lt ea gt x values An d16 An d8 An Xi 8 For Move Multiple instructions MOVEM the processor automatically generates line sized transfers if the operand address reaches a 0 modulo 16 boundary and there are four or more registers to be transferred For these line sized transfers the operand data is never captured nor displayed regardless of the CSR value The automatic line sized burst transfers are provided to maximize performance during these sequential memory access operation
65. 11 CO ADD 2 Figure 14 26 Multidrop Mode Timing Diagram A character sent from the master station consists of a start bit a programmed number of data bits an address data A D bit flag and a programmed number of stop bits A D 1 indicates an address character A D 0 indicates a data character The polarity of A D is selected through UMRIn PT UMRIn should be programmed before enabling the transmitter and loading the corresponding data bits into the transmit buffer In multidrop mode the receiver continuously monitors the received data stream regardless of whether it is enabled or disabled If the receiver is disabled it sets the RxRDY bit and loads the character into the receiver holding register FIFO stack provided the received A D bit is a one address tag The character is discarded if the received A D bit is zero data tag If the receiver is enabled all received characters are transferred to the CPU through the receiver holding register stack during read operations In either case the data bits are loaded into the data portion of the stack while the A D bit is loaded into the status portion of the stack normally used for a parity error USRn PE Framing error overrun error and break detection operate normally The A D bit takes the place of the parity bit therefore parity is neither calculated nor checked Messages in this M woronoLA Chapter 14 UART Modules 14 27 Operation mode may still contain error detec
66. 5 5 43 5 23 PST DDATA Specification for Supervisor Mode Instructions 5 46 6 1 SIM REGIST s rere nre ee ete rie ne ere e derent 6 3 6 2 MBAR Field Descriptions 6 5 6 3 RSR Field Descriptions nne reete rete pene eee Len eaaet 6 6 6 4 SYPCR Field Descriptions 6 8 6 5 PELIPLASettIN ES iroi 6 10 6 6 MPARK Field 5 6 11 7 1 PLLCR Field 1 7 3 7 2 PLE Module Input SIgnals rhetor etta oio tetas 7 3 7 3 PLL Module Output Signals eese nre 7 4 8 1 Interface Memory Map E EEEE ESS 8 6 8 2 PC Address Register Field 8 6 8 3 IFDR Field Descriptions reete treten sso feta oso diaeta sedo 8 7 8 4 PCR Field Descriptions cem o ete eee 8 8 8 5 PSR Field Descriptions ensinarnos 8 9 9 1 Interrupt Controller RegistetS erret rrt rtr terrae rto aee 9 2 9 2 Interrupt Control Registers 9 2 9 3 ICRz Field Descriptions ire tn tote tenons anuo ee ona ana o Eno donnus 9 3 9 4 Interrupt Priority SCHEMEC c ssscescesesesecesasscosesscosasscesesscesasscosesecesesesocesecesesesesesecesest 9 4
67. 7 4 Timing Relationships The MCF5307 uses CLKIN and BCLKO which is generated by the PLL and may be used as the bus timing reference for external devices The MCF5307 BCLKO frequency can be 1 2 1 3 or 1 4 the processor clock In this document bus timings are referenced from BCLKO Furthermore depending on the user configuration the BCLKO to processor clock ratio may differ from the CLKIN to processor clock ratio 7 4 1 PCLK PSTCLK and BCLKO Figure 7 3 shows the frequency relationships between PCLK PSTCLK CLKIN and the three possible versions of BCLKO This figure does not show the skew between CLKIN and PCLK PSTCLK and BCLKO PSTCLK is equal to frequency of PCLK Similarly the skew between PCLK and BCLKO is unspecified 7 4 MCF5307 User s Manual M woronoLA Timing Relationships 1 1 BCLKO 2 NEL EE m EM BCLKO 3 C GEI BCLKO 4 N N 1 1 1 1 NOTE The clock signals are shown with edges aligned to show frequency relationships only Actual signal edges have some skew between them Figure 7 3 CLKIN PCLK PSTCLK and BCLKO Timing 7 4 2 RSTI Timing Figure 7 4 shows PLL timing during reset As shown RSTI must be asserted for at least 80 CLKIN cycles to give the MCF5307 time to begin its initialization sequence At this time the configuration pins should be asserted D 3 2 for FREQ 1 0 and D 1 0 for DIVIDE 1 0 meeting the minimum setup and hold times to RSTI gi
68. 7 6 3 2 1 0 Field COS DB FFULL RxRDY TxRDY Reset 0000_0000 R W Read only for status write only for mask Address MBAR 0x1D4 UISRO 0x214 UISR1 MBAR 0x1D4 UIMRO 0x214 UIMR1 Figure 14 11 UART Interrupt Status Mask Registers UISRn UIMRn Table 14 9 describes UISRz UIMRn fields M MOTOROLA Chapter 14 UART Modules 14 13 Register Descriptions Table 14 9 UISRn UIMRn Field Descriptions Bits Name Description 7 COS Change of state 0 UIPCRn COS is not selected 1 Change of state occurred on CTS and was programmed in UACRn IEC to cause an interrupt 6 3 Reserved should be cleared 2 DB Delta break 0 No new break change condition to report Section 14 3 5 UART Command Registers UCRn describes the RESET BREAK CHANGE INTERRUPT command 1 The receiver detected the beginning or end of a received break 1 FFULL RxRDY receiver ready if UMR1n FFULL RxRDY 0 FIFO full FFULL if UMR1n FFULL RXRDY RxRDY 1 Duplicate of USRn FFULL RxRDY If FFULL is enabled for UARTO or UART1 DMA channels 2 or 3 are respectively interrupted when the FIFO is full 0 TxRDY Transmitter ready This bit is the duplication of USRn TxRDY 0 The transmitter holding register was loaded by the CPU or the transmitter is disabled Characters loaded into the transmitter holding register when TXRDY 0 are not sent 1 The transmitter holding register is empty and ready to be loaded
69. A at Reset B after Invalidation C and D Loading Pattern 4 10 4 5 Caching Operation seiniin ieies irii aseisiin seesi 4 11 4 6 Write Miss in Copyback Mode 4 16 4 7 Cache Bou 4 20 4 8 Cache Control Register 4 21 4 9 Access Control Register Format nnne 4 23 4 10 AN FOMA successes 4 24 4 11 Cache Line State Diagram Copyback Mode sse 4 26 4 12 Cache Line State Diagram Write Through Mode sse 4 26 5 1 Processor Debug Module Interface esee 5 1 5 2 T 5 3 5 3 Example JMP Instruction Output on PST DDATA sess 5 5 5 4 Debug Programming Model 5 6 5 5 Address Attribute Trigger Register 5 7 5 6 Address Breakpoint Registers ABLR 5 9 5 7 BDM Address Attribute Register BAAR eese nennen 5 9 5 8 Configuration Status Register 5 10 5 0 Data Breakpoint Mask Registers DBR and DBMRB esee 5 12 M MOTOROLA Illustrations Figure Number 5 10 5 11 5 12 5 13 5 14 5 15 5 16 5 17 5 19 5 18 5 21 5 20 5 23 5 22 5 24 5 25 5 26 5 27 5 28 5 29 5 31 5 30 5 33 5 32 5 35 5 34 5 37 5 36 5 39 5 38 5 41 5 40
70. Address MBAR 0 1 4 UCSRO 0x204 UCSR1 Figure 14 5 UART Clock Select Register UCSRn 14 8 MCF5307 User s Manual M woronoLA Register Descriptions Table 14 5 describes UCSRn fields Table 14 5 UCSRn Field Descriptions Bits Name Description 7 4 RCS Receiver clock select Selects the clock source for the receiver channel 1101 Prescaled BCLKO 1110 TIN divided by 16 1111 TIN 3 0 TCS Transmitter clock select Selects the clock source for the transmitter channel 1101 Prescaled BCLKO 1110 TIN divided by 16 1111 TIN 14 3 5 UART Command Registers UCRn The UART command registers UCRn Figure 14 6 supply commands to the UART Only multiple commands that do not conflict can be specified in a single write to a UCRz For example RESET TRANSMITTER and ENABLE TRANSMITTER cannot be specified in one command 7 6 4 3 2 1 0 Field MISC TC RC Reset 0000 0000 R W Write only Address MBAR 0x1C8 0x208 Figure 14 6 UART Command Register UCRn Table 14 6 describes UCRz fields and commands Examples in Section 14 5 2 Transmitter and Receiver Operating Modes show how these commands are used Table 14 6 UCRn Field Descriptions Bits Value Command Description 7 Reserved should be cleared M MOTOROLA Chapter 14 UART Modules 14 9 Register Descriptions Table 14 6 UCRn Field Descriptions Continued
71. Address Pin Assignment eese 17 13 17 14 CEKIN Frequency 17 13 17 15 BCLKO PSTCLK Divide Ratios 17 14 17 16 Processor Status Signal Encodings esses 17 19 18 1 ColdFire Bus Signal Summary sese 18 1 18 2 Bus Cycle Size Encoding ees oe eee ete ti re eniin tea o eei og aea tea doge 18 3 18 3 Accesses by Matches in CSCRs and 18 5 18 4 Bus mee eere eei tede 18 6 18 5 Allowable Line Access Patterns 18 12 18 6 MCF5307 Arbitration Protocol States 18 20 18 7 ColdFire Bus Arbitration Signal Summary sess 18 21 18 8 Cycles for Basic No Wait State External Master 18 23 18 9 Cycles for External Master Burst Line Access to 32 Bit 18 24 18 10 5307 Two Wire Bus Arbitration Protocol Transition Conditions 18 28 18 11 Three Wire Bus Arbitration Protocol Transition Conditions 18 32 18 12 Data Pin Configuration 18 35 19 1 JTAG Pin 19 3 19 2 JT Xeditiibob Ir 19 5 19 3 IDCODE Bit Assignments eese nennen nnne 19 6 19 4 Boundary Scan Bit 01 19 7 20 1 Absolute Maximum Ratings 20 1 20 2 Operating Temperatures
72. Channel 0 Channel 1 Channel 2 Channel 3 SARO SAR1 SAR2 SAR3 DARO DAR1 DAR2 DAR3 Interrupts External BCRO BCR1 BCR2 BCR3 Requests DCRO DCR1 DCR2 DCR3 DSRO DSR1 DSR2 DSR3 Channel A Channel Requests Attributes Channel Y Enables External Bus Address MUX External Bus Size MUX Current Master Attributes Control Arbitration Y a Control Data Path lt Interface Bus Data Path Control Read Bus Data Write Bus Data Registered Bus Signals Figure 12 1 DMA Signal Diagram M Chapter 12 DMA Controller Module 12 1 DMA Signal Description 12 1 1 DMA Module Features The DMA controller module features are as follows Four fully independent programmable DMA controller channels bus modules e Auto alignment feature for source or destination accesses e Dual and single address transfers Two external request pins DREQ 1 0 provided for channels 1 and 0 Channel arbitration on transfer boundaries Data transfers in 8 16 32 or 128 bit blocks using a 16 byte buffer e Continuous mode and cycle steal transfers Independent transfer widths for source and destination Independent source and destination address registers e Data transfer can occur in as few as two clocks 12 2 DMA Signal Description Table 12 1 briefly describes the DMA module signals that provide handshake control for either a source or destination external device Table 12 1 DMA Si
73. ColdFire Core Hardware Multiply Accumulate MAC Unit Local Memory Debug Support Part Il System Integration Module SIM SIM Overview Phase Locked Loop PLL IC Module Interrupt Controller Chip Select Module Synchronous Asynchronous DRAM Controller Module Part III Peripheral Module DMA Controller Module Timer Module UART Modules Parallel Port General Purpose I O Part IV Hardware Interface Mechanical Data Signal Descriptions Bus Operation IEEE 1149 1 Test Access Port JTAG Electrical Specifications Appendix Memory Map Glossary of Terms and Abbreviations Index Part Part Il ES Part III ps A ENS Eu mr Part IV lt gt r i9 umm um Ol IM Ne IND Part Part Il E ENS E Part 111 gt EM ON B Part IV N lt gt ES ES ES E Q Z Overview Part MCF5307 Processor Core ColdFire Core Hardware Multiply Accumulate MAC Unit Local Memory Debug Support Part Il System Integration Module SIM SIM Overview Phase Locked Loop PLL I C Module Interrupt Controller Chip Select Module Synchronous Asynchronous DRAM Controller Module Part III Peripheral Module DMA Controller Module Timer Module
74. DAR2 p 12 7 0x388 DMA control register 2 DCR2 p 12 8 0x38C Byte count register 2 BCR24BIT 0 Reserved 0x38C Reserved Byte count register 2 BCR24BIT 1 BCR2 p 12 7 0x390 DMA status register 2 Reserved DSR2 p 12 10 0x394 DMA interrupt vector Reserved register 2 DIVR2 p 12 11 M woronoLA Chapter 12 DMA Controller Module 12 5 DMA Controller Module Programming Model Table 12 2 Memory Map for DMA Controller Module Registers Continued Channel Offset 31 24 23 16 15 8 7 0 3 0x3C0 Source address register p 12 6 0x3C4 Destination address register 3 DAR3 p 12 7 0x3C8 DMA control register 3 DCR3 p 12 8 Ox3CC Byte count register BCR24BIT 0 1 Reserved 0x3CC Reserved Byte count register 3 BCR24BIT 1 BCR3 p 12 7 Ox3DO DMA status register 3 Reserved DSR3 p 12 10 0x3D4 DMA interrupt vector Reserved register 3 DIVR3 p 12 11 On the original MCF5307 mask set H55J the BCR of the DMA channels can accommodate only 16 bits However because the revised MCF5307 supports a 24 bit byte count range the position of the BCR in the memory map depends on whether a 16 or 24 bit byte counter is selected The 24 bit byte count can be selected by setting BCR24BIT 1 making DCR AT available The AT bit selects whether DMA channels assert acknowledge d
75. In either mode the MCF5307 bus arbiter operates synchronously and transitions between states on the rising edge of BCLKO Table 18 6 shows the four arbitration states the MCF5307 can be in during bus operation Table 18 6 MCF5307 Arbitration Protocol States State Master Bus BD Description Reset None Not Negated The MCF5307 enters reset state from any other state when RSTI or driven software watchdog reset is asserted If both are negated the MCF5307 enters implicit or external device mastership state depending on BG Implicit MCF5307 Not Negated The MCF5307 is bus master BG input is asserted but is not ready to master driven begin a bus cycle It continues to three state the bus until an internal bus request 18 20 MCF5307 User s Manual M woronoLA General Operation of External Master Transfers Table 18 6 MCF5307 Arbitration Protocol States Continued State Master Bus BD Description Explicit MCF5307 Driven Asserted The MCF5307 is explicit bus master when BG is asserted and at least master one bus cycle has been initiated It asserts BD and retains explicit mastership until BG is negated even if no active bus cycles are executed It releases the bus at the end of the current bus cycle then negates BD and three states the bus signals External External Not Negated An external device is bus master BG negated to MCF5307 The master driven MCF5307 can assert OE
76. Internal Counter Reset 1 Figure 8 4 Synchronized Clock SCL 8 4 3 Handshaking The clock synchronization mechanism can be used as a handshake in data transfers Slave devices can hold SCL low after completing one byte transfer 9 bits In such a case the clock mechanism halts the bus clock and forces the master clock into wait states until the slave releases SCL 8 4 4 Clock Stretching Slaves can use the clock synchronization mechanism to slow down the transfer bit rate After the master has driven SCL low the slave can drive SCL low for the required period and then release it If the slave SCL low period is longer than the master SCL low period the resulting SCL bus signal low period is stretched M MOTOROLA Chapter 8 Module 8 5 Programming Model 8 5 Programming Model Table 8 1 lists the configuration registers used in the interface Table 8 1 Interface Memory Map Op 31 24 23 16 15 8 7 0 0x280 12 address register IADR p 8 6 Reserved 0x284 C frequency divider register IFDR p 8 7 Reserved 0x288 12 control register 12 p 8 8 Reserved 0x28C 2 status register I2SR p 8 9 Reserved 0x290 12 data I O register I2DR p 8 10 Reserved NOTE External masters cannot access the MCF5307 s on chip memories or MBAR but can access any module register 8 5 1 I C Address Register IADR The IADR holds the address
77. MCF5307 connecting to an external device using the two wire mode The MCF5307 BG input is connected to the HOLDREQ output of the external device the MCF5307 BD output is connected to the HOLDACK input of the external device Because the external device controls the state of HOLDREQ it controls when the MCF5307 is granted the bus giving the MCF5307 lower priority BG lt HOLDREQ BD gt HOLDACK BR 31 0 gt A 81 0 D 31 0 1 D 31 0 IS TS RW gt RAV 514 1 0 SIZ 1 0 MCF5307 YYYY 1 External Bus Master To from external memory and control Figure 18 26 MCF5307 Two Wire Mode Bus Arbitration Interface When the external device is not using the bus it negates HOLDREQ driving BG low and granting the bus to the MCF5307 When the MCF5307 has an internal bus request pending and BG is low the MCF5307 drives BD low negating HOLDACK to the external device When the external bus device needs the external bus it asserts HOLDREQ driving BG high requesting the MCF5307 to release the bus If BG is negated while a bus cycle is in progress the MCF5307 releases the bus at the completion of the bus cycle Note that the MCF5307 considers the individual transfers of a burst or burst inhibited access to be a single bus cycle and does not release the bus until the last transfer of the series completes When the bus has been gran
78. Miscellaneous Instruction Execution Times esee nennen 2 45 General Branch Instruction Execution Times eene 2 46 Bcc Instruction Execution 4 2 47 Exception Vector 1 2 48 Format Field Encoding 2 49 Fault Status Encoding 2 50 AG ARIES can 2 50 MAC Instruction Summary 3 4 Two Operand MAC Instruction Execution Times sess 3 5 MAC Move Instruction Execution Times esee nennen 3 6 RAMBAR Field Description 4 3 Examples of Typical RAMBAR Settings 4 6 Valid and Modified Bit Settings 4 8 CACR Field Desorption i eere rire ta roe eere teta eee e teneat 4 21 Field Descriptions etre tr trente trei enn Een done i 4 23 Cache Line State Transitions eese 4 27 Cache Line State Transitions Current State 9 4 28 Cache Line State Transitions Current State Valid esses 4 28 Cache Line State Transitions Current State Modified sss 4 29 Debug Module Signals 5 2 M MOTOROLA Tables XXV TABLES Table Number Hae Number 5 2 Proc
79. No address multiplexing Some implementations require external multiplexing For example when linear addressing is required the DRAM should not multiplex addresses on DRAM accesses 0 The DRAM controller multiplexes the external address bus to provide column addresses 1 The DRAM controller does not multiplex the external address bus to provide column addresses 12 11 RRA Refresh RAS asserted Determines how long RAS is asserted during a refresh operation 00 2 clocks 01 3 clocks 10 4 clocks 11 5 clocks 10 9 RRP Refresh RAS precharge Controls how many clocks RAS is precharged after a refresh operation before accesses are allowed to DRAM 00 1 clock 01 2 clocks 10 3 clocks 11 4 clocks 8 0 RC Refresh count Controls refresh frequency The number of bus clocks between refresh cycles is RC 1 16 Refresh can range from 16 8192 bus clocks to accommodate both standard and low power DRAMS with bus clock operation from less than 2 MHz to greater than 50 MHz The following example calculates RC for an auto refresh period for 4096 rows to receive 64 mS of refresh every 15 625 us for each row 625 bus clocks at 40 MHz of bus clocks 625 RC field 1 16 RC 625 bus clocks 16 1 38 06 which rounds to 38 therefore RC 0x26 11 3 2 2 DRAM Address and Control Registers DACRO DACR1 DACRO and DACRI Figure 11 3 contain the base address compare value and the control bits for memory blocks 0 and 1 Address and timing
80. Provides a way to invert the logical sense of all the data breakpoint comparators This can develop a trigger based on the occurrence of a data value other than the DBR contents 20 18 EAx Enable address bits Setting an EA bit enables the corresponding address breakpoint Clearing all three 4 2 bits disables the breakpoint 20 4 EAI Enable address breakpoint inverted Breakpoint is based outside the range between ABLR and ABHR 19 3 EAR Enable address breakpoint range The breakpoint is based on the inclusive range defined by ABLR and ABHR 18 2 EAL Enable address breakpoint low The breakpoint is based on the address in the ABLR 17A EPC Enable PC breakpoint If set this bit enables the PC breakpoint 16 0 PCI Breakpoint invert If set this bit allows execution outside a given region as defined by PBR and PBMR to enable a trigger If cleared the PC breakpoint is defined within the region defined by PBR and PBMR 5 5 Background Debug Mode BDM The ColdFire Family implements a low level system debugger in the microprocessor hardware Communication with the development system is handled through a dedicated high speed serial command interface The ColdFire architecture implements the BDM controller in a dedicated hardware module Although some BDM operations such as CPU register accesses require the CPU to be halted other BDM commands such as memory accesses can be executed while the processor is running 5 5 1 CPU Ha
81. SA S S S S S S SN 7 7 D 7 0 latched RSTO Figure 18 34 Software Watchdog Reset Timing During the software watchdog reset period all signals that can be are driven to a high impedance state all those that cannot be are negated When RSTO negates bus signals remain in a high impedance state until the MCF5307 is granted the bus and the ColdFire core begins the first bus cycle for reset exception processing 18 36 MCF5307 User s Manual M MOTOROLA Chapter 19 IEEE 1149 1 Test Access Port JTAG This chapter describes configuration and operation of the MCF5307 JTAG test implementation It describes the use of JTAG instructions and provides information on how to disable JTAG functionality 19 1 Overview The MCF5307 dedicated user accessible test logic is fully compliant with the publication Standard Test Access Port and Boundary Scan Architecture IEEE Standard 1149 1 Use the following description in conjunction with the supporting IEEE document listed above This section includes the description of those chip specific items that the IEEE standard requires as well as those items specific to the MCF5307 implementation The MCF5307 JTAG test architecture supports circuit board test strategies based on the IEEE standard This architecture provides
82. SDRAM A1 A2 A4 A5 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 Pins 11 24 MCF5307 User s Manual M woronoLA Synchronous Operation Table 11 19 MCF5307 to SDRAM Interface 8 Bit Port 13 Column Address Lines MCF5307 A17 A16 A15 A14 A13 A12 A11 A10 A9 A19 A21 A23 A25 A26 A27 A28 A29 A30 A31 Pins Row 17 16 15 14 13 12 11 10 9 19 21 23 25 26 27 28 29 30 31 Column 0 1 2 4 5 7 18 20 22 24 SDRAM 1 a2 AA AS A7 AB A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 Pins Table 11 20 MCF5307 to SDRAM Interface 16 Bit Port 8 Column Address Lines MCF5307 A16 A15 A14 A13 A12 A11 A10 A9 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 Pins Row 16 15 14 13 12 11 10 9 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Column 1 2 3 4 5 6 7 8 SDRAM A0 A1 A2 A4 A7 AB AQ A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20
83. Select the receiver and transmitter clock Use timer as source if required UMR1n If preferred program operation of receiver ready to send RxRTS bit Select receiver ready or FIFO full notification RXRDY FFULL bit Select character or block error mode ERR bit Select parity mode and type PM and PT bits Select number of bits per character B Cx bits UMR2n Select the mode of operation CMx bits If preferred program operation of transmitter ready to send TxRTS If preferred program operation of clear to send TxCTS bit Select stop bit length SBx bits UCR M woronoLA Chapter 14 UART Modules 14 29 Operation ENABLE ANY ERRORS N ENABLE RECEIVER CHK1 CALL CHCHK ASSERT REQUEST TO SEND SERIAL MODULE SINIT INITIATE CHANNEL INTERRUPTS SAVE CHANNEL SINITR STATUS RETURN Figure 14 27 UART Mode Programming Flowchart Sheet 1 of 5 14 30 MCF5307 User s Manual M woronoLA Operation CHCHK PLACE CHANNEL IN LOCAL LOOPBACK MODE ENABLE TRANSMITTER CLEAR STATUS WORD IS TRANSMITTER READY WAITED TOO LONG SET TRANSMITTER NEVER READY FLAG SNDCHR SEND CHARACTER TO TRANSMITTER RXCHK lt WAITED SET RECEIVER T00 NEVER READY FLAG Figure 14 27 UART Mode Programming Flowchart Sheet 2 of 5 M MOTOROLA Chapter 14 UART Modules
84. System Integration P bi BCLKO Module SIM Interrupt Control a ll acl i Interrupt Logic Generation External clock TIN Controller Figure 14 1 Simplified Block Diagram The serial communication channel provides a full duplex asynchronous synchronous receiver and transmitter deriving an operating frequency from BCLKO or an external clock using the timer pin The transmitter converts parallel data from the CPU to a serial bit stream inserting appropriate start stop and parity bits It outputs the resulting stream on the channel transmitter serial data output TxD See Section 14 5 2 1 Transmitting The receiver converts serial data from the channel receiver serial data input RxD to parallel format checks for a start stop and parity bits or break conditions and transfers the assembled character onto the bus during read operations The receiver may be polled or interrupt driven See Section 14 5 2 2 Receiver M MOTOROLA Chapter 14 UART Modules 14 1 Serial Module Overview 14 2 Serial Module Overview The MCF5307 contains two independent UART modules whose features are as follows Each can be clocked by BCLKO eliminating a need for an external crystal e Full duplex asynchronous synchronous receiver transmitter channel e Quadruple buffered receiver e Double buffered transmitter Independently programmable receiver and transmitter clock sources Programmable data format 5 8 data bits plus parity
85. The ColdFire debug architecture supports the creation of single or double level triggers TDR 15 0 Level 2 trigger PC condition amp Address range amp Data condition 1 Level 2 trigger PC condition Address range amp Data condition TDR 14 0 Level 1 trigger PC condition amp Address range amp Data condition 1 Level 1 trigger PC condition Address range amp Data condition 2913 EBL Enable breakpoint Global enable for the breakpoint trigger Setting TDR EBL enables a breakpoint trigger Clearing it disables all breakpoints M MOTOROLA Chapter 5 Debug Support 5 15 Background Debug Mode BDM Table 5 14 TDR Field Descriptions Continued Bits Name Description 28 22 EDx Setting an EDx bit enables the corresponding data breakpoint condition based on the size and placement 12 6 on the processor s local data bus Clearing all EDx bits disables data breakpoints 28 12 EDLW Data longword Entire processor s local data bus 27 11 EDWL Lower data word 26 10 EDWU Upper data word 25 9 EDLL Lower lower data byte Low order byte of the low order word 24 8 EDLM Lower middle data byte High order byte of the low order word 23 7 EDUM Upper middle data byte Low order byte of the high order word 22 6 EDUU Upper upper data byte High order byte of the high order word 21 5 DI Data breakpoint invert
86. The following example shows how to set the MBAR to location 0x1000 0000 using the DO register Setting MBAR V validates the MBAR location This example assumes all accesses are valid move 1 0 10000001 movec DO MBAR 6 2 3 Reset Status Register RSR The reset status register RSR Figure 6 3 contains two status bits HRST and SWTR Reset control logic sets one of the bits depending on whether the last reset was caused by an external device asserting RSTI HRST 1 or by the software watchdog timer SWTR 1 Only one RSR bit can be set at any time If a reset occurs reset control logic sets only the bit that indicates the cause of reset 7 6 5 4 0 Field HRST SWTR Reset 1 0 0 1 0 0_0000 R W Read Write Address MBAR 0x000 Figure 6 3 Reset Status Register RSR M MOTOROLA Chapter 6 SIM Overview 6 5 Programming Model Table 6 3 describes RSR fields Table 6 3 RSR Field Descriptions Bits Name Description 7 HRST Hardware or system reset 1 An external device driving RSTI caused the last reset Assertion of reset by an external device causes the core processor to take a reset exception All registers in internal peripherals and the SIM are reset 6 Reserved should be cleared 5 SWTR Software watchdog timer reset 1 The last reset was caused by the software watchdog timer If SYPCR SWRI 1 and the software watchdog timer times out a hardware reset occurs
87. Word if read 1 0 0 1 if write 3 2 0 2 if write 2 1 Each timing entry is presented as C r w described as follows C is the number of processor clock cycles including all applicable operand fetches and writes as well as all internal core cycles required to complete the instruction execution r w is the number of operand reads r and writes w required by the instruction An operation performing a read modify write function is denoted as 1 1 2 7 1 MOVE Instruction Execution Times The execution times for the MOVE B W L instructions are shown in the next tables Table 2 12 shows the timing for the other generic move operations NOTE For all tables in this chapter the execution time of any instruction using the PC relative effective addressing modes is equivalent to the time using comparable An relative mode ET with ea ET with ea d16 PC equals ET with lt ea gt 416 d8 PC Xi SF equals ET with lt ea gt d8 An Xi SF The nomenclature xxx wl refers to both forms of absolute addressing xxx w and xxx l M MOTOROLA Chapter 2 ColdFire Core 2 41 Instruction Timing Table 2 10 lists execution times for MOVE B W instructions Table 2 10 Move Byte and Word Execution Times Destination Source Rx Ax d16 Ax d8 Ax Xi SF xxx wl Dy 1 0 0 1 0 1 1 0 1 1 0 1 1 0 1 2 0
88. describes the MCF5307 cache implementation including organization configuration and coherency It describes cache operations and how the cache interacts with other memory structures Chapter 5 Debug Support describes the Revision C enhanced hardware debug support in the MCF5307 This revision of the ColdFire debug architecture encompasses earlier revisions Part II System Integration Module SIM describes the system integration module which provides overall control of the bus and serves as the interface between the ColdFire core processor complex and internal peripheral devices It includes a general description of the SIM and individual chapters that describe components of the SIM such as the phase lock loop PLL timing source interrupt controller for peripherals configuration and operation of chip selects and the SDRAM controller Chapter 6 SIM Overview describes the SIM programming model bus arbitration and system protection functions for the MCF5307 Chapter 7 Phase Locked Loop PLL describes configuration and operation of the PLL module It describes in detail the registers and signals that support the PLL implementation Chapter 8 Module describes 5307 module including protocol clock synchronization and the registers in the PC programing model It also provides extensive programming examples Chapter 9 Interrupt Controller describ
89. except for the PLL reset mode selects such as PP RESET SEL or chip select settings should not change 5 SWP Software watchdog prescaler This bit interacts with SYPCR SWT 0 Software watchdog timer clock not prescaled 1 Software watchdog timer clock prescaled by 8192 4 3 SWT Software watchdog timing delay SWT and SWP select the timeout period for the watchdog timer At system reset the software watchdog timer is set to the minimum timeout period SWP 0 SWP 1 00 29 system frequency 00 2 system frequency 01 211 frequency 01 2 system frequency 10 2 3 system frequency 10 2 6 system frequency 11 2 5 system frequency 11 2 8 system frequency Note that if SWP and SWT are modified to select a new software timeout the software service sequence must be performed 0x55 followed by OxAA written to the SWSR before the new timeout period takes effect 6 8 MCF5307 User s Manual M woronoLA Programming Model Table 6 4 SYPCR Field Descriptions Continued Bits Name Description 2 SWTA Software watchdog transfer acknowledge enable 0 SWTA transfer acknowledge disabled 1 SWTA asserts transfer acknowledge enabled After one timeout period of the unacknowledged assertion of the software watchdog timer interrupt the software watchdog transfer acknowledge asserts which allows the watchdog timer to terminate a bus cycle and allow the IACK to occur 1 SWTAVAL Software watchdog transfer
90. respectively Dn Any data register n example D5 is data register 5 Dy Dx Source and destination data registers respectively Rc Any control register example VBR is the vector base register Rm MAC registers ACC MAC MASK Rn Any address or data register Rw Destination register w used for MAC instructions only Ry Rx Any source and destination registers respectively Xi index register i can be an address or data register Ai Di Register Names ACC MAC accumulator register CCR Condition code register lower byte of SR MACSR MAC status register MASK MAC mask register PC Program counter SR Status register Port Name DDATA Debug data port PST Processor status port Miscellaneous Operands lt data gt Immediate data following the 16 bit operation word of the instruction lt ea gt Effective address lt ea gt y lt ea gt x Source and destination effective addresses respectively label Assembly language program label list List of registers for MOVEM instruction example 03 00 shift Shift operation shift left lt lt shift right gt gt size Operand data size byte B word W longword L uc Unified cache lt vector gt Identifies the 4 bit vector number for trap instructions lt gt identifies an indirect data address referencing memory lt XXX gt identifies an absolute address referencing memory dn Signal displacement value n bits wide example d16 is a 16 bit displacement SF Scale factor x1 x2 x4 for
91. 0 mac w Ry Rx ea Rw 3 1 0 3 1 0 3 1 0 3 1 0 2 44 MCF5307 User s Manual M woronoLA Instruction Timing Table 2 14 Two Operand Instruction Execution Times Continued Effective Address Opcode ea Rn An An An d16 An d amp An Xi SF xxx wl lt gt mac Ry Rx ea Rw 5 1 0 5 1 0 5 1 0 5 1 0 moveq imm Dx 1 0 0 msac w Ry Rx ea Rw 3 1 0 3 1 0 3 1 0 3 1 0 msac Ry Rx ea Rw 5 1 0 5 1 0 5 1 0 5 1 0 muls w ea Dx 3 0 0 6 1 0 6 1 0 6 1 0 6 1 0 7 1 0 6 1 0 3 0 0 mulu w ea Dx 3 0 0 6 1 0 6 1 0 6 1 0 6 1 0 7 1 0 6 1 0 3 0 0 muls lt ea gt Dx 5 0 0 8 1 0 8 1 0 8 1 0 8 1 0 mulu lt ea gt Dx 5 0 0 8 1 0 8 1 0 8 1 0 8 1 0 or lt ea gt Rx 1 0 0 4 1 0 4 1 0 4 1 0 4 1 0 5 1 0 4 1 0 1 0 0 or Dy lt ea gt 4 14 4 1 1 4 1 1 4 1 1 5 1 1 4 1 1 orl imm Dx 1 0 0 rems lt ea gt Dx 35 0 0 35 1 0 35 1 0 35 1 0 35 1 0 remu lt ea gt Dx 35 0 0 35 1 0 35 1 0 35 1 0 35 1 0 sub lt ea gt Rx 1 0 0 4 1 0 4 1 0 4 1 0 4 1 0 5 1 0 4 1 0 1 0 0 sub Dy lt ea gt 4 14 4 1 1 4 1 1 4 1 1 5 1 1 4 1 1 subi l imm Dx
92. 0 1 ext w Dx PST 0 1 extb l Dx PST 0 1 jmp lt gt PST 0x5 PST Ox9AB DD target address jsr ea x PST 0x5 PST 0 9 DD target address PST 0xB DD destination operand lea lt gt PST 0 1 ink w Ay imm PST 0x1 PST DD destination operand 51 1 Dy imm Dx PST 0 1 srl Dy imm Dx PST 0 1 1 PST 0 1 1 Ry Rx PST 0 1 mac Ry Rx ea Rw PST 0x1 PST 0 DD source operand mac w PST 0 1 mac w Ry Rx PST 0 1 mac w Ry Rx ea Rw PST 0x1 PST 0xB DD source operand move b ea y cea x PST 0x1 PST 0x8 DD source PST 0x8 DD destination move ea y cea x PST 0x1 PST DD source PST 0xB DD destination move lt ea gt y ACC PST 0x1 move lt ea gt y MACSR PST 0x1 move lt ea gt y MASK PST 0 1 move ACC Rx PST 0 1 move MACSR CCR PST 0 1 move MACSR Rx PST 0 1 move MASK Rx PST 0x1 move w ea y cea x PST 0x1 PST 0x9 DD source PST 0x9 DD destination move w CCR Dx PST 0x1 move w Dy imm CCR PST 0x1 5 44 MCF5307 User s Manual M Processor Status DDATA Definition Table 5 22 PST DDATA Specification for User Mode Instructions Continued Instruction Operand Syntax PST DDATA movem list
93. 0 02913 0 04369 0 05825 20 14 0 48934 0 734 0 97867 0 03058 0 04588 0 06117 21 15 0 51264 0 76896 1 02527 0 03204 0 04806 0 06408 22 16 0 53594 0 80391 1 07188 0 0335 0 05024 0 06699 23 17 0 55924 0 83886 1 11848 0 03495 0 05243 0 06991 24 18 0 58254 0 87381 1 16508 0 03641 0 05461 0 07282 25 19 0 60584 0 90877 1 21169 0 03787 0 0568 0 07573 26 1A 0 62915 0 94372 1 25829 0 03932 0 05898 0 07864 27 1B 0 65245 0 97867 1 30489 0 04078 0 06117 0 08156 28 1C 0 67575 1 01362 1 3515 0 04223 0 06335 0 08447 29 1D 0 69905 1 04858 1 3981 0 04369 0 06554 0 08738 30 1E 0 72235 1 08353 1 4447 0 04515 0 06772 0 09029 31 1F 0 74565 1 11848 1 49131 0 0466 0 06991 0 09321 32 20 0 76896 1 15343 1 53791 0 04806 0 07209 0 09612 33 21 0 79226 1 18839 1 58451 0 04952 0 07427 0 09903 34 22 0 81556 1 22334 1 63112 0 05097 0 07646 0 10194 35 23 0 83886 1 25829 1 67772 0 05243 0 07864 0 10486 36 24 0 86216 1 29324 1 72432 0 05389 0 08083 0 10777 37 25 0 88546 1 3282 1 77093 0 05534 0 08301 0 11068 38 26 0 90877 1 36315 1 81753 0 0568 0 0852 0 1136 39 27 0 93207 1 3981 1 86414 0 05825 0 08738 0 11651 40 28 0 95537 1 43305 1 91074 0 05971 0 08957 0 11942 41 29 0 97867 1 46801 1 95734 0 06117 0 09175 0 122338 42 2A 1 00197 1 50296 2 00395 0 06262 0 09393 0 12525 43 2B 1 02527 1 53791 2 05055 0 06408 0 09612 0 12816 44 2C 1 04858 1 57286 2 09715 0 06554 0 0983 0 13107 45 2D 1 07188 1 60782 2 14376 0 06699 0 10049 0 13398 13 8 MCF5307 User s Manual M MOTOROLA Calculati
94. 0xD and exit 0x7 5 6 2 Concurrent BDM and Processor Operation The debug module supports concurrent operation of both the processor and most BDM commands BDM commands may be executed while the processor is running except those following operations that access processor memory registers M MOTOROLA Chapter 5 Debug Support 5 41 Motorola Recommended BDM Pinout e Read write address and data registers e Read write control registers For BDM commands that access memory the debug module requests the processor s local bus The processor responds by stalling the instruction fetch pipeline and waiting for current bus activity to complete before freeing the local bus for the debug module to perform its access After the debug module bus cycle the processor reclaims the bus Breakpoint registers must be carefully configured in a development system if the processor is executing The debug module contains no hardware interlocks so TDR should be disabled while breakpoint registers are loaded after which TDR can be written to define the exact trigger This prevents spurious breakpoint triggers Because there are no hardware interlocks in the debug unit no BDM operations are allowed while the CPU is writing the debug s registers DSCLK must be inactive 5 7 Motorola Recommended BDM Pinout The ColdFire BDM connector Figure 5 44 is a 26 pin Berg connector arranged 2 x 13 Developer reserved 1 2 GND 3
95. 1 1 0 1 Ay 1 0 0 1 0 1 1 0 1 1 0 1 1 0 1 2 0 1 1 0 1 Ay 4 1 0 4 1 1 4 1 1 4 1 1 4 1 1 5 1 1 4 1 1 4 1 0 4 1 1 4 1 1 4 1 1 4 1 1 5 1 1 4 1 1 4 1 0 4 1 1 4 1 1 4 1 1 4 1 1 5 1 1 4 1 1 916 4 1 0 4 1 1 4 1 1 4 1 1 4 1 1 d8 Ay Xi SF 5 1 0 5 1 1 5 1 1 5 1 1 4 1 0 4 1 1 4 1 1 4 1 1 E 4 1 0 4 1 4 1 1 4 1 1 d16 PC 4 1 0 4 1 1 4 1 1 4 1 1 4 1 1 ur Z d8 PC Xi SF 5 1 0 5 1 1 5 1 1 5 1 1 lt gt 1 0 0 2 0 1 2 0 1 2 0 1 Table 2 11 lists timings for MOVE L Table 2 11 Move Long Execution Times Destination Source Rx Ax Ax Ax d16 Ax d8 Ax Xi SF xxx wl Dy 1 0 0 1 0 1 1 0 1 1 0 1 1 0 1 2 0 1 1 0 1 Ay 1 0 0 1 0 1 1 0 1 1 0 1 1 0 1 2 0 1 1 0 1 Ay 3 1 0 3 1 1 3 1 1 3 1 1 3 1 1 4 1 1 3 1 1 3 1 0 3 1 1 3 1 1 4 1 1 3 1 1 Ay 3 1 0 3 1 1 3 1 1 3 1 1 3 1 1 4 1 1 3 1 1 916 3 1 0 3 1 1 3 1 1 3 1 1 3 1 1 d8 Ay Xi SF 4 1 0 4 1 1 4 1 1 4 1 1 xxx w 3 1 0 3 1 1 3 1 1 3 1 1 1 3 1 0 3 1 1 3 1 1 3 1 1 d16 PC 3 1 0 3 1 1 3 1 1 3 1 1 3 1 1 d8 PC Xi SF 4 1 0 4 1 1 4 1 1 4 1 1 lt XXX gt 1 0 0 2 0 1 2 0 1 2 0 1 Table 2 12 gives execution times f
96. 11 10 lists common SDRAM commands 11 16 MCF5307 User s Manual M woronoLA Synchronous Operation Table 11 10 SDRAM Commands Command Definition ACTV Activate Executed before READ or WRITE executes SDRAM registers and decodes row address MRS Mode register set NOP No op Does not affect SDRAM state machine DRAM controller control signals negated RAS asserted PALL Precharge all Precharges all internal banks of an SDRAM component executed before new page is opened READ Read access SDRAM registers column address and decodes that a read access is occurring REF Refresh Refreshes internal bank rows of an SDRAM component SELF Self refresh Refreshes internal bank rows of an SDRAM component when it is in low power mode SELFX Exit self refresh This command is sent to the DRAM controller when DCR IS is cleared WRITE Write access SDRAM registers column address and decodes that a write access is occurring SDRAMs operate differently than asynchronous DRAMS particularly in the use of data pipelines and commands to initiate special actions Commands are issued to memory using specific encodings on address and control pins Soon after system reset a command must be sent to the SDRAM mode register to configure SDRAM operating parameters Note that after synchronous operation is selected by setting DCR SO DRAM controller registers reflect the synchronous operation and there is no
97. 14 15 UART Module Signal Definitions sess 14 16 OPETAUON 14 18 Transmitter Receiver Clock Source sese 14 18 Programmable Divider sssssseeeeeee 14 18 Calculating Baud Rates iii cciccccccsssccssccssccsnccssesssessscsesedesadssesssessenssvessestees 14 19 BELKO Baud Rates essent 14 19 External Clock uento teet ettet tend 14 19 Transmitter and Receiver Operating Modes sess 14 19 d bruni ER 14 21 14 22 14 24 MONE S a ba 14 25 Automatic Echo Mode sse 14 25 Local Loop Back Mode sese 14 25 Remote Loop Back Mode sese 14 26 Multidrop Mode erg de en Ee e Per oe etate re egens 14 26 Bus Operation osoegsoe eene tee te epe eo DUE te exea rage 14 28 14 28 bue 14 28 Interrupt Acknowledge 14 28 Prosrammmng eterne aeneo grease 14 28 UART Module Initialization Sequence esee 14 29 Chapter 15 Parallel Port General Purpose I O Parallel Port Operation 15 1 Pin Assignment Register PAR sess 15 1 Port A Data Direction Register PADDR eere 15 2 Port Data Register
98. 16 17 18 19 A20 A21 Pins Table 11 27 MCF5307 to SDRAM Interface 32 Bit Port 9 Column Address Lines MCF5307 A15 A14 A13 A12 A11 A10 A9 A17 19 20 21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 Pins Row 15 14 13 12 11110 9 17 19 20 21 22 23 24 25 26 27 28 29 30 31 Column 2 3 4 5 6 718 16 18 SDRAM AO A1 A2 A4 A5 A7 A8 A9 10 11 12 13 14 15 16 17 18 19 A20 Table 11 28 MCF5307 to SDRAM Interface 32 Bit Port 10 Column Address Lines 5307 15 A14 A13 A12 A11 A10 A9 17 A19 A21 A22 A23 A24 A25 26 A27 A28 A29 A30 A31 Pins Row 15 14 13 12 11 10 9 17 19 21 22 23 24 25 26 27 28 29 30 31 Column 2 1314151617 8 16 18 20 SDRAM AO A1 A2 A4 A7 A8 A9 M0 A11 A12 A13 14 A15 16 A17 A18 A19 Pins 11 26 MCF5307 User s Manual M woronoLA Synchronous Operation Table 11 29 MCF5307 to SDRAM Interface 32 Bit Port 11 Column Address Lines MCF5307 15 A14 A13 A12 A11 A10 A9 A17 A19 A21 A23 A24 25 A26 A27 A28 A29 A30 A31 Pins Row 15 14 13 12 1
99. 27 continuous page mode 11 29 controller signals 11 17 edge select 11 18 general guidelines 11 23 initialization 11 33 interfacing 11 27 mask registers 11 22 mode register settings 11 33 register set 11 19 self refresh 11 32 DSCLK 5 2 E Electrical specifications clock timing 20 2 debug AC timing 20 12 DMA timing 20 19 general parameters 20 1 PC input output timing 20 15 input iutput AC timing 20 3 JTAG AC timing 20 20 parallel port timing 20 18 reset timing 20 12 timer module AC timing 20 14 UART module AC timing 20 16 F Fault on fault halt 5 16 H Halt fault on fault 5 16 Index 18 INDEX Pc address register 8 6 arbitration procedure 8 4 clock stretching 8 5 synchronization 8 5 control register 8 8 data I O register 8 10 features 8 1 frequency divider register 8 7 handshaking 8 5 interface memory map A 7 lost arbitration 8 13 overview 8 1 programming examples 8 10 model 8 6 protocol 8 3 repeated START generation 8 12 slave mode 8 13 software response 8 11 START generation 8 10 status register 8 9 STOP generation 8 12 system configuration 8 3 timing specifications 20 15 IEEE Standard 1149 1 Test Access Port see JTAG Instruction set general summary 2 34 MAC summary 3 4 MAC unit execution times 3 5 Integer data formats memory 2 32 registers 2 31 Interrupt controller autovector register 9 5 overview 9 1 pending and mask registers 9 6 po
100. 3 Data Transfer Operation Byte Enable BEO BE1 BE2 BES Pd D 31 24 03 16 05 8 D 7 0 Data Bus 32 Bit Port Bit 0 1 2 Byte 3 Y Y 16 Bit Port Byte 0 Byte 1 Driven with Memory Byte Byte 3 indeterminate values Y 8 Bit Port Byte 0 Memory Byte 1 Driven with Byte 2 indeterminate values Byte 3 Figure 18 2 Connections for External Memory Port Sizes The timing relationships between BCLKOchip select CS 7 0 byte enable byte write enables BE BWE 3 0 and output enable OE are similar to their relationships with address strobe AS in that all transitions occur during the low phase of BCLKO However as shown in Figure 18 3 differences in on chip signal routing and external loading may prevent signals from asserting simultaneously S 7 0 E 3 0 N E ENS LS Figure 18 3 TUM Module Output Timing Diagram E 52 18 4 1 Bus Cycle Execution When a bus cycle is initiated the MCF5307 first compares its address with the base address and mask configurations programmed for chip selects 0 7 CSCRO CSCR7 and for DRAM blocks 0 and 1 address and control registers DACRO and DACR1 If the driven address matches a programmed chip select or DRAM block the appropriate chip select is asserted or the DRAM block is selected using the specifications programmed in the respective configuration register Otherw
101. 4 DSCLK GND 5 6 Developer reserved RESET a 7 8 DSI Pad Voltage 9 10 DSO GND gt 11 12 PST3 PST2 gt 13 14 PST1 PSTO gt 15 16 DDATA3 DDATA2 gt 17 18 DDATA1 DDATAO 19 20 GND Motorola reserved 21 22 Motorola reserved GND 23 24 CLK CPU Core Voltage 25 26 TA Pins reserved for developer use Supplied by target Figure 5 44 Recommended BDM Connector 5 8 Processor Status DDATA Definition This section specifies the ColdFire processor and debug module s generation of the processor status PST and debug data DDATA output on an instruction basis In general the PST DDATA output for an instruction is defined as follows PST 0x1 PST 0x89B DDATA operand where the definition is optional operand information defined by the setting of the CSR 5 42 MCF5307 User s Manual M woronoLA Processor Status DDATA Definition The CSR provides capabilities to display operands based on reference type read write or both Additionally for certain change of flow branch instructions another CSR field provides the capability to display 0x2 0x3 0x4 bytes of the target instruction address For both situations an optional PST value 0x8 0x9 provides the marker identifying the size and presence of valid data on the D
102. 5 0 0 5 1 0 5 1 0 5 1 0 5 1 0 M MOTOROLA Chapter 3 Hardware Multiply Accumulate MAC Unit 3 5 MAC Instruction Execution Timings Table 3 3 shows standard timings for MAC move instructions Table 3 3 MAC Move Instruction Execution Times Effective Address Opcode ea Rn An An An d16 An d8 An Xi SF xxx wl lt xxx gt move lt ea gt ACC 1 0 0 1 0 0 move lt ea gt MACSR 6 0 0 6 0 0 move lt ea gt MASK 5 0 0 5 0 0 move ACC Rx 1 0 0 move MACSR CCR 1 0 0 move MACSR Rx 1 0 0 1 MASK Rx 1 0 0 3 6 MCF5307 User s Manual M Chapter 4 Local Memory This chapter describes the MCF5307 implementation of the ColdFire Version 3 local memory specification It consists of two major sections Section 4 2 SRAM Overview describes the MCF5307 on chip static RAM SRAM implementation It covers general operations configuration and initialization It also provides information and examples showing how to minimize power consumption when using the SRAM Section 4 7 Cache Overview describes the MCF5307 cache implementation including organization configuration and coherency It describes cache operations and how the cache in
103. 5 MHz 45 MHz 30 MHz 22 5 MHz 86 56 2 02725 3 04087 4 05449 0 1267 0 19005 0 25341 87 57 2 05055 3 07582 4 1011 0 12816 0 19224 0 25632 88 58 2 07385 3 11078 4 1477 0 12962 0 19442 0 25923 89 59 2 09715 3 14573 4 1943 0 13107 0 19661 0 26214 90 5A 2 12045 3 18068 4 24091 0 13253 0 19879 0 26506 91 5B 2 14376 3 21563 4 28751 0 13398 0 20098 0 26797 92 5C 2 16706 3 25059 4 33411 0 13544 0 20316 0 27088 93 5D 2 19036 3 28554 4 38072 0 1369 0 20535 0 27379 94 5E 2 21366 3 32049 4 42732 0 13835 0 20753 0 27671 95 5F 2 23696 3 35544 4 47392 0 13981 0 20972 0 27962 96 60 2 26026 3 3904 4 52053 0 14127 0 2119 0 28253 97 61 2 28357 3 42535 4 56713 0 14272 0 21408 0 28545 98 62 2 30687 3 4603 4 61373 0 14418 0 21627 0 28836 99 63 2 33017 3 49525 4 66034 0 14564 0 21845 0 29127 100 64 2 35347 3 53021 4 70694 0 14709 0 22064 0 29418 101 65 2 37677 3 56516 4 75354 0 14855 0 22282 0 2971 102 66 2 40007 3 60011 4 80015 0 15 0 22501 0 30001 103 67 2 42338 3 63506 4 84675 0 15146 0 22719 0 30292 104 68 2 44668 3 67002 4 89335 0 15292 0 22938 0 30583 105 69 2 46998 3 70497 4 93996 0 15437 0 23156 0 30875 106 6A 2 49328 3 73992 4 98656 0 15583 0 23375 0 31166 107 6B 2 51658 3 77487 5 03316 0 15729 0 23593 0 31457 108 6C 2 53988 3 80983 5 07977 0 15874 0 23811 0 31749 109 6D 2 56319 3 84478 5 12637 0 1602 0 2403 0 3204 110 6E 2 58649 3 87973 5 17297 0 16166 0 24248 0 32331 111 6F 2 60979 3 91468 5 21958 0 16311 0 24467 0 32622 112 70 2 63309 3 94964 5 26618 0 16457 0 2
104. 59241 7 45654 0 23302 0 34953 0 46603 160 AO 3 75157 5 62736 7 50314 0 23447 0 35171 0 46895 161 A1 3 77487 5 66231 7 54975 0 23593 0 35389 0 47186 162 A2 3 79818 5 69726 7 59635 0 23739 0 35608 0 47477 163 A3 3 82148 5 73222 7 64295 0 23884 0 35826 0 47768 164 A4 3 84478 5 76717 7 68956 0 2403 0 36045 0 4806 165 A5 3 86808 5 80212 7 73616 0 24176 0 36263 0 48351 M Chapter 13 Timer Module 13 11 Calculating Time Out Values Table 13 5 Calculated Time out Values 90 MHz Processor Clock Continued TMR PS TMR CLK 10 System Bus Clock 16 TMR CLK 01 System Bus Clock 1 Decimal Hex 45 MHz 30 MHz 22 5 MHz 45 MHz 30 MHz 22 5 MHz 166 A6 3 89138 5 83707 7 78276 0 24321 0 36482 0 48642 167 A7 3 91468 5 87203 7 82937 0 24467 0 367 0 48934 168 A8 3 93799 5 90698 7 87597 0 24612 0 36919 0 49225 169 A9 3 96129 5 94193 7 92257 0 24758 0 37137 0 49516 170 AA 3 98459 5 97688 7 96918 0 24904 0 37356 0 49807 171 AB 4 00789 6 01184 8 01578 0 25049 0 37574 0 50099 172 AC 4 03119 6 04679 8 06238 0 25195 0 37792 0 5039 173 AD 4 05449 6 08174 8 10899 0 25341 0 38011 0 50681 174 AE 4 0778 6 11669 8 15559 0 25486 0 38229 0 50972 175 AF 4 1011 6 15165 8 20219 0 25632 0 38448 0 51264 176 BO 4 1244 6 1866 8 2488 0 25777 0 38666 0 51555 177 1 4 1477 6 22155 8 2954
105. 7 BERR oh NEXT CMD READY Figure 5 39 wcREG Command Sequence Operand Data This instruction requires two longword operands The first selects the register to which the operand data is to be written the second contains the data Result Data Successful write operations return OxFFFF Bus errors on the write cycle are indicated by the setting of bit 16 in the status message and by a data pattern of 0x0001 M MOTOROLA Chapter 5 Debug Support 5 37 Background Debug Mode BDM 5 5 3 3 12 Read Debug Module Register RDMREG Read the selected debug module register and return the 32 bit result The only valid register selection for the RDMREG command is CSR DRc 0x00 Note that this read of the CSR clears the trigger status bits CSR BSTAT if either a level 2 breakpoint has been triggered or a level 1 breakpoint has been triggered and no level 2 breakpoint has been enabled Command Result Formats 15 14 189 12 1 10 9 7 6 5 4 8 2 1 0 Command 0x2 OxD 0 4 Result D 31 16 D 15 0 Figure 5 40 RDMREG BDM Command Result Formats Note 0x4 is a 3 bit field Table 5 20 shows the definition of DRc encoding Table 5 20 Definition of DRc Encoding Read DRc 4 0 Debug Register Definition Mnemonic Initial State Page 0x00 Configuration Status CSR 0 0 5 10 0 01 0 1 Reserved m Command Sequence RDMREG C X NEXT CMD 7
106. A21 A22 Pins Table 11 21 MCF5307 to SDRAM Interface 16 Bit Port 9 Column Address Lines MCF5307 A16 A15 14 13 A12 A11 10 A9 A18 A19 A20 21 22 A23 A24 A25 A26 A27 A28 A29 A30 A31 Pins Row 16 15 14 13 12 11 10 9 18 19 20 21 22 23 24 25 26 27 28 29 80 31 Column 1 2 3 4 5 67 8 17 SDRAM AO A1 A2 A4 A5 A7 8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 21 Pins Table 11 22 MCF5307 to SDRAM Interface 16 Bit Port 10 Column Address Lines MCF5307 A16 A15 A14 A13 12 A11 A10 A9 A18 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 Pins Row 16 15 14 13 12 11 10 9 18 20 21 22 23 24 25 26 27 28 29 30 31 Column 1 2 3 4 5 671 8 17 19 SDRAM AO A1 A2 A4 A7 A8 A9 A10 11 A12 A13 A14 A15 A16 A17 A18 A19 A20 Pins Table 11 23 MCF5307 to SDRAM Interface 16 Bit Port 11 Column Address Lines MCF5307 16 A15 A14 A13 A12 A11 A10 A9 A18 A20 A22 23 A24 A25 A26 A27 A28 A29 A30 A31 Pins Row 16 15 14 13 12 11 10 9 18 20 22 23 24 25 26 27 28 29 30 31 Column 1 2 4 5 6 7 17 19121 SDRAM AO A1 2 4 A7 A8 A9 A10 A11 A12 A13 14 15 A16 17 18 19 Pins M MOTOROLA Chapter 11 Synchronous Asynchronous DRAM Controller Module 11 25
107. ACC 0x005 Access control register 1 ACR1 Ox80E Status register SR 0x801 Vector base register VBR Ox80F Program register PC 0x804 MAC status register MACSR 0xC04 RAM base address register RAMBAR 1 Available if the optional MAC unit is present Command Sequence RCREG MS ADDR MS ADDR Fidi E 777 NOT READY READY REGISTER READY XXX NEXT CMD MS RESULT LS RESULT XXX NEXT CMD BERR NOT READY Figure 5 37 RcREG Command Sequence Operand Data The only operand is the 32 bit Rc control register select field Result Data Control register contents are returned as a longword most significant word first The implemented portion of registers smaller than 32 bits is guaranteed correct other bits are undefined 5 36 MCF5307 User s Manual M woronoLA Background Debug Mode BDM 5 5 3 3 11 Write Control Register WCREG The operand longword data is written to the specified control register The write alters all 32 register bits Command Result Formats 15 14 18 12 11 10 9 8 7 6 5 4 3 2 1 0 Command 0 2 0 8 0 8 0 0 0 0 0 0 0 0 0 0 0 0 Result D 31 16 D 15 0 Figure 5 38 wcREG Command Result Formats Command Sequence WCREG Ms ADDR MS ADDR MS DATA 22 NOT READYZ NOT READY READYY NOT READY REGISTER N 2 READY NEXT CMD COMPLETE
108. BDM address attribute 5 9 bus master park 6 11 chip select control 10 8 mask 10 6 module 10 5 condition code 2 28 condition code CCR 2 28 data breakpoint mask 5 12 data DO D7 2 27 DBR DBMR 5 7 debug attribute trigger 5 7 DMA byte count 12 7 source address 12 6 DRAM asynchronous address and control 11 5 DACR 11 5 DCR 11 4 DMR 11 7 mode signals 11 4 general operation 11 3 synchronous DACR 11 20 DCR 11 19 DMR 11 22 mode settings 11 33 PC address 8 6 control 8 8 data I O 8 10 frequency divider 8 7 status 8 9 I2CR 8 8 DDR 8 10 DSR 8 9 IADR 8 6 IFDR 8 7 interrupt controller autovector 9 5 pending and mask 9 6 port assignment 9 7 IPR and IMR 9 6 IRQPAR 9 7 JTAG Index 19 boundary scan 19 7 bypass 19 10 descriptions 19 4 IDCODE 19 6 instruction shift 19 5 MAC status 1 14 2 29 MASK 2 29 MBAR 6 4 MPARK 6 11 output port command 14 15 PADAT 15 2 PADDR 15 2 PAR 6 10 15 1 parallel port data 15 2 pin assignment 6 10 15 1 PLL control 7 3 PLLCR 7 3 read control 5 36 read debug module 5 38 reset status 6 5 RSR 6 5 S bit 1 12 SDRAM mode initialization 11 38 SIM base address 6 4 memory map 6 3 software watchdog interrupt 6 9 status 2 20 SWIVR 6 9 SWSR 6 9 SYPCR 6 8 system protection control 6 8 TCR 13 4 TER 13 5 timer module capture 13 4 event 13 5 mode 13 3 reference 13 4 TMR 13 3 trigger definition 5 14 ACR 14 12 ART
109. Cache Operation Figure 4 5 shows the general flow of a caching operation Address r 1 31 11 10 43 0 Way 3 Tag Data Tag Reference index STATUS Set Select A 10 4 8 M STATUS Data or Address Instruction A 31 11 Figure 4 5 Caching Operation The following steps determine if a cache line is allocated for a given address 1 The cache set index A 10 4 selects one cache set 2 A 31 11 and the cache set index are used as a tag reference or are used to update the cache line tag field Note that A 31 11 can specify 21 possible addresses that can be mapped to one of the four ways 3 The four tags from the selected cache set are compared with the tag reference A cache hit occurs if a tag matches the tag reference and the V bit is set indicating that the cache line contains valid data If a cacheable write access hits in a valid cache line the write can occur to the cache line without having to load it from memory If the memory space is copyback the updated cache line is marked modified M 1 because the new data has made the data in memory out of date If the memory location is write through the write is passed on to system memory and the M bit is never used Note that the tag does not have TT or TM bits To allocate a cache entry the cache set index selects one of the cache s 128 sets The cache control logic looks for an invalid cache line to use
110. DACR CASL 2 Figure 20 9 SDRAM Write Cycle with EDGESEL Tied Low Figure 20 10 shows AC timing showing high impedance OUTPUTS Figure 20 10 AC Output Timing High Impedance M woronoLA Chapter 20 Electrical Specifications 20 11 Reset Timing Specifications 20 4 Reset Timing Specifications Table 20 7 lists specifications for the reset timing parameters shown in Figure 20 11 Table 20 7 Reset Timing Specification 66 MHz 90 MHz Num Characteristic Units Min Max Min Max R1 Valid to CLKIN setup 7 5 5 5 nS R2 CLKIN to invalid hold 3 2 nS R3 RSTI to invalid hold 3 2 nS 1 RSTI and D 7 0 are synchronized internally Setup and hold times must be met only if recognition on a particular clock is required Figure 20 11 shows reset timing for the values in Table 20 7 CLKIN Xo N y VW f rH MQ YS va MW Om eae Note Mode selects are registered on the rising CLKIN edge before the cycle in which RSTI is recognized as being negated Figure 20 11 Reset Timing 20 5 Debug AC Timing Specifications Table 20 8 lists specifications for the debug AC timing parameters shown in Figure 20 13 Table 20 8 Debug AC Timing Specification 66 MHz 90 MHz Num Characteristic Units Min Max Min Max D1 PST DDATA to PSTCLK setup 7
111. DMA control register 2 DCR2 p 12 8 0x38C Byte count register 2 BCR24BIT 0 Reserved 0x38C Reserved Byte count register 2 BCR24BIT 1 BCR2 p 12 7 0x390 DMA status register 2 Reserved DSR2 p 12 10 A 8 MCF5307 User s Manual M woronoLA Table A 10 DMA Controller Registers Continued MBAR Offset 31 24 23 16 15 8 7 0 0x394 DMA interrupt vector Reserved register 2 DIVR2 p 12 11 0x3C0 Source address register p 12 6 0x3C4 Destination address register 3 DAR3 p 12 7 0x3C8 DMA control register 3 DCR3 p 12 8 Ox3CC Byte count register 3 BCR24BIT 0 Reserved 0x3CC Reserved Byte count register 3 BCR24BIT 1 BCR3 p 12 7 0 300 status register 3 Reserved DSR3 p 12 10 0x3D4 DMA interrupt vector Reserved register 3 DIVR3 p 12 11 1 the 0H55J and 1H55J revisions of the MCF5307 the byte count register of the DMA channels can accommodate only 16 bits However on the newest revision of the MCF5307 an expanded 24 bit byte count range provides greater flexibility For this reason the position of the byte count register BCR in the memory map depends on whether a 16 or 24 bit byte counter is chosen The selection is made by programming MPARK BCR24BIT in the SIM module In the new MCF5307 the 24 bit byte count can be selected by setting BCR24BIT 1 making DCR AT available The AT bit selects wh
112. EDGESEL D 31 0 A 23 0 SCKE SRAS SCAS DRAMW and PP 15 8 when individually configured as address outputs parallel port outputs Applies to RAS 1 0 CAS 1 0 SRAS SCAS DRAMW High Impedance three state D 31 0 7 Outputs that transition to high impedance due to bus arbitration A 23 0 R W SIZ 1 0 TS AS TA and PP 15 0 when individually configured as address outputs 8 Outputs that only change on falling edge of BCLKO AS CS 7 0 BE 3 0 OE Note that these figures show two representative bus operations and do not attempt to show all cases For explanations of the states SO S5 see Section 18 4 Data Transfer 20 4 MCF5307 User s Manual M woronoLA Input Output AC Timing Specifications Operation Note that Figure 20 4 does not show all signals that apply to each timing specification See the previous tables for a complete listing Figure 20 3 shows AC timings for normal read and write bus cycles S0 51 52 53 S4 S5 S0 Si 52 3 S4 S5 lt lt lt lt lt lt lt A 31 0 D EE MEN X Figure 20 3 AC Timings Normal Read and Write Bus Cycles Figure 20 4 shows timings for a read cycle with EDGESEL tied to buffered BCLKO M woronoLA Chapter 20 Electrical Specifications 20 5 Input Output AC Timing Specifications 112 4 5 6 9 11 12 13 14 BCLKO
113. EQU MBARx 0x18C Timer 1 counter EQU MBARx 0x151 Timer 0 event register TERI EQU MBARx 0x191 Timer 1 event register TMRO is defined as 5 OxFF divide clock by 256 CE 00disable interrupt OM 0 output active low pulse ORI 0 disable ref interrupt FRR 1 restart mode enabled CLK 10 BCLKO 16 RST 0 timer 0 disabled move w 0xFFOC DO move w move w 0x0000 D0 writing to the timer counter with any move w DO TCNO value resets it to zero move w AFAF DO set the timer 0 reference to be move w D0 TRRO defined as OxAFAF The simple example below uses 0 to count time out loops A time out occurs when the reference value Ox AFAF is reached timer0 ex 13 6 clr l DO clr 1l Dl clt 1 D2 move w 0x0000 D0 move w D0O TCNO reset the counter to 0x0000 move b 0x03 D0 writing ones to TERO REF CAP move b DO TERO clears the event flags MCF5307 User s Manual M woronoLA Calculating Time Out Values move w TMRO D0 save the contents of TMRO while setting bset 0 D0 the 0 bit This enables timer 0 and starts counting move w D0 TMRO load the value back into the register setting TMRO RST TO LOOP move b TERO D1 load TERO and see if btst 1 D1 TERO REF has been set TO LOOP 1 1 D2 Increment D2 cmp l 5 D2 Did D2 reach 5 i e timer ref has timed beq TO FINISH If so end timer0 example Otherwise jump back move b 0x02 D0 writing one to TERO
114. Enhancements For example if an unconditional BRA instruction is detected the IED calculates the target of the BRA instruction and the IAG immediately begins fetching at the target address Because of the decoupled nature of the two pipelines the target instruction is available to the OEP immediately after the BRA instruction giving it a single cycle execution time The acceleration logic uses a static prediction algorithm when processing conditional branch Bcc instructions The default scheme is forward Bcc instructions are predicted as not taken while backward Bcc instructions are predicted as taken A user mode control bit CCR 7 allows users to dynamically alter the prediction algorithm for forward Bcc instructions See Section 2 2 1 5 Condition Code Register CCR 2 1 2 2 Operand Execution Pipeline OEP The OEP is a two stage pipeline featuring a traditional RISC datapath with a register file feeding an arithmetic logic unit For simple register to register instructions the first stage of the OEP performs the instruction decode and fetching of the required register operands OC while the actual instruction execution is performed in the second stage EX For memory to register instructions the instruction is effectively staged through the OEP twice in the following way The instruction is decoded and the components of the operand address are selected DS The operand address is generated using the execute eng
115. If the reference is mapped into a region defined by the SRAM the SRAM provides data to the processor and any cache data is discarded Data accessed from the SRAM module are not cached Note also that the SRAM cannot be accessed by the on chip DMAs The on chip system configuration allows concurrent core and DMA execution where the core can reference code or data from the internal SRAM or cache while performing a DMA transfer 4 2 MCF5307 User s Manual M woronoLA SRAM Programming Model Accesses are attempted in the following order 1 SRAM 2 Cache if space is defined as cacheable 3 External access 4 4 SRAM Programming Model The SRAM programming model consists of RAMBAR 4 4 1 SRAM Base Address Register RAMBAR The SRAM modules are configured through the RAMBAR shown in Figure 4 1 RAMBAR holds the base address of the SRAM The MOVEC instruction provides write only access to this register from the processor RAMBAR can be read or written from the debug module in a similar manner All undefined RAMBAR bits are reserved These bits are ignored during writes to the RAMBAR and return zeros when read from the debug module The valid bit RAMBAR V is cleared at reset disabling the SRAM module All other bits are unaffected 31 15 14 9 8 7 6 5 4 3 2 1 0 Field BA WP C SC SD UC UD V Reset R W W for CPU R W for debug Address CPU space 0xC04 Figu
116. Internal External Termination esssss 18 14 Line Write Burst 3 2 2 2 with One Wait State Internal Termination 18 15 Line Write Burst Inhibited Internal Termination eeeeee 18 15 M MOTOROLA Illustrations xxiii Figure Number 18 19 18 20 18 21 18 22 18 23 18 24 18 25 18 26 18 27 18 28 18 29 18 30 18 31 18 32 18 33 18 34 19 1 19 2 19 4 19 5 20 1 20 2 20 3 20 4 20 5 20 6 20 7 20 8 20 9 20 10 20 11 20 12 20 13 20 14 20 15 20 16 20 17 20 18 20 19 xxiv ILLUSTRATIONS Tule Number Longword Read from an 8 Bit Port External Termination esses 18 16 Longword Read from an 8 Bit Port Internal Termination esses 18 16 Example of a Misaligned Longword Transfer 32 Bit Port 18 17 Example of a Misaligned Word Transfer 32 Bit Port sss 18 17 Interrupt Acknowledge Cycle Flowchart essen 18 20 Basic No Wait State External Master Access 18 22 External Master Burst Line Access to 32 Bit Port 18 24 MCF5307 Two Wire Mode Bus Arbitration Interface sess 18 25 Two Wire Bus Arbitration with Bus Request Asserted esses 18 26 Two Wire Implicit and Explicit Bus Mastership see 18 27 MCF5307 Two Wire Bus Arbitration Protocol State
117. MHz The MCF5307 core design emphasizes performance and backward compatibility represents the next step on the ColdFire performance roadmap The following list summarizes MCF5307 features e Variable length RISC clock multiplied Version 3 microprocessor core Two independent decoupled pipelines four stage instruction fetch pipeline IFP and two stage operand execution pipeline OEP Eight instruction FIFO buffer provides decoupling between the pipelines Branch prediction mechanisms for accelerating program execution 32 bit internal address bus supporting 4 Gbytes of linear address space e 32 bit data bus e 16 user accessible 32 bit wide general purpose registers e Supervisor user modes for system protection e Vector base register to relocate exception vector table Optimized for high level language constructs M MOTOROLA Chapter 2 ColdFire Core 2 21 Features and Enhancements 2 1 1 Clock Multiplied Microprocessor Core The MCF5307 incorporates a clock multiplying phase locked loop PLL Increasing the internal speed of the core also allows higher performance while providing the system designer with an easy to use lower speed system interface The frequency of the processor complex can be 2x 3x or 4x the external bus speed The processor cache integrated SRAM and misalignment module operate at the higher speed clock PCLK other system integrated modules operate at the speed of the bus clock BCLKO
118. MS RESULT LS RESULT NEXT CMD ILLEGAL READY Figure 5 41 Command Sequence Operand Data None Result Data The contents of the selected debug register are returned as a longword value The data is returned most significant word first 5 38 MCF5307 User s Manual M woronoLA Real Time Debug Support 5 5 3 3 13 Write Debug Module Register WDMREG The operand longword data is written to the specified debug module register All 32 bits of the register are altered by the write DSCLK must be inactive while the debug module register writes from the CPU accesses are performed using the WDEBUG instruction Command Format Figure 5 42 wWDMREG Command Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x2 OxC 0x4 DRc D 31 16 D 15 0 Note 0x4 is a three bit field Table 5 3 shows the definition of the DRc write encoding Command Sequence WDMREG MS DATA LS NEXTCMD NOT READY NOT READY CMD COMPLETE XXX NEXT CMD ILLEGAL NOT READY Figure 5 43 WOMREG Command Sequence Operand Data Longword data is written into the specified debug register The data is supplied most significant word first Result Data Command complete status OxFFFF is returned when register write is complete 5 6 Real Time Debug Support The ColdFire Family provides support debugging real time applications For these types of embedded systems the processor
119. PP1 enable rr 123 O Pin SRAS 4 1 VO 124 O Pin DRAMW 5 I Pin PP1 VO 125 O Pin CAS3 6 IO Ctl PP2 enable 126 O Pin CAS2 7 O Pin PP2 VO 127 O Pin CAST 8 I Pin PP2 VO 128 O Pin CASO 9 10 Ctl PP3 enable 129 O Pin RAS1 10 VO 130 O Pin RASO 9 11 I Pin PP3 VO 131 1 TIN1 12 4 enable 132 TINO 13 O Pin PP4 VO 133 O Pin TOUTO 14 I Pin PP4 VO 134 O Pin TOUT1 9 15 10 Ctl PP5 enable 135 I Pin BG 16 5 VO 136 O Pin BD 9 17 I Pin PP5 VO 137 O Pin BR 18 10 Ctl PP6 enable 138 I Pin IRQ1 19 O Pin PP6 VO 139 I Pin IRQ3 20 I Pin PP6 y o 140 1 IRQ5 21 10 Ctl PP7 enable 141 I Pin IRQ7 22 7 VO 142 1 RSTI 23 I Pin PP7 VO 143 O Pin TS yo 24 O Pin PST3 144 TS yo 25 O Pin PST2 145 TA enable 26 O Pin PST1 146 O Pin TA yo 27 O Pin PSTO 147 yo 28 O Pin DDATA3 148 O Pin R W yo M MOTOROLA Chapter 19 IEEE 1149 1 Test Access Port JTAG 19 7 JTAG Register Descriptions Table 19 4 Boundary Scan Bit Definitions Bit Cell Type Pin Cell Pin Type Bit Cell Type Pin Cell Pin Type 29 O Pin DDATA2 149 R W yo 30 O Pin DDATA1 150 O Pin AS yo 31 O Pin DDATAO 151 AS yo 32 O Pin PSTCLK 152 O P
120. Refresh 11 32 Refresh ense tr rr EIN Pa ei Rete E eia doses 11 32 Mode Register Set mrs Command esee 11 34 Initialization Values for DCR nnne nennen enne 11 35 SDRAM Configuration aee rete m re Ee rH ree ER e e EE 11 36 Register 11 36 DMRO REGIS EF M 11 37 Mode Register Mapping to MCF5307 A 31 0 sss 11 38 DMA Signal Diagram sese enne ennemi nennen 12 1 Dual Address a a eas 12 3 1 1 teet a 12 4 Source Address Registers 12 6 Destination Address Registers DARn eese nennen 12 7 Byte Count Registers BCRn BCR24BIT 1 eee 12 7 BCRn BCRO2ABIT 0 sees nnne ener 12 8 DMA Control Registers 12 8 Stat s Registets DSRn ect eee etat e aeris 12 10 Interrupt Vector Registers DIVRn eene 12 11 DREQ Timing Constraints Dual Address DMA 12 15 Dual Address Peripheral to SDRAM Lower Priority DMA Transfer 12 16 Single Address DMA 3
121. Registers ICRO ICRO9 Note that the UARTs can also automatically transfer data by using the DMA rather than interrupting the core When UIMR FFULL is 1 and a receiver s FIFO is full it can send an interrupt to DMA channel so the FIFO data can be transferred to memory Note also that UARTO and UART1 s interrupt requests are connected to DMA channel 2 and channel 3 respectively Table 14 13 briefly describes the UART module signals NOTE The terms assertion and negation are used to avoid confusion between active low and active high signals Asserted indicates that a signal is active independent of the voltage level negated indicates that a signal is inactive Table 14 13 UART Module Signals Signal Description Transmitter TxD is held high mark condition when the transmitter is disabled idle or operating in the local Serial Data loop back mode Data is shifted out on TxD on the falling edge of the clock source with the least Output TxD significant bit Isb sent first Receiver Data received on RxD is sampled on the rising edge of the clock source with the Isb received first Serial Data Input RxD Clear to This input can generate an interrupt on a change of state Send CTS Request to This output can be programmed to be negated or asserted automatically by either the receiver or the Send RTS transmitter When connected to a transmitters CTS RTS can
122. The SR stores the processor status the interrupt priority mask and other control bits Supervisor software can read or write the entire SR user software can read or write only SR 7 0 described in Section 2 2 1 5 Condition Code Register CCR The control bits indicate processor states trace mode T supervisor or user mode S and master or interrupt state M SR is set to 0x27xx after reset M MOTOROLA Chapter 2 ColdFire Core 2 29 Programming Model 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 System byte Condition code register CCR Field T S M X N Z V C Reset 0 0 1 0 0 111 0 00 RW RW RW R W R W R R W RW Figure 2 5 Status Register SR Table 2 3 describes SR fields Table 2 3 Status Field Descriptions Bits Name Description 15 b Trace enable When T is set the processor performs a trace exception after every instruction 13 S Supervisor user state Indicates whether the processor is in supervisor or user mode 0 User mode 1 Supervisor mode 12 M Master interrupt state Cleared by an interrupt exception It can be set by software during execution of the RTE or move to SR instructions so the OS can emulate an interrupt stack pointer 10 8 Interrupt priority mask Defines the current interrupt priority Interrupt requests are inhibited for all priority levels less than
123. UART Modules Parallel Port General Purpose Part IV Hardware Interface Mechanical Data Signal Descriptions Bus Operation IEEE 1149 1 Test Access Port JTAG Electrical Specifications Appendix B Memory Map Glossary of Terms and Abbreviations Index CONTENTS Paragraph Title Page Number Number About This Book Chapter 1 Overview 1 1 I ER 1 1 1 2 MGE9530 7 Eeatllt6S8 onse NEUE ERIS OR EG EE E EE CHEESE HEN 1 4 1 2 1 PHOCESS 7s 1 6 1 3 ColdFire Module Description esses 1 7 1 3 1 ColdEire G0 concer oe 1 7 1 3 1 1 Instruction Fetch Pipeline IFP enne 1 7 1 3 1 2 Operand Execution Pipeline OEP sse 1 7 1 3 1 3 Module 1 7 1 3 1 4 Integer Divide Module esee 1 7 1 3 1 5 8 Kbyte Unified essen 1 8 1 3 1 6 Internal 4 Kbyte SRAM eene 1 8 1 3 2 DRAM Cotiroller 5 9 dre NH I e e IUS 1 8 1 3 3 DMA Controller irr rore e b e ae ere rea 1 8 1 3 4 UART Modules tret eere reete tie ee cere eh eee ea een eodd 1 8 1 3 5 Timer Module tomum Sunburst 1 9 1 3 6 ER E EE qned 1 9 1 3 7 System Interface E EAEE 1 10 1 3 7 1 External Interface ert mee mt e aree 1 10 1 3 7 2 Chip Selects inte eet reet aie dienen 1 10 1 3 7 3 16 Bit Parallel Port Inte
124. UCSRn should be changed only after the receiver transmitter is issued a software reset command That is if channel operation is not disabled undesirable results may occur This address is for factory testing Reading this location results in undesired effects and possible incorrect transmission or reception of characters Register contents may also be changed Address triggered commands M woronoLA Appendix A List of Memory Maps A 6 Table A 7 UART1 Module Programming Model MBAR Offset 31 24 23 16 15 8 7 0 0x200 UART mode registers UMR1n p 14 4 UMR2n p 14 6 0x204 Read UART status registers USRn p 14 7 Write UART clock select register UCSRn p 14 8 0x208 Read Do not access Write UART command registers UCRn p 14 9 0x20C UART Read UART receiver buffers URBn p 14 11 UART Write UART transmitter buffers UTBn p 14 11 0x210 Read UART input port change registers UIPCRn p 14 12 Write UART auxiliary control registers UACRn p 14 12 0x214 Read UART interrupt status registers UISRn p 14 13 Write UART interrupt mask registers UIMRn p 14 13 0x218 UART divider upper registers UDUn p 14 14 0x21C UART divider lower registers UDLn p 14 14 MCF5307 User s Manual M MO
125. X X X X Address with An 011 reg no X X X Postincrement 100 X X X Address with 916 An 101 reg no X X X Predecrement Address with Displacement Address register indirect with index dg An 110 reg no X X X X 8 bit displacement Xi Program counter indirect with displacement dig PC 111 010 X X X Program counter indirect with index dg PC 111 011 X X X 8 bit displacement Xi Absolute data addressing Short xxx W 111 000 X X X Long xxx L 111 001 X X X Immediate lt XXX gt 111 100 X x 2 6 Instruction Set Summary The ColdFire instruction set is a simplified version of the M68000 instruction set The removed instructions include BCD bit field logical rotate decrement and branch and integer multiply with a 64 bit result Nine new MAC instructions have been added Table 2 6 lists notational conventions used throughout this manual Table 2 6 Notational Conventions Instruction Operand Syntax Opcode Wildcard cc Logical condition example NE for not equal 2 34 MCF5307 User s Manual M woronoLA Instruction Set Summary Table 2 6 Notational Conventions Continued Instruction Operand Syntax Register Specifications An Any address register n example A3 is address register 3 Ay Ax Source and destination address registers
126. a STOP command to the slave device placing it in idle state as if it were just power cycled on I2CR 0x0 I2CR dummy read of I2DR IBSR 0x0 I2CR 0x0 8 6 2 Generation of START After completion of the initialization procedure serial data can be transmitted by selecting the master transmitter mode On a multiple master bus system IBSR IBB must be tested to determine whether the serial bus is free If the bus is free IBB 0 the START signal 8 10 MCF5307 User s Manual M Pc Programming Examples and the first byte the slave address can be sent The data written to the data register comprises the address of the desired slave and the Isb indicates the transfer direction The free time between a STOP and the next START condition is built into the hardware that generates the START cycle Depending on the relative frequencies of the system clock and the SCL period it may be necessary to wait until the PC is busy after writing the calling address to the I2DR before proceeding with the following instructions The following example signals START and transmits the first byte of data slave address CHFLAG MOVE B I2SR A0 Check I2SR MBB BTST B 5 AQ BNE S CHFLAG If I2SR MBB 1 wait until it is clear TXSTART MOVE B I2CR A0 Set transmit mode BSET B 4 0 MOVE B 0 I2CR MOVE B I2CR A0 Set master mode BSET B 5 A0 Generate START condition MOVE B 0 I2CR MOVE B CA
127. access to all data and chip control pins from the board edge connector through the standard four pin test access port TAP and the JTAG reset pin TRST Test logic design is static and is independent of the system logic except where the JTAG is subordinate to other complimentary test modes as described in Chapter 5 Debug Support When in subordinate mode JTAG test logic is placed in reset and the TAP pins can be used for other purposes as described in Table 19 1 The MCF5307 JTAG implementation can do the following e Perform boundary scan operations to test circuit board electrical continuity e Bypass the MCF5307 by reducing the shift register path to a single cell Set MCF5307 output drive pins to fixed logic values while reducing the shift register path to a single cell Sample MCF5307 system pins during operation and transparently shift out the result e Protect MCF5307 system output and input pins from backdriving and random toggling such as during in circuit testing by placing all system pins in high impedance state NOTE IEEE Standard 1149 1 may interfere with system designs that do not incorporate JTAG capability Section 19 6 Disabling IEEE Standard 1149 1 Operation describes precautions for ensuring that this logic does not affect system or debug operation M MOTOROLA Chapter 19 IEEE 1149 1 Test Access Port JTAG 19 1 JTAG Signal Descriptions Figure 19 1 is a block diagram of the MCF5307 imple
128. acknowledge valid 0 SWTA transfer acknowledge has not occurred 1 SWTA transfer acknowledge has occurred Write a 1 to clear this flag bit 6 2 6 Software Watchdog Interrupt Vector Register SWIVR The SWIVR shown in Figure 6 6 contains the 8 bit interrupt vector SWIV that the SIM returns during an interrupt acknowledge cycle in response to a software watchdog timer generated interrupt SWIVR is set to the uninitialized vector OxOF at system reset 7 0 Field SWIV Reset 0000 1111 R W Supervisor write only Address MBAR 0x002 Figure 6 6 Software Watchdog Interrupt Vector Register SWIVR Note that the software watchdog interrupt cannot be autovectored 6 2 7 Software Watchdog Service Register SWSR The SWSR shown in Figure 6 7 is where the software watchdog timer servicing sequence should be written To prevent a watchdog timer timeout the software service sequence must be performed 0x55 followed by OxAA written to the SWSR Both writes must be performed in order before the timeout but any number of instructions or accesses to the SWSR can be executed between the two writes If the timer has timed out writing to SWSR does not cancel the interrupt that is IPR SWT remains set The interrupt is cancelled and SWT is cleared automatically when the IACK cycle is run 7 0 Field SWSR Reset Undetermined R W Supervisor write only Address MBAR 0x003 Figure 6 7 Softwar
129. after 5 TCK clocks If MTMODO is low DSCLK is selected DSCLK is the development serial clock for the serial interface to the debug module The maximum DSCLK frequency is 1 5 CLKIN See Chapter 5 Debug Support 17 14 2 Test Mode Select Breakpoint TMS BKPT If MTMODO is high TMS is selected The TMS input provides information to determine the JTAG test operation mode The state of TMS and the internal 16 state JTAG controller state machine at the rising edge of TCK determine whether the JTAG controller holds its current state or advances to the next state This directly controls whether JTAG data or instruction operations occur TMS has an internal pull up resistor so that if it is not driven low it defaults to a logic level of 1 But if TMS is not used it should be tied to Vpp If MTMODO is low BKPT is selected BKPT signals a hardware breakpoint to the processor in debug mode See Chapter 5 Debug Support 17 14 3 Test Data Input Development Serial Input TDI DSI If MTMODO is high TDI is selected TDI provides the serial data port for loading the various JTAG boundary scan bypass and instruction registers Shifting in data depends on the state of the JTAG controller state machine and the instruction in the instruction register Shifts occur on the TCK rising edge TDI has an internal pull up resistor so when not driven low it defaults to high But if TDI is not used it should be tied to Vpp If MTMODO is low DSI 15
130. and SDA 66 MHz 90 MHz Num Characteristic Units Min Max Min Max nt Start condition hold time 6 6 Bus clocks 121 Clock low period 10 10 Bus clocks I3 SCL SDA rise time Vi 0 5 V to 2 4 V uS 14 Data hold time 7 7 Bus clocks 15 3 SCL SDA fall time 2 4 V to V 0 5 V 3 3 nS 16 Clock high time 10 10 Bus clocks 171 Data setup time 2 2 Bus clocks 181 Start condition setup time for repeated start 20 20 Bus clocks condition only 19 Stop condition setup time 10 10 Bus clocks Note Output numbers depend on the value programmed into the IFDR an IFDR programmed with the maximum frequency IFDR 0x20 results in minimum output timings as shown in Table 20 11 The interface is designed to scale the actual data transition time to move it to the middle of the SCL low period The actual position is affected by the prescale and division values programmed into the IFDR however the numbers given in Table 20 11 are minimum values Because SCL and SDA are open collector type outputs which the processor can only actively drive low the time SCL or SDA take to reach a high level depends on external signal capacitance and pull up resistor values 3 Specified at a nominal 50 pF load M woronoLA Chapter 20 Electrical Specifications 20 15 UART Module AC Timing Specifications Figure 20 8 shows timing
131. and asynchronous DRAM Four channel DMA controller Two general purpose timers Two UARTs PC interface Parallel I O interface System integration module SIM Designed for embedded control applications the MCF5307 delivers 75 Dhrystone 2 1 MIPS at 90 MHz while minimizing system costs MOTOROLA Chapter 1 Overview 1 1 Features V3 COLDFIRE PROCESSOR COMPLEX JTAG Instruction Unit Branch Logic Instruction Fetch c CCR Pipeline IFP General Purpose Registers BOTT Eight Instruction FIFO Buffer Operand Execution Pipeline OEP 00 07 81 0 MAC lt PSTCLK SRAM Controller RAMBAR BCLKO 4 Kbyte sent off chip SRAM and to on chip peripherals Cache Controller 8 Kbyte SES 4 Entry Store Buffer Local Memory Bus DMA SYSTEM INTEGRATION MODULE SIM PLL Control System Control Base Address Bus Master Park Parallel Port Grace PLL RSR SWIVR MBAR MPARK PLL Ss 1 1 1 p 1 Software SYPCR SWSR Watchdog DRAM Controller Chip Select Module External Interrupt Controller Module DRAM Control Bus Interface DCR 8 8 8 CSARs CSCRs CSMRs Addr Cntrl Mask Two DACRO
132. and timer 1 It includes programming examples 13 1 Overview The timer module incorporates two independent general purpose 16 bit timers timer 0 and timer 1 The output of an 8 bit prescaler clocks each timer There are two sets of registers one for each timer The timers can operate from the system bus clock BCLKO or from an external clocking source using one of the TIN signals If BCLKO is selected it can be divided by 16 or 1 Figure 13 1 is a block diagram of one of the two identical ti5mer modules GENERAL PURPOSE TIMER System Bus Clock 1 or 16 f Timer Mode Register TMRn imer Prescaler Mode Bits ock Capture Detection Timer Counter TCNn contains incrementing value TOUT Timer Capture Register TCRn Timer Reference Register TRRn latches TCN value when triggered by TIN reference value for comparison with TCN Timer Event Register TERn indicates capture or when TCN TRRn Figure 13 1 Timer Block Diagram M MOTOROLA Chapter 13 Timer Module 13 1 General Purpose Timer Units 13 1 1 Key Features Each general purpose 16 bit timer unit has the following features Maximum period of 5 96 seconds at 45 MHz 27 nS resolution at 45 MHz Programmable sources for the clock input including external clock Input capture capability with programmable trigger edge on input pin Output compare with programmable mode for the output pin Free run and restart modes Maskable interrupts on input capture
133. are also controlled by these registers Memory areas defined for each block should not overlap operation is undefined for accesses in overlapping regions M MOTOROLA Chapter 11 Synchronous Asynchronous DRAM Controller Module 11 5 Asynchronous Operation 31 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 832 10 Field BA RE CAS RP RCD EDO PS PM Reset Unitialized 0 Unitialized R W R W Addr MBAR 0 10 DACRO 0x110 DACR1 Figure 11 3 DRAM Address and Control Registers DACRO DACR1 Table 11 4 describes DACRn fields Table 11 4 DACRO DACR1 Field Description Bits Name Description 31 18 BA Base address Used with DMR BAM to determine the address range in which the associated DRAM block is located Each BA bit is compared with the corresponding address of the bus cycle in progress If each bit matches or if bits that do not match are masked in the BAM the address selects the associated DRAM block 17 16 Reserved should be cleared 15 RE Refresh enable Determines whether the DRAM controller generates a refresh to the associated DRAM block DRAM contents are not preserved during hard reset or software watchdog reset 0 Do not refresh associated DRAM block Default at reset 1 Refresh associated DRAM block 14 Reserved should be cleared 13 12 CAS CAS timing Determines how long CAS is as
134. arithmetic operations when the result cannot be represented accurately in the destination register User mode The operating state of a processor used typically by application software In user mode software can access only certain control registers and can access only user memory space No privileged operations can be performed W Word A 16 bit data element Write through A cache memory update policy in which all processor write cycles are written to both the cache and memory M MOTOROLA Glossary of Terms and Abbreviations Glossary 15 Glossary 16 MCF5307 User s Manual M MOTOROLA A Accumulator ACC 2 28 Addressing mode summary 2 33 variant 5 5 Arbitration between masters 6 14 bus control 6 11 for internal transfers 6 12 B Baud rates calculating 14 19 Bus operation arbitration control 6 11 characteristics 18 2 control signals 18 1 data transfer back to back cycles 18 10 burst cycles line read bus 18 12 line transfers 18 12 line write bus 18 14 mixed port sizes 18 15 overview 18 11 cycle execution 18 4 cycle states 18 5 fast termination cycles 18 9 operation 18 3 read cycle 18 7 write cycle 18 8 errors 18 17 external master transfers general 18 21 two device arbitration protocol 18 25 two wire mode 18 25 features 18 1 interrupt exceptions 18 17 master park register 6 11 misaligned operands 18 16 reset master 18 34 overview 18 33 software watchdog 18 35 M MOTORO
135. be set either to a burst length of one or to not burst This allows bursting to be controlled by the MCF5307 instead The SDRAM mode register is written by setting the associated block s DACR IMRS First the base address and mask registers must be set to the appropriate configuration to allow the mode register to be set Note that improperly set DMR mask bits may prevent access to the mode register address Thus the user should determine the mapping of the mode register address to the MCF5307 address bits to find out if an access is blocked If the DMR setting prohibits mode register access the DMR should be reconfigured to enable the access and then set to its necessary configuration after the MRS command executes M MOTOROLA Chapter 11 Synchronous Asynchronous DRAM Controller Module 11 33 SDRAM Example The associated CBM bits should also be initialized After DACR IMRS is set the next access to the SDRAM address space generates the MRS command to that SDRAM The address of the access should be selected to place the correct mode information on the SDRAM address pins The address is not multiplexed for the MRS command The MRS access can be a read or write The important thing is that the address output of that access needs the correct mode programming information on the correct address bits Figure 11 24 shows the MRS command which occurs in the first clock of the bus cycle BCLKO 31 0 SRAS SCAS
136. being received is lost The command does not affect receiver status bits or other control registers If the UART module is programmed for local loop back or multidrop mode the receiver operates even though this command is selected If the receiver is already disabled the command has no effect 11 Reserved do not use 14 3 6 UART Receiver Buffers URBn The receiver buffers contain one serial shift register and three receiver holding registers which act as a FIFO RxD is connected to the serial shift register The CPU reads from the top of the stack while the receiver shifts and updates from the bottom when the shift register is full see Figure 14 20 RB contains the character in the receiver 7 0 Field RB Reset 0000 0000 R W Read only Address MBAR 0x1CC 0x20C Figure 14 7 UART Receiver Buffer URBO 14 3 7 UART Transmitter Buffers UTBn The transmitter buffers consist of the transmitter holding register and the transmitter shift register The holding register accepts characters from the bus master if channel s USRn TxRDY is set A write to the transmitter buffer clears TxRDY inhibiting any more characters until the shift register can accept more data When the shift register is empty it checks if the holding register has a valid character to be sent TxRDY 0 If there is a valid character the shift register loads it and sets USRn TxRDY again Writes to the transmitter buffer when
137. belr Dy lt ea gt x PST 0x1 PST 0x8 DD source PST 0x8 DD destination bra b w PST 0x5 bset imm lt ea gt x PST 0x1 PST 0x8 DD source PST 0x8 DD destination bset Dy lt ea gt x PST 0x1 PST 0x8 DD source PST 0x8 DD destination bsr b w PST 0x5 PST 0xB DD destination operand btst imm lt ea gt x PST 0x1 PST 0x8 DD source operand btst Dy lt ea gt x PST 0x1 PST 0x8 DD source operand clr b ea x PST 0x1 PST 0x8 DD destination operand clr ea x PST 0x1 PST 0xB DD destination operand clr w ea x PST 0x1 PST 0x9 DD destination operand M MOTOROLA Chapter 5 Debug Support 5 43 Processor Status DDATA Definition Table 5 22 PST DDATA Specification for User Mode Instructions Continued Instruction Operand Syntax PST DDATA cmp ea y Rx PST 0x1 PST 0xB DD source operand cmpi imm Dx PST 0x1 divs ea y Dx PST 0x1 PST DD source operand divs w ea y Dx PST 0x1 PST 0x9 DD source operand divu ea y Dx PST 0x1 PST 0xB DD source operand divu w ea y Dx PST 0x1 PST 0x9 DD source operand 1 Dy lt ea gt x PST 0 1 PST OxB DD source PST 0xB DD destination eori l imm Dx PST 0 1 ext Dx PST
138. bus cycle termination Whether the mode is synchronous or asynchronous determines signal control and termination To reduce complexity multiplexing is the same for both modes Table 11 6 shows the scheme for DRAM configurations This scheme works for symmetric configurations in which the number of rows equals the number of columns as well as asymmetric configurations in which the number of rows and columns are different Table 11 6 Generic Address Multiplexing Scheme Address Pin Row Address Column Address Notes Relating to Port Sizes 17 17 0 8 bit port only 16 16 1 8 and 16 bit ports only 15 15 2 14 14 3 13 13 4 12 12 5 11 11 6 10 10 7 9 9 8 17 17 16 32 bit port only 18 18 17 16 bit port only or 32 bit port with only 8 column address lines 19 19 18 16 bit port only when at least 9 column address lines are used 11 8 MCF5307 User s Manual M woronoLA Asynchronous Operation Table 11 6 Generic Address Multiplexing Scheme Continued Address Pin Row Address Column Address Notes Relating to Port Sizes 20 20 19 21 21 20 22 22 21 23 23 22 24 24 23 25 25 24 Note the following Each MCF5307 address bit drives both a row address and a column address bit As the user upgrades ADRAM corresponding MCF5307 address bits must be connected This multiplexing scheme allows various memory widths to be connected
139. bus signals on the rising edge of BCLKO 18 9 General Operation of External Master Transfers An external master asserts its hold signal such as HOLDREQ when it executes a bus cycle driving BG high and forcing the MCF5307 to hold all bus requests During an external master cycle the MCF5307 can provide memory control signals OE CS 7 0 BE BWE 3 0 RAS 1 0 CAS 3 0 and TA while the external master drives the address and data bus and other required bus control signals When the external master asserts TS or AS to the MCF5307 the beginning of a bus cycle is identified and the MCF5307 starts decoding the address driven M woronoLA Chapter 18 Bus Operation 18 21 General Operation of External Master Transfers Note the following regarding external master accesses For MCF5307 to assert a CSx during external master accesses CSMRn AM must be set External master hits use the corresponding CSCRz settings for auto acknowledge byte enables and wait states See Section 10 4 1 3 Chip Select Control Registers CSCRO CSCR7 e To enable DRAM control signals during external master accesses DCMRn AM must be set During external master bus cycles either TS or AS but not both should be driven to the MCF5307 Driving both during a bus cycle causes indeterminate results External master transfers that use the MCF5307 to drive memory control signals and TA are like normal MCF5307 transfers Figure 18 24 sh
140. command it continues until any character in the transmitter shift register is completely sent If the transmitter is reset through a software command operation stops immediately see Section 14 3 5 UART Command Registers UCRn The transmitter is reenabled through the to resume operation after a disable or software reset If the clear to send operation is enabled CTS must be asserted for the character to be transmitted If CTS is negated in the middle of a transmission the character in the shift register is sent and TxD remains in mark state until CTS is reasserted If the transmitter is forced to send a continuous low condition by issuing a SEND BREAK command the transmitter ignores the state of CTS If the transmitter is programmed to automatically negate RTS when a message transmission completes RTS must be asserted manually before a message is sent In applications in which the transmitter is disabled after transmission is complete and RTS is appropriately programmed RTS is negated one bit time after the character in the shift register is completely transmitted The transmitter must be manually reenabled by reasserting RTS before the next message is to be sent Figure 14 21 shows the functional timing information for the transmitter M MOTOROLA Chapter 14 UART Modules 14 21 Operation C1 in transmission TxD ci T T T rd C2 C3 4 C6 Transmitter
141. configured as general purpose I O Table 15 1 summarizes MCF5307 parallel port pins described in detail in Chapter 17 Signal Descriptions M MOTOROLA Chapter 15 Parallel Port General Purpose I O 15 1 Parallel Port Operation Table 15 1 Parallel Port Pin Descriptions Pin Description 15 8 MSB of the address bus parallel port Programmed through PAR 15 8 If a PAR bit is 0 the associated A 31 24 pin functions as a parallel port signal If a bit is 1 the pin functions as an address bus signal If all pins are address signals as much as 4 Gbytes of memory space are available TIP PP7 Transfer in progress output parallel port bit 7 Programmed through PAR 7 Assertion indicates a bus transfer is in progress negation indicates an idle bus cycle if the bus is still granted to the processor Note that TIP is held asserted on back to back bus cycles DREQ 1 0 DMA request inputs two bits of the parallel port Programmed through PAR 6 5 These inputs are PP 6 5 asserted by a peripheral device to request a DMA transfer TM 2 0 Transfer type outputs parallel port bits 4 2 Programmed through PAR 4 2 For DMA transfers these PP 4 2 signals provide acknowledge information For emulation transfers TM 2 0 indicate user or data transfer types For CPU space transfers TM 2 0 are low For interrupt acknowledge transfers TM 2 0 carry the interrupt level being acknowledged TT 1 0 Transfer
142. control serial data flow Figure 14 18 shows a signal configuration for a UART RS 232 interface UART RS 232 Transceiver JJ Qo T T c 012 9 002 TxD 011 RxD 001 Figure 14 18 UART RS 232 Interface M MOTOROLA Chapter 14 UART Modules 14 17 Operation 14 5 Operation This section describes operation of the clock source generator transmitter and receiver 14 5 1 Transmitter Receiver Clock Source BCLKO serves as the basic timing reference for the clock source generator logic which consists of a clock generator and a programmable 16 bit divider dedicated to the UART The clock generator cannot produce standard baud rates if BCLKO is used so the 16 bit divider should be used 14 5 1 1 Programmable Divider As Figure 14 19 shows the UART transmitter and receiver can use the following clock sources Anexternal clock signal on the TIN pin that can be divided by 16 When not divided TIN provides a synchronous clock mode when divided by 16 it is asynchronous e BCLKO supplies an asynchronous clock source that is divided by 32 and then divided by the 16 bit value programmed in UDUn and UDLx See Section 14 3 11 UART Divider Upper Lower Registers UDUn UDLn The choice of TIN or BCLKO is programmed in the UCSR Timer Module UART Clocking sources programmed in UCSR TOUT TIN x1 Prescaler TxD Tx Buff
143. data gt MACSR lt data gt MASK MOVE from CCR Dx W CCR Dx CCR MOVE to Dy CCR Dy CCR lt data gt CCR lt data gt CCR MOVEA lt ea gt y Ax W L L Source destination 2 38 MCF5307 User s Manual M woronoLA Instruction Set Summary Table 2 7 User Mode Instruction Set Summary Continued Instruction Operand Syntax Operand Size Operation MOVEM lt list gt lt ea 2 gt x L Listed registers gt destination lt ea 2 gt y lt list gt Source listed registers MOVEQ lt data gt Dx B L Sign extended immediate data destination MSAC RxSF L CWx W L ACC Ry x Rx lt lt 1 gt gt 1 gt ACC L Lx L L MSACL Ry RxSF ea 1 yRw L x gt L L ACC Ry x lt lt 1 gt gt 1 gt ACC L Lx L L L lt ea 1 gt y amp MASK Rw MULS ea y Dx WX W gt L Source x destination destination LX L L Signed operation MULU lt ea gt y Dx Source x destination destination LX L L Unsigned operation NEG Dx 0 destination destination NEGX Dx JL 0 destination X destination NOP none Unsized Synchronize pipelines PC 2 PC NOT Dx L Destination gt destination OR lt ea gt y Dx iL Source destination destination Dy lt ea gt x ORI lt data gt Dx L Immediate data destination gt destination PEA lt ea 3 gt y L SP 4
144. define attributes for two user defined memory regions Attributes include definition of cache mode write protect and buffer write enables See Section 4 10 2 Access Control Registers ACRO ACR1 2 2 2 5 RAM Base Address Register RAMBAR The RAMBAR register determines the base address location of the internal SRAM module and indicates the types of references mapped to it The RAMBAR includes a base address write protect bit address space mask bits and an enable The RAM base address must be aligned on a 0 modulo 32 Kbyte boundary See Section 4 4 1 SRAM Base Address Register RAMBAR 2 2 2 6 Module Base Address Register MBAR The module base address register MBAR defines the logical base address for the memory mapped space containing the control registers for the on chip peripherals See Section 6 2 2 Module Base Address Register MBAR 2 3 Integer Data Formats Table 2 4 lists the integer operand data formats Integer operands can reside in registers memory or instructions The operand size for each instruction is either explicitly encoded in the instruction or implicitly defined by the instruction operation Table 2 4 Integer Data Formats Operand Data Format Size Bit 1 bit Byte integer 8 bits Word integer 16 bits Longword integer 32 bits 2 4 Organization of Data in Registers The following sections describe data organization within the data address and control register
145. defined by destinationOffset The bytesToMove must be a multiple of 16 For best performance source and destination SRAM addresses should be line aligned 0 modulo 16 copyToCpuRam src destinationOffset bytesToMove 20 destinationOffset 24 bytesToMove RAMBASE EQU 0x20000000 SRAM base address RAMF LAGS EQU 0x00000035 RAMBAR valid mask bits 1 1 12 a7 a7 allocate temporary space movem 1 0x1c a7 Store D2 D3 D4 registers Stack arguments and locations 0 saved d2 4 saved d3 8 saved d4 s PIZ returnPc 16 pointer to source operand move l define RAMBAR contents movec 1 a0 rambar load it move l 16 a7 a0 load argument defining src 1 1 RAMBASE al memory pointer to RAM base add 1 20 a7 al include destinationOffset M MOTOROLA Chapter 4 Local Memory 4 5 Power Management move l 24 a7 d4 load byte count asr l 4 4 divide by 16 to convert to loop count align 4 force loop on 0 mod 4 address loop movem 1 a0 0xf read 16 bytes from source movem 1 0xf al store into RAM destination lea l 16 a0 a0 increment source pointer lea l 16 al al increment destination pointer subq 1 1 94 decrement loop counter bne b loop if done then exit else continue movem 1 a7 0x1c restore d2 d3 d4 registers 1 1 12 7 7 deallocate temporary space rts 4 6 Power Management Because processor memory reference
146. device releases control of the bus by asserting BG to the MCF5307 At this point there is an internal access pending so the MCF5307 asserts BD during C4 and begins the access Thus the MCF5307 becomes the explicit external bus master Also during C4 the external device removes the grant from the MCF5307 by negating BG As the current bus master the MCF5307 continues to assert BD until the current transfer completes Because BG is negated the MCF5307 negates BD during C9 and three states the external bus thereby returning external bus mastership to the external device 18 26 MCF5307 User s Manual M woronoLA General Operation of External Master Transfers C1 C2 C3 C4 C5 C6 C7 C8 C9 BCLKO A 31 0 TT 1 0 sin e TWO Hn x R W Implicit Explicit Mastership Mastership External Master MCF5307 Figure 18 28 Two Wire Implicit and Explicit Bus Mastership In Figure 18 28 the external device is master during C1 and C2 It releases bus control in C3 by asserting BG to the MCF5307 During C4 and C5 the MCF5307 is implicit master because no internal access is pending In C5 an internal bus request becomes pending causing the MCF5307 to become explicit bus master in C6 by asserting BD In C7 the external device removes the bus grant to the MCF5307 The MCF5307 does not release the bus the MCF5307 continues to assert BD until the t
147. else is omitted the instruction performs no operation Refer to the Bcc instruction description else as an example lt operations gt Subfields and Qualifiers Optional operation Identifies an indirect address dn Displacement value n bits wide example d4g is a 16 bit displacement Address Calculated effective address pointer Bit Bit selection example Bit 3 of DO Isb Least significant bit example Isb of DO LSB Least significant byte LSW Least significant word msb Vost significant bit MSB Vost significant byte MSW Most significant word xxxviii MCF5307 User s Manual M woronoLA Table ii Notational Conventions Continued Terminology and Notational Conventions Instruction Operand Syntax Condition Code Register Bit Names C Carry N Negative V Overflow X Extend Z Zero MOTOROLA AboutThis Book Xxxix Terminology and Notational Conventions xl MCF5307 User s Manual M MOTOROLA Chapter 1 Overview This chapter is an overview of the MCF5307 ColdFire processor It includes general descriptions of the modules and features incorporated in the MCF5307 1 1 Features The MCF5307 integrated microprocessor combines a V3 ColdFire processor core with the following components as shown in Figure 1 1 8 Kbyte unified cache 4 Kbyte on chip SRAM Integer fractional multiply accumulate MAC unit Divide unit System debug interface DRAM controller for synchronous
148. enable 3 0 Byte write enable 3 0 Chip select O 17 16 BG Bus grant Bus arbitration 17 12 BR Bus request Bus arbitration O 17 12 CAS 3 0 Column address strobe DRAM 17 16 CLKIN Clock input Clock reset 17 13 CS 7 0 Chip selects 7 0 UART O 17 16 CTS 1 0 Clear to send Serial module 17 18 DDATA 3 0 Debug data Debug 17 20 Clock Reset 17 15 DRAMW DRAM write DRAM O 17 17 DREQ 1 0 DMA request DMA 17 18 D 31 0 Data Bus VO 17 8 EDGESEL Sync edge select DRAM 17 17 Clock Reset 17 15 HIZ High impedance Debug 17 20 TRQ7 IRQS Interrupt request Interrupt control 17 12 IRQ3 IRQ1 MTMODJ3 0 Motorola test mode Debug 17 20 Output enable Chip select O 17 16 PP 15 0 Parallel port Parallel port VO 17 19 PSTCLK Processor clock out Debug 17 20 PST 0 Processor status Debug 17 20 PS CONFIG 1 0 Port size configuration Clock reset 17 14 R W Read Write Bus VO 17 8 RAS 1 0 Row address strobe DRAM O 17 16 RSTI Reset In Clock reset 17 13 RSTO Reset Out Clock reset 17 13 RTS 1 0 Request to send Serial module 17 18 RxD 1 0 Receive data Serial module 17 18 SCAS Synchronous column address strobe DRAM 17 17 SCKE Synchronous clock enable DRAM 17 17 SCL Serial clock line PC VO 17 19 SDA Serial data line PC VO 17 19 SIZ 1 0 Size Bus VO 17 8 17 6 MCF5307 User s Manual M MCF5307 Bus Signals Table 17 2 MCF507 Alphabetical Signal Index Continued
149. follows The pin assignment register PAR selects the function of the 16 multiplexed pins e Port A data direction register PADDR determines whether pins configured as parallel port signals are inputs or outputs The Port A data register PADAT shows the status of the parallel port signals The operations of the PAR PADDR and PADAT are described in the following sections 15 1 1 Pin Assignment Register PAR The pin assignment register PAR which is part of the system integration module SIM defines how each PAR bit determines each pin function as shown in Figure 15 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field PAR15 PAR 14 PAR 13 PAR12 PAR11 PAR10 PAR9 PAR8 PAR7 PAR6 PARS PARA PAR3 PAR1 PARO PAR n 0 PP15 14 PP13 PP12 11 PP10 PP8 PP7 PP6 PP5 PP4 PP3 PP2 PP1 PPO PAR n 1 A31 A30 29 A28 A27 26 A25 A24 TIP DREQO DREQI 2 1 TMO TT1 TTO Reset Determined by driving D4 ADDR_CONFIG with a 1 or 0 when RSTI negates The system is configured as PP 15 0 if D4 is low otherwise alternate pin functions selected by PAR n 1 are used R W R W Address Address MBAR 0x004 Figure 15 1 Parallel Port Pin Assignment Register PAR If PP 9 8 A 25 24 are unavailable because A 25 0 are needed for external addressing PP 15 10 A 31 26 can be
150. if UACRn IEC is enabled 0 The current state of the CTS input is asserted 1 The current state of the CTS input is negated 14 3 9 UART Auxiliary Control Register UACRn The UART auxiliary control registers UACRn Figure 14 7 control the input enable 14 12 MCF5307 User s Manual M woronoLA Register Descriptions Field IEC Reset 0000 0000 R W Write only Address MBAR 0x1D0 UACRO 0x210 UACR1 Figure 14 10 UART Auxiliary Control Register UACRn Table 14 8 describes UACRn fields Table 14 8 UACRn Field Descriptions Bits Name Description 7 1 Reserved should be cleared 0 IEC Input enable control 0 Setting the corresponding UIPCRn bit has no effect on UISRn COS 1 UISRn COS is set and an interrupt is generated when the UIPCRn COS is set by an external transition on the CTS input if UIMRn COS 1 14 3 10 UART Interrupt Status Mask Registers UISRn UIMRn The UART interrupt status registers UISRn Figure 14 11 provide status for all potential interrupt sources UISRn contents are masked by UIMRz If corresponding UISRn and UIMRz bits are set the internal interrupt output is asserted If a UIMRn bit is cleared the state of the corresponding UISR7 bit has no effect on the output NOTE True status is provided in the UISRn regardless of UIMRn settings UISRn is cleared when the UART module is reset
151. in Part III ADC Analog to digital conversion Table Ill i Acronyms and Abbreviated Terms BIST Built in self test s S e ojo lt O PLL Phase locked loop Most significant bit Ii MCF5307 User s Manual M woronoLA Table Ill i Acronyms and Abbreviated Terms Continued M Part Ill Peripheral Module IIl ii IIl iv MCF5307 User s Manual M Chapter 12 DMA Controller Module This chapter describes the MCF5307 DMA controller module It provides an overview of the module and describes in detail its signals and registers The latter sections of this chapter describe operations features and supported data transfer modes in detail 12 1 Overview The direct memory access DMA controller module provides an efficient way to move blocks of data with minimal processor interaction The DMA module shown in Figure 12 1 provides four channels that allow byte word or longword operand transfers Each channel has a dedicated set of registers that define the source and destination addresses SARn and DARn byte count and control and status DCRn and DSRn Transfers can be dual or single address to off chip devices or dual address to on chip devices such as UART SDRAM controller and parallel port
152. into memory In imprecise mode the FIFO store buffer can defer pending writes to maximize performance The store buffer can support as many as four entries 16 bytes maximum for this purpose Data writes destined for the store buffer cannot stall the core The store buffer effectively provides a measure of decoupling between the pipeline s ability to generate writes one per cycle maximum and the external bus s ability to retire those writes In imprecise mode writes stall only if the store buffer is full and a write operation is on the internal bus The internal write cycle is held stalling the data execution pipeline If the store buffer is not used that is store buffer disabled or cache inhibited precise mode external bus cycles are generated directly for each pipeline write operation The instruction is held in the pipeline until external bus transfer termination is received Therefore each write is stalled for 5 cycles making the minimum write time equal to 6 cycles when the store buffer is not used See Section 2 1 2 2 Operand Execution Pipeline The store buffer enable bit CACR ESB controls the enabling of the store buffer This bit can be set and cleared by the MOVEC instruction ESB is zero at reset and all writes are performed in order precise mode ACRn CM or CACR DCM generates the mode used when ESB is set Cacheable write through and cache inhibited imprecise modes use the store buffer The store buffer
153. lt ea gt x PST 0x1 PST 0xB DD destination 2 movem lt ea gt y list PST 0 1 PST 0xB DD source 2 moveq imm Dx PST 0x1 msac Ry Rx PST 0 1 msac Ry Rx ea Rw PST 0x1 PST DD source PST 0xB DD destination msac w Ry Rx PST 0 1 msac w Ry Rx ea Rw PST 0x1 PST 0xB DD source PST 0xB DD destination muls ea y Dx PST 0x1 PST 0xB DD source operand muls w ea y Dx PST 0x1 PST 0x9 DD source operand mulu ea y Dx PST 0x1 PST 0xB DD source operand mulu w ea y Dx PST 0x1 PST 0x9 DD source operand 1 PST 0 1 1 PST 0 1 PST 0 1 not I Dx PST 0 1 or ea y Dx PST 0x1 PST 0 DD source operand or l Dy lt ea gt x PST 0 1 PST DD source PST 0xB DD destination ori l imm Dx PST 0x1 pea lt ea gt y PST 0x1 PST 0xB DD destination operand pulse PST 0x4 rems l lt ea gt y Dx Dw PST 0x1 PST 0xB DD source operand remu l lt ea gt y Dx Dw PST 0x1 PST 0xB DD source operand rts PST 0x1 PST 0xB DD source operand PST 0x5 PST 0x9AB DD target address Scc Dx PST 0x1 sub I ea y Rx PST 0 1 PST 0xB DD source operand sub Dy lt ea gt x PST 0 1 PST DD source PST 0xB DD destination subi I imm Dx PST 0 1 subq imm lt ea gt x PST 0 1 PST DD source PST
154. masters cannot access MCF5307 on chip memories or MBAR but they can access DRAM controller registers M MOTOROLA Chapter 11 Synchronous Asynchronous DRAM Controller Module 11 3 Asynchronous Operation 11 3 Asynchronous Operation The DRAM controller supports asynchronous DRAMs for cost effective systems Typical access times for the DRAM controller interfacing to ADRAM are 4 3 3 3 The DRAM controller supports the following four asynchronous modes e Non page mode Burst page mode Continuous page mode e Extended data out mode In asynchronous mode RAS and CAS always transition at the falling clock edge As summarized previously operation and timing of each ADRAM block is controlled by separate registers but refresh is the same for both All ADRAM accesses should be terminated by the DRAM controller There is no priority encoding between memory blocks so programming blocks to overlap with other blocks or with other internal resources causes undefined behavior 11 3 1 DRAM Controller Signals in Asynchronous Mode Table 11 2 summarizes DRAM signals used in asynchronous mode Table 11 2 SDRAM Signal Summary Signal Description RAS 1 0 Row address strobes Interface to RAS inputs on industry standard ADRAMs When SDRAMs are used these signals interface to the chip select lines within an SDRAM s memory block Thus there is one RAS line for each of the two blocks 5 3 0 Column address strobes Interfac
155. memories are connected to the address bus The memory sizes show what DRAM size is accessed if the corresponding bits are connected to the memory In each case there is a base memory size This limitation exists to allow simple page mode multiplexing Notice also that MCF5307 pin 17 is treated differently in byte wide operations In byte wide operations address bits 16 and 17 are driven on MCF5307 physical address pins 16 and 17 rather than the two bits being driven solely on A17 as they are for 32 wide memories M MOTOROLA Chapter 11 Synchronous Asynchronous DRAM Controller Module 11 9 Asynchronous Operation Table 11 7 DRAM Addressing for Byte Wide Memories Mores Adress pin Ades Bit Mor Memory size 17 17 0 Base memory size of 16 16 1 256 Kbytes 15 15 2 14 14 3 13 13 4 12 12 5 11 11 6 10 10 7 9 9 8 19 19 18 1 Mbyte 21 21 20 4 Mbytes 23 23 22 16 Mbytes 25 25 24 64 Mbytes Note that in Table 11 8 MCF5307 pin A19 is not connected because DRAM address bit 18 is already provided on MCF5307 pin A18 thus the next MCF5307 pin used should be A20 Table 11 8 DRAM Addressing for 16 Bit Wide Memories Mores Adress Pin NOES Airs Bit Addresa emery Sz 16 16 1 Base memory size of 15 15 2 128 Kbytes 14 14 3 13 13 4 12 12 5 11 11 6 10 10 7 9 9 8 18 18 17 512 Kbytes 20 20 19 2
156. new address and asserts SCAS every clock for as long as accesses are in that page In burst page mode there are multiple read or write operations for every ACTV command in the SDRAM if the requested transfer size exceeds the port size of the associated SDRAM The primary cycle of the transfer generates the ACTV and READ or WRITE commands secondary cycles generate only READ or WRITE commands As soon as the transfer completes the PALL command is generated to prepare for the next access Note that in synchronous operation burst mode and address incrementing during burst cycles are controlled by the MCF5307 DRAM controller Thus instead of the SDRAM enabling its internal burst incrementing capability the MCF5307 controls this function This means that the burst function that is enabled in the mode register of SDRAMs must be disabled when interfacing to the MCF5307 Figure 11 18 shows a burst read operation In this example DACR CASL 01 for an SRAS to SCAS delay tgcp of 2 BCLKO cycles Because tpcp is equal to the read CAS M MOTOROLA Chapter 11 Synchronous Asynchronous DRAM Controller Module 11 27 Synchronous Operation latency SCAS assertion to data out this value is also 2 BCLKO cycles Notice that NOPs are executed until the last data is read A PALL command is executed one cycle after the last data transfer ms RASI0 1 X 2 amp
157. of SDA during the acknowledge bit of a bus cycle 0 An acknowledge signal was received after the completion of 8 bit data transmission on the bus 1 No acknowledge signal was detected at the ninth clock M MOTOROLA Chapter 8 Module 8 9 Pc Programming Examples 8 5 5 12 Data I O Register 1208 In master receive mode reading the I2DR Figure 8 9 allows a read to occur and initiates next byte data receiving In slave mode the same function is available after it is addressed 7 6 5 4 3 2 1 0 Field D Reset 0000 0000 R W Read Write Address MBAR 0x290 Figure 8 9 1 C Data I O Register I2DR 8 6 12 Programming Examples The following examples show programming for initialization signalling START post transfer software response signalling STOP and generating a repeated START 8 6 1 Initialization Sequence Before the interface can transfer serial data registers must be initialized as follows 1 Set IFDR IC to obtain SCL frequency from the system bus clock See Section 8 5 2 2 Frequency Divider Register IFDR 2 Update the IADR to define its slave address 3 Set DCR IEN to enable the bus interface system 4 Modify the I2CR to select master slave mode transmit receive mode and interrupt enable or not NOTE If IBSR IBB when the bus module is enabled execute the following code sequence before proceeding with normal initialization code This issues
158. on chip peripherals MCF5307 User s Manual M woronoLA Programming Model Addressing Modes and Instruction Set 1 4 4 Instruction Set The ColdFire instruction set supports high level languages and is optimized for those instructions most commonly generated by compilers in embedded applications Table 2 8 provides an alphabetized listing of the ColdFire instruction set opcodes supported operation sizes and assembler syntax For two operand instructions the first operand is generally the source operand and the second is the destination Because the ColdFire architecture provides an upgrade path for 68K customers its instruction set supports most of the common 68K opcodes A majority of the instructions are binary compatible or optimized 68K opcodes This feature when coupled with the code conversion tools from third party developers generally minimizes software porting issues for customers with 68K applications M MOTOROLA Chapter 1 Overview 1 15 Programming Model Addressing Modes and Instruction Set 1 16 MCF5307 User s Manual M woronoLA Part MCF5307 Processor Core Intended Audience Part I is intended for system designers who need a general understanding of the functionality supported by the MCF5307 It also describes the operation of the MCF5307 Contents Chapter 2 ColdFire Core provides an overview of the microprocessor core of the MCF5307 The chapter begins with a description of enhancemen
159. on the falling edge of TCK when the TAP state machine is in Update IR state To load instructions into the shift portion of the register place the serial data on TDI before each rising edge of TCK The msb of the instruction shift register is the bit closest to the TDI pin and the Isb is the bit closest to TDO Table 19 2 describes customer usable instructions Table 19 2 JTAG Instructions Instruction Class IR Description EXTEST Required 000 Selects the boundary scan register Forces all output pins and bidirectional pins EXT configured as outputs to the preloaded fixed values with the SAMPLE PRELOAD instruction and held in the boundary scan update registers EXTEST can also configure the direction of bidirectional pins and establish high impedance states on some pins EXTEST becomes active on the falling edge of TCK in the Update IR state when the data held in the instruction shift register is equivalent to octal 0 IDCODE Optional 001 Selects the IDCODE register for connection as a shift path between TDI and IDC Interrogates the MCF5307 for version number and other part identification The IDCODE register is implemented in accordance with IEEE Standard 1149 1 so the Isb of the shift register stage is set to logic 1 on the rising edge of TCK following entry into the capture DR state Therefore the first bit shifted out after selecting the IDCODE register is always a logic 1 The remaining 31 bits are also
160. or MBAR they can access any of the SIM memory map and peripheral registers such as those belonging to the interrupt controller chip select module UARTS timers DMA and Table 6 1 SIM Registers MBAR Offset 31 24 23 16 15 8 7 0 0x000 Reset status register System protection Software watchdog Software watchdog RSR p 6 5 control register interrupt vector register service register SWSR SYPCR p 6 8 SWIVR p 6 9 p 6 9 0x004 Pin assignment register PAR p 6 10 Interrupt port Reserved assignment register IRQPAR p 9 7 0x008 PLL control PLLCR Reserved p 7 3 0 00 Default bus master park Reserved register MPARK p 6 11 0x010 Reserved 0x03C Interrupt Controller Registers p 9 2 0x040 Interrupt pending register IPR p 9 6 0x044 Interrupt mask register IMR p 9 6 0x048 Reserved Autovector register AVR p 9 5 Interrupt Control Registers ICRs p 9 3 MOTOROLA Chapter 6 SIM Overview 6 3 Programming Model Table 6 1 SIM Registers Continued Men 31 24 23 16 15 8 7 0 0x04C Software watchdog TimerO ICR1 p 9 3 Timer1 ICR2 p 9 3 ICR3 9 3 timer ICRO p 9 3 0x050 UARTO ICR4 p 9 3 UART1 ICR5 9 3 DMAO ICR6 p 9 3 1 ICR7 p 9 3 0x054 DMA2 ICR8 p 9 3 ICR9 p 9 3 Reserved 6 2 2 Module Base Addre
161. or equal to the current priority except the edge sensitive level 7 request which cannot be masked 7 0 CCR Condition code register See Table 2 1 2 2 2 2 Vector Base Register VBR The VBR holds the base address of the exception vector table in memory The displacement of an exception vector is added to the value in this register to access the vector table VBR 19 0 are not implemented and are assumed to be zero forcing the vector table to be aligned on a 0 modulo 1 Mbyte boundary 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 54 3 2 1 0 Field Exception vector table base address Reset 0000 0000 0000 0000 0000 0000 0000 0000 R W Written from a BDM serial command or from the CPU using the MOVEC instruction VBR can be read from the debug module only The upper 12 bits are returned the low order 20 bits are undefined Re 11 0 0 801 Figure 2 6 Vector Base Register VBR 2 2 2 3 Cache Control Register CACR The CACR controls operation of both the instruction and data cache memory It includes bits for enabling freezing and invalidating cache contents It also includes bits for defining the default cache mode and write protect fields See Section 4 10 1 Cache Control Register CACR 2 30 MCF5307 User s Manual M woronoLA Integer Data Formats 2 2 2 4 Access Control Registers ACRO ACR 1 The access control registers ACRO ACR1
162. or reference compare 13 2 General Purpose Timer Units The general purpose timer units provide the following features Each timer can be programmed to count and compare to a reference value stored in a register or capture the timer value at an edge detected on TIN System bus clock can be divided by 16 or 1 This clock is input to the prescaler TIN is fed directly into the 8 bit prescaler The maximum value of TIN is 1 5 of CLKIN as described in Chapter 20 Electrical Specifications The 8 bit prescaler clock divides the clocking source and is user programmable from 1 to 256 Programmed events generate interrupts The timer output signal TOUT can be configured to toggle or pulse on an event 13 3 General Purpose Timer Programming Model The following features are programmable through the timer registers shown in Table 13 1 13 2 Prescaler The prescaler clock input is selected from BCLKO divided by 1 or 16 or from the corresponding timer input TIN TIN is synchronized to BCLKO The synchronization delay is between two and three BCLKO clocks The corresponding TMRnz ICLK selects the clock input source A programmable prescaler divides the clock input by values from 1 to 256 The prescaler is an input to the 16 bit counter Capture mode Each timer has a 16 bit timer capture register TCRO and TCR1 that latches the counter value when the corresponding input capture edge detector senses a defined TIN transition The captu
163. register write is complete M MOTOROLA Chapter 5 Debug Support 5 25 Background Debug Mode BDM 5 5 3 3 3 Read Memory Location READ Read data at the longword address Address space is defined by BAAR TT TM Hardware forces low order address bits to zeros for word and longword accesses to ensure that word addresses are word aligned and longword addresses are longword aligned Command Result Formats 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Byte 0 1 0 9 0 0 0 0 116 A 15 0 Result X X X X X X X X D 7 0 Word Command 0 1 0 9 0 4 0 0 A 31 16 A 15 0 Result D 15 0 Longword Command 0 1 0 9 0 8 0 0 31 16 15 0 Result D 31 16 D 15 0 Figure 5 22 READ Command Result Formats Command Sequence READ 7 READ B W MS ADDR LS ADDR MEMORY 21 READY READY LOCATION 27 READY _ CNEXT CMD XXX NEXT CMD BERR NOT READY READ 2 READ LONG MS ADDR ERADDR S MEMORY 1 READY READY LOCATION N NWOT READY XXX NEXT CMD MS RESULT LS RESULT XXX NEXT CMD BERR NOT READY Figure 5 23 READ Command Sequence Operand Data The only operand is the longword address of the requested location Result Data Word results return 16 bits of data longword results return 32 Bytes are returned in the LSB of a word result the upper byte is undefined
164. reserved for expansion Write accesses to these reserved address spaces and reserved register bits have no effect Table A 4 DRAM Controller Registers oe 31 24 23 16 15 8 7 0 0x100 DRAM control register DCR p 11 3 Reserved 0x104 Reserved 0x108 DRAM address and control register 0 DACRO p 11 3 0x10C DRAM mask register block 0 DMRO p 11 3 0x110 DRAM address and control register 1 DACR1 11 3 0x114 DRAM mask register block 1 DMR1 p 11 3 M MOTOROLA Appendix A List of Memory Maps A 3 Table A 5 General Purpose Timer Registers MBAR Offset 31 24 23 16 15 8 7 0 0x140 Timer 0 mode register TMRO p 13 3 Reserved 0x144 Timer 0 reference register TRRO p 13 4 Reserved 0x148 Timer 0 capture register TCRO p 13 4 Reserved 0x14C Timer 0 counter TCNO p 13 5 Reserved 0x150 Reserved Timer 0 event register Reserved TERO p 13 5 0x180 Timer 1 mode register TMR1 p 13 3 Reserved 0x184 Timer 1 reference register TRR1 p 13 4 Reserved 0x188 Timer 1 capture register TCR1 p 13 4 Reserved 0x18C Timer 1 counter TCN1 p 13 5 Reserved 0x190 Reserved Timer 1 event register Reserved TER1 p 13 5 Table A 6 UARTO Module Programming Model MBAR 4 Offset 31 24 23 16 15 8 7 0 0x1C0 UART mode registers
165. s mode register UMR17 status is provided in character or block modes USRn RxRDY is set when at least one character is available to be read by the CPU A read of the receiver buffer produces an output of data from the top of the FIFO stack After the read cycle the data at the top of the FIFO stack and its associated status bits are popped and the receiver shift register can add new data at the bottom of the stack The FIFO full status bit FFULL is set if all three stack positions are filled with data Either the RxRDY or FFULL bit can be selected to cause an interrupt The two error modes are selected by UMR1n ERR as follows In character mode UMR 1n ERR 0 status is given in the USR for the character at the top of the FIFO e In block mode the USRz shows a logical OR of all characters reaching the top of the FIFO stack since the last RESET ERROR STATUS command Status is updated as characters reach the top of the FIFO stack Block mode offers a data reception speed advantage where the software overhead of error checking each character cannot be tolerated However errors are not detected until the check is performed at the end of an entire message the faulting character is not identified In either mode reading the USR7 does not affect the FIFO The FIFO is popped when the receive buffer is read The USRn should be read before reading the receive buffer If all three receiver holding registers are full a new characte
166. set to fixed values See Section 19 4 2 IDCODE Register IDCODE is the default value in the IR when a JTAG reset occurs by either asserting TRST or holding TMS high while clocking TCK through at least five rising edges and the falling edge after the fifth rising edge A JTAG reset causes the TAP state machine to enter test logic reset state normal operation of the TAP state machine into the test logic reset state also places the default value of octal 1 into the instruction register The shift register portion of the instruction register is loaded with the default value of octal 1 in Capture IR state and a TCK rising edge occurs SAMPLE Required 100 Provides two separate functions It obtains a sample of the system data and control PRELOAD signals at the MCF5307 input pins and before the boundary scan cell at the output SMP pins This sampling occurs on the rising edge of TCK in the capture DR state when an instruction encoding of octal 4 is in the instruction register Sampled data is observed by shifting it through the boundary scan register to TDO by using shift DR state The data capture and shift are transparent to system operation The users must provide external synchronization to achieve meaningful results because there is no internal synchronization between TCK and CLK SAMPLE PRELOAD also initializes the boundary scan register update cells before selecting EXTEST or CLAMP This is done by ignoring data shifted out of TDO whil
167. shows a write cycle followed by a read cycle in continuous page mode The read hits in the same page as the write so RAS is not negated before the second cycle Note that the row address does not appear on the pins for a bus cycle that hits in the page Column addresses are immediately multiplexed onto the pins The third bus cycle is a page miss so RAS is precharged before the end of the bus cycle and no extra precharge delay is incurred BCLKO A 31 0 X y Col mn Column Row y Column Pag Miss 5 1 or 0 stage re e CAS 3 0 DRAMW IN ip oli a D 31 0 RS _ Bus Cycle 1 Bus Cycle 2 lt Bus Cycle 3 Figure 11 9 Continuous Page Mode Operation If a write cycle hits in the page CAS must be delayed by one clock to allow data to become valid as shown in Figure 11 10 11 14 MCF5307 User s Manual M woronoLA Asynchronous Operation BCLKO X em X Sm X X Colurm Page Hit RAS 1 or 0 CAS 3 0 DRAMW D 31 0 lt lt Bus Cycle 1 lt Bus Cycle 2 Figure 11 10 Write Hit Continuous Page Mode 11 3 3 4 Extended Data Out EDO Operation EDO is a variation of page mode that allows the DRAM to continue drivi
168. stop signal generation detection Repeated START signal generation M MOTOROLA Chapter 8 Module 8 1 Interface Features e Acknowledge bit generation detection e Bus busy detection Figure 8 1 is a block diagram of the module Internal Bus IRQ Address Data A Registers and ColdFire Interface Y Address Decode 3 Data MUX ne Frequency Control Status Data Address Divider Register Register Register Register Register IFDR 12 I2SR 1208 IADR E A E Y Y Clock gt moui Control Snit Start Stop egi ter and Arbitration Control Input gt Address Sync T Compare Y SCL SDA Figure 8 1 Module Block Diagram Figure 8 1 shows the relationships of the registers listed below address register IADR e PC frequency divider register IFDR e control register I2CR TC status register I2SR C data I O register These registers are described in Section 8 5 Programming Model 82 MCF5307 User s Manual M woronoLA System Configuration 8 3 12 System Configuration The IC module uses a serial data line SDA and a serial clock line SCL for data transfer For compliance all devices connected
169. the system external circuitry should assert RSTI for a minimum of 80 CLKIN cycles after Vcc is within tolerance Figure 18 33 is a functional timing diagram of the master reset operation showing relationships among Vcc RSTI mode selects and bus signals CLKIN must be stable by the time Vcc reaches the minimum operating specification CLKIN should start oscillating as Vcc is ramped up to clear out contention internal to the MCF5307 caused by the random states of internal flip flops on power up RSTI is internally synchronized for two CLKIN cycles before being used and must meet the specified setup and hold times in relationship to CLKIN to be recognized 100K CLKIN cycles gt 80 CLKIN cycles PLL lock time E T m RSTI RSTO Bus Signals Y li li li TTT G Figure 18 33 Master Reset Timing During the master reset period all signals capable of being three stated are driven to a high impedance all others are negated When RSTI negates all bus signals remain in a high impedance state until the MCF5307 is granted the bus and the core begins the first bus cycle for reset exception processing A master reset causes any bus cycle including DRAM refresh cycle to terminate and initializes registers appropriately for a reset exception Note that during reset D 7 0 are sampled on the negating
170. the channel s TXRDY 0 and when the transmitter is disabled have no effect on the transmitter buffer Figure 14 8 shows UTBO TB contains the character in the transmitter buffer MOTOROLA Chapter 14 UART Modules 14 11 Register Descriptions 7 0 Field TB Reset 0000 0000 R W Write only Address MBAR 0x1CC 0x20C Figure 14 8 UART Transmitter Buffer UTBO 14 3 8 UART Input Port Change Registers UIPCRn The input port change registers UIPCRn Figure 14 9 hold the current state and the change of state for CTS 7 5 4 3 1 0 Field COS 111 CTS Reset 0000 0 11 CTS R W Read only Address MBAR 0x1D0 UIPCRO 0x210 UIPCR1 Figure 14 9 UART Input Port Change Register UIPCRn Table 14 7 describes UIPCRn fields Table 14 7 UIPCRn Field Descriptions Bits Name Description 7 5 Reserved should be cleared 4 COS Change of state high to low or low to high transition 0 No change of state since the CPU last read UIPCRn Reading UIPCRn clears UISRn COS 1 A change of state longer than 25 50 us occurred on the CTS input UACRn can be programmed to generate an interrupt to the CPU when a change of state is detected 3 1 Reserved should be cleared 0 CTS Current state Starting two serial clock periods after reset CTS reflects the state of CTS If CTS is detected asserted at that time COS is set which initiates an interrupt
171. the rising edge of the BCLKO in which the last TA is asserted Note that the MCF5307 treats any series of burst or a burst inhibited transfers as a single bus cycle and does not release the bus until the last transfer of the series completes When the MCF5307 is granted the bus after it asserts BR one of two things can occur If the MCF5307 has an internal bus request pending it asserts BD indicating explicit bus mastership and begins the pending bus cycle by asserting TS The MCF5307 continues to assert BD until the external bus arbiter negates BG after which BD is negated at the completion of the bus cycle As long as BG is asserted BD remains asserted to indicate that the MCF5307 is bus master and the MCF5307 continuously drives the address bus attributes and control signals If no internal request is pending the MCF5307 takes implicit bus mastership It does not drive the bus and does not assert BD if the bus has an implicit master If an internal bus request is generated the MCF5307 assumes explicit bus mastership and immediately begins an access and asserts BD Figure 18 30 shows implicit and explicit bus mastership due to generation of an internal bus request M MOTOROLA Chapter 18 Bus Operation 18 29 General Operation of External Master Transfers C1 C2 4 5 C6 C7 C8 C9 BCLKO X m5 T Im
172. the system stack is always written with a value of 4 5 6 7 by the processor indicating a 2 longword frame format See Table 2 19 This field records any longword misalignment of the stack pointer that may have existed when the exception occurred Table 2 19 Format Field Encoding Original A7 at Time of A7 at First Instruction of Format Field Bits Exception Bits 1 0 Handler 31 28 00 Original A 7 8 0100 01 Original A 7 9 0101 10 Original A 7 10 0110 11 Original A 7 11 0111 Fault status field The 4 bit field FS 3 0 at the top of the system stack is defined for access and address errors along with interrupted debug service routines See Table 2 20 M MOTOROLA Chapter 2 ColdFire Core 2 49 Exception Processing Overview Table 2 20 Fault Status Encodings FS 3 0 Definition 0000 Not an access or address error 0001 001x Reserved 0100 Error on instruction fetch 0101 011x Reserved 1000 Error on operand write 1001 Attempted write to write protected space 101x Reserved 1100 Error on operand read 1101 111x Reserved e Vector number This 8 bit field vector 7 0 defines the exception type It is calculated by the processor for internal faults and is supplied by the peripheral for interrupts See Table 2 18 2 8 2 Processor Exceptions Table 2 21 describes MCF5307 exceptions Table 2 21 MCF5307 Exceptions Except
173. to 4 Gbyte memory block sizes Programmable wait states and port sizes e External master access to chip selects 10 2 Chip Select Module Signals Table 10 1 lists signals used by the chip select module Table 10 1 Chip Select Module Signals Signal Description Chip Selects Each CSn can be independently programmed for an address location as well as for masking port CS 7 0 size read write burst capability wait state generation and internal external termination Only CSO is initialized at reset when it acts as a global chip select that allows boot ROM to be at any defined address space Port size and termination internal versus external and byte enables for CSO are configured by the logic levels of D 7 5 when RSTI negates Output Interfaces to memory or to peripheral devices and enables a read transfer It is asserted and Enable OE negated on the falling edge of the clock OE is asserted only when one of the chip selects matches for the current address decode Byte Enables Byte Write Enables BE 3 0 BWEQ 3 0 These multiplexed signals are individually programmed through the byte enable mode bit CSCRn BEM described in Section 10 4 1 3 Chip Select Control Registers CSCRO CSCR7 These generated signals provide byte data select signals which are decoded from the transfer size A1 and AO signals in addition to the programmed port size and burstability of the memory accessed as
174. to the same location cached data is typically placed in the set whose cache line corresponding to that address was used least recently See Set associativity Set associativity Aspect of cache organization in which the cache space is divided into sections called sets The cache controller associates a particular main memory address with the contents of a particular set or region within the cache Slave The device addressed by a master device The slave is identified in the address tenure and is responsible for supplying or latching the requested data for the master during the data tenure Static branch prediction Mechanism by which software for example compilers can hint to the machine hardware about the direction a branch is likely to take Supervisor mode The privileged operation state of a processor In supervisor mode software typically the operating system can access all control registers and can access the supervisor memory space among other privileged operations MCF5307 User s Manual M woronoLA System memory The physical memory available to a processor Tenure A tenure consists of three phases arbitration transfer termination There can be separate address bus tenures and data bus tenures Throughput The measure of the number of instructions that are processed per clock cycle Transfer termination The successful or unsuccessful conclusion of a data transfer U Underflow A condition that occurs during
175. type outputs parallel port bits 1 0 Programmed through 1 0 PP 1 0 When the MCF5307 is bus master it outputs these signals They indicate the current bus access type 15 1 2 Port A Data Direction Register PADDR The PADDR determines the signal direction of each parallel port pin programmed as a general purpose I O port in the PAR 15 9 Field PADDR Reset 0000_0000_0000_0000 R W R W Address Address MBAR 0x244 Figure 15 2 Port A Data Direction Register PADDR Table 15 2 describes PADDR fields Table 15 2 PADDR Field Description Bits Name Description 15 0 PADDR Data direction bits Each data direction bit selects the direction of the signal as follows 0 Signal is defined as an input 1 Signal is defined as an output 15 1 3 Port A Data Register PADAT The PADAT value for inputs corresponds to the logic level at the pin for outputs the value corresponds to the logic level driven onto the pin Note the following e PADAT has no effect on pins not configured for general purpose I O e PADAT settings do not affect inputs PADAT bit values determine the corresponding logic levels of pins configured as outputs 15 2 MCF5307 User s Manual M woronoLA Parallel Port Operation e PADAT can be written to anytime A read from PADAT returns values of corresponding pins configured as general purpose I O in the PAR and designated as inputs by the PA
176. wake core 6 2 9 Pin Assignment Register PAR The pin assignment register PAR Figure 6 8 allows the selection of pin assignments 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field PAR15 PAR14 PAR13 PAR12 PAR11 PAR10 PAR9 PAR8 PAR7 PAR6 PARS PAR4 PARS PAR2 1 PARn 0 PP15 PP14 1 12 PP11 10 PP9 8 PP7 PP6 5 PP4 PP2 PP1 PPO PARn 1 A31 A30 29 A28 27 A26 A25 A24 TIP DREQO DREQM 2 TM1 TMO TT1 TTO Reset Determined by driving D4 ADDR_CONFIG with 1 or 0 when RSTI negates The system is configured as PP 15 0 if D4 is low otherwise alternate pin functions selected by PAR 1 are used R W R W Address Address MBAR 0x004 Figure 6 8 Pin Assignment Register PAR 6 10 MCF5307 User s Manual M woronoLA Programming Model 6 2 10 Bus Arbitration Control This section describes the bus arbitration register and the four arbitration schemes 6 2 10 1 Default Bus Master Park Register MPARK The MPARK shown in Figure 6 9 determines the default bus master arbitration between internal transfers core and DMA module and between internal and external transfers to internal resources This arbitration is needed because external masters can access internal registers within the MCF5307 peripherals Field Reset R W Address
177. way to return to asynchronous operation without resetting the processor 11 4 1 DRAM Controller Signals in Synchronous Mode Table 11 11 shows the behavior of DRAM signals in synchronous mode Table 11 11 Synchronous DRAM Signal Connections Signal Description SRAS Synchronous row address strobe Indicates a valid SDRAM row address is present and can be latched by the SDRAM SRAS should be connected to the corresponding SDRAM SRAS Do not confuse SRAS with the DRAM controller s RAS 1 0 which should not be interfaced to the SDRAM SRAS signals SCAS Synchronous column address strobe Indicates a valid column address is present and can be latched by the SDRAM SCAS should be connected to the corresponding signal labeled SCAS on the SDRAM Do not confuse SCAS with the DRAM controller s CAS 3 0 signals DRAMW DRAM read write Asserted for write operations and negated for read operations R gt S 1 0 Row address strobe Select each memory block of SDRAMs connected to the MCF5307 One RAS signal selects one SDRAM block and connects to the corresponding CS signals SCKE Synchronous DRAM clock enable Connected directly to the CKE clock enable signal of SDRAMs Enables and disables the clock internal to SDRAM When CKE is low memory can enter a power down mode where operations are suspended or they can enter self refresh mode SCKE functionality is controlled by DCR COC For designs using external multiplexing setti
178. while in user mode The ColdFire Violation Programmer s Reference Manual lists supervisor and user mode instructions 2 50 MCF5307 User s Manual M woronoLA Exception Processing Overview Table 2 21 MCF5307 Exceptions Continued Exception Description Trace Exception ColdFire processors provide instruction by instruction tracing While the processor is in trace mode SR T 1 instruction completion signals a trace exception This allows a debugger to monitor program execution The only exception to this definition is the STOP instruction If the processor is in trace mode the instruction before the STOP executes and then generates a trace exception In the exception stack frame the PC points to the STOP opcode When the trace handler is exited the STOP instruction is executed loading the SR with the immediate operand from the instruction The processor then generates a trace exception The PC in the exception stack frame points to the instruction after STOP and the SR reflects the just loaded value If the processor is not in trace mode and executes a STOP instruction where the immediate operand sets the trace bit in the SR hardware loads the SR and generates a trace exception The PC in the exception stack frame points to the instruction after STOP and the SR reflects the just loaded value Because ColdFire processors do not support hardware stacking of multiple exceptions it is the responsibility of the o
179. 0 Figure 18 21 Example of a Misaligned Longword Transfer 32 Bit Port If an operand is cacheable and is misaligned across a cache line boundary both lines are loaded into the cache The example in Figure 18 22 differs from the one in Figure 18 21 in that the operand is word sized and the transfer takes only two bus cycles 31 24 23 16 15 87 o A 2 0 Transfer 1 Byte 0 001 Transfer 2 Byte 0 100 Figure 18 22 Example of a Misaligned Word Transfer 32 Bit Port NOTE External masters using internal MCF5307 chip selects and default memory control signals must initiate aligned transfers 18 6 Bus Errors The MCF5307 has no bus monitor If the auto acknowledge feature is not enabled for the address that generates the error the bus cycle can be terminated by asserting TA or by using the software watchdog timer If it is required that the MCF5307 handle a bus error differently an interrupt handler can be invoked by asserting an interrupt to the core along with TA when the bus error occurs 18 7 Interrupt Exceptions A peripheral device uses the interrupt request signals IRQx to signal the core to take an interrupt exception when it needs the MCF5307 or is ready to send information to it The interrupt transfers control to an appropriate routine M Chapter 18 Bus Operation 18 17 Interrupt Exceptions The MCF5307 has the following two levels of interrupt
180. 0 050 ICR4 UARTO 0 051 ICR5 UART1 0x052 ICR6 DMAO MCF5307 User s Manual M MOTOROLA Interrupt Controller Registers Table 9 2 Interrupt Control Registers Continued MBAR Offset Register Name 0x053 ICR7 DMA1 0x054 ICR8 DMA2 0x055 ICR9 DMAS3 Internal interrupts are programmed to a level and priority Each internal interrupt has a unique ICR Each of the 7 interrupt levels has 5 priorities for a total of 35 possible priority levels encompassing internal and external interrupts The four external interrupt pins offer seven possible settings at a fixed interrupt level and priority The IRQPAR determines these settings for external interrupt request levels External interrupts can be programmed to supply an autovector or execute an external interrupt acknowledge cycle This is described in Section 9 2 2 Autovector Register AVR 9 2 1 Interrupt Control Registers ICRO ICR9 The interrupt control registers ICRO ICRO9 provide bits for defining the interrupt level and priority for the interrupt source assigned to the ICR shown in Table 9 2 7 6 5 4 3 2 1 0 Field AVEC IL IP Reset 0 0 00 00 R W R W Address MBAR 0x04C ICRO 0x04D ICR1 0x04E ICR2 0x04F ICR3 0x050 ICR4 0x051 ICR5 0x052 ICR6 0x053 ICR7 0x054 ICR8 0x055 ICR9 Figure 9 2 Interrupt Control Registers ICRO ICR9 Table 9 3 describes ICR fields Table 9 3 ICRn Field De
181. 0 which keeps auto refresh disabled because registers are being set up at this time 14 Reserved Don t care 13 12 CASL 00 Indicates a delay of data 1 cycle after CAS is asserted 11 Reserved Don t care 10 8 CBM 011 Command bit is pin 20 and bank selects are 21 and up 7 Reserved Don t care 6 IMRS 0 Indicates MRS command has not been initiated 5 4 PS 00 32 bit port 3 IP 0 Indicates precharge has not been initiated 11 36 MCF5307 User s Manual M MOTOROLA SDRAM Example Table 11 35 DACR Initialization Values Name Setting Description PM 1 Indicates continuous page mode Reserved Don t care 11 5 4 DMR Initialization In this example again only the second 512 Kbyte block of each 1 Mbyte space is accessed in each bank In addition the SDRAM component is mapped only to readable and writable supervisor and user data The DMRs have the following configuration Field Setting hex Field Setting hex 31 BAM 0 0 0 0 0 0 0 0 1 1 1 0 1 X X 0 0 7 4 15 9 8 7 6 5 4 3 2 1 0 AM SC SD UC UD V X X X X X X 0 X 1 1 1 0 1 0 1 0 0 7 5 Figure 11 28 DMRO Register With this configuration the DMRO 0x0074 0075 as described in Table 11 36 Table 11 36 DMRO Initialization Values Bits Name Setting Description 31 1
182. 0 00146 0 00218 0 00291 1 1 0 0466 0 06991 0 09321 0 00291 0 00437 0 00583 2 2 0 06991 0 10486 0 13981 0 00437 0 00655 0 00874 3 3 0 09321 0 13981 0 18641 0 00583 0 00874 0 01165 4 4 0 11651 0 17476 0 23302 0 00728 0 01092 0 01456 5 5 0 13981 0 20972 0 27962 0 00874 0 01311 0 01748 M MOTOROLA Chapter 13 Timer Module 18 7 Calculating Time Out Values Table 13 5 Calculated Time out Values 90 MHz Processor Clock Continued TMR PS TMR CLK 10 System Bus Clock 16 TMR CLK 01 System Bus Clock 1 Decimal Hex 45 MHz 30 MHz 22 5 MHz 45 MHz 30 MHz 22 5 MHz 6 6 0 16311 0 24467 0 32622 0 01019 0 01529 0 02039 7 0 18641 0 27962 0 37283 0 01165 0 01748 0 0233 8 8 0 20972 0 31457 0 41943 0 01311 0 01966 0 02621 9 9 0 23302 0 34953 0 46603 0 01456 0 02185 0 02913 10 0A 0 25632 0 38448 0 51264 0 01602 0 02403 0 03204 11 0B 0 27962 0 41943 0 55924 0 01748 0 02621 0 03495 12 0C 0 30292 0 45438 0 60584 0 01893 0 0284 0 03787 13 oD 0 32622 0 48934 0 65245 0 02039 0 03058 0 04078 14 0E 0 34953 0 52429 0 69905 0 02185 0 03277 0 04369 15 OF 0 37283 0 55924 0 74565 0 0233 0 03495 0 0466 16 10 0 39613 0 59419 0 79226 0 02476 0 03714 0 04952 17 11 0 41943 0 62915 0 83886 0 02621 0 03932 0 05243 18 12 0 44273 0 6641 0 88546 0 02767 0 04151 0 05534 19 13 0 46603 0 69905 0 93207
183. 0 25923 0 38885 0 51846 178 B2 4 171 6 2565 8 342 0 26069 0 39103 0 52138 179 B3 4 1943 6 29146 8 38861 0 26214 0 39322 0 52429 180 B4 4 21761 6 32641 8 43521 0 2636 0 3954 0 5272 181 B5 4 24091 6 36136 8 48181 0 26506 0 39759 0 53011 182 B6 4 26421 6 39631 8 52842 0 26651 0 39977 0 53303 183 B7 4 28751 6 43127 8 57502 0 26797 0 40195 0 53594 184 B8 4 31081 6 46622 8 62162 0 26943 0 40414 0 53885 185 B9 4 33411 6 50117 8 66823 0 27088 0 40632 0 54176 186 BA 4 35742 6 53612 8 71483 0 27234 0 40851 0 54468 187 BB 4 38072 6 57108 8 76144 0 27379 0 41069 0 54759 188 BC 4 40402 6 60603 8 80804 0 27525 0 41288 0 5505 189 BD 4 42732 6 64098 8 85464 0 27671 0 41506 0 55342 190 BE 4 45062 6 67593 8 90125 0 27816 0 41725 0 55633 191 BF 4 47392 6 71089 8 94785 0 27962 0 41943 0 55924 192 CO 4 49723 6 74584 8 99445 0 28108 0 42161 0 56215 193 C1 4 52053 6 78079 9 04106 0 28253 0 4238 0 56507 194 C2 4 54383 6 81574 9 08766 0 28399 0 42598 0 56798 195 4 56713 6 8507 9 13426 0 28545 0 42817 0 57089 196 C4 4 59043 6 88565 9 18087 0 2869 0 43035 0 5738 197 C5 4 61373 6 9206 9 22747 0 28836 0 43254 0 57672 198 C6 4 63704 6 95555 9 27407 0 28981 0 43472 0 57963 199 C7 4 66034 6 99051 9 32068 0 29127 0 43691 0 58254 200 C8 4 68364 7 02546 9 36728 0 29273 0 43909 0 58545 201 C9 4 70694 7 06041 9 41388 0 29418 0 44128 0 58837 202 CA 4 73024 7 09536 9 46049 0 29564 0 44346 0 59128 203 CB 4 75354 7 13032 9 50709 0 2971 0 44564 0 59419 204 cc 4 77685 7 16527 9 55369 0
184. 0 Timer Module Signals The signals in the following sections are external interfaces to the two general purpose MCF5307 timers These 16 bit timers can capture timer values trigger external events or internal interrupts or count external events 17 18 MCF5307 User s Manual M woronoLA Parallel I O Port PP 15 0 17 10 1 Timer Inputs TIN 1 0 TIN 1 0 can be programmed as clocks that cause events in the counter and prescalers They can also cause captures on the rising edge falling edge or both edges 17 10 2 Timer Outputs TOUT1 TOUTO The programmable timer outputs TOUT1 and TOUTO pulse or toggle on various timer events 17 11 Parallel 1 0 Port PP 15 0 This 16 bit bus is dedicated for general purpose I O The parallel port is multiplexed with the A 31 24 TT 1 0 TM 2 0 TIP and DREQ 1 0 These 16 bits are programmed for functionality with the PAR in the SIM The system designer controls the reset value of this register by driving D4 with a 1 or 0 on the rising edge of RSTI reset input to MCF5307 device At reset the system is configured as PP 15 0 if D4 is 0 otherwise alternate pin functions selected by PAR 1 are used Motorola recommends that D4 be driven during reset to a logic level 17 12 12 Module Signals The module acts as a two wire bidirectional serial interface between the MCF5307 and peripherals with an interface such as LED controller A to D converter or D to A c
185. 07 samples TA on the rising edge of the second cycle of the bus transfer Figure 18 9 shows a read cycle with fast termination Note that fast termination cannot be used with internal termination M woronoLA Chapter 18 Bus Operation 18 9 Data Transfer Operation 0 1 4 5 BCLKO A 31 0 TT 1 0 TM bol OH X X D z A d d Oo UJ p ag Read 55555552 L Figure 18 9 Read Cycle with Fast Termination D 3 5 TA gt Figure 18 10 shows a write cycle with fast termination S0 1 S4 S5 BCLKO A 31 0 TT 1 0 TM Siz o X X py NN D 31 0 Write 555995 Figure 18 10 Write Cycle with Fast Termination 18 4 6 Back to Back Bus Cycles The MCF5307 runs back to back bus cycles whenever possible For example when a longword read is started on a word size bus the processor performs two back to back word read accesses Back to back accesses are distinguished by the continuous assertion of TIP throughout the cycle Figure 18 11 shows a read back to back with a write 18 10 MCF5307 User s Manual M woronoLA Data Transfer Operation S0 51 S2 S3 S4 S5 S0 S1 S2 S3 S4 S5 BCLKO N A 31 0 TT 1 0 TL sz ol K R W gt
186. 09912 4 64869 6 19825 0 1937 0 29054 0 38739 133 85 3 12243 4 68364 6 24485 0 19515 0 29273 0 3903 134 86 3 14573 4 71859 6 29146 0 19661 0 29491 0 39322 135 87 3 16903 4 75354 6 33806 0 19806 0 2971 0 39613 136 88 3 19233 4 7885 6 38466 0 19952 0 29928 0 39904 137 89 3 21563 4 82345 6 43127 0 20098 0 30147 0 40195 138 8A 3 23893 4 8584 6 47787 0 20243 0 30365 0 40487 139 8B 3 26224 4 89335 6 52447 0 20389 0 30583 0 40778 140 8C 3 28554 4 92831 6 57108 0 20535 0 30802 0 41069 141 8D 3 30884 4 96326 6 61768 0 2068 0 3102 0 4136 142 8E 3 33214 4 99821 6 66428 0 20826 0 31239 0 41652 143 8F 3 35544 5 03316 6 71089 0 20972 0 31457 0 41943 144 90 3 37874 5 06812 6 75749 0 21117 0 31676 0 42234 145 91 3 40205 5 10307 6 80409 0 21263 0 31894 0 42526 146 92 3 42535 5 13802 6 8507 0 21408 0 32113 0 42817 147 93 3 44865 5 17297 6 8973 0 21554 0 32331 0 43108 148 94 3 47195 5 20793 6 9439 0 217 0 3255 0 43399 149 95 3 49525 5 24288 6 99051 0 21845 0 32768 0 43691 150 96 3 51856 5 27783 7 03711 0 21991 0 32986 0 43982 151 97 3 54186 5 31279 7 08371 0 22137 0 33205 0 44273 152 98 3 56516 5 34774 7 13032 0 22282 0 33423 0 44564 153 99 3 58846 5 38269 7 17692 0 22428 0 33642 0 44856 154 9A 3 61176 5 41764 7 22352 0 22574 0 3386 0 45147 155 9B 3 63506 5 4526 7 27013 0 22719 0 34079 0 45438 156 9C 3 65837 5 48755 7 31673 0 22865 0 34297 0 4573 157 9D 3 68167 5 5225 7 36333 0 2301 0 34516 0 46021 158 9E 3 70497 5 55745 7 40994 0 23156 0 34734 0 46312 159 9F 3 72827 5
187. 1 10 9 17 19 21 23 24 25 26 27 28 29 30 31 Column 2 3 4 5 6 7 8 16 18 20 22 SDRAM A1 A2 A4 A7 AB A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 Pins Table 11 30 MCF5307 to SDRAM Interface 32 Bit Port 12 Column Address Lines MCF5307 15 A14 A13 A12 A11 A10 9 17 19 A21 A23 A25 A26 A27 28 A29 A30 A31 Pins Row 15 14 13 12 11 10 9 17 19 21 23 25 26 27 28 29 30 31 Column 2 3 4 5 6 7 8 16 18 20 22 24 SDRAM AO A1 2 A4 A7 A9 A10 A11 A12 A13 A14 A15 A16 A17 Pins 11 4 4 2 Interfacing Example The tables in the previous section can be used to configure the interface in the following example To interface one 2M x 32 bit x 4 bank SDRAM component 8 columns to the 5307 the connections would be as shown in Table 11 31 Table 11 31 SDRAM Hardware Connections SDRAM AO Ai A2 A4 5 A7 AB A9 A10 CMD BAO BA1 Pins MCF5307 A15 A14 A13 A12 A11 A10 9 A17 A18 A19 A20 A21 A22 Pins 11 4 4 3 Burst Page Mode SDRAM can efficiently provide data when an SDRAM page is opened As soon as SCAS is issued the SDRAM accepts a
188. 1 1 0 1 ext w Dx 1 0 0 ext l Dx 1 0 0 n extb I Dx 1 0 0 m neg l Dx 1 0 0 negx I Dx 1 0 0 not Dx 1 0 0 scc Dx 1 0 0 swap Dx 1 0 0 tst b ea 1 0 0 4 1 0 4 1 0 4 1 0 4 1 0 5 1 0 4 1 0 1 0 0 tst w ea 1 0 0 4 1 0 4 1 0 4 1 0 4 1 0 5 1 0 4 1 0 1 0 0 tst I ea 1 0 0 3 1 0 3 1 0 3 1 0 3 1 0 4 1 0 3 1 0 1 0 0 2 7 3 Execution Timings Two Operand Instructions Table 2 14 shows standard timings for two operand instructions M MOTOROLA Chapter 2 ColdFire Core 2 43 Instruction Timing Table 2 14 Two Operand Instruction Execution Times Effective Address Opcode ea Rn An An d16 An d amp An Xi SF xxx wl lt xxx gt add l lt ea gt Rx 1 0 0 4 1 0 4 1 0 4 1 0 4 1 0 5 1 0 4 1 0 1 0 0 add l Dy lt ea gt 40 4 4 11 4 1 4 4 1 1 5 1 1 4 1 1 addi I imm Dx 1 0 0 addq imm lt ea gt 1 0 0 4 1 1 4 1 1 4 1 1 4 1 1 5 1 1 4 1 1 ER addx Dy Dx 1 0 0 and lt ea gt Rx 1 0 0 4 1 0 4 1 0 4 1 0 4 1 0 5 1 0 4 1 0 1 0 0 Dy lt ea gt 40 4 4 11 4 1 4 4 1 1 5 1 1 4 1 1 andi imm Dx 1 0 0 asl
189. 1 11 4 4 2 11 4 4 3 11 4 4 4 11 4 4 5 11 4 4 6 11 4 5 11 4 5 1 11 5 11 5 1 11 5 2 11 5 3 11 5 4 11 5 5 11 5 6 12 1 12 1 1 12 2 12 3 12 4 12 4 1 12 4 2 xii CONTENTS Page Tie Number Burst Page Mode Operation ssesssseeeeeeeene 11 12 Continuous Page Mode sse 11 13 Extended Data Out EDO Operation eene 11 15 Refresh Op ration esee eio eee tee dle EE IR Seres 11 16 Synchronous Operation esee enne 11 16 DRAM Controller Signals in Synchronous Mode 11 17 Using Edge Select EDGESEL 11 18 Synchronous Register Set sese 11 19 DRAM Control Register DCR in Synchronous Mode 11 19 DRAM Address and Control Registers DACRO DACR1 in Synchronous Mode essere 11 20 DRAM Controller Mask Registers IDMRO DMRI 11 22 General Synchronous Operation Guidelines sess 11 23 Address Multiplexing 11 23 Interfacing 11 27 Burst Page eoo nhe end 11 27 Continuous Page Mode esses 11 29 Auto Refresh Operation sss 11 31 Self Refresh Operation Initialization Sequence esses Mode Register Settings SDRAM Example 5 c eee tete nne nee insaniae o sed E eas SDRAM Int
190. 1 0 Transfer size Rising TA Transfer acknowledge Rising TIP Transfer in progress Three state Rising TM 2 0 Transfer modifier Three state Rising TS Transfer start Rising TT 1 0 Transfer type Three state Rising 1 These signals change after the falling edge In Chapter 20 Electrical Specifications these signals are specified off the rising edge because CLKIN is squared up internally 18 3 Bus Characteristics The MCF5307 uses an input clock signal CLKIN to generate its internal clock BCLKO is the bus clock rate where all bus operations are synchronous to the rising edge of BCLKO Some of the bus control signals BE BWE OE CSx and AS are synchronous to the falling edge shown in Figure 18 1 Bus characteristics may differ somewhat for interfacing with external DRAM BCLKO Rising Edge ignals Felling Edge ignals Inputs tvo tvo tvo Propagation delay of signal relative to BCLKO edge tho Output hold time relative to BCLKO edge tg Required input setup time relative to BCLKO edge thi Required input hold time relative to BCLKO edge Figure 18 1 Signal Relationship to BCLKO for Non DRAM Access 18 2 MCF5307 User s Manual M MOTOROLA Data Transfer Operation 18 4 Data Transfer Operation Data transfers between the MCF5307 and other devices involve the following signals e Address bus A 31 0 Data bus D 31 0 Control s
191. 1 0 0 subq l imm lt ea gt 1 0 0 4 1 1 4 1 1 4 1 1 4 1 1 5 1 1 4 1 1 subx Dy Dx 1 0 0 2 7 4 Miscellaneous Instruction Execution Times Table 2 15 lists timings for miscellaneous instructions Table 2 15 Miscellaneous Instruction Execution Times Effective Address Opcode ea Rn An An d16 An d8 An Xi SF xxx wl lt xxx gt cpushl Ax 11 0 1 link w Ay imm 2 0 1 move w CCR Dx 1 0 0 move w ea CCR 1 0 0 1 0 0 move w SR Dx 1 0 0 move w lt ea gt SR 9 0 0 9 0 0 movec Ry Rc 11 0 1 movem ea amp list 2 n n 0 2 n n 0 movem amp list lt ea gt 2 n 0 n 2 n 0 n M MOTOROLA Chapter 2 ColdFire Core 2 45 Instruction Timing Table 2 15 Miscellaneous Instruction Execution Times Continued Effective Address Opcode ea Rn An An d16 An d8 An Xi SF xxx wl lt gt nop 3 0 0 pea ea 2 0 1 2 0 1 8 3 0 1 4 2 0 1 pulse 1 0 0 stop imm 3 0 0 trap imm E 18 1 2 trapf 1 0 0
192. 14 31 Operation RSTCHN DISABLE TRANSMITTER HAVE FRAMING ERROR RESTORE TO ORIGINAL MODE RETURN HAVE PARITY ERROR SET PARITY ERROR FLAG CHRCHK GET CHARACTER FROM RECEIVER TRANSMITTED CHARACTER N SET INCORRECT CHARACTER FLAG Figure 14 27 UART Mode Programming Flowchart Sheet 3 of 5 14 32 MCF5307 User s Manual M woronoLA A WAS CAUSED BY BEGINNING CLEAR CHANGE IN BREAK STATUS BIT ABRKI1 IRQ ARRIVED YET CLEAR CHANGE IN BREAK STATUS BIT REMOVE BREAK CHARACTER FROM RECEIVER FIFO REPLACE RETURN ADDRESS ON SYSTEM STACK AND MONITOR WARM START ADDRESS Figure 14 27 UART Mode Programming Flowchart Sheet 4 of 5 MOTOROLA DOES CHANNEL RECEIVER HAVE A CHARACTER PLACE CHARACTER IN DO RETURN Chapter 14 UART Modules Operation 14 33 Operation IS TRANSMITTER READY SEND CHARACTER TO TRANSMITTER RETURN Figure 14 27 UART Mode Programming Flowchart Sheet 5 of 5 14 34 MCF5307 User s Manual M woronoLA Chapter 15 Parallel Port General Purpose 1 0 This chapter describes the operation and programming model of the parallel port pin assignment direction control and data registers It includes a code example for setting up the parallel port 15 1 Parallel Port Operation The MCF5307 parallel port module has 16 signals which are programmed as
193. 2 1 X TIP X X SIZ 1 0 X Line X Longword TS Vu y AS CSx E BWE D 31 0 oe Write Write y Write y Write B Fast B Fast i Fast gt Figure 18 18 Line Write Burst Inhibited Internal Termination 18 4 7 4 Transfers Using Mixed Port Sizes Figure 18 19 shows timing for a longword read from an 8 bit port using external termination Figure 18 20 shows the same transfer with internal termination For both SIZ 1 0 change only at the start of a new transfer because this burst is implemented as one M MOTOROLA Chapter 18 Bus Operation 18 15 Misaligned Operands transfer S0 S1 52 53 S4 S5 56 S7 S8 59 510 11 512 BCLKO A 31 0 TT 1 0 TM SIZ H X X R W N EE D 31 0 Ready Read ead 522222222222 T mu Figure 18 19 Longword Read from an 8 Bit Port External Termination Note that with external termination address signals do not change With internal termination Figure 18 20 A 1 0 increment for the same longword transfer S0 1 S2 S3 S4 S5 S6 7 S8 59 S10 S11 S12 BCLKO A A A 1 0 X X X X X X A 31 2 TT 1 0 a X X D 81 0 Read Read Read 55 DS Figure 18 20 Longword Read from an 8 Bit Port Internal Termin
194. 29855 0 44783 0 59711 205 CD 4 80015 7 20022 9 6003 0 30001 0 45001 0 60002 13 12 MCF5307 User s Manual M woronoLA Calculating Time Out Values Table 13 5 Calculated Time out Values 90 MHz Processor Clock Continued TMR PS TMR CLK 10 System Bus Clock 16 TMR CLK 01 System Bus Clock 1 Decimal Hex 45 MHz 30 MHz 22 5 MHz 45 MHz 30 MHz 22 5 MHz 206 CE 4 82345 7 23517 9 6469 0 30147 0 4522 0 60293 207 CF 4 84675 7 27013 9 6935 0 30292 0 45438 0 60584 208 DO 4 87005 7 30508 9 74011 0 30438 0 45657 0 60876 209 D1 4 89335 7 34003 9 78671 0 30583 0 45875 0 61167 210 D2 4 91666 7 37498 9 83331 0 30729 0 46094 0 61458 211 D3 4 93996 7 40994 9 87992 0 30875 0 46312 0 61749 212 D4 4 96326 7 44489 9 92652 0 3102 0 46531 0 62041 213 D5 4 98656 7 47984 9 97312 0 31166 0 46749 0 62332 214 D6 5 00986 7 51479 10 01973 0 31312 0 46967 0 62623 215 D7 5 03316 7 54975 10 06633 0 31457 0 47186 0 62915 216 D8 5 05647 7 5847 10 11293 0 31603 0 47404 0 63206 217 D9 5 07977 7 61965 10 15954 0 31749 0 47623 0 63497 218 DA 5 10307 7 6546 10 20614 0 31894 0 47841 0 63788 219 DB 5 12637 7 68956 10 25274 0 3204 0 4806 0 6408 220 DC 5 14967 7 72451 10 29935 0 32185 0 48278 0 64371 221 DD 5 17297 7 75946 10 34595 0 32331 0 48497 0 64662 222 DE 5 19628 7 79441 10 39255 0 32477 0 48715 0 64953 223 DF 5 21958 7 82937 10 43916 0 32622 0 4
195. 3 4 20 Address Base Address Mask E S CM W Uninitialized 0 Uninitialized Write R W by debug module ACRO 0x004 ACR1 0x005 Figure 4 9 Access Control Register Format ACRn Table 4 5 describes ACRn fields Table 4 5 ACRn Field Descriptions Bits Name Description 31 24 Address Address base Compared with address bits A 31 24 Eligible addresses that match are base assigned the access control attributes of this register 23 16 Address Address mask Setting a mask bit causes the corresponding address base bit to be ignored mask The low order mask bits can be set to define contiguous regions larger than 16 Mbytes The mask can define multiple noncontiguous regions of memory 15 E Enable Enables or disables the other ACRn bits 0 Access control attributes disabled 1 Access control attributes enabled 14 13 S Supervisor mode Specifies whether only user or supervisor accesses are allowed in this address range or if the type of access is a don t care 00 Match addresses only in user mode 01 Match addresses only in supervisor mode 1x Execute cache matching on all accesses 12 7 Reserved should be cleared 6 5 CM Cache mode Selects the cache mode and access precision Precise and imprecise modes are described in Section 4 9 2 Cache Inhibited Accesses 00 Cacheable write through 01 Cacheable copyback 10 Cache inhibited precise 11 Cache inhibited impre
196. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Field Setting X x X X X X X X X X X X 0 0 0 X hex 0 0 0 0 Field V Setting 0 0 0 0 1 0 0 X X X X X X X X X hex 0 8 0 0 Figure 11 29 Mode Register Mapping to MCF5307 A 31 0 Although A 31 20 corresponds to the address programmed in DACRO according to how DACRO and DMRO are initialized bit 19 must be set to hit in the SDRAM Thus before the mode register bit is set DMRO 19 must be set to enable masking 11 38 MCF5307 User s Manual M woronoLA SDRAM Example 11 5 6 Initialization Code The following assembly code initializes the SDRAM example Power Up Sequence move w 0x8026 Initialize DCR move w 40 DCR move l 0xFF880300 Initialize DACRO move l d0 DACRO move l 0x00740075 d0 Initialize DMRO move l DMRO Precharge Sequence move l 0xFF880308 Set DACRO IP move l 90 DACRO move l 0xBEADDEED dO Write to memory location to init precharge move l 40 OxFF880000 Refresh Sequence move l 0xFF888300 d0 Enable refresh bit in DACRO move l d0 DACRO Mode Register Initialization Sequence move l 0x00600075 Mask bit 19 of address move l DMRO move l 0xFF888340 Enable DACRO IMRS DACRO RE remains set move l 90 DACRO move l 0 00000000 Access SDRAM address to initialize mode register move l d0 OxFF800800 M MOTO
197. 36 0 19515 67 43 1 58451 2 37677 3 169038 0 09903 0 14855 0 19806 68 44 1 60782 2 41172 3 21563 0 10049 0 15073 0 20098 69 45 1 63112 2 44668 3 26224 0 10194 0 15292 0 20389 70 46 1 65442 2 48163 3 30884 0 1034 0 1551 0 2068 71 47 1 67772 2 51658 3 35544 0 10486 0 15729 0 20972 72 48 1 70102 2 55153 3 40205 0 10631 0 15947 0 21263 73 49 1 72432 2 58649 3 44865 0 10777 0 16166 0 21554 74 4A 1 74763 2 62144 3 49525 0 10923 0 16384 0 21845 75 4B 1 77093 2 65639 3 54186 0 11068 0 16602 0 22137 76 4C 1 79423 2 69135 3 58846 0 11214 0 16821 0 22428 77 4D 1 81753 2 7263 3 63506 0 1136 0 17039 0 22719 78 4E 1 84083 2 76125 3 68167 0 11505 0 17258 0 2301 79 4F 1 86414 2 7962 3 72827 0 11651 0 17476 0 23302 80 50 1 88744 2 83116 3 77487 0 11796 0 17695 0 23593 81 51 1 91074 2 86611 3 82148 0 11942 0 17913 0 23884 82 52 1 93404 2 90106 3 86808 0 12088 0 18132 0 24176 83 53 1 95734 2 93601 3 91468 0 12233 0 1835 0 24467 84 54 1 98064 2 97097 3 96129 0 12379 0 18569 0 24758 85 55 2 00395 3 00592 4 00789 0 12525 0 18787 0 25049 M MOTOROLA Chapter 13 Timer Module 13 9 Calculating Time Out Values Table 13 5 Calculated Time out Values 90 MHz Processor Clock Continued TMR PS TMR CLK 10 System Bus Clock 16 TMR CLK 01 System Bus Clock 1 Decimal Hex 45 MHz 30 MHz 22
198. 4 4 Write Cycle During a write cycle the MCF5307 sends data to memory or to a peripheral device The write cycle flowchart is shown in Figure 18 7 18 8 MCF5307 User s Manual M woronoLA Data Transfer Operation MCF5307 System 1 Set R W to write 2 Place address on A 31 0 3 Assert TT 1 0 TM 2 0 TIP and SIZ 1 0 4 Assert TS 5 Assert AS 6 Place data on D 31 0 M Haut 1 Decode address 7 TS 2 Store data on D 31 0 1 Sample TA low 3 gt 1 Negate 1 Tree state D 31 0 2 Start next cycle Figure 18 7 Write Cycle Flowchart The write cycle timing diagram is shown in Figure 18 8 0 1 2 3 4 5 BCLKO A 31 0 TT 1 0 Sia X X D 31 0 Write Figure 18 8 Basic Write Bus Cycle Table 18 4 describes the six states of a basic write cycle 18 4 5 Fast Termination Cycles Two clock cycle transfers are supported on the MCF5307 bus In most cases this is impractical to use in a system because the termination must take place in the same half clock during which AS is asserted Because this is atypical it is not referred to as the Zero wait state case but is called the fast termination case A fast termination cycle is one in which an external device or memory asserts TA as soon as TS is detected This means that the MCF53
199. 4685 0 32914 113 71 2 65639 3 98459 5 31279 0 16602 0 24904 0 33205 114 72 2 67969 4 01954 5 35939 0 16748 0 25122 0 33496 115 73 2 703 4 05449 5 40599 0 16894 0 25341 0 33787 116 74 2 7263 4 08945 5 4526 0 17039 0 25559 0 34079 117 75 2 7496 4 1244 5 4992 0 17185 0 25777 0 3437 118 76 2 7729 4 15935 5 5458 0 17331 0 25996 0 34661 119 77 2 7962 4 1943 5 59241 0 17476 0 26214 0 34953 120 78 2 8195 4 22926 5 63901 0 17622 0 26433 0 35244 121 79 2 84281 4 26421 5 68561 0 17768 0 26651 0 35535 122 7 2 86611 4 29916 5 73222 0 17913 0 2687 0 35826 123 7 2 88941 4 33411 5 77882 0 18059 0 27088 0 36118 124 7C 2 91271 4 36907 5 82542 0 18204 0 27307 0 36409 125 7D 2 93601 4 40402 5 87203 0 1835 0 27525 0 367 13 10 MCF5307 User s Manual M MOTOROLA Calculating Time Out Values Table 13 5 Calculated Time out Values 90 MHz Processor Clock Continued TMR PS TMR CLK 10 System Bus Clock 16 TMR CLK 01 System Bus Clock 1 Decimal Hex 45 MHz 30 MHz 22 5 MHz 45 MHz 30 MHz 22 5 MHz 126 7E 2 95931 4 43897 5 91863 0 18496 0 27744 0 36991 127 7F 2 98262 4 47392 5 96523 0 18641 0 27962 0 37283 128 80 3 00592 4 50888 6 01184 0 18787 0 2818 0 37574 129 81 3 02922 4 54383 6 05844 0 18933 0 28399 0 37865 130 82 3 05252 4 57878 6 10504 0 19078 0 28617 0 38157 131 83 3 07582 4 61373 6 15165 0 19224 0 28836 0 38448 132 84 3
200. 5 0 5 5 ns 1 Inputs BG A 23 0 15 0 SIZ 1 0 R W TS EDGESEL D 31 0 TRQ 7 5 3 1 and nputs AS 3 Inputs D 31 0 Table 20 6 lists specifications for timings in Figure 20 3 Figure 20 4 and Figure 20 10 Although output signals that share a specification number have approximately the same timing due to loading differences they do not necessarily change at the same time However they have similar timings that is minimum and maximum times are not mixed Table 20 6 Output AC Timing Specification 66 MHz 90 MHz Num Characteristic Units Min Max Min Max B10 123 BCLKO rising to valid 15 11 nS B11 29 BCLKO rising to invalid hold 1 1 nS 11 1235 BCLKO rising to invalid hold 0 5 0 5 B12 97 BCLKO to high impedance three state 15 11 nS B13 823 BCLKO rising to valid 15 11 nS B14 823 BCLKO rising to invalid hold 3 2 nS B1523 EDGESEL to valid 18 5 13 5 nS B1623 EDGESEL to invalid hold 3 2 nS H1 HIZ to high impedance 60 60 nS H2 HIZ to low Impedance 60 60 nS PP 15 8 when configured as parallel port outputs Outputs that can change on either BCLKO edge depending only upon EDGESEL D 31 0 A 23 0 SCKE SRAS SCAS DRAMW and PP 15 8 when individually configured as address outputs 3 Outputs that can change on either BCLKO edge depending only upon
201. 5 43 5 42 5 44 6 1 6 2 6 3 6 5 6 6 6 7 6 8 XX ILLUSTRATIONS Number Program Counter Breakpoint Register PBR sse 5 14 Program Counter Breakpoint Mask Register 5 14 Trigger Definition Register TDR sese 5 15 BDM Serial Interface Timing 5 18 Receive BDM Packet zi emeret eee e i ded 5 19 Transmit BOM Packet eerte tete e e Ue ORE aee E 5 19 BDM Command Forimat ote ret o ette 5 21 Command Sequence 1 5 22 RAREG RDREG Command Sequence sse 5 24 RAREG RDREG Command Format eese 5 24 WAREG WDREG Command Sequence essen 5 25 WAREG WDREG Command 5 25 READ Command 5 26 READ Command Result Formats eese eene nennen nennen nnne nnns 5 26 WRITE Command Format esee nennen nennen nnne nennen enne nnne 5 27 WRITE Command Sequence 5 28 DUMP Command Result Formats eese nennen nnne nnns 5 29 DUMP Command Sequence csccccccsscssasseoctsscsescbcosdescssacseostesdsssessocsescseastcocsseessesecessssesss 5 30 FILL Command Porimit 2 e uressocie o oe D D PORC REGERE 5 31 FILL Command SEQUENCE seisccsesccvseiecciesseoseestssescosevssecesveossesdstesncetssacecesseesesacsces
202. 5 5 5 nS D2 PSTCLK to PST DDATA hold 7 5 5 5 nS D3 DSI to DSCLK setup 1 1 PSTCLKs 20 12 MCF5307 User s Manual M woronoLA Debug AC Timing Specifications Table 20 8 Debug AC Timing Specification 66 MHz 90 MHz Num Characteristic Units Min Max Min Max 041 DSCLK to DSO hold 4 4 PSTCLKs D5 DSCLK cycle time 5 5 PSTCLKs DSCLK and DSI are synchronized interna ly D4 is measured from the synchronized DSCLK input relative to the rising edge of PSTCLK Figure 20 12 shows real time trace timing for the values in Table 20 8 PSTCLK N PST 3 0 DDATA 3 0 Figure 20 12 Real Time Trace AC Timing Figure 20 13 shows BDM serial port AC timing for the values in Table 20 8 PsTcLK uc pex e Le 0s DSCLK DSI X Current X Next p 0 DSO X Past X Current M MOTOROLA Figure 20 13 BDM Serial Port AC Timing Chapter 20 Electrical Specifications 20 13 Timer Module AC Timing Specifications 20 6 Timer Module AC Timing Specifications Table 20 9 lists specifications for timer module AC timing parameters shown in Figure 20 14 Figure 20 14 shows timings for Table 20 9 Table 20 9 Timer Module AC Timing Specification 66 MHz 90 MHz Num Characteristic Units Min Max Min Max T1 TIN cycle time 3 3
203. 5307 User s Manual M woronoLA Chip Select Module Signals of memory if desired ADDR CONFIG is multiplexed with D4 and its configuration is sampled at reset as shown in Table 17 14 Table 17 14 DA ADDR CONFIG Address Pin Assignment D4 ADDR_CONFIG PAR Configuration at Reset 0 PP 15 0 defaulted to inputs upon reset 1 A 31 24 TIP DREQ 1 0 TM 2 0 TT 1 0 17 5 7 D 3 2 Frequency Control PLL FREQ 1 0 The frequency control PLL input bus FREQ 1 0 indicates the CLKIN frequency range These signals are multiplexed with D 3 2 and are sampled during the assertion of RESET These signals indicate the operating frequency range to the PLL as shown in Table 17 15 Note that these signals do not affect the PLL frequency but are required to set up the analog PLL Table 17 15 CLKIN Frequency FREQ 1 0 D 3 2 CLKIN Frequency MHz 00 16 6 27 999 01 28 38 999 10 39 45 11 Reserved 17 5 8 D 1 0 Divide Control PCLK to BCLKO DIVIDE 1 0 This 2 bit input bus indicates the BCLKO PSTCLK ratio These signals are sampled during the assertion of RESET and indicate the ratios shown in Table 17 16 Table 17 16 BCLKO PSTCLK Divide Ratios DIVIDE 1 0 D 1 0 Ratio of BCLKO PSTCLK 00 1 4 01 Reserved 10 1 2 11 1 8 17 6 Chip Select Module Signals The MCF5307 device provides eight programmable chip select signals that can directly interface wi
204. 53x Read 539 Read HONK Read gt Sy TA Y Figure 18 14 Line Read Burst 3 2 2 2 External Termination Figure 18 15 shows a burst inhibited line read access with fast termination The external device executes a basic read cycle while determining that a line is being transferred The external device uses fast termination for subsequent transfers M MOTOROLA Chapter 18 Bus Operation 18 13 Data Transfer Operation 0 1 S2 53 54 55 50 1 4 55 SO 51 4 S5 50 51 4 S5 S6 S7 BCLKO A 31 0 X 2 00 As 2j201 X 2 10 X 2 1 X R W m X K TIP SIZ 1 0 X Line 4 Longword X ts m um m M NM E X Basic E Fast E Fast B Fast Figure 18 15 Line Read Burst Inhibited Fast External Termination 18 4 7 3 Line Write Bus Cycles Figure 18 16 shows a line access write with zero wait states It begins like a basic write bus cycle with data driven one clock after TS The next pipelined burst data is driven a cycle after the write data is registered on the rising edge of S6 Each subsequent burst takes a single cycle Note that as with the line read example in Figure 18 12 AS and CSx remain asserted throughout the burst transfer This example shows the behavior of the address lines for both internal and external termination Note that with external termination addres
205. 6 BAM With bits 17 and 16 as don t cares BAM 0x0074 which leaves bank select bits and upper 512K select bits unmasked Note that bits 22 and 21 are set because they are used as bank selects bit 20 is set because it controls the 1 Mbyte boundary address 15 9 Reserved Don t care 8 WP 0 Allow reads and writes 7 Reserved 6 1 Disable CPU space access 5 AM 1 Disable alternate master access 4 SC 1 Disable supervisor code accesses 3 SD 0 Enable supervisor data accesses 2 UC 1 Disable user code accesses 1 UD 0 Enable user data accesses 0 V 1 Enable accesses M MOTOROLA Chapter 11 Synchronous Asynchronous DRAM Controller Module 11 37 SDRAM Example 11 5 5 Mode Register Initialization When DACR IMRS is set a bus cycle initializes the mode register If the mode register setting is read on A 10 0 of the SDRAM on the first bus cycle the bit settings on the corresponding MCF5307 address pins must be determined while being aware of masking requirements Table 11 37 lists the desired initialization setting Table 11 37 Mode Register Initialization MCF5307 Pins SDRAM Pins Mode Register Initialization A20 A10 Reserved X A19 A9 WB 0 A18 A8 Opmode 0 A17 A7 Opmode 0 A9 A6 CASL 0 A10 A5 CASL 0 A11 A4 CASL 1 A12 A3 BT 0 A13 A2 BL 0 A14 A1 BL 0 A15 A0 BL 0 Next this information is mapped to an address to determine the hexadecimal value
206. 6 2 10 1 2 Arbitration between Internal and External Masters for Accessing Internal Resources eese 6 14 M Contents ix Paragraph Number 7 1 7 1 1 7 2 7 2 1 7 2 2 7 2 3 7 2 4 7 3 7 4 7 4 1 7 4 2 7 5 8 1 8 2 8 3 8 4 8 4 1 8 4 2 8 4 3 8 4 4 8 5 8 5 1 8 5 2 8 5 3 8 5 4 8 5 5 8 6 8 6 1 8 6 2 8 6 3 8 6 4 8 6 5 8 6 6 8 6 7 CONTENTS Page We Number Chapter 7 Phase Locked Loop PLL Oda 7 1 PEEEAPE LEG 7 2 PET Operation tinte tenti een t rete en ec 7 2 R set Initializatioti s ume heiter P P BER etie en 7 2 NormabEMode eie tenete treten 7 2 Reduced Power 7 2 PLL Control Register PLLCR eene 7 3 PEL POrt List eiie rr e E e eR ea A 7 3 Timing Relationships 7 4 PEEK PSTCLK and BECEKO isinin ei a 7 4 RSTI Timing sse tette teretes 7 5 PLL Power Supply Filter Circuit eese 7 6 Chapter 8 2 Module COVELVIEW T 8 1 Interface Eeatutes 8 1 PC System Configuration 8 3 8 3 Arbitration Procedure 8 4 Clock 7 8 5 Hand shaking ata ere tite eee te i i e RR AT RS Clock Stretching 3 notte eet et Programming Model Address Register IADR
207. 6 Internal 4 Kbyte SRAM The 4 Kbyte on chip SRAM module provides pipelined single cycle access to memory regions mapped to these devices The memory can be mapped to any 0 modulo 32K location in the 4 Gbyte address space The SRAM module is useful for storing time critical functions the system stack or heavily referenced data operands 1 3 2 DRAM Controller The MCF5307 DRAM controller provides a direct interface for up to two blocks of DRAM The controller supports 8 16 or 32 bit memory widths and can easily interface to PC 100 DIMMs A unique addressing scheme allows for increases in system memory size without rerouting address lines and rewiring boards The controller operates in normal mode or in page mode and supports SDRAMs and EDO DRAMs 1 3 3 DMA Controller The MCF5307 provides four fully programmable DMA channels for quick data transfer Dual and single address modes support bursting and cycle steal Data transfers are 32 bits long with packing and unpacking supported along with an auto alignment option for efficient block transfers Automatic block transfers from on chip serial UARTs are also supported through the DMA channels 1 3 4 UART Modules The MCF5307 contains two UARTs which function independently Either UART can be clocked by the system bus clock eliminating the need for an external crystal Each UART module interfaces directly to the CPU as shown in Figure 1 2 1 8 MCF5307 User s Manual M woronoLA ColdFi
208. 6 bit displacement Address Calculated effective address pointer Bit Bit selection example Bit 3 of DO Isb Least significant bit example Isb of DO LSB Least significant byte LSW Least significant word msb Vost significant bit MSB Vost significant byte MSW Vost significant word Condition Code Register Bit Names 2 36 MCF5307 User s Manual M woronoLA Instruction Set Summary Table 2 6 Notational Conventions Continued Instruction Operand Syntax Branch prediction Carry Negative Overflow Extend lt Z O Zero 2 6 1 Instruction Set Summary Table 2 7 lists implemented user mode instructions by opcode Table 2 7 User Mode Instruction Set Summary Instruction Operand Syntax Operand Size Operation ADD Dy lt ea gt x Source destination destination ea y Dx ADDA ea y Ax D Source destination destination ADDI lt data gt Dx aL Immediate data destination destination ADDQ lt data gt lt ea gt x Immediate data destination destination ADDX Dy Dx L Source destination X destination AND Dy lt ea gt x Source amp destination destination ea y Dx ANDI lt data gt Dx L Immediate data amp destination destination ASL Dy Dx Dx lt lt Dy 0 lt data gt Dx L lt Dx lt lt lt data gt
209. 7 A18 A19 A20 A21 A22 Pins Table 11 16 MCF5307 to SDRAM Interface 8 Bit Port 10 Column Address Lines MCF5307 17 A16 A15 A14 A13 A12 A11 A10 A9 A19 20 21 22 23 24 A25 A26 A27 A28 A29 A30 AS31 Pins Row 17 16 15 14 13 12 11110 9 19 20 21 22 23 24 25 26 27 28 29 30 31 Column 0 1112134516170 8 18 SDRAM 0 A1 A2 A4 A5 A7 A9 A10A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 Pins Table 11 17 MCF5307 to SDRAM Interface 8 Bit Port 11 Column Address Lines 5307 A17 A16 A15 A14 A13 A12 A11 A10 A9 A19 21 22 23 24 25 A26 A27 A28 A29 A30 A31 Pins Row 17 16 15 14 13 12 11110 9 19 21 22 23 24 25 26 27 28 29 30 31 Column 0 1 2 4 5 6 7 8 18 20 SDRAM AO A1 A2 A4 A5 A7 A8 A9 10 11 12 13 14 15 16 17 18 19 20 Pins Table 11 18 MCF5307 to SDRAM Interface 8 Bit Port 12 Column Address Lines MCF5307 A17 A16 A15 A14 A13 A12 A11 A10 A9 A19 21 23 24 25 26 A27 A28 A29 A30 AS31 Pins Row 17 16 15 14 13 12 11 101 9 19 21 23 24 25 26 27 28 29 30 31 Column 0 111213415161 7 8 18 20 22
210. 8934 0 65245 224 EO 5 24288 7 86432 10 48576 0 32768 0 49152 0 65536 225 E1 5 26618 7 89927 10 53236 0 32914 0 4937 0 65827 226 E2 5 28948 7 93423 10 57897 0 33059 0 49589 0 66119 227 E3 5 31279 7 96918 10 62557 0 33205 0 49807 0 6641 228 E4 5 33609 8 00413 10 67217 0 33351 0 50026 0 66701 229 E5 5 35939 8 03908 10 71878 0 33496 0 50244 0 66992 230 E6 5 38269 8 07404 10 76538 0 33642 0 50463 0 67284 231 E7 5 40599 8 10899 10 81198 0 33787 0 50681 0 67575 232 E8 5 42929 8 14394 10 85859 0 33933 0 509 0 67866 233 E9 5 4526 8 17889 10 90519 0 34079 0 51118 0 68157 234 EA 5 4759 8 21385 10 95179 0 34224 0 51337 0 68449 235 EB 5 4992 8 2488 10 9984 0 3437 0 51555 0 6874 236 EC 5 5225 8 28375 11 045 0 34516 0 51773 0 69031 237 ED 5 5458 8 3187 11 0916 0 34661 0 51992 0 69323 238 EE 5 5691 8 35366 11 13821 0 34807 0 5221 0 69614 239 EF 5 59241 8 38861 11 18481 0 34953 0 52429 0 69905 240 FO 5 61571 8 42356 11 23141 0 35098 0 52647 0 70196 241 F1 5 63901 8 45851 11 27802 0 35244 0 52866 0 70488 242 F2 5 66231 8 49347 11 32462 0 35389 0 53084 0 70779 243 F3 5 68561 8 52842 11 37122 0 35535 0 53303 0 7107 244 F4 5 70891 8 56337 11 41783 0 35681 0 53521 0 71361 245 F5 5 73222 8 59832 11 46443 0 35826 0 5374 0 71653 M Chapter 13 Timer Module 13 13 Calculating Time Out Values Table 13 5 Calculated Time out Values 90 MHz Processor Clock Continued
211. 9 5 AVR Field amp nennen 9 6 9 6 Autovector Register Bit Assignments 9 6 9 7 IPR and IMR Field 9 7 xxvi MCF5307 User s Manual M woronoLA TABLES Table Page Number He Number 9 8 IRQPAR Field DeScriptlons s cccicccisessecsieesssectecsionssvesiecsdonssvestecsdoneducsseussendsvecdesssensdueesen 9 8 10 1 Chip Select Module Signals 10 1 10 2 Byte Enables Byte Write Enable Signal Settings sse 10 2 10 3 Accesses by Matches in CSCRs and DACRS esse 10 3 10 4 D7 AA Automatic Acknowledge of Boot CSO eene 10 4 10 5 D 6 5 PS 1 0 Port Size of Boot CSO eese 10 4 10 6 Chip Select Registers AEE 10 5 10 7 CSARn Field Description 10 6 10 8 GSMRx Eield Descriptions centro ee tere ret re eni on lea o ein og aea tea doge d 10 7 10 9 CSCRnz Field 10 8 11 1 DRAM Controller Registers 11 3 11 2 SDRAM Signal Summary 11 4 11 3 DCR Field Descriptions Asynchronous Mode sse 11 5 11 4 DACRO DACRI Field Description 4 11 6 11 5 DMRO0 DMRI Field 11 7 11 6 Generic Address Multiplexing Scheme
212. A DMRO 1 General Purpose Timers 10 ICRs IRQPAR pec 32 Bit Address Bus 32 Bit Data Bus Control Signals IRQ 1 3 5 7 Figure 1 1 MCF5307 Block Diagram DRAM Controller Outputs 1 2 MCF5307 User s Manual M woronoLA Features Features common to many embedded applications such as DMAs various DRAM controller interfaces and on chip memories are integrated using advanced process technologies The MCF5307 extends the legacy of Motorola s 68K family by providing a compatible path for 68K and ColdFire customers in which development tools and customer code can be leveraged In fact customers moving from 68K to ColdFire can use code translation and emulation tools that facilitate modifying 68K assembly code to the ColdFire architecture Based on the concept of variable length RISC technology the ColdFire family combines the architectural simplicity of conventional 32 bit RISC with a memory saving variable length instruction set In defining the ColdFire architecture for embedded processing applications a 68K code compatible core combines performance advantages of a RISC architecture with the optimum code density of a streamlined variable length M68000 instruction set By using a variable length instruction set architecture embedded system designers using ColdFire RISC processors enjoy significant advantages over c
213. A channels are prioritized in ascending order channel 0 having highest priority and channel 3 having the lowest or as determined by DCR BWC If BWC for a DMA channel is 000 that channel has priority only over the channel immediately preceding it For example if DCR3 BWC 000 DMA channel 3 has priority over DMA channel 2 assuming DCR2 BWC 000 but not over DMA channel 1 If DCRI BWC DCR2 BWC 000 DMA 1 has priority over DMA 0 and DMA 2 DCR2 BWC 000 in this case does not affect prioritization Prioritization of simultaneous external requests is either ascending or as determined by each channel s BWC bits as described in the previous paragraphs 12 5 3 2 Programming the DMA Controller Module Note the following general guidelines for programming the DMA No mechanism exists to prevent writes to control registers during DMA accesses Ifthe BWC of sequential channels are equal channel priority is in ascending order The SAR is loaded with the source read address If the transfer is from a peripheral device to memory the source address is the location of the peripheral data register If the transfer M woronoLA Chapter 12 DMA Controller Module 12 13 DMA Controller Module Functional Description is from memory to either a peripheral device or memory the source address is the starting address of the data block This can be any aligned byte address In single address mode this data register is used regardless of tr
214. ARx 0x0DE Chip select 7 control register All other chip selects should be programmed and made valid before global chip select is de activated by validating CSO Program Chip Select 3 Registers move w 0x0040 D0 CSAR3 base address 0x00400000 move w 10 5 move w 0x00A0 D0 CSCR3 no wait states AA 0 PS 16 bit BEM 1 move w D0O CSCR3 BSTR 0 BSTW 0 move l 0x001F016B D0 Address range from 0x00400000 to OxOO05FFFFF move l D0 CSMR3 WP EM C I SD UD V 1 SC UC 0 Program Chip Select 2 Registers move w 0x0020 D0 CSAR2 base address 0x00200000 to Ox003FFFFF M MOTOROLA Chapter 10 Chip Select Module 10 9 Chip Select Registers move w DO CSAR2 move w 0x0538 D0 CSCR2 1 wait state AA 1 PS 32 bit BEM 1 move w DO CSCR2 BSTR 1 BSTW 1 move l 0x001F0001 D0 Address range from 0x00200000 to 0x003FFFFF move l D0O CSMR2 WP EM C 1I SC SD UC UD 0 V 1 Program Chip Select 1 Registers move w 0x0000 D0 CSAR1 base addresses 0x00000000 to Ox001FFFFF move w 10 5 and 0x80000000 to 0x801FFFFF move w 0 09 0 CSCR1 2 wait states AA 1 PS 16 bit BEM 1 move w DO CSCR1 BSTR 1 BSTW 0 move l 0Ox801F0001 D0 Address range from 0x00000000 to Ox001FFFFF and move l D0O CSMR1 0x80000000 to Ox801FFFFF WP EM C I SC SD UC UD 0 V 1 Program Chip Select 0 Registers move w 0x0080 D0 CSARO base address 0x00800000 to Ox009FFFFF move w move w 0x0D80 D0 CS
215. After IMRS is set the next access to an SDRAM block programs the SDRAM s mode register Thus the address of the access should be programmed to place the correct mode information on the SDRAM address pins Because the SDRAM does not register this information it doesn t matter if the IMRS access is a read or a write or what if any data is put onto the data bus The DRAM controller clears IMRS after the MRS command finishes 0 Take no action 1 Initiate MRS command 5 4 PS Port size Indicates the port size of the associated block of SDRAM which allows for dynamic sizing of associated SDRAM accesses PS functions the same in asynchronous operation 00 32 bit port 01 8 bit port 1x 16 bit port 3 IP Initiate precharge all PALL command The DRAM controller clears IP after the PALL command is finished Accesses via IP should be no wider than the port size programmed in PS 0 Take no action 1 A PALL command is sent to the associated SDRAM block During initialization this command is executed after all DRAM controller registers are programmed After IP is set the next write to an appropriate SDRAM address generates the PALL command to the SDRAM block 2 PM Page mode Indicates how the associated SDRAM block supports page mode operation 0 Page mode on bursts only The DRAM controller dynamically bursts the transfer if it falls within a single page and the transfer size exceeds the port size of the SDRAM block After the burst t
216. Assignment Register IRQPAR The interrupt port assignment register IRQPAR shown in Figure 9 5 provides the level assignment of the primary external interrupt pins IRQ5 IRQ3 The setting of IRQPAR2 IRQPARO determines the interrupt level of these external interrupt pins Field Reset R W Address 7 6 5 IRQPAR2 IRQPAR1 IRQPARO 0000 0000 R W MBAR 0x06 Figure 9 5 Interrupt Port Assignment Register IRQPAR Table 9 8 describes IRQPAR fields MOTOROLA Chapter 9 Interrupt Controller 9 7 Interrupt Controller Registers Table 9 8 IRQPAR Field Descriptions Bits Name Description 7 5 IRQPARn Configures the IRQ pin assignments and priorities IRQPARn External Pin IRQPARn 0 IRQPARn 1 IRQPAR2 IRQ5 Level 5 Level 4 IRQPAR1 IRQS Level 3 Level 6 IRQPARO IRQ1 Level 1 Level 2 4 0 Reserved should be cleared 9 8 MCF5307 User s Manual M woronoLA Chapter 10 Chip Select Module This chapter describes the MCF5307 chip select module including the operation and programming model of the chip select registers which include the chip select address mask and control registers 10 1 Overview The following list summarizes the key chip select features Eight independent user programmable chip select signals CS 7 0 that can interface with SRAM PROM EPROM EEPROM Flash and peripherals Address masking for 64 Kbyte
217. Breakpoint Mask Registers DBR DBMR The data breakpoint registers Figure 5 9 specify data patterns used as part of the trigger into debug mode Only DBR bits not masked with a corresponding zero in DBMR are compared with the data from the processor s local bus as defined in TDR 31 0 Field Data DBR Mask DBMR Reset Uninitialized R W is accessible in supervisor mode as debug control register OxOE using the WDEBUG instruction and through the BDM port using the RDMREG and WDMREG commands DBMR is accessible in supervisor mode as debug control register OxOF using the WDEBUG instruction and via the BDM port using the WOMREG command DRce 4 0 OxOE DBR OxOF DBMR Figure 5 9 Data Breakpoint Mask Registers DBR and DBMR 5 12 MCF5307 User s Manual M woronoLA Programming Model Table 5 9 describes DBR fields Table 5 9 DBR Field Descriptions Bits Name Description 31 0 Data Data breakpoint value Contains the value to be compared with the data value from the processor s local bus as a breakpoint trigger Table 5 10 describes DBMR fields Table 5 10 DBMR Field Descriptions Bits Name Description 31 0 Mask Data breakpoint mask The 32 bit mask for the data breakpoint trigger Clearing a DBR bit allows the corresponding DBR bit to be compared to the appropriate bit of the processor s local data bus Setting a DBMR bit causes that bit to be ignored
218. CRO three wait states AA 1 PS 16 bit BEM 0 move w D0O CSCRO BSTR 0 BSTW 0 Program Chip Select 0 Mask Register validate chip selects move l 0x001F0001 D0 Address range from 0x00800000 to Ox009FFFFF move l D0 CSMRO WP EM C 1I SC SD UC UD 0 V 1 10 10 MCF5307 User s Manual M woronoLA Chapter 11 Synchronous Asynchronous DRAM Controller Module This chapter describes configuration and operation of the synchronous asynchronous DRAM controller component of the system integration module SIM It begins with a general description and brief glossary and includes a description of signals involved in DRAM operations The remainder of the chapter consists of the two following parts Section 11 3 Asynchronous Operation describes the programming model and signal timing for the four basic asynchronous modes Non page mode Burst page mode Continuous page mode Extended data out mode Section 11 4 Synchronous Operation describes the programming model and signal timing as well as the command set required for synchronous operations This section also includes extensive examples the designer can follow to better understand how to configure the DRAM controller for synchronous operations 11 1 Overview The DRAM controller module provides glueless integration of DRAM with the ColdFire product The key features of the DRAM controller include the following e Support for two independent blocks of DRAM In
219. CS 7 0 BE BWE 3 0 TA and all DRAM controller signals RAS 1 0 CAS 8 0 SRAS SCAS DRAMW SCKE If the MCF5307 is the only possible master BG can be tied to GND no arbiter is needed 18 8 1 Bus Arbitration Signals Bus arbitration signal timings in Table 18 7 are referenced to the system clock which is not considered a bus signal Clock routing is expected to meet application requirements Table 18 7 ColdFire Bus Arbitration Signal Summary Signal 1 0 Description BR request Indicates to an external arbiter that the processor needs to become bus master BR is negated when the MCF5307 begins an access to the external bus with no other internal accesses pending BR remains negated until another internal request occurs BG Bus grant An external arbiter asserts BG to indicate that the MCF5307 can control the bus the next rising edge of BCLKO When the arbiter negates BG the MCF5307 must release the bus as Soon as the current transfer completes The external arbiter must not grant the bus to any other device until both BD and BG are negated BD Bus driven The MCF5307 asserts BD to indicate it is current master and is driving the bus If it loses bus mastership during a transfer it completes the last transfer of the current access negates BD and three states all bus signals on the rising edge of BCLKO If it loses mastership during an idle clock cycle it three states all
220. ColdFire instruction set Typically system programmers use the supervisor programming model to implement operating system functions and provide I O MCF5307 User s Manual M woronoLA Programming Model Addressing Modes and Instruction Set control The supervisor programming model provides access to the same registers as the user model plus additional registers for configuring on chip system resources as described in Section 1 4 3 Supervisor Registers Exceptions including interrupts are handled in supervisor mode 1 4 1 Programming Model Figure 1 4 shows the MCF5307 programming model 31 0 31 User Registers 31 31 19 15 CCR Must be zeros Supervisor Registers DO MACSR ACC MASK SR VBR CACR ACRO ACR1 RAMBAR MBAR Data registers Address registers Stack pointer Program counter Condition code register MAC status register MAC accumulator MAC mask register Status register Vector base register Cache control register Access control register 0 Access control register 1 RAM base address register Module base address register Figure 1 4 ColdFire MCF5307 Programming Model M MOTOROLA Chapter 1 Overview Programming Model Addressing Modes and Instruction Set 1 4 2 User Registers The user programming model is shown in Figure 1 4 and summarized in Table 1 1 Tab
221. Continued Bits Name Description 16 START Start transfer 0 DMA inactive 1 The DMA begins the transfer in accordance to the values in the control registers START is cleared automatically after one clock and is always read as logic 0 15 AT AT is available only if BCR24BIT 1 DMA acknowledge type Controls whether acknowledge information is provided for the entire transfer or only the final transfer 0 Entire transfer DMA acknowledge information is displayed anytime the channel is selected as the result of an external request 1 Final transfer when BCR reaches zero For dual address transfer the acknowledge information is displayed for both the read and write cycles 14 0 Reserved should be cleared 12 4 5 DMA Status Registers DSRO DSR3 In response to an event the DMA controller writes to the appropriate DSRz bit Figure 12 9 Only a write to DSRn DONE results in action 7 6 5 4 3 2 1 0 Field CE BES BED REQ BSY DONE Reset 0 0 0 0 0 0 R W R W Address MBAR 0x310 0x350 0x390 0x3D0 Figure 12 9 DMA Status Registers DSRn Table 12 4 describes DSRn fields Table 12 4 DSRn Field Descriptions Bits Name Description 7 Reserved should be cleared 6 CE Configuration error Occurs when BCR SAR or DAR does not match the requested transfer size or if BCR 0 when the DMA receives a start condition CE is clea
222. DATA output 5 8 1 User Instruction Set Table 5 22 shows the PST DDATA specification for user mode instructions Rn represents any Dn An register In this definition the y suffix generally denotes the source and x denotes the destination operand For a given instruction the optional operand data is displayed only for those effective addresses referencing memory The DD nomenclature refers to the DDATA outputs Table 5 22 PST DDATA Specification for User Mode Instructions Instruction Operand Syntax PST DDATA ea y Rx PST 0x1 PST 0xB DD source operand Dy lt ea gt x PST 0 1 PST DD source PST 0xB DD destination addi l imm Dx PST 0x1 addq imm lt ea gt x PST 0 1 PST DD source PST 0xB DD destination Dy Dx PST 0 1 ea y Dx PST 0x1 PST 0 DD source operand 1 Dy lt ea gt x PST 0 1 PST OxB DD source PST 0xB DD destination andi l imm Dx PST 0x1 asl l Dy imm Dx PST 0 1 asr l Dy imm Dx PST 0x1 bcc b w if taken then PST 0x5 else PST 0 1 bchg imm lt ea gt x PST 0x1 PST 0x8 DD source PST 0x8 DD destination bchg Dy lt ea gt x PST 0x1 PST 0x8 DD source PST 0x8 DD destination belr imm lt ea gt x PST 0x1 PST 0x8 DD source PST 0x8 DD destination
223. DDR 15 0 Field PADAT Reset 0000 0000 0000 0000 R W R W Address Address MBAR 0x248 Figure 15 3 Port A Data Register PADAT Table 15 3 shows relationships between PADAT bits and parallel port pins when PADAT is accessed The effect differs when the parallel port pin is an input or output The following results occur when a parallel port pin is configured as an input When the PADAT is read the value returned is the logic value on the pin When the PADAT is written the register contents are updated without affecting the logic value on the pin The following results occur when a parallel port pin is configured as an output When the PADAT is read the register contents are returned and the pin is the logic value of the register e When the PADAT is written the register contents are updated and the pin is the logic value of the register These relationships are also described in Table 15 3 Table 15 3 Relationship between PADAT Register and Parallel Port Pin PP PP Status PADAT R W Effect on PADAT Effect on PP ibt Read Register bit value is the pin s logic value No effect Source of logic value Write Register contents updated No effect on the logic value at the pin Read Register contents are returned Pin is the logic value of the register bit Output Write Register contents updated Pin is the logic value of the register bit NOTE Although external devices cannot access the MCF5307 s o
224. DGESEL tied high 20 8 MCF5307 User s Manual M woronoLA Input Output AC Timing Specifications o0 131 2 3 4 5 e 7 8 29 10 111 12 A A X AL 31 0 X Row X Column M DRAMW 7 X X N D 31 0 Fog Dia RAS gt 69 2 1 1 ACTV NOP WRITE NOP PALL 1 DACR CASL 2 Figure 20 7 SDRAM Write Cycle with EDGESEL Tied High Figure 20 8 shows an SDRAM read cycle with EDGESEL tied low M woronoLA Chapter 20 Electrical Specifications 20 9 Input Output AC Timing Specifications 1 2 4 5 6 10 11 12 13 t4 15 X E A E 6 A 31 0 x Row n Column X i DRAMW 7 0 31 0 dj gt 02 mi g ACTV NOP READ NOP NOP PALL 1 DACR CASL 2 Figure 20 8 SDRAM Read Cycle with EDGESEL Tied Low Figure 20 9 shows an SDRAM write cycle with EDGESEL tied low 20 10 MCF5307 User s Manual M Input Output AC Timing Specifications 0 1 2 4 5 6 7 8 9 10 11 12 X X A 31 0 X Row x Column A E DRAMW 7 X X N 0131 0 E Or I os X Lan ACTV NOP WRITE NOP PALL
225. DMA controller module Note that DCR AT is available only if BCR24BIT 1 31 30 20 28 27 25 24 23 22 21 20 19 18 17 16 Field INT EEXT CS AA BWC SAA 5 RW SINC SSIZE DINC DSIZE START Reset 0000 0000 0000 0000 R W R W 15 14 0 Field AT Reset 0 N A R W R W Address MBAR 0x308 0x348 0x388 0x3A8 Figure 12 8 DMA Control Registers DCRn Available only if BCR24BIT 1 otherwise reserved Table 12 3 describes DCR fields Table 12 3 DCRn Field Descriptions Bits Name Description 31 INT Interrupt on completion of transfer Determines whether an interrupt is generated by completing a transfer or by the occurrence of an error condition 0 No interrupt is generated 1 Internal interrupt signal is enabled 30 EEXT Enable external request Care should be taken because a collision can occur between the START bit and DREQ when EEXT 1 0 External request is ignored 1 Enables external request to initiate transfer Internal request is always enabled It is initiated by writing a 1 to the START bit 12 8 MCF5307 User s Manual M woronoLA DMA Controller Module Programming Model Table 12 3 DCRn Field Descriptions Continued Bits Name Description 29 CS Cycle steal 0 DMA continuously makes read write transfers until the BCR decrements to 0 1 Forces a single read write transfer p
226. DRAM Row Address Strobe SRAS The synchronous DRAM row address strobe output SRAS is registered during synchronous mode to route directly to the SRAS signal of external SDRAMs 17 7 6 Synchronous DRAM Clock Enable SCKE The synchronous DRAM clock enable output SCKE is registered during synchronous mode to route directly to the SCKE signal of external SDRAMs This signal provides the clock enable to the SDRAM 17 7 7 Synchronous Edge Select EDGESEL The synchronous edge select input EDGESEL helps select additional output hold times for signals that interface to external SDRAMs It provides the following three modes of operation for SDRAM control signals When EDGESEL is tied high SDRAM control signals change on the rising edge of BCLKO When EDGESEL is tied low SDRAM control signals change on the falling edge of BCLKO When EDGESEL is tied to the external clock normally buffered BCLKO which drives the SDRAM and other devices SDRAM signals are generated within the MCF5307 make a transition on the rising edge of the SDRAM clock See Figure 11 14 on page 11 19 This loop back configuration provides additional output hold time for MCF5307 interface signals provided to the SDRAM In this case the SDRAM clock operates at the BCLKO frequency with a possible slight phase delay 17 8 DMA Controller Module Signals The DMA controller module uses the signals in the following subsections to provide external request for eit
227. Data Array ZEND System xN ColdFire Integration Processor i Module Core Directory Array SIM Data Data Address X Address Path Figure 4 2 Unified Cache Organization The cache supports operation of copyback write through or cache inhibited modes The cache lock feature can be used to guarantee deterministic response for critical code or data areas A nonblocking cache services read hits or write hits from the processor while a fill caused by cache allocation is in progress As Figure 4 2 shows instruction and data accesses use a single bus connected to the cache All addresses from the processor to the cache are physical addresses A cache hit occurs when an address matches a cache entry For a read the cache supplies data to the processor For a write the processor updates the cache If an access does not match a cache entry misses the cache or if a write access must be written through to memory the cache performs a bus cycle on the internal bus and correspondingly on the external bus by way of the system integration module SIM The SRAM module does not implement bus snooping cache coherency with other possible bus masters must be maintained in software 4 8 Cache Organization A four way set associative cache is organized as four ways levels There are 128 sets in the 8 Kbyte cache with each line containing 16 bytes 4 longwords Enti
228. Data bus 8 129 Power input 130 D13 VO Data bus 8 131 D12 VO Data bus 8 132 D11 VO Data bus 8 133 GND Ground pin 134 D10 VO Data bus 8 135 D9 VO Data bus 8 136 D8 s Data bus 8 137 Power input 138 D7 CS_CONF2 lO Data bus Chip select configuration 8 139 D6 CS CONF1 lO Data bus Chip select configuration 8 140 D5 CS CONFO lO Data bus Chip select configuration 8 141 GND Ground pin MOTOROLA Chapter 16 Mechanical Data Pinout 16 5 Pinout Table 16 3 Pins 105 156 Right Bottom to Top Continued Description QUA No Name 142 D4 ADDR CONF Data bus Address configuration 8 143 D3 FREQ1 Data bus CLKIN Frequency 144 D2 FREQO Data bus CLKIN Frequency 145 Power input 146 D1 DIVIDE1 Data bus Divide control PCLK BCLKO 147 DO DIVIDEO Data bus Divide control PCLK BCLKO 148 GND Ground pin 149 DSCLK TRST Debug serial clock JTAG Reset 150 TCK TCK JTAG clock 151 DSO TDO Debug serial out JTAG data out 8 152 Power input 153 DSI TDI Debug serial input JTAG data in 154 BKPT TMS Debug breakpoint JTAG mode select 155 HIZ High impedance override 156 GND Gr
229. F5307 input clock frequency to the on board phase locked loop PLL clock generator CLKIN is used to internally clock or sequence the MCF5307 internal bus interface at a selected multiple of the input frequency used for internal module logic 17 5 3 Bus Clock Output BCLKO The internal PLL generates BCLKO and can be programmed to be 1 2 1 3 or 1 4 of the processor clock frequency BCLKO should be used as the bus timing reference 17 5 4 Reset Out RSTO After RSTI is asserted the PLL temporarily loses its lock during which time RSTO is asserted When the PLL regains its lock RSTO negates again This signal can be used to reset external devices 17 5 5 Data Configuration Pins D 7 0 This section describes data pins D 7 0 that are read at reset for configuration Table 17 11 shows pin assignments M MOTOROLA Chapter 17 Signal Descriptions 17 13 Clock and Reset Signals Table 17 11 Data Pin Configuration Pin Function D7 Auto acknowledge configuration AA CONFIG D 6 5 Port size configuration PS CONFIG 1 0 D4 Address configuration ADDR_CONFIG D4 D 3 2 Frequency Control PLL FREQ 1 0 D 1 0 Divide Control DIVIDE 1 0 17 5 5 1 D 7 5Boot Chip Select CSO Configuration D 7 5 determine defaults for the global chip select CSO the only chip select valid at reset These signals correspond to bits in chip select configuration register 0 CSCRO 17 5 5 2 D7 Auto Acknowledge Configuratio
230. For each ASn bit 0 An access to the SRAM module can occur for this address space 1 Disable this address space from the SRAM module If a reference using this address space is made it is inhibited from accessing the SRAM module and is processed like any other non SRAM reference 0 V Valid Enables disables the SRAM module V is cleared at reset 0 RAMBAR contents are not valid 1 RAMBAR contents are valid The mapping of a given access into the RAM uses the following algorithm to determine if the access hits in the memory if RAMBAR 0O 1 if requested address 31 15 RAMBAR 31 15 if requested address 14 12 0 if ASn of the requested type 0 Access is mapped to the RAM module if access read Read the RAM and return the data if access write if RAMBAR 8 0 Write the data into the RAM else Signal a write protect access error ASn refers to the five address space mask bits C I SC SD UC and UD 4 5 SRAM Initialization After a hardware reset the contents of the SRAM module are undefined The valid bit RAMBAR V is cleared disabling the SRAM module If the SRAM requires initialization with instructions or data the following steps should be performed 1 Read the source data and write it to the SRAM Various instructions support this function including memory to memory move instructions and the move multiple instruction MOVEM MOVEM is optimized to generate line sized burst fet
231. High parity 10 No parity n a 11 Multidrop mode Data character Address character 1 0 B C Bits per character Select the number of data bits per character to be sent The values shown do not include start parity or stop bits 00 5 bits 01 6 bits 10 7 bits 11 8 bits MOTOROLA Chapter 14 UART Modules 14 5 Register Descriptions 14 3 2 UART Mode Register 2 UMR2n UART mode registers 2 UMR2n control UART module configuration UMR2n can be read or written when the mode register pointer points to it which occurs after any access to UMRI1n UMR2n accesses do not update the pointer 7 6 5 4 3 0 Field CM TxRTS TxCTS SB Reset 0000 0000 R W R W Address MBAR 0x1C0 0x200 After UMR1n is read or written the pointer points to UMR2n Figure 14 3 UART Mode Register 2 UMR2n Table 14 3 describes UMR2n fields Table 14 3 UMR2n Field Descriptions Bits Name Description 7 6 CM Channel mode Selects a channel mode Section 14 5 3 Looping Modes describes individual modes 00 Normal 01 Automatic echo 10 Local loop back 11 Remote loop back 5 TxRTS Transmitter ready to send Controls negation of RTS to automatically terminate a message transmission Attempting to program a receiver and transmitter in the same channel for RTS control is not permitted and disables RTS control for both 0 The transmitter has no effect on RTS 1 In applications where the transm
232. IDCODE Bit Assignments Bits Description 31 28 Version number Indicates the revision number of the MCF5307 27 22 Design center Indicates the ColdFire design center 21 12 Device number Indicates an MCF5307 11 1 Indicates the reduced JEDEC ID for Motorola Joint Electron Device Engineering Council JEDEC Publication 106 A and Chapter 11 of the IEEE Standard 1149 1 give more information on this field 0 Identifies this as the JTAG IDCODE register and not the bypass register according to the IEEE Standard 1149 1 19 6 MCF5307 User s Manual M woronoLA 19 4 3 JTAG Boundary Scan Register The MCF5307 model includes an IEEE Standard 1149 1 compliant boundary scan register connected between TDI and TDO when the EXTEST or SAMPLE PRELOAD instructions are selected This register captures signal data on the input pins forces fixed values on the output pins and selects the direction and drive characteristics a logic value or high impedance of the bidirectional and three state pins Table 19 4 shows MCF5307 boundary scan register bits JTAG Register Descriptions Table 19 4 Boundary Scan Bit Definitions Bit Cell Type Pin Cell Pin Type Bit Cell Type Pin Cell Pin Type 0 O Ctl PPO enable 120 O Pin BEO 1 O Pin PPO VO 121 O Pin SCKE 9 2 I Pin PPO VO 122 O Pin SCAS 3
233. IEEE Standard Test Access Port and Boundary Scan Architecture IEEE Supplement to Standard Test Access Port and Boundary Scan Architecture 1149 1 Acronyms and Abbreviations Table IV i describes acronyms and abbreviations used in Part IV Table IV i Acronyms and Abbreviated Terms C femm NNI IV ii MCF5307 User s Manual M Table IV i Acronyms and Abbreviated Terms Continued m RISC Reduced instruction set computing M MOTOROLA Part IV Hardware Interface IV iii IV iv MCF5307 User s Manual M Chapter 16 Mechanical Data This chapter provides a function pin listing and package diagram for the MCF5307 See the website http www w motorola com coldfire for any updated information 16 1 Package The MCF5307 is assembled in a 208 pin thermally enhanced plastic QFP package 16 2 Pinout The MCF5307 pinout is detailed in the following tables including the primary and secondary functions of multiplexed signals Additional columns indicate the output drive capability of each pin whether it is internally synchronized and if the signal can change on a negative clock transition These tables show MCF5307 pin numbers including signal multiplexing Additional columns indicate the direction description and output drive capability of each pin Table 16 1 Pins 1 52 Left Top to Bottom E Des
234. IEIE SS 77 on E lt D co Note Parallel port pins are multiplexed with other bus functions as shown C is a Philips proprietary interface Figure 17 1 MCF5307 Block Diagram with Signal Interfaces Table 17 1 lists the MCF5307 signals grouped by functionality 17 2 MCF5307 User s Manual M woronoLA Table 17 1 MCF5307 Signal Index Overview Signal Name Abbreviation Function VO Reset Pull Up Page Section 17 2 MCF5307 Bus Signals 17 7 Address A 31 0 32 bit address bus A 4 2 indicate VO Three 17 7 the interrupt level for external state interrupts Data D 31 0 Data bus D 7 0 are loaded at reset I O Three 17 8 for bus configuration state Read Write R W Identifies read and write transfers Three Up 17 8 state Size SIZ 1 0 Indicates the data transfer size VO Three 17 8 state Transfer start TS Indicates the start of a bus transfer I O Three 17 9 state Address strobe AS Indicates a bus cycle has been Three Up 17 9 initiated and address is stable state Transfer acknowledge TA Assertion terminates transfer VO Three Up 17 9 synchronously state Transfer in progress TIP PP7 Indicates a bus cycle is in progress O Parallel 17 10 multiplexed with PP7 port Transfer type TT 1 0 Indicates transfer type normal CPU O Parallel 17 10 space emula
235. IN frequency range 17 15 Divide control PCLK DIVIDE 1 0 Indicates the BCLKO PSTCLK ratio 17 15 BCLKO Section 17 6 Chip Select Module Signals 17 15 Chip selects 7 0 CS 7 0 Enables peripherals at programmed O High 17 16 addresses CSO provides boot ROM selection Byte enable 3 0 BE 3 0 BE 3 0 select bytes in memory High 17 16 Byte write enable 3 0 BWE 3 0 Output enable OE Output enable for chip select read High 17 16 cycles Section 17 7 DRAM Controller Signals 17 16 Row address strobe RAS 1 0 DRAM row address strobe High 17 16 Column address strobe CAS 3 0 DRAM column address strobe High 17 16 DRAM write DRAMW Asserted for DRAM write negated High 17 17 for DRAM read Synchronous column SCAS SDRAM column address strobe High 17 17 address strobe Synchronous row SRAS SDRAM row address strobe High 17 17 address strobe Synchronous clock SCKE Clock enable for external SDRAM Low 17 17 enable Synchronous edge EDGESEL Timing select for external SDRAM User cfg 17 17 select Section 17 8 DMA Controller Module Signals 17 17 DMA request DREQ 1 0 External DMA transfer request 17 18 multiplexed with PP 6 5 Section 17 9 Serial Module Signals 17 18 Receive data RxD 1 0 Receive serial data input for UART 17 18 Transmit data TxD 1 0 Transmit serial data output for UART High 17 18 Request to send RTS 1 0 UART asserts when ready to High 17 18 receive data que
236. Index 22 MCF5307 User s Manual M MOTOROLA Overview Part MCF5307 Processor Core ColdFire Core Hardware Multiply Accumulate MAC Unit Local Memory Debug Support Part Il System Integration Module SIM SIM Overview Phase Locked Loop PLL IC Module Interrupt Controller Chip Select Module Synchronous Asynchronous DRAM Controller Module Part III Peripheral Module DMA Controller Module Timer Module UART Modules Parallel Port General Purpose I O Part IV Hardware Interface Mechanical Data Signal Descriptions Bus Operation IEEE 1149 1 Test Access Port JTAG Electrical Specifications Appendix Memory Map Glossary of Terms and Abbreviations Index Part Part Il ES Part III ps A ENS Eu mr Part IV lt gt ELEM r Part Part Il E ENS E Part 111 gt EM ON B Part IV N lt gt ES ES ES E A 9 Te Overview Part MCF5307 Processor Core ColdFire Core Hardware Multiply Accumulate MAC Unit Local Memory Debug Support Part Il System Integration Module SIM SIM Overview Phase Locked Loop PLL I C Module Interrupt Controller Chip Select Module Synchronous Asynchronous DRAM Controller Module Part III Peripheral Module DMA Contro
237. KEN IF OPERATION HAS NOT COMPLETED NEXT READ Es COMMAND MS ADDR LS ADDR MEMORY m CODE NOT READY NOT READY LOCATION XXX READY NEXT CMD LS RESULT XXX NEXT CMD gt BERR NOT READY SEQUENCE TAKEN IF BUS SEQUENCE TAKEN IF ERROR OCCURS ON ILLEGAL COMMAND MEMORY ACCESS IS RECEIVED BY DEBUG MODULE DATA UNUSED FROM THIS TRANSFER N NEXT CMD ILLEGAL NOT READY HIGH AND LOW ORDER RESULTS FROM PREVIOUS COMMAND 16 BITS OF RESULT RESPONSES FROM THE DEBUG MODULE Figure 5 17 Command Sequence Diagram The sequence is as follows 5 22 In cycle 1 the development system command is issued READ in this example The debug module responds with either the low order results of the previous command or a command complete status of the previous command if no results are required In cycle 2 the development system supplies the high order 16 address bits The debug module returns a not ready response unless the received command is decoded as unimplemented which is indicated by the illegal command encoding If this occurs the development system should retransmit the command NOTE A not ready response can be ignored except during a memory referencing cycle Otherwise the debug module can accept a new serial transfer after 32 processor clock periods In cycle 3 the development system supplies the low order 16 ad
238. Kbyte block of each 1 Mbyte partition in the SDRAM each 16 Mbytes The starting address of the SDRAM is OxFF80 0000 Continuous page mode feature is used M MOTOROLA Chapter 11 Synchronous Asynchronous DRAM Controller Module 11 35 SDRAM Example SDRAM Component Accessible Memory Bank 0 Bank 1 Bank 2 Bank 3 512 Kbyte 512 Kbyte 512 Kbyte 512 Kbyte 1 Mbyte 1 Mbyte 1 Mbyte 1 Mbyte 512 Kbyte 512 Kbyte 512 Kbyte 512 Kbyte Figure 11 26 SDRAM Configuration The DACRs should be programmed as shown in Figure 11 27 31 18 17 16 Field BA Setting 1111_1111_1000_10 XX hex 15 15 8 8 15 14 13 12 11 10 8 7 6 5 4 3 2 1 0 Field RE CASL CBM IMRS PS IP PM Setting 0 00 X 011 X 0 00 0 1 Xx hex 0 3 0 4 Figure 11 27 DACR Register Configuration This configuration results in a value of DACRO OxFF88_0304 as described in Table 11 35 DACRI initialization is not needed because there is only one block Subsequently DACR1 RE IMRS IP should be cleared everything else is a don t care Table 11 35 DACR Initialization Values Bits Name Setting Description 31 18 BA Base address So DACRO 31 16 OxFF88 which places the starting address of the SDRAM accessible memory at OXFF88 0000 17 16 Reserved Don t care 15 RE 0
239. L Used with WRITE to fill large blocks of memory An Steal 5 5 3 3 6 0x1C00 byte block initial WRITE is executed to set up the starting 0x1C40 word address of the block and to supply the first operand 0x1C80 Iword A FILL command writes subsequent operands Resume GO The pipeline is flushed and refilled before resuming Halted 5 5 3 3 7 0x0C00 execution instruction execution at the current PC No operation NOP Perform no operation may be used as a null Parallel 5 5 3 3 8 0x0000 command Output the SYNC PC Capture the current PC and display it on the Parallel 5 5 3 3 9 0x0001 current PC PST DDATA output pins Read control RCREG Read the system control register Halted 5 5 3 3 10 0x2980 register Write control WCREG Write the operand data to the system control Halted 5 5 3 3 11 0x2880 register register Read debug RDMREG Read the debug module register Parallel 5 5 3 3 12 0x2D 0x42 module DRc 4 0 register Write debug WOMREG Write the operand data to the debug module Parallel 5 5 3 3 13 Ox2C 0x4 module register Drc 4 0 register General command effect and or requirements on CPU operation Halted The CPU must be halted to perform this command Steal Command generates bus cycles that can be interleaved with bus accesses Parallel Command is executed in parallel with CPU activity 2 0x4is a three bit field Unassigned command opcodes are reserved by Motorola All unused
240. LA INDEX Index C CCR 2 28 Chip select module 8 16 and 32 bit port sizing 10 4 enable signals 17 15 operation 10 2 general 10 3 global 10 4 overview 10 1 registers 10 5 10 6 A 2 code example 10 9 control 10 8 mask 10 6 signals 10 1 Clock PLL control 6 10 ColdFire core addressing mode summary 2 33 condition code register CCR 2 28 exception processing overview 2 47 features and enhancements 2 21 instruction set summary 2 34 integer data formats 2 31 MAC registers 1 14 programming model 2 26 status register 2 29 supervisor programming model 2 29 user programming mode 2 27 CPU STOP instruction 6 10 D Debug attribute trigger register 5 7 BDM command set summary 5 20 breakpoint operation 5 40 real time support 5 39 taken branch 5 4 theory 5 40 DMA controller module byte count registers 12 7 programming model 12 4 signal description 12 2 source address registers 12 6 timing specifications 20 19 transfer overview 12 3 DRAM controller asynchronous operation Index 17 burst page mode 11 12 continuous page mode 11 13 extended data out 11 15 general 11 4 mode signals 11 4 register set 11 4 general guidelines 11 8 non page mode 11 11 refresh operation 11 16 registers 11 3 address and control 11 5 mask 11 7 signals 17 16 synchronous operation address and control registers 11 20 address multiplexing 11 23 auto refresh 11 31 burst page mode 11
241. LKO PCLK ratio 1 2 1 3 1 4 7 2 PLL Operation The following sections provide detailed information about the three PLL modes 7 2 1 Reset Initialization The PLL receives RSTI as an input directly from the pin Additionally signals are multiplexed with D 3 0 FREQ 1 0 DIVIDE 1 0 while RSTI is asserted These signals are sampled during reset and registered by the PLL on the negation of RSTI to provide initialization information FREQ 1 0 and DIVIDE 1 0 are used by the PLL to select the CLKIN frequency range and set the CLKIN PCLK ratio respectively 7 2 2 Normal Mode PCLK is divided to create the system bus clock BCLKO At reset the logic level of DIVIDE 1 0 D 1 0 determines the BCLKO divisor The bus clock can be 1 2 1 3 or 1 4 of the PCLK frequency 7 2 3 Reduced Power Mode The PCLK can be turned off in a predictable manner to conserve system power To allow fast restart of the MCF5307 processor core the PLL continues to operate at the frequency configured at reset PCLK is disabled using the CPU STOP instruction and resumes normal operation on interrupt as described in Section 7 2 4 PLL Control Register PLLCR 7 2 MCF5307 User s Manual M woronoLA PLL Port List 7 2 4 PLL Control Register PLLCR The PLL control register PLLCR Figure 7 2 provides control over the PLL 7 6 5 4 3 2 1 0 Field ENBSTOP PLLIPL Reset 0000_0000 R W R W Address MBAR 0x08
242. LLING A0 Transmit the calling address DO R W MOVE B 0 I2DR IFREE MOVE B I2SR A0 Check I2SR MBB If it is clear wait until it is set BTST B 5 0 BEQ S IFREE 8 6 3 Post Transfer Software Response Sending or receiving a byte sets the IDSR ICF which indicates one byte communication is finished I2SR IIF is also set An interrupt is generated if the interrupt function is enabled during initialization by setting I2CR IIEN Software must first clear in the interrupt routine ICF is cleared either by reading from I2DR in receive mode or by writing to I2DR in transmit mode Software can service the I C I O in the main program by monitoring IIF if the interrupt function is disabled Polling should monitor IIF rather than ICF because that operation is different when arbitration is lost When an interrupt occurs at the end of the address cycle the master is always in transmit mode that is the address is sent If master receive mode is required I2DR R W I2CR MTX should be toggled During slave mode address cycles I2SR IAAS 1 IDSR SRW is read to determine the direction of the next transfer MTX is programmed accordingly For slave mode data cycles AAS 0 SRW is invalid MTX should be read to determine the current transfer direction The following is an example of a software response by a master transmitter in the interrupt routine see Figure 8 10 I2SR LEA L I2SR A7 Load effective address BCL
243. M Interface 16 Bit Port 12 Column Address Lines 11 26 11 25 MCFS 307to SDRAM Interface 16 Bit Port 13 Column Address Lines 11 26 11 26 5307 to SDRAM Interface 32 Bit Port 8 Column Address Lines 11 26 11 27 5307 to SDRAM Interface 32 Bit Port 9 Column Address Lines 11 26 11 28 5307 to SDRAM Interface 32 Bit Port 10 Column Address Lines 11 26 11 29 5307 to SDRAM Interface 32 Bit Port 11 Column Address Lines 11 27 11 30 5307 to SDRAM Interface 32 Bit Port 12 Column Address Lines 11 27 11 31 SDRAM Hardware enne ener entente 11 27 11 32 SDRAM Example Specifications 11 34 11 33 SDRAM Hardware Connections essent enne 11 35 M MOTOROLA Tables xxvii TABLES Table Number Hae Number 11 34 DCR Initialization Values eet trente tratara aeneae 11 35 11 35 Initialization eee emen 11 36 11 36 DMRO Initialization Values eese nennen nennen 11 37 11 37 Mode Register Initialization eese 11 38 12 1 DMA EE 12 2 12 2 Memory Map for DMA Controller Module Registers sese 12 5 12 3 DCR7 Field Descriptions 12 8 12 4 DSRn Field Descriptions 12 10 13 1 General Purpose T
244. MA channel is in dual or single address mode 0 Dual address mode 1 Single address mode The DMA provides an address from the SAR and directional control bit S RW to allow two peripherals one might be memory to exchange data within a single access Data is not stored by the DMA 23 S RW Single address access read write value Valid only if SAA 1 Specifies the value of the read signal during single address accesses This provides directional control to the bus controller 0 Forces the read signal to 0 1 Forces the read signal to 1 22 SINC Source increment Controls whether a source address increments after each successful transfer 0 No change to SAR after a successful transfer 1 The SAR increments by 1 2 4 or 16 as determined by the transfer size 21 20 SSIZE Source size Determines the data size of the source bus cycle for the DMA control module 00 Longword 01 Byte 10 Word 11 Line 19 DINC Destination increment Controls whether a destination address increments after each successful transfer 0 No change to the DAR after a successful transfer 1 The DAR increments by 1 2 4 or 16 depending upon the size of the transfer 18 17 DSIZE Destination size Determines the data size of the destination bus cycle for the DMA controller 00 Longword 01 Byte 10 Word 11 Line M Chapter 12 DMA Controller Module 12 9 DMA Controller Module Programming Model Table 12 3 DCRn Field Descriptions
245. MC5307 This revision of the ColdFire debug architecture encompasses the earlier revision 5 1 Overview The debug module is shown in Figure 5 1 High speed ColdFire CPU Core T local bus Debug Module DDATA 3 ol Communication Port BKPT 10 PSTCLK DSCLK DSI DSO Figure 5 1 Processor Debug Module Interface Debug support is divided into three areas Real time trace support The ability to determine the dynamic execution path through an application is fundamental for debugging The ColdFire solution implements an 8 bit parallel output bus that reports processor execution status and data to an external emulator system See Section 5 3 Real Time Trace Support Background debug mode BDM Provides low level debugging in the ColdFire processor complex In BDM the processor complex is halted and a variety of commands can be sent to the processor to access memory and registers The external emulator uses a three pin serial full duplex channel See Section 5 5 Background Debug Mode BDM and Section 5 4 Programming Model Real time debug support BDM requires the processor to be halted which many real time embedded applications cannot do Debug interrupts let real time systems execute a unique service routine that can quickly save the contents of key registers and variables and return the system to normal operation The emulator can access saved data because the hardware supports concur
246. MCF5307 ColdFire Integrated Microprocessor User s Manual MCF5307UM D Rev 2 0 08 2000 Digital DNA 68KOKHIRE M woronoLA ColdFire is a registered trademark and DigitalDNA is a trademark of Motorola Inc is a registered trademark of Philips Semiconductors Motorola reserves the right to make changes without further notice to any products herein Motorola makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Motorola assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters which may be provided in Motorola data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts Motorola does not convey any license under its patent rights nor the rights of others Motorola products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur Should Buyer purchase or use Motorola
247. Mbytes 22 22 21 8 Mbytes 24 24 23 32 Mbytes 11 10 MCF5307 User s Manual M woronoLA Asynchronous Operation Table 11 9 DRAM Addressing for 32 Bit Wide Memories MCF5307 Address MCF5307 Address Bit MCF5307 Address Bit Driven Memory Size Pin Driven for RAS when CAS is Asserted 15 15 2 14 14 3 13 13 4 12 12 5 Base Memory Size of 11 11 6 64 Kbytes 10 10 T 9 9 8 17 17 16 256 Kbytes 19 19 18 1 Mbyte 21 21 20 4 Mbytes 23 23 22 16 Mbytes 25 25 24 64 Mbytes 11 3 3 1 Non Page Mode Operation In non page mode the simplest mode the DRAM controller provides termination and runs a separate bus cycle for each data transfer Figure 11 5 shows a non page mode access in which a DRAM read is followed by a write Addresses for a new bus cycle are driven at the rising clock edge For a DRAM block hit the associated RAS is driven at the next falling edge Here DACRn RCD 0 so the address is multiplexed at the next rising edge to provide the column address The required CAS signals are then driven at the next falling edge and remain asserted for the period programmed in DACRn CAS Here DACRn RNCN 1 so it is precharged one clock before CAS is negated On a read data is sampled on the last rising edge of the clock that CAS is valid BCLKO A 31 0 x pem X m X X RAS 1 or 0 DACRn RCD
248. O is three stated It can also be placed in three state mode to allow bussed or parallel connections to other devices having JTAG DSO provides single bit communication for debug module commands See Chapter 5 Debug Support TRST DSCLK Test reset MTMODO high development serial clock MTMODO low As TRST this pin asynchronously resets the internal JTAG controller to the test logic reset state causing the JTAG instruction register to choose the IDCODE instruction When this occurs all JTAG logic is benign and does not interfere with normal MCF5307 functionality Although this signal is asynchronous Motorola recommends that TRST make only an asserted to negated transition while TMS is held at a logic 1 value TRST has an internal pull up if it is not driven low its value defaults to a logic level of 1 However if TRST is not used it can either be tied to ground or if TCK is clocked to VDD The former connection places the JTAG controller in the test logic reset state immediately the latter connection eventually puts the JTAG controller if TMS is a logic 1 into the test logic reset state after 5 TCK cycles DSCLK is the development serial clock for the serial interface to the debug module The maximum DSCLK frequency is 1 2 the BCLKO frequency See Chapter 5 Debug Support 19 3 TAP Controller The state of TMS at the rising edge of TCK determines the current state of the TAP controller The TAP controll
249. OE signal is sent to the interfacing memory and or peripheral to enable a read transfer OE is asserted only when a chip select matches the current address decode 17 7 DRAM Controller Signals The DRAM signals in the following sections interface to external DRAM DRAM with widths of 8 16 and 32 bits are supported and can access as much as 512 Mbytes of DRAM 17 7 1 Row Address Strobes RAS 1 0 The row address strobes RAS 1 0 interface to RAS inputs on industry standard ADRAMs When SDRAMs are used these signals interface to the chip select lines of the SDRAMs within a memory block Thus there is one RAS line for each memory block 17 7 2 Column Address Strobes CAS 3 0 The column address strobes CAS 3 0 interface to CAS inputs on industry standard DRAMs These provide CAS for a given block When SDRAMs are used CAS signals control the byte enables for standard SDRAMs referred to as DQMx CAS3 accesses the LSB and CASO accesses the MSB of data 17 16 MCF5307 User s Manual M woronoLA DMA Controller Module Signals 17 7 3 DRAM Write DRAMW The DRAM write signal DRAMW is asserted to signify that a DRAM write cycle is underway A read bus cycle is indicated by the negation of DRAMW 17 7 4 Synchronous DRAM Column Address Strobe SCAS The synchronous DRAM column address strobe SCAS is registered during synchronous mode to route directly to the SCAS signal of SDRAMs 17 7 5 Synchronous
250. Outputs TOUTI TOUT esee 17 19 Parallel TO Port PP 15 0 a rrr m eres 17 19 PE Module Signals neret 17 19 I2G Serial Clock SCD si aeree ere bn e ert ios 17 19 I2C Serial Data SD A e Lena 17 19 Debug and Test Signals 17 20 Test Mode MTMODY 3 0 sess 17 20 High Impedance ee eee 17 20 Processor Clock Output PSTCLK eene 17 20 Debug Data DDATA 3 0 essere nennen 17 20 Processor Status PST 3 0 sees 17 20 Debug Module JTAG 1 5 17 21 Test Reset Development Serial Clock TRST DSCLK 17 21 Test Mode Select Breakpoint TMS BKPT 17 22 Test Data Input Development Serial Input TDI DSD 17 22 Test Data Output Development Serial Output TDO DSO 17 22 Test Clock TG et ee ete tre e be eee tees seeks 17 23 MCF5307 User s Manual M woronoLA Paragraph Number 18 1 18 2 18 3 18 4 18 4 1 18 4 2 18 4 3 18 4 4 18 4 5 18 4 6 18 4 7 18 4 7 1 18 4 7 2 18 4 7 3 18 4 7 4 18 5 18 6 18 7 18 7 1 18 7 2 18 8 18 8 1 18 9 18 9 1 18 9 2 18 10 18 10 1 18 10 2 19 1 19 2 19 3 19 4 19 4 1 19 4 2 19 4 3 CONTENTS Page Tie Number Chapter 18 Bus Operation Iun E
251. P SWT Therefore altering SWP and SWT improperly causes unpredictable processor behavior The following steps must be taken to change SWP or SWT M MOTOROLA Chapter 6 SIM Overview 6 7 Programming Model 1 Disable the software watchdog timer by clearing SYPCR SWE 2 Reset the counter by writing 0x55 and then OxAA to SWSR 3 Update SYPCR SWT SWP 4 Reenable the watchdog timer by setting SYPCR SWE This can be done in step 3 6 2 5 System Protection Control Register SYPCR The SYPCR Figure 6 5 controls the software watchdog timer timeout periods and software watchdog timer transfer acknowledge The SYPCR can be read at any time but can be written only if a software watchdog timer IRQ is not pending At system reset the software watchdog timer is disabled 7 6 5 4 3 2 1 0 Field SWE SWRI SWP SWT SWTA SWTAVAL Reset 0000_0000 R W R W Address MBAR 0x01 Figure 6 5 System Protection Control Register SYPCR Table 6 4 describes SYPCR fields Table 6 4 SYPCR Field Descriptions Bits Name Description 7 SWE Software watchdog timer enable 0 Software watchdog timer disabled 1 Software watchdog timer enabled 6 SWRI Software watchdog reset interrupt select 0 If a timeout occurs the watchdog timer generates an interrupt to the core processor at the level programmed into ICRO IL 1 The software watchdog timer causes soft reset to be asserted for all modules of the part
252. P commands Required number of READ or WRITE commandis to service the transfer size with the given port size Some transfers need more NOP commands to assure the ACTV to precharge delay PALL command Required number of idle clocks inserted to assure precharge to ACTV delay 11 4 4 4 Continuous Page Mode Continuous page mode is identical to burst page mode except that it allows the processor core to handle successive bus cycles that hit the same page without having to close the page When the current bus cycle finishes the MCF5307 core internal pipelined bus can predict whether the upcoming cycle will hit in the same page If the next bus cycle is not pending or misses in the page the PALL command is generated to the SDRAM If the next bus cycle is pending and hits in the page the page is left open and the next SDRAM access begins with a READ or WRITE command M MOTOROLA Chapter 11 Synchronous Asynchronous DRAM Controller Module 11 29 Synchronous Operation e Because of the nature of the internal CPU pipeline this condition does not occur often however the use of continuous page mode is recommended because it can provide a slight performance increase Figure 11 20 shows two read accesses in continuous page mode Note that there is no precharge between the two accesses Also notice that the second cycle begins with a read operation with no ACTV command BCLKO a a
253. R B 1 A7 Clear the IIF flag MOVE B I2CR A7 Push the address on stack M woronoLA Chapter 8 Module 8 11 Pc Programming Examples BTST B 5 A7 check the MSTA flag BEQ S SLAVE Branch if slave mode MOVE B I2CR A7 Push the address on stack BTST B 4 A7 check the mode flag BEQ S RECEIVE Branch if in receive mode MOVE B I2SR A7 Push the address on stack BTST B 0 A7 check ACK from receiver BNE B END If no ACK end of transmission TRANSMITMOVE B DATABUF A7 Stack data byte MOVE B A7 I2DR Transmit next byte of data 8 6 4 Generation of STOP A data transfer ends when the master signals a STOP which can occur after all data is sent as in the following example MASTX MOVE B I2SR A7 If no ACK branch to end BTST B 0 A7 BNE B END MOVE B TXCNT D0 Get value from the transmitting counter BEQ S END If no more data branch to end MOVE B DATABUF A7 Transmit next byte of data MOVE B A7 I2DR MOVE B TXCNT D0 Decrease the TXCNT SUBQ L 1 D0 MOVE B DO TXCNT BRA S EMASTX Exit END LEA L I2CR A7 Generate a STOP condition BCLR B 5 A7 EMASTX RTE Return from interrupt For a master receiver to terminate a data transfer it must inform the slave transmitter by not acknowledging the last data byte This is done by setting I2ZCR TXAK before reading the next to last byte Before the last byte is read a STOP signal must be generated as in the following example MASR MOVE B RXCNT D0 Dec
254. R asserted DMA module BR negated Figure 6 12 Park on DMA Module Priority PARK 10 MOTOROLA Chapter 6 SIM Overview 6 13 Programming Model e Park on current master priority PARK 11 The current bus master retains mastership as long as it needs the bus The other device can become the bus master only when the bus is idle For example if the core is bus master out of reset it retains mastership as long as it needs the bus It loses mastership only when it negates its bus request signal and the DMA asserts its internal bus request signal At this point the DMA module is the bus master and retains bus mastership as long as it needs the bus See Figure 6 13 DMA module BR asserted Core BR negated DMA module BR negated Gore Bh negated e CS Core BR asserted DMA module BR asserted Core BR asserted BR DMA module BR asserted DMA module BR negated Core BR asserted Figure 6 13 Park on Current Master Priority PARK 01 DMA module BR negated Core BR negated DMA Module 6 2 10 1 2 Arbitration between Internal and External Masters for Accessing Internal Resources If an external device is programmed to access internal MCF5307 resources EARBCTRL 1 the external device can gain bus mastership only when BG is negated This means neither the core nor the DMA controller can access the external bus until the external device asserts BG After the external master finishes its bus transfer and asserts BG the core has p
255. REF clears the event flag move b DO TERO jmp TO_LOOP TO_FINISH HALT End processing Example is finished 13 5 Calculating Time Out Values The formula below determines time out periods for various reference values Time out period 1 clock frequency x 1 or 16 x TMRn PS 1 x TRRn REF When calculating time out periods add 1 to the prescaler to simplify calculating because TMRn PS 0x00 yields a prescaler of 1 and TMRn PS OxFF yields prescaler of 256 For example if a 45 MHz timer clock is divided by 16 TMRn PS 0x7F and the timer is referenced at OXABCD 43 981 decimal the time out period is as follows Time out period 1 45 x 16 x 127 1 x 43 981 1 67S The time out values in Table 13 5 represent the time it takes the counter value in value to go from 0x0000 to the default reference value TRRn REF OxFFFF Time out values shown for BCLKO are divided by 1 and by 16 TMRn CLK is 01 or 10 respectively Any clock source BCLKO 1 BCLKO 16 or TIN can be prescaled using TMRn PS The BCLKO frequency depends on the prescaler value TMRn PS and on the PLL clock setting as described inChapter 7 Phase Locked Loop PLL Table 13 5 Calculated Time out Values 90 MHz Processor Clock TMR PS TMR CLK 10 System Bus Clock 16 TMR CLK 01 System Bus Clock 1 Decimal Hex 45 MHz 30 MHz 22 5 MHz 45 MHz 30 MHz 22 5 MHz 0 0 0 0233 0 03495 0 0466
256. ROLA Chapter 11 Synchronous Asynchronous DRAM Controller Module 11 39 SDRAM Example 11 40 MCF5307 User s Manual M woronoLA Part Ill Peripheral Module Intended Audience Part III describes the operation and configuration of the MCF5307 DMA timer UART and parallel port modules and describes how they interface with the system integration unit described in Part II Contents Part III contains the following chapters Chapter 12 DMA Controller Module provides an overview of the DMA controller module and describes in detail its signals and registers The latter sections of this chapter describe operations features and supported data transfer modes in detail showing timing diagrams for various operations Chapter 13 Timer Module describes configuration and operation of the two general purpose timer modules timer 0 and timer 1 It includes programming examples Chapter 14 UART Modules describes the use of the universal asynchronous synchronous receiver transmitters UARTs implemented on the MCF5307 and includes programming examples Chapter 15 Parallel Port General Purpose I O describes the operation and programming model of the parallel port pin assignment direction control and data registers It includes a code example for setting up the parallel port M Part Ill Peripheral Module Acronyms and Abbreviations Table III i describes acronyms and abbreviations used
257. RSR SWIVR MBAR MPARK PAR 1r 1 1 e SYPCR SWSR LL DRAM Controller Chip Select Module External Interrupt Controller Bus Interface DRAM Control DCR 8 8 8 10 ICRs IRQPAR CSARs CSCRs CSMRs IPR Addr Cntrl Mask MR DACRO 1 DMRO 1 32 Bit Data Bus 4 32 Bit Address Bus TRQ 1 3 5 7 f E DRAM Controller Outputs CS 7 0 Control Signals Figure 6 1 SIM Block Diagram M MOTOROLA Chapter 6 SIM Overview 6 1 Features The following is a list of the key SIM features 6 2 Module base address register MBAR Base address location of all internal peripherals and SIM resources Address space masking to internal peripherals and SIM resources Phase locked loop PLL clock control register PLLCR for CPU STOP instruction Control for turning off clocks to core and interrupt levels that turn clocks back on Chapter 7 Phase Locked Loop Interrupt controller Programmable interrupt level 1 7 for internal peripheral interrupts Programmable priority level 0 3 within each interrupt level Four external interrupts one set to interrupt level 7 three others programmable to two interrupt levels See Chapter 9 Interrupt Controller Chip select module Eight independent user programmable chip select signals CS 7 0 that can interface with SRAM PROM EPROM EEPROM Flash and peripherals Address maski
258. Register 8 9 PC Data Repister DDR utei ttt te reete ees 8 10 Flow Chart of Typical PC Interrupt Routine sese 8 14 Interrupt Controller Block 9 1 Interrupt Control Registers ICRO ICRO 9 3 Autovector Register AVR iie eeepc eese obest oai ineo donee von eene 9 5 Interrupt Pending Register IPR and Interrupt Mask Register IMR 9 7 Interrupt Port Assignment Register IRQPAR eee 9 7 Connections for External Memory Port Sizes 10 4 Chip Select Address Registers 7 10 6 Chip Select Mask Registers CSMRn esee 10 7 Chip Select Control Registers 5 7 10 8 Asynchronous Synchronous DRAM Controller Block Diagram 11 2 DRAM Control Register DCR Asynchronous Mode eese 11 5 DRAM Address and Control Registers DACRO DACRI esee 11 6 DRAM Controller Mask Registers DMRO and DMRI eere 11 7 Basic Non Page Mode Operation RCD 0 RNCN 1 4 4 4 4 11 11 Basic Non Page Mode Operation RCD 1 RNCN 0 5 5 5 5 11 12 Burst Page Mode Read Operation 4 3 3 3 sss 11 13 Burst Page Mode Write Operation 4 3 3 3
259. Registers 4 10 Cache Registers This section describes the MCF5307 implementation of the Version 3 cache registers 4 10 1 Cache Control Register CACR The CACR in Figure 4 8 contains bits for configuring the cache It can be written by the MOV EC register instruction and can be read or written from the debug facility A hardware reset clears CACR which disables the cache however reset does not affect the tags state information or data in the cache Field Reset R W Field Reset R W Re 31 30 29 28 27 26 25 24 23 20 19 18 17 16 EC ESB DPI HLCK CINVA 0000_0000_0000_0000 Write R W by debug module 13 12 11 10 9 8 0 DNFB DCM DW 0000 0000 0000 0000 Write R W by debug module 0x002 Figure 4 8 Cache Control Register CACR Table 4 4 describes CACR fields Table 4 4 CACR Field Descriptions Bits Name Description 31 EC Enable cache 0 Cache disabled The cache is not operational but data and tags are preserved 1 Cache enabled 30 a Reserved should be cleared 29 ESB Enable store buffer 0 Writes to write through or noncachable in imprecise mode bypass the store buffer and generate bus cycles directly Section 4 9 5 2 1 Push and Store Buffers describes the performance penalty for this 1 The four entry FIFO store buffer is enabled when imprecise mode is used this b
260. SEL Figure 11 13 MCF5307 SDRAM Interface 11 4 2 Using Edge Select EDGESEL EDGESEL can ease system level timings note that the optional buffer in Figure 11 13 is for memories that need extra delay The clock at the input to the SDRAM is monitored and data is held until the next edge of the bus clock adding required output hold time to the address data and control signals To generate SDRAM interface timing address data and control signals are clocked through a two stage shift register The first stage is clocked on the rising edge of BCLKO the second is clocked on the falling edge This makes the signal available for up to an additional half bus clock cycle of which only a small amount is needed for proper timing Using the connection shown in Figure 11 13 ensures that data remains held for a longer time after the rising edge of the SDRAM clock input This helps to match the MCF5307 output timing with the SDRAM clock Figure 11 14 shows the output wave forms for the interface signals changing on the rising edge A and falling edge B of BCLKO as determined by whether EDGESEL is tied high or low It also shows timing C with EDGESEL tied to buffered BCLKO 11 18 MCF5307 User s Manual M woronoLA Synchronous Operation BCLKO BCLKO i I i iu y ALID VALID Y VALID VALID Adds Vico XC VALID VALID j
261. SP Address of ea SP PULSE none Unsized Set PST 0x4 REMS lt ea 1 gt Dx L Dx ea y Dw 32 bit remainder Signed operation REMU lt ea 1 gt Dx b Dx lt ea gt y Dw 32 bit remainder Unsigned operation RTS none Unsized SP gt PC SP 4 SP Scc Dx B If condition true then 1s destination Else 0s destination SUB ea y Dx Destination source destination Dy lt ea gt x SUBA ea y Ax L Destination source destination SUBI lt data gt Dx L Destination immediate data destination SUBQ lt data gt lt ea gt x xls Destination immediate data destination SUBX Dy Dx L Destination source X destination SWAP Dx W MSW of lt gt LSW of Dx TRAP lt vector gt Unsized SP 4 SP PC gt SP SP 2 SP SR SP SP 2 SP format SP Vector address PC TRAPF None Unsized PC 2 lt data gt PC 4 gt E PC 6 M MOTOROLA Chapter 2 ColdFire Core 2 39 Instruction Timing Table 2 7 User Mode Instruction Set Summary Continued Instruction Operand Syntax Operand Size Operation TST ea y B W L Set condition codes UNLK Ax Unsized Ax gt SP SP Ax SP 4 gt SP WDDATA lt ea gt y B W L ea y DDATA port 1 By default the HALT instruction is a supervisor mode instruction however it can be configured to allow user mode execution by
262. Synchronous Operation Table 11 24 MCF5307 to SDRAM Interface 16 Bit Port 12 Column Address Lines BM 16 A15 A14 A13 12 A11 A10 A9 A18 A20 A22 A24 A25 A26 A27 A28 A29 A30 A31 Row 16 15 14 13 12 11 10 9 18 20 22 24 25 26 27 28 29 30 31 Column 1 2 3 4 5 6 7 8 17 19 21 23 SE AO 1 2 A4 A5 A6 A7 AB A9 A10 A11 A12 1 A14 A15 A16 A17 A18 Table 11 25 MCF5307to SDRAM Interface 16 Bit Port 13 Column Address Lines MCF5307 16 A15 14 A13 A12 A11 A10 A9 A18 A20 22 A24 A26 A27 A28 A29 A30 A31 Pins Row 16 15 14 13 12 11 10 9 18 20 22 24 26 27 28 29 30 31 Column 1 2 3 4 5 6 P 8 17 19 21 23 25 SDRAM AO A1 A2 A4 A5 A7 AB A9 ATO A11 A12 A13 A14 A15 A16 A17 Pins Table 11 26 MCF5307 to SDRAM Interface 32 Bit Port 8 Column Address Lines MCF5307 A15 A14 A13 A12 A11 A10 A9 A17 18 19 20 21 22 23 24 25 26 A27 A28 A29 A30 A31 Pins Row 15 14 13 12 11110 9 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Column 2 3 45 6 7 16 SDRAM A1 2 A4 A5 A7 A8 A9 10 11 12 1 14 15
263. T 1 0 11 TM 2 0 interrupt level 7 Assert TS for one BCLKO cycle Y 2 x m 1 Negate TS 2 Drive TM 2 0 to indicate interrupt acknowledge TM 2 0 interrupt level 1 Decode address and selectthe appropriate slave device 1 Read and store data D 31 24 2 Drive data on 0 31 24 2 Recognize the transfer is done 3 Assert TA for one BCLKO cycle Figure 18 23 Interrupt Acknowledge Cycle Flowchart 18 8 Bus Arbitration The MCF5307 bus protocol gives either the MCF5307 or an external device access to the external bus If more than one external device uses the bus an external arbiter can prioritize requests and determine which device is bus master When the MCF5307 is bus master it uses the bus to fetch instructions and transfer data to and from external memory When an external device is bus master the MCF5307 can monitor the external master s transfers and interact through its chip select DRAM control and transfer termination signals See Section 10 4 1 3 Chip Select Control Registers CSCRO CSCR7 and Chapter 11 Synchronous Asynchronous DRAM Controller Module Two wire bus arbitration is used where the MCF5307 shares the bus with a single external device This mode uses BG and BD The external device can ignore BR Three wire mode is used where the MCF5307 shares the bus with multiple external devices This requires an external bus arbiter and uses BG BD and BR
264. TOROLA Table A 7 UART1 Module Programming Model Continued MBAR Offset 31 24 23 16 15 8 7 0 0x220 Do not access 0x22C 0x230 UART interrupt vector register UIVRn p 14 15 0x234 Read UART input port registers UIPn p 14 15 Write Do not access 0x238 Read Do not access Write UART output port bit set command registers UOP1n p 14 15 0x23C Read Do not access Write UART output port bit reset command registers UOPO0n p 14 15 UMRin UMR2n and UCSRn should be changed only after the receiver transmitter is issued a software reset command That is if channel operation is not disabled undesirable results may occur This address is for factory testing Reading this location results in undesired effects and possible incorrect transmission or reception of characters Register contents may also be changed 3 Address triggered commands Table A 8 Parallel Port Memory Map MBAR y 31 24 23 16 15 8 7 0 Ox244 Parallel port data direction register PADDR Reserved p 15 2 0x248 Parallel port data register PADAT 15 2 Reserved Table A 9 12 Interface Memory MBAR 7 Offset 31 24 23 16 15 8 7 0 0x280 12 address register Reserved IADR p 8 6 0x284 12 frequen
265. Table 10 2 shows Table 10 2 shows the interaction of the byte enable byte write enables with related signals M MOTOROLA Chapter 10 Chip Select Module 10 1 Chip Select Operation Table 10 2 Byte Enables Byte Write Enable Signal Settings BEO BWEO BE1 BWE1 E2 BWE2 BE3 BWE3 Transfer Size Port Size Al AO D 31 24 D 23 16 D 15 8 D 7 0 Byte 8 bit 0 0 0 1 1 1 0 1 0 1 1 1 1 0 0 1 1 1 1 1 0 1 1 1 16 bit 0 0 0 1 1 1 0 1 1 0 1 1 1 0 0 1 1 1 1 1 1 0 1 1 32 bit 0 0 0 1 1 1 0 1 1 0 1 1 1 0 1 1 0 1 1 1 1 1 1 0 Word 8 bit 0 0 0 1 1 1 0 1 0 1 1 1 1 0 0 1 1 1 1 1 0 1 1 1 16 bit 0 0 0 0 1 1 1 0 0 0 1 1 32 bit 0 0 0 0 1 1 1 0 1 1 0 0 Longword 8 bit 0 0 0 1 1 1 0 1 0 1 1 1 1 0 0 1 1 1 1 1 0 1 1 1 16 bit 0 0 0 0 1 1 1 0 0 0 1 1 32 bit 0 0 0 0 0 0 Line 8 bit 0 0 0 1 1 1 0 1 0 1 1 1 1 0 0 1 1 1 1 1 0 1 1 1 16 bit 0 0 0 0 1 1 1 0 0 0 1 1 32 bit 0 0 0 0 0 0 10 3 Chip Select Operation Each chip select has a dedicated set of the following registers for configuration and control 10 2 Chip select address registers CSARn control the base address space of the chip select See Section 10 4 1 1 Chip Select Address Registers CSARO CSAR7 MCF5307 User s Manual MOTOROLA Chip Select Operation e Chip select mask registers CSMRn provide 16 bit address masking and acce
266. The term asserted indicates that a signal is active independent of the voltage level The term negated indicates that a signal is inactive Active low signals such as SRAS and TA are indicated with an overbar 17 1 Overview Figure 17 1 shows the block diagram of the MCF5307 with the signal interface MOTOROLA Chapter 17 Signal Descriptions 17 1 Overview TDO DSO BR TCK 5 BG JTAG 2 BG TMS BKPT port rETI TDI DSI N ec TRST DSCLK gt RSTO st AS ColdFire V3 Core TA 1 Test TS Controller TT 1 0 JPP 1 0 2 Non Debug Module EY PST 3 0 As F DDATA 3 0 TIP PP7 55 4 Kbyte SRAM D 31 0 lt x DIV MAC 2 External j c 8 Kbyte A 23 0 19 Internal unified Cache F aralle A 81 24 PP 15 8 S TM 2 0 PP 4 2 a Lf ay A TE CS 7 0 4 Chip Internal Bus Arbiter BE 3 0 BWE 3 0 7 4 Selects p OE IRQ7 IRQ5 Interrupt IRQ3 Controller TROT BATIH 2 System peel 4 Integration CAS 3 0 4 Module DMA UARTO UARTI Dual 2 Ur i i imer DRAM SM Module 5 Sie Module Module SCAS Controller SCKE EDGESEL T en BCLKO CLKIN ELL 5 88885566 PSTCLK T A X
267. When combined with the enhanced pipeline structure of the Version 3 ColdFire core the processor and its local memories provide a high level of performance for today s demanding embedded applications PCLK can be disabled to minimize dissipation when a low power mode is entered This is described in Section 7 2 3 Reduced Power Mode 2 1 2 Enhanced Pipelines The IFP prefetches instructions The OEP decodes instructions fetches required operands then executes the specified function The two independent decoupled pipeline structures maximize performance while minimizing core size Pipeline stages are shown in Figure 2 1 and are summarized as follows e Four stage plus optional instruction buffer stage Instruction address generation IAG calculates the next prefetch address Instruction fetch cycle 1 IC1 initiates prefetch on the processor s local instruction bus Instruction fetch cycle 2 IC2 completes prefetch on the processor s instruction local bus Instruction early decode IED generates time critical decode signals needed for the OEP Instruction buffer IB optional stage uses FIFO queue to minimize effects of fetch latency Two stage OEP Decode select operand fetch DSOC decodes the instruction and selects the required components for the effective address calculation or the operand fetch cycle Address generation execute AGEX Calculates the oeprand address or performs the exe
268. aced Clear To cause a bit or bit field to register a value of zero See also Set Copyback A cache memory update policy in which processor write cycles are directly written only to the cache External memory is updated only indirectly for example when a modified cache line is cast out to make room for newer data Effective address EA The 32 bit address specified for an instruction Exception A condition encountered by the processor that requires special supervisor level processing Exception handler A software routine that executes when an exception is taken Normally the exception handler corrects the condition that caused the exception or performs some other meaningful task that may include aborting the program that caused the exception The address for each exception handler is identified by an exception vector defined by the ColdFire architecture Fetch The act of retrieving instructions from either the cache or main memory and making them available to the instruction unit Flush An operation that causes a modified cache line to be invalidated and the data to be written to memory Illegal instructions A class of instructions that are not implemented for a particular processor These include instructions not defined by the ColdFire architecture MCF5307 User s Manual M woronoLA Implementation A particular processor that conforms to the ColdFire architecture but may differ from other architecture compliant i
269. al development system For compatibility with Rev A BAAR is loaded each time AATR is written DRc 4 0 0x05 Figure 5 7 BDM Address Attribute Register BAAR Table 5 7 describes BAAR fields M MOTOROLA Chapter 5 Debug Support 5 9 Programming Model Table 5 7 BAAR Field Descriptions Bits Name Description 7 R Read write 0 Write 1 Read 6 5 SZ Size 00 Longword 01 Byte 10 Word 11 Reserved 4 8 TT Transfer type See the TT definition in Table 5 4 2 0 TM Transfer modifier See the TM definition in Table 5 4 5 4 4 Configuration Status Register CSR The configuration status register CSR defines the debug configuration for the processor and memory subsystem and contains status information from the breakpoint logic 31 30 29 28 27 26 25 24 23 22 21 20 19 17 16 Field BSTAT FOF TRG HALT BKPT HRL BKD IPW Reset 0000 0 0 0 0 0001 0 Rw R R R R R RW 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field TRC EMU DDC UHE BTB NPL IPI SSM Reet 0 00 0 00 0 0 0 R W R W R W R W R W R W R W RW RW DRe 4 0 0x00 CSR is write only from the programming model It can be read from and written to through the BDM port CSR is accessible in supervisor mode as debug control register 0x00
270. al module XXX 20 100 00 XXX 21 3 011 11 Internal module XXX 22 011 10 XXX 23 XXX External interrupt pin IRQ3 x0x 24 011 01 Internal module XXX 25 011 00 XXX 26 2 010 11 Internal module XXX 27 010 10 XXX 28 xx External interrupt pin IRQ1 programmed as IRQ2 xxi 29 010 01 Internal module XXX 30 010 00 XXX 31 1 001 11 Internal module XXX 32 001 10 XXX 33 XXX xx External interrupt pin IRQ1 xx0 34 001 01 Internal module XXX 35 001 00 XXX 9 2 2 Autovector Register AVR The autovector register AVR shown in Figure 9 3 enables external interrupt sources to be autovectored using the vector offset defined in Table 2 19 in Section 2 8 Exception Processing Overview Note that the autovector enable for internal interrupt sources applies for respective ICRs 7 6 5 4 3 2 1 0 Field AVEC BLK Reset 0000 0000 R W R W Address MBAR 0x04B Figure 9 3 Autovector Register AVR M woronoLA Chapter 9 Interrupt Controller 9 5 Interrupt Controller Registers Table 9 5 describes AVR fields Table 9 5 AVR Field Descriptions Bit Name Description 7 1 AVEC Autovector control Determines whether the external interrupt at that level is autovectored 0 Interrupting source returns vector during interrupt acknowledge cycle 1 SIM generates autovector during interrupt acknowledge cycle 0 BLK Block address strobe AS for
271. alid there the cache can service additional read accesses from this buffer until another fill occurs or a cache invalidate all operation occurs If ACRn CM indicates cache inhibited mode precise or imprecise the controller bypasses the cache and performs an external transfer If a line in the cache matches the address and the mode is cache inhibited the cache does not automatically push the line if it is modified nor does it invalidate the line if it is valid Before switching cache mode execute a CPUSHL instruction or set CACR CINVA to invalidate the entire cache If ACRn CM indicates precise mode the sequence of read and write accesses to the region is guaranteed to match the instruction sequence In imprecise mode the processor core allows read accesses that hit in the cache to occur before completion of a pending write from a previous instruction Writes are not deferred past data read accesses that miss the cache that is that must be read from the bus Precise operation forces data read accesses for an instruction to occur only once by preventing the instruction from being interrupted after data is fetched Otherwise if the processor is not in precise mode an exception aborts the instruction and the data may be accessed again when the instruction is restarted These guarantees apply only when ACRn CM indicates precise mode and aligned accesses CPU space register accesses such as MOVEC are treated as cache inhibited and preci
272. allocate for addresses in a cacheable copyback region A copyback byte word longword or line write miss causes the following The cache initiates a line fill or flush 2 Space is allocated for a new line 3 V and M are both set to indicate valid and modified 4 Data is written in the allocated space No write to memory occurs Note the following e Read hits cannot change the status bits and no deallocation or replacement occurs the data or instructions are read from the cache If the cache hits on a write access data is written to the appropriate portion of the accessed cache line Write hits in cacheable write through regions generate an external write cycle and the cache line is marked valid but is never marked modified Write hits in cacheable copyback regions do not perform an external write cycle the cache line is marked valid and modified V 1 and M 1 e Misaligned accesses are broken into at least two cache accesses e Validity is provided only on a line basis Unless a whole line is loaded on a cache miss the cache controller does not validate data in the cache line Write accesses designated as cache inhibited by the CACR or ACR bypass the cache and perform a corresponding external write 4 12 MCF5307 User s Manual M woronoLA Cache Operation Normally cache inhibited reads bypass the cache and are performed on the external bus The exception to this normal operation occurs when all of the following c
273. als to identify the proper chip select and byte enable assertion The external device negates TS in C2 Address and R W are latched in the MCF5307 on the rising edge of BCLKO in C2 After C2 the address RAW are ignored for the rest of the burst transfer C4 On the falling edge of BCLKO the MCF5307 asserts the appropriate chip select for the external device access along with the appropriate byte enables C5 On the rising edge of BCLKO data is driven onto the bus by the device selected by CS The MCF5307 asserts T on the rising edge of BCLKO indicating the first data transfer is complete 18 24 MCF5307 User s Manual M woronoLA General Operation of External Master Transfers Table 18 9 Cycles for External Master Burst Line Access to 32 Bit Port Continued Cycle Definition C6 C8 No wait state data transfers 2 4 occur on the rising edges of BCLKO TA continues to be asserted indicating completion of each transfer TIP CSx and BE BWE 3 0 are driven c9 TA negates on the rising edge of BCLKO along with external device s negation of TIP On the falling edge the MCF5307 negates chip select and byte enables creating an opportunity for another cycle to begin 18 9 1 Two Device Bus Arbitration Protocol Two Wire Mode Two wire mode bus arbitration lets the MCF5307 share the external bus with a single external bus device without requiring an external bus arbiter Figure 18 26 shows the
274. and decoupled pipelines to maximize performance the instruction fetch pipeline IFP and the operand execution pipeline OEP 1 3 1 1 Instruction Fetch Pipeline IFP The four stage instruction fetch pipeline IFP is designed to prefetch instructions for the operand execution pipeline OEP Because the fetch and execution pipelines are decoupled by a eight instruction FIFO buffer the fetch mechanism can prefetch instructions in advance of their use by the OEP thereby minimizing the time stalled waiting for instructions To maximize the performance of branch instructions the Version 3 IFP implements a branch prediction mechanism Backward branches are predicted to be taken The prediction for forward branches is controlled by a bit in the Condition Code Register CCR These predictions allow the IFP to redirect the fetch stream down the path predicted to be taken well in advance of the actual instruction execution The result is significantly improved performance 1 3 1 2 Operand Execution Pipeline OEP The prefetched instruction stream is gated from the FIFO buffer into the two stage OEP The OEP consists of a traditional two stage RISC compute engine with a register file access feeding an arithmetic logic unit ALU The OEP decodes the instruction fetches the required operands and then executes the required function 1 3 1 3 MAC Module The MAC unit provides signal processing capabilities for the MCF5307 in a variety of application
275. and one from 0x8 0000 0x8 FFFF Likewise for CSO to access 32 Mbytes of address space starting at location 0x0 CS1 must begin at the next byte after CSO for a 16 Mbyte address space Then CSARO 0x0000 CSMRO BAM 0x01FF CSAR1 0x0200 and CSMR1 BAM Ox00FF 8 WP Write protect Controls write accesses to the address range in the corresponding CSAR Attempting to write to the range of addresses for which CSARn WP 1 results in the appropriate chip select not being selected No exception occurs 0 Both read and write accesses are allowed 1 Only read accesses are allowed 7 Reserved should be cleared 6 AM Alternate master When AM 0 during an external master or DMA access SC SD UC and UD are don t cares in the chip select decode 5 1 Address space mask bits These bits determine whether the specified accesses can occur to the SC address space defined by the BAM for this chip select UC CPU space and interrupt acknowledge cycle mask UD SC Supervisor code address space mask SD Supervisor data address space mask UC User code address space mask UD User data address space mask 0 The address space assigned to this chip select is available to the specified access type 1 The address space assigned to this chip select is not available masked to the specified access type If this address space is accessed chip select is not activated and a regular external bus cycle occurs Note that if if AM
276. ange 5 8 MCF5307 User s Manual M woronoLA Programming Model 31 0 Field Address Reset R W Write only is accessible in supervisor mode as debug control register 0 0 using the WOEBUG instruction and via the BDM port using the RDMREG and WDMREG commands ABLR is accessible in supervisor mode as debug control register OXOD using the WDEBUG instruction and via the BDM port using the WOMREG command DRc 4 0 0x0D ABLR 0x0C ABHR Figure 5 6 Address Breakpoint Registers ABLR ABHR Table 5 5 describes ABLR fields Table 5 5 ABLR Field Description Bits Name Description 31 0 Address Low address Holds the 32 bit address marking the lower bound of the address breakpoint range Breakpoints for specific addresses are programmed into ABLR Table 5 6 describes ABHR fields Table 5 6 ABHR Field Description Bits Name Description 31 0 Address High address Holds the 32 bit address marking the upper bound of the address breakpoint range 5 4 3 BDM Address Attribute Register BAAR The BAAR defines the address space for memory referencing BDM commands See Figure 5 7 The reset value of 0x5 sets supervisor data as the default address space Field R SZ TT TM Reset 0000 0101 R W Write only BAAR R SZ are loaded directly from the BDM command BAAR TT TM can be programmed as debug control register 0x05 from the extern
277. ansfer direction The DAR should contain the destination write address If the transfer is from a peripheral device to memory or memory to memory the DAR is loaded with the starting address of the data block to be written If the transfer is from memory to a peripheral device DAR is loaded with the address of the peripheral data register This address can be any aligned byte address DAR is not used in single address mode SAR and DAR change after each cycle depending on DCR SSIZE DSIZE SINC DINC and on the starting address Increment values can be 1 2 4 or 16 for byte word longword or line transfers respectively If the address register is programmed to remain unchanged no count the register is not incremented after the data transfer BCRn BCR must be loaded with the number of byte transfers to occur It is decremented by 1 2 4 or 16 at the end of each transfer depending on the transfer size DSR must be cleared for channel startup As soon as the channel has been initialized it is started by writing a one to DCR START or asserting DREQ depending on the status of DCR EEXT Programming the channel for internal request causes the channel to request the bus and start transferring data immediately If the channel is programmed for external request DREQ must be asserted before the channel requests the bus Changes to DCR are effective immediately while the channel is active To avoid problems with changing DMA channe
278. arbitration should be enabled The external master defaults to the highest priority internal master anytime BG is negated 4 EARBCTRL External bus arbitration control Enables internal register memory space to external bus arbitration Internal registers are those accessed at offsets to the MBAR These include the SIM DMA chip selects timers UARTs and parallel port registers These registers do not include the MBAR only the core can access the MBAR 0 Arbitration disabled 1 Arbitration enabled The use of this field is described in detail in Section 6 2 10 1 2 Arbitration between Internal and External Masters for Accessing Internal Resources M MOTOROLA Chapter 6 SIM Overview 6 11 Programming Model Table 6 6 MPARK Field Descriptions Continued Bits Name Description SHOWDATA Enable internal register data bus to be driven on external bus EARBCTRL must be set for this function to work Section 6 2 10 1 2 Arbitration between Internal and External Masters for Accessing Internal Resources describes the proper use of SHOWDATA 0 Do not drive internal register data bus values to external bus 1 Drive internal register data bus values to external bus Reserved should be cleared BCR24BIT Controls the BCR and address mapping for DMA Allows the BCR to be used as a 24 bit register Chapter 12 DMA Controller Module describes the BCRs 0 DMA BCRs function as 16 b
279. ask for MAC instructions that fetch operands from memory It is useful in the implementation of circular queues in operand memory e MAC status register MACSR This 8 bit register defines configuration of the MAC unit and contains indicator flags affected by MAC instructions Unless noted otherwise MACSR indicator flag settings are based on the final result that is the result of the final operation involving the product and accumulator 2 2 2 Supervisor Programming Model The MCF5307 supervisor programming model is shown in Figure 2 3 Typically system programmers use the supervisor programming model to implement operating system functions and provide memory and control The supervisor programming model provides access to the user registers and additional supervisor registers which include the upper byte of the status register SR the vector base register VBR and registers for configuring attributes of the address space connected to the Version 3 processor core Most supervisor mode registers are accessed by using the MOVEC instruction with the control register definitions in Table 2 2 Table 2 2 MOVEC Register Map Rc 11 0 Register Definition 0x002 Cache control register CACR 0x004 Access control register 0 ACRO 0x005 Access control register 1 ACR1 0x801 Vector base register VBR 0xC04 RAM base address register RAMBAR OxCOF Module base address register MBAR 2 2 2 1 Status Register SR
280. asserted during reads as well as writes BEM can be set in the relevant CSCR to provide the appropriate mode of byte enable in support of these SRAMs 0 Neither BE nor BWE is asserted for read BWE is generated for data write only 1 BE is asserted for read BWE is asserted for write 4 BSTR Burst read enable Specifies whether burst reads are used for memory associated with each CSn 0 Data exceeding the specified port size is broken into individual port sized non burst reads For example a longword read from an 8 bit port is broken into four 8 bit reads 1 Enables data burst reads larger than the specified port size including longword reads from 8 and 16 bit ports word reads from 8 bit ports and line reads from 8 16 and 32 bit ports 10 8 MCF5307 User s Manual M woronoLA Chip Select Registers Table 10 9 CSCRn Field Descriptions Bits Name Description 3 BSTW Burst write enable Specifies whether burst writes are used for memory associated with each CSn 0 Break data larger than the specified port size into individual port sized non burst writes For example a longword write to an 8 bit port takes four byte writes 1 Enables burst write of data larger than the specified port size including longword writes to 8 and 16 bit ports word writes to 8 bit ports and line writes to 8 16 and 32 bit ports 2 0 Reserved should be cleared 10 4 1 4 Code Example The code belo
281. at Chapter 11 Synchronous Asynchronous DRAM Controller Module describes DRAM cycles Chapter 19 IEEE 1149 1 Test Access Port JTAG describes configuration and operation of the MCF5307 JTAG test implementation It describes the use of JTAG instructions and provides information on how to disable JTAG functionality Chapter 20 Electrical Specifications describes AC and DC electrical specifications and thermal characteristics for the MCF5307 Because additional speeds may have become available since the publication of this book consult Motorola s ColdFire web page http www motorola com coldfire to confirm that this is the latest information M AboutThis Book xxxii Suggested Reading This manual includes the following appendix Appendix A List of Memory Maps lists the entire address map for MCF5307 memory mapped registers This manual also includes a glossary and an index Suggested Reading This section lists additional reading that provides background for the information in this manual as well as general information about the ColdFire architecture General Information The following documentation provides useful information about the ColdFire architecture and computer architecture in general ColdFire Documentation The ColdFire documentation is available from the sources listed on the back cover of this manual Document order numbers are included in parentheses for ease
282. ate some variance in the execution time of the algorithm larger more complicated algorithms such as orthogonal transforms may have more demanding speed requirements exceeding the scope of any processor architecture and requiring a fully developed DSP implementation The M68000 architecture was not designed for high speed signal processing and a large DSP engine would be excessive in an embedded environment In striking a middle ground between speed size and functionality the ColdFire MAC unit is optimized for a small set of operations that involve multiplication and cumulative additions Specifically the multiplier array is optimized for single cycle 16 x 16 multiplies producing a 32 bit result with a possible accumulation cycle following This is common in a large portion of signal processing applications In addition the ColdFire core architecture has been modified to allow for an operand fetch in parallel with a multiply increasing overall performance for certain DSP operations 3 1 1 MAC Programming Model Figure 3 2 shows the registers in the MAC portion of the user programming model 31 0 MACSR MAC status register ACC MAC accumulator MASK MAC mask register Figure 3 2 MAC Programming Model 3 2 MCF5307 User s Manual M woronoLA Overview These registers are described as follows e Accumulator ACC This 32 bit read write general purpose register is used to accumulate the results of MAC operation
283. ation 18 5 Misaligned Operands Because operands unlike opcodes can reside at any byte boundary they are allowed to be misaligned A byte operand is properly aligned at any address a word operand is misaligned at an odd address and a longword is misaligned at an address not a multiple of four Although the MCF5307 enforces no alignment restrictions for data operands including program counter PC relative data addressing additional bus cycles are required for misaligned operands 18 16 MCF5307 User s Manual M woronoLA Bus Errors Instruction words and extension words opcodes must reside on word boundaries Attempting to prefetch a misaligned instruction word causes an address error exception The MCF5307 converts misaligned cache inhibited operand accesses to multiple aligned accesses Figure 18 21 shows the transfer of a longword operand from a byte address to a 32 bit port In this example SIZ 1 0 specify a byte transfer and a byte offset of Ox1 The slave device supplies the byte and acknowledges the data transfer When the MCF5307 starts the second cycle SIZ 1 0 specify a word transfer with a byte offset of 0x2 The next two bytes are transferred in this cycle In the third cycle byte 3 is transferred The byte offset is now 0 0 the port supplies the final byte and the operation is complete 81 24 23 1615 87 o 2 0 Transfer 1 Byte 0 001 Transfer 2 m Byte 1 Byte 2 010 Transfer 3 Byte 3 10
284. ational Conventions Table ii Notational Conventions Continued Instruction Operand Syntax ic Instruction cache lt vector gt Identifies the 4 bit vector number for trap instructions lt gt identifies an indirect data address referencing memory lt XXX gt identifies an absolute address referencing memory dn Signal displacement value n bits wide example d16 is a 16 bit displacement SF Scale factor x1 x2 x4 for indexed addressing mode lt lt 1n gt gt for MAC operations Operations Arithmetic addition or postincrement indicator Arithmetic subtraction or predecrement indicator x Arithmetic multiplication Arithmetic division s Invert operand is logically complemented amp Logical AND Logical OR Logical exclusive OR Shift left example DO 3 is shift DO left 3 bits gt gt Shift right example DO gt gt 3 is shift DO right 3 bits gt Source operand is moved to destination operand lt gt Two operands are exchanged sign extended All bits of the upper portion are made equal to the high order bit of the lower portion If lt condition gt Test the condition If true the operations after then are performed If the condition is false and the then optional else clause is present the operations after else are performed If the condition is false lt operations gt and
285. ave receive mode A dummy read of I2DR in slave receive mode releases SCL allowing the master to send data In the slave transmitter routine I2SR RXAK must be tested before sending the next byte of data Setting RXAK means an end of data signal from the master receiver after which software must switch it from transmitter to receiver mode Reading I2DR then releases SCL so that the master can generate a STOP signal 8 6 7 Arbitration Lost If several devices try to engage the bus at the same time one becomes master Hardware immediately switches devices that lose arbitration to slave receive mode Data output to SDA stops but SCL is still generated until the end of the byte during which arbitration is lost An interrupt occurs at the falling edge of the ninth clock of this transfer with DSR IAL 1 and I2CR MSTA 0 If a device that is not a master tries to transmit or do a START hardware inhibits the transmission clears MSTA without signalling a STOP generates an interrupt to the CPU and sets IAL to indicate a failed attempt to engage the bus When considering these cases the slave service routine should first test IAL and software should clear it if it is set M woronoLA Chapter 8 Module 8 13 Pc Programming Examples Arbitration Lost ast Byte Transmitted Clear IAL Read Data from I2DR and Store Switch to Rx Mode Dummy Read from I2DR Head Data from I2DR And Store
286. ay in invalid state Cache push C W I7 No action stay in invalid state In Table 4 8 the current state is valid Table 4 8 Cache Line State Transitions Current State Valid Access Response Read miss C W V1 Read new line from memory and update cache supply data to processor stay in valid state Read hit C W V2 Supply data to processor stay in valid state Write miss copyback CV3 Read new line from memory and update cache write data to cache go to modified state Write miss write through WV3 Write data to memory stay in valid state Write hit copyback CV4 Write data to cache go to modified state Write hit write through WV4 Write data to memory and to cache stay in valid state Cache invalidate C W V5 No action go to invalid state Cache push C W V6 No action go to invalid state Cache push C W V7 No action stay in valid state 4 28 MCF5307 User s Manual M woronoLA Cache Initialization Code In the current state is modified Table 4 9 Cache Line State Transitions Current State Modified Access Response Read miss CD1 Push modified line to buffer read new line from memory and update cache supply data to processor write push buffer contents to memory go to valid state Read hit CD2 Supply data to processor stay in modified state Write miss CD3 Push modified line to buffer co
287. be AS Address strobe AS is asserted to indicate when the address is stable at the start of a bus cycle The address and attributes are guaranteed to be valid during the entire period that AS is asserted This signal is asserted and negated on the falling edge of the clock When the MCF5307 is not the bus master AS is an input 17 2 7 Transfer Acknowledge TA When the MCF5307 is bus master the external system drives this input to terminate the bus transfer The bus continues to be driven until this synchronous signal is asserted For write cycles the processor continues to drive data one clock after TA is asserted During read cycles the peripheral must continue to drive data until TA is recognized If all bus cycles support fast termination TA can be tied low However note that TA cannot be tied low if potential external bus masters are present The MCF5307 drives TA for an M MOTOROLA Chapter 17 Signal Descriptions 17 9 MCF5307 Bus Signals external master access This condition is indicated by the AM bit in the chip select mask register CSMR being cleared See Chapter 10 Chip Select Module 17 2 8 Transfer In Progress TIP PP7 The TIP PP7 pin is programmed in the PAR to serve as the transfer in progress output or as a parallel port bits The TIP output is asserted indicating a bus transfer is in progress It is negated during idle bus cycles if the bus is still granted to the processor It is three stated for externa
288. bus signals are driven during writes regardless of port width and operand size D 7 0 are used during reset initialization as inputs to configure the functions as described in Table 17 3 They are defined in Section 17 5 5 Data Configuration Pins D 7 0 Table 17 3 Data Pin Configuration Pin Function Section D7 Auto acknowledge configuration Section 17 5 5 2 D7 Auto Acknowledge Configuration AA_CONFIG AA_CONFIG D 6 5 Port size configuration PS CONFIG 1 0 Section 17 5 5 3 D 6 5 Port Size Configuration PS_CONFIG 1 0 D4 Address configuration ADDR_CONFIG D4 Section 17 5 6 D4 Address Configuration ADDR CONFIG D 3 2 Frequency Control PLL FREQ 1 0 Section 17 5 7 D 3 2 Frequency Control PLL FREQ 1 0 D 1 0 Divide Control DIVIDE 1 0 Section 17 5 8 D 1 0 Divide Control PCLK to BCLKO DIVIDE 1 0 17 2 3 Read Write R W When the MCF5307 is the bus master it drives the R W signal to indicate the direction of subsequent data transfers It is driven high during read bus cycles and driven low during write bus cycles This signal is an input during an external master access 17 2 4 Size SIZ 1 0 When it is the bus master the MCF5307 outputs these signals to indicate the requested data transfer size Table 17 4 shows the definition of the bus request size encodings When the MCF5307 device is not the bus master these signals function as
289. cally zero so attempting an RTE using this old format generates a format error on a ColdFire processor If the format field defines a valid type the processor does the following 1 Reloads the SR operand 2 Fetches the second longword operand 3 Adjusts the stack pointer by adding the format value to the auto incremented address after the first longword fetch 4 Transfers control to the instruction address defined by the second longword operand in the stack frame TRAP Executing TRAP always forces an exception and is useful for implementing system calls The trap instruction may be used to change from user to supervisor mode Interrupt Exception Interrupt exception processing with interrupt recognition and vector fetching includes uninitialized and spurious interrupts as well as those where the requesting device supplies the 8 bit interrupt vector Autovectoring may optionally be configured through the system interface module SIM See Section 9 2 2 Autovector Register AVR M MOTOROLA Chapter 2 ColdFire Core 2 51 Exception Processing Overview Table 2 21 MCF5307 Exceptions Continued Exception Description Reset Asserting the reset input signal RSTI causes a reset exception Reset has the highest exception Exception priority it provides for system initialization and recovery from catastrophic failure When assertion of RSTI is recognized current processing is aborted and cannot be re
290. can be used as software stack pointers index registers or base address registers and may be used for word and longword operations M MOTOROLA Chapter 2 ColdFire Core 2 27 Programming Model 2 2 1 3 Stack Pointer A7 SP The processor core supports a single hardware stack pointer A7 used during stacking for subroutine calls returns and exception handling The stack pointer is implicitly referenced by certain operations and can be explicitly referenced by any instruction specifying an address register The initial value of A7 is loaded from the reset exception vector address 0x0000 The same register is used for user and supervisor modes and may be used for word and longword operations A subroutine call saves the program counter PC on the stack and the return restores the PC from the stack The PC and the status register SR are saved on the stack during exception and interrupt processing The return from exception instruction restores SR and PC values from the stack 2 2 1 4 Program Counter PC The PC holds the address of the executing instruction For sequential instructions the processor automatically increments PC When program flow changes the PC is updated with the target instruction For some instructions the PC specifies the base address for PC relative operand addressing modes 2 2 1 5 Condition Code Register CCR The CCR Figure 2 4 occupies SR 7 0 as shown in Figure 2 3 CCR 4 0 are indicator flag
291. can queue data as much as 4 bytes wide per entry Each entry matches the corresponding bus cycle it generates therefore a misaligned longword write to a write through region creates two entries if the address is to an odd word boundary It creates three entries if it is to an odd byte boundary one per bus cycle 4 9 5 2 2 Push and Store Buffer Bus Operation As soon as the push or store buffer has valid data the internal bus controller uses the next available external bus cycle to generate the appropriate write cycles In the event that 4 18 MCF5307 User s Manual M Cache Operation another cache fill is required for example cache miss to process during the continued instruction execution by the processor pipeline the pipeline stalls until the push and store buffers are empty then generate the required external bus transaction Supervisor instructions the NOP instruction and exception processing synchronize the processor core and guarantee the push and store buffers are empty before proceeding Note that the NOP instruction should be used only to synchronize the pipeline The preferred no operation function is the TPF instruction 4 9 6 Cache Locking Ways 0 and 1 of the cache can be locked by setting CACR HLCK If the cache is locked cache lines in ways 0 and 1 are not subject to being deallocated by normal cache operations As Figure 4 7 B and C shows the algorithm for updating the cache and for identifyin
292. ce exception occurs 13 Force emulation mode If EMU 1 the processor begins executing in emulator mode See Section 5 6 1 1 Emulator Mode 12 11 DDC Debug data control Controls operand data capture for DDATA which displays the number of bytes defined by the operand reference size before the actual data byte displays 8 bits word displays 16 bits and long displays 32 bits one nibble at a time across multiple clock cycles See Table 5 2 00 No operand data is displayed 01 Capture all write data 10 Capture all read data 11 Capture all read and write data M MOTOROLA Chapter 5 Debug Support 5 11 Programming Model Table 5 8 CSR Field Descriptions Continued Bit Name Description 10 User halt enable Selects the CPU privilege level required to execute the HALT instruction 0 HALT is a supervisor only instruction 1 HALT is a supervisor user instruction 9 8 BTB Branch target bytes Defines the number of bytes of branch target address DDATA displays 00 0 bytes 01 Lower 2 bytes of the target address 10 Lower 3 bytes of the target address 11 Entire 4 byte target address See Section 5 3 1 Begin Execution of Taken Branch PST 0 5 7 Reserved should be cleared 6 NPL Non pipelined mode Determines whether the core operates in pipelined or mode or not 0 Pipelined mode 1 Nonpipelined mode The processor effectively executes one instruction at a t
293. ce reached does not affect interrupt on capture function 1 Enable interrupt upon reaching the reference value 3 FRR Free run restart 0 Free run Timer count continues to increment after reaching the reference value 1 Restart Timer count is reset immediately after reaching the reference value 2 1 Input clock source for the timer 00 Stop count 01 System bus clock divided by 1 10 System bus clock divided by 16 Note that this clock source is not synchronized to the timer thus successive time outs may vary slightly 11 TIN pin falling edge 0 RST Reset timer Performs a software timer reset similar to an external reset although other register values can still be written while RST 0 A transition of RST from 1 to 0 resets register values The timer counter is not clocked unless the timer is enabled 0 Reset timer software reset 1 Enable timer 13 3 2 Timer Reference Registers TRRO TRR1 Each timer reference register TRRO TRR1 Figure 13 3 contains the reference value compared with the respective free running timer counter TCNO TCNI as part of the output compare function The reference value is not matched until TCNn equals TRRz 15 id Field REF Reset 1111 1111 1111 1111 R W R W Address MBAR 0x144 TRRO 0x184 TRR1 Figure 13 3 Timer Reference Registers TRRO TRR1 13 3 3 Timer Capture Registers TCRO TCR1 Each timer capture register TCRO TCR1 Figur
294. ches on line aligned addresses so it generally provides maximum performance 2 After the data is loaded into the SRAM it may be appropriate to revise the RAMBAR attribute bits including the write protect and address space mask fields Remember that the SRAM cannot be accessed by the on chip DMAs The on chip system configuration allows concurrent core and DMA execution where the core can execute code 4 4 MCF5307 User s Manual M woronoLA SRAM Initialization out of internal SRAM or cache during DMA access The ColdFire processor or an external emulator using the debug module can perform these initialization functions 4 5 1 SRAM Initialization Code The code segment below initializes the SRAM The code sets the base address of the SRAM at 0x2000_0000 and then initializes the RAM to zeros RAMBASE EQU 0x20000000 set this variable to 0x20000000 RAMVALID EQU 0x00000035 move l RAMBASE RAMVALID DO load RAMBASE valid bit into DO 1 DO RAMBAR load RAMBAR and enable SRAM The following loop initializes the entire SRAM to zero lea l RAMBASE AO load pointer to SRAM move 1 1024 D0 load loop counter into DO SRAM INIT LOOP GIL 0 4 bytes of SRAM subq 1 1 D0 decrement loop counter bne b SRAM_INIT_LOOP exit if done else continue looping The following function copies the number of bytesToMove from the source src to the processor s local RAM at an offset relative to the SRAM base address
295. ciescisessscsiescssestecseontsvestecsdosssvesteessoncsusstestdendsvestesssendsecsies A 4 A 7 VART 1 Control Registers onere entente tenente te thee seco etae eerte eh ead A 6 A 8 Parallel Port Memory 7 9 Interface Memory EP A 8 A 10 DMA Controller Registers esee nennen enne A 8 Xxx MCF5307 User s Manual M About This Book The primary objective of this user s manual is to define the functionality of the MCF5307 processors for use by software and hardware developers The information in this book is subject to change without notice as described in the disclaimers on the title page of this book As with any technical documentation it is the readers responsibility to be sure they are using the most recent version of the documentation To locate any published errata or updates for this document refer to the world wide web at http www motorola com coldfire Audience This manual is intended for system software and hardware developers and applications programmers who want to develop products for the MCF5307 It is assumed that the reader understands operating systems microprocessor system design basic principles of software and hardware and basic details of the ColdFire architecture Organization Following is a summary and a brief description of the major sections of this manual Chapter 1 Overview
296. cise 4 3 Reserved should be cleared 2 Ww Write protect Selects the write privilege of the memory region 0 Read and write accesses permitted 1 Write accesses not permitted 1 0 Reserved should be cleared M woronoLA Chapter 4 Local Memory 4 23 Cache Management 4 11 Cache Management The cache can be enabled and configured by using a MOVEC instruction to access CACR A hardware reset clears CACR disabling the cache and removing all configuration information however reset does not affect the tags state information and data in the cache Set CACR CINVA to invalidate the cache before enabling it The privileged CPUSHL instruction supports cache management by selectively pushing and invalidating cache lines The address register used with CPUSHL directly addresses the cache s directory array The CPUSHL instruction flushes a cache line The value of CACR DPI determines whether CPUSHL invalidates a cache line after it is pushed To push the entire cache implement a software loop to index through all sets and through each of the four lines within each set a total of 512 lines The state of CACR EC does not affect the operation of CPUSHL or CACR CINVA Disabling the cache by setting CACR EC makes the cache nonoperational without affecting tags state information or contents The contents of An used with CPUSHL specify cache row and line indexes This differs from the MC68040 where a physical address is s
297. command formats within any revision level perform a NOP and return the illegal command response 5 5 3 1 ColdFire BDM Command Format All ColdFire Family BDM commands include a 16 bit operation word followed by an optional set of one or more extension words as shown in Figure 5 16 5 20 MCF5307 User s Manual M woronoLA Background Debug Mode BDM 15 10 9 8 7 6 5 4 3 2 0 Operation 0 R W Op Size 0 0 A D Register Extension Word s Figure 5 16 BDM Command Format Table 5 18 describes BDM fields Table 5 18 BDM Field Descriptions Bit Name Description 15 10 Operation Specifies the command These values are listed in Table 5 17 9 0 Reserved 8 R W Direction of operand transfer 0 Data is written to the CPU or to memory from the development system 1 The transfer is from the CPU to the development system 7 6 Operand Operand data size for sized operations Addresses are expressed as 32 bit absolute values Size Note that a command performing a byte sized memory read leaves the upper 8 bits of the response data undefined Referenced data is returned in the lower 8 bits of the response Operand Size Bit Values 00 Byte 8 bits 01 Word 16 bits 10 Longword 32 bits 11 Reserved 5 4 00 Reserved 3 A D Address data Determines whether the register field specifies a data or address register 0 Indicates a data register 1 Indicates an address register
298. covered The reset exception places the processor in supervisor mode by setting SR S and disables tracing by clearing SR T This exception also clears SR M and sets the processor s interrupt priority mask in the SR to the highest level level 7 Next the VBR is initialized to 0 0000 0000 Configuration registers controlling the operation of all processor local memories cache and RAM modules on the MCF5307 are invalidated disabling the memories Note Other implementation specific supervisor registers are also affected Refer to each of the modules in this manual for details on these registers After RSTI is negated the processor waits 80 cycles before beginning the actual reset exception process During this time certain events are sampled including the assertion of the debug breakpoint signal If the processor is not halted it initiates the reset exception by performing two longword read bus cycles The longword at address 0 is loaded into the stack pointer and the longword at address 4 is loaded into the PC After the initial instruction is fetched from memory program execution begins at the address in the PC If an access error or address error occurs before the first instruction executes the processor enters the fault on fault halted state Unsupported If the MCF5307 attempts to execute a valid instruction but the required optional hardware module is Instruction not present in the OEP a non supported instruction exception is gen
299. cription pir No Name 1 Power input 2 AO lO Address bus bit 8 3 A1 lO Address bus bit 8 4 GND Ground pin 5 A2 lO Address bus bit 8 6 A3 lO Address bus bit 8 7 Power input 8 A4 lO Address bus bit 8 9 A5 lO Address bus bit 8 10 GND Ground pin 11 A6 lO Address bus bit 8 12 A7 lO Address bus bit 8 M Chapter 16 Mechanical Data 16 1 Pinout 16 2 Table 16 1 Pins 1 52 Left Top to Bottom Continued Pin i Ne Nams Description mA 13 VCC Power input 14 A8 m lO Address bus bit 8 15 A9 lO Address bus bit 8 16 A10 lO Address bus bit 8 17 GND Ground pin 18 A11 lO Address bus bit 8 19 A12 lO Address bus bit 8 20 A13 lO Address bus bit 8 21 Power input 22 A14 Address bus bit 8 23 A15 lO Address bus bit 8 24 A16 lO Address bus bit 8 25 GND Ground pin 26 A17 lO Address bus bit 8 27 A18 lO Address bus bit 8 28 A19 lO Address bus bit 8 29 VCC Power input 30 A20 Address bus bit 8 31 A21 lO Address bus bit 8 32 A22 lO Address bus bit 8 33 GND Ground 34 A23 lO Address bus bit 8 35 PP8 A24 lO
300. ct control register bank 6 CSCR6 p 10 8 0 004 Chip select address register bank 7 CSAR7 10 6 Reserved M Chapter 10 Chip Select Module 10 5 Chip Select Registers Table 10 6 Chip Select Registers Continued MBAR Offset 31 24 23 16 15 8 7 0 0 008 Chip select mask register bank 7 CSMR7 p 10 6 0x0DC Reserved Chip select control register bank 7 CSCR7 p 10 8 Addresses not assigned to a register and undefined register bits are reserved for expansion Write accesses to these reserved address spaces and reserved register bits have no effect NOTE External masters cannot access MCF5307 on chip memories or MBAR but can access any of the chip select module registers 10 4 1 Chip Select Module Registers The chip select module is programmed through the chip select address registers CSARO CSAR7 chip select mask registers CSMRO CSMR7 and the chip select control registers CSCRO CSCR7 10 4 1 1 Chip Select Address Registers CSARO CSAR7 Chip select address registers Figure 10 2 specify the chip select base addresses 15 0 Field BA Reset Uninitialized R W R W Addr 0x080 CSARO 0x08C CSAR1 0x098 CSAR2 0x0A4 CSAR3 0x0B0 CSAR4 Ox0BC CSAR5 0x0C8 CSAR6 0x0D4 CSAR7 Figure 10 2 Chip Select Address Registers CSARO CSAR7 Table 10 7 describes CSAR BA Table 10 7 CSARn Field Descrip
301. ction regardless of whether a character is being received or transmitted 14 5 3 1 Automatic Echo Mode In automatic echo mode shown in Figure 14 23 the UART automatically resends received data bit by bit The local CPU to receiver communication continues normally but the CPU to transmitter link is disabled In this mode received data is clocked on the receiver clock and resent on TxD The receiver must be enabled but the transmitter need not be RxD Input CPU Disabled Disabled TxD Input Figure 14 23 Automatic Echo Because the transmitter is inactive USRn TXEMP TxRDY are inactive and data is sent as it is received Received parity is checked but is not recalculated for transmission Character framing is also checked but stop bits are sent as they are received A received break is echoed as received until the next valid start bit is detected 14 5 3 2 Local Loop Back Mode Figure 14 24 shows how TxD and RxD are internally connected in local loop back mode This mode is for testing the operation of a local UART module channel by sending data to the transmitter and checking data assembled by the receiver to ensure proper operations M woronoLA Chapter 14 UART Modules 14 25 Operation Rx Disabled Input CPU gt Ix Disabled Typ Input Figure 14 24 Local Loop Back Features of this local loop back mode are as follows Transmitte
302. cution of the instruction 2 22 MCF5307 User s Manual M woronoLA Features and Enhancements Instruction Address Generation Instruction Address 31 0 Fetch Cycle 1 gt Instruction Fetch Instruction Pipeline Fetch Cycle 2 Instruction Early Decode FIFO Instruction Buffer lt Data 31 0 DSOC Decode amp Select Operand Operand Fetch gt Execution Pipeline Address AGEX Generation Execute Figure 2 1 ColdFire Enhanced Pipeline 2 1 2 1 Instruction Fetch Pipeline IFP Because the fetch and execution pipelines are decoupled by an eight instruction FIFO buffer the IFP can prefetch instructions before the OEP needs them minimizing stalls 2 1 2 1 1 Branch Acceleration Because the IFP and the OEP are decoupled by the instruction buffer the increased depth of the IFP is generally hidden from the OEP s instruction execution The one exception is change of flow instructions such as unconditional branches or jumps subroutine calls and taken conditional branches To minimize the effects of the increased depth of the IFP the prefetched instruction stream is monitored for change of flow opcodes When certain types of change of flow instructions are detected the target instruction address is calculated and fetching immediately begins in the target stream M MOTOROLA Chapter 2 ColdFire Core 2 23 Features and
303. cy divider Reserved register IFDR p 8 7 M woronoLA Appendix A List of Memory Maps Table A 9 12 Interface Memory MBAR Offset 31 24 23 16 15 8 7 0 0x288 12 control register Reserved 12 p 8 8 Ox28C 1 status register Reserved I2SR p 8 9 0x290 12 data I O register Reserved I2DR p 8 10 Table A 10 DMA Controller Registers MBAR Offset 31 24 23 16 15 8 7 0 0x300 Source address register 0 SARO p 12 6 0x304 Destination address register 0 DARO p 12 7 0x308 DMA control register 0 DCRO p 12 8 0x30C Byte count register 0 BCR24BIT 0 Reserved 0x30C Reserved Byte count register 0 BCR24BIT 1 BCRO p 12 7 0x310 DMA status register 0 Reserved DSRO p 12 10 0x314 DMA interrupt vector Reserved register 0 DIVRO p 12 11 0x340 Source address register 1 SAR1 p 12 6 0x344 Destination address register 1 DAR1 p 12 7 0x348 DMA control register 1 DCR1 p 12 8 0x34C Byte count register 1 BCR24BIT 0 Reserved 0x34C Reserved Byte count register 1 BCR24BIT 1 BCR1 p 12 7 0x350 DMA status register 1 Reserved DSR1 p 12 10 0x354 DMA interrupt vector Reserved register 1 DIVR1 p 12 11 0x380 Source address register 2 SAR2 p 12 6 0x384 Destination address register 2 DAR2 p 12 7 0x388
304. cycle is generated on the external bus If autovector generation is used for external interrupts no interrupt acknowledge cycle is shown on the external bus AS is not asserted unless AVR BLK is 0 Consequently the external interrupt must be cleared in the interrupt service routine See Section 9 2 2 Autovector Register AVR 18 7 1 Level 7 Interrupts Level 7 interrupts are nonmaskable and are handled differently than other interrupts Level 7 interrupts are edge triggered by a transition from a lower priority request to the level 7 request Interrupts at all other levels are level sensitive Therefore if IRQ7 remains asserted the MCF5307 recognizes only one level 7 interrupt because only one transition from a lower level request to a level 7evel 7 request occurred For the processor to recognize two consecutive level 7 interrupts one of the following must occur 18 18 MCF5307 User s Manual M woronoLA Interrupt Exceptions The interrupt request on the interrupt control pins is raised to level 7 and stays there until an interrupt acknowledge cycle begins The level later drops but then returns to level 7 causing a second transition on the interrupt control lines The interrupt request on the interrupt control pins is raised to level 7 and stays there If the level 7 interrupt routine lowers the mask level a second level 7 interrupt is recognized without a transition of the interrupt control pins After the level 7 routin
305. d p 10 6 0x084 Chip select mask register bank 0 CSMR0O p 10 6 0x088 Reserved Chip select control register bank 0 CSCRO p 10 8 0x08C Chip select address register bank 1 CSAR1 Reserved p 10 6 0x090 Chip select mask register bank 1 CSMR1 p 10 6 0x094 Reserved Chip select control register bank 1 CSCR1 p 10 8 0x098 Chip select address register bank 2 CSAR2 Reserved p 10 6 0x09C Chip select mask register bank 2 CSMR2 p 10 6 Ox0A0 Reserved Chip select control register bank 2 CSCR2 p 10 8 0 0 4 Chip select address register bank 3 CSAR3 Reserved p 10 6 0x0A8 Chip select mask register bank 3 CSMR3 p 10 6 Ox0AC Reserved Chip select control register bank 3 CSCR3 p 10 8 Chip select address register bank 4 Reserved p 10 6 0x0B4 Chip select mask register bank 4 CSMR4 10 6 0x0B8 Reserved Chip select control register bank 4 CSCR4 p 10 8 0x0BC Chip select address register bank 5 CSAR5 Reserved p 10 6 0x0C0 Chip select mask register bank 5 CSMR5 p 10 6 0x0C4 Reserved Chip select control register bank 5 CSCR5 p 10 8 0x0C8 Chip select address register bank 6 CSAR6 Reserved p 10 6 0x0CC Chip select mask register bank 6 CSMR6 p 10 6 0 000 Reserved Chip select control register bank 6 CSCR6 p 10 8 0x0D4 Chip select address register bank 7 CSAR7 Reserved p 10 6 0 008 Chip select
306. d UIVRn is reset to OxOF indicating an uninitialized interrupt condition 14 3 13 UART Input Port Register UIPn The UART input port registers Figure 14 15 show the current state of the CTS input 7 1 0 Field CTS Reset 1111 1111 R W Read only Address MBAR 0x1F4 UIPO 0x234 UIP1 Figure 14 15 UART Input Port Register UIPn Table 14 11 describes UIP fields Table 14 11 UIPn Field Descriptions Bits Name Description 7 1 Reserved should be cleared 0 CTS Current state The CTS value is latched and reflects the state of the input pin when UIPn is read Note This bit has the same function and value as UIPCRn RTS 0 The current state of the CTS input is logic 0 1 The current state of the CTS input is logic 1 14 3 14 UART Output Port Command Registers UOP1n UOPOn In UART mode the RTS output can be asserted by writing a 1 to UOPIn RTS and negated by writing a 1 to UOPOn RTS See Figure 14 16 M MOTOROLA Chapter 14 UART Modules 14 15 UART Module Signal Definitions 7 1 0 Field RTS Reset 0000 0000 R W Write only Addr UARTO MBAR 0x1F8 UOP1 0x1FC UART1 0x238 UOP1 0x23C Figure 14 16 UART Output Port Command Register UOP1 UOPO Table 14 12 describes UOPI fields Table 14 12 UOP1 UOPO Field Descriptions Bits Name Description 7 1 Reserved sho
307. d C2 During C2 the MCF5307 requests the external bus because of a pending internal transfer On C3 the external releases mastership and the external arbiter grants the bus to the MCF5307 by asserting BG At this point an internal is access pending so the MCF5307 asserts BD during C4 and begins the access Thus the MCF5307 becomes the explicit bus master Also during C4 the external arbiter removes the grant from the MCF5307 by negating BG Because the MCF5307 is bus master it continues to assert BD until the current transfer completes Because BG is negated the MCF5307 negates BD during C9 and three states the external bus thereby passing mastership to an external device The MCF5307 can assert BR to signal the external arbiter that it needs the bus However there is no guarantee that when the bus is granted to the MCF5307 that a bus cycle will be performed At best BR must be used as a status output that indicates when the MCF5307 needs the bus but not as an indication that the MCF5307 is in a certain bus arbitration state Figure 18 32 is a high level state diagram for MCF5307 bus arbitration protocol Table 18 6 describes the four states shown in Figure 18 32 M MOTOROLA Chapter 18 Bus Operation 18 31 General Operation of External Master Transfers External Implicit Master D1 B3 Explicit Master Figure 18 32 Three Wire Bus Arbitration Protocol State Diagram Table 18 11 lists conditions that cause sta
308. data area CacheLoop tst b a0 touch location load into data cache lea 16 a0 a0 increment address to next line subq l1 1 d0 decrement loop counter bne b CacheLoop if done then exit else continue A 4K region has been loaded into levels 0 and 1 of the 8K cache lock it move l 0xA8000100 d0 set the cache lock bit movec d0 cacr o in the CACR rts align 16 4 12 Cache Operation Summary This section gives operational details for the cache and presents cache line state diagrams 4 12 1 Cache State Transitions Using the V and M bits the cache supports a line based protocol allowing individual cache lines to be invalid valid or modified To maintain memory coherency the cache supports both write through and copyback modes specified by the corresponding ACR CM or CACR DCM if no ACR matches Read or write misses to copyback regions cause the cache controller to read a cache line from memory into the cache If available tag and data from memory update an invalid line in the selected set The line state then changes from invalid to valid by setting the V bit If all lines in the row are already valid or modified the pseudo round robin replacement algorithm selects one of the four lines and replaces the tag and data Before replacement modified lines are temporarily buffered and later copied back to memory after the new line has been read from memory M woronoLA Chapter 4 Local Memory 4 25 Cache Operati
309. ddress character the slave receiver channel notifies its respective CPU by setting USRn RxRDY and generating an interrupt if programmed to do so Each slave station CPU then compares the received address to its station address and enables its receiver if it wishes to receive the subsequent data characters or block of data from the master station Slave stations not addressed continue monitoring the data stream Data fields in the data stream are separated by an address character After 14 26 MCF5307 User s Manual M woronoLA Operation a slave receives a block of data its CPU disables the receiver and repeats the process Functional timing information for multidrop mode is shown in Figure 14 26 Master Station A D A D A D T T T T TxD ADD1 i CO ADD2 1 L Transmitter Enabled USRn TxRDY N N internal module N vl N select UMRIn PM 11 CO ADD2 UMRtn PT 1 UMRtn PT 0 UMRtn PT 2 Peripheral Station A D A D A D A D A D T T T T TT T T T T f RxD o ADD11 co ADD21 0 L LA Receiver Enabled USRn RxRDY N internal module select UMR1n PM 11 ADD 1 Status Data Status Data UMR1n PM
310. de changed for the region corresponding to this line To avoid this state execute a CPUSHL instruction or set CACR CINVA before switching modes Cache C W I5 No action C W V5 No action CD5 No action modified data invalidate stay in invalid state go to invalid state lost go to invalid state Cache C W I6 No action C W V6 No action CD6 Push modified line to push C W I7 stay in invalid state go to invalid state memory go to invalid state C W V7 No action CD7 Push modified line to stay in valid state memory go to valid state M MOTOROLA Chapter 4 Local Memory 4 27 Cache Operation Summary The following tables present the same information as Table 4 6 organized by the current state of the cache line In Table 4 7 the current state is invalid Table 4 7 Cache Line State Transitions Current State Invalid Access Response Read miss C W I1 Read line from memory and update cache supply data to processor go to valid state Read hit C W I2 Not possible Write miss copyback Read line from memory update cache write data to cache go to modified state Write miss write through WI3 Write data to memory stay in invalid state Write hit copyback Cl4 Not possible Write hit write through WI4 Not possible Cache invalidate C W I5 No action stay in invalid state Cache push C W I6 No action st
311. destination device see Figure 12 2 Control and Data Memory Peripheral DMA Memory Peripheral Control and Data Figure 12 2 Dual Address Transfer e Single address transfers An external device can initiate a single address transfer by asserting DREQ The MCF5307 provides address and control signals for single address transfers The external device reads to or writes from the specified address as Figure 12 3 shows External logic is required M woronoLA Chapter 12 DMA Controller Module 12 3 DMA Controller Module Programming Model Write Control E M DMA Du Signals Data Memory Peripheral Read Control is OE DMA Bie Signals Data Memory gt Peripheral Figure 12 3 Single Address Transfers Any operation involving the DMA module follows the same three steps 1 Channel initialization Channel registers are loaded with control information address pointers and a byte transfer count 2 Data transfer The DMA accepts requests for operand transfers and provides addressing and bus control for the transfers 3 Channel termination Occurs after the operation is finished either successfully or due to an error The channel indicates the operation status in the channel s DSR described in Section 12 4 5 DMA Status Registers DSRO DSR3 12 4 DMA Controller Module Programming Model This section descr
312. dress attributes and a mask to be matched in the trigger The register value is compared with address attribute signals from the processor s local high speed bus as defined by the setting of the trigger definition register TDR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field RM SZM TTM TMM R SZ TT TM Reset 0000 0000 0000 0101 R W Write only AATR is accessible in supervisor mode as debug control register 0x06 using the WDEBUG instruction and through the BDM port using the WOMREG command DRe 4 0 0x06 Figure 5 5 Address Attribute Trigger Register AATR Table 5 4 describes AATR fields MOTOROLA Chapter 5 Debug Support 5 7 Programming Model Table 5 4 AATR Field Descriptions Bits Name Description 15 RM Read write mask Setting RM masks R in address comparisons 14 18 SZM Size mask Setting an SZM bit masks the corresponding SZ bit in address comparisons 12 11 TTM Transfer type mask Setting a TTM bit masks the corresponding TT bit in address comparisons 10 8 TMM Transfer modifier mask Setting a TMM bit masks the corresponding TM bit in address comparisons 7 R Read write R is compared with the R W signal of the processor s local bus 6 5 SZ Size Compared to the processor s local bus size signals 00 Longword 01 Byte 10 Word 11 Reserved 4 3 TT Transfer type Compared with the local bus transfer type signals 00 Normal processor access 01 Reser
313. dress bits The debug module always returns a not ready response At the completion of cycle 3 the debug module initiates a memory read operation Any serial transfers that begin during a memory access return a not ready response MCF5307 User s Manual M woronoLA Background Debug Mode BDM Results are returned in the two serial transfer cycles after the memory access completes For any command performing a byte sized memory read operation the upper 8 bits of the response data are undefined and the referenced data is returned in the lower 8 bits The next command s opcode is sent to the debug module during the final transfer If a memory or register access is terminated with a bus error the error status S 1 DATA 0x0001 is returned instead of result data 5 5 3 3 Command Set Descriptions The following sections describe the commands summarized in Table 5 17 NOTE The BDM status bit S is 0 for normally completed commands S 1 for illegal commands not ready responses and transfers with bus errors Section 5 5 2 Serial Interface describes the receive packet format Motorola reserves unassigned command opcodes for future expansion Unused command formats in any revision level perform a NOP and return an illegal command response M MOTOROLA Chapter 5 Debug Support 5 23 Background Debug Mode BDM 5 5 3 3 1 Read A D Register RAREG RDREG Read the selected address or data register and return the 32 bi
314. dress is incremented by the operand size 1 2 or 4 and saved in a temporary register after the memory write Subsequent FILL commands use this address perform the write increment it by the current operand size and store the updated address in the temporary register If an initial WRITE is not executed preceding the first FILL command the illegal command response is returned NOTE The FILL command does not check for a valid address FILL is a valid command only when preceded by another FILL a NOP or a WRITE command Otherwise an illegal command response is returned The NOP command can be used for intercommand padding without corrupting the address pointer The size field is examined each time a FILL command is processed allowing the operand size to be altered dynamically Command Formats 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Byte 0 1 OxC 0x0 0 0 D 7 0 Word 0 1 OxC 0 4 0x0 D 15 0 Longword 0 1 OxC 0x8 0 0 D 31 16 D 15 0 Figure 5 28 FILL Command Format M MOTOROLA Chapter 5 Debug Support 5 31 Background Debug Mode BDM Command Sequence MS DATA LS DATA ANOT READY gt READY gt XXX NEXT CMD ILLEGAL NOT READY WRITE MEMORY LOCATION FILL LONG 77 NOT READY NEXT CMD COMPLETE NEXT CMD NOT READY FILL B W 77 WRITE Ti gt s MEMORY tU
315. e completes the MCF5307 compares the mask level to the request level on the IRQx signals Because the mask level is lower than the requested level the interrupt mask is set back to level 7 To ensure it is recognized the level 7 request on IRQ7 must be held until the second interrupt acknowledge bus cycle begins 18 7 2 Interrupt Acknowledge Cycle When the MCF5307 processes an interrupt exception it performs an interrupt acknowledge bus cycle to obtain the vector number that contains the starting location of the interrupt exception handler The interrupt acknowledge bus cycle is a read transfer that differs from normal read cycles in the following respects TT 1 0 2 0x3 to indicate a CPU space or acknowledge bus cycle TM 2 0 the level of interrupt being acknowledged A 31 5 0x7F_FFFF A 4 2 the interrupt request level being acknowledged same as TM 2 0 A 1 0 00 During the interrupt acknowledge bus cycle a read cycle the responding device places the vector number on D 31 24 and the cycle is terminated normally with TA Figure 18 23 is a flow diagram for an interrupt acknowledge cycle terminated with TA M MOTOROLA Chapter 18 Bus Operation 18 19 Bus Arbitration MCF5307 SYSTEM Drive Ox7FFFFF on A 31 5 Drive 0x0 on A 1 0 Drive interrupt level on A 4 2 Drive R W to read R W 1 Drive SIZ 1 0 to indicate byte SIZ 1 0 01 Drive TT 1 0 and TM 2 0 to indicate interrupt acknowledge T
316. e shifting in initialization data The Update DR state in conjunction with the falling edge of TCK can then transfer this data to the update cells This data is applied to external outputs when an instruction listed above is applied HIGHZ Optional 101 Anticipates the need to backdrive outputs and protects inputs from random toggling HIZ during board testing Selects the bypass register forcing all output and bidirectional pins into high impedance HIGHZ goes active on the falling edge of TCK in the Update IR state when instruction shift register data held is equivalent to octal 5 M MOTOROLA Chapter 19 IEEE 1149 1 Test Access Port JTAG 19 5 JTAG Register Descriptions Table 19 2 JTAG Instructions Continued Instruction Class IR Description CLAMP Optional 110 Selects the bypass register and asserts functional reset while forcing all output and CMP bidirectional pins configured as outputs to fixed preloaded values in the boundary scan update registers Enhances test efficiency by reducing the overall shift path to one bit the bypass register while conducting an EXTEST type of instruction through the boundary scan register CLAMP becomes active on the falling edge of TCK in the Update IR state when instruction shift register data is equivalent to octal 6 BYPASS Required 111 Selects the single bit bypass register creating a single bit shift register path from TDI BYP to the bypass
317. e 13 4 latches the corresponding value during a capture operation when an edge occurs on TIN as programmed in TMRz 13 4 MCF5307 User s Manual M woronoLA General Purpose Timer Programming Model BCLKO is assumed to be the clock source TIN cannot simultaneously function as a clocking source and as an input capture pin 15 0 Field CAP 16 bit capture counter value Reset 0000 0000 0000 0000 R W Read only Address MBAR 0x148 TCRO 0x188 TCR1 Figure 13 4 Timer Capture Register TCRO TCR1 13 3 4 Timer Counters TCNO TCN1 The current value of the 16 bit incrementing timer counters TCNO TCN1 Figure 13 5 can be read anytime without affecting counting Writing to TCNn clears it The timer counter decrements on the clock source rising edge BCLKO 1 BCLKO 16 or TIN 15 0 Field 16 bit timer counter value count Reset 0000 0000 0000 0000 R W R W to reset Address MBAR 0x14C TCNO 0x18C TCN1 Figure 13 5 Timer Counters TCNO TCN1 13 3 5 Timer Event Registers TERO TER1 Each timer event register TERO TER1 Figure 13 6 reports capture or reference events events the timer recognizes by setting TERn CAP or TERn REF which it does regardless of the corresponding interrupt enable bit values Writing a 1 to either REF or CAP clears it writing a 0 does not affect bit value both bits can be cleared at the same time REF and CAP m
318. e 18 13 in that the address lines change only at the beginning assertion of TS and TIP and end negation of TIP of the transfer S0 51 S2 53 S4 S5 S6 57 S8 59 510 511 512 BCLKO A 31 0 TT 1 0 TM 0 SIZ a X X R W 1 0 Read gt TA ms m Figure 18 12 Line Read Burst 2 1 1 1 External Termination Figure 18 13 shows timing when internal termination is used 18 12 MCF5307 User s Manual M Data Transfer Operation 0 51 52 53 S4 S5 S6 57 S8 59 510 511 512 BCLKO 31 0 X X X X X 2 0 sz 9 X X R W N um B 5 CSX E BWEx OE D 31 0 Read Read Read Read DODD TA Figure 18 13 Line Read Burst 2 1 1 1 Internal Termination Figure 18 14 shows a line access read with one wait state programmed in CSCRx to give the peripheral or memory more time to return read data This figure follows the same execution as a zero wait state read burst with the exception of an added wait state S11645813 0 1 S2 S3 WS 54 S5 WS 56 S7 WS S8 S9 WS 510 512 BCLKO A A A A 31 0 TT 1 0 Tol Si E X X R W TP LN AS CSx BE BWEx D 31 0 Read
319. e Watchdog Service Register SWSR M MOTOROLA Chapter 6 SIM Overview 6 9 Programming Model 6 2 8 PLL Clock Control for CPU STOP Instruction The SIM contains the PLL clock control register which is described in detail in Section 7 2 4 PLL Control Register PLLCR PLLCR ENBSTOP PLLIPL are significant to the operation of the SIM and are described as follows PLLCR ENBSTOP must be set for the ColdFire CPU STOP instruction to be acknowledged This bit is cleared at reset and must be set for the MCF5307 to enter low power modes The CPU STOP instruction stops only clocks to the core processor All internal modules remain clocked and can generate interrupts to restart the ColdFire core For example the on chip timer can be used to interrupt the processor after a given timer countdown PLLCR PLLIPL determines the minimum level at which an interrupt decoded as an interrupt priority level or IPL must occur to awaken the PLL The PLL then turns clocks back on to the core processor and interrupt exception processing takes place Table 6 5 describes PLLIPL settings to be compared against the interrupt ranges that awaken the core processor from a CPU STOP instruction Table 6 5 PLLIPL Settings PLLIPL Description 000 Any interrupts can wake core 001 Interrupts 2 7 010 Interrupts 3 7 011 Interrupts 4 7 100 Interrupts 5 7 101 Interrupts 6 7 110 Interrupt 7 only 111 No interrupts can
320. e any other execution 4 Enable refresh set DACR RE and wait for at least 8 refreshes to occur 5 Before issuing the MRS command determine if the DMR mask bits need to be modified to allow the MRS to execute properly 6 Issue the MRS command by setting DACR IMRS and accessing a location in the SDRAM Note that mode register settings are driven on the SDRAM address bus so care must be taken to change DMR BAM if the mode register configuration does not fall in the address range determined by the address mask bits After the mode register is set DMR mask bits can be restored to their desired configuration 11 4 5 1 Mode Register Settings It is possible to configure the operation of SDRAMs namely their burst operation and CAS latency through the SDRAM component s mode register CAS latency is a function of the speed of the SDRAM and the bus clock of the DRAM controller The DRAM controller operates at a CAS latency of 1 2 or 3 Although the MCF5307 DRAM controller supports bursting operations it does not use the bursting features of the SDRAMs Because the MCF5307 can burst operand sizes of 1 2 4 or 16 bytes long the concept of a fixed burst length in the SDRAMs mode register becomes problematic Therefore the MCF5307 DRAM controller generates the burst cycles rather than the SDRAM device Because the MCF5307 generates a new address and a READ or WRITE command for each transfer within the burst the SDRAM mode register should
321. e appropriate chip select for the external master access along with the appropriate byte enables Figure 18 25 shows a burst line access for an external master transfer with the chip select set to no wait states and with internal transfer acknowledge assertion enabled M MOTOROLA Chapter 18 Bus Operation 18 23 General Operation of External Master Transfers C1 C2 4 C5 C6 C7 C8 C9 C10 C11 BCLKO ww oj AAA AA TT 1 0 Mes _ AS BR D 31 0 X X x BG BD2 E HOLDREQ External Master Depending on programming these signals may or may not be driven by the processor These signals are driven by the processor for an external master transfer Figure 18 25 External Master Burst Line Access to 32 Bit Port Table 18 9 defines the cycles for Figure 18 25 Table 18 9 Cycles for External Master Burst Line Access to 32 Bit Port Cycle Definition C1 The external device is bus master and asserts HOLDREQ indicating to the MCF5307 to hold all bus requests In other words BD should not be asserted The external master drives address TS R W TT 1 0 TM 2 0 TIP and SIZ 1 0 as inputs to the MCF5307 SIZ 1 0 inputs indicate a line transfer The MCF5307 is not asserting BR C2 C3 The MCF5307 decodes the external device s address and control sign
322. e attributes ACRO attributes else if address ACR1 address including mask effective attributes ACRI attributes else effective attributes CACR default attributes Addresses matching an ACR can also be write protected using ACR W Addresses that do not match either ACR can be write protected using CACR DW Reset disables the cache and clears all CACR bits As shown in Figure 4 4 reset does not automatically invalidate cache entries they must be invalidated through software The ACRs allow the defaults selected in the CACR to be overridden In addition some instructions for example CPUSHL and processor core operations perform accesses that have an implicit caching mode associated with them The following sections discuss the different caching accesses and their associated cache modes 4 9 1 1 Cacheable Accesses If ACRn CM or the default field of the CACR indicates write through or copyback the access is cacheable A read access to a write through or copyback region is read from the M woronoLA Chapter 4 Local Memory 4 13 Cache Operation cache if matching data is found Otherwise the data is read from memory and the cache is updated When a line is being read from memory for either a write through or copyback read miss the longword within the line that contains the core requested data is loaded first and the requested data is given immediately to the processor without waiting for the three remaining longwords to reach t
323. e changed only after the receiver transmitter is issued a software reset command That is if channel operation is not disabled undesirable results may occur This address is for factory testing Reading this location results in undesired effects and possible incorrect transmission or reception of characters Register contents may also be changed Address triggered commands NOTE UART registers are accessible only as bytes Although external masters cannot access on chip memories or MBAR they can access any UART registers 14 3 1 UART Mode Registers 1 UMR1 n The UART mode registers 1 UMRI1z control configuration UMRIz can be read or written when the mode register pointer points to it at RESET or after RESET MODE REGISTER POINTER command using UCRA MISC After UMR1n is read or written the pointer points to UMR2n 14 4 MCF5307 User s Manual M MOTOROLA Register Descriptions 6 5 4 3 2 1 0 Field RxRTS RxIRQ FFULL ERR PM PT B C Reset 0000 0000 R W R W Address MBAR 0x1C0 UARTO 0x200 UART1 After UMR1n is read or written the pointer points to UMR2n Figure 14 2 UART Mode Registers 1 UMR1n Table 14 2 describes UMRIn fields Table 14 2 UMR1n Field Descriptions Bits Name Description 7 RxRTS Receiver request to send Allows the RTS output to control the CTS input of the transmitting device to preve
324. e destination is auto aligned The address register chosen for alignment increments regardless of the increment value Configuration error checking is performed on registers not chosen for alignment If BCR is greater than 16 the address determines transfer size Bytes words or longwords are transferred until the address is aligned to the programmed size boundary at which time accesses begin using the programmed size If BCR is less than 16 at the start of a transfer the number of bytes remaining dictates transfer size For example AA 1 SAR 0x0001 BCR 0x00F0 SSIZE 00 longword and DSIZE 01 byte Because SSIZE gt DSIZE the source is auto aligned Error checking is performed on destination registers The access sequence is as follows 1 Read byte from 0x0001 write 1 byte increment SAR 2 Read word from 0x0002 write 2 bytes increment SAR 3 Read longword from 0x0004 write 4 bytes increment SAR M woronoLA Chapter 12 DMA Controller Module 12 17 DMA Controller Module Functional Description 4 Repeat longwords until SAR OxOOFO0 5 Read byte from 0x00F0 write byte increment SAR If DSIZE is another size data writes are optimized to write the largest size allowed based on the address but not exceeding the configured size 12 5 4 3 Bandwidth Control Bandwidth control makes it possible to force the DMA off the bus to allow access to another device DCR BWC provides seven levels of block transfe
325. e level of debug module functionality An emulator could use this information to identify the level of functionality supported 0000 Initial debug functionality Revision A 0001 Revision B this is the only valid value for the MCF5307 19 Reserved should be cleared 18 BKD Breakpoint disable Used to disable the normal BKPT input functionality and to allow the assertion of BKPT to generate a debug interrupt 0 Normal operation 1 BKPT is edge sensitive a high to low edge on BKPT signals a debug interrupt to the processor The processor makes this interrupt request pending until the next sample point when the exception is initiated In the ColdFire architecture the interrupt sample point occurs once per instruction There is no support for nesting debug interrupts 17 PCD PSTCLK disable Setting PCD disables generation of PSTCLK PST and DDATA outputs and forces them to remain quiescent 16 IPW Inhibit processor writes Setting IPW inhibits processor initiated writes to the debug module s programming model registers IPW can be modified only by commands from the external development system 15 MAP Force processor references in emulator mode 0 All emulator mode references are mapped into supervisor code and data spaces 1 The processor maps all references while in emulator mode to a special address space TT 10 TM 101 or 110 14 TRC Force emulation mode on trace exception If TRC 1 the processor enters emulator mode when a tra
326. e memory block and an address exception occurs Write accesses to a write protected DRAM region are compared in the chip select module for a hit If no hit occurs an external bus cycle is generated If this external bus cycle is not acknowledged an access exception occurs 7 Reserved should be cleared M MOTOROLA Chapter 11 Synchronous Asynchronous DRAM Controller Module 11 7 Asynchronous Operation Table 11 5 DMRO DMR1 Field Descriptions Continued Bits Name Description 6 1 AMx Address modifier masks Determine which accesses can occur in a given DRAM block 0 Allow access type to hit in DRAM 1 Do not allow access type to hit in DRAM Bit Associated Access Type Access Definition CPU space interrupt acknowledge MOVEC instruction or interrupt acknowledge cycle AM Alternate master External or DMA master SC Supervisor code Any supervisor only instruction access SD Supervisor data Any data fetched during the instruction access UC User code Any user instruction UD User data Any user data 0 V Valid Cleared at reset to ensure that the DRAM block is not erroneously decoded 0 Do not decode DRAM accesses 1 Registers controlling the DRAM block are initialized DRAM accesses can be decoded 11 3 3 General Asynchronous Operation Guidelines The DRAM controller provides control for RAS CAS and DRAMW signals as well as address multiplexing and
327. e moved efficiently by using the MOVEM instruction which automatically generates line sized burst references and is ideal for filling registers quickly with input data filter coefficients and output data Loading an operand from memory into a register during a MAC operation makes some DSP operations especially filtering and convolution more manageable The MACSR has a 4 bit operational mode field and three condition flags The operational mode bits control the overflow saturation mode whether operands are signed or unsigned whether operands are treated as integers or fractions and how rounding is performed Negative zero and overflow flags are also provided The three program visible MAC registers a 32 bit accumulator ACC the MAC mask register MASK and MACSR are described in Section 3 1 1 MAC Programming Model 3 1 3 MAC Instruction Set Summary The MAC unit supports the integer multiply operations defined by the baseline ColdFire architecture as well as the new multiply accumulate instructions Table 3 1 summarizes the MAC unit instruction set Table 3 1 MAC Instruction Summary Instruction Mnemonic Description Multiply Signed MULS ea y Dx Multiplies two signed operands yielding a signed result Multiply Unsigned MULU lt ea gt y Dx Multiplies two unsigned operands yielding an unsigned result Multiply Accumulate MAC Ry RxSF Multiplies two operands then adds or subtracts t
328. e remainder of the chapter is divided between descriptions of asynchronous and synchronous operations Suggested Reading The following literature may be helpful with respect to the topics in Part II The PC Bus Specification Version 2 1 January 2000 Acronyms and Abbreviations Table II i contains acronyms and abbreviations are used in Part II Table 1 1 Acronyms and Abbreviated Terms NN em Inter integrated circuit Institute for Electrical and Electronics Engineers s De Due wes wen 1 MCF5307 User s Manual M Table 11 Acronyms and Abbreviated Terms Continued BINNEN NN fron M Part Il System Integration Module SIM 11 Il iv MCF5307 User s Manual M Chapter 6 SIM Overview This chapter provides detailed operation information regarding the system integration module SIM It describes the SIM programming model bus arbitration and system protection functions for the MCF5307 6 1 Features The SIM shown in Figure 6 1 provides overall control of the bus and serves as the interface between the ColdFire core processor complex and the internal peripheral devices BCLKO to on chip peripherals V3 COLDFIRE PROCESSOR COMPLEX DMA SYSTEM INTEGRATION MODULE SIM Four PLL Control System Control Base Address Bus Master Park Parallel Port Channels PLL
329. e the SDRAMs are in self refresh the SDRAM controls the refresh period 10 9 RTIM Refresh timing Determines the timing operation of auto refresh in the DRAM controller Specifically it determines the number of clocks inserted between a REF command and the next possible ACTV command This same timing is used for both memory blocks controlled by the DRAM controller This corresponds to tac in the SDRAM specifications 00 3 clocks 01 6 clocks 1x 9 clocks 8 0 RC Refresh count Controls refresh frequency The number of bus clocks between refresh cycles is RC 1 16 Refresh can range from 16 8192 bus clocks to accommodate both standard and low power DRAMs with bus clock operation from less than 2 MHz to greater than 50 MHz The following example calculates RC for an auto refresh period for 4096 rows to receive 64 mS of refresh every 15 625 us for each row 625 bus clocks at 40 MHz This operation is the same as in asynchronous mode of bus clocks 625 RC field 1 16 RC 625 bus clocks 16 1 38 06 which rounds to 38 therefore RC 0x26 11 4 3 2 DRAM Address and Control Registers DACRO DACR1 in Synchronous Mode The DRAM address and control registers DACRO and DACR1 shown in Figure 11 16 contain the base address compare value and the control bits for both memory blocks 0 and 1 of the DRAM controller Address and timing are also controlled by bits in DACRn
330. e to CAS inputs on industry standard DRAMs These provide CAS for a given ADRAM block When SDRAMs are used CAS 3 0 control the byte enables DQMx for standard SDRAMs CAS 3 0 strobes data in least to most significant byte order CASO is MSB DRAMW DRAM read write Asserted when a DRAM write cycle is underway Negated for read bus cycles 11 3 2 Asynchronous Register Set The following register configurations apply when DCR SO is 0 indicating the DRAM controller is interfacing to asynchronous DRAMs 11 3 2 1 DRAM Control Register DCR in Asynchronous Mode The DCR provides programmable options for the refresh logic as well as the control bit to determine if the module is operating with synchronous or asynchronous DRAMs The DCR is shown in Figure 11 2 11 4 MCF5307 User s Manual M woronoLA Field Reset R W Address Asynchronous Operation SO NAM RRA RRP RC Uninitialized R W MBAR 0x100 Figure 11 2 DRAM Control Register DCR Asynchronous Mode Table 11 3 describes DCR fields Table 11 3 DCR Field Descriptions Asynchronous Mode Bits Name Description 15 SO Synchronous operation Selects synchronous or asynchronous mode A DRAM controller in synchronous mode can be switched to ADRAM mode only by resetting the MCF5307 0 Asynchronous DRAMs Default at reset 1 Synchronous DRAMs 14 Reserved should be cleared 13 NAM
331. ear addressing is required the DRAM should not multiplex addresses on DRAM accesses 0 The DRAM controller multiplexes the external address bus to provide column addresses 1 The DRAM controller does not multiplex the external address bus to provide column addresses M MOTOROLA Chapter 11 Synchronous Asynchronous DRAM Controller Module 11 19 Synchronous Operation Table 11 12 DCR Field Descriptions Synchronous Mode Continued Bits Name Description 12 COC Command on SDRAM clock enable SCKE Implementations that use external multiplexing NAM 1 must support command information to be multiplexed onto the SDRAM address bus 0 functions as a clock enable self refresh is initiated by the DRAM controller through DCR ISJ 1 SCKE drives command information Because SCKE is not a clock enable self refresh cannot be used setting DCR IS Thus external logic must be used if this functionality is desired External multiplexing is also responsible for putting the command information on the proper address bit 11 IS Initiate self refresh command 0 Take no action or issue a SELFX command to exit self refresh 1 If DCR COC 0 the DRAM controller sends SELF command to both SDRAM blocks to put them in low power self refresh state where they remain until IS is cleared at which point the controller sends a SELFX command for the SDRAMs to exit self refresh The refresh counter is suspended whil
332. ecoding for boot ROM before system initialization Its operation differs from other external chip select outputs after system reset After system reset CSO is asserted for every external access No other chip select can be used until the valid bit CSMRO V is set at which point CSO functions as configured and CS 7 1 can be used At reset the port size and automatic acknowledge functions of the global chip select are determined by the logic levels of the inputs on D 7 5 Table 10 4 and Table 10 5list the various reset encodings for the configuration signals multiplexed with D 7 5 Table 10 4 D7 AA Automatic Acknowledge of Boot CSO D7 AA Boot CS0 AA Configuration at Reset 0 Disabled 1 Enable with 15 wait states Provided the required address range is in the chip select address register CSARO CSO can Table 10 5 D 6 5 PS 1 0 Port Size of Boot CSO D 6 5 PS 1 0 Boot CS0 Port Size at Reset 00 32 bit port 01 8 bit port 1x 16 bit port 10 4 MCF5307 User s Manual M woronoLA Chip Select Registers be programmed to continue decoding for a range of addresses after the CSMRO V is set after which the global chip select can be restored only by a system reset 10 4 Chip Select Registers Table 10 6Table 10 6 is the chip select register memory map Reading reserved locations returns zeros Table 10 6 Chip Select Registers
333. ected Master mode is not aware that the bus is busy so initiating a start cycle may corrupt the current bus cycle ultimately causing either the current master or the module to lose arbitration after which bus operation returns to normal 0 The module is disabled but registers can still be accessed 1 The 2 module is enabled This bit must be set before any other I2CR bits have any effect 6 PC interrupt enable 0 module interrupts are disabled but currently pending interrupt condition are not cleared 1 12 module interrupts are enabled An interrupt occurs if I2SR IIF is also set 5 MSTA Master slave mode select bit If the master loses arbitration MSTA is cleared without generating a STOP signal 0 Slave mode Changing MSTA from 1 to 0 generates a STOP and selects slave mode 1 Master mode Changing MSTA from 0 to 1 signals a START on the bus and selects master mode 4 MTX Transmit receive mode select bit Selects the direction of master and slave transfers 0 Receive 1 Transmit When a slave is addressed software should set MTX according to I2SR SRW In master mode MTX should be set according to the type of transfer required Therefore for address cycles MTX is always 1 3 TXAK Transmit acknowledge enable Specifies the value driven onto SDA during acknowledge cycles for both master and slave receivers Note that writing TXAK applies only when the 12 bus is a receiver 0 An ackno
334. ed anywhere in a program IC Divider IC Divider IC Divider IC Divider 0x00 28 0x10 288 0x20 20 0x30 160 0x01 30 0 11 320 0 21 22 0x31 192 0x02 34 0x12 384 0x22 24 0x32 224 0x03 40 0x13 480 0x23 26 0x33 256 0x04 44 0x14 576 0x24 28 0x34 320 0x05 48 0x15 640 0x25 32 0x35 384 0x06 56 0x16 768 0x26 36 0x36 448 0x07 68 0x17 960 0x27 40 0x37 512 0x08 80 0x18 1152 0x28 48 0x38 640 0x09 88 0x19 1280 0x29 56 0x39 768 0x0A 104 1536 Ox2A 64 Ox3A 896 0x0B 128 0x1B 1920 0 2 72 Ox3B 1024 0x0C 144 0 1 2304 0 2 80 Ox3C 1280 0x0D 160 0x1D 2560 0 20 96 Ox3D 1536 OxOE 192 Ox1E 3072 Ox2E 112 Ox3E 1792 OxOF 240 Ox1F 3840 Ox2F 128 Ox3F 2048 M MOTOROLA Chapter 8 Module 8 7 Programming Model 8 5 3 12C Control Register I2CR The I2CR is used to enable the C module and the IC interrupt It also contains bits that govern operation as a slave or a master 7 6 5 4 3 2 1 0 Field IEN IIEN MSTA MTX TXAK RSTA Reset 0000_0000 R W Read Write Address MBAR 0x288 Figure 8 7 12 Control Register I2CR Table 8 4 describes I2CR fields Table 8 4 I2CR Field Descriptions Bits Name Description 7 IEN enable Controls the software reset of the entire C module If the module is enabled in the middle of a byte transfer slave mode ignores the current bus transfer and starts operating when the next start condition is det
335. edge of RSTI for initial MCF5307 configurations listed in Table 18 12 18 34 MCF5307 User s Manual M MOTOROLA Table 18 12 Data Pin Configuration Pin Function D7 Auto Acknowledge Configuration AA CONFIG D 6 5 Port Size Configuration PS CONFIG 1 0 D4 Address Configuration ADDR_CONFIG D4 D 3 2 Frequency of CLKIN FREQ 1 0 D 1 0 Ratio of BCLKO Processor Clock DIVIDE 1 0 Reset Operation See Section 17 5 5 Data Configuration Pins D 7 0 Motorola recommends that the data pins be driven rather than using a weak pull up or pull down resistor Table 17 1 lists the encoding of these pins sampled at reset 18 10 2 Software Watchdog Reset A software watchdog reset is performed if the executing software does not provide the correct write data sequence with the enable control bit set This reset helps prevent runaway software or unterminated bus cycles Figure 18 34 is a functional timing diagram of the software watchdog reset operation showing RSTO and bus signal relationships M MOTOROLA Chapter 18 Bus Operation 18 35 Reset Operation 100K CLKIN a gt 80 CLKIN ee Lock Tine gt CLKIN 30BCLKO M BCLKO 1 2 MODE MU 20BCLKO gt BCLKO 1 3 MODE M L 15BCLKO M BCLKO 1 4 MODE PSTCLK il D 7 0 Nw S S S SS S S S S S S S S S SS S SI SC S SC S
336. ee seeker eia a eo ear cete ete ede 20 1 20 3 DC Electrical 1 20 2 20 4 Clock Timing Specification ienaa e e E EEEE 20 2 20 5 Input AC Timing 20 3 20 6 Output AC Timing 1 20 4 20 7 Reset Timing 20 12 20 8 Debug AC Timing Specification 20 12 20 9 Timer Module AC Timing 0 20 14 20 10 PC Input Timing Specifications between SCL and 20 15 20 11 PC Output Timing Specifications between SCL and SDA 20 15 20 12 UART Module AC Timing 20 16 20 13 General Purpose I O Port AC Timing 20 18 20 14 AC Timing 20 19 20 15 IEEE 1149 1 JTAG AC Timing Specifications 20 20 1 SIM 1 2 Interrupt Controller Registers 1 3 Chip Select Registers 2 4 DRAM Controller Registers 3 5 General Purpose Timer 15 1 4 M MOTOROLA Tables xxix TABLES Table Number Hae Number A 6 UARTO Control Registers ccscc
337. ent system to the debug module 5 5 3 BDM Command Set Table 5 17 summarizes the BDM command set Subsequent paragraphs contain detailed descriptions of each command Issuing a BDM command when the processor is accessing debug module registers using the WDEBUG instruction causes undefined behavior M MOTOROLA Chapter 5 Debug Support 5 19 Background Debug Mode BDM Table 5 17 BDM Command Summary m CPU y Command Command Mnemonic Description State Section Hex Read A D RAREG Read the selected address or data register and Halted 5 5 3 3 1 0x218 A D register RDREG return the results through the serial interface Reg 2 0 Write A D WAREG Write the data operand to the specified address or Halted 5 5 3 3 2 0x208 A D register WDREG data register Reg 2 0 Read READ Read the data at the memory location specified by Steal 5 5 3 3 3 0x1900 byte memory the longword address 0x1940 word location 0x1980 lword Write WRITE Write the operand data to the memory location Steal 5 5 3 3 4 0x1800 byte memory specified by the longword address 0x1840 word location 0x1880 lword Dump DUMP Used with READ to dump large blocks of memory Steal 5 5 3 3 5 0x1D00 byte memory An initial READ is executed to set up the starting 0x1D40 word block address of the block and to retrieve the first result 0x1D80 Iword A DUMP command retrieves subsequent operands Fill memory FIL
338. er 000 CPU Space 001 Interrupt level 1 acknowledge MOTOROLA Chapter 17 Signal Descriptions 17 11 Interrupt Control Signals Table 17 10 TM 2 0 Encodings for TT 11 Interrupt Level Continued TM 2 0 Transfer Modifier 010 Interrupt level 2 acknowledge 011 Interrupt level 3 acknowledge 100 Interrupt level 4 acknowledge 101 Interrupt level 5 acknowledge 110 Interrupt level 6 acknowledge 111 Interrupt level 7 acknowledge 17 3 Interrupt Control Signals The interrupt control signals supply the external interrupt level to the MCF5307 device 17 3 1 Interrupt Request IRQ1 IRQ2 IRQ3 IRQ6 IRQ5 IRQ4 and IRQ7 The IRQ3 IRQS and IRQ7 signals are the default interrupt request signals TRQn However by setting the appropriate bit in the interrupt port assignment register IRQPAR IRQI IRQ3 and IRQ5 can be changed to function as IRQ2 IRQ6 and IRQ4 respectively See Section 9 2 4 Interrupt Port Assignment Register IRQPAR 17 4 Bus Arbitration Signals The bus arbitration signals provide the external bus arbitration control for the MCF5307 17 4 1 Bus Request BR The BR output indicates to an external arbiter that the processor is requesting to be bus master for one or more bus cycles BR is negated when the MCF5307 begins an access to the external bus with no other internal accesses pending BR remains negated until another internal request occurs
339. er PAR esee 6 10 MCF5307 User s Manual M woronoLA Figure Number 6 9 6 10 6 11 6 12 6 13 7 1 7 2 7 3 7 4 7 5 8 1 8 2 8 3 8 4 8 5 8 6 8 7 8 8 8 9 8 10 9 1 9 2 9 3 9 4 9 5 10 1 10 2 10 3 10 4 11 1 11 2 11 3 11 4 11 5 11 6 11 7 11 8 11 9 11 10 11 11 11 12 11 13 11 14 ILLUSTRATIONS Page pus Number Default Bus Master Register MPARK essent 6 11 Round Robin Arbitration PARK 00 6 12 Park on Master Core Priority PARK 01 eene 6 13 Park on DMA Module Priority PARK 10 eene 6 13 Park on Current Master Priority PARK 01 eene 6 14 PEL Module Block Diagram 090 7 1 PLL Control Register seven cusses tere eee ehh ehe e 7 3 CLKIN PCLK PSTCLK and BCLKO Timing eee 7 5 Reset and Initialization Timing eese 7 6 PLL Power Supply Filter Circuit 7 6 Module Block Diagram 8 2 Standard Communication Protocol c sssssssssssessssssessssssessssssessssssessesssessessseesessees 8 3 Repeated START T 8 4 Synchronized Clock trt ere tre n e Ier og dea Een 8 5 Address Register eer Per rr shee Preis 8 6 PC Frequency Divider Register 8 7 Control Register 8 8 PCR Status
340. er can follow two basic two paths one for executing JTAG instructions and the other for manipulating JTAG data based on JTAG instructions The various states of the TAP controller are shown in Figure 19 2 For more detail on each state see the IEEE Standard 1149 1 JTAG document Note that regardless of the TAP controller state test logic reset can be entered if TMS is held high for at least five rising edges of TCK Figure 19 2 shows the JTAG TAP controller state machine M MOTOROLA Chapter 19 IEEE 1149 1 Test Access Port JTAG 19 3 JTAG Register Descriptions Test Logic Reset TLR 0 Value of TMS at rising edge of TCK Run Test Idle RTI Select IR Scan SelR Select DR Scan SeDR Capture IR CalR Capture DR CaDR Shift IR ShIR Shift DR ShDR Exit1 IR E1IR Exit1 DR E1DR Exit2 IR E2IR Exit2 DR E2DR Update IR UpIR Update DR UpDR Figure 19 2 JTAG TAP Controller State Machine 19 4 JTAG Register Descriptions The following sections describe the JTAG registers implemented on the MCF5307 19 4 MCF5307 User s Manual M woronoLA JTAG Register Descriptions 19 4 1 JTAG Instruction Shift Register The MCF5307 IEEE Standard 1149 1 implementation uses a 3 bit instruction shift register IR without parity This register transfers its value to a parallel hold register and applies one of six instructions
341. er of wait states inserted before an internal transfer acknowledge is generated WS 0 inserts zero wait states WS OxF inserts 15 wait states If AA 0 TA must be asserted by the external system regardless of the number of wait states generated In that case the external transfer acknowledge ends the cycle An external TA supersedes the generation of an internal TA 9 Reserved should be cleared 8 AA Auto acknowledge enable Determines the assertion of the internal transfer acknowledge for accesses specified by the chip select address 0 No internal T is asserted Cycle is terminated externally 1 Internal TA is asserted as specified by WS Note that if AA 1 for a corresponding CSn and the external system asserts an external TA before the wait state countdown asserts the internal TA the cycle is terminated Burst cycles increment the address bus between each internal termination 7 6 PS Port size Specifies the width of the data associated with each chip select It determines where data is driven during write cycles and where data is sampled during read cycles See Section 10 3 1 1 8 16 and 32 Bit Port Sizing 00 32 bit port size Valid data sampled and driven on D 31 0 01 8 bit port size Valid data sampled and driven on D 31 24 1x 16 bit port size Valid data sampled and driven on D 31 16 5 BEM Byte enable mode Specifies the byte enable operation Certain SRAMs have byte enables that must be
342. er ra x16 Prescaler Clock 16 Bit x32 Generator Divider Prescaler RxD Rx Buffer BCLKO Figure 14 19 Clocking Source Diagram NOTE If TIN is a clocking source for either the timer or UART the timer module cannot use TIN for timer capture 14 18 MCF5307 User s Manual M woronoLA Operation 14 5 1 2 Calculating Baud Rates The following sections describe how to calculate baud rates 14 5 1 2 1 BCLKO Baud Rates When BCLKO is the UART clocking source it goes through a divide by 32 prescaler and then passes through the 16 bit divider of the concatenated UDUn and UDL registers Using a 45 MHz BCLKO the baud rate calculation is as follows 45MHz Baudrate _ audrate 2 x divider let baud rate 9600 then Divider MHZ 146 decimal 0092 hexadecimal 32 x 9600 therefore UDU 0x00 and UDL 0x92 14 5 1 2 2 External Clock An external source clock TIN can be used as is or divided by 16 Externalclockfrequency Baudrate 16071 14 5 2 Transmitter and Receiver Operating Modes Figure 14 20 is a functional block diagram of the transmitter and receiver showing the command and operating registers which are described generally in the following sections and described in detail in Section 14 3 Register Descriptions M MOTOROLA Chapter 14 UART Modules 14 19 Operation Receiver Holding Register 1
343. er request The request may be internal by setting the START bit or external by asserting DREQ 28 AA Auto align AA and SIZE determine whether the source or destination is auto aligned that is transfers are optimized based on the address and size See Section 12 5 4 2 Auto Alignment 0 Auto align disabled 1 If SSIZE indicates a transfer no smaller than DSIZE source accesses are auto aligned otherwise destination accesses are auto aligned Source alignment takes precedence over destination alignment If auto alignment is enabled the appropriate address register increments regardless of DINC or SINC 27 25 BWC Bandwidth control Indicates the number of bytes in a block transfer When the byte count reaches a multiple of the BWC value the DMA releases the bus For example if BCR24BIT is 0 BWC is 001 512 bytes or value of 0x0200 and BCR is 0x1000 the bus is relinquished after BCR values of 0x2000 0x1E00 0x1C00 0x1A00 0x1800 0x1600 0x1400 0x1200 0x1000 0x0E00 0x0C00 0x0A00 0x0800 0x0600 0x0400 and 0x0200 If BCR24BIT is 0 BWC is 110 and BCR is 33000 the bus is released after 232 bytes because the BCR is at 32768 a multiple of 16384 BCR24BIT 0 24 1 000 DMA has priority It does not negate its request until its transfer completes 001 512 16384 010 1024 32768 011 2048 65536 100 4096 131072 101 8192 262144 110 16384 524288 111 32768 1048576 24 SAA Single address access Determines whether the D
344. erated vector 0x61 Control is Exception then passed to an exception handler that can then process the opcode as required by the system If a ColdFire processor encounters any type of fault during the exception processing of another fault the processor immediately halts execution with the catastrophic fault on fault condition A reset is required to force the processor to exit this halted state 2 52 MCF5307 User s Manual M woronoLA Chapter 3 Hardware Multiply Accumulate MAC Unit This chapter describes the MCF5307 multiply accumulate MAC unit which executes integer multiply multiply accumulate and miscellaneous register instructions The MAC is integrated into the operand execution pipeline OEP 3 1 Overview The MAC unit provides hardware support for a limited set of digital signal processing DSP operations used in embedded code while supporting the integer multiply instructions in the ColdFire microprocessor family The MAC unit provides signal processing capabilities for the MCF5307 in a variety of applications including digital audio and servo control Integrated as an execution unit in the processor s OEP the MAC unit implements a three stage arithmetic pipeline optimized for 16 x 16 multiplies Both 16 and 32 bit input operands are supported by this design in addition to a full set of extensions for signed and unsigned integers plus signed fixed point fractional input operands The MAC unit provides fu
345. erated bus MA channel 0 would gain bus mastership next However if the core requests the bus during this DMA transfer bus mastership returns to the core rather than being granted to DMA channel 1 MCF5307 User s Manual M woronoLA Programming Model Note that the internal DMA has higher priority than the core if the internal DMA has its bandwidth BWC bits set to 000 maximum bandwidth e Park on master core priority PARK 01 The core retains bus mastership as long as it needs it After it negates its internal bus request the core does not have to rearbitrate for the bus unless the DMA module has requested the bus when it is idle The DMA module can be granted bus mastership only when the core is not asserting its bus request See Figure 6 11 Core BR negated Core BR negated DMA module BH negated DMA module BR asserted DMA Module Core BR asserted DMA module BR negated asserted Figure 6 11 Park on Master Core Priority PARK z 01 e Park on master DMA priority PARK 10 The DMA module retains bus mastership as long as it needs it After it negates its internal bus request the DMA module does not have to rearbitrate for the bus unless the core has requested the bus when it is idle The core can be granted bus mastership only when the DMA module is not asserting its bus request See Figure 6 12 DMA module BR asserted BR DMA BR negated Core BR negated asserted Core BR negated DMA Module Core B
346. erface Configuration sees 11 35 DCR 7 11 35 DACR Initialization eerte ttti k S in 11 35 DMR Initializati ni dedere eene depo esig eee pag 11 37 Mode Register Initialization 11 38 Initialization 11 39 Part Ill Peripheral Module Chapter 12 DMA Controller Module iau p 12 1 DMA Module 12 2 DMA Signal Description 12 2 DMA Transfer 12 3 DMA Controller Module Programming Model sese 12 4 Source Address Registers 5 12 6 Destination Address Registers DARO DAR3 12 7 MCF5307 User s Manual M woronoLA Paragraph Number 12 4 3 12 4 4 12 4 5 12 4 6 12 5 12 5 1 12 5 2 12 5 2 1 12 5 2 2 12 5 3 12 5 3 1 12 5 3 2 12 5 4 12 5 4 1 12 5 4 2 12 5 4 3 12 5 5 13 1 13 1 1 13 2 13 3 13 3 1 13 3 2 13 3 3 13 3 4 13 3 5 13 4 13 5 14 1 14 2 14 3 14 3 1 14 3 2 14 3 3 M MOTOROLA CONTENTS Page Me Number Byte Count Registers 12 7 DMA Control Registers DCRO DCR32 eene 12 8 Status Registers DSRO DSR3 seen 12 10 Interrupt Vector Registers 12 11 DMA Control
347. ernal master drives address TS R W TT 1 0 TM 2 0 TIP and SIZ 1 0 as MCF5307 inputs C2 C3 The MCF5307 decodes the external master s address and control signals to identify the proper chip select and byte enable assertion The external master negates TS in C2 C4 On the falling edge of BCLKO the MCF5307 asserts the appropriate chip select for the external master access along with the appropriate byte enables C5 On the rising edge of BCLKO data is driven onto the bus by the device selected by CS On the rising edge the MCF5307 asserts T to indicate the cycle is complete negates on the rising edge of BCLKO On the falling edge the MCF5307 negates the chip select and byte enables and the next cycle can begin C7 The external master negates TIP on the rising edge of BCLKO C8 The external device retains bus mastership and drives the address bus TS R W TT 1 0 TM 2 0 TIP and SIZ 1 0 as inputs to the MCF5307 C9 The MCF5307 decodes the external master s address and control signals to identify the proper chip select and byte enable assertion The external master negates TS The MCF5307 asserts BR on the rising edge of BCLKO signalling that it wants to arbitrate for the bus when the current cycle completes C10 MCF5307 continues to decode the external device s address and control signals to identify the proper chip select and byte enable assertion C11 On the falling edge of BCLKO the MCF5307 asserts th
348. erted Negated Implicit master D4 Negated Negated Asserted Asserted Explicit master 1 Both normal terminations and terminations due to bus errors generate an end of cycle Bus cycles resulting from a burst inhibited transfer are considered part of that original transfer The bus arbitration state diagram can be used for the MCF5307 three wire bus arbitration protocol to approximate the high level behavior of the MCF5307 It is assumed that all TS or AS signals in a system are tied together and each bus device s BD and BR signals are connected individually to the external arbiter The external arbiter must ensure that any external masters will have released the bus after the next rising edge of before asserting BG to the MCF5307 The MCF5307 does not monitor external bus master operation regarding bus arbitration NOTE The MCF5307 can start a transfer on the rising edge of the cycle after BG is asserted The external arbiter should not assert BG to the MCF5307 until the previous external master stops driving the bus or the part may be damaged 18 10 Reset Operation The MCF5307 supports two types of reset Asserting RSTI resets the entire MCF5307 A software watchdog reset resets everything but the internal PLL module M MOTOROLA Chapter 18 Bus Operation 18 33 Reset Operation 18 10 1 Master Reset To perform a master reset an external device asserts RSTI When power is applied to
349. es a fill A write to the line in the fill buffer goes to the external bus without updating or invalidating the buffer Subsequent reads of that written data are serviced by the fill buffer and receive stale information 9 8 DCM Default cache mode Selects the default cache mode and access precision as follows 00 Cacheable write through 01 Cacheable copy back 10 Cache inhibited precise exception model 11 Cache inhibited imprecise exception model Precise and imprecise modes are described in Section 4 9 2 Cache Inhibited Accesses 7 6 Reserved should be cleared 5 DW Default write protect Use of this bit is described in Section 4 9 1 Caching Modes 0 Read and write accesses permitted 1 Write accesses not permitted 4 0 Reserved should be cleared 4 10 2 Access Control Registers ACRO ACR 1 The ACRs Figure 4 9 assign control attributes such as cache mode and write protection to specified memory regions Registers are accessed with the MOVEC instruction with the Rc encodings in Figure 4 9 For overlapping regions ACRO takes priority Data transfers to and from these registers are longword transfers Bits 12 7 4 3 1 and 0 are always read as zeros 4 22 MCF5307 User s Manual M woronoLA Field Reset R W Rc Cache Registers NOTE The SIM MBAR region should be mapped as cache inhibited through an ACR 31 24 23 16 15 14 13 12 4 0 b 4
350. es of an address PSTCLK Pst X DDATA y 0x0 X 0x0 3 0 A 7 4 Y 5 12 X Figure 5 3 Example JMP Instruction Output on PST DDATA PST is driven with 0 5 in the first cycle and 0 9 in the second The 0 5 indicates a taken branch and the marker value 0x9 indicates a 2 byte address Thus the 4 subsequent DDATA nibbles display the lower 2 bytes of address register AO in least to most significant nibble order The PST output after the JMP instruction completes depends on the target instruction The PST can continue with the next instruction before the address has completely displayed on DDATA because of the DDATA FIFO If the FIFO is full and the next instruction has captured values to display on DDATA the pipeline stalls PST 0x0 until space is available in the FIFO 5 4 Programming Model In addition to the existing BDM commands that provide access to the processor s registers and the memory subsystem the debug module contains nine registers to support the required functionality These registers are also accessible from the processor s supervisor M MOTOROLA Chapter 5 Debug Support 5 5 Programming Model programming model by executing the WDEBUG instruction Thus the breakpoint hardware in the debug module can be accessed by the external development system using the debug serial interface or by the operating system running on
351. es operation of the interrupt controller portion of the SIM Includes descriptions of the registers in the interrupt controller memory map and the interrupt priority scheme Chapter 10 Chip Select Module describes the MCF5307 chip select implementation including the operation and programming model which includes the chip select address mask and control registers Chapter 11 Synchronous Asynchronous DRAM Controller Module describes configuration and operation of the synchronous asynchronous DRAM controller component of the SIM It begins with a general description and brief glossary and includes a description of signals involved in DRAM operations The remainder of the chapter is divided between descriptions of asynchronous and synchronous operations MCF5307 User s Manual M woronoLA Organization Part Peripheral Module describes the operation and configuration of the MCF5307 DMA timer UART and parallel port modules and describes how they interface with the system integration unit described in Part II Chapter 12 DMA Controller Module provides an overview of the DMA controller module and describes in detail its signals and registers The latter sections of this chapter describe operations features and supported data transfer modes in detail showing timing diagrams for various operations Chapter 13 Timer Module describes configuration and operation of the two genera
352. es write accesses to the memory block and an address exception occurs Write accesses to a write protected DRAM region are compared in the chip select module for a hit If no hit occurs an external bus cycle is generated If this external bus cycle is not acknowledged an access exception occurs 7 Reserved should be cleared 6 1 AMx Address modifier masks Determine which accesses can occur in a given DRAM block O Allow access type to hit in DRAM 1 Do not allow access type to hit in DRAM Bit Associated Access Type Access Definition CPU space interrupt acknowledge MOVEC instruction or interrupt acknowledge cycle AM Alternate master External or DMA master SC Supervisor code Any supervisor only instruction access SD Supervisor data Any data fetched during the instruction access UC User code Any user instruction UD User data Any user data 0 V Valid Cleared at reset to ensure that the DRAM block is not erroneously decoded 0 Do not decode DRAM accesses 1 Registers controlling the DRAM block are initialized DRAM accesses can be decoded 11 4 4 General Synchronous Operation Guidelines To reduce system logic and to support a variety of SDRAM sizes the DRAM controller provides SDRAM control signals as well as a multiplexed row address and column address to the SDRAM When SDRAM blocks are accessed the DRAM controller can operate in either burst or continuous
353. essor Status Encoding icone terrae iden 5 4 5 3 BDM Breakpoint Registers ee eeesesscseeescsseseeseeececececsscsecsessssseesesaeeneeaseneeaee 5 7 5 4 AATR Field DesctiptiOns unte eter rn tre ien og ine o Een on enge don anat 5 8 5 5 ABLR Field Description inesse nisi asia e i esa isinisi eas 5 9 5 6 ABHR Field 0 1 5 9 5 7 BAAR Field 5 10 5 8 CSR Field Descriptioris c ccscsiesssscsisesconsssesssesdesssvesieesconsssesseesdentsnestestcondsacsseusdesssnesce 5 11 5 9 DBR Field 5 5 13 5 10 DBMR Field Descriptions 5 13 5 11 Access Size and Operand Data 5 13 5 12 PBR Field Descriptions 5 14 5 13 PBMR Field Descriptions 5 14 5 14 TDR Field Descriptions treten eae eee eee aee 5 15 5 15 Receive BDM Packet Field Description 5 19 5 16 Transmit BDM Packet Field Description 5 19 5 17 BDM Command Summary 1 5 20 5 18 BDM Field 5 21 5 19 Control Register Map trente 5 36 5 20 Definition of DRc Encoding Read sese 5 38 5 21 DDATA 3 0 CSR BSTAT Breakpoint Response ener 5 40 5 22 PST DDATA Specification for User Mode
354. essor is stopped waiting for interrupt OxF 1111 Processor is halted 1 Rev B enhancement These encodings are asserted for multiple cycles 17 14 Debug Module JTAG Signals The MCF5307 complies with the IEEE 1149 1a JTAG testing standard JTAG test pins are multiplexed with background debug pins Except for TCK these signals are selected by the value of MTMODO If MTMODO is high JTAG signals are chosen if it is low debug module signals are chosen MTMODO should be changed only while RSTI is asserted 17 14 1 Test Reset Development Serial Clock TRST DSCLK If MTMODO is high TRST is selected TRST asynchronously resets the internal JTAG controller to the test logic reset state causing the JTAG instruction register to choose the bypass instruction When this occurs JTAG logic is benign and does not interfere with normal MCF5307 functionality Although TRST is asynchronous Motorola recommends that it makes asserted to negated transition only while TMS is held high TRST has an internal pull up resistor so if it is not driven low it defaults to a logic level of 1 If TRST is not used it can be tied to ground or if TCK is clocked to Vpp Tying TRST to ground places the JTAG M MOTOROLA Chapter 17 Signal Descriptions 17 21 Debug Module JTAG Signals controller in test logic reset state immediately Tying it to Vpp causes the JTAG controller if TMS is a logic level of 1 to eventually enter test logic reset state
355. ether the DMA channels assert an acknowledge during the entire transfer or only at the final transfer of a DMA transaction New applications should take advantage of the full range of the 24 bit byte counter including the AT bit The 16 bit byte count option BCR24BIT 0 is kept to retain compatibility with older revisions of the MCF5307 M MOTOROLA Appendix A List of Memory Maps A 10 MCF5307 User s Manual M MOTOROLA Glossary of Terms and Abbreviations The glossary contains an alphabetical list of terms phrases and abbreviations used in this book A Architecture A detailed specification of requirements for a processor or computer system It does not specify details of how the processor or computer system must be implemented instead it provides a template for a family of compatible implementations Autovector A method of determining the starting address of the service routine by fetching the value from a lookup table internal to the processor instead of requesting the value from the system B Branch prediction The process of guessing whether a branch will be taken Such predictions can be correct or incorrect the term predicted as it is used here does not imply that the prediction is correct successful Branch resolution The determination of whether a branch is taken or not taken A branch is said to be resolved when the processor can determine which instruction path to take If the branch is resolved as p
356. ew line from CD1 Push modified line to miss memory and update memory and update buffer cache cache read new line from memory supply data to supply data to processor and update cache processor stay in valid state supply data to processor go to valid state write push buffer contents to memory go to valid state Read hit C W I2 Not possible C W V2 Supply data to processor CD2 Supply data to processor stay in valid state stay in modified state Write Read line from CV3 Read new line from CD3 Push modified line to miss memory and update memory and update buffer copy cache cache read new line from memory back write data to cache write data to cache and update cache go to modified state go to modified state write push buffer contents to memory stay in modified state Write WIS Write data to Wv3 Write data to memory WD3 Write data to memory miss memory stay in valid state stay in modified state write stay in invalid state Cache mode changed for through the region corresponding to this line To avoid this state execute a CPUSHL instruction or set CACR CINVA before switching modes Write hit C14 Not possible CV4 Write data to cache CD4 Write data to cache copy go to modified state stay in modified state back Write hit WI4 Not possible WV4 Write data to memory and WD4 Write data to memory and write to cache to cache through stay in valid state go to valid state Cache mo
357. external AVEC access Available for users who use AS as a global chip select for peripherals and do not want to enable them during an AVEC cycle 0 Do not block address strobe 1 Block address strobe from asserting Table 9 6 shows the correlation between AVR AVEC and the external interrupts Note that an AVECn bit is valid only when the corresponding external interrupt request level is enabled in the IRQPAR Table 9 6 Autovector Register Bit Assignments Autovector Interrupt Source Autovector Register Bit Location Vector Offset External interrupt request 1 AVEC1 0x64 External interrupt request 2 AVEC2 0x68 External interrupt request 3 0 6 External interrupt request 4 AVECA 0x70 External interrupt request 5 5 0 74 External interrupt request 6 AVEC6 0x78 External interrupt request 7 AVEC7 0x7C 9 2 3 Interrupt Pending and Mask Registers IPR and IMR The interrupt pending register IPR Figure 9 4 makes visible the interrupt sources that have an interrupt pending The interrupt mask register IMR also shown in Figure 9 4 is used to mask the internal and external interrupt sources NOTE To mask interrupt sources first set the core s status register interrupt mask level to that of the source being masked in the IMR Then the IMR bit can be masked An interrupt is masked by setting and enabled by clearing the corresponding IMR bit When a masked inte
358. finitions Bit Cell Type Pin Cell Pin Type Bit Cell Type Pin Cell Pin Type 101 O Pin D26 221 A8 Vo 102 I Pin D26 VO 222 1 A8 Vo 103 O Pin D27 VO 223 O Pin A7 Vo 104 I Pin D27 224 1 7 Vo 105 O Pin D28 VO 225 O Pin A6 1 0 106 I Pin D28 VO 226 Pin A6 Vo 107 O Pin D29 VO 227 O Pin A5 Vo 108 I Pin D29 VO 228 1 5 109 229 4 Vo 110 I Pin D30 1 0 230 l Pin A4 Vo 111 O Pin D31 VO 231 O Pin A3 1 0 112 I Pin D31 VO 232 Pin A3 1 0 113 O Pin SDA OD 233 O Pin A2 Vo 114 I Pin SDA 234 Pin A2 Vo 115 O Pin SCL OD 235 O Pin A1 Vo 116 I Pin SCL 236 l Pin A1 Vo 117 O Pin BE3 237 O Pin A0 yo 118 O Pin BE2 238 l Pin AO 1 0 119 O Pin BET 19 4 4 JTAG Bypass Register The IEEE Standard 1149 1 compliant bypass register creates a single bit shift register path from TDI to the bypass register to TDO when the BYPASS instruction is selected 19 5 Restrictions Test logic design is static so TCK can be stopped in high or low state with no data loss However system logic uses a different system clock not internally synchronized to TCK Operation mixing 1149 1 test logic with system functional logic that uses both clocks must coordinate and synchronize these clocks externally to the MCF5307 19 10 MCF5307 User s Manual M MOTOROLA Disabling IEEE Standard 1149 1 Operati
359. first N 1 bits after the binary point Given an N bit number aw GN 28N 3 979140 its value is given by the following formula N 2 a5 auo ae i 0 This format can represent numbers in the range 1 lt operand lt 1 2 1 For words and longwords the greatest negative number that can be represented is 1 whose internal representation is 0x8000 and 0x0x8000 0000 respectively The most positive word is Ox7FFF or 1 2715 the most positive longword is Ox7FFF FFFF or 1 2 MAC Instruction Execution Timings Table 3 2 shows standard timings for two operand MAC instructions Table 3 2 Two Operand MAC Instruction Execution Times Effective Address Opcode ea Rn An An An d16 An d8 An Xi SF xxx wl lt xxx gt mac w Ry Rx 1 0 0 mac Ry Rx 3 0 0 msac w Ry Rx 1 0 0 msac Ry Rx 3 0 0 mac w Ry Rx ea Rw 1 1 0 1 1 0 1 1 0 1 1 0 mac Ry Rx ea Rw 3 1 0 3 1 0 3 1 0 3 1 0 msac w Ry Rx ea Rw 1 1 0 1 1 0 1 1 0 1 1 0 msac Ry Rx ea Rw 3 1 0 3 1 0 3 1 0 3 1 0 muls w ea Dx 3 0 0 3 1 0 3 1 0 3 1 0 3 1 0 4 1 0 3 1 0 3 0 0 mulu w ea Dx 3 0 0 3 1 0 3 1 0 3 1 0 3 1 0 4 1 0 3 1 0 3 0 0 muls lt ea gt Dx 5 0 0 5 1 0 5 1 0 5 1 0 5 1 0 mulu I ea Dx
360. for the new entry If none is available the cache controller uses a pseudo round robin replacement algorithm to choose the line to M woronoLA Chapter 4 Local Memory 4 11 Cache Operation be deallocated and replaced First the cache controller looks for an invalid line with way 0 the highest priority If all lines have valid data a 2 bit replacement counter is used to choose the way After a line is allocated the pointer increments to point to the next way Cache lines from ways 0 and 1 can be protected from deallocation by enabling half cache locking If CACR HLCK 1 the replacement pointer is restricted to way 2 or 3 As part of deallocation a valid unmodified cache line is invalidated It is consistent with system memory so memory does not need to be updated To deallocate a modified cache line data is placed in a push buffer for an external cache line push before being invalidated After invalidation the new entry can replace it The old cache line may be written after the new line is read When a cache line is selected to host a new cache entry the following three things happen 1 The new address tag bits A 31 11 are written to the tag 2 The cache line is updated with the new memory data 3 The cache line status changes to a valid state V 1 Read cycles that miss in the cache allocate normally as previously described Write cycles that miss in the cache do not allocate on a cacheable write through region but do
361. for the values in Table 20 10 and Table 20 11 Oe Ow ugh igs P SCL N ZEN SD e OR Q soa X X M Figure 20 15 I2C Input Output Timings 20 8 UART Module AC Timing Specifications Table 20 12 lists specifications for UART module AC timing parameters in Figure 20 16 Table 20 12 UART Module AC Timing Specifications 66 MHz 90 MHz Num Characteristic Units Min Max Min Max U1 RXD valid to BCLKO input setup 7 5 5 5 nS U2 BCLKO to RXD invalid input hold 3 2 nS U3 CTS valid to BCLKO input setup 7 5 5 5 nS U4 BCLKO to CTS invalid input hold 3 2 nS U5 BCLKO to TXD valid output valid 15 11 nS U6 BCLKO to TXD invalid output hold 1 5 1 5 nS U7 BCLKO to RTS valid output valid 15 11 nS U8 BCLKO to RTS invalid output hold 1 5 1 5 nS Figure 20 16 shows UART timing for the values in Table 20 12 20 16 MCF5307 User s Manual M UART Module AC Timing Specifications BCLKO A cn d Ze Figure 20 16 UARTO 1 Module AC Timing UART Mode M woronoLA Chapter 20 Electrical Specifications 20 17 Parallel Port General Purpose I O Timing Specifications 20 9 Parallel Port General Purpose l O Timing Specifications Table 20 13 lists specifications for general purpose I O ti
362. g cache lines to be deallocated is otherwise unchanged If ways 2 and 3 are entirely invalid cacheable accesses are first allocated in way 2 Way 3 is not used until the location in way 2 is occupied Ways 0 and 1 are still updated on write hits D in Figure 4 7 and may be pushed or cleared only explicitly by using specific cache push invalidate instructions However new cache lines cannot be allocated in ways 0 and 1 M Chapter 4 Local Memory 4 19 Cache Operation Invalid V 0 Valid not modified V 1 M 0 mem Valid modified V 1 1 A Ways 0 and 1 are filled B CACR DHLCK is set C When a set in Way 2is D Write hits to ways 0 Ways 2 and 3 are locking ways 0 and 1 occupied the setin way 3 and 1 update cache invalid is used for a cacheable lines access Way 0 Way1 Way2 Way 3 Way 0 Way 1 Way 2 Way 3 Way 0 Way 1 Way 2 Way 3 Way 0 Way 1 Way 2 Way 3 Set 0 Set 127 After reset the cache is After CACR HLCK is While the cache is While the cache is invalidated ways 0 and 1 set subsequent cache locked and after a locked ways 0 and 1 can are then written with data accesses go to ways 2 position in ways is full be updated by write hits that should not be and 3 the set in Way 3 is In this example memory deallocated updated is configured as copyback so updated cache lines are marked modified Figure 4 7 Cache Locking 4 20 MCF5307 User s Manual M woronoLA Cache
363. g Its 20 normal operation Signal low input current Vj 0 8 V 1 lit 0 1 mA Signal high input current 2 0 V i 0 1 Output high voltage lop 6 2 12 mA 2 4 Output low voltage Io 6 mA 12 mA VoL 0 5 Load capacitance all outputs CL 50 pF Capacitance Vin 0 V f 1 MHz Cin 10 pF 1 BKPT TMS DSI TDI DSCLK TRST D 31 0 23 0 PP 15 0 TS TA SIZ 1 0 R W BR BD RSTO AS CS 7 0 BE 3 0 OE PSTCLK PST 3 0 DDATA 3 0 DSO TOUT 1 0 SCL SDA RTS 1 0 TXD 1 0 3 BCLKO RAS 1 0 CAS 3 0 DRAMW SCKE SRAS SCAS Capacitance is periodically sampled rather than 100 tested 20 2 Clock Timing Specifications Table 20 4 lists specifications for the clock timing parameters shown in Figure 20 1 and Figure 20 2 Table 20 4 Clock Timing Specification 66 MHz 90 MHz Num Characteristic Units Min Max Min Max C1 CLKIN cycle time 30 22 nS C2 CLKIN rise time 0 5V to 2 4 V 5 5 nS C3 CLKIN fall time 2 4V to 0 5 V 5 5 nS C4 CLKIN duty cycle at 1 5 V 40 60 40 60 926 C5 PSTCLK cycle time 15 11 nS C6 PSTCLK duty cycle at 1 5 V 40 60 40 60 C7 BCLKO cycle time 30 22 nS C8 BCLKO duty cycle at 1 5 V 45 55 45 55 20 2 MCF5307 User s Manual M woronoLA Input Output AC Timing Specifications Figure 20 1 shows timings for the parameters listed in Table 20 4
364. g SR T The occurrence of an interrupt exception also forces SR M to be cleared and the interrupt priority mask to be set to the level of the current interrupt request 2 The processor determines the exception vector number For all faults except interrupts the processor performs this calculation based on the exception type For interrupts the processor performs an interrupt acknowledge IACK bus cycle to obtain the vector number from a peripheral device The IACK cycle is mapped to a special acknowledge address space with the interrupt level encoded in the address 3 The processor saves the current context by creating an exception stack frame on the system stack ColdFire processors support a single stack pointer in the A7 address register therefore there is no notion of separate supervisor and user stack pointers As a result the exception stack frame is created at a 0O modulo 4 address on the top of the current system stack Additionally the processor uses a simplified M MOTOROLA Chapter 2 ColdFire Core 2 47 Exception Processing Overview fixed length stack frame for all exceptions The exception type determines whether the program counter in the exception stack frame defines the address of the faulting instruction fault or of the next instruction to be executed next The processor acquires the address of the first instruction of the exception handler The exception vector table is aligned on a 1 Mbyte boundary This instruct
365. g enough to be sampled on one rising clock edge However note the following regarding the negation of DREQ Incycle steal mode DCR CS 1 the read write transaction is limited to a single transfer DREQ must be negated appropriately to avoid generating another request For dual address transfers DREQ must be negated before TS is asserted for the write portion as shown in Figure 12 11 clock cycle 7 For single address transfers DREQ must be negated before TS is asserted for the transfer as shown in Figure 12 13 clock cycle 4 In burst mode DCR CS 0 multiple read write transfers can occur on the bus as programmed DREQ need not be negated until DSR DONE is set indicating the block transfer is complete Another transfer cannot be initiated until the DMA registers are reprogrammed Figure 12 12 shows a dual address peripheral to 5DRAM DMA transfer The DMA is not parked on the bus so the diagram shows how the CPU can generate multiple bus cycles during DMA transfers It also shows TMO timing The TT signals indicate whether the CPU 0 or DMA 1 has bus mastership TM2 indicates dual address mode If DCR AT is 1 TM is asserted during the final transfer If DCR AT is 0 TM asserts during all DMA accesses M woronoLA Chapter 12 DMA Controller Module 12 15 DMA Controller Module Functional Description
366. g interrupt acknowledge cycles 17 2 1 2 Address Bus A 31 24 PP 15 8 These multiplexed pins can serve as the most significant byte of the address bus or as the most significant byte of the parallel port Programming the PAR in the system integration module SIM determines the function of each of these eight multiplexed pins These pins are programmable on a bit by bit basis M MOTOROLA Chapter 17 Signal Descriptions 17 7 MCF5307 Bus Signals e A 31 24 Pins are configured as address bits by setting corresponding PAR bits they represent the most significant address bus bits As much as 4 Gbytes of memory are available when all of these pins are programmed as address signals e PP 15 8 Pins are configured as parallel port signals by clearing corresponding PAR bits these represent the most significant parallel port bits 17 2 2 Data Bus D 31 0 The data bus is bidirectional and non multiplexed Data is sampled by the MCF5307 on the rising BCLKO edge The data bus port width wait states and internal termination are initially defined for the boot chip select by D 7 0 during reset The port width for each chip select and DRAM bank are programmable The data bus uses a default configuration if none of the chip selects or DRAM bank match the address decode The default configuration is a 32 bit port with external termination and burst inhibited transfers The data bus can transfer byte word or longword data widths All 32 data
367. gger status bits CSR BSTAT Section Table 5 14 TDR Field Descriptions describes how to handle multiple breakpoint conditions Reset Reset DRc 4 0 31 Second Level Trigger 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Field TRC EBL EDLW EDWL EDWU EDLM EDUM EDUU DI EAI EAR EAL EPC PCI 0000 0000 0000 0000 First Level Trigger 14 18 12 11 10 9 8 7 6 5 4 3 2 1 0 Field LxT EBL EDLW EDWL EDWU EDLM EDUM EDUU DI EAI EAR EAL EPC PCI 0000 0000 0000 0000 R W Write only Accessible in supervisor mode as debug control register 0x07 using the WDEBUG instruction and through the BDM port using the WOMREG command 0x07 Figure 5 12 Trigger Definition Register TDR Table 5 14 describes TDR fields Table 5 14 TDR Field Descriptions Bits Name Description 31 30 TRC Trigger response control Determines how the processor responds to a completed trigger condition The trigger response is always displayed on DDATA 00 Display on DDATA only 01 Processor halt 10 Debug interrupt 11 Reserved 15 14 LxT Level x trigger This is a Rev B function The Level x Trigger bit determines the logic operation for the trigger between the PC condition and the Address range amp Data condition where the inclusion of a Data condition is optional
368. gh mark within two bit times Any characters in the transmitter buffer are sent 3 2 TC Field This field selects a single command 00 NO ACTION TAKEN Causes the transmitter to stay in its current mode if the transmitter is enabled it remains enabled if the transmitter is disabled it remains disabled 01 TRANSMITTER Enables operation of the channel s transmitter USRn TXEMP TxRDY are set If ENABLE the transmitter is already enabled this command has no effect 10 TRANSMITTER Terminates transmitter operation and clears USRn TxEMP TxRDY If a character DISABLE is being sent when the transmitter is disabled transmission completes before the transmitter becomes inactive If the transmitter is already disabled the command has no effect 11 Reserved do not use 14 10 MCF5307 User s Manual M MOTOROLA Register Descriptions Table 14 6 UCRn Field Descriptions Continued Bits Value Command Description 1 0 RC This field selects a single command 00 NO ACTION TAKEN Causes the receiver to stay in its current mode If the receiver is enabled it remains enabled if disabled it remains disabled 01 RECEIVER ENABLE If the UART module is not in multidrop mode UMR1n PM 11 RECEIVER ENABLE enables the channel s receiver and forces it into search for start bit state If the receiver is already enabled this command has no effect 10 RECEIVER DISABLE Disables the receiver immediately Any character
369. gin 2 byte transfer on DDATA OxA Begin 3 byte transfer on DDATA OxB Begin 4 byte transfer on DDATA 0 1100 Exception processing Exceptions that enter emulation mode debug interrupt or optionally trace generate a different encoding as described below Because the 0xC encoding defines multiple cycle mode PST outputs are driven with OxC until exception processing completes OxD 1101 Entry into emulator mode Displayed during emulation mode debug interrupt or optionally trace Because this encoding defines a multiple cycle mode PSToutputs are driven with OxD until exception processing completes OxE 1110 Processor is stopped Appears in multiple cycle format when the MCF5307 executes a STOP instruction The ColdFire processor remains stopped until an interrupt occurs thus PST outputs display OxE until the stopped mode is exited OxF 1111 Processor is halted Because this encoding defines a multiple cycle mode the PST outputs display OxF until the processor is restarted or reset see Section 5 5 1 CPU Halt 5 3 1 Begin Execution of Taken Branch PST 0x5 PST is 0x5 when a taken branch is executed For some opcodes a branch target address may be displayed on DDATA depending on the CSR settings CSR also controls the number of address bytes displayed which is indicated by the PST marker value immediately preceding the DDATA nibble that begins the data output MCF5307 User s Ma
370. gnals Signal 1 0 Description DREQ 1 0 External DMA request DREQ 1 0 can serve as the DMA request inputs or as two parallel port PP 6 5 bits They are programmable individually through the PAR A peripheral device asserts these inputs to request an operand transfer between it and memory DREQ signals are asserted to initiate DMA accesses in the respective channels The system should drive unused DREQ signals to logic high Although each channel has an individual DREQ signal in the MCF5307 only channels 0 and 1 connect to external DREQ pins DREQ signals for channels 2 and 3 are connected to the UARTO and UART1 bus interrupt signals TT 1 0 O Transfer type A DMA access is indicated by the transfer type pins TT 1 0 01 The transfer PP 1 0 modifier TM 2 0 configurations shown below are meaningful only if TT 1 0 01 indicating an external master or DMA access TM 2 0 Multiplexed transfer attribute pins The encodings below are valid when TT 1 0 01 and PP 4 2 internal DMA channels are driving the bus DMA transfer information on TM 2 1 can be provided on every DMA transfer or only on the last transfer by programming DCR AT TM 2 1 Encoding 00 DMA acknowledge information not provided 01 DMA transfer channel 0 10 DMA transfer channel 1 11 Reserved TMO Encoding for DMA as master 01 0 Single address access negated 1 Single address access For TT 1 0 01 the TMO encoding is inde
371. h RAS 1 0 CAS 3 0 DRAMW M NWT Ty ey yt Figure 11 8 Burst Page Mode Write Operation 4 3 3 3 11 3 3 3 Continuous Page Mode Continuous page mode DACRn PM 11 is a type of page mode that balances performance complexity and size In typical page mode implementations sequential addresses are checked for multiple hits ina DRAM block On a hit RAS remains asserted and CAS is asserted with the new column address On a miss RAS must be precharged again before the bus cycle begins Continuous page mode supports page mode operation without requiring an address holding register per memory block and eliminates the delay for a miss to precharge RAS for the upcoming bus cycle Because the internal MCF5307 address bus is pipelined addresses for M MOTOROLA Chapter 11 Synchronous Asynchronous DRAM Controller Module 11 13 Asynchronous Operation the next bus cycle are often available before the current cycle completes The two addresses are compared at the end of the cycle to determine if the next address hits the same page If so RAS remains asserted If not or if no access is pending RAS is precharged before the next bus cycle is active on the external bus As a result a page miss suffers no penalty Single accesses not followed by a hit in the page look like non page mode accesses Figure 11 9
372. hapter 19 IEEE 1149 1 Test Access Port JTAG OVERVIEW e C 19 1 JTAG Signal Descriptions 1 19 2 TAP Controler iieiea e eee eee 19 3 JTAG Register Descriptions 19 4 JTAG Instruction Shift Register 19 5 IDCODE Register rrt ei 19 6 JTAG Boundary Scan Register 19 7 M Contents xvii Paragraph Number 19 4 4 19 5 19 6 19 7 20 1 20 2 20 3 20 4 20 5 20 6 20 7 20 8 20 9 20 10 20 11 xviii CONTENTS Page qe Number JTAG Bypass Register 19 10 R st ictlonsu 19 10 Disabling IEEE Standard 1149 1 Operation sse 19 11 Obtaining the IEEE Standard 1149 1 19 12 Chapter 20 Electrical Specifications General Parameters 20 1 Clock Timing 20 2 Input Output AC Timing 1 20 3 Reset Timing Specifications 20 12 Debug AC Timing 1 5 20 12 Timer Module AC Timing Specifications sese 20 14 PC Input Output Timing Specifications 20 15 UART Module AC Timing Specifications 20 16 Parallel Port General Purpose I O Timing Specifications 20 18 DMA Timing 1 5 20 19 IBEE 1149 1 JTAG AC Timing Specifications
373. he page closes and a precharge is issued 1 Continuous page mode The page stays open and only SCAS needs to be asserted for sequential SDRAM accesses that hit in the same page regardless of whether the access is a burst 1 0 Reserved should be cleared 11 4 3 3 DRAM Controller Mask Registers DMRO DMR1 The DMRz Figure 11 17 include mask bits for the base address and for address attributes They are the same as in asynchronous operation 31 18 17 9 8 7 6 Field BAM WP AM SC SD UC UD V Reset Uninitialized R W R W Addr MBAR 0x10C DMRO 0x114 DMR1 Figure 11 17 DRAM Controller Mask Registers DMRO and DMR1 Table 11 14 describes DMRn fields 11 22 MCF5307 User s Manual M woronoLA Synchronous Operation Table 11 14 DMRO DMR1 Field Descriptions Bits Name Description 31 18 BAM Base address mask Masks the associated DACRn BA Lets the DRAM controller connect to various DRAM sizes Mask bits need not be contiguous see Section 11 5 SDRAM Example 0 The associated address bit is used in decoding the DRAM hit to a memory block 1 The associated address bit is not used in the DRAM hit decode 17 9 Reserved should be cleared 8 WP Write protect Determines whether the associated block of DRAM is write protected 0 Allow write accesses 1 Ignore write accesses The DRAM controller ignor
374. he basic receive packet Figure 5 14 consists of 16 data bits and 1 status bit 16 15 0 S Data Field 15 0 Figure 5 14 Receive BDM Packet Table 5 15 describes receive BDM packet fields Table 5 15 Receive BDM Packet Field Description Bits Name Description 16 S Status Indicates the status of CPU generated messages listed below The not ready response can be ignored unless a memory referencing cycle is in progress Otherwise the debug module can accept a new serial transfer after 32 processor clock periods S Data Message 0 XXxx Valid data transfer 0 OxFFFF Status OK 1 1 1 0 0000 Not ready with response again 0x0001 Error Terminated bus cycle data invalid OxFFFF Illegal command 15 0 Data Data Contains the message to be sent from the debug module to the development system The response message is always a single word with the data field encoded as shown above 5 5 2 2 Transmit Packet Format The basic transmit packet Figure 5 15 consists of 16 data bits and 1 control bit 16 15 0 C D 15 0 Figure 5 15 Transmit BDM Packet Table 5 16 describes transmit BDM packet fields Table 5 16 Transmit BDM Packet Field Description Bits Name Description 16 C Control This bit is reserved Command and data transfers initiated by the development system should clear C 15 0 Data Contains the data to be sent from the developm
375. he cache The following sections describe write through and copyback modes in detail 4 9 1 2 Write Through Mode Write accesses to regions specified as write through are always passed on to the external bus although the cycle can be buffered depending on the state of CACR ESB Writes in write through mode are handled with a no write allocate policy that is writes that miss in the cache are written to the external bus but do not cause the corresponding line in memory to be loaded into the cache Write accesses that hit always write through to memory and update matching cache lines The cache supplies data to data read accesses that hit in the cache read misses cause a new cache line to be loaded into the cache 4 9 1 3 Copyback Mode Copyback regions are typically used for local data structures or stacks to minimize external bus use and reduce write access latency Write accesses to regions specified as copyback that hit in the cache update the cache line and set the corresponding M bit without an external bus access Be sure to flush the cache using the CPUSHL instruction before invalidating the cache in copyback mode Modified cache data is written to memory only if the line is replaced because of a miss or a CPUSHL instruction pushes the line If a byte word longword or line write access misses in the cache the required cache line is read from memory thereby updating the cache When a miss selects a modified cache line for replaceme
376. he product MSAC Ry RxSF to from the accumulator Multiply Accumulate Ry RxSF Rw Multiplies two operands then adds or subtracts the product with Load MSAC Ry to from the accumulator while loading a register with the memory operand Load Accumulator MOV L Ry imm ACC Loads the accumulator with a 32 bit operand Store Accumulator MOV L ACC Rx Writes the contents of the accumulator to a register Load MACSR MOV L Ry imm MACSR Writes a value to the MACSR Store MACSR MOV L MACSR Rx Write the contents of MACSR to a register Store MACSR to MOV L MACSR CCR Write the contents of MACSR to the processor s CCR register Load MASK MOV L Ry imm MASK Writes a value to MASK Store MASK MOV L MASK Rx Writes the contents of MASK to a register 3 1 4 Data Representation The MAC unit supports three basic operand types 3 4 MCF5307 User s Manual M woronoLA 3 2 MAC Instruction Execution Timings Two s complement signed integer In this format an N bit operand represents a number within the range 2N D lt operand lt 20D 1 The binary point is to the right of the least significant bit Two s complement unsigned integer In this format an N bit operand represents a number within the range 0 lt operand lt 2N 1 The binary point is to the right of the least significant bit Two s complement signed fractional In an N bit number the first bit is the sign bit The remaining bits signify the
377. her a source or destination M MOTOROLA Chapter 17 Signal Descriptions 17 17 Serial Module Signals 17 8 1 DMA Request DREQ 1 0 PP 6 5 The DMA request pins DREQ 1 0 PP 6 5 can serve as the DMA request inputs or as two bits of the parallel port as determined by individually programmable bits in the PAR These inputs are asserted by a peripheral device to request an operand transfer between that peripheral and memory by either channel 0 or 1 of the on chip DMA Note that DMA acknowledge indication is displayed on TM 2 0 during DMA transfers of channel 0 and 1 17 9 Serial Module Signals The signals in the following sections are used to transfer serial data between the two UART modules and external peripherals 17 9 1 Transmitter Serial Data Output TxD TxD is held high mark condition when the transmitter is disabled idle or operating in the local loop back mode Data is shifted out least significant bit Isb first on TxD on the falling edge of the clock source 17 9 2 Receiver Serial Data Input RxD Data received on RxD is sampled on the rising edge of the clock source with the lsb received first 17 9 3 Clear to Send CTS This input can generate an interrupt on a change of state 17 9 4 Request to Send RTS This output can be programmed to be negated or asserted automatically by either the receiver or the transmitter When connected to a transmitter s CTS RTS can control serial data flow 17 1
378. hich the data operand is to be written Byte data is sent as a 16 bit word justified in the LSB 16 and 32 bit operands are sent as 16 and 32 bits respectively Result Data Command complete status is indicated by returning OxFFFF with S cleared when the register write is complete A value of 0x0001 with S set is returned if a bus error occurs 5 28 MCF5307 User s Manual M woronoLA Background Debug Mode BDM 5 5 3 3 5 Dump Memory Block DUMP DUMP is used with the READ command to access large blocks of memory An initial READ is executed to set up the starting address of the block and to retrieve the first result If an initial READ is not executed before the first DUMP an illegal command response is returned The DUMP command retrieves subsequent operands The initial address is incremented by the operand size 1 2 or 4 and saved in a temporary register Subsequent DUMP commands use this address perform the memory read increment it by the current operand size and store the updated address in the temporary register NOTE DUMP does not check for a valid address it is a valid command only when preceded by NOP READ or another DUMP command Otherwise an illegal command response is returned NOP can be used for intercommand padding without corrupting the address pointer The size field is examined each time a DUMP command is processed allowing the operand size to be dynamically altered Command Result Formats
379. ibes each internal register and its bit assignment Note that there is no way to prevent a write to a control register during a DMA transfer Table 12 2 shows the mapping of DMA controller registers Note the differences for the byte count registers depending on the value of MPARK BCR2ABIT 12 4 MCF5307 User s Manual M woronoLA DMA Controller Module Programming Model Table 12 2 Memory Map for DMA Controller Module Registers Nun oa 31 24 23 16 15 8 7 0 0 0x300 Source address register 0 SARO p 12 6 0x304 Destination address register 0 DARO p 12 7 0x308 DMA control register 0 DCRO p 12 8 0x30C Byte count register 0 BCR24BIT 0 1 Reserved 0x30C Reserved Byte count register 0 BCR24BIT 1 BCRO p 12 7 0x310 DMA status register 0 Reserved DSRO p 12 10 0x314 DMA interrupt vector Reserved register 0 DIVRO p 12 11 1 0x340 Source address register 1 SAR1 p 12 6 0x344 Destination address register 1 DAR1 p 12 7 0x348 DMA control register 1 DCR1 p 12 8 0x34C Byte count register 1 BCR24BIT 0 Reserved 0 34 Reserved Byte count register 1 BCR24BIT 1 BCR1 p 12 7 0x350 DMA status register 1 Reserved DSR1 p 12 10 0x354 DMA interrupt vector Reserved register 1 DIVR1 p 12 11 2 0x380 Source address register 2 SAR2 p 12 6 0x384 Destination address register 2
380. ible because the PC breakpoint is enabled when interrupt sampling occurs For address and data breakpoints reporting is considered imprecise because several instructions may execute after the triggering address or data is detected As soon as the debug interrupt is recognized the processor aborts execution and initiates exception processing This event is signaled externally by the assertion of a unique PST value PST OxD for multiple cycles The core enters emulator mode when exception processing begins After the standard 8 byte exception stack is created the processor 5 40 MCF5307 User s Manual M woronoLA Real Time Debug Support fetches a unique exception vector 12 from the vector table Execution continues at the instruction address in the vector corresponding to the breakpoint triggered All interrupts are ignored while the processor is in emulator mode The debug interrupt handler can use supervisor instructions to save the necessary context such as the state of all program visible registers into a reserved memory area When debug interrupt operations complete the RTE instruction executes and the processor exits emulator mode After the debug interrupt handler completes execution the external development system can use BDM commands to read the reserved memory locations The generation of another debug interrupt during the first instruction after the RTE exits emulator mode is inhibited This behavior is consistent with the ex
381. ical 16 9 MCF5307 Case Drawing General View eese nennen 16 10 Case Drawitis 9 mmo gesund ve Uer er a RU Sg 16 11 MCF5307 Block Diagram with Signal Interfaces 17 2 Signal Relationship to BCLKO for Non DRAM Access 18 2 Connections for External Memory Port Sizes 18 4 Chip Select Module Output Timing Diagram sese 18 4 Data Transfer State Transition Diagram sees 18 6 Read Cycle Flowchatrt aint t eere te Renova eese eL en Ree tee va 18 7 Basic Read Bus Cycle testae tete 18 8 18 9 Basic Write Bus Cycle s c coscsiesesscosassiesesecesasecesesscesesssosesecosasesecesecesesesedesesetesesecesecess 18 9 Read Cycle with Fast Termination sss 18 10 Write Cycle with Fast Termination seen 18 10 Back to Back Bus Cycles vi ccscccitscivesiscsecscsvessvescestssessecsconsssesseessentsvestestcondsecsieussonssnss 18 11 Line Read Burst 2 1 1 1 External Termination 18 12 Line Read Burst 2 1 1 1 Internal Termination 18 13 Line Read Burst 3 2 2 2 External Termination eene 18 13 Line Read Burst Inhibited Fast External Termination 0 ccccccesssscceeeeeessseeees 18 14 Line Write Burst 2 1 1 1
382. ignals TS and TA AS CSx OE BE BWE Attribute signals R W SIZ TT TM and TIP The address bus write data TS and all attribute signals change on the rising edge of BCLKO Read data is latched into the MCF5307 on the rising edge of BCLKO AS CSx OE and BE BWE change on the falling edge The MCF5307 bus supports byte word and longword operand transfers and allows accesses to 8 16 and 32 bit data ports Transfer parameters such as port size the number of wait states for the external slave being accessed and whether internal transfer termination is enabled can be programmed in the chip select control registers CSCRs and DRAM control registers DACRs For aligned transfers larger than the port size SIZ 1 0 behaves as follows If bursting is used SIZ 1 0 stays at the size of transfer If bursting is inhibited SIZ 1 0 first shows the size of the transfer and then shows the port size Table 18 2 shows encoding for SIZ 1 0 Table 18 2 Bus Cycle Size Encoding SIZ 1 0 Port Size 00 Longword 01 Byte 10 Word 11 Line Figure 18 2 shows the byte lanes that external memory should be connected to and the sequential transfers if a longword is transferred for three port sizes For example an 8 bit memory should be connected to D 31 24 BEO A longword transfer takes four transfers on D 31 24 starting with the MSB and going to the LSB M woronoLA Chapter 18 Bus Operation 18
383. ime with no overlap This adds at least 5 cycles to the execution time of each instruction Instruction folding is disabled Given an average execution latency of 1 6 throughput in non pipeline mode would be 6 6 approximately 25 or less of pipelined performance Regardless of the NPL state a triggered PC breakpoint is always reported before the triggering instruction executes In normal pipeline operation the occurrence of an address and or data breakpoint trigger is imprecise In non pipeline mode triggers are always reported before the next instruction begins execution and trigger reporting can be considered precise An address or data breakpoint should always occur before the next instruction begins execution Therefore the occurrence of the address data breakpoints should be guaranteed 5 IPI Ignore pending interrupts 1 Core ignores any pending interrupt requests signalled while in single instruction step mode 0 Core services any pending interrupt requests that were signalled while in single step mode 4 SSM mode Setting SSM puts the processor in single step mode 0 Normal mode 1 Single step mode The processor halts after execution of each instruction While halted any BDM command can be executed On receipt of the GO command the processor executes the next instruction and halts again This process continues until SSM is cleared 3 0 Reserved should be cleared 5 4 5 Data
384. imer Module Memory Map sse 13 3 13 2 TMR Field Descriptions 13 4 13 3 TERn Field 13 6 13 5 Calculated Time out Values 90 MHz Processor Clock 13 7 14 1 UART Module Programming Model sese 14 3 14 2 UMR In Field 1 14 5 14 3 UMR2n Field 14 6 14 4 USRn Field Descriptions 14 7 14 5 UCSRn Field Descriptions 14 9 14 6 UGRn Held Descriptions sonrie rette E 14 9 14 7 UIPCRz Field Descriptions isseire 14 12 14 8 UACRn Field 14 13 14 9 UISRn UIMRn Field Descriptions 1 14 14 14 10 UIVRz Field Descriptions esee nennen 14 15 14 11 Field Descriptions seseseeeeeneenennennennennenne nennen emen 14 15 14 12 UOP1 UOPO Field Descriptions eseeseeeeeeneenennennennene EE nennen 14 16 14 13 UART Module Signals irte ire ette tert euer tr ater eer leche ether 14 17 14 14 UART Module Initialization Sequence sese 14 29 15 1 Parallel Port Pin 15 2 15 2 PADDR Field Description 15 2 15 3 Relationship between PADAT Register and Parallel Port Pin PP
385. in CS7 33 I Pin CLKIN 153 O Pin CS6 9 34 10 Ctl RSTO enable 154 O Pin CS5 35 O Pin RSTO 155 54 36 I Pin RSTO 156 CS3 37 O Pin BCLKO 157 O Pin CS2 38 I Pin EDGESEL 158 O Pin CS1 39 TXDO 159 O Pin cso 9 40 I Pin RXDO 160 O Pin OE 9 41 O Pin RTSO 161 O Pin 171 yo 42 I Pin CTSO 162 171 yo 43 O Pin TXD1 163 O Pin SIZO yo 44 I Pin RXD1 164 120 yo 45 O Pin RTS1 165 IO Ctl PP15 enable 46 I Pin CTS1 166 15 yo 47 I Pin HIZ 167 O Pin PP15 yo 48 10 Ctl Data enable 168 IO Ctl PP14 enable 49 O Pin DO VO 169 I Pin PP14 yo 50 I Pin DO VO 170 O Pin PP14 yo 51 O Pin D1 VO 171 IO Ctl PP13 enable 52 I Pin D1 VO 172 I Pin PP13 yo 53 O Pin D2 VO 173 O Pin PP13 yo 54 I Pin D2 VO 174 IO Ctl PP12 enable 55 O Pin D3 VO 175 I Pin PP12 VO 56 I Pin D3 VO 176 O Pin PP12 yo 57 O Pin D4 VO 177 PP11 enable 58 I Pin D4 VO 178 Pin PP11 VO 59 O Pin D5 VO 179 O Pin PP11 yo 60 I Pin D5 VO 180 IO Ctl PP10 enable 61 O Pin D6 VO 181 I Pin PP10 yo 62 I Pin D6 VO 182 O Pin PP10 yo 63 O Pin D7 VO 183 IO Ctl PP9 enable 64 I Pin D7 VO 184 I Pin PP9 yo 19 8 MCF5307 User s Manual M woronoLA JTAG Register Descriptions Table 19 4 Boundary Scan Bit Definitions Bit Cell Type Pin Cell Pin Type Bit Cell Type Pin Cel
386. in ordering e ColdFire Programmers Reference Manual R1 0 MCF5200PRM AD e User s manuals These books provide details about individual ColdFire implementations and are intended to be used in conjunction with The ColdFire Programmers Reference Manual These include the following ColdFire MCF5102 User s Manual MCF5102UM AD ColdFire MCF5202 User s Manual MCF5202UM AD ColdFire MCF5204 User s Manual MCF5204UM AD ColdFire MCF5206 User s Manual MCF5206EUM AD ColdFire MCF5206E User s Manual MCF5206EUM AD e ColdFire Programmers Reference Manual R1 0 MCF5200PRM AD e Using Microprocessors and Microcomputers The Motorola Family William C Wray Ross Bannatyne Joseph D Greenfield Additional literature on ColdFire implementations is being released as new processors become available For a current list of ColdFire documentation refer to the World Wide Web at http www motorola com ColdFire Conventions This document uses the following notational conventions MNEMONICS In text instruction mnemonics are shown in uppercase mnemonics In code and tables instruction mnemonics are shown in lowercase xxxiv MCF5307 User s Manual M MOTOROLA italics 0 0 ObO REG FIELD nibble byte word longword X n A amp Acronyms and Abbreviations Italics indicate variable command parameters Book titles in text are set in italics Prefix to denote hexadecimal number Prefix to denote binary nu
387. indexed addressing mode lt lt 1n gt gt for MAC operations M MOTOROLA Chapter 2 ColdFire Core 2 35 Instruction Set Summary Table 2 6 Notational Conventions Continued Instruction Operand Syntax Operations Arithmetic addition or postincrement indicator Arithmetic subtraction or predecrement indicator Arithmetic multiplication Arithmetic division d Invert operand is logically complemented amp Logical AND Logical OR Logical exclusive OR Shift left example DO 3 is shift DO left 3 bits gt gt Shift right example DO gt gt 3 is shift DO right 3 bits gt Source operand is moved to destination operand lt gt Two operands are exchanged sign extended All bits of the upper portion are made equal to the high order bit of the lower portion If condition Test the condition If the condition is true the operations in the then clause are performed If the then condition is false and the optional else clause is present the operations in the else claue are operations performed If the condition is false and the else clause is omitted the instruction performs no else operation Refer to the Bcc instruction description as an example operations Subfields and Qualifiers Optional operation Identifies an indirect address dn Displacement value n bits wide example dig is a 1
388. ine AG The memory operand is fetched while any register operand is simultaneously fetched OC The instruction is executed EX For register to memory operations the stage functions DS OC AG EX are effectively performed simultaneously allowing single cycle execution For read modify write instructions the pipeline effectively combines a memory to register operation with a store operation 2 1 2 2 1 Illegal Opcode Handling To aid in conversion from M68000 code every 16 bit operation word is decoded to ensure that each instruction is valid If the processor attempts execution of an illegal or unsupported instruction an illegal instruction exception vector 4 is taken 2 1 2 2 2 Hardware Multiply Accumulate MAC Unit The MAC is an optional unit in Version 3 that provides hardware support for a limited set of digital signal processing DSP operations used in embedded code while supporting the integer multiply instructions in the ColdFire microprocessor family The MAC features a three stage execution pipeline optimized for 16 x 16 multiplies It is tightly coupled to the OEP which can issue a 16 x 16 multiply with a 32 bit accumulation plus fetch a 32 bit operand in a single cycle A 32 x 32 multiply with a 32 bit accumulation requires three cycles before the next instruction can be issued 2 24 MCF5307 User s Manual M Features and Enhancements Figure 2 2 shows basic functionality of the MAC A fu
389. inputs Note that for misaligned transfers SIZ 1 0 indicate the size of each transfer For example if a longword access occurs at a misaligned offset of 0 1 a byte is transferred first SIZ 1 0 17 8 MCF5307 User s Manual M woronoLA MCF5307 Bus Signals 01 a word is next transferred at offset 0x2 SIZ 1 0 2 10 then the final byte is transferred at offset 0 4 SIZ 1 0 01 For aligned transfers larger than the port size SIZ 1 0 behaves as follows If bursting is used SIZ 1 0 stays at the size of transfer If bursting is inhibited SIZ 1 0 first shows the size of the transfer and then shows the port size Table 17 4 Bus Cycle Size Encoding SIZ 1 0 Port Size 00 Longword 01 Byte 10 Word 11 Line For burst inhibited transfers SIZ 1 0 changes with each TS assertion to reflect the next transfer size For transfers to port sizes smaller than the transfer size SIZ 1 0 indicates the size of the entire transfer on the first access and the size of the current port transfer on subsequent transfers For example for a longword write to an 8 bit port SIZ 1 0 00 for the first byte transfer and 01 for the next three 17 2 5 Transfer Start TS The MCF5307 asserts TS during the first clock cycle when address and attributes TM TT TIP R W and SIZ are valid TS is negated in the following clock cycle When the MCF5307 is not the bus master TS is an input 17 2 6 Address Stro
390. int address The 32 bit address to be compared with the PC as a breakpoint trigger Figure 5 11 shows PBMR 31 0 Field Mask Reset R W Write PBMR is accessible in supervisor mode as debug control register 0x09 using the WDEBUG instruction and via the BDM port using the wdmreg command DRc 4 0 0x09 Figure 5 11 Program Counter Breakpoint Mask Register PBMR Table 5 13 describes PBMR fields Table 5 13 PBMR Field Descriptions Bits Name Description 31 0 Mask PC breakpoint mask A zero in a bit position causes the corresponding PBR bit to be compared to the appropriate PC bit Set PBMR bits cause PBR bits to be ignored 5 4 7 Trigger Definition Register TDR The TDR shown in Table 5 12 configures the operation of the hardware breakpoint logic that corresponds with the ABHR ABLR AATR PBR PBMR and DBR DBMR registers within the debug module The TDR controls the actions taken under the defined conditions Breakpoint logic may be configured as a one or two level trigger TDR 31 16 define the second level trigger and bits 15 0 define the first level trigger 5 14 MCF5307 User s Manual M woronoLA Programming Model NOTE The debug module has no hardware interlocks so to prevent spurious breakpoint triggers while the breakpoint registers are being loaded disable TDR by clearing TDR 29 13 before defining triggers A write to TDR clears the CSR tri
391. internal pull ups enabled Figure 19 5 shows pin values recommended for disabling JTAG in debug mode TDI DSI Debug Interface gt TMS BKPT TRST DSCLK TCK Note MTMODO low prohibits JTAG Figure 19 5 Disabling JTAG in Debug Mode M Chapter 19 IEEE 1149 1 Test Access Port JTAG 19 11 Obtaining the IEEE Standard 1149 1 19 7 Obtaining the IEEE Standard 1149 1 The IEEE Standard 1149 1 JTAG specification is a copyrighted document and must be obtained directly from the IEEE IEEE Standards Department 445 Hoes Lane P O Box 1331 Piscataway NJ 08855 1331 USA http stdsbbs ieee org FAX 908 98 1 9667 Information 908 981 0060 or 1 800 678 4333 19 12 MCF5307 User s Manual M woronoLA Chapter 20 Electrical Specifications This chapter describes the AC and DC electrical specifications and thermal characteristics for the MCF5307 Note that this information was correct at the time this book was published As process technologies improve there is a likelihood that this information may change To confirm that this is the latest information see Motorola s ColdFire webpage http www motorola com coldfire 20 1 General Parameters Table 20 1 lists maximum and minimum ratings for supply and operating voltages and storage temperature Operating outside of these ranges may cause erratic behavior or damage to the processor Table 20 1 Absolute Maximum Ratings
392. ion address is obtained by fetching a value from the table at the address defined in the vector base register The index into the exception table is calculated as 4 x vector number When the index value is generated the vector table contents determine the address of the first instruction of the desired handler After the fetch of the first opcode of the handler is initiated exception processing terminates and normal instruction processing continues in the handler ColdFire processors support a 1024 byte vector table aligned on any 1 Mbyte address boundary see Table 2 18 The table contains 256 exception vectors where the first 64 are defined by Motorola the remaining 192 are user defined interrupt vectors Table 2 18 Exception Vector Assignments Vector Numbers Vector Offset Hex Stacked Program Counter 1 Assignment 0 000 Initial stack pointer 1 004 m Initial program counter 2 008 Fault Access error 3 00C Fault Address error 4 010 Fault Illegal instruction 5 014 Fault Divide by zero 6 7 018 01C Reserved 8 020 Fault Privilege violation 9 024 Next Trace 10 028 Fault Unimplemented line a opcode 11 02C Fault Unimplemented line f opcode 12 030 Next Debug interrupt 13 034 Reserved 14 038 Fault Format error 15 03C Next Uninitialized interrupt 16 23 040 05C Reserved 24 060 Next Spurious interrupt 25 31 064 07C Next Level 1 7 autovectored inter
393. ion Description Access Error Access errors are reported only in conjunction with an attempted store to write protected memory Thus access errors associated with instruction fetch or operand read accesses are not possible Address Caused by an attempted execution transferring control to an odd instruction address that is if bit O of Error the target address is set an attempted use of a word sized index register Xi w or a scale factor of 80n an indexed effective addressing mode or attempted execution of an instruction with a full format indexed addressing mode Illegal On Version 2 ColdFire implementations only some illegal opcodes were decoded and generated an Instruction illegal instruction exception The Version 3 processor decodes the full 16 bit opcode and generates this exception if execution of an unsupported instruction is attempted Additionally attempting to execute an illegal line A or line F opcode generates unique exception types vectors 10 and 11 respectively ColdFire processors do not provide illegal instruction detection on extension words of any instruction including MOVEC Attempting to execute an instruction with an illegal extension word causes undefined results Divide by Attempted division by zero causes an exception vector 5 offset 0x014 except when the PC points Zero to the faulting instruction DIVU DIVS REMU REMS Privilege Caused by attempted execution of a supervisor mode instruction
394. ion Operand Syntax Opcode Wildcard cc Logical condition example NE for not equal Register Specifications An Any address register n example A3 is address register 3 Source and destination address registers respectively Dn Any data register n example D5 is data register 5 Dy Dx Source and destination data registers respectively Rc Any control register example VBR is the vector base register Rm MAC registers ACC MAC MASK Rn Any address or data register Rw Destination register w used for MAC instructions only Ry Rx Any source and destination registers respectively Xi index register i can be an address or data register Ai Di Register Names ACC MAC accumulator register CCR Condition code register lower byte of SR MACSR MAC status register MASK MAC mask register PC Program counter SR Status register Port Name PSTDDATA Processor status debug data port Miscellaneous Operands lt data gt Immediate data following the 16 bit operation word of the instruction lt ea gt Effective address lt ea gt y lt ea gt x Source and destination effective addresses respectively label Assembly language program label list List of registers for MOVEM instruction example 03 00 shift Shift operation shift left lt lt shift right gt gt size Operand data size byte B word W longword L bc Both instruction and data caches dc Data cache M MOTOROLA AboutThis Book Terminology and Not
395. is being accessed Hits are passed to the control logic along with characteristics of the bus cycle to be generated Page hit logic Determines if the next DRAM access is in the same DRAM page as the previous one This information is passed on to the control logic Address multiplexing Multiplexes addresses to allow column and row addresses to share pins This allows glueless interface to DRAMs 11 2 DRAM Controller Operation The DRAM controller mode is programmed through DCR SO Asynchronous mode SO 0 includes support for page mode and EDO DRAMs Synchronous mode is designed to work with industry standard SDRAMs These modes act very differently from one another especially regarding the use of DRAM registers and pins Memory blocks cannot operate in different modes both are either synchronous or asynchronous 11 2 1 DRAM Controller Registers The DRAM controller registers memory map Table 11 1 is the same regardless of whether asynchronous or synchronous DRAM is used although bit configurations may vary Table 11 1 DRAM Controller Registers 31 24 23 16 15 8 7 0 0 100 DRAM control register DCR p 11 4 Reserved 0x104 Reserved 0x108 DRAM address and control register 0 DACRO p 11 5 0x10C DRAM mask register block 0 DMRO p 11 7 0x110 DRAM address and control register 1 DACR1 11 5 0x114 DRAM mask register block 1 DMR1 p 11 7 NOTE External
396. is complicated by any change in flow especially when branch target address calculation is based on the contents of a program visible register variant addressing DDATA outputs can be configured to display the target address of such instructions in sequential nibble increments across multiple processor clock cycles as described in Section 5 3 1 Begin Execution of Taken Branch PST 0 5 Two 32 bit storage elements form a FIFO buffer connecting the processor s high speed local bus to the external development system through PST 3 0 and DDATA 3 0 The buffer captures branch target addresses and certain data values for eventual display on the DDATA port one nibble at a time starting with the Isb Execution speed is affected only when both storage elements contain valid data to be dumped to the DDATA port The core stalls until one FIFO entry is available Table 5 2 shows the encoding of these signals M MOTOROLA Chapter 5 Debug Support 5 3 Real Time Trace Support Table 5 2 Processor Status Encoding PST 3 0 Hex Binary Definition 0x0 0000 Continue execution Many instructions execute in one processor cycle If an instruction requires more clock cycles subsequent clock cycles are indicated by driving PST outputs with this encoding 0 1 0001 Begin execution of one instruction For most instructions this encoding signals the first clock cycle of an instruction s execution Certain change of flow
397. ise the following occurs Ifthe address and attributes do not match in CSCR or DACR the MCF5307 runs an external burst inhibited bus cycle with a default of external termination on a 32 bit port e fan address and attribute match in multiple CSCRs the matching chip select signals are driven however the MCF5307 runs an external burst inhibited bus cycle with external termination on a 32 bit port e fanaddress and attribute match both DACRs or a DACR and a CSCR the operation is undefined 18 4 MCF5307 User s Manual M woronoLA Data Transfer Operation Table 18 3 shows the type of access as a function of match in the CSCRs and DACRs Table 18 3 Accesses by Matches in CSCRs and DACRs Number of CSCR Matches Number of DACR Matches Type of Access 0 0 External 1 0 Defined by CSCRs Multiple 0 External burst inhibited 32 bit 0 1 Defined by DACRs 1 1 Undefined Multiple 1 Undefined 0 Multiple Undefined 1 Multiple Undefined Multiple Multiple Undefined Basic bus operations occur in three clocks as follows 1 2 During the first clock the address attributes and TS are driven AS is asserted at the falling edge of the clock to indicate that address and attributes are valid and stable Data and TA are sampled during the second clock of a bus read cycle During a read the external device provides data and is sampled at the rising edge at the end of the second bus cloc
398. isting logic involving trace mode where the first instruction executes before another trace exception is generated Thus all hardware breakpoints are disabled until the first instruction after the RTE completes execution regardless of the programmed trigger response 5 6 1 1 Emulator Mode Emulator mode is used to facilitate non intrusive emulator functionality This mode can be entered in three different ways Setting CSR EMU forces the processor into emulator mode EMU is examined only if RSTI is negated and the processor begins reset exception processing It can be set while the processor is halted before reset exception processing begins See Section 5 5 1 CPU Halt A debug interrupt always puts the processor in emulation mode when debug interrupt exception processing begins Setting CSR TRC forces the processor into emulation mode when trace exception processing begins While operating in emulation mode the processor exhibits the following properties All interrupts are ignored including level 7 interrupts If CSR MAP 1 all caching of memory and the SRAM module are disabled All memory accesses are forced into a specially mapped address space signaled by 0x2 TM 0 5 or 0 6 This includes stack frame writes and the vector fetch for the exception that forced entry into this mode The RTE instruction exits emulation mode The processor status output port provides a unique encoding for emulator mode entry
399. it counters 1 DMA BCRs function as 24 bit counters 6 2 10 1 1 Arbitration for Internally Generated Transfers MPARK PARK MPARK PARK prioritizes internal transfers which can be initiated by the core and the on chip DMA module which contains all four DMA channels Priority among the four DMA channels in the module is determined by the BWC bits in their respective DMA control registers see Chapter 12 DMA Controller Module The four arbitration schemes for internally generated transfers are described as follows 6 12 Round robin scheme PARK 00 Figure 6 10 shows round robin arbitration between the core and DMA module Bus mastership alternates between the core and DMA module The DMA Internal Bus Mastership Alternates between Core and DMA Module DMA MODULE CORE Channel 0 5th Channel 1 3rd ath Channel 2 2nd Channel 3 1st Figure 6 10 Round Robin Arbitration PARK 00 module presents only the highest priority DMA request and bus mastership alternates between the core and DMA channel as long as both are requesting Operation bus mastership Section 12 5 4 1 External Request and Acknowledge includes a timing diagram showing a lower priority DMA transfer When the processor is initialized the core has first priority If DMA channels 0 and 1 both set transfer D to BWC 010 assert an internal bus request during a core gen
400. itter is disabled after transmission completes setting this bit automatically clears UOP RTS one bit time after any characters in the channel transmitter shift and holding registers are completely sent including the programmed number of stop bits 4 TxCTS Transmitter clear to send If both and TxRTS are enabled TxCTS controls the operation of the transmitter 0 CTS has no effect on the transmitter 1 Enables clear to send operation The transmitter checks the state of CTS each time it is ready to send a character If CTS is asserted the character is sent if it is negated the channel TxD remains in the high state and transmission is delayed until CTS is asserted Changes in CTS as a character is being sent do not affect its transmission 14 6 MCF5307 User s Manual M woronoLA Register Descriptions Table 14 3 UMR2n Field Descriptions Continued Bits Name Description 3 0 SB Stop bit length control Selects the length of the stop bit appended to the transmitted character Stop bit lengths of 9 16th to 2 bits are programmable for 6 8 bit characters Lengths of 1 1 16th to 2 bits are programmable for 5 bit characters In all cases the receiver checks only for a high condition at the center of the first stop bit position that is one bit time after the last data bit or after the parity bit if parity is enabled If an external 1x clock is used for the transmitter clearing bit 3 selects one st
401. izing for associated accesses 00 32 bit port 01 8 bit port 1x 16 bit port 3 2 PM Page mode Configures page mode operation for the memory block 00 No page mode 01 Burst page mode page mode for bursts only 10 Reserved 11 Continuous page mode 1 0 Reserved should be cleared 11 3 2 3 DRAM Controller Mask Registers DMRO DMR1 The DRAM controller mask registers DMRO and DMR1 shown in Figure 11 4 include mask bits for the base address and for address attributes 31 18 17 98 7 6 5 4 3 2 1 0 Field BAM WP C I AM SC SD UC UD V Reset Uninitialized R W R W Addr MBAR 0x10C DMRO 0x114 DMR1 Figure 11 4 DRAM Controller Mask Registers DMRO and DMR1 Table 11 5 describes DMRn fields Table 11 5 DMRO DMR1 Field Descriptions Bits Name Description 31 18 BAM Base address mask Masks the associated DACRn BA Lets the DRAM controller connect to various DRAM sizes Mask bits need not be contiguous see Section 11 5 SDRAM Example 0 The associated address bit is used in decoding the DRAM hit to a memory block 1 The associated address bit is not used in the DRAM hit decode 17 9 Reserved should be cleared 8 WP Write protect Determines whether the associated block of DRAM is write protected 0 Allow write accesses 1 Ignore write accesses The DRAM controller ignores write accesses to th
402. k This data is concurrent with TA which is also sampled at the rising clock edge During a write the MCF5307 drives data from the rising clock edge at the end of the first clock to the rising clock edge at the end of the bus cycle Wait states can be added between the first and second clocks by delaying the assertion of TA TA can be configured to be generated internally through DACRs and CSCRs If TA is not generated internally the system must provide it externally The last clock of the bus cycle uses what would be an idle clock between cycles to provide hold time for address attributes and write data Figure 18 6 and Figure 18 8 show the basic read and write operations 18 4 2 Data Transfer Cycle States The data transfer operation in the MCF5307 is controlled by an on chip state machine Each bus clock cycle is divided into two states Even states occur when BCLKO is high and odd states occur when BCLKO is low The state transition diagram for basic and fast termination read and write cycles is shown in Figure 18 4 M woronoLA Chapter 18 Bus Operation 18 5 Data Transfer Operation Next Cycle Basic Read Write Fast Termination States Figure 18 4 Data Transfer State Transition Diagram Table 18 4 describes the states as they appear in subsequent timing diagrams Note that the TT 1 0 TM 2 0 and TIP functions are chosen in the PAR as described in Section 15 1 1 Pin Assignment Register
403. kpoint status Section 17 14 Debug Module JTAG Signals 17 21 Test clock TCK Clock signal for IEEE 1149 1 JTAG Low 17 23 Test reset TRST DSCLK Asynchronous reset for JTAG Up 17 21 Development serial debug module clock input clock Test mode select TMS BKPT TMS JTAG hardware breakpoint Up 17 22 Breakpoint debug Test data input TDI DSI Multiplexed serial input for the JTAG Up 17 22 Development serial or background debug module input Test data output TDO DSO Multiplexed serial output for the Driven 17 22 Development serial JTAG or background debug module output 1 If there is no arbiter BG should be tied low otherwise it should be negated These data pins are sampled at reset for configuration Table 17 2 lists signals in alphabetical order by abbreviated name Table 17 2 MCF507 Alphabetical Signal Index Abbreviation Signal Name Function VO Page AA CONFIG Auto acknowledge configuration Clock reset 17 14 ADDR CONFIG Address configuration Clock reset 17 14 AS Address strobe Bus VO 17 9 A 31 0 Address Bus VO 17 7 M MOTOROLA Chapter 17 Signal Descriptions 17 5 Overview Table 17 2 MCF507 Alphabetical Signal Index Continued Abbreviation Signal Name Function VO Page BCLKO Bus clock out Clock reset 17 13 BD Bus driven Bus arbitration O 17 13 BE 3 0 BWE 3 0 Byte
404. l lt ea gt Dx 1 0 0 1 0 0 asr l lt ea gt Dx 1 0 0 1 0 0 bchg Dy lt ea gt 2 0 0 5 1 1 5 1 1 5 1 1 5 1 1 6 1 1 5 1 1 bchg imm lt ea gt 2 0 0 5 1 1 5 1 1 5 1 1 5 1 1 belr Dy lt ea gt 2 0 0 5 1 1 5 1 1 5 1 1 5 1 1 e 1 1 5 1 1 belr imm lt ea gt 2 0 0 5 1 1 5 1 1 5 1 1 5 1 1 bset Dy lt ea gt 2 0 0 5 1 1 5 1 1 5 1 1 5 1 1 6 1 1 5 1 1 bset imm lt ea gt 2 0 0 5 1 1 5 1 1 5 1 1 5 1 1 btst Dy lt ea gt 1 0 0 4 1 0 4 1 0 4 1 0 4 1 0 5 1 0 4 1 0 btst imm lt ea gt 1 0 0 4 1 0 4 1 0 4 1 0 4 1 0 emp l ea Rx 1 0 0 4 1 0 4 1 0 4 1 0 4 1 0 5 1 0 4 1 0 1 0 0 cmpi l imm Dx 1 0 0 divs w ea Dx 20 0 0 23 1 0 23 1 0 23 1 0 23 1 0 24 1 0 23 1 0 20 0 0 divu w ea Dx 20 0 0 23 1 0 23 1 0 23 1 0 23 1 0 24 1 0 23 1 0 20 0 0 divs lt ea gt Dx 35 0 0 35 1 0 35 1 0 35 1 0 35 1 0 divu l ea Dx 35 0 0 35 1 0 35 1 0 35 1 0 35 1 0 eor l Dy lt ea gt 1 0 0 4 1 1 4 1 1 4 1 1 4 1 1 5 1 1 4 1 1 eori l imm Dx 1 0 0 lea ea Ax 1 0 0 1 0 0 2 0 0 1 0 0 151 1 ea Dx 1 0 0 1 0 0 Isr lt ea gt Dx 1 0 0 1 0 0 mac w Ry Rx 1 0 0 mac Ry Rx 3 0 0 msac w Ry Rx 1 0 0 msac Ry Rx 3 0
405. l Pin Type 65 O Pin D8 185 9 Vo 66 I Pin D8 VO 186 10 Ctl PP8 enable 67 O Pin 09 VO 187 1 8 Vo 68 I Pin D9 188 8 1 0 69 O Pin D10 yo 189 TS R W SIZ enable 70 I Pin D10 VO 190 IO Ctl Address enable 71 O Pin D11 VO 191 O Pin A23 yo 72 I Pin D11 VO 192 Pin A23 1 0 73 O Pin D12 VO 193 O Pin A22 Vo 74 I Pin D12 194 l Pin A22 Vo 75 O Pin D13 195 21 Vo 76 I Pin D13 VO 196 1 21 Vo 77 O Pin D14 VO 197 O Pin A20 1 0 78 I Pin D14 VO 198 Pin A20 1 0 79 O Pin D15 VO 199 O Pin A19 yo 80 I Pin D15 200 1 19 Vo 81 O Pin D16 VO 201 O Pin A18 Vo 82 I Pin D16 VO 202 1 18 Vo 83 O Pin D17 203 17 Vo 84 I Pin D17 VO 204 1 17 Vo 85 O Pin D18 VO 205 O Pin A16 Vo 86 I Pin D18 VO 206 1 A16 Vo 87 O Pin D19 VO 207 O Pin A15 Vo 88 I Pin D19 VO 208 1 15 Vo 89 O Pin D20 VO 209 O Pin A14 Vo 90 I Pin D20 VO 210 Pin A14 Vo 91 O Pin 021 VO 211 O Pin A13 Vo 92 I Pin D21 212 1 A13 Vo 93 O Pin D22 VO 213 O Pin A12 Vo 94 I Pin D22 VO 214 1 12 Vo 95 O Pin D23 215 11 Vo 96 I Pin D23 VO 216 I Pin A11 Vo 97 O Pin D24 VO 217 O Pin A10 Vo 98 I Pin D24 VO 218 1 A10 Vo 99 O Pin D25 VO 219 O Pin AQ Vo 100 I Pin D25 VO 220 1 9 Vo M MOTOROLA Chapter 19 IEEE 1149 1 Test Access Port JTAG 19 9 Restrictions Table 19 4 Boundary Scan Bit De
406. l instruction that is the instruction following the STOP opcode CSR 27 24 indicates the halt source showing the highest priority source for multiple halt conditions 5 5 2 BDM Serial Interface When the CPU is halted and PST reflects the halt status the development system can send unrestricted commands to the debug module The debug module implements a synchronous protocol using two inputs DSCLK and DSI one output DSO where DSCLK and M MOTOROLA Chapter 5 Debug Support 5 17 Background Debug Mode BDM DSI must meet the required input setup and hold timings and the DSO is specified as a delay relative to the rising edge of the processor clock See Table 5 1 The development system serves as the serial communication channel master and must generate DSCLK The serial channel operates at a frequency from DC to 1 5 of the processor frequency The channel uses full duplex mode where data is sent and received simultaneously by both master and slave devices The transmission consists of 17 bit packets composed of a status control bit and a 16 bit data word As shown in Figure 5 13 all state transitions are enabled on a rising edge of the processor clock when DSCLK is high that is DSI is sampled and DSO is driven C1 C2 C3 C4 CPU CLK PSTCLK DSCLK DSI n Current P Next
407. l master accesses Note that TIP is held asserted on back to back bus cycles 17 2 9 Transfer Type TT 1 0 PP 1 0 The TT 1 0 PP 1 0 pins are programmed in the PAR to serve as the transfer type outputs or as two parallel port bits When the MCF5307 is bus master and TT 1 0 are enabled these signals are driven as outputs only If an external master owns the bus and TT 1 0 are enabled these pins are three stated by the MCF5307 and can be driven by the external master Table 17 5 shows the definition of the encodings Table 17 5 Bus Cycle Transfer Type Encoding TT 1 0 Transfer Type 00 Normal access 01 DMA access 10 Emulator access 11 CPU space or interrupt acknowledge 17 2 10 Transfer Modifier TM 2 0 PP 4 2 The TM 2 0 PP 4 2 pins are programmed in the PAR to serve as the transfer modifier outputs or as three parallel port bits These outputs provide supplemental information for each transfer type see Table 17 6 through Table 17 10 When the MCF5307 is the bus master and TM 2 0 are enabled these signals are driven as outputs only If an external device is bus master and TM 2 0 are enabled these pins are three stated by the MCF5307 and can be driven by the external master Table 17 6 TM 2 0 Encodings for TT 00 Normal Access TM 2 0 Transfer Modifier 000 Cache push access 001 User data access 010 User code access 011 100 Reserved 101 Supervisor data access
408. l purpose timer modules timer 0 and timer 1 It includes programming examples Chapter 14 UART Modules describes the use of the universal asynchronous synchronous receiver transmitters UARTs implemented on the MCF5307 and includes programming examples Chapter 15 Parallel Port General Purpose I O describes the operation and programming model of the parallel port pin assignment direction control and data registers It includes a code example for setting up the parallel port Part IV Hardware Interface provides a pinout and both electrical and functional descriptions of the MCF5307 signals It also describes how these signals interact to support the variety of bus operations shown in timing diagrams Chapter 16 Mechanical Data provides a functional pin listing and package diagram for the MCF5307 Chapter 17 Signal Descriptions provides an alphabetical listing of MCF5307 signals This chapter describes the MCF5307 signals In particular it shows which are inputs or outputs how they are multiplexed which signals require pull up resistors and the state of each signal at reset Chapter 18 Bus Operation describes data transfers error conditions bus arbitration and reset operations It describes transfers initiated by the MCF5307 and by an external bus master and includes detailed timing diagrams showing the interaction of signals in supported bus operations Note th
409. l setup write a one to DSR DONE to stop DMA channel 12 5 4 Data Transfer This section includes timing diagrams that illustrate the interaction of signals in DMA data transfers It also describes auto alignment and bandwidth control 12 5 4 4 External Request and Acknowledge Operation Channels 0 and 1 initiate transfers to an external module by means of DREQ 1 0 The request for channels 2 and 3 are connected internally to the UARTO and UARTI interrupt signals respectively If DCR EEXT 1 and the channel is idle the DMA initiates a transfer when DREQ is asserted Figure 12 11 shows the minimum 4 clock cycle delay from when DREQ is sampled asserted to when a DMA bus cycle begins This delay may be longer depending on DMA priority bus arbitration DRAM refresh operations and other factors 12 14 MCF5307 User s Manual M woronoLA DMA Controller Module Functional Description 0 1 2 3 4 5 6 7 8 9 10 11 CLKIN DREQO TMO TS M y ee ae TA Lf he RW A 31 0 X X Read Write Figure 12 11 DREQ Timing Constraints Dual Address DMA Transfer Although Figure 12 11 does not show TMO signaling a DMA acknowledgement this signal can provide an external request acknowledge response as shown in subsequent diagrams To initiate a request DREQ need only be asserted lon
410. le 1 1 User Level Registers Register Description Data registers 00 07 These 32 bit registers are for bit byte word and longword They can also be used as index registers Address registers 7 These 32 bit registers serve as software stack pointers index registers or base address registers The base address registers can be used for word and longword operations A7 functions as a hardware stack pointer during stacking for subroutine calls and exception handling Program counter PC Contains the address of the instruction currently being executed by the MCF5307 processor Condition code The CCR is the lower byte of the SR It contains indicator flags that reflect the result of a previous register CCR operation and are used for conditional instruction execution MAC status Defines the operating configuration of the MAC unit and contains indicator flags from the results register MACSR of MAC instructions Accumulator General purpose register used to accumulate the results of MAC operations ACC Mask register General purpose register provides an optional address mask for MAC instructions that fetch MASK operands from memory It is useful in the implementation of circular queues in operand memory 1 4 3 Supervisor Registers Table 1 2 summarizes the MCF5307 supervisor level registers Table 1 2 Supervisor Level Registers Register Descriptio
411. ler Module Functional 12 11 Transfer Requests Cycle Steal and Continuous Modes 12 12 Data Transfer Modes 12 12 Dual Address Transfers eese nennen 12 12 Single Address Transfers 12 13 Channel Initialization and Startup 12 13 Channel Prioritization esee eee nennen 12 13 Programming the DMA Controller Module sess 12 13 Trani SE Ci vote 12 14 External Request and Acknowledge Operation sess 12 14 12 17 Bandwadth Control e he aaa atm an manns 12 18 T rinimation 12 18 Chapter 13 Timer Module rona E tees 13 1 Key Eedtures 13 2 General Purpose Timer 13 2 General Purpose Timer Programming Model sessssess 13 2 Timer Mode Registers TMRO TMR1 eene 13 3 Timer Reference Registers TRRO TRR1 eere 13 4 Timer Capture Registers TCRO TCRI esee 13 4 Timer Counters CTONO TCNT iiie si iere dee eed 13 5 Timer Event Registers TERO TER1 eene 13 5 Code 2 eere 13 6 Calculating Time Out 13 7 Chapter 14 UART Modules M
412. ll set of instructions are provided for signed and unsigned integers plus signed fixed point fractional input operands Operand Y Operand X Shift 0 1 1 Accumulator Figure 2 2 ColdFire Multiply Accumulate Functionality Diagram The MAC provides functionality in the following three related areas which are described in detail in Chapter 3 Hardware Multiply Accumulate MAC Unit Signed and unsigned integer multiplies Multiply accumulate operations with signed and unsigned fractional operands Miscellaneous register operations 2 1 2 2 3 Hardware Divide Unit The hardware divide unit performs the following integer division operations 32 bit operand 16 bit operand producing 16 bit quotient and a 16 bit remainder e 32 bit operand 32 bit operand producing a 32 bit quotient e 32 bit operand 32 bit operand producing a 32 bit remainder 2 1 3 Debug Module Enhancements The ColdFire processor core debug interface supports system integration in conjunction with low cost development tools Real time trace and debug information can be accessed through a standard interface which allows the processor and system to be debugged at full speed without costly in circuit emulators The MCF5307 debug unit is a compatible upgrade to the MCF52xx debug module with enhancements that include Anew command to obtain the value of the program counter PC Allowing ORing of terms in creating breakpoint
413. ller Module Timer Module UART Modules Parallel Port General Purpose I O Part IV Hardware Interface Mechanical Data Signal Descriptions Bus Operation IEEE 1149 1 Test Access Port JTAG Electrical Specifications Appendix Memory Map Glossary of Terms and Abbreviations Index
414. ls the shortest A data arbitration procedure 84 MCF5307 User s Manual M I C Protocol determines the relative priority of competing devices A device loses arbitration if it sends logic high while another sends logic low it immediately switches to slave receive mode and stops driving SDA In this case the transition from master to slave mode does not generate a STOP condition Meanwhile hardware sets I2SR IAL to indicate loss of arbitration 8 4 2 Clock Synchronization Because wire AND logic is used a high to low transition on SCL affects devices connected to the bus Devices start counting their low period when the master drives SCL low When a device clock goes low it holds SCL low until the clock high state is reached However the low to high change in this device clock may not change the state of SCL if another device clock is still in its low period Therefore the device with the longest low period holds the synchronized clock SCL low Devices with shorter low periods enter a high wait state during this time See Figure 8 4 When all devices involved have counted off their low period the synchronized clock SCL is released and pulled high There is then no difference between device clocks and the state of SCL so all of the devices start counting their high periods The first device to complete its high period pulls SCL low again Wait Start counting high period nc d 2 ah
415. lt Although many BDM operations can occur in parallel with CPU operations unrestricted BDM operation requires the CPU to be halted The sources that can cause the CPU to halt are listed below in order of priority 1 A catastrophic fault on fault condition automatically halts the processor 5 16 MCF5307 User s Manual M woronoLA Background Debug Mode BDM 2 A hardware breakpoint can be configured to generate a pending halt condition similar to the assertion of BKPT This type of halt is always first made pending in the processor Next the processor samples for pending halt and interrupt conditions once per instruction When a pending condition is asserted the processor halts execution at the next sample point See Section 5 6 1 Theory of Operation 3 The execution of a HALT instruction immediately suspends execution Attempting to execute HALT in user mode while CSR UHE 0 generates a privilege violation exception If CSR UHE 1 HALT can be executed in user mode After HALT executes the processor can be restarted by serial shifting a GO command into the debug module Execution continues at the instruction after HALT 4 The assertion of the BKPT input is treated as a pseudo interrupt that is the halt condition is postponed until the processor core samples for halts interrupts The processor samples for these conditions once during the execution of each instruction If there is a pending halt condition at the sample ti
416. lt 0 ASR Dy Dx MSB gt gt Dy X C lt data gt Dx iL MSB Dx gt gt lt gt X C Bcc label B W If condition true then PC 2 d gt BCHG Dy lt ea gt x BL bit number of destination Z lt data gt lt ea 1 gt x B L Bit of destination BCLR Dy lt ea gt x B L bit number of destination 7 lt data gt lt ea 1 gt x B L 0 bit of destination BRA label B W PC 2 d gt PC BSET Dy lt ea gt x B L bit number of destination Z lt data gt lt ea 1 gt x B L 1 bit of destination BSR label B W SP 4 SP next sequential SP PC 2 d gt PC BTST Dy lt ea gt x B L lt bit number of destination Z lt data gt lt ea 1 gt x B L CLR lt ea gt y Dx B W L 0 destination CMP ea y Ax L Destination source CMPA lt ea gt y Dx L Destination source M MOTOROLA Chapter 2 ColdFire Core 2 37 Instruction Set Summary Table 2 7 User Mode Instruction Set Summary Continued Instruction Operand Syntax Operand Size Operation CMPI ea y Dx E Destination immediate data DIVS lt ea 1 gt y Dx W Dx ea y Dx 16 bit remainder 16 bit quotient lt ea gt y Dx L Dx ea y Dx 32 bit quotient Signed operation DIVU lt ea 1 gt y Dx W Dx ea y Dx 16 bit remainder 16 bit
417. mask register bank 7 CSMR7 p 10 6 0x0DC Reserved Chip select control register bank 7 CSCR7 p 10 8 A 2 MCF5307 User s Manual M woronoLA Table A 3 Chip Select Registers Continued MBAR 7 Offset 31 24 23 16 15 8 7 0 MBAR 3 Offset 31 24 23 16 15 8 7 0 0x080 Chip select address register bank 0 CSARO Reserved p 10 6 0x084 Chip select mask register bank 0 CSMR0O p 10 6 0x088 Reserved Chip select control register bank 0 CSCRO p 10 8 0x08C Chip select address register bank 1 CSAR1 Reserved p 10 6 0x090 Chip select mask register bank 1 CSMR1 p 10 6 0x094 Reserved Chip select control register bank 1 CSCR1 p 10 8 0x098 Chip select address register bank 2 CSAR2 Reserved p 10 6 0x09C Chip select mask register bank 2 CSMR2 p 10 6 Ox0A0 Reserved Chip select control register bank 2 CSCR2 p 10 8 0 0 4 Chip select address register bank 3 CSAR3 Reserved p 10 6 0x0A8 Chip select mask register bank 3 CSMR3 p 10 6 Reserved Chip select control register bank 3 CSCR3 p 10 8 Chip select address register bank 4 Reserved p 10 6 0x0B4 Chip select mask register bank 4 CSMR4 p 10 6 0x0B8 Reserved Chip select control register bank 4 CSCR4 p 10 8 Addresses not assigned to a register and undefined register bits are
418. masking Interrupt mask registers in the SIM compare interrupt inputs with programmable interrupt mask levels The SIM outputs only unmasked interrupts The status register uses a 3 bit interrupt priority mask The core recognizes only interrupt requests of higher priority than the value in the mask See Section 2 2 2 1 Status Register SR NOTE To mask a level 1 6 interrupt source write a higher level SR interrupt mask before setting IMR Then restore the mask to its previous value Do not mask a level 7 interrupt source The MCF5307 continuously samples and synchronizes external interrupt inputs An interrupt request must be held for at least two consecutive BCLKO periods to be considered valid To guarantee that the interrupt is recognized the request level must be maintained until the MCF5307 acknowledges the interrupt with an interrupt acknowledge cycle NOTE Interrupt levels 1 7 are level sensitive Level 7 is also edge triggered See Section 18 7 1 Level 7 Interrupts The MCF5307 takes an interrupt exception for a pending interrupt within one instruction boundary after processing any higher priority pending exception Thus the MCF5307 executes at least one instruction in an interrupt exception handler before recognizing another interrupt request If autovector generation is used for internal interrupts ICRn AVEC 1 the interrupt acknowledge vector is generated internally and no interrupt acknowledge
419. mber Abbreviations for registers are shown in uppercase Specific bits fields or ranges appear in brackets For example RAMBAR BA identifies the base address field in the RAM base address register A 4 bit data unit An 8 bit data unit A 16 bit data unit A 32 bit data unit In some contexts such as signal encodings x indicates a don t care Used to express an undefined numerical value NOT logical operator AND logical operator OR logical operator Acronyms and Abbreviations Table i lists acronyms and abbreviations used in this document Table i Acronyms and Abbreviated Terms ADC Analog to digital conversion ALU AVEC BIST CODEC DAC DMA Arithmetic logic unit Autovector Background debug mode Built in self test Code decode Digital to analog conversion Direct memory access Digital signal processing BSDL Boundary scan description language Effective address Extended data output DRAM First in first out M MOTOROLA AboutThis Book XXXV Acronyms and Abbreviations Table i Acronyms and Abbreviated Terms Continued NN xxxvi MCF5307 User s Manual M MOTOROLA Terminology and Notational Conventions Terminology and Notational Conventions Table ii shows notational conventions used throughout this document Table ii Notational Conventions Instruct
420. me subsequent accesses are streamlined Single accesses look the same as non page mode accesses Burst page mode accesses of any size byte word longword or line are assumed to reside in the same page In this mode the DRAM controller generates a burst transfer only when the operand is larger than the DRAM block port size such as a line transfer to a 32 bit port or a longword transfer to an 8 bit port The primary cycle asserts RAS and CAS subsequent cycles assert only CAS At the end of the access RAS is precharged The DRAM controller increments addresses between cycles Figure 11 7 shows a read access in burst page mode Four accesses take place which could be a 32 bit access to an 8 bit port or a line access to a 32 bit port Other burst page mode operations may be from 2 to 16 accesses long depending on the access and port sizes In those cases timing is similar with more or fewer accesses 11 12 MCF5307 User s Manual M woronoLA Asynchronous Operation BCLKO ei Column t Column 31 0 RAS 1 or 0 CAS 3 0 DRAMW 1 0 31 0 EE N py uei e Figure 11 7 Burst Page Mode Read Operation 4 3 3 3 Figure 11 8 shows the write operation with the same configuration BCLKO A 31 0 Ros Y Colum t qoem 3 ne cat
421. me the processor suspends execution and enters the halted state The assertion of BKPT should be considered in the following two special cases e After the system reset signal is negated the processor waits for 16 processor clock cycles before beginning reset exception processing If the BKPT input is asserted within eight cycles after RSTI is negated the processor enters the halt state signaling halt status OxF on the PST outputs While the processor is in this state all resources accessible through the debug module can be referenced This is the only chance to force the processor into emulation mode through CSR EMU After system initialization the processor s response to the GO command depends on the set of BDM commands performed while it is halted for a breakpoint Specifically if the PC register was loaded the GO command causes the processor to exit halted state and pass control to the instruction address in the PC bypassing normal reset exception processing If the PC was not loaded the GO command causes the processor to exit halted state and continue reset exception processing The ColdFire architecture also handles a special case of BKPT being asserted while the processor is stopped by execution of the STOP instruction For this case the processor exits the stopped mode and enters the halted state at which point all BDM commands may be exercised When restarted the processor continues by executing the next sequentia
422. mentation of the 1149 1 IEEE standard The test logic includes several test data registers an instruction register instruction register control decode and a 16 state dedicated TAP controller Test Data Registers Boundary Scan Register TDI ID Code Bypass 3 Bit Instruction Decode A i 3 Bit Instruction Register TDO Figure 19 1 JTAG Test Logic Block Diagram 19 2 JTAG Signal Descriptions JTAG operation on the MCF5307 is enabled when MTMODO is high logic 1 as described in Table 19 1 Otherwise JTAG TAP signals TCK TMS TDI TDO and TRST are interpreted as the debug port pins MTMODO should not be changed while RSTI is asserted Table 19 1 JTAG Pin Descriptions Pin Description Test clock The dedicated JTAG test logic clock is independent of the MCF5307 processor clock Various JTAG operations occur on the rising or falling edge of TCK Internal JTAG controller logic is designed such that holding TCK high or low indefinitely does cause the JTAG test logic to lose state information If TCK is not used it should be tied to ground Test mode select MTMODO high breakpoint MTMODO low TMS provides the JTAG controller with information to determine the test operation mode The states of TMS and of the internal 16 state JTAG controller state machine at the rising edge of TCK determine whether the JTAG controller hold
423. ming parameters in Figure 20 17 Table 20 13 General Purpose I O Port AC Timing Specifications 66 MHz 90 MHz Num Characteristic Units Min Max Min Max P1 PP valid to BCLKO input setup 7 5 5 5 nS P2 BCLKO to PP invalid input hold 3 2 nS P3 BCLKO to PP valid output valid 15 11 nS P4 BCLKO to PP invalid output hold 1 1 nS Figure 20 17 shows general purpose I O timing BCLKO EE m PP IN Figure 20 17 General Purpose I O Timing 20 18 MCF5307 User s Manual M woronoLA DMA Timing Specifications 20 10 DMA Timing Specifications Table 20 14 lists specifications for DMA timing parameters shown in Figure 20 17 Table 20 14 DMA AC Timing Specifications 66 MHz 90 MHz Num Characteristic Units Min Max Min Max M1 DREQ valid to BCLKO input setup 7 5 5 5 nS M2 BCLKO to DREQ invalid input hold 3 2 nS Figure 20 18 shows DMA AC timing Figure 20 18 DMA Timing M woronoLA Chapter 20 Electrical Specifications 20 19 IEEE 1149 1 JTAG AC Timing Specifications 20 11 IEEE 1149 1 JTAG AC Timing Specifications Table 20 15 lists specifications for JTAG AC timing parameters shown in Figure 20 19 Table 20 15 IEEE 1149 1 JTAG AC Timing Specifications All Num Characteristic Frequencies Units Min Max TCK frequency of
424. modules 14 2 14 16 CR 14 9 CSR 14 8 DU UDL 14 14 IP 14 15 IPCR 14 12 ISR 14 13 IVR 14 15 vector base 2 30 write control 5 37 write debug module 5 39 c C eC ce Index 20 o RSTI timing 7 5 SDRAM block diagram and major components 11 2 controller registers A 3 DACR initialization 11 35 DCR initialization 11 35 definitions 11 2 DMR initialization 11 37 example 11 34 initialization code 11 39 interface configuration 11 35 mode register initialization 11 38 overview 11 1 Signal descriptions 17 1 address bus 17 7 configuration 17 14 strobe 17 9 bus arbitration 17 12 clock output 17 13 data 17 8 driven 17 13 grant 17 12 request 17 12 chip select module 17 15 clock 17 13 clock and reset signals divide control 17 15 data bus 17 8 data configuration pins 17 13 debug high impedance 17 20 JTAG 17 21 processor clock output 17 20 test clock 17 23 mode 17 20 overview 17 20 DMA controller module 17 17 DRAM controller address strobes 17 16 overview 17 16 synchronous clock enable 17 17 column address strobe 17 17 edge select 17 17 row address strobe 17 17 write 17 17 module general 17 19 serial data and clock 17 19 MCF5307 User s Manual M woronoLA INDEX interrupt control signals 17 12 request 17 12 JTAG 19 2 parallel I O port 17 19 read write 17 8 reset in out 17 13 serial module general 17 18 receiver serial data in
425. mplementations for example in design feature set and implementation of optional features The ColdFire architecture has many different implementations Imprecise mode A memory access mode that allows write accesses to a specified memory region to occur out of order Instruction queue A holding place for instructions fetched from the current instruction stream Instruction latency The total number of clock cycles necessary to execute an instruction and make the results of that instruction available Interrupt An asynchronous exception On ColdFire processors interrupts are a special case of exceptions See also asynchronous exception Invalid state State of a cache entry that does not currently contain a valid copy of a cache line from memory aa Least significant bit Isb The bit of least value in an address register data element or instruction encoding Least significant byte LSB The byte of least value in an address register data element or instruction encoding Longword A 32 bit data element M Master A device able to initiate data transfers on a bus Bus mastering refers to a feature supported by some bus architectures that allow a controller connected to the bus to communicate directly with other devices on the bus without going through the CPU Memory coherency An aspect of caching in which it is ensured that an accurate view of memory is provided to all devices that share system memory Modified sta
426. must continue to operate during debug The foundation of this area of debug support is that while the processor cannot be halted to allow debugging the system can generally tolerate small intrusions into the real time operation The debug module provides three types of breakpoints PC with mask operand address range and data with mask These breakpoints can be configured into one or two level triggers with the exact trigger response also programmable The debug module programming model can be written from either the external development system using the debug serial interface or from the processor s supervisor programming model using the WDEBUG instruction Only CSR is readable using the external development system M MOTOROLA Chapter 5 Debug Support 5 39 Real Time Debug Support 5 6 1 Theory of Operation Breakpoint hardware can be configured to respond to triggers in several ways The response desired is programmed into TDR As shown in Table 5 21 when a breakpoint is triggered an indication CSR BSTAT is provided on the DDATA output port when it is not displaying captured processor status operands or branch addresses Table 5 21 DDATA 3 0 CSR BSTAT Breakpoint Response DDATA 3 0 CSR BSTAT 1 Breakpoint Status 0000 0000 No breakpoints enabled 0010 0001 Waiting for level 1 breakpoint 0100 0010 Level 1 breakpoint triggered 1010 0101 Waiting for level 2 breakpoint 1100 0110 Level 2 breakpoint triggered
427. n eee 14 13 UART Divider Upper Register 14 14 UART Divider Lower Register nennen 14 14 UART Interrupt Vector Register 14 15 UART Input Port Register UIPD cccicssssesssssevscsvestesscostsvessecssesssscsiecssontivestestsonsines 14 15 UART Block Diagram Showing External and Internal Interface Signals 14 16 UART Output Port Command Register UOPI UOPO sese 14 16 UART RS 232 Interface c s c cosesecesacesesesecosecsosesecesesesesesecesedesocesacesestcedesecetesesocesess 14 17 Clocking Source Diagram nennen 14 18 Transmitter and Receiver Functional 14 20 Transmitter Timing Diagram sees ennt nnne nennen enne 14 22 Receiver TIM Bis C 14 23 AULOMAUIC ECHO T 14 25 Local Loop Back s s c s cecssececosngesesaseseseseseseusdesasecosesecenesesoseeedesnsasecessconesesecesesesesesosesess 14 26 Remote Loop Back 1 14 26 Multidrop Mode Timing Diagram eese nennen 14 27 UART Mode Programming 14 30 Parallel Port Pin Assignment Register PAR sess 15 1 Port A Data Direction Register PADDR esee nnne 15 2 Port A Data Register 15 3 Mechan
428. n Status register SR The upper byte of the SR provides interrupt information in addition to a variety of mode indicators signaling the operating state of the ColdFire processor The lower byte of the SR is the CCR as shown in Figure 1 4 Vector base register VBR Defines the upper 12 bits of the base address of the exception vector table used during exception processing The low order 20 bits are forced to zero locating the vector table on 0 modulo 1 Mbyte address Cache configuration register CACR Defines the operating modes of the Version 4 cache memories Control fields configuring the instruction data and branch cache are provided by this register along with the default attributes for the 4 Gbyte address space Access control registers ACRO 1 Define address ranges and attributes associated with various memory regions within the 4 Gbyte address space Each ACR defines the location of a given memory region and assigns attributes such as write protection and cache mode copyback write through cacheability Additionally CACR fields assign default attributes to the instruction and data memory spaces RAM base address register RAMBAR Provide the logical base address for the 4 Kbyte SRAM module and define attributes and access types allowed for the SRAM Module base address register MBAR Defines the logical base address for the memory mapped space containing the control registers for the
429. n AA CONFIG At reset the enabling and disabling of auto acknowledge for boot CSO is determined by the logic level driven on D7 at the rising edge of AA CONFIG is multiplexed with D7 and sampled only at reset The D7 logic level is reflected as the reset value of CSCR AA Table 17 12 shows how the D7 logic level corresponds to the auto acknowledge timing for CS0 at reset Note that auto acknowledge can be disabled by driving a logic 0 on D7 at reset Table 17 12 D7 Selection of CSO Automatic Acknowledge D7 CSCRO AA Boot CS0 0 Disabled 1 Enabled with 15 wait states 17 5 5 3 D 6 5 Port Size Configuration PS CONFIG 1 0 The default port size value of the boot CSO is determined by the logic levels driven on D 6 5 at the rising edge of RSTI which are reflected as the reset value of CSCR PS Table 17 13 shows how the logic levels of D 6 5 correspond to the CSO port size at reset Table 17 13 D6 and D5 Selection of CSO Port Size D 6 5 CSCRO PS Boot CS0 Port Size 00 32 bit port 01 8 bit port 1x 16 bit port 17 5 6 D4 Address Configuration ADDR CONFIG The address configuration signal ADDR CONFIG programs the PAR of the parallel I O port to be either parallel I O or to be the upper address bus bits along with various attribute and control signals at reset to give the user the option to access a broader addressing range 17 14 MCF
430. n chip memories or MBAR they can access any parallel port module registers in the SIM 15 1 4 Code Example The following code example shows how to set up the parallel port Here PP 7 0 are general purpose I O PP 3 0 are inputs and PP 7 4 are outputs MOTOROLA Chapter 15 Parallel Port General Purpose I O 15 3 Parallel Port Operation 15 4 MBARX PAR PADDR PADAT move movec move move move move move move I ocozzzz EQU 0x00010000 EQU MBARx 0x004 EQU MBARx 0x244 EQU 0 248 MBARx DO DO MBAR 0x00FF DO PAR 0x00F0 D0 DO PADDR 0xA0 DO DO PADAT because MBAR is an internal register MBARx is used as label for the memory map address set up the PAR PP 7 0 set up as I O set PP 7 4 as outputs PP 3 0 as inputs 0xA0 written into PADAT PP 7 4 being outputs PP 7 4 becomes 1010 i e PP7 PP5 1 PP6 0 MCF5307 User s Manual M woronoLA Part IV Hardware Interface Intended Audience Part IV is intended for hardware designers who need to know the functions and electrical characteristics of the MCF5407 interface It includes a pinout and both electrical and functional descriptions of the MCF5307 signals It also describes how these signals interact to support the variety of bus operations shown in timing diagrams Contents Part IV contains the following chapters Chapter 16 Mechanical Data provides a functional
431. n internal refresh request flag is set and the counter begins counting down again The DRAM controller completes any active burst operation and then performs a PALL operation The DRAM controller then initiates a refresh cycle and clears the refresh request flag This refresh cycle includes a delay from any precharge to the auto refresh command the auto refresh command and then a delay until any ACTV command is allowed Any SDRAM access initiated during the auto refresh cycle is delayed until the cycle is completed Figure 11 22 shows the auto refresh timing In this case there is an SDRAM access when the refresh request becomes active The request is delayed by the precharge to ACTV delay programmed into the active SDRAM bank by the CAS bits The REF command is then generated and the delay required by DCR RTIM is inserted before the next ACTV command is generated In this example the next bus cycle is initiated but does not generate an SDRAM access until is finished Because both chip selects are active during the REF command it is passed to both blocks of external SDRAM M MOTOROLA Chapter 11 Synchronous Asynchronous DRAM Controller Module 11 31 Synchronous Operation SRAS i tao 6 Lt SCAS DRAMW RASIO or 1 PALL NOP REF
432. n of this command is considerably less obtrusive to the real time operation of an application than a HALT CPU READ PC RESUME command sequence Command Formats 0x0 0 0 0 0 0 1 Figure 5 34 sync_PC Command Format Command Sequence YNC PC NEXT CMD 22 COMPLETEY Figure 5 35 sYNC Command Sequence Operand Data None Result Data Command complete status OXFFFF is returned when the register write is complete M MOTOROLA Chapter 5 Debug Support 5 35 Background Debug Mode BDM 5 5 3 3 10 Read Control Register RCREG Read the selected control register and return the 32 bit result Accesses to the processor memory control registers are always 32 bits wide regardless of register width The second and third words of the command form a 32 bit address which the debug module uses to generate a special bus cycle to access the specified control register The 12 bit Rc field is the same as that used by the MOVEC instruction Command Result Formats 15 14 18 12 11 10 9 8 7 6 5 4 3 2 1 0 Command 0 2 0 9 0 8 0 0 0 0 0 0 0 0 0x0 0x0 Rc Result D 31 16 D 15 0 Figure 5 36 RcREG Command Result Formats Rc encoding Table 5 19 Control Register Map Rc Register Definition Rc Register Definition 0x002 Cache control register CACR 0x805 MAC mask register MASK 0x004 Access control register 0 ACRO 0x806 MAC accumulator
433. nals essen 17 4 1 Bus Request BR zn 420 28st ee e e p p edema 17 4 2 Bus Grant BG 17 4 3 Bus Driven BD eerte rei eee 17 5 Clock and Reset Sigmals ccc cciucsceticsccsscecostsscssaccocsssdssndbcocdescscedtcocsseescesedonssve 17 5 1 Reset In RSTD Bitte hia MMe ei EO 17 5 2 Clock Input CEKIN n ere terne eto teet eee ee tenehe 17 5 3 Bus Clock Output BCLKO eese nennen 17 5 4 Reset Out RSTO sss eene nennen nnne rennen nnne 17 5 5 Data Configuration Pins D 7 0 17 5 5 1 D 7 5Boot Chip Select CSO Configuration sss 17 14 17 5 5 2 D7 Auto Acknowledge Configuration AA_CONFIG 17 14 M MOTOROLA Contents Paragraph Number 17 5 5 3 17 5 6 17 5 7 17 5 8 17 6 17 6 1 17 6 2 17 6 3 17 7 17 7 1 17 7 2 17 7 3 17 7 4 17 7 5 17 7 6 17 7 7 17 8 17 8 1 17 9 17 9 1 17 9 2 17 9 3 17 9 4 17 10 17 10 1 17 10 2 17 11 17 12 17 12 1 17 12 2 17 13 17 13 1 17 13 2 17 13 3 17 13 4 17 13 5 17 14 17 14 1 17 14 2 17 14 3 17 14 4 17 14 5 xvi CONTENTS Page Number D 6 5 Port Size Configuration PS CONFIG 1 0 17 14 D4 Address Configuration ADDR CONFIO eee 17 14 D 3 2 Frequency Control PLL FREQ 1 0 eese 17 15 D 1 0 Divide C
434. nctionality in three related areas Signed and unsigned integer multiplies Multiply accumulate operations supporting signed unsigned and signed fractional operands Miscellaneous register operations Each of the three areas of support is addressed in detail in the succeeding sections Logic that supports this functionality is contained in MAC module as shown in Figure 3 1 The MAC unit is tightly coupled to the OEP and features a three stage execution pipeline To minimize silicon costs the ColdFire MAC is optimized for 16 x 16 multiply instructions The OEP can issue a 16 x 16 multiply with a 32 bit accumulation and fetch a 32 bit operand in the same cycle A 32 x 32 multiply with a 32 bit accumulation takes three cycles before the next instruction can be issued Figure 3 1 shows the basic functionality of the ColdFire MAC A full set of instructions is provided for signed and unsigned integers plus signed fixed point fractional input operands M MOTOROLA Chapter 3 Hardware Multiply Accumulate MAC Unit 3 1 Overview Operand Y Operand X Shift 0 1 1 Accumulator Figure 3 1 ColdFire MAC Multiplication and Accumulation The MAC unit is an extension of the basic multiplier found on most microprocessors It can perform operations native to signal processing algorithms in an acceptable number of cycles given the application constraints For example small digital filters can toler
435. nessosesscosesesocssecesesesecesese 20 13 Timer Module AC Timing sese 20 14 Input Output TUIS eer goa rd eL Le le a iom Ie Yo 20 16 UARTO0 1 Module AC Timing UART Mode eee 20 17 General Purpose Timing esee 20 18 eene eei ted te eei int Rem tir ees 20 19 1149 1 AC seen enne 20 21 MCF5307 User s Manual M woronoLA Table Number 1 1 1 2 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 2 10 2 11 2 12 2 13 2 14 2 15 2 16 2 17 2 18 2 19 2 20 2 21 3 1 3 2 3 3 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 1 TABLES 4 Number User Level Tusc 1 14 Supervisor Level Registers netten nenne iiia 1 14 CCR Field Descriptions MOVEC Register Map onion Status Field Descriptions Integer Data ColdFire Effective Addressing Modes sse 2 34 Notational Conventions 2 34 User Mode Instruction Set Summary sese 2 37 Supervisor Mode Instruction Set Summary sess 2 40 Misaligned Operand References essen emen 2 41 Move Byte and Word Execution 2 42 Move Long Execution Times nee MAC Move Execution Times One Operand Instruction Execution Times sese 2 43 Two Operand Instruction Execution Times sese 2 44
436. ng COC allows SCKE to provide command bit functionality 5 3 0 Column address strobe For synchronous operation CAS 3 0 function as byte enables to the SDRAMs They connect to the DQM signals or mask qualifiers of the SDRAMs M MOTOROLA Chapter 11 Synchronous Asynchronous DRAM Controller Module 11 17 Synchronous Operation Table 11 11 Synchronous DRAM Signal Connections Continued Signal Description BCLKO Bus clock output Connects to the CLK input of SDRAMs EDGESEL Synchronous edge select Provides additional output hold time for signals that interface to external SDRAMs EDGESEL supports the three following modes for SDRAM interface signals Tied high Signals change on the rising edge of BCLKO Tied low Signals change on the falling edge of BCLKO Tied to buffered BCLKO Signals change on the rising edge of the buffered clock EDGESEL can provide additional output hold time for SDRAM interface signals however the SDRAM clock and BCLKO frequencies must be the same See Section 11 4 2 Using Edge Select EDGESEL Figure 11 13 shows a typical signal configuration for synchronous mode MCF5307 SDRAM A 31 0 ADDRESS D 31 0 gt DATA CAS gt DQM DRAMW gt WE SCAS CAS SRAS RAS SCKE gt CKE 1 EDGESEL lt CLK BCLKO 1 Trace length from buffer to CLK must equal length from buffer to EDGE
437. ng Time Out Values Table 13 5 Calculated Time out Values 90 MHz Processor Clock Continued TMR PS TMR CLK 10 System Bus Clock 16 TMR CLK 01 System Bus Clock 1 Decimal Hex 45 MHz 30 MHz 22 5 MHz 45 MHz 30 MHz 22 5 MHz 46 2E 1 09518 1 64277 2 19036 0 06845 0 10267 0 1369 47 2F 1 11848 1 67772 2 23696 0 06991 0 10486 0 13981 48 30 1 14178 1 71267 2 28357 0 07136 0 10704 0 14272 49 31 1 16508 1 74763 2 33017 0 07282 0 10923 0 14564 50 32 1 18839 1 78258 2 37677 0 07427 0 11141 0 14855 51 33 1 21169 1 81753 2 42338 0 07573 0 1136 0 15146 52 34 1 23499 1 85248 2 46998 0 07719 0 11578 0 15437 53 35 1 25829 1 88744 2 51658 0 07864 0 11796 0 15729 54 36 1 28159 1 92239 2 56319 0 0801 0 12015 0 1602 55 37 1 30489 1 95734 2 60979 0 08156 0 12233 0 16311 56 38 1 3282 1 99229 2 65639 0 08301 0 12452 0 16602 57 39 1 3515 2 02725 2 703 0 08447 0 1267 0 16894 58 3A 1 3748 2 0622 2 7496 0 08592 0 12889 0 17185 59 3B 1 3981 2 09715 2 7962 0 08738 0 13107 0 17476 60 3C 1 4214 2 1321 2 84281 0 08884 0 13326 0 17768 61 3D 1 4447 2 16706 2 88941 0 09029 0 13544 0 18059 62 3E 1 46801 2 20201 2 93601 0 09175 0 13763 0 1835 63 3F 1 49131 2 23696 2 98262 0 09321 0 13981 0 18641 64 40 1 51461 2 27191 3 02922 0 09466 0 14199 0 18933 65 41 1 53791 2 30687 3 07582 0 09612 0 14418 0 19224 66 42 1 56121 2 34182 3 12243 0 09758 0 146
438. ng data out of the device while CAS is precharging To support EDO DRAMs the DRAM controller delays internal termination of the cycle by one clock so data can continue to be captured as CAS is being precharged For data to be driven by the DRAMs RAS is held after CAS is negated EDO operation does not affect write operations EDO DRAMs can be used in continuous page or burst page modes Single accesses not followed by a hit in the page look like non page mode accesses Figure 11 11 shows four consecutive EDO accesses Note that data is sampled after CAS is negated and that on the last page access CAS is held until after data is sampled to assure that the data is driven This allows RAS to be precharged before the end of the cycle 31 0 X X X RAS 1 or 0 CAS 3 0 DRAMW DIST ae EE ES Figure 11 11 EDO Read Operation 3 2 2 2 M MOTOROLA Chapter 11 Synchronous Asynchronous DRAM Controller Module 11 15 Synchronous Operation 11 3 3 5 Refresh Operation The DRAM controller supports CAS before RAS refresh operations that are not synchronized to bus activity A special DRAMW pin is provided so refresh can occur regardless of the state of the processor bus When the refresh counter rolls over it sets an internal flag to indicate that a refresh is pending If that happens during a c
439. ng for 64 Kbyte to 4 Gbyte memory block sizes Programmable wait states and port sizes External master access to chip selects See Chapter 10 Chip Select Module System protection and reset status Reset status indicating the cause of last reset Software watchdog timer with programmable secondary bus monitor See Section 6 2 4 Software Watchdog Timer Pin assignment register PAR configures the parallel port See Section 6 2 9 Pin Assignment Register PAR Bus arbitration Default bus master park register MPARK controls internal and external bus arbitration and enables display of internal accesses on the external bus for debugging Supports several arbitration algorithms See Section 6 2 10 Bus Arbitration Control MCF5307 User s Manual M woronoLA 6 2 Programming Model Programming Model The following sections describe the registers incorporated into the SIM 6 2 1 SIM Register Memory Map Table 6 1 shows the memory map for the SIM registers The internal registers in the SIM are memory mapped registers offset from the MBAR address pointer defined in MBAR BAJ This supervisor level register is described in Section 6 2 2 Module Base Address Register MBAR Because SIM registers depend on the base address defined in MBAR BA MBAR must be programmed before SIM registers can be accessed NOTE Although external masters cannot access the MCF5307 s on chip memories
440. ng literature may be helpful with respect to the topics in Part I e ColdFire Programmers Reference Manual R1 0 MCF5200PRM AD e Using Microprocessors and Microcomputers The Motorola Family William C Wray Ross Bannatyne Joseph D Greenfield Acronyms and Abbreviations Table I i contains acronyms and abbreviations are used in Part I Table 1 1 Acronyms and Abbreviated Terms sou I xviii MCF5307 User s Manual M MOTOROLA Table I i Acronyms and Abbreviated Terms Continued BINNEN NN _ M Part I MCF5307 Processor Core I xix I xx MCF5307 User s Manual M woronoLA Chapter 2 ColdFire Core This chapter provides an overview of the microprocessor core of the MCF5307 The chapter begins with a description of enhancements from the Version 2 V2 ColdFire core and then fully describes the V3 programming model as it is implemented on the MCF5307 It also includes a full description of exception handling data formats an instruction set summary and a table of instruction timings 2 1 Features and Enhancements The MCF5307 is the first standard product to contain a Version 3 ColdFire microprocessor core To reach higher levels of frequency and performance numerous enhancements were made to the V2 architecture Most notable are a deeper instruction pipeline branch acceleration and a unified cache which together provide 75 Dhrystone 2 1 MIPS at 90
441. nnel or from the processor s supervisor mode programming model The breakpoint registers can be configured to generate triggers by combining the address data and PC conditions in a variety of single or dual level definitions The trigger event can be programmed to generate a processor halt or initiate a debug interrupt exception The MCF5307 s new interrupt servicing options during emulator mode allow real time critical interrupt service routines to be serviced while processing a debug interrupt event thereby ensuring that the system continues to operate even during debugging To support program trace the Version 3 debug module provides processor status PST 3 0 and debug data DDATA 3 0 ports These buses and the PSTCLK output provide execution status captured operand data and branch target addresses defining processor activity at the CPU s clock rate 1 3 9 PLL Module The MCF5307 PLL module is shown in Figure 1 3 M MOTOROLA Chapter 1 Overview 1 11 Programming Model Addressing Modes and Instruction Set RSTO PCLK PSTCLK CLKIN Since 2 FREQ 1 0 RSTI DIVIDE 1 0 Figure 1 3 PLL Module The PLL module s three modes of operation are described as follows Reset mode When RSTI is asserted the PLL enters reset mode At reset the PLL asserts RSTO from the MCF5307 The core bus frequency ratio and other MCF5307 configurati
442. ns such as chip selects interrupt control bus arbitration and an IEEE 1149 1 JTAG module are included A sophisticated debug interface supports background debug mode plus real time trace and debug with expanded flexibility of on chip breakpoint registers This interface is present in all ColdFire standard products and allows common emulator support across the entire family of microprocessors M MOTOROLA Chapter 1 Overview 1 3 MCF5307 Features 1 2 MCF5307 Features The following list summarizes MCF5307 features ColdFire processor core Variable length RISC clock multiplied Version 3 microprocessor core Fully code compatible with Version 2 processors Two independent decoupled pipelines four stage instruction fetch pipeline IFP and two stage operand execution pipeline OEP Eight instruction FIFO buffer provides decoupling between the pipelines Branch prediction mechanisms for accelerating program execution 32 bit internal address bus supporting 4 Gbytes of linear address space 32 bit data bus 16 user accessible 32 bit wide general purpose registers Supervisor user modes for system protection Vector base register to relocate exception vector table Optimized for high level language constructs Multiply and accumulate unit MAC High speed complex arithmetic processing for DSP applications Tightly coupled to the OEP Three stage execute pipeline with one clock issue ra
443. nt the modified cache data moves to the push buffer The replacement line is read into the cache and the push buffer contents are then written to memory 4 9 2 Cache Inhibited Accesses Memory regions can be designated as cache inhibited which is useful for memory containing targets such as I O devices and shared data structures in multiprocessing systems It is also important to not cache the MCF5307 memory mapped registers If the corresponding ACRn CM or CACR DCM indicates cache inhibited precise or imprecise the access is cache inhibited The caching operation is identical for both cache inhibited modes which differ only regarding recovery from an external bus error In determining whether a memory location is cacheable or cache inhibited the CPU checks memory control registers in the following order 1 RAMBAR 2 ACRO 4 14 MCF5307 User s Manual M woronoLA Cache Operation 3 ACRI 4 If an access does not hit in RAMBAR or the ACRs the default is provided for all accesses in CACR Cache inhibited write accesses bypass the cache and a corresponding external write is performed Cache inhibited reads bypass the cache and are performed on the external bus except when all of the following conditions are true The cache inhibited fill buffer bit CACR DNFB is set The access is an instruction read The access is normal that is 0 In this case a fetched line is stored in the fill buffer and remains v
444. nt receiver overrun If both the receiver and transmitter are incorrectly programmed for RTS control RTS control is disabled for both Transmitter RTS control is configured in UMR2n TxRTS 0 The receiver has no effect on RTS 1 When a valid start bit is received RTS is negated if the UART s FIFO is full RTS is reasserted when the FIFO has an empty position available 6 RxIRQ Receiver interrupt select FFULL 0 RxRDY is the source that generates IRQ 1 FFULL is the source that generates IRQ 5 ERR Error mode Configures the FIFO status bits USRn RB FE PE 0 Character mode The USRn values reflect the status of the character at the top of the FIFO ERR must be 0 for correct A D flag information when in multidrop mode 1 Block mode The USRn values are the logical OR of the status for all characters reaching the top of the FIFO because the last RESET ERROR STATUS command for the channel was issued See Section 14 3 5 UART Command Registers UCRn 4 3 PM Parity mode Selects the parity or multidrop mode for the channel The parity bit is added to the transmitted character and the receiver performs a parity check on incoming data The value of PM affects PT as shown below 2 PT Parity type PM and PT together select parity type PM Ox or determine whether a data or address character is transmitted PM 11 PM Parity Mode Parity Type PT 0 Parity Type PT 1 00 With parity Even parity Odd parity 01 Force parity Low parity
445. nterface e IEEE 1149 1 test STAG module System debug support Real time trace for determining dynamic execution path while in emulator mode Background debug mode BDM for debug features while halted Real time debug support including 6 user visible hardware breakpoint registers supporting a variety of breakpoint configurations Supports comprehensive emulator functions through trace and breakpoint logic On chip PLL Supports processor clock bus clock ratios of 66 33 66 22 66 16 5 90 45 90 30 and 90 22 5 Supports low power mode e Product offerings 75 Dhrystone 2 1 MIPS at 90 MHz Implemented in 0 35 u triple layer metal process technology with 3 3 V operation 5 0 V compliant I O pads 208 pin plastic QFP package 0 70 C operating temperature 1 2 4 Process The MCF5307 is manufactured in a 0 35 u CMOS process with triple layer metal routing technology This process combines the high performance and low power needed for embedded system applications Inputs are 3 3 V tolerant outputs are CMOS or open drain CMOS with outputs operating from VDD 0 5 V to GND 0 5 V with guaranteed TTL level specifications 1 6 MCF5307 User s Manual M woronoLA ColdFire Module Description 1 3 ColdFire Module Description The following sections provide overviews of the various modules incorporated in the 5307 1 3 1 ColdFire Core The Version 4 ColdFire core consists of two independent
446. nual M woronoLA Programming Model Bytes are displayed in least to most significant order The processor captures only those target addresses associated with taken branches which use a variant addressing mode that is RTE and RTS instructions JMP and JSR instructions using address register indirect or indexed addressing modes and all exception vectors The simplest example of a branch instruction using a variant address is the compiled code for a C language case statement Typically the evaluation of this statement uses the variable of an expression as an index into a table of offsets where each offset points to a unique case within the structure For such change of flow operations the MCF5307 uses the debug pins to output the following sequence of information on successive processor clock cycles Use PST 0x5 to identify that a taken branch was executed 2 Using the PST pins optionally signal the target address to be displayed sequentially on the DDATA pins Encodings 0x9 0xB identify the number of bytes displayed 3 The new target address is optionally available on subsequent cycles using the DDATA port The number of bytes of the target address displayed on this port is configurable 2 3 or 4 bytes Another example of a variant branch instruction would be a JMP A0 instruction Figure 5 3 shows when the PST and DDATA outputs that indicate when a JMP A0 executed assuming the CSR was programmed to display the lower 2 byt
447. o separate port width accesses Unlike a burst access SIZ 1 0 11 only for the first port width access for the remaining accesses SIZ 1 0 reflects the port width with individual accesses separated by AS negations The address changes if internal termination is used but does not change if external termination is used as shown in Figure 18 12 and Figure 18 14 M woronoLA Chapter 18 Bus Operation 18 11 Data Transfer Operation 18 4 7 1 Line Transfers A line is a 16 byte aligned 16 byte value Despite the alignment a line access may not begin on the aligned address therefore the bus interface supports line transfers on multiple address boundaries Table 18 5 shows allowable patterns for line accesses Table 18 5 Allowable Line Access Patterns A 3 2 Longword Accesses 00 0 4 8 C 01 4 8 C 0 10 8 C 0 4 11 C 0 4 8 18 4 7 2 Line Read Bus Cycles Figure 18 12 shows line read with zero wait states The access starts like a basic read bus cycle with the first data transfer sampled on the rising edge of S4 but the next pipelined burst data is sampled a cycle later on the rising edge of S6 Each subsequent pipelined data burst is single cycle until the last one which can be held for up to 2 BCLKO cycles after TA is asserted Note that AS and CSx are asserted throughout the burst transfer This example shows the timing for external termination which differs only from the internal termination example in Figur
448. obe 8 63 RW Read Write 8 64 lO Transfer acknowledge 8 65 Power input 66 TS lO Transfer start 8 67 RSTI Reset 68 IRQ7 Interrupt request 69 GND Ground pin 70 IRQ5 IRQ4 Interrupt request 71 IRQ6 Interrupt request 72 TRQT TRQ2 Interrupt request 73 Power input 74 BR request 8 75 BD Bus driven 8 76 BG Bus grant 77 GND Ground pin Chapter 16 Mechanical Data Pinout 16 3 Pinout 16 4 Table 16 2 Pins 53 104 Bottom Left to Right Continued Pn Alternate e Description d No Name 78 TOUT1 Timer output 8 79 TOUTO Timer output 8 80 TINO Timer input 81 VCC Power input 82 TIN1 Timer input 83 RASO DRAM row address strobe 16 84 RAST O DRAM row address strobe 16 85 GND Ground pin 86 CASO DRAM column address strobe 16 87 CAS1 DRAM column address strobe 16 88 CAS2 DRAM column address strobe 16 89 VCC Power input 90 CAS3 DRAM column address strobe 16 91 DRAMW DRAM write 16 92 SRAS SDRAM row address strobe 16 93 GND Ground pin 94 SCAS O SDRAM column address strobe 16 95 SCKE O SDRAM clock enable 16 96 BEO BWEO Byte enable byte w
449. ocessor Status DDATA Definition Table 5 23 PST DDATA Specification for Supervisor Mode Instructions Instruction Operand Syntax PSTDDATA movec Ry Rc PST 0 1 rte PST 0x7 PST 0xB DD source operand PST 3 PST 0xB DD source operand PST 0x5 PST 0 9 DD target address stop imm PST 0 1 PST OxE wdebug lt ea gt y PST 0x1 PST DD source PST 0xB DD source The move to SR and RTE instructions include an optional PST 0x3 value indicating an entry into user mode Additionally if the execution of a RTE instruction returns the processor to emulator mode a multiple cycle status of OxD is signaled Similar to the exception processing mode the stopped state PST OxE and the halted state PST OxF display this status throughout the entire time the ColdFire processor is in the given mode MOTOROLA Chapter 5 Debug Support 5 47 Processor Status DDATA Definition 5 48 MCF5307 User s Manual M woronoLA Part Il System Integration Module SIM Intended Audience Part is intended for users who need to understand the interface between the ColdFire core processor complex described in Part I and internal peripheral devices described in Part III It includes a general description of the SIM and individual chapters that describe components of the SIM such as the phase lock loop PLL timing source interrupt controller for both on chi
450. odulo 32K location in the 4 Gbyte address space and configured to respond to either instruction or data accesses Time critical functions can be mapped into instruction the system stack Other heavily referenced data can be mapped into memory The following summarizes features of the MCF5307 SRAM implementation e 4 Kbyte SRAM organized as 1024 x 32 bits Single cycle throughput When the pipeline is full one access can occur per clock cycle Physical location on the processor s high speed local bus Memory location programmable on any 0 modulo 32K address boundary Byte word and longword address capabilities The RAM base address register RAMBAR defines the logical base address attributes and access types for the SRAM module 4 3 SRAM Operation The SRAM module provides a general purpose memory block that the ColdFire processor can access with single cycle throughput The location of the memory block can be specified to any word aligned address in the 4 Gbyte address space by described in Section 4 4 1 SRAM Base Address Register RAMBAR The memory is ideal for storing critical code or data structures or for use as the system stack Because the SRAM module connects physically to the processor s high speed local bus it can service processor initiated accesses or memory referencing debug module commands Instruction fetches and data reads can be sent to both the cache and SRAM blocks simultaneously
451. on 19 6 Disabling IEEE Standard 1149 1 Operation There are two ways to use the MCF5307 without IEEE Standard 1149 1 test logic being active e Nonuse of JTAG test logic by either nontermination disconnection or intentionally fixing TAP logic values The following issues must be addressed if IEEE Standard 1149 1 logic is not to be used when the MCF5307 is assembled onto a board IEEE Standard 1149 1 test logic must remain transparent and benign to the system logic during functional operation To ensure that the part enters the test logic reset state requires either connecting TRST to logic 0 or connecting TCK to a source that supplies five rising edges and a falling edge after the fifth rising edge The recommended solution is to connect TRST to logic 0 TCK has no internal pull up as is required on TMS TDI and TRST therefore it must be terminated to preclude mid level input values Figure 19 4 shows pin values recommended for disabling JTAG with the MCF5307 in JTAG mode VDD TMS BKPT TDI DSI 1 TRST DSCLK Note MTMODO high allows JTAG mode Figure 19 4 Disabling JTAG in JTAG Mode e Disabling JTAG test logic by holding MTMODO low during reset debug mode This allows the IEEE Standard 1149 1 test controller to enter test logic reset state when TRST is internally asserted to the controller TAP pins function as debug mode pins In JTAG mode inputs TDI DSI TMS BKPT and TRST DSCLK have
452. on Summary Figure 4 11 shows the three possible cache line states and possible processor initiated transitions for memory configured as copyback Transitions are labeled with a capital letter indicating the previous state and a number indicating the specific case listed in Table 4 11 CV1 CPU read miss CV2 CPU read hit CV7 CPUSHL amp DPI CI5 CINVA CI6 CPUSHL amp DPI CI7 CPUSHL amp DPI CI1 CPU read miss CV5 CINVA CV6 CPUSHL amp DPI U CD1 CPU read miss CD5 CINVA CD6 CPUSHL amp DPI CV3 CPU write miss CV4 CPU write hit CD2 CPU read hit CD3 CPU write miss CD4 CPU write hit Figure 4 11 Cache Line State Diagram Copyback Mode Figure 4 12 shows the two possible states for a cache line in write through mode WV1 CPU read miss WI3 CPU write miss WV2 CPU read hit WI5 CINVA WV3 CPU write miss BU WV4 CPU write hit WI1 CPU read miss WVZ OPUSHE amp DPI Invalid Valid WV5 CINVA WV6 CPUSHL amp DPI Figure 4 12 Cache Line State Diagram Write Through Mode Table 4 6 describes cache line transitions and the accesses that cause them 4 26 MCF5307 User s Manual M Cache Operation Summary Table 4 6 Cache Line State Transitions Current State Access Invalid V 0 Valid V 1 M 0 Modified V 1 M 1 Read C W I1 Read line from C W V1 Read n
453. on a 32 bit port Should an address and attribute match both DACRs or a DACR and a CSCR the operation is undefined Table 10 3 shows the type of access as a function of match in the CSCRs and DACRs Table 10 3 Accesses by Matches in CSCRs and DACRs Number of CSCR Matches Number of DACR Matches Type of Access 0 0 External 1 0 Defined by CSCR Multiple 0 External burst inhibited 32 bit 0 1 Defined by DACRs 1 1 Undefined Multiple 1 Undefined 0 Multiple Undefined 1 Multiple Undefined Multiple Multiple Undefined M MOTOROLA Chapter 10 Chip Select Module 10 3 Chip Select Operation 10 3 1 1 8 16 and 32 Bit Port Sizing Static bus sizing is programmable through the port size bits CSCR PS See Section 10 4 1 3 Chip Select Control Registers CSCRO CSCR7 Figure 10 1 shows the correspondence between data byte lanes and the external chip select memory Note that all lanes are driven although unused lines are undefined BEO BE1 BE2 BE3 Ext Gata bus DI31 24 D 23 316 15 8 0 7 0 32 bit port SO 0 B 1 Byte 2 Byte 3 16 bit port memory Byte 0 EN Driven undefined Byte 2 Byte 3 8 bit port memory Byte 0 Byte 1 Driven undefined Byte 2 Byte 3 Figure 10 1 Connections for External Memory Port Sizes 10 3 1 2 Global Chip Select Operation CSO the global boot chip select allows address d
454. on information are sampled during reset Normal mode In normal mode the input frequency programmed at reset is clock multiplied to provide the processor clock PCLK Reduced power mode In reduced power mode the PCLK is disabled by executing a sequence that includes programming a control bit in the system configuration register SCR and then executing the STOP instruction Register contents are retained in reduced power mode so the system can be reenabled quickly when an unmasked interrupt or reset is detected 1 4 Programming Model Addressing Modes and Instruction Set The ColdFire programming model has two privilege levels supervisor and user The S bit in the status register SR indicates the privilege level The processor identifies a logical address that differentiates between supervisor and user modes by accessing either the supervisor or user address space 1 12 User mode When the processor is in user mode SR S 0 only a subset of registers can be accessed and privileged instructions cannot be executed Typically most application processing occurs in user mode User mode is usually entered by executing a return from exception instruction RTE assuming the value of SR S saved on the stack is 0 or a MOVE SR instruction assuming SR S is 0 Supervisor mode This mode protects system resources from uncontrolled access by users In supervisor mode complete access is provided to all registers and the entire
455. onditions are true during a cache inhibited read The cache inhibited fill buffer bit CACR DNFB is set The access is an instruction read The access is normal that is transfer type TT equals 0 In this case an entire line is fetched and stored in the fill buffer It remains valid there and the cache can service additional read accesses from this buffer until either another fill or a cache invalidate all operation occurs Valid cache entries that match during cache inhibited address accesses are neither pushed nor invalidated Such a scenario suggests that the associated cache mode for this address space was changed To avoid this it is generally recommended to use the CPUSHL instruction to push or invalidate the cache entry or set CACR CINVA to invalidate the cache before switching cache modes 4 9 1 Caching Modes For every memory reference generated by the processor or debug module a set of effective attributes is determined based on the address and the ACRs Caching modes determine how the cache handles an access An access can be cacheable in either write through or copyback mode it can be cache inhibited in precise or imprecise modes For normal accesses the ACRn CM bit corresponding to the address of the access specifies the caching modes If an address does not match an ACR the default caching mode is defined by CACR DCM The specific algorithm is as follows if address ACRO address including mask effectiv
456. only R W through debug module only the debug module can read MBAR Address CPU 0 0 Figure 6 2 Module Base Address Register MBAR 6 4 MCF5307 User s Manual M woronoLA Programming Model Table 6 2 describes MBAR fields Table 6 2 MBAR Field Descriptions Bits Field Description 31 12 Base address Defines the base address for a 4 Kbyte address range 11 9 Reserved should be cleared 8 WP Write protect Mask bit for write cycles in the MBAR mapped register address range 0 Module address range is read write 1 Module address range is read only Reserved should be cleared 6 AM Alternate master mask When AM 0 and an alternate master external master or DMA accesses MBAR mapped registers MBAR SC SD UC UD are ignored in address decoding These fields mask address space placing the MBAR mapped register in a specific address space or spaces 5 Mask CPU space and interrupt acknowledge cycles 0 Activates the corresponding MBAR mapped register 1 Regular external bus access 4 SC Setting masks supervisor code space in MBAR address range 3 SD Setting masks supervisor data space in MBAR address range 2 UC Setting masks user code space in MBAR address range 1 UD Setting masks user data space in MBAR address range 0 V Valid Determines whether MBAR settings are valid 0 MBAR contents are invalid 1 MBAR contents are valid
457. ontinuous page mode access the page is closed RAS precharged when the data transfer completes to allow the refresh to occur The flag is cleared when the refresh cycle is run Both memory blocks are simultaneously refreshed as determined by the DCR DRAM accesses are delayed during refresh Only an active bus access to a DRAM block can delay refresh Figure 11 12 shows a bus cycle delayed by a refresh operation Notice that DRAMW is forced high during refresh The row address is held until the pending DRAM access BCLKO ABO X RAS 1 or 0 CAS 3 0 DRAMW 7 Refresh 14 Access Figure 11 12 DRAM Access Delayed by Refresh 11 4 Synchronous Operation By running synchronously with the system clock instead of responding to asynchronous control signals SDRAM can after an initial latency period be accessed on every clock 5 1 1 1 is a typical MCF5307 burst rate to SDRAM Note that because the MCF5307 cannot have more than one page open at a time it does not support interleaving SDRAM controllers are more sophisticated than asynchronous DRAM controllers Not only must they manage addresses and data but they must send special commands for such functions as precharge read write burst auto refresh and various combinations of these functions Table
458. ontrol PCLK to BCLKO DIVIDET 1 0 17 15 Chip Select Module Signals sese 17 15 Chip Select CSIO e ert eret aee tet net eee eee eevee ie 17 16 Byte Enables Byte Write Enables BE 3 0 BWE 3 0 17 16 Output Enable 17 16 DRAM Controller Signals sese 17 16 Row Address Strobes RAS 1 0 essen 17 16 Column Address Strobes 3 0 17 16 DRAM Write DRAMW Ja 17 17 Synchronous DRAM Column Address Strobe SCAS 17 17 Synchronous DRAM Row Address Strobe 17 17 Synchronous DRAM Clock Enable SCKE eese 17 17 Synchronous Edge Select EDGESEL eee 17 17 DMA Controller Module 12 5 17 17 DMA Request DREQ I 0 PP 6 5 eere 17 18 Serial Module Signals essere 17 18 Transmitter Serial Data Output TxD eene 17 18 Receiver Serial Data Input RxD eene 17 18 Glear to Send CTS iam a eese aee deae ae UR ERES 17 18 Request to Send RES correr em eme tr eren tr eue on 17 18 Timer Module Signals sse 17 18 Timer Inputs TINEO ones itii trt rti ee 17 19 Timer
459. onventional fixed length RISC architectures The denser binary code for ColdFire processors consumes less memory than many fixed length instruction set RISC processors available This improved code density means more efficient system memory use for a given application and allows use of slower less costly memory to help achieve a target performance level The MCF5307 is the first standard product to implement the Version 3 ColdFire microprocessor core To reach higher levels of frequency and performance numerous enhancements were made to the V2 architecture Most notable are a deeper instruction pipeline branch acceleration and a unified cache which together provide 75 Dhrystone 2 1 MIPS at 90 MHz Increasing the internal speed of the core also allows higher performance while providing the system designer with an easy to use lower speed system interface The processor complex frequency is an integer multiple 2 to 4 times of the external bus frequency The core clock can be stopped to support a low power mode Serial communication channels are provided by an PC interface module and two programmable full duplex UARTs Four channels of DMA allow for fast data transfer using a programmable burst mode independent of processor execution The two 16 bit general purpose multimode timers provide separate input and output signals For system protection the processor includes a programmable 16 bit software watchdog timer In addition common system functio
460. onverter Devices connected to the must have open drain or open collector outputs 17 12 1 1 Serial Clock SCL The bidirectional open drain PC serial clock signal SCL is the clock signal for module operation The module controls this signal when the bus is in master mode all devices drive this signal to synchronize PC timing 17 12 2 I C Serial Data SDA The bidirectional open drain serial data signal SDA is the data input output for the serial interface MOTOROLA Chapter 17 Signal Descriptions 17 19 Debug and Test Signals 17 13 Debug and Test Signals The signals in this section interface with external I O to provide processor status signals 17 13 1 Test Mode MTMOD 3 0 The test mode signals choose between multiplexed debug module and JTAG signals If MTMODO is low the part is in normal and background debug mode BDM if it is high it is in normal and JTAG mode All other MTMOD values are reserved MTMOD 3 1 should be tied to ground and MTMOD 3 0 should not be changed while RSTI is negated 17 13 2 High Impedance HIZ The assertion of HIZ forces all output drivers to high impedance state The timing on HIZ is independent of the clock Note that HIZ does not override the JTAG operation TDO DSO can be forced to high impedance by asserting TRST 17 13 3 Processor Clock Output PSTCLK The internal PLL generates this output signal and is the processor clock output tha
461. op bit and setting bit 3 selects 2 stop bits for transmission SB 5Bits 6 8 Bits SB 5Bits 6 8 Bits SB 5 8 Bits SB 5 8 Bits 0000 1 063 0 563 0100 1 313 0 813 1000 1 563 1100 1 813 0001 1 125 0 625 0101 1 375 0 875 1001 1 625 1101 1 875 0010 1 188 0 688 0110 1 438 0 938 1010 1 688 1110 1 938 0011 1 250 0 750 0111 1 500 1 000 1011 1 750 1111 2 000 14 3 3 UART Status Registers USRn The USRn Figure 14 4 shows status of the transmitter the receiver and the FIFO 7 6 5 4 3 2 1 0 Field RB FE PE OE TxRDY FFULL RxRDY Reset 0000 0000 R W Read only Address MBAR 0x1C4 USRO 0x204 USR1 Figure 14 4 UART Status Register USRn Table 14 4 describes USRn fields Table 14 4 USRn Field Descriptions Bits Name Description 7 RB Received break The received break circuit detects breaks that originate in the middle of a received character However a break in the middle of a character must persist until the end of the next detected character time 0 No break was received 1 An all zero character of the programmed length was received without a stop bit RB is valid only when RxRDY 1 Only a single FIFO position is occupied when a break is received Further entries to the FIFO are inhibited until RxD returns to the high state for at least one half bit time which is equal to two successi
462. opcodes plus the PULSE and WDDATA instructions generate different encodings 0x2 0010 Reserved 0x3 0011 Entry into user mode Signaled after execution of the instruction that caused the ColdFire processor to enter user mode 0 4 0100 Begin execution of PULSE and WDDATA instructions PULSE defines logic analyzer triggers for debug and or performance analysis WDDATA lets the core write any operand byte word or longword directly to the DDATA port independent of debug module configuration When WDDATA is executed a value of 0x4 is signaled on the PST port followed by the appropriate marker and then the data transfer on the DDATA port Transfer length depends on the WDDATA operand size 0x5 0101 Begin execution of taken branch For some opcodes a branch target address may be displayed on DDATA depending on the CSR settings CSR also controls the number of address bytes displayed indicated by the PST marker value preceding the DDATA nibble that begins the data output See Section 5 3 1 Begin Execution of Taken Branch PST 0 5 0x6 0110 Reserved 0 7 0111 Begin execution of return from exception RTE instruction 0x8 0xB 1000 1011 Indicates the number of bytes to be displayed on the DDATA port on subsequent clock cycles The value is driven onto the PST port one clock PSTCLK cycle before the data is displayed on DDATA 0 8 Begin 1 byte transfer on DDATA Ox9 Be
463. operation 0 10 MHz J1 TCK cycle time 100 nS J2a clock pulse high width measured at 1 5 V 40 nS J2b clock pulse low width measured at 1 5 V 40 nS J3a fall time Vi 2 4 V to 0 5V 5 nS J3b TCK rise time 0 5v to 2 4V 5 ns J4 TDI TMS to TCK rising input setup 10 ns J5 TCK rising to TDI TMS invalid hold 15 nS J6 Boundary scan data valid to TCK setup 10 nS J7 TCK to boundary scan data invalid hold 15 nS J8 TRST pulse width asynchronous to clock edges 15 J9 TCK falling to TDO valid signal from driven or 30 nS three state TCK falling to TDO high impedance 30 nS J11 TCK falling to boundary scan data valid signal from 30 ns driven or three state J12 TCK falling to boundary scan data high impedance 30 nS Figure 20 19 shows JTAG timing 20 20 MCF5307 User s Manual M MOTOROLA IEEE 1149 1 JTAG AC Timing Specifications TCK lA TDI TMS X X 16 1 1 s BOUNDARY SCAN DATA X X INPUT 7 1 1 4 2 TDO lt gt scs BOUNDARY OUTPUT A lt gt Figure 20 19 IEEE 1149 1 JTAG AC Timing M woronoLA Chapter 20 Electrical Specifications 20 21 IEEE 1149 1 JTAG AC Timing Specifications 20 22 MCF5307 User s Manual M woronoLA Appendix A List of Memory Maps Table A 1 SIM Registers
464. or MOVE L instructions accessing program visible registers of the MAC unit along with other MOVE L timings Execution times for moving contents of the ACC or MACSR into a destination location represent the best case scenario when the store instruction is executed and there are no load or MAC or MSAC instruction 2 42 MCF5307 User s Manual M woronoLA Instruction Timing in the MAC execution pipeline Table 2 12 MAC Move Execution Times Effective Address Opcode ea Rn An An An d16 An d amp An Xi SF xxx wl lt gt 1 lt ea gt ACC 1 0 0 1 0 0 move lt ea gt MACSR 2 0 0 2 0 0 move lt ea gt MASK 1 0 0 1 0 0 move ACC Rx 3 0 0 move l MACSR CCR 3 0 0 move l MACSR Rx 3 0 0 move MASK Rx 3 0 0 2 7 2 Execution Timings One Operand Instructions Table 2 13 shows standard timings for single operand instructions Table 2 13 One Operand Instruction Execution Times Effective Address Opcode ea Rn An An An d16 An d8 An Xi SF xxx wl XXX clr b lt ea gt 1 0 0 1 0 1 1 0 1 1 0 1 1 0 1 2 0 1 1 0 1 clr w lt ea gt 1 0 0 1 0 1 1 0 1 1 0 1 1 0 1 2 0 1 1 0 1 lt gt 1 0 0 1 0 1 1 0 1 1 0 1 1 0 1 2 0
465. ory Block 0 Hit Logic DRAMW DRAM Address Control Register 0 SCAS These signals 0 DRAM Control Register DCR _ SDRAM only Memory Block 1 Hit Logic DRAM Address Control Register 1 Refresh Counter DACR1 L 4 Figure 11 1 Asynchronous Synchronous DRAM Controller Block Diagram The DRAM controller s major components shown in Figure 11 1 are described as follows DRAM address and control registers DACRO and DACR1 The DRAM controller consists of two configuration register units one for each supported memory block DACRO is accessed at MBAR 0x0108 DACRI is accessed at 0x010 The register information is passed on to the hit logic 11 2 MCF5307 User s Manual M woronoLA DRAM Controller Operation Control logic and state machine Generates all DRAM signals taking bus cycle characteristic data from the block logic along with hit information to generate DRAM accesses Handles refresh requests from the refresh counter DRAM control register DCR Contains data to control refresh operation of the DRAM controller Both memory blocks are refreshed concurrently as controlled by DCR RC Refresh counter Determines when refresh should occur determined by the value of DCR RC It generates a refresh request to the control block Hitlogic Compares address and attribute signals of a current DRAM bus cycle to both DACRs to determine if a DRAM block
466. ound pin Table 16 4 Pins 157 208 Top Right to Left di ELE Description mA No Name 157 VCC Power input 158 CTS1 m UARTI clear to send 159 RTS1 O UART1 request to send 8 160 RXD1 UARTI receive data 161 TXD1 UART1 transmit data 8 162 GND Ground pin 163 50 UARTO clear to send 164 RTSO O UARTO request to send 8 165 RXDO UARTO receive data 166 TXDO UARTO transmit data 8 167 Power input 168 EDGESEL SDRAM bus clock edge select 169 GND Ground 170 BCLKO O Bus clock output 16 16 6 MCF5307 User s Manual M MOTOROLA Pinout Table 16 4 Pins 157 208 Top Right to Left Continued a Description s No Name 171 Power input 172 RSTO Processor reset output 8 173 GND Ground 174 CLKIN Clock input gt 175 Power input 176 MTMODO JTAG BDM select Tie high or low 177 MTMOD1 Tie high or low 178 PGND PLL ground pin 179 NC 180 PVCC Filter supply for PLL 181 MTMOD2 high or low 182 MTMOD3 Tie high or low 183 GND Ground 184 PSTCLK O Processor status clock 8 185 Power inp
467. ows timing for basic back to back bus cycles during an external master transfer C1 c2 C3 C4 C5 C6 C7 C8 C9 CH BCLKO sito TM _ X UJ BR BG BD 2 HOLDREQ External Master H Depending on programming these signals may or may not be driven by the processor This signal is driven by the processor for an external master transfer Figure 18 24 Basic No Wait State External Master Access R W is asserted high for reads and low for writes otherwise the transfers are the same In Figure 18 24 the MCF5307 chip select s internal transfer acknowledge is enabled and the MCF5307 drives TA as an output after a programmed number of wait states 18 22 MCF5307 User s Manual M woronoLA General Operation of External Master Transfers NOTE Bus timing diagrams for external master transfers are not valid for on chip internal four channel DMA accesses on the 5307 Timing diagrams describe transactions in general terms of bus cycles Cn rather than the states Sn used in the bus diagrams Table 18 8 defines the cycles for Figure 18 24 Table 18 8 Cycles for Basic No Wait State External Master Access Cycle Definition C1 The external master asserts HOLDREQ signaling the MCF5307 to hold bus requests BD should not be asserted The ext
468. p and external peripherals configuration and operation of chip selects and the SDRAM controller Contents Part II contains the following chapters Chapter 6 SIM Overview describes the SIM programming model bus arbitration and system protection functions for the MCF5307 Chapter 7 Phase Locked Loop PLL describes configuration and operation of the PLL module It describes in detail the registers and signals that support the PLL implementation Chapter 8 I2C Module describes the MCF5307 I2C module including I2C protocol clock synchronization and the registers in the I2C programing model It also provides extensive programming examples Chapter 9 Interrupt Controller describes operation of the interrupt controller portion of the SIM Includes descriptions of the registers in the interrupt controller memory map and the interrupt priority scheme Chapter 10 Chip Select Module describes the MCF5307 chip select implementation including the operation and programming model which includes the chip select address mask and control registers Chapter 11 Synchronous Asynchronous DRAM Controller Module describes configuration and operation of the synchronous asynchronous DRAM controller component of the SIM It begins with a general description and brief glossary and M Part Il System Integration Module SIM 1 includes a description of signals involved in DRAM operations Th
469. page mode The following sections describe the DRAM controller interface to SDRAM the supported bus transfers and initialization 11 4 4 1 Address Multiplexing Table 11 6 shows the generic address multiplexing scheme for SDRAM configurations All possible address connection configurations can be derived from this table The following tables provide a more comprehensive step by step way to determine the correct address line connections for interfacing the MCF5307 to SDRAM To use the MOTOROLA Chapter 11 Synchronous Asynchronous DRAM Controller Module 11 23 Synchronous Operation tables find the one that corresponds to the number of column address lines on the SDRAM and to the port size as seen by the MCF5307 which is not necessarily the SDRAM port size For example if two 1M x 16 bit SDRAMs together form a 2M x 32 bit memory the port size is 32 bits Most SDRAMs likely have fewer address lines than are shown in the tables so follow only the connections shown until all SDRAM address lines are connected Table 11 15 MCF5307 to SDRAM Interface 8 Bit Port 9 Column Address Lines MCF5307 A17 A16 A15 A14 A13A12 A11 A10 A9 A18 A19 A20 21 22 23 A24 A25 A26 27 A28 A29 A30 A31 Pins Row 17 16 15 14 13 12 11 10 9 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Column 0111213141516 718 SDRAM A1 A2 A4 AG A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A1
470. pecified Figure 4 10 shows the An format 31 11 10 4 3 0 0 Set Index Line Index Figure 4 10 An Format The following code example flushes the entire cache cache disable nop move w 0x2700 SR mask off IRQs jsr cache flush flush the cache completely clr l do movec d0 ACRO ACRO off movec dO ACRI ACR1 off move l 0x01000000 d0 Invalidate and disable cache movec d0 CACR rts cache flush nop Ssynchronize flush store buffer moveq 1 0 d0 initialize way counter moveg 1 0 d1 initialize set counter move l d0 a0 initialize cpushl pointer setloop cpushl bc a0 push cache line a0 add 1 0x0010 a0 increment set index by 1 addq 1 1 91 increment set counter 1 128 1 are sets for this way done bne setloop moveq 1 0 1 set counter to zero again addq 1 1 40 increment to next way 4 24 MCF5307 User s Manual M woronoLA Cache Operation Summary move l 90 0 set 0 way d0 cmpi l 4 d0 flushed all the ways bne setloop rts The following CACR loads assume the default cache mode is copyback CacheLoadAndLock move l 0xA1000100 d0 enable and invalidate cache movec dO cacr in the CACR The following code preloads half of the cache 4 Kbytes It assumes a contiguous block of data is to be mapped into the cache starting at a 0 modulo A4K address move l 256 d0 256 16 byte lines in 4K space lea data a0 load pointer defining
471. pendent of TM 2 1 If DCR SAA is set TMO designates a single address DMA access 12 2 MCF5307 User s Manual M DMA Transfer Overview 12 3 DMA Transfer Overview The DMA module usually transfers data faster than the ColdFire core can under software control The term direct memory access refers to peripheral device s ability to access system memory directly greatly improving overall system performance The DMA module consists of four independent functionally equivalent channels so references to DMA in this chapter apply to any of the channels It is not possible to implicitly address all four channels at once The MCF5307 on chip peripherals do not support single address transfers The processor generates DMA requests internally by setting DCR START a device can generate a DMA request externally by using DREQ pins The processor can program bus bandwidth for each channel The channels support cycle steal and continuous transfer modes see Section 12 5 1 Transfer Requests Cycle Steal and Continuous Modes The DMA controller supports dual and single address transfers as follows In both the DMA channel supports 32 address bits and 32 data bits e Dual address transfers A dual address transfer consists of a read followed by a write and is initiated by an internal request using the START bit or by an external device using DREQ Two types of transfer can occur a read from a source device or a write to a
472. perating system to check for trace mode after processing other exception types As an example consider a TRAP instruction executing in trace mode The processor initiates the TRAP exception and passes control to the corresponding handler If the system requires that a trace exception be processed the TRAP exception handler must check for this condition SR 15 in the exception stack frame asserted and pass control to the trace handler before returning from the original exception Debug Interrupt Caused by a hardware breakpoint register trigger Rather than generating an IACK cycle the processor internally calculates the vector number 12 Additionally the M bit and the interrupt priority mask fields of the SR are unaffected by the interrupt See Section 2 2 2 1 Status Register SR RTE and Format Error Exceptions When an RTE instruction executes the processor first examines the 4 bit format field to validate the frame type For a ColdFire processor any attempted execution of an RTE where the format is not equal to 4 5 6 7 generates a format error The exception stack frame for the format error is created without disturbing the original exception frame and the stacked PC points to RTE The selection of the format value provides limited debug support for porting code from M68000 applications On M68000 Family processors the SR was at the top of the stack Bit 30 of the longword addressed by the System stack pointer is typi
473. pin listing and package diagram for the MCF5307 Chapter 17 Signal Descriptions provides an alphabetical listing of MCF5307 signals This chapter describes the MCF5307 signals In particular it shows which are inputs or outputs how they are multiplexed which signals require pull up resistors and the state of each signal at reset Chapter 18 Bus Operation describes data transfers error conditions bus arbitration and reset operations It describes transfers initiated by the MCF5307 and by an external bus master and includes detailed timing diagrams showing the interaction of signals in supported bus operations Note that Chapter 11 Synchronous Asynchronous DRAM Controller Module describes DRAM cycles Chapter 19 IEEE 1149 1 Test Access Port JTAG describes configuration and operation of the MCF5307 JTAG test implementation It describes the use of JTAG instructions and provides information on how to disable JTAG functionality Chapter 20 Electrical Specifications describes AC and DC electrical specifications and thermal characteristics for the MCF5307 Because additional speeds may have become available since the publication of this book consult Motorola s ColdFire web page http www motorola com coldfire to confirm that this is the latest information M MOTOROLA Part IV Hardware Interface IV i Suggested Reading The following literature may be helpful with respect to the topics in Part IV
474. plicit Explicit Mastership Mastership External Master MCF5307 Figure 18 30 Three Wire Implicit and Explicit Bus Mastership In Figure 18 30 the external device is bus master during C1 and C2 releasing control in C3 at which time the external arbiter asserts BG to the MCF5307 During C4 and C5 the MCF5307 is implicit master because no internal access is pending In C5 an internal bus request becomes pending causing the MCF5307 to take explicit bus mastership in C6 by asserting BR and BD In C7 the external device removes the bus grant to the MCF5307 The MCF5307 does not release the bus the MCF5307 asserts BD until the transfer ends NOTE The MCF5307 can start a transfer in the cycle after BG is asserted The external arbiter should not assert BG to the MCF5307 until the previous external master stops driving the bus Asserting BG during another external master s transfer may damage the part 18 30 MCF5307 User s Manual M MOTOROLA General Operation of External Master Transfers C1 C2 C4 C5 C6 C7 C8 C9 lt lt lt lt lt lt lt lt lt gt BCLKO A 31 0 TT 1 0 SIZ 1 0 TM 2 0 X ENSE D 31 0 TA BR External MCF5307 Master Figure 18 31 Three Wire Bus Arbitration In Figure 18 31 the external device is bus master during C1 an
475. products for any such unintended or unauthorized application Buyer shall indemnify and hold Motorola and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part Motorola and are registered trademarks of Motorola Inc Motorola Inc is an Equal Opportunity Affirmative Action Employer How to reach us USA EUROPE Locations Not Listed Motorola Literature Distribution Box 5405 Denver Colorado 80217 1 303 675 2140 or 1 800 441 2447 JAPAN Motorola Japan Ltd SPS Technical Information Center 3 20 1 Minami Azabu Minato ku Tokyo 106 8573 Japan 81 3 3440 3569 ASIA PACIFIC Motorola Semiconductors H K Ltd Silicon Harbour Centre 2 Dai King Street Tai Po Industrial Estate Tai Po N T Hong Kong 852 26668334 Technical Information Center 1 800 521 6274 HOME PAGE hitp www motorola com semiconductors Document Comments FAX 512 895 2638 Attn RISC Applications Engineering World Wide Web Addresses http www motorola com PowerPC http www motorola com NetComm http www motorola com ColdFire Motorola Inc 2000 All rights reserved Overview Part MCF5307 Processor Core
476. put 17 18 send 17 18 transmitter serial data output 17 18 size 17 8 timer module 17 18 transfer acknowledge 17 9 in progress 17 10 modifier 17 10 start 17 9 Signals overview 17 1 SIM features 6 1 programming model 6 3 register memory map 6 3 Software watchdog interrupt vector register 6 9 service register 6 9 timer 6 6 STOP instruction 5 4 5 17 System protection control register 6 8 T Timer module calculating time out values 13 7 capture registers 13 4 code example 13 6 counters 13 5 event registers 13 5 general purpose programming model 13 2 mode registers 13 3 reference registers 13 4 Timing MAC unit instructions 3 5 PLL 7 4 RSTI 7 5 Transfers generated internally 6 12 U UART modules bus operation interrupt acknowledge cycles 14 28 read cycles 14 28 M MOTOROLA Index write cycles 14 28 clock source baud rates 14 19 external clock 14 19 FIFO stack in UARTO 14 24 initialization sequence 14 29 looping modes 14 25 automatic echo 14 25 local loop back 14 25 remote loop back 14 26 mode registers 14 4 multidrop mode 14 26 programming 14 28 receiver enabled 14 22 register description 14 2 serial overview 14 2 signal definitions 14 16 transmitter receiver clock source 14 18 modes 14 19 transmitting in UART mode 14 21 User programming model 2 27 V Variant address 5 5 Vector base register 2 30 WDDATA execution 5 4 Index 21 INDEX
477. pyback read new line from memory and update cache write push buffer contents to memory stay in modified state Write miss WD3 Write data to memory write through stay in modified state Cache mode changed for the region corresponding to this line To avoid this state execute a CPUSHL instruction or set CACR CINVA before switching modes Write hit CD4 Write data to cache copyback stay in modified state Write hit WD4 Write data to memory and to cache write through go to valid state Cache mode changed for the region corresponding to this line To avoid this state execute a CPUSHL instruction or set CACR CINVA before switching modes Cache invalidate CD5 No action modified data lost go to invalid state Cache push CD6 Push modified line to memory go to invalid state Cache push CD7 Push modified line to memory go to valid state 4 13 Cache Initialization Code The following example sets up the cache for FLASH or ROM space only move 140x81000300 D0 enable cache invalidate it default mode is cache inhibited imprecise movecD0 CACR move l 0xFF00C000 D0 cache FLASH space enable ignore FC2 cacheable writethrough movecDO ACRO M Chapter 4 Local Memory 4 29 Cache Initialization Code 4 30 MCF5307 User s Manual M woronoLA Chapter 5 Debug Support This chapter describes the Revision B enhanced hardware debug support in the
478. quotient Dy lt ea gt x iL Dx ea y Dx 32 bit quotient Unsigned operation EOR Dy lt ea gt x Source destination destination EORI lt data gt Dx Immediate data destination destination EXT lt data gt Dx Bw Sign extended destination destination Dx BL Sign extended destination destination HALT None Unsized Enter halted state JMP ea 3 y Unsized Address of ea gt PC JSR ea 3 y Unsized SP 4 SP next sequential PC SP ea gt PC LEA ea 3 y Ax L ea Ax LINK Ax lt d16 gt W SP 4 SP SP SP Ax SP 916 gt SP LSL Dy Dx 1 Dx lt lt Dy 0 lt data gt Dx L X C lt lt lt lt data gt lt 0 LSR Dy Dx 0 Dx gt gt Dy X C lt data gt Dx L 0 Dx gt gt lt data gt gt X C MAC RxSF L Wx W L ACC Ry x Rx lt lt 1 gt gt 1 ACC L Lx L L ACC Ry x Rx lt lt 1 gt gt 1 ACC lt ea gt y amp MASK Rw MACL Ry RxSF lt ea 1 gt y Rw L x L L ACC Ry x Rx lt lt 1 gt gt 1 ACC L Lx L L L ACC Ry x Rx lt lt 1 gt gt 1 lt ea 1 gt y amp MASK Rw MOVE lt gt lt gt B W L ea y ea x MOVE from MASK Rx L Rm Rx MAC ACC Rx MACSR Rx MACSR CCR L MACSR CCR MOVE to Ry ACC L Ry gt Rm MAC Ry MACSR Ry MASK lt data gt ACC L lt data gt gt Rm lt
479. r and CPU to receiver communications continue normally in this mode RxD input data is ignored e TxD is held marking The receiver is clocked by the transmitter clock The transmitter must be enabled but the receiver need not be 14 5 3 3 Remote Loop Back Mode In remote loop back mode shown in Figure 14 25 the channel automatically transmits received data bit by bit on the TxD output The local CPU to transmitter link is disabled This mode is useful in testing receiver and transmitter operation of a remote channel For this mode the transmitter uses the receiver clock Because the receiver is not active received data cannot be read by the CPU and error status conditions are inactive Received parity is not checked and is not recalculated for transmission Stop bits are sent as they are received A received break is echoed as received until the next valid start bit is detected Disabled Disabled RxD Input CPU Disabled Disabled TxD Input Figure 14 25 Remote Loop Back 14 5 4 Multidrop Mode Setting UMRIn PM programs the UART to operate in a wake up mode for multidrop or multiprocessor applications In this mode a master can transmit an address character followed by a block of data characters targeted for one of up to 256 slave stations Although slave stations have their channel receivers disabled they continuously monitor the master s data stream When the master sends an a
480. r is held in the receiver shift register until space is available However if a second new character is received the contents of the the character in the receiver shift register is lost the FIFOs are unaffected and USRn OE is set when the receiver detects the start bit of the new overrunning character To support flow control the receiver can be programmed to automatically negate and assert RTS in which case the receiver automatically negates RTS when a valid start bit is detected and the FIFO stack is full The receiver asserts RTS when a FIFO position becomes 14 24 MCF5307 User s Manual M Operation available therefore overrun errors can be prevented by connecting RTS to the CTS input of the transmitting device NOTE The receiver can still read characters in the FIFO stack if the receiver is disabled If the receiver is reset the FIFO stack RTS control all receiver status bits and interrupt requests are reset No more characters are received until the receiver is reenabled 14 5 3 Looping Modes The UART can be configured to operate in various looping modes as shown in Figure 14 22 on page 14 23 These modes are useful for local and remote system diagnostic functions The modes are described in the following paragraphs and in Section 14 3 Register Descriptions The UART s transmitter and receiver should be disabled when switching between modes The selected mode is activated immediately upon mode sele
481. r of the sizes specified by SSIZE and DSIZE See Section 12 4 4 DMA Control Registers DCRO DCR3 Source and destination address registers SAR and DAR can be programmed in the DCR M woronoLA Chapter 12 DMA Controller Module 12 11 DMA Controller Module Functional Description to increment at the completion of a successful transfer BCR decrements when an address transfer write completes for a single address access DCR SAA 0 or when SAA 1 12 5 1 Transfer Requests Cycle Steal and Continuous Modes The DMA channel supports internal and external requests A request is issued by setting DCR START or by asserting DREQ Setting DCR EEXT enables recognition of external interrupts Internal interrupts are always recognized Bus usage is minimized for either internal or external requests by selecting between cycle steal and continuous modes e Cycle steal mode DCR CS 1 Only one complete transfer from source to destination occurs for each request If DCR EEXT is set a request can be either internal or external Internal request is selected by setting DCR START An external request is initiated by asserting DREQ while EEXT is set Continuous mode DCR CS 0 After an internal or external request the DMA continuously transfers data until BCR reaches zero or a multiple of DCR BWC or DSR DONE is set If BCR is a multiple of BWC the DMA request signal is negated until the bus cycle terminates to allow the inte
482. r sizes If the BCR decrements to a multiple of the decode of the BWC the DMA bus request negates until the bus cycle terminates If a request is pending the arbiter may then pass bus mastership to another device If auto alignment is enabled DCR AA 1 the BCR may skip over the programmed boundary in which case the DMA bus request is not negated If BWC z 000 the request signal remains asserted until BCR reaches zero DMA has priority over the core Note that in this scheme the arbiter can always force the DMA to relinquish the bus See Section 6 2 10 1 Default Bus Master Park Register MPARK 12 5 5 Termination An unsuccessful transfer can terminate for one of the following reasons Error conditions When the MCF5307 encounters a read or write cycle that terminates with an error condition DSR BES is set for a read and DSR BED is set for a write before the transfer is halted If the error occurred in a write cycle data in the internal holding register is lost e Interrupts If DCR INT is set the DMA drives the appropriate internal interrupt signal The processor can read DSR to determine whether the transfer terminated successfully or with an error DSR DONE is then written with a one to clear the interrupt and the DONE and error bits 12 18 MCF5307 User s Manual M Chapter 13 Timer Module This chapter describes the configuration and operation of the two general purpose timer modules timer 0
483. r the serial communication port to the Input DSI debug module Development Serial Provides serial output communication for debug module responses DSO is registered Output DSO internally Breakpoint BKPT Input used to request a manual breakpoint Assertion of BKPT puts the processor into a halted state after the current instruction completes Halt status is reflected on processor status debug data signals PST 3 0 as the value OxF If CSR BKD is set disabling normal BKPT functionality asserting BKPT generates a debug interrupt exception in the processor Processor Status Clock PSTCLK Delayed version of the processor clock Its rising edge appears in the center of valid PST and DDATA output See Figure 5 2 PSTCLK indicates when the development system should sample PST and DDATA values If real time trace is not used setting CSR PCD keeps PSTCLK PST and DDATA outputs from toggling without disabling triggers Non quiescent operation can be reenabled by clearing CSR PCD although the emulator must resynchronize with the PST and DDATA outputs PSTCLK starts clocking only when the first non zero PST value 0xC OxD or occurs during system reset exception processing Table 5 2 describes PST values Chapter 7 Phase Locked Loop PLL describes PSTCLK generation Debug Data DDATA 3 0 These output signals display the hardware register breakpoint status as a default or optionally captured add
484. ramming Model These registers are accessed through the BDM port by new BDM commands WDMREG and RDMREG described in Section 5 5 3 3 Command Set Descriptions These commands contain a 5 bit field DRc that specifies the register as shown in Table 5 3 5 6 MCF5307 User s Manual M woronoLA Programming Model Table 5 3 BDM Breakpoint Registers DRc 4 0 Register Name Abbreviation Initial State Page 0x00 Configuration status register CSR 0x0010_0000 p 5 10 0x01 0x04 Reserved 0x05 BDM address attribute register BAAR 0x0000 0005 p 5 9 0x06 Address attribute trigger register AATR 0x0000 0005 5 7 0x07 Trigger definition register TDR 0x0000 0000 5 14 0x08 Program counter breakpoint register PBR p 5 13 0x09 Program counter breakpoint mask register PBMR p 5 13 0x0A 0x0B Reserved 0x0C Address breakpoint high register ABHR p 5 8 0x0D Address breakpoint low register ABLR p 5 8 OxOE Data breakpoint register DBR 5 12 OxOF Data breakpoint mask register DBMR 5 12 NOTE Debug control registers can be written by the external development system or the CPU through the WDEBUG instruction CSR is write only from the programming model It can be read or written through the BDM port using the RDMREG and WDMREG commands 5 4 1 Address Attribute Trigger Register AATR The address attribute trigger register AATR defines ad
485. ransfer ends NOTE The MCF5307 can start a transfer in the clock cycle after BG is asserted The external master must not assert BG to the MCF5307 while driving the bus or the part may be damaged Chapter 5 Debug Support is a MCF5307 bus arbitration state diagram States are described in Table 18 6 M Chapter 18 Bus Operation 18 27 General Operation of External Master Transfers External Master D1 Implicit B3 Explicit Master Figure 18 29 MCF5307 Two Wire Bus Arbitration Protocol State Diagram Table 18 10 describes the two wire bus arbitration protocol transition conditions Table 18 10 MCF5307 Two Wire Bus Arbitration Protocol Transition Conditions Present Condition RSTI Software Watchdog BG Bus Transfer in End of Next State Label Reset Request Progress Cycle State Al Reset A2 N3 A Reset Reset A3 N EM 4 A4 A Implicit mas B1 N EM Implicit B2 A Explicit mas Master B3 A N Implicit mas B4 A A Explicit mas C1 A Explicit mas C2 N Explicit mas Explicit Master x N 2i C4 N A N Explicit mas C5 N A A EM Di N EM mas External D2 A Explicit mas Master D3 A N Implicit mas D4 A A Explicit mas 18 28 MCF5307 User s Manual M
486. ration NoP NOP performs no operation and may be used as a null command where required Command Formats 15 12 11 8 4 0 0x0 0x0 0x0 0x0 Figure 5 32 NoP Command Format Command Sequence NOP NEXT CMD Figure 5 33 NoP Command Sequence Operand Data None Result Data The command complete response OxFFFF with S cleared is returned during the next shift operation 5 34 MCF5307 User s Manual M MOTOROLA Background Debug Mode BDM 5 5 3 3 9 Synchronize PC to the PST DDATA Lines SYNC PC The sYNC PC command captures the current PC and displays it on the PST DDATA outputs After the debug module receives the command it sends a signal to the ColdFire processor that the current PC must be displayed The processor then forces an instruction fetch at the next PC with the address being captured in the DDATA logic under control of CSR BTB The specific sequence of PST and DDATA values is as follows 1 Debug signals a SYNC PC command is pending 2 CPU completes the current instruction 3 CPU forces an instruction fetch to the next PC generates a PST 0x5 value indicating a taken branch and signals the capture of DDATA 4 The instruction address corresponding to the PC is captured 5 The PST marker 0x9 0xB is generated and displayed as defined by CSR BTB followed by the captured PC address The SYNC PC command can be used to dynamically access the PC for performance monitoring The executio
487. re 4 1 SRAM Base Address Register RAMBAR RAMBAR fields are described in detail in Table 4 1 Table 4 1 RAMBAR Field Description Bits Name Description 31 15 BA Base address Defines the SRAM module s word aligned base address The SRAM module occupies a 4 Kbyte space defined by the contents of BA SRAM may reside on any 32 Kbyte boundary in the 4 Gbyte address space 14 9 Reserved should be cleared 8 WP Write protect Controls read write properties of the SRAM 0 Allows read and write accesses to the SRAM module 1 Allows only read accesses to the SRAM module Any attempted write reference generates an access error exception to the ColdFire processor core 7 6 Reserved should be cleared M MOTOROLA Chapter 4 Local Memory 4 3 SRAM Initialization Table 4 1 RAMBAR Field Description Continued Bits Name Description 5 1 Address space masks ASn These fields allow certain types of accesses to be masked or SC inhibited from accessing the SRAM module These bits are useful for power management as SD described in Section 4 6 Power Management In particular is typically set UC The address space mask bits are follows UD CPU space interrupt acknowledge cycle mask Note that C I must be set if BA 0 SC Supervisor code address space mask SD Supervisor data address space mask UC User code address space mask UD User data address space mask
488. re Module Description UART TS Internal Channel Serial RTS Control Logic Communications Channel RxD TxD System Integration Programmable BCLKO Module SIM Interrupt Control k or Interrupt Logic Generation External clock TIN Controller Figure 1 2 UART Module Block Diagram Each UART module consists of the following major functional areas Serial communication channel 16 bit divider for clock generation Internal channel control logic e Interrupt control logic Each UART contains an programmable clock rate generator Data formats can be 5 6 7 or 8 bits with even odd or no parity and up to 2 stop bits in 1 16 increments The UARTS include 4 byte and 2 byte FIFO buffers The UART modules also provide several error detection and maskable interrupt capabilities Modem support includes request to send RTS and clear to send CTS lines BCLKO provides the time base through a programmable prescaler The UART time scale can also be sourced from a timer input Full duplex auto echo loopback local loopback and remote loopback modes allow testing of UART connections The programmable UARTs can interrupt the CPU on various normal or error condition events 1 3 5 Timer Module The timer module includes two general purpose timers each of which contains a free running 16 bit timer for use in any of three modes One mode captures the timer value with an external event Another mode triggers an external signal or interr
489. re cache lines are loaded from memory by burst mode accesses that cache 4 longwords of data or instructions All 4 longwords must be loaded for the cache line to be valid Figure 4 3 shows cache organization as well as terminology used MOTOROLA Chapter 4 Local Memory 4 7 Cache Organization Way 0 Way 1 Way 3 Set 0 Set 1 Set 126 Set 127 E ode Cache Line Format n URN TAG VIM Longword 0 Longword 1 Longword 2 Longword 3 Where TAG 21 bit address tag V Valid bit for line M Modified bit for line Figure 4 3 Cache Organization and Line Format A set is a group of four lines one from each level or way corresponding to the same index into the cache array 4 8 1 Cache Line States Invalid Valid Unmodified and Valid Modified As shown in Table 4 3 a cache line can be invalid valid unmodified often called exclusive or valid modified Table 4 3 Valid and Modified Bit Settings V M Description Invalid Invalid lines are ignored during lookups 1 0 Valid unmodified Cache line has valid data that matches system memory 1 1 Valid modified Cache line contains most recent data data at system memory location is stale A valid line can be explicitly invalidated by executing a CPUSHL instruction 4 8 MCF5307 User s Manual M Cache Organization 4 8 2 The Cache at Start Up As Figure 4 4 A shows af
490. re edge bits TMRn CE select the type of transition that triggers the capture sets the timer event register capture event bit TERn CAP and issues a maskable interrupt MCF5307 User s Manual M woronoLA General Purpose Timer Programming Model Reference compare A timer can be configured to count up to a reference value at which point TERA REF is set If TMRn ORI is one an interrupt is issued If the free run restart bit TMRn FRR is set a new count starts If it is clear the timer keeps running Output mode When a timer reaches the reference value selected by it can send an output signal on TOUTn TOUT can be an active low pulse or a toggle of the current output under program control NOTE Although external devices cannot access MCF5307 on chip memories or MBAR they can access timer module registers The timer module registers shown in Table 13 1 can be modified at any time Table 13 1 General Purpose Timer Module Memory Map ons 31 24 23 16 15 8 7 0 0x140 Timer 0 mode register TMRO p 13 3 Reserved 0x144 Timer 0 reference register TRRO p 13 4 Reserved 0x148 Timer 0 capture register TCRO p 13 4 Reserved 0x14C Timer 0 counter TCNO p 13 5 Reserved 0x150 Reserved Timer 0 event register Reserved TERO p 13 5 0x180 Timer 1 mode register TMR1 p 13 3 Reserved 0x184 Timer 1 reference register TRR1 p 13 4 Reserved 0
491. rease RXCNT SUBQ L 1 D0 MOVE B D0 RXCNT BEQ S ENMASR Last byte to be read MOVE B RXCNT D1 Check second to last byte to be read EXTB L D1 SUBI L 1 D1 BNE S NXMAR Not last one or second last LAMAR BSET B 3 I2CR Disable ACK BRA NXMAR ENMASR BCLR B 45 I2CR Last one generate STOP signal NXMAR MOVE B I2DR RXBUF Read data and store RTE 8 6 5 Generation of Repeated START After the data transfer if the master still wants the bus it can signal another START followed by another slave address without signalling a STOP as in the following example RESTART MOVE B I2CR A7 Repeat START RESTART BSET B 42 A7 MOVE B A7 I2CR MOVE B CALLING A7 Transmit the calling address DO R W MOVE B CALLING 7 MOVE B A7 I2DR 8 12 MCF5307 User s Manual M woronoLA Pc Programming Examples 8 6 6 Slave Mode In the slave interrupt service routine the module addressed as slave bit IAAS should be tested to check if a calling of its own address has just been received If IAAS is set software should set the transmit receive mode select bit I2CR MTX according to the I2SR SRW Writing to the I2CR clears the IAAS automatically The only time IAAS is read as set is from the interrupt at the end of the address cycle where an address match occurred interrupts resulting from subsequent data transfers will have IAAS cleared A data transfer can now be initiated by writing information to I2DR for slave transmits or read from I2DR in sl
492. red at hardware reset or by writing a 1 to DSR DONE 0 No configuration error exists 1 A configuration error has occurred 5 BES Bus error on source 0 No bus error occurred 1 The DMA channel terminated with a bus error either during the read portion of a transfer or during an access in single address mode SAA 1 4 BED Bus error on destination 0 No bus error occurred 1 The DMA channel terminated with a bus error during the write portion of a transfer 3 Reserved should be cleared 12 10 MCF5307 User s Manual M woronoLA DMA Controller Module Functional Description Table 12 4 DSRn Field Descriptions Continued Bits Name Description 2 REQ Request 0 No request is pending or the channel is currently active Cleared when the channel is selected 1 The DMA channel has a transfer remaining and the channel is not selected 1 BSY Busy 0 DMA channel is inactive Cleared when the DMA has finished the last transaction 1 BSY is set the first time the channel is enabled after a transfer is initiated 0 DONE Transactions done Set when all DMA controller transactions complete normally as determined by transfer count and error conditions When BCR reaches zero DONE is set when the final transfer completes successfully DONE can also be used to abort a transfer by resetting the status bits When a transfer completes software must clear DONE before reprogramming the DMA 0 Wri
493. redicted the instructions following the predicted branch that may have been speculatively executed can complete see completion If the branch is not resolved as predicted instructions on the mispredicted path and any results of speculative execution are purged from the pipeline and fetching continues from the nonpredicted path Burst A multiple beat data transfer C Cache High speed memory containing recently accessed data and or instructions subset of main memory Cache coherency An attribute wherein an accurate and common view of memory is provided to all devices that share the same memory system Caches are coherent if a processor performing a read from M MOTOROLA Glossary of Terms and Abbreviations Glossary 11 Glossary 12 its cache is supplied with data corresponding to the most recent value written to memory or to another processor s cache Cache flush An operation that removes from a cache any data from a specified address range This operation ensures that any modified data within the specified address range is written back to main memory Cache line The smallest unit of consecutive data or instructions that is stored in a cache For ColdFire processors a line consists of 16 bytes Caching inhibited A memory update policy in which the cache is bypassed and the load or store is performed to or from main memory Cast outs Cache lines that must be written to memory when a cache miss causes a cache line to be repl
494. register to TDO Enhances test efficiency by reducing the overall shift path when a device other than the MCF5307 is under test on a board design with multiple chips on the overall 1149 1 defined boundary scan chain The bypass register is implemented in accordance with 1149 1 so the shift register stage is set to logic 0 on the rising edge of TCK following entry into the capture DR state Therefore the first bit shifted out after selecting the bypass register is always a logic 0 to differentiate a part that supports an IDCODE register from a part that supports only the bypass register BYPASS goes active on the falling edge of TCK in the Update IR state when instruction shift register data is equivalent to octal 7 The IEEE Standard 1149 1 requires the EXTEST SAMPLE PRELOAD and BYPASS instructions IDCODE CLAMP and HIGHZ are optional standard instructions that the MCF5307 implementation supports and are described in the IEEE Standard 1149 1 19 4 2 IDCODE Register The MCF5307 includes an IEEE Standard 1149 1 compliant JTAG identification register IDCODE which is read by the MCF5307 JTAG instruction encoded as octal 1 31 30 29 28 222222221111111111987654 3210 2 9 8 6 5 3210 Version Number 0 1 010 111 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 1 1 0 1 0000 forH55J 0001 for J20C Table 19 3 describes IDCODE bit assignments Table 19 3
495. rent operation of the processor and BDM initiated commands See Section 5 6 Real Time Debug Support M MOTOROLA Chapter 5 Debug Support 5 1 Signal Description The Version 2 ColdFire core implemented the original debug architecture now called Revision A Based on feedback from customers and third party developers enhancements have been added to succeeding generations of ColdFire cores The Version 3 core implements Revision B of the debug architecture providing more flexibility for configuring the hardware breakpoint trigger registers and removing the restrictions involving concurrent BDM processing while hardware breakpoint registers are active 5 2 Signal Description Table 5 1 describes debug module signals All ColdFire debug signals are unidirectional and related to a rising edge of the processor core s clock signal The standard 26 pin debug connector is shown in Section 5 7 Motorola Recommended BDM Pinout Table 5 1 Debug Module Signals Signal Description Development Serial Clock DSCLK Internally synchronized input The logic level on DSCLK is validated if it has the same value on two consecutive rising CLKIN edges Clocks the serial communication port to the debug module Maximum frequency is 1 5 the processor CLK speed At the synchronized rising edge of DSCLK the data input on DSI is sampled and DSO changes state Development Serial Internally synchronized input that provides data input fo
496. ress and operand values The capturing of data values is controlled by the setting of the CSR Additionally execution of the WDDATA instruction by the processor captures operands which are displayed on DDATA These signals are updated each processor cycle Processor Status These output signals report the processor status Table 5 2 shows the encoding of these PST 3 0 signals These outputs indicate the current status of the processor pipeline and as a result are not related to the current bus transfer The PST value is updated each processor cycle 5 2 MCF5307 User s Manual M woronoLA Real Time Trace Support Figure 5 2 shows PSTCLK timing with respect to PST and DDATA PSTCLK PST or DDATA Figure 5 2 PSTCLK Timing 5 3 Real Time Trace Support Real time trace which defines the dynamic execution path is a fundamental debug function The ColdFire solution is to include a parallel output port providing encoded processor status and data to an external development system This port is partitioned into two 4 bit nibbles one nibble allows the processor to transmit processor status PST and the other allows operand data to be displayed debug data DDATA The processor status may not be related to the current bus transfer External development systems can use PST outputs with an external image of the program to completely track the dynamic execution path This tracking
497. rface eese 1 10 1 3 7 4 Interrupt Controller eese 1 10 1 3 7 5 JTA 1 11 1 3 8 System Debug Interface 1 11 1 3 9 PLE Modu le 5 1 11 1 4 Programming Model Addressing Modes and Instruction 1 12 1 4 1 Programming eee eterno tera eden 1 13 1 4 2 User Reglstets is sepe nep 1 14 1 4 3 Supervisor Registers a i in a en nennen nennen enne 1 14 1 4 4 struction hte eie Ue e ERR n RS 1 15 M Contents v CONTENTS Paragraph Title Page Number Number Part I MCF5407 Processor Core Chapter 2 ColdFire Core 2 1 Features and Enhancements rennen nennen nnns 2 21 2 1 1 Clock Multiplied Microprocessor 2 22 2 1 2 tette ete Eee 2 22 2 1 2 1 Instruction Fetch Pipeline IFP eene 2 23 2 1 2 1 1 Branch Acceleration eese 2 23 2 1 22 Operand Execution Pipeline OEP sess 2 24 2 1 22 1 Illegal Opcode Handling eee 2 24 2 1 2 2 2 Hardware Multiply Accumulate MAC Unit esses 2 24 2 1 2 2 3 Hardware Divide eee ee ete 2 25 2 1 3 Debug Module Enhancements 1 2 25 2 2 Programming Model sese 2 26 2 241 User Programming Model
498. riority on the next available bus cycle regardless of the value of PARK Thus if the core asserts its internal bus request on this first bus cycle it executes a bus cycle even if PARK indicates the DMA should have priority Then after the bus transfer the PARK scheme returns to programmed functioning and the DMA is given bus mastership NOTE In all arbitration modes if BG is negated the external master interface has highest priority In this case the ColdFire core has second highest priority until the internal bus grant is asserted nasingle master system the setting of EARBCTRL does not affect arbitration performance Typically BG is tied low and the MCF5307 always owns the external bus and internal register transfers are already shown on the external bus In a system where MCF5307 is the only master this bit may remain cleared If the system needs external visibility of the data bus values during internal register transfers for system debugging both EARBCTRL and SHOWDATA must be set Note that when an internal register transfer is driven externally T becomes an output which is asserted normally an input to prevent external devices and 6 14 MCF5307 User s Manual M Programming Model memories from responding to internal register transfers that go to the external bus The AS signal and all chip select related strobe signals are not asserted Do not immediately follow a cycle in which SHOWDATA is set wi
499. rite enable 8 97 VCC Power input 98 BET BWE1 Byte enable byte write enable 8 99 BE2 BWE2 Byte enable byte write enable 8 100 BES BWE3 Byte enable byte write enable 8 101 GND Ground pin 102 SCL VOD 1 Serial clock line 8 103 SDA VOD 1 Serial data line 8 104 GND Ground pin OD Open drain output Table 16 3 Pins 105 156 Right Bottom to Top Pin i eyes Description us No Name 105 Power input 106 D31 Data bus 8 MCF5307 User s Manual M MOTOROLA Table 16 3 Pins 105 156 Right Bottom to Top Continued Description QUA No Name 107 D30 Data bus 8 108 D29 VO Data bus 8 109 GND Ground pin 110 D28 VO Data bus 8 111 D27 VO Data bus 8 112 D26 VO Data bus 8 113 Power input 114 D25 VO Data bus 8 115 D24 Data bus 8 116 D23 VO Data bus 8 117 GND Ground pin 118 D22 Data bus 8 119 D21 VO Data bus 8 120 D20 Data bus 8 121 Power input 122 D19 VO Data bus 8 123 D18 VO Data bus 8 124 D17 VO Data bus 8 125 GND Ground 126 D16 x VO Data bus 8 127 D15 VO Data bus 8 128 D14 m VO
500. rnal arbiter to switch masters DCR BWC 000 specifies the maximum transfer rate other values specify a transfer rate limit The DMA performs the specified number of transfers then relinquishes bus control The DMA negates its internal bus request on the last transfer before the BCR reaches a multiple of the boundary specified in BWC On completion the DMA reasserts its bus request to regain mastership at the earliest opportunity The minimum time that the DMA loses bus control is one bus cycle 12 5 2 Data Transfer Modes Each channel supports dual and single address transfers described in the next sections 12 5 2 1 Dual Address Transfers Dual address transfers consist of a source operand read and a destination operand write The DMA controller module begins a dual address transfer sequence when DCR SAA is cleared during a DMA request If no error condition exists DSR REQ is set e Dual address read The DMA controller drives the SAR value onto the internal address bus If DCR SINC is set the SAR increments by the appropriate number of bytes upon a successful read cycle When the appropriate number of read cycles complete multiple reads if the destination size is wider than the source the DMA initiates the write portion of the transfer If a termination error occurs DSR BES DONE are set and DMA transactions stop 12 12 MCF5307 User s Manual M woronoLA DMA Controller Module Functional Description e Dual address
501. ronoLA Chapter 8 I C Module This chapter describes the MCF5307 PC module including PC protocol clock synchronization and the registers in the PC programing model It also provides extensive programming examples 8 1 Overview is a two wire bidirectional serial bus that provides a simple efficient method of data exchange minimizing the interconnection between devices This bus is suitable for applications requiring occasional communications over a short distance between many devices The flexible allows additional devices to be connected to the bus for expansion and system development The PC system is a true multiple master bus including arbitration and collision detection that prevents data corruption if multiple devices attempt to control the bus simultaneously This feature supports complex applications with multiprocessor control and can be used for rapid testing and alignment of end products through external connections to an assembly line computer 8 2 Interface Features The C module has the following key features Compatibility with bus standard e Support for 3 3 V tolerant devices Multiple master operation e Software programmable for one of 64 different serial clock frequencies e Software selectable acknowledge bit nterrupt driven byte by byte data transfer e Arbitration lost interrupt with automatic mode switching from master to slave Calling address identification interrupt e Start and
502. rrupt occurs the corresponding IPR bit is still set but no interrupt request is passed to the core 9 6 MCF5307 User s Manual M woronoLA Interrupt Controller Registers 81 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Field DMA3 DMA2 Reset 1 1 R W Read only IPR R W IMR 15 14 13 12 1 10 9 8 7 6 5 4 3 2 1 0 Field DMA1 DMAO UART1 UARTO I2C TIMER2 TIMER1 SWT EINT7 EINT6 EINTS EINT4 EINT3 EINT2 EINT1 Reset 1111 1111 1111 1 1 1 R W Read only IPR R W IMR Addr MBAR 0x040 IPR 0x044 IMR Figure 9 4 Interrupt Pending Register IPR and Interrupt Mask Register IMR Table 9 7 describes IPR and IMR fields Table 9 7 IPR and IMR Field Descriptions Figure corresponding IMR bit determines whether an interrupt condition can generate an interrupt At 9 4 every clock the IPR samples the signal generated by the interrupting source The corresponding IPR bit reflects the state of the interrupt signal even if the corresponding IMR bit is set 0 The corresponding interrupt source is not masked IMR and has no interrupt pending IPR 1 The corresponding interrupt source is masked IMR and has an interrupt pending IPR Bits Name Description 31 18 Reserved should be cleared 17 1 Interrupt pending mask Each bit corresponds to an interrupt source defined by the ICR The 9 2 4 Interrupt Port
503. rt an interrupt request at the same time they are serviced in the following order 1 ICRS IL 110 and ICRS IP 10 so UARTI is serviced first priority 7 in Table 9 4 2 External interrupt IRQ3 set to level 6 is serviced next priority 8 3 ICRA IL 110 and ICR5 IP 01 so UARTO is serviced last priority 9 Table 9 4 Interrupt Priority Scheme Priority Md S Interrupt Source IRQPAR IRQPAR IL IP 1 7 111 11 Internal module XXX 2 111 10 3 XXX External interrupt pin IRQ7 XXX 4 111 01 Internal module XXX 5 111 00 XXX 6 6 110 11 Internal module XXX 7 110 10 XXX 8 Xxx External interrupt pin IRQ3 programmed as IRQ6 xix 9 110 01 Internal module XXX 10 110 00 XXX 11 5 101 11 Internal module XXX 12 101 10 XXX 13 XXX External interrupt IRQ5 Oxx 14 101 01 Internal module XXX 15 101 00 XXX 9 4 MCF5307 User s Manual M woronoLA Interrupt Controller Registers Table 9 4 Interrupt Priority Scheme Continued Priority S zt Interrupt Source IRQPAR IRQPAR IL IP 16 4 100 11 Internal module XXX 17 100 10 XXX 18 XXX External interrupt IRQ5 programmed as IRQ4 1xx 19 100 01 Intern
504. rt assignment register 9 7 J JTAG AC timing 20 20 obtaining IEEE Standard 1149 1 19 12 overview 19 1 registers boundary scan 19 7 bypass 19 10 descriptions 19 4 IDCODE 19 6 instruction shift 19 5 restrictions 19 10 MCF5307 User s Manual M woronoLA INDEX signal descriptions 19 2 TAP controller 19 3 test logic disabling 19 11 MAC data representation 3 4 instruction execution timings 3 5 instruction set summary 3 4 operation 3 3 programming model 2 26 3 2 status register MACSR 1 14 2 29 Mask registers DRAM 11 7 11 22 MAC 1 14 2 29 MBAR 6 4 Mechanical data case drawing 16 9 diagram 16 8 pinout 16 1 Memory SIM register 6 3 MOVEC instruction 5 36 Output port command registers 14 15 P Parallel port code example 15 3 data direction register 15 2 data register 15 2 operation 15 1 Pin assignment register 6 10 15 1 PLL 7 2 clock control for STOP 6 10 clock frequency relationships 7 4 control register 7 3 modes 7 2 operation 7 2 overview 7 1 port list 7 3 power supply filter circuit 7 6 reset initialization 7 2 timing relationships 7 4 Power supply filter circuit 7 6 Privilege level modes 1 12 Programming models overview 2 26 SIM 6 3 summary A 1 supervisor 2 29 user 2 27 M MOTOROLA Index PST outputs 5 3 PULSE instruction 5 4 R Registers ABLR ABHR 5 7 5 8 address 0 2 27 AVR 9 5
505. rupts 32 47 080 0BC Next Trap 0 15 instructions 48 60 0CO0 O0FO0 Reserved 61 OF4 Fault Unsupported instruction 2 48 MCF5307 User s Manual M woronoLA Exception Processing Overview Table 2 18 Exception Vector Assignments Continued Vector Numbers Vector Offset Hex Stacked Program Counter 1 Assignment 62 63 OF8 OFC Reserved 64 255 100 3FC Next User defined interrupts The term fault refers to the PC of the instruction that caused the exception The term next refers to the PC of the instruction that immediately follows the instruction that caused the fault ColdFire processors inhibit sampling for interrupts during the first instruction of all exception handlers This allows any handler to effectively disable interrupts if necessary by raising the interrupt mask level contained in the status register 2 8 1 Exception Stack Frame Definition The exception stack frame is shown in Figure 2 10 The first longword of the exception stack frame contains the 16 bit format vector word F V and the 16 bit status register The second longword contains the 32 bit program counter address 31 28 27 26 25 18 17 16 15 0 A7 Format 5 3 2 Vector 7 0 FS 1 0 Status Register 4 0x04 Program Counter 31 0 Figure 2 10 Exception Stack Frame Form The 16 bit format vector word contains three unique fields Format field This 4 bit field at the top of
506. ry Clear to send TS 1 0 Signals UART that data can be sent 17 18 to peripheral Section 17 10 Timer Module Signals 17 18 Timer input TIN 1 0 Clock input to timer or trigger to 17 19 timer value capture logic Timer outputs TOUTT 1 0 Outputs waveform or pulse High 17 19 Section 17 11 Parallel Port PP 15 0 17 19 17 4 MCF5307 User s Manual M MOTOROLA Table 17 1 MCF5307 Signal Index Continued Overview Signal Name Abbreviation Function VO Reset Pull Up Page Parallel port PP 15 0 Interfaces with I O multiplexed with Input 17 19 bus address and attribute signals Section 17 12 I C Module Signals 17 19 Serial clock line SCL Clock signal for 2 operation Open 17 19 drain Serial data line SDA Serial data port for 2 operation Open 17 19 drain Section 17 13 Debug and Test Signals 17 20 Motorola test mode MTMODO Puts processor in functional or User cfg 17 20 emulator mode Motorola test mode MTMODJ3 1 Reserved Down 17 20 High impedance HIZ Assertion three states all outputs Up 17 20 Processor clock out PSTCLK Output clock used for PSTDDATA 17 20 Processor status PST 3 0 Displays captured processor data Driven 17 20 Debug data DDATA 3 0 Displays captured processor data Driven 17 20 and brea
507. s Mask register MASK This 16 bit general purpose register provides an optional address mask for MAC instructions that fetch operands from memory It is useful in the implementation of circular queues in operand memory e MAC status register MACSR This 8 bit register defines configuration of the MAC unit and contains indicator flags affected by MAC instructions Unless noted otherwise the setting of MACSR indicator flags is based on the final result that is the result of the final operation involving the product and accumulator 3 1 2 General Operation The MAC unit supports the ColdFire integer multiply instructions MULS and MULU and provides additional functionality for multiply accumulate operations The added MAC instructions to the ColdFire ISA provide for the multiplication of two numbers followed by the addition or subtraction of this number to or from the value contained in the accumulator The product may be optionally shifted left or right one bit before the addition or subtraction takes place Hardware support for saturation arithmetic may be enabled to minimize software overhead when dealing with potential overflow conditions using signed or unsigned operands These MAC operations treat the operands as one of the following formats Signed integers Unsigned integers Signed fixed point fractional numbers To maintain compactness the MAC module is optimized for 16 bit multiplications Two 16 bit operands prod
508. s 2 4 1 Organization of Integer Data Formats in Registers Figure 2 7 shows the integer format for data registers Each integer data register is 32 bits wide Byte and word operands occupy the lower 8 and 16 bit portions of integer data registers respectively Longword operands occupy the entire 32 bits of integer data registers A data register that is either a source or destination operand only uses or changes the appropriate lower 8 or 16 bits in byte or word operations respectively The remaining M MOTOROLA Chapter 2 ColdFire Core 2 31 Organization of Data in Registers high order portion does not change The least significant bit lsb of all integer sizes is zero the most significant bit msb of a longword integer is 31 the msb of a word integer is 15 and the msb of a byte integer is 7 31 30 1 0 msb 156 Bit 0 bit number 31 31 7 0 Not used msb Low order byte Isb Byte 8 bits 81 15 0 Not used msb Lower order word Isb Word 16 bits 31 0 msb Longword Isb Longword 32 bits Figure 2 7 Organization of Integer Data Formats in Data Registers The instruction set encodings do not allow the use of address registers for byte sized operands When an address register is a source operand either the low order word or the entire longword operand is used depending on the operation size Word length source operands are sign extended to 32 bits and then used in the opera
509. s 3 During normal exception processing the PST output is driven to a OxC indicating the exception processing state The exception stack write operands as well as the vector read and target address of the exception handler may also be displayed Exception Processing PST 0 PST OxB DD destination stack frame PST OxB DD destination stack frame PST OxB DD source vector read PST 0x5 PST 0x9AB DD target PC of handler The PST DDATA specification for the reset exception is shown below 0xC 0 5 PST 0x9AB DD target PC of handler Exception Processing PST PST The initial references at address 0 and 4 are never captured nor displayed since these accesses are treated as instruction fetches For all types of exception processing the PST OxC value is driven at all times unless the PST output is needed for one of the optional marker values or for the taken branch indicator 0x5 5 8 2 Supervisor Instruction Set The supervisor instruction set has complete access to the user mode instructions plus the opcodes shown below The PST DDATA specification for these opcodes is shown in Table 5 23 Table 5 23 PST DDATA Specification for Supervisor Mode Instructions Instruction Operand Syntax PSTDDATA cpushl PST 0 1 halt PST 0x1 PST OxF move w SR Dx PST 0 1 move w Dy imm SR PST 0x1 PST 3 5 46 MCF5307 User s Manual M woronoLA Pr
510. s Increased flexibility of the breakpoint registers M MOTOROLA Chapter 2 ColdFire Core 2 25 Programming Model On chip breakpoint resources include the following e Configuration status register CSR Background debug mode BDM address attributes register BAAR Bus attributes and mask register AATR e Breakpoint registers These can be used to define triggers combining address data and PC conditions in single or dual level definitions They include the following PC breakpoint register PBR PC breakpoint mask register PBMR Data operand address breakpoint registers ABHR ABLR Data breakpoint register DBR Data breakpoint mask register DBMR Trigger definition register TDR can be programmed to generate a processor halt or initiate a debug interrupt exception These registers can be accessed through the dedicated debug serial communication channel or from the processor s supervisor programming model using the WDEBUG instruction The enhancements of the Revision B debug specification are fully backward compatible with the A revision For more information see Chapter 5 Debug Support 2 2 Programming Model The MCF5307 programming model consists of three instruction and register groups user MAC also user mode and supervisor shown in Figure 2 2 User mode programs are restricted to user and MAC instructions and programming models Supervisor mode system software can reference all u
511. s lines like SIZ TT and TM hold the same value for the entire transfer S0 S1 S2 53 S4 S5 56 57 S8 59 510 511 BCLKO Internal X A X A A 31 0 External Termination X SIZ 1 0 y y TM 1 0 TT 1 0 E z D 81 0 Write Y Write Y Write XY Write TA B M Figure 18 16 Line Write Burst 2 1 1 1 Internal External Termination 18 14 MCF5307 User s Manual M woronoLA Data Transfer Operation Figure 18 17 shows a line burst write with one wait state insertion SO 1 S2 S3 WS S4 S5 WS S6 S7 WS S8 59 WS S10S11 gt BCLKO A 31 0 X m TM 2 0 y y Eu BWE D 31 0 Write Ywrite YXwrite Y write Bae ES ES Figure 18 17 Line Write Burst 3 2 2 2 with One Wait State Internal Termination 0 0 me Figure 18 18 shows a burst inhibited line write The external device executes a basic write cycle while determining that a line is being transferred The external device uses fast termination to end each subsequent transfer 0 51 S2 3 54 55 0 51 54 55 SO 51 54 S5 SO 51 54 S5 BCLKO 31 0 K A 3 2 00 X ApB2 o X Ap2 10 X
512. s based on results generated by arithmetic operations 7 6 5 4 3 2 1 0 Field P X N Z V C Reset 0 00 Undefined R W R W R R W RW RW RW Table 2 1 CCR Field Descriptions Bits Name Description 7 P Branch prediction bit Alters the static prediction algorithm used by the branch acceleration logic in the IFP on forward conditional branches 0 Predicted as not taken 1 Predicted as taken 6 5 Reserved should be cleared 4 X Extend condition code bit Assigned the value of the carry bit for arithmetic operations otherwise not affected or set to a specified result Also used as an input operand for multiple precision arithmetic 3 N Negative condition code bit Set if the msb of the result is set otherwise cleared 2 Z Zero condition code bit Set if the result equals zero otherwise cleared 2 28 MCF5307 User s Manual M woronoLA Programming Model Table 2 1 CCR Field Descriptions Continued Bits Name Description 1 V Overflow condition code bit Set if an arithmetic overflow occurs implying that the result cannot be represented in the operand size otherwise cleared 0 C Carry condition code bit Set if a carry out of the data operand msb occurs for an addition or if a borrow occurs in a subtraction otherwise cleared Mask register MASK This 16 bit general purpose register provides an optional address m
513. s cleared 1 Bus is busy When START is detected IBB is set 4 IAL Arbitration lost Set by hardware in the following circumstances IAL must be cleared by software by writing zero to it SDA sampled low when the master drives high during an address or data transmit cycle SDA sampled low when the master drives high during the acknowledge bit of a data receive cycle A start cycle is attempted when the bus is busy A repeated start cycle is requested in slave mode stop condition is detected when the master did not request it 3 Reserved should be cleared 2 SRW Slave read write When IAAS is set SRW indicates the value of the R W command bit of the calling address sent from the master SRW is valid only when a complete transfer has occurred no other transfers have been initiated and the module is a slave and has an address match 0 Slave receive master writing to slave 1 Slave transmit master reading from slave 1 interrupt Must be cleared by software by writing a zero to it in the interrupt routine 0 No interrupt pending 1 An interrupt is pending which causes a processor interrupt request if 1 Set when one of the following occurs Complete one byte transfer set at the falling edge of the ninth clock Reception of a calling address that matches its own specific address in slave receive mode Arbitration lost 0 RXAK Received acknowledge The value
514. s including digital audio and servo control Integrated as an execution unit in the processor s OEP the MAC unit implements a three stage arithmetic pipeline optimized for 16 x 16 multiplies Both 16 and 32 bit input operands are supported by this design in addition to a full set of extensions for signed and unsigned integers plus signed fixed point fractional input operands 1 3 1 4 Integer Divide Module Integrated into the OEP the divide module performs operations using signed and unsigned integers The module supports word and longword divides producing quotients and or remainders MOTOROLA Chapter 1 Overview 1 7 ColdFire Module Description 1 3 1 5 8 Kbyte Unified Cache The MCF5307 architecture includes an 8 Kbyte unified cache This four way set associative cache provides pipelined single cycle access on cached instructions and operands As with all ColdFire caches the cache controller implements a non lockup streaming design The use of processor local memories decouples performance from external memory speeds and increases available bandwidth for external devices or the on chip 4 channel DMA The cache implements line fill buffers to optimize 16 byte line burst accesses Additionally the cache supports copyback write through or cache inhibited modes A 4 entry 32 bit buffer is used for cache line push operations and can be configured for deferred write buffering in write through or cache inhibited modes 1 3 1
515. s its current state or advances to the next state This directly controls whether JTAG data or instruction operations occur TMS has an internal pull up so if it is not driven low its value defaults to a logic level of 1 If TMS is not used it should be tied to VDD BKPT signals a hardware breakpoint to the processor in debug mode See Chapter 5 Debug Support 19 2 MCF5307 User s Manual M TAP Controller Table 19 1 JTAG Pin Descriptions Pin Description TDI DSI Test data input MTMODO high development serial input MTMODO low TDI provides the serial data port for loading the JTAG boundary scan bypass and instruction registers Shifting in of data depends on the state of the JTAG controller state machine and the instruction in the instruction register This shift occurs on the rising edge of TCK TDI has an internal pull up so if it is not driven low its value defaults to a logical 1 If TDI is not used it should be tied to VDD DSI provides single bit communication for debug module commands See Chapter 5 Debug Support TDO DSO Test data output MTMODO high development serial output MTMODO low is the serial data port for outputting data from JTAG logic Shifting data out depends on the state of the JTAG controller state machine and the instruction currently in the instruction register This shift occurs on the falling edge of TCK When not outputting test data TD
516. s may be simultaneously sent to an SRAM module and cache power can be minimized by configuring RAMBAR address space masks as precisely as possible For example if an SRAM is mapped to the internal instruction bus and contains instruction data setting the ASn mask bits associated with operand references can decrease power dissipation Similarly if the SRAM contains data setting ASn bits associated with instruction fetches minimizes power Table 4 2 shows typical RAMBAR configurations Table 4 2 Examples of Typical RAMBAR Settings Data Contained in SRAM RAMBAR 5 0 Code only 0 2 Data only 0x35 Both code and data 0x21 4 7 Cache Overview This section describes the MCF5307 cache implementation including organization configuration and coherency It describes cache operations and how the cache interacts with other memory structures The MCF5307 processor contains a nonblocking 8 Kbyte 4 way set associative unified instruction and data cache with a 16 byte line size The cache improves system performance by providing low latency access to the instruction and data pipelines This decouples processor performance from system memory performance increasing bus availability for on chip DMA or external devices Figure 4 2 shows the organization and integration of the data cache 4 6 MCF5307 User s Manual M woronoLA Cache Organization Cache Control External Control Bus Control Logic
517. s out due to unterminated bus Sa NOTE The watchdog timer IRQ should be set to the highest level in the system Software watchdog timer IRQ Timeout 2 Watchdog timer interrupt cannot be serviced due to hung bus cycle Wait for another timeout before setting SYPGR SWTA Ns 3 TA held until another bus cycle starts Software f watchdog timer TA Timeout SYPCR SWTAVAL 1 gt 1 SWTAVAL is set if watchdog timer TA is asserted Watchdog timer IACK cycle Figure 6 4 MCF5307 Embedded System Recovery from Unterminated Access When the watchdog timer times out and SYPCR SWRI is programmed for a software reset an internal reset is asserted and RSR SWTR is set To prevent the watchdog timer from interrupting or resetting the SWSR must be serviced by performing the following sequence 1 Write 0x55 to SWSR 2 Write OxAA to the SWSR Both writes must occur in order before the timeout but any number of instructions or SWSR accesses can be executed between the two writes This order allows interrupts and exceptions to occur if necessary between the two writes Caution should be exercised when changing SYPCR values after the software watchdog timer has been enabled with the setting of SYPCR SWE because it is difficult to determine the state of the watchdog timer while it is running The countdown value is constantly compared with the timeout period specified by SYPCR SW
518. scriptions Bits Field Description 7 AVEC Autovector enable Determines whether the interrupt acknowledge cycle input for the internal interrupt level indicated in IL for each interrupt requires an autovector response 0 Interrupting source returns vector during interrupt acknowledge cycle 1 SIM generates autovector during interrupt acknowledge cycle 6 5 Reserved should be cleared 4 2 Interrupt level Indicates the interrupt level assigned to each interrupt input See Table 9 4 1 0 IP Interrupt priority Indicates the interrupt priority for internal modules within the interrupt level assignment See Table 9 4 00 Lowest 01 Low 10 High 11 Highest M woronoLA Chapter 9 Interrupt Controller 9 3 Interrupt Controller Registers NOTE Assigning the same interrupt level and priority to multiple ICRs causes unpredictable system behavior Table 9 4 shows possible priority schemes for internal and external sources of the MCF5307 The internal module interrupt source in this table can be any internal interrupt source programmed to the given level and priority This table shows how external interrupts are prioritized with respect to internal interrupt sources within the same level For example UARTO and UARTI sources are programmed to IL 110 in this case UARTO is given lower priority than UARTI so ICRA IP 01 and the ICR5 IP 10 IRQ3 is programmed to level 6 If all three asse
519. se 4 9 3 Cache Protocol The following sections describe the cache protocol for processor accesses and assumes that the data is cacheable that is write through or copyback 4 9 3 1 Read Miss A processor read that misses in the cache requests the cache controller to generate a bus transaction This bus transaction reads the needed line from memory and supplies the required data to the processor core The line is placed in the cache in the valid state M woronoLA Chapter 4 Local Memory 4 15 Cache Operation 4 9 3 2 Write Miss The cache controller handles processor writes that miss in the cache differently for write through and copyback regions Write misses to copyback regions cause the cache line to be read from system memory as shown in Figure 4 6 1 Writing character X to generates a write miss Data cannot be written to an invalid line Cache Line Ox0C 0x08 0x04 0x00 MCF5307 M uo 2 The cache line characters A P is updated from system memory and line is marked valid 0 0 0x08 0x04 0x00 Vet ABCD EFGH M 0 MUN 3 After the cache line is filled the write that initiated the write miss the character X completes to OxOB System Memory Ox0C 0x08 0x04 0x00 V MCF5307 ABCD EXGH IJKL MNOP M Figure 4 6 Write Miss in Copyback Mode uo a The new cache line is then updated with write da
520. selected DSI provides the single bit communication for debug module commands See Chapter 5 Debug Support 17 14 4 Test Data Output Development Serial Output TDO DSO If MTMODO is high is selected The TDO output provides the serial data port for outputting data from JTAG logic Shifting out data depends on the JTAG controller state machine and the instruction in the instruction register Data shifting occurs on the falling edge of TCK When TDO is not outputting test data it is three stated TDO can be three stated to allow bused or parallel connections to other devices having JTAG If MTMODO is low DSO is selected DSO provides single bit communication for debug module responses See Chapter 5 Debug Support 17 22 MCF5307 User s Manual M woronoLA Debug Module JTAG Signals 17 14 5 Test Clock TCK TCK is the dedicated JTAG test logic clock independent of the MCF5307 processor clock Various JTAG operations occur on the rising or falling edge of TCK Holding TCK high or low for an indefinite period does not cause JTAG test logic to lose state information If TCK is not used it must be tied to ground M MOTOROLA Chapter 17 Signal Descriptions 17 23 Debug Module JTAG Signals 17 24 MCF5307 User s Manual M woronoLA Chapter 18 Bus Operation This chapter describes data transfer operations error conditions bus arbitration and reset operations It describes transfers initiated by the MCF5307 and by an e
521. ser mode and MAC instructions and registers and additional supervisor instructions and control registers The user or supervisor programming model is selected based on SR S The following sections describe the registers in the user MAC and supervisor programming models 2 26 MCF5307 User s Manual M woronoLA Programming Model 3l 0 DO Data registers 31 0 AO Address registers User Registers A7 Stack pointer PC Program counter CCR Condition code register 31 0 MACSR MAC status register ACC MAC accumulator MASK MAC mask register 15 L 31 19 CCR SR Status register 50 Must be zeros VBR Vector base register 2 9 CACR Cache control register 55 ACRO Access control register 0 SQ ACR1 Access control register 1 RAMBAR base address register MBAR Module base address register Figure 2 3 ColdFire Programming Model 2 2 1 User Programming Model As Figure 2 3 shows the user programming model consists of the following registers 16 general purpose 32 bit registers DO D7 and 0 7 e 32 bit program counter e 8 bit condition code register 2 2 1 1 Data Registers 00 07 Registers 20 07 are used as data registers for bit byte 8 bit word 16 bit and longword 32 bit operations They may also be used as index registers 2 2 1 2 Address Registers A0 A6 The address registers A0 A6
522. serted during a DRAM access 00 1 clock cycle 01 2 clock cycles 10 3 clock cycles 11 4 clock cycles 11 10 RP RAS precharge timing Determines how long RAS is precharged between accesses Note that RP is different from DCR RRP 00 1 clock cycle 01 2 clock cycles 10 3 clock cycles 11 4 clock cycles RNCN RAS negate to CAS negate Controls whether RAS and CAS negate concurrently or one clock apart RNCN is ignored if CAS is asserted for only one clock and both RAS and CAS are negated RNCN is used only for non page mode accesses and single accesses in page mode 0 RAS negates concurrently with CAS 1 RAS negates one clock before CAS RCD RAS to CAS delay Determines the number of system clocks between assertions of RAS and CAS 0 1 clock cycle 1 2 clock cycles Reserved should be cleared EDO Extended data out Determines whether the DRAM block operates in a mode to take advantage of industry standard EDO DRAMs Do not use EDO mode with non EDO DRAM 0 EDO operation disabled 1 EDO operation enabled MCF5307 User s Manual M woronoLA Asynchronous Operation Table 11 4 DACRO DACR1 Field Description Continued Bits Name Description 5 4 PS Port size Determines the port size of the associated DRAM block For example if two 16 bit wide DRAM components form one DRAM block the port size is 32 bits Programming PS allows the DRAM controller to execute dynamic bus s
523. set STI Active low asynchronous input that when asserted indicates PLL is to enter reset mode As long as RSTI is asserted the PLL is held in reset and does not begin to lock M MOTOROLA Chapter 7 Phase Locked Loop PLL 7 3 Timing Relationships Table 7 2 PLL Module Input Signals Signal Description FREQ 1 0 Input bus indicating the CLKIN frequency range FREQ 1 0 are multiplexed with D 3 2 and are sampled while RSTI is asserted FREQ 1 0 must be correctly set for proper operation These signals do not affect CLKIN frequency but are required to set up the analog PLL to handle the input clock frequency 00 16 6 27 999 MHz 01 28 38 999 MHz 10 39 45 MHz 11 Not used DIVIDE 1 0 The MCF5307 samples clock ratio encodings on the lower data bits of the bus to determine the CLKIN to processor clock ratio D 1 0 DIVIDE 1 0 support the divide ratio combinations 00 1 4 01 Not used 10 1 2 11 1 8 Table 7 3 describes PLL module outputs Table 7 3 PLL Module Output Signals Output Description BCLKO This bus clock output provides a divided version of the processor clock frequency determined by DIVIDE 1 0 PSTCLK Provides a buffered processor status clock at 2X the CLKIN frequency PSTCLK is a delayed version of PCLK See Section 7 4 1 PCLK PSTCLK and BCLKO and Figure 7 1 RSTO This output provides an external reset for peripheral devices
524. setting CSR UHE Table 2 8 describes supervisor mode instructions Table 2 8 Supervisor Mode Instruction Set Summary Instruction Operand Syntax Operand Size Operation CPUSHL An Unsized Invalidate instruction cache line Push and invalidate data cache line Push data cache line and invalidate 1 D cache lines HALT none Unsized Enter halted state MOVE from SR Dx W SR Dx MOVE to SR Dy SR W Source gt SR lt data gt SR MOVEC Ry Rc L Ry Rc Rc Register Definition 0x002 Cache control register CACR 0x004 Access control register 0 ACRO 0x005 Access control register 1 ACR1 0x006 Access control register 2 ACR2 0x007 Access control register 3 ACR3 0x801 Vector base register VBR 0 04 base address register 0 RAMBARO 0 05 base address register 1 RAMBAR1 RTE None Unsized SP 2 SR SP 4 SP SP gt PC SP formatfield SP STOP lt data gt W Immediate data SR enter stopped state WDEBUG lt 2 gt lt 2 gt debug module 1 2 7 Instruction Timing The HALT instruction can be configured to allow user mode execution by setting CSR UHE The timing data presented in this section assumes the following The OEP is loaded with the opword and all required extension words at the beginning of each instruction execution This implies that the OEP spends no time waiting for the IFP to supply opwords and or extension
525. should negate TA Read including The external device can stop driving data after the rising edge of BCLKO fast termination However data could be driven up to S5 18 6 MCF5307 User s Manual M woronoLA Data Transfer Operation Table 18 4 Bus Cycle States Continued State Cycle BCLKO Description S5 S5 Low Read Write AS CS BE BWE and OE are negated on the BCLKO falling edge The MCF5307 stops driving address lines and R W on the rising edge of BCLKO terminating the read or write cycle At the same time the MCF5307 negates TT 1 0 TM 2 0 TIP and SIZ 1 0 on the rising edge of BCLKO Note that the rising edge of BCLKO may be the start of SO for the next access cycle in this case TIP remains asserted and R W may not transition depending on the nature of the back to back cycles The external device stops driving data between S4 and S5 The data bus returns to high impedance on the rising edge of BCLKO The rising edge of BCLKO may be the start of SO for the next access 18 4 3 Read Cycle NOTE An external device has at most two BCLKO cycles after the start of S4 to three state the data bus after data is sampled in S3 This applies to basic read cycles fast termination cycles and the last transfer of a burst During a read cycle the MCF5307 receives data from memory or from a peripheral device Figure 18 5 is a read cycle flowchart MCF5307 System 1 Se
526. smitter after a byte transmission it means end of data to the slave The slave releases SDA for the master to generate a STOP or START signal 4 STOP signal The master can terminate communication by generating a STOP signal to free the bus A STOP signal is defined as a low to high transition of SDA while SCL is at logical high F Note that a master can generate a STOP even if the slave has made an acknowledgment at which point the slave must release the bus Instead of signalling a STOP the master can repeat the START signal followed by a calling command A in Figure 8 3 A repeated START occurs when a START signal is generated without first generating a STOP signal to end the communication msb Isb msb Isb PLPURTURUSUSPURURE SDA METRE XX roroa Aoao AAAA Calling Add a A New Calling Add START alling Address Repeated ew Calling Address No STOP Signal Bit START ACK Signal Signal Bit Stop Figure 8 3 Repeated START The master uses a repeated START to communicate with another slave or with the same slave in a different mode transmit receive mode without releasing the bus 8 4 1 Arbitration Procedure If multiple devices simultaneously request the bus the bus clock is determined by a synchronization procedure in which the low period equals the longest clock low period among the devices and the high period equa
527. smitter and receiver are enabled SINIT calls CHCHK to perform the checks When called SINIT places the UART in local loop back mode and checks for the following errors Transmitter never ready Receiver never ready Parity error Incorrect character received driver routine This routine sheets 4 and 5 consists of INCH the terminal input character routine which gets a character from the receiver and OUTCH which sends a character to the transmitter 14 28 MCF5307 User s Manual M woronoLA Operation Interrupt handling Consists of SIRQ sheet 4 which is executed after the UART module generates an interrupt caused by a change in break beginning of a break SIRQ then clears the interrupt source waits for the next change in break interrupt end of break clears the interrupt source again then returns from exception processing to the system monitor 14 5 6 1 UART Module Initialization Sequence NOTE UART module registers can be accessed by word or byte operations but only data byte D 7 0 is valid Table 14 14 shows the UART module initialization sequence Table 14 14 UART Module Initialization Sequence Register Setting UCRn Reset the receiver and transmitter Reset the mode pointer MISC 2 0 0b001 UIVRn Program the vector number for a UART module interrupt UIMRn Enable the preferred interrupt sources UACRn Initialize the input enable control IEC bit UCSRn _
528. ss control See Section 10 4 1 2 Chip Select Mask Registers CSMRO CSMR7 e Chip select control registers CSCRn provide port size and burst capability indication wait state generation and automatic acknowledge generation features See Section 10 4 1 3 Chip Select Control Registers CSCRO CSCR7 Each CSn can assert during specific CPU space accesses such as interrupt acknowledge cycles and each can be accessed by an external master CSO is a global chip select after reset and provides relocatable boot ROM capability 10 3 1 General Chip Select Operation When a bus cycle is initiated the MCF5307 first compares its address with the base address and mask configurations programmed for chip selects 0 7 configured in CSCRO CSCR7 and DRAM block 0 and 1 address and control registers configured in DACRO and If the driven address matches a programmed chip select or DRAM block the appropriate chip select is asserted or the DRAM block is selected using the specifications programmed in the respective configuration register Otherwise the following occurs Ifthe address and attributes do not match in CSCR or DACR the MCF5307 runs an external burst inhibited bus cycle with a default of external termination on a 32 bit port e Should an address and attribute match in multiple CSCRs the matching chip select signals are driven however the MCF5307 runs an external burst inhibited bus cycle with external termination
529. ss Register MBAR The supervisor level MBAR Figure 6 2 specifies the base address and allowable access types for all internal peripherals It is written with a MOVEC instruction using the CPU address OxCOF See the ColdFire Family Programmer s Reference Manual MBAR can be read or written through the debug module as a read write register as described in Chapter 5 Debug Support Only the debug module can read MBAR The valid bit MBAR V is cleared at system reset to prevent incorrect references before MBAR is written other MBAR bits are uninitialized at reset To access internal peripherals write MBAR with the appropriate base address BA and set MBAR V after system reset All internal peripheral registers occupy a single relocatable memory block along 4 Kbyte boundaries If MBAR V is set MBAR BA is compared to the upper 20 bits of the full 32 bit internal address to determine if an internal peripheral is being accessed MBAR masks specific address spaces using the address space fields Attempts to access a masked address space generate an external bus access Addresses hitting overlapping memory spaces take the following priority 1 MBAR 2 SRAM and caches 3 Chip select NOTE The MBAR region must be mapped to non cacheable space Attribute Mask Bits 31 1211109 8 7 6 5 4 3 2 1 0 Field BA WP C IISC SD UC UD V Reset Undefined 0 R W W supervisor
530. st is being made regardless of whether it is masked in the IMR The autovector register AVEC controls whether the SIM supplies an autovector or executes an external interrupt acknowledge cycle for each IRQ The interrupt port assignment register IRQPAR provides the level assignment of the primary external interrupt pins IRQ5 IRQ3 and IRQI 9 2 Interrupt Controller Registers The interrupt controller register portion of the SIM memory map is shown in Table 9 2 Table 9 1 Interrupt Controller Registers ned 31 24 23 16 15 8 7 0 0x040 Interrupt pending register IPR p 9 6 0x044 Interrupt mask register IMR p 9 6 0x048 Reserved Autovector register AVR p 9 5 Interrupt Control Registers ICRs p 9 3 0x04C Software watchdog TimerO ICR1 p 9 3 Timer1 ICR2 p 9 3 ICR3 p 9 3 timer ICRO p 9 3 0x050 UARTO ICRA p 9 3 UART1 ICR5 9 3 DMAO ICR6 p 9 3 1 ICR7 p 9 3 0x054 DMA2 ICR8 p 9 3 ICR9 p 9 3 Reserved Each internal interrupt source has its own interrupt control register ICRO ICRO9 shown in Table 9 2 and described in Section 9 2 1 Interrupt Control Registers ICRO ICRO9 Table 9 2 Interrupt Control Registers 9 2 MBAR Offset Register Name 0x04C ICRO Software watchdog timer 0x04D ICR1 0 04 ICR2 Timer1 0 04 ICR3
531. t RW to read 2 Place address on A 31 0 3 Assert TT 1 0 TM 2 0 TIP and SIZ 1 0 4 Assert TS 5 Assert AS 6 Negate TS Decode address and select the appropriate slave device 2 Drive data on D 31 0 1 Sample T low and latch data 3 Assert TA 1 Negate TA 1 Start next cycle 2 Stop driving D 31 0 ING Figure 18 5 Read Cycle Flowchart The read cycle timing diagram is shown in Figure 18 6 NOTE In the following timing diagrams TA waveforms apply for chip selects programmed to enable either internal or external termination TA assertion should look the same in either case M MOTOROLA Chapter 18 Bus Operation 18 7 Data Transfer Operation S0 1 2 3 4 5 BCLKO R W TT 1 0 TM 2 0 SU ay ATO i X 4 Uu d mo me D 31 0 Read Spo gt Figure 18 6 Basic Read Bus Cycle Note the following characteristics of a basic read e In S3 data is made available by the external device on the falling edge of BCLKO and is sampled on the rising edge of BCLKO with TA asserted e In S4 the external device can stop driving data after the rising edge of BCLKO However data could be driven up to S5 e Fora read cycle the external device stops driving data between S4 and S5 States are described in Table 18 4 18
532. t is used as the timing reference for the debug bus timing DDATA 3 0 and PST 3 0 PSTCLK is at the same frequency as the core processor and cache memory The frequency is 2x the CLKIN 17 13 4 Debug Data DDATA 3 0 The debug data signals DDATA 3 0 display captured processor data and breakpoint status See Chapter 5 Debug Support for additional information on this bus 17 13 5 Processor Status PST 3 0 The processor status pins indicate the MCF5307 processor status During debug mode the timing is synchronous with the processor clock PSTCLK and the status is not related to the current bus transfer Table 2 11 shows the encodings of these signals 17 20 MCF5307 User s Manual M woronoLA Debug Module JTAG Signals Table 17 17 Processor Status Signal Encodings PST 3 0 Definition Hex Binary 0x0 0000 Continue execution 0 1 0001 Begin execution of an instruction 0x2 0010 Reserved 0x3 0011 Entry into user mode 0 4 0100 Begin execution of PULSE and WDDATA instructions 0x5 0101 Begin execution of taken branch or Synch PC 0x6 0110 Reserved 0 7 0111 Begin execution of RTE instruction 0x8 1000 Begin 1 byte data transfer on DDATA 0 9 1001 Begin 2 byte data transfer on DDATA OxA 1010 Begin 3 byte data transfer on DDATA OxB 1011 Begin 4 byte data transfer on DDATA OxC 1100 Exception processing OxD 1101 Emulator mode entry exception processing OxE 1110 Proc
533. t result A bus error response is returned if the CPU core is not halted Command Result Formats 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Command 0 2 0 1 0 8 A D Register Result D 31 16 D 15 0 Figure 5 18 RAREG RDREG Command Format Command Sequence RAREG RDREG NEXT CMD 22 LS RESULT XXX NEXT CMD BERR READYZ Figure 5 19 RAREG RDREG Command Sequence Operand Data None Result Data The contents of the selected register are returned as a longword value most significant word first 5 24 MCF5307 User s Manual M woronoLA Background Debug Mode BDM 5 5 3 3 2 Write A D Register WAREG WDREG The operand longword data is written to the specified address or data register A write alters all 32 register bits A bus error response is returned if the CPU core is not halted Command Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 2 0 0 0 8 A D Register D 31 16 D 15 0 Figure 5 20 WAREG WDREG Command Format Command Sequence WDREG WAREG MS DATA 5 READY READY CMD COMPLETE XXX NEXT CMD BERR NOT READY Figure 5 21 WAREG WDREG Command Sequence Operand Data Longword data is written into the specified address or data register The data is supplied most significant word first Result Data Command complete status is indicated by returning OxFFFF with S cleared when the
534. ta and the M bit is set for the line leaving it in modified state Write misses to write through regions write directly to memory without loading the corresponding cache line into the cache 4 9 3 3 Read Hit On a read hit the cache provides the data to the processor core and the cache line state remains unchanged If the cache mode changes for a specific region of address space lines in the cache corresponding to that region that contain modified data are not pushed out to memory when a read hit occurs within that line First execute a CPUSHL instruction or set CACR CINVA before switching the cache mode 4 9 3 4 Write Hit The cache controller handles processor writes that hit in the cache differently for write through and copyback regions For write hits to a write through region portions of cache lines corresponding to the size of the access are updated with the data The data is 4 16 MCF5307 User s Manual M woronoLA Cache Operation also written to external memory The cache line state is unchanged For copyback accesses the cache controller updates the cache line and sets the M bit for the line An external write is not performed and the cache line state changes to or remains in the modified state 4 9 4 Cache Coherency The MCF5307 provides limited cache coherency support in multiple master environments Both write through and copyback memory update techniques are supported to maintain coherency between the cache and memory
535. tdecesaceds 5 32 GO Command Sequence c s css sesscesssssessescessensesesscossnsesgusdesestsecesecenesesecssecessstsecesteess 5 33 GO Command 5 33 NOP Command Sequence 5 34 NOP Command Format eieiei n 5 34 SYNC PC Command Sequence 5 35 SYNC PC Comiand Format 5 35 RCREG Command 5 36 RCREG Command Result Formats eese nennen nnns 5 36 WCREG Command 5 37 WCREG Command Result Formats esee eee nnne 5 37 RDMREG Command Sequence ririri eni iorsin een e erni eE E EERE E Ea 5 38 RDMREG Command Result Formats eene nennen 5 38 WDMREG Command Sequence sse 5 39 WDMREG Command Format eese nennen nnne nnns 5 39 Recommended BDM 5 42 SIM Block Di gram 2 anteire IHE 6 1 Module Base Address Register MBAR eese 6 4 Reset Status Register 6 5 MCF5307 Embedded System Recovery from Unterminated 6 7 System Protection Control Register SYPCR sse 6 8 Software Watchdog Interrupt Vector Register SWIVR esee 6 9 Software Watchdog Service Register 6 9 Pin Assignment Regist
536. te Cache state in which only one caching device has the valid data for that address Most significant bit msb The highest order bit in an address registers data element or instruction encoding Most significant byte MSB The highest order byte in an address registers data element or instruction encoding M MOTOROLA Glossary of Terms and Abbreviations Glossary 13 Glossary 14 Nop No operation A single cycle operation that does not affect registers or generate bus activity Overflow An condition that occurs during arithmetic operations when the result cannot be stored accurately in the destination register s For example if two 16 bit numbers are multiplied the result may not be representable in 16 bits Pipelining A technique that breaks operations such as instruction processing or bus transactions into smaller distinct stages or tenures respectively so that a subsequent operation can begin before the previous one completes Precise mode A memory access mode that ensures that all write accesses to a specified memory region occur in order Set v To write a nonzero value to a bit or bit field the opposite of clear The term set may also be used to generally describe the updating of a bit or bit field Set A subdivision of a cache Cacheable data can be stored in a given location in any one of the sets typically corresponding to its lower order address bits Because several memory locations can map
537. te all Writing a 1 to this bit initiates entire cache invalidation Once invalidation is complete this bit automatically returns to 0 it is not necessary to clear it explicitly Note the caches are not cleared on power up or normal reset as shown in Figure 4 4 0 No invalidation is performed 1 Initiate invalidation of the entire cache The cache controller sequentially clears V and M bits in all sets Subsequent accesses stall until the invalidation is finished at which point this bit is automatically cleared In copyback mode the cache should be flushed using a CPUSHL instruction before setting this bit 23 11 Reserved should be cleared 10 DNFB Default noncacheable fill buffer Determines if the fill buffer can store noncacheable accesses 0 Fill buffer not used to store noncacheable instruction accesses 16 or 32 bits 1 Fill buffer used to store noncacheable accesses The fill buffer is used only for normal TT 0 instruction reads of a noncacheable region Instructions are loaded into the fill buffer by a burst access same as a line fill They stay in the buffer until they are displaced so subsequent accesses may not appear on the external bus Note that this feature can cause a coherency problem for self modifying code If DNFB 1 anda cache inhibited access uses the fill buffer instructions remain valid in the fill buffer until a cache invalidate all instruction another cache inhibited burst or a miss that initiat
538. te for 16 x 16 operations 16x 16 and 32 x 32 multiplies support all with 32 bit accumulate Signed or unsigned integer support plus signed fractional operands Hardware integer divide unit Unsigned and signed integer divide support Tightly coupled to the OEP 32 16 and 32 32 operation support producing quotient and or remainder results 8 Kbyte unified cache Four way set associative organization Operates at higher processor core frequency Provides pipelined single cycle access to critical code and data Supports write through and copyback modes Four entry 32 bit store buffer to improve performance of operand writes 4 Kbyte SRAM Programmable location anywhere within 4 Gbyte linear address space Higher core frequency operation Pipelined single cycle access to critical code or data MCF5307 User s Manual M woronoLA MCF5307 Features DMA controller Four fully programmable channels two support external requests Dual address and single address transfer support with 8 16 and 32 bit data capability Source destination address pointers that can increment or remain constant 24 bit transfer counter per channel Operand packing and unpacking supported Auto alignment transfers supported for efficient block movement Bursting and cycle steal support Two bus clock internal access Automatic DMA transfers from on chip UARTS using internal interrup
539. te transitions Table 18 11 Three Wire Bus Arbitration Protocol Transition Conditions ni Software Transfer ped M RSTI Watchdog BG PLA in E Next State Reset Progress y Reset A1 Asserted Reset A2 Negated Asserted Reset Negated Negated Negated EM A4 Negated Negated Asserted Implicit master Implicit B1 Negated Negated Negated External master device master B2 Negated Negated Asserted Explicit master B3 Negated Negated Asserted Negated Implicit master B4 Negated Negated Asserted Asserted Explicit master 18 32 MCF5307 User s Manual M woronoLA Reset Operation Table 18 11 Three Wire Bus Arbitration Protocol Transition Conditions Continued sa Software Transfer Current Condition RSTI Watchdog BG Bus in End 9 Next State State Label Request Cycle Reset Progress Explicit C1 Negated Negated Asserted Explicit master master C2 Negated Negated Negated Explicit master C3 Negated Negated Negated Negated External device master C4 Negated Negated Negated Yes Negated Explicit master C5 Negated Negated Negated Yes Yes External device master External D1 Negated Negated Negated External master device master D2 Negated Negated Asserted Explicit master D3 Negated Negated Ass
540. ted RxD is low for the entire character including the stop bit a character of all zeros is loaded into the receiver holding register RHR and USRn RB RxRDY are set RxD must return to a high condition for at least one half bit time before a search for the next start bit begins M woronoLA Chapter 14 UART Modules 14 23 Operation The receiver detects the beginning of a break in the middle of a character if the break persists through the next character time If the break begins in the middle of a character the receiver places the damaged character in the Rx FIFO stack and sets the corresponding USRn error bits and USRn RxRDY Then if the break lasts until the next character time the receiver places an all zero character into the Rx FIFO and sets USRn RB RxRDY 14 5 2 3 FIFO Stack The FIFO stack is used in the UART s receiver buffer logic The stack consists of three receiver holding registers The receive buffer consists of the FIFO and a receiver shift register connected to the RxD see Figure 14 20 Data is assembled in the receiver shift register and loaded into the top empty receiver holding register position of the FIFO Thus data flowing from the receiver to the CPU is quadruple buffered In addition to the data byte three status bits parity error PE framing error FE and received break RB are appended to each data character in the FIFO OE overrun error is not appended By programming the ERR bit in the channel
541. ted to the MCF5307 one of two situations can occur In the first case if the MCF5307 has an internal bus request pending the MCF5307 asserts BD to indicate explicit bus mastership and begins the pending bus cycle by asserting TS As M MOTOROLA Chapter 18 Bus Operation 18 25 General Operation of External Master Transfers shown in Figure 18 25 the MCF5307 continues to assert BD until the completion of the bus cycle If BG is negated by the end of the bus cycle the MCF5307 negates BD While BG is asserted BD remains asserted to indicate the MCF5307 is master and it continuously drives the address bus attributes and control signals Ci c2 c3 C4 C5 C6 C7 C8 BCLKO lt _ X RW xis External Master 5307 Figure 18 27 Two Wire Bus Arbitration with Bus Request Asserted In the second situation the bus is granted to the MCF5307 but it does not have an internal bus request pending so it takes implicit bus mastership The MCF5307 does not drive the bus and does not assert BD if the bus has an implicit master If an internal bus request is generated the MCF5307 assumes explicit bus mastership If explicit mastership was assumed because an internal request was generated the MCF5307 immediately begins an access and asserts BD In Figure 18 28 the external device is bus master during C1 and C2 During C3 the external
542. ter holding register and transmitter shift registers are empty This bit is set after transmission of the last stop bit of a character if there are no characters in the transmitter holding register awaiting transmission 2 TxRDY Transmitter ready 0 The CPU loaded the transmitter holding register or the transmitter is disabled 1 The transmitter holding register is empty and ready for a character TXRDY is set when a character is sent to the transmitter shift register and when the transmitter is first enabled If the transmitter is disabled characters loaded into the transmitter holding register are not sent 1 FFULL FIFO full 0 The FIFO is not full but may hold up to two unread characters 1 A character was received and is waiting in the receiver buffer FIFO 0 RxRDY Receiver ready 0 The CPU has read the receiver buffer and no characters remain in the FIFO after this read 1 One or more characters were received and are waiting in the receiver buffer FIFO 14 3 4 UART Clock Select Registers UCSRn The UART clock select registers UCSRn select an external clock on the TIN input divided by 1 or 16 or a prescaled BCLKO as the clocking source for the transmitter and receiver See Section 14 5 1 Transmitter Receiver Clock Source The transmitter and receiver can use different clock sources To use BCLKO for both set UCSR7 to OxDD 7 4 3 0 Field RCS TCS Reset 0000 0000 R W Write only
543. ter power up cache contents are undefined V and M may be set on some lines even though the cache may not contain the appropriate data for start up Because reset and power up do not invalidate cache lines automatically the cache should be cleared explicitly by setting CACR CINVA before the cache is enabled B After the entire cache is flushed cacheable entries are loaded first in way 0 If way 0 is occupied the cacheable entry is loaded into the same set in way 1 as shown in Figure 4 4 D This process is described in detail in Section 4 9 Cache Operation M MOTOROLA Chapter 4 Local Memory 4 9 Cache Organization Invalid V 0 m Valid not modified V 1 M 0 Valid modified V 1 M 1 A Cache population at B Cache after invalidation C Cache after loads in D First load in Way 1 start up before it is enabled Way 0 Way 0 Way 1 Way 2 Way 3 Way 0 Way 1 Way 2 Way 3 Way 0 Way 1 Way 2 Way 3 Way 0 Way 1 Way 2 Way 3 Set 0 Set 127 At reset cache contents Setting CACR CINVA Initial cacheable A line is loaded in are indeterminate V invalidates the entire accesses to memory fill way 1 only if that set is M may be set The cache cache positions in way 0 full in way 0 should be cleared explicitly by setting CACR CINVA before the cache is enabled Figure 4 4 Cache 4 at Reset B after Invalidation C and D Loading Pattern 4 10 MCF5307 User s Manual M woronoLA Cache Operation 4 9
544. terface 9 9 ete tette m mde 5 17 Receive Packet Format eere 5 19 Transmit Packet Format sees nennen eene 5 19 BDM Command Set esee nnne nennen 5 19 ColdFire Command Format eene 5 20 Extension Words as Required sese 5 21 Command Sequence Diagrams esses 5 21 Command Set Descriptions sess 5 23 Read A D Register RAREG RDREO eene 5 24 Write A D Register WAREG WDREG csscceccesseeseeeeeeeeeeseeeeeeeeeseenees 5 25 Read Memory Location READ esee 5 26 MCF5307 User s Manual M woronoLA CONTENTS Paragraph Title Page Number Number 5 5 3 3 4 Write Memory Location 5 27 5 5 3 3 5 Dump Memory Block 5 29 5 5 3 3 6 Fill Memory Block FILL nne 5 31 5 5 3 3 7 R sume Execution GO ate ae me Rae eee ta 5 33 5 5 3 3 8 No Operation NOP 5 5 3 3 9 Synchronize PC to the PST DDATA Lines SYNC PC 5 35 5 5 3 3 10 Read Control Register RCREO eese 5 36 5 5 3 3 11 Write Control Register WCREO eese 5 37 5 5 3 3 12 Read Debug Module Register RDMREO see 5 38 5 5 3 3 13 Write Debug Module Register WDMREG eee 5 39 5 6 Real Time Debug Support 5 39 5 6 1 Theory of
545. terface to standard synchronous asynchronous dynamic random access memory ADRAM SDRAM components Programmable SRAS SCAS and refresh timing e Support for page mode Support for 8 16 and 32 bit wide DRAM blocks e Support for synchronous and asynchronous DRAMs including EDO DRAM SDRAM and fast page mode M MOTOROLA Chapter 11 Synchronous Asynchronous DRAM Controller Module 11 1 Overview 11 1 1 Definitions The following terminology is used in this chapter e A SDRAM block Any group of DRAM memories selected by one of the MCF5307 RAS 1 0 signals Thus the MCF5307 can support two independent memory blocks The base address of each block is programmed in the DRAM address and control registers DACRO and DACR1 e SDRAM RAMSs that operate like asynchronous DRAMs but with a synchronous clock a pipelined multiple bank architecture and faster speed e SDRAM bank An internal partition in an SDRAM device For example a 64 Mbit SDRAM component might be configured as four 512K x 32 banks Banks are selected through the SDRAM component s bank select lines 11 1 2 Block Diagram and Major Components The basic components of the DRAM controller are shown in Figure 11 1 DRAM Controller Module E A 31 0 Address gt internal Multiplexing 31 0 A Page Hit m ml Logic Control Logig 2 State Machine RAS 1 0 CAS 3 0 Mem
546. terfaces with other memory structures 4 1 Interactions between Local Memory Modules Depending on configuration information instruction fetches and data read accesses may be sent simultaneously to the RAM and cache controllers This approach is required because both controllers are memory mapped devices and the hit miss determination is made concurrently with the read data access Power dissipation can be minimized by configuring the RAMBARs to mask unused address spaces whenever possible If the access address is mapped into the region defined by the RAM and this region is not masked the RAM provides the data back to the processor and the cache data is discarded Accesses from the RAM module are never cached The complete definition of the processor s local bus priority scheme for read references is as follows if RAM hits RAM supplies data to the processor else if cache hits cache supplies data to the processor else system memory reference to access data For data write references the memory mapping into the local memories is resolved before the appropriate destination memory is accessed Accordingly only the targeted local memory is accessed for data write transfers 4 2 SRAM Overview The 4 Kbyte on chip SRAM module is connected to the internal bus and provides pipelined single cycle access to memory mapped to the module Memory can be mapped to any MOTOROLA Chapter 4 Local Memory 4 1 SRAM Operation 0 m
547. th SRAM EPROM EEPROM and peripherals These signals are asserted and negated on the falling edge of the clock M MOTOROLA Chapter 17 Signal Descriptions 17 15 DRAM Controller Signals 17 6 1 Chip Select CS 7 0 Each chip select can be programmed for a base address location and for masking addresses port size and burst capability indication wait state generation and internal external termination Reset clears all chip select programming CSO is the only chip select initialized out of reset CSO is also unique because it can function at reset as a global chip select that allows boot ROM to be selected at any defined address space Port size and termination internal vs external for boot CSO are configured by the levels on D 7 5 on the rising edge of RSTI as described in Section 17 5 5 1 D 7 5Boot Chip Select CS0 Configuration The chip select implementation is described in Chapter 10 Chip Select Module 17 6 2 Byte Enables Byte Write Enables BE 3 0 BWE 3 0 The four byte enables are multiplexed with the MCF5307 byte write enable signals Each pin can be individually programmed through the chip select control registers CSCRs For each chip select assertion of byte enables for reads and byte write enables for write cycles can be programmed Alternatively users can program byte write enables to assert on writes and no byte enable assertion for read transfers 17 6 3 Output Enable OE The output enable
548. th a cycle using fast termination e In multiple master systems disabling arbitration with EARBCTRL allows performance improvement because internal register bus transfer cycles do not interfere with the external bus Having internal transfers go external may affect performance in two ways If the internal device does not control the bus immediately the core stalls until it wins arbitration of the external bus If the core wins arbitration instantly it may kick the external master off of the external bus unnecessarily for a transfer that did not need the external bus For debug where this performance penalty is not a concern setting EARBCTRL and SHOWDATA provides external visibility of the internal bus cycles M MOTOROLA Chapter 6 SIM Overview 6 15 Programming Model 6 16 MCF5307 User s Manual M Chapter 7 Phase Locked Loop PLL This chapter describes configuration and operation of the phase locked loop PLL module It describes in detail the registers and signals that support the PLL implementation 7 1 Overview The basic features of the MCF5307 PLL implementation are as follows The PLL locks to the clock input CLKIN frequency It provides a processor clock PCLK that is twice the input clock frequency and a programmable system bus clock output BCLKO that is 1 2 1 3 or 1 4 the PCLK frequency A buffered processor status clock PSTCLK is equal to the PCLK frequency as indicated in Fig
549. the responds to when addressed as a slave Note that it is not the address sent on the bus during the address transfer 7 6 5 4 3 2 1 0 Field ADR Reset 0000 0000 R W Read Write Address MBAR 0x280 Figure 8 5 12 Address Register IADR Table 8 2 describes IADR fields Table 8 2 C Address Register Field Descriptions Bits Name Description 7 1 ADR Slave address Contains the specific slave address to be used by the 2 module Slave mode is the default C mode for an address match on the bus 0 Reserved should be cleared 8 6 MCF5307 User s Manual M Programming Model 8 5 2 12 Frequency Divider Register IFDR The IFDR Figure 8 6 provides a programmable prescaler to configure the clock for bit rate selection 7 6 5 4 3 2 1 0 Field E IC Reset 0000_0000 R W Read Write Address MBAR 0x284 Figure 8 6 2 Frequency Divider Register IFDR Table 8 3 describes IFDR IC Table 8 3 IFDR Field Descriptions Bits Name Description 7 6 Reserved should be cleared 5 0 IC clock rate Prescales the clock for bit rate selection Due to potentially slow SCL and SDA rise and fall times bus signals are sampled at the prescaler frequency The serial bit clock frequency is equal to BCLKO divided by the divider shown below Note that IC can be chang
550. the processor core Software is responsible for guaranteeing that accesses to these resources are serialized and logically consistent Hardware provides a locking mechanism in the CSR to allow the external development system to disable any attempted writes by the processor to the breakpoint registers setting CSR IPW commands must not be issued if the MCF5307 is using the WDEBUG instruction to access debug module registers or the resulting behavior is undefined These registers shown in Figure 5 4 are treated as 32 bit quantities regardless of the number of implemented bits 31 15 7 0 Address attribute trigger register 31 15 0 ABLR Address low breakpoint register ABHR Address high breakpoint register 31 15 7 0 BAAR address attribute register 31 15 0 CSR Configuration status register 31 15 0 DBR Data breakpoint register DBMR Data breakpoint mask register 31 15 0 PBR PC breakpoint register PBMR breakpoint mask register 31 15 0 TDR Trigger definition register Note Each debug register is accessed as a 32 bit register shaded fields above are not used don t care All debug control registers are writable from the external development system or the CPU via the WDEBUG instruction CSR is write only from the programming model It can be read or written through the BDM port using the RDMREG and WDMREG commands Figure 5 4 Debug Prog
551. ting or reading a 0 has no effect 1 DMA transfer completed Writing a 1 to this bit clears all DMA status bits and can be used as an interrupt handler to clear the DMA interrupt and error bits 12 4 6 DMA Interrupt Vector Registers DIVRO DIVR3 The contents of a DMA interrupt vector register Figure 12 10 are driven onto the internal bus in response to an interrupt acknowledge cycle 7 0 Field Interrupt Vector Bits Reset 0000 1111 R W R W Address MBAR 0x314 0x354 0x394 0x3D4 Figure 12 10 DMA Interrupt Vector Registers DIVRn 12 5 DMA Controller Module Functional Description In the following discussion the term DMA request implies that DCR START or DCR EEXT is set followed by assertion of DREQ The START bit is cleared when the channel begins an internal access Before initiating a dual address access the DMA module verifies that DCR SSIZE DSIZE are consistent with the source and destination addresses If the source and destination are not the same size the configuration error bit DSR CE is also set If misalignment is detected no transfer occurs CE is set and depending on the DCR configuration an interrupt event is issued Note that if the auto align bit DCR AA is set error checking is performed on appropriate registers A read write transfer reads bytes from the source address and writes them to the destination address The number of bytes is the large
552. tion Bits Name Description 15 0 BA Base address Defines the base address for memory dedicated to chip select CS 7 0 BA is compared to bits 31 16 on the internal address bus to determine if chip select memory is being accessed 10 4 1 2 Chip Select Mask Registers CSMRO CSMR7 The chip select mask registers Figure 10 3 are used to specify the address mask and allowable access types for the respective chip selects 10 6 MCF5307 User s Manual M woronoLA Chip Select Registers 31 16 15 9 8 7 6 5432 1 0 Field BAM WP AM C I SC SD UC UD V Reset Unitialized 0 R W R W Addr 0x084 CSMRO 0x090 CSMR1 0 09 CSMR2 0x0A8 CSMR3 0x0B4 CSMR4 0x0CO CSMR5 0 0 CSMR6 0 008 CSMR7 Figure 10 3 Chip Select Mask Registers CSMRn Table 10 8 describes CSMR fields Table 10 8 CSMRn Field Descriptions Bits Name Description 31 16 BAM Base address mask Defines the chip select block by masking address bits Setting a BAM bit causes the corresponding CSAR bit to be ignored in the decode 0 Corresponding address bit is used in chip select decode 1 Corresponding address bit is a don t care in chip select decode The block size for CS 7 0 is 2 n number of bits set in respective CSMR BAM 16 So if CSARO 0x0000 and CSMRO BAM 0x0008 CS0 would address two discontinuous 64 Kbyte memory blocks one from 0x0000 0xFFFF
553. tion 1 2 3 3 SCAS assertion to data out 1 2 3 3 tras command to precharge command 2 4 6 6 tap Precharge command to command 1 2 3 3 taw tap Last data input to precharge 1 1 1 1 command tep Last data out to precharge command 1 1 1 1 11 Reserved should be cleared 10 8 CBM Command and bank MUX 2 0 Because different SDRAM configurations cause the command and bank select lines to correspond to different addresses these resources are programmable CBM determines the addresses onto which these functions are multiplexed CBM Command Bit Bank Select Bits 000 17 18 and up 001 18 19 and up 010 19 20 and up 011 20 21 and up 100 21 22 and up 101 22 23 and up 110 23 24 and up 111 24 25 and up This encoding and the address multiplexing scheme handle common SDRAM organizations Bank select bits include a base bit and all address bits above for SDRAMs with multiple bank select bits 7 Reserved should be cleared M MOTOROLA Chapter 11 Synchronous Asynchronous DRAM Controller Module 11 21 Synchronous Operation Table 11 13 DACRO DACR 1 Field Descriptions Synchronous Mode Continued Bit Name Description 6 IMRS Initiate mode register set MRS command Setting IMRS generates a MRS command to the associated SDRAMs In initialization IMRS should be set only after all DRAM controller registers are initialized and PALL and REFRESH commands have been issued
554. tion and correction information One way to provide error detection if 8 bit characters are not required is to use software to calculate parity and append it to the 5 6 or 7 bit character 14 5 5 Bus Operation This section describes bus operation during read write and interrupt acknowledge cycles to the UART module 14 5 5 1 Read Cycles The UART module responds to reads with byte data Reserved registers return zeros 14 5 5 2 Write Cycles The UART module accepts write data as bytes Write cycles to read only or reserved registers complete normally without exception processing but data is ignored NOTE The UART module is accessed by the CPU with zero wait states as BCLKO is used for the UART module 14 5 5 3 Interrupt Acknowledge Cycles The UART module supplies the interrupt vector in response to a UART IACK cycle If UIVRn is not initialized to provide a vector number a spurious exception is taken if an interrupt is generated This works in conjunction with the interrupt controller which allows a programmable priority level 14 5 6 Programming The software flowchart Figure 14 27 consists of the following UART module initialization These routines consist of SINIT and CHCHK sheets and 2 Before SINIT is called at system initialization the calling routine allocates 2 words on the system stack On return to the calling routine SINIT passes UART status data on the stack If SINIT finds no errors the tran
555. tion with anaddress register destination When an address register is a destination the entire register is affected regardless of the operation size Figure 2 8 shows integer formats for address registers 31 16 15 0 Sign Extended 16 Bit Address Operand 31 0 Full 32 Bit Address Operand Figure 2 8 Organization of Integer Data Formats in Address Registers The size of control registers varies according to function Some have undefined bits reserved for future definition by Motorola Those particular bits read as zeros and must be written as zeros for future compatibility All operations to the SR and CCR are word size operations For all CCR operations the upper byte is read as all zeros and is ignored when written regardless of privilege mode 2 4 2 Organization of Integer Data Formats in Memory All ColdFire processors use a big endian addressing scheme The byte addressable organization of memory allows lower addresses to correspond to higher order bytes The address N of a longword data item corresponds to the address of the high order word The lower order word is located at address N 2 The address N of a word data item corresponds to the address of the high order byte The lower order byte is located at address N 1 This 2 32 MCF5307 User s Manual M Addressing Mode Summary organization is shown in Figure 2 9 31 23 15 7 0 Longword 0x0000 0000 Word 0 0000 0000 Word 0 0000 0002
556. to the address bus Some differences exist for each of the three possible port sizes Note that only 8 bit ports use an AO address from the MCF5307 Because 16 and 32 bit ports issue either words or longwords when accessed they do not use the MCF5307 AO signal Likewise the configuration for 32 bit ports uses neither AO or A1 This presents a slight problem because DRAM address signal AO is issued on physical pin A17 of the MCF5307 along with the address signal A17 Although AO is not used for larger ports A17 is still needed The MCF5307 DRAM controller provides for this by changing the column address that appears on physical pin A17 of the processor whenever an 8 bit port is not selected This is determined by the DACRn PS settings For 8 bit ports MCF5307 physical pin A17 drives logical address AO during the CAS cycle When 16 or 32 bit port sizes are programmed the CAS cycle pin A17 drives logical address A16 as indicated in the generic connection scheme e fa32 bit port is used with only eight column address lines 18 must drive DRAM address bit A18 Otherwise in 32 bit port configurations the MCF5307 physical address line is not connected with more than eight column address lines e All ADRAM blocks have a fixed page size of 512 bytes for page mode operation The addresses are connected differently for various width combinations Table 11 7 Table 11 8 and Table 11 9 show how 8 16 and 32 bit symmetrical ADRAM
557. to these two signals must have open drain or open collector outputs There is no such requirement for inputs The logic AND function is exercised on both lines with external pull up resistors Out of reset the I C default is as slave receiver Thus when not programmed to be a master or responding to a slave transmit address the module should return to the default slave receiver state See Section 8 6 1 Initialization Sequence for exceptions NOTE The 2 module is designed to be compatible with the Philips bus protocol For information on system configuration protocol and restrictions see The Bus Specification Version 2 1 8 4 IC Protocol Normally a standard communication is composed of the following parts 1 START signal When no other device is bus master both SCL and SDA lines are at logic high a device can initiate communication by sending a START signal see A in Figure 8 2 A START signal is defined as a high to low transition of SDA while SCL is high This signal denotes the beginning of a data transfer each data transfer can be several bytes long and awakens all slaves msb Isb msb Isb MPL sf fet 1 1 1 1 1 1 1 1 1 1 1 1 1 1 o4 or sosfxos ioa soa nbafno fw os D5 7 os D2 Calling Address amp x 1 Data Byte A A Signal Bi Sonal sj
558. tor mode or DMA port multiplexed with PP 1 0 Transfer modifier TM 2 0 Provides transfer modifier O Parallel 17 10 information Multiplexed with port PP 4 2 Section 17 3 Interrupt Control Signals 17 12 Interrupt request IRQ7 IRQ5 Four external interrupts are set to Up 17 12 IRQS IRQ1 default levels 1 3 5 7 user alterable Section 17 4 Bus Arbitration Signals 17 12 Bus request BR Indicates processor needs bus High 17 12 Bus grant BG Arbiter asserts to grant mastership Note 17 12 Bus driven BD Indicates processor is driving bus High 17 13 Section 17 5 Clock and Reset Signals 17 13 Reset in RSTI Processor reset input Up 17 13 Clock input CLKIN Input used to clock internal logic 17 13 Bus clock out BCLKO Bus clock reference output 17 13 Reset out RSTO Processor reset output Low 17 13 Auto acknowledge AA CONFIG Controls auto acknowledge timing 17 14 configuration for CSO at reset Port size configuration 2 PS CONFIG 1 0 Controls port size for CSO at reset User cfg 17 14 Address configuration ADDR_CONFIG_ Programs parallel I O ports User cfg 17 14 M MOTOROLA Chapter 17 Signal Descriptions 17 3 Overview Table 17 1 MCF5307 Signal Index Continued Signal Name Abbreviation Function VO Reset Pull Up Page Frequency control PLL FREQ 1 0 Indicates CLK
559. transition of the start bit on RxD the state of RxD is sampled each 16x clock for eight clocks starting one half clock after the transition asynchronous operation or at the next rising edge of the bit time clock synchronous operation If RxD is sampled high the start bit is invalid and the search for the valid start bit begins again If RxD is still low a valid start bit is assumed and the receiver continues sampling the input at one bit time intervals at the theoretical center of the bit until the proper number of data bits and parity if any is assembled and one stop bit is detected Data on the RxD input is sampled on the rising edge of the programmed clock source The Isb is received first The data is then transferred to a receiver holding register and USRn RxRDY is set If the character is less than eight bits the most significant unused bits in the receiver holding register are cleared After the stop bit is detected the receiver immediately looks for the next start bit However if a non zero character is received without a stop bit framing error and RxD remains low for one half of the bit period after the stop bit is sampled the receiver operates as if a new start bit were detected Parity error framing error overrun error and received break conditions set the respective PE FE OE RB error and break flags in the USRn at the received character boundary and are valid only if USRn RxRDY is set If a break condition is detec
560. ts DRAM controller Synchronous DRAM SDRAM extended data out EDO DRAM and fast page mode support Up to 512 Mbytes of DRAM Programmable timer provides CAS before RAS refresh for asynchronous DRAMs Support for two separate memory blocks Two UARTs Full duplex operation Programmable clock Modem control signals available CTS RTS Processor interrupt capability Dual 16 bit general purpose multiple mode timers 8 bit prescaler Timer input and output pins Processor interrupt capability Up to 22 nS resolution at 45 MHz IC module Interchip bus interface for EEPROMs LCD controllers A D converters and keypads Fully compatible with industry standard PC bus Master or slave modes support multiple masters Automatic interrupt generation with programmable level e System interface module SIM Chip selects provide direct interface to 8 16 and 32 bit SRAM ROM M MOTOROLA Chapter 1 Overview 1 5 MCF5307 Features FLASH and memory mapped I O devices Eight fully programmable chip selects each with a base address register Programmable wait states and port sizes per chip select User programmable processor clock input clock frequency ratio Programmable interrupt controller Low interrupt latency Four external interrupt request inputs Programmable autovector generator Software watchdog timer e 16 bit general purpose I O i
561. ts from the V2 ColdFire core and then fully describes the V3 programming model as it is implemented on the MCF5307 It also includes a full description of exception handling data formats an instruction set summary and a table of instruction timings Chapter 3 Hardware Multiply Accumulate MAC Unit describes the MCF5307 multiply accumulate unit which executes integer multiply multiply accumulate and miscellaneous register instructions The MAC is integrated into the operand execution pipeline OEP Chapter 4 Local Memory This chapter describes the MCF5307 implementation of the ColdFire V3 local memory specification It consists of the two following major sections Section 4 2 SRAM Overview describes the MCF5307 on chip static RAM SRAM implementation It covers general operations configuration and initialization It also provides information and examples showing how to minimize power consumption when using the SRAM Section 4 7 Cache Overview describes the MCF5307 cache implementation including organization configuration and coherency It describes cache operations and how the cache interacts with other memory structures Chapter 5 Debug Support describes the Revision C enhanced hardware debug support in the MCF5307 This revision of the ColdFire debug architecture encompasses earlier revisions M MOTOROLA Part I MCF5307 Processor Core I xvii Suggested Reading The followi
562. uce a 32 bit product Longword operations are performed by reusing the 16 bit multiplier array at the expense of a small amount of extra control logic Again the product of two 32 bit operands is a 32 bit result For longword integer operations only the least significant 32 bits of the product are calculated For fractional operations the entire 63 bit product is calculated and then either truncated or rounded to a 32 bit result using the round to nearest even method Because the multiplier array is implemented in a 3 stage pipeline MAC instructions can have an effective issue rate of one clock for word operations three for longword integer operations and four for 32 bit fractional operations Arithmetic operations use register based input operands and summed values are stored internally in the accumulator Thus an additional MOVE instruction is necessary to store data in a general purpose register MAC instructions can choose the upper or lower word of a register as the input which helps filtering operations in which one data register is loaded with input data and another is loaded with coefficient data Two 16 bit MAC operations can be performed without fetching additional operands between instructions by alternating the word choice M MOTOROLA Chapter 3 Hardware Multiply Accumulate MAC Unit 3 3 Overview during the calculations The need to move large amounts of data quickly can limit throughput in DSP engines However data can b
563. uffer defers pending writes to write through or cache inhibited regions to maximize performance Cache inhibited precise mode accesses always bypass the store buffer 28 DPI Disable CPUSHL invalidation 0 Normal operation A CPUSHL instruction causes the selected line to be pushed if modified and then invalidated 1 No clear operation A CPUSHL instruction causes the selected line to be pushed if modified then left valid MOTOROLA Chapter 4 Local Memory 4 21 Cache Registers Table 4 4 CACR Field Descriptions Continued Bits Name Description 27 Half cache lock mode 0 Normal operation The cache allocates the lowest invalid way If all ways are valid the cache allocates the way pointed at by the counter and then increments this counter modulo 4 Half cache operation The cache allocates to the lower invalid way of levels 2 and 3 if both are valid the cache allocates to way 2 if the high order bit of the round robin counter is zero otherwise it allocates way 3 and increments the round robin counter modulo 2 This locks the content of ways 0 and 1 Ways 0 and 1 are still updated on write hits and may be pushed or cleared by specific cache push invalidate instructions This implementation allows maximum use of available cache memory and provides the flexibility of setting HLCK before during or after allocations occur 22 26 25 Reserved should be cleared 24 CINVA Cache invalida
564. uld be cleared 0 RTS Output port parallel output Controls assertion UOP1 negation UOPO of RTS output 0 Not affected 1 Asserts RTS UOP1 Negates RTS UOPO 14 4 UART Module Signal Definitions Figure 14 17 shows both the external and internal signal groups BELKO gt Clock Source External Clock TIN Generator Output Port RIS UART Module Internal Bus Input Port lg GIS _ A m Control External Internal Interface Control Four Character RxD Signals peace Address Bus Logic Receive Buffer to CPU I Data Two Character TxD _ gt Transmit Buffer ieu To Interrupt Controller IRQ SIM Y Figure 14 17 UART Block Diagram Showing External and Internal Interface Signals An internal interrupt request signal IRQ is provided to notify the interrupt controller of an interrupt condition The output is the logical NOR of unmasked UISRn bits The interrupt level of a UART module is programmed in the interrupt controller in the system integration module SIM The UART can use the autovector for the programmed interrupt level or supply the vector from the UIVRn when the UART interrupt is acknowledged 14 16 MCF5307 User s Manual M woronoLA UART Module Signal Definitions The interrupt level priority and auto vectoring capability is programmed in SIM register ICR4 for UARTO and ICR5 for UARTI See Section 9 2 1 Interrupt Control
565. upts the CPU when the timer reaches a set value while a third mode counts external events The timer unit has an 8 bit prescaler that allows programming of the clock input frequency which is derived from the system bus cycle or an external clock input pin TIN The programmable timer output pin generates either an active low pulse or toggles the output 1 3 6 I2C Module The I C interface is a two wire bidirectional serial bus used for quick data exchanges between devices The IC minimizes the interconnection between devices in the end system and is best suited for applications that need occasional bursts of rapid communication over M MOTOROLA Chapter 1 Overview 1 9 ColdFire Module Description short distances among several devices The PC can operate in master slave or multiple master modes 1 3 7 System Interface The MCF5307 processor provides a direct interface to 8 16 and 32 bit FLASH SRAM ROM and peripheral devices through the use of fully programmable chip selects and write enables Support for burst ROMs is also included Through the on chip PLL users can input a slower clock 16 6 to 45 MHz that is internally multiplied to create the faster processor clock 33 3 to 90 MHz 1 3 7 1 External Bus Interface The bus interface controller transfers information between the ColdFire core or DMA and memory peripherals or other devices on the external bus The external bus interface provides up to 32 bits of address b
566. ure 7 1 This signal is made available for system development The PLL module has the following three modes of operation Reset mode In reset mode the core bus frequency ratio and other configuration information is sampled At reset the PLL asserts the reset out signal RSTO Normal mode During normal operations the divide ratio is programmed at reset and is clock multiplied to provide a maximum frequency of 90 MHz Reduced power mode In reduced power mode the high speed processor core clocks are turned off without losing the register contents so that the system can be reenabled by an unmasked interrupt or reset Figure 7 1 shows the frequency relationships of PLL module clock signals RSTO PCLK E D PSTCLK idi CLKINX 4 po BCLKO FREQ 1 0 RSTI DIVIDE 1 0 Figure 7 1 PLL Module Block Diagram M MOTOROLA Chapter 7 Phase Locked Loop PLL 7 1 PLL Operation 7 1 1 PLL PCLK Ratios The specifications for the clocks in the PLL module are summarized in Table 0 1 Table 0 1 PLL Clock Specifications Symbol Description Frequency PLL lock time 2 2 mS with CLKIN running at 45 MHz CLKIN Input clock 16 67 MHz 45 MHz PCLK Internal processor clock 33 34 MHz 90 MHz CLKIN x 2 PSTCLK Processor status clock 33 34 MHz 90 MHz CLKIN x 2 BCLKO Output clock 16 67 MHz 45 MHz 11 11 MHz 30 MHz 8 24 MHz 22 5 MHz BC
567. uring the entire transfer or only at the final transfer of a DMA transaction New applications should take advantage of the full range of the 24 bit byte counter including the AT bit The 16 bit byte count option BCR24BIT 0 retains compatibility with older MCF5307 revisions NOTE External masters cannot access MCF5307 on chip memories or MBAR but they can access DMA module registers 12 4 1 Source Address Registers SARO SAR3 SARn Figure 12 4 contains the address from which the DMA controller requests data In single address mode SAR7 provides the address regardless of the direction 81 0 Field SAR Reset 0000 0000 0000 0000 0000 0000 0000 0000 R W R W Address MBAR 0x300 0x340 0x380 0x3CO Figure 12 4 Source Address Registers SARn NOTE SAR DAR address ranges cannot be programmed to on chip SRAM because it cannot be accessed by on chip DMA 12 6 MCF5307 User s Manual M woronoLA DMA Controller Module Programming Model 12 4 2 Destination Address Registers DARO DAR3 For dual address transfers only DARn Figure 12 5 holds the address to which the DMA controller sends data 31 0 Field DAR Reset 0000 0000 0000 0000 0000 0000 0000 0000 R W R W Address MBAR 304 0x344 0x384 0x3C4 Figure 12 5 Destination Address Registers DARn NOTE On chip DMAs do not maintain coherency with MCF5307 caches and so must not transfer data to cacheable memor
568. us space a 32 bit data bus and all associated control signals This interface implements an extended synchronous protocol that supports bursting operations Simple two wire request acknowledge bus arbitration between the MCF5307 processor and another bus master such as an external DMA device is glueless with arbitration logic internal to the MCF5307 processor Multiple master arbitration is also available with some simple external arbitration logic 1 3 7 2 Chip Selects Eight fully programmable chip select outputs support the use of external memory and peripheral circuits with user defined wait state insertion These signals interface to 8 16 or 32 bit ports The base address access permissions and internal bus transfer terminations are programmable with configuration registers for each chip select CSO also provides global chip select functionality of boot ROM upon reset for initializing the MCF5307 1 3 7 3 16 Bit Parallel Port Interface A 16 bit general purpose programmable parallel port serves as either an input or an output on a pin by pin basis 1 3 7 4 Interrupt Controller The interrupt controller provides user programmable control of ten internal peripheral interrupts and implements four external fixed interrupt request pins Each internal interrupt can be programmed to any one of seven interrupt levels and four priority levels within each of these levels Additionally the external interrupt request pins can be mapped to le
569. using the WDEBUG instruction and through the BDM port using the RDMREG and WDMREG commands 2 Bit 7 is reserved for Motorola use and must be written as a zero Figure 5 8 Configuration Status Register CSR Table 5 8 describes CSR fields 5 10 MCF5307 User s Manual M woronoLA Programming Model Table 5 8 CSR Field Descriptions Bit Name Description 31 28 BSTAT Breakpoint status Provides read only status information concerning hardware breakpoints BSTAT is cleared by a TDR write or by a CSR read when either a level 2 breakpoint is triggered or a level 1 breakpoint is triggered and the level 2 breakpoint is disabled 0000 No breakpoints enabled 0001 Waiting for level 1 breakpoint 0010 Level 1 breakpoint triggered 0101 Waiting for level 2 breakpoint 0110 Level 2 breakpoint triggered 27 FOF Fault on fault If FOF is set a catastrophic halt occurred and forced entry into BDM 26 TRG_ Hardware breakpoint trigger If TRG is set a hardware breakpoint halted the processor core and forced entry into BDM Reset and the debug Go command clear TRG 25 HALT Processor halt If HALT is set the processor executed a HALT and forced entry into BDM Reset and the debug GO command reset HALT 24 Breakpoint assert If BKPT is set BKPT was asserted forcing the processor into BDM Reset and the debug GO command clears this bit 23 20 HRL Hardware revision level Indicates th
570. ust be cleared early in the exception handler before the timer negates the IRQn to the interrupt controller 7 2 1 0 Field REF CAP Reset 0000_0000 R W R W ones clear zeros have no effect Address MBAR 0x151 TERO 0x191 TER1 Figure 13 6 Timer Event Registers TERO TER1 MOTOROLA Chapter 13 Timer Module 13 5 Code Example Table 13 3 describes TERn fields Table 13 3 TERn Field Descriptions Bits Name Description 7 2 Reserved 1 REF Output reference event The counter has reached the TRRn value Setting TMRn ORI enables the interrupt request caused by this event Writing a one to REF clears the event condition 0 CAP Capture event The counter value has been latched into TCRn Setting TMRn CE enables the interrupt request caused by this event Writing a 1 to CAP clears the event condition 13 4 Code Example The following code provides an example of how to initialize timer 0 and how to use the timer for counting time out periods MBARx EQU 0x10000 Defines the module base address at 0x10000 TMRO EQU MBARx 0x140 Timer 0 register 1 EQU MBARx 0x180 Timer 1 register TRRO EQU MBARx 0x144 Timer 0 reference register TRR1 EQU MBARx 0x184 Timer 1 reference register TCRO EQU 0 148 Timer 0 capture register EQU 0 188 Timer 1 capture register TCNO EQU 0 14 Timer 0 counter TCN1
571. ut 186 DDATAO O Debug data 8 187 DDATA1 O Debug data 8 188 GND Ground pin 189 DDATA2 O Debug data 8 190 DDATA3 O Debug data 8 191 Power input 192 PSTO Processor status 8 193 PST1 O Processor status 8 194 GND Ground pin 195 PST2 O Processor status 8 196 PST3 O Processor status 8 197 VCC Power input 198 PP7 TIP Parallel port bit transfer in progress 8 199 PP6 DREQO Parallel port bit DMA request 8 200 PP5 DREQ1 Parallel port bit DMA request 8 201 GND Ground 202 PP4 TM2 Parallel port bit Transfer modifier 8 203 PP3 TM1 Parallel port bit Transfer modifier 8 204 PP2 TMO Parallel port bit Transfer modifier 8 205 Power input M Chapter 16 Mechanical Data 16 7 Mechanical Diagram Table 16 4 Pins 157 208 Top Right to Left Continued 2 Description ae No Name 206 PP1 TT1 Parallel port bit Transfer type 8 207 PPO TTO Parallel port bit Transfer type 8 208 GND Ground 16 3 Mechanical Diagram Figure 16 1 is a mechanical diagram of the 208 pin QFP MCF5307 16 8 MCF5307 User s Manual M MOTOROLA Case Drawing on EB ES 5 58 088 9 8 rOQEEAEE Y o Qol lt lt
572. ve edges of the UART clock 6 FE Framing error 0 No framing error occurred 1 No stop bit was detected when the corresponding data character in the FIFO was received The stop bit check occurs in the middle of the first stop bit position FE is valid only when RxRDY 1 MOTOROLA Chapter 14 UART Modules 14 7 Register Descriptions Table 14 4 USRn Field Descriptions Continued Bits Name Description 5 PE Parity error Valid only if RXRDY 1 0 No parity error occurred 1 IF UMR1n PM Ox with parity or force parity the corresponding character in the FIFO was received with incorrect parity If UMR1n PM 11 multidrop PE stores the received A D bit 4 OE Overrun error Indicates whether an overrun occurs 0 No overrun occurred 1 One or more characters in the received data stream have been lost OE is set upon receipt of a new character when the FIFO is full and a character is already in the shift register waiting for an empty FIFO position When this occurs the character in the receiver shift register and its break detect framing error status and parity error if any are lost OE is cleared by the RESET ERROR STATUS command in UCRn 3 TxEMP Transmitter empty 0 The transmitter buffer is not empty Either a character is being shifted out or the transmitter is disabled The transmitter is enabled disabled by programming UCRn TC 1 The transmitter has underrun both the transmit
573. ved 10 Emulator mode access 11 Acknowledge CPU space access These bits also define the TT encoding for BDM memory commands In this case the 01 encoding indicates an external or DMA access for backward compatibility These bits affect the TM bits 2 0 TM Transfer modifier Compared with the local bus transfer modifier signals which give supplemental information for each transfer type TT 00 normal mode 000 Explicit cache line push 001 User data access 010 User code access 011 Reserved 100 Reserved 101 Supervisor data access 110 Supervisor code access 111 Reserved TT 10 emulator mode 0xx 100 Reserved 101 Emulator mode data access 110 Emulator mode code access 111 Reserved TT 11 acknowledge CPU space transfers 000 CPU space access 001 111 Interrupt acknowledge levels 1 7 These bits also define the TM encoding for BDM memory commands for backward compatibility 5 4 2 Address Breakpoint Registers ABLR ABHR The address breakpoint low and high registers ABLR ABHR Figure 5 6 define regions in the processor s data address space that can be used as part of the trigger These register values are compared with the address for each transfer on the processor s high speed local bus The trigger definition register TDR identifies the trigger as one of three cases 1 2 identically the value in ABLR inside the range bound by ABLR and ABHR inclusive 3 outside that same r
574. vels 1 3 5 and 7 or levels 2 4 6 and 7 Autovector capability is available for both internal and external interrupts 1 10 MCF5307 User s Manual M woronoLA ColdFire Module Description 1 3 7 5 JTAG To help with system diagnostics and manufacturing testing the MCF5307 processor includes dedicated user accessible test logic that complies with the IEEE 1149 1a standard for boundary scan testability often referred to as the Joint Test Action Group or JTAG For more information refer to the IEEE 1149 1a standard 1 3 8 System Debug Interface The ColdFire processor core debug interface is provided to support system debugging in conjunction with low cost debug and emulator development tools Through a standard debug interface users can access real time trace and debug information This allows the processor and system to be debugged at full speed without the need for costly in circuit emulators The debug unit in the MCF5307 is a compatible upgrade to the MCF52xx debug module with added flexibility in the breakpoint registers and a new command to view the program counter PC The on chip breakpoint resources include a total of 6 programmable registers a set of address registers with two 32 bit registers a set of data registers with a 32 bit data register plus a 32 bit data mask register and one 32 bit PC register plus a 32 bit PC mask register These registers can be accessed through the dedicated debug serial communication cha
575. ven in Chapter 20 Electrical Specifications On the rising edge of BCLKO before the rising edge of RSTI the data on D 7 0 is latched and the PLL begins ramping to its final operating frequency During this ramp and lock time BCLKO and PSTCLK are held low The PLL locks in about 2 2 mS with a 45 MHz CLKIN at which time BCLKOand PSTCLK begin normal operation in the specified mode The PLL requires 100 000 CLKIN cycles to guarantee PLL lock To allow for reset of external peripherals requiring a clock source RSTO remains asserted for a number of BCLKO cycles as shown in Figure 7 4 MOTOROLA Chapter 7 Phase Locked Loop PLL 7 5 PLL Power Supply Filter Circuit 100K CLKIN gt 80 CLKIN ee Lock Tine gt CLKIN lt ai 30BCLKO BCLKO 1 2 MODE MU 20BCLKO gt BCLKO 1 3 MODE M L 15BCLKO M BCLKO 1 4 MODE PSTCLK r we 7 EEEN D 7 0 latched Figure 7 4 Reset and Initialization Timing 7 5 PLL Power Supply Filter Circuit To ensure PLL stability the power supply to the PLL power pin should be filtered using a circuit similar to the one in Figure 7 5 The circuit should be placed as close as possible to the PLL power pin to ensure maximum noise filtering 10 Q Vdd O PLL power pin 10gF 04 uF Figure 7 5 PLL Power Supply Filter Circuit 7 6 MCF5307 User s Manual M wo
576. w provides an example of how to initialize the chip selects Only chip selects 0 1 2 and 3 are programmed here chip selects 4 5 6 and 7 are left invalid MBARx defines the base of the module address space CSARO EQU MBARx 0x080 Chip select 0 address register CSMRO EQU MBARx 0x084 Chip select 0 mask register CSCRO EQU MBARx 0x08A Chip select 0 control register CSAR1 EQU MBARx 0x08C Chip select 1 address register CSMR1 EQU MBARx 0x090 Chip select 1 mask register CSCR1 EQU MBARx 0x096 Chip select 1 control register CSAR2 EQU MBARx 0x098 Chip select 2 address register CSMR2 EQU MBARx 0x09C Chip select 2 mask register CSCR2 EQU MBARx 0x0A2 Chip select 2 control register CSAR3 EQU MBARx 0x0A4 Chip select 3 address register CSMR3 EQU MBARx 0x0A8 Chip select 3 mask register CSCR3 EQU MBARx 0x0AE Chip select 3 control register CSAR4 EQU MBARx 0x0BO Chip select 4 address register CSAR4 EQU MBARx 0x0B4 Chip select 4 mask register CSMR4 EQU MBARx 0x0BA Chip select 4 control register CSAR5 EQU MBARx 0x0BC Chip select 5 address register CSMR5 EQU MBARx 0x0CO Chip select 5 mask register CSCR5 EQU MBARx 0x0C6 Chip select 5 control register CSAR6 EQU MBARx 0x0C8 Chip select 6 address register CSMR6 EQU 0 0 Chip select 6 mask register CSCR6 EQU MBARx 0x0D2 Chip select 6 control register CSAR7 EQU MBARx 0x0D4 Chip select 7 address register CSMR7 EQU MBARx 0x0D8 Chip select 7 mask register CSCR7 EQU MB
577. which is the only possible access error Exception processing proceeds immediately Because the write cycle can be decoupled from the processor s issuing of the operation error signaling appears to be decoupled from the instruction that generated the write Accordingly the PC in the exception stack frame represents the program location when the access error was signaled See Section 2 8 2 Processor Exceptions M Chapter 4 Local Memory 4 17 Cache Operation 4 9 5 2 Cache Pushes Cache pushes occur for line replacement and as required for the execution of the CPUSHL instruction To reduce the requested data s latency in the new line the modified line being replaced is temporarily placed in the push buffer while the new line is fetched from memory After the bus transfer for the new line completes the modified cache line is written back to memory and the push buffer is invalidated 4 9 5 2 1 Push and Store Buffers The 16 byte push buffer reduces latency for requested new data on a cache miss by holding a displaced modified cache line while the new data is read from memory If a cache miss displaces a modified line a miss read reference is immediately generated While waiting for the response the current contents of the cache location load into the push buffer When the burst read bus transaction completes the cache controller can generate the appropriate line write bus transaction to write the push buffer contents
578. wing General View 16 10 MCF5307 User s Manual M woronoLA Case Drawing PLATING X B UR D e 2 View A Three Places Section A A 160 Places Rotated 90 CW GAGE PLANE View B Figure 16 3 Case Drawing Details The dimensions in Figure 16 2 and Figure 16 3 are referenced in Table 16 5 Table 16 5 Dimensions Dimension Millimeters Reference Minimum Maximum A 4 10 A1 0 25 0 50 A2 3 20 3 60 b 0 17 0 27 b1 0 17 0 23 c 0 09 0 20 c1 0 09 0 16 D 30 60 BSC M Chapter 16 Mechanical Data 16 11 Case Drawing 16 12 Table 16 5 Dimensions Continued Dimension Millimeters Reference Minimum Maximum D1 28 00 BSC 0 50 BSC E 30 60 BSC E1 28 00 BSC L 0 45 0 75 L1 1 30 REF R1 0 08 R2 0 08 0 25 S 0 20 9 0 8 91 0 02 5 16 MCF5307 User s Manual M MOTOROLA Chapter 17 Signal Descriptions This chapter describes MCF5307 signals It includes an alphabetical listing of signals showing multiplexing whether it is an input or output to the MCF5307 the state at reset and whether a pull up resistor should be used The following chapter Chapter 18 Bus Operation describes how these signals interact NOTE The terms assertion and negation are used to avoid confusion when dealing with a mixture of active low and active high signals
579. with a character 14 3 11 UART Divider Upper Lower Registers UDUn UDLn The UDUD registers formerly called UBG1n holds the and the UDLn registers formerly UBG2n hold the LSB of the preload value UDUn and UDLn concatenate to provide a divider to BCLKO for transmitter receiver operation as described in Section 14 5 1 2 1 BCLKO Baud Rates 7 0 Field Divider MSB Reset 0000_0000 R W R W Address MBAR 0x1D8 UDUO 0x218 UDU1 Figure 14 12 UART Divider Upper Register UDUn 7 0 Field Divider LSB Reset 0000_0000 R W R W Address MBAR 0x1DC UDLO 0x21C UDL1 Figure 14 13 UART Divider Lower Register UDL n NOTE The minimum value that can be loaded on the concatenation of UDUn with UDLn is 0x0002 Both UDUn and UDLz are write only and cannot be read by the CPU 14 14 MCF5307 User s Manual M woronoLA Register Descriptions 14 3 12 UART Interrupt Vector Register UIVRn The UIVRnz Figure 14 14 contain the 8 bit internal interrupt vector number IVR 7 0 Field IVR Reset 0000 1111 R W R W Address MBAR 0x1F0 UIVRO 0x230 UIVR1 Figure 14 14 UART Interrupt Vector Register UIVRn Table 14 10 describes UIVRn fields Table 14 10 UIVRn Field Descriptions Bits Name Description 7 0 Interrupt vector Indicates the vector number where the address of the exception handler for the specified interrupt is locate
580. wledge signal is sent to the bus at the ninth clock bit after receiving one byte of data 1 No acknowledge signal response is sent that is acknowledge bit 1 2 RSTA Repeat start Always read as 0 Attempting a repeat start without bus mastership causes loss of arbitration 0 No repeat start 1 Generates a repeated START condition 1 0 Reserved should be cleared 8 8 MCF5307 User s Manual M woronoLA Programming Model 8 5 4 12 Status Register I2SR This I2SR contains bits that indicate transaction direction and status 7 6 5 4 3 2 1 0 Field ICF IAAS IBB IAL SRW RXAK Reset 1000 0001 R W R R W R R W R Address MBAR 0x28C Figure 8 8 I2CR Status Register I2SR Table 8 5 describes I2SR fields Table 8 5 I2SR Field Descriptions Bits Name Description 7 ICF Data transferring bit While one byte of data is transferred ICF is cleared 0 Transfer in progress 1 Transfer complete Set by the falling edge of the ninth clock of a byte transfer 6 IAAS 2 addressed as a slave bit The CPU is interrupted if IPCR IIEN is set Next the CPU must check SRW and set its TX RX mode accordingly Writing to I2CR clears this bit 0 Not addressed 1 Addressed as a slave Set when its own address IADR matches the calling address 5 IBB bus busy bit Indicates the status of the bus 0 Bus is idle If a STOP signal is detected IBB i
581. words The OEP experiences no sequence related pipeline stalls For the MCF5307 the most common example of this type of stall involves consecutive store operations excluding the MOVEM instruction For all store operations except MOVEM 2 40 MCF5307 User s Manual M Instruction Timing certain hardware resources within the processor are marked as busy for two clock cycles after the final DSOC cycle of the store instruction If a subsequent store instruction is encountered within this two cycle window it is stalled until the resource again becomes available Thus the maximum pipeline stall involving consecutive store operations is two cycles e OEP can complete all memory accesses without memory causing any stall conditions Thus timing details in this section assume an infinite zero wait state memory attached to the core All operand data accesses are assumed to be aligned on the same byte boundary as the operand size 16 bit operands aligned on 0 modulo 2 addresses 32 bit operands aligned on 0 modulo 4 addresses Operands that do not meet these guidelines are misaligned Table 2 9 shows how the core decomposes a misaligned operand reference into a series of aligned accesses Table 2 9 Misaligned Operand References A 1 0 Size Bus Operations Additional C R W 1 x1 Word Byte Byte 2 1 0 if read 1 0 1 if write x1 Long Byte Word Byte 2 0 if read 10 Long Word
582. write The DMA controller drives the DAR value onto the address bus If DCR DINC is set DAR increments by the appropriate number of bytes at the completion of a successful write cycle The BCR decrements by the appropriate number of bytes DSR DONE is set when BCR reaches zero If the BCR is greater than zero another read write transfer is initiated If the BCR is a multiple of DCR BWC the DMA request signal is negated until termination of the bus cycle to allow the internal arbiter to switch masters If a termination error occurs DSR BES DONE are set and DMA transactions stop 12 5 2 2 Single Address Transfers Single address transfers consist of one DMA bus cycle allowing either a read or a write cycle to occur The DMA controller begins a single address transfer sequence when DCR SAA is set during a DMA request If no error condition exists DSR REQ is set When the channel is enabled DSR BSY is set and REQ is cleared SAR contents are then driven onto the address bus and the value of DCR S RW is driven on R W The BCR decrements on each successful address access until it is zero when DSR DONE is set If a termination error occurs DSR BES DONE are set and DMA transactions stop 12 5 3 Channel Initialization and Startup Before a block transfer starts channel registers must be initialized with information describing configuration request generation method and the data block 12 5 3 1 Channel Prioritization The four DM
583. x188 Timer 1 capture register TCR1 p 13 4 Reserved 0x18C Timer 1 counter TCN1 p 13 5 Reserved 0x190 Reserved Timer 1 event register Reserved TER1 p 13 5 13 3 1 Timer Mode Registers TMRO TMR1 Timer mode registers TMRO TMRI Figure 13 2 program the prescaler and various timer modes 15 8 7 6 5 4 3 2 1 0 Field PS CE OM ORI FRR CLK RST Reset 0000 0000 0000 0000 R W R W Address MBAR 0x140 TMRO 0x180 TMR1 Figure 13 2 Timer Mode Registers TMRO TMR1 Table 13 2 describes TMRn fields M MOTOROLA Chapter 13 Timer Module 13 3 General Purpose Timer Programming Model Table 13 2 TMRn Field Descriptions Bits Name Description 15 8 PS Prescaler value The prescaler is programmed to divide the clock input BCLKO 16 or 1 or clock TIN by values from 1 PS 0000 0000 to 256 PS 1111 1111 7 6 CE Capture edge and enable interrupt 00 Disable interrupt on capture event 01 Capture on rising edge only and enable interrupt on capture event 10 Capture on falling edge only and enable interrupt on capture event 11 Capture on any edge and enable interrupt on capture event 5 Output mode 0 Active low pulse for one BCLKO cycle 22 nS at 45 MHz 33 nS at 30 MHz 44 nS at 22 5 MHz 1 Toggle output 4 ORI Output reference interrupt enable If ORI is set when TERn REF 1 an interrupt occurs 0 Disable interrupt for referen
584. xternal bus master and includes detailed timing diagrams showing the interaction of signals in supported bus operations Chapter 11 Synchronous Asynchronous DRAM Controller Module describes DRAM cycles 18 1 Features The following list summarizes bus operation features e Up to 32 bits of address and data e 8 16 and 32 bit port sizes Byte word longword and line size transfers e Bus arbitration for external devices Burst and burst inhibited transfer support Internal termination for core and DMA bus cycles e External termination of bus cycles controlled by an external bus master Note that throughout this manual an overbar indicates an active low signal 18 2 Bus and Control Signals Table 18 1 summarizes MCF5307 bus signals described in Chapter17 Signal Descriptions Table 18 1 ColdFire Bus Signal Summary Signal Name Description MCF5307 Master External Master Edge AS Address strobe Falling A 31 0 Address bus Rising BE BWE Byte enable Byte write enable O Falling CS 7 0 Chip selects Falling D 31 0 Data bus VO VO Rising M Chapter 18 Bus Operation 18 1 Bus Characteristics Table 18 1 ColdFire Bus Signal Summary Continued Signal Name Description MCF5307 Master External Master Edge TRQ 7 5 3 1 Interrupt request Rising Output enable Falling R W Read write Rising SIZ
585. y 12 4 3 Byte Count Registers BCRO BCR3 BCRx Figure 12 6 and Figure 12 7 holds the number of bytes yet to be transferred for a given block The offset within the memory map is based on the value of MPARK BCR24BIT BCRz decrements the successful completion of the address transfer of either a write transfer in dual address mode or any transfer in single address mode decrements by 1 2 4 or 16 for byte word longword or line accesses respectively Figure 12 6 shows BCR for BCR24BIT 1 31 24 23 0 Field BCR Reset 0000_0000_0000_0000_0000_0000 R W R W Address MBAR 0x30C 0x34C 0x38C 0x3AC Figure 12 6 Byte Count Registers BCRn BCR24BIT z 1 Figure 12 7 shows BCR for BCR24BIT 0 M woronoLA Chapter 12 DMA Controller Module 12 7 DMA Controller Module Programming Model Bit 15 14 18 12 11 10 9 8 7 6 5 4 3 2 1 0 Field BCR Reset 0000 0000 0000 0000 R W Addr MBAR 0x30C 0x34C 0x38C 0x3AC Figure 12 7 BCRn BCR24BIT 0 DSR DONE shown in Figure 12 9 is set when the block transfer is complete When a transfer sequence is initiated and BCRn BCR is not divisible by 16 4 or 2 when the DMA is configured for line longword or word transfers respectively DSRn CE is set and no transfer occurs See Section 12 4 5 DMA Status Registers DSRO DSR3 12 4 4 DMA Control Registers DCRO DCR3 DCRn Figure 12 8 is used for configuring the
586. zs EDGESEL FN Le i 6 _ TA A 31 0 x Row RAS Column i mU NE E RAS 1 11 o og 1 ACTV NOP READ NOP NOP PALL NOP DACR CASL 2 Figure 20 4 SDRAM Read Cycle with EDGESEL Tied to Buffered BCLKO Figure 20 5 shows an SDRAM write cycle with EDGESEL tied to buffered BCLKO 20 6 MCF5307 User s Manual M woronoLA Input Output AC Timing Specifications 112 4 5 6 22 BCLKO 1 EDGESEL f X D 31 0 3 I n RAS s cs X qp EN NOP WRITE NOP PALL ne DACR CASL 2 Figure 20 5 SDRAM Write Cycle with EDGESEL Tied to Buffered BCLKO Figure 20 6 shows an SDRAM read cycle with EDGESEL tied high M Chapter 20 Electrical Specifications 20 7 Input Output AC Timing Specifications ol lelsl4lslej zlel e 11 12 1 14 15 4 L 60 lt A 31 0 x Row X Columh 3 DRAMW EX I 0 31 0 X F 1 ACTV NOP READ NOP NOP PALL DACR CASL 2 Figure 20 6 SDRAM Read Cycle with EDGESEL Tied High e gt oN Figure 20 7 shows an SDRAM write cycle with E

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MCF5307 ColdFire® Integrated Microprocessor User's Manual