User Manual - Hybrid DSP
Contents
1. CPLD LED3 CPLD LED2 CPLD LED1 CPLD LEDO amaan ERITREA sf Figure 5 CPLD LED locations 3 2 3 JTAG A JTAG connector is available on the FM482 for configuration purposes The JTAG can also be used to debug the FPGA design with the Xilinx Chipscope The JTAG connector is located on side 1 of the PCB see Figure 6 Figure 6 JTAG connector J6 location The JTAG connector pinout is as follows Table 5 JTAG pin assignment FM482 User manual April 2007 www 4dsp com 12 HOS FM482 user manual 3 3 Clock tree The FM482 clock architecture offers an efficient distribution of low jitter clocks In addition to the PCI Express bus the MGT reference clocks of 106 25MHz and 125MHz Epson EG2121CA make it possible to implement several standards over the MGT I Os connected to the optical transceivers Both FPGAs receive a low jitter 125MHz clock A low jitter programmable clock able to generate frequencies from 62 5MHz to 255 5MHz in steps of 0 5MHz is also available This clock management approach ensures maximum flexibility to efficiently implement multi clock domains algorithms and use the memory devices at different frequencies Both clock buffer devices CDM1804 and the frequency synthesizer I1CS8430 61 are controlled by the Virtex 4 device A 16MHz PClrPclx Teel Low jitter 3661 33MHz Frequency DDR A TILL Low jitter TI MGT clocks Virtex 4 p device B O ea device A 106 25MH2. All signals are user defined 3 3V LVTLL LVCMOS Signal ae FPGA Signal Ma 1 Pn4ioo mo mo _ Pndtor 2 3 Paio2 nu m1 Png 103 4 5 Pn4ioa n7_ Nag PM105 6 7 Paio ne Pe Pm 107 8 9 Pn4ios Pio Pu Pmio9g 10 11 Pn4toto po ng Pn41011 12 13 Pn 012 R8 Pa Pn4 1013 14 15 Pm41014 R6 R7 Png 015 16 17 Pn4 1016 N21 ma Pn41017 18 19 Pn4 018 m20 m9 Pn4 1019 20 21 Pn4 1020 P19 m9 Pn4 1021 22 28 Pn41022 N18 N17 Pm 023 24 25 Pn4 1024 P16 N16 Pm 1035 26 27 Pm41026 R18 Pig Pn4 1027 28 29 Pn4 1028 P21 P20 Pn4 1029 30 31 Pm41030 R17 R6 Pn4 1031 32 33 Pn4 1032 19 m5 Pn41033 34 35 Pn4 1034 15 AD11 Pn4 1035 36 37 Pn4 1036 AD10 L4 Pn4 1037 38 39 Pn4 1038 13 AB11 Pn4 1039 40 41 Pn4 1040 AC11 m Pn41041 42 43 Pn4 042 N4 T9 Png tas 44 45 Pm4 1044 78 P5 Pd 1045 46 47 Pm4 046 R5 amo Pm 1047 48 49 Pn4 1048 aB10 P4 Pm 1049 50 51 Pn4io50 R3 wio Pm 1051 52 53 Pn4 1052 y10 Na Pn41053 54 55 Pn4 1054 P3 ue Pn4 1055 56e 57 Pn4 1056 U5 T4 Pm 1057 58 59 Pn4 1058 73 u7 Pn 1059 60 61 Pm41060 V6 u4 Png 1061 62 63 Pn4 1062 V4 Ug Pn4 1063 64 Table 2 Pn4 pin assignment FM482 User manual April 2007 www
3. The Front Panel I O daughter card on side 1 of the PCB is powered via a 7 pin connector of type BKS Samtec Each pin can carry up to 1 5A The power connector s pin assignment is as follows Pin Signal Signal Pin 41 3 3V 33V 2 38 v GND 4 5 2V GND 6 7 12V Table 8 Daughter card power connector pin assignment on PMC side 1 On side 2 of the PCB the daughter card is powered via a 33 pin connector of type BKS Samtec Each pin can carry up to 1 5A The power connector s pin assignment is as follows 1 433V GND 2 3 3 3V GND 4 5 4 3 3V GND 6 7 33V GND 8 9 5V GND 10 41 45v GND 12 43 45V GND 14 45 45V GND 16 17 na GND 18 19 12V GND 20 21 a2 GND 22 23 12V GND 24 25 GND reserved 26 27 reserved reserved 28 29 reserved reserved 30 31 reserved reserved 32 33 GND Table 9 Daughter card power connector pin assignment on PMC side 2 FM482 User manual April 2007 www 4dsp com 16 HOS FM482 user manual 3 6 Front Panel optical transceivers Four 2 5Gb s optical transceivers LTP ST11M are available on the FM482 in the front panel area They are connected to the MGT I Os of the Virtex 4 device A Infiniband protocols as well as Gigabit Ethernet and Fibre channel SFPDP can be implemented over the transc
4. all care has been taken to ensure that power consumption will remain as low as possible for any given algorithm After power up the FM482 typically consumes 2W of power For precise power measurements it is recommended to use the Xilinx power estimation tools for both FPGA A and B The maximum current rating given in the table below is the maximum current that can be drawn from each voltage rail in the case resources are used to their maximum level Device Interface Voltage Maximum current rating DCI and memory reference 0 9V 5A voltage Virtex 4 device A amp B core 1 2V 12A QDR2 DDR2 SDRAM core and 1 8V 10A O banks Virtex 4 devices I O banks connected to the front panel daughter card Virtex 4 device A VO bank 3 3V 2A connected to the PCI bus Flash CPLD front Panel I O daughter card Front Panel IO daughter card 5V 1A Front Panel IO daughter card 12V 0 5A Front Panel IO daughter card 12V 0 5A MGT power supply 1 2V 1 5V 2 5V 1 7A 0 5A 0 01A Virtex 4 device B WO bank 1 8V 2 5 3 3V 1 5A respectively Table 10 Power supply Optionally the FM482 can be used as a stand alone module and is powered via the external power connector FM482 User manual April 2007 www 4dsp com 18 HOS PMC XMC connectors 12V Ld Front Panel I O 12V daughter card T wot rs E 1 5V MGT supplies Low noise 2 regulator Switching 1 regulator Switching 1 regu
5. 2 Nh iC D casera oases essence erent eee sede ecieamioas ematineees eeeeetinceseaetonieeanmanaes 9 3 2 FPGA devices CO MNIG UAT O Meecssnczeesee5s ccezcenunesdetooaeicsSaonansereoadensdenduanspszabagedoietonccect 10 3 2 1 ESARETTE E E E 10 3 2 2 BRED EEG eee eee 10 3 2 3 ITA EET ET E 12 3 3 RO TOO E E EE 13 3 4 Memory resources 1 axndaprestenasaiuenntsdavussenasesanans nee veudtorsaennactaseucustosssesoanmnnsedates 13 3 4 1 ID S RANE sncessocaezescenetovsesencentere concussteestessanboceeeseceneaessacaceecuasseoneeesietenccoss 13 3 4 2 DERES ANSE eee ner een eae ar ec oe ence cee rer 13 3 5 Front Panel IO daughter card race seces cecieataccecnatiactneascecbadutavcnc Gueeternaeasateceraedaetieememaees 14 3 5 1 Virtex 4 device B to I O front Panel daughter Card cccccsseeeceeeeeeeeeeseees 14 3 5 2 Power connection to the front panel I O daughter card 16 3 6 Front Panel optical transceivers ccccecccseecseecceeeceececeeeceeeeceeeceeeeceeecseeseeeeseeees 17 4 POWEP FOCUIFCING INNS a stcercecsvesssecoencssxcessecceesceeccsesdesenGuspscasecsuseeneccussesseciectecestemsseaseecasases 18 4 1 External power connector for stand alone mode cccceceeeeeeeeeeeeeeeeeeeeeneeeeeees 19 PEP e g 1 9 3 F RERENS SENERE cs tceaeg no cetentenauscudesenestenncevesedsenceesctcecscuecsiesseeutesenavduceneetueneeaccaste 20 5 1 TCAD EF AUIS EEN A ER ne 20 5 2 Gone ones I erea E E RA E A 20 53 CONGU CHOn COO errereen E aeea meena FE
6. 4dsp com 8 amp FM482 user manual JOSE V1 3 3 1 2 Virtex 4 device B 3 1 2 1 Virtex 4 device B family and package The Virtex 4 device B is dedicated to Digital Signal Processing applications and can be chosen from the SX or LX family devices Its package is based on Fineline Ball Grid array with 1148 balls In terms of logic and dedicated DSP resources the FPGA B can be chosen from the following types SX55 LX40 LX60 LX80 LX100 and LX160 3 1 2 2 Virtex 4 device B external memory interfaces The Virtex 4 device B interfaces to four 8Mbytes QDR2 SRAM devices with 32 bit data bus Please note that the four QDR2 SRAM devices are only available with the LX80 LX100 and LX160 devices For smaller Virtex 4 FPGAs LX40 LX60 and SX55 only three QDR2 SRAM devices are connected to the FPGA 3 1 2 3 Virtex 4 device B interface to Front Panel daughter card The Virtex 4 device B interfaces to the front panel daughter card on the FM482 via a high speed connector 114 I Os are available from the FPGA to from the daughter card Refer to the Front Panel I O section of this document for more details about the daughter card connector electrical characteristics FM482 User manual April 2007 www 4dsp com 9 HOS FM482 user manual 3 2 FPGA devices configuration 3 2 1 Flash storage The FPGA firmware is stored on board in a flash device The 128Mbit device is partly used to store the configuration for both FPGAs In the default CPLD f
7. amp FM482 user manual JOSE V1 3 FM482 User Manual 4DSP Inc 955 S Virginia Street Suite 214 Reno NV 89502 USA Email support 4dsp com This document is the property of 4DSP Inc and may not be copied nor communicated to a third party without the written permission of 4DSP Inc 4DSP Inc 2007 amp FM482 user manual JOSE V1 3 Revision History Date Revision Version 02 01 07 First release 10 02 23 07 Updated Pn4 pin allocation table 1 1 03 14 07 Updated clock tree diagram 1 2 04 26 07 Corrected typos 1 3 FM482 User manual April 2007 www 4dsp com FM482 user manual V1 3 Table of Contents 1 Acronyms and related documents c cccceeeseeeeseeeeneeeeeseeeeseeeeneeneeeeeeeseeeeneesensesoenees 4 1 1 PAC ORY NG sco cere TEE E suet ance nee end siaataweemesssac te 4 1 2 Related DOCUMEMS ssacciccececesecedeccaeuesncnssatacdtdssnedan haii aeeiiaii ne dele 4 1 3 GENCY al GOS CHOON assesseer REE REE ER ERE EDER REED ERE Er EF E 5 2 a CANNON E E E EDER rr 6 2 1 Requirements and handling instructions cccceeecseeeceeeeeeeeceeeeseeeseeeeseeseeeeneeess 6 2 2 Firmware and software ac chee ctoscietetenctenso acter sigeiaeistestra secs ecievaciad oactteatbans lt idedeaiseslceeieemekereesegneueiaien 6 3 DESO acess sc eet ce sees ett er ine oe ee A A DES ENEDES SES 6 3 1 FE PCV GSS ccc sot e esau aqeuiee sone E A 6 3 1 1 Vie EVISA orara ee ante EDER ee eae aero eee aan rer 6 3 1
8. 3 3V via a large 0 ohms resistor 3 3V is the default if not specified otherwise at the time of order Using the Xilinx DCI termination options to match the signals impedance allows many electrical standards to be supported by this interface All signals are routed as 100 ohm LVDS pairs The VRP and VRN pins on the I O banks connected to the daughter card connector are respectively pulled up and pulled down with 50 ohm resistors in order to ensure optimal performances when using the Xilinx DCI options The VREF pins are connected to 0 9V for DDR2 DCI terminations Please contact 4DSP Inc for more information about the daughter card types available The 120 pin Samtec connector pin assignment is as follows All signals are shown as LVDS pairs in the table but they can be used for any standard that does not breach the electrical rules of the Xilinx I O pad Connector Signal FPGA FPGA Signal Gra 001 FPPO W4 AA23 FPP 2 3 FP_NO Y24 AA24 FPM 4 5 FP_P2 AA25 AA28 FP_P3 6 7 FP N2 Aa26 AA29 FPN3 8 9 FP P4 AB30 AC28 FPP5 10 11 FPN4 AA30 AB28 FPN5 12 13 FPP6 AB22 AD27 FPP7 14 15 FPN6 AB23 AC27 FPN7 16 17 FPP8 Ac29 ac32 FPP9 18 19 FPN8 AC30 AC33 FPN9 20 o 21 FP P10 AD34 AE32 FP P11 22 23 FP_N10 AC34 AD32 FP_N11 24 25 FP P12 AE29 AF31 FP_P13 26 27 FP
9. E 20 0 Dalei annann EEFE E ENE ASEE SEEE EEA 20 T EMO rn EE ANE E EEEE 20 O Waman as EEG Eee 20 9 FMASZ DICU sE E E E E E 21 FM482 User manual April 2007 www 4dsp com 3 amp FM482 user manual JOSE V1 3 1 Acronyms and related documents 1 1 1 2 Acronyms JTAG Join Test Action Group LED Light Emitting Diode PCI Peripheral Component Interconnect PCl e PCI Express PLL Phase Locked Loop SDRAM Synchronous Dynamic Random Access memory SRAM Synchronous Random Access memory Table 1 Glossary Related Documents IEEE Std 1386 1 2001 IEEE Standard Physical and Environmental Layers for PCI Mezzanine Cards PMC ANSI VITA 39 2003 PCI X for PMC and Processor PMC ANSI VITA 20 2001 Conduction Cooled PMC ANSI VITA 42 0 2005 XMC Switched Mezzanine Card Auxiliary Standard IEEE Std 1386 2001 IEEE Standard for a Common Mezzanine Card CMC Family Xilinx Virtex 4 user guide Xilinx PCI X core datasheet Xilinx Virtex 4 Rocket I O guide FM482 User manual April 2007 www 4dsp com 4 HOS FM482 user manual 1 3 General description The FM482 is a high performance PMC XMC dedicated to digital signal processing applications with high bandwidth and complex algorithms requirements The FM482 can interface to a PCl e PCI X and or PCI bus It offers various interfaces fast on board memory resources and one Virtex 4 FPGA It can be utilized for example to acceler
10. N12 AD29 AE31 FP_N13 28 29 FP P14 AE33 AF33 FP P15 30 31 FPLN14 AE34 AF34 FP_N15 32 33 FP P16 AF29 AH19 FP_P17 34 35 FP_N16 AF30 AH18 FP_N17 36 37 Fp_pis acis acso FP_P19 38 39 FP_N18 AG17 AG31 FP_N19 40 Table 6 Front Panel IO daughter card pin assignment Bank A 1 Connected to a global clock pin on the FPGA LVDS output not supported 2 Connected to a regional clock pin on the FPGA LVDS output not supported FM482 User manual April 2007 www 4dsp com 14 FM482 user manual HOS Connector FPGA FPGA Connector pin Differential pin pin Differential pin 41 FP P20 AG32 AJ34 FPP21 42 48 FPN20 AG33 _ AH34 FP_N2t 44 45 FP P22 AH32 AJ30 FPP28 46 47 FP_N22 AH33 AH30 FP N23 48 49 FP P24 AK31 AK33 FPP25 50 51 FP_N24 AK32 AK34 FPN25 52 538 FP P26 AL33 AM31 FPP27 54 55 FPN26 AL34 AL31 FPN27 56 57 FPP28 AM32 AP30 FPP29 58 59 FP_N28 AM33 AN30 FPN29 60 61 FPP30 AM30 AH28 FPP31 62 63 FP_N30 AL30 AH29 FP N31 64 65 FP P32 AK29 AL28 FP_P33 66 67 FP N32 AJ29 AL29 FP N33 68 69 FP P34 AP29 AN28 FP P35 70 71 FP N34 AN29 AM28 FP_N35 72 73 FP_P36 AG27 AG28 FP
11. Pin 41 lasy 33av 2 3 sv SV 4 5 GND GND 6 7 GND GND 8 g lax 12V 10 Table 11 External power connector pin assignment FM482 User manual April 2007 www 4dsp com 19 HOS FM482 user manual 5 Environment 5 1 Temperature Operating temperature e OC to 60 C Commercial e 40 C to 85 C Industrial Storage temperature e 40Cto 120C 5 2 Convection cooling 600LFM minimum 5 3 Conduction cooling The FM482 can optionally be delivered as conduction cooled PMC The FM482 is compliant to ANSI VITA 20 2001 standard for conduction cooled PMC 6 Safety This module presents no hazard to the user 7 EMC This module is designed to operate from within an enclosed host system which is build to provide EMC shielding Operation within the EU EMC guidelines is not guaranteed unless it is installed within an adequate host system This module is protected from damage by fast voltage transients originating from outside the host system which may be introduced through the system 8 Warranty Basic Warranty included 1 Year from Date of Shipment 90 Days from Date of Shipment Extended Warranty optional 2 Years from Date of Shipment 1 Year from Date of Shipment FM482 User manual April 2007 www 4dsp com 20 amp FM482 user manual HOS V1 3 9 FM482 picture Figure 10 FM482 FM482 User manual April 2007 www 4dsp com 21
12. _N36 74 75 3 3V 2 5V 1 8V Vbatt 76 77 3 3V 2 5V 1 8V m 0 9V 78 79 3 3V 2 5V 1 8V 3 3V 2 5V 1 8V 80 81 FPP37 AF28 AJ27 FPP38 82 83 FP_N37___ AE27 _ AH27 FP_N38 84 85 FPP39 AM26 AP27 FP P40 86 87 FP_N39__ AM27 AN27 FPN40 88 89 FP_P41 AP25 AL26 FP P42 90 91 FP_N41 AP26 AK26 FP_N42 92 93 FP P43 aAG25 AF26 FP P44 94 95 FPN43 AG26 AE2Z6 FPN44 _ 96 97 FP P45 AJ17 AN25 FP P46 98 99 FP_N45 AH17 AM25 FP N46 100 101 FPP47 AP24 AK24 FPP48 102 103 FP_N47 AN24 AJ24 FPN48 104 105 FP P49 AG23 AK22 FP P50 106 107 FPN49 AF24 AK23 FPN50 108 109 FP_P51 AL23 AN22 FP P52 110 411 FP N51 AM23 _ AN23 FPN52 112 113 FP P53 AL24 AP21 FP P54 114 115 FP_N53 AL25 AP22 FP_N54 116 117 FP _P55 AE17 AK21 FPP56 118 119 FP_N55 AE16 AL21 FPN56 120 Table 7 Front Panel IO daughter card pin assignment Bank B and C 1 Connected to a global clock pin on the FPGA LVDS output not supported 2 Connected to a regional clock pin on the FPGA LVDS output not supported 3 Vpatt is connected to both Virtex 4 devices Vbatt pin April 2007 FM482 User manual www 4dsp com 15 amp FM482 user manual JOSE V1 3 3 5 2 Power connection to the front panel I O daughter card
13. ate frequency domain algorithms with off the shelf Intellectual Property cores for applications that require the highest level of performances The FM482 is mechanically and electrically compliant to the standard and specifications listed in section 1 2 of this document 4x 2 5Gb s optical Front Panel IO transceivers daughter card i Tet MER SN ray ie ee Sanne QDR2 SRAM QDR2 SRAM FPGA B n XC4VSX55 XC4VLX40 60 XC4VLX80 100 160 Not on 1X40 60 or SX55 Flash 128Mbit LED xd Power supply DC DC converters a ee ee User VO PCI X PC 66 33MHz 64 32 bit PCI Express Figure 1 FM482 block diagram FM482 User manual April 2007 www 4dsp com 5 amp FM482 user manual JOSE V1 3 2 Installation 2 1 Requirements and handling instructions e The FM482 must be installed on a motherboard compliant to the IEEE Std 1386 2001 standard for 3 3V PMC or on a motherboard compliant to the XMC Switched Mezzanine Card Auxiliary Standard e Do not flex the board e Observe SSD precautions when handling the board to prevent electrostatic discharges e Do not install the FM482 while the motherboard is powered up 2 2 Firmware and software Drivers API libraries and a program example working in combination with a pre programmed firmware for both FPGAs are provided The FM482 is delivered with an interface to the Xilinx PCI core in the Virtex 4 device A and an example VHDL design in the Virtex 4 de
14. eivers Lower rate optical transceivers 2 125Gb s and 1 0625Gb s are available in the same form factor Two low jitter clocks 106 25MHz and 125MHz are directly connected to the MGT clock inputs so multi rate applications can be implemented on the FM482 The MGT banks have power supplies independent from the digital supply provided to the FPGAs in order to insure low noise and data integrity The LT1963 device will be used to generate the 1 2V 1 5V and 2 5V necessary for the MGT to operate The power filtering network includes a 220nF decoupling capacitor and ferrite bead MP21608S221A per power pin The signal differential pairs are routed on a specific inner layer with one reference GND plane on each side of the layer stack up Please note that the optical transceivers are not available if the FM482 is Conduction Cooled PMC edge Front Panel Low jitter MGT clocks Virtex 4 1k device B bid PClexprass Front Panel Optical oO Trantever Daughter card k Fell Figure 8 Optical transceivers FM482 User manual April 2007 www 4dsp com 17 amp FM482 user manual JOSE V1 3 4 Power requirements The Power is supplied to the FM482 via the PMC and or XMC connectors Several DC DC converters generate the appropriate voltage rails for the different devices and interfaces present on board The FM482 power consumption depends mainly on the FPGA devices work load By using high efficiency power converters
15. irmware configuration the Virtex 4 devices A and B are directly configured from flash if a valid bitstream is stored in the flash for each FPGA The flash is pre programmed in factory with the default firmware example for both FPGAs 929GL126M 128Mbit Flash bit parallel a confiquration CoolRunner II CPLD Virtex 4 device A XC2C256 CP132 IP swich LED Figure 3 Configuration circuit 3 2 2 CPLD device As shown on Figure 2 a CPLD is present on board to interface between the flash device and the FPGA devices It is of type CoolRunner ll The CPLD is used to program and read the flash The data stored in the flash are transferred from the host motherboard via the PCI bus to the Virtex 4 device A and then to the CPLD that writes the required bit stream to the storage device A 31 25 MHz clock connects to the CPLD and is used to generate the configuration clock sent to the FPGA devices At power up if the CPLD detects that an FPGA configuration bitstream is stored in the flash for both FPGA devices it will start reading programming the devices in SelecMap mode Do NOT reprogram the CPLD without 4DSP approval The CPLD configuration is achieved by loading with a Xilinx download cable a bitstream from a host computer via the JTAG connector The FPGA devices configuration can also be performed using the JTAG FM482 User manual April 2007 www 4dsp com 10 FM482 user manual 3 2 2 1 HOS DIP Switch A
16. lator Switching 0 regulator FM482 user manual SV 8V 2V 9V 12V 5V 3 3V 12V External Power connector Figure 9 Power supply An ADT7411 device is used to monitor the power on the different voltage rails as well as the temperature The ADT7411 data are constantly passed to the Virtex 4 device A Measurements can be accessed from the host computer via the PCI bus A software utility delivered with the board allows the monitoring of the voltage on the 2 5V 1 8V 1 2V and 0 9V rails It also displays the Virtex 4 device B junction temperature 4 1 External power connector for stand alone mode An external power connector J2 is available on side 2 of the PMC next to the PMC connectors It is used to power the board when it is in stand alone mode This is a right angled connector and it will be mounted on board only if the card is ordered in its stand alone version FM482 SA The height and placement of this connector on the PCB breaches the PMC specifications and the module should not be used in an enclosed chassis compliant to PMC specifications if the external power connector is present on board Do not connect an external power source to J2 if the board is powered via the PMC connectors Doing so will result in damaging the board The external power connector is of type Molex 43045 1021 Each circuit can carry a maximum current of 5A The connector pin assignment is as follows Pin Signal Signal
17. s PCI X 64 bit 66MHZ2 133MHz PCI 64 bit 66MHz and PCI 32 bit 33MHz are supported on the FM482 The bus type must be communicated at the time of the order so the right Virtex 4 device A firmware can be loaded into the flash prior to delivery The following performances have been recorded with the FM482 transferring data on the bus gt PCI X 64 bit 133MHz 750Mbytes s sustained gt PCI X 64 bit 66MHz 450Mbytes s sustained gt PCI 32 bit 33MHz 120Mbytes s sustained The PCl express is using the MGT I Os on the Virtex 4 device A Power filtering low jitter clock and special routing are used to achieve the performances required by this standard Please refer to the Front Panel Optical transceivers section of this document for more details 3 6 3 1 1 5 LED Four LEDs are connected to the Virtex 4 device A In the default FPGA firmware the LEDs are driven by the Virtex 4 device B via the Virtex 4 device A Virtex 4 device B interface The LEDs are located on side 2 of the PCB in the front panel area o FPGA LED3 Ss is wet Sets 3 FPGA LEDO Figure 2 FPGA LED locations FM482 User manual April 2007 www 4dsp com 7 amp FM482 user manual JOSE V1 3 3 1 1 6 Pn4 user I O connector The Pn4 connector is wired to the Virtex 4 device A The 32 lower bits are available only if an XC4VFX60 device is mounted on board The 32 higher bits are available only if PCI 32 bit is used and only if specified at the time of order
18. switch J1 is located next to the JTAG programming connector J6 see Figure 4 The switch positions are defined as follows Switch 1 aa era iilii titer weeee Default setting The Virtex 4 device A configuration is loaded from the flash at power up Sw1 OFF ON Sw2 Sw3 Sw4 Virtex 4 device A safety configuration loaded from the flash at power up To be used only if the Virtex 4 device A cannot be configured or does not perform properly with the switch in the OFF position Reserved Reserved Reserved Table 3 Switch description 3 2 2 2 LED and board status Four LEDs connect to the CPLD and give information about the board status LED 0 Flashing FPGA A or B bitstream or user ROM register is currently being written to the flash ON FPGA A not configured OFF FPGA A configured LED 1 Flashing FPGA A or B bitstream or user ROM register is currently being written to the flash ON FPGA B not configured OFF FPGA B configured LED 2 Flashing The Virtex 4 device A has been configured with the safety configuration bitstream programmed in the flash at factory Please write a valid Virtex 4 device A bitstream to the flash ON Flash is busy writing or erasing OFF Flash device is not busy LED 3 ON CRC error Presumably a wrong or corrupted FPGA bitstream FM482 User manual April 2007 www 4dsp com 11 FM482 user manual
19. vice B so users can start performing high bandwidth data transfers over the PCI bus right out of the box For more information about software installation and FPGA firmware please refer the FM482 Get Started Guide 3 Design 3 1 FPGA devices The Virtex 4 FPGA devices interface to the various resources on the FM482 as shown on Figure 1 They also interconnect to each other via 86 general purpose pins and 2 clock pins 3 1 1 Virtex 4 device A 3 1 1 1 Virtex 4 device A family and package The Virtex 4 device A is from the Virtex 4 FX family It can be either an XC4VFX20 or XC4VFX6O0 in a Fineline Ball Grid array with 672 balls FF672 3 1 1 2 Power PC embedded processor Up to two IBM PowerPC RISC processor cores are available in the Virtex 4 device A This core can be used to execute C based algorithms and control the logic resources implemented in the FPGA 3 1 1 3 Virtex 4 device A external memory interfaces The Virtex 4 device A is connected to a 128Mbytes SDRAM bank with a 32 bit data bus width This memory resource can be used by the PowerPC core or can serve as data buffer FM482 User manual April 2007 www 4dsp com 6 HOS FM482 user manual 3 1 1 4 PCI interface The Virtex 4 device A interfaces directly to the PCI bus via the PMC Pn1 Pn2 and Pn3 connectors or to the PCl e bus via the Pn5 An embedded PCI core from Xilinx is used to communicate over the PCI bus with the host system on the motherboard PCl e 4 lane
20. z Kf twec LYPECL LYVCMOS 31 2 Shane synthesizer Front Panel F Virtex 4 CPLD Figure 7 Clock tree 3 4 Memory resources 3 4 1 QDR2 SRAM Four independent QDR2 SRAM devices are connected to the Virtex 4 device B The QDR2 SRAM devices available on the FM482 are 2M words deep 8Mbytes per memory device Please note that only three QDR SRAM devices are available to the user if the XC4VLX40 XC4VLX60 or XC4VSX55 FPGA device is mounted on board 3 4 2 DDR2 SDRAM Two 16 bit DDR2 SDRAM devices of 128MBytes each are connected to Virtex 4 device A The two memories share the same address and control bus and have their own data bus This memory resource can be accessed by the PowerPC processor in the Virtex 4 device A or can be used as a data buffer for custom user logic FM482 User manual April 2007 www 4dsp com 13 amp FM482 user manual JOSE V1 3 3 5 Front Panel IO daughter card 3 5 1 Virtex 4 device B to I O front Panel daughter card only available with daughter card purchase The Virtex 4 device B interfaces to a 120 pin connector placed in the Front panel I O area on both side 1 and side 2 of the PCB It serves as a base for a daughter card and offers I O diversity to the FM482 PMC On side 2 of the PCB the connectors and mounting holes placement complies with the SLB standard except for the 1 5V mounting hole that is not present on this module The FPGA I O banks are powered either by 1 8V 2 5V or
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