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CLC Configuration Tool User's Guide

1. Version 1 0 0 3 Company s customer for use solely and exclusively with products manufactured by the Company liability for the breach of the terms and conditions of this license SPECIAL INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON WHATSOEVER File clc or xor inc Generated by CLC Designer Date 6 6 2012 8 46 AM Device PIC16 L F1508 9 BANKSEL CLC1GLSO movlw H 02 movwf CLC1GLSO movlw H 00 movwf CLC1GLS1 movlw H 00 movwf CLC1GLS2 movlw H 80 movwf CLC1GLS3 movlw H 00 movwf CLC1SELO movlw H 50 movwf CLC1SEL1 movlw H 00 movwf CLC1POL movlw H c1 movwf CLC1CON BANKSEL CLC2GLS0 movlw H 02 movwf CLC2GLSO movlw H 00 movwf CLC2GLS1 movlw H 00 movwf CLC2GLS2 movlw H 80 movwf CLC2GLS3 movlw H 00 movwf CLC2SELO movlw H 50 movwf CLC2SEL1 movlw H 00 movwf CLC2POL movlw H cl movwf CLC2CON O 2011 2012 Microchip Technology Inc DS41597B page 35 CLC Configuration Tool User s Guide B 13 CLC AND INC Software License Agreement The software supplied herewith by Microchip Technology Incorporated the Company is intended and supplied to you the The software is owned by the Company and or its supplier and is protected under applicable copyright laws All rights are reserved Any use in violation of the foregoing restrictions may subject the user to criminal sanctions under applicable laws as well as to civil THIS SOFTWARE IS P
2. A AA DS41597B page 26 O 2011 2012 Microchip Technology Inc The Configurable Logic Cell CLC Designer Tool B4 OR XOR Creates exclusive OR of the input signals The Exclusive OR output is high when one input is high and the other is low is low when inputs are both high or both low FIGURE B 4 OR XOR CONFIGURATION OF CLC2 lola re r gt CLC Designer Version 1 0 0 3 INI Ver 1 0 File Device PIC16 L F1508 9 CLC2 INO RC3 Fosc CLC10UT Rising Interupt Falling Interrupt W Output Enable V CLC Enable CLC2 IN1 RC4 FIGURE B 5 LOGICAL XOR INPUT AND OUTPUT WAVEFORM EXAMPLE a Q Saleae Logic 1 1 15 Connected 8 MHz 2 M Samples 2M Samples YA PE ser Ops 100 us MO us 50 us 60 us 70 us 80 us 90 Optionsy 10 us 20 us 30 us 40 us 50 us 60 us 70 us 80 us 90 us 0 CLCANO Fe Um Measurements gF M 1 CLOIN FR gt 8 MHz 10 M Samples 16 v 2011 2012 Microchip Technology Inc DS41597B page 27 CLC Configuration Tool User s Guide B 5 AND Creates AND of the input signals The AND output is high when all inputs are high is low when any input is low FIGURE B 6 AND CONFIGURATION OF CLC2 r 7 2 CLC Designer Version 1 0 0 3 INI Ver 1 0 i ko xi File E
3. BANKSI CLC2GLSO movlw H 02 movwf CLC2GLS0 movlw H 00 movwf CLC2GLS1 movlw H 00 movwf CLC2GLS2 movlw H 80 movwf CLC2GLS3 movlw H 00 movwf CLC2SELO movlw H 50 movwf CLC2SEL1 movlw H 00 movwf CLC2PO movlw H C1 movwf CLC2CO td a Uses CLC2out banksel OSCCON movlw b 01110010 8MHz clock Does not matter for this demo movwf OSCCON banksel TRISC movlw b 10011000 RC3 amp RC4 as input to CLC2IN RCO as output form CLC2 movwf TRISC banksel ANSELC All digital outputs moviw 0x00 movwf ANSELC return return to main program SEE LR A a ae DS41597B page 24 O 2011 2012 Microchip Technology Inc MICROCHIP CLC CONFIGURATION TOOL USER S GUIDE Appendix B The Configurable Logic Cell CLC Designer Tool B 1 INTRODUCTION Appendix B provides a reference example for each of the tabs AND OR OR XOR AND in the CLC designer tool Screenshots input output waveforms and source code provide a starting point for developing custom logic implementations Examples in Appendix B were developed using the CLC2 block of a PIC16F 1509 microcontroller B 2 BLOCK DIAGRAM In order to provide the input signals that will exercise the CLC block we are using the PIC MCU to drive the INO and IN1 signals with RC3 and RC4 respectively FIGURE B 1 BLOCK DIAGRAM SHOWING PORT SIGNALS FEEDING CLC BLOCK RC3 X
4. MICROCHIP Configurable Logic Cell CLC Configuration Tool User s Guide Note the following details of the code protection feature on Microchip devices Microchip products meet the specification contained in their particular Microchip Data Sheet Microchip believes that its family of products is one of the most secure families of its kind on the market today when used in the intended manner and under normal conditions There are dishonest and possibly illegal methods used to breach the code protection feature All of these methods to our knowledge require using the Microchip products in a manner outside the operating specifications contained in Microchip s Data Sheets Most likely the person doing so is engaged in theft of intellectual property Microchip is willing to work with the customer who is concerned about the integrity of their code Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code Code protection does not mean that we are guaranteeing the product as unbreakable Code protection is constantly evolving We at Microchip are committed to continuously improving the code protection features of our products Attempts to break Microchip s code protection feature may be a violation of the Digital Millennium Copyright Act If such acts allow unauthorized access to your software or other copyrighted work you may have a right to sue for relief under that Act
5. Tel 33 1 69 53 63 20 Fax 33 1 69 30 90 79 Germany Munich Tel 49 89 627 144 0 Fax 49 89 627 144 44 Italy Milan Tel 39 0331 742611 Fax 39 0331 466781 Netherlands Drunen Tel 31 416 690399 Fax 31 416 690340 Spain Madrid Tel 34 91 708 08 90 Fax 34 91 708 08 91 UK Wokingham Tel 44 118 921 5869 Fax 44 118 921 5820 11 29 12 2011 2012 Microchip Technology Inc DS41597B page 43
6. x PIC16F1509 CLC2INO CLC Block CLC2IN1 PIC MCU Port Logic RCO CLC2 RC3 drives CLC2 INO RC4 drives CLC2 IN1 CLC2 OUT is the output of the CLC module 2011 2012 Microchip Technology Inc DS41597B page 25 CLC Configuration Tool User s Guide B 3 AND OR This creates an OR of the two input signals Signals are connected by clicking to the left of the gate note the red circle in Figure B 2 Connections alternate between connected inverted and not connected Also note that gates 2 and 3 have inverted outputs This causes a 1 to be present at the output of the gate and will allow the input signal to pass through the AND gates FIGURE B 2 AND OR CONFIGURATION OF CLC2 ES CLC Designer Version 1 0 0 3 INI Ver 1 0 1 So File Bowes PICI6 P1508 3 z CC Cle v ANDOR ORXOR AND SR D Rop ORD JK Dutch CLC2 INO RC3 CLC2INO CLC1 OUT X f I Rising Interrupt E Falling Interrupt CLC2 IN1 RC4 X R M Output Enable A Y CLC Enable FIGURE B 3 LOGICAL OR INPUT AND OUTPUT WAVEFORM EXAMPLE 7 I SE Optionsv 100 ps 20 us 30 us 40 ps 50 us 60 us 70 us 80 us 90 us s 10 us 20 us 30 us 40 us 50 us 60 us 20 us 80 us 90 us 10 us 20 us 30 us 40 us 50 us 6 0 CLCANO Oat 3 AR a 1 CLON FE EE O o T2 M Ba AAA Q gt 8 MHz 10 M Samples 16 gt
7. 001 101 CLC1IN1 CLC2IN1 CLCxIN 2 010 110 Reserved Reserved CLCxIN 3 011 111 Reserved Reserved CLCXxIN 4 100 000 Fosc Fosc CLCxIN 5 101 001 TMROIF TMROIF CLCxIN 6 110 010 TMR1IF TMRAIF CLCxIN 7 111 011 TMR2 PR2 TMR2 PR2 CLCXxIN 8 100 000 CLC10UT CLC10UT CLCxIN 9 101 001 CLC2OUT CLC2OUT CLCxIN 10 110 010 Reserved Reserved CLCxIN 11 111 011 Reserved Reserved CLCxIN 12 100 000 NCO1OUT LFINTOSC CLCxIN 13 101 001 HFINTOSC ADCFRC CLCxIN 14 110 010 PWM30UT PWM10UT CLCxIN 15 111 011 PWM40UT PWM20UT O 2011 2012 Microchip Technology Inc DS41597B page 13 CLC Configuration Tool User s Guide FIGURE 1 4 SELECTION FOSC AS AN INPUT FOR TWO DIFFERENT GATES Fosc Timer0 OVF Timer1 OVF Timer2 PR2 CLC1 OUT CLC2 OUT Reserved Reserved 1 5 4 Gate Inputs Once the data inputs are selected they can be mapped into each of the four gates The output of each gate will differ according to the logic function selected To select an input into a gate simply hover over the desired X and click once The cursor arrow will have changed to the pointer and a line extending the input into the gate will appear To invert the signal click again where the X was and now a bubble should appear indicating an inversion If clicked once more the bubble and line should disappear and default back to the original unconn
8. 5 1 This is where the device such as the PIC16F 1508 will be selected When a device is selected the program will configure itself automatically to that specific device such as data inputs and number of available CLC outputs 1 5 2 CLC Module This drop down menu will display each CLC module Some devices such as the PIC10F320 will only have one available CLC module in the selected device The x in each CLC register will be replaced by whichever CLC module is used 1 5 3 There are four input selection groups Each group consists of eight selections For devices with only 8 inputs all 8 inputs are available in every group For devices with 16 inputs only 8 of the 16 are available in each group but are distributed in such a way to minimize precluding some input selection combinations No input will appear twice in the same group but will appear as an input in other groups Device Data Inputs As seen in Table 1 2 each drop down item correlates to a logic cell data input group Icxdx Each data input is selectable at least two different times in two or more different groups For example Fosc could be selected as an input in the first and second drop down menus in the CLC tool for a PIC16F150 as shown in Figure 1 4 TABLE 1 2 CLCX DATA INPUT SELECTION FOR THE PIC16F 1507 Data Input Fe oe a e CLC1 CLC2 CLCxIN 0 000 000 CLC1INO CLC2INO CLCxIN 1
9. 792 7277 Technical Support http www microchip com support Web Address www microchip com Atlanta Duluth GA Tel 678 957 9614 Fax 678 957 1455 Boston Westborough MA Tel 774 760 0087 Fax 774 760 0088 Chicago Itasca IL Tel 630 285 0071 Fax 630 285 0075 Cleveland Independence OH Tel 216 447 0464 Fax 216 447 0643 Dallas Addison TX Tel 972 818 7423 Fax 972 818 2924 Detroit Farmington Hills MI Tel 248 538 2250 Fax 248 538 2260 Indianapolis Noblesville IN Tel 317 773 8323 Fax 317 773 5453 Los Angeles Mission Viejo CA Tel 949 462 9523 Fax 949 462 9608 Santa Clara Santa Clara CA Tel 408 961 6444 Fax 408 961 6445 Toronto Mississauga Ontario Canada Tel 905 673 0699 Fax 905 673 6509 ASIA PACIFIC Asia Pacific Office Suites 3707 14 37th Floor Tower 6 The Gateway Harbour City Kowloon Hong Kong Tel 852 2401 1200 Fax 852 2401 3431 Australia Sydney Tel 61 2 9868 6733 Fax 61 2 9868 6755 China Beijing Tel 86 10 8569 7000 Fax 86 10 8528 2104 China Chengdu Tel 86 28 8665 5511 Fax 86 28 8665 7889 China Chongqing Tel 86 23 8980 9588 Fax 86 23 8980 9500 China Hangzhou Tel 86 571 2819 3187 Fax 86 571 2819 3189 China Hong Kong SAR Tel 852 2943 5100 Fax 852 2401 3431 China Nanjing Tel 86 25 8473 2460 Fax 86 25 8473 2470 China Qingdao Tel 86 532 8502 7355 Fax 86 532 8502 7205 China Shanghai Tel 86 21 5407 5533
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11. Samples fee M um D us 0 us 10 us 20 us 30 us 40 us 50 us 60 us 70 us 80 us 90 us de 10 us 20 us 30 us 40 us 50 us 60 us 70 us 80 us 90 us I y _ gt 0 CLC2ANO PE UM Me el Fr E 1 CLOIN MA 12 yze 2 CLC2 IA i 4 Q gt 8 MHz 10 MSamples 16 v O 2011 2012 Microchip Technology Inc DS41597B page 33 CLC Configuration Tool User s Guide B 11 CLC AND OR INC Software License Agreement The software supplied herewith by Microchip Technology Incorporated the Company is intended and supplied to you the Company s customer for use solely and exclusively with products manufactured by the Company The software is owned by the Company and or its supplier and is protected under applicable copyright laws All rights are reserved Any use in violation of the foregoing restrictions may subject the user to criminal sanctions under applicable laws as well as to civil liability for the breach of the terms and conditions of this license THIS SOFTWARE IS PROVIDED IN AN AS IS CONDITION NO WARRANTIES WHETHER EXPRESS IMPLIED OR STATU TORY INCLUDING BUT NOT LIMITED TO IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICU LAR PURPOSE APPLY TO THIS SOFTWARE THE COMPANY SHALL NOT IN ANY CIRCUMSTANCES BE LIABLE FOR SPECIAL INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON WHATSOEVER File clc and or inc Generated by CLC Designer
12. Version 1 0 0 3 Date 6 7 2012 8 09 AM Device PIC16 L F1508 9 BANKSEL CLC1GLSO movlw H 02 movwf CLC1GLSO movlw H 00 movwf CLC1GLS1 movlw H 00 movwf CLC1GLS2 movlw H 80 movwf CLC1GLS3 movlw H 00 movwf CLC1SELO movlw H 50 movwf CLC1SEL1 movlw HOOD movwf CLCIPOL movlw H C1 movwf CLCICON BANKSEL CLC2GLS0 movlw H 02 movwf CLC2GLSO movlw H 00 movwf CLC2GLS1 movlw H 00 movwf CLC2GLS2 movlw H 80 movwf CLC2GLS3 movlw H 00 movwf CLC2SELO movlw H 50 movwf CLC2SEL1 movlw H 06 movwf CLC2POL movlw H CO movwf CLC2CON DS41597B page 34 O 2011 2012 Microchip Technology Inc The Configurable Logic Cell CLC Designer Tool B 12 CLC OR XOR INC Software License Agreement The software supplied herewith by Microchip Technology Incorporated the Company is intended and supplied to you the The software is owned by the Company and or its supplier and is protected under applicable copyright laws All rights are reserved Any use in violation of the foregoing restrictions may subject the user to criminal sanctions under applicable laws as well as to civil THIS SOFTWARE IS PROVIDED IN AN AS IS CONDITION NO WARRANTIES WHETHER EXPRESS IMPLIED OR STATU TORY INCLUDING BUT NOT LIMITED TO IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICU LAR PURPOSE APPLY TO THIS SOFTWARE THE COMPANY SHALL NOT IN ANY CIRCUMSTANCES BE LIABLE FOR
13. rC EF 1508 9 y SR DFop ORD JK Ditch CLC2 INO RC3 m Fosc y CLC1OUT E Rising Interrupt Falling Interrupt CLC2 IN1 RC4 b F Output Enable Y CLC Enable FIGURE B 7 LOGICAL AND INPUT AND OUTPUT WAVEFORM EXAMPLE Saleae Logic 1 1 15 Connected 8 MHz 2 M Samples s e 115 jam 0 100 20 us 30 us 40 us 50 us 60 us 70 us 80 ys 90 us 10 ps 20 us 30 us 40 us 50 us 60 us 70 ps 80 us 90 us ce 10 ps 20 ps 30 us 40 us 50 us 60 y 0 CLCANO FE UM Measurements gt 8 MHz 10 M Samples 16 ES DS41597B page 28 2011 2012 Microchip Technology Inc The Configurable Logic Cell CLC Designer Tool B 6 S R The S R Latch output is high when the S input is high and stays high when the S input goes low is low when the R input is high and stays low when the R input goes low is low when both S and R inputs are high FIGURE B 8 S R CONFIGURATION OF CLC2 E gt CLC Designer Version 1 0 0 3 INI Ver 1 Sox File Device PIC16 L F1508 9 y CIC CL D Lich CLC2 INO RC3 CLC1 OUT y Rising Interrupt Falling Interrupt V Output Enable v CLC Enable CLC2 IN1 RC4 X L C FIGURE B 9 S R LATCH INPUT AND OUTPUT WAVEFORM EXAMPLE A ogic 1 1 15 Connected 8 MHz 2 M Samples ri Ops 100 ps 200 ps 50 ys 20 us 80 us 90 ps 5 10 us 20 us 30
14. same folder as the CLCDesigner ini file To run the program double click on the execut able and the screen in Figure 1 1 should be presented FIGURE 1 1 CLC GUI ON INITIAL START UP De CLC Designer Versor 1000 1 dis le Figure 1 2 shows the error when the INI file is not placed in the same directory as the executable FIGURE 1 2 ERROR MESSAGE Initialization Fault Ia CLCDesigner INI file fault DS41597B page 10 O 2011 2012 Microchip Technology Inc CLC Configuration Tool Overview 1 5 DESIGN METHODOLOGY STEPS 1 Identify the input and output signals that will be required and make sure they are not conflicting with other required peripherals on the chip It should be noted that some CLC modules have alternate output pins Also some peripheral signals can be routed to alternate pins through an unused CLC module For example A PWM signal could be routed through a CLC block and the output could be presented on an alternate pin I O configuration as such is handled as part of the system initialization and therefore is not included in the CLC Designer 2 To design custom logic for the CLC module it is suggested that the designer first approach the design by creating timing diagrams and then sketch out the gate logic for their design 3 Once that has been completed the designer should break the circuit into sepa rate elements ex flip flop XOR gate etc each
15. the U S A Silicon Storage Technology is a registered trademark of Microchip Technology Inc in other countries Analog for the Digital Age Application Maestro BodyCom chipK IT chipKIT logo CodeGuard dsPICDEM dsPICDEM net dsPICworks dsSPEAK ECAN ECONOMONITOR FanSense HI TIDE In Circuit Serial Programming ICSP Mindi MiWi MPASM MPF MPLAB Certified logo MPLIB MPLINK mTouch Omniscient Code Generation PICC PICC 18 PICDEM PICDEM net PICKkit PICtail REAL ICE rfLAB Select Mode SQI Serial Quad I O Total Endurance TSHARC UniWinDriver WiperLock ZENA and Z Scale are trademarks of Microchip Technology Incorporated in the U S A and other countries SQTP is a service mark of Microchip Technology Incorporated in the U S A GestIC and ULPP are registered trademarks of Microchip Technology Germany ll GmbH amp Co amp KG a subsidiary of Microchip Technology Inc in other countries All other trademarks mentioned herein are property of their respective companies 2011 2012 Microchip Technology Incorporated Printed in the U S A All Rights Reserved LI Printed on recycled paper ISBN 9781620768044 Microchip received ISO TS 16949 2009 certification for its worldwide headquarters design and wafer fabrication facilities in Chandler and Tempe Arizona Gresham Oregon and design centers in California and India The Company s quality system processes and procedures are for its PIC MCUs and dsPIC
16. us 40 ps 50 us 60 us 10 us 80 us 9 us 5 10 us 20 us 30 us 40 us 50 us 60 us 70 us 80 us 90 us 4 y _ __ gt _ _ 0 CLC2INO Fe M eque Im 1 CLOIN MA 12 i E Q gt 8MHz 10 M Samples 16 v A ET O 2011 2012 Microchip Technology Inc DS41597B page 29 CLC Configuration Tool User s Guide B 7 D FLOP In this example CLC2 INO is being used as the clock and CLC2 IN1 is the data signal to the D flip flop The D Flip Flop output goes to the level at D on the rising edge of the clock input FIGURE B 10 D FLOP CONFIGURATION OF CLC2 rye CLC Designer Version 1 0 0 3 INI Ver 1 Sox File Device PIC16 L F1508 9 cic CIC CLC2 INO RC3 I Fosc CLC1 OUT Rising Interrupt Falling Interupt CLC2 IN1 RC4 Y Output Enable Y CLC Enable i o gt Q output changes on the rising edge of the clock Figure B 11 FIGURE B 11 D FLOP INPUT AND OUTPUT WAVEFORM EXAMPLE hi ogic 1 1 15 Connected 8 MHz 2 M Samples amp LE je 2M Samples Blame O See o Options 0 us 100 us ous 40 us 50us 60us 70us 80us 90us Ous 20us 30u0s 40 us 50us 60us 70us 8Qps s90us lOus 20us 0us 40us 50us 60 us 70 us WAA 0 CLC2INO Pen Um y ncy A Q gt 8 MHz 10 M Samples 16 v A DS41597B page 30 O 2011
17. 1 2012 Microchip Technology Inc DS41597B page 37 CLC Configuration Tool User s Guide B 15 CLC D FLOP INC Software License Agreement The software supplied herewith by Microchip Technology Incorporated the Company is intended and supplied to you the The software is owned by the Company and or its supplier and is protected under applicable copyright laws All rights are reserved Any use in violation of the foregoing restrictions may subject the user to criminal sanctions under applicable laws as well as to civil THIS SOFTWARE IS PROVIDED IN AN AS IS CONDITION NO WARRANTIES WHETHER EXPRESS IMPLIED OR STATU TORY INCLUDING BUT NOT LIMITED TO IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICU LAR PURPOSE APPLY TO THIS SOFTWARE THE COMPANY SHALL NOT IN ANY CIRCUMSTANCES BE LIABLE FOR Version 1 0 0 3 Company s customer for use solely and exclusively with products manufactured by the Company liability for the breach of the terms and conditions of this license SPECIAL INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON WHATSOEVER File clc d flop inc Generated by CLC Designer Date 6 6 2012 10 01 AM Device PIC16 L F1508 9 BANKSEL CLC1GLSO movlw H 02 movwf CLC1GLSO movlw H 00 movwf CLC1GLS1 movlw H 00 movwf CLC1GLS2 movlw H 80 movwf CLC1GLS3 movlw H 00 movwf CLC1SELO movlw a movwf CLC1SEL1 movlw H 00 movwf CLC1POL mo
18. 2012 Microchip Technology Inc The Configurable Logic Cell CLC Designer Tool B 8 OR D The OR D Flip Flop output goes high on the rising edge of the clock input when either input to the OR gate is high goes low on the rising edge of the clock when both inputs to the OR gate are low FIGURE B 12 OR D CONFIGURATION OF CLC2 Z gt CLC Designer Version 1 0 0 3 INI Ver 1 ASEO File Be C1 1508 9 id a ANDOR ORXOR ano SR D op ORD uk Ditch Sop ad Show CLC2 INO RC3 CLC1 OUT A Rising Interrupt Falling Interrupt CLC2 IN1 RC4 X 9 Output Enable Y CLC Enable O FIGURE B 13 OR D INPUT AND OUTPUT WAVEFORM EXAMPLE gic 1 1 15 Connected 8 MHz 2 M Samples 2M Samples r fem NET Optonsv 0 ys 100 us 30 ps 40 us 50 us 60 us 70 us 80 ps 90 us A 10 us 20 us 30 ps 40 us 50 us 60 us 70 us 80 us 90 us rn 0 CLC2INO AU 10 us 20 us 20 us 40 us 50 us 60 us 70 us Y Measurements O 2011 2012 Microchip Technology Inc DS41597B page 31 CLC Configuration Tool User s Guide B 9 J K The J K output remains unchanged when J and K are both low toggles on the rising click when J and K are both high goes high on the rising clock when the J is high and K is low goes low on the rising clock when J is low and K is high FIGURE B 14 J K CONFIGURA
19. DSCs KEELOQ code hopping devices Serial EEPROMs microperipherals nonvolatile memory and analog products In addition Microchip s quality system for the design and manufacture of development systems is ISO 9001 2000 certified DS41597B page 2 2011 2012 Microchip Technology Inc CLC CONFIGURATION TOOL MICROCHIP USER S GUIDE Table of Contents Chapter 1 CLC Configuration Tool Overview 154 INMODUCUON Lee nn laos Bele AN asa nile 7 A OO 7 1 3 CLC Configuration Tool Purpose coommmocinoncccnnncnonnnnancnccnnnn rana nnncn cnn 7 1 4 Installing the Program atte A ne Can de tt 8 1 5 Design Methodology Steps 2e naine dan need 9 UN IA ws hea tee ae Aa KA ott AA 11 1AA EC Modul od E a ii Mami 11 1 5 3 Data Input tua o id MA WAA MAMAA 11 1 5 4 Gate INPUTS 22522 ei e a ete ne eae e WA a E eas 12 1 5 5 Gate OutpUIS siii lat rd id E diia 12 1 5 6 Digital Logic BIOCKS oooooocccinnonaccccocccnncnncnnncnonannnnconncnnnnnnnnnnnnnnnn niwa 13 1 5 7 Output Control ainia At 14 LO SAVING LOGGING ui Ata 14 Chapter 2 Manchester Line Code Example 2 1 Introduction enea aid 17 2 2 MONOS ii A Resto Re Se ee ABA 17 2 3 Example Problem ss 17 2 4 Proposed Solution sise 17 2 5 Extended Solution sas rar a ada ibid 19 Appendix A Appendix B Manchester Encoding Program ASSY The Configurable Logic Cell CLC Designer Tool Bl Introduction ia 23 BZ Block Diagramme ada
20. Icxg4 LCxMODE lt 2 0 gt 011 S R Latch Q H Iexq 1 Input D Flip Flop with S and R Icxg4 S Icxg2 D Q Iexq Icxg1 gt R Icxg3 LCxMODE lt 2 0 gt 100 Icxg4 D Q lcxq Icxg2 Icxg1 cxg D R Icxg3 LCxMODE lt 2 0 gt 101 2 Input D Flip Flop with R J K Flip Flop with R Icxg2 J Q H lexq Icxg1 lcxg4 3 K xg R Icxg3 LCxMODE lt 2 0 gt 110 1 Input Transparent Latch with S andR cxg4 S cxg2 D Q LE cxg1 R cxg3 LCxMODE lt 2 0 gt 111 Icxq 2011 2012 Microchip Technology Inc DS41597B page 15 CLC Configuration Tool User s Guide 1 5 7 Output Control The output from the logic block is fed to the last stage of the CLC the inversion gate To invert the output click on the buffer output pin once for a bubble to appear From here the output can be routed to other peripherals an output pin or back to the CLC input An interrupt can be enabled upon a rising and or falling edge from the CLC output Figure 1 7 shows the configuration for enabling the module enabling the output to the CLCx output pin and producing an interrupt upon a rising edge being detected The CLC output will also be inverted FIGURE 1 7 CLC OUTPUT OPTIONS v Rising Interrupt Falling Interrupt Y Output Enable v CLC Enable 1 6 SAVING LOADING The program provi
21. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates It is your responsibility to ensure that your application meets with your specifications MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED WRITTEN OR ORAL STATUTORY OR OTHERWISE RELATED TO THE INFORMATION INCLUDING BUT NOT LIMITED TO ITS CONDITION QUALITY PERFORMANCE MERCHANTABILITY OR FITNESS FOR PURPOSE Microchip disclaims all liability arising from this information and its use Use of Microchip devices in life support and or safety applications is entirely at the buyer s risk and the buyer agrees to defend indemnify and hold harmless Microchip from any and all damages claims suits or expenses resulting from such use No licenses are conveyed implicitly or otherwise under any Microchip intellectual property rights QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV ISO TS 16949 Trademarks The Microchip name and logo the Microchip logo dsPIC FlashFlex KEELOQ KEELOQ logo MPLAB PIC PlCmicro PICSTART PIC logo rfPIC SST SST Logo SuperFlash and UNI O are registered trademarks of Microchip Technology Incorporated in the U S A and other countries FilterLab Hampshire HI TECH C Linear Active Thermistor MTP SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in
22. NESS FOR A PARTICU LAR PURPOSE APPLY TO THIS SOFTWARE THE COMPANY SHALL NOT IN ANY CIRCUMSTANCES BE LIABLE FOR SPECIAL INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON WHATSOEVER Filer cle y k ine Generated by CLC Designer Version 1 0 0 3 Date 6 6 2012 11 16 AM Device PIC16 L F1508 9 BANKSEL CLC1GLSO movlw Aga movwf CLC1GLSO movlw H 00 movwf CLC1GLS1 movlw H 00 movwf CLC1GLS2 movlw H 80 movwf CLC1GLS3 movlw H 00 movwf CLC1SELO movlw HS 0 movwf CLC1SEL1 movlw H 00 movwf CLCIPOL movlw sae ia movwf CLCICON BANKSEL CLC2GLS0 movlw H 08 movwf CLC2GLSO movlw H 02 movwf CLC2GLS1 movlw H 00 movwf CLC2GLS2 movlw H 80 movwf CLC2GLS3 movlw H 00 movwf CLC2SELO movlw H 50 movwf CLC2SEL1 movlw H 00 movwf CLC2POL movlw H C6 movwf CLC2CON DS41597B page 40 O 2011 2012 Microchip Technology Inc The Configurable Logic Cell CLC Designer Tool B 18 CLC D LTCH INC Software License Agreement The software supplied herewith by Microchip Technology Incorporated the Company is intended and supplied to you the The software is owned by the Company and or its supplier and is protected under applicable copyright laws All rights are reserved Any use in violation of the foregoing restrictions may subject the user to criminal sanctions under applicable laws as well as to civil THIS SOFTWARE IS PROVIDED IN AN AS IS CONDITION
23. NO WARRANTIES WHETHER EXPRESS IMPLIED OR STATU TORY INCLUDING BUT NOT LIMITED TO IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICU LAR PURPOSE APPLY TO THIS SOFTWARE THE COMPANY SHALL NOT IN ANY CIRCUMSTANCES BE LIABLE FOR Version 1 0 0 3 Company s customer for use solely and exclusively with products manufactured by the Company liability for the breach of the terms and conditions of this license SPECIAL INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON WHATSOEVER File clc d ltch inc Generated by CLC Designer Date 8 1 2012 8 54 AM Device PIC16 L F1508 9 BANKSEL CLC1GLSO movlw H 02 movwf CLC1GLSO movlw H 00 movwf CLC1GLS1 movlw H 00 movwf CLC1GLS2 movlw H 80 movwf CLC1GLS3 movlw H 00 movwf CLC1SELO movlw H 50 movwf CLC1SEL1 movlw H 00 movwf CLC1POL movlw HET movwf CLCICON BANKSEL CLC2GLS0 movlw H 02 movwf CLC2GLSO movlw H 80 movwf CLC2GLS1 movlw H 00 movwf CLC2GLS2 movlw H 00 movwf CLC2GLS3 movlw H 00 movwf CLC2SELO movlw H 50 movwf CLC2SEL1 movlw H 00 movwf CLC2POL movlw 4 Cc7 movwf CLC2CON O 2011 2012 Microchip Technology Inc DS41597B page 41 CLC Configuration Tool User s Guide NOTES DS41597B page 42 2011 2012 Microchip Technology Inc MICROCHIP Worldwide Sales and Service AMERICAS Corporate Office 2355 West Chandler Blvd Chandler AZ 85224 6199 Tel 480 792 7200 Fax 480
24. ROVIDED IN AN AS IS CONDITION NO WARRANTIES WHETHER EXPRESS IMPLIED OR STATU TORY INCLUDING BUT NOT LIMITED TO IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICU LAR PURPOSE APPLY TO THIS SOFTWARE THE COMPANY SHALL NOT IN ANY CIRCUMSTANCES BE LIABLE FOR Version 1 0 0 3 Company s customer for use solely and exclusively with products manufactured by the Company liability for the breach of the terms and conditions of this license SPECIAL INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON WHATSOEVER File clc and inc Generated by CLC Designer Date 6 6 2012 8 49 AM Device PIC16 1 F1508 9 BANKSEL CLCIGLSO movlw H 02 movwf CLC1GLSO movlw H 00 movwf CLC1GLS1 movlw H 00 movwf CLC1GLS2 movlw H 80 movwf CLC1GLS3 movlw H 00 movwf CLC1SELO movlw H 50 movwf CLC1SEL1 movlw H 00 movwf CLC1POL movlw Act movwf CLC1CO BANKSEL CLC2GLS0 movlw AO movwf CLC2GLSO movlw H 00 movwf CLC2GLS1 movlw H 00 movwf CLC2GLS2 movlw H 80 movwf CLC2GLS3 movlw H 00 movwf CLC2SELO movlw H 50 movwf CLC2SEL1 movlw H 06 movwf CLC2POL movlw OA movwf CLC2CON DS41597B page 36 O 2011 2012 Microchip Technology Inc The Configurable Logic Cell CLC Designer Tool B 14 CLC S R INC Software License Agreement The software supplied herewith by Microchip Technology Incorporated the Company is intended and supplied to you the The
25. TION OF CLC2 CLC Designer Version 1 0 0 3 INI Ver 1 Se x File Device PICTE L F1508 9 s bac is ANDOR ORXOR AND SR Do ORD JK Ditch f CLC2 INO RC3 M Fosc y CLC1 OUT f q E Rising Interrupt f E Falling Interupt CLC2 INT RC4 y 7 Output Enable A Y CLC Enable A SS gt FIGURE B 15 J K INPUT AND OUTPUT WAVEFORM EXAMPLE gic 1 1 15 Connected 8 MHz 2 M Samples ag a Y ry DIRA Lies 2M sampes gt fem NET Options 10 us 20 us 30 us 40 us 50 us 60 ys 70 us 80 us RE 0 CLC2INO mi 4 Measurements Emma T2 4 Q gt 8 MHz 10 M Samples 16 v AA 3 AA DS41597B page 32 2011 2012 Microchip Technology Inc The Configurable Logic Cell CLC Designer Tool B 10 DLTCH The D Latch output follows the D input when the LE input is high holds the output to the level D when LE goes low FIGURE B 16 D LTCH CONFIGURATION OF CLC2 Be CLC Designer Version 1 0 0 3 INI Ver 1 o E EX File 2e tnt x Eco is ANDOR ORXOR ano SR DRop ORD uk Ditch Com and Show CLC2 INO RC3 CLC1 OUT A Rising Interrupt Falling Interrupt Y Output Enable Y CLC Enable CLC2 INT RCA m L FIGURE B 17 D LTCH INPUT AND OUTPUT WAVEFORM EXAMPLE gic 1 1 15 Connected 8 MHz 2 M Samples 2M
26. age 20 O 2011 2012 Microchip Technology Inc Manchester Line Code Example 2 5 EXTENDED SOLUTION If the user wants to generate a Manchester encoded message from the PIC device directly this is easily achieved through the MSSP Simply select the PIC16F1508 and replace the data clock inputs from the external device with SPI SCK and SPI SDO FIGURE 2 4 CLC DESIGN FOR THE ENCODE HANDLING USING THE MSSP AS INPUTS Be CLC Designer Version LOOO gt File Devis PC 6156495 Yu 4 gt T Copy and Show Device Clay 15089 ac acs ANDOR ROR AND SR 0 Fue ORO JK D un Y Note See Appendix A Manchester Encoding Program ASSY for assembly code solution XA O 2011 2012 Microchip Technology Inc DS41597B page 21 CLC Configuration Tool User s Guide NOTES DS41597B page 22 2011 2012 Microchip Technology Inc CLC CONFIGURATION TOOL MICROCHIP USER S GUIDE Appendix A Manchester Encoding Program ASSY Software License Agreement The software supplied herewith by Microchip Technology Incorporated the Company is intended and supplied to you the Company s customer for use solely and exclusively with products manufactured by the Company The software is owned by the Company and or its supplier and is protected under applicable copyright laws All rights are reserved Any use in violation of the foregoing restrictions may subject the user to criminal
27. ation so all signals should be validated in the actual hardware Another de bugging validation technique is to set up each CLC module independently monitoring inputs and outputs to verify functionality before multiple CLC modules are tied together 2011 2012 Microchip Technology Inc DS41597B page 11 CLC Configuration Tool User s Guide The CLC Configuration Tool presents the following options in initial start up as seen in Figure 1 3 FIGURE 1 3 CLC INPUT OUTPUT OPTIONS E cuc Designer Version 1 0 0 0 T aT ao Fil a e A arr Ji E ANOOR TORMOR AND SR Jomploro yx Jou Cox ani Shon ix 3 il The CLC Configuration Tool provides a friendly alternative to manually configuring the 8 CLC registers for each module in software Table 1 1 correlates each block in the above figure with its matching register in the device s data sheet TABLE 1 1 CORRELATION BETWEEN GUI REPRESENTATION AND THEIR EFFECTS ON DATA SHEET CLC REGISTERS CLC GUI Representation CLC Registers 1 Device All 2 CLC module All 3 Data inputs CLCxSEL1 2 4 Gate inputs CLCxGLS1 4 5 Gate output polarity CLCxPOL 6 Digital logic blocks CLCxCON 7 CLC output control CLCxCON The following sections explains each block s functionality and purpose labeled in Figure 1 3 DS41597B page 12 2011 2012 Microchip Technology Inc CLC Configuration Tool Overview 1
28. by clicking the Copy and Show in the current module and then Paste in another CLC module This will copy all of the content from one CLC to another The clipboard contents cannot be pasted to any window outside of the CLC tool The Clear button will reset all fields to their default state DS41597B page 18 2011 2012 Microchip Technology Inc CLC CONFIGURATION TOOL MICROCHIP USER S GUIDE Chapter 2 Manchester Line Code Example 2 1 INTRODUCTION This example will use the information in Chapter 1 CLC Configuration Tool Overview in solving a typical problem that can now be achieved with ease using the Configurable Logic Cell Configuration Tool It is recommended that the reader first understand how to use the program before continuing 2 2 HIGHLIGHTS This chapter discusses Example Problem Proposed Solution e Extended Solution 2 3 EXAMPLE PROBLEM You want to encode a bit stream of a typical non return to zero NRZ line code from a certain device to a slimmer more versatile Manchester line code A Manchester line code has advantages over the typical NRZ code in that Manchester encoding combines the clock and data into one data stream It has no DC component and is self clocking A diagram of a potential setup is shown in Figure 2 1 FIGURE 2 1 NRZ LINE CODE ENCODED TO A MANCHESTER CODE NRZ Line Code Manchester Line Code CLOCK CLOCK DATA gt DEVICE 2 4 PROPOSED SOLUTION Usi
29. des convenient methods in saving or loading the design When the design is concluded and ready to be implemented in software click the File pull down menu in the top left corner of the dialog box as shown in Figure 1 8 FIGURE 1 8 LOCATION OF LOADING AND SAVING CODE IN THE PROGRAM D CLC Designer Version 1 0 0 0 File Save ASSY code Save C code ied CLC CLC1 Load code pi y OA Then click file gt Save ASSY code or Save C code depending on the desired output language The code for all configured CLCs of the selected device will be included in the output file The resultant file will have an inc extension Figure 1 7 shows example output code for the setup as seen in Figure 1 6 with the inclusion of the AND OR logic block and the rest having default settings The device used in the example is a PIC16F1507 with module CLC1 DS41597B page 16 O 2011 2012 Microchip Technology Inc CLC Configuration Tool Overview EXAMPLE 1 1 EXAMPLE C AND ASSEMBLY GENERATED CODE CLC Designer Version 1 0 0 0 1 PM nog RENE LE EEE EE Both pieces of code produce the same affect The assembly is longer due to the nature of the language The code can now be easily included as a library file or pasted into an existing program It is important that the comment section is left intact because the CLC tool uses the comments specifically the device row to correctly repopulate the fields To load previo
30. dialog Underlined italic text with A menu path File gt Save right angle bracket Bold characters A dialog button Click OK A tab Click the Power tab N Rnnnn A number in verilog format 4 b0010 2 hF1 where N is the total number of digits R is the radix and n is a digit Text in angle brackets lt gt A key on the keyboard Press lt Enter gt lt F1 gt Courier New font Plain Courier New Sample source code define START Filenames autoexec bat File paths e mecl8 h Keywords _asm endasm static Command line options Opa Opa Bit values Ojo 2 Constants OxFF A Italic Courier New A variable argument file o where file can be any valid filename Square brackets Optional arguments mcc18 options file options Curly brackets and pipe Choice of mutually exclusive errorlevel 011 character arguments an OR selection Ellipses Replaces repeated text var_name var_name Represents code supplied by void main void user DS41597B page 6 2011 2012 Microchip Technology Inc Preface THE MICROCHIP WEB SITE Microchip provides online support via our web site at www microchip com This web site is used as a means to make files and information easily available to customers Accessible by using your favorite Internet browser the web site contains the following information Product Support Data sheets and errata application notes and sample p
31. ected state 1 5 5 Gate Outputs Each of the gate outputs can be inverted To do so simply click once on the output of an individual gate for a bubble to appear The output is now inverted To undo this click the bubble again for it to disappear It is important to note that any gate with no inputs selected will have its output default to the Off state logic zero If a constant logic one is desired then invert the default logic zero by clicking the output for the inverting bubble Figure 1 5 shows the setup of having Fosc and an inverted Timer0 OVF as inputs to Gate 2 with its output inverted FIGURE 1 5 GATE INPUT OUTPUT WITH INVERSION Fosc Timer0 OVF DS41597B page 14 2011 2012 Microchip Technology Inc CLC Configuration Tool Overview 1 5 6 Digital Logic Blocks There are eight available logic functions selected by the tabs of the CLC tool The logic blocks cannot be configured other than what is shown Only one logic function can be used at a single time for each CLC module Figure 1 6 displays all of the available functions FIGURE 1 6 GATE INPUT OUTPUT WITH INVERSION Icxg4 AND OR Icxg1 Icxg2 lexq Icxg3 LCxMODE lt 2 0 gt 000 Icxg1 Icxg2 Icxg3 Icxg4 OR XOR Dy D LCxMODE lt 2 0 gt 001 Icxg1 Icxg4 4 Input AND Icxg2 lexq Icxg3 LCxMODE lt 2 0 gt 010 Icxg1 S Icxg2 Icxg3 R
32. element being implementable as a single CLC module For an example of how this is done reference Figure 4 of application note AN1451 Glitch Free Design Using the Configurable Logic Cel DS01451 available on the Microchip web site 4 Once the circuit has been broken into logic elements use the CLCx DATA INPUT SELECTION table in the data sheet device specific to check for signals that can feed between the CLC blocks and PIC MCU internal signals and place these labels on the logic design Pay particular attention to the MUX selection codes in the DxS columns of the table Most MUX selections are mutually exclusive which limits your signal selection choices Some inputs are duplicated such as PWM2 on the 1509 Both CLC2 and CLC3 have access to these making those two input MUX s not exclusive Doing this search beforehand avoids the unpleasant task of hunting for the CLC Input combination that works since the CLC Designer is organized so that invalid selections are not possible 5 After it is understood how each CLC module will be configured use the CLC Designer tool GUI to implement the complete design and to generate the code either C or assembly 6 After the CLC code has been included in the project the inputs outputs should be thoroughly tested to ensure that everything is working properly and that interrupts will not be falsely generated etc The CLC Designer tool does not support timing or signal simul
33. er of resources available on that particular chip Further direct design of the logic and interconnect keeps the designer visually aware of the signal and logic limitations of the CLC peripheral 1 2 HIGHLIGHTS This chapter discusses e CLC Configuration Tool Purpose e Installing the Program e Design Methodology Steps e Saving Loading 1 3 CLC CONFIGURATION TOOL PURPOSE The CLC consists of multiple combination and sequential circuits that can have their functionality pre programmed or programmed dynamically This provides greater flexi bility and potential in embedded designs since the CLC module can operate outside the limitations of software execution and supports a vast amount of output designs The configuration tool s purpose is to streamline the setup process of the CLC module by simulating the functionality of the registers in a graphical user interface GUI The end result of using the tool will be a generated resource file written in either C or assembly which can be dropped into an existing project to be included in a program The created file is custom generated depending on the user inputs and preferences such as programming language 2011 2012 Microchip Technology Inc DS41597B page 9 CLC Configuration Tool User s Guide 1 4 INSTALLING THE PROGRAM The most recent version of the software can be installed from Microchip s web site at http www microchip com Simply place the CLCDesignerTool exe in the
34. he MPLAB IDE online help Select the Help menu and then Topics to open a list of available online help files INTRODUCTION This chapter contains general information that will be useful to know before using the Configurable Logic Cell CLC Configuration Tool Items discussed in this chapter include e Conventions Used in this Guide e The Microchip Web Site e Customer Support e Document Revision History DOCUMENT LAYOUT This document describes how to use the Configurable Logic Cell CLC Configuration Tool as a development to emulate and debug firmware on a target board as well as how to program devices The document is organized as follows Chapter 1 CLC Configuration Tool Overview Chapter 2 Manchester Line Code Example Appendix A Manchester Encoding Program ASSY Appendix B The Configurable Logic Cell CLC Designer Tool 2011 2012 Microchip Technology Inc DS41597B page 5 CLC Configuration Tool User s Guide CONVENTIONS USED IN THIS GUIDE This manual uses the following documentation conventions DOCUMENTATION CONVENTIONS Description Represents Examples Arial font Italic characters Referenced books MPLAB IDE User s Guide Emphasized text is the only compiler Initial caps A window the Output window A dialog the Settings dialog A menu selection select Enable Programmer Quotes A field name in a window or Save project before build
35. is 23 B S AND OR ER aaa 24 B4ORXOR ET Re Mn is 25 BANDE nn eanga Sea A eine tenta tu ete tnt tien te dE date ee ae doute tent tee G an 26 BIOS Re Rs PIA AE MAA MEI dan nd eal AMI WA AME WA detre ibn Te 27 BiG DROPS oil tratar laa 28 BS ORD aaa 29 O NN 30 NA ON 31 B 11 cl and OriINC osna anna ads 32 Bi 12 CIC OF XOPMIAG sitiada iia dable ia ds 33 BAS CCAA Taca 34 BAA MESEN at kai 35 B T15 cle d OP INC citas 36 ekoo enel Ee NNA cocida tdi id ubh an 37 O 2011 2012 Microchip Technology Inc DS41597B page 3 CLC Configuration Tool User s Guide BACARES a coi 38 B18 cled MIRE AAA WAWA AAA S dha wi dr MOL GS nent 39 DS41597B page 4 2011 2012 Microchip Technology Inc CLC CONFIGURATION TOOL MICROCHIP USER S GUIDE Preface NOTICE TO CUSTOMERS All documentation becomes dated and this manual is no exception Microchip tools and documentation are constantly evolving to meet customer needs so some actual dialogs and or tool descriptions may differ from those in this document Please refer to our web site www microchip com to obtain the latest documentation available Documents are identified with a DS number This number is located on the bottom of each page in front of the page number The numbering convention for the DS number is DSXXXXXA where XXXXX is the document number and A is the revision level of the document For the most up to date information on development tools see t
36. ng only one CLC module on a PIC device would accomplish this task There would be no limitation to the clock speed since the CLC is not controlled by software This allows the CPU to focus on the main program without dealing with the encoding process This also saves the designer additional costs by not having to include more external hardware to perform the same task The encoding process simply requires an XOR gate with the data and clock inputs For this design a PIC16F1507 is used with its CLC2 module 2011 2012 Microchip Technology Inc DS41597B page 19 CLC Configuration Tool User s Guide The data and clock are mapped to CLC2s input on RC3 and RC4 respectively It is vital that their respective TRIS bits are configured as inputs Enable the CLC output and the module itself as well as clear the TRIS bit for the CLC output pin Figure 2 2 shows the CLC design FIGURE 2 2 CLC DESIGN FOR THE ENCODE HANDLING Be CAC Deng Verse 10 When finished include a short description in the comment box and save the design in either C or Assembly format See Appendix A Manchester Encoding Program ASSY for the source code in Assembly Figure 2 3 shows a screenshot of the output of the CLC assuming an input of OxE4 from the device FIGURE 2 3 MANCHESTER LINE ENCODING FROM AN NRZ SOURCE USING THE CLC Note Green CLC output 1 Red data 2 White clock 3 DS41597B p
37. onfiguration Tool Overview 1 1 INTRODUCTION The intention of this user s guide is to assist the reader in becoming acquainted with the Configurable Logic Cell CLC Configuration Tool It will explain how to setup the tool and configure it with an applicable example of creating a Manchester encoder This document will help the reader become familiar with the purpose and functionality ofthe CLC module and be able to use the CLC Configuration Tool with ease In addition to the Manchester encoder additional appendices have been added which provide examples for each type of configurable logic Screenshots and corresponding source code examples can be found in Appendix B The Configurable Logic Cell CLC Designer Tool The CLC is very useful for simple switching and logic operations but admittedly the CLC module is more limited in its functionality and interconnect than a PAL Program mable Array Logic The CLC module is not intended as a replacement for a PAL but offers value in the reduction of external glue logic faster event response and custom interfacing For designers that are familiar with PAL design and synthesis timing tools associated with such technology use of the CLC module entails a design methodol ogy similar to that of introductory logic courses The CLC Designer tool allows edits to one module at a time Because the number of CLC modules per device varies this technique limits the designer to the numb
38. rograms design resources user s guides and hardware support documents latest software releases and archived software General Technical Support Frequently Asked Questions FAQs technical support requests online discussion groups Microchip consultant program member listing Business of Microchip Product selector and ordering guides latest Microchip press releases listing of seminars and events listings of Microchip sales offices distributors and factory representatives CUSTOMER SUPPORT Users of Microchip products can receive assistance through several channels Distributor or Representative e Local Sales Office e Field Application Engineer FAE e Technical Support Customers should contact their distributor representative or field application engineer FAE for support Local sales offices are also available to help customers Technical support is available through the web site at http www microchip com support DOCUMENT REVISION HISTORY Revision A August 2011 e Initial Release of this Document Revision B December 2012 e Updated the design methodology Section 1 5 Design Methodology Steps Added Appendix B The Configurable Logic Cell CLC Designer Tool AA ET 2011 2012 Microchip Technology Inc DS41597B page 7 CLC Configuration Tool User s Guide NOTES DS41597B page 8 2011 2012 Microchip Technology Inc CLC CONFIGURATION TOOL MICROCHIP USER S GUIDE Chapter 1 CLC C
39. sanctions under applicable laws as well as to civil liability for the breach of the terms and conditions of this license THIS SOFTWARE IS PROVIDED IN AN AS IS CONDITION NO WARRANTIES WHETHER EXPRESS IMPLIED OR STATU TORY INCLUDING BUT NOT LIMITED TO IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICU LAR PURPOSE APPLY TO THIS SOFTWARE THE COMPANY SHALL NOT IN ANY CIRCUMSTANCES BE LIABLE FOR SPECIAL INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON WHATSOEVER include p16f1507 inc __CONFIG CONFIGI FOSC INTOSC amp WDTE OFF amp PWRTE OFF _CLKOUTEN_ OFF _ CONFIG CONFIG2 LVP OFF amp STVREN ON Stack over under flow will cause a reset errorlevel 302 suppress bank selection not zero warning ORG 0x00 main call main init init CLC and configure PIC inputs outputs goto main loop main waiting loop main loop goto main loop sit here forever main init File clc inc Generated by CLC Designer Version 1 0 0 0 Date 7 13 2011 12 44 PM Device PIC16 L F1507 2011 2012 Microchip Technology Inc DS41597B page 23 CLC Configuration Tool User s Guide BANKSEL CLCIGLSO movlw H 00 movwf CLCIGLSO movlw H 00 movwf CLC1GLS1 movlw H 00 movwf CLCIGLS2 movlw H 00 movwf CLC1GLS3 movlw H 00 movwf CLCISELO movlw H 00 movwf CLCISELI movlw H 00 movwf CLC1PO movlw H 00 movwf CLC1CO
40. software is owned by the Company and or its supplier and is protected under applicable copyright laws All rights are reserved Any use in violation of the foregoing restrictions may subject the user to criminal sanctions under applicable laws as well as to civil THIS SOFTWARE IS PROVIDED IN AN AS IS CONDITION NO WARRANTIES WHETHER EXPRESS IMPLIED OR STATU TORY INCLUDING BUT NOT LIMITED TO IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICU LAR PURPOSE APPLY TO THIS SOFTWARE THE COMPANY SHALL NOT IN ANY CIRCUMSTANCES BE LIABLE FOR Version 1 0 0 3 Company s customer for use solely and exclusively with products manufactured by the Company liability for the breach of the terms and conditions of this license SPECIAL INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON WHATSOEVER File clc s r inc Generated by CLC Designer Date 6 6 2012 8 51 AM Device PIC16 1 F1508 9 BANKSEL CLC1GLSO movlw H 02 movwf CLC1GLSO movlw H 00 movwf CLC1GLS1 movlw H 00 movwf CLC1GLS2 movlw H 80 movwf CLC1GLS3 movlw H 00 movwf CLC1SELO movlw H 50 movwf CLC1SEL1 movlw H 00 movwf CLC1POL movlw HCI movwf CLC1CON BANKSEL CLC2GLS0 movlw H 02 movwf CLC2GLSO movlw H 00 movwf CLC2GLS1 movlw H 00 movwf CLC2GLS2 movlw H 80 movwf CLC2GLS3 movlw H 00 movwf CLC2SELO movlw H 50 movwf CLC2SEL1 movlw H 00 movwf CLC2POL movlw H 3 movwf CLC2CON O 201
41. ted by CLC Designer Date 6 6 2012 10 15 AM Device PIC16 L F1508 9 BANKSEL CLCIGLSO movlw H 02 movwf CLC1GLSO movlw H 00 movwf CLC1GLS1 movlw H 00 movwf CLC1GLS2 movlw H 80 movwf CLC1GLS3 movlw H 00 movwf CLC1SELO movlw H 50 movwf CLC1SEL1 movlw H 00 movwf CLCIPOL movlw H C1 movwf CLC1CO BANKSEL CLC2GLS0 movlw H 80 movwf CLC2GLSO movlw H 02 movwf CLC2GLS1 movlw H 00 movwf CLC2GLS2 movlw H 00 movwf CLC2GLS3 movlw H 00 movwf CLC2SELO movlw geo movwf CLC2SEL1 movlw H 00 movwf CLC2POL movlw Arco movwf CLC2CON O 2011 2012 Microchip Technology Inc DS41597B page 39 CLC Configuration Tool User s Guide B 17 CLC J K INC Software License Agreement The software supplied herewith by Microchip Technology Incorporated the Company is intended and supplied to you the Company s customer for use solely and exclusively with products manufactured by the Company The software is owned by the Company and or its supplier and is protected under applicable copyright laws All rights are reserved Any use in violation of the foregoing restrictions may subject the user to criminal sanctions under applicable laws as well as to civil liability for the breach of the terms and conditions of this license THIS SOFTWARE IS PROVIDED IN AN AS IS CONDITION NO WARRANTIES WHETHER EXPRESS IMPLIED OR STATU TORY INCLUDING BUT NOT LIMITED TO IMPLIED WARRANTIES OF MERCHANTABILITY AND FIT
42. usly saved code from the CLC tool click file gt load code If imported successfully the tool will have populated the GUI with the appropriate values corre sponding to the registers in the loaded code If the message is received as seen in Figure 1 9 the device ID in the comments was deleted and must be put back into place FIGURE 1 9 ERROR MESSAGE IF DEVICE ID IS MISSING IN THE COMMENTS OF LOADED CODE Code Load Error jes No valid device found I Comments can also be saved and loaded within the output file To do so simply fill out the comments input text area as seen in Figure 1 10 and when the project is ready to be saved the comments will also be included in the output file 2011 2012 Microchip Technology Inc DS41597B page 17 CLC Configuration Tool User s Guide FIGURE 1 10 COMMENT TEXT AREA Comments Here can explain the purpose behind the design and how works This is a good practice and Paste eliminates confusion when sharing code or looking back as a reference This comment fieldbox wil be cleared when the Clear button to the right is pressed The button Copy and Show is used to get a quick view of the register values for the present configuration When pressed the boxes below the button will be filled with the settings that correspond to the design If multiple CLCs share similar configurations one CLC module can be designed and then pasted into another
43. vlw ACL movwf CLC1CON BANKSEL CLC2GLS0 movlw H 80 movwf CLC2GLSO movlw H 02 movwf CLC2GLS1 movlw H 00 movwf CLC2GLS2 movlw H 00 movwf CLC2GLS3 movlw H 00 movwf CLC2SELO movlw H 50 movwf CLC2SEL1 movlw H 00 movwf CLC2POL movlw H C4 movwf CLC2CON DS41597B page 38 O 2011 2012 Microchip Technology Inc The Configurable Logic Cell CLC Designer Tool B 16 CLC OR D INC Software License Agreement The software supplied herewith by Microchip Technology Incorporated the Company is intended and supplied to you the The software is owned by the Company and or its supplier and is protected under applicable copyright laws All rights are reserved Any use in violation of the foregoing restrictions may subject the user to criminal sanctions under applicable laws as well as to civil THIS SOFTWARE IS PROVIDED IN AN AS IS CONDITION NO WARRANTIES WHETHER EXPRESS IMPLIED OR STATU TORY INCLUDING BUT NOT LIMITED TO IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICU LAR PURPOSE APPLY TO THIS SOFTWARE THE COMPANY SHALL NOT IN ANY CIRCUMSTANCES BE LIABLE FOR Version 1 0 0 3 Company s customer for use solely and exclusively with products manufactured by the Company liability for the breach of the terms and conditions of this license SPECIAL INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON WHATSOEVER File clc or d inc Genera

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