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User guide for the Master Processor, Virtex-7

1. 41 Figure 16 Power architecture of the MP7 XE board s see a aaa aaa aaa aaa aaa aaa ennemis 43 Figure 17 Front panel layout of the MP7 Yellow regions indicate uTCA infrastructure zones red regions contains LEDs etc the purple region contains the micro USB connector and microSDHC card connector whilst the orange region indicates the approx 37mm wide zone available for general 54 purpose I O connections Screw mount MTP adapters are required to take up any slack in the ribbon cables manufacturing tolerances Board layout as of 08 02 2012 eesasa aaa aaa aaa aaa naaaanaiiana 44 Figure 18 The front panel design provided with a standard MP7 card asasae saa anna nana aaa ssczaaaaa 44 Figure 19 Prototype laser etched front panel uuau aaa a aaa aaa aaa aa aaa aaa ara aa nennen enne nns 44 Figure 20 Two photographs of the first prototype Imperial MP7 processor card The optical ribbons used are samples with an additional prizm connector that is not required in the final design The Virtex 7 FPGA is located under the blue heat lt Sink ccoooccccnoncccncconccanononannnccnnnnnncnnnannnconnn nn nccnnrnnnccnnn ono 45 Figure 21 Two photographs of the Imperial MP7 R1 processor card The Virtex 7 FPGA is located under the custom designed black heat sink esses eene nnne nnn nnn nennen na 46 List of Tables Table 1 Differential connections of the
2. The clocking architecture of the MP7 XE has been modified to rationalize the design and to provide more flexibility and significantly higher performance The shortcomings of the MP7 RO and MP7 R1 are use limit here in the most perfectionist way possible The MP7 RO and MP7 R1 can run the links at any speed up to in excess of 10Gbps synchronous or asynchronous It works 39 e There are two cross point switches and a fan out buffer between the SI5326 clock synthesizer and the MGTs each component contributing to the additive jitter e Only one clock is available to each MGT quad e The clock traces are run between power planes rather than between ground planes e The clocking logic is powered directly from the general purpose regulators On the MP7 XE two independent SI5326 clock synthesizers are each fanned out through their own Silicon Labs Si53314 1 to 6 Low Jitter Universal Buffer 21 minimizing additive jitter Furthermore each group of three MGT quads receives two independent clocks allowing mixed clocking modes Finally all clock traces have been routed purely between ground planes and all clocking logic has been driven by dedicated high precision LDO regulators with the option for additional ferrites to ensure the cleanest possible clocking environment The clocking architecture for the MP7 XE can be seen in Figure 14 210 219 Programmable Oscillator Top front Top back i A 153314 5153314
3. Bottom front External 15326 inputs 15326 FPGA Fabric Oscillator SY89540U DS91M125 Figure 14 Clocking architecture of the MP7 XE 40 Power The MP7 uses a similar power architecture to the Mini T5 Figure 15 RT9040 Bench top operation HUTCA crate 0 9V operation RT9040 1v5 8A AAA gt 1v8 8A FPGA I O Clocking LTM4628 3V3 BA 2v5 8A LTC3529 12v LTM4628 X 1v0Q 8A LTM4606 LTM4606 LTM4606 5V FPGA Core MIC5319 MIC5319 Upper GTX GTH 1v0 96A LTM4606 3 1v2 6A Lower GTX GTH Figure 15 Power architecture of the MP7 RO board For the MP7 R1 the LTM4628 providing 1v0 is replaced by an LTM4620 and the LTM4606s providing 1v0 are replaced by LTM4601s The main power supplies on the MP7 RO are Linear Technologies LTM4628 uModule Buck Regulators 22 each providing two independent supplies at 8A or one supply at 16A On the MP7 R1 and MP7 XE the 1V core supply is replaced with a Linear Technologies LTM4620 uModule Buck Regulator 24 which is footprint compatible with the LTM4628 used on the MP7 RO but capable of providing two independent supplies at 13A or one supply at 26A On the MP7 RO power for the MGT banks on the Virtex 7 are provided by Linear Technologies LTM4606 Ultralow EMI regulators 25 as used on the Mini T with dedicated supplies for each of the two banks The primary swi
4. 18Mbit CY7C2163KV18 1M x 18bit e 36Mbit CY7C2263KV18 2M x 18 bit e 72Mbit CY7C25632KV18 4M x 18 bit e 144Mbit CY7C2663KV18 8M x 18 bit Although the BGA package of the 18 36 and 72Mbit parts are physically smaller than the 144Mbit part the ball pitch and electrical connections are identical 38 Clocking The clocking architecture of the MP7 RO and MP7 R1 cards is based on that of the Mini T5 with minor changes to accommodate the difference between the Virtex 5 and the Virtex 7 The MP7 has LVDS clock inputs from AMC card edge connections TCLKA FCLKA and TCLKC Unlike the Mini T5 FCLKA is available for use as a PCle clock as well as for distribution of the LHC machine clock from an AMC13 card located in the redundant slot of a standard dual star UTCA crate Any of the AMC clocks may be passed through a Silicon Labs SI5326 20 jitter attenuator which can also act in a standalone frequency synthesis mode The MP7 also accepts a clock input through the front panel on a pair of SMP connectors 22 The clocking architecture for the MP7 RO and MP7 R1 can be Top front seen in Figure 13 SY89540U SY89540U SY89833AL SY89833AL SY89833AL SY89833AL External inputs Oscillator Oscillator 15326 DS91M125 SY89540U Figure 13 Clocking architecture of the MP7 RO and MP7 R1 On the MP7 RO and MP7 R1 there are several shortcomings in the clocking architecture which limit the performance of the board
5. Jas WTSI INFO Reset done INFO Configuring clock 40 external INFO Configuring Xpoint INFO Comiignziiag S559526 INFO Using OEC clou 3 0 mo7 5315926 MP7 815326 20130606 40 1MHz CKIN1 to 160 4MHz CKOUT1 NoIncDec Regs Txt INFO Measuring clk40 frequency Give me a second INFO Clock 40 frequency 39 999720 Mhz INFO Conmicgn a nom EEC INFO Resetting algos INFO Measured f40 39 999720 Mhz INFO BCO reg decl INFO CO tmeeinnel 98 0 INFO BCOMEO CK cael INFO IBC ier g 0 INFO Status OOOO ECO sues clecid laca 509 lies 1 Odo 23 Link configuration and alignment in loopback mode The MP7 links have 2 operation modes standard and loopback In loopback mode for each link the output data stream is rerouted to the input after the link serialization stage The input data must be aligned when entering the algorithm block The MP7 core firmware provides a mechanism to automatically align the incoming data from all channels An example on how to configure and align the MP7 links is in the mp7 test mgtconfig py script mp7 test configlinks py MET IESU J00p 929 5E The command line syntax slightly differs from mp7 test reset py The script first argument is the name of the board to connect to as specified in the connection file tests etc uhal connections test xml by default The script includes two stages link configuration and input link alignment Both need to be completed
6. Technologies QSFP Pluggable Parallel Fiber Optics Module 18 September 2009 http www avagotech com docs AV02 1839EN Reflex Photonics Inc InterBOARD 40 Gbps SNAP 12 Parallel Fiber Optic Transmitter and Receiver Board Edge Modules December 2010 http reflexphotonics com PDFs SN 970 004 00 Rev 3 6 InterBoard Board Edge Data Sheet pdf Avago Technologies AFBR 775BxxxZ AFBR 785BxxxZ Twelve Channel Transmitter and Receiver Pluggable Parallel Fiber Optics Modules 07 August 2009 http www avagotech com docs AV02 2179EN Xilinx Inc DS180 7 Series FPGAs Overview 13 September 2011 http www xilinx com support documentation data sheets ds180 7Series Overview pdf Park Advanced Circuitry Materials Corp Nelco N4000 13 EP SI Rev 4 11 2011 http www parkelectro com parkelectro images n4000 13ep pdf Xilinx Inc Virtex7 Product Table http www xilinx com publications prod mktg Virtex7 Product Table pdf Avago Technologies MiniPOD Twelve Channel Transmitter Twelve Channel Receiver High Density Pluggable Parallel Fiber Optics Modules Product Brief AV02 2842EN 2011 FCI connect MEG ARRAY CONNECTOR SYSTEM http portal fciconnect com Comergent fci documentation 950554 007 meg array pdf Corning Cable Systems LLC EVO 996 EN Non Peelable Fiber Optic Ribbon 12 Fibers November 2009 US Conec Ltd MTP brand connectors 2011 http www usconec com pages products connect adapter connect
7. addresses in the format IP 0 IP S3 MAC O MAC 5 FLAGS 27 Flags is a bitmask The only bit that is currently used is 0x80 If this is returned the network parameters have been modified but not written to the EEPROM Power cycling IPbus to MMC interface Hardware overview The board layout of the top and bottom faces of the MP7 RO and MP7 R1 cards can be seen in Figure 5 29 ENU ER EE z jJ AIC CHRYSE on 905 spe la E Ua a ae ae T E gt ia Faden i l Oy if illl A e i VERE A H X ll 4 RE MM MM 2277 14 RO 00000 ESTARAS Do d icd a Top face 30 TA o b Bottom face projected through board Figure 5 Annotated layout of the MP7 RO and MP7 R1 cards The MP7 XE layout is similar except that many of the clocking components are relocated to the top face of the card 31 Hardware full specification PCB Whilst the Mini T5 was built on an FR4 PCB the MP7 RO and MP7 R1 are built on a Nelco N4000 13 EP SI substrate 7 because of the latter s superior high frequency characteristics A 16 layer stack up is used as shown in Figure 6 Description Thickness Thickness thickness er impedance 1 Type IA Soldermask 0 020 3 200 SolderMask 1 KA Hy Foil 0 012 0 035 nz Foil 4000 1351 1080 0 075 0 075 3 300 PREPREG 2 0 018 0 0
8. also has the ability to record and log events as well as set alarms depending on what thresholds are set in the SDR Setting the IP and Mac addresses To configure the board addresses first set the Mac address by running ipmitool with the command ipmitool aeolemessl P Ww H Q F x92 so 7 e GOGRESSSUNEEEWAIM Mec address where address3 is the position of the board in the crate according to the uTCA specification 37 Addr 0x70 S 2 e g the address of slot AMCO8 is 0x80 The Mac address is input using hexadecimal numerals separated with a space The 0x82 address in the command above is the IPMB 0 address of the carrier manager and this should not be changed The IP address should then be set using ipmitool fedoressi P Y B Q m x92 so 7 e eooress3 raw I address where the IP address is again input using hexadecimal numerals separated by a space The settings should then be saved by writing to the EEPROM to ensure that the addresses are not reset to default when the board is power cycled This is done with the command ipmitool H 192 168 0 41 P B 0 T 0x82 b 7 t 0x86 raw 0x30 0x01 OxFE OxEF The data bytes at the end of this command are a magic word to prevent accidental EEPROM writes To display the current network settings of the board use the command ipmitool H 192 168 0 41 P B 0 T 0x82 b 7 t 0x86 raw 0x30 0x04 which returns the IP and Mac
9. board Adapted from 8 RR 33 Figure 8 Avago MiniPOD optics with unruggedized left and ruggedized right optical ribbons 34 Figure 9 An example of Avago MiniPODs in use showing how unruggedized optical ribbons can be threaded through sequential devices suas see eau aa aa aaa aaa aaa aaa eene n tenia nn nsns 34 Figure 10 Samtec SS4 ST4 ultra fine pitch high speed connectors A single such connector provides 30 differential pairs to from the FPGA 3v3 2v5 and 1v8 supplies and dedicated I2C lines to the A TR KARE 36 Figure 11 Samtec Edge Rate connector and cable assembly one proposed solution for front panel VOOnthe MP7 ais 36 Figure 12 Connections of the JTAG network on the MP7 Two JTAG source the Switched JTAG header and the AMC connector can be connected to any of four JTAG targets with the configuration of the chain controlled by the DIP switches The CPLD is itself programmed by a dedicated JTAG header labelled CPLD TAG x aaa a za kB A Cohn tee rait ree tete dA ene eec tes ARA Each 38 Figure 13 Clocking architecture of the MP7 RO and MP7 R1 sssesee aa aa aa aaa aa aa ennemis 39 Figure 14 Clocking architecture of the MP7 XE uuaaa aaa aaa aa aaa ener enne nennen enti i ranis 40 Figure 15 Power architecture of the MP7 RO board For the MP7 R1 the LTM4628 providing 1v0 is replaced by an LTM4620 and the LTM4606s providing 1v0 are replaced by LTM46015
10. for the configuration to be considered successful The loopback option enables the loopback mode When in loopback mode a self generated pattern from the Tx buffers is used to align the Rx inputs After alignment completion all the channels are checked for CRC errors and alignment errors If required the board can be reset before configuring the links using reset option MIP JUS access GSUXCCOSS Uu INFO Iu NESI built INFO Rx buffer disabled INFO Tx buffer configured for pattern generation INFO Configuring Quads 0 INFO Done 0 INFO Clearing counters INFO Alignment INFO Status c0000018 INFO Checking Quads for errors INFO Clock 40 is locked INFO Alignment Ok INFO CRGO SENE Capturing input and output data stream A basic introduction of the MP7 buffer system is provided here For a more comprehensive description please refer to the Core firmware section on page 11 src mode ipBus PPE mode ipBus e Patterns from algorithms block Figure 3 Link buffers and generators For each link the incoming data can be routed to a buffer where to be capture Alternatively the same buffer can operate in playback mode the pattern loaded via IPbus is played back every orbit into the algorithm block Eventually a generator is included as well that produces a hardcoded pattern every orbit The same structure is replicated on the output line aft
11. http www silabs com pages DownloadDoc aspx FILEURL Support Documents TechnicalDocs Si5326 pdf amp src DocumentationWebPart Silicon Labs Inc Si53314 1 6 Low Jitter Universal Buffer Level Translator With 2 1 Input Mux And Individual OE 1 25 GHz October 2012 http www silabs com Support 20Documents TechnicalDocs Si53314 pdf Samtec Inc SMP EM 50 Ohm SMP RF Plug Edge Mount 29 October 2010 http www samtec com documents webfiles codf SMP PX P XX ST EM3 MKT pdf Linear Technology Corp LTM4628 Dual 8A or Single 16A DC DC uModule Regulator July 2011 http cds linear com docs Datasheet 4628fb pdf Linear Technology Corp LTM4620 Dual 13A or Single 26A DC DC uModule Regulator October 2013 http cds linear com docs Datasheet 4620fa pdf Linear Technology Corp LTM4606 Ultralow EMI 28VIN 6A DC DC uModule Regulator March 2011 http cds linear com docs Datasheet 4606fb pdf Linear Technology Corp LTM4601 LTM4601 1 12A uModule Regulators with PLL Output Tracking and Margining March 2012 http cds linear com docs en datasheet 4601fc pdf Micrel Inc MIC5319 500mA uCap Ultra Low Dropout High PSRR LDO Regulator May 2010 http www micrel com PDF MIC5319 pdf You may need to manually copy this link into your internet browser 52 28 29 30 31 32 33 34 35 36 37 Richtek Technology Corp RT9040 DDR Termination Regulator July 2011 http tw richtek com do
12. optics limiting the flexibility of the interfaces For these two reasons the Mini T5 design was evolved into the MP7 board a board base on the Xilinx Virtex 7 FPGA 6 and using a single optical form factor An additional advantage of using the 7 series FPGAs is the significant increase in serial I O bandwidth To mitigate risk the MP7 design began with the Mini T5 design and features changed only as necessary The MP7 board has been tested extensively using standalone tests MP7 MP7 tests and with the MP7 being driven by other hardware Three versions of the board exist e The MP7 RO e The MP7 R1 e The MP7 XE All three versions of the board are fully usable although the MP7 RO and MP7 R1 must only be used in a Vadatech VT 892 crate since certain components are located too close to the backplane connector such that they may be damaged upon insertion into other crates The MP7 XE was designed to provide higher performance clocking for 13Gbps operation but rather than produce both an MP7 R2 fixing the backplane component problem and MP7 XE it was decided that all future support for the MP7 would be for the MP7 XE card Memorandum of understanding This section represents a contract of responsibility which the user implicitly accepts when they use an MP7 card whether purchased borrowed or otherwise The following lists the firmware package that will be supplied with the MP7 card The firmware will be available in the CERN SVN Trigge
13. 0 1 470 Total Block RAM Kbits 31 680 37 080 42 480 52 920 Clocking CMTs 1 MMCM 1 PLL 12 14 20 20 ARIE Maximum Single Ended I O 600 700 600 1 000 Maximum Differential LO Pairs 288 336 288 480 DSP48E1 Slices 2 160 2 800 2 880 3 600 Gen2 PCI Express Interface Blocks 4 Gen3 PCI Express Interface Blocks 2 2 parm Agile Mixed Signal AMS XADC 1 1 1 1 Himm Configuration AES HMAC Blocks 1 1 1 1 GTX 12 5Gb s Transceivers 56 GTH 13 1Gb s Transceivers 48 80 80 GTZ 28 05Gb s Transceivers Commercial 41 2 1 2 TE PZ Speed Grades Extended 2L 3 A 3 2L 3 2L 3 Industrial 4 2 42 EZ TEE Configuration Configuration Memory Mbits 131 5 1547 2192 2192 Package Area Available User VO 3 3V SelectiO Pins 1 8V SelectlO Pins GTX GTH Transceivers Flip chip fine pitch BGA 1 0 mm ball spacing FFG1927 45 x 45 mm 0 600 0 48 0 600 56 0 0 600 0 80 0 600 0 80 Figure 7 Comparison of the Xilinx Virtex 7 series FPGAs which can be used on the MP7 board Adapted from 8 The engineering silicon for the Virtex 7 series is the XC7VX485T part with 56 GTX links The MP7 board has however been designed from the outset to accept the XC7VX690T part with 80 GTH links The high speed serial links are divided as e 1link Gigabit Ethernet Backplane e 1link Data Acquisition Pathway Backplane e 1link SATA SAS Backplane e 1link PCI express SRIO Backplane e 4 links Extended FAT PIPEs Bac
14. 0x000001 bx 0xd3e cmd 7d 10 V 1 L1A 0 orb 0x000001 bx 0xd3e cmd VE iat veil DIASO OmiosO lt OOWUOON Joss OIS eunels 7 i V 1 L1A 0 orb 0x000001 bx 0xd3e cmd 80 13 V 1 L1A 0 orb 0x000001 bx 0xd3e cmd 8 14 V 1 LIA 0 orb 0x000001 bx 0xd3e cmd 82 15 V 1 LIA 0 orb 0x000001 bx 0xd3e cmd 83 e V data valid e L1A the command is a L1A e orb orbit number e bx bunch crossing e cmd BGo command Core software The C components e Description of the core software o Briefly cover principle of uHAL operation o Cover derived nodes provided for MP7 e Description of the programs provided for standard functions and out of the box testing User software e Guide for how to write a program which uses and extends the core software MMG monitoring and IPMI The Atmel AT32 UC3A 3256 17 32 bit microcontroller MMC manages the power supplies on the MP7 provides IPMI functionality and configures the sensor readout It supports both USB 2 and a microSDHC card interfaces such that the MMC can be programmed via USB and firmware uploaded to the FPGA from a microSD card It is responsible for configuring network settings on the MP7 which allows the FPGA to be programmed via the gigabit ethernet connection on the backplane The firmware that provides this functionality is pre installed onto the MMC before distribution The MMC has a single user flash page dedicated to user data storage This is used to store the FRU info and persistent us
15. 1 8 MP7 XE Power Transceiver 1 2V You may need to manually copy this link into your internet browser Component Nelco N4000 13 EP SI Xilinx Virtex 7 XC7VX415T XC7VX485T XC7VX550T XC7VX690T Avago Technologies MiniPOD AFBR 81uVxyZ Avago Technologies MiniPOD AFBR 82uVxyZ Samtec SS4 4mm 0157 Super Low Profile Socket Strip SS4 50 4mm 0157 Atmel AT32 UC3A 3256 Xilinx CoolRunner II XC2C256 6FT256C Cypress CY7C2163KV18 550BZXI CY7C2263KV18 550BZXI CY7C25632KV18 550BZXI CY7C2663KV18 550BZXC Silicon Labs SI5326 Micrel SY89540U Micrel SY89833AL Silicon Labs SI53314 Samtec SMP EM 50 Ohm SMP RF Plug Edge Mount Linear Technology LTM4628 Linear Technology LTM4628 Linear Technology LTM4628 Linear Technology LTM4620 Linear Technology LTM4606 Datasheet http www parkelectro com parkelectro im ages n4000 13ep pdf http www xilinx com support documentat ion data sheets ds180 7Series Overview p df http www avagotech com pages minipod micropod http www avagotech com pages minipod micropod http www samtec com documents webfil es cpdf SS4 XX X XX X D X XX TR MKT pdf http www atmel com dyn resources prod documents doc32072 pdf http www xilinx com su ion data sheets ds094 pdf ort documentat http http http ress com doclD 32757 ress com doclD 31966 ress com doclD 27917 http ress com doclD 33228 http www silabs com pages Download
16. 18 N4000 13SI 0 075 0 075 3 300 Core 3 0 018 0 018 3 4 4000 1381 1080 0 075 0 075 3 300 PREPREG 4 0 018 0 018 N4000 13SI 0 075 0 075 3 300 Core 5 0 018 0 018 5 6 4000 1381 1080 0 075 0 075 3 300 PREPREG 6 0 018 0 018 N4000 13S 0 075 0 075 3 300 Core 7 0 018 0 018 7 8 P 4000 1351 1080 0 075 0 075 3 300 PREPREG 8 3 Foil 0 012 0 035 Foil 3 4000 1351 1080 0 075 0 075 3 300 PREPREG Es 4000 1381 1080 0 075 0 075 3 300 PREPREG 9 5 Foil 0 012 0 035 Foil 4000 1381 1080 0 075 0 075 3 300 PREPREG 10 0 018 0 018 9 10 N4000 13SI 0 075 0 075 3 300 Core 11 0 018 0 018 4000 1381 1080 0 075 0 075 3 300 PREPREG 12 0 018 0 018 11 12 N4000 13SI 0 075 0 075 3 300 Core 13 0 018 0 018 4000 13S1 1080 0 075 0 075 3 300 PREPREG 14 0 018 0 018 13 14 N4000 13SI 0 075 0 075 3 300 Core 15 0 018 0 018 4000 1381 1080 0 075 0 075 3 300 PREPREG 16 W mm Foil 0 012 0 035 15 16 Foil E Socermask 0 020 3 200 SolderMask Copper Thickness 0 353 Dielectric Thickness 1 200 Overall Processed Thickness 1 553 Figure 6 Layer stack up for the MP7 Nelco N4000 13 EP SI is used rather than FR4 because of its superior high frequency characteristics Thicknesses measured in thousandths of an inch unless otherwise stated To prevent skew across the members of the high speed differential pairs the alignment of the weave of the PCB is to be at an angle of 22 degrees relative to the orientation of the board so that neither the horizontal the vertical nor the dia
17. 7 Testing retient a cali 8 Getting started Basic connectivity test eee aaa aaa aaa aa aaa aaa aaa wawa aaaa aaa a akwa kaaa sss s sensi ta sanas nnns 8 Firmware OVEPVIEW twarza io Oczka AEO AO O tei 10 Core MWA E A RN 11 EN AA a bd 11 Link control at a global level i e latency and alignment ee uuseeua aa aa aaa aaa aaa aa nononononononononnnos 11 Link control at a local level i e protocols line rates error checking ooococccocnnococonnnononannnononanos 12 USEF FIN EIER 13 Building Firmwares iio 14 Programming the MPZ iia A Ad CAT wywi PAC WA 16 SUE Nell 19 Core software Standard scripts provided for quick configuration essen 19 Setting clock and TTC inputs sess nnnennnn inanes esset kaka aaa essentia sans nnn 19 Link configuration and alignment in loopback mode eeeeuao sua aaa aaa aaa aaa oaza aaa nennen 20 Capturing input and output data stream eeueeeu sss aa aaa aaa aaa aaa aaa aaa aaa aaa nnne nnn ener nnne 21 D ta do Mati ai 23 Configuring AMC13 to generate clock and L1A BCOs signals essen 24 CHECKING TTC INP Ut T m 24 Core software The C components ccccccccecesessssssseeececeseesesneaeeeeeceseesesaeaeeeeecesseaaeaeeeesesseeseasaeeeesens 25 User SOftwafe se a R a 25 MMC monitoring and IPM c cccccccccecsssessnsececececsesesenaeeeeeceseesesae
18. AMC card edge connector Ports shaded orange 0 1 2 and 4 to 8 are routed to multi gigabit transceivers on the FPGA Ports shaded green 12 to 15 are routed to the general I O of the FPGA Ports shaded red 17 to 20 are currently unassigned Other AMC card edge connections not included in this table are Telecoms Clock A Fabric Clock A geographic addressing IPMI and JTAQG esses nennen nennen nennen iia kanadia iniae kasiet 35 Table 2 Assignment of DIP switch functionality for selecting the JTAG source and controlling the inclusion exclusion of targets from the JTAG Chain ooooncccncocnnononnnonnononnnononnnonannnnnanonnnnno nan entren 37 Table 3 A summary of the component parts for the MP7 board and links to their datasheets Where there is a choice of part numbers the target part is underlined eese 48 55 Revision History Revision Release Date Notes 0 1 15 01 2014 Initial release 0 2 11 02 2014 Add Alessandro s getting started guide Add how to program the FPGA 56
19. Doc aspx FILEURL Support Documents TechnicalDocs Si5326 pdf amp src DocumentationWebPart http www micrel com PDF HBW sy8954 Ou pdf http www micrel com PDF HBW sy8983 3al pdf http www silabs com Support 20Docume nts TechnicalDocs Si53314 pdf http www samtec com documents webfil es cpdf SMP PX P XX ST EM3 MKT pdf WWW C WWW C WWW C WWW C http cds linear com docs Datasheet 4628f pd http cds linear com docs Datasheet 4628f pd http cds linear com docs Datasheet 4628f pd http cds linear com docs Datasheet 4620f a pdf http cds linear com docs Datasheet 4606f b pdf 47 Power Transceiver 1 0V MP7 Linear Technology http cds linear com docs Datasheet 4606f RO LTM4606 b pdf Power Transceiver 1 0V MP7 Linear Technology http cds linear com docs en datasheet 46 R1 amp MP7 XE LTM4601 O1fc pdf Power Transciever aux 1 8V Micrel http www micrel com PDF MIC5319 pdf MIC5319 Power CPLD 2 5V Micrel http www micrel com PDF MIC5319 pdf MIC5319 Power CPLD 1 8V Micrel http www micrel com PDF MIC5319 pdf MIC5319 Power SRAM 0 9V Richtec http tw richtek com download_ds jsp s 5 RT9040 23 Flash PROM Micron Serial NOR Flash http www micron com parts nor Memory 3V Multiple I O 4KB flash serial nor Sector Erase flash media Documents Products Data 2 N25Q256A13ESF40G OSheet NOR 20Flash Serial620N0R N250 5989n25q 256mb 3v 65nm ashx Monitoring Temperature Line
20. N Swap Bits OFF UFP C format Auto Select PROM Description In this step you will enter information to assist in setting up and generating a PROM file for the targeted storage device and mode 12 Checksum Fill Value When data is insufficient to fill the entire memory of a PROM the value specified here is used to calculate the checksum of the unused portions Output File Name This allows you to specify the base name of the file to which your PROM data will be written RZ OK Cancel Help 2 From SVN check out 3 Change into the imperial_mmc tools imgtool directory and run make to create the imgtool executable 16 If using an external card reader plug it into your linux PC WITHOUT THE SD CARD INSERTED 5 Insert the SD card 6 Run sudo sbin fdisk l There should be an entry that says Disk XXX doesn t contain a valid partition table Note the name of this disk 7 Run sudo chmod 777 XXX 8 The imgtool executable has several options The usage options can be seen by running imgtool Command Description format lt label gt Formats an image list List files in an image add lt name gt lt file gt Adds a file to an image get lt name gt lt file gt Gets a file from an image del lt name gt Deletes a file from an image check lt name gt Verifies the checksum of a file swap Byte swap an image 9 Usage of imgtool is then imgtool XXX Com
21. P7 version v value A standalone script is provided to perform the connectivity test The default values for address table and uri are ipbusudp 2 0 192 168 0 128 50001 and file etc uhal mp7_defaul top xml as in the example above For details on the other scripts provided for performing more complicated tasks please see section Core software Standard scripts provided for quick configuration on page 19 Firmware overview Since the MP7 is a generic data stream processor it can and will be used in many different roles The generic nature of the hardware however can only be fully realized if the firmware is also sufficiently generic Specifically the functionality of the board which is what the end user cares about must be abstracted from the physical hardware and the related service tasks much in the same way that when running an executable within an operating system the details of the hardware platform on which the executable is running is largely irrelevant On the MP7 this has been achieved using the layers of abstraction shown in Figure 1 a concrete example of the distinct regions is shown in Figure 2 Physical IO setup monitor Control Figure 1 The model of abstraction used in defining the MP7 firmware Figure 2 Firmware implementation in an MP7 R1 690 used in a CERN integration test The firmware clearly demonstrates the same segregation shown in the abstract model with the MGTs and DAQ buffer
22. UESTION HAS ALREADY BEEN ASKED BEFORE SUBMITTING A NEW TICKET Getting started Requirements e Linux SL6 64 bit recommended or Linux SL5 32 or 64 bit deprecated e Ethernet connection with the uT CA MCH e PBus suite version 2 2 installation instructions available at https svnweb cern ch trac cactus wiki uhalQuickTutorialifHowtolnstallthelPbusSuite Getting started Software overview The MP7 package is available on the cactus svn repository https svnweb cern ch trac cactus It is based on the uhal suite available at the same address Currently the mp7 package is available via svn only and needs to be compiled by the used It is planned to be released as RPM in the next future The MP7 software package is organized in 4 sub packages e mp7 C driver library e pycomp 7 python bindings to the C driver e gui MP7 dedicated gui work in progress e tests test programs and scripts The driver library contains the high level functions As C doesn t provide the necessary flexibility for board testing the mp7 library is provided with python bindings through the pycomp module In the tests folder are collected binaries and scripts for testing MP7s All the examples covered in the following sections are supposed to be executed in the tests folder Getting started Software Installation 1 Check out from SVN export LD LIBRARY PATH opt cactus lib LD LIBRARY PATH export PATH opt cactus bin SPATH Getting start
23. User guide for the IMP Master Processor Virtex 7 Andrew W Rose Greg Iles Aaron Bundock Sarah Greenwood Imperial College London John Jones Iceberg Technology Alessandro Thea RAL Dave Newbold Bristol This document contains information that is and remains the Intellectual Property of the High Energy Physics HEP group Imperial College London and Iceberg Technology Cornwall Duplication sharing or forwarding of the information contained in this document in part or in its entirety is expressly forbidden without the written consent of one of the authors Thank you for you cooperation User guide for the MP7 Master Processor Virtex 7 Contents Introduction odi o di rc 4 Memorandum of understanding esses eene nennen nennen rnnt nensis nn naar n rennen innen enne 5 Where can I find the helpful people see sea aaa aaa aaa aaa aaa eee nnne en nnne sene nenne 6 Getti g started xot A RS EL 7 REQUIFEMIENES ace sie ZE AA EE ERR Pa O CEEP A 7 Getting started Software overview seuas sauna nennen nnn enne nnne nennen nnne snnt enn 7 Getting started Software Installation essuaaa aaa aaa aaa aaa aaa rinanta isorinis aiia a 7 1 Check Gut trom SVN ee U u 7 2 Ensure that the uhal environment variable are properly set ssseuaa aaa aaa aaa anna aaa canaaae 7 A A O O 7 Getting started MP
24. aeeeeeceseeseaaeseeeeecesseseaaeseeeesensseseaaeeas 26 Firmware upload to FPGA from microSD Cardl cccccononooooncnncnnnnnnnonnnnnnnnnnnnnnnnnnonnnnnnnnnnononnnnnnncninanones 26 Al A A Wd ld at ee lento 26 Setting the IP and Mac addresSeS uuauao aaa aaa aaa aaa aaa aa aaa aaa a sese suas sais ases se sas asas anna 27 A A EE E T E E T 28 IPbusito MMC interface id 28 RET go rema 29 Hardware full specification uu aaa aaa awa a aa aaa aa aa anna aaa aaa aa waza aaa nenne aaa kaza aaa seas eniin stessa sena taik 32 PEB catan OOOO A AA A AAA Aa tras 32 duce N 33 Optical interface neenon ni entonces R W LE 34 Backplane connectiorns s t berti a E 35 General purpose I O 2 5 tuii kiwa lees ret eat en de n qe SR De ER ea A AR Fea SEEN AE 36 MMEController wst e 37 CRED AAN AAA e te iuberet are tete OOOO 37 A EM 37 RAM esse M 38 Clockin uui RUE REP ER ea E CEU 39 POWE esa ior reet Ren pre ane Eae ARR Re RARE EN A ERA CD RE Re NER ERE D RN oda RA EER EN ORAE Ne ERE ER 41 Flash PROMI zoe aloe ette RA OCR desl haute a etude on ice ere det settee OWA 42 On board Monitoring er t as 42 ENTERA E EE E EE E E E 43 Photographs of the MP7 RO prototype cccconocoocccconcnnconononnnnnononnnanononnnnnnnnnnnnnonnnnnnnnnnnnnnnr nn nnnnnnananannnnnnons 45 Pho
25. all links are checked for alignment If a link is not aligned the buffer read pointer is incremented This process repeats until all the links are aligned Next all read pointers including the master are incremented until the pointer read write clash occurs i e we have reduced the latency too much so that the read occurs before the write has completed This is detected by a jump in the position of the master alignment marker and or by loss of alignment While it is highly likely with 72 channels that loss of alignment will occur in the read write pointer overlap area this may not be the case for a few channels and will not work at all if just the master link is selected Hence the only way to detect the read write pointer overlap area is to monitor if the master link position moves this in turn requires that we can predict the next master link alignment marker which forces the master alignment signal to be periodic This is normally the case for CMS experiments in which there is generally 1 marker per orbit however care must be taken in more complex arrangements e g Time Multiplexed Trigger When the read write pointer clash has been detected the firmware decrements to read pointers of all links so that there is some margin between the read write pointers This is the align_margin parameter and some experimentation may be required to see how small this can be made and for the links to be stable Note that at present this firmware simply m
26. ar Technology http cds linear com docs Datasheet 2990f Current amp Voltage LTC2990 c pdf Monitoring Humidity Sensirion http www sensirion com en pdf product i SHT21 nformation Datasheet humidity sensor SHT21 pdf Front panel Schroff 20849 132 Table 3 A summary of the component parts for the MP7 board and links to their datasheets Where there is a choice of part numbers the target part is underlined 48 Hardware trouble shooting I was reprogramming the MMC in the Crate and now the MMC is powered but the rest of the board is not and without the CPLD I cannot JTAG the MMC This is an unfortunate by product of using the CPLD to route the JTAG chain and of the fact that the CPLD draws too much current to be safely run on the management power The double pole double throw switch mechanism on the power supply means that the card has two modes Desktop mode and Crate mode In Crate mode the MMC enables the bulk supplies and is itself enabled by the enable signal from the AMC connector If the MMC is bricked by uploading a bad program then it can disable the power supplies breaking the JTAG chain and thus preventing reprogramming of the MMC In Desktop mode the bulk supplies are enabled automatically since the MMC must be powered from the bulk 3v3 supply The only solution to restore a bricked MMC is to put the card in Desktop mode and reprogram it with a good image Trying to reprogram the MMC gives me erro
27. at the back half of the uTCA card The optical ribbons enter and leave the MiniPOD devices approximately 10 5mm above the surface of the PCB To avoid any risk of the optical ribbons becoming delaminated in the airflow of a uTCA crate it was proposed that the ribbons be mechanically fixed to a structural plane please see section Layout 8 Mechanics carrying them to the front panel connection at the same height above the PCB as they exit the MiniPOD It transpires however that the non peelable optical ribbon 11 used are sufficiently robust so as to eliminate this risk without the need for additional mechanical support The front panel optical connections are four 48 way MTP connectors 12 of which 36 channels on each connector are utilized All channels within each MTP carry data in the same direction The interface to external fibres is via MTP MTP adaptors which are mounted on the front panel of the board The board has been designed to also accept Molex Circular MT connectors 13 requiring only a different design of front panel should that option be necessary or desirable in future Backplane connections The MP7 uses the same AMC card edge connector as the Mini T5 rather than using a component connector since space on the board is limited and because such an approach reduces design risk As well as Telecoms Clock A Fabric Clock A geographic addressing IPMI and JTAG the AMC card edge connector features differential connections as
28. avoid any risk of the optical ribbons becoming delaminated in the airflow of a uTCA crate the ribbons would be mechanically fixed to a structural plane carrying them to the front panel connection at the same height above the PCB as they exit the MiniPOD It has since been found that the fibres are sufficiently rugged that the threat of delamination is negligible and that a mechanical fibre routing plane is unnecessary It has been found however that the thermal output of the Virtex 7 FPGA is significantly higher than the values initially provided by Xilinx The mounting holes which were originally included for the routing plane have instead been repurposed for supporting a large custom designed heat sink Figure 21 to provide considerable extra thermal dissipation compared to the off the shelf heatsink used on the original prototype Figure 20 43 The front panel layout can be seen in Figure 17 Figure 17 Front panel layout of the MP7 Yellow regions indicate UTCA infrastructure zones red regions contains LEDs etc the purple region contains the micro USB connector and microSDHC card connector whilst the orange region indicates the approx 37mm wide zone available for general purpose I O connections Screw mount MTP adapters are required to take up any slack in the ribbon cables manufacturing tolerances Board layout as of 08 02 2012 The front panels for the MP7 are based on front panel and e
29. chain on page 37 in the chapter Hardware full specification If you cannot see the XC7VX690T in your JTAG chain please see the section Trying to reprogram the FPGA gives me a wrong or unknown device in IMPACT on page 50 in the section Hardware trouble shooting Loading new firmwares over GbE has recently been achieved and is currently in the final stages of testing When this is complete a new version of this document will be released The MMC will need updating before remote uploading will work Directly programming the SD card can be a little awkward 1 Using IMPACT create a PROM file using the parameters e Generic Parallel PROM e Auto Select PROM e File Format BIN Swap Bits ON PROM File Formatter x Step 1 Select Storage Target Step 2 Add Storage Device s Step 3 Enter Data Storage Device Type a c zeneral File Deta Value ax FiastyPROM Parallel PROM Bytes 8K 8192 due Checksum Fill FF Non Volatile FPGA Add Storage Device Remove Storage Device Spartan3AN M a e HF HE SPI Flash Output File Na FILENAME Configure Single FPGA c Configure MultiBoot FPGA Output File Lo firmware E BPI Flash Configure Single FPGA Flash PROM File Property Value Configure MultiBoot FPGA gt Configure from Paralleled PROMS File Format MCS Generic Parallel PROM Loading Direction EXO Number Of Revisions AA HEX Swap Bits OFF BIN Swap Bits ON BI
30. d playback bunch crossing ranges are temporarily hard coded to bunch crossings O to 170 Data format The mp7 software uses a standard format to export and import data from the board buffers This format is used both for data injection and data capture and automatically converted by the mp7 library into the native buffer format An example of data file is shown below 4 channels only Board MP7 TEST Quad Chan q00c0 q00c1 q00c2 q00c3 Link 00 01 02 03 Frame 0000 0v00000000 0v00010000 0v00020000 0v00030000 Frame 0001 0v00000001 0v00010001 0v00020001 0v00030001 Frame 0002 0v00000002 0v00010002 0v00020002 0v00030002 Frame 0003 0v00000003 0v00010003 0v00020003 0v00030003 Frame 0004 0v00000004 0v00010004 0v00020004 0v00030004 Frame 0005 0v00000005 0v00010005 0v00020005 0v00030005 Frame 0006 0v00000006 0v00010006 0v00020006 0v00030006 Frame 0007 0v00000007 0v00010007 0v00020007 0v00030007 Frame 0008 0v00000008 0v00010008 0v00020008 0v00030008 Frame 0009 0v00000009 0v00010009 0v00020009 0v00030009 Frame 0010 0v0000000a 0v0001000a 0v0002000a 0v0003000a Frame 0011 0v0000000b 0v0001000b 0v0002000b 0v0003000b Frame 0012 0v0000000c 0v0001000c 0v0002000c 0v0003000c The first 3 rows are the header Multiple data blocks can be stored in the same file if necessary The Board field is used to identify the block in the file The Quad Chan and Link rows are included to 23 increase readability and are not used The rows starting with Frame dddd dd
31. dd is the frame number in decimal representation are the payloads The elements in the row have the format XVYYYYYYY where YYYYYYYY a the 32 bit word in hex format and X is the data valid bit Configuring AMC13 to generate clock and L1A BCOs signals The AMC13 board has the capability to generate internal clock 40 and feed them to the AMCs in the uTCA crate L1As and BCOs can be generated as well connecting the TTS output to the TTC input See the AMC13 documentation for further information A basic script to configure the AMC13 is included in the MP7 tests package Checking TTC input In case debugging the TTC inputs is needed the MP7 can capture and store up to 2048 L1As and B commands For each signal bunch crossing orbit and command are recorded as well as the command type The mp7 test ttchistory py script allows to capture the TTChistory from command line mp test ttccapture py MP7 TEST In addition the maskBCO option can be used to avoid storing BCOs in the TTC history MP7 WASI accesso successful INFO MiP WESI loyal Lie 0 V 1 L1A 0 orb 0x000001 bx 0xd3e cmd 74 1 Well DIASO qeuosQsx0QOOOI less Osos cunols 15 2 V 1 L1A 0 orb 0x000001 bx 0xd3e cmd 76 E Veil DIASO eulos l xsb5xolxe Cimes 77 4 V 1 L1A 0 orb 0x000001 bx 0xd3e cmd 78 5 V 1 L1A 0 orb 0x000001 bx 0xd3e cmd 79 6 V 1 L1A 0 orb 0x000001 bx 0xd3e cmd Ve U Weil DIASO duelo lo xo bxol5xe unes 715 8 Val DIASO eulos lx boe Cimes 76 9 V 1 L1A 0 orb
32. e processing clock domain by stripping out any padding words lastly the CRC is then checked and stripped from the packet The align marker i e the event within the data stream that is used for alignment is also defined here although it could be overwritten at a higher level if a user wanted to use something other than the start of the packet Coming in the next version of this document In the meantime please contact dave newbold cern ch or g ilesQimperial ac uk User firmware As stated previously the firmware model used is one where the user s algorithms firmware is fully abstracted from the details of the hardware implementation The entity declaration for the user s code is shown here use work mp data types all use work ipbus all entity algo is generic NCHAN positive F POTE Jobus Cels im STE logue Jobus mg alin WAD wows Jobus Outs OUE iplo Wows 7 dara Ciks am sia Logie Cece sms in ldata NCHAN 1 downto 0 data out out ldata NCHAN 1 downto 0 end algo e NCHAN is the number of optical data channels available For MP7 cards built with an XC7VX485T FPGA this is always 48 For MP7 cards built with an XC7VX690T FPGA this is always 72 13 e ipbus_clk ipbus in and ipbus out are the IPbus control bus for configuring the algorithms The use of these signals is described elsewhere Reference for use of IPbus is coming in the next version of this docum
33. ed MP7 Testing To set the test environment up do source setup sh in the tests folder Several examples are available in the scripts folder showing the basic capabilities of the MP7 service firmware e mp7 test ipbusaccess py simple IPbus access e mp7 test reset py board reset e mp7 test alignment py links configuration and alignment e mp7 test datacapture py links buffers setup and capture A few additional scripts are included to help setting up the test environment e amc13 setupinternalTTC py Configure an AMC13 to generate internal clock and BCOs e mp7 test ttccapture py Capture the TTC commands All the scripts include a commandline help Use lt script py gt help h to display the help It is recommended to use the ipython command shell for interactive access to the mp7 classes Getting started Basic connectivity test A preliminary health check is to checking the connectivity to the MP7 board Here is assumed the uTCA MCH to be reachable at 192 168 0 103 and the MP7 at 192 168 0 128 Instructions on how to change the MP7 IP address are available in the Error Reference source not found section 1 Check MCH and MP7 responsiveness to pings 5 pings each ping c5 192 168 0 103 import uhal board uhal getDevice mp7 board MODUSCACZZADE ZOZ 1665 0 129 9 5000 Dope ece unal mp deLanl cop mi E v board getNode ctrl id read board dispatch print M
34. ent In the meantime please contact dave newbold cern ch e data in and data out are the input and output pipes which are externally connected to the optical links with data being clocked through both pipes on the rising edge of signal data clk Type data is an unconstrained array of type word where lword is a record with entries o data a 32 bitstd logic vector o valid astd logic flag indicating whether or not the accompanying data is valid In theory the interface to the QDR ram could also be exposed although the use case for this has not yet been demonstrated There may also be a use case for a reset line e Dave is there a use case for a reset line Coming in the next version of this document In the meantime please contact dave newbold cern ch Building Firmwares Because of the complexities involved in collaboratively building firmwares a TCL based build system is used for building firmwares which are based on components in the CACTUS library To create a new firmware for the MP7 perform the following operations 1 If you do not already have a copy check out the CACTUS trunk Either Full Checkout svn co https svn cern ch reps cactus trunk opt cactus Minimal Checkout just firmware components evn CO UFEDSE sm cer en reps caccus crtnk boards https svn cern ch reps cactus trunk components opt cactus trunk Where the opt cactus may be set to whichev
35. er location you wish to install CACTUS in 2 Run the following BASH commands 14 export MP7 VERSION mp7 485 or mp7 690es export CACTUS TRUNK opt cactus trunk In Sia S CACTUS TRUNK boards mp7 base fw MP7 VERSION ln sf CACTUS_TRUNK components ipbus 1n 5f CACPUS TRUNK componemts mp7 etri ln sf CACTUS_TRUNK components mp7 counters NE sf CACTUS TRUNK components mp7 xpoint ln sf S CACTUS TRUNK components opencores 126 ln sf S CACTUS TRUNK components mp7 ttc ln sf CACTUS TRUNK components mp7 mgt ln SF CACTUS TRONK components mo ND EDS cp rf CACTUS TRUNK components mp7 algo main In sf main mp7 algo export REPOS FW DIR pwd export REPOS BUILD DIR pwd MP7 VERSION isel4 mkdir work cd work Source RELOS EW DIR 1pBusS Ti irmwere examole desgus scripes setup Sh ed Making sure to set the CACTUS TRUNK and MP7 VERSION environment variables appropriately 3 Change into the work directory and open the generated xise file using ISE Add your algorithm code to the file main firmware hdl null algo vhd Coming im Ehe next version of this document Tn the meentime please contact dave newbold cern ch 15 Programming the MP7 The board has the multiple means of programming e JTAG e Remote programming over IPbus e Direct programming of the SD card The JTAG chain is described in the section JTAG
36. er settings such as the IP address or the FPGA boot image file name This section provides details on how to utilize the MMC functionality to set up the MP7 for operation and monitor its sensors Firmware upload to FPGA from microSD card The SD card is formatted with a file system known as simple firmware file system SFWFS The storage medium is divided into slots around the size of a firmware image guaranteeing an image can be stored without fragmentation An index table at the front of the disk stores whether a slot is in use a file name file size and checksum which allows access by name A full library of SFWFS operations is included The image files are stored in the blocks after the header They do not require their own header and just start at the appropriate block slot and end before the next image Any unused space in the slot should be padded with OxFFFFFFFF if the images are being used to configure the FPGA Sensor monitoring In the course of debugging the sensors on the MP7 it has come to light that there is a bug in ipmitool which can cause sensors to incorrectly appear as Disabled When using ipmiutil or NatView these sensors are seen to operate correctly There are 8 LTC2990 sensors on the MP7 that are monitored using the IPMI out of band management protocol The raw values from the sensors are converted according to settings in the sensor data repository SDR written to the MMC The sensor readi
37. er the algorithm block as shown in Figure 3 Each buffer is 1024 entries deep Each entry has 33bits The first 32 bits are the data payload bit 33 is the data valid bit The buffers operation mode is configurable via IPbus When set to capture the buffers are filled with data over a user selected bunch crossing range When the buffer block is in playback mode the user must define a bunch crossing range as well within the range the data valid bit is used outside data valid is forcefully set to low The data capture is triggered via IPbus The capture data is accessible via IPbus as well 21 rx deser buffer transciever loop loop m b a algo block tx ser c d Figure 4 Schematic view of the available link buffer configurations a Simple loop b Link loop c Algorithm test d Data capture mp7 test datacapture py is a test script to configure the MP7 link buffer system capture data and save it to file The buffers configurations can be grouped in 4 main categories e Simple loop Tx buffers are the data source connected to Rx buffers via an direct loop Figure 4a Used to test the buffer system functionalities e Link loop similar to the previous category but the loopback connection goes through the links serialization deserialization stage Figure 4b Requires the loopback option e Algorithm test Useful to validate the algorithm block with user pattern or Monte Carlo data The data is genera
38. gonal traces are aligned with the PCB weave Due to issues with material availability and problems with the hydrophilic properties of NELCO for the MP7 XE was chosen as the preferred material 32 FPGA The MP7 uses a mid range Xilinx Virtex 7 FPGAS of one of four pin compatible parts e XC7VX415T 48 GTH links e XC7VX485T 56 GTX links e XC7VX550T 80 GTH links e XC7VX690T 80 GTH links With all being available in a 45mm x 45mm FFG1927 package GTX transceivers support selected line rates up to 12 5 Gb s in the 3E and 2GE speed grades and up to 10 3125 Gb s in the 2C 2LE and 2l speed grades GTH transceivers support selected line rates up to 13 1 Gb s in the 3E and 2GE speed grades up to 11 3 Gb s in the 2C and 2LE speed grades and up to 10 3125 Gb s in the 21 speed grade The wide range of pin compatible parts and speed grades allows for flexibility in balancing cost and performance A comparison of the four pin compatible parts can be seen in Figure 7 Virtex 7 FPGAs 1 0V 0 9V Part Number XC7VX415T XC7VX485T XC7VX550T XC7VX600T EasyPath Cost Reduction Solutions XCE7TVX415T XCE7VX485T XCE7VXS550T XCETVXE90T T Slices 64400 75 200 86 600 108 300 Logic Cells 412 160 485 760 554 240 603 120 CLB Flip Flops 515200 607 200 602 800 866 400 Maximum Distributed RAM Kbits _ 6 525 8 175 8 725 10 888 e Block RAM FIFO wi ECC 36Kbits each 880 1 030 1 18
39. he SD card dip switch 5 on the MP7 RO and dip switch 4 on the MP7 R1 or MP7 XE must be down 18 Software Overview Coming in the next version of this document In the meantime please contact Al essandro Thea cern ch Core software Standard scripts provided for quick configuration For instructions on how to get the standard MP7 scripts please see section Getting started Software Installation on page 7 in the chapter Getting started Setting clock and TTC inputs The MP7 can either generate the 40 MHz clock internally use an external clock generator or the TTC clock from the AMC13 TTC signals and in particularly BCOs are used in synchronization and data capture procedures The MP7 can generate BCO signals internally in case no external generator is available The mp7 test reset py script shows how to reset an MP7 board and configure 40 MHz clock and reference clock Two clock configurations are supported by mp7 test reset py e External 40 Mhz clock and external TTC signals mp7 test reset py clk40 external TTC inputs are enabled as well e Internal 40 MHz clock and BCO External TTC inputs are disabled whilst the internal BCO generator is active In case the MP7 responds on a different ip address the connection uri can be set using the uri flag The configuration is completed if clock 40 and BCO are successfully locked MIP TESTI ACCESS suecos sil WARNING RSsSeuw ciao DOELE IMP
40. in which is at the BOTTOM edge of the board and is labelled SWITCHED JTAG The switched JTAG chain is controlled by the DIP switches Table 2 Switch Switch MP7 RO MP7 R1 and MP7 XE Function UP to exclude from JTAG chain DOWN to include in JTAG chain SRAM 1 JTAG source e UP for SWITCHED JTAG local header e DOWN for AMC connector Table 2 Assignment of DIP switch functionality for selecting the JTAG source and controlling the inclusion exclusion of targets from the JTAG chain 37 Switched JTAG header AMC connector CPLD DIP JTAG switches header Figure 12 Connections of the JTAG network on the MP7 Two JTAG source the Switched JTAG header and the AMC connector can be connected to any of four JTAG targets with the configuration of the chain controlled by the DIP switches The CPLD is itself programmed by a dedicated JTAG header labelled CPLD JTAG To boot from the SD card dip switch 5 on the MP7 RO and dip switch 4 on the MP7 R1 or MP7 XE must be down To boot from the SPI PROM dip switch 5 on the MP7 RO and dip switch 4 on the MP7 R1 or MP7 XE must be up RAM The MP7 provides up to 288Mbit of QDR ll SRAM in the form of 2 x 144Mbit Cypress CY7C2663KV18 550BZXC 8Mx18bit 19 chips giving memory access of up to 550MHz DDR 1100MHz per chip The SRAM chosen is pin compatible with lower capacity parts and so cost and performance may be balanced The pin compatible parts are e
41. inimises latency lt may be necessary to augment the functionality of the block so that the latency i e read pointer location is set in relation to TTC and thus fixed Link control at a local level i e protocols line rates error checking The main link functionality i e error checking line protocol definition and the Rx buffer is defined in the entity ext align gth spartan which is wrapped by the entity quad wrapper gth so that an ipbus interface can be added and the object used at the global level The process of transmitting data out of the transceiver consists of the following steps a CRC is appended at the end of the data stream as defined by the end of the data valid signal the data is bridged from the processing clock domain i e typically 160MHz or 240MHz to that necessary for the line rate i e 250MHz for 10Gb s with padding words inserted if necessary the data words are replaced with 8b 10b k codes where data valid is de asserted so that the 8b 10b byte alignment can be performed comma 0x505050BC with charisk set to 0b0001 or where padding words have been inserted padding word OxF7F7F7F7 with charisk set to 0b1111 12 The receive data path consists of is first passing the data through the Rx buffer entity Rxdata_simple_cdc_buf which allows the data to be delayed for link alignment and latency control It also performs the clock bridging from the link clock domain which is defined by the line rate to th
42. kplane e 72 links XC7VX550T or XC7VX690T or 48 links XC7VX485T Optical transceivers 33 Optical interface Whilst the Mini T5 used PPOD optics there is insufficient front panel space on a UTCA board to mount enough PPODs to take full advantage of the Virtex 7 s serial link capability Instead new mid board optics designed for the super computing industry are used namely the Avago MiniPOD 9 Figure 8 p 39 Figure 9 An example of Avago MiniPODs in use showing how unruggedized optical ribbons can be threaded through sequential devices MiniPODs are pluggable optical devices whose electro mechanical interface for is a 9x9 MegArray connector 10 very similar to the 10x10 MegArray connector used by the PPODs on the Mini T5 Each MiniPOD device provides 12 serial channels at line rates of 10 3125Gb s Because MiniPODs are mid board devices they may be positioned to minimize the trace length and maximize signal integrity When used with unruggedized fibres MiniPOD devices can be placed close together and the ribbons threaded through sequential devices Figure 9 allowing for a very high data density The MP7 board has 6 MiniPOD transmitter sites and 6 MiniPOD receiver sites giving 72 links in each direction For use with an XC7VX485T FPGA only 4 transmitters and 4 receivers need be fitted further reducing cost 34 Manufacturing constraints on the length of optical ribbon cables constrains the optics to be located
43. mand parameters imgtool XXX format Firmware JAumtoodl AGO eol WA Sa AAZ aoM imgtool XXX swap Where XXX is the name of the SD card as reported by fdisk in step 6 YYY bin is the name you wish the firmware to have on the SD card and ZZZ bin is the name of the PROM file created in step 1 This formats the SD and gives it the volume name Firmware On old versions of the MMC only one firmware image is supported and that image must always be called ipbus2 bin if this file does not exist on the SD card the FPGA will not be programmed On the latest version of the MMC the name of the firmware image from which the card is booted at power up must always be GoldenImage bin if this file does not exist on the SD card the FPGA will not be programmed at power up and so Ethernet access will not be available 11 To list the contents of an existing SD card imgtool XXX swap gt aumento XO ASE imgtool XXX swap 17 The swap command is currently required as the file allocation table is read NATIVE endian The Atmel UC3A3256 is big endian whereas most PCs are little endian and so the endianness must be swapped before it may be read by a PC and then swapped back before it is given to the microcontroller It is proposed that this will change in future and the endianness handled automatically in imgtool The checksum functionality currently has a bug in the implementation and should not be used To boot from t
44. mination voltages It has been suggested that the primary cause of the failure of optical components in the ATLAS experiment may be the humidity of the operating environment 31 and that the same may apply to optical failures seen by CMS Given the high density of optics on the MP7 a SHT21 humidity and temperature sensor by Sensirion 32 is used to monitor atmospheric humidity 42 R T9040 0 9V Bench top operation HTCA crate operation SRAM in RT9040 TE 1v5 8A A SY 1v8Q 8A MIC5319 1 FPGA I O 2 5V 1 8V LTM4628 3v3 8A LTM4628 LTC3529 my o EM 1v0G8A 5V LTM4601 FPGA Core 1v0 6A MIC5319 ive 1 458 Upper GTX GTH 1v2 96A MIC5319 LTM4601 1v006A LTM4606 a 1v2 6A Lower GTX GTH Figure 16 Power architecture of the MP7 XE board Layout amp Mechanics As stated in the Optical interface section manufacturing constraints on the length of optical ribbon cables constrains the optics to be located at the back half of the uTCA card Rather than mounting the Virtex 7 FPGA between the MiniPOD optics which would have minimized the lengths of the 10Gbit s traces the FPGA is mounted forward of the optics to ensure unobstructed airflow for heat dissipation The optical ribbons enter and leave the MiniPOD devices approximately 10 5mm above the surface of the PCB and it was originally proposed that to
45. nectors A single such connector provides 30 differential pairs to from the FPGA 3v3 2v5 and 1v8 supplies and dedicated I2C lines to the microcontroller Front panel space is severely restricted and any connector must be less than approx 37mm wide see also section Layout 8 Mechanics The Samtec SS4 ultra fine pitch connector can be used to provide front panel I O by means of a miniature smaller than approx 37mm x 53mm daughter card Since the front panel I O is mounted on a daughter card the user has many options open to them It is perhaps worth reemphasizing that front panel space is severely restricted and any connector must be less than approx 37mm wide One possibility is to use Samtec Edge Rate connectors 16 Figure 11 providing 16 general purpose LVDS pairs although mechanical considerations must still be checked for this Figure 11 Samtec Edge Rate connector and cable assembly one proposed solution for front panel I O on the MP7 36 MMC Controller The MP7 implements MMC functionality using the same 32 bit microcontroller as the Mini T5 namely an Atmel AT32 UC3A 3256 17 The microcontroller implements IPMI communications and management and monitoring of the UTCA extraction handle the temperature humidity sensors and the uTCA indicator LEDS The microcontroller also provides a USB 2 interface to the board a serial console and sets the IP address of the board The USB connector on the MP7 is a mic
46. ngs can be retrieved using the ipmitool software 34 or the NatView program 35 With ipmitool the sensors can be readout from the command line with ipmitool H addressi A none sdr entity address2 where the first address is that of the MCH module and the second address is the board location in the UTCA crate The rest of the options shown above are explained in the ipmitool manual Please note that use of the ipmitool software requires the OpeniPMI package 36 included in standard distributions The command above returns a list detailing the sensors names and corresponding measurements If the sensor reading is outside of the range nominal value nominal value the command will return status ns not set and Disabled for that sensor This does not necessarily mean that the sensor is not operating but that the value is not within the correct range to be converted and sent as a 8 bit signed int over IPMI Details of all boards in the crate including the board address address2 above and the status of sensors can be listed using the command 26 ljwniicood A 192 188 041 A none Sensor To monitor the sensor output in NatView one must open the program and first connect to the MCH module by clicking on the Connect icon at the top left and enter the MCH IP address Once successfully connected the program will display all boards running in that crate and the complete list of sensor readings is then available Natview
47. o each quad with rst p The alignment mechanism that is performed at a global level is controlled by rst cntrl Data to from the quad d and q is presented in the form of an array of links of type Idata that is made up of the record type Iword than contains a 32bit data word and data valid signal The serial interface to the transceiver is presented by refclkp n Rxp n and Txp n Link control at a global level i e latency and alignment Components quad wrapper gth and Rxdata simple cdc ctrl are the significant components within mp7 mgt The former simply wraps the main quad code ext align gth spartan with an ipbus interface The latter Rxdata simple cdc ctrl allows control of the cdc clock domain crossing buffer that is instantiated for each channel This buffer bridges from the transceiver Rxuserclk2 clock domain whether it be asynchronous or synchronous to the LHC clock to the processing clock domain In the synchronous case the Rxuserclk2 clock may be the processing clock and a dual port ram would not be needed however there would still need to be a FIFO like object to align links and provide the option of latency control The buffer dual port ram relaxes the operational characteristics of the transceiver and makes the system more flexible albeit with a small increase in latency that can be offset by running the links at a slightly faster asynchronous rate internal transceiver logic runs faster Originally there was a dedicated b
48. or mtpconnector rev4 pdf Molex Inc Circular MT Optical Cable Assemblies 2010 http www molex com elgNow elgRedir htm ref http rhu004 sma promail com SQLlmages kelmscott Molex PDF Images 987650 3051 PDF 51 14 15 16 17 18 19 20 21 22 23 24 25 26 27 Larsen R S PICMG xTCA standards extensions for Physics New developments and future plans Real Time Conference RT 17 IEEE NPSS vol no pp 1 7 24 28 May 2010 http ieeexplore ieee org stamp stamp jsp tp amp arnumber 5750327 amp isnumber 5750311 Samtec Inc SS4 4mm 0157 Super Low Profile Socket Strip 19 April 2007 http www samtec com documents webfiles cpdf SS4 XX X XX X D X XX TR MKT pdf Samtec Inc ERF8 RA 8mm 0315 Edge Rate Socket Strip Right Angle 10 August 2010 http www samtec com documents webfiles cpdf ERF8 XXX XX X D RA XXX TR MKT pdf Atmel Corp AT32UC3A3 A4 Series November 2011 http www atmel com dyn resources prod documents doc32072 pdf Xilinx Inc DSO94 XC2C256 CoolRunner Il CPLD 11 September 2008 http www xilinx com support documentation data sheets ds094 pdf Cypress Semiconductor Corp 144 Mbit QDR II SRAM 4 Word Burst Architecture 2 5 Cycle Read Latency with ODT 6 December 2011 http www cypress com doclID 33228 Silicon Labs Inc Si5326 Any Frequency Precision Clock Multiplier Jitter Attenuator September 2010
49. ower has been supplied by Micrel MIC5319 regulators 27 chosen for their low noise and ultra small footprint Specialist regulators are used for the QDR termination voltage on the SRAM 28 To improve the performance of the clocking on the MP7 XE the clocking components on that board are also supplied by dedicated Micrel MIC5319 regulators again chosen for their low noise and ultra small footprint The power architecture of the MP7 XE can be seen in Figure 16 Flash PROM The MP7 is to use a Micron N250256A13ESF40G 256Mb SPI NOR Flash 29 which is pin compatible with parts up to 1Gb Investigations are also on going into the feasibility of using the microSDHC card see also section MMC Controller to store firmware images and to use the MMC controller as a boot loader for the FPGA Even if this method works satisfactorily a Flash PROM is still included in the design On board Monitoring Systems monitoring is particularly important on the MP7 because of the board s extreme performance and the complexity of and tight requirements placed on the power supply network Linear Technologies LTC2990 Quad I C Voltage Current and Temperature Monitors 30 are used to monitor e the temperature output voltage and current draw on each of the LTM4628 regulators e the temperature output voltage and current draw on each pair of the LTM4606 regulators e the temperature and supply voltages at the centre of each group of optics e the SRAM ter
50. r Upgrade CACTUS repository e AMC13 TTC decoder amp TTS encoder e AMC13 DAQ interface e QDRII RAM example e Ethernet interface IPBus e MMC diagnostics temperature voltage current e Clock configuration interface e MGT Quad interface only QPLL supported for lower power consumption amp improved signal integrity albeit with reduced line rate support e FPGA firmware storage via MMC MicroSD card e FPGA firmware remote load via IPbus e MMC Backdoor to the FPGA IPbus e MACaddress storage and retrieval for IPbus e P address assignment method final method TBD by the DAQ group The listed modules are provided by Imperial College London the University of Bristol Rutherford Appleton Laboratory and Iceberg technology and are supported as is Any change or modification to any of these modules invalidates the terms of use the contract of support will no longer be valid and the responsibility for debugging is with the user with assistance completely at the discretion of the developer Where can I find the helpful people A mailing list exists using the CERN e groups system over which news updates changes modifications etc to the hardware firmware and software will be announced This list may be joined at https e groups cern ch e groups Egroup do egroupName mp7 users Questions and bug tracking is managed through the CACTUS TRAC ticket system https svnweb cern ch trac cactus report 1 PLEASE CHECK TO SEE IF YOUR Q
51. res Figure 1 The model of abstraction used in defining the MP7 firmware eese 10 Figure 2 Firmware implementation in an MP7 R1 690 used in a CERN integration test The firmware clearly demonstrates the same segregation shown in the abstract model with the MGTs and DAQ buffers regions corresponding to the blue and green layers in Figure 1 and the DAQ and Communication regions corresponding to the grey control block The central unlabelled part of the firmware is the firmware dedicated to the user s algorithms sees 10 Figure 3 Link buffers and generatorS euuueaaaa aaa aaa aaa aaa aaa aaa nennen enne nsns ne tennis nass sn ense nian nis 21 Figure 4 Schematic view of the available link buffer configurations a Simple loop b Link loop c Algorithm test d Data Capture ua ana eia esee e Ce Pee i toe estt Fees 22 Figure 5 Annotated layout of the MP7 RO and MP7 R1 cards The MP7 XE layout is similar except that many of the clocking components are relocated to the top face of the card 31 Figure 6 Layer stack up for the MP7 Nelco N4000 13 EP SI is used rather than FR4 because of its superior high frequency characteristics Thicknesses measured in thousandths of an inch unless Otherwise Iidem I 32 Figure 7 Comparison of the Xilinx Virtex 7 series FPGAs which can be used on the MP7
52. ro B type connector rather than the mini B type on the Mini T5 so that it fits on the bottom face of the board The Atmel AT32 UC3A 3256 also supports a microSDHC card interface and a microSDHC card connector is also included at the front panel of the MP7 This is again on the bottom face of the board The software for the MMC controller has been tested on the Mini T5 and the board level connections of the microcontroller are to be kept as similar as possible such that the same software may be used on both boards Because of changes in the powering of the Virtex 7 FPGA it was necessary to reroute the FPGA to microcontroller bus through the CPLD to provide level translation This change does not affect the microcontroller software CPLD As per the Mini T5 the MP7 uses a Xilinx XC2C256 CoolRunner II CPLD 18 On the Mini T5 the CPLD was primarily used for programmable routing of the JTAG chains On the MP7 the CPLD is also be used as a level translator for various other components due to the changes in the powering of the Virtex 7 FPGA JTAG chain The JTAG chain of the MP7 is routed through the CPLD allowing components to be switched in and out of the chain and to allow switching between sources Figure 12 Because the CPLD is itself programmed via JTAG the MP7 has two JTAG headers One for programming the CPLD which is at the TOP edge of the board and labelled CPLD JTAG and one for programming the components in the JTAG cha
53. rs in AVR32STUDIO Does your error look like this 4 Tasks 2 Problems Executables 4 Search lt terminated gt DEBUG MP7 AVR Application opt as4e ide plugins com atmel avr utilities linux x86 64 3 0 0 201009140848 os linux x86 64 bin avr32gdbproxy Connected to JTAGICE mkII version 6 6 6 6 at USB 070000005B22 Failed to initialize the AVR32 GDB proxy Failed to initialize emulator No device detected Tried both JTAG and aWire Failed to initialize AVR32 aWire mode setParameter he command was not understood by the JTAGICE mkII unit Failed to initialize AVR32 JTAG mode Got unknown JTAG ID Oxffffffff Your JTAG chain is broken Three possible causes e Are the dip switches correctly On the MP7 RO switch 2 should be down and switches 1 3 4 and 7 should be up On the MP7 R1 and MP7 XE switch 7 should be down and switches 8 6 5 and 2 should be up e You are connected to the wrong JTAG header Make sure that you are connected to the SWITCHED JTAG header at the bottom edge of the card not the CPLD JTAG header at the top edge of the card e Your dongle for adapting the ATMEL style JTAG header to the Xilinx style JTAG socket is broken faulty 49 Trying to reprogram the FPGA gives me a wrong or unknown device in IMPACT Does your error look like this A ISE IMPACT P 68d firmware Eb File Edit View Operations Output Debug Window Help SA ET E ENE 088 Right click device to select opera
54. s regions corresponding to the blue and green layers in Figure 1 and the DAQ and Communication regions corresponding to the grey control block The central unlabelled part of the firmware is the firmware dedicated to the user s algorithms 10 Core firmware Link control The top level entity mp7_mgt provides access to the serial links in groups of 4 links called quads The number of quads is set by the generic NQUAD The other generics CLOCK_RATIO and LHC_BUNCH_COUNT refer to the ratio between the LHC clock 40MHz and the data rate in out of the transceiver e g the CLOCK_RATIO 6 if the data is clocked at 240MHz The LHC_BUNCH_COUNT is simply the number of bunch crossing per orbit 3564 for LHC but for debugging it can be useful to reduce this The core has 4 ipbus interfaces for controlling channel functionality channel alignment and the internal transceiver characteristics at both the channel level and the characteristics common to all channels via the Dynamic Reconfiguration Ports DRP The signal qsel selects which quad is selected for ipbus communication ant any given time The utility clock sysclk should always be present It is used to drive startup state machines in the transceiver At present this is sourced from the 125MHz free running clock clk_fr The reset signals rst p and rst cntrl are all in the processing clock clk_p domain i e typically 160MHz or 240MHz The reset signal is provided t
55. shown in Table 1 Port O Gigabit Ethernet Port 1 DAQ Port 2 SATA SAS Port 4 PCl express SRIO Port 5 PCl express SRIO Port 6 PCl express SRIO Port 7 PCl express SRIO Port 8 Extended FAT PIPE Table 1 Differential connections of the AMC card edge connector Ports shaded orange 0 1 2 and 4 to 8 are routed to multi gigabit transceivers on the FPGA Ports shaded green 12 to 15 are routed to the general I O of the FPGA Ports shaded red 17 to 20 are currently unassigned Other AMC card edge connections not included in this table are Telecoms Clock A Fabric Clock A geographic addressing IPMI and JTAG General purpose I O The MP7 provides two general purpose that is non MGT interfaces via the AMC card edge connector and through low profile connectors on the top face of the board The connector on the top face of the board is positioned such that it may also be used as front panel I O The Select I O resources on the Virtex 7 FPGA allow each differential pair to run at speeds of up to 1 866 Gbit s The AMC card edge connection include 7 general purpose LVDS pairs for details please see section Backplane connections The low profile I O is provided by a single Samtec SS4 ultra fine pitch connector 15 Figure 10 with 30 differential pairs to from the FPGA 3v3 2v5 and 1v8 supplies and dedicated I2C lines to the microcontroller Figure 10 Samtec SS4 ST4 ultra fine pitch high speed con
56. tching supplies are phased to reduce transient loads On the MP7 R1 and MP7 XE the 1 0V supplies for the MGT banks were changed to Linear Technologies LTM4601 regulators 26 because of the need for a higher current rating Naturally the possibility of power supply changes introducing noise was a major concern so several test cards which could be 41 mounted on a revision 0 card were produced to test alternative power supply designs Noise was measured both electrically and by its effect on the error rate of the 10Gbps optical links The noise performance of all the tested designs was similar and the design based on the Linear LTM4601 switch mode regulator was chosen since the LTM4601 is the same size as the LTM4606 and uses similar external components making it the simplest and safest replacement On the Mini T5 it is possible to bridge the 3 3V supply to the management power supply for bench top operation using a single 12V supply by means of a 0 1 header jumper This presents the risk of shorting the power supplies if the jumper is not removed before the card is inserted into a uTCA crate To avoid this possibility on the MP7 the design has been changed to switch between the two supplies rather than bridging the two by using a double throw switch For convenience the enable signal for the switching supplies has been routed from either 12V or the microcontroller by the same switch The CPLD I O power and the FPGA transceiver aux p
57. ted by the Rx buffers and captured by the Tx buffers Figure 4c e Data capture As in standard operation mode the data is received from an external source Tx buffers Rx buffers or both are configured for capture see Figure 4c The details command line syntax is The m mode option selects the operation mode Mode Description Tx Rx disabled No capture Both Tx and Rx buffers are disabled disabled disabled algoPlay Rx buffer data played back into the algorithm capture playback block algoPatt Hardcoded pattern into the algorithm block capture pattern loopPlayB2B Direct buffer to buffer loop with data playback playback capture loopPlayMGT Buffer to buffer loop via the MGT loopback pattern capture with data playback Requires loopback loopPattB2B Direct buffer to buffer loop with hardcoded playback capture 22 loopPattMGT Buffer to buffer loop via the MGT loopback with hardcoded pattern Requires loopback Rx buffer capture captureTx Tx buffer capture captureRxTx Rx and Tx capture Rx receiving buffers Tx transmitting buffers pattern capture disabled capture capture captureRx capture disabled capture Additional options are e inject to specifies what data to upload to the buffers configured for playback e path to select in what folder the captured data is saved e reset align and loopback with the same functionality as in mp7 test configlinks py The capture an
58. tions Boundary Scan E SystemaAcE E Create PROM File PROM File F TDI E WebTalk Data unknown bypass TD Your dip switches are most likely set incorrectly and you are connected to the MMC not the FPGA On the MP7 RO switch 1 should be down and switches 2 3 4 and 7 should be up On the MP7 R1 and MP7 XE switch 8 should be down and switches 7 6 5 and 2 should be up Does your error look like this A ISE IMPACT P 68d firmware EG File Edit View Operations Output Debug Window Help DAA EE E E ICE EU PR iMPACT Flows E amp 3 SystemACE E Create PROM File PROM File F TDI E WebTalk Data xc2c256 bypass TDI This is the CPLD you are connected to the wrong JTAG header Make sure that you are connected to the SWITCHED JTAG header at the bottom edge of the card not the CPLD JTAG header at the top edge of the card My board is booting from the PROM rather than the SD card To boot from the SD card dip switch 5 on the MP7 RO and dip switch 4 on the MP7 R1 or MP7 XE must be down 50 References 1 10 11 12 13 G lles and A Rose CMS IN2011_008 A Time Multiplexed Calorimeter Trigger for CMS 22 March 2011 http cms cern ch iCMS jsp openfile jsp type IN amp year 2011 amp files IN2011 008 pdf Xilinx Inc UG190 Virtex 5 FPGA User Guide 17 May 2010 http www xilinx com support documentation user guides ug190 pdf Avago
59. tographs Ofthe MP7 RI a A AS A wid A a annie 46 Parts SUMMA a a Wd ek ed ena heh ER E a aE 47 Hardware trouble shooting nseri aaae a A Eaa a E a aiaa EE a aaa Ta eaaa tiaia 49 was reprogramming the MMC in the Crate and now the MMC is powered but the rest of the board is not and without the CPLD I cannot JTAG the MMC uee eee ee eee aaa aaa aa a aaaaaaanaecea 49 Trying to reprogram the MMC gives me errors in AVR32STUDIO l ccccnnnnonococnnonononononannnnnnncconanonos 49 Trying to reprogram the FPGA gives me a wrong or unknown device in IMPACT 50 My board is booting from the PROM rather than the SD cardl ccccccnnnoconoonnnnoninanonanannnononinnnonos 50 References UE 51 List of Figures List of Tables Revision Hist le ada AE Introduction to the MP7 The MP7 Master Processor board Virtex 7 is the successor to Imperial College s Mini T5 board 1 The Mini T5 board is a technology demonstrator board with considerable processing capability in its own right a system of six Mini T5 R2 boards has been used to demonstrate the feasibility of the Time Multiplexed trigger concept although it is sufficiently flexible that it is equally suitable for use in a conventional trigger The long term use of the Mini T5 board is however not recommended for two reasons first it uses the now outdated Xilinx Virtex 5 series FPGA 2 and second it uses both QSFP 3 and either SNAP 12 4 or PPOD 5
60. uffer control logic for each channel but because of concern over logic resource usage it was extracted and placed at a global level Rxdata simple cdc ctrl The advantage of this is that automatically minimising latency across channels becomes simple however it is necessary to have intermediate FFs to meet timing particularly when sending the align marker signal i e the marker in each link that other links should be aligned to from the buffer to the central logic because the signal is travelling from the periphery to the centre and thus clock skew is not negligible 11 The buffer control is intended to be quite simple There are just 4 signals buf_ptr_inc and buf_ptr_dec which increment or decrement the buffer read pointer i e adjusting latency buf_rst which resets the read and write pointers and buf master which indicates to the channel if it is the master link If the channel is the master then the buffer read pointer is set to 50 rather than O upon buf_rst This guarantees that the read pointer from all links other than the master link will need to be incremented rather than decremented to achieve alignment The write pointer is set to 110 i e far end of the buffer to ensure no overlap with read pointer after reset Hence after reset the buffer data is valid i e no read write pointer clash but the links are not aligned and the latency is large Upon receipt of the align_marker signal from the master link i e align_master
61. wnload ds jsp s 523 Micron Technology Inc Micron Serial NOR Flash Memory 3V Multiple I O 4KB Sector Erase January 2012 http www micron com parts nor flash serial nor flash media Documents Products Data 20Sheet NOR 20Flash Serial 20NOR N25Q 59 89n25q 256mb 3v 65nm ashx Linear Technology Corp LTC2990 Quad 12C Voltage Current and Temperature Monitor December 2011 http cds linear com docs Datasheet 2990fc pdf Weidberg T Electrical Tapes Optical Links Quality Workshop 2011 CERN 4 November 2011 https indico cern ch getFile py access contribld 10 amp sessionld 9 amp resid 1 amp materialld slid es amp confld 148944 Sensirion AG SHT21 Humidity and Temperature Sensor IC May 2010 http www sensirion com en pdf product_information Datasheet humidity sensor SHT21 pdf Schroff 20849 132 AdvancedMC module mechanism pull handle mechanism PIGMG AMC O R2 0RC1 2 J Audet et al IPMItool open source command line interface to IPMI enabled devices sourceforge net projects ipmitool October 2013 N A T Europe NATview Visualization tool for any MicroTCA system http www nateurope com products NATview html December 2013 C Minyard IPMI A Gentle Introduction with OpenIPMI http openipmi sourceforge net February 2006 PICMG uTCA Micro Telecommunications Computing Architecture Short Form Specification September 2006 53 List of Figu
62. xtraction handle kits by Schroff part number 20849 132 33 The panels provided with standard MP7 cards will be laser etched with the decal shown in Figure 18 Figure 18 The front panel design provided with a standard MP7 card A prototype front panel is shown in Figure 19 Figure 19 Prototype laser etched front panel 44 Photographs of the MP7 RO prototype Figure 20 Two photographs of the first prototype Imperial MP7 processor card The optical ribbons used are samples with an additional prizm connector that is not required in the final design The Virtex 7 FPGA is located under the blue heat sink 45 Photographs of the MP7 R1 Won je hA qi d APM i LUUD 1 Fus wie U oo sim Figure 21 Two photographs of the Imperial MP7 R1 processor card The Virtex 7 FPGA is located under the custom designed black heat sink 46 Parts Summary Part PCB material MP7 RO 8 MP7 R1 PCB material MP7 XE Optics Transmitter Optics Receiver General purpose I O Top surface front panel MMC Controller CPLD QDR SRAM Clocking Frequency Synthesiser Jitter Attenuator Clocking 4 4Cross point switch Clocking 1 4 Fanout Buffers MP7 RO amp MP7 R1 Clocking 1 6 Fanout Buffers MP7 XE Front panel clock inputs Power General 3 3V 2 5V Power General 1 8V 1 5V Power General 1 0V MP7 RO Power General 1 0V MP7 R

User guide for the Master Processor, Virtex-7

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