RaggedStone2 User Manual Issue – 1.02
Contents
1. J7 J10 PINI DGND PINI 3 3V PIN2 L20 PIN2 M20 PIN3 L22 PIN3 N16 PIN4 K22 PIN4 N19 PINS K21 PINS P20 The connections to J7 are LVDS pairs connecting to Global Clock inputs on the FPGA On J10 connections to N19 and P20 are an LVDS pair and Global Clock inputs The Connections to M20 and N16 are to general purpose IO pins The horizontal distance between J7 and J10 is 0 6inch 15 25mm 2 7 SEGMENT DISPLAY HEADER The two 8 pin headers which form the 7 segment display holder U6 have 14 connections to the FPGA Of these 14 connections 8 have series 470ohm resistors which are normally used as current limiting resistors for the 7 segment display This should be taken into account if this header is used for other purposes The connections between U6 and the FPGA are shown below PIN16 PIN15 PIN 14 PIN13 PIN12 PIN11 PIN10 PIN9 N20 P19 R19 R20 T20 V20 N C N C PIN1 PIN2 PINS PIN4 PIN5 PIN6 PIN7 PIN8 N22 T22 V19 P16 U20 U19 V21 AB19 It should be noted that AB19 is on BANK2 All the other connections are on BANKI The vertical distance between the upper and lower pins of U6 is 0 4inch 10 2mm Enterpoint Ltd RaggedStone2 Manual Issue 1 02 29 06 2010 15 U6 PINI PIN16 PINI PIN1 PIN1 d z HEADER TOP 99 J10 PINS Sis ia i Mar PINS 3 ii 4 PUACCYC Quv 0 Figure 8 Raggedstone2 SIL Header2. point RaggedStone2 User Manual Issue 1 02 Enterpoint Ltd RaggedStone2 Manual Issue 1 02 29 06 2010 Kit Contents You should receive the following items with you Raggedstone2 development kit 1 Raggedstone2 Board 2 4 Digit 7 Segment LED display usually fitted 3 PCI mounting bracket usually fitted 3 Prog parallel port or Prog3 USB programming cable Enterpoint Ltd RaggedStone2 Manual Issue 1 02 29 06 2010 Contents Kit Contents Foreword Trademarks INTRODUCTION RAGGEDSTONE2 BOARD GETTING STARTED SELECTING THE FPGA BANKVOLTAGES DIU By AIN PROGRAMMING RAGGEDSTONE2 RAGGEDSTONE FEATURES 11 POWER INPUTS AND PICKUPS 11 POWER REGULATORS 12 DIL HEADERS 13 SIL HEADERS 15 CLOCK MODULE HEADER 15 7 SEGMENT DISPLAY HEADER 15 FPGA 17 OSCILLATOR 17 LEDS 17 USB 18 SWITCHES 19 BATTERY BACKUP 19 DDR3 MEMORY 20 SATA 21 PCIE 24 SERIAL EEPROM 22 SPI FLASH 22 TEMPERATURE SENSOR 23 MECHANICAL 24 Medical and Safety Critical Use 25 Warranty 25 Support 25 Enterpoint Ltd RaggedStone2 Manual Issue 1 02 29 06 2010 Foreword PLEASE READ THIS ENTIRE MANUAL BEFORE PLUGGING IN OR POWERING UP YOUR RAGGEDSTONE2 BOARD P
3. J8 PIN 2 D9 J9 PIN 2 J14 PIN 2 C15 J8 PIN 3 C9 J9 PIN 3 C13 J14 PIN 3 D15 J8 PIN5 AS J9 PIN 5 A14 J14 PIN 5 A16 J8 PIN 6 B8 J9 PIN 6 B14 J14 PIN 6 B16 CLOCK Cll CLOCK Al2 CLOCK E12 CLOCK D11 CLOCK B12 CLOCK F12 SATA2 SATA1 CONNECTOR SATA3 CONNECTOR CONNECTOR dii I nm E 20000009 P in oo Mi SAPEDSTONEZ E SATA CLOCK LEE DEVICE Has A o PUACCY nl ce C DDR3 Enterpoint Ltd RaggedStone2 Manual Issue 1 02 29 06 2010 www orterpotri oo um c 2010 Enterpoint Lis OO 21 PCIe Edge Connector The Raggedstone2 has a x1 PCIe Interface The pin out of the Spartan 6 FPGA has been chosen such that the PCI interface follows the pinout for the Xilinx M Spartan 6 hard core for PCIe which can be generated automatically by the Xilinx Core Generator The connections between the PCIe connector and the FPGA are shown below SIGNAL PCIE CONNECTOR FPGA PIN NAME PIN PCIE_CLK_P A13 A10 PCIE_CLK_N A14 B10 PCIE_TX_P A16 B6 PCIE TX N A17 A6 PCIE RX P Bl4 D7 PCIE_RX_N B15 C7 PCIE_PRESENT 1 Al P5 PCIE_PRESENT 2 B17 P5 Serial EEPROM Raggedstone2 has a 16K Two Wire Atmel AT24C16BY6 EEPROM device which uses a simple Parallel address and single serial data line and clock There is also a write protect line which can be used to electronically safeguard the information contained in the device The EEPROM has 3 address lines which are permanently connected to
4. 6 and choose Add SPI BPI Flash Navigate to your programming file mcs and click OPEN Use the next dialogue box to select SPI flash and M25P128 Data width should be set to 1 The flash memory should appear as shown below TDI xcBslxd5t bypass TDO Right click on the icon representing the flash memory and choose Program to load your program into the device It is recommended that options to Verify and Erase before programming are chosen Otherwise all defaults can be accepted The programming operation will take some time This time depends on which programming cable you use and it s setup but typically expect this to take 3 to 4 minutes Field Updating the SPI flash via USB Serial Interface or Other Interface It is possible to update the Raggedstone2 via it s FT232 USB or other interface if a basic build supporting a field updating mode has been previously loaded into the Raggedstone2 It is also possible to Multiboot the Spartan 6 FPGA with bitstream loaded dependent on a switch or other stimulus These advanced topics are not covered in this manual and are only mentioned here for completeness We are hoping to provide further information on this in our TechiTips section of our Engineering Website Bitstream Encryption Raggedstone2 can support bitstream encryption on versions of the board with XC6SLX75T XC6SLX100T or XC6SLX150T FPGAs fitted XC6SLX45T versions of the product do not support bitstream
5. DGND 3 3V K19 AA16 DGND 3 3V AA14 F20 DGND 3 3V K18 AB16 DGND 3 3V AB14 F18 DGND 3 3V J16 R13 DGND 3 3V Y13 F19 DGND 3 3V J17 T14 DGND 3 3V AB13 E20 DGND 3 3V H18 U14 DGND 3 3V W12 E22 DGND 3 3V H19 U13 DGND 3 3V Y12 C20 DGND 3 3V F21 AA12 DGND 3 3V Y11 C22 DGND 3 3V F22 AB12 DGND 3 3V AB11 B18 DGND 3 3V D18 T12 DGND 3 3V Y9 A18 DGND 3 3V D19 U12 DGND 3 3V AB9 D17 DGND 3 3V C19 AA10 DGND 3 3V AA8 C18 DGND 3 3V A19 AB10 DGND 3 3V AB8 G16 DGND 3 3V B20 W9 DGND 3 3V T7 F17 DGND 3 3V A20 Y8 DGND 3 3V U6 E16 DGND 3 3V C17 Y7 DGND 3 3V Y5 F16 DGND 3 3V A17 AB7 DGND 3 3V ABS H14 DGND 3 3V F14 AA6 DGND 3 3V AA4 G15 DGND 3 3V F15 AB6 DGND 3 3V AB4 H13 DGND 3 3V H10 W17 DGND 3 3V Y16 G13 DGND 3 3V H11 Y18 DGND 3 3V W15 H12 DGND 3 3V F7 W14 DGND 3 3V V13 G11 DGND 3 3V F8 Y14 DGND 3 3V W13 G9 DGND 3 3V D4 T10 DGND 3 3V VII F10 DGND 3 3V D5 U10 DGND 3 3V W11 G8 DGND 3 3V C4 W10 DGND 3 3V U9 F9 DGND 3 3V A4 Y10 DGND 3 3V V9 E5 DGND 3 3V B3 H9 DGND 3 3V T8 E6 DGND 3 3V A3 H8 DGND 3 3V U8 C5 DGND 3 3V B2 V7 DGND 3 3V W6 A5 DGND 3 3V A2 W8 DGND 3 3V Y6 The signals on the DIL headers are arranged in LVDS pairs and routed such that the trace lengths approximately match and skew is minimised within pair Adjacent LVDS P and LVDS N fo
6. o ET ce Fed www ontarpoiri c0 va c 2010 Ertorpoiri Li 0 75V REGULATOR Figure 6 Raggedstone2 POWER REGULATION Enterpoint Ltd RaggedStone2 Manual Issue 1 02 29 06 2010 12 DIL Headers The DIL Headers provide a simple mechanical and electrical interface for add on modules The connectors on this header are on a 0 linch 2 54mm pitch and allow either custom modules or strip board to be fitted The headers have a row of permanent positive power sockets 3 3V to the left of JL2 and JR2 and a row of permanent GND DGND 0V sockets to the right of the JL1 and JR1 Voltages outside the range OV to 3 3V must not be applied to the DIL headers The Spartan 6 has an absolute maximum IO input voltage of 4 1V The connections between the DIL the headers and the FPGA are shown below LEFT DIL HEADER RIGHT DIL HEADER JL1 JL2 JRI JR2 K17 DGND 3 3V M17 AA18 DGND 3 3V Y17 L17 DGND 3 3V M18 AB18 DGND 3 3V AB17 G20 DGND 3 3V M21 V17 DGND 3 3V Y15 G22 DGND 3 3V M22 W18 DGND 3 3V AB15 G19
7. encryption Enterpoint Ltd RaggedStone2 Manual Issue 1 02 29 06 2010 10 Raggedstone Features Power Inputs and Pick ups Raggedstone2 can be powered either from the PCIe edge connector or from a single 5V power supply input via the 2 1mmDC jack socket The 5V DC jack input to Raggedstone2 is initially regulated down to 3 3V by an AP1184 regulator The resultant 3 3V is fed to power selection header J4 located between the USB connector and 5V Jack Fitting a jumper between Pinl and Pin2 selects the 5V DC Jack feed derived 3 3V Fitting the jumper between Pins 2 and 3 selects the PCIe 3 3V input The 3 3V output of J4 then acts as the main 3 3V for the board and also the main power feed to the regulators for 1 2V 1 5V and 2 5V A pair of low current control voltage rails are also produced by diode ORs of 12V PCIe and 5V Jack for use at the main regulators On Raggedstone2 there are 2 sets of 34 header pins with 3 3V and DGND OV available on each side of the board for users to access power for their own add on circuitry These pins are arranged on a 0 linch grid to enable users to plug in their own strip board designs or even custom add on PCBs 2 1MM JACK SOCKET 34 34 0V SOCKETS 3 3V SOCKETS 34 34 OV SOCKETS 3 3V SOCKETS ilit P 14944 i n a E 111 odd t nm 00 i ees s 2 1 2V TEST POINT 00000000 00000000000 929999999000 CT pal HEADER TOP ir 3 ti LYCEE CE WWW Le sar po
8. to use this service Other specialised warranty programs can be offered to users of multiple Enterpoint products Please contact sales on boardsales enterpoint co uk if you are interested in these types of warranty Support Enterpoint offers support during normal United Kingdom working hours 9 00am to 5 00pm Please examine our Raggedstone2 FAQ web page and the contents of this manual before raising a support query We can be contacted as follows Telephone 44 0 121 288 3945 Email support enterpoint co uk Enterpoint Ltd RaggedStone2 Manual Issue 1 02 29 06 2010
9. DGND It can run at speeds up to 400 kHz This serial memory has 2048 words of 8 bits and employs a byte or page programming system The connections between the EEPROM and the FPGA are shown below EEPROM SIGNAL FPGA PIN SDA P22 SCL P21 WP R22 SPI Flash Memory The M25P128 SPI flash memory device configures the FPGA when it is powered providing a suitable bitstream is programmed into the device The M25P128 has a capacity of 128Mbits with a single configuration bitstream for Raggedstone2 taking between 3 6Mbits LX16 and 11 4Mbits LX45 Any remaining space can be used for alternative configurations or code and data storage The HOLD pin of this memory device is permanently connected to 3 3V After configuration the SPI Flash can be accessed via the following pins of the FPGA M25P128 FUNCTION FPGA PIN CCLK Y20 MOSI AB20 WRITE D3 DIN AA20 CSO_B AA3 Temperature Sensor Enterpoint Ltd RaggedStone2 Manual Issue 1 02 29 06 2010 There is a temperature sensor type LM75C on Raggedstone2 which has a 2 wire serial interface and an output which behaves as an over temperature warning The connections to the FPGA are shown below TEMPERATURE SENSOR PCIE CONNECTOR OVER TEMPERATURE V22 i m in aber sosie o 4i 1 3 1357 66000006 ul 00000000 ay Te pow nine SPI FLASH s ND s M 9 Succ o s EEPROM Enterpoint Lt
10. LEASE TAKE SPECIAL NOTE OF THE WARNINGS WITHIN THIS MANUAL Trademarks Spartan ISE EDK Webpack and Xilinx are the registered trademarks of Xilinx Inc San Jose California US Raggedstone2 is a trademark of Enterpoint Ltd i TIT j i 59946 7 sasabit jeu 9 dipl 11927 133357 00000006 dei i 9 mue a 90000000 oe 4 FVACCY C 94V 0 CE E o www enterpolnt co uk c 2010 Enterpoint Lic Figure 1 Raggedstone2 Board Enterpoint Ltd RaggedStone2 Manual Issue 1 02 29 06 2010 Introduction Welcome to your Raggedstone2 board Raggedstone2 is X1 PCIe development board based on a single Xilinx Spartan 6 FPGA This product has been designed as a migration product for users of our highly popular Raggedstonel board with a high degree of feature and mechanical compatibility The aim of this manual is to assist in using the main features of Raggedstone2 It is aimed as a basic manual and may not cover in sufficient depth some of the advanced features of this product Our support team can be contacted on support enterpoint co uk for information beyond the scope of this manual Raggedstone2 is initially offered in a single variant based on an XC6SLX45T 4FGG484C Spartan 6 We will offer options subject to demand including bigger faster and industrial grade FPGAs Please ask our board sales team boardsales enterpoint co uk to quote for any specific requirements As with all of our products we
11. ace ve CE x www onterpolnt oo va 2010 Enterpoint Lic Figure 4a Pin allocation of J6 J12 is identical Enterpoint Ltd RaggedStone2 Manual Issue 1 02 29 06 2010 Programming Raggedstone2 The programming of the FPGA and SPI Flash on Raggedstone2 is achieved using a JTAG connection Principally it is anticipated that a JTAG connection will be used in conjunction with Xilinx SETM software although other alternatives do exist Our Prog2 parallel port or Prog3 USB programming cables are normally supplied with this board unless your ware buying OEM versions where cables are not supplied There is a single JTAG chain on Raggedstone2 The JTAG chain allows the programming of the Spartan 6 and the SPI Flash device The JTAG connector has a layout as follows Top edge of board GND GND GND GND GND GND GND NC NC TDI Using the ISE IMPACT tool the boundary scan the JTAG chain appears like this ISPIJBPI xcBslx45t bypass TDO Programming the FPGA directly Direct JTAG programming of the Spartan 6 FPGA is volatile and the FPGA will lose its configuration every time the board power is cycled For sustained use of an FPGA design programming the design into the Flash memory is recommended see 2 and 3 below Bit files are usually used for direct JTAG programming and these are generated by the Xilinx ISE tool chain This powerful set of tools is available from Xilinx The fr
12. can offer OEM customers semi custom or full custom derivative designs based on this product Please ask our board sales team boardsales enterpoint co uk to quote for custom derivative products In addition Raggedstone2 is supported by our wide range of add on modules Some examples of these include ADC 7927 MODULE LED DOT MATRIX MODULE BUTTONS SWITCHES SATA MEMORY MODULE RS232 AND RS485 HEADER MODULES DP83816 ETHERNET MODULE SD CARD MODULE DDR2 MODULE IDE 5V TOLERANT CPLD MODULE USB MODULE D A CONVERTER MODULE ADV70202 MODULE We can also offer custom DIL Header modules should you require a function not covered by our current range of modules Typical turn around for this service is 4 8 weeks depending upon quantity ordered and availability of components Enterpoint Ltd RaggedStone2 Manual Issue 1 02 29 06 2010 Raggedstone2 Main Features USB 3 SATA JTAG INTERFACE CONNECTORS CONNECTOR 7 SEGMENT DISPLAY 4USERLEDS BATTERY BACKUP I H I 1119 3 gt Oa he w ser 100000000 5 128m FLASH imu AGGEDSTONE2 MEMORY ns t 10 En HEADERS 2 PUSH BUTTON SWITCHES DUCTS gw e CE ww www otter pom CO uk c 2010 Enterpoint Lit OO FPGA PCIE CONNECTOR USER DEFINED DDR3 OSCILLATOR Figure 2 Raggedstone2 MAIN FEATURES Getting Started Your Raggedstone2 will be supplied with a default setting of jumpers fitted 1 Please read the entire user manual 2 Fit the LED 7 segment display into its c
13. d RaggedStone2 Manual Issue 1 02 29 06 2010 22 23 Mechanical information 600000 000000 oo eo eo 00 oo 0 ol eo 9 9 LEE 0 9 eo CRE eo eo 00 oo 00 oa 00 e ol eo LESE eo co 6 ol 6 ol cel 00 Tng 17 OGND ON All dimensions are shown in millimetres If you need any further mechanical information please contact us Contact information is shown on page 26 of this manual Enterpoint Ltd RaggedStone2 Manual Issue 1 02 29 06 2010 24 Medical and Safety Critical Use Raggedstone2 boards are not authorised for the use in or use in the design of medical or other safety critical systems without the express written person of the Board of Enterpoint If such use is allowed the said use will be entirely the responsibility of the user Enterpoint Ltd will accepts no liability for any failure or defect of the Raggedstone2 board or its design when it is used in any medical or safety critical application Warranty Raggedstone2 comes with a 90 return to base warranty Do not attempt to solder connections to the Raggedstone2 Enterpoint reserves the right not honour a warranty if the failure is due to soldering or other maltreatment of the Raggedstone2 board Outside warranty Enterpoint offers a fixed price repair or replacement service We reserve the right not to offer this service where a Raggedstone2 has been maltreated or otherwise deliberately damaged Please contact support if need
14. ee ISE Webpack version will support XC6SLXAST and XC6SLX75T based versions of Raggedstone2 Versions of Raggedstone2 using XC6SLX100 and XC6SLX150 will need a paid license version of ISE to build and program the internal FPGA design Once you have built the design in ISE click on program device to open the Impact part of the ISETM toolset Once you have selected boundary scan mode and Initialised the chain you should see FPGA portrayed as shown above Right click the icon representing the Spartan 6 FPGA and choose Assign New Configuration File Navigate to your bit file and choose OPEN The next dialogue box will offer to add a flash memory and you should decline Right click the icon representing the Spartan 6 FPGA and choose Program On the next dialogue box ensure that the Verify box is not checked If it is you should uncheck it failure to do this will result in error messages being displayed Click OK The Spartan 6 will program This process is very quick and is typically a few seconds Enterpoint Ltd RaggedStone2 Manual Issue 1 02 29 06 2010 Programming the SPI flash memory using Boundary Scan Once the SPI Flash memory has been programmed the Spartan 6 device will automatically load from the Flash memory at power up Generation of suitable Flash memory files mcs can be achieved using ISE IMPACT s Prom File Formatter mode Right click on the icon representing the Spartan
15. id o A a 313 a wow artarpolet coi OOs 99 e 2010 Emarpont ii 09 OSCILLATOR SOCKET Figure 8 Raggedstone2 FPGA Oscillator socket and LEDs Enterpoint Ltd RaggedStone2 Manual Issue 1 02 29 06 2010 17 USB USB SOCKET MINI B FTDI DEVICE 44944 unu e Jih un nm 50000006 od ae te po at 100000000 i o o lia RAGGEDSTONE2 gt eo 16H 2 00 00 a PLACCYC Gr CE wud www orterpoint co uk c 2010 Emterpoint Lic OO The USB interface on the Raggedstone2 is achieved using an FT232R USB to serial UART interface The datasheet and drivers for this device are available from http www ftdichip com When appropriate drivers are installed the Raggedstone2 USB port should be detected as a serial port Alternative data optimised drivers are also available from FTDI The FT232R is connected to the Spartan 6 and provided a simple UART or other converter is implemented then the data sent over the USB serial port can be used either as control and or data information This allows a host computer to act in a number of ways including system control and data storage functions The connections between the USB device and the FPGA are shown below Enterpoint Ltd RaggedStone2 Manual Issue 1 02 29 06 2010 18 Push Button Switches Raggedstone2 has two tactile push button switches To u
16. ject to limitations of the memory controller The DDR3 has 12 address lines and 16 data lines to address all the available memory which can be accessed at speeds of 1 87ns More details of the DDR3 can be found in http download micron com pdf datasheets dram ddr3 1Gb_DDR3_SDRAM pdf The DDR3 site has the following connections to the FPGA DDR3 FUNCTION mes PIN DDR3 FUNCTION FPGA PIN DDR_DQ3 PI KI DDRDQ4 B k K DDRDO l1 m X DRDQ6 O Mo H3 J DDRDQ M k M3 DDR DQ8S T l4 j DDRDQ TI X K6 DDRDOI B G o pporpgli TT Gio DDRDO2 y A4 DRD WI E DDRDQM Y2 FI JDDRDOQS5S Y 376 DDRIDM NM H5 pbRIDOSS N O DI DDRLDOSN MN J 4 B DDRUDM od PB n p s PS PS gori DDR UDOSN V1 sk O _ 6 Mu D a ES DDR_DQO 17 DDR DQI RI i NENNEN DDR_DQ2 P2 KA The signals shown shaded in yellow are terminated using suitable arrangements of resistors Enterpoint Ltd RaggedStone2 Manual Issue 1 02 29 06 2010 SATA 20 Raggedstone2 has 3 SATA connectors which are connected to the MGT interface of the Spartan6 An ICS844071 is used to generate the SATA Clock The connections between the SATA Clock the SATA connectors and the FPGA are shown below omitting series capacitors
17. lint co uk c 20111 Emtarpoint Lic OO PCIE CONNECTOR 2 5V TESTPOINT 4 54 TESTPOINT Figure 3 Raggedstone2 Power Supply Features WARNING THE REGULATORS AND SURROUNDING PCB MAY BECOME HOT WHILST IN NORMAL OPERATION Enterpoint Ltd RaggedStone2 Manual Issue 1 02 29 06 2010 11 Power Regulators Raggedstone2 has a power backbone based on four AP1184 linear regulators These regulators are each capable of delivering 4 amps The structure of the regulator circuit limits the maximum power drawn from the supply and minimises losses by regulating the 5V or 12v PCIe supply to 3 3V which is then used to supply the 1 2V 1 5V and 2 5V regulators The maximum current that can be delivered into Raggedstone2 has also been limited by a resettable fuse to a maximum current to 1 1A at 3 3V through to the board This limit should be considered when adding user circuitry onto the header pins If more current is drawn the resettable fuse will cut the supply to the board if this happens the power supply must be switched off and time given for the fuse to reset which occurs when the fuse has cooled and reconnected its internal contacts This typically takes 1 2 seconds A fifth regulator LP2996 provides a 0 75V reference for the DDR3 memory device 3 3V REGULATOR i m i mI Hut dadi ii o 4111 un nm LL VF wt 000000 Ta a pdt eea L D MET 1 2V REGULATOR x Too an i 1 5V REGULATOR 2 5V REGULATO
18. onnector if needed 3 Check the bank voltage jumper selections are set as required by your application 4 Check that power selection header J4 has a jumper fitted as appropriate for PC hosting or stand alone bench operation 5 Fit an oscillator into the DIL socket if needed 6 Either plug the Raggedstone2 board into a un poweredPCle host connector or alternatively plug in a SV power supply into the 2 1mm Jack socket 7 Switch on you host system with PCIe connector or switch on your SV power supply Enterpoint Ltd RaggedStone2 Manual Issue 1 02 29 06 2010 Selecting the FPGA Bank voltages The main User I O pins of the Spartan M_6 on Raggedstone2 are divided into 2 banks The left hand side header pins are routed to BANKI of the FPGA the Right hand side headers are routed to BANK2 The IO voltages are usually set to either 3 3V or 2 5V using jumpers on the 6 pin headers J6 for BANKI and J12 for BANK Alternatively a user generated Bank IO voltage could be introduced on pin 2 of J6 or J12 There is a DGND OV reference on pin 5 of J6 and J12 for this purpose If you choose to use this option please refer to the Spartan 6 user guide from www Xilinx com to check the allowed IO voltage range for the FPGA J6 000000 0000 o 899999999992999999992 o o o o o 1 in 099090 J12 i a 49984 uit 444 v 2 4i Hg nn 66000006 d aly 00 i 00000000 tz RAGGEDSTONE2 195 ME EB o Pi
19. rm the matched pair at the DIL Header and the Spartan 6 FPGA For example K17 and L17 form one pair All LVDS pairs can be used as general inputs outputs from the Spartan6 Enterpoint Ltd RaggedStone2 Manual Issue 1 02 29 06 2010 JL1 JL2 JR1 JR2 di 1 66000006 i E HA PACTS ml CE Seri s www enterpoint co wi c 2010 Enterpont Lx Figure 7 Raggedstone2 DIL Headers Enterpoint Ltd RaggedStone2 Manual Issue 1 02 29 06 2010 13 PIN1 PIN34 14 SIL Headers There are 4 SIP headers on Raggedstone2 They are arranged as 2 pairs J7 and J10 form the Clock Module header and have 5 pins each The two 8 pin SIL headers are usually used to support the LTC C4627JR 4 digit 7 segment display U6 however the 7 segment display can be removed to make these pins available to the user Voltages outside the range OV to 3 3V must not be applied to the SIL headers The Spartan 6 has a maximum IO input voltage of 4 1V 1 CLOCKMODULE HEADER These header pins are designed to allow the Enterpoint Clock module to be fitted This module is fitted with an ICS8442 700MHZ Crystal Oscillator To Differential Lvds Frequency Synthesizer device If this module is not fitted the header pins are available to the user J10 has a permanent positive power pin 3V3 at the top position J7 has a Gnd DGND 0V connection at the top position The connections to the FPGA BANK1 are shown below
20. s Enterpoint Ltd RaggedStone2 Manual Issue 1 02 29 06 2010 16 FPGA Raggedstone2 supports Spartan M_6 devices in the FGG484 package Raggedstone2 is normally available with the XC6SLX45T 4FGG484C fitted which has 43 661 logic cells Should you have an application that needs bigger devices industrial or faster speed grades please contact sales for a quote at boardsales enterpoint co uk Oscillator The oscillator socket on Raggedstone2 supports 3 3V 8 pin DIL outline oscillator crystals The on board clock signal is routed directly through to the FPGA pin M19 which is a Global Clock input to the FPGA The Spartan 6 has Digital Clock Multipliers DCMs to produce multiples divisions and phases of clock signals Please consult the Spartan 6 datasheet available from the Xilinx website at http www Xilinx com if multiple clock signals are required LEDs On Raggedstone2 there are 5 LEDS LEDI is situated on the top left corner of the board and isindicates the presence of the 3 3V power rail It is not available for other uses LEDs 2 to 5 which are situated the top of the board between the rightmost SATA connectors and the Battery holder are user LEDs and are connected to the FPGA as indicated below LED2 LED3 LED4 LEDS W22 W20 Y22 Y21 LEDS 2 TO 5 LED1 LEDS 44944 mM dana 06 du HUT Hum 66000006 a 00 Ta pom m mm 00000000 ORE n 00 s tim BAGAEDSTONE2 3 r
21. se these switches it is necessary to set the IO pins connected to the switches to have a pull up resistor setting in the constraints file Any switch pressed or made will then give a LOW signal at the FPGA otherwise a HIGH is seen The two push button switches are connected to the following IO pins SWITCH 1 SWITCH 2 R7 W4 Battery Backup The Raggedstone2 has a battery holder which is available to provide battery backup to the FPGA It is connected to the SpartanM 6 on pin T16 The battery holder accepts a 3V Lithium battery size CR1220 or equivalent BATTERY HOLDER POSITION us LUN 2 un nm 06000000 a dad eo i n p r00000000 os Rf _ oo majaa HEADER TOP as se 00 33 23 007 Sw2 Ji EE Sw Aare o o 2 c 2010 Erterpoint Lx Enterpoint Ltd RaggedStone2 Manual Issue 1 02 29 06 2010 19 DDR3 Raggedstone2 has a 1GBIT DDR3 Micron MT41J64M16LA device as standard This device is organised as 8 Meg x 16 x 8 banks This device is supported by the hard core memory controller that is in the Spartan 6 FPGA To add this core to your design the COREGEN tool part of the ISE suite will generate implementation templates in VHDL or Verilog for the configuration that you want to use More details on the memory controller can be found in the user guide http www Xilinx com support documentation user_guides ug388 pdf For OEM applications we can fit bigger DDR3 parts sub
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