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ModelSim User's Manual - Electronics and Computer Science

1. OEM versions of ModelSim have limited Dataflow functionality Many of the features described below will operate differently The window will show only one process and its attached signals or one signal and its attached processes as displayed in Figure 2 9 Figure 2 9 Dataflow Window File Edit View Navigate Trace Tools Window Si Rab DBIA ee gt eK Dea amp Q iD m INITIAL 58 addr_r data_r wee 4 L The Dataflow window displays e processes ModelSim User s Manual v6 29 49 February 2007 Simulator Windows Dataflow Window e signals nets and registers The window has built in mappings for all Verilog primitive gates i e AND OR PMOS NMOS etc For components other than Verilog primitives you can define a mapping between processes and built in symbols See Symbol Mapping for details Dataflow Window Toolbar The buttons on the Dataflow window toolbar are described below Table 2 8 Dataflow Window Toolbar Button Menu equivalent Print print the current view of the Dataflow File Print Windows window File Print Postscript UNIX Select mode set left mouse button to select View Select mode and middle mouse button to zoom mode Zoom mode set left mouse button to zoom View Zoom Ey mode and middle mouse button to pan mode Pan mode set left mouse button to pan mo
2. ModelSim User s Manual v6 2g 285 February 2007 Value Change Dump VCD Files Capturing Port Driver Data 1 0 O O 0 0 O 0 amp 0 0 1200 Sdumpall 1 os 0 0 amp 0 0 0 O O 0 Send Capturing Port Driver Data Some ASIC vendors toolkits read a VCD file format that provides details on port drivers This information can be used for example to drive a tester See the ASIC vendor s documentation for toolkit specific information In ModelSim use the vcd dumpports command to create a VCD file that captures port driver data Each time an external or internal port driver changes values a new value change is recorded in the VCD file with the following format p state 0 strength 1 strength identifier code Driver States The driver states are recorded as TSSI states if the direction is known as detailed in this table Table 12 4 Driver States Input testfixture Output dut D low L low U high H high N unknown X unknown Z tri state T tri state 286 ModelSim User s Manual v6 2g February 2007 Value Change Dump VCD Files Capturing Port Driver Data Table 12 4 Driver States cont Input testfixture Output dut d low two or more 1 low two or more drivers active drivers active u high twoormore h high two or drivers active more drivers active If the direction is unknown the
3. 0 0 0 e 271 Table 11 15 Matching SDF NOCHANGE to Verilog 0 0 0 eee eee eee 271 Table 11 16 Matching Verilog Timing Checks to SDF SETUP 271 Table 11 17 SDF Data May Be More Accurate Than Model 4 272 Table 11 18 Matching Explicit Verilog Edge Transitions to Verilog 272 Table 11 19 SDF Timing Check Conditions 0 00 0 cece eee eee eee 272 Table 11 20 SDF Path Delay Conditions 22 noedesete kr RR ES ph d Rh Rhen 273 Table 11 21 Disabling Timing Checks eseeeeeee eee 274 Table 12 1 VCD Commands and SystemTasks 0 0 0 cece eee eee 281 Table 12 2 VCD Dumpport Commands and System Tasks 00 281 Table 12 3 VCD Commands and System Tasks for Multiple VCD Files 282 abled 2 DIVer SidlbS 244202 dau od eee eee dee Pee beter P erpepipN dee fads 286 Table 12 5 State When Direction is Unknown 0 0 cee eee eee ee 287 Table 12 6 Driver Strength 22222200i202 mE ERES RR ierat dap R RR RE E S 287 Table 12 7 Values for file format Argument seseeeeee e 289 Table 17 8 Sample Driver Data 52 29 ep REX se ode eas I CER REA NERA Dd ERE A ADU 290 Table 13 1 4 2229 EEurLrRa eo eee as Lele seem eed eet s adquiri eed ele ee 294 Table 13 2 Tcl Backslash Sequences 0 0 eee eee eee 296 Table 13 3 Tcl List Commands 2 25 0 in 5 aon bei Rd e EE ERR IR EX EE RP ES 300 Table 13 4
4. eleleeeeeeees 102 Figure 4 3 Edit Library Mapping Dialog 0 0 eee eee BRA 103 Figure 4 4 Import Library Wizard 2224s ua e ER apace eh bee urease nda XR ERG 108 Figure 5 1 VHDL Delta Delay Process leleeeeeeee I 116 Figure 6 1 Selecting Use System Verilog Compile Option 00 141 Figure 7 1 Displaying Two Datasets in the Wave Window leleleeeeeese 176 Figure 7 2 Open Dataset Dialog BOX osos Rr RR RP SR RAP EROR Pe RES 178 Figure 7 3 Structure Tabs in Workspace Pane 0 0 0 cee esee 179 Figure 7 4 The Dataset Browser s lt ss cider sade aces de eiSeeenes sderavecsdees ad 180 Figure 7 5 Dataset Snapshot Dialog i2 dues eer tee sealers passe sere deals Saks 182 Figure 7 6 Virtual Objects Indicated by Orange Diamond 04 184 Figure 8 1 Undocking the Wave Window eeeeeeeeeee nee 188 Figure 8 2 Docking the Wave Window 0 0 e eee cece eee eens 189 Figure 8 3 Panes in the Wave Window 0 0 cece eee eee teens 190 Figure 8 4 Tabular Format of the List Window 0 0 cece eee eee 19 Figure 8 5 Cursor Names Values and Time Measurements 00 5 193 Figure 8 6 Time Markers in the List Window 00 ee eee eee eee 195 Figure 8 7 Bookmark Properties Dialog 2 0 0 0 0 eee eee eee 198 Figure 8 8 Find Signals by Name or Value 0 0 e eee eee ee eee 199 Figure
5. end endmodule ModelSim User s Manual v6 2g 259 February 2007 Signal Spy signal release signal release The signal_release system task releases any force that was applied to an existing VHDL signal or Verilog register net called the dest object This allows you to release signals registers or nets at any level of the design hierarchy from within a Verilog module e g a testbench A S signal release works the same as the noforce command signal release can be called concurrently or sequentially in a process Syntax signal release dest object lt verbose gt Returns Nothing Arguments dest object Required string A full hierarchical path or relative downward path with reference to the calling block to an existing VHDL signal or Verilog register net Use the path separator to which your simulation is set i e or A full hierarchical path must begin with a or The path must be contained within double quotes verbose Optional integer Possible values are 0 or 1 Specifies whether you want a message reported in the Transcript stating that the signal is being released and the time of the release Default is 0 no message Related tasks init signal driver Sinit signal spy signal force Limitations e You cannot release a bit or slice of a register you can release only the entire register signal release Example This example releases any forces on the signals
6. design dut q d clk endmodule Contents of design v module design output bit q input bit d clk timeunit ins timeprecision 10ps always posedge clk q d endmodule Compile the design incrementally as follows ModelSim gt vlog testbench sv Top level modules testbench ModelSim vlog sv testl v Top level modules dut Note that the compiler lists each module as a top level module although ultimately only testbench is a top level module If a module is not referenced by another module compiled in the same invocation of the compiler then it is listed as a top level module This is just an informative message and can be ignored during incremental compilation 142 ModelSim User s Manual v6 2g February 2007 Verilog and SystemVerilog Simulation Compiling Verilog Files The message is more useful when you compile an entire design in one invocation of the compiler and need to know the top level module names for the simulator For example vlog top v and2 v or2 v Compiling module top Compiling module and2 Compiling module or2 Top level modules top Automatic Incremental Compilation with incr The most efficient method of incremental compilation is to manually compile only the modules that have changed However this is not always convenient especially if your source files have compiler directive interdependencies such as macros In this case you m
7. Note that if your design uses two libraries one that depends on vital95 and one that depends on vital2000 then you will have to change the references in the source code to vital2000 Changing the library mapping will not work ModelSim User s Manual v6 2g 123 February 2007 VHDL Simulation VITAL Compliance VITAL Compliance A simulator is VITAL compliant if it implements the SDF mapping and if it correctly simulates designs using the VITAL packages as outlined in the VITAL Model Development Specification ModelSim is compliant with the IEEE 1076 4 VITAL ASIC Modeling Specification In addition ModelSim accelerates the VITAL Timing VITAL Primitives and VITAL memory packages The optimized procedures are functionally equivalent to the IEEE 1076 4 VITAL ASIC Modeling Specification VITAL 1995 and 2000 VITAL Compliance Checking If you are using VITAL 2 2b you must turn off the compliance checking either by not setting the attributes or by invoking vcom with the option novitalcheck Compiling and Simulating with Accelerated VITAL Packages vcom automatically recognizes that a VITAL function is being referenced from the ieee library and generates code to call the optimized built in routines Invoke with the novital option if you do not want to use the built in VITAL routines when debugging for instance To exclude all VITAL functions use novital all vcom novital all design vhd To exclude selected VITAL functio
8. There may be a problem that will affect the accuracy of your results The tool cannot complete the operation The tool cannot complete execution e Tool indicates which ModelSim tool was being executed when the message was generated For example tool could be vcom vdel vsim etc e Group indicates the topic to which the problem is related For example group could be FLI PLL VCD etc Example Error vsim PLI 3071 src 19 testfile 77 Sfdumplimit Too few arguments Getting More Information Each message is identified by a unique MsgNum id You can access additional information about a message using the unique id and the verror command For example ModelSim User s Manual v6 2g 355 February 2007 Error and Warning Messages Suppressing Warning Messages o verror 3071 Message 3071 Not enough arguments are being passed to the specified system task or function Changing Message Severity Level You can suppress or change the severity of notes warnings and errors that come from vcom vlog and vsim You cannot change the severity of or suppress Fatal or Internal messages There are two ways to modify the severity of or suppress notes warnings and errors e Use the error fatal note suppress and warning arguments to vcom vlog or vsim See the command descriptions in the Reference Manual for details on those arguments e Seta permanent default in the msg syst
9. 18800 ps to 23200 ps Now 750 ns Delta 2 216 ModelSim User s Manual v6 2g February 2007 Waveform Analysis Configuring New Line Triggering in the List Window Configuring New Line Triggering in the List Window New line triggering refers to what events cause a new line of data to be added to the List window By default ModelSim adds a new line for any signal change including deltas within a single unit of time resolution You can set new line triggering on a signal by signal basis or for the whole simulation To set for a single signal select View Signal Properties from the List window menu bar when the window is undocked and select the Triggers line setting Individual signal settings override global settings Figure 8 23 Line Triggering in the List Window List Signal Properties SI Signat test_counter count Display Name counter Radix C Symbolic Width 21 Characters C Binary C Octal C Decimal C Unsigned Tnager qu I ASCII Does not trigger line Default To modify new line triggering for the whole simulation select Tools gt List Preferences from the List window menu bar when the window is undocked or use the configure command When you select Tools gt List Preferences the Modify Display Properties dialog appears ModelSim User s Manual v6 2g 217 February 2007 Waveform Analysis Configuring New Line Triggering in the List Window Figure 8 24 Setting Trigger
10. IK CU F F z 4 461968 ns to 462962 ns Now 500 us Delta 2 Mii Landes Mme Eme 4 a E q Here is an example of a Wave window that is undocked from the MDI frame All menus and icons associated with Wave window functions now appear in the menu and toolbar areas of the Wave window 72 ModelSim User s Manual v6 2g February 2007 Simulator Windows Wave Window Figure 2 30 Wave Window Dock Button M wave default E File Edit View Add Format Tools Window test_counter chk test_counter teset test_counter count 7 If the Wave window is docked into the Main window MDI frame all menus and icons that were in the standalone version of the Wave window move into the Main window menu bar and toolbar The Wave window is divided into a number of window panes All window panes in the Wave window can be resized by clicking and dragging the bar between any two panes ModelSim User s Manual v6 2g 73 February 2007 Simulator Windows Wave Window Example 2 1 Wave Window Panes pathnames values waveforms F wave def ult i ni xj e cR vef d Format Te Wey IEEE Jest counter ckk test_counter reset test_counter count 7 434260 ns to 4346 Pns p Now 495 852 ns Delta 2 The following types of objects can be viewed in the Wave window e VHDL objects indicated by a dark blue diamond signals aliases process variables and shared variables Veri
11. ModelSim identifies certain kinds of arrays in various scopes as memories Memory identification depends on the array element kind as well as the overall array kind i e associative array unpacked array etc Table 2 9 Memories J VHDL Verilog SystemVerilog Element kind enum std logic vector std bit vector or integer any integral type i e integer type shortint int longint byte bit 2 state logic reg integer time 4 state packed struct packed union 2 state packed struct packed union 4 state packed array single Dim multi D 2 state and 4 state enum or string Scope recognizable in architecture process or record module interface package compilation unit struct or static variables within a task function named block class 56 single dimensional or multi dimensional any combination of unpacked dynamic and associative arrays ModelSim User s Manual v6 2g February 2007 Simulator Windows Memory Panes 1 These enumerated type value sets must have values that are longer than one character The listed width is the number of entries in the enumerated type definition and the depth is the size of the array itself 2 Any combination of unpacked dynamic and associative arrays is considered a memory provided the leaf level of the data structure is a string or an integral type Associative Arrays in Verilog SystemVerilog For an associative array to
12. You can set this variable interactively in the GUI refer to Setting Simulator Control Variables With The GUI e Value Range symbolic binary octal decimal unsigned hexadecimal ascii e Default symbolic 332 ModelSim User s Manual v6 2g February 2007 Simulator Variables Simulator Control Variables DefaultRestartOptions This variable sets the default behavior for the restart command e Value Range one or more of force noassertions nobreakpoint nofcovers nolist nolog nowave e Default commented out DelayFileOpen This variable instructs the tool to open VHDL387 files on first read or write else open files when elaborated e Value Range 0 1 e Default off 0 DumpportsCollapse This variable collapses vectors VCD id entries in dumpports output e Value Range 0 1 e Default off 0 GenerateFormat This variable controls the format of a generate statement label Do not enclose the argument in quotation marks e Value Range Any non quoted string containing at a minimum a s followed by a d e Default s__ d GlobalSharedObjectsList This variable instruct the tool to load the specified PLI FLI shared objects with global symbol visibility e Value Range comma separated list of filenames e Default commented out IgnoreError This variable instructs the tool to ignore VHDL assertion errors You can set this variable interactively in the GUI refer to Setting Simulator Control
13. active events e inactive events e non blocking assignment update events 154 ModelSim User s Manual v6 2g February 2007 Verilog and SystemVerilog Simulation Simulating Verilog Designs e monitor events e future events o inactive events o non blocking assignment update events The LRM dictates that events are processed as follows 1 all active events are processed 2 the inactive events are moved to the active event queue and then processed 3 the non blocking events are moved to the active event queue and then processed 4 the monitor events are moved to the active queue and then processed 5 simulation advances to the next time where there is an inactive event or a non blocking assignment update event Within the active event queue the events can be processed in any order and new active events can be added to the queue in any order In other words you cannot control event order within the active queue The example below illustrates potential ramifications of this situation Say you have these four statements 1 always q p q 2 always q p2 not q 3 always p or p2 clk p and p2 4 always posedge clk and current values as follows q 0 p 0 p2 1 The tables below show two of the many valid evaluations of these statements Evaluation events are denoted by a number where the number is the statement to be evaluated Update events are denoted lt name gt old gt new where lt name gt indicates
14. end ModelSim User s Manual v6 29 249 February 2007 Signal Spy signal release signal release The signal release procedure releases any force that was applied to an existing VHDL signal or Verilog register net called the dest object This allows you to release signals registers or nets at any level of the design hierarchy from within a VHDL architecture e g a testbench A signal release works the same as the noforce command Signal release can be called concurrently or sequentially in a process Syntax signal release dest object lt verbose gt Returns Nothing Arguments dest object Required string A full hierarchical path or relative downward path with reference to the calling block to an existing VHDL signal or Verilog register net Use the path separator to which your simulation is set i e or A full hierarchical path must begin with a or The path must be contained within double quotes verbose Optional integer Possible values are 0 or 1 Specifies whether you want a message reported in the Transcript stating that the signal is being released and the time of the release Default is 0 no message Related procedures init signal driver init signal spy signal force Limitations e You cannot release a bit or slice of a register you can release only the entire register signal release Example This example releases any forces on the signals data and c k when the
15. 15 16 parameter counter size 4 17 parameter buffer size 16 18 19 Define blocks I O s 20 input clock reset oeenable txda 21 input counter size 2 0 ramadrs 22 output buffer size 1 0 buffer 23 24 Define wires for connecting wires Za wire clock reset oeenable txda outstrobe rxda 26 wire counter size 2 0 ramadrs H gp wave C ringbuf h H control vhd h store v h Untitled 1 KE See Organizing Windows with Tab Groups for more information on these tabs Dragging and Dropping Objects into the Wave and List Windows ModelSim allows you to drag and drop objects from the Source window to the Wave and List windows Double click an object to highlight it then drag the object to the Wave or List window To place a group of objects into the Wave and List windows drag and drop any section of highlighted code ModelSim User s Manual v6 2g 63 February 2007 Simulator Windows Source Window Setting your Context by Navigating Source Files When debugging your design from within the GUI you can change your context while analyzing your source files Figure 2 21 shows the pop up menu the tool displays after you select then right click an instance name in a source file Figure 2 21 Setting Context from Source Files mponent vlogchk Fr f gt 1 iR in i end mer mant Open Instance signa Ascend Env td T begin Back 1 is aftet ns Gut ne O after ns C
16. Accessing the Call Stack Pane View Call Stack Figure 2 8 Call Stack Pane Call stack 0 Module bot ca a 1 Function f3 25 C Justa AANA Te83a41f 2 Function f2 20 C QuestaT estcases calistackView callstack sv 7e83a18f 3 Function f 15 C QuestaT estcases callstackView callstack sv 7e839efd 4 Module top 35 C QuestaTestcases calistackView callstack sv 7e83a9b5 Using the Call Stack Pane The Call Stack pane contains five columns of information to assist you in debugging your design 48 indicates the depth of the function call with the most recent at the top In indicates the function Line indicates the line number containing the function call File indicates the location of the file containing the function call ModelSim User s Manual v6 2g February 2007 Simulator Windows Dataflow Window e Address indicates the address of the execution in a foreign subprogram such as C The Call Stack pane allows you to perform the following actions within the pane e Double click on the line of any function call o Displays the local variables at that level in the Locals Pane o Displays the corresponding source code in the Source Window e Right click in the column headings o Displays a pop up window that allows you to show or hide columns Dataflow Window The Dataflow window allows you to explore the physical connectivity of your design Note
17. Expand net to readers As you expand the view note that the layout of the design may adjust to best show the connectivity For example the location of an input signal may shift from the bottom to the top of a process ModelSim User s Manual v6 29 February 2007 227 Tracing Signals with the Dataflow Window The Embedded Wave Viewer Tracking Your Path Through the Design You can quickly traverse through many components in your design To help mark your path the objects that you have expanded are highlighted in green Figure 9 2 Green Highlighting Shows Your Path Through the Design RASSIGNRI 721 Fost HAND 24 Yu t ut t You can clear this highlighting using the Edit Erase highlight command or by clicking the Erase highlight icon in the toolbar The Embedded Wave Viewer Another way of exploring your design is to use the Dataflow window s embedded wave viewer This viewer closely resembles in appearance and operation the stand alone Wave window see Waveform Analysis for more information The wave viewer is opened using the View Show Wave command or by clicking the Show Wave icon One common scenario is to place signals in the wave viewer and the Dataflow panes run the design for some amount of time and then use time cursors to investigate value changes In other Words as you place and move cursors in the wave viewer pane see Measuring Time with Cursors in the Wave Window for details the s
18. Viewing Single and Multidimensional Memories 00 00 c eee eee eee 57 Viewing Packed ATIS caus eraksaexerktRs IA RE RENARIEA Sense se PESE 57 Viewing Memory Contents ideseduokbeex aurere earar 57 Saving Memory Formats in a DO File seeeeeeeeeee ee 58 Direct Address Navigation 44 veia eases Ee E WE ranean 58 Splitting the Memory Contents Pane 24 2 zs edo enn 4E ERE TRADERE RS RIAM E neds 58 Objects Pane iussa bed RR ARR AR RR REESE CR RES RR EE ES ix d exe S Edo E 60 Fillerme the Objects List sss 294 203 no Rb eaaa aa aa ee eg eee nee S 60 Filtering by Name iuc kr sd ke Re Rp Sake eos E Ie Ru REG RS UR RR RR Peed 60 Filtering by Signal Type sse sesr astuan SEPA ES Era daos SERE p eed aps das 61 Source WiDndOW eser aka Reda ERR EGRE Rx dei ri Fax su A RE Edd 62 Opening Source Files oed prc EP RI WEAEA ROM HQ e DURO IMMER ES 62 Displaying Multiple Source Files llle 63 Dragging and Dropping Objects into the Wave and List Windows 63 Setting your Context by Navigating Source Files 64 Language Lemplales sees c PERRESE AERA TEE OE IATa ROEE IRE EE ad 65 Setting File Line Break poss vices 2 4 yiee redox Reda eEX ERE ORE bed Ee 67 Checking Object Values and Descriptions 0 0 cece eee eee eee 67 Marking Lines with Bookmarks 012 59 sse ER EE aus eer RR aie dearest 68 Customizing the Source Window 00 cee eect eee tenes 68 br ggg M 70 Adding Objects to the Pane
19. cut the selected text to the clipboard Copy Edit gt Copy copy the selected text to the clipboard Paste Edit gt Paste HA paste the clipboard text Undo Edit Undo undo the last edit Redo Edit Redo redo the last undone edit Fi Edit Find find text in the active window Collapse All Edit gt Expand gt Collapse All collapse all instances in the active window Expand All Edit gt Expand gt Expand All expand all instance in the active window aoe ModelSim User s Manual v6 2g 45 February 2007 Simulator Windows Navigating in the Main Window 46 Table 2 7 Main Window Toolbar Buttons Compile open the Compile Source Files dialog to select files for compilation Menu equivalent Compile Compile Command equivalents Compile All compile all files in the open project Simulate load the selected design unit or simulation configuration object Compile gt Compile All Simulate gt Start Simulation Break stop the current simulation run Simulate gt Break Environment up move up one level in the design hierarchy Environment back navigate backward to a previously selected context Environment forward navigate forward to a previously selected context r r Restart reload the design elements and reset the simulation time to zero with the option of maintaining various settings and objects Simulate gt Run gt Restart E
20. sdftyp lt instance gt lt filename gt sdfmax lt instance gt lt filename gt Any number of SDF files can be applied to any instance in the design by specifying one of the above options for each file Use sdfmin to select minimum sdftyp to select typical and sdfmax to select maximum timing values from the SDF file Instance Specification The instance paths in the SDF file are relative to the instance to which the SDF is applied Usually this instance is an ASIC or FPGA model instantiated under a testbench For example to annotate maximum timing values from the SDF file myasic sdf to an instance u under a top level named testbench invoke the simulator as follows vsim sdfmax testbench u1 myasic sdf testbench If the instance name is omitted then the SDF file is applied to the top level This is usually incorrect because in most cases the model is instantiated under a testbench or within a larger system level simulation In fact the design can have several models each having its own SDF file In this case specify an SDF file for each instance For example ModelSim User s Manual v6 2g 263 February 2007 Standard Delay Format SDF Timing Annotation Specifying SDF Files for Simulation vsim sdfmax system u1 asic1 sdf sdfmax system u2 asic2 sdf system SDF Specification with the GUI As an alternative to the command line options you can specify SDF files in the Start Simulation dialog box under the SDF tab
21. 5 tpw clk reset eq 0 The SDF statement CONDELSE when targeted for Vital cells is annotated to a tpd generic of the form tpd_ lt inputPort gt _ lt outputPort gt Resolving Errors If the simulator finds the cell instance but not the generic then an error message is issued For example ModelSim User s Manual v6 2g 265 February 2007 Standard Delay Format SDF Timing Annotation Verilog SDF Error vsim SDF 3240 myasic sdf 18 Instance testbench dut ul does not have a generic named tpd a y In this case make sure that the design is using the appropriate VITAL library cells If it is then there is probably a mismatch between the SDF and the VITAL cells You need to find the cell instance and compare its generic names to those expected by the annotator Look in the VHDL source files provided by the cell library vendor If none of the generic names look like VITAL timing generic names then perhaps the VITAL library cells are not being used If the generic names do look like VITAL timing generic names but don t match the names expected by the annotator then there are several possibilities e The vendor s tools are not conforming to the VITAL specification e The SDF file was accidentally applied to the wrong instance In this case the simulator also issues other error messages indicating that cell instances in the SDF could not be located in the design e The vendor s library and SDF were develo
22. Figure 11 1 SDF Tab in Start Simulation Dialog Start Simulation X Design VHDL Verilog Libraries SDF Others d m SDF Files Add Modify Delete SDF Options Multi Source delay Disable SDF wamings vi Reduce SDF errors to warnings aK C Cancel You can access this dialog by invoking the simulator without any arguments or by selecting Simulate Start Simulation See the GUI chapter for a description of this dialog For Verilog designs you can also specify SDF files by using the sdf annotate system task See sdf annotate for more details Errors and Warnings Errors issued by the SDF annotator while loading the design prevent the simulation from continuing whereas warnings do not Use the sdfnoerror option with vsim to change SDF errors to warnings so that the simulation can continue Warning messages can be suppressed by using vsim with either the sdfnowarn or nosdfwarn options 264 ModelSim User s Manual v6 2g February 2007 Standard Delay Format SDF Timing Annotation VHDL VITAL SDF Another option is to use the SDF tab from the Start Simulation dialog box shown above Select Disable SDF warnings sdfnowarn nosdfwarn to disable warnings or select Reduce SDF errors to warnings sdfnoerror to change errors to warnings See Troubleshooting for more information on errors and warnings and how to avoid them VHDL VITAL SDF VHDL SDF annotati
23. Hugh Smith at The University of Guelph Redistribution and use in source and binary forms with or without modification are permitted provided that the following conditions are met Redistributions of source code must retain the above copyright notice this list of conditions and the following disclaimer 2 Redistributions in binary form must reproduce the above copyright notice this list of conditions and the following disclaimer in the documentation and or other materials provided with the distribution 3 All advertising materials mentioning features or use of this software must display the following acknowledgement This product includes software developed by the University of California Berkeley and its contributors 4 Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS AS IS AND ANY EXPRESS OR IMPLIED WARRANTIES INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT INDIRECT INCIDENTAL SPECIAL EXEMPLARY OR CONSEQUENTIAL DAMAGES INCLUDING BUT NOT LIMITED TO PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES LOSS OF USE DATA OR PROFITS OR
24. In Verilog escaped identifiers start with the backslash character and end with a white space Neither the backslash at the beginning or the white space at the end are considered to be a part of the identifier When a ModelSim displays Verilog escaped identifiers however a backslash is added at the end in order to match the VHDL syntax for escaped identifiers This is because all Verilog escaped identifiers can be easily converted to VHDL but the converse is not true So for example a Verilog escaped identifier like the following Vtop dut 03 will be displayed as follows Vtop dut 03 When entering Verilog identifiers with the ModelSim command line interface you should use the VHDL syntax with a backslash at the beginning and end of the identifier In Tcl the backslash is one of a number of characters that have a special meaning For example n creates a new line When a Tcl command is used in the command line interface the TCL backslash should be escaped by adding another backslash For example force freeze top ix iy yw 1 10 0 01 50 ns r 100 The Verilog identifier in this example is yw 1 Here double backslashes are used because it is necessary to escape the square brackets which have a special meaning in Tcl For a more detailed description of special characters in Tcl and how backslashes should be used with those characters click Help gt Tcl Syntax in the menu bar of the graphic interface or sim
25. In this situation ModelSim reports strengths for both the zero and one components of the value if the strengths are the same If the strengths are different ModelSim reports only the winning strength In other words the two strength values either match e g pA 5 5 or the winning strength is shown and the other is zero e g pH 0 5 Extended dumpports Syntax ModelSim extends the dumpports system task in order to support exclusion of strength ranges The extended syntax is as follows Sdumpports scope list file pathname ncsim file index file format The nc sim index argument is required yet ignored by ModelSim It is required only to be compatible with NCSim s argument list The file format argument accepts the following values or an ORed combination thereof see examples below Table 12 7 Values for file format Argument File format value Meaning Ignore strength range Use strength ranges produces IEEE 1364 compliant behavior Compress the EVCD output Include port direction information in the EVCD file header same as using direction argument to ved dumpports Here are some examples ignore strength range dumpports top filename O0 0 compress and ignore strength range Sdumpports top filename 0 4 print direction and ignore strength range Sdumpports top filename O0 8 ModelSim User s Manual v6 2g 289 February 2007 Value Change Dump VCD Files
26. ModelSim User s Manual Software Version 6 2g February 2007 1991 2007 Mentor Graphics Corporation All rights reserved This document contains information that is proprietary to Mentor Graphics Corporation The original recipient of this document may duplicate this document in whole or in part for internal business purposes only provided that this entire notice appears in all copies In duplicating any part of this document the recipient agrees to make every reasonable effort to prevent the unauthorized use and distribution of the proprietary information This document is for information and instruction purposes Mentor Graphics reserves the right to make changes in specifications and other information contained in this publication without prior notice and the reader should in all cases consult Mentor Graphics to determine whether any changes have been made The terms and conditions governing the sale and licensing of Mentor Graphics products are set forth in written agreements between Mentor Graphics and its customers No representation or other affirmation of fact contained in this publication shall be deemed to be a warranty or give rise to any liability of Mentor Graphics whatsoever MENTOR GRAPHICS MAKES NO WARRANTY OF ANY KIND WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE MENTOR GRAPHICS SHALL NOT BE LIABLE FOR ANY INCIDENTAL IND
27. See signal release for complete details to real to real converts the physical type time value into a real value with respect to the current simulator resolution The precision of the converted value is determined by the simulator resolution For example if you were converting 1900 fs to a real and the simulator resolution was ps then the real value would be 2 0 1 e 2 ps Syntax realval to real timeval Returns Name Type Description realval real The time value represented as a real with respect to the simulator resolution Arguments Name Type Description timeval time The value of the physical type time Related functions e get resolution e to time Example If the simulator resolution is set to ps and you enter the following function 126 ModelSim User s Manual v6 2g February 2007 realval to real 12 99 ns VHDL Simulation Util Package then the value returned to realval would be 12990 0 If you wanted the returned value to be in units of nanoseconds ns instead you would use the get resolution function to recalculate the value realval 1e 9 to real 12 99 ns get resolution If you wanted the returned value to be in units of femtoseconds fs you would enter the function this way realval 1e 15 to real 12 99 ns get resolution to time to time converts a real value into a time value with respect to the current simulator resolution The precision of the co
28. This command acquires displays any signals using your radix setting either the default or as you specify unless you specify the radix in the value you set Syntax signal force dest object value rel time force type cancel period lt verbose gt Returns Nothing Arguments 248 dest object Required string A full hierarchical path or relative downward path with reference to the calling block to an existing VHDL signal or Verilog register net Use the path separator to which your simulation is set 1 e or A full hierarchical path must begin with a or The path must be contained within double quotes value Required string Specifies the value to which the dest object is to be forced The specified value must be appropriate for the type rel time Optional time Specifies a time relative to the current simulation time for the force to occur The default is 0 force_type Optional forcetype Specifies the type of force that will be applied The value must be one of the following default deposit drive or freeze The default is default which is freeze for unresolved objects or drive for resolved objects See the force command for further details on force type cancel_period Optional time Cancels the signal_force command after the specified period of time units Cancellation occurs at the last simulation delta cycle of a time unit A value of zero cancels the for
29. e WLF Size Limit Limit the size of a WLF file to n megabytes by truncating from the front of the file as necessary e WLF Time Limit Limit the size of a WLF file to lt t gt time by truncating from the front of the file as necessary e WLF Compression Compress the data in the WLF file e WLF Optimization Write additional data to the WLF file to improve draw performance at large zoom ranges Optimization results in approximately 15 larger ModelSim User s Manual v6 2g 177 February 2007 WLF Files Datasets and Virtuals Opening Datasets WLF files Disabling WLF optimization also prevents ModelSim from reading a previously generated WLF file that contains optimized data e WLF Delete on Quit Delete the WLF file automatically when the simulation exits Valid for current simulation dataset vsim wlf only e WLF Cache Size Specify the size in megabytes of the WLF reader cache WLF reader cache is enabled by default The default value is 256 This feature caches blocks of the WLF file to reduce redundant file I O If the cache is made smaller or disabled least recently used data will be freed to reduce the cache to the specified size e WLF Collapse Mode WLFE event collapsing has three settings disabled delta time o When disabled all events and event order are preserved o Delta mode records an object s value at the end of a simulation delta iteration only Default o Time mode records an objec
30. e dest object Required string A full hierarchical path or relative downward path with reference to the calling block to a VHDL signal or Verilog register net This path should match the path that was specified in the init signal spy call that you wish to disable e verbose Optional integer Possible values are 0 or 1 Specifies whether you want a message reported in the transcript stating that a disable occurred and the simulation time that it occurred Default is 0 no message Related procedures init_signal_spy enable_signal_spy Example See init_signal_spy Example ModelSim User s Manual v6 2g 241 February 2007 Signal Spy enable signal spy enable signal spy The enable signal spy procedure enables the associated init signal spy The association between the enable signal spy call and the init signal spy call is based on specifying the same src object and dest object arguments to both functions The enable signal spy call can only affect init signal spy calls that had their control state argument set to 0 or 1 Syntax enable signal spy src object dest object lt verbose gt Returns Nothing Arguments e src object Required string A full hierarchical path or relative downward path with reference to the calling block to a VHDL signal or Verilog register net This path should match the path that was specified in the init signal spy call that you wish to enable e dest object Required
31. routine is called However some of the objects are created on demand and the handles to these objects become invalid after acc close is called The following object types are created on demand in ModelSim Verilog accOperator acc handle condition accWirePath acc handle path accTerminal acc handle terminal acc next cell load acc next driver and acc next load accPathTerminal acc next input and acc next output accTchkTerminal acc handle tchkarg1 and acc handle tchkarg2 accPartSelect acc handle conn acc handle pathin and acc handle pathout If your PLI application uses these types of objects then it is important to call acc close to free the memory allocated for these objects when the application is done using them If your PLI application places value change callbacks on accRegBit or accTerminal objects do not call acc close while these callbacks are in effect Third Party PLI Applications Many third party PLI applications come with instructions on using them with ModelSim Verilog Even without the instructions it is still likely that you can get it to work with ModelSim Verilog as long as the application uses standard PLI routines The following guidelines are for preparing a Verilog XL PLI application to work with ModelSim Verilog Generally a Verilog XL PLI application comes with a collection of object files and a veriuser c file The veriuser c file contains the registration information as described above
32. 64 bit IBM RS 6000 Platform Only versions 5 1 and later of AIX support the 64 bit platform A gcc 64 bit compiler is not available at this time e VisualAge cc compiler cc c q64 I lt install_dir gt modeltech include app c Id o app s1 app o b64 bE app exports bl lt install_dir gt modeltech rs64 mti_exports bM SRE bnoentry lc DPI Imports on 64 bit IBM RS 6000 Platform When linking the shared objects be sure to specify bE lt isymfile gt option on the link command line lt isymfile gt is the name of the file generated by the isymfile argument to the vlog command Once you have created the lt isymfile gt it contains a complete list of all imported tasks and functions expected by ModelSim ModelSim User s Manual v6 2g 379 February 2007 Verilog PLI VPI DPI Compiling and Linking C Applications for PLI VPI DPI DPI Flow for Exported Tasks and Functions on 64 bit IBM RS 6000 Platform Since the RS6000 platform lacks the necessary runtime linking capabilities you must perform an additional manual step in order to prepare shared objects containing calls to exported SystemVerilog tasks or functions shared object file You need to invoke a special run of vsim The command is as follows vsim top du list dpiexportobj lt objname gt other args The dpiexportobj generates the object file lt objname gt o that contains glue code for exported tasks and functions You must add that object file to the link lin
33. 64 bit Linux for IA64 Platform 64 bit Linux is supported on RedHat Linux Advanced Workstation 2 1 for Itanium 2 e GNU C compiler version gcc 3 2 or later g c fPIC I lt install_dir gt modeltech include app cpp Id shared Bsymbolic E allow shlib undefined o app so app o If your PLI VPI application requires a user or vendor supplied C library or an additional system library you will need to specify that library when you link your PLI VPI application For example to use the system math library libm specify Im to the Id command g c fPIC I lt install_dir gt modeltech include math app cpp Id shared Bsymbolic E allow shlib undefined o math app so math app o Im 64 bit Linux for Opteron Athlon 64 and EM64T Platforms 64 bit Linux is supported on RedHat Linux EWS 3 0 for Opteron Athlon 64 and EM64T e GNU C compiler version gcc 3 2 or later g c fPIC I lt install_dir gt modeltech include app cpp Id shared Bsymbolic E allow shlib undefined o app so app o To compile for 32 bit operation specify the m32 argument on the gcc command line If your PLI VPI DPI application requires a user or vendor supplied C library or an additional system library you will need to specify that library when you link your PLI VPI DPI application For example to use the system math library libm specify Im to the ld command g c fPIC I lt install_dir gt modeltech include math app cpp Id shared Bsymboli
34. A Verilog design is ready for simulation after it has been compiled with vlog The simulator may then be invoked with the names of the top level modules many designs contain only one top level module For example if your top level modules are testbench and globals then invoke the simulator as follows vsim testbench globals After the simulator loads the top level modules it iteratively loads the instantiated modules and UDPs in the design hierarchy linking the design together by connecting the ports and resolving hierarchical references By default all modules and UDPs are loaded from the library named work Modules and UDPs from other libraries can be specified using the L or Lf arguments to vsim see Library Usage for details On successful loading of the design the simulation time is set to zero and you must enter a run command to begin simulation Commonly you enter run all to run until there are no more simulation events or until finish is executed in the Verilog code You can also run for specific time periods e g run 100 ns Enter the quit command to exit the simulator Simulator Resolution Limit Verilog The simulator internally represents time as a 64 bit integer in units equivalent to the smallest unit of simulation time also known as the simulator resolution limit The resolution limit defaults to the smallest time precision found among all of the timescale compiler directives in the design Here is an exampl
35. CODE name in square brackets in the warning message For example vlog nowarnDECAY suppresses decay warning messages Suppressing VSIM Warning Messages Use the nowarn lt CODE gt argument to vsim to suppress a specific warning message Warnings that can be disabled include the lt CODE gt name in square brackets in the warning message For example vsim nowarnTFMPC suppresses warning messages about too few port connections Exit Codes The table below describes exit codes used by ModelSim tools Table C 2 Exit Codes Exit code Description 0 Normal non error return 1 Incorrect invocation of tool Previous errors prevent continuing Cannot create a system process execv fork spawn etc Cannot create open find read write a design library Cannot create open find read write a design unit 2 3 d Licensing problem 5 6 7 Cannot open read write dup a file open lseek write mmap munmap fopen fdopen fread dup2 etc File is corrupted or incorrect type version or format of file Memory allocation error ModelSim User s Manual v6 2g 357 February 2007 Error and Warning Messages Exit Codes Exit code 10 Table C 2 Exit Codes Description General language semantics error 11 General language syntax error Problem during load or elaboration Problem during restore Problem during refresh Communication problem Cannot create read write clos
36. Cancel 3 Give the bookmark a name and click OK Editing Bookmarks Once a bookmark exists you can change its properties by selecting Wave gt Bookmarks gt Bookmarks if the Wave window is docked or by selecting Tools gt Bookmarks if the Wave window is undocked Searching in the Wave and List Windows The Wave and List windows provide two methods for locating objects e Finding signal names Select Edit gt Find or use the find command to search for the name of a signal e Search for values or transitions Select Edit gt Signal Search to locate transitions or signal values The search feature is not available in all versions of ModelSim Finding Signal Names The Find command is used to locate a signal name or value in the Wave or List window When you select Edit gt Find the Find dialog appears 198 ModelSim User s Manual v6 2g February 2007 Waveform Analysis Searching in the Wave and List Windows Figure 8 8 Find Signals by Name or Value CC 8 h Find FindNext Field Direction Close Name Down lm C Value C Up IV Auto Wrap One option of note is the Exact checkbox Check Exact if you only want to find objects that match your search exactly For example searching for clk without Exact will find top clk and clk1 There are two differences between the Wave and List windows as it relates to the Find feature e Inthe Wave window you can specify a value to search
37. Capturing Port Driver Data compress print direction and ignore strength range dumpports top filename 0 12 Example 12 5 VCD Output from vcd dumpports This example demonstrates how vcd dumpports resolves values based on certain combinations of driver values and strengths and whether or not you use strength ranges Table 12 8 is sample driver data Table 12 8 Sample Driver Data in value out value in strength value out strength value range range 0 7 strong 7 strong 0 0 0 1 1 1 6 strong 7 strong 5 strong 7 strong 6 strong 7 strong 5 strong 4 weak 27500 4 weak 4 weak 27600 1 3 weak 4 weak Given the driver data above and use of 1364 strength ranges here is what the VCD file output would look like 0 0 0 0 4 weak 7 strong 0 1 1 1 p070 0 p07 0 0 p07 0 0 pL 7 0 0 900 pB 7 0 0 27400 pu 0 5 lt 0 27500 pl 0 4 0 27600 pl 0 4 0 Here is what the output would look like if you ignore strength ranges 290 ModelSim User s Manual v6 2g February 2007 O eec Se se t E l e ModelSim User s Manual v6 29 February 2007 0 0 0 Value Change Dump VCD Files Capturing Port Driver Data 291 Value Change Dump VCD Files Capturing Port Driver Data 292 ModelSim User s Manual v6 29 February 2007 Chapt
38. DATA OR PROFITS OR BUSINESS INTERRUPTION HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY WHETHER IN CONTRACT STRICT LIABILITY OR TORT INCLUDING NEGLIGENCE OR OTHERWISE ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE Refer to the license file in your install directory install directory2 docs legal gnu gcc pdf This product may include freeWrap open source software Dennis R LaBelle All Rights Reserved Disclaimer of warranty Licensor provides the software on an as is basis Licensor does not warrant guarantee or make any representations regarding the use or results of the software with respect to it correctness accuracy reliability or performance The entire risk of the use and performance of the software is assumed by licensee ALL WARANTIES INCLUDING WITHOUT LIMITATION ANY WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR MERCHANTABILITY ARE HEREBY EXCLUDED This software application may include MinGW GNU diffutils version 2 7 third party software 1991 1993 The Regents of the University of California All rights reserved UNIX System Laboratories Inc All or some portions of this file are derived from material licensed to the University of California by American Telephone and Telegraph Co or Unix System Laboratories Inc and are reproduced herein with the permission of UNIX System Laboratories Inc This code is derived from software contributed to Berkeley by
39. Example 12 5 VCD Output from vcd dumpports 0 0 00 eee eee eee 290 Example D 1 VPI Application Registration 2 0 0 0 0 cece eee eee eee 368 Example F 1 Configure Window Layouts Dialog Box 0 000000 00s 412 14 ModelSim User s Manual v6 2g February 2007 List of Figures Figure 1 1 Tool Structure and FIOQ iso dsveprew 4 gER xS EEVRNESVAPFRREMPEEE REN 22 Figure 2 1 Graphical User Interface 5 22s oe ee tases oes See ee RR eee eee 33 Figure 2 2 Mati WINdOW 2 ba deed abe So ae PR UR RR ROUEN TER Suid Re PO ER 37 Figure 2 3 Message Viewer Tab 2 2 oie ades uu REEL EAE RE E RR hay tee oe AERE RR 4 Figure 2 4 Tabs in the MDI Frame ase ee EE RR RARE EM ER neta bed eae 42 Figure 2 5 Organizing Files in Tab Groups 0 0 0 0 cece eee eee eee 43 Figure 2 6 Main Window Status Bar 44 Figure 2 7 Active Processes Pane cus oo desk hes WE cad E EPORRERSETRRAGREAS ues E PES 47 Figure 2 8 Call Stack Pane 2 22h use pR RR Re OEX ER RR RR Qe ede XE ee REG 48 Figure 2 9 Dataflow WildOW gt iaceo rRP e a RbeAeqer Ae bee Rer Rex EE Rasa 49 Figure 2 10 List Window Docked in Main Window MDI Frame 53 Figure 2 11 List Window Undocked 2 020 0s0 65d20s0e0 5000 p rrr ee 54 Figure 2 12 Iocals Pane c coss ross bu dads at haer RR hee PE Ag hp Pb qood adt 55 Figure 2 13 Memory Panes ios ER ru E Rd RR ER RN LR EUER AER ERR RNAd md 56 Figure 2 14 Viewing Multiple Memories 222 2
40. February 2007 Projects Creating a Simulation Configuration To ungroup files select the group and click the Ungroup button zz Creating a Simulation Configuration A Simulation Configuration associates a design unit s and its simulation options For example say you routinely load a particular design and you have to specify the simulator resolution generics and SDF timing files Ordinarily you would have to specify those options each time you load the design With a Simulation Configuration you would specify the design and those options and then save the configuration with a name e g top config The name is then listed in the Project tab and you can double click it to load the design along with its options To create a Simulation Configuration follow these steps 1 Select Project gt Add to Project gt Simulation Configuration from the main menu or right click the Project tab and select Add to Project Simulation Configuration from the popup context menu in the Project tab Figure 3 13 Simulation Configuration Dialog Add Simulation Configuration X m Simulation Configuration Name Place in Folder Simulation 1 Top Level i Add Folder Design VHDL Verilog Libraries SDF Others Fr work Library C Tutorial examples tutorials mixed compare work sv std Library MODEL TECH sv std vital2000 Library MODEL_TECH vital2000 ieee Library MODEL_TECH ieee modelsim_lib Librar
41. INCIDENTAL SPECIAL EXEMPLARY OR CONSEQUENTIAL DAMAGES INCLUDING BUT NOT LIMITED TO PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES LOSS OF USE DATA OR PROFITS OR BUSINESS INTERRUPTION HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY WHETHER IN CONTRACT STRICT LIABILITY OR TORT INCLUDING NEGLIGENCE OR OTHERWISE ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE Refer to the license file in your install directory install directory2 docs legal gnu gcc pdf This software application may include GNU third party software distributed by The Free Software Foundation Free Software Foundation To view a copy of the GNU GPL LGPL Library and Documentation licenses refer to http www fsf org licensing licenses Refer to the license file in your install directory install directory docs legal gnu gcc pdf This software application may include GNU GCC third party software The Regents of the University of California All rights reserved THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS AS IS AND ANY EXPRESS OR IMPLIED WARRANTIES INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT INDIRECT INCIDENTAL SPECIAL EXEMPLARY OR CONSEQUENTIAL DAMAGES INCLUDING BUT NOT LIMITED TO PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES LOSS OF USE
42. Im to the Id command cc c DD64 l install dir2 modeltech include math app c Id b o math app sl math app o Im 32 bit IBM RS 6000 Platform ModelSim loads shared libraries on the IBM RS 6000 workstation The shared library must import ModelSim s PLI VPI DPI symbols and it must export the PLI or VPI application s initialization function or table The ModelSim tool s export file is located in the ModelSim installation directory in r 6000 mti exports If your PLI VPI DPI application uses anything from a system library you ll need to specify that library when you link your PLI VPI DPI application For example to use the standard C library specify Ic to the Id command The resulting object must be marked as shared reentrant using these gcc or cc compiler commands for AIX 4 x e gcc compiler gcc c l lt install_dir gt modeltech include app c Id o app s app o bE app exp blz install dir modeltech rs6000 mti exports bM SRE bnoentry lc cccompiler cc c I lt install_dir gt modeltech include app c Id o app sl app o bE app exp blz install dir modeltech rs6000 mti exports bM SRE bnoentry lc 378 ModelSim User s Manual v6 2g February 2007 Verilog PLI VPI DPI Compiling and Linking C Applications for PLI VPI DPI The app exp file must export the PLI VPI initialization function or table For the PLI the exported symbol should be init usertfs Alternatively if there is no init usertfs functi
43. Runtime Options Dialog Box WLF Files Tab zax Defaults Assertions WLF Files WLF File Size Limit WLF File Time Limit No Size Limit amp No Time Limit C Size Limit O Me C Time Limit ne WLF Attributes Design Hierarchy v Compress WLF data Save regions containing logged signals Delete WLF file on exit C Save all regions in design OK Cancel e WLF File Size Limit Limits the WLF file by size as closely as possible to the specified number of megabytes If both size and time limits are specified the most restrictive is used Setting it to 0 results in no limit The corresponding modelsim ini variable is WLFSizeLimit e WLF File Time Limit Limits the WLF file by size as closely as possible to the specified amount of time If both time and size limits are specified the most restrictive is used Setting it to O results in no limit The corresponding modelsim ini variable is WLFTimeLimit e WLF Attributes Specifies whether to compress WLF files and whether to delete the WLF file when the simulation ends You would typically only disable compression for troubleshooting purposes The corresponding modelsim ini variables are WLFCompress for compression and WLFDeleteOnQuit for WLF file deletion e Design Hierarchy Specifies whether to save all design hierarchy in the WLF file or only regions containing logged signals The corresponding modelsim ini variable is WLFSaveAllRegions Mess
44. Simulator Specific Tcl Commands 0 0 0 0 cece eee eee 300 Table 13 5 Tcl Time Conversion Commands 0 0 0 cece eee eee eee 302 Table 13 6 Tcl Time Relation Commands 2 2 2s 2s ddr Rs RR RR 302 Table 13 7 Tcl Time Arithmetic Commands 0 e eee eee ee eee 303 Table 13 8 Commands for Handling Breakpoints and Errors in Macros 310 Table A 1 Add Library Mappings to modelsim ini File 0000005 318 Table A 2 AssertionFormat Variable Accepted Values 0 0 0 0 00 0s ee eee 329 Table A 3 License Variable License Options 0 0 c eee eee eee ee 335 Table C 1 Severity Level Types q s ciseaund ssdevadeeideeureresenaneesderend 355 Table lt 2 Exit CodeS Lua ss sere du ES oeS eh aR eosin E E ED SR aA eed dad iR EE 357 Table D 1 vsim Arguments for DPI Application llleeeeee eee 387 Table D 2 Supported VHDL Objects 2 22222 des Rr eRRRERESaR RARE RR RR 393 Table D 3 Supported ACC Routines lseeeeeeeeee eh 395 Table D 4 Supported TF Rowtines s2 5 s Rr REX EREA RES IDA Ee RIA E REGE Ed 307 Table D 5 Values for action Argument 2060 e eee eee eee eens 399 Table E 1 Command History Shortcuts 0 cece eee eee eee 403 Table E22 Mouse Shortculs 22 22424 cine oe estates tel xe ewe dashes see bees eres 404 ModelSim User s Manual v6 2g 19 February 2007 20 List of Tables Table E 3 Keyboard SloPneuls
45. The path must be contained within double quotes ModelSim User s Manual v6 29 245 February 2007 Signal Spy init signal spy e verbose Optional integer Possible values are 0 or 1 Specifies whether you want a message reported in the Transcript stating that the src_object s value is mirrored onto the dest_object Default is 0 no message control state Optional integer Possible values are 1 0 or 1 Specifies whether or not you want the ability to enable disable mirroring of values and if so specifies the initial state The default is 1 no ability to enable disable and mirroring is enabled 0 turns on the ability to enable disable and initially disables mirroring 1 turns on the ability to enable disable and initially enables mirroring Related procedures init signal driver signal force signal release enable signal spy disable signal spy Limitations e When mirroring the value of a Verilog register net onto a VHDL signal the VHDL signal must be of type bit bit_vector std_logic or std_logic_vector e Verilog memories arrays of registers are not supported init_signal_spy Example In this example the value of top uut inst1 sig1 is mirrored onto top top sig1 A message is issued to the transcript The ability to control the mirroring of values is turned on and the init signal spy is initially enabled The mirroring of values will be disabled when enable sig transitions to a 0 and enable when enab
46. VHDL SystemVerilog an object refers to any valid design element in those languages The word object is used whenever a specific language reference is not needed Depending on the context object can refer to any of the following 30 Table 1 3 Definition of Object by Language Language An object can be block statement component instantiation constant generate statement generic package signal alias or variable Verilog function module instantiation named fork named begin net task register or variable SystemVerilog In addition to those listed above for Verilog class package program interface array directive property or sequence ModelSim User s Manual v6 2g February 2007 Introduction Text Conventions Table 1 3 Definition of Object by Language Language An object can be property sequence directive or endpoint Text Conventions Text conventions used in this manual include Table 1 4 Text Conventions Text Type Description italic text provides emphasis and sets off filenames pathnames and design unit names bold text indicates commands command options menu choices package and library logical names as well as variables dialog box selections and language keywords monospace type monospace type is used for program and command examples The right angle 2 is used to connect menu choices when traversing menus as in File Quit UPPER CASE denotes f
47. WarnConstantChange 339 WaveSignalNameWidth 339 WLFCacheSize 339 WLFCollapseMode 340 WLFCompress 340 WLFDeleteOnQuit 340 WLFFilename 340 WLFOptmize 340 WLFSaveAllRegions 340 WLESizeLimit 341 WLFTimeLimit 341 ini variables set simulator control with GUI 342 modelsim file in initialization sequence 422 purpose 419 So shared object file loading PLI VPI DPI C applications 373 loading PLI VPI DPI C applications 380 Numerics 0 In tools setting environment variable 314 1076 IEEE Std 28 differences between versions 111 1364 IEEE Std 28 139 64 bit libraries 107 64 bit time now variable 350 Tcl time commands 301 425 ABCDEFGHI 64 bit vsim using with 32 bit FLI apps 398 A ACC routines 395 accelerated packages 106 access hierarchical objects 239 Active Processes pane 47 see also windows Active Processes pane architecture simulator state variable 349 archives described 100 argc simulator state variable 349 arguments passing to a DO file 308 arithmetic package warnings disabling 347 AssertFile ini file variable 329 AssertionDebug ini variable 329 AssertionFormat ini file variable 329 AssertionFormatBreak ini file variable 330 AssertionFormatError ini file variable 330 AssertionFormatFail ini file variable 330 AssertionFormatFatal ini file variable 330 AssertionFormatNote ini file variable 330 AssertionFormatWarning ini file variable 331 ass
48. When more than one dataset is open ModelSim will automatically prefix names in the Wave and List windows with the dataset name You can change this default by selecting Tools Window Preferences Wave and List windows ModelSim also remembers a current context within each open dataset You can toggle between the current context of each dataset using the environment command specifying the dataset without a path For example env foo sets the active dataset to foo and the current context to the context last specified for foo The context is then applied to any unlocked windows The current context of the current dataset usually referred to as just current context is used for finding objects specified without a path The Objects pane can be locked to a specific context of a dataset Being locked to a dataset means that the pane will update only when the content of that dataset changes If locked to both a dataset and a context e g test top foo the pane will update only when that specific context changes You specify the dataset to which the pane is locked by selecting File Environment Restricting the Dataset Prefix Display The default for dataset prefix viewing is set with a variable in pref tcl PrefMain DisplayDatasetPrefix Setting the variable to 1 will display the prefix setting it to 0 will not It is set to 1 by default Either edit the pref tcl file directly or use the Tools gt Edit Preferences command to cha
49. Zoom gt Zoom Active Cursor Cursor Cursor ModelSim User s Manual v6 2g 193 February 2007 Waveform Analysis Measuring Time with Cursors in the Wave Window Lock cursor Wave Edit Cursor Edit Edit Cursor Table 8 1 Actions for Cursors cont Menu command Menu command Toolbar button Wave window docked Wave window undocked Name cursor Wave Edit Cursor Edit Edit Cursor Select cursor Wave Cursors View Cursors Shortcuts for Working with Cursors There are a number of useful keyboard and mouse shortcuts related to the actions listed above Select a cursor by clicking the cursor name Jump to a hidden cursor one that is out of view by double clicking the cursor name Name a cursor by right clicking the cursor name and entering a new value Press Enter on your keyboard after you have typed the new name Move a locked cursor by holding down the shift key and then clicking and dragging the cursor Move a cursor to a particular time by right clicking the cursor value and typing the value to which you want to scroll Press Enter on your keyboard after you have typed the new value Understanding Cursor Behavior The following list describes how cursors behave when you click in various panes of the Wave window 194 If you click in the waveform pane the cursor closest to the mouse position is selected and then moved to the mouse position Clicking in a horizon
50. clause may itself contain an others clause you can use this feature to chain a set of hierarchical INI files for library mappings Creating a Transcript File A feature in the system initialization file allows you to keep a record of everything that occurs in the transcript error messages assertions commands command outputs etc To do this set 346 ModelSim User s Manual v6 2g February 2007 Simulator Variables Simulator Control Variables the value for the TranscriptFile line in the modelsim ini file to the name of the file in which you would like to record the ModelSim history Save the command window contents to this file TranscriptFile trnscrpt You can disable the creation of the transcript file by using the following ModelSim command immediately after ModelSim starts transcript file Using a Startup File The system initialization file allows you to specify a command or a do file that is to be executed after the design is loaded For example VSIM Startup command Startup do mystartup do The line shown above instructs ModelSim to execute the commands in the macro file named mystartup do VSIM Startup command Startup run all The line shown above instructs VSIM to run until there are no events scheduled See the do command for additional information on creating do files Turning Off Assertion Messages You can turn off assertion messages from your VHDL code by setting a switch in the modelsim
51. g I install dir modeltech include hello c c ld G Bsymbolic o hello c so hello c o Simulate the design vsim c sv lib hello c hello top Loading work hello c Loading hello_c so VSIM 1 run all Hello from c task Hello from verilog task VSIM 2 quit The PLI Callback reason Argument The second argument to a PLI callback function is the reason argument The values of the various reason constants are defined in the veriuser h include file See IEEE Std 1364 for a description of the reason constants The following details relate to ModelSim Verilog and may not be obvious in the IEEE Std 1364 Specifically the simulator passes the reason values to the misctf callback functions under the following circumstances reason endofcompile For the completion of loading the design reason finish For the execution of the finish system task or the quit command reason startofsave For the start of execution of the checkpoint command but before any of the simulation state has been saved This allows the PLI application to prepare for the save but it shouldn t save its data with calls to tf write save until it is called with reason save reason save For the execution of the checkpoint command This is when the PLI application must save its state with calls to tf write save reason startofrestart For the start of execution of the restore command
52. install dir include hello c ld G Bsymbolic o hello sl hello o ile the Verilog code vlib work vlog hello v Simulate the design vsim c pli hello sl hello Loading work hello Loading hello sl VSIM 1 run all Hello world VSIM 2 quit oe oe Com oe O oe DPI Example The following example is a trivial but complete DPI application For win32 and RS6000 platforms an additional step is required For additional examples see the install dir modeltech examples systemverilog dpi directory hello c c include svdpi h include dpiheader h int c task int i int o printf Hello from c_task n verilog task i 0 o i return 0 Return success required by tasks hello v module hello top int ret export DPI C task verilog task task verilog task input int i 10 Sdisplay Hello from verilog task endtask import DPI C initial begin C task 1 ret end endmodule Compile the Verilog code vlib work vlog sv dpiheader dpiheader h hello v Call back into Verilog output int o context task c task input int i output int o Call the c task named c task ox oe ModelSim User s Manual v6 2g 389 February 2007 Verilog PLI VPI DPI The PLI Callback reason Argument Compile the DPI code for the Solaris operating system 9 gcc c
53. myasic sdf 0 Failed to find INSTANCE testbench u5 Warning vsim SDF 3432 myasic sdf This file is probably applied to the wrong instance Warning vsim SDF 3432 myasic sdf Ignoring subsequent missing instances from this file After annotation is done the simulator issues a summary of how many instances were not found and possibly a suggestion for a qualifying instance Warning vsim SDF 3440 myasic sdf Failed to find any of the 358 instances from this file Warning vsim SDF 3442 myasic sdf Try instance testbench dut It contains all instance paths from this file The simulator recommends an instance only if the file was applied to the top level and a qualifying instance is found one level down Also see Resolving Errors for specific VHDL VITAL SDF troubleshooting 276 ModelSim User s Manual v6 2g February 2007 Chapter 12 Value Change Dump VCD Files This chapter describes how to use VCD files in ModelSim The VCD file format is specified in the IEEE 1364 standard It is an ASCII file containing header information variable definitions and variable value changes VCD is in common use for Verilog designs and is controlled by VCD system task calls in the Verilog source code ModelSim provides command equivalents for these system tasks and extends VCD support to VHDL designs The ModelSim commands can be used on VHDL Verilog or mixed designs If you need ve
54. nonexclusive license for experimental use to test and evaluate the Beta Code without charge for a limited period of time specified by Mentor Graphics This grant and your use of the Beta Code shall not be construed as marketing or offering to sell a license to the Beta Code which Mentor Graphics may choose not to release commercially in any form If Mentor Graphics authorizes you to use the Beta Code you agree to evaluate and test the Beta Code under normal conditions as directed by Mentor Graphics You will contact Mentor Graphics periodically during your use of the Beta Code to discuss any malfunctions or suggested improvements Upon completion of your evaluation and testing you will send to Mentor Graphics a written evaluation of the Beta Code including its strengths weaknesses and recommended improvements You agree that any written evaluations and all inventions product improvements modifications or developments that Mentor Graphics conceived or made during or subsequent to this Agreement including those based partly or wholly on your feedback will be the exclusive property of Mentor Graphics Mentor Graphics will have exclusive rights title and interest in all such property The provisions of this section 3 shall survive the termination or expiration of this Agreement RESTRICTIONS ON USE You may copy Software only as reasonably necessary to support the authorized use Each copy must include all notices and legends embedded in Software and af
55. or Tcl script Different commands interpret their words differently Words of a command are separated by white space except for newlines which are command separators If the first character of a word is a double quote then the word is terminated by the next double quote character If semi colons close brackets or white space characters including newlines appear between the quotes then they are treated as ordinary characters and included in the word Command substitution variable substitution and backslash substitution are performed on the characters between the quotes as described below The double quotes are not retained as part of the word ModelSim User s Manual v6 2g February 2007 Tcl and Macros DO Files Tcl Command Syntax 5 If the first character of a word is an open brace then the word is terminated by the matching close brace Braces nest within the word for each additional open brace there must be an additional close brace however if an open brace or close brace within the word is quoted with a backslash then it is not counted in locating the matching close brace No substitutions are performed on the characters between the braces except for backslash newline substitutions described below nor do semi colons newlines close brackets or white space receive any special interpretation The word will consist of exactly the characters between the outer braces not including the braces themselves 6 If a wo
56. result in misleading timing constraint violations because the ports may satisfy the constraint while the delayed versions may not If the simulator seems to report incorrect violations be sure to account for the effect of interconnect delays ModelSim User s Manual v6 2g 273 February 2007 Standard Delay Format SDF Timing Annotation Disabling Timing Checks Disabling Timing Checks ModelSim offers a number of options for disabling timing checks on a global or individual basis The table below provides a summary of those options See the command and argument descriptions in the Reference Manual for more details Table 11 21 Disabling Timing Checks Command and argument Effect vlog notimingchecks disables timing check system tasks for all instances in the specified Verilog design vlog nospecify disables specify path delays and timing checks for all instances in the specified Verilog design vsim no neg tchk disables negative timing check limits by setting them to zero for all instances in the specified design vsim no_notifier disables the toggling of the notifier register argument of the timing check system tasks for all instances in the specified design vsim no tchk msg disables error messages issued by timing check system tasks when timing check violations occur for all instances in the specified design vsim notimingchecks disables Verilog and VITAL timing checks for all instances in the specified des
57. subdirectory that matches the logical name An error is generated by the compiler if you specify a logical name that does not resolve to an existing directory Moving a Library Individual design units in a design library cannot be moved An entire design library can be moved however by using standard operating system commands for moving a directory or an archive Setting Up Libraries for Group Use By adding an others clause to your modelsim ini file you can have a hierarchy of library mappings If the tool does not find a mapping in the modelsim ini file then it will search the library section of the initialization file specified by the others clause For example library asic_lib work my_work usr modeltech modelsim ini cae asic lib others You can specify only one others clause in the library section of a given modelsim ini file The others clause only instructs the tool to look in the specified modelsim ini file for a library it does not load any other part of the specified file ModelSim User s Manual v6 2g February 2007 104 Design Libraries Specifying the Resource Libraries Specifying the Resource Libraries Verilog Resource Libraries ModelSim supports separate compilation of distinct portions of a Verilog design The vlog compiler is used to compile one or more source files into a specified library The library thus contains pre compiled modules and UDPs that are referenced by the sim
58. v6 2g February 2007 Appendix B Location Mapping Pathnames to source files are recorded in libraries by storing the working directory from which the compile is invoked and the pathname to the file as specified in the invocation of the compiler The pathname may be either a complete pathname or a relative pathname Referencing Source Files with Location Maps ModelSim tools that reference source files from the library locate a source file as follows e Ifthe pathname stored in the library is complete then this is the path used to reference the file e Ifthe pathname is relative then the tool looks for the file relative to the current working directory If this file does not exist then the path relative to the working directory stored in the library is used This method of referencing source files generally works fine if the libraries are created and used on a single system However when multiple systems access a library across a network the physical pathnames are not always the same and the source file reference rules do not always work Using Location Mapping Location maps are used to replace prefixes of physical pathnames in the library with environment variables The location map defines a mapping between physical pathname prefixes and environment variables ModelSim tools open the location map file on invocation if the MGC LOCATION MAP environment variable is set If MGC LOCATION MAP is not set ModelSim will look for a file n
59. we data in addr inaddr outaddr WAIT UN WAIT UN data in addr inaddr WAIT UN WAIT UN data in addr inaddr WAIT UN WAIT UN data in addr inaddr WAIT UN WAIT UN we addr outaddr WAIT UN WAIT UN addr outaddr WAIT UN WAIT UN addr outaddr WAIT UN WAIT UN addr outaddr WAIT UN WAIT UN END LOOP ASSERT REPORT false IL IL IL IL IL IL IL IL IL IL IL IL IL IL lt rit lt to unsigned 9000 lt to unsigned i lt to unsigned i lt to unsigned i CIk EVENT AND clk CLkK EVENT AND clk lt to_unsigned 7 lt to unsigned 1 lt to unsigned 1 Clk EVENT AND clk Clk EVENT AND clk lt to_unsigned 3 dat lt to_unsigned 2 i lt to_unsigned 2 i Clk EVENT AND clk Clk EVENT AND clk lt to_unsigned 30330 lt to unsigned 3 i lt to unsigned 3 Clk EVENT AND clk Clk EVENT AND clk lt Q F lt to_unsigned i lt to_unsigned i c1k EVENT AND clk CIk EVENT AND clk lt to unsigned 1 lt to unsigned 1 Clk EVENT AND clk Clk EVENT AND clk lt to_unsigned 2 lt to unsigned 2 Clk EVENT AND clk Clk EVENT AND clk lt to_unsigned 3 lt to_unsigned 3 Clk EVENT AND clk
60. 1 and 2 of the Commercial Computer Software Restricted Rights clause at FAR 52 227 19 as applicable Contractor manufacturer is Mentor Graphics Corporation 8005 SW Boeckman Road Wilsonville Oregon 97070 7777 USA THIRD PARTY BENEFICIARY For any Software under this Agreement licensed by Mentor Graphics from Microsoft or other licensors Microsoft or the applicable licensor is a third party beneficiary of this Agreement with the right to enforce the obligations set forth herein AUDIT RIGHTS You will monitor access to location and use of Software With reasonable prior notice and during your normal business hours Mentor Graphics shall have the right to review your software monitoring system and reasonably relevant records to confirm your compliance with the terms of this Agreement an addendum to this Agreement or U S or other local export laws Such review may include FLEXIm or FLEXnet report log files that you shall capture and provide at Mentor Graphics request Mentor Graphics shall treat as confidential information all of your information gained as a result of any request or review and shall only use or disclose such information as required by law or to enforce its rights under this Agreement or addendum to this Agreement The provisions of this section 14 shall survive the expiration or termination of this Agreement 15 16 17 CONTROLLING LAW JURISDICTION AND DISPUTE RESOLUTION THIS AGREEMENT SHALL BE GOVERNED BY AND CONST
61. 114 Simulator Resolution Limit VHDL llllleeeeeeeee Re 114 cold PPP 115 Delia DelayS soneca acano R4 qur RR ER REESE Re ETRG DEEP q RS RTR EUR 116 Usine the Text Package 2 cnsasud cao Reb soe apt E acea seed eee Rees 118 Syntax for File Declatgtollos espesor ei EE EE RE EERERSRRERAT RES WERE ES 119 Using STD INPUT and STD OUTPUT Within the Tool 004 119 TextIO Implementation ISSugs 2 5 eos e duae rrr dE REXTEPEEOP OPE b RRERLES EU REX 120 Writing Strings and Aggregates cseuesersu ee Eu RM RE EE REPERTA RM EE Eg 120 Reading and Writing Hexadecimal Numbers 0 0 cece eee eee eee 121 Dangling POmiets lt c lt esse tc edex RP eR EQ S ROC AT QN ES ci eR hetea qd EO TA d qux 121 The ENDLINE PUDCHO 52g 3 rne e ota nona medea TR pp DER Rhe e pr 121 ModelSim User s Manual v6 2g 5 February 2007 Table of Contents The ENDFILE Function xb harm ic Xr RE X eR ESCENA ERAN 122 Using Alternative Input Output Files 0 0 0 cece eee e 122 Plushie the LEX TIO Bullet iiueedes P qUERCLESA Y horr QC ERE rO EPOD ERR 122 Pr viding Stimulus 4 5 eek eC Ino R HoRO Padre V Races i Cea ieee e qa ps eg qa ER 122 VITAL Specification and Source Code iv Sae yw Ra REX EXERCERE AO RE E EU 123 VITAL PAGEdUBS 3 2 29 va eser aie APSE GR VEI DER PI S UR EERO Red 123 VITAL Compliance ossa b XO RR RN amb C a dedo Sca ces do ERU 124 VITAL Compliance Checking L4 uuu acad e do ACRYLIC RO RICO 124 Compiling
62. 4 gt quit f There will now be an extended VCD file called myvcdfile vcd in the working directory Note There is an internal limit to the number of port driver changes that can be created with the vcd dumpports command If that limit is reached use the ved add command with the dumpports option to create additional port driver changes By default ModelSim uses strength ranges for resolving conflicts as specified by IEEE 1364 2005 You can ignore strength ranges using the no_strength_range argument to the vcd dumpports command See Resolving Values for more details Case Sensitivity VHDL is not case sensitive so ModelSim converts all signal names to lower case when it produces a VCD file Conversely Verilog designs are case sensitive so ModelSim maintains case when it produces a VCD file Using Extended VCD as Stimulus You can use an extended VCD file as stimulus to re simulate your design There are two ways to do this 1 simulate the top level of a design unit with the input values from an extended VCD file and 2 specify one or more instances in a design to be replaced with the output values from the associated VCD file Simulating with Input Values from a VCD File When simulating with inputs from an extended VCD file you can simulate only one design unit at a time In other words you can apply the VCD file inputs only to the top level of the design unit for which you captured port data The general procedure includes t
63. 8 9 Wave Signal Search Dialog 2 5 22 5 c lt seu a ga deee sae xe ERRARE ERE ERA 200 Figure 8 10 Expression Builder Dialog 0 0 eee eee cee eee eee 201 Figure 8 11 Display Tab of the Wave Window Preferences Dialog 203 Figure 8 12 Grid amp Timeline Tab of Wave Window Preferences Dialog 204 Figure 8 13 Clock Cycles in Timeline of Wave Window eeslseeesese 204 Figure 8 14 Changing Signal Radix 2o2iooosoeoslee e Rr RR REER r ses 205 Figure 8 15 Separate Signals with Wave Window Dividers 0 000 5 206 Figure 8 16 Splitting Wave Window Panes 02 eee eee ee eee 208 Figure 8 17 Fill in the name of the group in the Group Name field 209 Figure 8 18 Wave groups denoted by red diamond lslsllel eee eee ee 209 Figure 8 19 Modifying List Window Display Properties 211 Figure 8 20 List Signal Properties Dialog 0 0 cece ee eee 212 Figure 8 21 Changing the Radix in the List Window 0 0 0 0 0c ee eee eee 213 Figure 8 22 Signals Combined to Create Virtual Bus 0 0 00 00 eee eee 216 Figure 8 23 Line Triggering in the List Window 217 16 ModelSim User s Manual v6 2g February 2007 List of Figures Figure 8 24 Setting Trigger Properteso sors de ERR RR RES RRRRPERE P 218 Figure 8 25 Trigger Gating Using Expression Builder 00000000005 220 Figure 9 1 The Dataflow Wi
64. Builder 5 Click OK to close the Expression Builder You should see the name of the signal plus rising added to the Expression entry box of the Modify Display Properties dialog box 6 Click OK to close the dialog If you already have simulation data in the List window the display should immediately switch to showing only those cycles for which the gating signal is rising If that isn t quite what you want you can go back to the expression builder and play with it until you get it the way you want it If you want the enable signal to work like a One Shot that would display all values for the next say 10 ns after the rising edge of enable then set the On Duration value to 10 ns Trigger Gating Example Using Commands The following commands show the gating portion of a trigger configuration statement configure list usegating 1 configure list gateduration 100 configure list gateexpr test_delta iom_dd rising See the configure command for more details 220 ModelSim User s Manual v6 2g February 2007 Waveform Analysis Miscellaneous Tasks Sampling Signals at a Clock Change You easily can sample signals at a clock change using the add list command with the notrigger argument The notrigger argument disables triggering the display on the specified signals For example add list clk notrigger a b c When you run the simulation List window entries for clk a b and c appear only when clk changes If you want
65. Clk EVENT AND clk SEVERITY failure END PROCESS END testbench ModelSim User s Manual v6 2g February 2007 End of Simulation VHDL Simulation Modeling Memory i data in length addr length inaddr length outaddr length Vt s vy ts data in length addr length inaddr length ts VT a in length addr length inaddr length Vy ts vos data in length addr length inaddr length oTa vts addr length outaddr length Vots ots addr length outaddr length Urs Vt s addr length outaddr length LES Vs addr length outaddr length Tors vts 135 VHDL Simulation Affecting Performance by Cancelling Scheduled Events Affecting Performance by Cancelling Scheduled Events Performance will suffer if events are scheduled far into the future but then cancelled before they take effect This situation will act like a memory leak and slow down simulation In VHDL this situation can occur several ways The most common are waits with time out clauses and projected waveforms in signal assignments The following code shows a wait with a time out signals synch bit 0 p process begin wait for 10 ms until synch 1 end process synch not synch after 10 ns At time 0 process p makes an event for time 10ms When synch goes to 1 at 10 ns the event at 10 ms is marked as cancelled but not deleted and a new
66. DOWNTO 0 END COMPONENT ModelSim User s Manual v6 2g 133 February 2007 VHDL Simulation Modeling Memory 134 Intermediate signals and constants SIGNAL addr unsigned 19 DOWNTO 0 SIGNAL inaddr unsigned 3 DOWNTO 0 SIGNAL outaddr unsigned 3 DOWNTO 0 SIGNAL data in unsigned 31 DOWNTO 0 SIGNAL data inl std logic vector 7 DOWNTO 0 SIGNAL data spl std logic vector 7 DOWNTO 0 SIGNAL we std logic SIGNAL clk std logic CONSTANT clk pd time 100 ns BEGIN instantiations of single port RAM architectures All architectures behav quivalently but they have different implementations The signal based architecture rtl is not a recommended style spraml entity work sp syn ram protected GENERIC MAP data width gt 8 addr width gt 12 PORT MAP inclk gt clk outclk gt clk we gt we addr gt addr 11 downto 0 data in gt data inl data out data spl clock generator clock driver PROCESS BEGIN clk lt 0 WAIT FOR clk_pd 2 LOOP clk lt 1 O AFTER clk pd 2 WAIT FOR clk pd END LOOP END PROCESS data in process datain drivers PROCESS data in BEGIN data inl std logic vector data in 7 downto 0 END PROCESS simulation control process ctrl sim PROCESS ModelSim User s Manual v6 2g February 2007 BEGIN FOR i IN 0 TO 1023 LOOP
67. Displaying Drivers of the Selected Waveform Sorting a Group of Objects in the Wave Window Creating and managing breakpoints Signal breakpoints File line breakpoints Tracing Signals with the Dataflow Window Dataflow Window Overview Objects You Can View in the Dataflow Window Adding Objects to the Window Links to Other Windows Exploring the Connectivity of the Design Tracking Your Path Through the Design The Embedded Wave Viewer Zooming and Panning Panning with the Mouse Tracing Events Causality Tracing the Source of an Unknown State StX Table of Contents ModelSim User s Manual v6 2g February 2007 Table of Contents Finding Objects by Name in the Dataflow Window ssseeeeleeeeeee 232 Printing and Saving the Display 224 6 esu kle erA RR RRRERSERREERIZSA RENE RR 233 Saving a eps File and Printing the Dataflow Display from UNIX 233 Printing from the Dataflow Display on Windows Platforms lesse 234 Configuring Page Seter dee Sus seen ston cel ERVERP AG P CREER E eee ese Ea 235 Symbol Mapping sese sasat egeta Re Sud UE Eee eng eee eee eee eee E Qu E 235 Configuring Window Options 0 0 cece eee I e 237 Chapter 10 Signal SPY 269 995992 RRRTRLRERERVRRREEERORIRERERTE RS E SEETRRDERKARE S CSS 239 Designed tor Testbenclies sa soos iov assa Ee rh pes deter rr merce pw Y ex dq eyes 239 disable signal SD sees reeR XRR aeRRE RAW PSR eS eee Se eee Oe eee ee ERS 241 enable signal S
68. For more information on resource libraries and working libraries see Working Library Versus Resource Libraries Managing Library Contents Working with Design Libraries and Specifying the Resource Libraries 24 ModelSim User s Manual v6 2g February 2007 Introduction Basic Steps for Simulation Creating the Logical Library vlib Before you can compile your source files you must create a library in which to store the compilation results You can create the logical library using the GUI using File gt New gt Library see Creating a Library or you can use the vlib command For example the command vlib work creates a library named work By default compilation results are stored in the work library Mapping the Logical Work to the Physical Work Directory vmap VHDL uses logical library names that can be mapped to ModelSim library directories If libraries are not mapped properly and you invoke your simulation necessary components will not be loaded and simulation will fail Similarly compilation can also depend on proper library mapping By default ModelSim can find libraries in your current directory assuming they have the right name but for it to find libraries located elsewhere you need to map a logical library name to the pathname of the library You can use the GUI Library Mappings with the GUI a command Library Mapping from the Command Line or a project Getting Started with Projects to assign a logica
69. Instances with Output Values from a VCD File 00000 280 VCD Commands and VCD TaSk8 oder E DR RARE ERR E EN RIA RE RE cot 281 Compressing Files with VCD Tasks ioisosueessu RR RR dat egheedededuse ds 282 VCD File from Source To OUIBUE ood o Sea shh ane mide REOR cence eae wes 282 VHDL Source CODO ds Sos eed eee ad nce ine olde suka eRe Soins eid ee aera a 282 VCD Simulator Commands 212a ERROR ERR AG ERE REGE URRE RA RA EIU 283 VCD AJB DUU usage ire 24055 iral Soap EE NOR Sr RERUM ade Sat RU Heese eked Rees 283 Capturing Port Driver Data iiic RR ERRARE RR ER REG RE RR Ta da bens 286 Diver States MT 286 Driver Strength i22 ce ERI RR Y X Ee ex yates E DR EPA eee idee ed 287 Netter Code PF CD LT 288 Resolving Value esso oec eee eek oe eee ERAS LASER MER SES ae arietis 288 Chapter 13 Tel and Macros DO Filles ie ERR M ER RE S SANSONE 293 el CAME e PU 293 Tel References P TEE 293 device 293 Tel Command Syntax 45i cui salueemd RE RR uA me E RR S Rd RE Puck E ac radon Pac s 294 If Comm nd Syntax eaae duse ones EARS herd IR a a Ra Edd EU add swage 297 Command Substitution osave eee une ee ces hex ur ar da Ra x ae css 297 Command SepardtOr sss erbe E RerERURTOG eed ee epee Oe RYG4 TERRAS ERE E 298 Miultiple Line Commands iu ossaa ste RA RDARROEEEISA REFRS RR REA E ed eens eds 298 Evaluation Ordets seer rne ce exa berRrweamue ad a he Caseeaderadeer KE
70. ModelSim User s Manual v6 2g February 2007 Chapter 4 Design Libraries VHDL designs are associated with libraries which are objects that contain compiled design units Verilog and SystemVerilog designs simulated within ModelSim are compiled into libraries as well Design Library Overview A design library is a directory or archive that serves as a repository for compiled design units The design units contained in a design library consist of VHDL entities packages architectures and configurations Verilog modules and UDPs user defined primitives The design units are classified as follows e Primary design units Consist of entities package declarations configuration declarations modulesUDPs Primary design units within a given library must have unique names e Secondary design units Consist of architecture bodiespackage bodies Secondary design units are associated with a primary design unit Architectures by the same name can exist if they are associated with different entities or modules Design Unit Information The information stored for each design unit in a design library is e retargetable executable code e debugging information e dependency information Working Library Versus Resource Libraries Design libraries can be used in two ways 1 asa local working library that contains the compiled version of your design 2 as a resource library The contents of your working library will change as you updat
71. OR OTHERWISE ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE Free Software Foundation Inc All rights reserved Refer to the license file in your install directory install directory docs legal mingw gcc pdf e This software application may include GNU GCC third party software AT amp T All rights reserved Permission to use copy modify and distribute this software for any purpose without fee is hereby granted provided that this entire notice is included in all copies of any software which is or includes a copy or modification of this software and in all copies of the supporting documentation for such software THIS SOFTWARE IS BEING PROVIDED AS IS WITHOUT ANY EXPRESS OR IMPLIED WARRANTY IN PARTICULAR NEITHER THE AUTHOR NOR AT amp T MAKES ANY REPRESENTATION OR WARRANTY OF ANY KIND CONCERNING THE MERCHANTABILITY OF THIS SOFTWARE OR ITS FITNESS FOR ANY PARTICULAR PURPOSE Refer to the license file in your install directory install directory docs legal gnu gcc pdf This software application may include GNU GCC third party software Doug Bell All Rights Reserved THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS AS IS AND ANY EXPRESS OR IMPLIED WARRANTIES INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT INDIRECT
72. Properties and Project Settings To customize specific files select the file s in the Project tab right click on the file names and select Properties The resulting Project Compiler Settings dialog Figure 3 18 varies depending on the number and type of files you have selected If you select a single VHDL or Verilog file you will see the General tab Coverage tab and the VHDL or Verilog tab respectively On the General tab you will see file properties such as Type Location and Size If you select multiple files the file properties on the General tab are not listed Finally if you select both a VHDL file and a Verilog file you will see all tabs but no file information on the General tab Figure 3 18 Specifying File Properties xl General Verilog Coverage BE General Settings Do Not Compile Compile to library work vi Place in Folder Top Level vi File Properties File sm v Location C examples coverage verilog sm v MS DOS name C examples coverage verilog sm Type Verilog Change T ype Size 2459 2KB Modification Time Thu Nov 04 7 35 06 PM Pacific Standard Time Last Compile Source has not been compiled File Attributes Archive OK Cancel When setting options on a group of files keep in mind the following e If two or more files have different settings for the same option the checkbox in the dialog will be grayed out If you change the option you cannot change
73. Run Length specify the run length for the current simulation Simulate gt Runtime Options Run run the current simulation for the specified run length Simulate gt Run gt Run default_run_length eh EJ Continue Run continue the current simulation run until the end of the specified run length or until it hits a breakpoint or specified break event Simulate Run Continue run continue ModelSim User s Manual v6 2g February 2007 Simulator Windows Active Processes Pane Table 2 7 Main Window Toolbar Buttons Menu equivalent Command equivalents Run All Simulate gt Run gt Run All run all run the current simulation forever or until it hits a breakpoint or specified break event Step Simulate gt Run gt Step step the current simulation to the next statement Step Over Simulate gt Run gt step over HDL statements are executed but Step Over treated as simple statements instead of entered and traced line by line E Contains Filt SUAM l I filter items in Objects pane Contains zz 2 Show Language Templates View Source display language templates Show Language Templates Active Processes Pane The Active Processes pane displays a list of HDL processes Processes are also displayed in the structure tabs of the Main window Workspace To filter displayed processes in the structure tabs select View Filter Processes Figure 2 7 Ac
74. TMPDIR above will help you locate and remove the file Simulator Control Variables Initialization INI files contain control variables that specify reference library paths and compiler and simulator settings The default initialization file is modelsim ini and is located in your install directory To set these variables edit the initialization file directly with any text editor The syntax for variables in the file is lt variable gt lt value gt Comments within the file are preceded with a semicolon The following sections contain information about the variables e Library Path Variables e Verilog Compiler Control Variables e VHDL Compiler Control Variables e Simulation Control Variables Library Path Variables You can find these variables under the heading Library in the modelsim ini file ieee This variable sets the path to the library containing IEEE and Synopsys arithmetic packages e Value Range any valid path may include environment variables e Default MODEL TECH ieee ModelSim User s Manual v6 2g 319 February 2007 Simulator Variables Simulator Control Variables modelsim lib This variable sets the path to the library containing Model Technology VHDL utilities such as Signal Spy e Value Range any valid path may include environment variables e Default SMODEL TECH modelsim lib std This variable sets the path to the VHDL STD library e Value Range any valid path may include enviro
75. Table A 3 License Variable License Options license option Inlonly mixedonly Description only use msimhdlsim and hdlsim exclude single language licenses nomgc exclude MGC licenses nolnl nomix exclude language neutral licenses exclude msimhdlmix and hdlmix nomti exclude MTI licenses noqueue noslvhdl do not wait in license queue if no licenses are available exclude qhsimvh and vsim noslvlog exclude qhsimvl and vsimvlog plus only use PLUS license only use VLOG license only use VHDL license e Default search all licenses LockedMemory For HP UX 10 2 use only This variable enables memory locking to speed up large designs gt 500mb memory footprint e Value Range positive integer in units of MB Default disabled MaxReportRhsCrossProducts This variable specifies a limit on number of Cross bin products which are listed against a Cross when a XML or UCDB report is generated The warning reports when any instance of unusually high number of Cross bin product and truncation of Cross bin product list for a Cross e Value Range positive integer ModelSim User s Manual v6 29 February 2007 335 Simulator Variables Simulator Control Variables e Default 1000 NumericStdNoWarnings This variable disables warnings generated within the accelerated numeric_std and numeric_bit packages You can set this variable interactively in the GUI
76. VCOM 326 Quiet ini file variable VLOG 322 R race condition problems with event order 154 radix List window 211 SystemVerilog types 75 205 Wave window 205 range checking 110 readers and drivers 227 real type converting to time 127 reconstruct RTL level design busses 184 RECOVERY matching to Verilog 270 recovery 169 RECREM matching to Verilog 270 redirecting messages TranscriptFile 338 refreshing library images 106 regions virtual 186 registers values of displaying in Objects window 60 saving as binary log file 175 waveforms viewing 72 REMOVAL matching to Verilog 270 report simulator control 313 simulator state 313 RequireConfigForAllDefaultBinding variable 326 resolution 434 JKLMNOPQRSTUVWXYZ returning as a real 125 verilog simulation 151 VHDL simulation 114 Resolution ini file variable 337 resolution simulator state variable 350 resource libraries 105 restart command defaults 348 toolbar button 46 78 results saving simulations 175 RTL level design busses reconstructing 184 RunLength ini file variable 337 Runtime Options dialog 342 9 saveLines preference variable 39 saving simulation options in a project 91 waveforms 175 scaling fonts 35 SDF disabling timing checks 274 errors and warnings 264 instance specification 263 interconnect delays 273 mixed VHDL and Verilog designs 273 specification with the GUI 264 troubleshooting 27
77. VHDL 2002 VITAL95 must be compiled with VHDL 87 A typical error message that indicates the need to compile under language version VHDL 87 is VITALPathDelay DefaultDelay parameter must be locally static Purity of NOW In VHDL 93 the function now is impure Consequently any function that invokes now must also be declared to be impure Such calls to now occur in VITAL A typical error message Cannot call impure function now from inside pure function Y name Yom Files File syntax and usage changed between VHDL 87 and VHDL 93 In many cases vcom issues a warning and continues Using 1076 1987 syntax for file declaration In addition when files are passed as parameters the following warning message is produced Subprogram parameter name is declared using VHDL 1987 syntax This message often involves calls to endfile lt name gt where name is a file parameter Files and packages Each package header and body should be compiled with the same language version Common problems in this area involve files as parameters and the size of type CHARACTER For example consider a package header and body with a procedure that has a file parameter procedure procl out file out std textio text If you compile the package header with VHDL 87 and the body with VHDL 93 or VHDL 2002 you will get an error message such as Error mixed package b vhd 4 Parameter kinds do not conform between declarati
78. VPI DPI We strongly encourage that unless you have a reason to do otherwise you should use the built in g compiler that is shipped with the ModelSim compiler to compile your C code This is the version that has been tested and is supported for any given release Specifying Your Own g Compiler If you must use a different g compiler other than that shipped with ModelSim you need to set a variable in your modelsim ini file as follows CppPath usr bin g to point to the desired g version ModelSim User s Manual v6 2g 365 February 2007 Verilog PLI VPI DPI Registering PLI Applications Registering PLI Applications Each PLI application must register its system tasks and functions with the simulator providing the name of each system task and function and the associated callback routines Since many PLI applications already interface to Verilog XL ModelSim Verilog PLI applications make use of the same mechanism to register information about each system task and function in an array of s_tfcell structures This structure is declared in the veriuser h include file as follows typedef int p tffn typedef struct t_tfcell short type USERTASK USERFUNCTION or USERREALFUNCTION short data passed as data argument of callback function p tffn checktf argument checking callback function p tffn sizetf function return size callback function p tffn calltf task or fun
79. Variables With The GUI ModelSim User s Manual v6 2g 333 February 2007 Simulator Variables Simulator Control Variables e Value Range 0 1 e Default off 0 IgnoreFailure This variable instructs the tool to ignore VHDL assertion failures You can set this variable interactively in the GUI refer to Setting Simulator Control Variables With The GUI e Value Range 0 1 e Default off 0 IgnoreNote This variable instructs the tool to ignore VHDL assertion notes You can set this variable interactively in the GUI refer to Setting Simulator Control Variables With The GUI e Value Range 0 1 e Default off 0 IgnoreWarning This variable instructs the tool to ignore VHDL assertion warnings You can set this variable interactively in the GUI refer to Setting Simulator Control Variables With The GUI e Value Range 0 1 e Default off 0 IterationLimit This variable specifies a limit on simulation kernel iterations allowed without advancing time You can set this variable interactively in the GUI refer to Setting Simulator Control Variables With The GUI e Value Range positive integer e Default 5000 334 ModelSim User s Manual v6 2g February 2007 License Simulator Variables Simulator Control Variables This variable controls the license file search e Value Range one ore more of the following license option separated by spaces if using multiple entries Refer also to the vsim license option
80. Window Keyboard Shortcuts Table E 3 Keyboard Shortcuts cont FI Windows on The Main window allows insertions or pastes only after the prompt therefore you don t need to set the cursor when copying strings to the command line List Window Keyboard Shortcuts Using the following keys when the mouse cursor is within the List window will cause the indicated actions Table E 4 List Window Keyboard Shortcuts Key UNIX and Windows Left Arrow Action scroll listing left selects and highlights the item to the left of the currently selected item Right Arrow scroll listing right selects and highlights the item to the right of the currently selected item Up Arrow scroll listing up Down Arrow scroll listing down Page Up Ctrl Up Arrow Page Down Ctrl Down Arrow scroll listing up by page scroll listing down by page Tab Shift Tab searches forward down to the next transition on the selected signal searches backward up to the previous transition on the selected signal does not function on HP workstations Shift Left Arrow Shift Right Arrow extends selection left right Ctrl f Windows Ctrl s UNIX ModelSim User s Manual v6 2g February 2007 opens the Find dialog box to find the specified item label within the list display 407 Command and Keyboard Shortcuts Wave Window Mouse and Keyboard Shortcuts Wave Window Mouse and Key
81. acc handle calling mod m acc handle condition acc handle conn acc handle hiconn acc handle interactive scope acc handle loconn acc handle modpath acc handle notifier acc handle object acc handle parent acc handle path acc handle pathin acc handle pathout acc handle port acc handle scope acc handle simulated net acc handle tchk acc handle tchkargl acc handle tchkarg2 acc handle terminal acc handle tfarg acc handle itfarg acc handle tfinst acc initialize Verilog PLI VPI DPI IEEE Std 1364 ACC Routines Table D 3 Supported ACC Routines acc_next acc_next_bit acc_next_cell acc_next_cell_load acc_next_child acc_next_driver acc_next_hiconn acc_next_input acc_next_load acc_next_loconn acc_next_modpath acc_next_net acc_next_output acc_next_parameter acc_next_port acc_next_portout acc_next_primitive acc_next_scope acc_next_specparam acc_next_tchk acc_next_terminal acc_next_topmod acc_object_in_typelist acc_object_of_type acc_product_type acc_product_version acc_release_object acc_replace_delays acc_replace_pulsere acc_reset_buffer acc_set_interactive_scope acc_set_pulsere acc_set_scope acc_set_value acc_vcl_add acc_vcl_delete acc_version 395 Verilog PLI VPI DPI IEEE Std 1364 ACC Routines acc_fetch_paramval cannot be used on 64 bit platforms to fetch a string value of a parameter Because of this the function acc_fetch_paramval_str has been added to the PLI for this use ac
82. allow shlib undefined o app so app o To compile for 32 bit operation specify the m32 argument on the gcc command line If your PLI VPI DPI application requires a user or vendor supplied C library or an additional system library you will need to specify that library when you link your 376 ModelSim User s Manual v6 2g February 2007 Verilog PLI VPI DPI Compiling and Linking C Applications for PLI VPI DPI PLI VPI DPI application For example to use the system math library libm specify Im to the Id command gcc c fPIC I install dir modeltech include math app c Id shared Bsymbolic E allow shlib undefined o math app so math app o Im 32 bit Solaris Platform If your PLI VPI DPI application uses anything from a system library you will need to specify that library when you link your PLI VPI DPI application For example to use the standard C library specify Ic to the Id command gcc compiler gcc c l lt install_dir gt modeltech include app c Id G Bsymbolic o app so app o lc cccompiler cc c I lt install_dir gt modeltech include app c Id G Bsymbolic o app so app o lc 64 bit Solaris Platform gcc compiler gcc c l lt install_dir gt modeltech include m64 fPIC app c gcc shared Bsymbolic o app so m64 app o This was tested with gcc 3 2 2 You may need to add the location of libgcc_s so 1 to the LD LIBRARY PATH 64 environment variable cccompiler cc v xarch v9 O l
83. an example of a simple library map file library work top v library rtlLib lrm ex top v library gateLib lrm ex adder vg library aLib lrm ex adder v Here is an example of a library map file that uses incdir library libl src dir v incdir include dir2 my incdir The name of the library map file is arbitrary You specify the library map file using the libmap argument to the vlog command Alternatively you can specify the file name as the first item on the vlog command line and the compiler will read it as a library map file The library map file must be compiled along with the Verilog source files Multiple map files are allowed but each must be preceded by the libmap argument ModelSim User s Manual v6 2g 149 February 2007 Verilog and SystemVerilog Simulation Compiling Verilog Files The library map file and the configuration can exist in the same or different files If they are separate only the map file needs the libmap argument The configuration is treated as any other Verilog source file Configurations and the Library Named work The library named work is treated specially by ModelSim see The Library Named work for details for Verilog configurations Consider the following code example config cfg design top instance top ul use work ul endconfig In this case work ul indicates to load u from the current library Verilog Generate Statements The Verilog 2001 rules for
84. and Keyboard Shortcuts Table E 6 Wave Window Keyboard Shortcuts Keystroke Up Arrow Down Arrow scrolls entire window up or down one line when mouse pointer is over waveform pane scrolls highlight up or down one line when mouse pointer is over pathname or values pane Left Arrow scroll pathname values or waveform pane left Right Arrow scroll pathname values or waveform pane right Page Up scroll waveform pane up by a page Page Down scroll waveform pane down by a page Tab Shift Tab search forward right to the next transition on the selected signal finds the next edge search backward left to the previous transition on the selected signal finds the previous edge Ctrl f Windows Ctrl s UNIX Ctrl Left Arrow Ctrl Right Arrow ModelSim User s Manual v6 2g February 2007 open the find dialog box searches within the specified field in the pathname pane for text strings scroll pathname values or waveform pane left or right by a page 409 Command and Keyboard Shortcuts Wave Window Mouse and Keyboard Shortcuts 410 ModelSim User s Manual v6 2g February 2007 Appendix F Setting GUI Preferences The ModelSim GUI is programmed using Tcl Tk It is highly customizable You can control everything from window size position and color to the text of window prompts default output filenames and so forth Most user GUI preferences are stored as Tcl v
85. and Macros DO Files List Processing List Processing In Tcl a list is a set of strings in curly braces separated by spaces Several Tcl commands are available for creating lists indexing into lists appending to lists getting the length of lists and shifting lists These commands are Table 13 3 Tcl List Commands Command syntax Description lappend var name vall val2 appends vall val2 etc to list var name lindex list name index returns the index th element of list name the first element is 0 linsert list name index vall val2 inserts vall val2 etc just before the index th element of list name list vall val2 returns a Tcl list consisting of vall val2 etc llength list name returns the number of elements in list name Irange list name first last returns a sublist of list name from index first to index last first or last may be end which refers to the last element in the list Ireplace list name first last vall replaces elements first through last with vall val2 etc vaL Two other commands Isearch and Isort are also available for list manipulation See the Tcl man pages Help Tcl Man Pages for more information on these commands Simulator Tcl Commands These additional commands enhance the interface between Tcl and ModelSim Only brief descriptions are provided here for more information and command syntax see the Reference Manual Table 13 4 Simulator Sp
86. and expense a replace or modify Software so that it becomes noninfringing b procure for you the right to continue using Software or c require the return of Software and refund to you any license fee paid less a reasonable allowance for use 9 3 Mentor Graphics has no liability to you if infringement is based upon a the combination of Software with any product not furnished by Mentor Graphics b the modification of Software other than by Mentor Graphics c the use of other than a current unaltered release of Software d the use of Software as part of an infringing process e a product that you make use or sell f any Beta Code contained in Software g any Software provided by Mentor Graphics licensors who do not provide such indemnification to Mentor Graphics customers or h infringement by you that is deemed willful In the case of h you shall reimburse Mentor Graphics for its attorney fees and other costs related to the action upon a final judgment 9 4 THIS SECTION IS SUBJECT TO SECTION 6 ABOVE AND STATES THE ENTIRE LIABILITY OF MENTOR GRAPHICS AND ITS LICENSORS AND YOUR SOLE AND EXCLUSIVE REMEDY WITH RESPECT TO ANY ALLEGED PATENT OR COPYRIGHT INFRINGEMENT OR TRADE SECRET MISAPPROPRIATION BY ANY SOFTWARE LICENSED UNDER THIS AGREEMENT TERM This Agreement remains effective until expiration or termination This Agreement will immediately terminate upon notice if you exceed the scope of license granted or otherwise fail
87. annotate myasic sdf testbench ul To also specify maximum delay values sdf annotate myasic sdf testbench ul maximum SDF to Verilog Construct Matching The annotator matches SDF constructs to corresponding Verilog constructs in the cells Usually the cells contain path delays and timing checks within specify blocks For each SDF construct the annotator locates the cell instance and updates each specify path delay or timing check that matches An SDF construct can have multiple matches in which case each matching specify statement is updated with the SDF timing value SDF constructs are matched to Verilog constructs as follows e IOPATH is matched to specify path delays or primitives Table 11 2 Matching SDF IOPATH to Verilog IOPATH posedge clk q 3 4 posedge clk gt q 0 IOPATH a y 3 4 buf ul y a The IOPATH construct usually annotates path delays If ModelSim can t locate a corresponding specify path delay it returns an error unless you use the sdf iopath to prim ok argument to vsim If you specify that argument and the module contains no path delays then all primitives that drive the specified output port are annotated e INTERCONNECT and PORT are matched to input ports Table 11 3 Matching SDF INTERCONNECT and PORT to Verilog INTERCONNECT UT 2a 5 PORT Wa Both of these constructs identify a module input or inout port and create an internal net that is a delayed vers
88. begin Clk0 1 forever begin 20 clkO clk0 end end initial begin init signal driver clk0 testbench uut blk1l clk 1 init signal driver clk0 testbench uut blk2 clk 100 1 end endmodule ModelSim User s Manual v6 2g 255 February 2007 Signal Spy init signal spy init signal spy The Sinit signal spy system task mirrors the value of a VHDL signal or Verilog register net called the src object onto an existing VHDL signal or Verilog register called the dest object This allows you to reference signals registers or nets at any level of hierarchy from within a Verilog module e g a testbench The Sinit signal spy system task only sets the value onto the destination signal and does not drive or force the value Any existing or subsequent drive or force of the destination signal by some other means will override the value set by Sinit signal spy Call only once The Sinit signal spy system task creates a persistent relationship between the source and the destination signal Hence you need to call Sinit signal spy only once for a particular pair of signals Once Sinit signal spy is called any change on the source signal will mirror on the destination signal until the end of the simulation unless the control state is set The control state determines whether the mirroring of values can be enabled disabled and what the initial state is Subsequent control of whether
89. can open a different project by selecting File Open and choosing Project Files from the Files of type drop down Close a Project Right click in the Project tab and select Close Project This closes the Project tab but leaves the Library tab open in the workspace Note that you cannot close a project while a simulation is in progress The Project Tab The Project tab contains information about the objects in your project By default the tab is divided into five columns Figure 3 10 Project Displayed in Workspace Workspace Bp nel F5 Folder adder vhd VHDL 3 06 07 06 07 35 46 PM testadder vhd VHDL 2 06 07 06 07 36 26 PM Verilog files Folder uL tcounter v y Verilog 0 06 07 06 07 36 21 PM NE counter v Verilog 1 06 07 06 07 35 56 PM verllog sim Simulation Project Library e Name The name of a file or object e Status Identifies whether a source file has been successfully compiled Applies only to VHDL or Verilog files A question mark means the file hasn t been compiled or the source file has changed since the last successful compile an X means the compile failed a check mark means the compile succeeded a checkmark with a yellow triangle behind it means the file compiled but there were warnings generated e Type The file type as determined by registered file types on Windows or the type you specify when you add the file to the project e Order The order in which the file
90. cece eee e 353 Using Location Mapp 22c69audedes isedap kedi a E EE RE RF RIRS POE RENS 353 Pathnaime Syntax ioca es exp bp RR es REED Ra MERE XR dd eee 354 How Location Mapping Works ao bez ruer eteP xc Rer Wick he serene caeeeads 354 Mapping with TCL Variables d ves e ue erm y RERCER ORO eH are Rd rH WERE 354 Appendix C Error and Warning Messages 644 604040 4c 4006 460466 16 ee DP East dee ias ela 355 Message System 24 wove re dec bers eee tied utes E ee beset abe decus Bed Ba dede Mes 355 Message Format EPETP 1 TTM 355 Getting More Information diac RICE ode ee LO ERO E Rs dedo cans 355 Changing Message Severity Level 222 2 2ce24eseudees ee beers p E EET 356 Suppressing Warning Messages sax vas Pauw ae rRPEREPadG Pd exGdoeEES XR BRAXEPRSATPA 356 Suppressing VCOM Warning Messages 0 00 e cece eee he 356 Suppressing VLOG Warning Messages uo ehe RR RESI RR RR 357 Suppressing VSIM Warning Messages 0 0 cece eee eee eee teens 357 3390 MMD rm 357 Miscellaneous Messages 4s es Xx Cx RR ERR ERA PRESE Ra e EAE Sam e EAT EE 359 Enforcing Strict 1076 Compliance 2 0 0 teens 362 Appendix D ModelSim User s Manual v6 29 11 February 2007 Verilog PLUVPUDPI i swseeszacskuesk e ROT EXS eX ors Implementation Information lsleleeeeeeeeese g Compiler Support for use with PLI VPI DPI Registering PLI Applications llle Registering VPI Application
91. click a line number and select Add Remove Bookmark To remove a bookmark right click the line number and select Add Remove Bookmark again Customizing the Source Window You can customize a variety of settings for Source windows For example you can change fonts spacing colors syntax highlighting and so forth To customize Source window settings select Tools Edit Preferences This opens the Preferences dialog Select Source Windows from the Window List 68 ModelSim User s Manual v6 2g February 2007 Simulator Windows Source Window Figure 2 26 Preferences Dialog for Customizing Source Window Preferences By Window By Name x dol Window List Source Windows Color Scheme Dataflow Windows Category List Windows A A Main Window don Memory Windows Document Types Active Process Window Default Objects Window Printing Source o Structure Windows konte Locals Window Spacing Wave Windows XML CRE tel Parsing Printing Fonts Spacing Syntax Highlighting Code Browser verilog Parsing Printing Fonts Spacing Syntax Highlighting Code Browser vhdl verilog Syntax Highlighting IV Enable Syntax Highlighting IV Highlight keyword when typed IV Highlight matching construct when typed Syntax Compiler Directiv Function name Gate instance nam Keyword Macro substitutio Misspelled word Module instance n Module name et rae Keywords Sam
92. compile and link your PLI VPI DPI C applications so that they can be loaded by ModelSim Various native C C compilers are supported on different platforms The gcc compiler is supported on all platforms The following PLI VPI DPI routines are declared in the include files located in the ModelSim install dir modeltech include directory e acc user h declares the ACC routines e veriuser h declares the TF routines e vpi user h declares the VPI routines e svdpi h declares DPI routines ModelSim User s Manual v6 2g 373 February 2007 Verilog PLI VPI DPI Compiling and Linking C Applications for PLI VPI DPI The following instructions assume that the PLI VPI or DPI application is in a single source file For multiple source files compile each file as specified in the instructions and link all of the resulting object files together with the specified link instructions Although compilation and simulation switches are platform specific loading shared libraries is the same for all platforms For information on loading libraries for PLI VPI see PLI VPI file loading For DPI loading instructions see DPI File Loading For all UNIX Platforms The information in this section applies to all UNIX platforms app so If app so is not in your current directory you must tell the OS where to search for the shared object You can do this one of two ways e Add a path before app so in the command line option or control variabl
93. compile in ModelSim Incremental Compilation ModelSim Verilog supports incremental compilation of designs Unlike other Verilog simulators there is no requirement that you compile the entire design in one invocation of the compiler You are not required to compile your design in any particular order unless you are using System Verilog packages see note below because all module and UDP instantiations and external hierarchical references are resolved when the design is loaded by the simulator ModelSim User s Manual v6 2g 141 February 2007 Verilog and SystemVerilog Simulation Compiling Verilog Files Note 2222 LLLLL L 3 Compilation order may matter when using SystemVerilog packages As stated in the IEEE std p1800 2005 LRM section entitled Referencing data in packages which states Packages must exist in order for the items they define to be recognized by the scopes in which they are imported Incremental compilation is made possible by deferring these bindings and as a result some errors cannot be detected during compilation Commonly these errors include modules that were referenced but not compiled incorrect port connections and incorrect hierarchical references Example 6 2 Incremental Compilation Example Contents of testbench sv module testbench timeunit 1ns timeprecision 10ps bit d 1 clk 0 wire q initial for int cycles 0 cycles lt 100 cycles 100 clk clk
94. current working directory The compile uselibs argument does not affect this usage of uselib For example the following directive uselib dirz h vendorA libextz v is equivalent to the following command line arguments y h vendorA libext v Since the uselib directives are embedded in the Verilog source code there is more flexibility in defining the source libraries for the instantiations in the design The appearance of a uselib directive in the source code explicitly defines how instantiations that follow it are resolved completely overriding any previous uselib directives compile_uselibs Argument Use the compile uselibs argument to vlog to reference uselib directives The argument finds the source files referenced in the directive compiles them into automatically created object libraries and updates the modelsim ini file with the logical mappings to the libraries When using compile uselibs ModelSim determines into which directory to compile the object libraries by choosing in order from the following three values e The directory name specified by the compile uselibs argument For example compile_uselibs mydir e The directory specified by the MTI_USELIB_DIR environment variable see Environment Variables e A directory named mti_uselibs that is created in the current working directory The following code fragment and compiler invocation show how two different modules that have the same name can be instant
95. data and clk when the register release flag transitions to a 1 Both calls will send a message to the transcript stating which signal was released and when 260 ModelSim User s Manual v6 2g February 2007 Signal Spy signal release module testbench reg release flag always 8 posedge release flag begin signal r ase testbench dut blkl1 data 1 signal release testbench dut blk1 clk 1 end endmodule ModelSim User s Manual v6 2g 261 February 2007 Signal Spy signal release 262 ModelSim User s Manual v6 29 February 2007 Chapter 11 Standard Delay Format SDF Timing Annotation This chapter discusses ModelSim s implementation of SDF Standard Delay Format timing annotation Included are sections on VITAL SDF and Verilog SDF plus troubleshooting Verilog and VHDL VITAL timing data can be annotated from SDF files by using the simulator s built in SDF annotator Note SDF timing annotations can be applied only to your FPGA vendor s libraries all other libraries will simulate without annotation Specifying SDF Files for Simulation ModelSim supports SDF versions 1 0 through 4 0 except the NETDELAY statement The simulator s built in SDF annotator automatically adjusts to the version of the file Use the following vsim command line options to specify the SDF files the desired timing values and their associated design instances sdfmin lt instance gt lt filename gt
96. declared in veriuser h as follows void mti RegisterUserTF p tfcell usertf The storage for each usertf entry passed to the simulator must persist throughout the simulation because the simulator de references the usertf pointer to call the callback functions We recommend that you define your entries in an array with the last entry set to O If the array is named veriusertfs as is the case for linking to Verilog XL then you don t have to provide an 366 ModelSim User s Manual v6 2g February 2007 Verilog PLI VPI DPI Registering VPI Applications init_usertfs function and the simulator will automatically register the entries directly from the array the last entry must be 0 For example S tfcell veriusertfs usertask 0 0 0 abc calltf 0 Sabc usertask 0 0 0 xyz calltf 0 Sxyz 0 last entry must be 0 Alternatively you can add an init_usertfs function to explicitly register each entry from the array void init_usertfs p_tfcell usertf veriusertfs whil usertf type mti RegisterUserTF usertf t It is an error if a PLI shared library does not contain a veriusertfs array or an init_usertfs function Since PLI applications are dynamically loaded by the simulator you must specify which applications to load each application must be a dynamically loadable library see Compiling and Linking C Applications for PLI VPI DPI The PLI applications are specified as follows not
97. default compilation results are stored in the work library The work library is actually a subdirectory named work This subdirectory contains a special file named info Do not create libraries using UNIX commands always use the vlib See Design Libraries for additional information on working with libraries Invoking the Verilog Compiler The Verilog compiler vlog compiles Verilog source code into retargetable executable code The library format is compatible across all supported platforms and you can simulate your design on any platform without having to recompile your design As the design compiles the resulting object code for modules and UDPs is generated into a library As noted above the compiler places results into the work library by default You can specify an alternate library with the work argument Example 6 1 Invocation of the Verilog Compiler Here is a sample invocation of vlog vlog top v libext v u y vlog lib After compiling top v vlog will scan the vlog lib library for files with modules with the same name as primitives referenced but undefined in top v The use of libext v u implies filenames with a v or u suffix any combination of suffixes may be used Only referenced definitions will be compiled Parsing SystemVerilog Keywords With standard Verilog files lt filename gt v vlog will not automatically parse SystemVerilog keywords SystemVerilog keywords are parsed when any of the follow
98. detected by setting the break on assertion level to Error To enable hazard detection you must invoke vlog with the hazards argument when you compile your source code and you must also invoke vsim with the hazards argument when you simulate Note _ Enabling hazards implicitly enables the compat argument As a result using this argument may affect your simulation results Hazard Detection and Optimization Levels In certain cases hazard detection results are affected by the optimization level used in the simulation Some optimizations change the read write operations performed on a variable if the transformation is determined to yield equivalent results Since the hazard detection algorithm doesn t know whether or not the read write operations can affect the simulation results the optimizations can result in different hazard detection results Generally the optimizations reduce the number of false hazards by eliminating unnecessary reads and writes but there are also optimizations that can produce additional false hazards Limitations of Hazard Detection e Reads and writes involving bit and part selects of vectors are not considered for hazard detection The overhead of tracking the overlap between the bit and part selects is too high e AWRITE WRITE hazard is flagged even if the same value is written by both processes e A WRITE READ or READ WRITE hazard is flagged even if the write does not modify the va
99. determine the actual delay observed Most Verilog cells use path delays exclusively with the distributed delays set to zero For example module and2 y a b input a b output y and y a b specify a gt y b gt y endspecify endmodule In the above two input and gate cell the distributed delay for the and primitive is zero and the actual delays observed on the module ports are taken from the path delays This is typical for most cells but a complex cell may require non zero distributed delays to work properly Even so these delays are usually small enough that the path delays take priority over the distributed delays The rule is that if a module contains both path delays and distributed delays then the larger of the two delays for each path shall be used as defined by the IEEE Std 1364 This is the default behavior but you can specify alternate delay modes with compiler directives and 162 ModelSim User s Manual v6 2g February 2007 Verilog and SystemVerilog Simulation System Tasks and Functions arguments These arguments and directives are compatible with Verilog XL Compiler delay mode arguments take precedence over delay mode directives in the source code Distributed Delay Mode In distributed delay mode the specify path delays are ignored in favor of the distributed delays Select this delay mode with the delay mode distributed compiler argument or the delay mode distributed compiler directive Pat
100. digits may be present Backslash substitution is not performed on words enclosed in braces except for backslash newline as described above Ifa hash character appears at a point where Tcl is expecting the first character of the first word of a command then the hash character and the characters that follow it up through the next newline are treated as a comment and ignored The comment character only has significance when it appears at the beginning of a command Each character is processed exactly once by the Tcl interpreter as part of creating the words of a command For example if variable substitution occurs then no further substitutions are performed on the value of the variable the value is inserted into the word verbatim If command substitution occurs then the nested command is processed entirely by the recursive call to the Tcl interpreter no substitutions are performed before making the recursive call and no additional substitutions are performed on the result of the nested script ModelSim User s Manual v6 2g February 2007 Tcl and Macros DO Files Tcl Command Syntax 11 Substitutions do not affect the word boundaries of a command For example during variable substitution the entire value of the variable becomes part of a single word even if the variable s value contains spaces If Command Syntax The Tcl if command executes scripts conditionally Note that in the syntax below the question mark indicate
101. directory project file printer defaults and other user customized GUI characteristics modelsim tcl project name mpf contains user customized settings for fonts colors prompts other GUI characteristics maintained for backwards compatibility with older versions see The modelsim tcl File if available loads last project file which is specified in the registry Windows or HOME modelsim UNIX see What are Projects for details on project settings ModelSim User s Manual v6 29 February 2007 419 System Initialization Environment Variables Accessed During Startup Environment Variables Accessed During Startup The table below describes the environment variables that are read during startup They are listed in the order in which they are accessed For more information on environment variables see Environment Variables Table G 2 Environment Variables Accessed During Startup Environment variable MODEL TECH Purpose set by ModelSim to the directory in which the binary executables reside e g modeltech lt platform gt MODEL_TECH_OVERRIDE provides an alternative directory for the binary executables MODEL_TECH is set to this path MODELSIM identifies the pathname of the modelsim ini file MGC WD identifies the Mentor Graphics working directory MGC LOCATION MAP MODEL TECH TCL identifies the pathname of the location map file set by ModelSim if not defined
102. e Default off 0 NoCaseStaticError This variable changes case statement static errors to warnings e Value Range 0 1 e Default off 0 NoDebug This variable disables turns off inclusion of debugging info within design units e Value Range 0 1 e Default off 0 NolndexCheck This variable disables run time index checks e Value Range 0 1 e Default off 0 NoOthersStaticError This variable disables errors caused by aggregates that are not locally static e Value Range 0 1 e Default off 0 NoRangeCheck This variable disables run time range checking e Value Range 0 1 e Default off 0 NoVital This variable disables acceleration of the VITAL packages e Value Range 0 1 e Default off 0 ModelSim User s Manual v6 2g 325 February 2007 Simulator Variables Simulator Control Variables NoVitalCheck This variable disables VITAL compliance checking e Value Range 0 1 e Default off 0 Optimize_1164 This variable disables optimization for the IEEE std_logic_1164 package e Value Range 0 1 e Default on 1 PedanticErrors This variable overrides NoCaseStaticError and NoOthersStaticError e Value Range 0 1 e Default off 0 Quiet This variable disables the loading messages e Value Range 0 1 e Default off 0 RequireConfigForAllDefaultBinding This variable instructs the compiler not to generate a default binding during compilation e Value Range 0 1 e Default off 0 Show_Lint This variable ena
103. enable the breakpoint To delete the breakpoint completely right click the red circle and select Remove Breakpoint Other options on the context menu include e Disable Enable Breakpoint Deactivate or activate the selected breakpoint e Edit Breakpoint Open the File Breakpoint dialog to change breakpoint arguments e Edit All Breakpoints Open the Modify Breakpoints dialog Checking Object Values and Descriptions There are two quick methods to determine the value and description of an object displayed in the Source window e select an object then right click and select Examine or Describe from the context menu e pause over an object with your mouse pointer to see an examine pop up ModelSim User s Manual v6 2g 67 February 2007 Simulator Windows Source Window Select Tools Options Examine Now or Tools Options Examine Current Cursor to choose at what simulation time the object is examined or described You can also invoke the examine and or describe commands on the command line or in a macro Marking Lines with Bookmarks Source window bookmarks are blue circles that mark lines in a source file These graphical icons may ease navigation through a large source file by highlighting certain lines As noted above in the discussion about finding text in the Source window you can insert bookmarks on any line containing the text for which you are searching The other method for inserting bookmarks is to right
104. example vlib work This creates a library named work By default compilation results are stored in the work library The work library is actually a subdirectory named work This subdirectory contains a special file named info Do not create libraries using UNIX MS Windows or DOS commands always use the vlib command See Design Libraries for additional information on working with libraries ModelSim User s Manual v6 2g 109 February 2007 VHDL Simulation Compiling VHDL Files Invoking the VHDL Compiler ModelSim compiles one or more VHDL design units with a single invocation of vcom the VHDL compiler The design units are compiled in the order that they appear on the command line For VHDL the order of compilation is important you must compile any entities or configurations before an architecture that references them You can simulate a design containing units written with 1076 1987 1076 1993 and 1076 2002 versions of VHDL To do so you will need to compile units from each VHDL version separately The vcom command compiles using 1076 2002 rules by default use the 87 or 93 argument to vcom to compile units written with version 1076 1987 or 1076 1993 respectively You can also change the default by modifying the VHDL93 variable in the modelsim ini file see Simulator Control Variables for more information Dependency Checking Dependent design units must be reanalyzed when the design units they depend on are cha
105. file depend on which options you specify when creating the file Default Behavior By default ModelSim generates output according to IEEE 1364 2005 The standard states that the values 0 both input and output are active with value 0 and 1 both input and output are active with value 1 are conflict states The standard then defines two strength ranges e Strong strengths 7 6 and 5 e Weak strengths 4 3 2 1 The rules for resolving values are as follows e Ifthe input and output are driving the same value with the same range of strength the resolved value is 0 or 1 and the strength is the stronger of the two e If the input is driving a strong strength and the output is driving a weak strength the resolved value is D d U or u and the strength is the strength of the input e If the input is driving a weak strength and the output is driving a strong strength the resolved value is L 1 H or h and the strength is the strength of the output 288 ModelSim User s Manual v6 2g February 2007 Value Change Dump VCD Files Capturing Port Driver Data Ignoring Strength Ranges You may wish to ignore strength ranges and have ModelSim handle each strength separately Any of the following options will produce this behavior e Use the no_strength_range argument to the vcd dumpports command e Use an optional argument to dumpports see Extended dumpports Syntax below e Use the dumpports no_strength_range argument to vsim command
106. following O default 1 deposit 2 drive or 3 freeze The default is default which is freeze for unresolved objects or drive for resolved objects See the force command for further details on force type cancel period Optional integer real time Cancels the signal force command after the specified period of time units Cancellation occurs at the last simulation delta cycle of a time unit A value of zero cancels the force at the end of the current time period Default is 1 A negative value means that the force will not be cancelled ModelSim User s Manual v6 2g February 2007 Signal Spy signal force e verbose Optional integer Possible values are 0 or 1 Specifies whether you want a message reported in the Transcript stating that the value is being forced on the dest_object at the specified time Default is 0 no message Related tasks init_signal_driver init_signal_spy signal_release Limitations e You cannot force bits or slices of a register you can force only the entire register e Verilog memories arrays of registers are not supported signal_force Example This example forces reset to a 1 from time 0 ns to 40 ns At 40 ns reset is forced to a 0 200000 ns after the second signal force call was executed timescale 1 ns 1 ns module testbench initial begin signal force testbench uut blkl reset 1 0 3 1 signal force testbench uut blkl reset 0 40 3 200000 1
107. forces the value specified onto an existing VHDL signal or Verilog register net called the dest object This allows you to force signals registers or nets at any level of the design hierarchy from within a Verilog module e g a testbench A S signal force works the same as the force command with the exception that you cannot issue a repeating force The force will remain on the signal until a signal release a force or release command or a subsequent signal force is issued signal force can be called concurrently or sequentially in a process Syntax signal force dest object value rel time force type cancel period verbose Returns Nothing Arguments 258 dest object Required string A full hierarchical path or relative downward path with reference to the calling block to an existing VHDL signal or Verilog register net Use the path separator to which your simulation is set 1 e or A full hierarchical path must begin with a or The path must be contained within double quotes value Required string Specifies the value to which the dest object is to be forced The specified value must be appropriate for the type rel time Optional integer real or time Specifies a time relative to the current simulation time for the force to occur The default is 0 force type Optional integer Specifies the type of force that will be applied The value must be one of the
108. format of messages for VHDL Note assertions If undefined AssertionFormat is used unless assertion causes a breakpoint in which case AssertionFormatBreak is used 330 ModelSim User s Manual v6 2g February 2007 Simulator Variables Simulator Control Variables e Value Range Refer to Table A 2 e Default S R n Time T Iteration D I n AssertionFormatWarning This variable defines the format of messages for VHDL Warning assertions If undefined AssertionFormat is used unless assertion causes a breakpoint in which case AssertionFormatBreak is used e Value Range Refer to Table A 2 e Default S R n Time T Iteration D I n BreakOnAssertion This variable defines the severity of VHDL assertions that cause a simulation break It also controls any messages in the source code that use assertion_failure_ For example since most runtime messages use some form of assertion_failure_ any runtime error will cause the simulation to break if the user sets BreakOnAssertion to 2 You can set this variable interactively in the GUI refer to Setting Simulator Control Variables With The GUI e Value Range 0 note 1 warning 2 error 3 failure 4 fatal e Default 3 failure CheckPlusargs This variable defines the simulator s behavior when encountering unrecognized plusargs e Value Range 0 ignores 1 issues warning simulates while ignoring 2 issues error exits e Default 0 ignores CheckpointC
109. identifies the pathname of all Tcl libraries installed with ModelSim HOME identifies your login directory UNIX only MGC HOME identifies the pathname of the MGC tool suite TCL LIBRARY identifies the pathname of the Tcl library set by ModelSim to the same pathname as MODEL TECH TCL must point to libraries supplied by Model Technology TK LIBRARY identifies the pathname of the Tk library set by ModelSim to the same pathname as MODEL TECH TCL must point to libraries supplied by Model Technology ITCL LIBRARY identifies the pathname of the incr Tcl library set by ModelSim to the same path as MODEL TECH TCL must point to libraries supplied by Model Technology ITK LIBRARY identifies the pathname of the incr Tk library set by ModelSim to the same pathname as MODEL TECH TCL must point to libraries supplied by Model Technology VSIM LIBRARY identifies the pathname of the Tcl files that are used by ModelSim set by ModelSim to the same pathname as MODEL TECH TCL must point to libraries supplied by Model Technology MTI COSIM TRACE creates an mti trace cosim file containing debugging information about FLI PLI VPI function calls set to any value before invoking the simulator MTI LIB DIR 420 identifies the path to all Tcl libraries installed with ModelSim ModelSim User s Manual v6 2g February 2007 System Initialization Initialization Sequence Table G 2 Environm
110. in Registering PLI Applications To prepare the application for ModelSim Verilog you must compile the veriuser c file and link it to the object files to create a dynamically loadable object see Compiling and Linking C Applications for PLI VPI DPI For example if you have a veriuser c file and a library archive libapp a file that contains the application s object files then the following commands should be used to create a dynamically loadable object for the Solaris operating system 9o cc c l lt install_dir gt modeltech include veriuser c 96 Id G o app sl veriuser o libapp a The PLI application is now ready to be run with ModelSim Verilog All that s left is to specify the resulting object file to the simulator for loading using the Veriuser entry in the modesim ini file the pli simulator argument or the PLIOBJS environment variable see Registering PLI Applications 392 ModelSim User s Manual v6 2g February 2007 Note Verilog PLI VPI DPI Support for VHDL Objects 3 On the HP700 platform the object files must be compiled as position independent code by using the z compiler argument Since the object files supplied for Verilog XL may be compiled for static linking you may not be able to use the object files to create a dynamically loadable object for ModelSim Verilog In this case you must get the third party application vendor to supply the object files compiled as position independent code Support for VHDL Objec
111. in Tab Groups C madeltech examples memory verilog dp syn ram v 4 ln 00000000 00010001100101000 E l Copyright Model Technology 00000001 OOOO00000000000111 oo000002 OooOoOooooOoOOOOOO0011 00000003 00111011001111010 OO000004 xxxxxxxxxxxxxxxxx OOOO000S xxxxxxxxxxxxxxxxx Corporation company Z004 2 3 4 timescale lns lns 5 module idp syn ram rtl 6 8 fiparameter data width 8 00000006 xxxxxxxxxxxxxxxxx parameter addr width 3 00000007 XxXXXXXXXXXXXXXXXX input addr width 1 0 i 00000008 xxxxxxxXXxxxxxxxxx 9 input addr width 1 0 o 00000009 xxxxxxxxxxxxxxxxx 10 input data width 1 0 d o000000a xxxxxxxxxxxxxxxxx 11 input i O000000b XXXXXXXXXXXXXXXXX lz input o 0000000c xxxxxxxxxxXxxxXxxx Ii So mpi RECA Tren nem nf The commands for creating and organizing tab groups are accessed by right clicking on any window tab The table below describes the commands associated with tab groups Table 2 5 Commands for Tab Groups Command Description New Tab Group Creates a new tab group containing the selected tab Move Next Group Moves the selected tab to the next group in the MDI Move Prev Group Moves the selected tab to the previous group in the MDI View gt Vertical Arranges tab groups top to bottom vertical or Horizontal right to left horizontal Note that you can also move the tabs within a tab group by dragging them
112. in the Find field The Match case selection will enforce case sensitive matching of your entry And the Zoom to selection will zoom in to the item in Find field Instance C Signal The Find All button allows you to find and highlight all occurrences of the item in the Find field If Zoom to is checked the view will change such that all selected items are viewable If Zoom to is not selected then no change is made to zoom or scroll state Printing and Saving the Display Saving a eps File and Printing the Dataflow Display from UNIX Select File gt Print Postscript to setup and print the Dataflow display in UNIX or save the waveform as a eps file on any platform ModelSim User s Manual v6 2g 233 February 2007 Tracing Signals with the Dataflow Window Printing and Saving the Display Figure 9 6 The Print Postscript Dialog Printer Print d f d Ip1 Print comman p d Ip vi See C File name dataflow ps Browse Paper Paper size Letter vi Border Width 0 4 m Font Helvetica vi DK Cancel Printing from the Dataflow Display on Windows Platforms Select File gt Print to print the Dataflow display or to save the display to a file Figure 9 7 The Print Dialog CREE 0 m Printer Name HP LaserJet 5L Properties Status Ready Type HP LaserJet 5L Where LPT1 Comment Print to file Print range Copies All Number of copies 1 C Pages from
113. in the ModelSim installation directory in r 6000 mti exports If your PLI VPI application uses anything from a system library you ll need to specify that library when you link your PLI VPI application For example to use the standard C library specify Ic to the Id command The resulting object must be marked as shared reentrant using these gcc or cc compiler commands for AIX 4 x e GNU C compiler version gcc 3 2 or later g c l zinstall dir modeltech include app cpp Id o app s app o bE app exp bl install dir2 modeltech rs6000 mti exports bM SRE bnoentry lc e VisualAge C Compiler cc c I lt install_dir gt modeltech include app cpp Id o app s app o bE app exp bl install dir modeltech rs6000 mti exports bM SRE bnoentry lc The app exp file must export the PLI VPI initialization function or table For the PLI the exported symbol should be init usertfs Alternatively if there is no init usertfs function then the exported symbol should be veriusertfs For the VPI the exported symbol should be vlog startup routines These requirements ensure that the appropriate symbol is exported and thus ModelSim can find the symbol when it dynamically loads the shared object 384 ModelSim User s Manual v6 2g February 2007 Verilog PLI VPI DPI Compiling and Linking C Applications for PLI VPI DPI For DPI Imports When linking the shared objects be sure to specify bE lt isymfile gt option on
114. in the wave window b Select the Tools Group menu item The Wave Group Create dialog will appear Figure 8 17 Fill in the name of the group in the Group Name field Wave Group Create x Group Name om Group Height OK Cancel c Click Ok The new wave group will be denoted by a red diamond in the Wave window pathnames Figure 8 18 Wave groups denoted by red diamond p sim test sm addr 0000110011 0000110011 E sim ztest_sm loop MRKHRKRRKRRERRARERED mygroup sim test_sm i sim test_sm rd_ sim test_sm wr_ Now 746 ns to 750200 ps Now 750 ns Delta 2 2 Use the group argument to the add wave command Example 1 The following command will create a group named mygroup containing three items add wave group mygroup sigl sig2 sig3 Example 2 The following command will create an empty group named mygroup add wave group mygroup ModelSim User s Manual v6 2g 209 February 2007 Waveform Analysis Wave Groups Deleting or Ungrouping a Wave Group If a wave group is selected and cut or deleted the entire group and all its contents will be removed from the wave window Likewise the delete wave command will remove the entire group if the group name is specified If a wave group is selected and the Tools Ungroup menu item is selected the group will be removed and all of its contents will remain in the Wave window in existing order Adding Items to an Existing Wav
115. individual parameters across multiple files in previous versions you could only set parameters one file at a time e enable what if analysis you can copy a project manipulate the settings and rerun it to observe the new results e reload the initial settings from the project mpf file every time the project is opened Project Conversion Between Versions Projects are generally not backwards compatible for either number or letter releases When you open a project created in an earlier version you will see a message warning that the project will be converted to the newer version You have the option of continuing with the conversion or cancelling the operation As stated in the warning message a backup of the original project is created before the conversion occurs The backup file is named project name mpf bak and is created in the same directory in which the original project is located Getting Started with Projects This section describes the four basic steps to working with a project e Step 1 Creating a New Project This creates a mpf file and a working library e Step 2 Adding Items to the Project Projects can reference or include source files folders for organization simulations and any other files you want to associate with the project You can copy files into the project directory or simply create mappings to files in other locations e Step3 Compiling the Files This checks syntax and semantics and crea
116. input ports 268 interconnect delays 273 IOPATH matching to specify path delays 268 iteration limit infinite zero delay loops 118 IterationLimit ini file variable 334 K keyboard shortcuts List window 407 Main window 404 Source window 404 Wave window 408 keywords SystemVerilog 140 L L work 144 language templates 65 language versions VHDL 111 libraries 64 bit and 32 bit in same library 107 creating 101 design libraries creating 101 design library types 99 design units 99 group use setting up 104 430 IEEE 106 importing FPGA libraries 107 mapping from the command line 103 from the GUI 103 hierarchically 346 search rules 104 modelsim lib 124 moving 104 multiple libraries with common modules 144 naming 102 predefined 105 refreshing library images 106 resource libraries 90 std library 105 Synopsys 106 Verilog 144 VHDL library clause 105 working libraries 99 working vs resource 24 working with contents of 101 library map file Verilog configurations 149 library mapping overview 25 library maps Verilog 2001 149 library simulator state variable 349 library definition 24 License ini file variable 335 licensing License variable in ini file 335 List pane see also pane List pane List window 53 190 setting triggers 219 see also windows List window LM LICENSE FILE environment variable 315 loading the design overview 26 Locals window 55 s
117. is the new value for the register or net The value remains until there is a subsequent driver transaction or another deposit task for the same register or net This system task operates identically to the ModelSim force deposit command disable_warnings lt keyword gt lt module_instance gt This system task instructs ModelSim to disable warnings about timing check violations or triregs that acquire a value of X due to charge decay keyword may be decay or timing You can specify one or more module instance names If you don t specify a module instance ModelSim disables warnings for the entire simulation enable warnings keyword module instance This system task enables warnings about timing check violations or triregs that acquire a value of X due to charge decay keyword may be decay or timing You can specify one or more module instance names If you don t specify a module instance ModelSim enables warnings for the entire simulation system command This system function takes a literal string argument executes the specified operating system command and displays the status of the underlying OS process Double quotes are required for the OS command For example to list the contents of the working directory on Unix system ls 1 ModelSim User s Manual v6 2g February 2007 k A Verilog and SystemVerilog Simulation System Tasks and Functions Return value of t
118. it back to a multi state setting without cancelling out of the dialog Once you click OK ModelSim will set the option the same for all selected files e If you select a combination of VHDL and Verilog files the options you set on the VHDL and Verilog tabs apply only to those file types ModelSim User s Manual v6 2g 95 February 2007 Projects Specifying File Properties and Project Settings Project Settings To modify project settings right click anywhere within the Project tab and select Project Settings Figure 3 19 Project Settings Dialog Project Settings x m Compile Output Display compiler output v Save compile report m Location map Convert pathnames to softnames 1 Additional Properties v Automatically reopen all source files when opening a project m Double click Behavior File Type VHDL vi Action Edi vi Custom DK Cancel Converting Pathnames to Softnames for Location Mapping If you are using location mapping you can convert a relative pathname full pathname or pathname with an environment variable to a softname A softname is a term for a pathname that uses the location mapping MGC LOCATION MAD It looks like a pathname containing an environment variable however it is resolved using the location map rather than the environment To convert the pathname to a softname for projects using location mapping follow these steps 1 Right click a
119. macro supported by Visual C You can place this macro before every DPI import task or function declaration in your C source All the marked functions will be available for use by vsim as DPI import tasks and functions DPI Flow for Exported Tasks and Functions on Windows Platforms Since the Windows platform lacks the necessary runtime linking capabilities you must perform an additional manual step in order to prepare shared objects containing calls to exported SystemVerilog tasks or functions You need to invoke a special run of vsim The command is as follows vsim top du list dpiexportobj lt objname gt other args The dpiexportobj generates an object file lt objname gt obj that contains glue code for exported tasks and functions You must add that object file to the link line for your dll listed after the other object files For example a link line for MinGW would be gcc shared Bsymbolic o app dll app obj lt objname gt obj L lt install_dir gt modeltech win32 Imtipli and a link line for Visual C would be ModelSim User s Manual v6 2g 375 February 2007 Verilog PLI VPI DPI Compiling and Linking C Applications for PLI VPI DPI link dll export init function app obj lt objname gt obj install dir modeltechWwin32 mtipli lib out app dll 32 bit Linux Platform If your PLI VPI DPI application uses anything from a system library you will need to specify that library when you link your PLI VPI DPI ap
120. mfcu argument to vlog e For all compilations by setting the variable MultiFileCompilationUnit 1 in the modelsim ini file By using either of these methods you allow declarations in unit scope to remain in effect throughout the compilation of all files In case you have made MFCU the default behavior by setting MultiFileCompilationUnit 1 in your modelsim ini file it is possible to override the default behavior on specific compilations by using the sfcu argument to vlog Macro Definitions and Compiler Directives in Compilation Unit Scope According to the SystemVerilog IEEE Std p1800 2005 LRM the visibility of macro definitions and compiler directives span the lifetime of a single compilation unit By default this means the definitions of macros and settings of compiler directives terminate at the end of each source file They do not carry forward from one file to another except when a module interface or package declaration begins in one file and ends in another file In that case the compilation unit spans from the file containing the beginning of the definition to the file containing the end of the definition See Declarations in Compilation Unit Scope for instructions on how to control vlog s handling of compilation units Note Compiler directives revert to their default values at the end of a compilation unit If a compiler directive is specified as an option to the compiler this setting is used for all compilat
121. must match the port names of the Entity ModulelProcess in the case of the process it s the signal names that the process reads writes 236 ModelSim User s Manual v6 2g February 2007 Tracing Signals with the Dataflow Window Configuring Window Options Note __ LLLLLL 3 When you create or modify a symlib file you must generate a file index This index is how the Nlview widget finds and extracts symbols from the file To generate the index select Tools Create symlib index Dataflow window and specify the symlib file The file will be rewritten with a correct up to date index Configuring Window Options You can configure several options that determine how the Dataflow window behaves The settings affect only the current session Select Tools gt Options to open the Dataflow Options dialog box Figure 9 9 Configuring Dataflow Options Dataflow Options s General options Warning options v Hide cells v Keep Dataflow Keep previous contents when adding new nets or Show Hierarchy instances to the Dataflow window I Bottom inout pins Disable Sprout Select equivalent nets Log nets IV Select Environment v Automatic Add to Wave OK Cancel ModelSim User s Manual v6 2g 237 February 2007 Tracing Signals with the Dataflow Window Configuring Window Options 238 ModelSim User s Manual v6 2g February 2007 Chapter 10 Signal Spy The Verilog lan
122. o If the Dataflow window is undocked select Trace gt TraceX Trace gt TraceX Delay Trace gt ChaseX or Trace gt ChaseX Delay These commands behave as follows e TraceX TraceX Delay Steps back to the last driver of an X value TraceX Delay works similarly but it steps back in time to the last driver of an X value TraceX should be used for RTL designs TraceX Delay should be used for gate level netlists with back annotated delays e ChaseX ChaseX Delay Jumps through a design from output to input following X values ChaseX Delay acts the same as ChaseX but also moves backwards in time to the point where the output value transitions to X ChaseX should be used for RTL designs ChaseX Delay should be used for gate level netlists with back annotated delays Finding Objects by Name in the Dataflow Window for signal net or register names or an instance of a component This opens the Find in Select Edit gt Find from the menu bar or click the Find icon in the toolbar to search Dataflow dialog Figure 9 5 232 ModelSim User s Manual v6 2g February 2007 Tracing Signals with the Dataflow Window Printing and Saving the Display Figure 9 5 Find in Dataflow Dialog x Find Next Exact Match case Find All Zoom to Close With the Find in Dataflow dialog you can limit the search by type to instances or signals You select Exact to find an item that exactly matches the entry you ve typed
123. o ta o C Selection E ES E 234 ModelSim User s Manual v6 29 February 2007 Tracing Signals with the Dataflow Window Configuring Page Setup Configuring Page Setup Clicking the Setup button in the Print Postscript or Print dialog box allows you to configure page view highlight color mode orientation and paper options this is the same dialog that opens via File Page setup Symbol Figure 9 8 The Dataflow Page Setup Dialog View Highlight C Ful Off Current View C On r Color Mode Orientation Color jj Portrait C Invert Color A Landscape Mono Paper Font Helvetica vi OK Cancel Mapping The Dataflow window has built in mappings for all Verilog primitive gates i e AND OR etc For components other than Verilog primitives you can define a mapping between processes and built in symbols This is done through a file containing name pairs one per line where the first name is the concatenation of the design unit and process names DUname Processname and the second name is the name of a built in symbol For example xorg on ly pl XOR org only pl OR andg on ly pl AND Entities and modules are mapped the same way ModelSim User s Manual v6 2g 235 February 2007 Tracing Signals with the Dataflow Window Symbol Mapping AND1 AND AND2 AND A 2 input and gate AND3 AND AND4 AND AND5 AND AND6 AND x
124. of a typical mapping For mapping from a logical pathname back to the physical pathname ModelSim expects an environment variable to be set for each logical pathname with the same name ModelSim reads the location map file when a tool is invoked If the environment variables corresponding to logical pathnames have not been set in your shell ModelSim sets the variables to the first physical pathname following the logical pathname in the location map For example if you don t set the SRC environment variable ModelSim will automatically set it to home vhdl src Mapping with TCL Variables Two Tcl variables may also be used to specify alternative source file paths SourceDir and SourceMap You would define these variables in a modelsim tcl file See the The modelsim tcl File for details 354 ModelSim User s Manual v6 2g February 2007 Appendix C Error and Warning Messages Message System The ModelSim message system helps you identify and troubleshoot problems while using the application The messages display in a standard format in the Transcript pane Accordingly you can also access them from a saved transcript file see Saving the Transcript File for more details Message Format The format for the messages is SEVERITY LEVEL Tool Group MsgNum Message e SEVERITY LEVEL may be one of the following Table C 1 Severity Level Types severity level meaning This is an informational message
125. only once for a particular pair of signals Once init signal driver is called any change on the source signal will be driven on the destination signal until the end of the simulation Thus we recommend that you place all init signal driver calls in a VHDL process You need to code the VHDL process correctly so that it is executed only once The VHDL process should not be sensitive to any signals and should contain only init signal driver calls and a simple wait statement The process will execute once and then wait forever See the example below Syntax init signal driver src object dest object delay delay type lt verbose gt Returns Nothing Arguments e src object Required string A full hierarchical path or relative downward path with reference to the calling block to a VHDL signal or Verilog net Use the path separator to which your simulation is set i e or A full hierarchical path must begin with a or The path must be contained within double quotes e dest object Required string A full hierarchical path or relative downward path with reference to the calling block to an existing VHDL signal or Verilog net Use the path separator to which your simulation is set i e or A full hierarchical path must begin with a or The path must be contained within double quotes e delay Optional time value Specifies a delay relative to the time at which the src object cha
126. portion of the Main window maintains a running history of commands that are invoked and messages that occur as you work with ModelSim When a simulation is running the Transcript displays a VSIM prompt allowing you to enter command line commands from within the graphic interface 38 ModelSim User s Manual v6 2g February 2007 Simulator Windows Main Window You can scroll backward and forward through the current work history by using the vertical scrollbar You can also use arrow keys to recall previous commands or copy and paste using the mouse within the window see Main and Source Window Mouse and Keyboard Shortcuts for details Saving the Transcript File Variable settings determine the filename used for saving the transcript If either PrefMain file in the modelsim file or TranscriptFile in the modelsim ini file is set then the transcript output is logged to the specified file By default the TranscriptFile variable in modelsim ini is set to transcript If either variable is set the transcript contents are always saved and no explicit saving is necessary If you would like to save an additional copy of the transcript with a different filename click in the Transcript pane and then select File Save As or File Save The initial save must be made with the Save As selection which stores the filename in the Tcl variable PrefMain saveFile Subsequent saves can be made with the Save selection Since no automatic saves are perf
127. ringbuf h H control vhd hy Untitled 1 Some of the fields such as module_name in the example above are to be replaced with names you type Other fields can be expanded by double clicking and still others offer a context menu 66 ModelSim User s Manual v6 2g February 2007 Simulator Windows Source Window of options when double clicked The example below shows the menu that appears when you double click module item then select gate instantiation Figure 2 25 Language Template Context Menus B C modeltech examples systeme sc_vhdl_vlog Untitled 1 Language Templates PN New Design Wizard AN Create Testbench list of t Create Testbenc module module name list of ansi params Module Primitive module item declaration gt Declarations module instantiation Statements gate instantiation n input gate Instantiations peser peneneg n output gate Compiler Directi ompiler Directives Blocks enable gate Blocks System T asks and Fur pullup Stimulus Generators pulldown mos switch cmos switch pass switch 3p 1 gt pass_enable_switch C ringbuf h H control vhd hy Untitled 1 Setting File Line Breakpoints You can easily set File line breakpoints in a Source window using your mouse Click on a red line number at the left side of the Source window and a red circle denoting a breakpoint will appear The breakpoints are toggles click once to create the breakpoint click again to disable or
128. select a region that had a filter applied that filter is restored This allows you to apply different filters to different regions Filtering by Signal Type The View gt Filter menu selection allows you to specify which signal types to display in the Objects window Multiple options can be selected ModelSim User s Manual v6 2g 61 February 2007 Simulator Windows Source Window Source Window Source files display by default in the MDI frame of the Main window The window can be undocked from the Main window by pressing the Undock button in the window header or by using the view undock source command You can edit source files as well as set breakpoints step through design files and view code coverage statistics By default the Source window displays your source code with line numbers You may also see the following graphic elements Red line numbers denote lines on which you can set a breakpoint Blue arrow denotes the currently active line or a process that you have selected in the Active Processes Pane Red circles denote file line breakpoints gray circles denote breakpoints that are currently disabled Blue circles denote line bookmarks Language Templates pane displays Language Templates Figure 2 19 Figure 2 19 Source Window Showing Language Templates Stimulus Generators P Counter Aj Stop Simulation Language Templates BN New Design Wizard Create Testbench GH 7 Languag
129. set b list set i expr llength a 1j while i gt 0 lappend b lindex Sa i incr i 1 This example uses the Tcl for command to copy a list from variable a to variable b reversing the order of the elements along the way set b list for set i expr llength a 1 i gt 0 incr i 1 lappend b lindex Sa i This example uses the Tcl foreach command to copy a list from variable a to variable b reversing the order of the elements along the way the foreach command iterates over all of the elements of a list set b list foreach i a set b linsert b 0 i This example shows a list reversal as above this time aborting on a particular element using the Tcl break command set b list foreach i a if i ZZZ break set b linsert b 0 i This example is a list reversal that skips a particular element by using the Tcl continue command ModelSim User s Manual v6 2g 303 February 2007 Tcl and Macros DO Files Tcl Examples set b list foreach i a if i ZZZ continue set b linsert Sb 0 i The next example works in UNIX only In a Windows environment the Tcl exec command will execute compiled files only not system commands The example shows how you can access system information and transfer it into VHDL variables or signals and Verilog nets or registers When a particular HDL source breakpoint occurs a Tcl function is called that gets the d
130. signal release flag is a 1 Both calls will send a message to the transcript stating which signal was released and when 250 library IEEE modelsim lib use IEEE std logic 1164 a11 use modelsim lib util all entity testbench is end architecture only of testbench is signal release flag std logic ModelSim User s Manual v6 2g February 2007 Signal Spy signal release begin stim design process begin wait until release flag 1 signal release testbench dut blkl data 1 signal release testbench dut blkl clk 1 end process stim design end ModelSim User s Manual v6 2g 251 February 2007 Signal Spy disable signal spy disable signal spy The disable signal spy system task disables the associated Sinit signal spy task The association between the disable signal spy task and the Sinit signal spy task is based on specifying the same src object and dest object arguments to both tasks The disable signal spy task can only affect Sinit signal spy tasks that had their control state argument set to 0 or 1 Syntax disable signal spy src object dest object lt verbose gt Returns Nothing Arguments src object Required string A full hierarchical path or relative downward path with reference to the calling block to a VHDL signal or Verilog register net This path should match the path that was specified in the init signal spy call t
131. signal release works the same as the noforce command See signal release for complete details sdf done This task is a cleanup function that removes internal buffers called MIPDs that have a delay value of zero These MIPDs are inserted in response to the v2k int delay argument to the vsim command In general the simulator will automatically remove all zero delay MIPDs However if you have sdf_annotate calls in your design that are not getting executed the zero delay MIPDs are not removed Adding the sdf_done task after your last sdf_annotate will remove any zero delay MIPDs that have been created ModelSim User s Manual v6 29 167 February 2007 Verilog and SystemVerilog Simulation System Tasks and Functions Verilog XL Compatible System Tasks and Functions ModelSim supports a number of Verilog XL specific system tasks and functions Supported Tasks and Functions Mentioned in IEEE Std 1364 The following supported system tasks and functions though not part of the IEEE standard are described in an annex of the IEEE Std 1364 countdrivers getpattern sreadmemb sreadmemh Supported Tasks not Described in the IEEE Std 1364 The following system tasks are also provided for compatibility with Verilog XL though they are not described in the IEEE Std 1364 168 deposit variable value This system task sets a Verilog register or net to the specified value variable is the register or net to be changed value
132. sque eere oes eS 0x see nab Eee ee PSE ee Ree eR ee EP 404 Table E 4 List Window Keyboard Shortcuts l llle lees 407 Table E 5 Wave Window Mouse Shortcuts llle 408 Table E 6 Wave Window Keyboard Shortcuts 0 0 0 cee eee ene 408 Table F 1 Predefined GUI Layouts seseeeeeeeeeeee nh 411 Table G 1 Files Accessed During Startup 0 cece cece cece eee en eeeee 419 Table G 2 Environment Variables Accessed During Startup leues 420 ModelSim User s Manual v6 2g February 2007 Chapter 1 Introduction This documentation was written for UNIX Linux and Microsoft Windows users Not all versions of ModelSim are supported on all platforms Contact your Mentor Graphics sales representative for details Tool Structure and Flow The diagram below illustrates the structure of the ModelSim tool and the flow of that tool as it is used to verify a design ModelSim User s Manual v6 2g 21 February 2007 Introduction Simulation Task Overview Figure 1 1 Tool Structure and Flow Map libraries local work Libraries library Verilog VHDL Analyze Compile compiled database vsim Simulate Debug Simulation Output e g vcd Post processing Debug Simulation Task Overview The following table provides a reference for the tasks required for compiling loading and simulating a design in ModelSim 22 ModelSim User s Manual v6 2g Februar
133. state will be recorded as one of the following Table 12 5 State When Direction is Unknown Unknown direction O low both input and output are driving low 1 high both input and output are driving high unknown both input and output are driving unknown F three state input and output unconnected A unknown input driving low and output driving high a unknown input driving low and output driving unknown B unknown input driving high and output driving low b unknown input driving high and output driving unknown C unknown input driving unknown and output driving low c unknown input driving unknown and output driving high f unknown input and output three stated Driver Strength The recorded 0 and 1 strength values are based on Verilog strengths Table 12 6 Driver Strength Strength VHDL std logic mappings 0 highz UE 1 small ModelSim User s Manual v6 29 287 February 2007 Value Change Dump VCD Files Capturing Port Driver Data Table 12 6 Driver Strength cont Strength VHDL std logic mappings 2 medium 3 weak 4 large 5 pull W PR D 6 strong UX O m1 Identifier Code The lt identifier_code gt is an integer preceded by lt that starts at zero and is incremented for each port in the order the ports are specified Also the variable type recorded in the VCD header is port Resolving Values The resolved values written to the VCD
134. tab ModelSim automatically displays a memory contents pane in the MDI frame see Multiple Document Interface MDI Frame You can also enter the command add mem instance at the vsim command prompt Viewing Multiple Memory Instances You can view multiple memory instances simultaneously A memory tab appears in the MDI frame for each instance you double click in the Memory list ModelSim User s Manual v6 2g 57 February 2007 Simulator Windows Memory Panes Figure 2 14 Viewing Multiple Memories z memory ram tb spram1 mem 00000000 80101000 00101001 00101010 00101011 00101100 00101101 00101110 Qo000007 00101111 00110000 00110001 00110010 00110011 00110100 00110101 O000000e 00110110 00110111 00111000 00111001 00111010 00111011 00111100 00000015 00111101 00111110 00111111 01000000 01000001 01000010 01000011 O000001c 1000100 01000101 01000110 01000111 01001000 01001001 01001010 00000023 01001011 01001100 01001101 01001110 01001111 01010000 01010001 00000028 01010010 01010011 01010100 01010101 01010110 01010111 01011000 00000031 01011001 01011010 01011011 01011100 01011101 01011110 01011111 00000038 01100000 01100001 01100010 01100011 01100100 01100101 01100110 nnnnnn r NINANI 01308 nn 03098008 01308 08 0 0183 08 083 013083060 01313011 018 See Organizing Windows with Tab Groups for more information on tabs Saving Memory Formats in a DO File You can save all open memory instances and their formats e g addre
135. the List or Wave window or the current log file Figure 2 16 Objects Pane data_in ooo00000000000 data spl 01111010 data sp2 00111011001111 data_sp3 B0000000000000 data sp4 01110110011110 data dpl 01111010 4 7 sto gt 6 St 4 5 St gt 4 St 4 3 St 4 2 cm A A EEEEE Filtering the Objects List You can filter the objects list by name or by object type Filtering by Name To filter by name undock the Objects pane from the Main window and start typing letters in the Contains field in the toolbar Figure 2 17 Objects Filter Ti 4 Contains e As you type the objects list filters to show only those signals that contain those letters 60 ModelSim User s Manual v6 2g February 2007 Simulator Windows Objects Pane Figure 2 18 Filtering the Objects List by Name data in Packed Array Intemal data spl 01111010 Net Internal _ the objects list filters dynamically data_sp2 00111011001111 Net Internal to show only objects that match your data_sp3 Net Internal entry data sp 0111011001111010 Net Internal data dpl 01111010 Net Internal 7 St Net Intemal 6 Stl Net Internal 5 Sti Net Internal 4 Stl Net Internal 3 Sti Net Internal 2 Sto Net Internal 1 Stl Net Internal 0 St0 Net Internal To display all objects again click the Eraser icon to clear the entry Filters are stored relative to the region selected in the Structure window If you re
136. the associated signals are added to the Wave window move a cursor in the Wave window and the values update in the Dataflow window Source Window select an object in the Dataflow window and the Source window updates if that object is in a different source file Exploring the Connectivity of the Design A primary use of the Dataflow window is exploring the physical connectivity of your design One way of doing this is by expanding the view from process to process This allows you to see the drivers receivers of a particular signal net or register You can expand the view of your design using menu commands or your mouse To expand with the mouse simply double click a signal register or process Depending on the specific object you click the view will expand to show the driving process and interconnect the reading process and interconnect or both Alternatively you can select a signal register or net and use one of the toolbar buttons or menu commands described in Table 9 2 Table 9 2 Icon and Menu Selections for Exploring Design Connectivity Expand net to all drivers display driver s of the selected signal net or register Navigate Expand net to drivers Expand net to all drivers and readers Navigate Expand net display driver s and reader s of the selected signal net or register Expand net to all readers display reader s of the selected signal net or register Navigate
137. the display of available libraries and design units Assigning a Logical Name to a Design Library VHDL uses logical library names that can be mapped to ModelSim library directories By default ModelSim can find libraries in your current directory assuming they have the right name but for it to find libraries located elsewhere you need to map a logical library name to the pathname of the library You can use the GUI a command or a project to assign a logical name to a design library 102 ModelSim User s Manual v6 2g February 2007 Design Libraries Working with Design Libraries Library Mappings with the GUI To associate a logical name with a library select the library in the workspace right click you mouse and select Edit from the context menu that appears This brings up a dialog box that allows you to edit the mapping Figure 4 3 Edit Library Mapping Dialog ES Library Mapping Name simprim m Library Pathname CM odeltech 5 7b simprim Browse OK Cancel The dialog box includes these options e Library Mapping Name The logical name of the library e Library Pathname The pathname to the library Library Mapping from the Command Line You can set the mapping between a logical library name and a directory with the vmap command using the following syntax vmap logical name directory pathname You may invoke this command from either a UNIX DOS prompt or fr
138. the link command line lt isymfile gt is the name of the file generated by the isymfile argument to the vlog command Once you have created the lt isymfile gt it contains a complete list of all imported tasks and functions expected by ModelSim DPI Special Flow for Exported Tasks and Functions Since the RS6000 platform lacks the necessary runtime linking capabilities you must perform an additional manual step in order to prepare shared objects containing calls to exported System Verilog tasks or functions shared object file You need to invoke a special run of vsim The command is as follows vsim top du list dpiexportobj lt objname gt other args The dpiexportobj generates the object file lt objname gt o that contains glue code for exported tasks and functions You must add that object file to the link line listed after the other object files For example a link line would be Id o app dll app o lt objname gt o bE lt isymfile gt bl install dir modeltech rs6000 mti exports bM SRE bnoentry lc 64 bit IBM RS 6000 Platform Only version 5 1 and later of AIX supports the 64 bit platform A gcc 64 bit compiler is not available at this time e VisualAge C Compiler cc c q64 I lt install_dir gt modeltech include app cpp Id o app s1 app o b64 bE app exports bl lt install_dir gt modeltech rs64 mti_exports bM SRE bnoentry lc For DPI Imports When linking the shared objects be sure to sp
139. the set of 10 1x x0 is equivalent to negedge A match occurs if any of the explicit edges in the specify port match any of the explicit edges implied by the SDF port Optional Conditions Timing check ports and path delays can have optional conditions The annotator uses the following rules to match conditions e A match occurs if the SDF does not have a condition e A match occurs for a timing check if the SDF port condition is semantically equivalent to the specify port condition e A match occurs for a path delay if the SDF condition is lexically identical to the specify condition Timing check conditions are limited to very simple conditions therefore the annotator can match the expressions based on semantics For example Table 11 19 SDF Timing Check Conditions SETUP data COND reset 1 setup data posedge clk amp amp amp posedge clock 5 reset 0 0 272 ModelSim User s Manual v6 2g February 2007 Standard Delay Format SDF Timing Annotation SDF for Mixed VHDL and Verilog Designs The conditions are semantically equivalent and a match occurs In contrast path delay conditions may be complicated and semantically equivalent conditions may not match For example Table 11 20 SDF Path Delay Conditions COND r1 Il r2 IOPATH clk q 5 if r1 Il r2 clk gt q 5 matches COND r1 Il 12 IOPATH clk q 5 if r2 I r1 clk gt q 5 does not match The annotator does
140. the types STRING and BIT VECTOR These lines are reproduced here procedure WRITE L inout LINE VALUE in BIT VECTOR JUSTIFIED in SIDE RIGHT FIELD in WIDTH 0 procedure WRITE L inout LINE VALUE in STRING JUSTIFIED in SIDE RIGHT FIELD in WIDTH 0 The error occurs because the argument hello could be interpreted as a string or a bit vector but the compiler is not allowed to determine the argument type until it knows which function is being called The following procedure call also generates an error WRITE L 010101 This call is even more ambiguous because the compiler could not determine even if allowed to whether the argument 010101 should be interpreted as a string or a bit vector There are two possible solutions to this problem e Use a qualified expression to specify the type as in 120 ModelSim User s Manual v6 2g February 2007 VHDL Simulation TextlO Implementation Issues WRITE L string hello e Call a procedure that is not overloaded as in WRITE STRING L hello The WRITE STRING procedure simply defines the value to be a STRING and calls the WRITE procedure but it serves as a shell around the WRITE procedure that solves the overloading problem For further details refer to the WRITE STRING procedure in the io utils package which is located in the file install dir modeltech examples misc io utils vhd Reading and Writing Hexadecim
141. these scripts with the Tools TCL Execute Macro menu selection or the do command Creating DO Files You can create DO files like any other Tcl script by typing the required commands in any editor and saving the file Alternatively you can save the transcript as a DO file see Saving the Transcript File All event watching commands e g onbreak onerror etc must be placed before run commands within the macros in order to take effect The following is a simple DO file that was saved from the transcript It is used in the dataset exercise in the ModelSim Tutorial This DO file adds several signals to the Wave window provides stimulus to those signals and then advances the simulation ModelSim User s Manual v6 2g 307 February 2007 Tcl and Macros DO Files Macros DO Files add wave ld add wave rst add wave clk add wave d add wave q force freeze clk 00 1 50 ns r 100 force rst 1 force rst 0 10 force ld 0 force d 1010 onerror cont run 1700 force ld 1 run 100 force ld 0 run 400 force rst 1 run 200 force rst 0 10 run 1500 Using Parameters with DO Files You can increase the flexibility of DO files by using parameters Parameters specify values that are passed to the corresponding parameters 1 through 9 in the macro file For example say the macro festfile contains the line bp 1 2 The command below would place a breakpoint in the source file named design vhd at line 127 do te
142. time to improve simulation performance This happens automatically and should be largely transparent However you can disable automatic inlining two ways 110 ModelSim User s Manual v6 2g February 2007 VHDL Simulation Compiling VHDL Files Invoke vcom with the O0 or O1 argument Use the mti inhibit inline attribute as described below Single stepping through a simulation varies slightly depending on whether inlining occurred When single stepping to a subprogram call that has not been inlined the simulator stops first at the line of the call and then proceeds to the line of the first executable statement in the called subprogram If the called subprogram has been inlined the simulator does not first stop at the subprogram call but stops immediately at the line of the first executable statement mti inhibit inline Attribute You can disable inlining for individual design units a package architecture or entity or subprograms with the mti inhibit inline attribute Follow these rules to use the attribute Declare the attribute within the design unit s scope as follows attribute mti inhibit inline boolean Assign the value true to the attribute for the appropriate scope For example to inhibit inlining for a particular function e g foo add the following attribute assignment attribute mti inhibit inline of foo procedure is true To inhibit inlining for a particular package e g pack add the following
143. to add items of that type _ Create New File Add Existing File Create Simulation Create New Folder Close The name of the current project is shown at the bottom left corner of the Main window Step 2 Adding Items to the Project The Add Items to the Project dialog includes these options e Create New File Create a new VHDL Verilog Tcl or text file using the Source editor See below for details e Add Existing File Add an existing file See below for details e Create Simulation Create a Simulation Configuration that specifies source files and simulator options See Creating a Simulation Configuration for details e Create New Folder Create an organization folder See Organizing Projects with Folders for details Create New File The File New Source menu selections allow you to create a new VHDL Verilog Tcl or text file using the Source editor You can also create a new project file by selecting Project Add to Project New File the Project tab in the Workspace must be active or right clicking in the Project tab and selecting Add to Project New File This will open the Create Project File dialog Figure 3 4 84 ModelSim User s Manual v6 2g February 2007 Projects Getting Started with Projects Figure 3 4 Create Project File Dialog Create Project File E x File Name foo Browse r Add file as type Folder Verilog Top Level
144. to put a call to acc product version as the first executable statement in your application code Then after vsim has been loaded into the debugger set a breakpoint in this function Once you have set the breakpoint run vsim with the usual arguments When the breakpoint is reached the shared library containing your application code has been loaded 4 Insome debuggers you must use the share command to load the application s symbols At this point all of the application s symbols should be visible You can now set breakpoints in and single step through your application code Troubleshooting a Missing DPI Import Function DPI uses C function linkage If your DPI application is written in C it is important to remember to use extern C declaration syntax appropriately Otherwise the C compiler will produce a mangled C name for the function and the simulator is not able to locate and bind the DPI call to that function 400 ModelSim User s Manual v6 2g February 2007 Verilog PLI VPI DPI Debugging PLI VPI DPI Application Code Also if you do not use the Bsymbolic argument on the command line for specifying a link the system may bind to an incorrect function resulting in unexpected behavior For more information see Correct Linking of Shared Libraries with Bsymbolic HP UX Specific Warnings On HP UX you might see some warning messages that vsim does not have debugging information available This is normal If you are us
145. ur RRRR D RS RAE ERES 58 Figure 2 15 Split Screen View of Memory Contents es 59 Fig re 2 16 Objects Pane ii sd edes ht rr que PETI Ennn Ame Y CAPSQEA SORA quA 60 Fig re 2 17 ODJects Milter is uoi oko PU Rae ga Ea weg PER CREE RE RO ER ERR 60 Figure 2 18 Filtering the Objects List by Name 0 0 0 0 eee e 61 Figure 2 19 Source Window Showing Language Templates 005 62 Figure 2 20 Displaying Multiple Source Files 2 0 0 0 0 0 eee eee eee 63 Figure 2 21 Setting Context from Source Files llle 64 Figure 2 22 Language Templates i45osoa dios e di eeu e dum RE ex bane s eed yee EN 65 Figure 2 23 Create New Design Wizard i issc esos eri e REG AD EIEIG AR 66 Figure 2 24 Inserting Module Statement from Verilog Language Template 66 Figure 2 25 Language Template Context Menus 0 0 0 0 c ee eee eee ee 67 Figure 2 26 Preferences Dialog for Customizing Source Window 69 Pieure 2 27 Watch Pane o daos edern re RAPI EG RR RR E RP RS E RENE EE 70 Figure 2 28 Grouping Objects in the Watch Pane 0 0 00 ec ee eee eee 71 Figure 2 29 Wave Window Undock Button 72 Figure 2 30 Wave Window Dock Button 0 0 ce eee eee e 73 Figure 3 1 Create Project Dialog 42s neue exec gee eines RENS ea E PE EE ES 83 Figure 3 2 Project Tab in Workspace Pane 0 0c eee eee eee ene 83 Figure 3 3 Add items to the Project Dialog 44 s exert REA ave
146. use this vlib command vlib directory pathname To create a new library with the graphic interface select File New Library Figure 4 1 Creating a New Library Create C amapto an existing library Library Name work Library Physical Name work When you click OK ModelSim creates the specified library directory and writes a specially formatted file named info into that directory The _info file must remain in the directory to distinguish it as a ModelSim library The new map entry is written to the modelsim ini file in the Library section Refer to Library Path Variables for more information Note Remember that a design library is a special kind of directory The only way to create a library is to use the ModelSim GUI or the vlib command Do not try to create libraries using UNIX DOS or Windows commands Managing Library Contents Library contents can be viewed deleted recompiled edited and so on using either the graphic interface or command line ModelSim User s Manual v6 2g 101 February 2007 Design Libraries Working with Design Libraries The Library tab in the Workspace pane provides access to design units configurations modules packages entitiesarchitectures in a library Various information about the design units is displayed in columns to the right of the design unit name Figure 4 2 Design Unit Information in the Workspace Workspace E FG x M NARCISS
147. vi DK Cancel Specify a name file type and folder location for the new file When you select OK the file is listed in the Project tab Double click the name of the new file and a Source editor window will open allowing you to create source code Add Existing File You can add an existing file to the project by selecting Project gt Add to Project gt Existing File or by right clicking in the Project tab and selecting Add to Project gt Existing File Figure 3 5 Add file to Project Dialog Add file to Project x File Name counter v tcounter Browse Add file as type Folder ini x Top Level v Reference from current location Copy to project directory OK Cancel When you select OK the file s is added to the Project tab Step 3 Compiling the Files The question marks in the Status column in the Project tab denote either the files haven t been compiled into the project or the source has changed since the last compile To compile the files select Compile gt Compile All or right click in the Project tab and select Compile gt Compile All Figure 3 6 ModelSim User s Manual v6 2g 85 February 2007 Projects Getting Started with Projects Figure 3 6 Right click Compile Menu in Project Tab of Workspace Verilog 1 03 04 05 07 55 38 Py 0 03 04 05 07 55 40 P Compile Selected Add to Project 3 Remove from Project CompileQut of D
148. view individual bit values by double clicking the array or record As shown in the graphic above ram tb dpraml inaddr has been expanded to show all the individual bit values Notice the arrow that ties the array to the individual bit display 70 ModelSim User s Manual v6 2g February 2007 Simulator Windows Watch Pane Grouping and Ungrouping Objects You can group objects in the Watch pane so they display and move together Select the objects then right click one of the objects and choose Group In the graphic below two different sets of objects have been grouped together Figure 2 28 Grouping Objects in the Watch Pane Displays Aram tb we 1 ram_tb i 525 ram_tb inaddr 0001 ram_tb outaddr 0001 To ungroup them right click the group and select Ungroup Saving and Reloading Format Files You can save a format file a DO file actually that will redraw the contents of the Watch window Right click anywhere in the window and select Save Format Once you have saved the file you can reload it by right clicking and selecting Load Format ModelSim User s Manual v6 2g 71 February 2007 Simulator Windows Wave Window Wave Window The Wave window like the List window allows you to view the results of your simulation In the Wave window however you can see the results as waveforms and their values The Wave window opens by default in the MDI frame of the Main window as shown below The wind
149. will be compiled when you execute a Compile All command 88 ModelSim User s Manual v6 2g February 2007 Projects Changing Compile Order e Modified The date and time of the last modification to the file You can hide or show columns by right clicking on a column title and selecting or deselecting entries Sorting the List You can sort the list by any of the five columns Click on a column heading to sort by that column click the heading again to invert the sort order An arrow in the column heading indicates which field the list is sorted by and whether the sort order is descending down arrow or ascending up arrow Changing Compile Order The Compile Order dialog box is functional for HDL only designs When you compile all files in a project ModelSim by default compiles the files in the order in which they were added to the project You have two alternatives for changing the default compile order 1 select and compile each file individually 2 specify a custom compile order To specify a custom compile order follow these steps 1 Select Compile gt Compile Order or select it from the context menu in the Project tab Figure 3 11 Setting Compile Order xl m Current Order util vhd cache v memory v proc v set vhd top vhd fial j Auto Generate OK C 2 Drag the files into the correct order or use the up and down arrow buttons Note that you can select multiple files and dr
150. window 404 Source window 404 Wave window 408 mpf file 81 loading from the command line 97 order of access during startup 419 msgmode ini file variable 345 msgmode variable 40 mti cosim trace environment variable 316 mti inhibit inline attribute 111 MTI TF LIMIT environment variable 316 multi file compilation issues SystemVerilog 145 MultiFileCompilationUnit ini file variable 322 multiple document interface 41 Multiple simulations 175 N n simulator state variable 350 Name field Project tab 88 name visibility in Verilog generates 150 names modules with the same 144 negative timing setuphold recovery 169 432 JKLMNOPQRSTUVWXYZ algorithm for calculating delays 159 check limits 159 nets Dataflow window displaying in 49 225 values of displaying in Objects window 60 saving as binary log file 175 waveforms viewing 72 Nlview widget Symlib format 236 NoCaseStaticError ini file variable 325 NOCHANGE matching to Verilog 271 NoDebug ini file variable VCOM 325 NoDebug ini file variable VLOG 322 NoIndexCheck ini file variable 325 NOMMATP environment variable 317 non blocking assignments 156 NoOthersStaticError ini file variable 325 NoRangeCheck ini file variable 325 Note ini file variable 345 Notepad windows text editing 404 notrigger argument 221 NoVital ini file variable 325 NoVitalCheck ini file variable 326 Now simulator state variable 350 now sim
151. window where n is 1 to the number of windows Default file root is wave Also creates windowSet do file that contains title and geometry info 304 ModelSim User s Manual v6 2g February 2007 Tcl and Macros DO Files Tcl Examples load wave lt file root gt Opens and loads wave windows for all files matching lt file root gt lt n gt do where lt n gt are the numbers from 1 9 Default lt file root gt is wave Also runs windowSet do file if it exists Add wave management buttons to the main toolbar proc add_wave_buttons _add_menu main controls right SystemMenu SystemWindowFrame Load Waves load_wave _add_menu main controls right SystemMenu SystemWindowFrame Save Waves save wave add menu main controls right SystemMenu SystemWindowFrame New Wave new wave Simple Dialog requests name of new wave window Defaults to Wave lt n gt proc new wave global vsimPriv set defaultName Wave llength vsimPriv WaveWindows set windowName GetValue Create Named Wave Window SdefaultName if SwindowName Dialog canceled abort operation return Debug puts Window name windowName n if SwindowName set windowName if SwindowName named wave SwindowName else named wa
152. with the middle mouse button Navigating in the Main Window The Main window can contain of a number of panes and sub windows that display various types of information about your design simulation or debugging session Here are a few important points to keep in mind about the Main window interface e Windows panes can be resized moved zoomed undocked etc and the changes are persistent ModelSim User s Manual v6 2g 43 February 2007 Simulator Windows Navigating in the Main Window You have a number of options for re sizing re positioning undocking redocking and generally modifying the physical characteristics of windows and panes Windows and panes can be undocked from the main window by pressing the Undock button in the header or by using the view undock window name command For example view undock objects will undock the Objects window The default docked or undocked status of each window or pane can be set with the PrefMain ViewUnDocked window name preference variable When you exit ModelSim the current layout is saved so that it appears the same the next time you invoke the tool e Menus are context sensitive The menu items that are available and how certain menu items behave depend on which pane or window is active For example if the sim tab in the Workspace is active and you choose Edit from the menu bar the Clear command is disabled However if you click in the Transcript pane and choose Edit t
153. you want to replace vcd dumpports vcdstim file proc vcd top p vcd dumpports vcdstim file cache vcd top c vcd dumpports vcdstim file memory vcd top m run 1000 Next simulate your design and map the instances to the VCD files you created vsim top vcdstim top p proc vcd vcdstim top c cache vcd vcdstim top m memory vcd Port Order Issues The vedstim argument to the ved dumpports command ensures the order that port names appear in the VCD file matches the order that they are declared in the instance s module or entity declaration Consider the following module declaration module proc clk addr data rw strb rdy input clk rdy output addr rw strb inout data 280 ModelSim User s Manual v6 2g February 2007 Value Change Dump VCD Files VCD Commands and VCD Tasks The order of the ports in the module line clk addr data does not match the order of those ports in the input output and inout lines clk rdy addr In this case the vcdstim argument to the ved dumpports command needs to be used In cases where the order is the same you do not need to use the vcdstim argument to ved dumpports Also module declarations of the form module proc input clk output addr inout data do not require use of the argument VCD Commands and VCD Tasks ModelSim VCD commands map to IEEE Std 1364 VCD system tasks and appear in the VCD file along with the results of those commands The ta
154. z 51 zd 715000 0 0 206 0 1 206 z 51 E 164 lines Aside from the List Signal Properties dialog there are three other ways to change the radix e Change the default radix for the current simulation using Simulate gt Runtime Options Main window e Change the default radix for the current simulation using the radix command e Change the default radix permanently by editing the DefaultRadix variable in the modelsim ini file Saving the Window Format By default all Wave and List window information is forgotten once you close the windows If you want to restore the windows to a previously configured layout you must save a window format file Follow these steps 1 Add the objects you want to the Wave or List window 2 Edit and format the objects to create the view you want 3 Save the format to a file by selecting File Save Format To use the format file start with a blank Wave or List window and run the DO file in one of two ways e Invoke the do command from the command line VSIM gt do lt my_format_file gt ModelSim User s Manual v6 2g 213 February 2007 Waveform Analysis Printing and Saving Waveforms in the Wave window e Select File gt Load Note Window format files are design specific Use them only with the design you were simulating when they were created Printing and Saving Waveforms in the Wave window You can print the waveform display or save it as an encapsulated postscript E
155. 0 1l 1 TEUNUET ZZZZZ222222222222 0 1l 1l 0001 Dll 1001 ZZZZZZZZZZZZZZZZ 0 11 ah fo ah al oooooo0o00000000 O O 1 0011 Dooooo0O000000000 O O 1 ab ey boa oooooo0000000000 O O 1 eh fe eh ah oooooo0000000000 O 1 1 fe fe ah al ms ooooooooooooOoO000 O 1 1 D lines I DmelImbee l me SSS The window can be undocked from the Main window by clicking the Undock button in the window header or by using the view undock list command ModelSim User s Manual v6 2g 53 February 2007 Simulator Windows List Window Figure 2 11 List Window Undocked GNE dux File Edit View Add Tools Window Ospa 42 9C M23 psy ftest sm into s delta ftest sm outof ftest sm rst ftest sm clk 490000 0 00000020 171 O 1 ee OOOOOOKOKOOOOO00000000000010 491000 1 000000320 171 0 1 495000 0 ooo00000 1710 1 500000 0 ooooo000 17100 510000 0 ooo00000 1710 1 511000 1 oooo0000 171 0 l ooooo000 01 515000 0 40000000 187 0 al 520000 0 40000000 187 0 0 529000 1 40000000 187 O O uaau au aulaan ululatu ata aaa 164 lines l E The following type of objects can be viewed in the List pane e VHDL signals aliases process variables and shared variables e Verilog nets registers and variables e Virtuals Virtual signals and functions 54 ModelSim User s Manual v6 2g February 2007 Simulator Windows Locals Pane Locals Pane The Locals pane displays data objects that are immediately visible fr
156. 0111100 00111101 00111110 00111111 00000018 01000000 01000001 01000010 01000011 01000100 01000101 0000001le 01000110 01000111 01001000 01001001 01001010 01001011 00000024 01001100 01001101 01001110 01001111 01010000 01010001 00000028 01010010 01010011 01010100 01010101 01010110 01010111 zl 00000000 00101000 00101001 00101010 00101011 00101100 00101101 00000006 00101110 00101111 00110000 00110001 00110010 00110011 0000000c 00110100 00110101 00110110 00110111 00111000 00111001 00000012 00111010 00111011 00111100 00111101 00111110 00111111 00000018 01000000 01000001 01000010 01000011 01000100 01000101 000000le 01000110 01000111 01001000 01001001 01001010 01001011 90000024 01001100 01001101 01001110 01001111 01010000 01010001 o00000Za 01010010 01010011 01010100 01010101 01010110 01010111 ModelSim User s Manual v6 2g February 2007 59 Simulator Windows Objects Pane Objects Pane The Objects pane shows the names and current values of declared data objects in the current region selected in the structure tabs of the Workspace Data objects include signals nets registers constants and variables not declared in a process generics parameters Clicking an entry in the window highlights that object in the Dataflow and Wave windows Double clicking an entry highlights that object in a Source editor window opening a Source editor window if one is not open already You can also right click an object name and add it to
157. 1 sim test_sm loop wxxHHEHHNNXRRRRRHNNN sim test sm i x sim test_sm rd_ st gold test sm clk gold test_sm out_ gold test sm dat zzzzzzzzzzzzzzzzzzz gold test sm addr O000110011 gold test sm loop x xxXHHNNXXRRRRKKNN gold test_sm i x gold test_sm rd_ Stl Cursor 1 50400 ps to 565800 ps Now 750 ns Delta 2 Sa i i Bro m ean Y The simulator resolution see Simulator Resolution Limit Verilog or Simulator Resolution Limit VHDL must be the same for all datasets you are comparing including the current simulation If you have a WLF file that is in a different resolution you can use the wlfman command to change it Saving a Simulation to a WLF File If you add objects to the Dataflow List or Wave windows or log objects with the log command the results of each simulation run are automatically saved to a WLF file called vsim wlf in the current directory If you then run a new simulation in the same directory the vsim wlf file is overwritten with the new results If you want to save the WLF file and not have it be overwritten select the dataset tab in the Workspace and then select File Save Or you can use the wIf filename argument to the vsim command or the dataset save command 176 ModelSim User s Manual v6 2g February 2007 WLF Files Datasets and Virtuals Saving a Simulation to a WLF File Note If you do not use dat
158. 1 42 kae e o RE e Gee ee bd ea REG Rd ek 70 Expanding Objects to Show Individual Bits llle eese 70 Grouping and Ungrouping Objects 20 0 cee cece ene eens 71 saving and Reloading Format Files d s0caec sneeiber Rem RR AR 71 Wave nig ML Ern 72 Waye Window Panes ore ese see Sere I rean SERS SO ee Sees eee GER Ie EE xd 75 Wave Window Toolbar oss ces 220 RR RENG REA RENEREPATRENARASARENAGTRSEREENG RE 76 Chapter 3 Projects soos dorsa RE RERO EO P ERA ERA CRENA QUO IERP E UE RSMA DEN PAR S ROS 81 What are Projects Tw 81 What are the Benefits af Projects 2 c2 lt 405 eveshebeeh see RR EE REESE ER HA 8l Project Conversion Between Versions 2 0 c cece eee eee ene ene as 82 Getting Started with Projects as cues axe Ex RR RESET RC EERG HARE SAME ek sagweu ds 82 Step 1 Creating a New PEGIGOL 2 6rd oS CREE TORRE RR EQUES HR ERES 83 Step 2 Adding Items to the Project 2 cene edu Lora donee x sx ue ER 84 Step 3 Compiling the Piles sa ehe b RR RVCRPER tinen eunes Eienaar a RA 85 Step 4 Simulating a Design c222d ee or RSuup3EPPREE ei ease eee oa wee RES 86 Other Basic Project Operations 2 202522 ebad bead a RR R9 REA RARE 88 The Project Tab PT OEEEP 88 Sorting the LISE ivo ee 3 qure on E RU DEN EAA See sense bebe RR ERE 89 Changing ompile ORIGE 25 oed ape sio E Rue EEVREREE EE ERE EE RE PERSE ERSES 89 Auto Generating Compile Order sisse aee E RR RR CR RC RR RR 90 G
159. 101011 500000 0 00 0101011 510000 0 511000 41 511000 2 Y 515000 010111011 52zo0o000 0 D 010111011 529000 1 530000 0 usuIudSIu dude u uo n 0010111011 531000 11 WISIS RUE 0010111011 531000 2 535000 0 muinu 00000000 oooooo0o00000000000000001 oooooooo00000000000000001 oooooooo00000000000000001 EC O O O o 0 0000000000000000000000001 0 ooooooO00O00000000000000001 1 oooo000000000000000000001 l al al ojojo tel te pes pooo Tooo ruine i wj Working with Markers The table below summarizes actions you can take with markers Table 8 2 Actions for Time Markers Method Add marker Select a line and then select Edit gt Add Marker ModelSim User s Manual v6 2g 195 February 2007 Waveform Analysis Zooming the Wave Window Display Table 8 2 Actions for Time Markers cont Delete marker Select a tagged line and then select Edit gt Delete Marker Goto marker Select View Goto time Zooming the Wave Window Display Zooming lets you change the simulation range in the waveform pane You can zoom using the context menu toolbar buttons mouse keyboard or commands Zooming with the Menu Toolbar and Mouse You can access Zoom commands from the View menu in the Wave window when it is undocked from the Wave Zoom menu selections in the Main window when the Wave window is docked or by clicking the right mouse button in the wa
160. 10fs returns the current simulation time with time units e g 110000 ns Note will not return comma between thousands resolution This variable returns the current simulation time resolution Referencing Simulator State Variables Variable values may be referenced in simulator commands by preceding the variable name with a dollar sign For example to use the now and resolution variables in an echo command type echo The time is now resolution Depending on the current simulator state this command could result in The time is 12390 ps 10ps If you do not want the dollar sign to denote a simulator variable precede it with a V For example now will not be interpreted as the current simulator time Special Considerations for the now Variable For the when command special processing is performed on comparisons involving the now variable If you specify when now 100 the simulator will stop at time 100 regardless of the multiplier applied to the time resolution You must use 64 bit time operators if the time value of now will exceed 2147483647 the limit of 32 bit numbers For example 350 ModelSim User s Manual v6 2g February 2007 Simulator Variables Simulator State Variables if gt Time now 2us See Simulator Tcl Time Commands for details on 64 bit time operators ModelSim User s Manual v6 2g 351 February 2007 Simulator Variables Simulator State Variables 352 ModelSim User s Manual
161. 187 225 grouping files for compile 90 grouping objects Monitor window 71 groups in wave window 208 GUI expression format GUI expression builder 200 H Hazard ini file variable VLOG 322 hazards limitations on detection 158 hierarchy driving signals in 243 254 forcing signals in 126 248 258 referencing signals in 125 245 256 releasing signals in 126 250 260 highlighting in Source window 68 history of commands shortcuts for reuse 403 HOLD matching to Verilog 269 HOME environment variable 314 HOME OIN environment variable 314 I O TextIO package 118 icons shapes and meanings 35 identifiers escaped 161 ieee ini file variable 319 IEEE libraries 106 IEEE Std 1076 28 differences between versions 111 IEEE Std 1364 28 139 IgnoreError ini file variable 333 IgnoreFailure ini file variable 334 IgnoreNote ini file variable 334 IgnoreVitalErrors ini file variable 324 IgnoreWarning ini file variable 334 429 ABCDEFGHIJKLMNOPQRSTUVWXYZ importing FPGA libraries 107 Incremental ini file variable 322 incremental compilation automatic 143 manual 143 with Verilog 141 index checking 110 init signal driver 254 init signal driver 243 init signal spy 256 init signal spy 125 245 init usertfs function 366 initialization sequence 421 inlining VHDL subprograms 110 input ports matching to INTERCONNECT 268 matching to PORT 268 INTERCONNECT matching to
162. 3 254 referencing in 125 245 256 releasing anywhere in 250 releasing in 126 260 sampling at a clock change 221 transitions searching for 196 types selecting which to view 60 values of displaying in Objects window 60 forcing anywhere in the hierarchy 126 248 258 saving as binary log file 175 virtual 184 waveforms viewing 72 simulating batch mode 27 command line mode 27 comparing simulations 175 default run length 342 iteration limit 343 saving dataflow display as a Postscript file 233 saving options in a project 91 saving simulations 175 saving waveform as a Postscript file 214 Verilog 151 delay modes 162 hazard detection 158 resolution limit 151 XL compatible simulator options 160 VHDL 114 viewing results in List pane 53 viewing results in List window 190 VITAL packages 124 simulating the design overview 26 simulation basic steps for 23 Simulation Configuration creating 91 simulation task overview 22 simulations event order in 154 saving results 175 436 JKLMNOPQRSTUVWX YZ saving results at intervals 182 simulator control with ini variables 342 simulator resolution returning as a real 125 Verilog 151 VHDL 114 simulator state variables 349 sizetf callback function 391 SKEW matching to Verilog 270 so shared object file loading PLI VPI DPI C applications 373 loading PLI VPI DPI C applications 380 source files referencing with location maps 353 source fi
163. 3 380 DO files macros error handling 311 executing at startup 315 338 parameters passing to 308 Tcl source command 311 docking window panes 413 DOPATH environment variable 314 DPI export TFs 359 missing DPI import function 400 registering applications 369 use flow 370 DPI access routines 397 DPI export TFs 359 DPI VPI PLI 365 drivers Dataflow Window 227 show in Dataflow window 221 Wave window 221 dumpports tasks VCD files 281 DumpportsCollapse ini file variable 333 a Editing 428 in notepad windows 404 in the Main window 404 in the Source window 404 EDITOR environment variable 314 editor default changing 314 embedded wave viewer 228 empty port name warning 359 enable_signal_spy 242 ENDFILE function 122 ENDLINE function 121 entities default binding rules 115 entity simulator state variable 349 environment variables 313 accessed during startup 420 expansion 313 referencing from command line 318 referencing with VHDL FILE variable 318 setting 314 setting in Windows 317 TranscriptFile specifying location of 338 used in Solaris linking for FLI 374 381 used in Solaris linking for PLI VPI DPI FLI 315 using with location mapping 353 variable substitution using Tcl 299 error can t locate C compiler 359 Error ini file variable 345 errors bad magic number 177 DPI missing import function 400 getting more information 355 severity level changing 356 SystemVer
164. 324 system calls VCD 282 Verilog 163 system commands 299 system tasks proprietary 167 VCD 282 Verilog 163 Verilog XL compatible 168 SystemVerilog keyword considerations 140 multi file compilation 145 suppported implementation details 28 SystemVerilog DPI specifying the DPI file to load 387 System Verilog types radix 75 205 T tab groups 42 tab stops Source window 68 ModelSim User s Manual v6 2g February 2007 JKLMNOPQRSTUVWXYZ Tcl to 303 command separator 298 command substitution 297 command syntax 294 evaluation order 298 history shortcuts 403 preference variables 415 relational expression evaluation 298 time commands 301 variable substitution 299 VSIM Tcl commands 300 Tcl_init error message 360 temp files VSOUT 319 testbench accessing internal objectsfrom 239 text and command syntax 31 Text editing 404 TEXTIO buffer flushing 122 TextIO package alternative I O files 122 containing hexadecimal numbers 121 dangling pointers 121 ENDFILE function 122 ENDLINE function 121 file declaration 119 implementation issues 120 providing stimulus 122 standard input 120 standard output 120 WRITE procedure 120 WRITE_STRING procedure 121 TF routines 397 TFMPC explanation 361 time measuring in Wave window 192 time resolution as a simulator state variable 350 time collapsing 182 time resolution in Verilog 151 in VHDL 114 time type converting to
165. 364 2005 We recommend that you obtain these specifications for reference The following functionality is partially implemented in ModelSim e Verilog Procedural Interface VPI see install dir modeltech docs technotes Verilog VPI note for details e JEEE Std P1800 2005 SystemVerilog see install dir modeltech docs technotes sysvlog note for implementation details Terminology This chapter uses the term Verilog to represent both Verilog and SystemVerilog unless otherwise noted Basic Verilog Flow Simulating Verilog designs with ModelSim includes four general steps 1 Compile your Verilog code into one or more libraries using the vlog command See Compiling Verilog Files for details 2 Load your design with the vsim command See Simulating Verilog Designs for details 3 Run and debug your design Compiling Verilog Files The first time you compile a design there is a two step process 1 Create a working library with vlib or select File gt New gt Library 2 Compile the design using vlog or select Compile Compile ModelSim User s Manual v6 2g 139 February 2007 Verilog and SystemVerilog Simulation Compiling Verilog Files Creating a Working Library Before you can compile your design you must create a library in which to store the compilation results Use the vlib command or select File New Library to create a new library For example vlib work This creates a library named work By
166. 364 System Tasks and Functions lsleeleleeeeeeeees 164 System Verilog System Tasks and Functions lllleleeee eese 166 System Tasks and Functions Specific to the Tool 0 0 0 eee ee ee eee 167 Verilog XL Compatible System Tasks and Functions llle eese 168 Compiler Direeli ves J 5 eade QA RUNE Ra REID RE AE ERERCEPISMUeREVEERIS 171 IEEE Std 1364 Compiler Ditecivesi zdzexcesuo ERES dese eared sehen p EE Gd 171 Verilog XL Compatible Compiler Directives nnan nananana 172 Verilog PLI VPI and SystemVerilog DPI 2 0 eee eee eee ee ees 173 Chapter 7 WLF Files Datasets and Virtuals ccc ccc ccc ccc cece cece eee e nnn 175 Saving a Simulation to a WLF File c cc0s cic see ER ARR D REPE REPARARE EP 176 WLP Pile Parameter DyerviewW 2iskeskessRReneter 4kebXekt Reraerzrd 9 eere Rd 177 Opening Datasets nc ss tucwhd es Dec beeibwe xe Ce l ua be Ce tc xe tadqeAbReRPesaGs 178 Viewing Dataset Stirs o a s aedis RR e pU OAR POR PR RN Re deg d e Roe PNG del dc LR S 179 Structure Tab Columns i 2 ce p n UR SER RA REESE RR RR E qupR eis A RES 179 Managing Multiple Datasets casses tot orare EE RIPE OU ERE C PERFDEeES EP EET 180 GUL PTT a E a a a a a e a a 180 Command ANS s esse seed oud ect se ORR ROS ina n ACH Mo E OES KA a eio ande y 180 Restricting the Dataset Prefix Display 0 cece ee eee ee 181 Saving at Intervals with Dataset Snapshot 0 0 c eee eee eee 182 Colla
167. 4 Verilog sdf_annotate system task 267 optional conditions 272 optional edge specifications 271 rounded timing values 273 SDF to Verilog construct matching 268 VHDL resolving errors 265 SDF to VHDL generic matching 265 SDF DEVICE matching to Verilog constructs 269 SDF GLOBALPATHPULSE matching to Verilog constructs 269 SDF HOLD matching to Verilog constructs 269 SDF INTERCONNECT matching to Verilog constructs 268 ModelSim User s Manual v6 2g February 2007 ABCDEFGHI SDF IOPATH matching to Verilog constructs 268 SDF NOCHANGE matching to Verilog constructs 271 SDF PATHPULSE matching to Verilog constructs 269 SDF PERIOD matching to Verilog constructs 271 SDF PORT matching to Verilog constructs 268 SDF RECOVERY matching to Verilog constructs 270 SDF RECREM matching to Verilog constructs 270 SDF REMOVAL matching to Verilog constructs 270 SDF SETUPHOLD matching to Verilog constructs 270 SDF SKEW matching to Verilog constructs 270 SDF WIDTH matching to Verilog constructs 271 sdf done 167 searching Expression Builder 200 Verilog libraries 144 sensitivity list warning 360 set simulator control with GUI 342 SETUP matching to Verilog 269 SETUPHOLD matching to Verilog 270 setuphold 169 severity changing level for errors 356 shared objects loading FLI applications see FLI Reference manual loading PLI VPI DPI C applications 373 loading PLI VPI DPI C applications 380 lo
168. 6 2g February 2007 Simulator Windows Wave Window Table 2 10 Wave Window Toolbar Buttons and Menu Selections Insert Cursor add a cursor to the waveform pane E Menu equivalent Add Wave Cursor Main window Add Cursor undocked Wave window Other options right click in cursor pane and select New Cursor Delete Cursor delete the selected cursor from the window gt Find Previous Transition locate the previous signal value change for the selected signal Edit gt Delete Cursor Edit gt Search Search Reverse right mouse in cursor pane gt Delete Cursor n keyboard Shift Tab Find Next Transition locate the next signal value change for the selected signal Edit gt Search Search Forward keyboard Tab Select Mode set mouse to Select Mode click left mouse button to select drag middle mouse button to zoom View gt Zoom gt Mouse Mode gt Select Mode Zoom Mode set mouse to Zoom Mode drag left mouse button to zoom click middle mouse button to select a View gt Zoom gt Mouse Mode gt Zoom Mode Zoom In 2x zoom in by a factor of two from the current view View gt Zoom gt Zoom In keyboard 1 I or right mouse in wave pane gt Zoom In Zoom Out 2x zoom out by a factor of two from current view View gt Zoom gt Zoom Out keyboard o O or right mouse in wave pane gt Zoom Out Zoom in on Active Curs
169. AT NO COST OR C EXPERIMENTAL BETA CODE ALL OF WHICH ARE PROVIDED AS IS 5 2 THE WARRANTIES SET FORTH IN THIS SECTION 5 ARE EXCLUSIVE NEITHER MENTOR GRAPHICS NOR ITS LICENSORS MAKE ANY OTHER WARRANTIES EXPRESS IMPLIED OR STATUTORY WITH RESPECT TO SOFTWARE OR OTHER MATERIAL PROVIDED UNDER THIS AGREEMENT MENTOR GRAPHICS AND ITS LICENSORS SPECIFICALLY DISCLAIM ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE AND NON INFRINGEMENT OF INTELLECTUAL PROPERTY LIMITATION OF LIABILITY EXCEPT WHERE THIS EXCLUSION OR RESTRICTION OF LIABILITY WOULD BE VOID OR INEFFECTIVE UNDER APPLICABLE LAW IN NO EVENT SHALL MENTOR GRAPHICS OR ITS LICENSORS BE LIABLE FOR INDIRECT SPECIAL INCIDENTAL OR CONSEQUENTIAL DAMAGES INCLUDING LOST PROFITS OR SAVINGS WHETHER BASED ON CONTRACT TORT OR ANY OTHER LEGAL THEORY EVEN IF MENTOR GRAPHICS OR ITS LICENSORS HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES IN NO EVENT SHALL MENTOR GRAPHICS OR ITS LICENSORS LIABILITY UNDER THIS AGREEMENT EXCEED THE AMOUNT PAID BY YOU FOR THE SOFTWARE OR SERVICE GIVING RISE TO THE CLAIM IN THE CASE WHERE NO AMOUNT WAS PAID MENTOR GRAPHICS AND ITS LICENSORS SHALL HAVE NO LIABILITY FOR ANY DAMAGES WHATSOEVER THE PROVISIONS OF THIS SECTION 6 SHALL SURVIVE THE EXPIRATION OR TERMINATION OF THIS AGREEMENT LIFE ENDANGERING ACTIVITIES NEITHER MENTOR GRAPHICS NOR ITS LICENSORS SHALL BE LIABLE FOR ANY DAMAGES RESULTING FROM OR IN CONNECTION WITH THE
170. Access Toolbars 0 0 RR ran 415 Simulator GUI Preferences sau sehe RPOE Fue eX x RA URINE Eq PP ETE ER Kee 415 Setting Preference Variables from the GUI 20 00 eee eee 416 Saving GUI Preferences rcce cg aee SEI URS CEN CPP RO CPI A ODER REP 417 The modelsim tel PUS sees rude eee etude RT PLE e e Tx SUE RE ERE T E EE 417 Appendix G System Initialization s isis chases od kes se ee Eae E ER P TATE ER VE ERE RS 419 Files Accessed During Stamp v34 r nsnur PER RP eh ERE Oe PON eee OEE ESS 419 Environment Variables Accessed During Startup 420 Initial Zt SEQUENCE g cade arc CRI C rA DEM UU RET EE WR EPS OR ERROR EER 42 Index Third Party Information End User License Agreement ModelSim User s Manual v6 2g 13 February 2007 List of Examples Example 2 1 Wave Window Panes sie 2504 24494459 ERE ERXENRERE RANK REESE ERE 74 Example 6 1 Invocation of the Verilog Compiler 0 0 0 0 0 cee eee eee 140 Example 6 2 Incremental Compilation Example 0 0 0 eee eee eee eee 142 Example 6 3 Sub Modules with Common Names 0 0 0 c eee eee eee ee 145 Example 6 4 Negative Timing Check 0 2 2 0 cece eee eee eee een eens 159 Example 12 1 Verilog Counter iso ure RR rw need RR Rar REX E 279 Example 12 2 VHDL Adder oscura RR RR ERAS ena kA ERR ERR 279 Example 12 3 Mixed HDL Desions 51 205425 exce pex EX RE eux ese ERRARE 219 Example 12 4 Replacing Instances 2 2 0 0 cece teens 280
171. Also 1f this file is read only the toolset will not update or otherwise modify the file This variable may contain a relative pathname in which case the file will be relative to the working directory at the time the tool is started MODELSIM TCL The toolset uses the MODELSIM_TCL environment variable to look for an optional graphical preference file The argument can be a colon separated UNIX or semi colon separated Windows list of file paths MTI COSIM TRACE The MTI COSIM TRACE environment variable creates an mti trace cosim file containing debugging information about FLI PLI VPI function calls You should set this variable to any value before invoking the simulator MTI TF LIMIT The MTI TF LIMIT environment variable limits the size of the VSOUT temp file generated by the toolset s kernel Set the argument of this variable to the size of k bytes The environment variable TMPDIR controls the location of this file while STDOUT controls the name The default setting is 10 and a value of 0 specifies that there is no limit This variable does not control the size of the transcript file MTI RELEASE ON SUSPEND The MTI RELEASE ON SUSPEND environment variable allows you to turn off or modify the delay for the functionality of releasing all licenses when the tool is suspended The default setting is 10 in seconds which means that if you do not set this variable your licenses will be released 10 seconds after your run is suspend
172. Architecture templates are available for VHDL files Double click an object in the list to open a wizard or to begin creating code Some of the objects bring up wizards while others insert code into your source file The dialog below is part of the wizard for creating a new design Simply follow the directions in the wizards Figure 2 23 Create New Design Wizard Create New Design Wizard E 2 15 x The New Design Wizard will step you through the tasks necessary to add a VHDL Design Unit or Verilog Module or SystemC SC_MODULE to your code Design Unit First you need to enter the name you want for the design unit and Please enter the name you then the wizard will allow you to enter each of the pins on the want to use for this design block you want to create S S Design Unit Name Next gt Cancel lt Previous Code inserted into your source contains a variety of highlighted fields The example below shows a module statement inserted from the Verilog template Figure 2 24 Inserting Module Statement from Verilog Language Template Ihi C modeltech examples systeme sc_vhdl_vlog Untitled 1 Language Templates A New Design Wizard AN Create Testbench Ebr T Language Constructs module module nene BEBSENGEEMHSEENSENNS ESCEGEN TERE Primitive module item Declarations Statements endmodule Instantiations Compiler Directives Blocks System T asks and Fur Stimulus Generators um 6 C
173. BUSINESS INTERRUPTION HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY WHETHER IN CONTRACT STRICT LIABILITY OR TORT INCLUDING NEGLIGENCE OR OTHERWISE ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE This software application may include MinGW GNU diffutils version 2 7 third party software You can view the complete license at http www fsf org licensing licenses lgpl html Refer to the license file in your install directory install directory docs legal Igpl pdf End User License Agreement The latest version of the End User License Agreement is available on line at www mentor com terms conditions enduser cfm IMPORTANT INFORMATION USE OF THIS SOFTWARE IS SUBJECT TO LICENSE RESTRICTIONS CAREFULLY READ THIS LICENSE AGREEMENT BEFORE USING THE SOFTWARE USE OF SOFTWARE INDICATES YOUR COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH IN THIS AGREEMENT ANY ADDITIONAL OR DIFFERENT PURCHASE ORDER TERMS AND CONDITIONS SHALL NOT APPLY END USER LICENSE AGREEMENT Agreement This is a legal agreement concerning the use of Software between you the end user as an authorized representative of the company acquiring the license and Mentor Graphics Corporation and Mentor Graphics Ireland Limited acting directly or through their subsidiaries collectively Mentor Graphics Except for license agreements related to the subject matter of this lic
174. D3 S 23524 he osasnd eee ese eka CE EAM HR EHE REESE ERAN I Ree RSS ee 242 inu sighal dHVeb isuuacx teders hee teen een ES NAE E E ERE NE Seanad 243 Sie al SPY ot ects eA etaa E teen ID TIL TTD 245 signal force ise caper teed seeds AUR QS QE DER Gods ba ERE E EE a ERE 248 ari ic MOM ETT 250 dis ble signal Sy 522 asabE os Ed RO REALE Sa ESQ e e ES Res AS Pd ERES 252 enable sional WV esce deeds o p E SCAN Y do OO Eee ewe ac CIE ed SUR 253 itii SISNAl dflVer 4 4613 eX doce OR PEG CR QUOC SHIOURR RH PARAS REN ORS 254 imit signal SPY onsen Qa RU EU A e Sak RR ER PP EP ERIS RCRUM DEP ME 256 Deel JOBS Su oss ad Rn doc oii d d a d qi ede d da dp ERU iEn Sea osa 258 bsicilal telese cu 242 1 eekS CREE UMP PLC CERT RPEPDERP TI UPPER EUKPET EMPTIS 260 Chapter 11 Standard Delay Format SDF Timing Annotation eee 263 Specifying SDF Files for Simulation 0 0 0 cece eee eee 263 Instance SDOCIHCOllOH s ses by x ve Eu REX seer IEA EI es d aie dd Rs 263 SDF Specification with the GUI usse serae RE RR ER HR Rr n Ro ed 264 Errors and Warnes d a e6DecabererUcsr he e ea bercuex dee mA dqaa deii ure 264 VEDI VELAT SIDE utera eae x rare RERO ERES IER RO eq eee EO iced 265 SDF to VHDL Generic Matching iy Ryuxa RR RRE AGAR EPA REN Ku 265 Resolving Bas osa Sacs oe Ra ES eR onda weed a haghed PRERE ERS ENERET KERENT EE 265 boo SD c m 266 sdf_annotate PNEPEPPEHHENO PERD
175. E EREE NS 298 Tcl Relational Expression Evaluation 0 0 0 c cece eee eee 298 Variable SubstitUti n c vse cane deed eases Boe ARE WE EG ER oe eey ened heaves ok 299 System COMMANIS s sus asco RIS usyE Eg exe R Id SS PEE aed ERI Vd E ede 299 List PrOCesMNE MP tease ieii atk eased eeaudeivees ieee Gene doheSe res 300 Simulator Tcl Commands 4 2 ga scere ood teed des oa ass eee ea HR n 300 Simulator Tcl Time Commands 0 0 0 eee n 301 CONVERSIONS V esa lcob dq ep Sg a A E es ades ei dud JA e sees eee eye se 302 Relations PCT 302 Fwd ic TTD 303 Tel Examples nsei oda eso e rite ex E EAE RERNE adr dcc vi ddr ce e qiiae fs 303 Macr s DO Files ol PE RR BOR OS PETE Roe HO VER PE LS NR RP E Cd 307 Creatin DO Piles 2 cohssstiefaekaiderkeRessekee reibwerNet ias8eerddd as At ds 307 Using Parameters with DO Pes ce eciiteRORe sereisee4 e RR RerR PETAT 308 Deleting a Pile from a do Script 2 eus eee ed RCM tek tx cro R Ore ERROR Donde 308 Making Macro Parameters Optional lleleeeeee ree 309 Useful Commands for Handling Breakpoints and Errors 0000 000 310 10 ModelSim User s Manual v6 2g February 2007 Table of Contents Error Action um DO Piles iueweb euatatiebke e eetheno ARP EEPRQETP CA RUE RIA EE 311 Appendix A Simulator V ic PT m 313 Variable Settings Report isa c RE RR be MEG CR baad OR ER e ad v WERE ME ER XR EA 313 Environment Variables uico d acr
176. EEE Std 1364 File I O Tasks cont File I O tasks fgets ftell swriteb fmonitor fwrite swriteh fmonitorb fwriteb swriteo fmonitorh ungetc SystemVerilog System Tasks and Functions The following ModelSim supported system tasks and functions are described in detail in the System Verilog IEEE Std p1800 2005 LRM Table 6 8 SystemVerilog System Tasks and Functions 1 Expression size function Range function bits isunbounded Table 6 9 SystemVerilog System Tasks and Functions 2 Shortreal Array querying conversions functions shortrealbits dimensions bitstoshortreal left right low high increment size Table 6 10 SystemVerilog System Tasks and Functions 4 Reading packed data Writing packed data Other functions functions functions readmemb writememb root readmemh writememh unit 166 ModelSim User s Manual v6 2g February 2007 Verilog and SystemVerilog Simulation System Tasks and Functions System Tasks and Functions Specific to the Tool The following system tasks and functions are specific to ModelSim They are not included in the IEEE Std 1364 nor are they likely supported in other simulators Their use may limit the portability of your code init signal driver The Sinit signal driver system task drives the value of a VHDL signal or Verilog net onto an existing VHDL signal or Verilog net This allows you to drive signals or nets at any level of the design hierarchy from
177. ERE 267 SDF to Verilog Construct Matching 0 cece eee ee 268 Optional Edge SpeclfICatlolis sd suas ve d x RO Reed Iu A ed xk OA SESS aa ERES 271 Optional Conditions n se eR eaea 272 Rounded Timing Values 2 04 sedisset eme RP ASAP RS EA PAS EE EE d ga 273 SDF for Mixed VHDL and Verilog Designs 0 0 0 cece ee 273 Interconnect Delays 232saw snes x eb E E RESP Fb X ML eR E Sd E qao 219 Disabling Timing Checks os 2 cacao segues ER RESEAeRPR E E NRARAR ERA SR KW w E EE 274 Troubleshooting coucou euer diver RECOREP Cae ea SESE RES FOR SES CFL SEL SRE ES 274 Specifying the Wrong Instance sva s uk eh re i eek CER ER ORA RERECS E Pu 274 Mistaking a Component or Module Name for an Instance Label 275 Forgetting to Specify the Instance 1226092 deze er Red RELIER EE ER 275 ModelSim User s Manual v6 2g 9 February 2007 Chapter 12 Table of Contents Value Chance Dump V CD Miles nua don nior xp ER e seeks Ac exe Ree va 277 Creating VCD File iios casae tea ka Rr P Eix KENE RARE RE RES EET RR eds 271 Flow for Four State VCD File 24240066424 20sbe0dee0eepee0ebeeredaeoweeteeens 277 Flow for Extended VCD File 22c0 c424 exe gr r9 R3 e RR ue eR 278 Cas Sensitivity cep Ee ox 08 Sg cd RU SSA esp E RS P Ru ES MC reap p UP dto RH GRE 278 Using Extended VCD as Stimulus ska eter e E pae RERO RR GR ER Hn ERO RS 278 Simulating with Input Values from a VCD File 0 0 0 cee eee ees 278 Replacing
178. Group Use 324 se aseseeces ae dSee5 ERE BERI s REX 104 Specifying the Resource Libraries ids abated ee ed apnea xa Rcx m ER RR aes 105 Verilog Resource Libraries 242 4044 ets oR ees pP x EI e REREHOREG S RE ecd EET Rd 105 VHDL Resource Libraries 2 5222 c rer RE RR REX RR bodega ES 105 Predetined Libraries s esae Rb e ennea RRRCEHRCR EM REDE nee ew ee Leelee P E Ed 105 Alternate IEEE Libraries Supplied 2220022502 esu RE RR REIR ERR ERE 106 Regenerating Your Design Libraries 5 24cusacist cer Pe aves RAE LRPEERE ERES 106 Maintaining 32 and 64 bit Versions in the Same Library 004 107 Importing FPGA Libraries idu ERPRRES RO RP ee eee SEE eee DRE RYE 107 Chapter 5 VHDL Sunulati0B 42 2549 eR tasen Enr San EOS EAE R EE ES ERA nas 109 Basic VHDL FloW 456a kecukR v be ERE ERR aR PLATE AR ds 109 Compiling VHDL Biles c2 c cscee 20 Oh4R os Sb cies Re ecwerdheraieeadesecta de 109 Creating a Design Library dor VHDL 2s cutee sbeediees ceGever bea RERRES ERES 109 Invoking the VHDL Compiler ses 2t aseeteeeane es deeescecgeeeyeetders vex ear 110 Dependency Checking e iu ase dude g uted aheghedsuce needak Conon shasta es 110 Range and Index Checking 2 id eberRPex ERRAT e A cider nnet Rad ER PS EAE 110 Subprogram Inlining eder oux Tr ee vo pp RENT db arr Exe dE Boe eee 110 Differences Between Language VersionsS 0 cece eee eee teens 111 ounulatimne VHDL Desens 6 esasen neen RE ER REX ERES RR EE EAE Ed EE
179. IRECT SPECIAL OR CONSEQUENTIAL DAMAGES WHATSOEVER INCLUDING BUT NOT LIMITED TO LOST PROFITS ARISING OUT OF OR RELATED TO THIS PUBLICATION OR THE INFORMATION CONTAINED IN IT EVEN IF MENTOR GRAPHICS CORPORATION HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES RESTRICTED RIGHTS LEGEND 03 97 U S Government Restricted Rights The SOFTWARE and documentation have been developed entirely at private expense and are commercial computer software provided with restricted rights Use duplication or disclosure by the U S Government or a U S Government subcontractor is subject to the restrictions set forth in the license agreement provided with the software pursuant to DFARS 227 7202 3 a or as set forth in subparagraph c 1 and 2 of the Commercial Computer Software Restricted Rights clause at FAR 52 227 19 as applicable Contractor manufacturer is Mentor Graphics Corporation 8005 S W Boeckman Road Wilsonville Oregon 97070 7777 Telephone 503 685 7000 Toll Free Telephone 800 592 2210 Website www mentor com TRADEMARKS The trademarks logos and service marks Marks used herein are the property of Mentor Graphics Corporation or other third parties No one is permitted to use these Marks without the prior written consent of Mentor Graphics or the respective third party owner The use herein of a third party Mark is not an attempt to indicate Mentor Graphics as a source of a product but is intended to indicate a product from or ass
180. Language Templates ModelSim language templates help you write code They are a collection of wizards menus and dialogs that produce code for new designs testbenches language constructs logic blocks etc NOIB lt The language templates are not intended to replace thorough knowledge of coding They are intended as an interactive reference for creating small sections of code If you are unfamiliar with a particular language you should attend a training class or consult one of the many available books To use the templates either open an existing file or select File gt New gt Source to create a new file Once the file is open select Source gt Show Language Templates if the Source window is docked in the Main window select View gt Show Language Templates of the Source window is undocked This displays a pane that shows the available templates Figure 2 22 Language Templates lh C modeltech examples systemc sc_vhdl_vlog Untitled 1 Language Templates DN New Design Wizard PW Create Testbench P Language Constructs Stimulus Generators m C ringbuf h H control vhd h Untitled 1 ModelSim User s Manual v6 2g 65 February 2007 Simulator Windows Source Window The templates that appear depend on the type of file you create For example Module and Primitive templates are available for Verilog files and Entity and
181. M For example vsim sv lib test top When Your DPI Export Function is Not Getting Called This issue can arise in your C code due to the way the C linker resolves symbols It happens if a name you choose for a SystemVerilog export function happens to match a function name in a custom or even standard C library In this case your C compiler will bind calls to the function in that C library rather than to the export function in the SystemVerilog simulator The symptoms of such a misbinding can be difficult to detect Generally the misbound function silently returns an unexpected or incorrect value To determine if you have this type of name aliasing problem consult the C library documentation either the online help or man pages Simplified Import of FLI PLI C Library Functions In addition to the traditional method of importing FLI PLI C library functions a simplified method can be used you can declare VPI and FLI functions as DPI C imports When you ModelSim User s Manual v6 2g 371 February 2007 Verilog PLI VPI DPI DPI Use Flow declare VPI and FLI functions as DPI C imports the DPI shared object is loaded at runtime automatically Neither the C implementation of the import tf nor the sv lib argument is required Also on most platforms see Platform Specific Information you can declare most standard C library functions as DPI C imports The following example is processed directly without DPI C code p
182. PS file Saving a eps Waveform File and Printing in UNIX Select File gt Print Postscript Wave window to print all or part of the waveform in the current Wave window in UNIX or save the waveform as a eps file on any platform see also the write wave command Printing from the Wave Window on Windows Platforms Select File gt Print Wave window to print all or part of the waveform in the current Wave window or save the waveform as a printer file a Postscript file for Postscript printers Printer Page Setup Select File gt Page setup or click the Setup button in the Write Postscript or Print dialog box to define how the printed page will appear Saving List Window Data to a File Select File gt Write List in the List window to save the data in one of these formats e Tabular writes a text file that looks like the window listing ns delta a b cin sum cout 0 0 X X U X U 0 1 0 1 0 X U 2 0 0 1 0 X U e Events writes a text file containing transitions during simulation 214 ModelSim User s Manual v6 29 February 2007 Waveform Analysis Combining Objects into Buses O 0 a X b X cin U sum X cout U Q0 1 a 0 b 1 cin 0 e TSSI writes a file in standard TSSI format see also the write tssi command 00000000000000010000000010 0 2 3 00000000000000010 010 4 100 00000001000000010000000010 You can also save List window output using the write list command Combini
183. Properties Modify Display Properties list E lol x Deltas ExpandDeltas Colapse Delas No Deltas Trigger On Iv Signal Change Strobe First Strobe at o ns Strobe Period 0 ns m Trigger Gating Use Gating Expression Use Expression Builder Expression On Duration o ns DK Cancel Apply The following table summaries the triggering options Table 8 5 Triggering Options Description Deltas Choose between displaying all deltas Expand Deltas displaying the value at the final delta Collapse Delta You can also hide the delta column all together No Delta however this will display the value at the final delta Strobe trigger Specify an interval at which you want to trigger data display Trigger gating 218 Use a gating expression to control triggering see Using Gating Expressions to Control Triggering for more details ModelSim User s Manual v6 2g February 2007 Waveform Analysis Configuring New Line Triggering in the List Window Using Gating Expressions to Control Triggering Trigger gating controls the display of data based on an expression Triggering is enabled once the gating expression evaluates to true This setup behaves much like a hardware signal analyzer that starts recording data on a specified setup of address bits and clock edges Here are some points about gating expressions e Gating expr
184. Providing Stimulus to the Design You can provide stimulus to your design in several ways e Language based testbench e Tcl based ModelSim interactive command force e VCD files commands See Creating a VCD File and Using Extended VCD as Stimulus e 3rd party testbench generation tools What is a Library A library is a location where data to be used for simulation is stored Libraries are ModelSim s way of managing the creation of data before it is needed for use in simulation It also serves as a way to streamline simulation invocation Instead of compiling all design data each and every time you simulate ModelSim uses binary pre compiled data from these libraries So if you make a changes to a single Verilog module only that module is recompiled rather than all modules in the design Working and Resource Libraries Design libraries can be used in two ways 1 as a local working library that contains the compiled version of your design 2 as a resource library The contents of your working library will change as you update your design and recompile A resource library is typically unchanging and serves as a parts source for your design Examples of resource libraries might be shared information within your group vendor libraries packages or previously compiled elements of your own working design You can create your own resource libraries or they may be supplied by another design team or a third party e g a silicon vendor
185. RE E ERE RA ERE RR RES 399 T voki g a Trac estass meg saua pid a ke ad a aaa p EO E ESE aae a daaa Ba ea 399 Debugging PLI VPI DPI Application Code 0 0 eee eee eee 400 Troubleshooting a Missing DPI Import Function 400 HP UX Specific Warnings 2iiercue beck REG Ra RERO RR RARA SERA ERAT LA RES 401 Appendix E Command and Keyboard Shortcuts o esee ortho eR ESO RPP E eed eases 403 Command SHORCING ses sass itsa ine aiaa aara a h iie a a POE E ae EEEE a i E EA e 403 Command History Shortcuts llle 403 Main and Source Window Mouse and Keyboard Shortcuts 0000 eee 404 List Window Keyboard Shortcuts 0 0 eect e 407 Wave Window Mouse and Keyboard Shortcuts llle 408 Appendix F Settna GUI Prererences eers ond eaa dox kd ke Yd ere aawa d daria dida uade a ping 411 Customizing the Simulator GUI Layout 0 0 0 cece ee nee 411 Layouts and Modes of Operation 20s aswawkeauEE EP Ex we Ve Sao SASS N S S ee RES 411 Custom Layouts 522v RRRELVeERA ARRA RA GA he eek AR RE RSAdav sbkvadaxeda 411 Automatic Saving Of Layouts oua susce den dh RR EHE ALD o SR de de 413 Resetting Layouts to Their Defaults 0 2 0 0 0 cece eens 413 Navigating the Graphic User Interface iius 20cesngseershaye aode aces eee de 4E E ERES 413 Manipulating Panes 2 eccsa Re b Rr eee ckans oop be e adobe e ee ade ede ss 413 Columnar Information DISplay ae cae 4t PY RerRX WR het eru berdrRew s 415 Quick
186. RUED UNDER THE LAWS OF THE STATE OF OREGON USA IF YOU ARE LOCATED IN NORTH OR SOUTH AMERICA AND THE LAWS OF IRELAND IF YOU ARE LOCATED OUTSIDE OF NORTH OR SOUTH AMERICA All disputes arising out of or in relation to this Agreement shall be submitted to the exclusive jurisdiction of Portland Oregon when the laws of Oregon apply or Dublin Ireland when the laws of Ireland apply Notwithstanding the foregoing all disputes in Asia except for Japan arising out of or in relation to this Agreement shall be resolved by arbitration in Singapore before a single arbitrator to be appointed by the Chairman of the Singapore International Arbitration Centre SIAC to be conducted in the English language in accordance with the Arbitration Rules of the SIAC in effect at the time of the dispute which rules are deemed to be incorporated by reference in this section 15 This section shall not restrict Mentor Graphics right to bring an action against you in the jurisdiction where your place of business is located The United Nations Convention on Contracts for the International Sale of Goods does not apply to this Agreement SEVERABILITY If any provision of this Agreement is held by a court of competent jurisdiction to be void invalid unenforceable or illegal such provision shall be severed from this Agreement and the remaining provisions will remain in full force and effect PAYMENT TERMS AND MISCELLANEOUS You will pay amounts invoiced in the currency spe
187. Shortcuts The following mouse actions and special keystrokes can be used to edit commands in the entry region of the Main window They can also be used in editing the file displayed in the Source window and all Notepad windows enter the notepad command within ModelSim to open the Notepad editor Table E 2 Mouse Shortcuts Mouse UNIX and Windows Result Click the left mouse button relocate the cursor Click and drag the left mouse button select an area Shift click the left mouse button extend selection Double click the left mouse button select a word Double click and drag the left mouse button select a group of words Ctrl click the left mouse button move insertion cursor without changing the selection Click the left mouse button on a previous copy and paste previous command string to ModelSim or VSIM prompt current prompt Click the middle mouse button paste selection to the clipboard Click and drag the middle mouse button scroll the window Table E 3 Keyboard Shortcuts Left Arrow move cursor left or right one character Right Arrow 404 ModelSim User s Manual v6 2g February 2007 Command and Keyboard Shortcuts Main and Source Window Mouse and Keyboard Shortcuts Table E 3 Keyboard Shortcuts cont Keystrokes UNIX and Windows Ctrl Left Arrow Ctrl Right Arrow move cursor left or right one word Shift Any Arrow extend text selection Ctrl Shift Left Arro
188. Signal Properties Dialog List Signal Properties E gt 51 x Signal Display Name l Radix Symbolic Width I Characters C Binary C Octal C Decimal C Unsigned Trigger C Hexadecimal Triggers line C ASCII Does not trigger line C Default OK Cancel Apply The default radix is symbolic which means that for an enumerated type the window lists the actual values of the enumerated type of that object For the other radixes binary octal decimal unsigned hexadecimal or ASCII the object value is converted to an appropriate representation in that radix Changing the radix can make it easier to view information in the List window Compare the image below with decimal values with the image in the section List Window Overview with symbolic values 212 ModelSim User s Manual v6 2g February 2007 Waveform Analysis Saving the Window Format Figure 8 21 Changing the Radix in the List Window IDi x File Edit View Add Tools Window MERETET psc test sm rst ftest sm dat delta est sm outof ftest sm addr ftest sm clk ftest sm out wire 680000 0 0 205 0 0 206 z 50 690000 0 0 zos ol 206 z 50 691000 1 0 zos ol 206 z 51 691000 2 0 zos ol 206 206 51 695000 0 80 206 0 1 206 206 51 700000 0380 206 00 206 206 1 709000 1380 206 0 0 206 207 51 710000 0 80 206 0 1 206 207 51 711000 1 80 206 0 1 206 207 51 711000 2 80 206 0 1 206
189. Simulation Simulating VHDL Designs Note that these last three searches are an extension to the 1076 standard Disabling Default Binding If you want default binding to occur only via configurations you can disable ModelSim s normal default binding methods by setting the RequireConfigForAllDefaultBinding variable in the modelsim ini to 1 true Delta Delays Event based simulators such as ModelSim may process many events at a given simulation time Multiple signals may need updating statements that are sensitive to these signals must be executed and any new events that result from these statements must then be queued and executed as well The steps taken to evaluate the design without advancing simulation time are referred to as delta times or just deltas The diagram below represents the process for VHDL designs This process continues until the end of simulation time Figure 5 1 VHDL Delta Delay Process Execute concurrent statements at current time w Advance delta time lt Advance simulation time No Any transactions to process Yes Any events to process j Execute concurrent statements that are sensitive to events This mechanism in event based simulators may cause unexpected results Consider the following code snippet 116 ModelSim User s Manual v6 2g February 2007 VHDL Simulation Simulating VHDL Designs cl
190. T block Pest angbuf nng INST block Jtest angi nng INST block Pest sngbul ing INST block est angit nng INST block Asl sngiul ang INST block Now pju RAES 4i ons ew E e CN KI a we Ay OO A JE Cotan 0 0 0 100001000 E 100001000 o 0010m 1 500000 ne 462100 re_ 462700 ne E fel hl SS ay 461968 ns to 462962 ns Now 500 us Delta 2 PES Er a Now 500 us Delta 2 sim test ringbuf 4 Here is an example of a Wave window that is undocked from the MDI frame All menus and icons associated with Wave window functions now appear in the menu and toolbar areas of the Wave window 188 ModelSim User s Manual v6 29 February 2007 Waveform Analysis Wave Window Overview Figure 8 2 Docking the Wave Window M wave default File Edit View Add Format Tools Window test_counter chk test_counter reset test_counter count 7 434260 ns to 434677 ns Now 495 852 ns Delta 2 y If the Wave window is docked into the Main window MDI frame all menus and icons that were in the standalone version of the Wave window move into the Main window menu bar and toolbar The Wave window is divided into a number of window panes All window panes in the Wave window can be resized by clicking and dragging the bar between any two panes ModelSim User s Manual v6 2g 189 February 2007 Waveform Analysis List Window Overview Figure 8 3 P
191. The equivalent simulator command is restart restart filename This system task sets the simulation to the state specified by filename saved in a previous call to save The equivalent simulator command is restore lt filename gt save filename This system task saves the current simulation state to the file specified by filename The equivalent simulator command is checkpoint lt filename gt scope hierarchical_name ModelSim User s Manual v6 2g February 2007 Verilog and SystemVerilog Simulation Compiler Directives This system task sets the interactive scope to the scope specified by hierarchical name The equivalent simulator command is environment lt pathname gt showscopes This system task displays a list of scopes defined in the current interactive scope The equivalent simulator command is show showvars This system task displays a list of registers and nets defined in the current interactive scope The equivalent simulator command is show Compiler Directives ModelSim Verilog supports all of the compiler directives defined in the IEEE Std 1364 some Verilog XL compiler directives and some that are proprietary The SystemVerilog IEEE Std P1800 2005 version of the define and include compiler directives are not currently supported Many of the compiler directives such as timescale take effect at the point they are defined in the source code and stay in effect until the directive is redefi
192. This behavior is called Single File Compilation Unit SFCU mode Refer to SystemVerilog Multi File Compilation Issues for details on the implications of these settings Note i The default behavior in versions prior to 6 1 was opposite of the current default behavior NoDebug This variable when on disables the inclusion of debugging info within design units e Value Range 0 1 e Default off 0 Quiet This variable turns off loading messages e Value Range 0 1 e Default off 0 322 ModelSim User s Manual v6 2g February 2007 Simulator Variables Simulator Control Variables Show BadOptionWarning This variable instructs the tool to generate a warning whenever an unknown plus argument is encountered e Value Range 0 1 e Default off 0 Show Lint This variable instructs the tool to display lint warning messages e Value Range 0 1 e Default off 0 Show WarnCantDoCoverage This variable instructs the tool to display warning messages when the simulator encounters constructs which code coverage cannot handle e Value Range 0 1 e Default on 1 Show WarnMatchCadence This variable instructs the tool to display warning messages about non LRM compliance in order to match Cadence behavior e Value Range 0 e Default on 1 Show_source This variable instructs the tool to show any source line containing an error e Value Range 0 1 e Default off 0 vlog95compat This varia
193. UP d posedge clk 5 setuphold posedge clk d 0 0 e HOLD is matched to hold and setuphold Table 11 7 Matching SDF HOLD to Verilog HOLD d posedge clk 5 hold posedge clk d 0 HOLD d posedge clk 5 setuphold posedge clk d 0 0 ModelSim User s Manual v6 2g 269 February 2007 Standard Delay Format SDF Timing Annotation sdf annotate e SETUPHOLD is matched to setup hold and setuphold Table 11 8 Matching SDF SETUPHOLD to Verilog C e SETUPHOLD d posedge clk 5 5 setup d posedge clk 0 SETUPHOLD d posedge clk 5 5 hold posedge clk d 0 SETUPHOLD d posedge clk 5 5 setuphold posedge clk d 0 0 e RECOVERY is matched to recovery Table 11 9 Matching SDF RECOVERY to Verilog C RN RECOVERY negedge reset posedge clk recovery negedge reset posedge clk 0 5 e REMOVAL is matched to removal Table 11 10 Matching SDF REMOVAL to Verilog pp Vg 0 REMOVAL negedge reset posedge clk removal negedge reset posedge clk 0 5 e RECREM is matched to recovery removal and recrem Table 11 11 Matching SDF RECREM to Verilog Verilog RECREM negedge reset posedge clk recovery negedge reset posedge clk 0 5 5 RECREM negedge reset posedge clk removal negedge reset posedge clk 0 5 5 RECREM negedge reset posedge clk recrem negedge reset posedge clk 0 5 5 e SKEW is mat
194. US SS TUBES SS ESNE LR e EH work Library C modeltech examples mixedHDL work j cache Module C modeltech examples mixedHDL cach E cache set Entity C modeltech examplessmisedHDL set AJ memory Module C modeltech examples mixedHDL mem 1J Proc Module C modeltech examples mixedHDL proc v iP std logic util Package C modeltech examplessmixedHDL util EHE top Entity C modeltech examplessmixedHDL top Al only Architecture vital2000 Library MODEL_TECH vital2000 ieee Library MODEL_TECH ieee modelsim lib Library MODEL TECH modelsim lib tJ i LL ert Tees 3 2 Library The Library tab has a context menu with various commands that you access by clicking your right mouse button Windows 2nd button UNIX 3rd button in the Library tab The context menu includes the following commands e Simulate Loads the selected design unit and opens structure and Files tabs in the workspace Related command line command is vsim e Edit Opens the selected design unit in the Source window or if a library is selected opens the Edit Library Mapping dialog refer to Library Mappings with the GUI e Refresh Rebuilds the library image of the selected library without using source code Related command line command is vcom or vlog with the refresh argument e Recompile Recompiles the selected design unit Related command line command is vcom or vlog e Update Updates
195. USE OF SOFTWARE IN ANY APPLICATION WHERE THE FAILURE OR INACCURACY OF THE SOFTWARE MIGHT RESULT IN DEATH OR PERSONAL INJURY THE PROVISIONS OF THIS SECTION 7 SHALL SURVIVE THE EXPIRATION OR TERMINATION OF THIS AGREEMENT INDEMNIFICATION YOU AGREE TO INDEMNIFY AND HOLD HARMLESS MENTOR GRAPHICS AND ITS LICENSORS FROM ANY CLAIMS LOSS COST DAMAGE EXPENSE OR LIABILITY INCLUDING ATTORNEYS FEES ARISING OUT OF OR IN CONNECTION WITH YOUR USE OF SOFTWARE AS 10 11 12 13 14 DESCRIBED IN SECTION 7 THE PROVISIONS OF THIS SECTION 8 SHALL SURVIVE THE EXPIRATION OR TERMINATION OF THIS AGREEMENT INFRINGEMENT 9 1 Mentor Graphics will defend or settle at its option and expense any action brought against you alleging that Software infringes a patent or copyright or misappropriates a trade secret in the United States Canada Japan or member state of the European Patent Office Mentor Graphics will pay any costs and damages finally awarded against you that are attributable to the infringement action You understand and agree that as conditions to Mentor Graphics obligations under this section you must a notify Mentor Graphics promptly in writing of the action b provide Mentor Graphics all reasonable information and assistance to defend or settle the action and c grant Mentor Graphics sole authority and control of the defense or settlement of the action 9 2 If an infringement claim is made Mentor Graphics may at its option
196. WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT INDIRECT INCIDENTAL SPECIAL EXEMPLARY OR CONSEQUENTIAL DAMAGES INCLUDING BUT NOT LIMITED TO PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES LOSS OF USE DATA OR PROFITS OR BUSINESS INTERRUPTION HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY WHETHER IN CONTRACT STRICT LIABILITY OR TORT INCLUDING NEGLIGENCE OR OTHERWISE ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE e This product may use MinGW GCC third party software Red Hat Inc All rights reserved Pipeline Associates Inc All rights reserved Matthew Self All rights reserved National Research Council of Canada All rights reserved The Regents of the University of California THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS AS IS AND ANY EXPRESS OR IMPLIED WARRANTIES INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT INDIRECT INCIDENTAL SPECIAL EXEMPLARY OR CONSEQUENTIAL DAMAGES INCLUDING BUT NOT LIMITED TO PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES LOSS OF USE DATA OR PROFITS OR BUSINESS INTERRUPTION HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY WHETHER IN CONTRACT STRICT LIABILITY OR TORT INCLUDING NEGLIGENCE
197. Window Evaluating Only on Clock Edges Click the amp amp button to AND this condition with the rest of the expression Then select the clock in the Wave window and click Insert Selected Signal and rising You can also select the falling edge or both edges Operators Other buttons will add operators of various kinds see Expression Syntax or you can type them in Formatting the Wave Window Setting Wave Window Display Preferences You can set Wave Window display preferences by selecting Tools Options Wave Preferences when the window is docked in the MDI frame or Tools Window Preferences when the window is undocked These commands open the Wave Window Preferences dialog Figure 8 11 202 ModelSim User s Manual v6 29 February 2007 Waveform Analysis Formatting the Wave Window Figure 8 11 Display Tab of the Wave Window Preferences Dialog xi Display Grid amp Timeline Display Signal Path Snap Distance D elements 10 ipte Use 0 for full path Row Margin 4 pixels Justify Value Child Row Margin 7 Left C Right 2 pixels Enable Disable JV Waveform Popup Enabled Waveform Selection Highlighting Enabled v Double Click to Show Drivers Dataflow Window On Close Warn for Save Format Always undock wave window v On Close Warn for saving editable wave Commands Dataset Prefix Display C Always Show Dataset Prefixes Show Data
198. Y MODEL_TECH_TCL tcl8 3 e set TK_LIBRARY MODEL_TECH_TCL Ak8 3 e setITCL LIBRARY MODEL TECH TCLJitcl3 0 e setITK LIBRARY MODEL TECH TCLJitk3 0 e set VSIM LIBRARY MODEL TECH TCLyvsim Initializes the simulator s Tcl interpreter Checks for a valid license a license is not checked out unless specified by a modelsim ini setting or command line option The next four steps relate to initializing the graphical user interface Sets Tcl variable MTI LIB DIR MODEL TECH TCL Loads MTI LIB DIR vsim pref tcl Loads GUI preferences project file etc from the registry Windows or HOME modelsim UNIX Searches for the modelsim tcl file by evaluating the following conditions e use MODELSIM TCL environment variable if it exists Gf MODELSIM TCL is a list of files each file is loaded in the order that it appears in the list else ModelSim User s Manual v6 2g February 2007 System Initialization Initialization Sequence use modelsim tcl else e use HOME modelsim tcl if it exists That completes the initialization sequence Also note the following about the modelsim ini file e When you change the working directory within ModelSim the tool reads the library vcom and vlog sections of the local modelsim ini file When you make changes in the compiler or simulator options dialog or use the vmap command the tool updates the appropriate sections of the file e The pref tcl file references the default ini
199. You can use the CTRL C keyboard interrupt to break batch simulation in UNIX and Windows environments Standards Supported ModelSim VHDL implements the VHDL language as defined by IEEE Standards 1076 1987 1076 1993 and 1076 2002 ModelSim also supports the 1164 1993 Standard Multivalue Logic System for VHDL Interoperability and the 1076 2 1996 Standard VHDL Mathematical Packages standards Any design developed with ModelSim will be compatible with any other VHDL system that is compliant with the 1076 specs ModelSim Verilog implements the Verilog language as defined by the IEEE Std 1364 1995 and 1364 2005 ModelSim Verilog also supports a partial implementation of SystemVerilog P1800 2005 see lt install_dir gt modeltech docs technotes sysvlog note for implementation details 28 ModelSim User s Manual v6 2g February 2007 Introduction Assumptions Both PLI Programming Language Interface and VCD Value Change Dump are supported for ModelSim users In addition all products support SDF 1 0 through 4 0 except the NETDELAY statement VITAL 2 2b VITAL 95 IEEE 1076 4 1995 and VITAL 2000 IEEE 1076 4 2000 Assumptions We assume that you are familiar with the use of your operating system and its graphical interface We also assume that you have a working knowledge of the design languages Although ModelSim is an excellent tool to use while learning HDL concepts and practices this document is not written to support tha
200. _PATH vsim prompt 1 The dollar sign character is Tcl syntax that indicates a variable The backslash character is an escape character that prevents the variable from being evaluated during the execution of vmap You can easily add additional hierarchy to the path For example vmap MORE_VITAL MY_PATH more_path and_more_path vmap MORE_VITAL MY_PATH more_path and_more_path Referencing Environment Variables There are two ways to reference environment variables within ModelSim Environment variables are allowed in a FILE variable being opened in VHDL For example use std textio all entity test is end architecture only of test is begin process FILE in_file text is in SENV_VAR_NAME begin wait end process end Environment variables may also be referenced from the ModelSim command line or in macros using the Tcl env array mechanism echo env ENV_VAR_NAME 318 ModelSim User s Manual v6 2g February 2007 Simulator Variables Simulator Control Variables Note Environment variable expansion does not occur in files that are referenced via the f argument to vcom vlog or vsim Removing Temp Files VSOUT The VSOUT temp file is the communication mechanism between the simulator kernel and the Graphical User Interface In normal circumstances the file is deleted when the simulator exits If the tool crashes however the temp file must be deleted manually Specifying the location of the temp file with
201. _dir gt win32 mtipli lib out app dll For the Verilog PLI the init function should be init usertfs Alternatively if there is no init usertfs function the init function specified on the command line should be veriusertfs For the Verilog VPI the init function should be vlog startup routines These requirements ensure that the appropriate symbol is exported and thus ModelSim can find the symbol when it dynamically loads the DLL When executing cl commands in a DO file use the NOLOGO switch to prevent the Microsoft C compiler from writing the logo banner to stderr Writing the logo causes Tcl to think an error occurred e MinGW gcc 3 2 3 gcc c l lt install_dir gt include app c gcc shared Bsymbolic o app dll app o L lt install_dir gt win32 Imtipli The ModelSim tool requires the use of MinGW gcc compiler rather than the Cygwin gcc compiler MinGW gcc is available on the ModelSim FTP site Remember to add the path to your gcc executable in the Windows environment variables DPI Imports on Windows Platforms When linking the shared objects be sure to specify one export option for each DPI imported task or function in your linking command line You can use the isymfile argument from the vlog command to obtain a complete list of all imported tasks functions expected by ModelSim As an alternative to specifying one export option for each imported task or function you can make use of the __declspec dllexport
202. able e dest object Required string A full hierarchical path or relative downward path with reference to the calling block to a VHDL signal or Verilog register net This path should match the path that was specified in the init signal spy call that you wish to enable e verbose Optional integer Possible values are 0 or 1 Specifies whether you want a message reported in the transcript stating that an enable occurred and the simulation time that it occurred Default is 0 no message Related tasks init_signal_spy disable_signal_spy Example See init_signal_spy Example ModelSim User s Manual v6 2g 253 February 2007 Signal Spy init signal driver init signal driver The Sinit signal driver system task drives the value of a VHDL signal or Verilog net called the src object onto an existing VHDL signal or Verilog register net called the dest object This allows you to drive signals or nets at any level of the design hierarchy from within a Verilog module e g a testbench The Sinit signal driver system task drives the value onto the destination signal just as if the signals were directly connected in the HDL code Any existing or subsequent drive or force of the destination signal by some other means will be considered with the Sinit signal driver value in the resolution of the signal Call only once The Sinit signal driver system task creates a persistent relationship between the source and destination s
203. able and the change is saved when you exit ModelSim Preferences ux By Window By Name gt Window List Figure F 9 Preferences Dialog Box By Window Tab Dataflow Windows List Windows Main Window Memory Windows Active Process Window Objects Window Source Windows Structure Windows Locals Window Wave Windows X al Main Window Color Scheme assertColor background errorColor errorProjectCompile foreground z nnandDrninant Tarama fun LU rs Note test message Time Ons Iteration O Ir rrun Indian Red f invalid command name rrun VSIM 44 gt Font ms Sans Serif 8 Choose Sample Text 01234567830 DK Apply Cancel The By Name tab lists every Tcl variable in a tree structure Expand the tree highlight a variable and click Change Value to edit the current value 416 ModelSim User s Manual v6 2g February 2007 Setting GUI Preferences Simulator GUI Preferences Figure F 10 Preferences Dialog Box By Name Tab Preferences MT By Window By Name l l Preferences Assertions Compare defaultAddToave 1 if setto 1 comparison items are automatically adde defaultClockName default_clock the default clock name used in the add signal regior defaultDiffsFile compare dif specifies the default file name for saving compare di defaultDiffsReportF compare tx the default file name for a c
204. accSignal ModelSim User s Manual v6 29 February 2007 signal declaration 393 Verilog PLI VPI DPI Support for VHDL Objects The type and fulltype constants for VHDL objects are defined in the acc_vhdl h include file All of these objects except signals are scope objects that define levels of hierarchy in the structure window Currently the PLI ACC interface has no provision for obtaining handles to generics types constants variables attributes subprograms and processes 394 ModelSim User s Manual v6 2g February 2007 IEEE Std 1364 ACC Routines ModelSim Verilog supports the following ACC routines Routines acc append delays acc append pulsere acc close acc collect acc compare handles acc configure acc count acc fetch argc acc fetch argv acc fetch attribute acc fetch attribute int acc fetch attribute str acc fetch defname acc fetch delay mode acc fetch delays acc fetch direction acc fetch edge acc fetch fullname acc fetch fulltype acc fetch index acc fetch location acc fetch name acc fetch paramtype acc fetch paramval acc fetch polarity acc fetch precision acc fetch pulsere acc fetch range acc fetch size acc fetch tfarg acc fetch itfarg acc fetch tfarg int acc fetch itfarg int acc fetch tfarg str acc fetch itfarg str acc fetch timescale info acc fetch type acc fetch type str acc fetch value ModelSim User s Manual v6 29 February 2007 acc free acc handle by name
205. ackage cmath import DPI C function real sin input real x import DPI C function real sqrt input real x endpackage package fli import DPI C function mti Cmd input string cmd endpackage module top import cmath import fli int status A initial begin Sdisplay sin 0 98 Sf sin 0 98 Sdisplay sqrt 0 98 Sf sqrt 0 98 status mti_Cmd change A 123 Sdisplay A 1d status 1d A status end endmodule To simulate you would simply enter a command such as vsim top Platform Specific Information This feature is not supported on AIX On Windows only FLI and PLI commands may be imported in this fashion C library functions are not automatically importable They must be wrapped in user DPI C functions which are brought into the simulator using the sv_lib argument Use Model for Read Only Work Libraries You may want to create the work library as a read only entity which enables multiple users to simultaneously share the design library at runtime The steps are as follows e Windows and RS6000 RS64 On these platforms simply change the permissions on the design library to read only by issuing a command such as chmod R a w lt libname gt Do this after you have finished compiling with vlog vcom and vopt 372 ModelSim User s Manual v6 2g February 2007 Verilog PLI VPI DPI Compiling and Linking C Applications for PLI VPI DPI e All Other Platforms If a design co
206. ading with global symbol visibility 387 Shortcuts text editing 404 shortcuts command history 403 ModelSim User s Manual v6 2g February 2007 JKLMNOPQRSTUVWX YZ command line caveat 403 List window 407 Main window 404 Source window 404 Wave window 408 show drivers Dataflow window 227 Wave window 221 Show_ WarnMatchCadence ini file variable 323 Show_BadOptionWarning ini file variable 323 Show_Lint ini file variable VCOM 326 Show_Lint ini file variable VLOG 323 Show source ini file variable VCOM 326 Show source ini file variable VLOG 323 Show VitalChecksOpt ini file variable 327 Show VitalChecksWarning ini file variable 327 Show WarnCantDoCoverage ini file variable 323 Show WarnCantDoCoverage variable 327 Show Warningl ini file variable 327 Show Warningl0O ini file variable 328 Show Warning2 ini file variable 327 Show Warning3 ini file variable 327 Show Warning4 ini file variable 328 Show Warnings ini file variable 328 Show Warning9 ini file variable 328 Show WarnLocallyStaticError variable 328 signal groups in wave window 208 Signal Spy 125 245 disable 241 252 enable 242 253 signal force 258 signal force 126 248 signal release 260 signal release 126 250 signals combining into a user defined bus 215 Dataflow window displaying in 49 225 driving in the hierarchy 243 435 ABCDEFGH I filtering in the Objects window 60 hierarchy driving in 24
207. ag them simultaneously ModelSim User s Manual v6 2g 89 February 2007 Projects Changing Compile Order Auto Generating Compile Order Auto Generate is supported for HDL only designs The Auto Generate button in the Compile Order dialog see above determines the correct compile order by making multiple passes over the files It starts compiling from the top if a file fails to compile due to dependencies it moves that file to the bottom and then recompiles it after compiling the rest of the files It continues in this manner until all files compile successfully or until a file s can t be compiled for reasons other than dependency Files can be displayed in the Project tab in alphabetical or compile order by clicking the column headings Keep in mind that the order you see in the Project tab is not necessarily the order in which the files will be compiled Grouping Files You can group two or more files in the Compile Order dialog so they are sent to the compiler at the same time For example you might have one file with a bunch of Verilog define statements and a second file that is a Verilog module You would want to compile these two files together To group files follow these steps 1 Select the files you want to group Figure 3 12 Grouping Files xi m Curent Order cache v util vhd set vhd top vhd Auto Generate OK Cancel 2 Click the Group button E 90 ModelSim User s Manual v6 2g
208. age System Variables The message system variables located under the msg system heading help you identify and troubleshoot problems while using the application See also Message System 344 ModelSim User s Manual v6 2g February 2007 Simulator Variables Simulator Control Variables error This variable changes the severity of the listed message numbers to error Refer to Changing Message Severity Level for more information e Value Range list of message numbers e Default none fatal This variable changes the severity of the listed message numbers to fatal Refer to Changing Message Severity Level for more information e Value Range list of message numbers Default none note This variable changes the severity of the listed message numbers to note Refer to Changing Message Severity Level for more information e Value Range list of message numbers e Default none suppress This variable suppresses the listed message numbers Refer to Changing Message Severity Level for more information e Value Range list of message numbers Default none warning This variable changes the severity of the listed message numbers to warning Refer to Changing Message Severity Level for more information e Value Range list of message numbers Default none msgmode This variable controls where the simulator outputs elaboration and runtime messages Refer to the section Message Viewer for more info
209. ain Window Active Processes displays all processes that are scheduled Active Processes Pane to run during the current simulation cycle Dataflow displays physical connectivity and Dataflow Window lets you trace events causality List shows waveform data in a tabular List Window format Locals displays data objects that are Locals Pane immediately visible at the current PC of the selected process a Workspace tab and MDI windows Memory Panes that show memories and their contents displays signal or variable values at the Watch Pane current simulation time Objects displays all declared data objects in the Objects Pane current scope Source a text editor for viewing and editing Source Window HDL DO etc files Transcript keeps a running history of commands Transcript and messages and provides a command line interface displays waveforms Wave Window Workspace provides easy access to projects Workspace libraries compiled design units memories etc The windows and panes are customizable in that you can position and size them as you see fit and ModelSim will remember your settings upon subsequent invocations See Navigating the Graphic User Interface for more details 34 ModelSim User s Manual v6 2g February 2007 Simulator Windows Design Object Icons and Their Meaning Design Object Icons and Their Meaning The color and shape of icons convey information about the language and
210. akpoints File line breakpoints are set on executable lines in your source files When the line is hit the simulator stops and the Source window opens to show the line with the breakpoint You can change this behavior by editing the PrefSource OpenOnBreak variable See Simulator GUI Preferences for details on setting preference variables Setting file line breakpoints from the command line You use the bp command to set a file line breakpoint from the VSIM gt prompt Setting file line breakpoints from the GUI File line breakpoints are most easily set using your mouse in the Source Window Click on a blue line number at the left side of the Source window and a red diamond denoting a breakpoint 222 ModelSim User s Manual v6 2g February 2007 Waveform Analysis Creating and managing breakpoints will appear The breakpoints are toggles click once to create the colored diamond click again to disable or enable the breakpoint To delete the breakpoint completely click the red diamond with your right mouse button and select Remove Breakpoint ModelSim User s Manual v6 2g 223 February 2007 Waveform Analysis Creating and managing breakpoints 224 ModelSim User s Manual v6 29 February 2007 Chapter 9 Tracing Signals with the Dataflow Window This chapter discusses how to use the Dataflow window for tracing signal values and browsing the physical connectivity of your design Dataflow Window Overview The Dataflow window allo
211. al Numbers The reading and writing of hexadecimal numbers is not specified in standard VHDL The Issues Screening and Analysis Committee of the VHDL Analysis and Standardization Group ISAC VASG has specified that the TextIO package reads and writes only decimal numbers To expand this functionality ModelSim supplies hexadecimal routines in the package io utils which is located in the file install dir2 modeltech examples misc io utils vhd To use these routines compile the io utils package and then include the following use clauses in your VHDL source code use std textio all use work io utils all Dangling Pointers Dangling pointers are easily created when using the TextIO package because WRITELINE de allocates the access type pointer that is passed to it Following are examples of good and bad VHDL coding styles Bad VHDL because L1 and L2 both point to the same buffer READLINE infile L1 Read and allocate buffer L2 L1 Copy pointers WRITELINE outfile L1 Deallocate buffer Good VHDL because L1 and L2 point to different buffers READLINE infile L1 Read and allocate buffer L2 new string Ll all Copy contents WRITELINE outfile L1 Deallocate buffer The ENDLINE Function The ENDLINE function described in the JEEE Standard VHDL Language Reference Manual IEEE Std 1076 1987 contains invalid VHDL syntax and cannot be implemented in VHDL This ModelSim Us
212. also windows Dataflow window dataflow bsm file 235 Dataset Browser 180 Dataset Snapshot 182 datasets 175 managing 180 opening 178 restrict dataset prefix display 181 view structure 179 DatasetSeparator ini file variable 332 debugging the design overview 26 default binding BindAtCompile ini file variable 324 disabling 116 default binding rules 115 Default editor changing 314 DefaultForceKind ini file variable 332 DefaultRadix ini file variable 332 DefaultRestartOptions ini variable 333 DefaultRestartOptions variable 348 delay delta delays 116 modes for Verilog models 162 DelayFileOpen ini file variable 333 deleting library contents 101 delta collapsing 182 delta simulator state variable 349 deltas in List window 218 referencing simulator iteration as a simulator state variable 349 dependent design units 110 descriptions of HDL items 67 design library creating 101 logical name assigning 102 427 ABCDEFGHIJKLMNOPQRSTUVWXYZ mapping search rules 104 resource type 99 VHDL design units 109 working type 99 design object icons described 35 design units 99 DEVICE matching to specify path delays 269 dialogs Runtime Options 342 Direct Programming Interface 365 directories moving libraries 104 disable signal spy 241 DisableOpt ini file variable 321 display preferences Wave window 202 distributed delay mode 163 dividers Wave window 206 DLL files loading 37
213. amed mgc location map in the following locations in order e the current directory e your home directory e the directory containing the ModelSim binaries e the ModelSim installation directory Use these two steps to map your files ModelSim User s Manual v6 2g 353 February 2007 Location Mapping Referencing Source Files with Location Maps 1 Set the environment variable MGC LOCATION MAP to the path to your location map file 2 Specify the mappings from physical pathnames to logical pathnames SSRC home vhdl src usr vhdl src SIEEE usr modeltech ieee Pathname Syntax The logical pathnames must begin with and the physical pathnames must begin with The logical pathname is followed by one or more equivalent physical pathnames Physical pathnames are equivalent if they refer to the same physical directory they just have different pathnames on different systems How Location Mapping Works When a pathname is stored an attempt is made to map the physical pathname to a path relative to a logical pathname This is done by searching the location map file for the first physical pathname that is a prefix to the pathname in question The logical pathname is then substituted for the prefix For example usr vhdl src test vhd is mapped to SRC test vhd If a mapping can be made to a logical pathname then this is the pathname that is saved The path to a source file entry for a design unit in a library is a good example
214. and functions registered by calls to mti_RegisterUserTF will be defined e If an init_usertfs function does not exist but a veriusertfs table does exist then only those system tasks and functions listed in the veriusertfs table will be defined e If an init_usertfs function does not exist and a veriusertfs table does not exist but a vlog_startup_routines table does exist then only those system tasks and functions and callbacks registered by functions in the vlog_startup_routines table will be defined As a result when PLI and VPI applications exist in the same application object file they must be registered in the same manner VPI registration functions that would normally be listed in a vlog startup routines table can be called from an init usertfs function instead Registering DPI Applications DPI applications do not need to be registered However each DPI imported or exported task or function must be identified using SystemVerilog import DPI C or export DPI C syntax Examples of the syntax follow export DPI C task tl task tl input int i output int o end task import DPI C function void fl input int i output int o Your code must provide imported functions or tasks compiled with an external compiler An imported task must return an int value 1 indicating that it is returning due to a disable or 0 indicating otherwise These imported functions or objects may then be loaded as a share
215. and Simulating with Accelerated VITAL Packages lesse 124 LaL PAC aS yg s saisons xk Sd EX Sha SURVIE UR al QR RDS egi eae ee 124 Bet resolution Lus vade en d Ea Ead a X RR Ad RE eek ra doa ERR adu dab d 125 ipu signal VOC kes ner ener ERU E dew EP IARE RESTRIQuUR ES AR QAO rd dea 125 iut Serial Spy eoa erede ops eeu done eid Rs esae eens eats oie lindos sh 125 Sinal TUIGSU ondes ct eR REPERTA ERRE RE nese Gees Bees Gee Rohe oO Reset Sharks 126 signal release Oo esas ER EEATEESRERPENPRRE EG oases EF RENATA dee eae pP kd ee 126 tO Teal ese helles I D RE SRE Gadd shee RUMP seas ade e 126 O MIME us aues ech caus oe eae eine eM Re faros tet en du mud sane 127 Modeling Memory cssuree pu X REA RR EGG Ru RRRESRE REF Gu Ru RES X eR 128 VHDL and V HDL9S Exaiiples 2ccsacsceersoene cease ta aen oie saeco RF 129 VHDLO2 Gxample 3i5 cake uade aa Mie awe cata ead aaah apnea esa Ra ee RA dd RR 132 Affecting Performance by Cancelling Scheduled Events 0000005 136 Converting an Integer Into a bit_vector 0 eee eee tenes 136 Chapter 6 Verilog and SystemVerilog Simulation 0 cece cece cece cece ee eee ee ees 139 liu y cs gc Bo Sues Chea ea dae wh ee oA Shee de eh e a ot weed nee eee eee 139 Basic Verilog FIOW 222235 cndcnadeeavada diaas a dba a eieaa ni id RE baal rcs dod aw 139 Compiling Verilog PIHeS 22242cncmerhehbc nh ER AERIS iaaa ia d Ride d 139 Creating a Working Library 2 242 c224cn
216. anes in the Wave Window pathnames values waveforms M wave def ult jase Ad 22 AE ds NL sls Boe jtest counter clk test counter reset Q test counter count 4 7 4 434260 ns to 4346 jns qum Now 495 852 ns Delta 2 List Window Overview The List window displays simulation results in tabular format Common tasks that people use the window for include e Using gating expressions and trigger settings to focus in on particular signals or events See Configuring New Line Triggering in the List Window e Debugging delta delay issues See Delta Delays for more information The window is divided into two adjustable panes which allows you to scroll horizontally through the listing on the right while keeping time and delta visible on the left 190 ModelSim User s Manual v6 2g February 2007 Waveform Analysis Adding Objects to the Wave or List Window Figure 8 4 Tabular Format of the List Window GN lins File Edit View Add Tools Window o8B4 22800 AE psc ftest sm into delta ftest sm outof f test sm rst test_sm clky 490000 0 00000030 Pte ee OOCooddoooo00000000000001010 491000 1 00000030 eal fol al 495000 0 oooooo000 thea oy ah jc 500000 0 oo000000 171 O O j 510000 0 00000000 171 O l1 i 511000 1 ooooo0000 isa un ak jo ooo00000 01 515000 0 40000000 187 Olt 520000 0 40000000 is 0 O j 529000 1 40000000 187 O O maau a a uulu u aulu e e fu nd
217. antiated module or UDP in the library that contains the module that does the instantiation In the example above you would invoke vsim as follows vsim L work L lib1 L lib2 top SystemVerilog Multi File Compilation Issues Declarations in Compilation Unit Scope System Verilog allows the declaration of types variables functions tasks and other constructs in compilation unit scope unit The visibility of declarations in unit scope does not extend outside the current compilation unit Thus it is important to understand how compilation units are defined by the tool during compilation By default vlog operates in Single File Compilation Unit mode SFCU This means the visibility of declarations in unit scope terminates at the end of each source file Visibility does not carry forward from one file to another except when a module interface or package ModelSim User s Manual v6 2g 145 February 2007 Verilog and SystemVerilog Simulation Compiling Verilog Files declaration begins in one file and ends in another file In that case the compilation unit spans from the file containing the beginning of the declaration to the file containing the end of the declaration vlog also supports a non default behavior called Multi File Compilation Unit mode MFCU In MFCU mode vlog compiles all files given on the command line into one compilation unit You can invoke vlog in MFCU mode as follows e Fora specific compilation with the
218. ariables in the modelsim file on Unix Linux platforms or the Registry on Windows platforms The variable values save automatically when you exit ModelSim Some of the variables are modified by actions you take with menus or windows e g resizing a window changes its geometry variable Or you can edit the variables directly either from the ModelSim prompt or the Edit Preferences dialog Customizing the Simulator GUI Layout You can customize the layout of panes windows toolbars etc This section discusses layouts and how they are used in ModelSim Layouts and Modes of Operation ModelSim ships with three default layouts that correspond to three modes of operation Table F 1 Predefined GUI Layouts NoDesign a design is not yet loaded Simulate a design is loaded a design is loaded with code coverage enabled As you load and unload designs ModelSim switches between the layouts Custom Layouts You can create custom layouts or modify the three default layouts Creating Custom Layouts To create a custom layout or modify one of the default layouts follow these steps 1 Rearrange the GUI as you see fit see Navigating the Graphic User Interface for details ModelSim User s Manual v6 29 411 February 2007 Setting GUI Preferences Customizing the Simulator GUI Layout 2 Select Layout Save Figure F 1 Save Current Window Layout Dialog Box lolx Save Layout As NoD esign wi v Use this layout when no desig
219. arning messages in ModelSim Verilog These are not implemented in ModelSim Verilog and any code containing these directives may behave differently in ModelSim Verilog than in Verilog XL default trireg strength signed unsigned Verilog PLI VPI and SystemVerilog DPI ModelSim supports the use of the Verilog PLI Programming Language Interface and VPI Verilog Procedural Interface and the SystemVerilog DPI Direct Programming Interface These three interfaces provide a mechanism for defining tasks and functions that communicate with the simulator through a C procedural interface For more information on the ModelSim implementation see Verilog PLI VPI DPI ModelSim User s Manual v6 2g 173 February 2007 Verilog and SystemVerilog Simulation Verilog PLI VPI and SystemVerilog DPI 174 ModelSim User s Manual v6 2g February 2007 Chapter 7 WLF Files Datasets and Virtuals This chapter describes the Wave Log Format WLF file and how you should and can use it in your simulation flow A ModelSim simulation can be saved to a wave log format WLF file for future viewing or comparison to a current simulation We use the term dataset to refer to a WLF file that has been reopened for viewing You can open more than one WLF file for simultaneous viewing You can also create virtual signals that are simple logical combinations of or logical functions of signals from different datasets WLF files are recordings of simulation ru
220. asednde escent LP QUAE TAS qEL aa 56 Table 2 10 Wave Window Toolbar Buttons and Menu Selections 76 Table 6 1 Sample Modules With and Without Timescale Directive 152 Table 6 2 Evaluation 1 of always Statements lees 155 Table 6 3 Evaluation 2 of always Statement lseeeeeeeleeeeeeeee 156 Table 6 4 IEEE Std 1364 System Tasks and Functions 1 0 000 5 164 Table 6 5 IEEE Std 1364 System Tasks and Functions 2 0 0 0 0000005 164 Table 6 6 IEEE Sid 1364 System Tasks i2 ekek eR RE RETRE4R RR RENR ens 164 Table 6 7 IEEE Std 1364 File I O Tasks 0 0 cece eee eens 165 Table 6 8 System Verilog System Tasks and Functions 1 0 0000 166 Table 6 9 System Verilog System Tasks and Functions 2 llllelleeesssn 166 Table 6 10 SystemVerilog System Tasks and Functions 4 000000 166 Table 7 1 WLF Pile Parameters i eRk RT RRRERWO e boeri pEr DeC EP ER dE 177 Table 7 2 Structure Tab Columns 2oxesuvenbensexsteessee 33e ene AE EG re RR 179 Table 7 3 vsim Arguments for Collapsing Time and Delta Steps 183 Table 8 1 Actions for Cursors Lou xso sso Re eee ened ey Ryo sad der esr e Rcs 193 Table 8 2 Actions for Time Markers llelleeeeeeeeeeee 195 Table 8 3 Actions Tor Bookmarks i2 osos se ht hr REAPER GUEST ERRAT KR 197 Table 8 4 Actions Tor Dividers is 6854005052 eee oh pak eShea a
221. aset save or dataset snapshot you must end a simulation session with a quit or quit sim command in order to produce a valid WLF file If you don t end the simulation in this manner the WLF file will not close properly and ModelSim may issue the error message bad magic number when you try to open an incomplete dataset in subsequent sessions If you end up with a damaged WLF file you can try to repair it using the wlfrecover command WLF File Parameter Overview There are a number of WLF file parameters that you can control via the modelsim ini file or a simulator argument This section summarizes the various parameters Table 7 1 WLF File Parameters Feature vsim argument modelsim ini Default WLF Filename wlf filename WLFFilename lt filename gt vsim wlf WLE Size Limit wlfslim lt n gt WLESizeLimit n no limit WLE Time Limit wlftlim lt t gt WLFTimeLimit lt t gt no limit WLE Compression wlfcompress WLFCompress Oll 1 wlfcompress wlfnocompress WLF Optimization wlfopt WLFOptimize Ol1 1 wlfopt wlfnoopt WLF Delete on Quit wlfdeleteonquit WLFDeleteOnQuit Ol wlfnodeleteonquit WLF Cache Size Wlfcachesize n WLFCacheSize n WLF Collapse Mode wlfnocollapse WLFCollapseModel 01112 wlfcollapsedelta wlfcollapsetime 1 These parameters can also be set using the dataset config command e WLF Filename Specify the name of the WLF file
222. ate Close Project Compile Order Update Compile Report l m Compile Summary Properties Project Settings Compile Properties c E l Once compilation is finished click the Library tab expand library work by clicking the and you will see the compiled design units Figure 3 7 Click Plus Sign to Show Design Hierarchy W m rk space i modelsim_lib Library MODEL TECH modelsim il std Library MODEL TECH std std developerskit Library MODEL TECH std develor synopsys Library MODEL TECH synopsys verilog Library MODEL_TECH verilog work Library C 6 1 Tutorial examples work n counter Module C 6 1 Tutorial examples count n lest counter Module C B 1 Tutorial examples tcoun Step 4 Simulating a Design To simulate a design do one of the following e double click the Name of an appropriate design object such as a testbench module or entity in the Library tab of the Workspace right click the Name of an appropriate design object and select Simulate from the popup menu 86 ModelSim User s Manual v6 2g February 2007 Projects Getting Started with Projects e select Simulate gt Start Simulation from the menus to open the Start Simulation dialog Figure 3 8 Select a design unit in the Design tab Set other options in the VHDL Verilog Libraries SDF and Others tabs Then click OK to start the simulation Figure 3 8 Sta
223. ate and time and deposits it into a VHDL signal of type STRING If a particular environment variable DO_ECHO is set the function also echoes the new date and time to the transcript file by examining the VHDL variable in VHDL source signal datime string 1 to 28 28 spaces on VSIM command line or in macro proc set date global env set do the echo set env DO ECHO set s clock format clock seconds force deposit datime s if do the echo echo New time is examin value datime bp src waveadd vhd 133 set_date continue sets the breakpoint to call set_date This next example shows a complete Tcl script that restores multiple Wave windows to their state in a previous simulation including signals listed geometry and screen position It also adds buttons to the Main window toolbar to ease management of the wave files This file contains procedures to manage multiple wave files Source this file from the command line or as a startup script source path wave mgr tcl add wave buttons Add wave management buttons to the main toolbar new save and load new wav Dialog box creates a new wave window with the user provided name named wave name Creates a new wave window with the specified title save wave lt file root gt Saves name window location and contents for all open windows wave windows Creates file root n do file for each
224. ations that do not explicitly declare a decay time The decay time can be expressed as a real or integer number or as infinite to specify that the charge never decays delay mode distributed This directive disables path delays in favor of distributed delays See Delay Modes for details delay mode path This directive sets distributed delays to zero in favor of path delays See Delay Modes for details delay mode unit This directive sets path delays to zero and non zero distributed delays to one time unit See Delay Modes for details delay mode zero This directive sets path delays and distributed delays to zero See Delay Modes for details uselib This directive is an alternative to the v y and libext source library compiler arguments See Verilog XL uselib Compiler Directive for details The following Verilog XL compiler directives are silently ignored by ModelSim Verilog Many of these directives are irrelevant to ModelSim Verilog but may appear in code being ported from Verilog XL 172 ModelSim User s Manual v6 2g February 2007 Verilog and SystemVerilog Simulation Verilog PLI VPI and SystemVerilog DPI accelerate autoexpand vectornets disable portfaults enable portfaults expand vectornets noaccelerate noexpand vectornets noremove gatenames noremove_netnames nosuppress faults remove gatenames remove netnames suppress faults The following Verilog XL compiler directives produce w
225. attribute assignment attribute mti inhibit inline of pack package is true Do similarly for entities and architectures Differences Between Language Versions There are three versions of the IEEE VHDL 1076 standard VHDL 1987 VHDL 1993 and VHDL 2002 The default language version for ModelSim is VHDL 2002 If your code was written according to the 87 or 93 version you may need to update your code or instruct ModelSim to use the earlier versions rules To select a specific language version do one of the following Select the appropriate version from the compiler options menu in the GUI Invoke vcom using the argument 87 93 or 2002 Set the VHDL93 variable in the vcom section of the modelsim ini file Appropriate values for VHDL93 are 0 87 or 1987 for VHDL 1987 1 93 0r 1993 for VHDL 1993 ModelSim User s Manual v6 2g 111 February 2007 VHDL Simulation Compiling VHDL Files 2 02 or 2002 for VHDL 2002 The following is a list of language incompatibilities that may cause problems when compiling a design 112 VHDL 93 and VHDL 2002 The only major problem between VHDL 93 and VHDL 2002 is the addition of the keyword PROTECTED VHDL 93 programs which use this as an identifier should choose a different name All other incompatibilities are between VHDL 87 and VHDL 93 VITAL and SDF It is important to use the correct language version for VITAL VITAL2000 must be compiled with VHDL 93 or
226. ave Window Layout Automatically Resetting Layouts to Their Defaults You can reset the layouts for the three modes to their original defaults Select Layout Reset This command does not delete custom layouts Navigating the Graphic User Interface This section discusses how to rearrange various elements of the GUI Manipulating Panes Window panes e g Workspace can be positioned at various places within the parent window or they can be dragged out undocked of the parent window altogether Figure F 2 GUI Window Pane HA sv_std Library MODE H vital2000 Library MODE f ieee Library MODE i modelsim_lib Library MODE H std Library MODE i std_developerskit Library MODE i synopsys Library MODE H veros Library MODE a n Library EE ModelSim User s Manual v6 29 413 February 2007 Setting GUI Preferences Navigating the Graphic User Interface Moving Panes When you see a double bar at the top edge of a pane it means you can modify the pane position Figure F 3 GUI Double Bar Workspace 3 L 2 FH A Click and drag the pane handle in the middle of a double bar your mouse pointer will change to a four headed arrow when it is in the correct location to reposition the pane inside the parent window As you move the mouse to various parts of the main window a gray outline will show you valid locations to drop the pane Or drag th
227. ay be executed as well Table 13 8 Commands for Handling Breakpoints and Errors in Macros command run continue continue as if the breakpoint had not been executed completes the run that was interrupted onbreak specify a command to run when you hit a breakpoint within a macro onElabError specify a command to run when an error is encountered during elaboration onerror specify a command to run when an error is encountered within a macro status get a traceback of nested macro calls when a macro is interrupted abort terminate a macro once the macro has been interrupted or paused pause cause the macro to be interrupted the macro can be resumed by entering a resume command via the command line 310 ModelSim User s Manual v6 2g February 2007 Tcl and Macros DO Files Macros DO Files You can also set the OnErrorDefaultAction Tcl variable to determine what action ModelSim takes when an error occurs To set the variable on a permanent basis you must define the variable in a modelsim tcl file see The modelsim tcl File for details Error Action in DO Files If a command in a macro returns an error ModelSim does the following 1 If an onerror command has been set in the macro script ModelSim executes that command The onerror command must be placed prior to the run command in the DO file to take effect 2 If no onerror command has been specified in the script ModelSim checks the OnErrorDefaul
228. ay prefer to compile your entire design along with the incr argument This causes the compiler to automatically determine which modules have changed and generate code only for those modules The following is an example of how to compile a design with automatic incremental compilation vlog incr top v and2 v or2 v Compiling module top Compiling module and2 Compiling module or2 Top level modules top Now suppose that you modify the functionality of the or2 module vlog incr top v and2 v or2 v Skipping module top Skipping module and2 Compiling module or2 Top level modules top The compiler informs you that it skipped the modules top and and2 and compiled or2 Automatic incremental compilation is intelligent about when to compile a module For example changing a comment in your source code does not result in a recompile however changing the compiler command line arguments results in a recompile of all modules Note LL Changes to your source code that do not change functionality but that do affect source code line numbers such as adding a comment line will cause all affected modules to be recompiled This happens because debug information must be kept current so that ModelSim can trace back to the correct areas of the source code ModelSim User s Manual v6 2g 143 February 2007 Verilog and SystemVerilog Simulation Compiling Verilog Files Library Usage All modules and UDPs
229. be recognized as a memory the index must be of an integral type see above or wildcard type For associative arrays the element kind can be any type allowed for fixed size arrays Viewing Single and Multidimensional Memories Single dimensional arrays of integers are interpreted as 2D memory arrays In these cases the word width listed in the Memory List pane is equal to the integer size and the depth is the size of the array itself Memories with three or more dimensions display with a plus sign next to their names in the Memory List Click the to show the array indices under that level When you finally expand down to the 2D level you can double click on the index and the data for the selected 2D slice of the memory will appear in a memory contents pane in the MDI frame Viewing Packed Arrays By default packed dimensions are treated as single vectors in the memory contents pane To expand packed dimensions of packed arrays select View Memory Contents Expand Packed Memories To change the permanent default edit the PrefMemory ExpandPackedMem variable This variable affects only packed arrays If the variable is set to 1 the packed arrays are treated as unpacked arrays and are expanded along the packed dimensions such that they appear as a linearized bit vector See Simulator GUI Preferences for details on setting preference variables Viewing Memory Contents When you double click an instance on the Memory
230. bility 387 specifying which apps to load 367 Veriuser entry 367 ModelSim User s Manual v6 29 February 2007 JKLMNOPQRSTUVWXYZ PLI VPI 173 tracing 398 PLI VPI DPI 365 registering DPlapplications 369 specifying the DPI file to load 387 PLIOBJS environment variable 317 367 PORT matching to input ports 268 Port driver data capturing 286 Postscript saving a waveform in 214 saving the Dataflow display in 233 precedence of variables 349 precision simulator resolution 151 preference variables Ani files located in 319 editing 415 saving 415 preferences saving 415 Wave window display 202 PrefMain EnableCommandHelp 40 PrefMain ShowFilePane preference variable 38 PrefMemory ExpandPackedMem variable 57 primitives symbols in Dataflow window 235 printing Dataflow window display 233 waveforms in the Wave window 214 Programming Language Interface 173 365 project tab information in 88 sorting 89 projects 81 accessing from the command line 97 adding files to 84 benefits 81 close 88 compile order 89 changing 89 compiler properties in 94 compiling files 85 creating 83 creating simulation configurations 91 folders in 92 433 ABCDEFGH I grouping files in 90 loading a design 86 MODELSIM environment variable 315 open and existing 88 overview 81 protected types 128 Q quick reference table of simulation tasks 22 Quiet ini file variable
231. ble below maps the VCD commands to their associated tasks Table 12 1 VCD Commands and SystemTasks VCD commands vcd add vcd checkpoint VCD system tasks dumpvars dumpall vcd file dumpfile vcd flush vcd limit dumpflush dumplimit vcd off dumpoff ved on dumpon ModelSim also supports extended VCD dumpports system tasks The table below maps the VCD dumpports commands to their associated tasks Table 12 2 VCD Dumpport Commands and System Tasks VCD dumpports commands vcd dumpports VCD system tasks dumpports vcd dumpportsall dumpportsall vcd dumpportsflush dumpportsflush vcd dumpportslimit dumpportslimit vcd dumpportsoff dumpportsoff vcd dumpportson dumpportson ModelSim User s Manual v6 2g February 2007 281 Value Change Dump VCD Files VCD File from Source To Output ModelSim supports multiple VCD files This functionality is an extension of the IEEE Std 1364 specification The tasks behave the same as the IEEE equivalent tasks such as dumpfile dumpvar etc The difference is that fdumpfile can be called multiple times to create more than one VCD file and the remaining tasks require a filename argument to associate their actions with a specific file Table 12 3 VCD Commands and System Tasks for Multiple VCD Files VCD commands VCD system tasks vcd add file filename fdumpvars ved checkpo
232. ble instructs the tool to disable System Verilog and Verilog 2001 support making the compiler compatible with IEEE Std 1364 1995 e Value Range 0 ModelSim User s Manual v6 2g 323 February 2007 Simulator Variables Simulator Control Variables e Default off 0 VHDL Compiler Control Variables You can find these variables under the heading vcom BindAtCompile This variable instructs the tool to perform VHDL default binding at compile time rather than load time Refer to Default Binding for more information e Value Range 0 1 e Default off 0 CheckSynthesis This variable turns on limited synthesis rule compliance checking which includes checking only signals used read by a process and understanding only combinational logic not clocked logic e Value Range 0 1 e Default off 0 DisableOpt This variable disables all optimizations enacted by the compiler similar to using the O0 argument to vcom e Value Range 0 1 e Default off 0 Explicit This variable enables the resolving of ambiguous function overloading in favor of the explicit function declaration not the one automatically created by the compiler for each type declaration e Value Range 0 1 e Default on 1 IgnoreVitalErrors This variable instructs the tool to ignore VITAL compliance checking errors e Value Range 0 1 324 ModelSim User s Manual v6 2g February 2007 Simulator Variables Simulator Control Variables
233. bles lint style checking e Value Range 0 1 e Default off 0 Show_source This variable shows source line containing error 326 ModelSim User s Manual v6 2g February 2007 Simulator Variables Simulator Control Variables e Value Range 0 1 e Default off 0 Show VitalChecksOpt This variable enables VITAL optimization warnings e Value Range 0 1 e Default on 1 Show_VitalChecksWarnings This variable enables VITAL compliance check warnings e Value Range 0 1 e Default on 1 Show_WarnCantDoCoverage This variable enables warnings when the simulator encounters constructs which code coverage cannot handle e Value Range 0 1 e Default on 1 Show Warning1 This variable enables unbound component warnings e Value Range 0 1 e Default on 1 Show Warning2 This variable enables process without a wait statement warnings e Value Range 0 1 e Default on 1 Show Warning3 This variable enables null range warnings e Value Range 0 1 ModelSim User s Manual v6 2g 327 February 2007 Simulator Variables Simulator Control Variables e Default on 1 Show Warning4 This variable enables no space in time literal warnings e Value Range 0 1 e Default on 1 Show Warning5 This variable enables multiple drivers on unresolved signal warnings e Value Range 0 1 e Default on 1 Show Warning9 This variable enables warnings about signal value dependency at elaboration e Value Range 0 1 e Default o
234. board Shortcuts The following mouse actions and keystrokes can be used in the Wave window 408 Table E 5 Wave Window Mouse Shortcuts Mouse action Result Ctrl Click left mouse button and drag Ctrl Click left mouse button Zoom area in and drag zoom out Ctrl Click left mouse button M zoom fit and drag Click left mouse button and drag moves closest cursor Ctrl Click left mouse button on a scrolls window to very top or scroll bar arrow bottom vertical scroll or far left or right horizontal scroll Click middle mouse button in scroll bar scrolls window to position of UNIX only click 1 If you enter zoom mode by selecting View gt Zoom gt Mouse Mode gt Zoom Mode you do not need to hold down the Ctrl key Table E 6 Wave Window Keyboard Shortcuts Keystroke i Shift i Action bring into view and center the currently active cursor zoom in mouse pointer must be over the cursor or waveform panes o Shift o zoom out mouse pointer must be over the cursor or waveform panes f Shift f zoom full mouse pointer must be over the cursor or waveform panes l Shift 1 zoom last mouse pointer must be over the cursor or waveform panes r Shift r zoom range mouse pointer must be over the cursor or waveform panes ModelSim User s Manual v6 2g February 2007 Command and Keyboard Shortcuts Wave Window Mouse
235. but before any of the simulation state has been restored This allows the PLI application to prepare for the restore but it shouldn t restore its state with calls to tf read restart until it is called with reason restart The reason startofrestart value is passed only for a restore command and not in the case that the simulator is invoked with restore reason restart For the execution of the restore command This is when the PLI application must restore its state with calls to tf read restart reason reset For the execution of the restart command This is when the PLI application should free its memory and reset its state We recommend that all PLI applications reset their internal state during a restart as the shared library containing the PLI code might not be 390 ModelSim User s Manual v6 2g February 2007 Verilog PLI VPI DPI The sizetf Callback Function reloaded See the keeploaded and keeploadedrestart arguments to vsim for related information reason_endofreset For the completion of the restart command after the simulation state has been reset but before the design has been reloaded reason_interactive For the execution of the stop system task or any other time the simulation is interrupted and waiting for user input reason scope For the execution of the environment command or selecting a scope in the structure window Also for the call to acc set interactive scope if the callback flag argument is
236. by clicking the column list drop down arrow and selecting an object Quick Access Toolbars Toolbar buttons provide access to commonly used commands and functions Toolbars can be docked and undocked moved to or from the main toolbar area by clicking and dragging on the toolbar handle at the left edge of a toolbar Figure F 8 Toolbar Manipulation Toolbar Handle You can also hide show the various toolbars To hide or show a toolbar right click on a blank spot of the main toolbar area and select a toolbar from the list To reset toolbars to their original state right click on a blank spot of the main toolbar area and select Reset Simulator GUI Preferences Simulator GUI preferences are stored by default either in the modelsim file in your HOME directory on UNIX Linux platforms or the Registry on Windows platforms ModelSim User s Manual v6 2g 415 February 2007 Setting GUI Preferences Simulator GUI Preferences Setting Preference Variables from the GUI To edit a variable value from the GUI select Tools Edit Preferences The dialog organizes preferences by window and by name The By Window tab primarily allows you to change colors and fonts for various GUI objects For example if you want to change the color of assertion messages in the Main window you would select Main window in the first column select assertColor in the second column and click a color on the palette Clicking OK or Apply changes the vari
237. c E allow shlib undefined o math app so math app o Im 382 ModelSim User s Manual v6 2g February 2007 Verilog PLI VPI DPI Compiling and Linking C Applications for PLI VPI DPI 32 bit Solaris Platform If your PLI VPI application uses anything from a system library you will need to specify that library when you link your PLI VPI application For example to use the standard C library specify lc to the Id command e GNU C compiler version gcc 3 2 or later g c I lt install_dir gt modeltech include app cpp Id G Bsymbolic o app so app o lc e Sun Forte C Compiler cc c l lt install_dir gt modeltech include app cpp Id G Bsymbolic o app so app o lc 64 bit Solaris Platform e GNU C compiler version gcc 3 2 or later g c l lt install_dir gt modeltech include m64 fPIC app cpp g shared Bsymbolic o app so m64 app o This was tested with gcc 3 2 2 You may need to add the location of libgcc_s so 1 to the LD LIBRARY PATH 64 environment variable cccompiler cc v xarchzv9 O l lt install_dir gt modeltech include c app cpp Id G Bsymbolic app o o app so 32 bit HP700 Platform A shared library is created by creating object files that contain position independent code use the z or fPIC compiler argument and by linking as a shared library use the b linker argument If your PLI VPI application uses anything from a system library you ll need to specify that library wh
238. c RE OR ETE RR eee 84 Figure 3 4 Create Project File Dialog 0 0 0 cece cere cece eee nn 85 Figure 3 5 Add file to Project Dialog 4 54 agencvee nod ea eG cee eee ke PADRE eee ke 85 Figure 3 6 Right click Compile Menu in Project Tab of Workspace 86 Figure 3 7 Click Plus Sign to Show Design Hierarchy 0 0 0 0 eee eee 86 Figure 3 8 Start Simulation Dialog aiios oes o ERE e tee RE PRS4 ERRARE ERES 87 Figure 3 9 Structure Tab of the Workspace 0 0 0 0 eee eee eee eee 87 15 ModelSim User s Manual v6 2g February 2007 List of Figures Figure 3 10 Project Displayed in Workspace lseeleeeee eee 88 Figure 3 11 Setting Compile Order 2 06265 c42 e004 ee re 9 Rr Eee eee See dese 89 Figure 3 12 Grouping Files ici ossccesadateiadaceee beset RENERTA RESET EG E ER 90 Figure 3 13 Simulation Configuration Dialog llle 91 Figure 3 14 Simulation Configuration in the Project Tab 00 0 0000005 92 Figure 3 15 Add Polder Dialog i24 oetese1edht Re hk RE UPS TAPER E Aa Ra 93 Figure 3 16 Specifying a Project Folder 0 0 eee eee eee ee 93 Figure 3 17 Project Compiler Settings Dialog llle 94 Figure 3 18 Specifying File Properties 5222s aeos esee hr eh hy eR Ea 95 Figure 3 19 Project Settings Dialog 96 Figure 4 1 Creating a New Library 24s ba y Reese eee eee SEES P ERRES 101 Figure 4 2 Design Unit Information in the Workspace
239. c_fetch_paramval_str is declared in acc_user h It functions in a manner similar to acc_fetch_paramval except that it returns a char acc_fetch_paramval_str can be used on all platforms 396 ModelSim User s Manual v6 2g February 2007 IEEE Std 1364 TF Routines ModelSim Verilog supports the following TF task and function routines Routines io mcdprintf 1o printf mc scan plusargs tf add long tf asynchoff tf iasynchoff tf asynchon tf iasynchon tf clearalldelays tf iclearalldelays tf compare long tf copypvc flag tf icopypvc flag tf divide long tf dofinish tf dostop tf error tf evaluatep tf ievaluatep tf exprinfo tf iexprinfo tf getcstringp tf igetcstringp tf getinstance tf getlongp tf igetlongp tf getlongtime tf igetlongtime tf getnextlongtime tf getp tf igetp tf getpchange tf igetpchange tf getrealp tf igetrealp Verilog PLI VPI DPI IEEE Std 1364 TF Routines Table D 4 Supported TF Routines tf getrealtime tf igetrealtime tf gettime tf igettime tf gettimeprecision tf igettimeprecision tf gettimeunit tf igettimeunit tf getworkarea tf igetworkarea tf long to real tf longtime tostr tf message tf mipname tf imipname tf movepvc flag tf imovepvc flag tf multiply long tf nodeinfo tf inodeinfo tf nump tf inump tf propagatep tf ipropagatep tf putlongp tf iputlongp tf putp tf iputp tf putrealp tf iputrealp tf read restart tf real to long
240. ce at the end of the current time period Default is 1 ms A negative value means that the force will not be cancelled ModelSim User s Manual v6 2g February 2007 Signal Spy signal force e verbose Optional integer Possible values are 0 or 1 Specifies whether you want a message reported in the Transcript stating that the value is being forced on the dest_object at the specified time Default is 0 no message Related procedures init_signal_driver init_signal_spy signal_release Limitations You cannot force bits or slices of a register you can force only the entire register signal_force Example This example forces reset to a 1 from time 0 ns to 40 ns At 40 ns reset is forced to a 0 2 ms after the second signal force call was executed If you want to skip parameters so that you can specify subsequent parameters you need to use the keyword open as a placeholder for the skipped parameter s The first signal force procedure illustrates this where an open for the cancel period parameter means that the default value of 1 ms is used library IEEE modelsim lib use IEEE std logic 1164 a11 use modelsim lib util all entity testbench is end architecture only of testbench is begin force process process begin signal force testbench uut blkl reset 1 0 ns freeze open 1 signal force testbench uut blkl reset 0 40 ns freeze 2 ms 1 wait end process force process
241. ch libraries specified with L arguments in the order they appear on the command line e Search the work library e Search the library explicitly named in the special escaped identifier instance name Handling Sub Modules with Common Names Sometimes in one design you need to reference two different modules that have the same name This situation can occur if you have hierarchical modules organized into separate libraries and 144 ModelSim User s Manual v6 2g February 2007 Verilog and SystemVerilog Simulation Compiling Verilog Files you have commonly named sub modules in the libraries that have different definitions This may happen if you are using vendor supplied libraries For example say you have the following design configuration Example 6 3 Sub Modules with Common Names top modA modB gt a libl lib2 modA modB cellX cellX The normal library search rules will fail in this situation For example if you load the design as follows vsim L lib1 L lib2 top both instantiations of cellX resolve to the lib version of cellX On the other hand if you specify L lib2 L lib1 both instantiations of cellX resolve to the lib2 version of cellX To handle this situation ModelSim implements a special interpretation of the expression L work When you specify L work first in the search library arguments you are directing vsim to search for the inst
242. ch win32 Imtipli ModelSim requires the use of MinGW gcc compiler rather than the Cygwin gcc compiler DPI Imports on Windows Platforms When linking the shared objects be sure to specify one export option for each DPI imported task or function in your linking command line You can use Verilog s isymfile option to obtain a complete list of all imported tasks and functions expected by ModelSim DPI Special Flow for Exported Tasks and Functions Since the Windows platform lacks the necessary runtime linking complexity you must perform an additional manual step in order to compile the HDL source files into the shared object file You need to invoke a special run of vsim The command is as follows vsim top du list dpiexportobj lt objname gt other args ModelSim User s Manual v6 2g 381 February 2007 Verilog PLI VPI DPI Compiling and Linking C Applications for PLI VPI DPI The dpiexportobj generates the object file lt objname gt obj that contains glue code for exported tasks and functions You must add that object file to the link line listed after the other object files For example if the object name was dpi the link line for MinGW would be g shared Bsymbolic o app dll app obj lt objname gt obj L lt install_dir gt modeltech win32 Imtipli 32 bit Linux Platform e GNU C Version 2 95 3 or Later g c fPIC l lt install_dir gt modeltech include app cpp g shared Bsymbolic fPIC o app so app o
243. ched to skew Table 11 12 Matching SDF SKEW to Verilog SKEW posedge clk1 posedge clk2 5 skew posedge clk1 posedge clk2 0 270 ModelSim User s Manual v6 2g February 2007 Standard Delay Format SDF Timing Annotation sdf annotate e WIDTH is matched to width Table 11 13 Matching SDF WIDTH to Verilog SDF Verilog WIDTH posedge clk 5 width posedge clk 0 e PERIOD is matched to period Table 11 14 Matching SDF PERIOD to Verilog SDF Verilog PERIOD posedge clk 5 period posedge clk 0 e NOCHANGE is matched to nochange Table 11 15 Matching SDF NOCHANGE to Verilog SDF Verilog NOCHANGE negedge write addr 5 5 nochange negedge write addr 0 0 Optional Edge Specifications Timing check ports and path delay input ports can have optional edge specifications The annotator uses the following rules to match edges e A match occurs if the SDF port does not have an edge e A match occurs if the specify port does not have an edge e A match occurs if the SDF port edge is identical to the specify port edge e A match occurs if explicit edge transitions in the specify port edge overlap with the SDF port edge These rules allow SDF annotation to take place even if there is a difference between the number of edge specific constructs in the SDF file and the Verilog specify block For example the Verilog specify block may contain separate setup timing checks for a falling a
244. cified break event Main menu Simulate gt Run gt Run All use the run all command at the VSIM prompt Break stop the current simulation run 78 Find First Difference find the first difference in a waveform comparison Find Previous Annotated Difference find the previous annotated difference in a waveform comparison Find Previous Difference find the previous difference in a waveform comparison ModelSim User s Manual v6 2g February 2007 Simulator Windows Wave Window Table 2 10 Wave Window Toolbar Buttons and Menu Selections Menu equivalent Other options Find Next Difference find the next difference in a waveform comparison Find Next Annotated Difference find the next annotated difference in a waveform comparison Find Last Difference find the last difference in a waveform comparison ModelSim User s Manual v6 2g 79 February 2007 Simulator Windows Wave Window 80 ModelSim User s Manual v6 2g February 2007 Chapter 3 Projects Projects simplify the process of compiling and simulating a design and are a great tool for getting started with ModelSim What are Projects Projects are collection entities for designs under specification or test At a minimum projects have a root directory a work library and metadata which are stored in a mpf file located in a project s root directory The metadata include compiler switch settings compile order and file mappi
245. cified on the applicable invoice within 30 days from the date of such invoice Any past due invoices will be subject to the imposition of interest charges in the amount of one and one half percent per month or the applicable legal rate currently in effect whichever is lower Some Software may contain code distributed under a third party license agreement that may provide additional rights to you Please see the applicable Software documentation for details This Agreement may only be modified in writing by authorized representatives of the parties Waiver of terms or excuse of breach must be in writing and shall not constitute subsequent consent waiver or excuse Rev 060210 Part No 227900
246. cl Command Syntax ModelSim command names that conflict with Tcl commands have been renamed or have been replaced by Tcl commands See the list below Table 13 1 Previous ModelSim Command changed to or replaced by command continue run with the continue option format list wave write format with either list or wave specified if replaced by the Tcl if command see If Command Syntax for more information list add list nolist nowave delete with either list or wave specified set replaced by the Tcl set command Source vsource wave add wave Tcl Command Syntax The following eleven rules define the syntax and semantics of the Tcl language Additional details on If Command Syntax 294 1 A Tcl script is a string containing one or more commands Semi colons and newlines are command separators unless quoted as described below Close brackets are command terminators during command substitution see below unless quoted A command is evaluated in two steps First the Tcl interpreter breaks the command into words and performs substitutions as described below These substitutions are performed in the same way for all commands The first word is used to locate a command procedure to carry out the command then all of the words of the command are passed to the command procedure The command procedure is free to interpret each of its words in any way it likes such as an integer variable name list
247. ction call callback function p tffn misctf miscellaneous reason callback function char tfname name of system task or function The following fields are ignored by ModelSim Verilog int forwref char tfveritool char tferrmessage int hash struct t tfcell left p struct t tfcell right p char namecell p int warning printed s tfcell p tfcell The various callback functions checktf sizetf calltf and misctf are described in detail in the IEEE Std 1364 The simulator calls these functions for various reasons All callback functions are optional but most applications contain at least the calltf function which is called when the system task or function is executed in the Verilog code The first argument to the callback functions is the value supplied in the data field many PLI applications don t use this field The type field defines the entry as either a system task USERTASK or a system function that returns either a register USERFUNCTION or a real USERREALFUNCTION The tfname field is the system task or function name it must begin with The remaining fields are not used by ModelSim Verilog On loading of a PLI application the simulator first looks for an init usertfs function and then a veriusertfs array If init usertfs is found the simulator calls that function so that it can call mti RegisterUserTF for each system task or function defined The mti RegisterUserTF function 1s
248. ctionality for negative timing constraints and an alternate method of conditioning as in Verilog XL recovery reference event data event removal limit recovery limit notifier tstamp cond tcheck cond delayed reference delayed data The recovery system task normally takes a recovery limit as the third argument and an optional notifier as the fourth argument By specifying a limit for both the third and fourth arguments the recovery timing check is transformed into a combination removal and recovery timing check similar to the recrem timing check The only difference is that the removal_limit and recovery_limit are swapped setuphold clk event data event setup limit hold limit notifier tstamp_cond tcheck cond delayed clk delayed data The tstamp cond argument conditions the data event for the setup check and the clk event for the hold check This alternate method of conditioning precludes specifying conditions in the clk event and data event arguments ModelSim User s Manual v6 2g 169 February 2007 Verilog and SystemVerilog Simulation System Tasks and Functions The tcheck cond argument conditions the data event for the hold check and the clk event for the setup check This alternate method of conditioning precludes specifying conditions in the clk event and data event arguments The delayed clk argument is a net that is continuously assigned the value of the net specified in the clk event The de
249. d e Size of CHARACTER type In VHDL 87 type CHARACTER has 128 values in VHDL 93 it has 256 values Code which depends on this size will behave incorrectly This situation occurs most commonly in test suites that check VHDL functionality It s unlikely to occur in practical designs A typical instance is the replacement of warning message range nul downto del is null by range nul downto y is null range is nul downto y umlaut e bit string literals In VHDL 87 bit string literals are of type bit vector In VHDL 93 they can also be of type STRING or STD_LOGIC_VECTOR This implies that some expressions that are unambiguous in VHDL 87 now become ambiguous is VHDL 93 A typical error message is Error bit string literal vhd 5 Subprogram is ambiguous Suitable definitions exist in packages std logic 1164 and standard e Sub element association In VHDL 87 when using individual sub element association in an association list associating individual sub elements with NULL is discouraged In VHDL 93 such association is forbidden A typical message is Formal name must not be associated with OPEN when subelements are associated individually ModelSim User s Manual v6 2g 113 February 2007 VHDL Simulation Simulating VHDL Designs Simulating VHDL Designs A VHDL design is ready for simulation after it has been compiled with vcom The simulator may then be invoked with the name of the co
250. d EXTESE REA 207 Table 8 5 Triggering Options usd EQ RP RENE ER OCDHES CER ER dA hen cae 218 Table 9 1 Dataflow Window Links to Other Windows and Panes 226 Table 9 2 Icon and Menu Selections for Exploring Design Connectivity 227 Table 10 1 Signal Spy Mapping VHDL Procedures to Verilog System Tasks 239 Table 11 1 Matching SDF to VHDL Generics 0 0 cece eee 265 Table 11 2 Matching SDF IOPATH to Verilog 0 0 eee eee eee 268 Table 11 3 Matching SDF INTERCONNECT and PORT to Verilog 268 Table 11 4 Matching SDF PATHPULSE and GLOBALPATHPULSE to Verilog 269 ModelSim User s Manual v6 2g 18 February 2007 List of Tables Table 11 5 Matching SDF DEVICE to Verilog eee 269 Table 11 6 Matching SDF SETUP to Verilog 0 0 0 0 0 cee eee eee eee 269 Table 11 7 Matching SDF HOLD to Verilog 0 0 2 cece eee eee 269 Table 11 8 Matching SDF SETUPHOLD to Verilog 0 0 0 0000 5 270 Table 11 9 Matching SDF RECOVERY to Verilog 0 0 0 e ee eee eee 270 Table 11 10 Matching SDF REMOVAL to Verilog 0 0 0 0 e eee eee eee 270 Table 11 11 Matching SDF RECREM to Verilog 0 0 00 cee eee eee ee 270 Table 11 12 Matching SDF SKEW to Verilog 0 0 0 cece ee eee 270 Table 11 13 Matching SDF WIDTH to Verilog seeeee BA 271 Table 11 14 Matching SDF PERIOD to Verilog
251. d dropped from the Objects pane to the Wave and List windows Virtual signals are automatically attached to the design region in the hierarchy that corresponds to the nearest common ancestor of all the elements of the virtual signal The virtual signal command has an install lt region gt option to specify where the virtual signal should be installed This can be used to install the virtual signal in a user defined region in order to reconstruct the original RTL hierarchy when simulating and driving a post synthesis gate level implementation A virtual signal can be used to reconstruct RTL level design buses that were broken down during synthesis The virtual hide command can be used to hide the display of the broken down bits if you don t want them cluttering up the Objects pane If the virtual signal has elements from more than one WLF file it will be automatically installed in the virtual region virtuals Signals 184 ModelSim User s Manual v6 2g February 2007 WLF Files Datasets and Virtuals Virtual Objects Virtual signals are not hierarchical if two virtual signals are concatenated to become a third virtual signal the resulting virtual signal will be a concatenation of all the scalar elements of the first two virtual signals The definitions of virtuals can be saved to a macro file using the virtual save command By default when quitting ModelSim will append any newly created virtuals that have not been saved to the vi
252. d library into the simulator with either the command line option sv lib lib or sv liblist bootstrap file For example vlog dut v gcc shared Bsymbolic o imports so imports c vsim sv lib imports top do do file The sv lib option specifies the shared library name without an extension A file extension is added by the tool as appropriate to your platform For a list of file extensions accepted by platform see DPI File Loading ModelSim User s Manual v6 2g 369 February 2007 Verilog PLI VPI DPI DPI Use Flow You can also use the command line options sv root and sv liblist to control the process for loading imported functions and tasks These options are defined in the IEEE Std P1800 2005 LRM DPI Use Flow Correct use of ModelSim DPI depends on the flow presented in this section Figure D 1 DPI Use Flow Diagram Step 1 Create header vlog dpiheader dpiheader h dpiheader h Step 2 Include header include dpiheader h Step 1 5 Required for Windows only vsim dpiexportobj lt exportobj gt gcc lt exportobj gt C compiler mtipli lib 0 compiled user code Id link loader linker Step 3 Compile and load link C code lt test gt so shared object Step 4 Simulate vsim sv lib lt test gt 1 Run vlog to generate a dpiheader h file This file defines the interface between C and ModelSim for expor
253. d numeric_bit packages The corresponding modelsim ini variable is NumericStdNoWarnings e Default Run Sets the default run length for the current simulation The corresponding modelsim ini variable is RunLength 342 ModelSim User s Manual v6 2g February 2007 Simulator Variables Simulator Control Variables e Iteration Limit Sets a limit on the number of deltas within the same simulation time unit to prevent infinite looping The corresponding modelsim ini variable is IterationLimit e Default Force Type Selects the default force type for the current simulation The corresponding modelsim ini variable is DefaultForceKind The Assertions tab includes these options Figure A 2 Runtime Options Dialog Box Assertions Tab zx Defaults I Assertions WLF Files l l Immediate Assertion Break Severity No Message Display For C Fatal tiio l Verilog e Failure r Failure m Fatal C Eno Emo Eror C Waning Warming v Warning UK Cancel Apply e No Message Display For VHDL Selects the VHDL assertion severity for which messages will not be displayed even if break on assertion is set for that severity Multiple selections are possible The corresponding modelsim ini variables are IgnoreFailure IgnoreError IgnoreWarning and IgnoreNote The WLF Files tab includes these options ModelSim User s Manual v6 2g 343 February 2007 Simulator Variables Simulator Control Variables Figure A 3
254. dHelp preference variable to 0 See Simulator GUI Preferences for details on setting preference variables Message Viewer The Message Viewer tab found in the Transcript pane allows you to easily access organize and analyze any Note Warning Error or other elaboration and runtime messages written to the transcript during the simulation run By default the tool writes transcripted messages to both the transcript and the WLF file By writing to the WLF file the Message Viewer tab is able to organize the messages for your analysis Controlling the Message Viewer Data Command Line The msgmode argument to vsim controls where the simulator outputs the messages vsim msgmode both tran wlf where o both outputs messages to both the transcript and the WLF file Default behavior o tran outputs messages only to the transcript therefore they are not available in the Message Viewer o wlf outputs messages only to the WLF file Message Viewer therefore they are not available in the transcript e modelsim ini File The msgmode variable in the modelsim ini file accepts the same values described above for the msgmode argument Message Viewer Interface and Tasks The Message Viewer tab does not display by default You can bring it up after a simulation run with the View gt Message Viewer menu item The message viewer is also automatically displayed when you perform the dataset open command Figure 2 3 and Tabl
255. datetedess tedeee youn Gases KERAS EUR se ES 140 Invoking the Verilog Compiler sso avs xxu exp RP ERES ERG X XP XX RES 140 Incremental Compilation 1454s ah he nk E ERE CR RU Re RADAR RE aes 141 Library USap P 144 SystemVerilog Multi File Compilation Issues llle eee eee 145 Verilog XL Compatible Compiler Arguments 146 Verilog XL uselib Compiler Directive llle 147 Verilog Configurdiblis ioc paduri ca dernteisdensse cider ends Ra qu ER PA qM 149 Verilog Generate Statements oir oar ceat oe a ea Ke RH CX ROC Ie EPI RU c Ia E SN 150 Simulating Verilog Destgnssa sud bee REI E REERR PARERE EERULDRES RC ARP CEP 151 Simulator Resolution Limit Verilog 0 cece eee een 151 Event Ordering in Verilog Designs 0 0 0 0 cece eect eee ee 154 Debugging Event Order Issues Lunes 4404494 0440 REEL CR es eee Ss 137 Negative Timing Check Limits 0 0 0 cece eee eee nee 159 Verilog XL Compatible Simulator Arguments 0 0 c eee eee eee eee 160 Using Escaped Identifiers esses ak eebemaeck e Rx ea RC aa RA Pa RR aces 161 Cell IMATE ioa o4 es her PCI Rec Qa Rer Deu Re cases ate re Dqeaheceag at 162 SDF Timing AUOD essendo eke ue ERE EU REURATO P RR BED eR SUE eR 162 Delay M d s 3 0 shane een Tac RE eee eee dA AQ PEE eee eee eee 162 System Tasks and Functions ivesexdaxers RR ESARLESa C VERE E EaARESREXRa NEM RU 163 6 ModelSim User s Manual v6 2g February 2007 Table of Contents IEEE Std 1
256. de View Pan and middle mouse button to zoom mode Cut cut the selected object s Edit Cut d Copy copy the selected object s Edit Copy Paste paste the previously cut or copied Edit Paste object s E Undo undo the last action Edit Undo 5 cu Find search for an instance or signal Edit gt Find e Redo redo the last undone action Edit Redo 50 ModelSim User s Manual v6 2g February 2007 Simulator Windows Dataflow Window Table 2 8 Dataflow Window Toolbar Button Menu equivalent Trace input net to event move the next event Trace Trace next event cursor to the next input event driving the selected output Trace Set jump to the source of the selected Trace Trace event set input event Trace Reset return the next event cursor to the Trace Trace event reset selected output Trace net to driver of X step back to the last Trace gt TraceX driver of an unknown value Expand net to all drivers display driver s of Navigate gt Expand net to drivers the selected signal net or register Expand net to all drivers and readers display Navigate Expand net driver s and reader s of the selected signal net or register Expand net to all readers display reader s of Navigate gt Expand net to readers the selected signal net or register Erase highlight clear the green highlighting Edit Erase hig
257. dialog box e select the Builder button 200 ModelSim User s Manual v6 2g February 2007 Waveform Analysis Searching in the Wave and List Windows Figure 8 10 Expression Builder Dialog Expression Builder B X r Expression Expression Builder Insert Selected Signal EJ E cca a a Id peo suf x 2 ef saf saj ep Jf The Expression Builder dialog box provides an array of buttons that help you build a GUI expression For instance rather than typing in a signal name you can select the signal in the associated Wave or List window and press Insert Selected Signal All Expression Builder buttons correspond to the Expression Syntax Saving an Expression to a Tcl Variable Clicking the Save button will save the expression to a Tcl variable Once saved this variable can be used in place of the expression For example say you save an expression to the variable foo Here are some operations you could do with the saved variable e Read the value of foo with the set command set foo e Put foo in the Expression entry box for the Search for Expression selection e Issue a searchlog command using foo searchlog expr foo 0 Searching for when a Signal Reaches a Particular Value Select the signal in the Wave window and click Insert Selected Signal and Then click the value buttons or type a value ModelSim User s Manual v6 2g 201 February 2007 Waveform Analysis Formatting the Wave
258. dow menu bar If the Wave window stands alone undocked from the Main window select Add gt Divider from the Wave window menu bar 3 Specify the divider name in the Wave Divider Properties dialog The default name is New Divider Unnamed dividers are permitted Simply delete New Divider in the Divider Name field to create an unnamed divider 4 Specify the divider height default height is 17 pixels and then click OK You can also insert dividers with the divider argument to the add wave command 206 ModelSim User s Manual v6 2g February 2007 Waveform Analysis Formatting the Wave Window Working with Dividers The table below summarizes several actions you can take with dividers Table 8 4 Actions for Dividers Move a divider Click and drag the divider to the desired location Change a divider s Right click the divider and select Divider Properties name or size Delete a divider Right click the divider and select Delete Splitting Wave Window Panes The pathnames values and waveforms panes of the Wave window display can be split to accommodate signals from one or more datasets For more information on viewing multiple simulations see WLF Files Datasets and Virtuals To split the window select Add Window Pane In the illustration below the top split shows the current active simulation with the prefix sim and the bottom split shows a second dataset with the prefix gold ModelSim User s Manua
259. e The path may include environment variables e Put the path in a UNIX shell environment variable LD LIBRARY PATH 32 library path without filename for Solaris Linux 32 bit Or LD LIBRARY PATH 64 library path without filename for Solaris 64 bit Or SHLIB PATH library path without filename for HP UX Correct Linking of Shared Libraries with Bsymbolic In the examples shown throughout this appendix the Bsymbolic linker option is used with the compilation gcc or g or link Id commands to correctly resolve symbols This option instructs the linker to search for the symbol within the local shared library and bind to that symbol if it exists If the symbol is not found within the library the linker searches for the symbol within the vsimk executable and binds to that symbol if it exists When using the Bsymbolic option the linker may warn about symbol references that are not resolved within the local shared library It is safe to ignore these warnings provided the symbols are present in other shared libraries or the vsimk executable An example of such a warning would be a reference to a common API call such as vpi_printf Windows Platforms e Microsoft Visual C 4 1 or Later 374 ModelSim User s Manual v6 2g February 2007 Verilog PLI VPI DPI Compiling and Linking C Applications for PLI VPI DPI cl c l lt install_dir gt modeltech include app c link dll export init function app obj lt install
260. e listed after the other object files For example a link line would be Id o app dll app o lt objname gt o bE lt isymfile gt bl install dir modeltech rs6000 mti exports bM SRE bnoentry lc Compiling and Linking C Applications for PLI VPI DPI ModelSim does not have direct support for any language other than standard C however C code can be loaded and executed under certain conditions Since ModelSim s PLI VPI DPI functions have a standard C prototype you must prevent the C compiler from mangling the PLI VPI DPI function names This can be accomplished by using the following type of extern extern C lt PLI VPI DPI application function prototypes gt The header files veriuser h acc_user h and vpi_user h svdpi h and dpiheader h already include this type of extern You must also put the PLI VPI DPI shared library entry point veriusertfs init usertfs or vlog startup routines inside of this type of extern The following platform specific instructions show you how to compile and link your PLI VPI DPI C applications so that they can be loaded by ModelSim Although compilation and simulation switches are platform specific loading shared libraries is the same for all platforms For information on loading libraries see DPI File Loading For PLI VPI only If app so is not in your current directory you must tell Solaris where to search for the shared object You can do this one of two ways 380 Mod
261. e pipe socket Version incompatibility License manager not found unreadable unexecutable vlm mgvlm Lost license License read write failure Modeltech daemon license checkout failure 44 Modeltech daemon license checkout failure 45 Assertion failure SEVERITY _QUIT Unexpected error in tool GUI Tcl initialization failure GUI Tk initialization failure GUI IncrTk initialization failure X11 display error Interrupt SIGINT Illegal instruction SIGILL Trace trap SIGTRAP Abort SIGABRT Floating point exception SIGFPE Bus error SIGBUS Segmentation violation SIGSEGV Write on a pipe with no reader SIGPIPE Alarm clock SIGALRM 358 Software termination signal from kill SIGTERM ModelSim User s Manual v6 2g February 2007 Error and Warning Messages Miscellaneous Messages Table C 2 Exit Codes Exit code Description 216 User defined signal 1 SIGUSR1 217 User defined signal 2 SIGUSR2 Child status change SIGCHLD Exceeded CPU limit SIGXCPU Exceeded file size limit SIGXFSZ Miscellaneous Messages This section describes miscellaneous messages which may be associated with ModelSim Compilation of DPI Export TFs Error Fatal vsim 3740 Can t locate a C compiler for compilation of DPI export tasks functions e Description ModelSim was unable to locate a C compiler to compile the DPI e
262. e 2 4 provide an overview of the Message Viewer and several tasks you can perform 40 ModelSim User s Manual v6 2g February 2007 Simulator Windows Main Window Figure 2 3 Message Viewer Tab Column Headings Right click to view heading options Left click to toggle sort order eee A vm 3473 Component instance u7 vlogbuf2 is not bound 3473 top 3 SOF 2 JA Warning 2 R Waning vein DF 3240 test ef G Enliy Vhvdichic does 3540 Ons test sdi 18 Waming ivsim SDF 3240 test sdi 18r Enthy dich does 3040 Ons test sdi 18 ee generic named Ysetup_d_ck_noedge_negedge lb g E aT B A cells v 15 setup d 20 ns posedge ck 25 ns 8 ns EX celk v 15 setup d 40 ns posedge ck 45 ns 8 ns FR cells 16 holdi posedge clk 25 ns 30 ns 9 ns XH Warring 3 Table 2 4 Message Viewer Tasks Action Display a detailed description of the right click the message text then message select View Verbose Message Open the source file and add a bookmark to double click the object name s the location of the object s Change the focus of the Workspace and double click the hierarchical Objects panes reference Open the source file and set a marker at the double click the file name line number Multiple Document Interface MDI Frame The MDI frame is an area in the Main window where source editor memory content wave and list windows d
263. e Constructs always posedge clock begin Storer integer i dena if reset 1 b0 begin uci buffer lt 0 nstantiations 1 Compiler Directives end else if oeenable 1 bO begin Blocks i ramadrs counter size 2 count System Tasks and Fur buffer i lt txda Clock end end endmodule Opening Source Files You can open source files using the File gt Open command Alternatively you can open source files by double clicking objects in other windows For example if you double click an item in 62 ModelSim User s Manual v6 2g February 2007 Simulator Windows Source Window the Objects window or in the structure tab of the Workspace the underlying source file for the object will open and the cursor will scroll to the line where the object is defined By default files you open from within the design e g by double clicking an object in the Objects pane open in Read Only mode To make the file editable right click in the Source window and select Read Only To change this default behavior set the PrefSource ReadOnly variable to 0 See Simulator GUI Preferences for details on setting preference variables Displaying Multiple Source Files By default each file you open or create is marked by a window tab as shown in the graphic below Figure 2 20 Displaying Multiple Source Files C modeltech examples systemc sc vhdl vlog store v 14 module store clock reset oeenable ramadrs txda buffer
264. e Group There are three ways to add items to an existing wave group Using the drag and drop capability to move items outside of the group or from other windows within ModelSim into the group The insertion indicator will show the position the item will be dropped into the group If the cursor is moved over the lower portion of the group item name a box will be drawn around the group name indicating the item will be dropped into the last position in the group 2 The cut copy paste functions may be used to paste items into a group 3 Use the add wave group command The following example adds two more signals to an existing group called mygroup add wave group mygroup sig4 sig5 Removing Items from an Existing Wave Group You can use any of the following methods to remove an item from a wave group Use the drag and drop capability to move an item outside of the group 2 Use menu or icon selections to cut or delete an item or items from the group 3 Use the delete wave command to specify a signal to be removed from the group Note The delete wave command removes all occurrences of a specified name from the wave window not just an occurrence within a group Miscellaneous Wave Group Features Dragging a wave group from the Wave window to the List window will result in all of the items within the group being added to the List window 210 ModelSim User s Manual v6 2g February 2007 Waveform Analysis Formatting the Lis
265. e number of concurrently open files can be controlled by the ConcurrentFileLimit variable These variables help you manage a large number of files during simulation See Simulator Variables for more details Using STD INPUT and STD OUTPUT Within the Tool The standard VHDL 87 TextIO package contains the following file declarations file input TEXT is in STD INPUT file output TEXT is out STD OUTPUT ModelSim User s Manual v6 29 119 February 2007 VHDL Simulation TextlO Implementation Issues Updated versions of the TextIO package contain these file declarations file input TEXT open read mode is STD INPUT file output TEXT open write mode is STD OUTPUT STD INPUT is a file logical name that refers to characters that are entered interactively from the keyboard and STD OUTPUT refers to text that is displayed on the screen In ModelSim reading from the STD INPUT file allows you to enter text into the current buffer from a prompt in the Transcript pane The lines written to the STD OUTPUT file appear in the Transcript TextlO Implementation Issues Writing Strings and Aggregates A common error in VHDL source code occurs when a call to a WRITE procedure does not specify whether the argument is of type STRING or BIT VECTOR For example the VHDL procedure WRITE L hello will cause the following error ERROR Subprogram WRITE is ambiguous In the TextIO package the WRITE procedure is overloaded for
266. e of a timescale directive timescale 1 ns 100 ps ModelSim User s Manual v6 2g 151 February 2007 Verilog and SystemVerilog Simulation Simulating Verilog Designs The first number is the time units and the second number is the time precision The directive above causes time values to be read as ns and to be rounded to the nearest 100 ps Time units and precision can also be specified with SystemVerilog keywords as follows timeunit 1 ns timeprecision 100 ps Modules Without Timescale Directives You may encounter unexpected behavior if your design contains some modules with timescale directives and others without The time units for modules without a timescale directive default to the simulator resolution For example say you have the two modules shown in the table below Table 6 1 Sample Modules With and Without Timescale Directive Module 1 Module 2 timescale 1 ns 10 ps module mod2 set module mod1 set output set reg set output set parameter d 1 55 reg set parameter d 1 55 initial begin initial set I bz begin ftd set 1 b0 set I bz ftd set I bl ftd set 1 b0 end ftd set I bl end endmodule endmodule If you invoke vsim as vsim mod2 mod1 then Module 1 sets the simulator resolution to 10 ps Module 2 has no timescale directive so the time units default to the simulator resolution in this case 10 ps If you watched mod1 set and mod2 set in the Wave window you d se
267. e pane outside of the parent window and when you let go of the mouse button the pane becomes a free floating window Docking and Undocking Panes You can undock a pane by clicking the undock button in the heading of a pane Figure F 4 GUI Undock Button g To redock a floating pane click on the pane handle at the top of the window and drag it back into the parent window or click the dock icon Figure F 5 GUI Dock Button i You can expand panes to fill the entire Main window by clicking the zoom icon in the heading of the pane Zooming Panes Figure F 6 GUI Zoom Button To restore the pane to its original size and position click the unzoom button in the heading of the pane 414 ModelSim User s Manual v6 2g February 2007 Setting GUI Preferences Simulator GUI Preferences Figure F 7 GUI Zoom Button Columnar Information Display Many panes e g Objects Workspace etc display information in a columnar format You can perform a number of operations on columnar formats e Click and drag on a column heading to rearrange columns e Click and drag on a border between column names to increase decrease column size e Sort columns by clicking once on the column heading to sort in ascending order clicking twice to sort in descending order and clicking three times to sort in default order e Hide or show columns by either right clicking a column heading and selecting an object from the context menu or
268. e reduced by 1 2 orders of magnitude e startup and run times are reduced e associated memory allocation errors are eliminated In the VHDL example below we illustrate three alternative architectures for entity memory e Architecture bad style 57 uses a vhdl signal to store the ram data e Architecture style 87 uses variables in the memory process e Architecture style 93 uses variables in the architecture For large memories architecture bad style 57 runs many times longer than the other two and uses much more memory This style should be avoided Architectures style 87 and style 95 work with equal efficiently However VHDL 1993 offers additional flexibility because the ram storage can be shared between multiple processes For example a second process is shown that initializes the memory you could add other processes to create a multi ported memory To implement this model you will need functions that convert vectors to integers To use it you will probably need to convert integers to vectors Example functions are provided below in package conversions For completeness sake we also show an example using VHDL 2002 protected types though in this example protected types offer no advantage over shared variables 128 ModelSim User s Manual v6 2g February 2007 VHDL Simulation Modeling Memory VHDL87 and VHDL93 Example library ieee use ieee std logic 1164 all use work conversions all entity memory is generic add b
269. e that in Module 1 it transitions every 1 55 ns as expected because of the 1 ns time unit in the timescale directive However in Module 2 set transitions every 20 ps That s because the delay of 1 55 in Module 2 is read as 15 5 ps and is rounded up to 20 ps In such cases ModelSim will issue the following warning message during elaboration 152 ModelSim User s Manual v6 2g February 2007 Verilog and SystemVerilog Simulation Simulating Verilog Designs Warning vsim 3010 TSCALE Module modl1 has a timescale directive in effect but previous modules do not If you invoke vsim as vsim mod1 mod2 the simulation results would be the same but ModelSim would produce a different warning message Warning vsim 3009 TSCALE Module mod2 does not have a timescale directive in effect but previous modules do These warnings should ALWAYS be investigated If the design contains no timescale directives then the resolution limit and time units default to the value specified by the Resolution variable in the modelsim ini file The variable is set to 1 ps by default timescale Option The timescale option can be used with the vlog and vopt to specifies the default timescale for modules not having an explicit timescale directive in effect during compilation The format of the timescale argument is the same as that of the timescale directive timescale time units time precision The format fo
270. e that on a Windows platform the file extension would be dll e As alist in the Veriuser entry in the modelsim ini file Veriuser pliapp1 so pliapp2 so pliappn so e Asa list in the PLIOBJS environment variable setenv PLIOBJS pliapp1 so pliapp2 so pliappn so e Asa pli argument to the simulator multiple arguments are allowed pli pliapp1 so pli pliapp2 so pli pliappn so The various methods of specifying PLI applications can be used simultaneously The libraries are loaded in the order listed above Environment variable references can be used in the paths to the libraries in all cases Registering VPI Applications Each VPI application must register its system tasks and functions and its callbacks with the simulator To accomplish this one or more user created registration routines must be called at simulation startup Each registration routine should make one or more calls to vpi register systf to register user defined system tasks and functions and vpi register cb to register callbacks The registration routines must be placed in a table named ModelSim User s Manual v6 2g 367 February 2007 Verilog PLI VPI DPI Registering VPI Applications vlog startup routines so that the simulator can find them The table must be terminated with a 0 entry Example D 1 VPI Application Registration PLI INT32 MyFuncCalltf PLI BYTE8 user data PLI INT32 MyFuncCompiletf PLI BYTE8 user data PLI INT32 MyFuncSizetf PLI BYTE8
271. e your design and recompile A resource library is typically static and serves as a parts source for your design You can create ModelSim User s Manual v6 2g 99 February 2007 Design Libraries Working with Design Libraries your own resource libraries or they may be supplied by another design team or a third party e g a silicon vendor Only one library can be the working library Any number of libraries can be resource libraries during a compilation You specify which resource libraries will be used when the design is compiled and there are rules to specify in which order they are searched refer to Specifying the Resource Libraries A common example of using both a working library and a resource library is one in which your gate level design and testbench are compiled into the working library and the design references gate level models in a separate resource library The Library Named work The library named work has special attributes within ModelSim it is predefined in the compiler and need not be declared explicitly i e library work It is also the library name used by the compiler as the default destination of compiled design units 1 e it does not need to be mapped In other words the work library is the default working library Archives By default design libraries are stored in a directory structure with a sub directory for each design unit in the library Alternatively you can configure a design library
272. ebruary 2007 Introduction What is an Object Chapter 10 Signal Spy This chapter describes Signal Spy a set of VHDL procedures and Verilog system tasks that let you monitor drive force or release a design object from anywhere in the hierarchy of a VHDL or mixed design Chapter 11 Standard Delay Format SDF Timing Annotation This chapter discusses ModelSim s implementation of SDF Standard Delay Format timing annotation Included are sections on VITAL SDF and Verilog SDF plus troubleshooting Chapter 12 Value Change Dump VCD Files This chapter explains Model Technology s Verilog VCD implementation for ModelSim The VCD usage is extended to include VHDL designs Chapter 13 Tcl and Macros DO Files This chapter provides an overview of Tcl tool command language as used with ModelSim Appendix A Simulator Variables This appendix describes environment system and preference variables used in ModelSim Appendix C Error and Warning Messages This appendix describes ModelSim error and warning messages Appendix D Verilog PLI VPI DPI This appendix describes the ModelSim implementation of the Verilog PLI and VPI Appendix E Command and Keyboard Shortcuts This appendix describes ModelSim keyboard and mouse shortcuts Appendix G System Initialization This appendix describes what happens during ModelSim startup What is an Object Because ModelSim works with so many languages Verilog
273. ebugging Event Order Issues Since many models have been developed on Verilog XL ModelSim tries to duplicate Verilog XL event ordering to ease the porting of those models to ModelSim However ModelSim does not match Verilog XL event ordering in all cases and if a model ported to ModelSim does not behave as expected then you should suspect that there are event order dependencies ModelSim helps you track down event order dependencies with the following compiler arguments compat hazards and keep_delta See the vlog command for descriptions of compat and hazards ModelSim User s Manual v6 2g 157 February 2007 Verilog and SystemVerilog Simulation Simulating Verilog Designs Hazard Detection The hazard argument to vsim detects event order hazards involving simultaneous reading and writing of the same register in concurrently executing processes vsim detects the following kinds of hazards e WRITE WRITE Two processes writing to the same variable at the same time e READ WRITE One process reading a variable at the same time it is being written to by another process ModelSim calls this a READ WRITE hazard if it executed the read first e WRITE READ Same as a READ WRITE hazard except that ModelSim executed the write first vsim issues an error message when it detects a hazard The message pinpoints the variable and the two processes involved You can have the simulator break on the statement where the hazard is
274. ecific Tcl Commands alias creates a new Tcl procedure that evaluates the specified commands used to create a user defined alias find locates incrTcl classes and objects Ishift takes a Tcl list as argument and shifts it in place one place to the left eliminating the Oth element Isublist returns a sublist of the specified Tcl list that matches the specified Tcl glob pattern 300 ModelSim User s Manual v6 2g February 2007 Tcl and Macros DO Files Simulator Tcl Time Commands Table 13 4 Simulator Specific Tcl Commands printenv echoes to the Transcript pane the current names and values of all environment variables Simulator Tcl Time Commands ModelSim Tcl time commands make simulator time based values available for use within other Tcl procedures Time values may optionally contain a units specifier where the intervening space is also optional If the space is present the value must be quoted e g 10ns 10 ns Time values without units are taken to be in the UserTimeScale Return values are always in the current Time Scale Units All time values are converted to a 64 bit integer value in the current Time Scale This means that values smaller than the current Time Scale will be truncated to 0 ModelSim User s Manual v6 2g 301 February 2007 Tcl and Macros DO Files Simulator Tcl Time Commands Conversions Table 13 5 Tcl Time Conversion Commands Command Description intl oTime intHi32 lt intLo32
275. ecify bE lt isymfile gt option on the link command line lt isymfile gt is the name of the file generated by the isymfile argument to the vlog command Once you have created the lt isymfile gt it contains a complete list of all imported tasks and functions expected by ModelSim DPI Special Flow for Exported Tasks and Functions Since the RS6000 platform lacks the necessary runtime linking capabilities you must perform an additional manual step in order to prepare shared objects containing calls to exported SystemVerilog tasks or functions shared object file You need to invoke a special run of vsim The command is as follows ModelSim User s Manual v6 2g 385 February 2007 Verilog PLI VPI DPI Specifying Application Files to Load vsim top du list dpiexportobj objname other args The dpiexportobj generates the object file lt objname gt o that contains glue code for exported tasks and functions You must add that object file to the link line listed after the other object files For example a link line would be Id o app so app o lt objname gt o bE lt isymfile gt bl install dir modeltech rs6000 mti exports bM SRE bnoentry lc Specifying Application Files to Load PLI and VPI file loading is identical DPI file loading uses switches to the vsim command PLI VPI file loading The PLI VPI applications are specified as follows e Asa listin the Veriuser entry in the modelsim ini file Veriuser z plia
276. ecture bad style 87 of memory is Signal ram ram type begin memory process cs variable address natural 0 begin if rising edge cs then address sulv to natural add in if mwrite 1 then ram address lt data in data out data in else data out lt ram address end if end if end process end bad style 87 library ieee use ieee std logic 1164 all package conversions is function sulv to natural x std ulogic vector return natural function natural to sulv n bits natural return std ulogic vector end conversions package body conversions is function sulv to natural x std ulogic vector return natural is variable n natural 0 variable failure boolean false begin assert x high x low 1 lt 31 report Range of sulv to natural argument exceeds natural range severity error for i in x range loop n ie n 2 case x i is 130 ModelSim User s Manual v6 2g February 2007 when 1 when O when others end case end loop assert not failure report H Vr sulv to natural cannot convert VHDL Simulation Modeling Memory gt n Nn 1 gt null gt failure indefinite std ulogic vector severity error if failure then return 0 else return n end if end sulv to natural function natural to sulv n J Vector is std ulogic bits natural return variable x std ulogic vector b
277. ed If you set this environment variable with an argument of 0 zero the tool will not release the licenses after being suspended You can change the default length of time number of seconds by setting this environment variable to an integer greater than 0 zero 316 ModelSim User s Manual v6 2g February 2007 Simulator Variables Environment Variables MTI USELIB DIR The MTI USELIB DIR environment variable specifies the directory into which object libraries are compiled when using the compile uselibs argument to the vlog command NOMMAP When set to 1 the NOMMAP environment variable disables memory mapping in the toolset You should only use this variable when running on Linux 7 1 because it will decrease the speed with which the tool reads files PLIOBJS The toolset uses the PLIOBJS environment variable to search for PLI object files for loading The argument consists of a space separated list of file or path names STDOUT The argument to the STDOUT environment variable specifies a filename to which the simulator saves the VSOUT temp file information Typically this information is deleted when the simulator exits The location for this file is set with the TMPDIR variable which allows you to find and delete the file in the event of a crash because an unnamed VSOUT file is not deleted after a crash TMP Windows environments The TMP environment variable specifies the path to a tempnam generated file VSOUT containing all s
278. ee also windows Locals window location maps referencing source files 353 locations maps specifying source files with 353 lock message 359 LockedMemory ini file variable 335 ModelSim User s Manual v6 2g February 2007 ABCDEFGHI locking cursors 193 log file overview 175 see also WLF files long simulations saving at intervals 182 M MacroNestingLevel simulator state variable 350 macros DO files 307 creating from a saved transcript 39 depth of nesting simulator state variable 350 error handling 311 parameters as a simulator state variable n 350 passing 308 total number passed 349 startup macros 347 Main window 36 see also windows Main window mapping libraries from the command line 103 hierarchically 346 symbols Dataflow window 235 mapping libraries library mapping 103 math_complex package 106 math_real package 106 MDI frame 41 MDI pane tab groups 42 memories displaying the contents of 56 navigation 58 saving formats 58 selecting memory instances 57 viewing contents 57 viewing multiple instances 57 memory modeling in VHDL 128 memory leak cancelling scheduled events 136 Memory pane 56 pane ModelSim User s Manual v6 2g February 2007 JKLMNOPQRSTUVWXYZ Memory pane see also Memory pane memory tab memories you can view 56 Memory window 56 see also windows Memory window message system 355 Message Viewer tab 40 Messages 40 messages 355 bad magic n
279. ees 31 Installation Directory Pathniames 4 02008508 er RR ERR ERR SERERE E 31 Chapter 2 Simulator WIDIOWS iuoesse uod urRs RE RA aR RUE RA tans wa dadaes 4 RC R RT Rd ACER 33 Design Object Icons and Their Meaning is soos sos er RR RE RE REIS RR 35 Setting Fonts MMC 35 Main WIBOdOW 222 ressarree r Er en ne E E RAEE M RIPE E ERENS 36 b fpes prereset nekeer NERON A eA AoE NEEE r NERE 37 d cur do 4 40 5 4 a Ra rr E E Od ER A ee cE ee ee 38 Messag VIBWBE as euh baci quyac en e oui v e bey PAREN Eod eee He teem EAE PR 40 Multiple Document Interface MDI Frame leleeeee eee 41 Organizing Windows with Tab Groups slseeeeeeeee eere 42 Navigating in the Main Window 0 0 cece eee eee eh 43 Main Window Status Bar is oa sso eR CLR REA enead UR TOR S Ape SOR og Pra 44 Main Window Toolbar 0 0 eee eee e ene n een eee 45 ACUVE PROCESSES Pliego s s d dor ar cabe xa Oe P Kad SASS o e and doti aOR ee 47 PROCESS SUIS La ads De Ru ERREUR ahd RR dee RR A da CR RE ade X TR ada d d 48 Call Stack Palle S od od Deo tI CH ERO PE QUO Te N Ce HERI RP UE 48 Dataflow Window s oue ede etie ree atcog e lac e ROI oe ans eg s ddp CEN p RNC RON 49 Dataflow Window Loolbata 542s44005en eee PSG EOE eed Cee POS SSSR SRE A 50 List dns bs os ook ae rem 33 Ici P T 53 lufiuadu PR 56 Associative Arrays in Verilog SystemVerilog 2 0 0 cece eee eee eee 57 ModelSim User s Manual v6 2g 3 February 2007 Table of Contents
280. eg sear dba bese passe sewed Eee Suse 414 Figure F 6 GUI Zoom Button 222 sess pu RR Re RE Ro RR REA OR KE 414 Figure F 7 GUI Zoom BUCO e aia iro spe d Rare mre eeeeuecteaeoneeeeeaes 415 Figure F 8 Toolbar Manipulation s e elei e hr hh 415 Figure F 9 Preferences Dialog Box By Window Tab 0 0 0 2 ee ee eee 416 Figure F 10 Preferences Dialog Box By Name Tab 0 0 0 0 00s ee eee 417 ModelSim User s Manual v6 2g 17 February 2007 List of Tables Table 1 1 Simulation Tasks axes eRESREIA X RRVA DEE EErEE PR ESSERE ES 23 Table 1 2 Use Mod s ss stu Co eee our eee RA PER TEE Vin US ed Rar ex cod ease 2T Table 1 3 Definition of Object by Language 0 0 cece e 30 Table 1 4 Text Conventions ous ds dad ex VY SEE wA V EX Rex EE sauve tep e EE 31 Table 2 1 GUI Windows and Panes 0 0 00 nannaa 34 Table 2 2 Design Object Icons 20042ee4eeeditedoueideoeesedies auuesdgewses 35 Table 2 3 Icon Shapes and Design Object Types 0 0 0 cece eee ene 35 Table 2 4 Message Viewer Tasks 2 2224 5420eeeeSeenpeen Seed See eheenpornS ene de 4 Table 2 5 Commands for Tab Groups 0 00 0 cece eee eee ene 43 Table 2 6 Information Displayed in Status Bar 0 0 cece ee ee eee 44 Table 2 7 Main Window Toolbar Buttons 0 0 cece eee eee nee 45 Table 2 8 Dataflow Window Toolbar 0 0 cece eect eee 50 Table 2 9 Memories 2342054 cceces esSuesnee
281. elSim User s Manual v6 2g February 2007 Verilog PLI VPI DPI Compiling and Linking C Applications for PLI VPI DPI e Add a path before app so in the foreign attribute specification The path may include environment variables e Put the path in a UNIX shell environment variable LD_LIBRARY_PATH_32 library path without filename 32 bit or LD_LIBRARY_PATH_64 library path without filename gt 64 bit Windows Platforms e Microsoft Visual C 4 1 or Later cl c GX l lt install_dir gt modeltech include app cxx link dll export lt init_function gt app obj lt install_dir gt modeltech win32 mtipli lib out app dll The GX argument enables exception handling For the Verilog PLI the lt init_function gt should be init_usertfs Alternatively if there is no init_usertfs function the lt init_function gt specified on the command line should be veriusertfs For the Verilog VPI the init function should be vlog startup routines These requirements ensure that the appropriate symbol is exported and thus ModelSim can find the symbol when it dynamically loads the DLL When executing cl commands in a DO file use the NOLOGO switch to prevent the Microsoft C compiler from writing the logo banner to stderr Writing the logo causes Tcl to think an error occurred e MinGW C Version 3 2 3 g c l lt install_dir gt modeltech include app cpp g shared Bsymbolic o app dll app o L lt install_dir gt modelte
282. em section of the modelsim ini file See Simulator Control Variables for more information Suppressing Warning Messages You can suppress some warning messages For example you may receive warning messages about unbound components about which you are not concerned Suppressing VCOM Warning Messages Use the nowarn number argument to vcom to suppress a specific warning message For example vcom nowarn 1 suppresses unbound component warning messages Alternatively warnings may be disabled for all compiles via the modelsim ini file see Verilog Compiler Control Variables The warning message numbers are unbound component process without a wait statement null range no space in time literal multiple drivers on unresolved signal compliance checks optimization messages lint checks Signal value dependency at elaboration VHDL93 constructs in VHDL87 code locally static error deferred until simulation run r2 mpBR g0 1o0 014 C0 hN rP ll bt Oo 356 ModelSim User s Manual v6 2g February 2007 Error and Warning Messages Exit Codes These numbers are category of warning message numbers They are unrelated to vcom arguments that are specified by numbers such as vcom 87 which disables support for VHDL 1993 and 2002 Suppressing VLOG Warning Messages Use the nowarn lt CODE gt argument to vlog to suppress a specific warning message Warnings that can be disabled include the
283. en used within ModelSim DO files macros The variables are referenced in commands by prefixing the name with a dollar sign argc This variable returns the total number of parameters passed to the current macro architecture This variable returns the name of the top level architecture currently being simulated for a configuration or Verilog module this variable returns an empty string configuration This variable returns the name of the top level configuration currently being simulated returns an empty string if no configuration delta This variable returns the number of the current simulator iteration entity This variable returns the name of the top level VHDL entity or Verilog module currently being simulated library This variable returns the library name for the current region ModelSim User s Manual v6 2g 349 February 2007 Simulator Variables Simulator State Variables MacroNestingLevel This variable returns the current depth of macro call nesting n This variable represents a macro parameter where n can be an integer in the range 1 9 Now This variable always returns the current simulation time with time units e g 110 000 ns Note will return a comma between thousands now This variable when time resolution is a unary unit i e Ins Ips 1fs returns the current simulation time without time units e g 100000 when time resolution is a multiple of the unary unit i e 1Ons 100ps
284. en you link your PLI VPI application For example to use the standard C library specify Ic to the Id command e GNU C compiler g c fPIC I lt install_dir gt modeltech include app cpp Id b o app sl app o Ic e cc compiler cc c z DD32 l lt install_dir gt modeltech include app cpp Id b o app sl app o lc Note that fPIC may not work with all versions of gcc ModelSim User s Manual v6 2g 383 February 2007 Verilog PLI VPI DPI Compiling and Linking C Applications for PLI VPI DPI 64 bit HP Platform cc Compiler cc v DD64 O l lt install_dir gt modeltech include c app cpp Id b o app sl app o Ic 64 bit HP for IA64 Platform e HP ANSI C Compiler opt ansic bin cc usr ccs bin ld cc c DD64 l install dir modeltech include app cpp Id b o app s app o If your PLI VPI application requires a user or vendor supplied C library or an additional system library you will need to specify that library when you link your PLI VPI application For example to use the system math library specify Im to the 1d command cc c DD64 l install dir2 modeltech include math app c Id b o math app sl math app o Im 32 bit IBM RS 6000 Platform ModelSim loads shared libraries on the IBM RS 6000 workstation The shared library must import ModelSim s PLI VPI symbols and it must export the PLI or VPI application s initialization function or table The ModelSim tool s export file is located
285. ense agreement which are physically signed by you and an authorized representative of Mentor Graphics this Agreement and the applicable quotation contain the parties entire understanding relating to the subject matter and supersede all prior or contemporaneous agreements If you do not agree to these terms and conditions promptly return or if received electronically certify destruction of Software and all accompanying items within five days after receipt of Software and receive a full refund of any license fee paid GRANT OF LICENSE The software programs including any updates modifications revisions copies documentation and design data Software are copyrighted trade secret and confidential information of Mentor Graphics or its licensors who maintain exclusive title to all Software and retain all rights not expressly granted by this Agreement Mentor Graphics grants to you subject to payment of appropriate license fees a nontransferable nonexclusive license to use Software solely a in machine readable object code form b for your internal business purposes c for the license term and d on the computer hardware and at the site authorized by Mentor Graphics A site is restricted to a one half mile 800 meter radius Mentor Graphics standard policies and programs which vary depending on Software license fees paid or services purchased apply to the following a relocation of Software b use of Software which may be limited
286. ent Variables Accessed During Startup Environment variable Purpose MTI VCO MODE determines which version of ModelSim to use on platforms that support both 32 and 64 bit versions when ModelSim executables are invoked from the modeltech bin directory by a Unix shell command using full path specification or PATH search MODELSIM TCL identifies the pathname to a user preference file e g C nodeltech nodelsim tcl can be a list of file pathnames separated by semicolons Windows or colons UNIX note that user preferences are now stored in the modelsim file Unix or registry Windows ModelSim will still read this environment variable but it will then save all the settings to the modelsim file when you exit the tool Initialization Sequence The following list describes in detail ModelSim s initialization sequence The sequence includes a number of conditional structures the results of which are determined by the existence of certain files and the current settings of environment variables In the steps below names in uppercase denote environment variables except MTI LIB DIR which is a Tcl variable Instances of NAME denote paths that are determined by an environment variable except MTI LIB DIR which is determined by a Tcl variable 1 Determines the path to the executable directory modeltech lt platform gt Sets MODEL TECH to this path unless MODEL TECH OVERRIDE exists in which case MODEL TECH is set to
287. ent between the delayed and undelayed timing checks By far the greatest difference between these modes is evident when there are conditions on a delayed check event because the condition is not implicitly delayed Also timing checks specified without explicit delayed signals are delayed if necessary when they reference an input that is delayed for a negative timing check limit Other simulators perform timing checks on the delayed inputs To be compatible ModelSim supports both methods Verilog XL Compatible Simulator Arguments The simulator arguments listed below are equivalent to Verilog XL arguments and may ease the porting of a design to ModelSim See the vsim command for a description of each argument talt path delays l filename maxdelays mindelays tmultisource_int_delays no_cancelled_e_msg no neg tchk tno notifier tno path edge tno pulse msg no risefall delaynets tno show cancelled e nosdfwarn nowarn lt mnemonic gt 160 ModelSim User s Manual v6 2g February 2007 Verilog and SystemVerilog Simulation Simulating Verilog Designs se e percent se e style ondetect pulse e style onevent S S S pulse int e percent pulse int r percent pul tsdf nocheck celltype tsdf verbose tshow cancelled e ttransport int delays ttransport path delays ttypdelays Using Escaped Identifiers ModelSim always converts Verilog escaped identifiers to VHDL syntax
288. er 13 Tcl and Macros DO Files Tcl is a scripting language for controlling and extending ModelSim Within ModelSim you can develop implementations from Tcl scripts without the use of C code Because Tcl is interpreted development is rapid you can generate and execute Tcl scripts on the fly without stopping to recompile or restart ModelSim In addition if ModelSim does not provide the command you need you can use Tcl to create your own commands Tcl Features Using Tcl with ModelSim gives you these features e command history like that in C shells e full expression evaluation and support for all C language operators e a full range of math and trig functions e support of lists and arrays e regular expression pattern matching procedures e the ability to define your own commands e command substitution that is commands may be nested robust scripting language for macros Tcl References Two books about Tcl are Tcl and the Tk Toolkit by John K Ousterhout published by Addison Wesley Publishing Company Inc and Practical Programming in Tcl and Tk by Brent Welch published by Prentice Hall You can also consult the following online references e Select Help gt Tcl Man Pages Tcl Commands For complete information on Tcl commands select Help Tcl Man Pages Also see Simulator GUI Preferences for information on Tcl preference variables ModelSim User s Manual v6 2g 293 February 2007 Tcl and Macros DO Files T
289. er s Manual v6 29 121 February 2007 VHDL Simulation TextlO Implementation Issues is because access values must be passed as variables but functions do not allow variable parameters Based on an ISAC VASG recommendation the ENDLINE function has been removed from the TextIO package The following test may be substituted for this function L NULL OR L LENGTH 0 The ENDFILE Function In the VHDL Language Reference Manuals the ENDFILE function is listed as function ENDFILE L in TEXT return BOOLEAN As you can see this function is commented out of the standard TextIO package This is because the ENDFILE function is implicitly declared so it can be used with files of any type not just files of type TEXT Using Alternative Input Output Files You can use the TextIO package to read and write to your own files To do this just declare an input or output file of type TEXT For example for an input file The VHDL 87 declaration is file myinput TEXT is in pathname dat The VHDL 93 declaration is file myinput TEXT open read mode is pathname dat Then include the identifier for this file myinput in this example in the READLINE or WRITELINE procedure call Flushing the TEXTIO Buffer Flushing of the TEXTIO buffer is controlled by the UnbufferedOutput variable in the modelsim ini file Providing Stimulus You can stimulate and test a design by reading vectors from a file using them t
290. ermination of the Agreement and licenses granted under this Agreement The terms of this Agreement including without limitation the licensing and assignment provisions shall be binding upon your successors in interest and assigns The provisions of this section 4 shall survive the termination or expiration of this Agreement LIMITED WARRANTY 5 1 Mentor Graphics warrants that during the warranty period Software when properly installed will substantially conform to the functional specifications set forth in the applicable user manual Mentor Graphics does not warrant that Software will meet your requirements or that operation of Software will be uninterrupted or error free The warranty period is 90 days starting on the 15th day after delivery or upon installation whichever first occurs You must notify Mentor Graphics in writing of any nonconformity within the warranty period This warranty shall not be valid if Software has been subject to misuse unauthorized modification or improper installation MENTOR GRAPHICS ENTIRE LIABILITY AND YOUR EXCLUSIVE REMEDY SHALL BE AT MENTOR GRAPHICS OPTION EITHER A REFUND OF THE PRICE PAID UPON RETURN OF SOFTWARE TO MENTOR GRAPHICS OR B MODIFICATION OR REPLACEMENT OF SOFTWARE THAT DOES NOT MEET THIS LIMITED WARRANTY PROVIDED YOU HAVE OTHERWISE COMPLIED WITH THIS AGREEMENT MENTOR GRAPHICS MAKES NO WARRANTIES WITH RESPECT TO A SERVICES B SOFTWARE WHICH IS LICENSED TO YOU FOR A LIMITED TERM OR LICENSED
291. ertions file and line number 329 message display 343 messages turning off 347 setting format of messages 329 warnings locating 329 B bad magic number error message 177 base radix List window 211 Wave window 205 batch mode simulations 28 BindAtCompile ini file variable 324 binding VHDL default 115 blocking assignments 156 bookmarks Source window 68 Wave window 197 break 426 JKLMNOPQRSTUVWXYZ stop simulation run 46 BreakOnAssertion ini file variable 331 breakpoints deleting 67 223 setting 67 Source window viewing in 62 bsm file 235 buffered unbuffered output 338 busses RTL level reconstructing 184 user defined 215 G C applications compiling and linking 373 C applications compiling and linking 380 Call Stack pane 48 cancelling scheduled events performance 136 causality tracing in Dataflow window 230 cell libraries 162 chasing X 231 check_synthesis argument warning message 360 CheckPlusargs ini file variable VLOG 331 CheckpointCompressMode ini file variable 331 CheckSynthesis ini file variable 324 clock change sampling signals at 221 clock cycles display in timeline 203 collapsing time and delta steps 182 colorization in Source window 68 columns hide showing in GUI 415 moving 415 sorting by 415 combining signals busses 215 CommandHistory ini file variable 331 command line mode 27 commands event watching in DO
292. es ep ICD od ee e da E doc e OG 313 Environment Variable Expansion 0 0 0 cece eee eee nee eee 313 Setting Environment Variables zr Saunas hoes x rx GSEs SA ARAS Y eee 314 Creating Environment Variables in Windows 0 00 c eee eee eee eee eee 317 Referencing Environment Variables La order x EXE RERO EPA AURA Ax URS 318 Removing Temp Files VSOUT 0 ccc cece cee cece cence ht hn 319 Simulator Control Variables 224 55 sdex0s eu sees SEES ew GS RE RU DREE RT I ee EEL Eee 319 Library Path Variables suu saan sg RRENRRERERSERCRAZ ARENGRSAR CEA XGA PENAS 319 Verilog Compiler Control Variables llle 321 VHDL Compiler Control Variables 32 224 4044 5200 rh RE RR rh RE 324 Simulation Control Variables 0 0 e 329 Setting Simulator Control Variables With The GUI 0 000000 0000 342 Message System Variables 22 22 2acacsedsne been REX ERES amd x RR REA E 344 Commonly Used INI Variables 24 sese s hr n rh eg RR REED 346 Variable Precedence ase ba CR cse OR e Ra Ra Re Au C RR e RU Cd vb URS 349 Simulator State Variables iius ek e P Re ERE RERERAeREEE HP RA ERR ROMA HEX Kd 349 Referencing Simulator State Variables lille 350 Special Considerations for the now Variable 0 0 cee eee eee 350 Appendix B Location MAD DING vcd cage xndiand ac oboe Rea beue E ac d deo aD NU Hd o eee de d a uic 353 Referencing Source Files with Location Maps 0 0 00
293. essions affect the display of data but not acquisition of the data e The expression is evaluated when the List window would normally have displayed a row of data given the other trigger settings e The duration determines for how long triggering stays enabled after the gating expression returns to false 0 The default of O duration will enable triggering only while the expression is true 1 The duration is expressed in x number of default timescale units e Gating is level sensitive rather than edge triggered Trigger Gating Example Using the Expression Builder This example shows how to create a gating expression with the ModelSim Expression Builder Here is the procedure 1 Select Tools gt Window Preferences from the List window menu bar when the window is undocked and select the Triggers tab 2 Click the Use Expression Builder button ModelSim User s Manual v6 2g 219 February 2007 Waveform Analysis Configuring New Line Triggering in the List Window Figure 8 25 Trigger Gating Using Expression Builder Expression Builder ojx Expression Builder Insert Selected Signal Eg l nal oe ad fe d ef I edel odd doen Clear Save Test Ok Cancel 3 Select the signal in the List window that you want to be the enable signal by clicking on its name in the header area of the List window 4 Click Insert Selected Signal and then rising in the Expression
294. et top p rw_out top p test top p test2 top p _tw 4 T The procedure for tracing to the source of an unknown state in the Dataflow window is as follows 1 Load your design ModelSim User s Manual v6 29 231 February 2007 Tracing Signals with the Dataflow Window Finding Objects by Name in the Dataflow Window d Log all signals in the design or any signals that may possibly contribute to the unknown value log r will log all signals in the design Add signals to the Wave window or wave viewer pane and run your design the desired length of time Put a Wave window cursor on the time at which the signal value is unknown StX In Figure 9 4 Cursor 1 at time 2305 shows an unknown state on signal t out Add the signal of interest to the Dataflow window by doing one of the following o double clicking on the signal s waveform in the Wave window o right clicking the signal in the Objects window and selecting Add to Dataflow gt Selected Signals from the popup menu o selecting the signal in the Objects window and selecting Add Dataflow Selected Signals from the menu bar In the Dataflow window make sure the signal of interest is selected Trace to the source of the unknown by doing one of the following o Ifthe Dataflow window is docked select Tools gt Trace gt TraceX Tools gt Trace gt TraceX Delay Tools gt Trace gt ChaseX or Tools gt Trace gt ChaseX Delay
295. etting GUI Preferences Simulator GUI Preferences e use MODELSIM TCL environment variable if it exists if MODELSIM TCL is a list of files each file is loaded in the order that it appears in the list else e use modelsim tcl else e use HOME modelsim tcl if it exists Note that in versions 6 1 and later ModelSim will save to the modelsim file any variables it reads in from a modelsim tcl file The values from the modelsim tcl file will override like variables in the modelsim file 418 ModelSim User s Manual v6 2g February 2007 Appendix G System Initialization ModelSim goes through numerous steps as it initializes the system during startup It accesses various files and environment variables to determine library mappings configure the GUI check licensing and so forth Files Accessed During Startup The table below describes the files that are read during startup They are listed in the order in which they are accessed Table G 1 Files Accessed During Startup modelsim ini contains initial tool settings see Simulator Control Variables for specific details on the modelsim ini file location map file pref tcl used by ModelSim tools to find source files based on easily reallocated soft paths default file name is mgc location map contains defaults for fonts colors prompts window positions and other simulator window characteristics modelsim UNIX or Windows registry contains last working
296. event is scheduled at 10ms 10ns The cancelled events are not reclaimed until time 10ms is reached and the cancelled event is processed As a result there will be 500000 10ms 20ns cancelled but un deleted events Once 10ms is reached memory will no longer increase because the simulator will be reclaiming events as fast as they are added For projected waveforms the following would behave the same way signals synch bit 0 p process synch begin output lt 0 1 after 10ms end process synch lt not synch after 10 ns Converting an Integer Into a bit_vector The following code demonstrates how to convert an integer into a bit_vector 136 ModelSim User s Manual v6 2g February 2007 VHDL Simulation Converting an Integer Into a bit vector library ieee use ieee numerioc bit ALL entity test is end test architecture only of test is signal sl bit vector 7 downto 0 signal int integer 45 begin p process begin wait for 10 ns sl lt bit vector to signed int 8 end process p end only ModelSim User s Manual v6 2g 137 February 2007 VHDL Simulation Converting an Integer Into a bit vector 138 ModelSim User s Manual v6 2g February 2007 Chapter 6 Verilog and SystemVerilog Simulation This chapter describes how to compile and simulate Verilog and SystemVerilog designs with ModelSim ModelSim implements the Verilog language as defined by the IEEE Standards 1364 1995 and 1
297. exec rm Sf Provide file root argument and load_wave restores all saved windows Default file root is wave proc load_wave fileroot wave foreach f lsort glob nocomplain fileroot 1 9 do echo Loading f view new wave do f if file exists windowSet Sfileroot do do windowSet Sfileroot do This next example specifies the compiler arguments and lets you compile any number of files 306 ModelSim User s Manual v6 2g February 2007 Tcl and Macros DO Files Macros DO Files set Files list set nbrArgs Sarge for set x 1 x lt SnbrArgs incr x set lappend Files 1 shift eval vcom 93 explicit noaccel Files This example is an enhanced version of the last one The additional code determines whether the files are VHDL or Verilog and uses the appropriate compiler and arguments depending on the file type Note that the macro assumes your VHDL files have a vhd file extension set vhdFiles list set vFiles list set nbrArgs Sarge for set x 1 x lt SnbrArgs incr x if string match vhd 1 lappend vhdFiles 1 else lappend vFiles 1 shift if llength SvhdFiles gt 0 eval vcom 93 explicit noaccel vhdFiles if llength SvFiles gt 0 eval vlog vFiles Macros DO Files ModelSim macros also called DO files are simply scripts that contain ModelSim and optionally Tcl commands You invoke
298. fault default Veriuser This variable specifies a list of dynamically loadable objects for Verilog PLI VPI applications e Value Range one or more valid shared object names e Default commented out WarnConstantChange This variable controls whether a warning is issued when the change command changes the value of a VHDL constant or generic e Value Range 0 1 e Default on 1 WaveSignalNameWidth This variable controls the number of visible hierarchical regions of a signal name shown in the Wave Window e Value Range 0 display full name positive integer display corresponding level of hierarchy e Default 0 WLFCacheSize This variable sets the number of megabytes for the WLF reader cache WLF reader caching caches blocks of the WLF file to reduce redundant file I O e Value Range positive integer ModelSim User s Manual v6 2g 339 February 2007 Simulator Variables Simulator Control Variables e Default 0 WLFCollapseMode This variable controls when the WLF file records values e Value Range 0 every change of logged object 1 end of each delta step 2 end of simulator time step e Default WLFCompress This variable enables WLF file compression e Value Range 0 1 e Default 1 on WLFDeleteOnQuit This variable specifies whether a WLF file should be deleted when the simulation ends e Value Range 0 1 e Default 0 do not delete WLFFilename This variable specifies the default WLF file na
299. file 307 system 299 VSIM Tcl commands 300 comment character Tcl and DO files 296 ModelSim User s Manual v6 2g February 2007 ABCDEFGHIJKLMNOPQRSTUVWXYZ compare signal virtual restrictions 215 compare simulations 175 compilation multi file issues SystemVerilog 145 compilation unit scope 145 compile order auto generate 90 changing 89 SystemVerilog packages 142 compiler directives 171 IEEE Std 1364 2000 171 XL compatible compiler directives 172 compiling overview 25 changing order in the GUI 89 grouping files 90 order changing in projects 89 properties in projects 94 range checking in VHDL 110 Verilog 140 incremental compilation 141 XL uselib compiler directive 147 XL compatible options 146 VHDL 109 110 VITAL packages 124 compiling C code gcc 375 component default binding rules 115 Compressing files VCD tasks 282 ConcurrentFileLimit ini file variable 332 configuration simulator state variable 349 configurations Verilog 149 connectivity exploring 227 context menus Library tab 102 convert real to time 127 convert time to real 126 cursors adding deleting locking naming 193 link to Dataflow window 227 measuring time with 192 trace events with 230 Wave window 192 ModelSim User s Manual v6 2g February 2007 customizing via preference variables 415 D deltas explained 116 Dataflow window 49 225 extended mode 225 pan 229 zoom 229 see
300. file via the GetPrivateProfileString Tcl command The ini file that is read will be the default file defined at the time pref tcl is loaded ModelSim User s Manual v6 2g 423 February 2007 System Initialization Initialization Sequence 424 ModelSim User s Manual v6 29 February 2007 ABCDEFGH I Symbols comment character 296 disable_signal_spy 252 enable_signal_spy 253 finish behavior customizing 336 unit scope visibility in SV declarations 145 Ani control variables AssertFile 329 AssertionDebug 329 AssertionFormat 329 AssertionFormatBreak 330 AssertionFormatError 330 AssertionFormatFail 330 AssertionFormatFatal 330 AssertionFormatNote 330 AssertionFormatWarning 331 BreakOnAssertion 331 CheckPlusargs 331 CheckpointCompressMode 331 CommandHistory 331 ConcurrentFileLimit 332 DatasetSeparator 332 DefaultForceKind 332 DefaultRadix 332 DefaultRestartOptions 333 DelayFileOpen 333 DumpportsCollapse 333 GenerateFormat 333 GlobalSharedObjectList 333 IgnoreError 333 IgnoreFailure 334 IgnoreNote 334 IgnoreWarning 334 IterationLimit 334 License 335 LockedMemory 335 NumericStdNoWarnings 336 PathSeparator 336 Resolution 337 ModelSim User s Manual v6 29 February 2007 JKLMNOPQRSTUVWXYZ Index RunLength 337 Startup 338 StdArithNoWarnings 338 ToggleMaxIntValues 338 TranscriptFile 338 UnbufferedOutput 338 UseCsupV2 338 UserTimeUnit 339 Veriuser 339
301. fixed to its medium and container as received from Mentor Graphics All copies shall remain the property of Mentor Graphics or its licensors You shall maintain a record of the number and primary location of all copies of Software including copies merged with other software and shall make those records available to Mentor Graphics upon request You shall not make Software available in any form to any person other than employees and on site contractors excluding Mentor Graphics competitors whose job performance requires access and who are under obligations of confidentiality You shall take appropriate action to protect the confidentiality of Software and ensure that any person permitted access to Software does not disclose it or use it except as permitted by this Agreement Except as otherwise permitted for purposes of interoperability as specified by applicable and mandatory local law you shall not reverse assemble reverse compile reverse engineer or in any way derive from Software any source code You may not sublicense assign or otherwise transfer Software this Agreement or the rights under it whether by operation of law or otherwise attempted transfer without Mentor Graphics prior written consent and payment of Mentor Graphics then current applicable transfer charges Any attempted transfer without Mentor Graphics prior written consent shall be a material breach of this Agreement and may at Mentor Graphics option result in the immediate t
302. for example to execution of a single session by a single user on the authorized hardware or for a restricted period of time such limitations may be technically implemented through the use of authorization codes or similar devices and c support services provided including eligibility to receive telephone support updates modifications and revisions EMBEDDED SOFTWARE If you purchased a license to use embedded software development ESD Software if applicable Mentor Graphics grants to you a nontransferable nonexclusive license to reproduce and distribute executable files created using ESD compilers including the ESD run time libraries distributed with ESD C and C compiler Software that are linked into a composite program as an integral part of your compiled computer program provided that you distribute these files only in conjunction with your compiled computer program Mentor Graphics does NOT grant you any right to duplicate incorporate or embed copies of Mentor Graphics real time operating systems or other embedded software products into your products or applications without first signing or otherwise agreeing to a separate agreement with Mentor Graphics for such purpose BETA CODE Software may contain code for experimental testing and evaluation Beta Code which may not be used without Mentor Graphics explicit authorization Upon Mentor Graphics authorization Mentor Graphics grants to you a temporary nontransferable
303. for in the values pane e The find operation works only within the active pane in the Wave window Searching for Values or Transitions Available in some versions of ModelSim the Search command lets you search for transitions or values on selected signals When you select Edit Search Signals the Signal Search dialog appears ModelSim User s Manual v6 2g 199 February 2007 Waveform Analysis Searching in the Wave and List Windows Figure 8 9 Wave Signal Search Dialog Wave Signal Search window wave Iof x Signal Name s No Signals Selected Search Type Any Transition C Rising Edge C Falling Edge C Search for Signal Value Yaj Search for Expression Open i Bue Search ptions Search Forward Search Reverse Search Results Status Time Done One option of note is Search for Expression The expression can involve more than one signal but is limited to signals currently in the window Expressions can include constants variables and DO files See Expression Syntax for more information Using the Expression Builder for Expression Searches The Expression Builder is a feature of the Wave and List Signal Search dialog boxes and the List trigger properties dialog box It aids in building a search expression that follows the GUI expression format To locate the Builder select Edit Search Signals List or Wave window select the Search for Expression option in the resulting
304. form 000000004 32 bit IBM RS 6000 Platform 000 4 64 bit IBM RS 6000 Platform 000 Specifying Application Files to Load 0 PLY VPI file loading asa Geka ade eee bak RARE whats DPI File Loading is isctacdve eR REA RR een RR RES Loading Shared Objects with Global Symbol Visibility PLI Example 222 xs Xx seeks RERER GU ERIT ORE abs HERE VPLEXIIDIG eg ino 3 ag sa e ees OS Re Sings Ma dads DPI Example eRE GERE ERR ARA HaT Edo GA ERE EA dE The PLI Callback reason Argument 04 The sizetf Callback Function 222 ssa zer vn eevee PLI Object Handles i Ge exsee ete e Rte bees eter Sees A Rd Third Party PLI Applications sess ere REERI ES E REA Support for VHDL Objects 424 naonana YR RIA X TRERES IEEE Std 1364 ACC Routines 2222s luec e RR nn 12 Table of Contents ModelSim User s Manual v6 2g February 2007 Table of Contents IEEE Std 1364 TF Routines oder ERE ER REX REPRE CRPE REA CARRP EXER ERR ERUE 307 SystemVerilog DPI Access Routines 0 0 cece cece ehh 397 Verilog XL Compatible Routines xoc RA ER REN a head ER kA P XE ER CRAS 398 64 bit Support for PLI uid ks e aor end eh REREESM FPERCPSOUGC eee theo ERR ERR 398 Using 64 bit ModelSim with 32 bit Applications 0 0 eee eee eee eee 398 PLUVPI Tracing 32 0644e i420 yo Bie dade ee cee beeen don Riesa YS eeeeeae E 398 The Purpose of Tracing Files 1522 asec
305. from a standard package To track the problem note the time the warning occurs restart the simulation and run to one time unit before the noted time At this point start stepping the simulator until the warning appears The location of the blue arrow in a Source window will be pointing at the line following the line with the comparison These messages can be turned off by setting the NumericStdNoWarnings variable to 1 from the command line or in the modelsim ini file Sensitivity list warning signal is read by the process but is not in the sensitivity list e Description ModelSim outputs this message when you use the check synthesis argument to vcom It reports the warning for any signal that is read by the process but is not in the sensitivity list e Suggested action There are cases where you may purposely omit signals from the sensitivity list even though they are read by the process For example in a strictly sequential process you may prefer to include only the clock and reset in the sensitivity list because it would be a design error if any other signal triggered the process In such cases your only option is to not use the check synthesis argument Tcl Initialization error 2 Tcl Init Error 2 Can t find a usable Init tcl in the following directories tcl tc18 3 e Description This message typically occurs when the base file was not included in a Unix installation When you install ModelSim you need to do
306. function executed is the only one printed to the transcript This may cause some unexpected behavior in certain circumstances Consider this example vsim c do run 20 simstats quit f top You probably expect the simstats results to display in the Transcript window but they will not because the last command is quit f To see the return values of intermediate commands you must explicitly print the results For example vsim do run 20 echo simstats quit f c top Command History Shortcuts You can review the simulator command history or reuse previously entered commands with the following shortcuts at the ModelSim VSIM prompt Table E 1 Command History Shortcuts repeats the last command repeats command number n n is the VSIM prompt number e g for this prompt VSIM 12 gt n 12 repeats the most recent command starting with abc ModelSim User s Manual v6 2g 403 February 2007 Command and Keyboard Shortcuts Main and Source Window Mouse and Keyboard Shortcuts Table E 1 Command History Shortcuts cont xyz ab replaces xyz in the last command with ab up arrow and down scrolls through the command history arrow keys click on prompt left click once on a previous ModelSim or VSIM prompt in the transcript to copy the command typed at that prompt to the active cursor his or history shows the last few commands up to 50 are kept Main and Source Window Mouse and Keyboard
307. g 2001 disabling support 323 Verilog PLI VP DPII registering VPI applications 367 Verilog PLI VPI 64 bit support in the PLI 398 debugging PLI VPI code 399 Verilog PLI VPI DPI compiling and linking PLI VPI C applications 380 compiling and linking PLI VPI CPI C applications 373 PLI callback reason argument 390 PLI support for VHDL objects 393 registering PLI applications 366 specifying the PLI VPI file to load 386 ModelSim User s Manual v6 2g February 2007 JKLMNOPQRSTUVWX YZ Verilog XL compatibility with 139 365 Veriuser ini file variable 339 367 Veriuser specifying PLI applications 367 veriuser c file 392 VHDL compiling design units 109 creating a design library 109 delay file opening 348 dependency checking 110 file opening delay 348 language templates 65 language versions 111 library clause 105 object support in PLI 393 optimizations inlining 110 simulating 114 source code viewing 62 standards 28 timing check disabling 114 VITAL package 106 VHDL utilities 124 125 245 256 get_resolution 125 to_real 126 to_time 127 VHDL 1987 compilation problems 111 VHDL 1993 enabling support for 328 VHDL 2002 enabling support for 328 VHDLOS3 ini file variable 328 viewing 40 library contents 101 waveforms 175 virtual compare signal restrictions 215 virtual hide command 184 virtual objects 183 virtual functions 185 virtual regions 186 virtua
308. generate statements had numerous inconsistencies and ambiguities As a result ModelSim implements the rules that have been adopted for Verilog 2005 Most of the rules are backwards compatible but there is one key difference related to name visibility Name Visibility in Generate Statements Consider the following code example module m parameter p 1 generate if p integer x 1 else real x 2 0 endgenerate initial display x endmodule This code sample is legal under 2001 rules However it is illegal under the 2005 rules and will cause an error in ModelSim Under the new rules you cannot hierarchically reference a name in an anonymous scope from outside that scope In the example above x does not propagate its visibility upwards and each condition alternative is considered to be an anonymous scope To fix the code such that it will simulate properly in ModelSim write it like this instead 150 ModelSim User s Manual v6 2g February 2007 Verilog and SystemVerilog Simulation Simulating Verilog Designs module m parameter p 1 if p begin s integer x 1 end else begin s real x 2 0 end initial Sdisplay s x endmodule Since the scope is named in this example normal hierarchical resolution rules apply and the code is fine Note too that the keywords generate endgenerate are optional under the 2005 rules and are excluded in the second example Simulating Verilog Designs
309. goes in the future queue 156 ModelSim User s Manual v6 2g February 2007 Verilog and SystemVerilog Simulation Simulating Verilog Designs Non Blocking Assignments A non blocking assignment goes into either the non blocking assignment update event queue or the future non blocking assignment update event queue Non blocking assignments with no delays and those with explicit zero delays are treated the same Non blocking assignments should be used only for outputs of flip flops This insures that all outputs of flip flops do not change until after all flip flops have been evaluated Attempting to use non blocking assignments in combinational logic paths to remove race conditions may only cause more problems In the preceding example changing all statements to non blocking assignments would not remove the race condition This includes using non blocking assignments in the generation of gated clocks The following is an example of how to properly use non blocking assignments w genl always master clkl master gen2 always clk1 Clk2 clk1 fl always posedge clk1 begin ql lt dl end 25 always posedge clk2 begin q2 lt ql end If written this way a value on d always takes two clock cycles to get from d to q2 If you change c k master and clk2 clk1 to non blocking assignments or q2 lt q1 and q1 lt dl to blocking assignments then d7 may get to q2 is less than two clock cycles D
310. gt converts two 32 bit pieces high and low order into a 64 bit quantity Time in ModelSim is a 64 bit integer RealToTime real converts a real number to a 64 bit integer in the current Time Scale scaleTime time lt scaleFactor gt returns the value of time multiplied by the scaleFactor integer Relations Table 13 6 Tcl Time Relation Commands Command Description eqTime time time evaluates for equal neqTime time time evaluates for not equal gtTime time time evaluates for greater than gteTime time time evaluates for greater than or equal ItTime time time evaluates for less than IteTime time time evaluates for less than or equal All relation operations return 1 or 0 for true or false respectively and are suitable return values for TCL conditional expressions For example if eqTime Now 1750ns 302 ModelSim User s Manual v6 2g February 2007 Tcl and Macros DO Files Tcl Examples Arithmetic Table 13 7 Tcl Time Arithmetic Commands Command Description addTime time time add time divTime time time 64 bit integer divide mulTime time time 64 bit integer multiply subTime time time subtract time Tcl Examples This is an example of using the Tcl while loop to copy a list from variable a to variable b reversing the order of the elements along the way
311. guage allows access to any signal from any other hierarchical block without having to route it via the interface This means you can use hierarchical notation to either assign or determine the value of a signal in the design hierarchy from a testbench This capability fails when a Verilog testbench attempts to reference a signal in a VHDL block or reference a signal in a Verilog block through a VHDL level of hierarchy This limitation exists because VHDL does not allow hierarchical notation In order to reference internal hierarchical signals you have to resort to defining signals in a global package and then utilize those signals in the hierarchical blocks in question But this requires that you keep making changes depending on the signals that you want to reference The Signal Spy procedures and system tasks overcome the aforementioned limitations They allow you to monitor spy drive force or release hierarchical objects in a VHDL or mixed design The VHDL procedures are provided via the Util Package within the modelsim lib library To access the procedures you would add lines like the following to your VHDL code library modelsim lib use modelsim lib util all The Verilog tasks are available as built in System Tasks and Functions The table below shows the VHDL procedures and their corresponding Verilog system tasks Table 10 1 Signal Spy Mapping VHDL Procedures to Verilog System Tasks VHDL procedures Verilog system tasks di
312. h Delay Mode In path delay mode the distributed delays are set to zero in any module that contains a path delay Select this delay mode with the delay mode path compiler argument or the delay mode path compiler directive Unit Delay Mode In unit delay mode the non zero distributed delays are set to one unit of simulation resolution determined by the minimum time precision argument in all timescale directives in your design or the value specified with the t argument to vsim and the specify path delays and timing constraints are ignored Select this delay mode with the delay mode unit compiler argument or the delay mode unit compiler directive Zero Delay Mode In zero delay mode the distributed delays are set to zero and the specify path delays and timing constraints are ignored Select this delay mode with the delay mode zero compiler argument or the delay mode zero compiler directive System Tasks and Functions ModelSim supports system tasks and functions as follows e All system tasks and functions defined in IEEE Std 1364 e Some system tasks and functions defined in SystemVerilog IEEE std p1800 2005 LRM e Several system tasks and functions that are specific to ModelSim e Several non standard Verilog XL system tasks The system tasks and functions listed in this section are built into the simulator although some designs depend on user defined system tasks implemented with the Programming Language Interface PLI Veril
313. hat you wish to disable e dest object Required string A full hierarchical path or relative downward path with reference to the calling block to a VHDL signal or Verilog register net This path should match the path that was specified in the init signal spy call that you wish to disable e verbose Optional integer Possible values are 0 or 1 Specifies whether you want a message reported in the transcript stating that a disable occurred and the simulation time that it occurred Default is 0 no message Related tasks init_signal_spy enable_signal_spy Example See Sinit signal spy Example 252 ModelSim User s Manual v6 2g February 2007 Signal Spy enable signal spy enable signal spy The S enable signal spy system task enables the associated Sinit signal spy task The association between the enable signal spy task and the Sinit signal spy task is based on specifying the same src object and dest object arguments to both tasks The Senable signal spy task can only affect Sinit signal spys tasks that had their control state argument set to 0 or 1 Syntax S enable signal spy src object dest object lt verbose gt Returns Nothing Arguments src object Required string A full hierarchical path or relative downward path with reference to the calling block to a VHDL signal or Verilog register net This path should match the path that was specified in the init signal spy call that you wish to en
314. he system function is a 32 bit integer that is set to the exit status code of the underlying OS process Note 222 LLL There is a known issue in the return value of this system function on the win32 platform If the OS command is built with a cygwin compiler the exit status code may not be reported correctly when an exception is thrown and thus the return code may be wrong The workaround is to avoid building the application using cygwin or to use the switch mno cygwin in cygwin the gcc command line systemf list of args This system function can take any number of arguments The list of args is treated exactly the same as with the display function The OS command that will be run is the final output from display given the same list of args Return value of the systemf function is a 32 bit integer that is set to the exit status code of the underlying OS process Note There is a known issue in the return value of this system function on the win32 platform If the OS command is built with a cygwin compiler the exit status code may not be reported correctly when an exception is thrown and thus the return code may be wrong The workaround is to avoid building the application using cygwin or to use the switch mno cygwin in cygwin the gcc command line Supported Tasks that Have Been Extended The following system tasks are extended to provide additional fun
315. he Clear command is enabled The active pane is denoted by a blue title bar For more information see Navigating the Graphic User Interface Main Window Status Bar Figure 2 6 Main Window Status Bar Project rtl Now Ons Delta 0 sim top p Z Fields at the bottom of the Main window provide the following information about the current simulation Table 2 6 Information Displayed in Status Bar Field Description Project name of the current project Now the current simulation time Delta the current simulation iteration number Profile Samples the number of profile samples collected during the current simulation Memory the total memory used during the current simulation environment name of the current context object selected in the active Structure tab of the Workspace line column line and column numbers of the cursor in the active Source window 44 ModelSim User s Manual v6 29 February 2007 Simulator Windows Navigating in the Main Window Main Window Toolbar Buttons on the Main window toolbar give you quick access to various ModelSim commands and functions Table 2 7 Main Window Toolbar Buttons Button Menu equivalent Command equivalents New File File New Source create a new source file Open File Open open the Open File dialog Save File Save save the contents of the active pane E 5 Print File Print open the Print dialog Cut Edit Cut 4
316. hlight which identifies the path you ve traversed through the design Erase all clear the window Edit Erase all Regenerate clear and redraw the display using Edit Regenerate an optimal layout Zoom In zoom in by a factor of two from current view Zoom Out zoom out by a factor of two from current view Zoom Full zoom out to show all components in the window ModelSim User s Manual v6 2g 51 February 2007 Simulator Windows Dataflow Window Table 2 8 Dataflow Window Toolbar Button Menu equivalent Stop Drawing halt any drawing currently happening in the window pane Show Wave display the embedded wave viewer View Show Wave re 52 ModelSim User s Manual v6 2g February 2007 Simulator Windows List Window List Window The List window displays the results of your simulation run in tabular format The window is divided into two adjustable columns which allow you to scroll horizontally through the listing on the right while keeping time and delta visible on the left The List window opens by default in the MDI frame of the Main window as shown in Figure 2 10 Figure 2 10 List Window Docked in Main Window MDI Frame top clk IEETERESUSA ftop pdatay ftop prw y ftop sruy ftop pstrb ftop sstrby top sa ftop prdy ftop srdyy OXXX 329000000000000UQUQC X X X XXX 001 1 jjj 2222222222222222 0 1 1 eh fej eh al 2222222222222222
317. how the delays in the module would be handled in each case e tnotset The delay will be rounded to 12 5 as directed by the module s timescale directive e tis set to 1 fs The delay will be rounded to 12 5 Again the module s precision is determined by the timescale directive ModelSim does not override the module s precision e tissetto 1 ns The delay will be rounded to 12 The module s precision is determined by the t setting ModelSim has no choice but to round the module s time values because the entire simulation is operating at 1 ns Choosing the Resolution for Verilog You should choose the coarsest resolution limit possible that does not result in undesired rounding of your delays The time precision should not be unnecessarily small because it will limit the maximum simulation time limit and it will degrade performance in some cases Event Ordering in Verilog Designs Event based simulators such as ModelSim may process multiple events at a given simulation time The Verilog language is defined such that you cannot explicitly control the order in which simultaneous events are processed Unfortunately some designs rely on a particular event order and these designs may behave differently than you expect Event Queues Section 5 of the IEEE Std 1364 1995 LRM defines several event queues that determine the order in which events are evaluated At the current simulation time the simulator has the following pending events
318. iamond in the Wave window virtual signals buses and functions see Virtual Objects for more information Wave Window Overview The Wave window opens by default in the MDI frame of the Main window as shown below The window can be undocked from the main window by pressing the Undock button in the window header or by using the view undock wave command The preference variable PrefMain ViewUnDocked wave can be used to control this default behavior Setting this variable will open the Wave Window undocked each time you start ModelSim ModelSim User s Manual v6 2g 187 February 2007 Waveform Analysis Wave Window Overview Figure 8 1 Undocking the Wave Window Fle Edt Vew Foma Comple Smidse Add Tools Window Help Undock button gl X BW amp Q E lest sngbuft clock sc clock ang INST tingbul ScModule block contol Architect block2 store Module block3 relreve Module dj setiever retrieve Statement d MLW relieve Process a BASS miava Pownce Ald zi BE ay iie Te T 6 ese 1111010010 0100011011 VSIM 5 Oc d 3926 2 4S est angbut nng INST tc Restinga Aing INST clock Pest angbf nng INST Aeset Pest angbuf ang INST Atada Aest_angbuf ang_ INST outet Aest angbut nng INST block Aest_angouf ang_ NST block Aest_sngbut ing_INST block Aest_angbut ang_INST block Pest angbuf ang INST block Ptest sngbf nng INST block Aest angbuf ang INS
319. iated within the same design 148 ModelSim User s Manual v6 2g February 2007 Verilog and SystemVerilog Simulation Compiling Verilog Files module top uselib dir h vendorA libext v NAND2 ul n1 n2 n3 uselib dir h vendorB libext v NAND2 u2 n4 n5 n6 endmodule vlog compile uselibs top This allows the NAND2 module to have different definitions in the vendorA and vendorB libraries uselib is Persistent As mentioned above the appearance of a uselib directive in the source code explicitly defines how instantiations that follow it are resolved This may result in unexpected consequences For example consider the following compile command vlog compile uselibs dut v srtr v Assume that dut v contains a uselib directive Since srtr v is compiled after dut v the uselib directive is still in effect When srtr is loaded it is using the uselib directive from dut v to decide where to locate modules If this is not what you intend then you need to put an empty uselib at the end of dut v to close the previous uselib statement Verilog Configurations The Verilog 2001 specification added configurations Configurations specify how a design is assembled during the elaboration phase of simulation Configurations actually consist of two pieces the library mapping and the configuration itself The library mapping is used at compile time to determine into which libraries the source files are to be compiled Here is
320. ign vsim nospecify disables specify path delays and timing checks for all instances in the specified design Troubleshooting Specifying the Wrong Instance By far the most common mistake in SDF annotation is to specify the wrong instance to the simulator s SDF options The most common case is to leave off the instance altogether which is the same as selecting the top level design unit This is generally wrong because the instance paths in the SDF are relative to the ASIC or FPGA model which is usually instantiated under a top level testbench See Instance Specification for an example A common example for both VHDL and Verilog testbenches is provided below For simplicity the test benches do nothing more than instantiate a model that has no ports VHDL Testbench entity testbench is end 274 ModelSim User s Manual v6 2g February 2007 Standard Delay Format SDF Timing Annotation Troubleshooting architecture only of testbench is component myasic end component begin dut myasic end Verilog Testbench module testbench myasic dut endmodule The name of the model is myasic and the instance label is dut For either testbench an appropriate simulator invocation might be vsim sdfmax testbench dutzmyasic sdf testbench Optionally you can leave off the name of the top level vsim sdfmax dut myasic sdf testbench The important thing is to select the instance for which the SDF is intended If the
321. ignal driver e delay type Optional integer Specifies the type of delay that will be applied The value must be either 0 inertial or 1 transport The default is 0 e verbose Optional integer Possible values are 0 or 1 Specifies whether you want a message reported in the Transcript stating that the src_object is driving the dest_object Default is 0 no message Related tasks init_signal_spy signal_force signal_release Limitations e When driving a Verilog net the only delay type allowed is inertial If you set the delay type to 1 transport the setting will be ignored and the delay type will be inertial e Any delays that are set to a value less than the simulator resolution will be rounded to the nearest resolution unit no special warning will be issued e Verilog memories arrays of registers are not supported init_signal_driver Example This example creates a local clock c k0 and connects it to two clocks within the design hierarchy The bIkI clk will match local c k0 and a message will be displayed The bIk2 clk will match the local c k0 but be delayed by 100 ps For the second call to work the blk2 clk must be a VHDL based signal because if it were a Verilog net a 100 ps inertial delay would consume the 40 ps clock period Verilog nets are limited to only inertial delays and thus the setting of 1 transport delay would be ignored timescale 1 ps 1 ps module testbench reg clk0 initial
322. ignal values update in the Dataflow pane 228 ModelSim User s Manual v6 29 February 2007 Tracing Signals with the Dataflow Window Zooming and Panning Figure 9 3 Wave Viewer Displays Inputs and Outputs of Selected Process dataflow default default iW File Edit Yiew Add Trace Tools Window R StOtest NAND SO Inputs 4 jtop c clk top c pstrb 4 jtop c prw E top c hit gm op c paddr Inouts fi P op c setsel Outputs E top c oen E op c wen 4 jtop c prdy r Now St St sta 0000 00000011 1000 1111 0111 1 2820 ns a000 m o Oon Oon Oo Ny au T D RU ZR EL eh eFC ee te 10 20 30 40 50 ns 1s Keep T GEOR 55 Another scenario is to select a process in the Dataflow pane which automatically adds to the wave viewer pane all signals attached to the process See Tracing Events Causality for another example of using the embedded wave viewer Zooming and Panning The Dataflow window offers several tools for zooming and panning the display ModelSim User s Manual v6 2g February 2007 229 Tracing Signals with the Dataflow Window Tracing Events Causality These zoom buttons are available on the toolbar Zoom In Zoom Out Zoom Full zoom in by a factor zoom out by a zoom out to view of two from the factor of two from the entire schematic current view current view To zoom with the mouse you can e
323. ignals Hence you need to call Sinit signal driver only once for a particular pair of signals Once S init signal driver is called any change on the source signal will be driven on the destination signal until the end of the simulation Thus we recommend that you place all Sinit signal driver calls in a Verilog initial block See the example below Syntax init signal driver src object dest object delay delay type lt verbose gt Returns Nothing Arguments src object Required string A full hierarchical path or relative downward path with reference to the calling block to a VHDL signal or Verilog net Use the path separator to which your simulation is set 1 e or A full hierarchical path must begin with a or The path must be contained within double quotes e dest object Required string A full hierarchical path or relative downward path with reference to the calling block to an existing VHDL signal or Verilog net Use the path separator to which your simulation is set i e or A full hierarchical path must begin with a or The path must be contained within double quotes e delay Optional integer real or time Specifies a delay relative to the time at which the src object changes The delay can be an inertial or transport delay If no delay is specified then a delay of zero is assumed 254 ModelSim User s Manual v6 2g February 2007 Signal Spy init s
324. il the end of the simulation unless the control state is set The control state determines whether the mirroring of values can be enabled disabled and what the initial state is Subsequent control of whether the mirroring of values is enabled disabled is handled by the enable signal spy and disable signal spy calls We recommend that you place all init signal spy calls in a VHDL process You need to code the VHDL process correctly so that it is executed only once The VHDL process should not be sensitive to any signals and should contain only init signal spy calls and a simple wait statement The process will execute once and then wait forever which is the desired behavior See the example below Syntax init signal spy src object dest object lt verbose gt control state Returns Nothing Arguments e src object Required string A full hierarchical path or relative downward path with reference to the calling block to a VHDL signal or Verilog register net Use the path separator to which your simulation is set i e or A full hierarchical path must begin with a or The path must be contained within double quotes e dest object Required string A full hierarchical path or relative downward path with reference to the calling block to an existing VHDL signal or Verilog register Use the path separator to which your simulation is set 1 e or A full hierarchical path must begin with a or
325. ile e Default commented out StdArithNoWarnings This variable suppresses warnings generated within the accelerated Synopsys std_arith packages You can set this variable interactively in the GUI refer to Setting Simulator Control Variables With The GUI e Value Range 0 1 e Default off 0 ToggleMaxintValues This variable sets the maximum number of VHDL integer values to record with toggle coverage e Value Range positive integer e Default 100 TranscriptFile This variable specifies a file for saving command transcript You can specify environment variables in the pathname e Value Range any valid filename Default transcript UnbufferedOutput This variable controls VHDL and Verilog files open for write e Value Range 0 buffered 1 unbuffered e Default 0 UseCsupV2 Applies only to HP UX 11 00 and when you compiled FLI PLI VPI C code with the AA option for aCC 338 ModelSim User s Manual v6 2g February 2007 Simulator Variables Simulator Control Variables This variable instructs vsim to use usr lib libCsup v2 sl for shared object loading e Value Range 0 1 e Default off 0 UserTimeUnit This variable specifies scaling for the Wave window and the default time units to use for commands such as force and run You should generally set this variable to default in which case it takes the value of the Resolution variable e Value Range fs ps ns us ms sec or default e De
326. ile types used by ModelSim e g DO WLF INI MPF PDF etc Installation Directory Pathnames When referring to installation paths this manual uses modeltech as a generic representation of the installation directory for all versions of ModelSim The actual installation directory on your system may contain version information ModelSim User s Manual v6 2g 31 February 2007 Introduction Installation Directory Pathnames 32 ModelSim User s Manual v6 2g February 2007 Chapter 2 Simulator Windows ModelSim s graphical user interface GUI consists of various windows that give access to parts of your design and numerous debugging tools Some of the windows display as panes within the ModelSim Main window and some display as windows in the Multiple Document Interface MDI frame Figure 2 1 Graphical User Interface sQm eesim ssunuimPxga c I 7 ROS x m adi S Qe eB LETS ou eji be o zx SEL sA 52 019 S A EBD qd XOX Workspace ON Hix rm 1e ie te std logic 1164 standard M Time 2820 ne Iteration Instance top p VSIM 7 LA Transcrit bl Now 2840 ns Delta 1 sim top Limited Visibility Region rego ns to 2040 ns P ModelSim User s Manual v6 2g 33 February 2007 Simulator Windows The following table summarizes all of the available windows and panes Table 2 1 GUI Windows and Panes Window pane name Description More details Main central GUI access point M
327. ilog missing declaration 322 Tcl_init error 360 VSIM license lost 362 escaped identifiers 161 event order in Verilog simulation 154 event queues 154 event watching commands placement of 307 events tracing 230 exit codes 357 expand ModelSim User s Manual v6 2g February 2007 ABCDEFGHIJKLMNOPQRSTUVWXYZ environment variables 313 expand net 227 Explicit ini file variable 324 export TFs in DPI 359 Expression Builder 200 configuring a List trigger with 219 saving expressions to Tcl variable 201 Lam F8 function key 406 Fatal ini file variable 345 File compression VCD tasks 282 file I O TextIO package 118 file line breakpoints 67 files modelsim 419 files grouping for compile 90 filter processes 47 filtering signals in Objects window 60 folders in projects 92 fonts controlling in X sessions 36 scaling 35 force command defaults 348 format file 213 Wave window 213 FPGA libraries importing 107 Function call debugging 48 functions virtual 185 G generate statements Veilog 150 GenerateFormat ini file variable 333 GenerateLooplterationMax ini file variable 321 GenerateRecursionDepthMax ini variable 321 get resolution VHDL function 125 global visibility PLI FLI shared objects 387 ModelSim User s Manual v6 29 February 2007 GLOBALPATHPULSE matching to specify path delays 269 GlobalSharedObjectsList ini file variable 333 graphic interface
328. ilog PLI VPI DPI This appendix describes the ModelSim implementation of the Verilog PLI Programming Language Interface VPI Verilog Procedural Interface and SystemVerilog DPI Direct Programming Interface These three interfaces provide a mechanism for defining tasks and functions that communicate with the simulator through a C procedural interface There are many third party applications available that interface to Verilog simulators through the PLI see Third Party PLI Applications In addition you may write your own PLI VPI DPI applications Implementation Information ModelSim Verilog implements the PLI as defined in the IEEE Std 1364 2001 with the exception of the acc handle datapath routine We did not implement the acc handle datapath routine because the information it returns is more appropriate for a static timing analysis tool The VPI is partially implemented as defined in the IEEE Std 1364 2005 The list of currently supported functionality can be found in the following file install dir modeltech docs technotes Verilog VPl note ModelSim SystemVerilog implements DPI as defined in IEEE Std P1800 2005 The IEEE Std 1364 is the reference that defines the usage of the PLI VPI routines and the IEEE Std P1800 2005 Language Reference Manual LRM defines the usage of DPI routines This manual describes only the details of using the PLI VPI DPI with ModelSim Verilog and SystemVerilog g Compiler Support for use with PLI
329. ilog PLI VPI DPI Debugging PLI VPI DPI Application Code The tracing operations will provide tracing during all user foreign code calls including PLI VPI user tasks and functions calltf checktf sizetf and misctf routines and Verilog VCL callbacks Debugging PLI VPI DPI Application Code In order to debug your PLI VPI DPI application code in a debugger you must first 1 Compile the application code with debugging information using the g option and without optimizations for example don t use the O option 2 Load vsim into a debugger Even though vsim is stripped most debuggers will still execute it You can invoke the debugger directly on vsimk the simulation kernel where your application code is loaded for example ddd which vsimk or you can attach the debugger to an already running vsim process In the second case you must attach to the PID for vsimk and you must specify the full path to the vsimk executable for example gdb MTI_HOME sunos5 vsimk 1234 On Solaris AIX and Linux systems you can use either gdb or ddd On HP UX systems you can use the wdb debugger from HP You will need version 1 2 or later 3 Setanentry point using breakpoint Since initially the debugger recognizes only vsim s PLI VPI DPI function symbols when invoking the debugger directly on vsim you need to place a breakpoint in the first PLI VPI DPI function that is called by your application code An easy way to set an entry point is
330. in This process is repeated until all references are resolved or until no new unresolved references are found Source libraries are searched in the order they appear on the command line v lt filename gt y lt directory gt libext lt suffix gt librescan nolibcell R lt simargs gt Verilog XL uselib Compiler Directive The uselib compiler directive is an alternative source library management scheme to the v y and libext compiler arguments It has the advantage that a design may reference different modules having the same name You compile designs that contain uselib directive statements using the compile_uselibs argument described below to vlog The syntax for the uselib directive is uselib library references where library reference can be one or more of the following ModelSim User s Manual v6 29 147 February 2007 Verilog and SystemVerilog Simulation Compiling Verilog Files e dir library directory which is equivalent to the command line argument y library directory file library file which is equivalent to the command line argument v library file e libext file extension which is equivalent to the command line argument libext lt file_extension gt lib library name which references a library for instantiated objects This behaves similarly to a LIBRARY USE clause in VHDL You must ensure the correct mappings are set up if the library does not exist in the
331. in a Verilog design must be compiled into one or more libraries One library is usually sufficient for a simple design but you may want to organize your modules into various libraries for a complex design If your design uses different modules having the same name then you are required to put those modules in different libraries because design unit names must be unique within a library The following is an example of how you may organize your ASIC cells into one library and the rest of your design into another vlib work vlib asiclib vlog work asiclib and2 v or2 v Compiling module and2 Compiling module or2 Top level modules o vlog top v Compiling module top Top level modules top Note that the first compilation uses the work asiclib argument to instruct the compiler to place the results in the asiclib library rather than the default work library Library Search Rules for vlog Since instantiation bindings are not determined at compile time you must instruct the simulator to search your libraries when loading the design The top level modules are loaded from the library named work unless you prefix the modules with the library option All other Verilog instantiations are resolved in the following order e Search libraries specified with Lf arguments in the order they appear on the command line e Search the library specified in the Verilog XL uselib Compiler Directive section e Sear
332. ing Exceed to access an HP machine from Windows NT it is recommended that you run vsim in command line or batch mode because your NT machine may hang if you run vsim in GUI mode Click on the go button or use F5 or the go command to execute vsim in wdb You might also see a warning about not finding dld flags in the object file This warning can be ignored You should see a list of libraries loaded into the debugger It should include the library for your PLI VPI DPI application Alternatively you can use share to load only a single library ModelSim User s Manual v6 2g 401 February 2007 Verilog PLI VPI DPI Debugging PLI VPI DPI Application Code 402 ModelSim User s Manual v6 29 February 2007 Appendix E Command and Keyboard Shortcuts This appendix is a collection of the keyboard and command shortcuts available in the ModelSim GUI Command Shortcuts e You may abbreviate command syntax but there s a catch the minimum number of characters required to execute a command are those that make it unique Remember as we add new commands some of the old shortcuts may not work For this reason ModelSim does not allow command name abbreviations in macro files This minimizes your need to update macro files as new commands are added e Multiple commands may be entered on one line if they are separated by semi colons For example vlog nodebug ports level3 v level2 v vlog nodebug top v The return value of the last
333. ing situations exists e any file within the design contains the sv file extension e the sv argument is used with the vlog command 140 ModelSim User s Manual v6 2g February 2007 Verilog and SystemVerilog Simulation Compiling Verilog Files e the Use System Verilog option is selected in the Verilog tab of the Compiler Options dialog Access this dialog by selecting Compile Compile Options from the Main window menu bar Figure 6 1 Selecting Use System Verilog Compile Option VHDL Verilog Coverage l SystemC m Language Syntax C Default C Use Verilog 1995 C Use Verilog 2001 Use SystemVerilog Here are two examples of the vlog command that will enable SystemVerilog features and keywords in ModelSim vlog testbench sv top v memory v cache v vlog sv testbench v proc v In the first example the sv extension for testbench automatically instructs ModelSim to parse System Verilog keywords The sv option used in the second example enables SystemVerilog features and keywords Though a primary goal of the SystemVerilog standardization efforts has been to ensure full backward compatibility with the Verilog standard there is an issue with keywords System Verilog adds several new keywords to the Verilog language see Table B 1 in Appendix B of the P1800 SystemVerilog standard If your design uses one of these keywords as a regular identifier for a variable module task function etc your design will not
334. ing the virtual region command Virtual Types User defined enumerated types can be defined in order to display signal bit sequences as meaningful alphanumeric names The virtual type is then used in a type conversion expression to convert a signal to values of the new type When the converted signal is displayed in any of the windows the value will be displayed as the enumeration string corresponding to the value of the original signal Virtual types are created using the virtual type command 186 ModelSim User s Manual v6 2g February 2007 Chapter 8 Waveform Analysis When your simulation finishes you will often want to analyze waveforms to assess and debug your design Designers typically use the Wave window for waveform analysis However you can also look at waveform data in a textual format in the List window To analyze waveforms in ModelSim follow these steps 1 Compile your files 2 Load your design 3 Add objects to the Wave or List window add wave object name add list object name 4 Run the design Objects You Can View The list below identifies the types of objects can be viewed in the Wave or List window e VHDL objects indicated by dark blue diamond in the Wave window signals aliases process variables and shared variables e Verilog objects indicated by light blue diamond in the Wave window nets registers variables and named events e Virtual objects indicated by an orange d
335. ini file This option was added because some utility packages print a huge number of warnings vsim IgnoreNote 1 IgnoreWarning 1 IgnoreError 1 IgnoreFailure 1 Turning off Warnings from Arithmetic Packages You can disable warnings from the Synopsys and numeric standard packages by adding the following lines to the vsim section of the modelsim ini file vsim NumericStdNoWarnings 1 StdArithNoWarnings 1 ModelSim User s Manual v6 2g 347 February 2007 Simulator Variables Simulator Control Variables Force Command Defaults The force command has freeze drive and deposit options When none of these is specified then freeze is assumed for unresolved signals and drive is assumed for resolved signals But if you prefer freeze as the default for both resolved and unresolved signals you can change the defaults in the modelsim ini file vsim Default Force Kind The choices are freeze drive or deposit DefaultForceKind freeze Restart Command Defaults The restart command has force nobreakpoint nofcovers nolist nolog and nowave options You can set any of these as defaults by entering the following line in the modelsim ini file DefaultRestartOptions lt options gt where options can be one or more of force nobreakpoint nofcovers nolist nolog and nowave Example DefaultRestartOptions nolog force VHDL Standard You can specify which version of the 1076 S
336. ini file if it is writable and affect the current session as well as all future sessions If the file is read only the changes affect only the current session The Runtime Options dialog is accessible by selecting Simulate Runtime Options in the Main window The dialog contains three tabs Defaults Assertions and WLF Files The Defaults tab includes these options Figure A 1 Runtime Options Dialog Defaults Tab Runtime Options E Defaults Assertions WLF Files Default Radix Suppress Wamings Symbolic C Binary C Octal Default Run C Decimal p C Unsigned iy C Hexadecimal CILE C ASCII 500 From Synopsys Packages FromlIEEE Numeric Std Packages Default Force Type C Freeze C Drive C Deposit Default based on type e Default Radix Sets the default radix for the current simulation run You can also use the radix command to set the same temporary default The chosen radix is used for all commands force examine change are examples and for displayed values in the Objects Locals Dataflow List and Wave windows The corresponding modelsim ini variable is DefaultRadix e Suppress Warnings o Selecting From Synopsys Packages suppresses warnings generated within the accelerated Synopsys std_arith packages The corresponding modelsim ini variable is StdArithNoWarnings o Selecting From IEEE Numeric Std Packages suppresses warnings generated within the accelerated numeric_std an
337. int lt filename gt fdumpall ved files lt filename gt fdumpfile ved flush lt filename gt fdumpflush ved limit lt filename gt fdumplimit ved off lt filename gt fdumpoff ved on lt filename gt fdumpon Compressing Files with VCD Tasks ModelSim can produce compressed VCD files using the gzip compression algorithm Since we cannot change the syntax of the system tasks we act on the extension of the output file name If you specify a gz extension on the filename ModelSim will compress the output VCD File from Source To Output The following example shows the VHDL source a set of simulator commands and the resulting VCD output VHDL Source Code The design is a simple shifter device represented by the following VHDL source code 282 ModelSim User s Manual v6 2g February 2007 Value Change Dump VCD Files VCD File from Source To Output library IEEE use IEEE STD LOGIC 1164 a11 entity SHIFTER MOD is port CLK RESET data in IN STD LOGIC Q INOUT STD LOGIC VECTOR 8 downto 0 END SHIFTER MOD architecture RTL of SHIFTER MOD is begin process CLK RESET begin if RESET 1 then Q lt others gt 0 elsif CLK event and CLK 1 then Q lt Q Q left 1 downto 0 amp data in end if end process end VCD Simulator Commands At simulator time zero the designer executes the following commands vcd file output vcd vcd add r force rese
338. ion of the port This is called a Module Input Port Delay MIPD All primitives specify path delays and specify timing checks connected to the original port are reconnected to the new MIPD net 268 ModelSim User s Manual v6 2g February 2007 Standard Delay Format SDF Timing Annotation sdf annotate e PATHPULSE and GLOBALPATHPULSE are matched to specify path delays Table 11 4 Matching SDF PATHPULSE and GLOBALPATHPULSE to Verilog PATHPULSE a y 5 10 a 2 y 20 GLOBALPATHPULSE a y 30 60 a gt y 0 If the input and output ports are omitted in the SDF then all path delays are matched in the cell e DEVICE is matched to primitives or specify path delays Table 11 5 Matching SDF DEVICE to Verilog DEVICE y 5 and ul y a b DEVICE y 5 a gt y 0 b gt y 0 If the SDF cell instance is a primitive instance then that primitive s delay is annotated If it is a module instance then all specify path delays are annotated that drive the output port specified in the DEVICE construct all path delays are annotated if the output port is omitted If the module contains no path delays then all primitives that drive the specified output port are annotated or all primitives that drive any output port if the output port is omitted SETUP is matched to setup and setuphold Table 11 6 Matching SDF SETUP to Verilog SETUP d posedge clk 5 setup d posedge clk 0 SET
339. ion units present in the current compilation Verilog XL Compatible Compiler Arguments The compiler arguments listed below are equivalent to Verilog XL arguments and may ease the porting of a design to ModelSim See the vlog command for a description of each argument 146 ModelSim User s Manual v6 2g February 2007 Verilog and SystemVerilog Simulation Compiling Verilog Files tdefine t macro name macro text tdelay mode distributed tdelay mode path delay mode unit tdelay mode zero f filename tincdirt lt directory gt mindelays maxdelays nowarn lt mnemonic gt ttypdelays Arguments Supporting Source Libraries The compiler arguments listed below support source libraries in the same manner as Verilog XL See the vlog command for a description of each argument Note that these source libraries are very different from the libraries that the ModelSim compiler uses to store compilation results You may find it convenient to use these arguments if you are porting a design to ModelSim or if you are familiar with these arguments and prefer to use them Source libraries are searched after the source files on the command line are compiled If there are any unresolved references to modules or UDPs then the compiler searches the source libraries to satisfy them The modules compiled from source libraries may in turn have additional unresolved references that cause the source libraries to be searched aga
340. iple levels of folders and sub folders However no actual directories are created via the file system the folders are present only within the project file Adding a Folder To add a folder to your project select Project gt Add to Project gt Folder or right click in the Project tab and select Add to Project gt Folder Figure 3 15 92 ModelSim User s Manual v6 2g February 2007 Projects Organizing Projects with Folders Figure 3 15 Add Folder Dialog Folder Name Design Files Folder Location Top Level vi OK Cancel Specify the Folder Name the location for the folder and click OK The folder will be displayed in the Project tab You use the folders when you add new objects to the project For example when you add a file you can select which folder to place it in Figure 3 16 Specifying a Project Folder Add file to Project x File Name counter tcounter vy Browse Add file as type Folder defaut w veniog files vi Reference from current location C Copy to project directory OK Cancel If you want to move a file into a folder later on you can do so using the Properties dialog for the file Simply right click on the filename in the Project tab and select Properties from the context menu that appears This will open the Project Compiler Settings Dialog Figure 3 17 Use the Place in Folder field to specify a folder Specify a folder here ModelSim Use
341. isplay The frame allows multiple windows to be displayed simultaneously as shown below A tab appears for each window ModelSim User s Manual v6 2g 41 February 2007 Simulator Windows Organizing Windows with Tab Groups Figure 2 4 Tabs in the MDI Frame Object name Copyright Mentor Graphics Corporation 2004 2 3 f f Bll Rights Reserved 4 5 THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPE 6 MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS 7 8 define clk pd 100 9 10 timescale Ins lns 11 juodule ram tb 12 reg we 13 reg clk l4 reg 19 0 addr 15 reg 3 0 inaddr l6 reg 3 0 outaddr 1 reg 31 0 data in 18 19 wire 7 0 data spl E rye as 7 ui v BES RGSS TE pa usse ent ro sr rom ven bem 7 EE Window tabs The object name is displayed in the title bar at the top of the window You can switch between the windows by clicking on a tab Organizing Windows with Tab Groups The MDI can quickly become unwieldy if many windows are open You can create tab groups to help organize the windows A tab group is a collection of tabs that are separated from other groups of tabs Figure 2 5 shows how the collection of files in Figure 2 4 could be organized into two tab groups 42 ModelSim User s Manual v6 29 February 2007 Simulator Windows Navigating in the Main Window Figure 2 5 Organizing Files
342. ither use the middle mouse button or enter Zoom Mode by selecting View Zoom and then use the left mouse button Four zoom options are possible by clicking and dragging in different directions e Down Right Zoom Area In e Up Right Zoom Out zoom amount is displayed at the mouse cursor e Down Left Zoom Selected e Up Left Zoom Full The zoom amount is displayed at the mouse cursor zoom operation must be more than 10 pixels to activate Panning with the Mouse You can pan with the mouse in two ways 1 enter Pan Mode by selecting View Pan and then drag with the left mouse button to move the design 2 hold down the lt Ctrl gt key and drag with the middle mouse button to move the design Tracing Events Causality One of the most useful features of the Dataflow window is tracing an event to see the cause of an unexpected output This feature uses the Dataflow window s embedded wave viewer see The Embedded Wave Viewer for more details In short you identify an output of interest in the Dataflow pane and then use time cursors in the wave viewer pane to identify events that contribute to the output The process for tracing events is as follows 1 Log all signals before starting the simulation add log r 2 After running a simulation for some period of time open the Dataflow window and the wave viewer pane 3 Adda process or signal of interest into the Dataflow window if adding a signal find its driving
343. itial She Ilo endmodule Compile the PLI code for the Solaris operating system oe oe ile the Veril vlib work Com oe oe TO Simulate the desi o vsim c pli og code vlog hello v gn cc c I install dir modeltech include hello c ld G Bsymbolic o hello sl hello o hello sl hello Loading work Hi there VSIM 2 quit VPI Example The following example is a trivial but complete VPI application A general VPI example can be found in install dir modeltech examples verilog vpi 388 hello c static PLI INT vpi printf return 0 Loading hel VSIM 1 run all hello lo sl include vpi user h 32 hello PLI BYTE8 param Hello world n void RegisterMyTfs void S vpi systf data systf data vpiHandle systf handle systf data systf data systf data systf data systf data systf data systf data systf_handl vpi_free_ob type tfname calltf compiletf sizetf user data vpiSysTask sysfunctype vpiSysTask Shello hello 0 0 0 e vpi register systf amp systf data ject systf handle ModelSim User s Manual v6 2g February 2007 Verilog PLIAVPI DP DPI Example void vlog startup routines O RegisterMyTfs 0 hello v module hello initial Shello endmodule Compile the VPI code for the Solaris operating system gcc c I
344. its integer 12 data bits integer 32 port add in in std ulogic vector add bits 1 downto 0 data in in std ulogic vector data bits 1 downto 0 data out out std ulogic vector data bits 1 downto 0 cs mwrite in std ulogic do init in std ulogio subtype word is std ulogic vector data bits 1 downto 0 constant nwords integer 2 add bits type ram type is array 0 to nwords 1 of word end architecture style 93 of memory is shared variable ram ram type begin memory process cs variable address natural begin if rising edge cs then address sulv to natural add in if mwrite 1 then ram address data in end if data out lt ram address end if end process memory illustrates a second process using the shared variable initialize process do init variable address natural begin if rising edge do init then for address in 0 to nwords 1 loop ram address data in end loop end if end process initialize end architecture style 93 architecture style 87 of memory is begin memory process cs variable ram ram type variable address natural ModelSim User s Manual v6 2g 129 February 2007 VHDL Simulation Modeling Memory begin if rising edge cs then address sulv to natural add in if mwrite 1 then ram address data in end if data out lt ram address end if end process end style 87 archit
345. its 1 downto 0 others gt 0 variable tempn natural n begin for i in x reverse range loop if tempn mod 2 1 then x 1 2 TL end if tempn tempn 2 end loop return x end natural to sulv end conversions ModelSim User s Manual v6 29 February 2007 131 VHDL Simulation Modeling Memory VHDLO2 example Source Sp syn ram protected vhd Component VHDL synchronous single port RAM Remarks Various VHDL examples random access memory RAM LIBRARY ieee USE ieee std logic 1164 ALL USE ieee numerioc std ALL ENTITY sp syn ram protected IS GENERIC data width positive 8 addr width positive 3 PORT inclk IN std logic outclk IN std logic we IN std logic addr IN unsigned addr width 1 DOWNTO 0 data in IN std logic vector data width 1 DOWNTO 0 data out OUT std logic vector data width 1 DOWNTO 0 END sp syn ram protecteg ARCHITECTURE intarch OF sp syn ram protected IS TYPE mem type IS PROTECTED PROCEDURE write data IN std logic vector data width 1 downto 0 addr IN unsigned addr width 1 DOWNTO 0 IMPURE FUNCTION read addr IN unsigned addr width 1 DOWNTO 0 RETURN std logic vector END PROTECTED mem type TYPE mem type IS PROTECTED BODY TYPE mem array IS ARRAY 0 TO 2 addr width 1 OF std logic vector data width 1 DOWNTO 0 VARIABLE mem mem array PROCEDURE write data IN std logic vector data wid
346. k2 lt clk process rst clk begin if rst 0 then s0 lt 0 elsif clk event and clk 1 then s0 lt inp end if end process process rst clk2 begin if rst 0 then sl lt 1013 elsif clk2 event and clk2 2 1 then sl lt s0 end if end process In this example you have two synchronous processes one triggered with c k and the other with clk2 To your surprise the signals change in the c k2 process on the same edge as they are set in the clk process As a result the value of inp appears at s rather than 50 During simulation an event on clk occurs from the testbench From this event ModelSim performs the clk2 lt clk assignment and the process which is sensitive to c k Before advancing the simulation time ModelSim finds that the process sensitive to c k2 can also be run Since there are no delays present the effect is that the value of inp appears at s in the same simulation cycle In order to get the expected results you must do one of the following e Insert a delay at every output e Make certain to use the same clock e Insert a delta delay To insert a delta delay you would modify the code like this ModelSim User s Manual v6 2g 117 February 2007 VHDL Simulation Using the TextlO Package process rst clk begin if rst 0 then s0 lt 0 elsif clk event and clk 1 then s0 lt inp sOQ_delayed lt s0 end if end process process rst clk2 begin if r
347. l v6 29 207 February 2007 Waveform Analysis Wave Groups Figure 8 16 Splitting Wave Window Panes Mwave deraue T File Edit View Add Format Tools Window sim test_sm dat 2222222222222222222 fH LLL H sim test sm addr 0000110011 OOO OTRO COR B 0 1000 7000 1700 sim test sm loop KXXRKKRRKKRRKKRXKRER sim test_sm i x sim test_sm rd_ St gold test_sm clk 1 gold test sm out gold test sm dat zzzzzzzzzzzzzzzzzzz gold test sm addr 0000110011 gold test sm loop XXKKRRXKKKRRXKKKRRE gold test sm i x gold test sm td SH Cursor 1 D ps Eu 41 jJ AKT 50400 ps to 565800 ps Now 750 ns Delta 2 The Active Split The active split is denoted with a solid white bar to the left of the signal names The active split becomes the target for objects added to the Wave window Wave Groups Wave groups are a wave window specific container object for creating arbitrary groups of items A wave group may contain 0 1 or many items The command line as well as drag and drop may be used to add or remove items from a group Groups themselves may be dragged around the wave window or to another wave window Currently groups may not be nested Creating a Wave Group There are two ways to create a wave group 1 Use the Tools gt Group menu selection 208 ModelSim User s Manual v6 2g February 2007 Waveform Analysis Wave Groups a Selecta set of signals
348. l name to a design library The format for command line entry is vmap logical name directory pathname This command sets the mapping between a logical library name and a directory Step 2 Compiling the Design vlog vcom sccom Designs are compiled with one of the three language compilers Compiling Verilog vlog ModelSim s compiler for the Verilog modules in your design is vlog Verilog files may be compiled in any order as they are not order dependent See Compiling Verilog Files for details Compiling VHDL vcom ModelSim s compiler for VHDL design units is vcom VHDL files must be compiled according to the design requirements of the design Projects may assist you in determining the compile order for more information see Auto Generating Compile Order See Compiling VHDL Files for details on VHDL compilation ModelSim User s Manual v6 2g 25 February 2007 Introduction Basic Steps for Simulation Step 3 Loading the Design for Simulation vsim topLevelModule Your design is ready for simulation after it has been compiled You may then invoke vsim with the names of the top level modules many designs contain only one top level module For example if your top level modules are testbench and globals then invoke the simulator as follows vsim testbench globals After the simulator loads the top level modules it iteratively loads the instantiated modules and UDPs in the design hierarchy linking
349. l part of an association element is in the form of a conversion function call or a type conversion and the formal is of an unconstrained array type the return type of the conversion function type mark of the type conversion must be of a constrained array subtype We relax this with a warning unless pedanticerrors is present when it becomes an error e OTHERS choice in a record aggregate must refer to at least one record element e Inan array aggregate of an array type whose element subtype is itself an array all expressions in the array aggregate must have the same index constraint which is the element s index constraint No warning is issued the presence of pedanticerrors will produce an error e Non static choice in an array aggregate must be the only choice in the only element association of the aggregate e The range constraint of a scalar subtype indication must have bounds both of the same type as the type mark of the subtype indication e The index constraint of an array subtype indication must have index ranges each of whose both bounds must be of the same type as the corresponding index subtype e When compiling VHDL 1987 various VHDL 1993 and 2002 syntax is allowed Use pedanticerrors to force strict compliance Warnings are all level 10 ModelSim User s Manual v6 2g 363 February 2007 Error and Warning Messages Enforcing Strict 1076 Compliance 364 ModelSim User s Manual v6 2g February 2007 Appendix D Ver
350. l signals 184 virtual types 186 virtual region command 186 virtual regions reconstruct RTL hierarchy 186 virtual save command 185 virtual signal command 184 439 ABCDEFGH I virtual signals reconstruct RTL level design busses 184 reconstruct the original RTL hierarchy 184 virtual hide command 184 visibility of declarations in unit 145 VITAL compiling and simulating with accelerated VITAL packages 124 disabling optimizations for debugging 124 specification and source code 123 VITAL packages 124 vital95 ini file variable 321 vlog95compat ini file variable 323 VPI registering applications 367 VPUPLI 173 VPI PLI DPI 365 compiling and linking C applications 373 compiling and linking C applications 380 VSIM license lost 362 VSOUT temp file 319 W WarnConstantChange ini file variable 339 Warning ini file variable 345 warnings empty port name 359 exit codes 357 getting more information 355 messages long description 355 metavalue detected 360 severity level changing 356 suppressing VCOM warning messages 356 suppressing VLOG warning messages 357 suppressing VSIM warning messages 357 Tcl initialization error 2 360 too few port connections 361 turning off warnings from arithmetic packages 347 waiting for lock 359 watching a signal value 70 wave groups 208 add items to existing 210 creating 208 440 JKLMNOPQRSTUVWXYZ deleting 210 drag from Wave to Lis
351. lay ModelSim User s Manual v6 2g 35 February 2007 Simulator Windows Main Window resolution or the hardware monitor or video card The font scaling applies to Windows and UNIX operating systems On UNIX systems the font scaling is stored based on the SDISPLAY environment variable Controlling Fonts in an X session When executed via an X session e g Exceed VNC ModelSim uses font definitions from the Xdefaults file To ensure that the fonts look correct create a Xdefaults file with the following lines vsim Font adobe courier medium r normal 120 vsim SystemFont adobe courier medium r normal 120 vsim StandardFont adobe courier medium r normal 120 vsim MenuFont adobe courier medium r normal 120 x xoxo ox xo ox ox ox Alternatively you can choose a different font Use the program xlsfonts to identify which fonts are available on your system Also the following command can be used to update the X resources if you make changes to the Xdefaults and wish to use those changes on a UNIX machine xrdb merge Xdefaults Main Window The primary access point in the ModelSim GUI is called the Main window It provides convenient access to design libraries and objects source files debugging commands simulation status messages etc When you load a design or bring up debugging tools ModelSim adds panes or opens windows appropriate for your debugging envir
352. lay design objects in a hierarchical tree format e The Transcript pane tracks command history and messages and provides a command line interface where you can enter ModelSim commands e The Objects pane displays design objects such as signals nets generics etc in the current design scope Workspace The Workspace provides convenient access to projects libraries design files compiled design units simulation dataset structures and Waveform Comparison objects It can be hidden or displayed by selecting View Windows Workspace Main window The Workspace can display the types of tabs listed below ModelSim User s Manual v6 2g 37 February 2007 Simulator Windows Main Window Project tab Shows all files that are included in the open project Refer to Projects for details Library tab Shows design libraries and compiled design units To update the current view of the library select a library and then Right click Update See Managing Library Contents for details on library management Structure tabs Shows a hierarchical view of the active simulation and any open datasets There is one tab for the current simulation named sim and one tab for each open dataset See Viewing Dataset Structure for details An entry is created by each object within the design When you select a region in a structure tab it becomes the current region and is highlighted The Source Window and Objects Pane change dynamically to ref
353. lay is non zero if the setup limit is negative zero otherwise The delayed data argument is a net that is continuously assigned the value of the net specified in the data event The delay is non zero if the hold limit is negative zero otherwise The delayed clk and delayed data arguments are provided to ease the modeling of devices that may have negative timing constraints The model s logic should reference the delayed clk and delayed data nets in place of the normal clk and data nets This ensures that the correct data is latched in the presence of negative constraints The simulator automatically calculates the delays for delayed clk and delayed data such that the correct data is latched as long as a timing constraint has not been violated See Negative Timing Check Limits for more details Unsupported Verilog XL System Tasks The following system tasks are Verilog XL system tasks that are not implemented in ModelSim Verilog but have equivalent simulator commands 170 input filename This system task reads commands from the specified filename The equivalent simulator command is do lt filename gt list hierarchical_name This system task lists the source code for the specified scope The equivalent functionality is provided by selecting a module in the structure pane of the Workspace The corresponding source code is displayed in a Source window reset This system task resets the simulation back to its time 0 state
354. le sig transitions to a 1 library ieee library modelsim lib use ieee std logic 1164 a11 use modelsim entity top end is ib util arll architecture only of top is signal top_sigl begin spy_process begin std logic gt process init signal spy top uut insti sigl1 top top sig1 1 1 wait end process spy process Spy enabl begin e disabl if enable sig enabl e signal lseif e process enable sig 1 then _spy top uut inst1 sigl top top_sigi 0 246 enable_sig 0 ModelSim User s Manual v6 2g February 2007 Signal Spy init signal spy disable signal spy top uut instl sigl1 top top sigl 0 end if end process spy enable disable end ModelSim User s Manual v6 2g 247 February 2007 Signal Spy signal force signal force The signal force procedure forces the value specified onto an existing VHDL signal or Verilog register or net called the dest object This allows you to force signals registers or nets at any level of the design hierarchy from within a VHDL architecture e g a testbench A signal force works the same as the force command with the exception that you cannot issue a repeating force The force will remain on the signal until a signal release a force or release command or a subsequent signal force is issued Signal force can be called concurrently or sequentially in a process
355. lect the information for the current region This feature provides a useful method for finding the source code for a selected region because the system keeps track of the pathname where the source is located and displays it automatically without the need for you to provide the pathname Also when you select a region in the structure pane the Active Processes Pane is updated The Active Processes window will in turn update the Locals Pane Objects can be dragged from the structure tabs to the Dataflow List and Wave windows You can toggle the display of processes by clicking in a Structure tab and selecting View Filter Processes You can also control implicit wire processes using a preference variable By default Structure tabs suppress the display of implicit wire processes To enable the display of implicit wire processes set PrefMain HideImplicitWires to 0 select Tools gt Edit Preferences By Name tab and expand the Main object Files tab Shows the source files for the loaded design You can disable the display of this tab by setting the PrefMain ShowFilePane preference variable to 0 See Simulator GUI Preferences for information on setting preference variables Memories tab Shows a hierarchical list of all memories in the design To display this tab select View Windows Memory When you select a memory on the tab a memory contents page opens in the MDI frame See Memory Panes Transcript The Transcript
356. ler simulator and various other functions Simulator State Variables Variables that provide feedback on the state of the current simulation Variable Settings Report The report command returns a list of current settings for either the simulator state or simulator control variables Use the following commands at either the ModelSim or VSIM prompt report simulator state report simulator control Environment Variables Environment Variable Expansion The shell commands vcom vlog vsim and vmap no longer expand environment variables in filename arguments and options Instead variables should be expanded by the shell beforehand in the usual manner The f option that most of these commands support now performs environment variable expansion throughout the file Environment variable expansion is still performed in the following places Pathname and other values in the modelsim ini file Strings used as file pathnames in VHDL and Verilog VHDL Foreign attributes The PLIOBJS environment variable may contain a path that has an environment variable Verilog uselib file and dir directives ModelSim User s Manual v6 2g 313 February 2007 Simulator Variables Environment Variables e Anywhere in the contents of a f file The recommended method for using flexible pathnames is to make use of the MGC Location Map system see Using Location Mapping When this is used then pathnames stored in libraries and project files mpf
357. les specifying with location maps 353 source highlighting customizing 68 source libraries arguments supporting 147 Source window 62 colorization 68 tab stops in 68 see also windows Source window specify path delays matching to DEVICE construct 269 matching to GLOBALPATHPULSE construct 269 matching to IOPATH statements 268 matching to PATHPULSE construct 269 standards supported 28 startup environment variables access during 420 files accessed during 419 macro in the modelsim ini file 338 macros 347 startup macro in command line mode 27 using a startup file 347 Startup ini file variable 338 state variables 349 status bar Main window 44 Status field Project tab 88 ModelSim User s Manual v6 2g February 2007 ABCDEFGHI std ini file variable 320 std arith package disabling warning messages 347 std developerskit ini file variable 320 std logic arith package 106 std logic signed package 106 std logic textio 106 std logic unsigned package 106 StdArithNoWarnings ini file variable 338 STDOUT environment variable 317 steps for simulation overview 23 subprogram inlining 110 subprogram write is ambiguous error fixing 120 Suppress ini file variable 345 sv std ini file variable 320 symbol mapping Dataflow window 235 symbolic link to design libraries UNIX 104 synopsys ini file variable 320 Synopsys libraries 106 syntax highlighting 68 synthesis rule compliance checking
358. lies to VHDL 2002 only ModelSim User s Manual v6 2g February 2007 Error and Warning Messages Enforcing Strict 1076 Compliance e Expressions evaluated during elaboration cannot depend on signal values Warning is level 9 e Non standard use of output port s in PSL expression Warning is level 11 e Non standard use of linkage port s in PSL expression Warning is level 11 e Type mark of type conversion expression must be a named type or subtype it can t have a constraint on it e When the actual in a PORT MAP association is an expression it must be a globally static expression The port must also be of mode IN e The expression in the CASE and selected signal assignment statements must follow the rules given in 8 8 of the LRM In certain cases we can relax these rules but pedanticerrors forces strict compliance A CASE choice expression must be a locally static expression We allow it to be only globally static but pedanticerrors will check that it is locally static Same rule for selected signal assignment statement choices Warning level is 8 e When making a default binding for a component instantiation ModelSim s non standard search rules found a matching entity VHDL 2002 LRM Section 5 2 2 spells out the standard search rules Warning level is 1 e Both FOR GENERATE and IF GENERATE expressions must be globally static We allow non static expressions unless pedanticerrors is present e When the actua
359. log objects indicated by a light blue diamond nets registers variables and named events Virtual objects indicated by an orange diamond virtual signals buses and functions see Virtual Objects for more information The data in the object values pane is very similar to the Objects window except that the values change dynamically whenever a cursor in the waveform pane is moved At the bottom of the waveform pane you can see a time line tick marks and the time value of each cursor s position As you click and drag to move a cursor the time value at the cursor location is updated at the bottom of the cursor You can resize the window panes by clicking on the bar between them and dragging the bar to a new location 74 ModelSim User s Manual v6 2g February 2007 Simulator Windows Wave Window Waveform and signal name formatting are easily changed via the Format menu You can reuse any formatting changes you make by saving a Wave window format file see Saving the Window Format Wave Window Panes The sections below describe the various Wave window panes Pathname Pane The pathname pane displays signal pathnames Signals can be displayed with full pathnames as shown here or with only the leaf element displayed You can increase the size of the pane by clicking and dragging on the right border The selected signal is highlighted The white bar along the left margin indicates the selected dataset see Splitti
360. lt install_dir gt modeltech include c app c Id G Bsymbolic app o o app so 32 bit HP700 Platform A shared library is created by creating object files that contain position independent code use the z or fPIC compiler argument and by linking as a shared library use the b linker argument If your PLI VPI DPI application uses anything from a system library you ll need to specify that library when you link your PLI VPI DPI application For example to use the standard C library specify Ic to the Id command e gcc compiler gcc c fPIC I lt install_dir gt modeltech include app c Id b o app sl app o lc ModelSim User s Manual v6 2g 377 February 2007 Verilog PLI VPI DPI Compiling and Linking C Applications for PLI VPI DPI Note that fPIC may not work with all versions of gcc e cc compiler cc c z DD32 I lt install_dir gt modeltech include app c Id b o app sl app o lc 64 bit HP Platform cc compiler cc v DD64 O l lt install_dir gt modeltech include c app c Id b o app sl app o Ic 64 bit HP for IA64 Platform e cc compiler opt ansic bin cc usr ccs bin ld cc c DD64 l lt install_dir gt modeltech include app c Id b o app sl app o If your PLI VPI DPI application requires a user or vendor supplied C library or an additional system library you will need to specify that library when you link your PLI VPI DPI application For example to use the system math library specify
361. lusive OR of two signals e afunction defined as a repetitive clock e afunction defined as the rising edge of CLK delayed by 1 34 ns Virtual functions can also be used to convert signal types and map signal values The result type of a virtual function can be any of the types supported in the GUI expression syntax integer real boolean std logic std logic vector and arrays and records of these types Verilog types are converted to VHDL 9 state std logic equivalents and Verilog net strengths are ignored ModelSim User s Manual v6 2g 185 February 2007 WLF Files Datasets and Virtuals Virtual Objects Virtual functions can be created using the virtual function command Virtual functions are also implicitly created by ModelSim when referencing bit selects or part selects of Verilog registers in the GUI or when expanding Verilog registers in the Objects Wave or List window This is necessary because referencing Verilog register elements requires an intermediate step of shifting and masking of the Verilog vreg data structure Virtual Regions User defined design hierarchy regions can be defined and attached to any existing design region or to the virtuals context tree They can be used to reconstruct the RTL hierarchy in a gate level design and to locate virtual signals Thus virtual signals and virtual regions can be used in a gate level design to allow you to use the RTL test bench Virtual regions are created and attached us
362. map file Refer to Simulator Control Variables for additional information HOME OIN The HOME OIN environment variable identifies the location of the 0 In executables directory Refer to the 0 In documentation for more information 314 ModelSim User s Manual v6 2g February 2007 Simulator Variables Environment Variables LD LIBRARY PATH A UNIX shell environment variable setting the search directories for shared libraries It instructs the OS where to search for the shared libraries for FLI PLI VPI DPI This variable is used for both 32 bit and 64 bit shared libraries on Solaris Linux systems LD LIBRARY PATH 32 A UNIX shell environment variable setting the search directories for shared libraries It instructs the OS where to search for the shared libraries for FLI PLI VPI DPI This variable is used only for 32 bit shared libraries on Solaris Linux systems LD LIBRARY PATH 64 A UNIX shell environment variable setting the search directories for shared libraries It instructs the OS where to search for the shared libraries for FLI PLI VPI DPI This variable is used only for 64 bit shared libraries on Solaris Linux systems LM LICENSE FILE The toolset s file manager uses the LM LICENSE FILE environment variable to find the location of the license file The argument may be a colon separated semi colon for Windows set of paths including paths to other vendor license files The environment variable is required MODEL TECH The tool
363. me e Value Range 0 1 e Default vsim wlf WLFOptimize This variable specifies whether the viewing of waveforms is optimized e Value Range 0 1 e Default 1 on WLFSaveAllRegions This variable specifies the regions to save in the WLF file e Value Range 0 only regions containing logged signals 1 all design hierarchy e Default 0 340 ModelSim User s Manual v6 2g February 2007 Simulator Variables Simulator Control Variables WLFSizeLimit This variable limits the WLF file by size as closely as possible to the specified number of megabytes if both size and time limits are specified the most restrictive is used You can set this variable interactively in the GUI refer to Setting Simulator Control Variables With The GUI e Value Range any positive integer in units of MB or 0 unlimited e Default O unlimited WLFTimeLimit This variable limits the WLF file by time as closely as possible to the specified amount of time If both time and size limits are specified the most restrictive is used You can set this variable interactively in the GUI refer to Setting Simulator Control Variables With The GUI e Value Range any positive integer or 0 unlimited e Default O unlimited ModelSim User s Manual v6 2g 341 February 2007 Simulator Variables Simulator Control Variables Setting Simulator Control Variables With The GUI Changes made in the Runtime Options dialog are written to the active modelsim
364. model is deep within the design hierarchy an easy way to find the instance name is to first invoke the simulator without SDF options view the structure pane navigate to the model instance select it and enter the environment command This command displays the instance name that should be used in the SDF command line option Mistaking a Component or Module Name for an Instance Label Another common error is to specify the component or module name rather than the instance label For example the following invocation is wrong for the above testbenches vsim sdfmax testbench myasiczmyasic sdf testbench This results in the following error message Error vsim SDF 3250 myasic sdf 0 Failed to find INSTANCE testbench myasic Forgetting to Specify the Instance If you leave off the instance altogether then the simulator issues a message for each instance path in the SDF that is not found in the design For example vsim sdfmax myasic sdf testbench Results in ModelSim User s Manual v6 2g 275 February 2007 Standard Delay Format SDF Timing Annotation Troubleshooting Error vsim SDF 3250 myasic sdf 0 Failed to find INSTANCE testbench ul Error vsim SDF 3250 myasic sdf 0 Failed to find INSTANCE testbench u2 Error vsim SDF 3250 myasic sdf 0 Failed to find INSTANCE testbench u3 Error vsim SDF 3250 myasic sdf 0 Failed to find INSTANCE testbench u4 Error vsim SDF 3250
365. n clear the window and display all signals from the current region e Add region display all signals from the current region without first clearing window e View all nets clear the window and display all signals from the entire design e Add ports add port symbols to the port signals in the current region When you view regions or entire nets the window initially displays only the drivers of the added objects in order to reduce clutter You can easily view readers by selecting an object and invoking Navigate Expand net to readers A small circle above an input signal on a block denotes a trigger signal that is on the process sensitivity list Links to Other Windows The Dataflow window has links to other windows as described below Table 9 1 Dataflow Window Links to Other Windows and Panes Window Main Window select a signal or process in the Dataflow window and the structure tab updates if that object is in a different design unit Active Processes Pane select a process in either window and that process is highlighted in the other 226 ModelSim User s Manual v6 2g February 2007 Tracing Signals with the Dataflow Window Exploring the Connectivity of the Design Table 9 1 Dataflow Window Links to Other Windows and Panes cont Objects Pane select a design object in either window and that object is highlighted in the other Wave Window e trace through the design in the Dataflow window and
366. n 1 Show Warning10 This variable enables warnings about VHDL 1993 constructs in VHDL 1987 code e Value Range 0 1 e Default on 1 Show WarnLocallyStaticError This variable enables warnings about locally static errors deferred until run time e Value Range 0 1 e Default on 1 VHDL93 This variable enables support for VHDL 1987 where 1 enables support for VHDL 1993 and 2 enables support for VHDL 2002 e Value Range 0 1 2 e Default 2 328 ModelSim User s Manual v6 2g February 2007 Simulator Variables Simulator Control Variables Simulation Control Variables You can find these variables under the heading vsim in the modelsim ini file AssertFile This variable specifies an alternative file for storing VHDL assertion messages e Value Range any valid filename e Default transcript AssertionDebug This variable specifies that SVA assertion passes are reported e Value Range 0 1 e Default off 0 AssertionFormat This variable defines the format of VHDL assertion messages e Value Range Table A 2 AssertionFormat Variable Accepted Values Variable Description severity level report message time of assertion delta instance or region pathname if available instance pathname with process process name kind of object path points to returns Instance Signal Process or Unknown instance or region path without leaf process file line number of asser
367. n e 164lines 0 1 Adding Objects to the Wave or List Window You can add objects to the Wave or List window in several ways Adding Objects with Drag and Drop You can drag and drop objects into the Wave or List window from the Workspace Active Processes Memory Objects Source or Locals panes You can also drag objects from the Wave window to the List window and vice versa Select the objects in the first window then drop them into the Wave window Depending on what you select all objects or any portion of the design can be added Adding Objects with a Menu Command The Add menu in the Main windows let you add objects to the Wave window List window or Log file Adding Objects with a Command Use the add list or add wave commands to add objects from the command line For example VSIM gt add wave proc a Adds signal proc a to the Wave window ModelSim User s Manual v6 29 191 February 2007 Waveform Analysis Measuring Time with Cursors in the Wave Window VSIM gt add list Adds all the objects in the current region to the List window VSIM gt add wave r Adds all objects in the design to the Wave window Adding Objects with a Window Format File Select File gt Open gt Format and specify a previously saved format file See Saving the Window Format for details on how to create a format file Measuring Time with Cursors in the Wave Window ModelSim uses cursors to measure time in the Wave window C
368. n is loaded Also save main window geometry OK Cancel 3 Specify a new name or use an existing name to overwrite that layout 4 Click OK The layout is saved to the modelsim file or Registry on Windows Assigning Layouts to Modes You can assign which layout appears in each mode no design loaded design loaded design loaded with coverage Follow these steps 1 Create your custom layouts as described above 2 Select Layout gt Configure Example F 1 Configure Window Layouts Dialog Box Configure Window Layouts ES ml xj m Specify a Layout to Use When no design loaded NoDesign v When a design is loaded Simulate v When a design is loaded with coverage enabled Coverage v IV Save Window Layout Automatically OK Cancel 3 Select a layout for each mode 4 Click OK The layout assignment is saved to the modelsim file Registry on Windows 412 ModelSim User s Manual v6 2g February 2007 Setting GUI Preferences Navigating the Graphic User Interface Automatic Saving of Layouts By default any changes you make to a layout are saved automatically when you exit the tool or when you change modes For example if you load a design with code coverage rearrange some windows and then quit the simulation the changes are saved to whatever layout was assigned to the load with coverage mode To disable automatic saving of layouts select Layout Configure and uncheck S
369. n the symbolic radix is chosen for SystemVerilog reg and integer types the values are treated as binary When the symbolic radix is chosen for SystemVerilog bit and int types the values are considered to be decimal Aside from the Wave Signal Properties dialog there are three other ways to change the radix e Change the default radix for the current simulation using Simulate gt Runtime Options Main window e Change the default radix for the current simulation using the radix command e Change the default radix permanently by editing the DefaultRadix variable in the modelsim ini file ModelSim User s Manual v6 2g 205 February 2007 Waveform Analysis Formatting the Wave Window Dividing the Wave Window Dividers serve as a visual aid for debugging allowing you to separate signals and waveforms for easier viewing In the graphic below a bus is separated from the two signals above it with a divider called Bus Figure 8 15 Separate Signals with Wave Window Dividers ap wave default EM Eile Edt View Add Format Tools Window Jg amp BO0 gt ae 4 test_counter clk 4 fest counter reset I Bus g jest counter count 7 6 5 4 3 2 n 0 Pd 4 E 4 To insert a divider follow these steps 1 Select the signal above which you want to place the divider 2 Ifthe Wave pane is docked in MDI frame of the Main window select Add gt Wave gt Divider from the Main win
370. n value and units for example Resoultion 10fs You can override this value with the t argument to vsim You should set a smaller resolution if your delays get truncated e Value Range fs ps ns us ms or sec with optional prefix of 1 10 or 100 e Default ps RunLength This variable specifies the default simulation length in units specified by the UserTimeUnit variable You can set this variable interactively in the GUI refer to Setting Simulator Control Variables With The GUI e Value Range positive integer Default 100 ShowFunctions This variable sets the format for Breakpoint and Fatal error messages When set to 1 the default value messages will display the name of the function task subprogram module or architecture where the condition occurred in addition to the file and line number Set to 0 to revert messages to previous format e Value Range 0 1 e Default 1 SignalSpyPathSeparator This variable specifies a unique path separator for the Signal Spy functions The argument to SignalSpyPathSeparator must not be the same character as DatasetSeparator e Value Range any character except those with special meaning such as V etc e Default ModelSim User s Manual v6 2g 337 February 2007 Simulator Variables Simulator Control Variables Startup This variable specifies a simulation startup macro Refer to the do command e Value Range do DO filename any valid macro do f
371. n words enclosed in braces 8 Ifa backslash V appears within a word then backslash substitution occurs In all cases but those described below the backslash is dropped and the following character is treated as an ordinary character and included in the word This allows characters such as double quotes close brackets and dollar signs to be included in words without ModelSim User s Manual v6 2g 295 February 2007 Tcl and Macros DO Files Tcl Command Syntax triggering special processing The following table lists the backslash sequences that are handled specially along with the value that replaces each sequence Table 13 2 Tcl Backslash Sequences Sequence Value Audible alert bell 0x7 Backspace 0x8 Form feed Oxc Newline Oxa Carriage return Oxd Tab 0x9 Vertical tab Oxb lt newline gt whiteSpace A single space character replaces the backslash newline and all spaces and tabs after the newline This backslash sequence is unique in that it is replaced in a separate pre pass before the command is actually parsed This means that it will be replaced even when it occurs between braces and the resulting space will be treated as a word separator if it isn t in braces or quotes Backslash The digits ooo one two or three of them give the octal value of the character 10 296 The hexadecimal digits hh give the hexadecimal value of the character Any number of
372. name C dataflow vsim snapshot wlf DK Cancel Collapsing Time and Delta Steps By default ModelSim collapses delta steps This means each logged signal that has events during a simulation delta has its final value recorded to the WLF file when the delta has expired The event order in the WLF file matches the order of the first events of each signal 182 ModelSim User s Manual v6 29 February 2007 WLF Files Datasets and Virtuals Virtual Objects You can configure how ModelSim collapses time and delta steps using arguments to the vsim command or by setting the WLFCollapseMode variable in the modelsim ini file The table below summarizes the arguments and how they affect event recording Table 7 3 vsim Arguments for Collapsing Time and Delta Steps vsim argument effect modelsim ini setting wlfnocollapse All events for each logged signal are WLFCollapseMode 0 recorded to the WLF file in the exact order they occur in the simulation wlfdeltacollapse Each logged signal which has events during a WLFCollapseMode 1 simulation delta has its final value recorded to the WLF file when the delta has expired Default wlftimecollapse Same as delta collapsing but at the timestep WLFCollapseMode 2 granularity When a run completes that includes single stepping or hitting a breakpoint all events are flushed to the WLF file regardless of the time collapse mode It s possible that single stepping thro
373. ncy of this problem Enforcing Strict 1076 Compliance The optional pedanticerrors argument to vcom enforces strict compliance to the IEEE 1076 LRM in the cases listed below The default behavior for these cases is to issue an insuppressible warning message If you compile with pedanticerrors the warnings change to an error unless otherwise noted Descriptions in quotes are actual warning error messages emitted by vcom As noted in some cases you can suppress the warning using nowarn level 362 Type conversion between array types where the element subtypes of the arrays do not have identical constraints Extended identifier terminates at newline character Oxa Extended identifier contains non graphic character 0x x Extended identifier s contains no graphic characters Extended identifier s did not terminate with backslash character An abstract literal and an identifier must have a separator between them This is for forming physical literals which comprise an optional numeric literal followed by a separator followed by an identifier the unit name Warning is level 4 which means nowarn 4 will suppress it In VHDL 1993 or 2002 a subprogram parameter was declared using VHDL 1987 syntax which means that it was a class VARIABLE parameter of a file type which is the only way to do it in VHDL 1987 and is illegal in later VHDLs Warning is level 10 Shared variables must be of a protected type App
374. nd rising edge on data with respect to clock while the SDF file may contain only a single setup check for both edges Table 11 16 Matching Verilog Timing Checks to SDF SETUP SETUP data posedge clock 5 setup posedge data posedge clk 0 SETUP data posedge clock 5 setup negedge data posedge clk 0 ModelSim User s Manual v6 2g 271 February 2007 Standard Delay Format SDF Timing Annotation sdf annotate In this case the cell accommodates more accurate data than can be supplied by the tool that created the SDF file and both timing checks correctly receive the same value Likewise the SDF file may contain more accurate data than the model can accommodate Table 11 17 SDF Data May Be More Accurate Than Model SETUP posedge data posedge clock 4 setup data posedge clk 0 SETUP negedge data posedge clock 6 setup data posedge clk 0 In this case both SDF constructs are matched and the timing check receives the value from the last one encountered Timing check edge specifiers can also use explicit edge transitions instead of posedge and negedge However the SDF file is limited to posedge and negedge For example Table 11 18 Matching Explicit Verilog Edge Transitions to Verilog SETUP data posedge clock 5 setup data edge 01 Ox clk 0 The explicit edge specifiers are 01 Ox 10 1x x0 and x1 The set of 01 Ox x1 is equivalent to posedge while
375. ndor specific ASIC design flow documentation that incorporates VCD please contact your ASIC vendor Creating a VCD File There are two flows in ModelSim for creating a VCD file One flow produces a four state VCD file with variable changes in 0 1 x and z with no strength information the other produces an extended VCD file with variable changes in all states and strength information and port driver data Both flows will also capture port driver changes unless filtered out with optional command line arguments Flow for Four State VCD File First compile and load the design 96 cd modeltech examples misc 96 vlib work 96 vlog counter v tcounter v vsim test counter Next with the design loaded specify the VCD file name with the vcd file command and add objects to the file with the vcd add command VSIM 1 gt vcd file myvcdfile vcd VSIM 2 vcd add test counter dut VSIM 3 run VSIM 4 gt quit f There will now be a VCD file in the working directory ModelSim User s Manual v6 2g 277 February 2007 Value Change Dump VCD Files Using Extended VCD as Stimulus Flow for Extended VCD File First compile and load the design 96 cd modeltech examples misc 96 vlib work 96 vlog counter v tcounter v 96 vsim test counter Next with the design loaded specify the VCD file name and objects to add with the vcd dumpports command VSIM 1 gt ved dumpports file myvcdfile vcd test counter dut VSIM 3 run VSIM
376. ndow undocked 0 cee cee eee ee eee 225 Figure 9 2 Green Highlighting Shows Your Path Through the Design 228 Figure 9 3 Wave Viewer Displays Inputs and Outputs of Selected Process 229 Figure 9 4 Unknown States Shown as Red Lines in Wave Window 231 Figure 9 5 Find in Dataflow Dialog 4 2 osx 3os ER sad ood exe REX RUE E Ra RE 233 Figure 9 6 The Print Postscript Dialog 22 sscccvaeeseea RR RR serene 234 Figure 9 7 The Print Dialog 24 ou acere aoea gea kaat ete eae PLE RR d a PEE uon 234 Figure 9 8 The Dataflow Page Setup Dialog 0 0 0 0 cece eee ee 235 Figure 9 9 Configuring Dataflow Options 0 0 00 eee eee eee eee 237 Figure 11 1 SDF Tab in Start Simulation Dialog 0 0 0 eee eee 264 Figure A 1 Runtime Options Dialog Defaults Tab 0 000 002 eee eee 342 Figure A 2 Runtime Options Dialog Box Assertions Tab 343 Figure A 3 Runtime Options Dialog Box WLF Files Tab 00 344 Figure D 1 DPI Use Flow Diagram 2444 seed exa e Ip PER R9 hd ume PER 370 Figure F 1 Save Current Window Layout Dialog Box 0 0 0 0 ce eee eee 412 Figure F 2 GUI Window Pane 5c smee ey RR REXIRROEIHP RE RO RPEREP ERR YS 413 Figure F 3 GUI Double Bar 2 222 sud rr cea exe RP Yr pdEr EET RE ERER 414 Figure F 4 GUI Undock Button 2256 c cersrdescewene eideesne sr serene ci deeend 414 Figure bs GUL Dock Button uoo dete duce d
377. ndows Ctrl s UNIX Ctrl f Windows find Ctrl t reverse the order of the two characters on either side of the cursor Ctrl u delete line Page Down Ctrl v UNIX only move cursor down one screen Ctrl w UNIX Ctrl x Windows cut the selection Ctrl s Ctrl x UNIX Only Ctrl y UNIX Ctrl v Windows paste the selection Ctrl a Windows Only Ctrl select the entire contents of the widget clear any selection in the widget Ctrl UNIX Ctrl UNIX Ctrl z Windows Meta lt UNIX only undoes previous edits in the Source window move cursor to the beginning of the file Meta gt UNIX only move cursor to the end of the file Page Up Meta v UNIX only move cursor up one screen Meta w UNIX Ctrl c Windows copy selection F3 F4 Shift F4 Peforms a Find Next action in the Source Window Change focus to next pane in main window Change focus to previous pane in main window F5 Shift F5 Toggle between expanding and restoring size of pane to fit the entire main window Toggle on off the pane headers F8 search for the most recent command that matches the characters typed Main window only F9 F10 run simulation continue simulation F11 Windows only 406 single step ModelSim User s Manual v6 2g February 2007 Command and Keyboard Shortcuts List
378. ne flushes the VCD file buffer same effect as calling dumpflush in the Verilog code int tf getlongsimtime int aof hightime This routine gets the current simulation time as a 64 bit integer The low order bits are returned by the routine while the high order bits are stored in the aof hightime argument 64 bit Support for PLI The PLI function acc fetch paramval cannot be used on 64 bit platforms to fetch a string value of a parameter Because of this the function acc fetch paramval str has been added to the PLI for this use acc fetch paramval str is declared in acc user h It functions in a manner similar to acc fetch paramval except that it returns a char acc fetch paramval str can be used on all platforms Using 64 bit ModelSim with 32 bit Applications If you have 32 bit PLI VPI DPI applications and wish to use 64 bit ModelSim you will need to port your code to 64 bits by moving from the ILP32 data model to the LP64 data model We strongly recommend that you consult the 64 bit porting guides for Sun and HP PLI VPI Tracing The foreign interface tracing feature is available for tracing PLI and VPI function calls Foreign interface tracing creates two kinds of traces a human readable log of what functions were called the value of the arguments and the results returned and a set of C language files that can be used to replay what the foreign interface code did 398 ModelSim User s Manual v6 2g Februa
379. ned or until it is reset to its default by a resetall directive The effect of compiler directives spans source files so the order of source files on the compilation command line could be significant For example if you have a file that defines some common macros for the entire design then you might need to place it first in the list of files to be compiled The resetall directive affects only the following directives by resetting them back to their default settings this information is not provided in the IEEE Std 1364 celldefine default decay time default nettype delay mode distributed delay mode path delay mode unit delay mode zero protected timescale unconnected drive uselib ModelSim Verilog implicitly defines the following macro define MODEL TECH IEEE Std 1364 Compiler Directives The following compiler directives are described in detail in the IEEE Std 1364 ModelSim User s Manual v6 2g 171 February 2007 Verilog and SystemVerilog Simulation Compiler Directives celldefine default nettype define else elsif endcelldefine endif ifdef ifndef include line nounconnected drive resetall timescale unconnected drive undef Verilog XL Compatible Compiler Directives The following compiler directives are provided for compatibility with Verilog XL default_decay_time lt time gt This directive specifies the default decay time to be used in trireg net declar
380. nfiguration or entity architecture pair Note A This section discusses simulation from the UNIX or Windows DOS command line You can also use a project to simulate see Getting Started with Projects or the Simulate dialog box This example invokes vsim on the entity my asic and the architecture structure vsim my asic structure vsim is capable of annotating a design using VITAL compliant models with timing data from an SDF file You can specify the min typ max delay by invoking vsim with the sdfmin sdftyp or sdfmax option Using the SDF file 7 sdf in the current work directory the following invocation of vsim annotates maximum timing values for the design unit my_asic vsim sdfmax my_asic f1 sdf my asic By default the timing checks within VITAL models are enabled They can be disabled with the notimingchecks option For example vsim notimingchecks topmod Simulator Resolution Limit VHDL The simulator internally represents time as a 64 bit integer in units equivalent to the smallest unit of simulation time also known as the simulator resolution limit The default resolution limit is set to the value specified by the Resolution variable in the modelsim ini file You can view the current resolution by invoking the report command with the simulator state option Overriding the Resolution You can override ModelSim s default resolution by specifying the t option on the command line or by selecting a differen
381. ng Objects into Buses You can combine signals in the Wave or List window into buses A bus is a collection of signals concatenated in a specific order to create a new virtual signal with a specific value A virtual compare signal the result of a comparison simulation is not supported for combination with any other signal To combine signals into a bus use one of the following methods e Select two or more signals in the Wave or List window and then choose Tools gt Combine Signals from the menu bar A virtual signal that is the result of a comparison simulation is not supported for combining with any other signal e Use the virtual signal command at the Main window command prompt In the illustration below three signals have been combined to form a new bus called Bus1 Note that the component signals are listed in the order in which they were selected in the Wave window Also note that the value of the bus is made up of the values of its component signals arranged in a specific order ModelSim User s Manual v6 29 215 February 2007 Waveform Analysis Combining Objects into Buses Figure 8 22 Signals Combined to Create Virtual Bus wave detoun s linis File Edit View Add Format Tools Window Osp iben test_sm into test_sm outof ooooo000000000001 test_sm tst D test_sm Bus1 TOOOOOOOOOOOT 34 test_sm clk 1 33 downto 2 test sm i MEC EN O test_sm wr_ test_sm clk 750000 ps Cursor 1 Ops iA p a
382. ng Wave Window Panes Value Pane The value pane displays the values of the displayed signals The radix for each signal can be symbolic binary octal decimal unsigned hexadecimal ASCII or default The default radix can be set by selecting Simulate Runtime Options Note When the symbolic radix is chosen for SystemVerilog reg and integer types the values are treated as binary When the symbolic radix is chosen for SystemVerilog bit and int types the values are considered to be decimal The data in this pane is similar to that shown in the Objects Pane except that the values change dynamically whenever a cursor in the waveform pane is moved Waveform Pane The waveform pane displays the waveforms that correspond to the displayed signal pathnames It also displays up to 20 cursors Signal values can be displayed in analog step analog interpolated analog backstep literal logic and event formats The radix of each signal can be set individually by selecting the signal and then choosing The default radix is logic If you rest your mouse pointer on a signal in the waveform pane a popup displays with information about the signal You can toggle this popup on and off in the Wave Window Properties dialog ModelSim User s Manual v6 2g 75 February 2007 Simulator Windows Wave Window Cursor Panes There are three cursor panes the left pane shows the cursor names the middle pane shows the current simulation time and
383. nge the variable value Additionally you can restrict display of the dataset prefix if you use the environment nodataset command to view a dataset To display the prefix use the environment command with the dataset option you won t need to specify this option if the variable noted above is set to 1 The environment command line switches override the pref tcl variable ModelSim User s Manual v6 29 181 February 2007 WLF Files Datasets and Virtuals Saving at Intervals with Dataset Snapshot Saving at Intervals with Dataset Snapshot Dataset Snapshot lets you periodically copy data from the current simulation WLF file to another file This is useful for taking periodic snapshots of your simulation or for clearing the current simulation WLF file based on size or elapsed time Once you have logged the appropriate objects select Tools Dataset Snapshot Wave window Figure 7 5 Dataset Snapshot Dialog x Dataset Snapshot State Enabled C Disabled Snapshot Type Simulation Time 1000000 ns wl C WLF File Size 100 Megabytes m Snapshot Contents Snapshot contains only data since previous snapshot Snapshot contains all previous data m Snapshot Directory and File Directory File Prefix c dataflow Browse vsim snapshot Uverwrite Increment Always replace snapshot file C Use incrementing suffix on snapshot files Selected Snapshot File
384. nged in the library vcom determines whether or not the compilation results have changed For example if you keep an entity and its architectures in the same source file and you modify only an architecture and recompile the source file the entity compilation results will remain unchanged and you will not have to recompile design units that depend on the entity Range and Index Checking A range check verifies that a scalar value defined with a range subtype is always assigned a value within its range An index check verifies that whenever an array subscript expression is evaluated the subscript will be within the array s range Range and index checks are performed by default when you compile your design You can disable range checks potentially offering a performance advantage and index checks using arguments to the vcom command Or you can use the NoRangeCheck and NoIndexCheck variables in the modelsim ini file to specify whether or not they are performed See Simulator Control Variables Range checks in ModelSim are slightly more restrictive than those specified by the VHDL LRM ModelSim requires any assignment to a signal to also be in range whereas the LRM requires only that range checks be done whenever a signal is updated Most assignments to signals update the signal anyway and the more restrictive requirement allows ModelSim to generate better error messages Subprogram Inlining ModelSim attempts to inline subprograms at compile
385. nges The delay can be an inertial or transport delay If no delay is specified then a delay of zero is assumed ModelSim User s Manual v6 2g 243 February 2007 Signal Spy init signal driver e delay type Optional del mode Specifies the type of delay that will be applied The value must be either mti inertial or mti transport The default is mti inertial e verbose Optional integer Possible values are 0 or 1 Specifies whether you want a message reported in the Transcript stating that the src_object is driving the dest_object Default is 0 no message Related procedures init_signal_spy signal_force signal_release Limitations e When driving a Verilog net the only delay_type allowed is inertial If you set the delay type to mti transport the setting will be ignored and the delay type will be mti_inertial e Any delays that are set to a value less than the simulator resolution will be rounded to the nearest resolution unit no special warning will be issued init signal driver Example This example creates a local clock c k0 and connects it to two clocks within the design hierarchy The bIkI clk will match local c kO and a message will be displayed The open entries allow the default delay and delay type while setting the verbose parameter to a 1 The blk2 clk will match the local c k0 but be delayed by 100 ps library IEEE modelsim lib use IEEE std logic 1164 a11 use modelsim lib util all en
386. ngs Projects may also include e Source files or references to source files other files such as READMES or other project documentation e local libraries e references to global libraries e Simulation Configurations see Creating a Simulation Configuration e Folders see Organizing Projects with Folders IEEE 5 5 eure o o Project metadata are updated and stored only for actions taken within the project itself For example if you have a file in a project and you compile that file from the command line rather than using the project menu commands the project will not update to reflect any new compile settings What are the Benefits of Projects Projects offer benefits to both new and advanced users Projects e simplify interaction with ModelSim you don t need to understand the intricacies of compiler switches and library mappings eliminate the need to remember a conceptual model of the design the compile order is maintained for you in the project Compile order is maintained for HDL only designs e remove the necessity to re establish compiler switches and settings at each session these are stored in the project metadata as are mappings to source files ModelSim User s Manual v6 2g 81 February 2007 Projects Getting Started with Projects e allow users to share libraries without copying files to a local directory you can establish references to source files that are stored remotely or locally e allow you to change
387. nment variables Default MODEL_TECH std std_developerskit This variable sets the path to the libraries for MGC standard developer s kit e Value Range any valid path may include environment variables e Default MODEL_TECH std_developerskit synopsys This variable sets the path to the accelerated arithmetic packages e Value Range any valid path may include environment variables e Default MODEL_TECH synopsys sv_std This variable sets the path to the SystemVerilog STD library e Value Range any valid path may include environment variables e Default MODEL_TECH sv_std verilog This variable sets the path to the library containing VHDL Verilog type mappings e Value Range any valid path may include environment variables e Default MODEL_TECH verilog 320 ModelSim User s Manual v6 2g February 2007 Simulator Variables Simulator Control Variables vital2000 This variable sets the path to the VITAL 2000 library e Value Range any valid path may include environment variables e Default MODEL TECH vital2000 others This variable points to another modelsim ini file whose library path variables will also be read the pathname must include modelsim ini only one others variable can be specified in any modelsim ini file e Value Range any valid path may include environment variables e Default none Verilog Compiler Control Variables You can find these variables under the heading vlog in the m
388. non zero reason paramvc For the change of value on the system task or function argument reason synch For the end of time step event scheduled by tf synchronize reason rosynch For the end of time step event scheduled by tf rosynchronize reason reactivate For the simulation event scheduled by tf setdelay reason paramdrc Not supported in ModelSim Verilog reason force Not supported in ModelSim Verilog reason release Not supported in ModelSim Verilog reason disable Not supported in ModelSim Verilog The sizetf Callback Function A user defined system function specifies the width of its return value with the sizetf callback function and the simulator calls this function while loading the design The following details on the sizetf callback function are not found in the IEEE Std 1364 e If you omit the sizetf function then a return width of 32 is assumed e The sizetf function should return 0 if the system function return value is of Verilog type real e The sizetf function should return 32 if the system function return value is of Verilog type integer ModelSim User s Manual v6 2g 391 February 2007 Verilog PLI VPI DPI PLI Object Handles PLI Object Handles Many of the object handles returned by the PLI ACC routines are pointers to objects that naturally exist in the simulation data structures and the handles to these objects are valid throughout the simulation even after the acc close
389. nor test XNOR Note that for primitive gate symbols pin mapping is automatic The Dataflow window looks in the current working directory and inside each library referenced by the design for the file dataflow bsm bsm stands for Built in Symbol Map It will read all files found User defined symbols You can also define your own symbols using an ASCII symbol library file format for defining symbol shapes This capability is delivered via Concept Engineering s Nlview M widget Symlib format The Dataflow window will search the current working directory and inside each library referenced by the design for the file dataflow sym Any and all files found will be given to the Nlview widget to use for symbol lookups Again as with the built in symbols the DU name and optional process name is used for the symbol lookup Here s an example of a symbol for a full adder symbol adder structural DEF port a in loc 12 15 0 15 pinattrdsp name cl 2 15 8 port b in loc 12 15 0 15 pinattrdsp name cl 2 15 8 port cin in loc 20 40 20 28 pinattrdsp name uc 19 26 8 port cout out loc 20 40 20 28 pinattrdsp name lc 19 26 8 port sum out loc 630 510 pinattrdsp name cr 49 0 8 path 10 007 path 0 7 0 35 path 0 35 51 17 path 51 17 51 17 path 51 17 0 35 path 0 35 0 7 N path 0 7 10 0 Port mapping is done by name for these symbols so the port names in the symbol definition
390. not match the second condition above because the order of rl and r2 are reversed Rounded Timing Values The SDF TIMESCALE construct specifies time units of values in the SDF file The annotator rounds timing values from the SDF file to the time precision of the module that is annotated For example if the SDF TIMESCALE is Ins and a value of 016 is annotated to a path delay in a module having a time precision of 10ps from the timescale directive then the path delay receives a value of 20ps The SDF value of 16ps is rounded to 20ps Interconnect delays are rounded to the time precision of the module that contains the annotated MIPD SDF for Mixed VHDL and Verilog Designs Annotation of a mixed VHDL and Verilog design is very flexible VHDL VITAL cells and Verilog cells can be annotated from the same SDF file This flexibility is available only by using the simulator s SDF command line options The Verilog sdf annotate system task can annotate Verilog cells only See the vsim command for more information on SDF command line options Interconnect Delays An interconnect delay represents the delay from the output of one device to the input of another ModelSim can model single interconnect delays or multisource interconnect delays for Verilog VHDL VITAL or mixed designs See the vsim command for more information on the relevant command line arguments Timing checks are performed on the interconnect delayed versions of input ports This may
391. ns The WLF file is written as an archive file in binary format and is used to drive the debug windows at a later time The files contain data from logged objects e g signals and variables and the design hierarchy in which the logged objects are found You can record the entire design or choose specific objects The WLF file provides you with precise in simulation and post simulation debugging capability Any number of WLF files can be reloaded for viewing or comparing to the active simulation A dataset is a previously recorded simulation that has been loaded into ModelSim Each dataset has a logical name to let you indicate the dataset to which any command applies This logical name is displayed as a prefix The current active simulation is prefixed by sim while any other datasets are prefixed by the name of the WLF file by default Two datasets are displayed in the Wave window in Figure 7 1 The current simulation is shown in the top pane and is indicated by the sim prefix A dataset from a previous simulation is shown in the bottom pane and is indicated by the gold prefix ModelSim User s Manual v6 2g 175 February 2007 WLF Files Datasets and Virtuals Saving a Simulation to a WLF File Figure 7 1 Displaying Two Datasets in the Wave Window Mwave derame oo MNT TE File Edit View Add Format Tools Window RL 100ps3 EL EIEL tP XX en T m sim test_sm dat 2222222222222222222 sim test_sm addr 000011001
392. ns use one or more novital lt fname gt options vcom novital VitalTimingCheck novital VitalAND design vhd The novital switch only affects calls to VITAL functions from the design units currently being compiled Pre compiled design units referenced from the current design units will still call the built in functions unless they too are compiled with the novital option ModelSim VITAL built ins will be updated in step with new releases of the VITAL packages Util Package The util package serves as a container for various VHDL utilities The package is part of the modelsim lib library which is located in the modeltech tree and is mapped in the default modelsim ini file To access the utilities in the package you would add lines like the following to your VHDL code library modelsim lib use modelsim lib util all 124 ModelSim User s Manual v6 2g February 2007 VHDL Simulation Util Package get resolution get resolution returns the current simulator resolution as a real number For example 1 femtosecond corresponds to le 15 Syntax resval get_resolution Returns Name Type Description resval real The simulator resolution represented as a real Arguments None Related functions to real e to time Example If the simulator resolution is set to 10ps and you invoke the command resval z get resolution the value returned to resval would be 1e 11 init signal driver The init signal driver p
393. ntains no DPI export tasks or functions the work library can be changed by simply changing the permissions as shown for win32 and rs6000 rs64 above For designs that contain DPI export tasks and functions and are not run on Windows or RS6000 RS64 by default vsim creates a shared object in directory lt libname gt _dpi This shared object is called exportwrapper so Linux and Solaris or exportwrapper sl hp700 hppa64 and hpux_ia64 If you are using a read only library vsim must not create any objects in the library To prevent vsim from creating objects in the library at runtime the vsim dpiexportobj flow is available on all platforms Use this flow after compilation but before you start simulation using the design library An example command sequence on Linux would be vlib work vlog dpiheader dpiheader h test sv gcc shared Bsymbolic o test so test c vsim c dpiexportobj work _dpi exportwrapper top chmod R a w work The library is now ready for simulation by multiple simultaneous users as follows vsim top sv_lib test The work _dpi exportwrapper argument provides a basename for the shared object At runtime vsim automatically checks to see if the file work _dpi exportwrapper so is up to date with respect to its C source code If it is out of date an error message is issued and elaboration stops Compiling and Linking C Applications for PLI VPI DPI The following platform specific instructions show you how to
394. nverted value is determined by the simulator resolution For example if you were converting 5 9 to a time and the simulator resolution was ps then the time value would be 6 ps Syntax timeval to time realval Returns Name Type timeval time Arguments Name Type realval real Related functions e get resolution to real Example Description The real value represented as a physical type time with respect to the simulator resolution Description The value of the type real If the simulator resolution is set to ps and you enter the following function timeval to time 72 49 then the value returned to timeval would be 72 ps ModelSim User s Manual v6 29 February 2007 127 VHDL Simulation Modeling Memory Modeling Memory As a VHDL user you might be tempted to model a memory using signals Two common simulator problems are the likely result e You may get a memory allocation error message which typically means the simulator ran out of memory and failed to allocate enough storage e Or you may get very long load elaboration or run times These problems are usually explained by the fact that signals consume a substantial amount of memory many dozens of bytes per bit all of which needs to be loaded or initialized before your simulation starts Modeling memory with variables or protected types instead provides some excellent performance benefits e storage required to model the memory can b
395. nvironment variables 313 LM LICENSE FILE 315 precedence between ini and tcl 349 setting environment variables 314 simulator state variables current settings report 313 iteration number 349 name of entity or module as a variable 349 resolution 349 simulation time 349 values of displaying in Objects window 60 saving as binary log file 175 VCD files capturing port driver data 286 case sensitivity 278 creating 277 dumpports tasks 281 from VHDL source to VCD output 282 stimulus using as 278 supported TSSI states 286 VCD system tasks 282 Verilog ACC routines 395 capturing port driver data with dumpports 286 cell libraries 162 ModelSim User s Manual v6 2g February 2007 ABCDEFGHI compiler directives 171 compiling and linking PLI C applications 373 compiling and linking PLI C applications 380 compiling design units 140 compiling with XL uselib compiler directive 147 configurations 149 DPI access routines 397 event order in simulation 154 generate statements 150 language templates 65 library usage 144 SDF annotation 266 sdf annotate system task 266 simulating 151 delay modes 162 XL compatible options 160 simulation hazard detection 158 simulation resolution limit 151 source code viewing 62 standards 28 system tasks 163 TF routines 397 XL compatible compiler options 146 XL compatible routines 398 XL compatible system tasks 168 verilog ini file variable 320 Verilo
396. nywhere within the Project tab and select Project Settings 2 Enable the Convert pathnames to softnames within the Location map area of the dialog Figure 3 19 Once enabled all pathnames currently in the project and any that are added later are then converted to softnames During conversion if there is no softname in the mgc location map matching the entry the pathname is converted in to a full hardened pathname A pathname is hardened by removing the environment variable or the relative portion of the path If this happens any existing 96 ModelSim User s Manual v6 2g February 2007 Projects Accessing Projects from the Command Line pathnames that are either relative or use environment variables are also changed either to softnames if possible or to hardened pathnames if not For more information on location mapping and pathnames see Location Mapping Accessing Projects from the Command Line Generally projects are used from within the ModelSim GUI However standalone tools will use the project file if they are invoked in the project s root directory If you want to invoke outside the project directory set the MODELSIM environment variable with the path to the project file Project Root Dir Project Name mpf You can also use the project command from the command line to perform common operations on projects ModelSim User s Manual v6 2g 97 February 2007 Projects Accessing Projects from the Command Line 98
397. o drive values onto signals and testing the results A VHDL test bench has been included with the ModelSim install files as an example Check for this file install dir modeltech examples misc stimulus vhd 122 ModelSim User s Manual v6 2g February 2007 VHDL Simulation VITAL Specification and Source Code VITAL Specification and Source Code VITAL ASIC Modeling Specification The IEEE 1076 4 VITAL ASIC Modeling Specification is available from the Institute of Electrical and Electronics Engineers Inc IEEE Customer Service 445 Hoes Lane Piscataway NJ 08854 1331 Tel 732 981 0060 Fax 732 981 1721 home page http www ieee org VITAL source code The source code for VITAL packages is provided in the directories install dir vhdl src vital22b vital95 vital2000 VITAL Packages VITAL 1995 accelerated packages are pre compiled into the ieee library in the installation directory VITAL 2000 accelerated packages are pre compiled into the vital2000 library If you need to use the newer library you either need to change the ieee library mapping or add a use clause to your VHDL code to access the VITAL 2000 packages To change the ieee library mapping issue the following command vmap ieee lt modeltech gt vital2000 Or alternatively add use clauses to your code LIBRARY vital2000 USE vital2000 vital_primitives all USE vital2000 vital_timing all USE vital2000 vital_memory all
398. ociated with a particular third party A current list of Mentor Graphics trademarks may be viewed at www mentor com terms conditions trademarks cfm Table of Contents Chapter 1 Introduction PPP Pr m 21 Tool Struct re and POW aee doque hr IH OCER EC HIR C RE URP EUR CEP TERI e RES 21 Simulation Task Overview 5 204 i4465 ed actes e Suche RO tg en e c e RR E ES EE REN 22 Basic Steps for Simulation sa vore pa ee bce REC RENE RPAU RECEFQGG PENAT ARE S RES 23 Step 1 Collecting Files and Mapping Libraries lllllel eese 24 Step 2 Compiling the Design vlog vcom sccom ssns usuena nanara 25 Step 3 Loading the Design for Simulation 0 cee eee eee 26 Step 4 Simulating the Design 0 0 ec e 26 Step 5 Debugging the Design 4 452 voe qo e uegW x Iu A Fe xA RES Y eens 26 Modes of Operalolr a zs sepaxa d kA Ra PRXGRGURS ek EGUPARdORG RR RN Ga ba X ER RA RR AA 27 Command Lime MOS iu od 1er cp dirt 1r S USE CREW Fed doa 27 Batch Mode s oet dk riaan d EG ER DR QE D Hon Reb Y RUP EET RUP AXES REOR 28 standards SUPDOBEI Los exuere xpPS EE SEINS oS Mo EE E Eee qo EE aS Beek 28 PSU ON Signs deg e em dar Rr nC EOE ER dad ws d x SEN Nd RN RAO 29 Sections In This Document oc inqua p RE e co deer noes See ete csSek oo ee Pee HAS 29 Wh tisan ODCCU Scusa 6 uy REC PSNPPRL ANE RU PERLE NERA UE Ed EM GNE 30 Text Conventos seer xr aee XR TUAE oon ERR robes Ga keen eueeesas eee
399. odelsim ini file DisableOpt This variable when on disables all optimizations enacted by the compiler same as the O0 argument to vlog e Value Range 0 1 e Default off 0 GenerateLooplterationMax This variable specifies the maximum number of iterations permitted for a generate loop restricting this permits the implementation to recognize infinite generate loops e Value Range natural integer gt 0 e Default 100000 GenerateRecursionDepthMax This variable specifies the maximum depth permitted for a recursive generate instantiation restricting this permits the implementation to recognize infinite recursions e Value Range natural integer gt 0 e Default 200 ModelSim User s Manual v6 2g 321 February 2007 Simulator Variables Simulator Control Variables Hazard This variable turns on Verilog hazard checking order dependent accessing of global variables e Value Range 0 1 e Default off 0 Incremental This variable activates the incremental compilation of modules e Value Range 0 1 e Default off 0 MultiFileCompilationUnit Controls how Verilog files are compiled into compilation units Valid arguments e 0n Compiles all files on command line into a single compilation unit This behavior is called Multi File Compilation Unit MFCU mode same as mfcu argument to e 0 Off Default value Compiles each file in the compilation command line into separate compilation units
400. of the signal selected in the Wave window The Wave pane in the Dataflow window also opens to show the selected signal ModelSim User s Manual v6 29 221 February 2007 Waveform Analysis Creating and managing breakpoints with a cursor at the selected time The Dataflow window shows the signal s values at the current cursor position Sorting a Group of Objects in the Wave Window Select View Sort to sort the objects in the pathname and values panes Creating and managing breakpoints ModelSim supports both signal i e when conditions and file line breakpoints Breakpoints can be set from multiple locations in the GUI or from the command line Signal breakpoints Signal breakpoints when conditions instruct ModelSim to perform actions when the specified conditions are met For example you can break on a signal value or at a specific simulator time see the when command for additional details When a breakpoint is hit a message in the Main window transcript identifies the signal that caused the breakpoint Setting signal breakpoints from the command line You use the when command to set a signal breakpoint from the VSIM gt prompt Setting signal breakpoints from the GUI Signal breakpoints are most easily set in the Objects Pane and the Wave Window Overview Right click a signal and select Insert Breakpoint from the context menu A breakpoint is set on that signal and will be listed in the Breakpoints dialog File line bre
401. og Procedural Interface VPI or the SystemVerilog DPI Direct Programming Interface If the simulator issues warnings regarding undefined system tasks or functions then it is likely that these tasks or functions are defined by a PLI VPI application that must be loaded by the simulator ModelSim User s Manual v6 2g 163 February 2007 Verilog and SystemVerilog Simulation System Tasks and Functions IEEE Std 1364 System Tasks and Functions The following system tasks and functions are described in detail in the IEEE Std 1364 Table 6 4 IEEE Std 1364 System Tasks and Functions 1 Timescale tasks Simulator control Simulation time Command line input tasks functions printtimescale finish realtime test plusargs timeformat stop stime value plusargs time Table 6 5 IEEE Std 1364 System Tasks and Functions 2 Probabilistic Conversion Stochastic analysis Timing check tasks distribution functions tasks functions dist_chi_square bitstoreal q_add hold dist_erlang itor q exam nochange dist_exponential realtobits q_full period dist_normal rtoi q_initialize recovery dist_poisson signed q_remove setup dist_t Sunsigned setuphold dist_uniform skew random width removal recrem 1 Verilog XL ignores the threshold argument even though it is part of the Verilog spec ModelSim does not ignore this argument Be careful that you don t set the threshold argument greater than or equal to the limit arg
402. ogic 1164 std logic misc std logic textio std logic arith std logic signed std logic unsigned vital primitives and vital timing You can select which library to use by changing the mapping in the modelsim ini file The modelsim ini file in the installation directory defaults to the ieee library Regenerating Your Design Libraries Depending on your current ModelSim version you may need to regenerate your design libraries before running a simulation Check the installation README file to see if your libraries require an update You can regenerate your design libraries using the Refresh command from the Library tab context menu refer to Managing Library Contents or by using the refresh argument to vcom and vlog From the command line you would use vcom with the refresh argument to update VHDL design units in a library and vlog with the refresh argument to update Verilog design units By default the work library is updated Use either vcom or vlog with the work library argument to update a different library For example if you have a library named mylib that contains both VHDL and Verilog design units vcom work mylib refresh vlog work mylib refresh An important feature of refresh is that it rebuilds the library image without using source code This means that models delivered as compiled libraries without source code can be rebuilt for a specific release of ModelSim In general this works for moving forwards or backward
403. om the command line within ModelSim The vmap command adds the mapping to the library section of the modelsim ini file You can also modify modelsim ini manually by adding a mapping line To do this use a text editor and add a line under the Library section heading using the syntax logical name directory pathname More than one logical name can be mapped to a single directory For example suppose the modelsim ini file in the current working directory contains following lines Library work usr rick design my asic usr rick design ModelSim User s Manual v6 2g 103 February 2007 Design Libraries Working with Design Libraries This would allow you to use either the logical name work or my asic in a library or use clause to refer to the same design library Unix Symbolic Links You can also create a UNIX symbolic link to the library using the host platform command In s directory pathname logical name The vmap command can also be used to display the mapping of a logical library name to a directory To do this enter the shortened form of the command vmap logical name Library Search Rules The system searches for the mapping of a logical name in the following order First the system looks for a modelsim ini file If the system doesn t find a modelsim ini file or if the specified logical name does not e exist in the modelsim ini file the system searches the current working directory for a
404. om the statement that will be executed next that statement is denoted by a blue arrow in the Source editor window The contents of the window change from one statement to the next The Locals pane includes two columns The first column lists the names of the immediately visible data objects The second column lists the current value s associated with each name Figure 2 12 Locals Pane SOR mem read_proc ModelSim User s Manual v6 2g 55 February 2007 Simulator Windows Memory Panes Memory Panes The Main window lists all memories in your design in the Memories tab of the Main window Workspace and displays the contents of a selected memory in the Main window MDI frame Figure 2 13 Memory Panes memory fram_tb spram2 mem 00010001 100101100 00010001100101101 00010001100101110 00010001100101111 000100011001 10000 00010001100110001 gt ram tb spram4 mem 0 3 gt Iram tb dprami mem 0 15 gt ram tb spram3 mem 0 65535 65536 4 16 16 8 00010001100110010 00010001100110011 00010001100110100 00010001100110101 00010001100110110 00010001100110111 00010001100111000 00010001100111001 00010001100111010 00010001100111011 00010001104111100 00010001100111101 AAA nnn 30 94440 w vows 9 0099341413 Memory list Memory contents The memory list is from the top level of the design In other words it is not sensitive to the context selected in the Structure tab
405. ompare differences repol defaultFast n defaultGoldDataset gold default name for the reference dataset in a waveforrr defaultHidelfMoDiffs 0 defaultlgnoreVerilo 1 setting to 1 specifies that Verilog net strengths shou defaultLeadTolera 0 specifies a time value to use for asynchronous comp defaultLeadUnits ns specifies the default units for lead tolerances range aj 2l DK Apply Cancel Saving GUI Preferences GUI preferences are saved automatically when you exit the tool If you prefer to store GUI preferences elsewhere set the MODELSIM PREFERENCES environment variable to designate where these preferences are stored Setting this variable causes ModelSim to use a specified path and file instead of the default location Here are some additional points to keep in mind about this variable setting e The file does not need to exist before setting the variable as ModelSim will initialize it e If the file is read only ModelSim will not update or otherwise modify the file e This variable may contain a relative pathname in which case the file is relative to the working directory at the time the tool is started The modelsim tcl File Previous versions saved user GUI preferences into a modelsim tcl file Current versions will still read in a modelsim tcl file if it exists ModelSim searches for the file as follows ModelSim User s Manual v6 2g 417 February 2007 S
406. ompressMode This variable specifies that checkpoint files are written in compressed format e Value Range 0 1 e Default on 1 CommandHistory This variable specifies the name of a file in which to store the Main window command history ModelSim User s Manual v6 2g 331 February 2007 Simulator Variables Simulator Control Variables e Value Range any valid filename e Default commented out ConcurrentFileLimit This variable controls the number of VHDL files open concurrently This number should be less than the current limit setting for max file descriptors e Value Range any positive integer or 0 unlimited Default 40 DatasetSeparator This variable specifies the dataset separator for fully rooted contexts for example sim top The argument to DatasetSeparator must not be the same character as PathSeparator e Value Range any character except those with special meaning such as V etc e Default DefaultForceKind This variable defines the kind of force used when not otherwise specified You can set this variable interactively in the GUI refer to Setting Simulator Control Variables With The GUI e Value Range freeze drive or deposit e Default drive for resolved signals freeze for unresolved signals DefaultRadix This variable specifies a numeric radix may be specified as a name or number For example you can specify binary as binary or 2 or octal as octal or 8
407. on then the exported symbol should be veriusertfs For the VPI the exported symbol should be vlog startup routines These requirements ensure that the appropriate symbol is exported and thus ModelSim can find the symbol when it dynamically loads the shared object DPI Imports on 32 bit IBM RS 6000 Platform When linking the shared objects be sure to specify bE lt isymfile gt option on the link command line lt isymfile gt is the name of the file generated by the isymfile argument to the vlog command Once you have created the lt isymfile gt it contains a complete list of all imported tasks and functions expected by ModelSim DPI Flow for Exported Tasks and Functions on 32 bit IBM RS 6000 Platform Since the RS6000 platform lacks the necessary runtime linking capabilities you must perform an additional manual step in order to prepare shared objects containing calls to exported SystemVerilog tasks or functions shared object file You need to invoke a special run of vsim The command is as follows vsim top du list dpiexportobj lt objname gt other args The dpiexportobj generates the object file lt objname gt o that contains glue code for exported tasks and functions You must add that object file to the link line listed after the other object files For example a link line would be Id o app so app o lt objname gt o bE lt isymfile gt bl install dir modeltech rs6000 mti exports bM SRE bnoentry Ic
408. on works on VITAL cells only The IEEE 1076 4 VITAL ASIC Modeling Specification describes how cells must be written to support SDF annotation Once again the designer does not need to know the details of this specification because the library provider has already written the VITAL cells and tools that create compatible SDF files However the following summary may help you understand simulator error messages For additional VITAL specification information see VITAL Specification and Source Code SDF to VHDL Generic Matching An SDF file contains delay and timing constraint data for cell instances in the design The annotator must locate the cell instances and the placeholders VHDL generics for the timing data Each type of SDF timing construct is mapped to the name of a generic as specified by the VITAL modeling specification The annotator locates the generic and updates it with the timing value from the SDF file It is an error if the annotator fails to find the cell instance or the named generic The following are examples of SDF constructs and their associated generic names Table 11 1 Matching SDF to VHDL Generics IOPATH a y 3 tpd a y IOPATH posedge clk q 1 2 tpd clk q posedge INTERCONNECT ul y u2 a 5 tipd a SETUP d posedge clk 5 tsetup d clk noedge posedge HOLD negedge d posedge clk 5 thold d clk negedge posedge SETUPHOLD d clk 5 5 tsetup d clk amp thold d clk WIDTH COND reset 1 b0 clk
409. onment Figure 2 2 36 ModelSim User s Manual v6 2g February 2007 Simulator Windows Main Window Figure 2 2 Main Window File Edit View Format Compile Simulate Add Tools Window Help Osna LBL Aga SLAR 4 Fos BPs wl wl owel a O Workspace SL gsx Design unit Design u zi ram_tb Module ram_tb Statemer ram tb Statemer sp syn ram Module d Nsp syn ram Module 4 ddr spram3 sp_syn_ram Module 4 in spram4 Nsp syn ra Module 4 a6 dprami Sdp syn ra Module OBIMPLICIT wIRE data ram tb Process OSIMPLICIT wWIRE outa ram tb Process i SIMPLICIT wWIRE inad ram tb Process amp data_dpl OSIMPLICIT AWIRE we ram tb Process D SIMPLICIT wIRE clk ram tb Process OSIMPLICIT wWIRE clk ram tb Process SJMPLICIT wWIRE data ram tb Process RIMPLICIT wWIRE addi ram tb Process ET Akh Bon Ee Romy Transcript vsim work ram_tb Loading work ram_tb Loading work sp_syn_ram ttl Loading work sp_syn_ram 3D Loading ork dp_syn_ram rtl IVSIM 3 Now 0 nd DetaO N sim ram_tb Workspace tabs The Transcript pane The Objects pane Multiple document interface organize design reports status and displays data MDI pane elementsina provides a command objects in the hierarchical tree line interface CUITSHESDODS structure Notice some of the elements that appear e Workspace tabs organize and disp
410. ons in package header and body out file Direction of concatenation To solve some technical problems the rules for direction and bounds of concatenation were changed from VHDL 87 to VHDL 93 You won t see any difference in simple variable signal assignments such as ModelSim User s Manual v6 2g February 2007 VHDL Simulation Compiling VHDL Files But if you 1 have a function that takes an unconstrained array as a parameter 2 pass a concatenation expression as a formal argument to this parameter and 3 the body of the function makes assumptions about the direction or bounds of the parameter then you will get unexpected results This may be a problem in environments that assume all arrays have downto direction e xnor xnor is a reserved word in VHDL 93 If you declare an xnor function in VHDL 87 without quotes and compile it under VHDL 2002 you will get an error message like the following Error xnor vhd 3 near xnor expecting STRING IDENTIFIER e FOREIGN attribute In VHDL 93 package STANDARD declares an attribute FOREIGN If you declare your own attribute with that name in another package then ModelSim issues a warning such as the following Compiling package foopack Warning foreign vhd 9 vcom 1140 VHDL 1993 added a definition of the attribute foreign to package std standard The attribute is also defined in package standard Using the definition from package standar
411. oo many arguments The macro accepts 0 2 args Example 2 This macro specifies the compiler arguments and lets you compile any number of files variable Files set nbrArgs Sarge for set x 1 x lt SnbrArgs incr x set Files concat Files 1 shift eval vcom 93 explicit noaccel Files Example 3 This macro is an enhanced version of the one shown in example 2 The additional code determines whether the files are VHDL or Verilog and uses the appropriate compiler and arguments depending on the file type Note that the macro assumes your VHDL files have a vhd file extension ModelSim User s Manual v6 2g 309 February 2007 Tcl and Macros DO Files Macros DO Files variable vhdFiles variable vFiles set nbrArgs Sarge set vhdFilesExist O0 set vFilesExist 0 for set x 1 x lt SnbrArgs incr x if string match vhd 11 set vhdFiles concat SvhdFiles 1 set vhdFilesExist 1 else set vFiles concat SvFiles 1 set vFilesExist 1 shift if vhdFilesExist 1 eval vcom 93 explicit noaccel vhdFiles if SvFilesExist 1 eval vlog vFiles Useful Commands for Handling Breakpoints and Errors If you are executing a macro when your simulation hits a breakpoint or causes a run time error ModelSim interrupts the macro and returns control to the command line The following commands may be useful for handling such events Any other legal command m
412. opy Paste yl 1 Find 1 Examine y i Describe i j5 Drivers 1 t LA Readers je ner at sc B k t y 4 r end ge reakpoints 17 GoTo y2 yl end Show Language Templates Show Source Annotation v Read Onl i n X o LC This functionality allows you to easily navigate your design for debugging purposes by remembering where you have been similar to the functionality in most web browsers The navigation options in the pop up menu function as follows e Open Instance changes your context to the instance you have selected within the source file This is not available if you have not placed your cursor in or highlighted the name of an instance within your source file If any ambiguities exists most likely due to generate statements this option opens a dialog box allowing you to choose from all available instances e Ascend Env changes your context to the next level up within the design This is not available if you are at the top level of your design 64 ModelSim User s Manual v6 2g February 2007 Simulator Windows Source Window e Forward Back allows you to change to previously selected contexts This is not available if you have not changed your context The Open Instance option is essentially executing an environment command to change your context therefore any time you use this command manually at the command prompt that information is also saved for use with the Forward Back options
413. or center active cursor in the display and zoom in View gt Zoom gt Zoom Cursor keyboard c or C Zoom Full zoom out to view the full range of the simulation from time 0 to the current time gt e Ne ModelSim User s Manual v6 2g February 2007 View gt Zoom gt Zoom Full keyboard f or F right mouse in wave pane gt Zoom Full 77 Simulator Windows Wave Window Table 2 10 Wave Window Toolbar Buttons and Menu Selections Stop Wave Drawing halts any waves currently being drawn in the Wave window Menu equivalent Other options Show Drivers display driver s of the selected signal net or register in the Dataflow window Restart reloads the design elements and resets the simulation time to zero with the option of keeping the current formatting breakpoints and WLF file Dataflow window Navigate Expand net to drivers Main menu Simulate Run Restart Dataflow window Expand net to all drivers right mouse in wave pane Show Drivers restart arguments Run run the current simulation for the default time length Continue Run continue the current simulation run Main menu Simulate Run Run default length Main menu Simulate gt Run gt Continue use the run command at the VSIM prompt use the run continue command at the VSIM prompt Run All run the current simulation forever or until it hits a breakpoint or spe
414. or from the OS command windows push buttons shell prompt Example menus and a command OS vsim line in the transcript Default mode Command line interactive command with c argument at the OS command prompt line no GUI Example OS vsim c non interactive batch at OS command shell prompt using redirection script no windows or of standard input Example interactive command line C vsim vfiles v infile gt outfile The ModelSim User s Manual focuses primarily on the GUI mode of operation However this section provides an introduction to the Command line and Batch modes Command Line Mode In command line mode ModelSim executes any startup command specified by the Startup variable in the modelsim ini file If vsim is invoked with the do command string option a DO file macro is called A DO file executed in this manner will override any startup command in the modelsim ini file During simulation a transcript file is created containing any messages to stdout A transcript file created in command line mode may be used as a DO file if you invoke the transcript on command after the design loads see the example below The transcript on command writes all of the commands you invoke to the transcript file For example the following series of commands results in a transcript file that can be used for command input if top is re simulated remove the quit f command from the transcript file if you want to remain in
415. ormed for this file itis written only when you invoke a Save command The file is written to the specified directory and records the contents of the transcript at the time of the save Using the Saved Transcript as a Macro DO file Saved transcript files can be used as macros DO files Refer to the do command for more information Changing the Number of Lines Saved in the Transcript Window By default the Transcript window retains the last 5000 lines of output from the transcript You can change this default by altering the saveLines preference variable Setting this variable to 0 instructs the tool to retain all lines of the transcript See Simulator GUI Preferences for details on setting preference variables Disabling Creation of the Transcript File You can disable the creation of the transcript file by using the following ModelSim command immediately after ModelSim starts transcript file Automatic Command Help When you start typing a command at the Transcript prompt a dropdown box appears which lists the available commands matching what has been typed so far You may use the Up and Down arrow keys or the mouse to select the desired command When a unique command has been entered the command usage is presented in the drop down box ModelSim User s Manual v6 2g 39 February 2007 Simulator Windows Main Window You can disable this feature by selecting Help Command Completion or by setting the PrefMain EnableComman
416. ou now can use examine value radix name which allows the flexibility of specifying command options The radix specification is optional ModelSim User s Manual v6 2g 297 February 2007 Tcl and Macros DO Files Tcl Command Syntax Command Separator A semicolon character works as a separator for multiple commands on the same line It is not required at the end of a line in a command sequence Multiple Line Commands With Tcl multiple line commands can be used within macros and on the command line The command line prompt will change as in a C shell until the multiple line command is complete In the example below note the way the opening brace is at the end of the if and else lines This is important because otherwise the Tcl scanner won t know that there is more coming in the command and will try to execute what it has up to that point which won t be what you intend if exa sig a 001122 echo Signal value matches do macro 1l do else echo Signal value fails do macro 2 do Evaluation Order An important thing to remember when using Tcl is that anything put in braces is not evaluated immediately This is important for if then else statements procedures loops and so forth Tcl Relational Expression Evaluation When you are comparing values the following hints may be useful e Tcl stores all values as strings and will convert certain strings to numeric values when ap
417. ow can be undocked from the main window by clicking the Undock button in the window header or by using the view undock wave command The preference variable PrefMain ViewUnDocked wave can be used to control this default behavior Setting this variable will open the Wave Window undocked each time you start ModelSim Figure 2 29 Wave Window Undock Button Undock button gl Fie Edt View Foma Comple Smidse Add Tools Window Help J eS 802 HF SHRM RM eT ims 1 48 ngn bE LE ui BS v al ae QQ Bede ET room EP ay come CO Hor THOR a x m contol Jj bleck2 store Mode block 3 reineve Module AM cemever retrieve MLW relieve Process a RASSI miava Porras pr zi oo E e Tee Inter tt RESTORED al 202900 ns Data seturmed to expected value deseo let VSMS Now 500 us Delta 2 eim test ringbuf Jes ETAO c Aest_angtuf ring_INST clock Pest angbuf nng INST heset Aest_angbuf ing INST Asda Mest _sngdut ning_INST outee Pest angbuf ang INST block Pest angbuf ang INST block Atest angbuf nng INST block Pest ang f ang INST block Aest_angbut ning_INST block Pest angbuf nng INST block Pest angbuf nng INST block LLN DM block Pest angbd nng INST block Pest angbul ing INST block 4 nest sngb nng INST block ELE SUL CUBE d Now A 100001000 so 100001000 Sn mmmn 1 500000 ne 1 462100 ns 462700 ns
418. owing statement in your VHDL source code USE std textio all 118 ModelSim User s Manual v6 2g February 2007 VHDL Simulation Using the TextlO Package A simple example using the package TextIO is USE std textio all ENTITY simple textio IS END ARCHITECTURE simple behavior OF simple textio IS BEGIN PROCESS VARIABLE i INTEGER 42 VARIABLE LLL LINE BEGIN WRITE LLL i WRITELINE OUTPUT LLL WAIT END PROCESS END simple behavior Syntax for File Declaration The VHDL 87 syntax for a file declaration is file identifier subtype indication is mode file logical name where file logical name must be a string expression In newer versions of the 1076 spec syntax for a file declaration is file identifier list subtype indication file open information where file open information is open file open kind expression is file logical name You can specify a full or relative path as the file logical name for example VHDL 87 Normally if a file is declared within an architecture process or package the file is opened when you start the simulator and is closed when you exit from it If a file is declared in a subprogram the file is opened when the subprogram is called and closed when execution RETURNs from the subprogram Alternatively the opening of files can be delayed until the first read or write by setting the DelayFileOpen variable in the modelsim ini file Also th
419. pare gold test sm View gold wif sim test_sm Simulation vsim wlf an Open SaveAs Close Make Active Rename Done Command Line You can open multiple datasets when the simulator is invoked by specifying more than one vsim view filename option By default the dataset prefix will be the filename of the WLF file You can specify a different dataset name as an optional qualifier to the vsim view switch on the command line using the following syntax view lt dataset gt lt filename gt For example vsim view foo vsim wlf 180 ModelSim User s Manual v6 2g February 2007 WLF Files Datasets and Virtuals Managing Multiple Datasets ModelSim designates one of the datasets to be the active dataset and refers all names without dataset prefixes to that dataset The active dataset is displayed in the context path at the bottom of the Main window When you select a design unit in a dataset s structure tab that dataset becomes active automatically Alternatively you can use the Dataset Browser or the environment command to change the active dataset Design regions and signal names can be fully specified over multiple WLF files by using the dataset name as a prefix in the path For example sim top alu out view top alu out golden top alu out Dataset prefixes are not required unless more than one dataset is open and you want to refer to something outside the active dataset
420. ped for the older VITAL 2 2b specification This version uses different name mapping rules In this case invoke vsim with the vital2 2b option vsim vital2 2b sdfmax testbench u1 myasic sdf testbench For more information on resolving errors see Troubleshooting Verilog SDF Verilog designs can be annotated using either the simulator command line options or the sdf_annotate system task also commonly used in other Verilog simulators The command line options annotate the design immediately after it is loaded but before any simulation events take place The sdf_annotate task annotates the design at the time it is called in the Verilog source code This provides more flexibility than the command line options 266 ModelSim User s Manual v6 2g February 2007 Standard Delay Format SDF Timing Annotation sdf annotate sdf annotate Syntax sdf annotate lt sdffile gt lt instance gt lt config_file gt lt log_file gt lt mtm_spec gt lt scale_factor gt lt scale_type gt Arguments lt sdffile gt String that specifies the SDF file Required lt instance gt Hierarchical name of the instance to be annotated Optional Defaults to the instance where the sdf_annotate call is made lt config_file gt String that specifies the configuration file Optional Currently not supported this argument is ignored log file gt String that specifies the logfile Optional Cur
421. ple Brace Foreground _ Background o fs z Styles DK Apply Cancel Select an item from the Category list and then edit the available properties on the right Click OK or Apply to accept the changes The changes will be active for the next Source window you open The changes are saved automatically when you quit ModelSim ModelSim User s Manual v6 29 February 2007 69 Simulator Windows Watch Pane Watch Pane The Watch pane shows values for signals and variables at the current simulation time Unlike the Objects or Locals pane the Watch pane allows you to view any signal or variable in the design regardless of the current context Figure 2 27 Watch Pane zinixi oe E ram_tb we 1 ram tb dpram1 inaddr 0001 ram_tb data_sp3 O0000000000000000111011001111010 ram_tb clk 0 ram tb i 625 You can view the following objects in the watch pane e VHDL objects signals aliases generics constants and variables e Verilog objects nets registers variables named events and module parameters e Virtual objects virtual signals and virtual functions Adding Objects to the Pane To add objects to the Watch pane drag and drop objects from the Structure tab Objects pane or Locals pane Alternatively use the add watch command Expanding Objects to Show Individual Bits If you add an array or record to the Watch pane you can
422. plication For example to use the standard C library specify Ic to the Id command e gcc compiler gcc c l lt install_dir gt modeltech include app c Id shared Bsymbolic E o app so app o lc If you are using ModelSim with RedHat version 7 1 or below you also need to add the noinhibit exec switch when you specify Bsymbolic The compiler switch freg struct return must be used when compiling any FLI application code that contains foreign functions that return real or time values 64 bit Linux for IA64 Platform 64 bit Linux is supported on RedHat Linux Advanced Workstation 2 1 for Itanium 2 e gcc compiler gcc 3 2 or later gcc c fPIC l lt install_dir gt modeltech include app c Id shared Bsymbolic E allow shlib undefined o app so app o If your PLI VPI DPI application requires a user or vendor supplied C library or an additional system library you will need to specify that library when you link your PLI VPI DPI application For example to use the system math library libm specify Im to the ld command gcc c fPIC I lt install_dir gt modeltech include math app c Id shared Bsymbolic E allow shlib undefined o math app so math app o Im 64 bit Linux for Opteron Athlon 64 and EM64T Platforms 64 bit Linux is supported on RedHat Linux EWS 3 0 for Opteron Athlon 64 and EM64T gcc compiler gcc 3 2 or later gcc c fPIC I lt install_dir gt modeltech include app c Id shared Bsymbolic E
423. ply open the docs tcl_help_html TclCmd directory in your ModelSim installation ModelSim User s Manual v6 2g 161 February 2007 Verilog and SystemVerilog Simulation Cell Libraries Cell Libraries Model Technology passed the ASIC Council s Verilog test suite and achieved the Library Tested and Approved designation from S12 Labs This test suite is designed to ensure Verilog timing accuracy and functionality and is the first significant hurdle to complete on the way to achieving full ASIC vendor support As a consequence many ASIC and FPGA vendors Verilog cell libraries are compatible with ModelSim Verilog The cell models generally contain Verilog specify blocks that describe the path delays and timing constraints for the cells See section 13 in the IEEE Std 1364 1995 for details on specify blocks and section 14 5 for details on timing constraints ModelSim Verilog fully implements specify blocks and timing constraints as defined in IEEE Std 1364 along with some Verilog XL compatible extensions SDF Timing Annotation ModelSim Verilog supports timing annotation from Standard Delay Format SDF files See Standard Delay Format SDF Timing Annotation for details Delay Modes Verilog models may contain both distributed delays and path delays The delays on primitives UDPs and continuous assignments are the distributed delays whereas the port to port delays specified in specify blocks are the path delays These delays interact to
424. pp1 so pliapp2 so pliappn so e Asalistin the PLIOBJS environment variable 96 setenv PLIOBJS pliapp1 so pliapp2 so pliappn so e Asa pli argument to the simulator multiple arguments are allowed pli pliapp1 so pli pliapp2 so pli pliappn so Note 5555555 LLL On Windows platforms the file names shown above should end with d rather than so The various methods of specifying PLI VPI applications can be used simultaneously The libraries are loaded in the order listed above Environment variable references can be used in the paths to the libraries in all cases See also Simulator Variables for more information on the modelsim ini file 386 ModelSim User s Manual v6 2g February 2007 Verilog PLI VPI DPI PLI Example DPI File Loading DPI applications are specified to vsim using the following SystemVerilog arguments Table D 1 vsim Arguments for DPI Application Argument Description sv lib lt name gt specifies a library name to be searched and used No filename extensions must be specified The extensions ModelSim expects are sl for HP dll for Win32 so for all other platforms SV root lt name gt specifies a new prefix for shared objects as specified by sv lib sv_liblist specifies a bootstrap file to use When the simulator finds an imported task or function it searches for the symbol in the collection of shared objects specified using these arguments For example you can specify
425. process Select the process and all signals attached to the selected process will appear in the wave viewer pane 230 ModelSim User s Manual v6 2g February 2007 Tracing Signals with the Dataflow Window Tracing the Source of an Unknown State StX 4 Place a time cursor on an edge of interest the edge should be on a signal that is an output of the process 5 Select Trace gt Trace input net to event A second cursor is added at the most recent input event 6 Keep selecting Trace Trace next event until you ve reached an input event of interest Note that the signals with the events are selected in the wave pane 7 Now select Trace gt Trace Set The Dataflow display jumps to the source of the selected input event s The operation follows all signals selected in the wave viewer pane You can change which signals are followed by changing the selection 8 To continue tracing go back to step 5 and repeat If you want to start over at the originally selected output select Trace Trace event reset Tracing the Source of an Unknown State StX Another useful Dataflow window debugging tool is the ability to trace an unknown state StX back to its source Unknown values are indicated by red lines in the Wave window Figure 9 4 and in the wave viewer of the Dataflow window Figure 9 4 Unknown States Shown as Red Lines in Wave Window Atop p data r Ztop p rw r top p strb_r top p verbose top p t_out top p t_s
426. propriate If you want a literal to be treated as a numeric value don t quote it if exa var 1 345 The following will also work if exa var 1 345 e However if a literal cannot be represented as a number you must quote it or Tcl will give you an error For instance if exa var 2 0012 will give an error if exa var 2 001Z2 J 298 ModelSim User s Manual v6 2g February 2007 Tcl and Macros DO Files Tcl Command Syntax will work okay e Don t quote single characters in single quotes if exa var 3 X will give an error if ema var 3 X will work okay e For the equal operator you must use the C operator For not equal you must use the C operator Variable Substitution When a lt var_name gt is encountered the Tcl parser will look for variables that have been defined either by ModelSim or by you and substitute the value of the variable Note Tcl is case sensitive for variable names To access environment variables use the construct env var name echo My user name is env USER Environment variables can also be set using the env array set env SHELL bin csh See Simulator State Variables for more information about ModelSim defined variables System Commands To pass commands to the UNIX shell or DOS window use the Tcl exec command echo The date is exec date ModelSim User s Manual v6 2g 299 February 2007 Tcl
427. psing Time and Delta Steps 2s osx d eR EAR ERE dune Giied Ss e EAE RN 182 Virmal ODJ nse e bee Rad rar QURE co HORS DP E LEE HD eee eee IDERERRI QE 183 Virtual Signals 45 2085 eu edo e I e EX rox CE eo RI ee RE bac udo de ir arm bac e a 184 Virtual FSIGUIS user REPERI I ee Shee RCEREERSTPQRRRECR EA CREER ARP E ERS 185 Virtual Cu CERTE MK 186 Xinual Types xscasedeenvakeczerewaRXa av d eic rad QR REGdeR EBRD RATERS 186 Chapter 8 Waveform Analysis 440422224 62 xRexeerRA RE Rara EA CES ARR RC RT EG X ER EA 187 Objects You Can VIEW X v es ew Rus een eee eee seu VE PRECES ME CER CERE PREAS RR AVE 187 Wave Window Overview co s s cee deedves ERe x ECRIRE RE GRECE TI RS qi coe 187 List Window Overview 52x32 exkas cefeseet reskersx ebbe Rubadai eg da er RV 190 Adding Objects to the Wave or List Window 0 0 cece eee eee ene 191 Adding Objects with Drag and Drop 20 00 cece eee eens 191 Adding Objects with a Menu Command 0 0 eee eee 191 Adding Objects with a Command 01 4 492046 o sa er ha y meh RE 191 Adding Objects with a Window Format File nananana anaana 192 Measuring Time with Cursors in the Wave Window 0 0 e eee eee eee 192 Working with Cursors itor x OR RR Hr pr ud RR OR RE RA E cede aa RE 193 Understanding Cursor Bebaylot 29042059 xyaeso ese d RXSESRREYF XD RE E E REMS 194 Jumping to a Signal Transition eRash ky ER RR 4 ru RRRRR RARE RARE EE REESE 195 Setting Time Marker
428. r time units and time precision is n units The value of n must be 1 10 or 100 The value of units must be fs ps ns us ms or s In addition the time units must be greater than or equal to the time precision For example timescale 1ns 1ps The argument above needs quotes because it contains white space Multiple Timescale Directives As alluded to above your design can have multiple timescale directives The timescale directive takes effect where it appears in a source file and applies to all source files which follow in the same vlog command Separately compiled modules can also have different timescales The simulator determines the smallest timescale of all the modules in a design and uses that as the simulator resolution timescale t and Rounding The optional vsim argument t sets the simulator resolution limit for the overall simulation If the resolution set by t is larger than the precision set in a module the time values in that module are rounded up If the resolution set by t is smaller than the precision of the module the precision of that module remains whatever is specified by the timescale directive Consider the following code ModelSim User s Manual v6 2g 153 February 2007 Verilog and SystemVerilog Simulation Simulating Verilog Designs timescale 1 ns 100 ps module foo initial 12 536 Sdisplay The list below shows three possibilities for t and
429. r s Manual v6 2g 93 February 2007 Projects Specifying File Properties and Project Settings Figure 3 17 Project Compiler Settings Dialog Project Compiler Settings o a4 General VHDL Coverage General Settings Do Not Compile Compile to library work yi Place in Folder VHDL v m File Properties File stimulus vhd Location C examples stimulus vhd MS DOS name C examples stimulus vhd Type VHDL Change Type Size 3145 3KB Modification Time 13 47 28 Pacific Standard Time Last Compile Source has not been compiled File Attributes Archive On Windows platforms you can also just drag and drop a file into a folder Specifying File Properties and Project Settings You can set two types of properties in a project file properties and project settings File properties affect individual files project settings affect the entire project File Compilation Properties The VHDL and Verilog compilers vcom and vlog respectively have numerous options that affect how a design is compiled and subsequently simulated You can customize the settings on individual files or a group of files Note Any changes you make to the compile properties outside of the project whether from the command line the GUI or the modelsim ini file will not affect the properties of files already in the project 94 ModelSim User s Manual v6 2g February 2007 Projects Specifying File
430. rd contains an open bracket then Tcl performs command substitution To do this it invokes the Tcl interpreter recursively to process the characters following the open bracket as a Tcl script The script may contain any number of commands and must be terminated by a close bracket The result of the script i e the result of its last command is substituted into the word in place of the brackets and all of the characters between them There may be any number of command substitutions in a single word Command substitution is not performed on words enclosed in braces 7 If a word contains a dollar sign then Tcl performs variable substitution the dollar sign and the following characters are replaced in the word by the value of a variable Variable substitution may take any of the following forms o S name Name is the name of a scalar variable the name is terminated by any character that isn t a letter digit or underscore o S name index Name gives the name of an array variable and index gives the name of an element within that array Name must contain only letters digits and underscores Command substitutions variable substitutions and backslash substitutions are performed on the characters of index o name Name is the name of a scalar variable It may contain any characters whatsoever except for close braces There may be any number of variable substitutions in a single word Variable substitution is not performed o
431. real 126 437 ABCDEFGHIJKLMNOPQRSTUVWXYZ timeline display clock cycles 203 timescale directive warning investigating 152 timing setuphold recovery 169 disabling checks 274 negative check limits described 159 TMPDIR environment variable 317 to real VHDL function 126 to time VHDL function 127 toggle coverage max VHDL integer values 338 too few port connections explanation 361 tool structure 21 toolbar Dataflow window 50 Main window 45 tracing events 230 source of unknown 231 transcript disable file creation 39 347 file name specifed in modelsim ini 346 saving 39 using as a DO file 39 Transcript window changing buffer size 39 changing line count 39 TranscriptFile ini file variable 338 triggers in the List window 219 triggers in the List window setting 217 troubleshooting DPI missing import funtion 400 TSSI in VCD files 286 type converting real to time 127 converting time to real 126 Type field Project tab 88 types virtual 186 U UnbufferedOutput ini file variable 338 438 ungrouping in wave window 210 ungrouping objects Monitor window 71 unit delay mode 163 unknowns tracing 231 use clause specifying a library 105 use flow DPI 370 UseCsupV2 ini file variable 338 user defined bus 183 215 UserTimeUnit ini file variable 339 util package 124 Vy values of HDL items 67 variables 342 environment 313 expanding e
432. refer to Setting Simulator Control Variables With The GUI e Value Range 0 1 e Default off 0 OnFinish This variable controls the behavior of the tool when it encounters finish in the design code e Value Range e ask o In batch mode the simulation exits o In GUI mode a dialog box pops up and asks for user confirmation on whether to quit the simulation e stop Causes the simulation to stay loaded in memory This can make some post simulation tasks easier e exit The simulation exits without asking for any confirmation e Default ask Exits in batch mode prompts user in GUI mode PathSeparator This variable specifies the character used for hierarchical boundaries of HDL modules This variable does not affect file system paths The argument to PathSeparator must not be the same character as DatasetSeparator e Value Range any character except those with special meaning such as V etc e Default PrintSimStats This variable instructs the simulator to print the output of the simstats command upon exit You can set this variable interactively with the printsimstats argument to the vsim command e Value Range 0 1 336 ModelSim User s Manual v6 2g February 2007 Simulator Variables Simulator Control Variables Default 0 Resolution This variable specifies the simulator resolution The argument must be less than or equal to the UserTimeUnit and must not contain a space betwee
433. rently not supported this argument is ignored mtm spec String that specifies the delay selection Optional The allowed strings are minimum typical maximum and tool control Case is ignored and the default is tool control The tool control argument means to use the delay specified on the command line by mindelays typdelays or maxdelays defaults to typdelays lt scale_factor gt String that specifies delay scaling factors Optional The format is lt min_mult gt lt typ_mult gt lt max_mult gt Each multiplier is a real number that is used to scale the corresponding delay in the SDF file lt scale_type gt String that overrides the lt mtm_spec gt delay selection Optional The lt mtm_spec gt delay selection is always used to select the delay scaling factor but if a scale type is specified then it will determine the min typ max selection from the SDF file The allowed strings are from min from minimum from typ from typical from max from maximum and from mtm Case is ignored and the default is from mtm which means to use the mtm spec value Examples Optional arguments can be omitted by using commas or by leaving them out if they are at the end of the argument list For example to specify only the SDF file and the instance to which it applies ModelSim User s Manual v6 2g 267 February 2007 Standard Delay Format SDF Timing Annotation sdf annotate sdf
434. riable s value 158 ModelSim User s Manual v6 2g February 2007 Verilog and SystemVerilog Simulation Simulating Verilog Designs e Glitches on nets caused by non guaranteed event ordering are not detected e A non blocking assignment is not treated as a WRITE for hazard detection purposes This is because non blocking assignments are not normally involved in hazards In fact they should be used to avoid hazards e Hazards caused by simultaneous forces are not detected Negative Timing Check Limits Verilog supports negative limit values in the setuphold and recrem system tasks These tasks have optional delayed versions of input signals to insure proper evaluation of models with negative timing check limits Delay values for these delayed nets are determined by the simulator so that valid data is available for evaluation before a clocking signal Example 6 4 Negative Timing Check setuphold posedge clk negedge d 5 3 Notifier clk dly d dly d violation 5 3 region clk ModelSim calculates the delay for signal d_dly as 4 time units instead of 3 It does this to prevent d_dly and clk_dly from occurring simultaneously when a violation isn t reported ModelSim accepts negative limit checks by default unlike current versions of Verilog XL To match Verilog XL default behavior i e zeroing all negative timing check limits use the no_neg_tcheck argument to vsim Negative Timing Constraint Algorithm The algori
435. rid Period field and select Display grid period count cycle count The timeline will now show the number of clock cycles as shown in Figure 8 13 Figure 8 13 Clock Cycles in Timeline of Wave Window test_counter clk test_counter reset Formatting Objects in the Wave Window You can adjust various object properties to create the view you find most useful Select one or more objects and then select View gt Properties or use the selections in the Format menu 204 ModelSim User s Manual v6 2g February 2007 Waveform Analysis Formatting the Wave Window Changing Radix base for the Wave Window One common adjustment is changing the radix base of an object When you select View gt Properties the Wave Signal Properties dialog appears Figure 8 14 Changing Signal Radix Wave Signal Properties Signal sim top paddr View S SRS m Display Name m Radig 4 r Wave Color C Symbolic Unsigned Colors C Binary C Hexadecimal C Octal C ASCII Name Color 3 C Decimal Default Colors Dk Cancel Apply The default radix is symbolic which means that for an enumerated type the value pane lists the actual values of the enumerated type of that object For the other radixes binary octal decimal unsigned hexadecimal or ASCII the object value is converted to an appropriate representation in that radix Note Whe
436. ring of values and if so specifies the initial state The default is 1 no ability to enable disable and mirroring is enabled 0 turns on the ability to enable disable and initially disables mirroring 1 turns on the ability to enable disable and initially enables mirroring Related tasks init_signal_driver signal_force signal_release disable_signal_spy Limitations e When mirroring the value of a VHDL signal onto a Verilog register the VHDL signal must be of type bit bit_vector std_logic or std_logic_vector e Verilog memories arrays of registers are not supported init_signal_spy Example In this example the value of top uut inst1 sig is mirrored onto top top_sig A message is issued to the transcript The ability to control the mirroring of values is turned on and the init_signal_spy is initially enabled The mirroring of values will be disabled when enable reg transitions to a 0 and enabled when enable reg transitions to a l module top reg top sigl reg enable reg initial begin S init signal spy top uut instl sigl top top sig1 1 1 end always posedg nable_reg begin Senable signal spy top uut instl sigl top top sig1 0 end always 8 negedg nable reg begin disable signal spy top uut instl sigl top top sig1 0 end endmodule ModelSim User s Manual v6 29 257 February 2007 Signal Spy signal force signal force The signal_force system task
437. rk menu Bookmarks are saved in the Wave format file see Adding Objects with a Window Format File and are restored when the format file is read Managing Bookmarks The table below summarizes actions you can take with bookmarks Action Add bookmark Table 8 3 Actions for Bookmarks Menu commands Wave window docked Add Wave Bookmark Menu commands Wave window undocked Add Bookmark Command bookmark add wave View bookmark Delete bookmark Wave Bookmarks bookmark name Wave Bookmarks Bookmarks select bookmark then Delete Adding Bookmarks To add a bookmark follow these steps View Bookmarks bookmark name View Bookmarks Bookmarks select bookmark then Delete bookmark goto wave bookmark delete wave 1 Zoom the wave window as you see fit using one of the techniques discussed in Zooming the Wave Window Display 2 If the Wave window is docked select Add Wave Bookmark If the Wave window is undocked select Add Bookmark ModelSim User s Manual v6 29 February 2007 197 Waveform Analysis Searching in the Wave and List Windows Figure 8 7 Bookmark Properties Dialog Bookmark Properties wave ES Bookmark Name Ee Zoom Range Top Index o ns tol 315 ns T v Save zoom range with bookmark AA Irere ede Deeetre deep seno esas epos ens oo seno senses ossa sees sense strae oos ea ee Dk
438. rmation ModelSim User s Manual v6 2g 345 February 2007 Simulator Variables Simulator Control Variables e Value Range tran transcript only wlf wlf file only both e Default both Commonly Used INI Variables Several of the more commonly used modelsim ini variables are further explained below Common Environment Variables You can use environment variables in your initialization files Use a dollar sign before the environment variable name For example Library work SHOME work_lib test lib STESTNUM work vsim IgnoreNote SIGNORE_ASSERTS IgnoreWarning SIGNORE_ASSERTS IgnoreError 0 IgnoreFailure 0 There is one environment variable MODEL_TECH that you cannot and should not set MODEL_TECH is a special variable set by Model Technology software Its value is the name of the directory from which the VCOM or VLOG compilers or VSIM simulator was invoked MODEL_TECH is used by the other Model Technology tools to find the libraries Hierarchical Library Mapping By adding an others clause to your modelsim ini file you can have a hierarchy of library mappings If the ModelSim tools don t find a mapping in the modelsim ini file then they will search only the library section of the initialization file specified by the others clause For example Library asic lib cae asic lib work my work others install dir modeltech modelsim ini Since the file referred to by the others
439. rocedure drives the value of a VHDL signal or Verilog net onto an existing VHDL signal or Verilog net This allows you to drive signals or nets at any level of the design hierarchy from within a VHDL architecture e g a testbench See init signal driver for complete details init signal spy The init signal spy utility mirrors the value of a VHDL signal or Verilog register net onto an existing VHDL signal or Verilog register This allows you to reference signals registers or nets at any level of hierarchy from within a VHDL architecture e g a testbench See init signal spy for complete details ModelSim User s Manual v6 29 125 February 2007 VHDL Simulation Util Package signal force The signal force procedure forces the value specified onto an existing VHDL signal or Verilog register or net This allows you to force signals registers or nets at any level of the design hierarchy from within a VHDL architecture e g a testbench A signal force works the same as the force command with the exception that you cannot issue a repeating force See signal force for complete details signal release The signal release procedure releases any force that was applied to an existing VHDL signal or Verilog register or net This allows you to release signals registers or nets at any level of the design hierarchy from within a VHDL architecture e g a testbench A signal release works the same as the noforce command
440. rouping Fles 2 2cen cheaters he tates ekr Reese cass tee Deva ecc quae 90 Creatine a Simulation Configuration os 240526 25e0Gdiees settee tee ERR eek bea GRE 91 Organizing Projects with Folders 4 2sac2aSeawed cider ngdecteeestsesee lt deeeven ts 92 Adding a Folder 146205 ctuasdaek enint ArAnA E A E E E Weegee 32 92 4 ModelSim User s Manual v6 2g February 2007 Table of Contents Specifying File Properties and Project Settings leere 94 File Compilation Properties osse ssszerkeRoRRsueRRS A RPET RE RA RENRGQISR REG RE 94 Project Settings METH Mm 96 Accessing Projects from the Command Line 0 0 0 cece eee ee eee 97 Chapter 4 Design Libraries iio pxdebauebeacsRuePt eP Aa d PP REPRE a3 e PCs asd epq ew 99 Desiren Library Overviews s olas ne tassi S24 os heehee eS ded EE pss pA Vb 99 Design Unit Information 2 e RD ae RATER REESE QR eR MES REaM E 99 Working Library Versus Resource Libraries 0 0 0 0c eee ee eee eee 99 Pw OS liane ous ithe Cyanine Pr wikis oaks diei 100 Working with Design Libraries 22 5 20 lt nse2soeeebSes Koen 9 Ee Kees a SEE E ARP Repas 100 Creating a Library co sos RA SERIEA ARN REETREIG Geese se AG aRRezdAA4 ied sd idqne es 101 Managing Library Contents 24codetecci de a e aber RE REX RASqEA DELE E EAE 101 Assigning a Logical Name to a Design Library 0 0 0 eee eee eee 102 Moving a Library eser RR RA eget estates ERR AG DRE E ERR ERR RED RE 104 Setting Up Libraries Tor
441. rs e Specify the bindAtCompile argument to vcom e Set the BindAtCompile variable in the modelsim ini to 1 true Default Binding Rules When looking for an entity to bind with ModelSim searches the currently visible libraries for an entity with the same name as the component ModelSim does this because IEEE 1076 1987 contained a flaw that made it almost impossible for an entity to be directly visible if it had the same name as the component In short if a component was declared in an architecture any like named entity above that declaration would be hidden because component entity names cannot be overloaded As a result we implemented the following rules for determining default binding e If performing default binding at load time search the libraries specified with the Lf argument to vsim e Ifadirectly visible entity has the same name as the component use it e If an entity would be directly visible in the absence of the component declaration use it e If the component is declared in a package search the library that contained the package for an entity with the same name If none of these methods is successful ModelSim will also do the following e Search the work library e Search all other libraries that are currently visible by means of the library clause e If performing default binding at load time search the libraries specified with the L argument to vsim ModelSim User s Manual v6 29 115 February 2007 VHDL
442. rt Simulation Dialog x Design VHDL Verilog Libraries SDF Others bl Library C Tutorial examples tutorials verilog pr Module C Tutorial examples tutorials verilog pr test_counter Module C Tutorial examples tutorials verilog pr Library MODEL TECH sv std i vital2000 Library MODEL TECH vital2000 i ieee Library MODEL TECH ieee i modelsim_lib Library MODEL TECH modelsim lib rn td Library MODEL TECH std dB b el b d std daeelenercbi I ihrarn THOME TECH std davalanarsk it zl eee gt Design Unit s Resolution p default Optimization Enable optimization Optimization Options OK Cancel A new tab named sim appears that shows the structure of the active simulation Figure 3 9 Figure 3 9 Structure Tab of the Workspace Workspace HA denm A TA BYE test counter test counter acc lt ull g dut Counter Module eeu dj increment counter Function accecdull At this point you are ready to run the simulation and analyze your results You often do this by adding signals to the Wave window and running the simulation for a given period of time See the ModelSim Tutorial for examples ModelSim User s Manual v6 2g 87 February 2007 Projects The Project Tab Other Basic Project Operations Open an Existing Project If you previously exited ModelSim with a project open ModelSim automatically will open that same project upon startup You
443. rtuals do file in the local directory If you have virtual signals displayed in the Wave or List window when you save the Wave or List format you will need to execute the virtuals do file or some other equivalent to restore the virtual signal definitions before you re load the Wave or List format during a later run There is one exception implicit virtuals are automatically saved with the Wave or List format Implicit and Explicit Virtuals An implicit virtual is a virtual signal that was automatically created by ModelSim without your knowledge and without you providing a name for it An example would be if you expand a bus in the Wave window then drag one bit out of the bus to display it separately That action creates a one bit virtual signal whose definition is stored in a special location and is not visible in the Objects pane or to the normal virtual commands All other virtual signals are considered explicit virtuals Virtual Functions Virtual functions behave in the GUI like signals but are not aliases of combinations or elements of signals logged by the kernel They consist of logical operations on logged signals and can be dependent on simulation time They can be displayed in the Objects Wave and List windows and accessed by the examine command but cannot be set by the force command Examples of virtual functions include the following e afunction defined as the inverse of a given signal e afunction defined as the exc
444. ry 2007 Verilog PLI VPI DPI PLI VPI Tracing The Purpose of Tracing Files The purpose of the logfile is to aid you in debugging PLI or VPI code The primary purpose of the replay facility is to send the replay files to support for debugging co simulation problems or debugging PLI VPI problems for which it is impractical to send the PLI VPI code We still need you to send the VHDL Verilog part of the design to actually execute a replay but many problems can be resolved with the trace only Invoking a Trace To invoke the trace call vsim with the trace_foreign argument Syntax vsim trace_foreign lt action gt tag lt name gt Arguments lt action gt Can be either the value 1 2 or 3 Specifies one of the following actions Table D 5 Values for lt action gt Argument Operation Result create log only writes a local file called mti_trace_ lt tag gt create replay only writes local files called mti_data_ lt tag gt c mti init tag c mti replay tag c and mti top tag c create both log and writes all above files replay tag lt name gt Used to give distinct file names for multiple traces Optional Examples vsim trace foreign 1 mydesign Creates a logfile vsim trace foreign 3 mydesign Creates both a logfile and a set of replay files vsim trace foreign 1 tag 2 mydesign Creates a logfile with a tag of 2 ModelSim User s Manual v6 2g 399 February 2007 Ver
445. s 000002 e eee Registering DPI Applications 2 20 2 eee DPI Use FLOW ssc diveesensathsacaddve Se RE E pedos When Your DPI Export Function is Not Getting Called Simplified Import of FLI PLI C Library Functions Use Model for Read Only Work Libraries Compiling and Linking C Applications for PLI VPI DPI For all UNIX Platforms 12224 ERR ER ESI REST RE Windows Platforms lu oov sud ex n doces nde rae dn 32 bit Linux Platform 1 2 2 0 ee eee ee eee 64 bit Linux for IA64 Platform 000 4 64 bit Linux for Opteron Athlon 64 and EM64T Platforms 32 bit Solaris Platform le eee 64 bit Solaris Platform e 32 bit HP700 Platform l l 64 bit HP Platform eese RR 64 bit HP for IA64 Platform 00 0 0 0 0 0 ee eee 32 bit IBM RS 6000 Platform 0 0000 64 bit IBM RS 6000 Platform 0 0 0 0 08 Compiling and Linking C Applications for PLI VPI DPI Windows Platforms 0 000 cee RII 32 bit Linux Platform sse 64 bit Linux for IA64 Platform 000 64 bit Linux for Opteron Athlon 64 and EM64T Platforms 32 bit Solaris Platform 0 0 00 cee ee ee eee 64 bit Solaris Platform 0 0 eee eee eee 32 bit HP700 Platform 2 22 ss ase cesses RR DER RES 64 bit HP Platform 232224 ha RE REDDE PER E REP 64 bit HP for IA64 Plat
446. s an optional argument Syntax if expr1 then body elseif expr2 then body2 elseif else bodyN Description The if command evaluates expr as an expression The value of the expression must be a boolean a numeric value where 0 is false and anything else is true or a string value such as true or yes for true and false or no for false if it is true then body is executed by passing it to the Tcl interpreter Otherwise expr2 is evaluated as an expression and if it is true then body2 is executed and so on If none of the expressions evaluates to true then bodyN is executed The then and else arguments are optional noise words to make the command easier to read There may be any number of elseif clauses including zero BodyN may also be omitted as long as else is omitted too The return value from the command is the result of the body script that was executed or an empty string if none of the expressions was non zero and there was no bodyN Command Substitution Placing a command in square brackets will cause that command to be evaluated first and its results returned in place of the command An example is set a 25 set b 11 setc 3 echo the result is expr a b c will output the result is 12 This feature allows VHDL variables and signals and Verilog nets and registers to be accessed using examine lt radix gt name The name substitution is no longer supported Everywhere name could be used y
447. s in a library or package that are to be visible within a design unit during compilation A use clause references the compiled version of the package not the source By default every VHDL design unit is assumed to contain the following declarations LIBRARY std work USE std standard all To specify that all declarations in a library or package can be referenced add the suffix all to the library package name For example the use clause above specifies that all declarations in the package standard in the design library named std are to be visible to the VHDL design unit ModelSim User s Manual v6 2g 105 February 2007 Design Libraries Specifying the Resource Libraries immediately following the use clause Other libraries or packages are not visible unless they are explicitly specified using a library or use clause Another predefined library is work the library where a design unit is stored after it is compiled as described earlier There is no limit to the number of libraries that can be referenced but only one library is modified during compilation Alternate IEEE Libraries Supplied The installation directory may contain two or more versions of the IEEE library e ieeepure Contains only IEEE approved packages accelerated for ModelSim e ieee Contains precompiled Synopsys and IEEE arithmetic packages which have been accelerated by Model Technology including math complex math real numeric bit numeric std std l
448. s in the List Window eleseeeee eee 195 Working with Markers Se oso s es eed ebook ee ERR RII OS E RER ER MERE 195 Zooming the Wave Window Display seseeeeeeee III 196 Zooming with the Menu Toolbar and Mouse 0 0 0 0 cee eee ee eee 196 Saving Zoom Range and Scroll Position with Bookmarks 0000 197 Searching in the Wave and List Windows sleeeeeeeeeeeeee eee 198 ModelSim User s Manual v6 2g 7 February 2007 Finding Signal Names Searching for Values or Transitions Using the Expression Builder for Expression Searches Formatting the Wave Window Setting Wave Window Display Preferences Formatting Objects in the Wave Window Dividing the Wave Window Splitting Wave Window Panes Creating a Wave Group Deleting or Ungrouping a Wave Group Adding Items to an Existing Wave Group Removing Items from an Existing Wave Group Miscellaneous Wave Group Features Formatting the List Window Setting List Window Display Properties Formatting Objects in the List Window Saving the Window Format Printing and Saving Waveforms in the Wave window Saving a eps Waveform File and Printing in UNIX Printing from the Wave Window on Windows Platforms Printer Page Setup Saving List Window Data to a File Combining Objects into Buses Configuring New Line Triggering in the List Window Using Gating Expressions to Control Triggering Sampling Signals at a Clock Change Miscellaneous Tasks Examining Waveform Values
449. s on a release Moving backwards on a release may not work if the models used compiler switches directives language constructs or features that do not exist in the older release 106 ModelSim User s Manual v6 2g February 2007 Design Libraries Importing FPGA Libraries Note You don t need to regenerate the std ieee vital22b and verilog libraries Also you cannot use the refresh option to update libraries that were built before the 4 6 release Maintaining 32 and 64 bit Versions in the Same Library ModelSim allows you to maintain 32 bit and 64 bit versions of a design in the same library To do this you must compile the design with the 32 bit version and then refresh the design with the 64 bit version For example Using the 32 bit version of ModelSim vlog file1 v file2 v forcecode work asic lib Next using the 64 bit version of ModelSim vlog work asic lib refresh This allows you to use either version without having to do a refresh Do not compile the design with one version and then recompile it with the other If you do this ModelSim will remove the first module because it could be stale Importing FPGA Libraries ModelSim includes an import wizard for referencing and using vendor FPGA libraries The wizard scans for and enforces dependencies in the libraries and determines the correct mappings and target directories D MEME The FPGA libraries you import must be pre compiled Most FPGA vendors
450. sable signal spy disable signal spy enable signal spy S enable signal spy init signal driver init signal driver init signal spy Sinit signal spy signal force signal force signal release signal release Designed for Testbenches Signal Spy limits the portability of your code HDL code with Signal Spy procedures or tasks works only in ModelSim not other simulators We therefore recommend using Signal Spy only ModelSim User s Manual v6 2g 239 February 2007 Signal Spy in testbenches where portability is less of a concern and the need for such a tool is more applicable 240 ModelSim User s Manual v6 2g February 2007 Signal Spy disable signal spy disable signal spy The disable signal spy procedure disables the associated init signal spy The association between the disable signal spy call and the init signal spy call is based on specifying the same src object and dest object arguments to both functions The disable signal spy call can only affect init signal spy calls that had their control state argument set to 0 or 1 Syntax disable signal spy src object dest object lt verbose gt Returns Nothing Arguments e src object Required string A full hierarchical path or relative downward path with reference to the calling block to a VHDL signal or Verilog register net This path should match the path that was specified in the init signal spy call that you wish to disable
451. set Prefixes if 2 or more C Never Show Dataset Prefixes OK Cancel Hiding Showing Path Hierarchy You can set how many elements of the object path display by changing the Display Signal Path value in the Wave Window Preferences dialog Figure 8 11 Zero indicates the full path while a non zero number indicates the number of path elements to be displayed Setting the Timeline to Count Clock Cycles You can set the timeline of the Wave window to count clock cycles rather than elapsed time If the Wave window is docked in the MDI frame open the Wave Window Preferences dialog by selecting Tools Options Wave Preferences from the Main window menus If the Wave window is undocked select Tools Window Preferences from the Wave window menus This opens the Wave Window Preferences dialog In the dialog select the Grid amp Timeline tab Figure 8 12 ModelSim User s Manual v6 2g 203 February 2007 Waveform Analysis Formatting the Wave Window Figure 8 12 Grid amp Timeline Tab of Wave Window Preferences Dialog Wave Window Preferences x Display Grid amp Timeline bl Grid Configuration Grid Offset M Minimum Grid Spacing o ns 40 Grid Period 34 20 ht Reset to Default r Timeline Configuration Display simulation time in timeline area Display grid period count cycle count DK Cancel Enter the period of your clock in the G
452. set automatically sets the MODEL TECH environment variable to the directory in which the binary executable resides DO NOT SET THIS VARIABLE MODEL TECH TCL The toolset uses the MODEL TECH TCL environment variable to find Tcl libraries for Tcl Tk 8 3 and vsim and may also be used to specify a startup DO file This variable defaults to modeltech tcl however you may set it to an alternate path MGC LOCATION MAP The toolset uses the MGC LOCATION MAP environment variable to find source files based on easily reallocated soft paths MODELSIM The toolset uses the MODELSIM environment variable to find the modelsim ini file The argument consists of a path including the file name An alternative use of this variable is to set it to the path of a project file Project Root Dir Project Name mpf This allows you to use project settings with ModelSim User s Manual v6 2g 315 February 2007 Simulator Variables Environment Variables command line tools However if you do this the mpf file will replace modelsim ini as the initialization file for all tools MODELSIM PREFERENCES The MODELSIM PREFERENCES environment variable specifies the location to store user interface preferences Setting this variable with the path of a file instructs the toolset to use this file instead of the default location your HOME directory in UNIX or in the registry in Windows The file does not need to exist beforehand the toolset will initialize it
453. ss radix data radix etc by creating a DO file With the memory tab active select File Save As The Save memory format dialog box opens where you can specify the name for the saved file By default it is named mem do The file will contain all open memory instances and their formats To load it at a later time select File Load Direct Address Navigation You can navigate to any address location directly by editing the address in the address column Double click on any address type in the desired address and hit Enter The address display scrolls to the specified location Splitting the Memory Contents Pane To split a memory contents window into two screens displaying the contents of a single memory instance so any one of the following select Memories Split Screen if the Memory Contents Pane is docked in the Main window select View Split Screen if the Memory Contents Pane is undocked right click in the pane and select Split Screen from the pop up menu This allows you to view different address locations within the same memory instance simultaneously 58 ModelSim User s Manual v6 2g February 2007 Simulator Windows Figure 2 15 Split Screen View of Memory Contents Memory Panes mem 90000000 00101000 00101001 00101010 00101011 00101100 00101101 00000006 00101110 00101111 00110000 00110001 00110010 00110011 0000000c 00110100 00110101 00110110 00110111 00111000 00111001 00000012 00111010 00111011 0
454. ssociation foo instl a e b f c g named association Any instantiation above will leave pin d unconnected but the first example has a placeholder for the connection Here s another example foo instl e g h foo instl a e b c g d h Suggested actions o Check that there is not an extra comma at the end of the port list e g model a b The extra comma is legal Verilog and implies that there is a third port connection that is unnamed o If you are purposefully leaving pins unconnected you can disable these messages using the nowarnTFMPC argument to vsim ModelSim User s Manual v6 2g 361 February 2007 Error and Warning Messages Enforcing Strict 1076 Compliance VSIM license lost Console output Signal 0 caught Closing vsim vlm child vsim is exiting with code 4 FATAL ERROR in license manager transcript vsim output t Error VSIM license lost attempting to re establish Time 5027 ns Iteration 2 Fatal Unable to kill and restart license process Time 5027 ns Iteration 2 Description ModelSim queries the license server for a license at regular intervals Usually these License Lost error messages indicate that network traffic is high and communication with the license server times out Suggested action Anything you can do to improve network communication with the license server will probably solve or decrease the freque
455. st 0 then Sl lt NOt elsif clk2 event and clk2 2 1 then sl lt s0 delayeg end if end process The best way to debug delta delay problems is observe your signals in the List window There you can see how values change at each delta time Detecting Infinite Zero Delay Loops If a large number of deltas occur without advancing time it is usually a symptom of an infinite zero delay loop in the design In order to detect the presence of these loops ModelSim defines a limit the iteration limit on the number of successive deltas that can occur When ModelSim reaches the iteration limit it issues a warning message The iteration limit default value is 1000 If you receive an iteration limit warning first increase the iteration limit and try to continue simulation You can set the iteration limit from the Simulate gt Runtime Options menu or by modifying the IterationLimit variable in the modelsim ini See Simulator Control Variables for more information on modifying the modelsim ini file If the problem persists look for zero delay loops Run the simulation and look at the source code when the error occurs Use the step button to step through the code and see which signals or variables are continuously oscillating Two common causes are a loop that has no exit or a series of gates with zero delay where the outputs are connected back to the inputs Using the TextlO Package To access the routines in TextIO include the foll
456. stfile design vhd 127 There is no limit on the number of parameters that can be passed to macros but only nine values are visible at one time You can use the shift command to see the other parameters Deleting a File from a do Script To delete a file from a do script use the Tcl file command as follows file delete myfile log This will delete the file myfile log You can also use the transcript file command to perform a deletion transcript file transcript file my file log The first line will close the current log file The second will open a new log file If it has the same name as an existing file it will replace the previous one 308 ModelSim User s Manual v6 2g February 2007 Tcl and Macros DO Files Macros DO Files Making Macro Parameters Optional If you want to make macro parameters optional i e be able to specify fewer parameter values with the do command than the number of parameters referenced in the macro you must use the argc simulator state variable The arge simulator state variable returns the number of parameters passed The examples below show several ways of using argc Example 1 This macro specifies the files to compile and handles 0 2 compiler arguments as parameters If you supply more arguments ModelSim generates a message switch Sarge 0 vcom filel vhd file2 vhd file3 vhd 1 vcom 1 filel vhd file2 vhd file3 vhd 2 vcom 1 2 filel vhd file2 vhd file3 vhd default echo T
457. string A full hierarchical path or relative downward path with reference to the calling block to a VHDL signal or Verilog register net This path should match the path that was specified in the init signal spy call that you wish to enable e verbose Optional integer Possible values are 0 or 1 Specifies whether you want a message reported in the transcript stating that an enable occurred and the simulation time that it occurred Default is 0 no message Related procedures init_signal_spy disable_signal_spy Example See init_signal_spy Example 242 ModelSim User s Manual v6 2g February 2007 Signal Spy init signal driver init signal driver The init signal driver procedure drives the value of a VHDL signal or Verilog net called the src object onto an existing VHDL signal or Verilog net called the dest object This allows you to drive signals or nets at any level of the design hierarchy from within a VHDL architecture e g a testbench The init signal driver procedure drives the value onto the destination signal just as if the signals were directly connected in the HDL code Any existing or subsequent drive or force of the destination signal by some other means will be considered with the init signal driver value in the resolution of the signal Call only once The init signal driver procedure creates a persistent relationship between the source and destination signals Hence you need to call init signal driver
458. supply pre compiled libraries configured for use with ModelSim To import an FPGA library select File Import Library ModelSim User s Manual v6 29 107 February 2007 Design Libraries Importing FPGA Libraries Figure 4 4 Import Library Wizard Import Library Wizard Follow the instructions in the wizard to complete the import 108 ModelSim User s Manual v6 2g February 2007 Chapter 5 VHDL Simulation This chapter describes how to compile optimize and simulate VHDL designs in ModelSim It also discusses using the TextIO package with ModelSim ModelSim s implementation of the VITAL VHDL Initiative Towards ASIC Libraries specification for ASIC modeling and ModelSim s special built in utilities package The TextIO package is defined within the VHDL Language Reference Manual IEEE Std 1076 it allows human readable text input from a declared source within a VHDL file during simulation Basic VHDL Flow Simulating VHDL designs with ModelSim includes four general steps 1 Compile your VHDL code into one or more libraries using the vcom command See Compiling VHDL Files for details 2 Load your design with the vsim command See Simulating VHDL Designs for details 3 Run and debug your design Compiling VHDL Files Creating a Design Library for VHDL Before you can compile your source files you must create a library in which to store the compilation results Use vlib to create a new library For
459. t 210 drag from Wave to Transcript 210 removing items from existing 210 ungrouping 210 Wave Log Format WLF file 175 wave log format WLF file see also WLF files wave viewer Dataflow window 228 Wave window 72 187 docking and undocking 72 188 in the Dataflow window 228 saving layout 213 timeline display clock cycles 203 see also windows Wave window waveform logfile overview 175 see also WLF files waveforms 175 optimize viewing of 340 viewing 72 WaveSignalNameWidth ini file variable 339 WIDTH matching to Verilog 271 windows Active Processes pane 47 Dataflow window 49 225 toolbar 50 zooming 229 List window 53 190 display properties of 211 formatting HDL items 211 saving data to a file 214 setting triggers 217 219 Locals window 55 Main window 36 status bar 44 text editing 404 time and delta display 44 toolbar 45 Memory window 56 monitor 70 Objects window 60 Signals window ModelSim User s Manual v6 2g February 2007 ABCDEFGHI VHDL and Verilog items viewed in 60 Source window 62 text editing 404 viewing HDL source code 62 Variables window VHDL and Verilog items viewed in 55 Wave window 72 187 adding HDL items to 191 cursor measurements 192 display preferences 202 display range zoom changing 196 format file saving 213 path elements changing 339 time cursors 192 zooming 196 WLF file parameters cache size 178 collapse mode 178 compression 177 dele
460. t 1 0 force data in 0 0 force clk 0 0 run 100 force clk 1 0 0 50 repeat 100 run 100 vcd off force reset 0 0 force data in 1 0 run 100 vcd on run 850 force reset 1 0 run 50 vcd checkpoint quit sim VCD Output The VCD file created as a result of the preceding scenario would be called output vcd The following pages show how it would look ModelSim User s Manual v6 29 February 2007 283 Value Change Dump VCD Files VCD File from Source To Output 284 Sdate Thu Sep 18 11 07 43 2003 Send Svers ion ModelSim Version 6 1 Send Stimescale in Send S scope module var var var Svar Svar Svar Svar Svar Svar Svar Svar Svar wire 1 wire 1 wir wire 1 wire 1 wire 1 wire 1 wire 1 wire 1 wire 1 wire 1 wire Supscope Se Senddefinitions end 0 Sdump 0 Od 0 0 0 amp 0 0 0 O O 0 end 100 1 150 0 200 1 Vars Sdumpoff x x xi x xX X amp x x x x xt X o9 i Tox 8 MO O Q9 9 Q0 Q Q OQ nd shifter mod Send clk Send reset Send data in Send 8 OrFRNWA UO I Send Send Send Send Send Send Send Send Send ModelSim User s Manual v6 2g February 2007 Value Change Dump VCD Files VCD File from Source To Output Send 500 550 600 l 750 800
461. t Simulator Resolution in the Simulate dialog box Available resolutions are 1x 10x or 100x of fs ps ns us ms or sec For example this command chooses 10 ps resolution vsim t 10ps topmod Clearly you need to be careful when doing this type of operation If the resolution set by t is larger than a delay value in your design the delay values in that design unit are rounded to the closest multiple of the resolution In the example above a delay of 4 ps would be rounded to 0 ps 114 ModelSim User s Manual v6 2g February 2007 VHDL Simulation Simulating VHDL Designs Choosing the Resolution for VHDL You should choose the coarsest resolution limit possible that does not result in undesired rounding of your delays The time precision should not be unnecessarily small because it will limit the maximum simulation time limit and it will degrade performance in some cases Default Binding By default ModelSim performs default binding when you load the design with vsim The advantage of performing default binding at load time is that it provides more flexibility for compile order Namely entities don t necessarily have to be compiled before other entities architectures which instantiate them However you can force ModelSim to perform default binding at compile time This may allow you to catch design errors e g entities with incorrect port lists earlier in the flow Use one of these two methods to change when default binding occu
462. t Window Dragging a group from the Wave window to the Transcript window will result in a list of all of the items within the group being added to the existing command line if any Formatting the List Window Setting List Window Display Properties Before you add objects to the List window you can set the window s display properties To change when and how a signal is displayed in the List window select Tools List Preferences from the List window menu bar when the window is undocked Figure 8 19 Modifying List Window Display Properties Modify Display Properties list xj Window Properties Triggers BE Signal Names fo Path Elements 0 for Full Path Max Title Rows 5 Dataset Prefix C Always Show Dataset Prefixes Show Dataset Prefixes if 2 or more C Never Show Dataset Prefixes Always undock list windows OK Cancel Apply Formatting Objects in the List Window You can adjust various properties of objects to create the view you find most useful Select one or more objects and then select View gt Signal Properties from the List window menu bar when the window is undocked Changing Radix base for the List Window One common adjustment is changing the radix base of an object When you select View gt Signal Properties the List Signal Properties dialog appears Figure 8 20 ModelSim User s Manual v6 2g 211 February 2007 Waveform Analysis Formatting the List Window Figure 8 20 List
463. t goal Finally we assume that you have worked the appropriate lessons in the ModelSim Tutorial and are familiar with the basic functionality of ModelSim The ModelSim Tutorial is available from the ModelSim Help menu Sections In This Document In addition to this introduction you will find the following major sections in this document Chapter 3 Projects This chapter discusses ModelSim projects a container for design files and their associated simulation properties Chapter 4 Design Libraries To simulate an HDL design using ModelSim you need to know how to create compile maintain and delete design libraries as described in this chapter Chapter 5 VHDL Simulation This chapter is an overview of compilation and simulation for VHDL within the ModelSim environment Chapter 6 Verilog and SystemVerilog Simulation This chapter is an overview of compilation and simulation for Verilog and SystemVerilog within the ModelSim environment Chapter 7 WLF Files Datasets and Virtuals This chapter describes datasets and virtuals both methods for viewing and organizing simulation data in ModelSim Chapter 8 Waveform Analysis This chapter describes how to perform waveform analysis with the ModelSim Wave and List windows Chapter 9 Tracing Signals with the Dataflow Window This chapter describes how to trace signals and assess causality using the ModelSim Dataflow window ModelSim User s Manual v6 2g 29 F
464. t s value at the end of a simulation time step only Opening Datasets To open a dataset do one of the following e Select File gt Open and choose Log Files or use the dataset open command Figure 7 2 Open Dataset Dialog Box Open Dataset x m Dataset Pathname Po gh Browse gt Logical Name for Dataset DK Cancel The Open Dataset dialog includes the following options e Dataset Pathname Identifies the path and filename of the WLF file you want to open e Logical Name for Dataset This is the name by which the dataset will be referred By default this is the name of the WLF file 178 ModelSim User s Manual v6 2g February 2007 Viewing Dataset Structure Each dataset you open creates a structure tab in the Main window workspace The tab is labeled with the name of the dataset and displays a hierarchy of the design units in that dataset WLF Files Datasets and Virtuals Viewing Dataset Structure The graphic below shows three structure tabs one for the active simulation sim and one each for two datasets test and gold Figure 7 3 Structure Tabs in Workspace Pane ini x EH acc test ringbuf gf clock B rina INST block AM block2 A block3 Mf standard gj std logic 1154 Mf std logic arith lf std logic unsigned Workspace l1 ON ScModule ScModule ScModule Architecture Module Module test_ringbuf sc clock rinabuf control r
465. t vhd top vhd 96 vsim top VSIM 1 vcd dumpports file proc vcd top p VSIM 2 gt vcd dumpports file cache vcd top c VSIM 3 gt vcd dumpports file memory vcd top m VSIM 4 run 1000 VSIM 5 gt quit f ModelSim User s Manual v6 2g 279 February 2007 Value Change Dump VCD Files Using Extended VCD as Stimulus Next rerun each module separately using the captured VCD stimulus 96 vsim vcdstim proc vcd proc do add wave run 1000 VSIM 1 gt quit f 9o vsim vcdstim cache vcd cache do add wave run 1000 VSIM 1 gt quit f 96 vsim vcdstim memory vcd memory do add wave run 1000 VSIM 1 gt quit f Replacing Instances with Output Values from a VCD File Replacing instances with output values from a VCD file lets you simulate without the instance s source or even the compiled object The general procedure includes two steps 1 Create VCD files for one or more instances in your design using the vcd dumpports command If necessary use the vcdstim switch to handle port order problems see below 2 Re simulate your design using the vcdstim instance filename argument to vsim Note that this works only with VCD files that were created by a ModelSim simulation Example 12 4 Replacing Instances In the following example the three instances top p top c and top m are replaced in simulation by the output values found in the corresponding VCD files First create VCD files for all instances
466. tAction variable If the variable 1s defined its action will be invoked 3 If neither 1 or 2 is true the macro aborts Using the Tcl Source Command with DO Files Either the do command or Tcl source command can execute a DO file but they behave differently With the source command the DO file is executed exactly as if the commands in it were typed in by hand at the prompt Each time a breakpoint is hit the Source window is updated to show the breakpoint This behavior could be inconvenient with a large DO file containing many breakpoints When a do command is interrupted by an error or breakpoint it does not update any windows and keeps the DO file locked This keeps the Source window from flashing scrolling and moving the arrow when a complex DO file is executed Typically an onbreak resume command is used to keep the macro running as it hits breakpoints Add an onbreak abort command to the DO file if you want to exit the macro and update the Source window ModelSim User s Manual v6 2g 311 February 2007 Tcl and Macros DO Files Macros DO Files 312 ModelSim User s Manual v6 29 February 2007 Appendix A Simulator Variables This appendix documents the following types of variables Environment Variables Variables referenced and set according to operating system conventions Environment variables prepare the ModelSim environment prior to simulation Simulator Control Variables Variables used to control compi
467. tal track in the cursor pane selects that cursor and moves it to the mouse position Cursors snap to a waveform edge if you click or drag a cursor along the selected waveform to within ten pixels of a waveform edge You can set the snap distance in the Window Preferences dialog Select Tools Options Wave Preferences when the Wave window is docked in the Main window MDI frame Select Tools Window Preferences when the Wave window is a stand alone undocked window You can position a cursor without snapping by dragging in the cursor pane below the waveforms ModelSim User s Manual v6 2g February 2007 Waveform Analysis Setting Time Markers in the List Window Jumping to a Signal Transition You can move the active cursor to the next or previous transition on the selected signal using these two buttons on the toolbar Find Previous Find Next Transition Je Transition l locate the next signal locate the previous value change for the signal value change selected signal for the selected signal Setting Time Markers in the List Window Time markers in the List window are similar to cursors in the Wave window Time markers tag lines in the data table so you can quickly jump back to that time Markers are indicated by a thin box surrounding the marked line Figure 8 6 Time Markers in the List Window Ipi xi 1 sim test sm out El Ez list Fie Edit view Add Tools Window 495000 0 suu nin niana 0010
468. td ModelSim follows by default using the VHDL93 variable VHDL93 variable selects language version as the default Default is VHDL 2002 Value of 0 or 1987 for VHDL 1987 Value of 1 or 1993 for VHDL 1993 Default or value of 2 or 2002 for VHDL 2002 VHDL93 2002 Opening VHDL Files You can delay the opening of VHDL files with an entry in the ZMI file if you wish Normally VHDL files are opened when the file declaration is elaborated If the DelayFileOpen option is enabled then the file is not opened until the first read or write to that file vsim DelayFileOpen 1 348 ModelSim User s Manual v6 2g February 2007 Simulator Variables Variable Precedence Variable Precedence Note that some variables can be set in a modelsim file Registry in Windows or a ini file A variable set in the modelsim file takes precedence over the same variable set in a ini file For example assume you have the following line in your modelsim ini file TranscriptFile transcript And assume you have the following line in your modelsim file set PrefMain file In this case the setting in the modelsim file overrides that in the modelsim ini file and a transcript file will not be produced Simulator State Variables Unlike other variables that must be explicitly set simulator state variables return a value relative to the current simulation Simulator state variables can be useful in commands especially wh
469. tdout from the simulation kernel TMPDIR UNIX environments The TMPDIR environment variable specifies the path to a tempnam generated file VSOUT containing all stdout from the simulation kernel Creating Environment Variables in Windows In addition to the predefined variables shown above you can define your own environment variables This example shows a user defined library path variable that can be referenced by the vmap command to add library mapping to the modelsim ini file 1 From your desktop right click your My Computer icon and select Properties 2 In the System Properties dialog box select the Advanced tab 3 Click Environment Variables 4 In the Environment Variables dialog box and User variables for user pane select New ModelSim User s Manual v6 2g 317 February 2007 Simulator Variables Environment Variables 5 In the New User Variable dialog box add the new variable with this data Variable ame MY PATH Variable value temp work 6 OK New User Variable Environment Variable and System Properties dialog boxes Library Mapping with Environment Variables Once the MY PATH variable is set you can use it with the vmap command to add library mappings to the current modelsim ini file Table A 1 Add Library Mappings to modelsim ini File Prompt Type Command Result added to modelsim ini DOS prompt vmap MY VITAL MY_PATH MY VITAL c temp work ModelSim or vmap MY VITAL MY_PATH MY VITAL MY
470. te on quit 178 filename 177 optimization 177 overview 177 size limit 177 time limit 177 WLF files collapsing events 182 optimizing waveform viewing 340 saving 176 saving at intervals 182 WLFCacheSize ini file variable 339 WLFCollapseMode ini file variable 340 WLFCompress ini variable 340 WLFDeleteOnQuit ini variable 340 WLFFilename ini file variable 340 WLFSaveAllRegions ini variable 340 WLESizeLimit ini variable 341 WLFTimeLimit ini variable 341 work library 100 creating 101 workspace 37 WRITE procedure problems with 120 x X tracing unknowns 231 ModelSim User s Manual v6 29 February 2007 Xdefaults file controlling fonts 36 X session controlling fonts 36 A zero delay elements 116 zero delay mode 163 zero delay loop infinite 118 zero delay oscillation 118 zero delay race condition 154 zoom Dataflow window 229 saving range with bookmarks 197 zooming window panes 414 JKLMNOPQRSTUVWXYZ 441 ABCDEFGHIJKLMNOPQRSTUVWXYZ 442 ModelSim User s Manual v6 29 February 2007 Third Party Information This section provides information on third party software that may be included in the ModelSim product including any additional license terms e This product may include Valgrind third party software Julian Seward All rights reserved THIS SOFTWARE IS PROVIDED BY THE AUTHOR AS IS AND ANY EXPRESS OR IMPLIED WARRANTIES INCLUDING BUT NOT LIMITED TO THE IMPLIED
471. ted and imported tasks and functions Though the dpiheader h is a user convenience file rather than requirement including dpiheader h in your C code can immediately solve problems 370 ModelSim User s Manual v6 2g February 2007 Verilog PLI VPI DPI DPI Use Flow caused by an improperly defined interface An example command for creating the header file would be vlog dpiheader lt dpiheader gt h files v 2 Required for Windows only Run a preliminary invocation of vsim with the dpiexportobj argument Because of limitations with the linker loader provided on Windows this additional step is required You must create the exported task function compiled object file exportobj by running a preliminary vsim command such as vsim dpiexportobj exportobj top 3 Include the dpiheader h file in your C code ModelSim recommends that any user DPI C code that accesses exported tasks functions or defines imported tasks functions will include the dpiheader h file This allows the C compiler to verify the interface between C and ModelSim 4 Compile the C code into a shared object Compile your code providing any a or other o files required For Windows users In this step the object file needs to be bound together with the obj that you created using the dpiexportobj argument into a single dll file 5 Simulate the design When simulating specify the name of the imported DPI C shared object according to the SystemVerilog LR
472. tes the pseudo machine code ModelSim uses for simulation e Step 4 Simulating a Design This specifies the design unit you want to simulate and opens a structure tab in the Workspace pane 82 ModelSim User s Manual v6 2g February 2007 Projects Getting Started with Projects Step 1 Creating a New Project Select File New Project to create a new project This opens the Create Project dialog where you can specify a project name location and default library name You can generally leave the Default Library Name set to work The name you specify will be used to create a working library subdirectory within the Project Location This dialog also allows you to reference library settings from a selected ini file or copy them directly into the project Figure 3 1 Create Project Dialog Create Project xi Project Name proj Project Location Ic Tutorial examples Browse Default Library Name work Copy Settings From modelsim ini Browse Copy Library Mappings Reference Library Mappings OK Cancel After selecting OK you will see a blank Project tab in the Workspace pane of the Main window Figure 3 2 Figure 3 2 Project Tab in Workspace Pane Workspace and the Add Items to the Project dialog Figure 3 3 ModelSim User s Manual v6 2g 83 February 2007 Projects Getting Started with Projects Figure 3 3 Add items to the Project Dialog X m Click on the icon
473. tf rosynchronize tf irosynchronize tf scale longdelay tf scale realdelay tf setdelay tf isetdelay tf setlongdelay tf isetlongdelay tf setrealdelay tf isetrealdelay tf setworkarea tf isetworkarea tf sizep tf isizep tf spname tf ispname tf strdelputp tf istrdelputp tf strgetp tf istrgetp tf strgettime tf strlongdelputp tf istrlongdelputp tf strrealdelputp tf istrrealdelputp tf subtract long tf synchronize tf isynchronize tf testpvc flag tf itestpvc flag tf text tf typep tf itypep tf unscale longdelay tf unscale realdelay tf warning tf write save SystemVerilog DPI Access Routines ModelSim SystemVerilog supports all routines defined in the svdpi h file defined in P1800 2005 ModelSim User s Manual v6 29 February 2007 397 Verilog PLI VPI DPI Verilog XL Compatible Routines Verilog XL Compatible Routines The following PLI routines are not defined in IEEE Std 1364 but ModelSim Verilog provides them for compatibility with Verilog XL char acc decompile exp handle condition This routine provides similar functionality to the Verilog XL acc decompile expr routine The condition argument must be a handle obtained from the acc handle condition routine The value returned by acc decompile exp is the string representation of the condition expression char tf dumpfilename void This routine returns the name of the VCD file void tf dumpflush void A call to this routi
474. th 1 downto 0 addr IN unsigned addr width 1 DOWNTO 0 IS BEGIN mem to integer addr data END IMPURE FUNCTION read addr IN unsigned addr width 1 DOWNTO 0 RETURN std logic vector IS BEGIN return mem to integer addr END END PROTECTED BODY mem type 132 ModelSim User s Manual v6 2g February 2007 VHDL Simulation Modeling Memory SHARED VARIABLE memory mem type BEGIN ASSERT data width 32 REPORT Illegal data width detected SEVERITY failure control proc PROCESS inclk outclk BEGIN IF inclk event AND inclk 1 THEN IF we 1 THEN memory write data in addr END IF END IF IF outclk event AND outclk 1 THEN data out memory read addr END IF END PROCESS END intarch Source ram tb vhd Component VHDL testbench for RAM memory exampl Remarks Simple VHDL example random access memory RAM LIBRARY ieee USE ieee std logic 1164 ALL USE ieee numerioc std ALL ENTITY ram tb IS END ram tb ARCHITECTURE testbench OF ram tb IS Component declaration single port RAM COMPONENT sp syn ram protected GENERIC data width positive 8 addr width positive 3 PORT inclk IN std logic outclk IN std logic we IN std logic addr IN unsigned addr width 1 DOWNTO 0 data in IN std logic vector data width 1 DOWNTO 0 data out OUT std logic vector data width 1
475. the DPI application as follows vsim sv_lib dpiapp1 sv_lib dpiapp2 sv_lib dpiappn top It is a mistake to specify DPI import tasks and functions tf inside PLI VPI shared objects However a DPI import tf can make calls to PLI VPI C code providing that vsim gblso was used to mark the PLI VPI shared object with global symbol visibility See Loading Shared Objects with Global Symbol Visibility Loading Shared Objects with Global Symbol Visibility On Unix platforms you can load shared objects such that all symbols in the object have global visibility To do this use the gblso argument to vsim when you load your PLI VPI application For example vsim pli obj1 so pli obj2 so gblso obj1 so top The gblso argument works in conjunction with the GlobalSharedObjectList variable in the modelsim ini file This variable allows user C code in other shared objects to refer to symbols in a shared object that has been marked as global All shared objects marked as global are loaded by the simulator earlier than any non global shared objects PLI Example The following example is a trivial but complete PLI application hello c ModelSim User s Manual v6 2g 387 February 2007 Verilog PLI VPI DPI VPI Example include veriuser h static PLI INT32 hello io printf Hi there n return 0 S tfcell veriusertfs 0 0 O hello 0 Shello 0 last entry must be 0 usertask hello v module hello in
476. the design together by connecting the ports and resolving hierarchical references Using SDF You can incorporate actual delay values to the simulation by applying SDF back annotation files to the design For more information on how SDF is used in the design see Specifying SDF Files for Simulation Step 4 Simulating the Design Once the design has been successfully loaded the simulation time is set to zero and you must enter a run command to begin simulation For more information see Verilog and System Verilog Simulation and VHDL Simulation The basic simulator commands are e add wave e force e bp e run e step Step 5 Debugging the Design Numerous tools and windows useful in debugging your design are available from the ModelSim GUI In addition several basic simulation commands are available from the command line to assist you in debugging your design describe drivers 26 ModelSim User s Manual v6 2g February 2007 Introduction Modes of Operation examine force e log e show Modes of Operation Many users run ModelSim interactively pushing buttons and or pulling down menus in a series of windows in the GUI graphical user interface But there are really three modes of ModelSim operation the characteristics of which are outlined in the following table Table 1 2 Use Modes ModelSim use Characteristics How ModelSim is invoked mode interactive has graphical via a desktop icon
477. the mirroring of values is enabled disabled is handled by the S enable signal spy and disable signal spy tasks We recommend that you place all Sinit signal spy tasks in a Verilog initial block See the example below Syntax init signal spy src object dest object verbose control state Returns Nothing Arguments src object Required string A full hierarchical path or relative downward path with reference to the calling block to a VHDL signal or Verilog register net Use the path separator to which your simulation is set i e or A full hierarchical path must begin with a or The path must be contained within double quotes e dest object Required string A full hierarchical path or relative downward path with reference to the calling block to a Verilog register or VHDL signal Use the path separator to which your simulation is set 1 e or A full hierarchical path must begin with a or The path must be contained within double quotes e verbose Optional integer Possible values are 0 or 1 Specifies whether you want a message reported in the Transcript stating that the src_object s value is mirrored onto the dest_object Default is 0 no message 256 ModelSim User s Manual v6 2g February 2007 Signal Spy init signal spy e control state Optional integer Possible values are 1 0 or 1 Specifies whether or not you want the ability to enable disable mirro
478. the reg being updated and new is the updated value Table 6 2 Evaluation 1 of always Statements q 0 gt 1 1 2 p 0 1 2 p 0 gt 1 3 2 3 clk 0 gt 1 2 clk 0 gt 1 4 2 2 p2 1 gt 0 ModelSim User s Manual v6 2g 155 February 2007 Verilog and SystemVerilog Simulation Simulating Verilog Designs Table 6 2 Evaluation 1 of always Statements cont Event being processed Active event queue p2 1 gt 0 3 3 clk 1 gt 0 clk 1 gt 0 lt empty gt Table 6 3 Evaluation 2 of always Statement q 0 gt 1 1 2 p 0 1 2 p2 1 gt 0 p 0 gt 1 p 0 gt 1 3 p2 1 gt 0 p2 1 0 3 3 empty clk doesn t change Again both evaluations are valid However in Evaluation 1 clk has a glitch on it in Evaluation 2 clk doesn t This indicates that the design has a zero delay race condition on clk Controlling Event Queues with Blocking or Non Blocking Assignments The only control you have over event order is to assign an event to a particular queue You do this via blocking or non blocking assignments Blocking Assignments Blocking assignments place an event in the active inactive or future queues depending on what type of delay they have e ablocking assignment without a delay goes in the active queue e ablocking assignment with an explicit delay of 0 goes in the inactive queue e a blocking assignment with a non zero delay
479. the same value as MODEL TECH OVERRIDE 2 Finds the modelsim ini file by evaluating the following conditions use MODELSIM modelsim ini if it exists else e use MGC_PWD modelsim ini else e use modelsim ini else e use MODEL_TECH modelsim ini else e use MODEL TECH modelsim ini else e use MGC HOMEVlib modelsim ini else e set path to modelsim ini even though the file doesn t exist 3 Finds the location map file by evaluating the following conditions e use MGC LOCATION MAP if it exists if this variable is set to no map ModelSim skips initialization of the location map else ModelSim User s Manual v6 2g 421 February 2007 System Initialization Initialization Sequence 10 11 12 13 422 e userngc location map if it exists else e use HOME mgc mgc location map else e use HOME mgc location map else e use MGC HOMEYyetc mgc location map else e use MGC HOMEYys5shared etc mgc location map else e use MODEL TECHymgc location map else e use MODEL TECH mgc location map else e use no map Reads various variables from the vsim section of the modelsim ini file See Simulation Control Variables for more details Parses any command line arguments that were included when you started ModelSim and reports any problems Defines the following environment variables e use MODEL TECH TCL if it exists else e set MODEL TECH TCL MODEL TECH y tcl e set TCL_LIBRAR
480. the simulator ModelSim User s Manual v6 29 27 February 2007 Introduction Standards Supported vsim c top library and design loading messages then execute transcript on force clk 1 50 0 100 repeat 100 run 500 run 85000 quit f Rename transcript files that you intend to use as DO files They will be overwritten the next time you run vsim if you don t rename them Also simulator messages are already commented out but any messages generated from your design and subsequently written to the transcript file will cause the simulator to pause A transcript file that contains only valid simulator commands will work fine comment out anything else with a Stand alone tools pick up project settings in command line mode if they are invoked in the project s root directory If invoked outside the project directory stand alone tools pick up project settings only if you set the MODELSIM environment variable to the path to the project file Project Root Dir Project Name mpf Batch Mode Batch mode is an operational mode that provides neither an interactive command line nor interactive windows In a Windows environment vsim is run from a Windows command prompt and standard input and output are redirected from and to files Here is an example of a batch mode simulation using redirection of std input and output vsim counter yourfile outfile where yourfile is a script containing various ModelSim commands
481. the value for each cursor and the right pane shows the absolute time value for each cursor and relative time between cursors Up to 20 cursors can be displayed See Measuring Time with Cursors in the Wave Window for more information Wave Window Toolbar The Wave window toolbar in the undocked Wave window gives you quick access to these ModelSim commands and functions Button Table 2 10 Wave Window Toolbar Buttons and Menu Selections Open Dataset open a previously saved dataset Menu equivalent File Open Other options File Open from Main window when Transcript window sim tab is active Save Format save the current Wave window display and signal preferences to a DO macro file Print print a user selected range of the current Wave window display to a printer or a file File Save File Print File Print Postscript none Export Waveform export a created waveform Cut cut the selected signal from the Wave window File gt Export gt Waveform Edit Cut right mouse in pathname pane Cut Copy copy the signal selected in the pathname pane Edit Copy right mouse in pathname pane Copy 76 Paste paste the copied signal above another selected signal Find find a name or value in the Wave window Edit Paste Edit Find right mouse in pathname pane Paste lt control f gt Windows control s UNIX ModelSim User s Manual v
482. thm ModelSim uses to calculate delays for delayed nets isn t described in IEEE Std 1364 Rather ModelSim matches Verilog XL behavior The algorithm attempts to find a set of delays so the data net is valid when the clock net transitions and the timing checks are satisfied The algorithm is iterative because a set of delays can be selected that satisfies all timing checks for a pair of inputs but then causes mis ordering of another pair where both pairs of inputs share a common input When a set of delays that satisfies all timing checks is found the delays are said to converge Using Delayed Inputs for Timing Checks By default ModelSim performs timing checks on inputs specified in the timing check If you want timing checks performed on the delayed inputs use the delayed timing checks argument with the vsim command ModelSim User s Manual v6 2g 159 February 2007 Verilog and SystemVerilog Simulation Simulating Verilog Designs Consider an example This timing check setuphold posedge clk posedge t 20 12 NOTIFIER clk dly t dly reports a timing violation when posedge f occurs in the violation region 20 12 With the delayed_timing_checks argument the violation region between the delayed inputs is t dly clk dly Although the check is performed on the delayed inputs the timing check violation message is adjusted to reference the undelayed inputs Only the report time of the violation message is noticeably differ
483. tion or if from subprogram line from which call is made print character ModelSim User s Manual v6 2g 329 February 2007 Simulator Variables Simulator Control Variables e Default S R n Time T Iteration D I n AssertionFormatBreak This variable defines the format of messages for VHDL assertions that trigger a breakpoint e Value Range Refer to Table A 2 e Default S R n Time T Iteration WD 96K i File F n AssertionFormatError This variable defines the format of messages for VHDL Error assertions If undefined AssertionFormat is used unless assertion causes a breakpoint in which case AssertionFormatBreak is used e Value Range Refer to Table A 2 Default S R n Time T Iteration WD K i File F n AssertionFormatFail This variable defines the format of messages for VHDL Fail assertions If undefined AssertionFormat is used unless assertion causes a breakpoint in which case AssertionFormatBreak is used e Value Range Refer to Table A 2 Default S R n Time T Iteration WD K i File F n AssertionFormatFatal This variable defines the format of messages for VHDL Fatal assertions If undefined AssertionFormat is used unless assertion causes a breakpoint in which case AssertionFormatBreak is used e Value Range Refer to Table A 2 Default S R n Time T Iteration WD K i File F n AssertionFormatNote This variable defines the
484. tity testbench is end architecture only of testbench is signal clk0 std logic begin gen clkO0 process begin clkO lt 1 after 0 ps O after 20 ps wait for 40 ps end process gen clk0 drive sig process process begin init signal driver clk0 testbench uut blk1l clk open open 1 init signal driver clk0 testbench uut blk2 clk 100 ps mti transport wait end process drive sig process end 244 ModelSim User s Manual v6 2g February 2007 Signal Spy init signal spy init signal spy The init signal spy procedure mirrors the value of a VHDL signal or Verilog register net called the src object onto an existing VHDL signal or Verilog register called the dest object This allows you to reference signals registers or nets at any level of hierarchy from within a VHDL architecture e g a testbench The init signal spy procedure only sets the value onto the destination signal and does not drive or force the value Any existing or subsequent drive or force of the destination signal by some other means will override the value that was set by init signal spy Call only once The init signal spy procedure creates a persistent relationship between the source and destination signals Hence you need to call init signal spy once for a particular pair of signals Once init signal spy is called any change on the source signal will mirror on the destination signal unt
485. tive Processes Pane Active Processes Ready IMPLICIT WIRE clk 130 test_sm Ready IMPLICIT WIRE rst 130 test sm Ready IMPLICIT WIRE into 130 test_sm Ready HINITIALH test sm Ready HINITIALH81 test sm Ready INITIALH107 test sm Ready HIMPLICIT wIRE in rea 31 28 H30 test sm sm seq Readu HIMPLICIT AWIRE fnutafltt21 stest sm sm senh ModelSim User s Manual v6 2g 47 February 2007 Simulator Windows Call Stack Pane Process Status Each object in the scrollbox is preceded by one of the following indicators Ready Indicates that the process is scheduled to be executed within the current delta time If you select a Ready process it will be executed next by the simulator Wait Indicates that the process is waiting for a VHDL signal or Verilog net or variable to change or for a specified time out period Done Indicates that the process has executed a VHDL wait statement without a time out or a sensitivity list The process will not restart during the current simulation run Call Stack Pane The Call Stack pane displays the current call stack when you single step your simulation or when the simulation has encountered a breakpoint When debugging your design you can use the call stack data to analyze the depth of function calls which include Verilog functions and tasks and VHDL functions and procedures that led up to the current point of the simulation
486. tl store retrieve standard Package std_logic_1 Package std_logic_arith Package std logic un Package acc lt full gt acc lt full gt acc lt full gt acc lt none gt acc full acc lt full gt acc acc v acc v acc v lest ringbuf ScMethod test ringbuf ScMethod test ringbuf ScMethod test ringbuf ScMethod lest ringbuf ScMethod TE pae If you have too many tabs to display in the available space you can scroll the tabs left or right by clicking the arrow icons at the bottom right hand corner of the window reset generator generate data wd compare data print error print restore Click here to scroll tabs Structure Tab Columns Each structure tab displays three columns by default Table 7 2 Structure Tab Columns Instance the name of the instance Design unit the name of the design unit ModelSim User s Manual v6 29 179 February 2007 WLF Files Datasets and Virtuals Managing Multiple Datasets Table 7 2 Structure Tab Columns cont Design unit type the type e g Module Entity etc of the design unit You can hide or show columns by right clicking a column name and selecting the name on the list Managing Multiple Datasets GUI When you have one or more datasets open you can manage them using the Dataset Browser To open the browser select File Datasets Figure 7 4 The Dataset Browser x Dataset Conte Mode Pathname com
487. to comply with the provisions of Sections 1 2 or 4 For any other material breach under this Agreement Mentor Graphics may terminate this Agreement upon 30 days written notice if you are in material breach and fail to cure such breach within the 30 day notice period If Software was provided for limited term use this Agreement will automatically expire at the end of the authorized term Upon any termination or expiration you agree to cease all use of Software and return it to Mentor Graphics or certify deletion and destruction of Software including all copies to Mentor Graphics reasonable satisfaction EXPORT Software is subject to regulation by local laws and United States government agencies which prohibit export or diversion of certain products information about the products and direct products of the products to certain countries and certain persons You agree that you will not export any Software or direct product of Software in any manner without first obtaining all necessary approval from appropriate local and United States government agencies RESTRICTED RIGHTS NOTICE Software was developed entirely at private expense and is commercial computer software provided with RESTRICTED RIGHTS Use duplication or disclosure by the U S Government or a U S Government subcontractor is subject to the restrictions set forth in the license agreement under which Software was obtained pursuant to DFARS 227 7202 3 a or as set forth in subparagraphs c
488. to display on rising edges only you have two options 1 Turn off the List window triggering on the clock signal and then define a repeating strobe for the List window 2 Define a gating expression for the List window that requires the clock to be in a specified state See above Miscellaneous Tasks Examining Waveform Values You can use your mouse to display a dialog that shows the value of a waveform at a particular time You can do this two ways e Rest your mouse pointer on a waveform After a short delay a dialog will pop up that displays the value for the time at which your mouse pointer is positioned If you d prefer that this popup not display it can be toggled off in the display properties See Setting Wave Window Display Preferences e Right click a waveform and select Examine A dialog displays the value for the time at which you clicked your mouse This method works in the List window as well Displaying Drivers of the Selected Waveform You can automatically display in the Dataflow window the drivers of a signal selected in the Wave window You can do this three ways e Select a waveform and click the Show Drivers button on the toolbar Select a waveform and select Show Drivers from the shortcut menu e Double click a waveform edge you can enable disable this option in the display properties dialog see Setting Wave Window Display Preferences This operation opens the Dataflow window and displays the drivers
489. to use archives In this case each design unit is stored in its own archive file To create an archive use the archive argument to the vlib command Generally you would do this only in the rare case that you hit the reference count limit on I nodes due to the entries in the lower level directories the maximum number of sub directories on UNIX and Linux is 65533 An example of an error message that is produced when this limit is hit is mkdir cannot create directory 65534 Too many links Archives may also have limited value to customers seeking disk space savings Note d GMAKE won t work with these archives on the IBM platform Working with Design Libraries The implementation of a design library is not defined within standard VHDL or Verilog Within ModelSim design libraries are implemented as directories and can have any legal name allowed by the operating system with one exception extended identifiers are not supported for library names 100 ModelSim User s Manual v6 2g February 2007 Design Libraries Working with Design Libraries Creating a Library When you create a project refer to Getting Started with Projects ModelSim automatically creates a working design library If you don t create a project you need to create a working design library before you run the compiler This can be done from either the command line or from the ModelSim graphic interface From the ModelSim prompt or a UNIX DOS prompt
490. ts The PLI ACC routines also provide limited support for VHDL objects in either an all VHDL design or a mixed VHDL Verilog design The following table lists the VHDL objects for which handles may be obtained and their type and fulltype constants Table D 2 Supported VHDL Objects accArchitecture Fulltype accArchitecture Description instantiation of an architecture accArchitecture accArchitecture accEntity VitalLevelO accArchVitalLevelO instantiation of an architecture whose entity is marked with the attribute VITAL_Level0 instantiation of an architecture which is marked with the attribute VITAL LevelO accArchitecture accArchitecture accArchVitalLevell accForeignArch instantiation of an architecture which is marked with the attribute VITAL Levell instantiation of an architecture which is marked with the attribute FOREIGN and which does not contain any VHDL statements or objects other than ports and generics accArchitecture accForeignArchMixed instantiation of an architecture which is marked with the attribute FOREIGN and which contains some VHDL statements or objects besides ports and generics accBlock accForLoop accBlock accForLoop block statement for loop statement accForeign accShadow foreign scope created by mti CreateRegion accGenerate accPackage accGenerate accPackage generate statement package declaration accSignal
491. type of a design object shows the icon colors and the languages they indicate Table 2 2 Design Object Icons Icon color Design Language light blue Verilog or SystemVerilog dark blue VHDL orange virtual object Here is a list of icon shapes and the design object types they indicate Table 2 3 Icon Shapes and Design Object Types icon shape example design object type square any scope VHDL block Verilog named block SC module class interface task function etc circle 2 process valued object signals nets registers etc diamond an editable waveform created with the waveform editor with red dot star transaction The color of the star for each transaction depends on the language of the region in which the transaction stream occurs dark blue for VHDL light blue for Verilog and SystemVerilog green for SystemC magenta for PSL Setting Fonts You may need to adjust font settings to accommodate the aspect ratios of wide screen and double screen displays or to handle launching ModelSim from an X session Font Scaling To change font scaling select Tools Options Adjust Font Scaling You ll need a ruler to complete the instructions in the lower right corner of the dialog When you have entered the pixel and inches information click OK to close the dialog Then restart ModelSim to see the change This is a one time setting you shouldn t have to set it again unless you change disp
492. ugh part of a simulation may yield a slightly different WLF file than just running over that piece of code If particular detail is required in debugging you should disable time collapsing Virtual Objects Virtual objects are signal like or region like objects created in the GUI that do not exist in the ModelSim simulation kernel ModelSim supports the following kinds of virtual objects Virtual Signals Virtual Functions Virtual Regions Virtual Types Virtual objects are indicated by an orange diamond as illustrated by bus in Figure 7 6 ModelSim User s Manual v6 2g 183 February 2007 WLF Files Datasets and Virtuals Virtual Objects Figure 7 6 Virtual Objects Indicated by Orange Diamond 15x File Edit view Add Format Tools Window Jee BeN p test sm into p est sm outof 4 jtest sm rst 34 test sm clk 1 test sm rd O test_sm vr_ 4 jtest sm clk 4 4 33 downto 2 test sm i 4 4 18800 ps to 23200 ps Now 750 ns Delta 2 Virtual Signals Virtual signals are aliases for combinations or subelements of signals written to the WLF file by the simulation kernel They can be displayed in the Objects List and Wave windows accessed by the examine command and set using the force command You can create virtual signals using the Tools gt Combine Signals Wave and List windows menu selections or by using the virtual signal command Once created virtual signals can be dragged an
493. ulator as it loads the design Note Resource libraries are specified differently for Verilog and VHDL For Verilog you use either the L or Lf argument to vlog Refer to Library Usage for more information VHDL Resource Libraries Within a VHDL source file you use the VHDL library clause to specify logical names of one or more resource libraries to be referenced in the subsequent design unit The scope of a library clause includes the text region that starts immediately after the library clause and extends to the end of the declarative region of the associated design unit It does not extend to the next design unit in the file Note that the library clause is not used to specify the working library into which the design unit is placed after compilation The vcom command adds compiled design units to the current working library By default this is the library named work To change the current working library you can use vcom work and specify the name of the desired target library Predefined Libraries Certain resource libraries are predefined in standard VHDL The library named std contains the packages standard and textio which should not be modified The contents of these packages and other aspects of the predefined language environment are documented in the JEEE Standard VHDL Language Reference Manual Std 1076 Refer also to Using the TextIO Package A VHDL use clause can be specified to select particular declaration
494. ulator state variable 350 numeric bit package 106 numeric std package 106 disabling warning messages 347 NumericStdNoWarnings ini file variable 336 ec object defined 30 objects virtual 183 Objects window 60 see also windows Objects window operating systems supported See Installation Guide optimizations VHDL subprogram inlining 110 Optimize 1164 ini file variable 326 ordering files for compile 89 organizing projects with folders 92 organizing windows MDI pane 42 ModelSim User s Manual v6 2g February 2007 ABCDEFGH I others ini file variable 321 overview simulation tasks 22 P packages standard 105 textio 105 util 124 VITAL 1995 123 VITAL 2000 123 page setup Dataflow window 235 Wave window 214 pan Dataflow window 229 panes docking and undocking 413 Memory panes 56 parameters making optional 309 using with macros 308 path delay mode 163 path delays matching to DEVICE statements 269 path delays matching to GLOBALPATHPULSE statements 269 path delays matching to IOPATH statements 268 path delays matching to PATHPULSE statements 269 pathnames hiding in Wave window 203 PATHPULSE matching to specify path delays 269 PathSeparator ini file variable 336 PedanticErrors ini file variable 326 performance cancelling scheduled events 136 PERIOD matching to Verilog 271 platforms supported See Installation Guide PLI loading shared objects with global symbol visi
495. umber 177 empty port name warning 359 exit codes 357 getting more information 355 lock message 359 long description 355 message system variables 344 metavalue detected 360 redirecting 338 sensitivity list warning 360 suppressing warnings from arithmetic packages 347 Tcl init error 360 too few port connections 361 turning off assertion messages 347 VSIM license lost 362 warning suppressing 356 metavalue detected warning 360 MGC LOCATION MAP env variable 353 MGC LOCATION MAP variable 315 MinGW gcc 375 381 missing DPI import function 400 MODEL TECH environment variable 315 MODEL TECH TCL environment variable 315 modeling memory in VHDL 128 MODELSIM environment variable 315 modelsim ini found by the tool 421 default to VHDL93 348 delay file opening with 348 environment variables in 346 force command default setting 348 hierarchical library mapping 346 opening VHDL files 348 431 ABCDEFGH I restart command defaults setting 348 startup file specifying with 347 transcript file created from 346 turning off arithmetic package warnings 347 turning off assertion messages 347 modelsim tcl 417 modelsim_lib 124 path to 320 MODELSIM_PREFERENCES variable 316 417 MODELSIM_TCL environment variable 316 modes of operation 27 Modified field Project tab 89 modules handling multiple common names 144 Monitor window grouping ungrouping objects 71 monitor window 70 mouse shortcuts Main
496. ument as that essentially disables the width check Note too that you cannot override the threshold argument via SDF annotation Table 6 6 IEEE Std 1364 System Tasks Display tasks PLA modeling tasks Value change dump VCD file tasks display async and array dumpall 164 ModelSim User s Manual v6 2g February 2007 Verilog and SystemVerilog Simulation System Tasks and Functions Table 6 6 IEEE Std 1364 System Tasks cont Display tasks PLA modeling tasks Value change dump VCD file tasks displayb async nand array dumpfile displayh async or array dumpflush displayo async nor array dumplimit monitor async and plane dumpoff monitorb async nand plane dumpon monitorh async or plane dumpvars monitoro async nor plane monitoroff sync and array monitoron sync nand array strobe sync or array strobeb sync nor array strobeh sync and plane strobeo sync nand plane write sync or plane writeb sync nor plane writeh writeo Table 6 7 IEEE Std 1364 File I O Tasks File I O tasks fclose fmonitoro fwriteh fdisplay fopen fwriteo fdisplayb fread readmemb fdisplayh fscanf readmemh fdisplayo fseek rewind feof fstrobe sdf_annotate ferror fstrobeb sformat fflush fstrobeh sscanf fgetc fstrobeo swrite ModelSimUsers Manual V amp 2g 00 465 February 2007 Verilog and SystemVerilog Simulation System Tasks and Functions Table 6 7 I
497. ursors extend a vertical line over the waveform display and identify a specific simulation time Multiple cursors can be used to measure time intervals as shown in the graphic below When the Wave window is first drawn there is one cursor located at time zero Clicking anywhere in the waveform display brings that cursor to the mouse location The selected cursor is drawn as a bold solid line all other cursors are drawn with thin lines As shown in the graphic below three window panes relate to cursors the cursor name pane on the bottom left the cursor value pane in the bottom middle and the cursor pane with horizontal tracks on the bottom right 192 ModelSim User s Manual v6 2g February 2007 Waveform Analysis Measuring Time with Cursors in the Wave Window Figure 8 5 Cursor Names Values and Time Measurements M wave default SAROIA 2 Eile Edit yew Add Format Tools Window amp test_counter clk test_countet reset g test_counter count 4 434260 ns tp Now 495 85 jns Delta 2 right click here locked cursor is red to name cursor Working with Cursors The table below summarizes common cursor actions Table 8 1 Actions for Cursors Menu command Menu command Toolbar button Wave window docked Wave window undocked Add cursor Add gt Wave gt Cursor Add gt Cursor Delete cursor Wave gt Delete Cursor Edit gt Delete Cursor Zoom In on Wave gt Zoom gt Zoom View gt
498. user data PLI INT32 MyEndOfCompCB p cb data cb data p PLI INT32 MyStartOfSimCB p cb data cb data p void RegisterMySystfs void vpiHandle tmpH S cb data callback S vpi systf data systf data systf data type vpiSysFunc systf data sysfunctype vpiSizedFunc systf data tfname Smyfunc systf_data calltf MyFuncCalltf systf_data compiletf MyFuncCompiletf systf_data sizetf MyFuncSizetf systf_data user_data 0 tmpH vpi register systf amp systf data vpi free object tmpH callback reason cbEndOfCompile callback cb rtn MyEndOfCompCB callback user data 0 tmpH vpi register cb amp callback vpi free object tmpH callback reason cbStartOfSimulation callback cb rtn MyStartOfSimCB callback user data 0 tmpH vpi register cb amp callback vpi free object tmpH void vlog_startup_routines RegisterMySystfs 0 last entry must be 0 Loading VPI applications into the simulator is the same as described in Registering PLI Applications 368 ModelSim User s Manual v6 2g February 2007 Verilog PLI VPI DPI Registering DPI Applications Using PLI and VPI Together PLI and VPI applications can co exist in the same application object file In such cases the applications are loaded at startup as follows e If an init_usertfs function exists then it is executed and only those system tasks
499. ve defaultName Creates a new wave window with the provided name defaults to Wave proc named_wave name Wave set newWav view new wave if string length Sname gt 0 wm title SnewWave nam Writes out format of all wave windows stores geometry and title info in windowSet do file Removes any extra files with the same fileroot Default file name is wave lt n gt starting from 1 ModelSim User s Manual v6 2g 305 February 2007 Tcl and Macros DO Files Tcl Examples proc save wave fileroot wave global vsimPriv set n 1 if catch open windowSet_ fileroot do w 755 fileId error Open failure for fileroot fileId foreach w vsimPriv WaveWindows echo Saving wm title w set filename fileroot n do if file exists S filename Use different file set n2 0 while file exists fileroot S n n2 do incr n2 set filename fileroot S n n2 do write format wave window w filename puts SfileId wm title Sw wm title w N puts fileId wm geometry w wm geometry w puts fileId mtiGrid colconfig w grid name width mtiGrid colcget w grid name width puts fileId mtiGrid colconfig w grid value width mtiGrid colcget w grid value width flush SfileId incr n foreach f lsort glob nocomplain fileroot n 9 do echo Removing f
500. veform pane of the Wave window These zoom buttons are available on the toolbar Zoom In 2x Zoom Out 2x zoom in by a factor of two zoom out by a factor of two from the current view from current view Zoom In on Active Cursor Zoom Full centers the active cursor in zoom out to view the full the waveform display and a range of the simulation from zooms in time 0 to the current time Zoom Mode 4 change mouse pointer to zoom mode see below To zoom with the mouse first enter zoom mode by selecting View gt Zoom gt Mouse Mode gt Zoom Mode The left mouse button then offers 3 zoom options by clicking and dragging in different directions e Down Right or Down Left Zoom Area In e Up Right Zoom Out Up Left Zoom Fit Also note the following about zooming with the mouse 196 ModelSim User s Manual v6 2g February 2007 Waveform Analysis Zooming the Wave Window Display e The zoom amount is displayed at the mouse cursor A zoom operation must be more than 10 pixels to activate e You can enter zoom mode temporarily by holding the Ctrl key down while in select mode e With the mouse in the Select Mode the middle mouse button will perform the above zoom operations Saving Zoom Range and Scroll Position with Bookmarks Bookmarks save a particular zoom range and scroll position This lets you return easily to a specific view later You save the bookmark with a name and then access the named bookmark from the Bookma
501. w Ctrl Shift Right Arrow extend text selection by one word Up Arrow Down Arrow Transcript Pane scroll through command history Source Window move cursor one line up or down Ctrl Up Arrow Ctrl Down Arrow Transcript Pane moves cursor to first or last line Source Window moves cursor up or down one paragraph Ctrl Home move cursor to the beginning of the text Ctrl End move cursor to the end of the text Backspace Ctrl h UNIX only Delete Ctrl d UNIX only delete character to the left delete character to the right Esc Windows only cancel Alt activate or inactivate menu bar mode Alt F4 close active window Home Ctrl a UNIX only Ctrl b move cursor to the beginning of the line move cursor left Ctrl d delete character to the right End Ctrl e move cursor to the end of the line Ctrl f UNIX Right Arrow Windows move cursor right one character Ctrl k Ctrl n delete to the end of line move cursor one line down Source window only under Windows Ctrl o UNIX only insert a new line character at the cursor Ctrl p ModelSim User s Manual v6 2g February 2007 move cursor one line up Source window only under Windows 405 Command and Keyboard Shortcuts Main and Source Window Mouse and Keyboard Shortcuts Table E 3 Keyboard Shortcuts cont Keystrokes UNIX and Wi
502. will be converted to logical pathnames If a file or path name contains the dollar sign character and must be used in one of the places listed above that accepts environment variables then the explicit dollar sign must be escaped by using a double dollar sign Setting Environment Variables Before compiling or simulating several environment variables may be set to provide the functions described below The variables are set through the System control panel on Windows 2000 and XP machines For UNIX the variables are typically found in the ogin script The LM LICENSE FILE variable is required all others are optional DOPATH The toolset uses the DOPATH environment variable to search for DO files macros DOPATH consists of a colon separated semi colon for Windows list of paths to directories You can override this environment variable with the DOPATH Tcl preference variable The DOPATH environment variable isn t accessible when you invoke vsim from a UNIX shell or from a Windows command prompt It is accessible once ModelSim or vsim is invoked If you need to invoke from a shell or command line and use the DOPATH environment variable use the following syntax vsim do do dofile name design unit EDITOR The EDITOR environment variable specifies the editor to invoke with the edit command HOME The toolset uses the HOME environment variable to look for an optional graphical preference file and optional location
503. within a Verilog module e g a testbench See S init signal driver for complete details init signal spy The Sinit signal spy system task mirrors the value of a VHDL signal or Verilog register net onto an existing Verilog register or VHDL signal This system task allows you to reference signals registers or nets at any level of hierarchy from within a Verilog module e g a testbench See Sinit signal spy for complete details psprintf The S psprintf system function behaves like the sformat file I O task except that the string result is passed back to the user as the function return value for psprintf not placed in the first argument as for sformat Thus psprintf can be used where a string is valid Note that at this time unlike other system tasks and functions psprintf cannot be overridden by a user defined system function in the PLI signal force The signal force system task forces the value specified onto an existing VHDL signal or Verilog register or net This allows you to force signals registers or nets at any level of the design hierarchy from within a Verilog module e g a testbench A signal force works the same as the force command with the exception that you cannot issue a repeating force See signal force for complete details signal release The signal_release system task releases a value that had previously been forced onto an existing VHDL signal or Verilog register or net A
504. wnload and install 3 files from the ftp site These files are modeltech base tar gz modeltech docs tar gz modeltech platform exe gz If you install only the platform file you will not get the Tcl files that are located in the base file This message could also occur if the file or directory was deleted or corrupted e Suggested action Reinstall ModelSim with all three files 360 ModelSim User s Manual v6 2g February 2007 Error and Warning Messages Miscellaneous Messages Too few port connections Warning vsim 3017 foo v 1422 TFMPC Too few port connections Expected 2 found 1 Region foo tb Description This warning occurs when an instantiation has fewer port connections than the corresponding module definition The warning doesn t necessarily mean anything is wrong it is legal in Verilog to have an instantiation that doesn t connect all of the pins However someone that expects all pins to be connected would like to see such a warning Here are some examples of legal instantiations that will and will not cause the warning message Module definition module foo a b c 3 Instantiation that does not connect all pins but will not produce the warning foo instl e f g positional association foo instl a e b f c g d named association Instantiation that does not connect all pins but will produce the warning foo instl e f g positional a
505. wo steps 278 ModelSim User s Manual v6 2g February 2007 Value Change Dump VCD Files Using Extended VCD as Stimulus 1 Create a VCD file for a single design unit using the vcd dumpports command 2 Resimulate the single design unit using the vcdstim argument to vsim Note that vcdstim works only with VCD files that were created by a ModelSim simulation Example 12 1 Verilog Counter First create the VCD file for the single instance using vcd dumpports 96 cd modeltech examples misc 96 vlib work 96 vlog counter v tcounter v 9o vsim test counter VSIM 1 gt vcd dumpports file counter vcd test counter dut VSIM 2 run VSIM 3 gt quit f Next rerun the counter without the testbench using the vcdstim argument 96 vsim vcdstim counter vcd counter VSIM 1 gt add wave VSIM 2 run 200 Example 12 2 VHDL Adder First create the VCD file using ved dumpports 96 cd modeltech examples misc 96 vlib work 96 vcom gates vhd adder vhd stimulus vhd 96 vsim testbench2 VSIM 1 gt vcd dumpports file addern vcd testbench2 uut VSIM 2 run 1000 VSIM 3 gt quit f Next rerun the adder without the testbench using the vcdstim argument 96 vsim vcdstim addern vcd addern gnz8 do add wave run 1000 Example 12 3 Mixed HDL Design First create three VCD files one for each module 96 cd modeltech examples tutorials mixed projects 96 vlib work 96 vlog cache v memory v proc v 96 vcom util vhd se
506. ws you to explore the physical connectivity of your design Note 3 OEM versions of ModelSim have limited Dataflow functionality Many of the features described below will operate differently The window will show only one process and its attached signals or one signal and its attached processes as displayed in Figure 9 1 Figure 9 1 The Dataflow Window undocked z dataflow File Edit View Navigate Trace Tools Window amp X m 4 i BANS AA be 5 X 3e 30 9 AGA amp amp A wl FINITIAL 58 addr_r data r wr 4 b Objects You Can View in the Dataflow Window The Dataflow window displays processes ModelSim User s Manual v6 29 225 February 2007 Tracing Signals with the Dataflow Window Adding Objects to the Window e signals nets and registers The window has built in mappings for all Verilog primitive gates 1 e AND OR etc For components other than Verilog primitives you can define a mapping between processes and built in symbols See Symbol Mapping for details Adding Objects to the Window You can use any of the following methods to add objects to the Dataflow window e drag and drop objects from other windows e use the Navigate menu options in the Dataflow window e use the add dataflow command e double click any waveform in the Wave window display The Navigate menu offers four commands that will add objects to the window The commands include e View regio
507. xported tasks or functions in your design e Suggested Action Make sure that a C compiler is visible from where you are running the simulation Empty port name warning WARNING 8 path file name empty port name in port list e Description ModelSim reports these warnings if you use the lint argument to vlog It reports the warning for any NULL module ports e Suggested action If you wish to ignore this warning do not use the lint argument Lock message waiting for lock by user user Lockfile is library path lock e Description The _lock file is created in a library when you begin a compilation into that library and it is removed when the compilation completes This prevents simultaneous updates to the library If a previous compile did not terminate properly ModelSim may fail to remove the _lock file e Suggested action Manually remove the ock file after making sure that no one else is actually using that library ModelSim User s Manual v6 2g 359 February 2007 Error and Warning Messages Miscellaneous Messages Metavalue detected warning Warning NUMERIC_STD gt metavalue detected returning FALSE e Description This warning is an assertion being issued by the IEEE numeric std package It indicates that there is an X in the comparison e Suggested action The message does not indicate which comparison is reporting the problem since the assertion is coming
508. y MODEL TECH modelsim lib n std Library MODEL_TECH std std_developerskit Library MODEL TECH std developerskit i synopsys Library MODEL_TECH synopsys din e al IMAP mS 8 m oOo d r Design Unit s Resolution default r Optimization v Enable optimization ptimization Options Cancel 2 Specify a name in the Simulation Configuration Name field ModelSim User s Manual v6 2g 91 February 2007 Projects Organizing Projects with Folders 3 Specify the folder in which you want to place the configuration see Organizing Projects with Folders 4 Select one or more design unit s Use the Control and or Shift keys to select more than one design unit The design unit names appear in the Simulate field when you select them 5 Use the other tabs in the dialog to specify any required simulation options Click OK and the simulation configuration is added to the Project tab Figure 3 14 Simulation Configuration in the Project Tab Folder VHDL 06 07 04 07 35 46 PM VHDL 06 07 04 07 36 26 PM Folder Verilog 06 07 04 07 36 21 PM Verilog 06 07 04 07 35 56 PM Double click the Simulation Configuration verilog_sim to load the design Organizing Projects with Folders The more files you add to a project the harder it can be to locate the item you need You can add folders to the project to organize your files These folders are akin to directories in that you can have mult
509. y 2007 Introduction Basic Steps for Simulation Table 1 1 Simulation Tasks Example Command Line GUI Menu Pull down GUI Icons Entry Step 1 vlib library name a File New Project Map libraries vmap work library name b Enter library name c Add design files to project Step 2 vlog filel v file2 v a Compile Compile Compile or Compile the Verilog or Compile All design vcom filel vhd file2 vhd Compile gt Compile All icons VHDL Step 3 vsim lt top gt or a Simulate gt Start Simulate icon Load the vsim lt opt_name gt Simulation design into the b Click on top design E simulator module or optimized design unit name c Click OK This action loads the design for simulation Step 4 Simulate gt Run Run or Run the Run continue or simulation Run all icons Common debugging commands bp describe drivers examine force log show Basic Steps for Simulation This section provides further detail related to each step in the process of simulating your design using ModelSim ModelSim User s Manual v6 2g 23 February 2007 Introduction Basic Steps for Simulation Step 1 Collecting Files and Mapping Libraries Files needed to run ModelSim on your design e design files VHDL and or Verilog including stimulus for the design e libraries both working and resource e modelsim ini automatically created by the library mapping command

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