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Xilinx Virtex-4 User Guide

1. ALMOST FULL OFFSET gt X 000 Sets almost full threshold ALMOST EMPTY OFFSET X 000 Sets the almost empty threshold DATA WIDTH gt 36 Sets data width to 4 9 18 or 36 FIRST WORD FALL THROUGH gt FALSE Sets the FIFO FWFT to TRUE or FALSE port map ALMOSTEMPTY gt ALMOSTEMPTY 1 bit almost empty output flag ALMOSTFULL ALMOSTFULL 1 bit almost full output flag DO DO 32 bit data output DOP DOP 4 bit parity data output EMPTY gt EMPTY 1 bit empty output flag FULL gt FULL 1 bit full output flag RDCOUNT gt RDCOUNT 12 bit read count output RDERR gt RDERR 1 bit read error output WRCOUNT gt WRCOUNT 12 bit write count output WRERR gt WRERR 1 bit write error 146 www xilinx com Virtex 4 User Guide UG070 v1 5 March 21 2006 XILINX FIFO VHDL and Verilog Templates DI gt DI 32 bit data input DIP gt DIP 4 bit partity input RDCLK gt RDCLK 1 bit read clock input RDEN gt RDEN 1 bit read enable input RST gt RST 1 bit reset input WRCLK gt WRCLK 1 bit write clock input WREN gt WREN 1 bit write enable input End of FIFO16 inst instantiation FIFO Verilog Template FIFO16 To incorporate this function into the design the Verilog following instance declaration needs to be placed in instance the body of the design code The
2. synthesis synthesis synthesis synthesis synthesis synthesis synthesis synthesis synthesis BIT O iserdes clkout Q1 Q2 Q30 Q4 Q50 Q6 SHIFTOUT1 SHIFTOUT2 BITSLIP 1 b0 CEl1 1 b1 CE2 1 b1 LK iobclk LKDIV clkdiv clk in LYCE 1 Db0 LYINC 1 b0 LYRST 1 b0 CLK 1 b0 EV 1 b0 HIFTIN1 1 b0 HIFTIN2 1 b0 R rst o uuuougogogoan Jur SLIP ENABLE of fwd clk is FALSE DATA RATE of fwd clk is DDR DATA WIDTH of fwd clk is 4 INTERFACE TYPE of fwd clk is NETWORKING IOB IOBI IOBI NUM SERI DELAY of fwd clk is NONE DELAY TYPE of fwd clk is DEFAULT DELAY VALUE of fwd clk is 0 CE of fwd clk is 1 DES MODE of fwd clk is MASTER Instantiate Master ISERDES for data channel 1 10 Deserialization Factor ISERDES data chan master 00 O1 data internal 0 Q2 data internal 1 Q3 data internal 2 Q4 data internal 3 Q5 data internal 4 Q6 data internal 5 SHIFTOUT1 shiftdatal Virtex 4 User Guide UG070 v1 5 March 21 2006 www xilinx com 363 Chapter 8 Advanced SelectlO Logic Resources Zr XILINX SHIFTOUT2 shiftdata2 BITSLIP 1 b0 El 1 b1 E2 1 b1 LK iobclk Din YCE 1 5b0 LYINC 1 b0 LYRST 1 b0 CLK 1 b0 EV 1 b0
3. loscck Tce TCE __ ff y lt lt SR Tospck T Teme AL X X loscko ra Tosco qe i T TQ ug070_8_16_080204 Figure 8 16 OSERDES 2 1 SDR 3 State Control Serialization Timing Diagram Virtex 4 User Guide www xilinx com 383 UG070 v1 5 March 21 2006 Chapter 8 Advanced SelectlO Logic Resources XILINX Clock Event 1 e Attime Toscck Tcr before Clock Event 1 CLK the output clock enable pin becomes valid high at the TCE input of the OSERDES enabling the output register to transmit data to the TQ output Clock Event 2 e At time Tospcx r before Clock Event 2 CLKDIV data on the T1 and T2 inputs become valid e At time Toscko ro after Clock Event 2 CLK data appears at the TO output Clock Event 3 e Attime Clock Event 3 the reset signal is asserted High an asynchronous reset e Attime Tosco 1o after Clock Event 3 the TQ output is asynchronously reset to zero OSERDES VHDL and Verilog Instantiation Templates The following examples illustrate the instantiation of the OSERDES module in VHDL and Verilog OSERDES VHDL Template Example OSERDES Component Declaration component OSERDES generic DATA RATE OQ string DDR DATA RATE TQ string DDR DATA WIDTH integer 4 INIT OQ bit 0 INIT TQ bit 0 SERDES MODE string MASTER SRVAL OQ bit 0 SRVAL TQ bit 0 TRIS
4. End of FIFO16 1kx18 inst instantiation Virtex 4 User Guide www xilinx com 147 UGO070 v1 5 March 21 2006 Chapter 4 Block RAM XILINX FIFO Timing Models and Parameters Table 4 14 shows the FIFO parameters Table 4 14 FIFO Timing Parameters Parameter Function Setup and Hold Relative to Clock CLK Control Signal Description TpxcK Setup time before clock edge Tpckx Hold time after clock edge The following descriptions are for setup times only TFDCK_D1 Data inputs DI Time before WRCLK that data must be stable at the Trckp pi DI inputs of the FIFO TECCK_RDEN Read enable RDEN Time before RDCLK that Read Enable must be TECKC_RDEN stable at the RDEN inputs of the FIFO TECCK_WREN Write enable WREN Time before WRCLK that write enable must be TECKC_WREN stable at the WREN inputs of the FIFO Sequential Delays Treko po Clock to data output DO Time after RDCLK that the output data is stable at the DO outputs of the FIFO Tgcko AEMPTY Clock to almost empty AEMPTY Timeafter RDCLK that the Almost Empty signal is output stable at the ALMOSTEMPTY outputs of the FIFO Tgcko AFULL Clock to almost full AFULL Time after WRCLK that the Almost Full signal is output stable at the ALMOSTFULL outputs of the FIFO Tgcko EMPTY Clock to empty output EMPTY Timeafter RDCLK that the Empty signal is stable at the EMPTY outputs of the FIFO TECKO_ F
5. parameter RST_DEASSERT_CLK CLKA endmodule Example PMCD instantiation PMCD U_PMCD CLKA1 user clkal CLKA1D2 user clkai1d2 CLKA1D4 user clkaid4 CLKA1D8 user clkal188 CLKB1 user clkb1 CLKC1 user clkc1 CLKD1 user clkd1 CLKA user clka CLKB user clkb CLKC user clkc CLKD user clkd REL user rel RST user rst CLKB1 CLKC1 CLKD1 108 www xilinx com Virtex 4 User Guide UG070 v1 5 March 21 2006 XILINX Chapter 4 Block RAM Block RAM Summary The Virtex 4 block RAMs are similar to the Virtex II and Spartan 3 block RAMs Each block RAM stores 18K bits of data Write and Read are synchronous operations the two ports are symmetrical and totally independent sharing only the stored data Each port can be configured in any aspect ratio from 16Kx1 8Kx2 to 512x36 and the two ports are independent even in this regard The memory content can be defined or cleared by the configuration bitstream During a write operation the data output can either reflect the new data being written or the previous data now being overwritten or the output can remain unchanged New Virtex 4 enhancements of the basic block RAM include e The user can invoke a pipeline register at the data read output still inside the block RAM This allows a higher clock rate at the cost of one additional clock period latency e Two adjacent block RAMs can be comb
6. 2 XILINX UGO70 7 28 080204 Figure 7 28 OLOGIC 3 State Register Timing Characteristics Clock Event 1 At time Torceck before Clock Event 1 the 3 state clock enable signal becomes valid high at the TCE input of the 3 state register enabling the 3 state register for incoming data At time Torck before Clock Event 1 the 3 state signal becomes valid high at the T input of the 3 state register returning the pad to high impedance at time Tocxg after Clock Event 1 Clock Event 2 At time Tosgcy before Clock Event 2 the SR signal configured as synchronous reset in this case becomes valid high resetting the 3 state register at time Tg after Clock Event 2 Figure 7 29 illustrates IOB DDR 3 state register timing This example is shown using DDR in opposite edge mode For other modes add the appropriate latencies as shown in Figure 7 7 page 315 www xilinx com Virtex 4 User Guide UGO070 v1 5 March 21 2006 XILINX OLOGIC Resources 1 2 3 4 5 6 T 8 9 10 11 NM a ww A mae rm g T oroK ug070 7 29 080104 Figure 7 29 OLOGIC ODDR 3 State Register Timing Characteristics Clock Event 1 e At time TorcrcK before Clock Event 1 the 3 state clock enable signal becomes valid High at the TCE input of the ODDR 3 state registers enabling them for incoming data Since the TCE signal is common to all ODDR registers care must be taken to toggle this signal between th
7. C INV OBUF BUFG to IBUFG Figure 2 11 Virtex 4 FPGA DCM_ADV CLKO CLK90 CLK180 CLK270 CLK2X RST CLK2X180 PSINCDEC CLKDV CLKFX CLKFX180 CLKIN CLKFB PSEN PSCLK DADDR 6 0 DI 15 0 DWE LOCKED DEN DO 15 0 DCLK BUFG This circuit can be duplicated to multiple Virtex devices Use CLKDLL for Virtex and Virtex E devices DCM for Virtex Il and Virtex Il Pro devices UGO70 2 11 071204 Board Deskew with Internal Deskew Interfacing to Other Virtex Devices RST Virtex 4 User Guide UGO070 v1 5 March 21 2006 www xilinx com 81 Chapter 2 Digital Clock Managers DCMs XILINX The example in Figure 2 12 shows an interface from Virtex 4 FPGAs to non Virtex devices IBUFG gt IBUFG gt Virtex 4 FPGA DCM_ADV CLKIN CLKO CLK90 CESEB CLK180 CLK270 CLK2X RST CLK2X180 CLKDV PSINCDEC CLKFX PSEN CLKFX180 PSCLK DADDR 6 0 DI 15 0 LOCKED DWE DO 15 DEN O 15 0 DCLK DCM ADV CLKIN CLKO CLK90 CLKFB CLK180 CLK270 RST CLK2X CLK2X180 PSINCDEC CLKDV PSEN CLKFX PSCLK CLKFX180 DADDR 6 0 DI 15 0 DWE DEN LOCKED DCLK DO 15 0 Voc BUFG 4 gt LGND BUFG ODDR D1 Q C hon Virtex chips UGO070 2 12 072604 Figure 2 12 Board Deskew with Internal Deskew Interfacing to Non Virtex Devices 82 www xilinx com
8. parameter DATA RATE OQ parameter DATA RATE TQ parameter DATA WIDTH parameter INIT OQ 1 b0 parameter INIT TQ 1 b0 parameter SERDES MODE MASTER parameter SRVAL OQ 1 b0 parameter SRVAL TQ 1 b0 parameter TRISTATE WIDTH 4 DDR DDR e output OQ output SHIFTOUT1 output SHIFTOUT2 output TQ CLKDIV D1 D2 TCI Virtex 4 User Guide UGO070 v1 5 March 21 2006 www xilinx com 385 Chapter 8 Advanced SelectlO Logic Resources XILINX input CLK input CLKDIV input D1 input D2 input D3 input D4 input D5 input D6 tri0 GSR glbl GSR input OCE input REV input SHIFTIN1 input SHIFTIN2 input SR input T1 input T2 input T3 input T4 input TCE endmodule Example OSERDES instantiation OSERDES U OSERDES OQ user oq SHIFTOUT1 user shiftout1 SHIFTOUT2 user shiftout2 TO user tq CLK user clk CLKDIV user clkdiv D1 user d1 D2 user 32 D3 user d3 DA4 user d4 D5 user d5 D6 user d6 OCE user oce REV user rev SHIFTIN1 user shiftinl SHIFTIN2 user shiftin2 SR user sr T1 user t1 T2 user t2 T3 user t3 T4 user t4 TCE user tce 386 www xilinx com Virtex 4 User Guide UGO070 v1 5 March 21 2006 XILINX Chapter 9 Temperature Sensing Diode Temperature Sensing Diode TDP TDN
9. DIFF HSTL Il DCI 18 DIFF HSTL Il DCI 18 2Rypp 2297 1000 2Rypy 2Zg 1002 IOB IOB 2Rypp 2Zg 1002 2Rypy 2Zg 1000 DIFF_HSTL_II_DCI_18 DIFF HSTL Il DCI 18 Veco 1 8V 2Rypp 2Zg 1000 2Rypy 2Zg 1000 UJ AAAA M A 51 9 2 4 2Rypp 2Zo 1002 2Rypy 2Zg 1002 DIFF_HSTL_II_DCI_18 Figure 6 55 Differential HSTL 1 8V Class II DCI Bidirectional Termination Virtex 4 User Guide ug070_6_53_071904 Table 6 21 lists the differential HSTL Class II 1 8V DC voltage specifications DIFF HSTL Il DCI 18 Table 6 21 Differential HSTL Class Il 1 8V DC Voltage Specifications Min Typ Max Vcco 1 7 1 8 1 9 Ver Veco x 0 5 Vin DC 0 30 Veco 0 30 Voter DC 0 20 Veco 0 60 Vem DC 0 78 1 12 Vprrr AC 0 40 Veco 0 60 Vx Crossover 0 78 1 12 Notes 1 Common mode voltage Vem Vp Vp Vn 2 2 Crossover point Vy where Vp Vy 0 AC coupled UG070 v1 5 March 21 2006 www xilinx com 263 Chapter 6 SelectlO Resources XILINX HSTL Class III 1 8V Figure 6 56 shows a sample circuit illustrating a valid termination technique for HSTL Class III 1 8V External Termination Var 1 8V IOB 10B HSTL Ill 18 HSTL III 18 Rp Zo 500 53 0 x Dj Vesey 4 L DCI Ra IOB IO
10. 0 0 cee cece he hh teen ees 67 Input Clock Requirements escicn esa iai e eens 68 Input Glock Changes see bebe aene wae x deduc emiten aai 68 Qutpu t Clocks iia tet acte sete bates dH acere dte E E a erede edes 69 DCM During Configuration and Startup 6 6 6c ee ees 69 Deskew Adjust eerie e ded diced date Bld cet eed eas cae 70 Characteristics of the Deskew Circuit 0 0 nuanua nunnan nanena 71 Frequency Synthesis er tirik onsin iaa e i e a ae E 71 Frequency Synthesis Operation esee 71 Frequency Synthesizer Characteristics s ansann ee eens 72 Phase Shifting esee unte eee epe PI e was pla te ol e ted ced tel E tne gach 72 Phase Shifting Operation lt i c g eere daos ee de nct eee aped ron 72 Interaction of PSEN PSINCDEC PSCLK and PSDONE 2 0 0c cee 74 Phase Shift Overflow 0 0 0 0 ccc ccc ehh 75 Phase Shift Characteristics 0 eee ehh rare 76 Dynamic Reconfiguration 0 0 6 66 nn 76 Connecting DCMs to Other Clock Resources in Virtex 4 Devices 77 IBUEG to DEM iii eH eee RH IRE pe e e E bus i a ae ee 77 DEM t BUFGETRE sns codes ae erie dias e ide ee ditus antes ey RE RE 77 BUEFGCTREt19 DCM 4rd odbuce bt o Pa etit due ded ac eid Diete deos 77 DCM To arid From PMCGCD 4er oh reed n Cene piesa eie de du dos 77 Application Examples jis ors ce bua Ext ER REIR IA e UE e d OC gi eet 77 Standard Usage sess epasle tov a saaat bagea RAE OR RR ORA Seb e a ges 78
11. O Before A X O After x X ug070 7 12 080104 Figure 7 12 DELAY Timing Diagram Clock Event 1 e At time Tycgcy before Clock Event 1 CE is valid high enabling the IDELAY to increment or decrement e Attime Tgwccy before Clock Event 1 INC is valid high to increment IDELAY e Attime Tjypgr AYRESOLUTION after Clock Event 1 the next clock after increment or decrement O After is sampling data at the next tap in the delay element Clock Event 2 e Attime TypstcK before Clock Event 2 the reset configured synchronously is set to valid High e At the next clock after RST O After is sampling data at the tap specified by the IOBDELAY VALUE attribute In this example IOBDELAY VALUE 0 IDELAY VHDL and Verilog Instantiation Template VHDL and Verilog instantiation templates are available in the Libraries Guide for all primitives and submodules In VHDL each template has a component declaration section and an architecture section Each part of the template should be inserted within the VHDL design file The port map of the architecture section should include the design signals names VHDL for Zero Hold Time Delay Mode The following VHDL code shows how to instantiate the IDELAY module in a zero hold time delay mode Module IDELAY Description VHDL instantiation template Zero Hold Time Mode Device Virtex 4 Family 324 www xilinx com Virtex 4 User Guide UG070 v1 5 March 21 2006 2 X
12. 1x Output Clock CLKO The CLKO output clock provides a clock with the same frequency as the DCM s effective CLKIN frequency By default the effective input clock frequency is equal to the CLKIN frequency The CLKIN DIVIDE BY 2 attribute is set to True to make the effective CLKIN frequency the actual CLKIN frequency The CLKIN DIVIDE BY 2 Attribute description provides further information When CLKFB is connected CLKO is phase aligned to CLKIN 1x Output Clock 90 Phase Shift CLK90 The CLK90 output clock provides a clock with the same frequency as the DCM s CLKO only phase shifted by 90 1x Output Clock 180 Phase Shift CLK180 The CLK180 output clock provides a clock with the same frequency as the DCM s CLKO only phase shifted by 180 1x Output Clock 270 Phase Shift CLK270 The CLK270 output clock provides a clock with the same frequency as the DCM s CLKO only phase shifted by 270 2x Output Clock CLK2X The CLK2X output clock provides a clock that is phase aligned to CLKO with twice the CLKO frequency and with an automatic 50 50 duty cycle correction Until the DCM is locked the CLK2X output appears as a 1x version of the input clock with a 25 75 duty cycle This behavior allows the DCM to lock on the correct edge with respect to the source clock Virtex 4 User Guide www xilinx com 59 UGO070 v1 5 March 21 2006 Chapter 2 Digital Clock Managers DCMs XILINX 2x Output Clock 180 Phase Shift CLK2
13. Ro Rygw Rypp o T2 020 t4 ug070 6 31 071904 Figure 6 31 Controlled Impedance Driver with Half Impedance Unidirectional Termination IOB 10B LVDCI_DV2 LVDCI_DV2 Ro Ayan Rypp Zo Ro Rypy Rypp o l l lt x l l l l l l ug070_6_32_071904 Figure 6 32 Controlled Impedance Driver with Half Impedance Bidirectional Termination Virtex 4 User Guide www xilinx com 241 UG070 v1 5 March 21 2006 Chapter 6 SelectlO Resources XILINX There are no drive strength settings for LVDCI drivers When the driver impedance is one half of the VRN VRP reference resistors it is indicated by the addition of DV2 to the attribute name Table 6 5 lists the LVCMOS LVDCI and LVDCI DV2 voltage specifications Table 6 5 LVCMOS LVDCI and LVDCI DV2 DC Voltage Specifications at Various Voltage References UT 3 3V 2 5V 1 8V 1 5V Min Typ Max Min Typ Max Min Typ Max Min Typ Max Vin V 2 0 3 6 17 27 119 195 1 05 1 65 Vir V 05 08 05 07 05 04 05 03 Vou V 26l PO see qom ee ee ee 1105 VoL V 1 los l osl o4 oem LOU Iy HA 5 5 5 5 Notes Vo and Voy for lower drive currents are sample tested HSLVDCI High Speed Low Voltage Digitally Controlled Impedance The HSLVDCI standard is i
14. The Virtex 4 temperature sensing diode is accessible through the TDP anode and TDN cathode pins The TDP and TDN pins are wired internally to a diode connected transistor which creates a remote temperature sensor TDP and TDN are dedicated pins attached to the substrate die and cannot be accessed through the software tools TDP and TDN are always available and no special design is necessary The TDP and TDN pins are unconnected when this feature is not used The temperature sensing diode is one part of a two part system A temperature sensor interface device is also required Most temperature sensor interface devices provide corresponding pins to connect directly to the Virtex 4 TDP and TDN pins Once the upper and lower temperature limits are set an output signal is created when these bounds are exceeded This output can be an interrupt to turn off the clock turn on a fan or perform another operation to reduce heat The accuracy of the temperature measurement achieved by this two part system does not depend on the temperature sensing diode TDN TDP pins The voltage versus temperature curve is determined by the physical nature of the diode Numerical readout accuracy relies on the temperature sensor interface device to translate the IV versus temperature curves into an actual temperature reading The accuracy specifications are listed in the specific temperature sensor data sheets Temperature Sensor Examples Maxim Remote Local T
15. www xilinx com Virtex 4 User Guide UG070 v1 5 March 21 2006 XILINX ILOGIC Resources B oae ads oai Le DIA D3A D5A D7A D9A D10A D11A D12A D13A Q1 DOA D2A D4A D6A D8A D10A Q2 D1A D3A D5A D7A D9A D11A ug070 7 07 072904 Figure 7 7 Input DDR Timing in SAME EDGE PIPELINED Mode Input DDR Primitive IDDR Figure 7 8 shows the block diagram of the IDDR primitive Table 7 3 lists the IDDR port signals Table 7 4 describes the various attributes available and default values for the IDDR primitive S D Q1 CE Q2 C R ug070 7 08 071404 Figure 7 8 DDR Primitive Block Diagram Table 7 3 IDDR Port Signals Port Function Description Name Q1 and Q2 Data outputs IDDR register outputs Q1 is rising edge data Q2 is falling edge data C Clock input port The C pin represents the clock input pin CE Clock enable port The enable pin affects the loading of data into the DDR flip flop When Low clock transitions are ignored and new data is not loaded into the DDR flip flop CE must be High to load new data into the DDR flip flop D Data input DDR IDDR register input from IOB Virtex 4 User Guide www xilinx com 315 UGO070 v1 5 March 21 2006 Chapter 7 SelectlO Logic Resources XILINX Table 7 3 DDR Port Signals Continued Pon Function Description Name R Reset Synchronous Asynchronous reset pin Reset is asserted High
16. BUFG gt UG070_2_07_071204 Virtex 4 User Guide UG070 v1 5 March 21 2006 XILINX Application Examples Board Level Clock Generation The board level clock generation example in Figure 2 8 illustrates how to use a DCM to generate output clocks for other components on the board This clock can then be used to interface with other devices In this example a DDR register is used with its inputs connected to GND and Vcc Because the output of the DCM is routed to BUFG the clock stays within global routing until it reaches the output register The quality of the clock is maintained If the design requires global buffers in other areas use an OBUF instead of BUFG and ODDR Figure 2 9 However the clock quality will not be as well preserved as when connected using a global buffer and a DDR register Figure 2 10 Outside FPGA Inside FPGA Voc A ODDR IBUFG DCM_ADV BUFG gt CLKO gt CLKIN CLK90 CLK180 Cc IBUFG CLKFB CLK270 GND CLK2X CLK2X180 RST CLKDV CLKFX PSINCDEC CLKFX180 V PSEN PSCLK DADDR 6 0 DOCKED DO 15 0 UG070_2_08_071204 Figure 2 8 Board Level Clock Using DDR Register with External Feedback Virtex 4 User Guide www xilinx com 79 UG070 v1 5 March 21 2006 Chapter 2 Digital Clock Managers DCMs 80 Outside FPGA XILINX Inside FPGA IBUFG gt IBUFG gt DCM_ADV CLKO CLKIN CLK90 CLK1
17. E Output Registered Output optional ug070 5 05 071504 Figure 5 5 Distributed RAM RAM16x1S 170 www xilinx com Virtex 4 User Guide UGO070 v1 5 March 21 2006 XILINX CLB Overview RAM 32x1S A 4 4 A 3 0 WE WCLK Output Registered Output gt optional F5MUX 5 ug070_5_06_071504 Figure 5 6 Single Port Distributed RAM RAM32x1S RAM 16x1D W dual port m RAM WG 4 1 D A 3 0 G 4 1 D WE WCLK A 3 0 F 4 1 DPRA 3 0 WF 4 1 ug070 5 07 071504 Figure 5 7 Dual Port Distributed RAM RAM16x1D Virtex 4 User Guide www xilinx com 171 UGO070 v1 5 March 21 2006 Chapter 5 Configurable Logic Blocks CLBs 2 XILINX If two dual port 16 x 1 bit modules are built the two RAM16X1D primitives can occupy two slices in a CLB as long as they share the same clock and write enable as illustrated in Figure 5 8 RAM16X1D Bit 0 B Slice M RAM16X1D Bit 1 D 1 LC SPO 1 DPO 1 Slice M ug070 5 08 071504 Figure 5 8 Two RAM16X1D Placement The RAM64X1S primitive occupies two slices The RAM64X18 read path is built on the MUXF5 and MUXF6 multiplexers 172 www xilinx com Virtex 4 User Guide UG070 v1 5 March 21 2006 XILINX CLB Overview Read Only Memory ROM
18. Each function generator in SLICEM and SLICEL can implement a 16 x 1 bit ROM Four configurations are available ROM16x1 ROM32x1 ROM64x1 and ROM128x1 The ROM elements are cascadable to implement wider and or deeper ROM ROM contents are loaded at device configuration Table 5 4 shows the number of LUTs occupied by each configuration Table 5 4 ROM Configuration ROM Number of LUTs 16x1 1 32x1 2 64x 1 4 128 x1 8 256 x1 16 2 CLBs Shift Registers Available in SLICEM only ASLICEM function generator can also be configured as a 16 bit shift register without using the flip flops available in a slice Used in this way each LUT can delay serial data anywhere from one to 16 clock cycles The SHIFTIN and SHIFTOUT lines cascade LUTs to form larger shift registers The four left hand LUTs in SLICEM of a single CLB are thus cascaded to produce delays up to 64 clock cycles It is also possible to combine shift registers across more than one CLB The resulting programmable delays can be used to balance the timing of data pipelines Applications requiring delay or latency compensation use these shift registers to develop efficient designs Shift registers are also useful in synchronous FIFO and content addressable memory CAM designs To quickly generate a Virtex 4 shift register without using flip flops i e using the SRL16 element s use the CORE Generator RAM based shift register module The write op
19. Ior at Vor mA 24 z Notes 1 Vor and Voy for lower drive currents are sample tested 2 Per EIA JESD8 6 The value of Vggr is to be selected by the user to provide optimum noise margin in the use conditions specified by the user Virtex 4 User Guide www xilinx com 255 UG070 v1 5 March 21 2006 Chapter 6 SelectlO Resources XILINX HSTL Class IV Figure 6 47 shows a sample circuit illustrating a valid unidirectional termination technique for HSTL Class IV External Termination op Vay 1 5V Vir 15V og HSTL_IV HSTL_IV Rp Zj 502 Rp Zy 500 X 2 bd Vngr 0 9V L DCI IOB IOB Rypp Zg 509 Rypp Zo 502 HSTL_IV_DCI HSTL_IV_DCI X x Vper 0 9V ug070 6 45 071904 Figure 6 47 HSTL Class IV Unidirectional Termination Figure 6 48 shows a sample circuit illustrating a valid bidirectional termination technique for HSTL Class IV 256 www Xilinx com Virtex 4 User Guide UG070 v1 5 March 21 2006 XILINX Specific Guidelines for Virtex 4 I O Supported Standards External Termination ioB Vez 1 5V Vat 1 5V qug HSTL_IV ee HSTL_IV pep PRSS Dd 20 X i Vper 0 9V Veer 0 9V DCI IOB IOB Rypp Zo 509 Rygp Zg 502 HSTL_IV_DCI HSTL IV DCI Vrer 0 9V 4 ug070_6_46_071904 Figure 6 48 HSTL Class IV Bidirectional Termination Virtex 4 User Guide www xilinx com
20. XILINX Summary Virtex 4 devices support 3 3V I O standards LVTTL LVCMOS33 LVDCI33 PCI33 66 and PCI X when the following guidelines are met e Keep signal overshoot and undershoot within the absolute maximum FPGA device specifications Source termination using LVDCI_33 Slow slew rate and or reduced drive current Voltage regulation at 3 0V External high speed bus switches e The absolute maximum junction temperature Ty is 125 C for 3 3V I O operation 294 www xilinx com Virtex 4 User Guide UG070 v1 5 March 21 2006 X XILINX Simultaneous Switching Output Limits Simultaneous Switching Output Limits When multiple output drivers change state at the same time power supply disturbance occurs These disturbances can cause undesired transient behavior in output drivers input receivers or in internal logic These disturbances are often referred to as Simultaneous Switching Output SSO noise The SSO limits govern the number and type of I O output drivers that can be switched simultaneously while maintaining a safe level of SSO noise The Virtex 4 SSO limits are divided into two categories Sparce Chevron SC and Non Sparse Chevron NSC corresponding to package pinout style SSO limits for SC packages are simpler and less restrictive than for NSC packages Sparse Chevron Packages Virtex 4 packaging falls into two categories according to pinout sparse chevron and non sparse chevron The spar
21. pe TBCCkO O uut scis mcr east I I o E EE Los N atio Begin 11 Clock Off Virtex 4 User Guide Figure 1 16 BUFGMUX_VIRTEX4 with a CE Timing Diagram In Figure 1 16 e At time event 1 output O uses input IO e Before time event 2 S is asserted High UG070_1_16_082504 e At time TgccKxo o after time event 2 output O uses input I1 This occurs after a High to Low transition of I0 followed by a High to Low transition of I1 is completed e At time Tpccck cr before time event 3 CE is asserted Low The clock output is switched Low and kept at Low after a High to Low transition of I1 is completed www xilinx com UGO070 v1 5 March 21 2006 31 Chapter 1 Clock Resources XILINX 32 Clock Tree and Nets GCLK Virtex 4 clock trees are designed for low skew and low power operation Any unused branch is disconnected The clock trees also manage the load fanout when all the logic resources are used All global clock lines and buffers are implemented differentially This facilitates much better duty cycles and common mode noise rejection In the Virtex 4 architecture the pin access of the global clock lines are not limited to the logic resources clock pins The global clock lines can access other pins in the CLBs without using local interconnects Applications requiring a very fast signal connection and large load fanout benefit from this architecture www xilinx com Virtex 4 User Guide UG070 v1 5 Ma
22. Asynchronous L T scoao Reset Reset ug070 8 05 073004 Figure 8 5 SERDES Output Data Timing Diagram Clock Event 1 e Attime Trscko o after Clock Event 1 data appears on the Q1 to Q6 output pins Clock Event 2 e Attime Clock Event 2 the reset signal is valid high an asynchronous reset e After Clock Event 2 the O1 to Q6 output pins are asynchronously reset to zero 8 1 SDR ISERDES Figure 8 6 illustrates an ISERDES timing diagram for an 8 1 SDR ISERDES Due to the nature of the ISERDES it takes multiple CLKDIV cycles for data to appear The number of cycles depends on the INTERFACE TYPE attribute Timing parameter names are different depending on the mode SDR DDR however they do not change for different bus input Virtex 4 User Guide www xilinx com 367 UGO070 v1 5 March 21 2006 Chapter 8 Advanced SelectlO Logic Resources XILINX widths In DDR mode the example is similar except the data input D switches every CLK edge rising and falling The first data bit received appears on the highest order output CLKDIV Event 1 CLK CLK CLKDIV Reset Event 1 1 2 Event 2 CLK anniina cov l lI Lf 1L LOr 1 NT SR l J Tiscck ce I CE Tispck p o SCO LEFT 1 1 Tiscko_a Q1 Q8 00000000 00000000 11111010 C 00000000 11100101 UG070_8_06_072904 Figure 8 6 8 1 SDR ISERDES CLKDIV Event 1 e At time Tiscck cp before CLKDIV event 1 the
23. At time event 4 IGNORE is asserted At time event 5 CEO and S0 are asserted High while CE1 and S1 are deasserted Low At Tpccko o after time event 7 output O has switched from I1 to I0 without requiring a High to Low transition of I1 Other capabilities of BUFGCTRL are 24 Pre selection of the I0 and I1 inputs are made after configuration but before device operation The initial output after configuration can be selected as either High or Low Clock selection using CE0 and CE1 only S0 and S1 tied High can change the clock selection without waiting for a High to Low transition on the previously selected clock Virtex 4 User Guide UGO070 v1 5 March 21 2006 www xilinx com XILINX Global Clocking Resources Table 1 5 summarizes the attributes for the BUFGCTRL primitive Table 1 5 BUFGCTRL Attributes Attribute Name Description Possible Values INIT_OUT Initializes the BUFGCTRL output to the specified 0 default 1 value after configuration Sets the positive or negative edge behavior Sets the output level when changing clock selection PRESELECT IO If TRUE BUFGCTRL output will use the I0 input FALSE default after configuration TRUE PRESELECT I1 If TRUE BUFGCTRL output will use the I1 input FALSE default after configuration TRUE Notes 1 Both PRESELECT attributes cannot be TRUE at the same time 2 The LOC constraint is available BUFG BUFG is simply a cloc
24. IDELAY Every ISERDES block contains a programmable absolute delay element called IDELAY IDELAY is a 64 tap wraparound delay element with a fixed guaranteed tap resolution see Virtex 4 Data Sheet It can be applied to the combinatorial input path registered input path or both There are three modes of operation a DEFAULT Zero hold time delay mode similar to the Virtex II and Virtex II Pro delay elements b FIXED Delay value is set to the value in the IOBDELAY VALUE www xilinx com 355 Chapter 8 Advanced SelectlO Logic Resources XILINX c VARIABLE Delay value can be changed at run time by manipulating a set of control signals The section Input Delay Element IDELAY in Chapter 7 discusses IDELAY in detail e Bitslip Sub Module The Bitslip sub module allows designers to reorder the sequence of the parallel data stream going into the FPGA fabric This can be used for training source synchronous interfaces that include a training pattern e Dedicated Support for Strobe based Memory Interfaces ISERDES contains dedicated circuitry including the OCLK input pin to handle the strobe to FPGA clock domain crossover entirely within the ISERDES block This allows for higher performance and a simplified implementation e Dedicated support for Networking interfaces Figure 8 1 shows the block diagram of the ISERDES highlighting all the major components and features of the block D DLYINC C gt
25. IDELAYCTRL dlyctrl n RDY rdy n REFCLK refclk RST rst n The user should either declare the LOC constraints in the Nerilog design file or in the UCF file Declaring LOC constraints in the Verilog file synthesis attribute loc of dlyctrl 1 is IDELAYCTRL X0YO0 synthesis attribute loc of dlyctrl 2 is IDELAYCTRL_XOY1 synthesis attribute loc of dlyctrl N is IDELAYCTRL XnYn Declaring LOC constraints in the UCF file INST dlyctrl 1 LOC IDELAYCTRL X0Y0 INST dlyctrl 2 LOC IDELAYCTRL X0Y1 INST dlyctrl n LOC IDELAYCTRL XnYn One instantiation of an IDELAYCTRL primitive without LOC constraint RST and RDY port signals are independent from LOC ed instances IDELAYCTRL dlyctrl noloc RDY rdy noloc REFCLK refclk RST rst noloc 340 www xilinx com Virtex 4 User Guide UGO070 v1 5 March 21 2006 XILINX ILOGIC Resources The circuitry that results from instantiating the IDELAYCTRL components as shown is illustrated in Figure 7 19 REFCLK RST_NOLOC rst 1 rst 2 rst n Instantiated with LOC Constraint REFCLK RDY IDELAYCTRL 1 RST REFCLK RDY IDELAYCTRL 2 RST REFCLK RDY IDELAYCTRL n RST Instantiated without LOC Constraint REFCLK RDY IDELAYCTRL_noloc RST rdy 1 rdy 2 rdy n REFCLK RDY IDELAYCTRL_noloc RST Replicated for all IDELAYCTRL sites REFCLK RDY
26. Q out std ulogic C in std ulogic CE in std ulogic D1 in std ulogic D2 in std ulogic R in std ulogic S in std ulogic he end component Example ODDR instantiation U_ODDR ODDR Port map Q gt user q C gt user_c CE gt user_ce R D1 gt user_dl D2 gt user_d2 gt user_r S gt user_s 348 www xilinx com Virtex 4 User Guide UG070 v1 5 March 21 2006 XILINX OLOGIC Resources ODDR Verilog Template Example ODDR module declaration module ODDR Q C CE D1 D2 R S output Q input C input CE input D1 input D2 tri0 GSR glbl GSR input R input S parameter DDR_CLK_EDGE OPPOSITE_EDGE parameter INIT 1 b0 parameter SRTYPE SYNC endmodule Example ODDR instantiation ODDR U ODDR Q user q C user c CE user ce Dl user d1 D2 user d2 R user r S user_s OLOGIC Timing Models This section discusses all timing models associated with the OLOGIC block Table 7 14 describes the function and control signals of the OLOGIC switching characteristics in the Virtex 4 Data Sheet Table 7 14 OLOGIC Switching Characteristics Symbol Description Setup Hold Topck Tockp D1 D2 pins Setup Hold with respect to CLK Toocreck Tockocg OCE pin Setup Hold with respect to CLK TosRck lTocksR SR REV pin Setup Hold with respect to CLK Torck Tockr T1 T2 pins
27. S Set Synchronous Asynchronous set pin Set is asserted High Table 7 4 IDDR Attributes Attribute Name Description Possible Values DDR CLK EDGE Sets the IDDR mode of operation OPPOSITE EDGE default with respect to clock edge SAME EDGE SAME EDGE PIPELINED INIT O1 Sets the initial value for O1 port 0 default 1 INIT Q2 Sets the initial value for Q2 port 0 default 1 SRTYPE Set Reset type with respect to ASYNC SYNC default clock C IDDR VHDL and Verilog Templates The following examples illustrate the instantiation of the IDDR primitive in VHDL and Verilog IDDR VHDL Template Example IDDR component declaration component IDDR generic ys port Jus DDR CLK EDGE string OPPOSITE EDGE INIT Ol bit Q INIT_Q2 bit t0 SRTYPE String SYNC Q1 out std ulogic Q2 out std ulogic e in std ulogic CE in std ulogic D in std ulogic R in std ulogic S in std ulogic end component Example IDDR instantiation U IDDR 316 IDDR www xilinx com Virtex 4 User Guide UGO070 v1 5 March 21 2006 2 XILINX ILOGIC Resources Port map Ql gt u Q2 gt u ser_ql ser_q2 C gt user_c CE gt u D gt us R gt us S gt us Nes ser_ce er_d er_r er_s IDDR Verilog Template Example IDDR module declaration module IDDR Q1 Q2 C CE D R S output Q1 outp
28. This attribute determines the A B read port width of the block RAM The valid values are 0 default 1 2 4 9 18 and 36 Write Width WRITE WIDTH A B This attribute determines the A B write port width of the block RAM The valid values are 0 default 1 2 4 9 18 and 36 Write Mode WRITE MODE AB This attribute determines the write mode of the A B input ports The possible values are WRITE FIRST default READ FIRST and NO CHANGE Additional information on the write modes is in the Operating Modes section Block RAM Location Constraints Block RAM instances can have LOC properties attached to them to constrain placement Block RAM placement locations differ from the convention used for naming CLB locations allowing LOC properties to transfer easily from array to array www xilinx com Virtex 4 User Guide UGO070 v1 5 March 21 2006 XILINX Block RAM Initialization in VHDL or Verilog Code The LOC properties use the following form LOC RAMB16 XiYi The RAMB16 X0YO is the bottom left block RAM location on the device If RAMB16 is constrained to RAMB16_X Y the FIFO cannot be constrained to FIFO16_X Y since they share a location An example location constraint is shown in the Block RAM VHDL and Verilog Templates section Block RAM Initialization in VHDL or Verilog Code Block RAM memory attributes and content can be initialized in VHDL or Verilog code for both synthesis and simulation by using
29. Vin DO 0 30 Veco 0 30 Vip DO 0 25 Veco 0 60 Vip AC 0 50 Veco 0 60 Vix AC 0 675 1 125 Output Parameters Vox AC 9 0 725 1 075 Notes 1 Viv DC specifies the allowable DC excursion of each differential input 2 Per EIA JESD8 6 The value of Vggp is to be selected by the user to provide optimum noise margin in the use conditions specified by the user 3 Vip DC specifies the input differential voltage required for switching e Vix AC indicates the voltage where the differential input signals must cross 5 Vox AC indicates the voltage where the differential output signals must cross www xilinx com 281 282 Chapter 6 SelectlO Resources XILINX Table 6 31 details the allowed attributes that can be applied to the SSTL I O standards Table 6 31 Allowed Attributes for the SSTL I O Standards Primitives Attributes IBUFDS IBUFGDS OBUFDS OBUFTDS IOBUFDS IOSTANDARD All possible SSTL standards CAPACITANCE LOW NORMAL DONT CARE Table 6 32 Allowed Attributes for the DIFF SSTL I O Standards Primitives Attributes IBUFDS IBUFGDS OBUFDS OBUFTDS IOBUFDS IOSTANDARD All possible DIFF SSTL standards CAPACITANCE LOW NORMAL DONT CARE Differential Termination DIFF TERM Attribute Virtex 4 IOBs provide a 100 Odifferential termination across the input differential receiver terminals This attribute is used in conjunction with LVDS 25 LVDSEXT 25 L
30. WE Optional EN Control Engine Inverter e Optional configurable Options UGO70 4 05 071204 Figure 4 5 Block RAM Logic Diagram One Port Shown Independent Read and Write Port Width Selection All block RAM ports have control over data width and address depth aspect ratio Virtex 4 devices extend this flexibility to each individual port where Read and Write can be configured with different data widths See Block RAM Attributes page 122 If the Read port width differs from the Write port width and is configured in WRITE FIRST mode then DO shows valid new data only if all the write bytes are enabled Independent Read and Write port width selection increases the efficiency of implementing a content addressable memory CAM in block RAM Excluding the built in FIFO this option is available for all RAM port sizes and modes Cascadable Block RAM Virtex 4 User Guide Combining two 16K x 1 RAMs to form one 32K x 1 RAM is possible in the Virtex 4 block RAM architecture without using local interconnect or additional CLB logic resources NO CHANGE mode is not supported in 32K x 1 RAM configuration Any two adjacent block RAMs can be cascaded to generate a 32K x 1 block RAM Increasing the depth of the block RAM by cascading two block RAMs is available only in the 32K x 1 mode Further information on cascadeable block RAM is described in the Additional RAMB16 Primitive Design Considerations section For other wider and o
31. X 0000000000000000000000000000000000000000000000000000000000000000 INIT 11 gt X 0000000000000000000000000000000000000000000000000000000000000000 INIT 12 gt X 0000000000000000000000000000000000000000000000000000000000000000 126 www xilinx com Virtex 4 User Guide UGO070 v1 5 March 21 2006 2 XILINX Virtex 4 User Guide UG070 v1 5 March 21 2006 Block RAM VHDL and Verilog Templates INIT_13 gt X 0000000000000000000000000000000000000000000000000000000000000000 INIT 14 gt X 0000000000000000000000000000000000000000000000000000000000000000 INIT 15 gt X 0000000000000000000000000000000000000000000000000000000000000000 INIT 16 gt X 0000000000000000000000000000000000000000000000000000000000000000 INIT 17 gt X 0000000000000000000000000000000000000000000000000000000000000000 INIT 18 gt X 0000000000000000000000000000000000000000000000000000000000000000 INIT 19 gt X 0000000000000000000000000000000000000000000000000000000000000000 INIT 1A X 0000000000000000000000000000000000000000000000000000000000000000 INIT 1B X 0000000000000000000000000000000000000000000000000000000000000000 INIT 1C X 0000000000000000000000000000000000000000000000000000000000000000 INIT 1D X 0000000000000000000000000000000000000000000000000000000000000000 INIT 1E X 0000000000000000000000000000000000000000000000000000000000000000 INIT 1F X 000000000000000000000000000000000000000000000000
32. Zero Hold Time Mode ip Device Virtex 4 Family of FoF SS a a Se SS SS SS SS SSeS Instantiation Section IDELAY U1 O data_output I data input C CE INC RST Set IOBDELAY TYPE attribute to DEFAULT for Zero Hold Time Mode synthesis attribute IOBDELAY TYPE of Ul is DEFAULT synthesis attribute IOBDELAY VALUE of U1 is 0 synthesis translate off defparam U1 lIOBDELAY TYPE DEFAULT defparam U1 lIOBDELAY VALUE 0 synthesis translate on Fixed Delay Mode The following code shows how to instantiate the IDELAY module in fixed delay mode with a tap setting of 31 IDELAYCTRL must also be instantiated when operating in this mode see IDELAYCTRL Overview page 330 VHDL for Fixed Delay Mode The IDELAYCTRL primitive must be instantiated in conjunction with the IDELAY primitive when used in Fixed Delay Mode Module IDELAY Description VHDL instantiation template Fixed Delay Mode Device Virtex 4 Family Components Declarations Component Declaration for IDELAY should be placed after architecture statement but before begin keyword component IDELAY synthesis translate off generic IOBDELAY TYPE string DEFAULT DEFAULT FIXED VARIABLE IOBDELAY VALUE integer 0 0 to 63 326 www xilinx com Virtex 4 User Guide UGO070 v1 5 March 21 2006 XILINX ILOGIC
33. attribute BUFR_DIVIDE string attribute LOC string attribute INIT_OUT of U_BUFR label is BYPASS attribute LOC of U_BUFR label is BUFR_X Y where is valid integer locations of BUFR Verilog Template Example BUFR module declaration module BUFR O CE CLR I output O input CE input CLR input I parameter BUFR DIVIDE BYPASS endmodule Virtex 4 User Guide www xilinx com 49 UGO070 v1 5 March 21 2006 Chapter 1 Clock Resources XILINX Example BUFR instantiation BUFR U_BUFR O user_o CE user_ce CLR user clr I user i Declaring constraints in Verilog synthesis attribute BUFR DIVIDE of U BUFR is BYPASS synthesis attribute LOC of U BUFR is BUFR_X Y where is valid integer locations of BUFR Declaring Constraints in UCF File INST U BUFR BUFR DIVIDE BYPASS INST U BUFR LOC BUFR_X Y where is valid integer locations of BUFR 50 www xilinx com Virtex 4 User Guide UG070 v1 5 March 21 2006 XILINX Chapter 2 Digital Clock Managers DCMs DCM Summary The Virtex 4 Digital Clock Managers DCMs provide a wide range of powerful clock management features Virtex 4 User Guide UG070 v1 5 March 21 2006 Clock Deskew The DCM contains a delay locked loop DLL to completely eliminate clock distribution delays by deskewing the DCM s output clocks with respect to the input clock The DLL contai
34. e Case 3 Reading From a Full FIFO e Case 4 Reading From An Empty or Almost Empty FIFO e Case 5 Resetting All Flags Case 1 Writing to an Empty FIFO Prior to the operations performed in Figure 4 17 the FIFO is completely empty 1 23 4 WRCLK l l l l l l l TrFCCK WREN WREN l l he Trpck pi m TFDCK DI DI CRX Cu XC OC 8 XC 06 RDCLK l l l l l l l l l RDEN l l x F Trcko po DO 00 I gt M Trcko EMPTY EMPTY l TFCKO AEMPTY gt F AEMPTY i i ug070_4_17_071204 Figure 4 17 Writing to an Empty FIFO in FWFT Mode Clock Event 1 and Clock Event 3 Write Operation and Deassertion of EMPTY Signal During a write operation to an empty FIFO the content of the FIFO at the first address is replaced by the data value on the DI pins Three read clock cycles later four read clock cycles for FWFT mode the EMPTY pin is deasserted when the FIFO is no longer empty For the example in Figure 4 17 the timing diagram is drawn to reflect FWFT mode Clock event 1 is with respect to the write clock while clock event 3 is with respect to the read clock Clock event 3 appears four read clock cycles after clock event 1 e At time TgpcK pr before clock event 1 WRCLK data 00 becomes valid at the DI inputs of the FIFO e At time Trcck wren before clock event 1 WRCLK write enable becomes valid at the WREN input of the
35. 200 J gt Kw ED m Veer 0 9V DCI IOB IOB 2Rypp 2Zo 1000 2Rypp 2Zo 1000 solr reste SSTL18 Il DCI b T gt Veer 0 9V Ro 2200 REF 2Rygw 2Zg 1000 E 2Rypy 2Zg 1000 Var 0 9V lt Ro 20Q ug070 6 66 071904 Figure 6 68 SSTL 1 8V Class Il Termination Table 6 29 lists the SSTL 1 8V DC voltage specifications Table 6 29 SSTL 1 8V DC Voltage Specifications Class Class Il Min Typ Max Min Typ Max Veco 1 7 1 8 1 9 1 7 1 8 1 9 Vrer 0 5 x Veco 0 833 0 9 0 969 0 833 0 9 0 969 Ver Vggre NO 0 793 0 9 1 009 0 793 0 9 1 009 Vig 2 Vggg 0 125 0 958 2 22 0 958 2 2 20 Vg S Veep 0 125 0 3 0 844 0 3 0 844 Vou Vrr 0 6030 1 396 1 396 Vor lt Ver 0 603 0 406 0 406 278 www xilinx com Virtex 4 User Guide UG070 v1 5 March 21 2006 XILINX Specific Guidelines for Virtex 4 I O Supported Standards Table 6 29 SSTL 1 8V DC Voltage Specifications Continued Class Class Il Min Typ Max Min Typ Max Iou at Voy mA 6 7 13 4 Iot at VoL mA 6 7 13 4 Notes 1 N must be greater than or equal to 0 04 and less than or equal to 0 04 2 Viy maximum is Vcco 0 3 3 Vy minimum does not conform to the formula 4 Because SSTL I DCI uses a controlled impedance driver Voy and Voy are diff
36. 2006 Chapter 6 SelectlO Resources XILINX Table 6 15 lists the HSTL 1 5V Class II DC voltage specifications Table 6 15 HSTL 1 5V Class Il DC Voltage Specifications Min Typ Max Vcco 140 1 50 1 60 Vggr 2 0 68 0 75 0 90 Vir 2 Vcco x 0 5 VH Veer 0 1 Va Vggr 0 1 Vou Veco 04 VoL 0 4 Tox at Voy mA 16 Ior at Vor mA 16 Notes 1 Vor and Vog for lower drive currents are sample tested 2 Per EIA JESD8 6 The value of Vppr is to be selected by the user to provide optimum noise margin in the use conditions specified by the user Complementary Single Ended CSE Differential HSTL Class II Figure 6 42 shows a sample circuit illustrating a valid termination technique for differential HSTL Class II 1 5V with unidirectional termination External Termination V 0 75V V 0 75V 0B T u IOB DIFF HSTL Il 500 500 Dj TZ mx DIFF HSTL II Vr 0 75V Vr 0 75V DIFF HSTL Il ug070 6 40 071904 Figure 6 42 Differential HSTL 1 5V Class II Unidirectional Termination 252 www xilinx com Virtex 4 User Guide UGO070 v1 5 March 21 2006 XILINX DCI Specific Guidelines for Virtex 4 I O Supported Standards Figure 6 43 shows a sample circuit illustrating a valid termination technique for differential HSTL Class II 1 5V with unidirectional DCI termination IOB Veco 1 5V DIFF_H
37. 255 256 to 255 256 by having the DCM set the zero phase skew point in the middle of the delay line This divides the total delay line range in half Absolute Range Fixed FINE SHIFT RANGE In the fixed mode a phase shift is set during configuration in the range of 255 256 to 255 256 Absolute Range Variable Positive and Direct Modes FINE SHIFT RANGE In the variable positive and direct modes the phase shift only operates in the positive range The DCM sets the zero phase skew point at the beginning of the delay line This produces a full delay line in one direction Both the PHASE SHIFT attribute and the FINE SHIFT RANGE parameter need to be considered to determine the limiting range of each application The Phase Shift Examples section illustrates possible scenarios In variable and direct mode the PHASE SHIFT value can dynamically increment or decrement as determined by PSINCDEC synchronously to PSCLK when the PSEN input is active Phase Shift Examples The following usage examples take both the PHASE SHIFT attribute and the FINE SHIFT RANGE components into consideration e If PERIODCLKIN 2 x FINE SHIFT RANGE then the PHASE SHIFT in fixed mode is limited to 128 In variable positive mode PHASE SHIFT is limited to 128 In variable center mode the PHASE SHIFT is limited to 64 e If PERIODCLKIN FINE SHIFT RANGE then the PHASE SHIFT in variable positive mode is limited to 255 In fixed and variable cente
38. 50 O external reference resistors The DCI I O standards supporting drivers with split termination are HSTL II DCI HSTL II DCI 18 SSTL2 II DCI SSTL18 II DCI DIFF HSTL II DCI DIFF HSTL II DCI 18 DIFF SSTL2 II DCI and DIFF SSTL18 II DCI Virtex 4 User Guide www xilinx com 223 UGO070 v1 5 March 21 2006 Chapter 6 SelectlO Resources 224 X XILINX Figure 6 13 illustrates a driver with split termination inside a Virtex 4 device IOB I Veco 2R l gt l 47 San Virtex 4 DCI_ UG070_6_13_071904 Figure 6 13 Driver with Termination to Vcco 2 Using DCI Split Termination www xilinx com Virtex 4 User Guide UG070 v1 5 March 21 2006 XILINX SelectlO Resources General Guidelines DCI in Virtex 4 Hardware DCI works with single ended I O standards and the 2 5V LVDS I O standard DCI supports the following Virtex 4 standards LVDCI HSLVDCI LVDCI DV2 GTL_DCI GTLP DCI HSTL_I_DCI HSTL II DCI HSTL III DCT HSTL IV DCT HSTL I DCI 18 HSTL II DCI 18 HSTL III DCI 18 HSTL IV DCI 18 SSTI2 I DCT SSTIL2 II DCI SSTL18 I DCI SSTL18 II DCI DIFF HSTL II DCI DIFF HSTL II DCI 18 DIFF SSIT2 II DCI DIFF SSTL18 II DCI LVDS 25 DCI and LVDSEXT 25 DCI To correctly use DCI in a Virtex 4 device users must follow the following rules 1 Veco pins must be connected to the appropriate Vcco voltage based on the IOSTANDARDs in that bank 2 Correct DCI I O buff
39. 600 mV 600 mV 663 mV 0 905 SSO Allowance SF1 x SF2 x SF3 x 100 0 909 x 0 917 x 0 905 x 100 75 496 Weighted Average Calculation of SSO This section describes the SSO calculation where the SSO contributions of all I O in a bank are combined into a single figure SSO of an individual bank is calculated by summing the SSO contributions of the individual I O standards in the bank The SSO contribution is the percentage of full utilization of any one I O standard in any one bank For drivers of each I O standard the calculation follows Bank SSO limit L O group n I O Standard SSO limit x Equivalent Vcco GND pairs in bank SSO Contribution I O group n quantity of drivers Bank SSO limit For a bank with drivers of multiple I O standards the SSO calculation is Bank SSO SSO Contribution n 1 to n 304 www xilinx com Virtex 4 User Guide UG070 v1 5 March 21 2006 XILINX Simultaneous Switching Output Limits A sample SSO calculation follows The system parameters used are Device XC4VLX60 FF1148 Bank 1 I O Standards Quantities SSTL2 II 22 LVCMOS25 16 Fast 6 LVCMOS25 6 Fast 19 First SSO limits for each I O standard are obtained from Table 6 42 1 0 Group 1 0 Standard SSO Limit Drivers per Vcco GND Pair 1 SSTL2 II 10 2 LVCMOS25 16 Fast 8 3 LVCMOS25 6 Fast 17 From Table 6 41 the number of equivalent Vcco GND pairs in Bank 1 for the FF1148 package is eight The Bank SSO li
40. A Microsoft Excel based spreadsheet the Virtex 4 SSO Calculator automates all the PFDM and WASSO calculations The Virtex 4 SSO calculator uses PCB geometry board thickness via diameter and breakout trace width and length to determine power system inductance It determines the smallest undershoot and logic low threshold voltage among all input devices calculates the average output capacitance and determines the SSO allowance by taking into account all of the board level design parameters mentioned in this document In addition the Virtex 4 SSO calculator checks the adjacent bank and package SSO ensuring the full device design does not exceed the SSO allowance Since bank number assignment for Virtex 4 devices is different from package to package due to its columnar architecture versus the peripheral I O architecture of previous devices there is a separate tab at the bottom of the SSO calculator display for each Virtex 4 package This customizing allows for the arrangement of physically adjacent banks as they appear clockwise on each unique package even though they are not labeled in a contiguous manner and the hard coding of the number of Vcco GND pairs per bank The Virtex 4 SSO Calculator can be downloaded from the Xilinx web site at http www xilinx com bvdocs userguides ug070 zip www xilinx com 307 UGO070 v1 5 March 21 2006 308 Chapter 6 SelectlO Resources XILINX Other SSO Assumptions LVDCI and HSLVDCI Drive
41. Chapter 7 SelectlO Logic Resources XILINX 1 2 RST TIDELAYCTRL_RPW eA__ i ____ _ _ MH E TipELAYCTRLCO RDY ug070 7 14 080104 Figure 7 14 Timing Relationship Between RST and RDY RST Event 1 e AtRST Event 1 the RST pin is asserted RST Event 2 e At RST Event 2 the RST pin is deasserted At TiDELAYCTRLCO RDY after RST Event 2 RDY is asserted High 332 www xilinx com Virtex 4 User Guide UG070 v1 5 March 21 2006 X XILINX ILOGIC Resources IDELAYCTRL Locations 1 Clock Region 16 I O tiles IDELAYCTRL An IDELAYCTRL module exists in an I O column in every clock region An IDELAYCTRL module calibrates all the IDELAY modules within its clock region See Global and Regional Clocks in Chapter 1 for the definition of a clock region Figure 7 15 illustrates the relative locations of the IDELAYCTRL modules for an XC4VLX15 device Left I O Center I O Right I O Column roam Column ELE zi LIH m i i _ yO E he E EN DCM ug070_7_15_080104 Figure 7 15 Relative Locations of IDELAYCTRL Modules for an XC4VLX15 Device IDELAYCTRL Usage and Design Guidelines Virtex 4 User Guide This section describes using the Virtex 4 IDELAYCTRL modules design guidelines and recommended usage Instantiating IDELAYCTRL Without LOC Constraints When instantiating IDELAYCTRL without LOC constraints the user must instantiate only
42. Chapter 8 Added ISERDES Latencies page 365 and OSERDES Latencies page 381 Revised Guidelines for Using the Bitslip Sub Module section 09 12 05 1 4 Chapter 2 Revised FACTORY_JF value in Table 2 7 page 65 The LOCKED signal description is updated in Figure 2 19 and Figure 2 20 Chapter 6 Revised the Simultaneous Switching Output Limits section Chapter 8 Added more information to Clock Enable Inputs CE1 and CE2 page 358 UGO070 v1 5 March 21 2006 www xilinx com Virtex 4 User Guide Version Revision 03 21 06 1 5 Chapter 1 Updated description under Table 1 1 Updated Figure 1 21 page 38 Chapter 4 Changed Table 4 8 page 136 and added a note Updated the discussions in NO_CHANGE Mode and Cascadable Block RAM sections Removed synchronous FIFO application example Chapter 5 Revised slice label in Figure 5 30 page 206 Chapter 6 Added to the Xilinx DCI section Added IBUF to the PULLUP PULLDOWN KEEPER for IBUF OBUFT and IOBUF discussion Added Veco numbers in the 1 5V column in Table 6 5 page 242 Corrected Figure 6 70 page 280 Added notes 4 and 5 to Table 6 38 page 288 Updated 3 3V I O Design Guidelines Summary page 294 Added HSLVDCI High Speed Low Voltage Digitally Controlled Impedance page 242 section Added 1 2V to Table 6 40 page 296 and added link to SSO calculator to text above table Added HSLVDCI to Table 6 42 page 298 Rev
43. EN_REL TRUE PMCD 2 CLKA CLKA1 gt CLKB CLKA1D2 D RST CLKA1D4 T REL CLKA1D8 9D Reset RST_DEASSERT_CLK CLKB EN_REL TRUE UGO070_3_08_071404 Figure 3 8 DCM and Parallel PMCDs IBUFG BUFG and PMCD When deskewed clocks are not required a PMCD can be used without a DCM Figure 3 9 and Figure 3 10 illustrate these examples PMCD GCLK T BUFGs gt CLKA1D2 Ce gt p CLKA1D4 CLKA1D8 RST_DEASSERT_CLK CLKA EN_REL FALSE UG070_3_09_071404 Figure 3 9 PMCD Driven by IBUFG GCLK IOB 102 www xilinx com Virtex 4 User Guide UGO070 v1 5 March 21 2006 XILINX Application Examples PMCD CLKA CLKA1 CLKA1D2 RST CLKA1D4 REL CLKA1D8 BUFG BUFGs GCLK gt RST_DEASSERT_CLK CLKA EN_REL TRUE Logic to synchronize REL from the PMCD output clock domain to the PMCD input clock domain UGO070 3 10 071404 Figure 3 10 PMCD Driven by BUFG and Synchronous Logic PMCD for Further Division of Clock Frequencies PMCDs can be used to further divide clock frequencies A dedicated local connection exists from the CLKA1D8 output of each PMCD to the CLKA input of the other PMCD within the same tile group of two Thus only CLKA1D8 can directly connect two PMCDs in series Figure 3 11 illustrates an example of dividing clock frequencies using a DCM and a PMCD Note the following guidelines e The
44. IBUF IBUFG OBUF OBUFT IOBUF IOSTANDARD All possible HSTL standards CAPACITANCE LOW NORMAL DONT CARE Table 6 25 details the allowed attributes that can be applied to the DIFF HSTL I O standards Table 6 25 Allowed Attributes of the DIFF HSTL I O Standards Primitives Attributes IBUFDS IBUFGDS OBUFDS OBUFTDS IOBUFDS IOSTANDARD All possible DIFF HSTL standards CAPACITANCE LOW NORMAL DONT CARE Virtex 4 User Guide www xilinx com 267 UGO070 v1 5 March 21 2006 Chapter 6 SelectlO Resources XILINX SSTL Stub Series Terminated Logic The Stub Series Terminated Logic SSTL for 2 5V SSTL2 and 1 8V SSTL18 is a standard for a general purpose memory bus These standards are sponsored by Hitachi IBM and are defined in the JEDEC JESD8 15 documents The standard has two classes Class I is for unidirectional and class II is for bidirectional signaling Virtex 4 I O supports both standards for single ended signaling and Class II only for differential signaling This standard requires a differential amplifier input buffer and a push pull output buffer SSTL2 I SSTL18 Usage Class I signaling uses Vtr Vcco 2 as a parallel termination voltage to a 50 O resistor at the receiver A series resistor 25 O at 2 5V 20 O at 1 8V must be connected to the transmitter output SSTL2 DCI SSTL18 DCI Usage The DCI transmitter provides the internal series resistance 25 Qat2 5V 20 Qat1 8V The DCI
45. IDELAYCTRL_noloc RST Auto generated by mapper tool Instantiating Multiple IDELAYCTRLs Without LOC Constraints Instantiating multiple IDELAYCTRL instances without LOC properties is prohibited If this occurs an error is issued by the implementation tools Virtex 4 User Guide UG070 v1 5 March 21 2006 www xilinx com RDY_NOLOC ug070_7_19_080104 Figure 7 19 Mixed Instantiation of IDELAYCTRL Elements 341 Chapter 7 SelectlO Logic Resources XILINX OLOGIC Resources 342 OLOGIC blocks include six storage elements shown in Figure 7 20 The top three registers TFF1 TFF2 and TFF3 are used for 3 state control The bottom three registers OFF1 OFF2 and OFF3 are used for data output Both sets of registers are functionally the same To build an edge triggered D type flip flop use the topmost register OFF1 TFF1 This register is also the only register that can be configured as a level sensitive latch The other two registers OFF2 TFF2 and OFF3 TFF3 are used to build various output DDR registers See Output DDR Overview ODDR page 344 for further discussion on output DDR The three data registers share a common clock enable OCE Similarly the three 3 state control registers share a different clock enable TCE The clock enable signals are default active High If left unconnected the clock enable pin for the storage element defaults to the active state All registers in O
46. If the RDY port of the non location constrained IDELAYCTRL instance is ignored then all the RDY signals of the replicated IDELAYCTRL instances are also ignored If the RDY port of the non location constrained IDELAYCTRL instance is connected then the RDY port of the non location constrained instance plus the RDY ports of the replicated instances are connected to an auto generated AND gate The implementation tools assign the signal name connected to the RDY port of the non location constrained instance to the output of the AND gate All the ports of the location constrained instances RST REFCLK and RDY are independent from each other and from the replicated instances www xilinx com Virtex 4 User Guide UG070 v1 5 March 21 2006 XILINX ILOGIC Resources The VHDL and Verilog use models for instantiating a mixed usage model are provided In the example a user is instantiating a non location constrained IDELAYCTRL instance with the RDY signal connected This discussion is also valid when the RDY signal is ignored VHDL Use Model Multiple instantiations of IDELAYCTRL primitives with LOC constraints Each instance has its own RST and RDY signal to allow for partial reconfiguration The REFCLK signal is common to all instances LOC and replicated instances dlyctrl 1 IDELAYCTRL port map RDY gt rdy _1 REFCLK gt refclk RST rst 1 dlyctrl 2 IDELAYCTRL port map RDY gt rdy 2 REFCLK gt
47. In addition a phase shift overflow DO 0 status indicates when the phase shift counter has reached the end of the phase shift delay line or the maximum value 255 for variable mode 1023 for direct mode After the DCM locks the initial phase in the VARIABLE POSITIVE and VARIABLE CENTER modes is determined by the PHASE SHIFT value The initial phase in the DIRECT mode is always 0 regardless of the value specified by the PHASE SHIFT 74 www xilinx com Virtex 4 User Guide UGO070 v1 5 March 21 2006 X XILINX DCM Design Guidelines attribute The non zero PHASE_SHIFT value for DIRECT mode can only be loaded to the DCM when a specific load phase shift value command is given by Dynamic Reconfiguration Refer to the Techniques section in the Virtex 4 Configuration Guide for more information The phase of DCM output clock will be incremented decremented according to the interaction of PSEN PSINCDEC PSCLK and PSDONE from the initial or dynamically reconfigured phase PSEN PSINCDEC and PSDONE are synchronous to PSCLK When PSEN is asserted for one PSCLK clock period a phase shift increment decrement is initiated When PSINCDEC is High an increment is initiated and when PSINCDEC is Low a decrement is initiated Each increment adds to the phase shift of DCM clock outputs by 1 256 of the CLKIN period Similarly each decrement decreases the phase shift by 1 256 of the CLKIN period PSEN must be active for exactly one PSCLK period
48. OBUF Primitive www xilinx com 229 UGO070 v1 5 March 21 2006 Chapter 6 SelectlO Resources XILINX OBUFT The generic 3 state output buffer OBUFT shown in Figure 6 19 typically implements 3 state outputs or bidirectional I O OBUFT 3 state input Input O Output From FPGA to device pad ug070 6 19 071904 Figure 6 19 3 State Output Buffer OBUFT Primitive IOBUF The IOBUF primitive is needed when bidirectional signals require both an input buffer and a 3 state output buffer with an active High 3 state pin Figure 6 20 shows a generic Virtex 4 IOBUF IOBUF T 3 state input Input VO from FPGA to from device pad O Output to FPGA ug070 6 20 071904 Figure 6 20 Input Output Buffer IOBUF Primitive IBUFDS and IBUFGDS The usage and rules corresponding to the differential primitives are similar to the single ended SelectIO primitives Differential SelectIO primitives have two pins to and from the device pads to show the P and N channel pins in a differential pair N channel pins have a B suffix Figure 6 21 shows the differential input buffer primitive IBUFDS IBUFGDS i8 Inputs from device pads Output to FPGA ug070 6 21 071904 Figure 6 21 Differential Input Buffer Primitive IBUFDS IBUFGDS 230 www xilinx com Virtex 4 User Guide UGO070 v1 5 March 21 2006 XILINX Virtex 4 SelectlO Primitives OBUFDS Figure 6 22 shows the differential output buffer primitiv
49. Vcco but does not require the use of a reference voltage Vpgp or a termination voltage V7 Sample circuits illustrating both unidirectional and bidirectional LVTTL termination techniques are shown in Figure 6 25 and Figure 6 26 IOB IOB LVTTL LVTTL 54 x gt EN RENE IOB lOB LVTTL LVTTL Rs Zo Rp Kew x gt er d IOB Yr poa LVTTL LVTTL Rp Zo 54 x gt Note V is any voltage from OV to Veco ug070 6 25 071904 Figure 6 25 LVTTL Unidirectional Termination www xilinx com Virtex 4 User Guide UGO070 v1 5 March 21 2006 X XILINX Specific Guidelines for Virtex 4 I O Supported Standards IOB IOB LVTTL LVTTL gt x QA m gt lop Vmr Vor IOB LVTTL LVTTL Dpp ami gt X x P4 IED XX ug070 6 26 071904 Figure 6 26 LVTTL Bidirectional Termination Note V is any voltage from OV to Veco Table 6 1 lists the LVTTL DC voltage specifications Table 6 1 LVTTL DC Voltage Specifications Parameter Min Typ Max VREF Ver Vin 2 0 3 6 Vit 0 5 0 8 Vog 24 Vor 0 4 Toy at Voy mA 24 Iorat VoL mA 24 Notes 1 Voz and Vog for lower drive currents are sample tested Virtex 4 User Guide www xilinx com 237 UG070 v1 5 March 21 2006 Chapter 6 SelectlO Resources XILINX Table 6 2 details the allowed attributes that
50. Veco Unconnected BM pU x VETED i kd ug070 6 33 071904 Figure 6 35 GTL with External Parallel Termination and Unconnected Veco GTL DCI Usage GTL does not require a Veco voltage However for GTL_DCI Veco must be connected to 1 2V GTL_DCI provides single termination to Vcco for inputs or outputs A sample circuit illustrating a valid termination technique for GTL_DCI with internal parallel driver and receiver termination is shown in Figure 6 36 B IOB IOB a Veco 1 2V Veco 1 2V E Rypp Zo 500 Rypp Zo 502 X lt I 7o 59 1X 4 Vper 0 8V ug070 6 34 071904 Figure 6 36 GTL_DCI with Internal Parallel Driver and Receiver Termination Table 6 10 lists the GTL DC voltage specifications Table 6 10 GTL DC Voltage Specifications Parameter Min Typ Max Vcco N A B Veer N x Voz 0 74 0 8 0 86 Vir 1 14 1 2 1 26 Vin Veer 0 05 0 79 0 85 Vi Veer 0 05 0 75 0 81 Vou Virtex 4 User Guide www xilinx com 245 UGO070 v1 5 March 21 2006 XILINX Chapter 6 SelectlO Resources Table 6 10 GTL DC Voltage Specifications Continued Parameter Min Typ Max Voi 0 2 0 4 lon at Von mA s Toy at Vor mA at 0 4V 32 Ior at Vor mA at 0 2V 40 Notes 1 N must be greater than or equal to 0 653 and less than or equal to 0 68 Table 6 11 details the allowed attribute
51. Virtex 4 User Guide UGO070 v1 5 March 21 2006 XILINX VHDL and Verilog Templates and the Clocking Wizard Clock Switching Between Two DCMs Figure 2 13 illustrates switching between two clocks from two DCMs while keeping both DCMs locked gt CLKIN CLko gt CLK90 CLK180 CLKA CLKFB CLK270 CLKOX RST CLK2X180 PSINCDEC ee BUFGMUX PSEN Sey CLKFX180 DADDRI6 0 LOCKED DO 15 0 IBUFG DCM ADV BUFG CLKO CLK90 CLK180 CLKB CLKFE CLK270 RST CLK2X CLK2X180 PSINCDEC CLKDV PSEN CLKFX PSCLK CLKFX180 DADDR 6 0 LOCKED DO 15 0 UGO70 2 13 071204 Figure 2 13 Clock Switching Between Two DCMs VHDL and Verilog Templates and the Clocking Wizard VHDL and Verilog instantiation templates are available in the Libraries Guide for all primitives In addition VHDL and Verilog files are generated by the Clocking Wizard in the ISE software The Clocking Wizard sets appropriate DCM attributes input output clocks and buffers for general use cases Virtex 4 User Guide www xilinx com 83 UGO070 v1 5 March 21 2006 Chapter 2 Digital Clock Managers DCMs XILINX The Clocking Maan is accessed bed the Xilinx ISE software in the Project Navigator Refer to the Xilinx S are Manuals for more information on Xilinx ISE software 1 From the Project Navigator menu select Project gt New Source The New Source window appears Enter a file name and select IP Cor
52. integer attribute NUM CE integer attribute SERDES MODE string Component Instantiation for ISERDES should be placed in architecture after the begin keyword Virtex 4 User Guide www xilinx com 369 UGO070 v1 5 March 21 2006 Chapter 8 Advanced SelectlO Logic Resources XILINX Instantiation Section Ul ISERDES synthesis translate off generic map BI INT SLIP_ENABLE gt DATA_RATE gt DDR SDR DDR DATA_WIDTH gt 4 U ERFACE TYPE gt MI IOBDELAY gt NONE NONI IOBDELAY_TYPE gt DEFAULT DEFAULT FIXED VARIABLI IOBDELAY_VALUE gt 0 NUM_CE gt 2 1 2 SERDES_MODE gt MAST JF synthesis translate_on port map O gt data_output Q1 Q2 Q3 Q4 Q5 06 Q 0 Q 1 Q 2 Q 3 open open SHIFTOUT1 gt open SHIFTOUT2 gt open BITSLIP bitslip CEI gt CE2 gt CLK gt CLKDIV oc REV LK ce open clk gt clkdiv D gt data_input DLYCE gt dlyce DLYINC gt dlyinc DLYRST gt dlyrst gt open gt open SHIFTIN1 gt open SHIFTIN2 gt open SR gt rst FALSE EMORY TRUE FALSE 2 3 4 5 6 7 8 10 MEMORY NETWORKING E IBUF IFD BOTH Lj 0 to 63 ER MASTER SLAVE 370 www xilinx com Virtex 4 User Guide UG
53. one instance of IDELAYCTRL in the HDL design code The implementation tools auto replicate IDELAYCTRL instances throughout the entire device even in clock regions not using the delay element This results in higher power consumption due to higher resource utilization the use of one global clock resource in every clock region and a greater use of routing resources The signals connected to the RST and REFCLK input ports of the instantiated IDELAYCTRL instance are connected to the corresponding input ports of the replicated IDELAYCTRL instances There are two special cases 1 When the RDY port is ignored the RDY signals of all the replacement IDELAYCTRL instances are left unconnected The VHDL and Verilog use models for instantiating an IDELAYCTRL primitive without LOC constraints leaving the RDY output port unconnected are provided www xilinx com 333 UG070 v1 5 March 21 2006 Chapter 7 SelectlO Logic Resources XILINX VHDL Use Model Only one instance of IDELAYCTRL primitive is instantiated The RDY port is left open dlyctrl IDELAYCTRL port map RDY open REFCLK refclk RST rst Verilog Use Model Only one instance of IDELAYCTRL primitive is instantiated The RDY port is left open IDELAYCTRL dlyctrl RDY REFCLK refclk RST rst m The resulting circuitry after instantiating the IDELAYCTRL components is illustrated in Figure 7 16 Instantiated by user REFCLK RE
54. or decrement will increase or decrease the phase shift by a period of 1 256 x CLKIN period When set to DIRECT the DCM output can be phase shifted in variable mode in the positive range with respect to CLKIN Each phase shift increment decrement will increase decrease the phase shift by one DCM TAP see the Virtex 4 Data Sheet The starting phase in the VARIABLE POSITIVE and VARIABLE CENTER modes is determined by the phase shift value The starting phase in the DIRECT mode is always zero regardless of the value specified by the PHASE SHIFT attribute Thus the PHASE SHIFT attribute should be set to zero when DIRECT mode is used A non zero phase shift value for DIRECT mode can be loaded to the DCM using Dynamic Reconfiguration Ports in the Virtex 4 Configuration Guide CLK FEEDBACK Attribute Virtex 4 User Guide The CLK FEEDBACK attribute determines the type of feedback applied to the CLKFB The possible values are 1X or NONE The default value is 1X When set to 1X CLKFB pin must be driven by CLKO When set to NONE leave the CLKFB pin unconnected www xilinx com 63 UGO070 v1 5 March 21 2006 64 Chapter 2 Digital Clock Managers DCMs XILINX DESKEW_ADJUST Attribute The DESKEW_ADJUST attribute affects the amount of delay in the feedback path The possible values are SYSTEM_SYNCHRONOUS SOURCE_SYNCHRONOUS 0 1 2 3 or 31 The default value is SYSTEM_SYNCHRONOUS For most designs the default value is appropr
55. output without RDEN asserted DATA_WIDTH Integer 4 9 18 36 36 LOC String Valid FIFO16 Sets the location of the FIFO16 location Notes 1 If FIFO16 is constrained to FIFO16_X Y then RAMB16 can not be constrained to RAMB16_X Y since the same location would be used FIFO Almost Full Empty Flag Offset Range The offset ranges for Almost Empty and Almost Full are listed in Table 4 13 Table 4 13 FIFO Almost Full Empty Flag Offset Range ALMOST_EMPTY_OFFSET Configuration ALMOST_FULL_OFFSET Standard FWFT 4k x4 5 to 4092 6 to 4093 4 to 4091 2k x9 5 to 2044 6 to 2045 4 to 2043 1k x 18 5 to 1020 6 to 1021 4 to 1019 512 x 36 5 to 508 6 to 509 4 to 507 Notes 1 ALMOST_EMPTY_OFFSET and ALMOST_FULL_OFFSET for any design must be less than the FIFO depth The Almost Full and Almost Empty offsets are usually set to a small value of less than 10 to provide a warning that the FIFO is about to reach its limits Since the full capacity of any FIFO is normally not critical most applications use the ALMOST_FULL flag not only as a warning but also as a signal to stop writing Virtex 4 User Guide www xilinx com 145 UGO070 v1 5 March 21 2006 Chapter 4 Block RAM XILINX Similarly the ALMOST_EMPTY flag can be used to stop reading However this would make it impossible to read the very last entries remaining in the FIFO The user can ignore the Almost Empty signal and continue to r
56. the DCM needs to be reset to resume operation DO 15 Not assigned When LOCKED is Low during reset or the locking process all the status signals deassert Low Dynamic Reconfiguration Ready Output DRDY Virtex 4 User Guide The dynamic reconfiguration ready DRDY output pin provides the response to the DEN signal for the DCM s dynamic reconfiguration feature Further information on the DRDY pin is available in the dynamic reconfiguration section in the Virtex 4 Configuration Guide www xilinx com 61 UGO070 v1 5 March 21 2006 Chapter 2 Digital Clock Managers DCMs XILINX DCM Attributes A handful of DCM attributes govern the DCM functionality Table 2 7 summarizes all the applicable DCM attributes This section provides a detailed description of each attribute For more information on applying these attributes in UCF VHDL or Verilog code refer to the Constraints Guide at http www support xilinx com support software manuals htm CLKDV DIVIDE Attribute The CLKDV DIVIDE attribute controls the CLKDV frequency The source clock frequency is divided by the value of this attribute The possible values for CLKDV DIVIDE are 1 5 2 2 5 8 8 5 4 4 5 5 5 5 6 6 5 7 7 5 8 9 10 11 12 13 14 15 or 16 The default value is 2 In the low frequency mode any CLKDV DIVIDE value produces a CLKDV output with a 50 50 duty cycle In the high frequency mode the CLKDV_DIVIDE valu
57. the DCM sees half the frequency applied to the CLKIN input and operates based on this frequency For example if a 100 MHz clock drives CLKIN and CLKIN DIVIDE BY 2 is set to True then the effective CLKIN frequency is 50 MHz Thus CLKO output is 50 MHz and CLK2X output is 100 MHz The effective CLKIN frequency must be used to evaluate any operation or specification derived from CLKIN frequency The possible values for CLKIN DIVIDE BY 2 are True and False The default value is False CLKOUT PHASE SHIFT Attribute The CLKOUT PHASE SHIFT attribute indicates the mode of the phase shift applied to the DCM outputs The possible values are NONE FIXED VARIABLE POSITIVE VARIABLE CENTER or DIRECT The default value is NONE When set to NONE a phase shift cannot be performed and a phase shift value has no effect on the DCM outputs When set to FIXED the DCM outputs are phase shifted by a fixed phase from the CLKIN The phase shift value is determined by the PHASE SHIFT attribute If the CLKOUT PHASE SHIFT attribute is set to FIXED or NONE then the PSEN PSINCDEC and the PSCLK inputs must be tied to ground When set to VARIABLE POSITIVE the DCM outputs can be phase shifted in variable mode in the positive range with respect to CLKIN When set to VARIABLE CENTER the DCM outputs can be phase shifted in variable mode in the positive and negative range with respect to CLKIN If set to VARIABLE POSITIVE or VARIABLE CENTER each phase shift increment
58. 0 Default Condition SR REV Function 0 0 NOP 0 1 Set 1 0 Reset 1 1 Reset Table 7 2 Truth Table when SRVAL 1 SR REV Function 0 0 NOP 0 1 Reset 1 0 Set 1 1 Reset The SRVAL attributes can be set individually for each storage element in the ILOGIC block but the choice of synchronous or asynchronous set reset SRTYPE can not be set individually for each storage element in the ILOGIC block 310 www xilinx com Virtex 4 User Guide UG070 v1 5 March 21 2006 XILINX ILOGIC Resources Most of the control signals have an optional inverter Any inverter placed on a control signal is automatically absorbed into the ILOGIC block i e no CLBs are used IDELMUX1USED D 1 1 2 IDELMUX IMUX IDELAYMUX IDELAY o IFF1 i OFB IFF3 Qi Q1MUX i TFB PLYINC DLYRST DLYCE IFF2 i PE 3 IFF4u Q2 L5 CLKDIV CE1 LT ack Goats CLKDIVINV CE1INV CLK gt E D gt SB HEN IFF2 CLKINV SR j E SRINV REV m c gt REVINV Virtex 4 User Guide ug070 7 01 072904 Figure 7 1 ILOGIC Block Diagram The following sections discuss the various resources within the ILOGIC blocks All connections between the ILOGIC resources are managed in Xilinx software Combinatorial Input Path The combinatorial input path is used to create a direct connection fr
59. 1 1 0 0 1 0 0 ISERDES L gt 0 0 1 1 1 0 0 1 0 Master 1 0 0 1 1 1 0 0 1 Q5 m gt 0 1 0 0 1 1 1 0 0 Q6 mj 0 0 1 0 0 1 1 1 0 BITSLIP SHIFTOUT1 SHIFTOUT2 SHIFTIN1 SHIFTIN2 D Q1 Q2 ISERDES Q7 Q3 1 0 0 1 0 0 1 1 1 Slave Q8 Q4 gt 1 1 0 0 1 0 0 1 1 Q5 Q6 BITSLIP 1 e Bitslip signal from system SERDES MODE SLAVE BITSLIP ENABLE TRUE Note 1 This is a repeating pattern mm Figure 8 8 Circuit Diagram for Bitslip Configuration 372 www xilinx com Virtex 4 User Guide UG070 v1 5 March 21 2006 XILINX Input Serial to Parallel Logic Resources ISERDES Guidelines for Using the Bitslip Sub Module Set the BITSLIP_ENABLE attribute to TRUE When BITSLIP ENABLE is set to FALSE the Bitslip pin has no effect In a master slave configuration the BITSLIP ENABLE attribute in both modules must be set to TRUE To invoke a Bitslip operation the BITSLIP port must be asserted High for one and only one CLKDIV cycle In both SDR and DDR mode the output pattern will be stable after two CLKDIV cycles to become stable Bitslip Timing Model and Parameters This section discusses the timing models associated with the Bitslip controller Figure 8 9 shows the Bitslip timing diagram 1 2 ak LTITLTLTLITLTUTLILTLTLTUTLITLTLITLITTLITTITL CLKDIV DL y Lo y Q1 to Q6 Q3 and Q4 Tisckoa 4 of Master of Slave 10010011 11001001 MSB LSB T ISCCK_BITSLIP ma BITSLIP ug070_8_18_072904 Figure 8 9 Bitslip Timing Diagr
60. 1002 LVDS 25 DCI l l l Veco 2 5V CC l 2Rypp 2Zg 1002 2Rypy 2Zg 1002 ugo70 6 72 071904 Figure 6 74 LVDS 25 DCI Receiver Termination Virtex 4 User Guide www xilinx com 283 UG070 v1 5 March 21 2006 Chapter 6 SelectlO Resources XILINX Figure 6 75 is an example of a differential termination for an LVDS receiver on a board with 50 Q transmission lines IOB IOB 9 Zg 500 LVDS 25 piel LVDS 25 Rpirr 1000 Z 502 o AX Data in ug070 6 73 071904 Figure 6 75 LVDS 25 With DIFF TERM Receiver Termination Table 6 33 lists the available Virtex 4 LVDS I O standards and attributes supported Table 6 33 Allowed Attributes of the LVDS I O Standard Primitives Attributes IBUFDS IBUFGDS OBUFDS OBUFGDS IOSTANDARD LVDS 25 LVDSEXT 25 ULVDS 25 CAPACITANCE LOW NORMAL NORMAL DONT CARE DIFF TERM TRUE FALSE Unused Table 6 34 lists the available Virtex 4 LVDS DCI I O standards and attributes supported Table 6 34 Allowed Attributes of the LVDS DCI I O Standard Primitives Attributes IBUFDS IBUFGDS OBUFDS OBUFGDS IOSTANDARD LVDS 25 DCI Unused LVDSEXT 25 DCI CAPACITANCE LOW NORMAL Unused DONT CARE HyperTransport Protocol LDT The Hypertransport protocol or formally known as Lightning Data Transport LDT is a low voltage standard for high speed interfaces Its differential signaling based in
61. 2 1 OUTBUF INBUF DIFFI IN L gt ug070_6_02_071904 Figure 6 2 Basic IOB Diagram Each IOB has a direct connection to an ILOGIC OLOGIC pair containing the input and output logic resources for data and 3 state control for the IOB When using multiple clocks in Virtex 4 I O tiles the input clocks to the two ILOGIC blocks and the two OLOGIC blocks are not shared Both ILOGIC and OLOGIC can be configured as ISERDES and OSERDES respectively as described in Chapter 8 Advanced SelectIO Logic Resources SelectlO Resources General Guidelines This section summarizes the general guidelines to be considered when designing with the Virtex 4 SelectIO resources Virtex 4 I O Bank Rules The number of banks available in Virtex 4 devices is not limited to eight as in previous Xilinx architectures In Virtex 4 devices with some exceptions in the center column an I O bank consists of 64 IOBs 32 CLBs and two clock regions As a result the number of banks 216 www xilinx com Virtex 4 User Guide UGO070 v1 5 March 21 2006 XILINX SelectlO Resources General Guidelines depends upon the device size In the Virtex 4 Overview the total number of I O banks is listed by device type The XC4VLX25 has 10 usable I O banks and one configuration bank Figure 6 3 is an example of a columnar floorplan showing the XC4VLX25 I O banks ug070 6 03 071404 Figure 6 3 Virtex 4 XC4VLX25 I O Ban
62. 5 March 21 2006 www xilinx com 379 Chapter 8 Advanced SelectlO Logic Resources XILINX OSERDES Width Expansion Two OSERDES modules are used to build a parallel to serial converter larger than 6 1 In every I O tile there are two OSERDES modules one master and one slave By connecting the SHIFTIN ports of the master OSERDES to the SHIFTOUT ports of the slave OSERDES the parallel to serial converter can be expanded to up to 10 1 DDR and 8 1 SDR Figure 8 3 illustrates a block diagram of a 10 1 DDR parallel to serial converter using the master and slave OSERDES modules Ports Q3 Q6 are used for the last four bits of the parallel interface on the slave OSERDES LSB to MSB SERDES MODE MASTER Data Out Datalnputs 5 ee SHIFTIN1 SHIFTIN2 OSERDES Slave Data Inputs 6 9 SERDES MODE SLAVE ug070 8 20 073004 Figure 8 12 Block Diagram of OSERDES Width Expansion Table 8 9 lists the data width availability for SDR and DDR mode Table 8 9 OSERDES SDR DDR Data Width Availability SDR Data Widths 2 3 4 5 6 7 8 DDR Data Widths 4 6 8 10 Guidelines for Expanding the Parallel to Serial Converter Bit Width 1 Both the OSERDES modules must be adjacent master and slave pairs 2 Setthe SERDES MODE attribute for the master OSERDES to MASTER and the slave OSERDES to SLAVE see SERDES MODE Attribute 3 The user must connect the SHIFTIN ports of the MASTER to the SHIFTOUT ports
63. 5 2 Diagram of SLICEM 166 www xilinx com Virtex 4 User Guide UGO070 v1 5 March 21 2006 XILINX CLB Overview COUT A COUTUSED P YB YBUSED so cymUXG o 1 F5MUX FXINB po EXINA gt E FXUSED FX end D a a YMUXUSED gt gt Y ES A ne gt P a i R YMUX YUSED me A2 im E M Ai p FE BY Kk LATCH DYMUX INIT1 INITO SRHIGH FFY_INIT_ATTR SRLOW SR REV FFY SR ATTR CY0G FFY BY G2 eoo G3 Lor 1 GAND 1 o BYINV By BY FD gt REVUSED P gt xB CYMUXF XBUSED So o 1 I b FBUSED IL lo SO F5 F5 F5MUX XMUXUSED P T gt XMUX FXOR E XUSED 5 f gt e A Ii DXMUX CR a p KMUX EE A2 XORF x 5 3 EXC oe OFF BX OLATCH CK F DINIT OINITO OSRHIGH FFX_INIT_ATTR OSRLOW SR REV FFX SR ATTR FFX BX F2 gt F3 f BXCIN FAND H cvor cyinit BX BX gt xt BXINV D CE CEB cp lt CEINV pK CLK CLK B EX ruis RESET TYPE Sa OSYNC gt da DIASYNC SRINV SYNC_ATTR CIN ug070 5 03 071504 Figure 5 3 Diagram of SLICEL Virtex 4 User Guide UGO070 v1 5 March 2
64. 8 1 18 bit width 16 2 and 36 bit width 32 4 configurations The ninth bit associated with each byte can store parity or error correction bits No specific function is performed on this bit The separate bus for parity bits facilitates some designs However other designs safely use a 9 bit 18 bit or 36 bit bus by merging the regular data bus with the parity bus Read write and storage operations are identical for all bits including the parity bits Some block RAM attributes can only be configured using the RAMB16 primitive e g pipeline register cascade etc See the Block RAM Attributes section Figure 4 10 shows the generic dual port block RAM primitive DIA DIPA ADDRA DOA DOPA and the corresponding signals on port B are buses RAMB16 SX SY DIA X 0 DIPA X 0 ADDRA X 0 DOA 4 0 WEA DOPA 0 ENA SSRA DIB Y 0 DIPB Y 0 ADDRB Y 0 DOB 0 WEB DOPB 0 ENB SSRB ug070 4 10 071204 Figure 4 10 Dual Port Block RAM Primitive Virtex 4 User Guide www xilinx com 133 UGO070 v1 5 March 21 2006 Chapter 4 Block RAM XILINX Table 4 6 lists the available dual port primitives for synthesis and simulation Table 4 6 Dual Port Block RAM Primitives Primitive Port A Width Port B Width RAMB16_S1_S1 1 1 RAMB16_S1_S2 2 RAMB16 S1 S4 4 RAMBI6 S1 S9 8 1 RAMB16_S1_S18
65. A1 A0 Q SRLC16 16 bits CLK A3 A2 A1 A0 Q Q15 SRLC16E 16 bits CLK CE A3 A2 A1 A0 Q Q15 SRLC16_1 16 bits CLK A3 A2 A1 A0 Q O15 SRLC16E_1 16 bits CLK CE A3 A2 A1 A0 Q Q15 In addition to the 16 bit primitives 32 bit and 64 bit cascadable shift registers can be implemented in VHDL and Verilog Table 5 14 lists the available submodules Table 5 14 Shift Register Submodules Submodule Length Control Address Inputs Output SRLC32bE MACRO 32bits CLK CE A4 A3 A2 A1 A0 Q O31 SRLCO64E MACRO 64bits CLK CE A5 A4 A3 A2 A1 A0 Q Q63 The submodules are based on SRLC16E primitives and are associated with dedicated multiplexers MUXF5 MUXF6 and so forth This implementation allows a fast static and dynamic length mode even for very large shift registers Figure 5 29 represents the cascadable shift registers 32 bit and 64 bit implemented by the submodules in Table 5 14 www xilinx com 203 UGO070 v1 5 March 21 2006 Chapter 5 Configurable Logic Blocks CLBs A4 Add 34 A3 A2 A1 AO pI 4 Q15 SRLC16E 4 Q15 SRLC16E 32 bit Shift Register 204 Add Sz MUXF5 Q31 A5 A4 A5 2 XILINX X A3 A2 A1 AO Q15 SRLC16E Q15 SRLC16E Q15 SRLC16E A4 Q15 SRLC16E v MUXF5 MUXF5 MUXF6 gt Q63 64 bit Shift Register Figure 5 29 Shift Register Submodules
66. A5 The address inputs select the memory cells for read or write The width of the port determines the required address inputs Note that the address inputs are not a bus in VHDL or Verilog instantiations Data In D The data input provides the new data value to be written into the RAM Data Out O SPO and DPO The data out O Single Port or SPO and DPO Dual Port reflects the contents of the memory cells referenced by the address inputs Following an active write clock edge the data out O or SPO reflects the newly written data Inverting Control Pins The two control pins WCLK and WE each have an individual inversion option Any control signal including the clock can be active at 0 negative edge for the clock or at 1 positive edge for the clock without requiring other logic resources Global Set Reset GSH The global set reset GSR signal does not affect distributed RAM modules For more information on the GSR see the BUFGSR section in the Xilinx Software Manual Virtex 4 User Guide www xilinx com 199 UGO070 v1 5 March 21 2006 Chapter 5 Configurable Logic Blocks CLBs XILINX Attributes Content Initialization INIT With the INIT attributes users can define the initial memory contents after configuration By default distributed RAM is initialized with all zeros during the device configuration sequence The initialization attribute INIT represents the specified memory contents Each INIT is a he
67. Attribute ccc eee ran 379 DATA WIDTH Att Bite 2 ue Petre he PR bte Re e ecc e o RR d 379 SERDES MODE Attribute 0 0 eee tenn rhe 379 TRISTATE_WIDTH Attribute 2 2 0 0 hh han 379 Virtex 4 User Guide www xilinx com UG070 v1 5 March 21 2006 15 XILINX OSERDES Width Expansion 0 6 ccc eee 380 Guidelines for Expanding the Parallel to Serial Converter Bit Width 380 OSERDES Latenci s 14v vig cued e ya x rb Uri ER EE E EE UE vas 381 OSERDES Timing Model and Parameters eee 381 Timing Characteristics essseksks bue RR PRbryeePped rb vedios sae eens 382 OSERDES VHDL and Verilog Instantiation Templates 000 384 OSERDES VHDL Template 2 reppu de Siu p cu TETEE eee ee aie e EY eas 384 OSERDES Verilog Template 22 b cernere bre oe RR HER d e rea 385 Chapter 9 Temperature Sensing Diode Temperature Sensing Diode TDP TDN ess esses 387 Temperature Sensor Examples slssseseeee eee 387 Maxim Remote Local Temperature Sensors lllleeeeeeeee eee 387 National Semiconductor LM83 or LM86 0 0 0 cece eee eee eee 388 ip THEOD 389 16 www xilinx com Virtex 4 User Guide UG070 v1 5 March 21 2006 XILINX Preface About This Guide This document describes the Virtex 4 architecture Complete and up to date documentation of the Virtex 4 family of FPGAs is available on the Xilinx web site at h
68. Board Level Clock Generation 00 c ccc ence n 79 Board Deskew with Internal Deskew 00 eee 80 Clock Switching Between Two DCMS 6 cece eee ee 83 VHDL and Verilog Templates and the Clocking Wizard 83 DCM Timing Models 3 2 int ieh te wGre hoc at Ree ERR Sat e ee aed enue nde 88 Reset Dock e hte ebd ace ER deeded b ce ae end ace d ce sca eg 88 Pixed Phase Shif ng deer curent eur beara eae eme epit ende prn etie di 89 Variable Phase Shifting 0 0 6 enn nee 90 Stat s PAS e cesset ena oeste iter Rte tained bee CHR e NUR E Id gor i E 91 Legacy Support er eL heed Rae oie eot bdo ER Een e idet ipd 92 Chapter 3 Phase Matched Clock Dividers PMCDs PMCID Summary os say CIS VPERTXENT VERE Ra ewe R peat EXEAT E Cp prada 93 Virtex 4 User Guide www xilinx com 7 UGO070 v1 5 March 21 2006 X XILINX PMCD Primitives Ports and Attributes 0 00 00 0000 eese 95 PMCD Usage and Design Guidelines ehm ern 96 Phase Matched Divided Clocks 00000 e cece eee eee eens 96 Matched Clock Phase ent ig ertt tere ete pie prt erem ende er nannies 97 Reset RST and Release REL Control Signals lslssssssseseseeees 98 Connecting PMCD to other Clock Resources ssssssssee eee eee ee 100 IBUFG t PMED aces 5 dgeed oe odore eere siTe eg Gier ented arte eic seed 100 DEM EnIuu Pp 100 BUFGCTRE to PMC Diss cv Roe eet ae e a e pbi dece pd P ce Pra oes 100 PMCD to
69. CE input I endmodule Example BUFGCE instantiation BUFGCE U_BUFGCE O user_o CEO user ce 10 user_i Declaring constraints in Verilog synthesis attribute LOC of U BUFGCE is BUFGCTRL_X Y where is valid integer locations of BUFGCTRL Declaring Constraints in UCF File INST U BUFGCE LOC BUFGCTRL_X Y where is valid integer locations of BUFGCTRL BUFGMUX and BUFGMUX 1 VHDL and Verilog Templates The following examples illustrate the instantiation of the BUFGMUX module in VHDL and Verilog The instantiation of BUFGMUX 1 is exactly the same as BUFGMUX with exception of the primitive name VHDL Template Example BUFGMUX declaration component BUFGMUX port O out std ulogic I0 in std ulogic I1 in std ulogic S in std ulogic hy end component Example BUFGMUX instantiation U BUFGMUX BUFGMUX Port map O user o IO user i0 I1 gt user i1 S user S Declaring constraints in VHDL file attribute LOC string attribute LOC of U BUFGMUX label is BUFGCTRL_X Y where is valid integer locations of BUFGCTRL Virtex 4 User Guide www xilinx com 45 UGO070 v1 5 March 21 2006 Chapter 1 Clock Resources XILINX Verilog Template Example BUFGMUX module declaration module BUFGMUX O IO I1 S output O input I0 input I1 input S endmodule Example BUFGMUX instantiation BUFGMUX U BUFGMUX O us
70. DDR edge with respect to CLK DATA RATE TO Defines whether the 3 state TO changes String BUF SDR or DDR at every clock edge every positive clock DDR edge with respect to clock or is set to buffer configuration DATA_WIDTH Defines the parallel to serial data Integer 2 3 4 5 6 7 8 or 10 4 converter width This value also depends If DATA RATE OQ DDR on the DATA RATE OQ value value is limited to 4 6 8 or 10 If DATA RATE OQ SDR value is limited to 2 3 4 5 6 7 or 8 378 www xilinx com Virtex 4 User Guide UG070 v1 5 March 21 2006 XILINX Output Parallel to Serial Logic Resources OSERDES Table 8 8 OSERDES Attribute Summary Continued OSERDES Attribute Description Value Default Value SERDES_MODE Defines whether the OSERDES moduleisa String MASTER or MASTER master or slave when using width SLAVE expansion TRISTATE_WIDTH Defines the parallel to serial 3 state Integer 1 2 or 4 4 converter width If DATA RATE TQ DDR value is limited to 2 and 4 If DATA_RATE_TQ SDR or BUF value is limited to 1 DATA_RATE_OQ Attribute The DATA_RATE_OQ attribute defines whether data is processed as single data rate SDR or double data rate DDR The allowed values for this attribute are SDR and DDR The default value is DDR DATA_RATE_TQ Attribute The DATA RATE TO attribute defines whether 3 state control is to be p
71. Event 4 the SR signal configured as synchronous reset in this case becomes valid high resetting the input register and reflected at the O1 output of the IOB at time Tyco after Clock Event 4 ILOGIC Timing Characteristics DDR Figure 7 10 illustrates the ILOGIC in IDDR mode timing characteristics When IDELAY is used T pocx is replaced by Tjpocykp The example shown uses IDDR in OPPOSITE EDGE mode For other modes add the appropriate latencies as shown in Figure 7 7 page 315 318 www xilinx com Virtex 4 User Guide UGO070 v1 5 March 21 2006 XILINX ILOGIC Resources CLK A NASIS NSAI NSI NAI NASA Tipock _ F Tipock D nA Maw T T T TNL po ligick CE1 A l Il isnck Ticko Ee Ticka Q1 aw NEL do d d 0 Nil D Led ICKQ 1 ICKQ a ee d as Y t mee ale UG070_7_10_072904 Figure 7 10 ILOGIC in IDDR Mode Timing Characteristics Clock Event 1 e Attime T cg ck before Clock Event 1 the input clock enable signal becomes valid high at the CE1 input of both of the DDR input registers enabling them for incoming data Since the CE1 and D signals are common to both DDR registers care must be taken to toggle these signals between the rising edges and falling edges of CLK as well as meeting the register setup time relative to both clocks e At time T pocx before Clock Event 1 rising edge of CLK the input signal becomes valid high at
72. FIFO e At time Trcko po after clock event 3 RDCLK data 00 becomes valid at the DO output pins of the FIFO In the case of standard mode data 00 does not appear at the DO output pins of the FIFO 150 www xilinx com Virtex 4 User Guide UGO070 v1 5 March 21 2006 XILINX FIFO Timing Models and Parameters e At time Trcko Empty after clock event 3 RDCLK EMPTY is deasserted In the case of standard mode EMPTY is deasserted one read clock earlier than clock event 3 If the rising WRCLK edge is close to the rising RDCLK edge EMPTY could be deasserted one RDCLK period later Clock Event 2 and Clock Event 4 Write Operation and Deassertion of Almost EMPTY Signal Three read clock cycles after the fourth data is written into the FIFO the Almost EMPTY pin is deasserted to signify that the FIFO is not in the almost EMPTY state For the example in Figure 4 17 the timing diagram is drawn to reflect FWFT mode Clock event 2 is with respect to write clock while clock event 4 is with respect to read clock Clock event 4 appears three read clock cycles after clock event 2 e Attime Tppcy pr before clock event 2 WRCLK data 03 becomes valid at the DI inputs of the FIFO e Write enable remains asserted at the WREN input of the FIFO e At clock event 4 DO output pins of the FIFO remains at 00 since no read has been performed In the case of standard mode data 00 will never appear at the DO output pins of the FIFO e At time Trck
73. Full or Almost Full FIFO 6 6 0 cee 151 Case 3 Reading From a Full FIFO 1 6 eee eens 153 Case 4 Reading From An Empty or Almost Empty FIFO 0000 154 Case 5 Resetting All Flags i522 sre ese Ee e a e r3 TR XX EP 155 FIFO Applications 13 143 prre EE Dar et HE ee eei ee dura e HORROR ERU 156 Cascading FIFOs to Increase Depth lisssssssseeeeeeeeeeee 156 Cascading FIFOs to Increase Width 0 eens 157 Built in Block RAM Error Correction Code suuuusss 157 Top Level View of the Block RAM ECC Architecture 00000004 158 Block RAM ECC Primitive lesse s 158 Block RAM ECC Port Description slsssssseeeee eee 159 Error Status Description esses cue eee dc e eben RR e der d ean 160 Block RAM ECC Attribute 2 0 00 0 ccc ccc cence eee en eees 160 Block RAM ECC VHDL and Verilog Templates 600 c cee eee ee 160 Block RAM ECC VHDL Template eeseeeeeeee cece eee 160 Block RAM ECC Verilog Template see 161 Chapter 5 Configurable Logic Blocks CLBs CLB Ovetvlew encre eben rte en bua b Eee dep oe deciden 163 Slice Description eene tem ee tee eee eer Renee eR e ded ees 164 CLB Slice Configurations 4 4 uere d p etr eade rae dee eras 164 Eook Up Table LUT a cy foe aca sols esd bt te eto ener ere usse eb peer edu di aes 168 Storage Elements us cue Gan So etae be eee Pos eb Ro barn ego dead 168
74. Guide UGO070 v1 5 March 21 2006 XILINX Specific Guidelines for Virtex 4 I O Supported Standards SSTL2 Class 2 5V Figure 6 59 shows a sample circuit illustrating a valid termination technique for SSTL2 Class I External Termination Eo eee Vez 1 25V IOB SSTL2 SSTL2 Rg 250 Rp 29 500 E wq x Vper 1 25V DCI IOB IOB Voco 2 5V 2Rypp 2Zo 1000 SSTL2 I DCI SSTL2 DCI gt 49 2 I Veer 1 25V Ro 250 REP 2 2Rypy 2Zg 1002 L ug070 6 57 071904 Figure 6 59 SSTL2 Class Termination Virtex 4 User Guide www xilinx com 269 UG070 v1 5 March 21 2006 Chapter 6 SelectlO Resources XILINX Table 6 26 lists the SSTL2 DC voltage specifications for Class I Table 6 26 SSTL2 DC Voltage Specifications Class Min Typ Max Vcco 2 3 25 2 7 Veer 7 05x Veco 1 13 1 25 1 38 Vor 2 Vger NO 1 09 1 25 1 42 Vg 2 Vggr 0 15 1 28 1 4 3 0 Vg Veer 0 15 0 3 1 1 1 23 Von 2 Vrer 0 61 1 74 1 84 1 94 VoL lt Vggr 0 614 0 56 0 66 0 76 Tox at Voy mA 8 1 Io at Vor mA 8 1 Notes 1 N must be greater than or equal to 0 04 and less than or equal to 0 04 2 Viy maximum is Vcco 0 3 3 Vy minimum does not conform to the formula 4 Because SSTL2_I_DCI uses a controlled impedance driver Voy and Voy are different SSTL2 Class Il 2 5V Figure 6 60 shows a sample circuit i
75. InsD i4e3 m Re E e re P LY RH HR eg d oed ees 205 Clock Enable CE optional seeeeeeeeeeee e 205 Address AO AJ A2 AB 0 ccc ccc hh hr hrs 205 D ta Out Q ive s Ete deed atin E e htec eR rates pum eet RR RR cete d 205 Data Qut OT5 optiorial i anter t edet d eei bete e idend 205 Inverting Control Pins de Ru Re eee ae ow eee ade ee 205 Global Set Reset GSR ccc ccc eee rh rh ah hh hihi 205 JAEEEIDUITOS outta iren estesa tst ease tardi fede ten eld reed e aa pL ol reet 206 Content Initialization INIT 0 0 eee nee e eens 206 Location Constraints 2e nce eee er e Re o e ree LAS Sak RR RO RR RU 206 Fully Synchronous Shift Registers 2 6 0 6 207 Static Length Shift Registers 0 6 6 ene eens 207 VHDL and Verilog Instantiation 0 66 208 VHDL and Verilog Templates 0 ccc eee ees 208 Multiplexer Primitives and Verilog VHDL Examples 210 Multiplexer Primitives and Submodules 0 0 0000 esses 210 Port Signals c os TEE EEE E R AE AET LN d ee piece 211 Data In DATA T 22 44 xp RERER dU thee a RE ERA ces 211 Control In SELECT IL 2 ce eee eee n 211 Data O t DATA Q i reri ereinen ia E ess UV ed ewido behets vexat ans 211 Multiplexer Verilog VHDL Examples sssssssessee 211 Virtex 4 User Guide www xilinx com 11 UGO070 v1 5 March 21 2006 X XILINX VHDL and Verilog Instantiation ciis n 211 VHDL and Verilog Su
76. Parallel to Serial Converter The data parallel to serial converter in one OSERDES blocks receives two to six bits of parallel data from the fabric 10 1 if using OSERDES Width Expansion serializes the data and presents it to the IOB via the OQ outputs Parallel data is serialized from lowest order data input pin to highest i e data on the D1 input pin is the first bit transmitted at the OQ pins The data parallel to serial converter is available in two modes single data rate SDR and double data rate DDR www xilinx com Virtex 4 User Guide UG070 v1 5 March 21 2006 XILINX Output Parallel to Serial Logic Resources OSERDES The OSERDES uses two clocks CLK and CLKDIV for data rate conversion CLK is the high speed serial clock CLKDIV is the divided parallel clock It is assumed that CLK and CLKDIV are phase aligned Table 8 6 describes the relationship between CLK and CLKDIV in all modes Table 8 6 CLK CLKDIV Relationship of the Data Parallel to Serial Converter Input p Lol dd in Input pos Hen 2S in CLK CLKDIV 2 4 2X X 3 6 3X X 4 8 4X X 5 10 5X X 6 6X X 7 7X X 8 8X X 3 State Parallel to Serial Conversion In addition to parallel to serial conversion of data an OSERDES module also contains a parallel to serial converter for 3 state control of the IOB Unlike data conversion the 3 state converter can only serialize up to four bits of parallel 3 state signals T
77. REL CLKB1 Reset RST_DEASSERT_CLK CLKA EN_REL FALSE Figure 3 7 DCM and a Single PMCD UGO070 3 07 071404 DCM and Parallel PMCDs A DCM can be connected to parallel PMCDs Figure 3 8 illustrates this example Note the following guidelines e The DCM feedback CLKFB must be driven by the same frequency as CLKIN for 1X feedback Therefore the PMCD output corresponding to CLKO must be used to drive the CLKFB pin e The RST DEASSERT CIK attribute must be set to the PMCD input driven by CLKO When a DCM is connected to a PMCD all output clocks except CLKO and CLKOX are held Low until LOCKED is High Thus setting RST DEASSERT CLK Virtex 4 User Guide www xilinx com 101 UGO070 v1 5 March 21 2006 Chapter 3 Phase Matched Clock Dividers PMCDs XILINX to the corresponding DCM feedback clock ensures all PMCD outputs will start synchronously Note CLK2X feedback is not supported e The REL signals of the parallel PMCDs must be driven directly from the DCM LOCKED output Dedicated timing matched routes for both CLK signals and LOCKED signals exist from the DCMs to the PMCDs on the same top bottom half of the device To match output skews between two PMCDs a DCM must connect to two PMCDs in the same tile group of two DCM PMCD 1 sees CLKIN CLKO CLKFB CLK180 CLKA1D2 T CLKA1D4 D CLKA1D8 gt Reset Heset EE LOCKED Le RST_DEASSERT_CLK CLKA
78. SHIFTIN1 1 SHIFTIN2 1 SR rst Jr BITSLIP ENABLE of data c DATA RATE of data chan i DATA WIDTH of data chan INTERFACE TYPE of data c IOBDELAY of data chan is IOBDELAY TYPE of data ch IOBDELAY VALUE of data c NUM CE of data chan is SERDES MODE of data chan gmouugvuaaaoQ I synthesis synthesis synthesis synthesis synthesis synthesis synthesis synthesis synthesis rid p rid Instantiate Slave ISERDES for data 1 10 Deserialization Factor ISERDES data_chan_slave O JOT Q2 Q3 dy data_int Q4 data int Q5 data int Q6 data int SHIFTOUT1 SHIFTOUT2 BITSLIP 1 b El 1 b1 E2 1 b1 LK iobclk LKDIV clkd 1 b0 YCE 1 5b0 LYINC 1 b0 LYRST 1 b0 CLK 1 b0 EV 1 b0 SHIFTIN1 sh SHIFTIN2 sh SR rst Jr gmoguuguaaaoQ synthesis synthesis synthesis synthesis synthesis synthesis BITSLIP 1 DATA RATE of data chan i DATA WIDTH of data chan INIT O1 of data chan is INIT Q2 of data chan is INIT Q3 of data chan is ENABLE of data chan is 1 LKDIV clkdiv b0 b0 han is FALSE S DDR is 10 han is NETWORKING NONE an is DEFAULT han is 0 1i is MASTER channel ernal 6 ernal 7 ernal 8 ernal 9 1 1 0 1 iv D iftdatal iftdata2 FALSE S
79. SRL Timing Parameters Table 5 7 shows the SLICEM SRL timing parameters for a majority of the paths in Figure 5 24 Table 5 7 Slice SRL Timing Parameters CLB Slice Timing Models Parameter Function Description Sequential Delays for Slice LUT Configured as SRL Select Shift Register TREG CLK to X Y outputs Time after the Clock CLK of a Write operation that the data written to the SRL is stable on the X Y outputs of the slice TCKSH CLK to Shift_out Time after the Clock CLK of a Write operation that the data written to the SRL is stable on the Shift_out or XB YB outputs of the slice TREGES5 CLK to F5 output Time after the Clock CLK of a Write operation that the data written to the SRL is stable on the F5 output of the slice TRECXB CLK to XB YB outputs Time after the Clock CLK of a Write operation that the data TREGYB written to the SRL is stable on the XB YB outputs of the slice Setup Hold for Slice LUT Configured as SRL Select Shift Register Tyg Setup time before clock edge The following descriptions are for setup times only Tyxn Hold time after clock edge Tws CE input WE Time before the clock that the write enable signal must be stable at TwH the WE input of the slice LUT configured as SRL Tps BX BY configured as data Time before the clock that the data must be stable at the BX BY TDH input DI input of the slice Virtex 4 User Guide www xilinx com 1
80. Setup Hold with respect to CLK TorcEgck lockrcg TCE pin Setup Hold with respect to CLK Clock to Out Tocko CLK to OQ TQ out Tro SR REV pin to OQ TQ out Virtex 4 User Guide www xilinx com 349 UGO070 v1 5 March 21 2006 Chapter 7 SelectlO Logic Resources XILINX Timing Characteristics Figure 7 26 illustrates the OLOGIC output register timing 1 2 3 4 5 i UN SF NSF VIF NC M BT ON TloDck LI TOOCECK Of NE E EE D ee ce ee GER ees eee gt TocKa on NEL UM Ww ONE 1 ug070 7 26 080204 Figure 7 26 OLOGIC Output Register Timing Characteristics Clock Event 1 e Attime Toocgcy before Clock Event 1 the output clock enable signal becomes valid high at the CE input of the output register enabling the output register for incoming data e Attime Topcy before Clock Event 1 the output signal becomes valid high at the D1 input of the output register and is reflected at the Q output at time Tocko after Clock Event 1 Clock Event 4 At time Tosrcx before Clock Event 4 the SR signal configured as synchronous reset in this case becomes valid high resetting the output register and reflected at the Q output at time Trg after Clock Event 4 350 www xilinx com Virtex 4 User Guide UG070 v1 5 March 21 2006 XILINX OLOGIC Resources Figure 7 27 illustrates the OLOGIC ODDR register timing ug070_7_27_080204 Figure 7 27 OLOGIC ODDR Regis
81. TFcck_RDEN TFCCK RDEN RDEN Trcko Do TFcko po l DO lt 00 X 01 X 02 X OS X 04 TrFcko EMPTY E EMPTY l TrcKo_AEMPTY AEMPTY TEckO RDERR 4 RDERR ee a FCKO_RDERR ug070 4 20 071204 Figure 4 20 Reading From an Empty Almost Empty FIFO Standard Mode Clock Event 1 Read Operation and Assertion of Almost EMPTY Signal During a read operation to an almost empty FIFO the Almost EMPTY signal is asserted e At time Trcck RDEN before clock event 1 RDCLK read enable becomes valid at the RDEN input of the FIFO e At time Trcko po after clock event 1 RDCLK data 00 becomes valid at the DO outputs of the FIFO e At time Trcko AEMPrTYy One clock cycle after clock event 1 RDCLK Almost Empty is asserted at the AEMPTY output pin of the FIFO Clock Event 2 Read Operation and Assertion of EMPTY Signal The EMPTY signal pin is asserted when the FIFO is empty e Read enable remains asserted at the RDEN input of the FIFO e At time Trcko po after clock event 2 RDCLK data 04 last data becomes valid at the DO outputs of the FIFO e At time Trcko Empty after clock event 2 RDCLK Empty is asserted at the EMPTY output pin of the FIFO In the event that the FIFO is empty and a write followed by a read is performed the EMPTY signal remains asserted 154 www xilinx com Virtex 4 User Guide UG070 v1 5 March 21 2006 2 XILINX FIFO Timing Models and Pa
82. Table 1 7 lists the BUFIO ports A location constraint is available for BUFIO BUFIO ug070 1 18 071304 Figure 1 18 BUFIO Primitive Table 1 7 BUFIO Port List and Definitions Port Name Type Width Definition O Output 1 Clock output port I Input 1 Clock input port Virtex 4 User Guide www xilinx com 35 UG070 v1 5 March 21 2006 Chapter 1 Clock Resources BUFIO Use Models XILINX In Figure 1 19 a BUFIO is used to drive the I O logic using the clock capable I O This implementation is ideal in source synchronous applications where a forwarded clock is used to capture incoming data To Adjacent VOTile 4 Region 4 I O Tile 4 I O Tile 4 I O Tile 4 I O Tile 4 I O Tile 4 I O Tile 4 Clock Capable I O VO Tile BUFR Clock Capable I O O Tile I O Tile 4 I O Tile 4 I O Tile 4 I O Tile 4 O Tile 4 O Tile 4 SL To Adjacent Region de To Fabric ug070 1 19 072204 Figure 1 19 BUFIO Driving I O Logic In a Single Clock Region 36 www xilinx com Virtex 4 User Guide UG070 v1 5 March 21 2006 X XILINX Regional Clocking Resources Regional Clock Buffer BUFR The regional clock buffer BUFR is another new clock buffer available in Virtex 4 devices BUFRSs drive clock signals to a dedicated clock net within a clock region independent from the global clock tree Each BUFR can drive the two regional clock nets in the region it is located and the t
83. Table 8 4 SERDES Latencies SERDES MODE Data RATE Latency in Memory Mode Latency in Networking Mode SDR 1 CLKDIV cycle 2 CLKDIV cycle DDR 1 CLKDIV cycle 2 CLKDIV cycles Virtex 4 User Guide UGO070 v1 5 March 21 2006 www xilinx com 365 Chapter 8 Advanced SelectlO Logic Resources 2 XILINX ISERDES Timing Model and Parameters Table 8 5 describes the function and control signals of the ISERDES switching characteristics in the Virtex 4 Data Sheet Table 8 5 ISERDES Switching Characteristics Symbol Setup Hold for Control Lines Description TISCCK_BITSLIP TiscKC_BITSLIP BITSLIP pin Setup Hold with respect to CLKDIV Trscck cx TiscKC_CE CE pin Setup Hold with respect to CLK for CE1 Trscck cx TiscKC_CE CE pin Setup Hold with respect to CLKDIV for CE2 Trscck pryce TiscKC_DLYCE DLYCE pin Setup Hold with respect to CLKDIV Triscck prviNc TiscKC_DLYINC DLYINC pin Setup Hold with respect to CLKDIV TISCCK_DLYRST TiscKC_DLYRST DLYRST pin Setup Hold with respect to CLKDIV Setup Hold for Data Lines Trspck p Trsckp p D pin Setup Hold with respect to CLK IOBDELAY IBUF or NONE D pin Setup Hold with respect to CLK IOBDELAY IFD or BOTH IOBDELAY TYPE DEFAULT D pin Setup Hold with respect to CLK IOBDELAY IFD or BOTH IOBDELAY TYPE FIXED IOBDELAY VALUE 0 Trispck ppn TiscKD_DDR D pin Setup Hold with respect to CLK
84. Veco R gm Z l 0 gt VREF Virtex 4 DCI UGO70 6 07 071904 Figure 6 7 Input Termination Using DCI Single Termination Input Termination to Vcco 2 Split Termination Virtex 4 User Guide Some I O standards e g HSTL Class I and II require an input termination voltage of Vcco 2 see Figure 6 8 Vcco 2 IOB R Zo VREF Virtex 4 UG070_6_08_071904 Figure 6 8 Input Termination to Vcco 2 without DCI This is equivalent to having a split termination composed of two resistors One terminates to Vcco the other to ground The resistor values are 2R DCI provides termination to Vcco 2 using split termination The termination resistance is set by the external reference resistors i e the resistors to Vcco and ground are each twice the reference resistor value Both HSTL and SSTL standards need 50 OQ external reference resistors The DCI I O standards supporting split termination are HSTL I DCI HSTL I DCI 18 HSTL II DCI HSTL II DCI 18 DIFF HSTL II DCI DIFF HSTL II DCI 18 SSTL2 I DCI SSTL2 II DCI SSTL18 I DCI SSTL18 II DCI DIFF SSTL2 II DCI and DIFF SSTLI18 II DCI www xilinx com 221 UGO070 v1 5 March 21 2006 Chapter 6 SelectlO Resources XILINX Figure 6 9 illustrates split termination inside a Virtex 4 device IOB Veco 2R o gt k J VREF Virtex 4 DCI UG070_6_09_071904 Figure 6 9 Input Termination to Vcco 2 Using DCI Split Terminatio
85. Virtex 4 User Guide www xilinx com 165 UG070 v1 5 March 21 2006 Chapter 5 Configurable Logic Blocks CLBs XILINX To From Slice on Top SHIFTIN cour saurus To Fabric 1 YBUSED n D D p B From YEMUX p evourusep BYOUT I BYINVOUTUSED aviou FSMUX FXINB P FXUSED p FX FXINA gt FX YMUXUSED YMUX IDUAL PORT sone GXOR b Ex CSHIFT_REG MUX wie G4 gt D Y o LYB DS YMUX Sa Y Lp YQ gt BY p MG4USED DYMUX A G3USED ONT gt D NG2USED DINITO gt OOSRHIGH SHINN DSRLOW sm nv rrv ALTDIG c ALTDIG BY DIG MUX GAND piers Ic b BY c LH BYINV BYINV REVUSED XBMUX SLICEWE1 SLICEWE1USED BUSED Pistceweousen CYMUXF 9 D gt xB gt D FSUSED SHIFTIN rs F5 mxo XMUXUSED ux TOES s l XUSED FXMUX gt D E E4 DIF gt DE xe E2 IXMU x gt x D mm x gt Dose suse DRM gt B wr 2usep TINT EIINITO WF USED LISRHIGH OSRLOW 1DUAL PORT SR REV FFX COSHIFT_REG F CYINIT BXCIN x BX gt oe BXB Bxinv cE c Le CE B ogwv CLK pK me RESET TYPE cK B CLKINV T SR gt me p p SR B SRINV SRFFMUX SYNC ATTR SHIFTOUTUSED CIN sau To From Slice on Bottom UG070 5 02 071504 Figure
86. after reset RST almost empty is asserted at the AEMPTY output pin of the FIFO e At time Trco FULL after reset RST full is deasserted at the FULL output pin of the FIFO e Attime Teco AFULL after reset RST almost full is deasserted at the AFULL output pin of the FIFO Reset is an asynchronous signal used to reset all flags Hold the reset signal High for three read and write clock cycles to ensure that all internal states and flags are reset to the correct value www xilinx com 155 UG070 v1 5 March 21 2006 Chapter 4 Block RAM XILINX FIFO Applications There are various uses for the Virtex 4 block RAM FIFO e Cascading two asynchronous FIFOs to form a deeper FIFO e Building wider asynchronous FIFO by connecting two FIFOs in parallel Cascading FIFOs to Increase Depth Figure 4 22 shows a way of cascading FIFOs to increase depth The application sets the first FIFO in FWFT mode and uses external resources to connect to the second FIFO The ALMOST_FULL_OFFSET of the second FIFO should be four or more The data latency of this application can be up to double that of a single FIFO and the maximum frequency is limited by the feedback path The NOR gate is implemented using CLB logic DIN lt 3 0 gt DOUT lt 3 0 gt DOUT lt 3 0 gt WREN AFULL RDCLK FIFO 2 RDEN 4 8K x 4 FIFO ug070 4 23 071204 Figure 4 22 Cascading FIFO 156 www xilinx com Virtex 4 User
87. and frequency to CLKIN The phase shift clock signal can be driven by any clock source external or internal including 1 IBUF Input Buffer 2 IBUFG Global Clock Input Buffer To access the dedicated routing only the IBUFGs on the same edge of the device top or bottom as the DCM can be used to drive a PSCLK input of the DCM 3 BUFGCTRL An Internal Global Buffer 4 Internal Clock Any internal clock using general purpose routing The frequency range of PSCLK is defined by PSCLK FREO LF HEF see the Virtex 4 Data Sheet This input must be tied to ground when the CLKOUT PHASE SHIFT attribute is set to NONE or FIXED Dynamic Reconfiguration Clock Input DCLK The dynamic reconfiguration clock DCLK input pin provides the source clock for the DCM s dynamic reconfiguration circuit The frequency of DCLK can be asynchronous in phase and frequency to CLKIN The dynamic reconfiguration clock signal is driven by any clock source external or internal including 1 IBUF Input Buffer 2 IBUFG Global Clock Input Buffer Only the IBUFGs on the same edge of the device top or bottom as the DCM can be used to drive a CLKIN input of the DCM 3 BUFGCTRL An Internal Global Buffer 4 Internal Clock Any internal clock using general purpose routing The frequency range of DCLK is described in the Virtex 4 Data Sheet When dynamic reconfiguration is not used this input must be tied to ground See the dynamic reconfiguration chapter in th
88. ans Reale o altero ble tte toe cuted a 35 I O Clock Buffer BUFIO seseeeeeeeee tte teen t 35 BUHO Primitive rrean e Ro OS ek AG ec Rue a a Rc ten eta pe dew dee fecutus a he 35 BUFIO Use Models l leeeeeeeee eer hrs 36 Regional Clock Buffer BUFR 2 2 occ III 37 BUFER Primitive iat er kde ba eae A Re Rx e Re E cR Rae Rina 37 BUFR Attributes and Modes 00 c cece eee 38 BUFR Use Models 00 ccc ccc eee a e eee een e eens 39 Regional Clock Nets i lees ek extet ese ep eek eee kl koe RUE RR EE E ER eade d 40 VHDL and Verilog Templates suse ee 41 BUFGCTRL VHDL and Verilog Templates n n 0 066 41 VHDE Template 28e perd pee dtes te eee eae eee dei ires 41 Verilog Template 45 45 oe ddnde uen esie autetn etii dis 42 Declaring Constraints in UCF File esses 42 BUFG VHDL and Verilog Templates 0 06 cece eee 43 VHDL Template nb tpa e pae db ee pl eet de ode A ee ees 43 Verilog Template serietips inda beds tree eger Gee esie ei eese edu ai 44 Declaring Constraints in UCF File esses 44 BUFGCE and BUFGCE 1 VHDL and Verilog Templates 44 VADE Template 3 24 eripe ri eCcUHbecep terere deca sd te bd cate quete 44 Verilog Template seres segis emer er ned sheet HERE RMLES LAE YN er dd 45 Declaring Constraints in UCF File cesses 45 BUFGMUX and BUFGMUX 1 VHDL and Verilog Templates 45 VEIDETemplate 2 cas temario br
89. at DDR mode IOBDELAY IBUF or NONE D pin Setup Hold with respect to CLK at DDR mode IOBDELAY IFD or BOTH IOBDELAY TYPE DEFAULT D pin Setup Hold with respect to CLK at DDR mode IOBDELAY IFD or BOTH IOBDELAY TYPE FIXED IOBDELAY VALUE 0 Sequential Delay Tiscko o CLKDIV to Out at Q pins Timing Characteristics In the timing diagrams of Figure 8 4 and Figure 8 5 the timing parameter names change for different modes SDR DDR However the names do not change when a different bus input width including when two ISERDES are cascaded together to form 10 bits In DDR mode the data input D switches at every CLK edge rising and falling 366 www xilinx com Virtex 4 User Guide UGO070 v1 5 March 21 2006 XILINX Input Serial to Parallel Logic Resources ISERDES Figure 8 4 illustrates an ISERDES timing diagram for the input data to the ISERDES 1 2 l o r liscck cg CE I qe Tsocko XL XC X X X Gl ug070 8 04 072904 Figure 8 4 ISERDES Input Data Timing Diagram Clock Event 1 e At time Tiscck cr before Clock Event 1 the clock enable signal becomes valid high and the ISERDES can sample data Clock Event 2 e Attime Trspcy p before Clock Event 2 the input data pin D becomes valid and is sampled at the next positive clock edge Figure 8 5 illustrates an ISERDES timing diagram for the output data from the ISERDES 1 2 CLKDIV i
90. bounce or Vcc bounce and is usually a combination of the two This bounce is a deviation of the die supply voltage die GND rail or die Vcc rail with respect to the voltage of the associated PCB supply PCB GND rail or PCB Verc rail The deviation of die supplies from PCB supplies comes from www xilinx com Virtex 4 User Guide UG070 v1 5 March 21 2006 X XILINX Simultaneous Switching Output Limits the voltage induced across power system parasitics by supply current transients One cause of current transients is output driver switching events Numerous output switching events occurring at the same time lead to bigger current transients and therefore bigger induced voltages ground bounce Vcc bounce or rail collapse Relevant transient current paths exist in the die package and PCB therefore parasitics from all three must be considered The larger the value of these parasitics the larger the voltage induced by a current transient power supply disturbance Vcc bounce affects stable high outputs Ground bounce affects stable low outputs Ground bounce also affects inputs configured as certain I O standards because they interpret incoming signals by comparing them to a threshold referenced to the die ground as opposed to I O standards with input thresholds referenced to a Vggg voltage If the die voltage disturbance exceeds the instantaneous noise margin for the interface then a non changing input or output can be interpreted a
91. can be applied to the LVTTL I O standard Table 6 2 Allowed Attributes for the LVTTL I O Standard Primitives Attributes IBUF IBUFG OBUF OBUFT IOBUF IOSTANDARD LVTTL LVTTL LVTTL CAPACITANCE LOW NORMAL DONT_CARE DRIVE UNUSED 2 4 6 8 12 16 24 2 4 6 8 12 16 24 SLEW UNUSED FAST SLOW FAST SLOW LVCMOS Low Voltage Complementary Metal Oxide Semiconductor LVCMOS is a widely used switching standard implemented in CMOS transistors This standard is defined by JEDEC JESD 8 5 Sample circuits illustrating both unidirectional and bidirectional LVCMOS termination techniques are shown in Figure 6 27 and Figure 6 28 LVCMOS z om gt IOB IOB LVCMOS LVCMOS Rg Zo Rp Dew x gt IOB Yr 0B LVCMOS LVCMOS Rp Zo Hon gt Note V is any voltage from OV to Voco ug070 6 27 071904 Figure 6 27 LVCMOS Unidirectional Termination 238 www xilinx com Virtex 4 User Guide UG070 v1 5 March 21 2006 X XILINX Virtex 4 User Guide Specific Guidelines for Virtex 4 I O Supported Standards LVCMOS gt 3 LVCMOS gt 3 IOB IOB LVCMOS x QA m gt lop Ym jin IOB Huc ines LVCMOS P3 om 53 gt Note V is any voltage from OV to Veco ug070 6 28 071904 Figure 6 28 LVCMOS Bidirectional Termination Table 6 3 details the allowed attributes that can be applied to the
92. data word available at DI into the FIFO whenever WREN is active a set up time before the rising WRCLK edge www xilinx com 139 UGO070 v1 5 March 21 2006 Chapter 4 Block RAM XILINX The read operation is also synchronous presenting the next data word at DO whenever the RDEN is active one set up time before the rising RDCLK edge Data flow control is automatic the user need not be concerned about the block RAM addressing sequence although WRCOUNT and RDCOUNT are also brought out if needed for unusual applications The user must however observe the FULL and EMPTY flags and stop writing when FULL is High and stop reading when EMPTY is High If these rules are violated an active WREN while FULL is High will activate the WRERR flag and an active RDEN while EMPTY is High will activate the RDERR flag In either violation the FIFO content will however be preserved and the address counters will stay valid Programmable ALMOSTFULL and ALMOSTEMPTY flags are brought out to give the user an early warning when the FIFO is approaching its limits Both these flag values can be set by configuration to almost anywhere in the FIFO address range Two operating modes affect the reading of the first word after the FIFO was empty e InStandard mode the first word written into an empty FIFO will appear at DO after the user has activated RDEN The user must pull the data out of the FIFO e In FWFT mode the first word written into an
93. empty FIFO will automatically appear at DO without the user activating RDEN The FIFO pushes the data onto DO The next RDEN will then pull the subsequent data word onto DO EMPTY Latency The rising edge of EMPTY is fast and inherently synchronous with RDCLK The empty condition can only be terminated by WRCLK asynchronous to RDCLK The falling edge of EMPTY must therefore artificially be moved onto the RDCLK time domain Since the two clocks have an unknown phase relationship it takes several cascaded flip flops to guarantee that such a move does not cause glitches or metastable problems The falling edge of EMPTY is thus delayed by several RDCLK periods after the first write into the previously empty FIFO This delay guarantees proper operation under all circumstances and causes an insignificant loss of performance after the FIFO had gone empty Table 4 9 shows the FIFO capacity in the two modes Table 4 9 FIFO Capacity Standard Mode FWFT Mode 4k 1 entries by 4 bits 4k 2 entries by 4 bits 2k 1 entries by 9 bits 2k 2 entries by 9 bits 1k 1 entries by 18 bits 1k 2 entries by 18 bits 512 1 entries by 36 bits 512 2 entries by 36 bits 140 www xilinx com Virtex 4 User Guide UG070 v1 5 March 21 2006 XILINX Top Level View of FIFO Architecture Top Level View of FIFO Architecture Figure 4 14 shows a top level view of the Virtex 4 FIFO architecture The read pointer write pointer and status flag lo
94. external reference resistors with resistance equal to the trace characteristic impedance Zp Sample circuits illustrating both unidirectional and bidirectional termination techniques for a controlled impedance driver are shown in Figure 6 29 and Figure 6 30 The DCI I O standards supporting a controlled impedance driver are LVDCI 15 LVDCI 18 LVDCI 25 and LVDCI 33 IOB IOB LVDCI LVDCI 4 oD Hw Ro ven Rvrp Zo ug070 6 29 071904 Figure 6 29 Controlled Impedance Driver with Unidirectional Termination www xilinx com Virtex 4 User Guide UGO070 v1 5 March 21 2006 XILINX Specific Guidelines for Virtex 4 I O Supported Standards LVDCI LVDCI Ro Rynw Rypgp Zo Ro Rynw Rypgp Zo ug070 6 30 071904 Figure 6 30 Controlled Impedance Driver with Bidirectional Termination LVDCI_DV2 A controlled impedance driver with half impedance source termination can also provide drivers with one half of the impedance of the reference resistors The I O standards supporting a controlled impedance driver with half impedance are LVDCI_DV2_15 LVDCI_DV2_18 and LVDCI_DV2_25 Figure 6 31 and Figure 6 32 illustrate a controlled driver with half impedance unidirectional and bidirectional termination To match the drive impedance to Zo when using a driver with half impedance the reference resistor R must be twice Zp IOB OB LVDCI_DV2 LVDCI_DV2
95. from array to array 200 www xilinx com Virtex 4 User Guide UGO070 v1 5 March 21 2006 XILINX CLB Primitives and Verilog VHDL Examples Creating Larger RAM Structures Wider and or deeper memory structures can be created using multiple distributed RAM instances Table 5 12 shows the generic VHDL and Verilog distributed RAM examples provided to implement n bit wide memories Table 5 12 VHDL and Verilog Submodules Submodules Primitive Size Type XC4V_RAM16XN_S RAMI6XIS 16wordsxn bit single port XC4V_RAM32XN_S RAM32X1S 32 words x n bit single port XC4V_RAM64XN_S RAM64X1S 64 words x n bit single port XC4AV RAMI6XN D RAM16X1D 16 words x n bit dual port By using the read write port for the write address and the second read port for the read address a FIFO that can read and write simultaneously is easily generated Simultaneous access doubles the effective throughput of the memory VHDL and Verilog Templates VHDL and Verilog templates are available for all single port and dual port primitives The number in each template indicates the number of bits for example RAM 165 is the template for the 16 x 1 bit RAM S indicates single port and D indicates dual port In VHDL each template has a component declaration section and an architecture section Each part of the template should be inserted within the VHDL design file The port map of the architecture section should include the design si
96. generic maps VHDL or defparams Verilog within the instantiated component Modifying the values of the generic map or defparam will effect both the simulation behavior and the implemented synthesis results Block RAM VHDL and Verilog Templates The following template is a RAMB16 example in both VHDL and Verilog This primitive is the building block for all different sizes of block RAM RAMB16 VHDL Template RAMB16 To incorporate this function into the design VHDL following instance declaration needs to be placed in instance the architecture body of the design code The declaration RAMB16 inst and or the port declarations code after the gt assignment can be changed to properly reference and connect this function to the design All inputs and outputs must be connected Library In addition to adding the instance declaration a use declaration statement for the UNISIM v components library needs for to be added before the entity declaration This library Xilinx contains the component declarations for all Xilinx primitives primitives and points to the models that will be used for simulation Copy the following two statements and paste them before the Entity declaration unless they already exist Library UNISIM use UNISIM vcomponents all Cut code below this line and paste into the architecture body gt RAMB16 Virtex 4 16k 2k Parity Param
97. gt and DIP lt 3 0 gt as shown in Table 4 2 120 www xilinx com Virtex 4 User Guide UGO070 v1 5 March 21 2006 XILINX Block RAM Port Signals Data Out Buses DO A B lt 0 gt and DOP A B lt 0 gt Data out buses reflect the contents of memory cells referenced by the address bus at the last active clock edge during a read operation During a write operation WRITE_FIRST or READ FIRST configuration the data out buses reflect either the data in buses or the stored value before write During a write operation in NO CHANGE mode data out buses are not affected The regular data out bus DO and the parity data out bus DOP when available have a total width equal to the port width as shown in Table 4 2 Cascade CASCADEIN A B The CASCADEIN pins are used to connect two block RAMs to form the 32K x 1 mode This pin is used when the block RAM is the UPPER block RAM and is connected to the CASCADEOUT pins of the LOWER block RAM When cascade mode is not used this pin does not need to be connected Refer to the Cascadable Block RAM for further information Cascade CASCADEOUT A B The CASCADEOUT pins are used to connect two block RAMs to form the 32K x 1 mode This pin is used when the block RAM is the LOWER block RAM and is connected to the CASCADEIN pins of the UPPER block RAM When cascade mode is not used this pin does not need to be connected Refer to the Cascadable Block RAM for further information Inve
98. instance name declaration FIFO16 1kx18 inst and or the port declarations code within the parenthesis can be changed to properly reference and connect this function to the design All inputs and outputs must be connected io Xee Cut code below this line gt FIFO16 Virtex 4 Block RAM Asynchrnous FIFO configured for 1k deep x 18 wide Nirtex 4 User Guide FIFO16 ALMOST FULL OFFSET 12 h000 Sets almost full threshold ALMOST EMPTY OFFSET 12 h000 Sets the almost empty threshold DATA WIDTH 36 Sets data width to 4 9 18 or 36 FIRST WORD FALL THROUGH FALSE Sets the FIFO FWFT to TRUE or FALSE FIFO16 inst ALMOSTEMPTY ALMOSTEMPTY 1 bit almost empty output flag ALMOSTFULL ALMOSTFULL 1 bit almost full output flag DO DO 32 bit data output DOP DOP 4 bit parity data output EMPTY EMPTY 1 bit empty output flag FULL FULL 1 bit full output flag RDCOUNT RDCOUNT 12 bit read count output RDERR RDERR 1 bit read error output WRCOUNT WRCOUNT 12 bit write count output WRERR WRERR 1 bit write error DI DI 32 bit data input DIP DIP 4 bit partity input RDCLK RDCLK 1 bit read clock input RDEN RDEN 1 bit read enable input RST RST 1 bit reset input WRCLK WRCLK 1 bit write clock input WREN WREN 1 bit write enable input
99. o Bcc 230 IBUFDS and IBUFGDS sussseeeeseeeee a hh 230 OBUEDJOS reru tipiena s ee qo eng vice diesen tere UR tain Ane don RU cr e c rRNA 231 OBUFIDS enr rey rr aee eee end ee ey A D e e EE v n oe rs 231 IOBUEDS 252i tel RR DR eme b PR esa pte ade e ai E tado aces ile ae tede uns ud 231 Virtex 4 SelectIO Attributes Constraints leen 232 Location Constraints ys desiu seanu RE 4 et RN RRERER X EN vada d RI ae 232 IOStatidard Attribute 11232 panded REOS bate tah EAD REY ROS T P DS EE 232 Output Slew Rate Attributes 0 0 6 e ne 232 Output Drive Strength Attributes csse eee 233 Lower Capacitance I O Attributes 0 0 cece cee 233 PULLUP PULLDOWN KEEPER for IBUF OBUFT and IOBUF 233 Differential Termination Attribute llle rn 234 Virtex 4 I O Resource VHDL Verilog Examples seeeeee 234 VHDL Template ves oi hola kysi ev eve EN beer ieee ied uvas 234 Verilog Template rriena aa EEE eripit ea peer iu peu dian ay ae ira 235 Specific Guidelines for Virtex 4 I O Supported Standards 235 LVTTL Low Voltage Transistor Transistor Logic 0 00000005 236 LVCMOS Low Voltage Complementary Metal Oxide Semiconductor 238 LVDCI Low Voltage Digitally Controlled Impedance sees 240 LVDCI DV2 cziekreeee see eae du rope ese uer es Peau awa Mae da 241 HSLVDCI High Speed Low Voltage Digitally Controlled Impedance 242 PCI
100. of the SLAVE 4 The SLAVE only uses the ports D3 to D6 as an input www xilinx com Virtex 4 User Guide 380 UGO070 v1 5 March 21 2006 XILINX OSERDES Latencies The input to output latencies of OSERDES blocks depend on the DATA_RATE and Output Parallel to Serial Logic Resources OSERDES DATA_WIDTH attributes Latency is defined as the number of slow clock CLKDIV cycles needed to sample the parallel data into OSERDES followed by the number of fast clock CLK cycles needed for the OSERDES to deliver the first serialized data into the QQ output after the parallel data is sampled Table 8 10 summarizes the various OSERDES latency values Table 8 10 OSERDES Latencies DATA_RATE DATA_WIDTH Latency SDR 2 1 1 CLKDIV cycle and 1 CLK cycle 3 1 1 CLKDIV cycle and 3 CLK cycle 4 1 1 CLKDIV cycle and 4 CLK cycle 5 1 1 CLKDIV cycle and 4 CLK cycle 6 1 1 CLKDIV cycle and 5 CLK cycle 7 1 1 CLKDIV cycle and 5 CLK cycle 8 1 1 CLKDIV cycle and 6 CLK cycle DDR 4 1 1 CLKDIV cycle and 1 CLK cycle 6 1 1 CLKDIV cycle and 3 CLK cycle 8 1 1 CLKDIV cycle and 4 CLK cycle 10 1 1 CLKDIV cycle and 4 CLK cycle OSERDES Timing Model and Parameters This section discusses all timing models associated with the OSERDES primitive Table 8 11 describes the function and control signals of the OSERDES switching characteristics in the Virtex 4 Data Sheet Table 8 11 OSERDES Switching Characteris
101. output of a DCM connects to a global buffer on the same top or bottom half of the device The output of the global buffer connects to the CLKFB input of the same DCM During the external feedback configuration the following rules apply 1 To forward the clock the CLKO of the DCM must directly drive an OBUF or a BUFG to DDR configuration 2 External to the FPGA the forwarded clock signal must be connected to the IBUFG GCLK pin or the IBUF driving the CLKFB of the DCM Both CLK and CLKFB should have identical I O buffers Figure 2 8 and Figure 2 9 in Application Examples page 77 illustrate clock forwarding with external feedback configuration www xilinx com Virtex 4 User Guide UG070 v1 5 March 21 2006 XILINX DCM Ports The feedback clock input signal can be driven by one of the following buffers 1 IBUFG Global Clock Input Buffer This is the preferred source for an external feedback configuration When an IBUFG drives a CLKFB pin of a DCM in the same top or bottom half of the device the pad to DCM skew is compensated for deskew 2 BUFGCTRL Internal Global Clock Buffer This is an internal feedback configuration 3 IBUF Input Buffer This is an external feedback configuration When IBUF is used the PAD to DCM input skew is not compensated Phase Shift Clock Input PSCLK The phase shift clock PSCLK input pin provides the source clock for the DCM phase shift The PSCLK can be asynchronous in phase
102. refclk RST gt rst_2 Ma dlyctrl n IDELAYCTRL port map RDY rdy n REFCLK refclk RST gt rst n di The user should either declare the LOC constraints in the VHDL design file or in the UCF file Declaring LOC constraints in the VHDL file attribute loc string attribute loc of dlyctrl 1 1abel is IDELAYCTRL_X0OYO attribute loc of dlyctrl 2 1abel is IDELAYCTRL XO0Y1 attribute loc of dlyctrl n label is IDELAYCTRL XnYn Declaring LOC constraints in the UCF file INST dlyctrl 1 LOC IDELAYCTRL X0Y0 INST dlyctrl 2 LOC IDELAYCTRL X0Y1 INST dlyctrl n LOC IDELAYCTRL XnYn One instantiation of an IDELAYCTRL primitive without LOC constraint RST and RDY port signals are independent from LOC ed instances dlyctrl noloc IDELAYCTRL port map RDY rdy noloc REFCLK refclk RST rst noloc di Virtex 4 User Guide www xilinx com 339 UG070 v1 5 March 21 2006 Chapter 7 SelectlO Logic Resources XILINX Verilog Use Model Multiple instantiations of IDELAYCTRL primitives with LOC contraints Each instance has its own RST and RDY signal to allow for partial reconfiguration The REFCLK signal is common to all instances LOC and replicated instances IDELAYCTRL dlyctrl 1 RDY rdy 1 REFCLK refclk RSTi rst 1 Ju IDELAYCTRL dlyctrl 2 RDY rdy 2 REFCLK refclk RST rst 2
103. region This clock must be driven by a global clock buffer BUFGCTRL REFCLK must be Fipgraycrri REF the specified ppm tolerance IDELAYCTRL_REF_PRECISION to guarantee a specified IDELAY resolution TIDELAYRESOLUTION REFCLK can be supplied directly from a user supplied source or from the DCM and must be routed on a global clock buffer Table 7 10 shows possible DCM and clock configurations for sources of REFCLK These configurations are fully characterized Table 7 10 Generating Reference Clock from DCM Input Clock MHz M D 25 8 30 20 33 3 40 50 66 7 75 100 l2 00 wy AI Oo O oaol m B mn B mnmb mB i cgo mn RDY Ready The ready RDY signal indicates when the IDELAY modules in the specific region are calibrated The RDY signal is deasserted if REFCLK is held High or Low for one clock period or more If RDY is deasserted Low the IDELAYCTRL module must be reset The implementation tools allow RDY to be unconnected ignored Figure 7 14 illustrates the timing relationship between RDY and RST IDELAYCTRL Timing Table 7 11 shows the IDELAYCTRL switching characteristics Table 7 11 IDELAYCTRL Switching Characteristics Symbol Description FIDELAYCTRL REF REFCLK frequency IDELAYCTRL REF PRECISION REFCLK precision TipELAYCTRL RPW Reset pulse width TIDELAYCTRLCO_RDY Reset Startup to Ready for IDELAYCTRL www xilinx com 331 UG070 v1 5 March 21 2006
104. registers allows connecting the last bit of one shift register to the first bit of the next without using the LUT D output See Figure 5 11 Longer shift registers can be built with dynamic access to any bit in the chain The shift register chaining and the MUXF5 and MUXF6 multiplexers allow up to a 64 bit shift register with addressable access to be implemented in one CLB 174 www xilinx com Virtex 4 User Guide UGO070 v1 5 March 21 2006 XILINX CLB Overview 1 Shift Chain in CLB SRLC16 i unavailable in this slice DI FF gt FF gt SLICE S3 SRLC16 i unavailable in this slice DI FF gt FF gt SLICE S1 SHIFTIN SRLC16 MC15 SHIFTIN DI D SRLC16 MC15 DI p SRLC16 MC15 SLICE SO CLB l l l l l l l l l l l l l l l l l l l l l l l l l l l l DI D l l l l l l l l l l l l l l l l l l l l l l l l l l l l CASCADABLE OUT ug070_5_11_071504 Figure 5 11 Cascadable Shift Register Virtex 4 User Guide www xilinx com 175 UG070 v1 5 March 21 2006 176 Chapter 5 Configurable Logic Blocks CLBs XILINX The block diagrams of the shift register SRL16E and the cascadable shift register SRLC16E are illustrated in Figure 5 12 The pin descriptions of SRL16E and SRLC16E are located in the SRL Primitives and Submodules section SRLC16E D Q Address SRL16E CE CLK Q15 D Q Address CE SRLC16E CLK D Q Address
105. requires one clock edge Virtex 4 User Guide www xilinx com 109 UGO070 v1 5 March 21 2006 Chapter 4 Block RAM XILINX e A read operation requires one clock edge e DO has an optional internal pipeline register e Data input and output signals are always described as buses that is in a 1 bit width configuration the data input signal is DI 0 and the data output signal is DO 0 Block RAM Introduction Synchronous In addition to distributed RAM memory Virtex 4 devices feature a large number of 18 Kb block RAM memories True Dual Port RAM offers fast blocks of memory in the device Block RAMs are placed in columns and the total number of block RAM memory depends on the size of the Virtex 4 device The 18 Kb blocks are cascadable to enable a deeper and wider memory implementation with a minimal timing penalty Embedded dual or single port RAM modules ROM modules synchronous FIFOs and data width converters are easily implemented using the Xilinx CORE Generator block memory modules Asynchronous FIFOs can be generated using the CORE Generator FIFO Generator module The synchronous or asynchronous FIFO implementation does not require additional CLB resources for the FIFO control logic since it uses dedicated hardware resources Dual Port and Single Port RAMs Data Flow 110 The 18 Kb block RAM dual port memory consists of an 18 Kb storage area and two completely independent access ports A and B The structure
106. resources Table 6 43 Equivalent Vcco GND Pairs per Bank Non Sparse Chevron Bank Number Package Virtex 4 LX Family 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SF363 1 05 05 1 1 ETAIET IE UE drm FF668 2 Virtex 4 SX Family FF668 2 2 2 2 2 45 5 5 4 3 3 ge a Notes 1 These numbers are based on the package files and device pinout Some of the numbers are not integers as these banks share their GND pin with other banks Most of the limitations are based on the availability of GND pins in the vicinity of the bank There are a few instances where the limitation is due to Vcco pins 2 Bank 0 in all devices contains no user I O Therefore SSO analysis is unnecessary for Bank 0 Actual SSO Limits versus Nominal SSO Limits The Virtex 4 SSO limits are defined in for a set of nominal system conditions in Table 6 40 and Table 6 42 To compute the actual limits for a specific user s system the automated Parasitic Factors Derating Method PFDM must be used The PFDM allows the user to account for differences between actual and nominal PCB power systems receiver capacitive loading and maximum allowable ground bounce or Vcc bounce A spreadsheet calculator Full Device SSO Calculator automates this process Electrical Basis of SSO Noise 302 Power supply disturbance can take the form of ground
107. signal is stable at the FULL outputs of the FIFO Trco RDERR Reset to read error RDERR Time after reset that the Read error signal is stable output at the RDERR outputs of the FIFO Trco wRERR Reset to write error WRERR Time after reset that the Write error signal is stable output at the WRERR outputs of the FIFO Trco RDCOUNT Reset to read pointer RDCOUNT Time after reset that the Read pointer signal is output stable at the RDCOUNT outputs of the FIFO Trco wRCOUNT Reset to write pointer WRCOUNT Time after reset that the Write pointer signal is output stable at the WRCOUNT outputs of the FIFO Notes 1 Trcko po includes parity output Trcko pop 2 In the Virtex 4 Data Sheet TECKO_AEMPTY TECKO_AFULL TECKO_EMPTY Trcko FULL TRCKO_RDERR TFCKO_WRERR are combined into TrCKO FLAGS 3 In the Virtex 4 Data Sheet TECKO_RDCOUNT and TECKO_WRCOUNT are combined into TECKO_POINTERS e Trcpcxk pi includes parity inputs Tgcpck prp 5 In the Virtex 4 Data Sheet WRITE and READ enables are combined into Tgcck gw Virtex 4 User Guide UGO070 v1 5 March 21 2006 www xilinx com 149 Chapter 4 Block RAM XILINX FIFO Timing Characteristics The various timing parameters in the FIFO are described in this section There is also additional data on FIFO functionality The timing diagrams describe the behavior in these five cases e Case 1 Writing to an Empty FIFO e Case 2 Writing to a Full or Almost Full FIFO
108. signaling RocketIO signaling power distribution systems PCB breakout and parts placement e Virtex 4 Packaging Specifications This specification includes the tables for device package combinations and maximum I Os pin definitions pinout tables pinout diagrams mechanical drawings and thermal specifications e Virtex 4 RocketIO Multi Gigabit Transceiver User Guide This guide describes the RocketIO Multi Gigabit Transceivers available in the Virtex 4 FX family e Virtex A4 Tri mode Ethernet Media Access Controller This guide describes the Tri mode Ethernet Media Access Controller available in the Virtex 4 FX family e PowerPC 405 Processor Block Reference Guide This guide is updated to include the PowerPC 405 processor block available in the Virtex 4 FX family Additional Support Resources To search the database of silicon and software questions and answers or to create a technical support case in WebCase see the Xilinx website at http www xilinx com support Typographical Conventions This document uses the following typographical conventions An example illustrates each convention Convention Meaning or Use Example he Vi 4 j ti References to other documents cage EE Cons 3 in jid Guide for more information Italic font The address F is asserted after Emphasis in text clock event 2 Underlined Text Indicates a link to a web page http www xilinx com virtex4 18
109. the D input of both registers and is reflected on the Q1 output of input register 1 at time Tick after Clock Event 1 Clock Event 2 e Attime Typocy before Clock Event 2 falling edge of CLK the input signal becomes valid low at the D input of both registers and is reflected on the Q2 output of input register 2 at time Tjcko after Clock Event 2 no change in this case Clock Event 9 e At time Tyspcy before Clock Event 9 the SR signal configured as synchronous reset in this case becomes valid high resetting IFF1 O1 at time Tjcko after Clock Event 9 and IFF2 Q2 at time TicKg after Clock Event 10 Virtex 4 User Guide www xilinx com 319 UGO070 v1 5 March 21 2006 Chapter 7 SelectlO Logic Resources XILINX Table 7 5 describes the function and control signals of the ILOGIC switching characteristics in the Virtex 4 Data Sheet Table 7 5 LOGIC Switching Characteristics Symbol Description Setup Hold Ticrick TickcEl CE1 pin Setup Hold with respect to CLK TicecK Tickck DLYCE pin Setup Hold with respect to CLKDIV TirstcK Ticxrst DLYRST pin Setup Hold with respect to CLKDIV TrnccKk Ticxinc DLYINC pin Setup Hold with respect to CLKDIV Tisrck TicksR SR REV pin Setup Hold with respect to CLK Tipock Tiockp D pin Setup Hold with respect to CLK without Delay Tipockp liockpp D pin Setup Hold with respect to CLK IOBDELAY TYPE DEFAULT D pin Setup Hold with respect to CLK IOBDELAY T
110. the logic resources in one CLB All of the CLBs are identical and each CLB or slice can be implemented in one of the configurations listed Table 5 2 shows the available resources in all CLBs Table 5 1 Logic Resources in One CLB Arithmetic amp Distributed Shift Slices LUTs Flip Flops MULT ANDs Carry Chains RAM 1 Registers 1 4 8 8 8 2 64 bits 64 bits Notes 1 SLICEM only www xilinx com Virtex 4 User Guide UG070 v1 5 March 21 2006 XILINX CLB Overview Table 5 2 Virtex 4 Logic Resources Available in All CLBs Device cu Arty Number of NDE Distributed RAM or MUM Shift Registers Kb XCAVLXI15 64 x 24 6 144 12 288 96 12 288 XCAVLX25 96 x 28 10 752 21 504 168 21 504 XCAVLX40 128 x 36 18 432 36 864 288 36 864 XCA4VLX60 128 x 52 26 624 53 248 416 53 248 XC4VLX80 160 x 56 35 840 71 680 560 71 680 XC4VLX100 192 x 64 49 152 98 304 768 98 304 XC4VLX160 192 x 88 67 584 135 168 1056 135 168 XCAVLX200 192 x 116 89 088 178 176 1392 178 176 XC4VSX25 64 x 40 10 240 20 480 160 20 480 XC4VSX35 96 x 40 15 360 30 720 240 30 720 XC4VSX55 128 x 48 24 576 49 152 384 49 152 XCAVFEX12 64 x 24 5472 10 944 86 10 944 XCAVFX20 64 x 36 8 544 17 088 134 17 088 XC4AVFX40 96 x 52 18 624 37 248 291 37 248 XCAVFX60 128 x 52 25 280 50 560 395 50 560 XCAVFX100 160 x 68 42 176 84 352 659 84 352 XCAVFEX140 192x 84 63 168 126 336 987 126 336
111. the output data is stable at the DO Min DO outputs of the block RAM with output register Notes 1 While EN is active ADDR inputs must be stable during the entire setup hold time window even if WEN is inactive Violating this requirement can result in block RAM data corruption If ADDR timing could violate the specified requirements EN must be inactive disabled 136 Virtex 4 User Guide UG070 v1 5 March 21 2006 www xilinx com XILINX Block RAM Timing Model Block RAM Timing Characteristics The timing diagram in Figure 4 12 describes a single port block RAM in write first mode without the optional output register The timing for read first and no change modes are similar For timing using the optional output register an additional clock latency appears at the DO pin CLK Ae ft mE L ERE DI D X DDD X ccce gt 0000 eet DO DO MEM 00 gt CCCC MEM 7E 0101 ADDR EN SSR p TRCCK EN TRCCK_SSR TRCCK WEN WM GM xD C MEN IMEEM EMT Disabled Read Write Read Reset Disabled WEN Write Mode WRITE_FIRST SRVAL 0101 ug070 4 12 071204 Figure 4 12 Block RAM Timing Diagram At time 0 the block RAM is disabled EN enable is Low Clock Event 1 Read Operation During a read operation the contents of the memory at the address on the ADDR inputs are unchanged e Trcck_ADprR before clock event 1 address 00 becomes valid at the AD
112. the training pattern is seen The tables in Figure 8 7 illustrate the effects of a Bitslip operation in SDR and DDR mode For illustrative purposes the data width is eight The Bitslip operation is synchronous to CLKDIV In SDR mode every Bitslip operation causes the output pattern to shift left by one In DDR mode every Bitslip operation causes the output pattern to alternate between a shift right by one and shift left by three In this example on the eighth Bitslip operation the output pattern reverts to the initial pattern This assumes that serial data is an eight bit repeating pattern www xilinx com 371 UGO070 v1 5 March 21 2006 Chapter 8 Advanced SelectlO Logic Resources XILINX Bitslip Operation in SDR Mode Bitslip Operation in DDR Mode Bitslip Output Bitslip Output Operations Pattern 8 1 Operations Pattern 8 1 Executed Executed 6 11100100 6 11001001 ug070 8 16 072604 Figure 8 7 Bitslip Operation Examples Figure 8 8 illustrates the ISERDES configured in Bitslip mode Two ISERDES modules are in a master slave configuration for a data width of eight The Bitslip operation in SDR mode is also shown IOB SERDES MODE MASTER 1st 2nd 3th 4th 5th 6th 7th 8th Bitslip BITSLIP ENABLE TRUE Initial Bitslip Bitslip Bitslip Bitslip Bitslip Bitslip Bitslip Back to initial Note 1 1001 0011 Q1 1 1 1 0 0 1 0 0 1 Q2 0 1
113. time Toscck ocr before Clock Event 1 CLK the output clock enable pin becomes valid high at the OCE input of the OSERDES enabling the output register to transmit data to the OQ output Clock Event 2 e At time Tospck p before Clock Event 2 CLKDIV data on the D1 and D2 inputs become valid e Attime Toscko oc after Clock Event 2 CLK data appears at the OQ output Clock Event 3 e At Clock Event 3 the reset signal is asserted High an asynchronous reset e At time Tosco oo after Clock Event 3 the OQ output is asynchronous reset to zero 382 www xilinx com Virtex 4 User Guide UGO070 v1 5 March 21 2006 XILINX Output Parallel to Serial Logic Resources OSERDES The timing diagrams in Figure 8 14 and Figure 8 15 illustrate the OSERDES data I O ports and their relationship with CLK and CLKDIV ecl LIB BEL CE GO FO FU OF CLKDV d LL D1 DIA D1B D1C D6 D6A D6B D6C ug070 8 14 033105 Figure 8 14 Example SDR 6 1 OSERDES Operation ae Jon fea on een 20 eso 0 Joo ug070 8 15 033105 Figure 8 15 Example DDR 6 1 OSERDES Operation In Figure 8 16 the timing of a 2 1 SDR 3 state control serialization is illustrated The timing parameter names and behavior do not change for different bus widths including when two OSERDES are cascaded together The same examples apply for DDR mode with the exception that OQ switches at every CLK edge rising and falling CLKDIV
114. to the DCM feedback path decreases the effective delay of the actual clock path from the FPGA clock input pin to the clock input of any flip flop Decreasing the clock delay increases the setup time represented in the input flip flop and reduces any positive hold times required The clock path delay includes the delay through the IBUFG route DCM BUFG and clock tree to the destination flip flop If the feedback delay equals the clock path delay the effective clock path delay is zero System Synchronous Setting Default By default the feedback delay is set to system synchronous mode The primary timing requirements for a system synchronous system are non positive hold times or minimally positive hold times and minimal clock to out and setup times Faster clock to out and setup times allow shorter system clock periods Ideally the purpose of a DLL is to zero out the clock delay to produce faster clock to out and non positive hold times The system synchronous setting default for DESKEW ADJUST configures the feedback delay element to guarantee non positive hold times for all input IOB registers The exact delay number added to the feedback path is device size dependent This is determined by characterization In the timing report this is included as timing reduction to input clock path represented by the Tpcwrvo parameter As shown in Figure 2 4 the feedback path includes tap delays in the default setting red line The pin to pin timing par
115. www xilinx com Virtex 4 User Guide UG070 v1 5 March 21 2006 XILINX Chapter 1 Clock Resources Global and Regional Clocks For clocking purposes each Virtex 4 device is divided into regions The number of regions varies with device size eight regions in the smallest device to 24 regions in the largest one Global Clocks Each Virtex 4 device has 32 matched skew global clock lines that can clock all sequential resources on the whole device CLB block RAM DCMs and I O and also drive logic signals Any eight of these 32 global clock lines can be used in any region Global clock lines are only driven by a global clock buffer and can also be used as a clock enable circuit or a glitch free multiplexer It can select between two clock sources and can also switch away from a failed clock source this is new in the Virtex 4 architecture A global clock buffer is often driven by a Digital Clock Manager DCM to eliminate the clock distribution delay or to adjust its delay relative to another clock There are more global clocks than DCMs but a DCM often drives more than one global clock Regional Clocks and I O Clocks Each region has two clock capable regional clock inputs Each input can differentially or single endedly drive regional clocks and I O clocks in the same region and also in the region above or below i e in up to three adjacent regions The regional clock buffer can be programmed to divide the incoming cl
116. yes rub ER EE PK ESE OEE n b ER ERE oa Se 121 OIR erer eer AAEREN SE RE eased eees sees sacs RUE sedans EP DE RR EEG CERE 121 Urused Inputs cesses ines che ge oats een HORE Ye qned iori qae ete eue 121 Block RAM Address Mapping sssussssssssse eee 122 Block RAM Attributes sssssssssssssssss e 122 Content Initialization INIT xx cc RR RR hs 122 Content Initialization INITP xx seseeeeee RR RR e 123 Output Latches Initialization INIT INIT A amp INIT B ssssesss 123 Output Latches Synchronous Set Reset SRVAL SRVAL A amp SRVAL B 123 Optional Output Register On Off Switch DO A BJ_LREG 0 124 Clock Inversion at Output Register Switch INVERT CLK DO A B REG 124 Extended Mode Address Determinant RAM EXTENSION AB 124 Read Width READ WIDTH A B 2 cece ee eee eee eee 124 Write Width WRITE_WIDTH_ A B 00 eee eee eee eee 124 Write Mode WRITE_MODE_ A B 0 0 cece eee eee eee eee 124 Block RAM Location Constraints 0 0000s 124 Block RAM Initialization in VHDL or Verilog Code 125 Block RAM VHDL and Verilog Templates 0 0 00008 125 RAMBI6 VHDL Template 2 ee be e ERR e EP eee 125 RAMB16 Verilog Templates sir reisti irei e e ee 9 eR RR ceva 129 Additional RAMB16 Primitive Design Considerations 131
117. 0 and 270 phases of CLKO to make CLK90 CLK180 and CLK270 clock outputs The 180 phase of CLK2X and CLKFX provide the respective CLK2X180 and CLKFX180 clock outputs There are also four modes of fine grained phase shifting fixed variable positive variable center and direct modes Fine grained phase shifting allows all DCM output clocks to be phase shifted with respect to CLKIN while maintaining the relationship between the coarse phase outputs With fixed mode a fixed fraction of phase shift can be defined during configuration and in multiples of the clock period divided by 256 Using the variable positive and variable center modes the phase can be dynamically and repetitively moved forward and backwards by 1 256 of the clock period With the www xilinx com 51 Chapter 2 Digital Clock Managers DCMs XILINX direct mode the phase can be dynamically and repetitively moved forward and backwards by the value of one DCM_TAP See the DCM Timing Parameters section in the Virtex 4 Data Sheet e Dynamic Reconfiguration There is a bus connection to the DCM to change DCM attributes without reconfiguring the rest of the device For more information see the Dynamic Reconfiguration chapter of the Virtex 4 Configuration Guide The DADDR 6 0 DI 15 0 DWE DEN DCLK inputs and DO 15 0 and DRDY outputs are available to dynamically reconfigure select DCM functions With dynamic reconfiguration DCM attributes can be changed to select a di
118. 0 boolean boolean Jes port O out std ulogic CEO in std ulogic CE1 in std ulogic I0 in std ulogic Ij in std ulogic IGNOREO in std ulogic IGNORE1 in std ulogic S0 in std ulogic S1 in std ulogic J end component Example BUFGCTRL instantiation U_BUFGCTRL BUFGCTRL Port map O gt user_o CE0 gt user_ce0 CE1 gt user cel IO gt user i0 Il gt user i1 IGNOREO gt user ignoreO IGNORE1 gt user ignorel SO gt user sO0 S1 gt user s1 Jor Declaring constraints in VHDL file attribute INIT OUT integer attribute PRESELECT I0 boolean attribute PRESELECT I1 boolean attribute LOC string attribute INIT OUT of U BUFGCTRL attribute PRESELECT IO of U BUFGCTRL attribute PRESELECT I1 of U BUFGCTRL attribute LOC of U BUFGCTRL label is false false label is 0 label is FALSE label is FALSE BUFGCTRL_X Y where is valid integer locations of BUFGCTRL www xilinx com UG070 v1 5 March 21 2006 41 Chapter 1 Clock Resources XILINX Verilog Template Example BUFGCTRL module declaration module BUFGCTRL O CEO CE1 IO I1 IGNOREO IGNORE1 SO S1 output O input CEO input CE1 input I0 input I1 input IGNOR input IGNORI input S0 input S1 parameter INIT OUT 0 parameter PRESELECT IO FALSE parameter PRESELECT I1 FALSE endmodule Example BUFGCTRL instantiation BUFGCTRL U BUFGCTRL O user 0 CEO
119. 0 3 5 4 0 4 5 N 5 0 5 5 6 0 6 5 7 0 7 5 8 9 This feature provides automatic 10 11 12 13 14 15 16 duty cycle correction such that the CLKDV output pin has a 50 50 duty cycle always in low frequency mode as well as for all integer values of the division factor N in high frequency mode CLKFX_DIVIDE Integer 1 to 32 1 CLKFX_MULTIPLY Integer 2 to 32 4 CLKIN_PERIOD This specifies the source clock Real in ns 0 0 period to help DCM adjust for optimum CLKFX CLKFX180 outputs Virtex 4 User Guide www xilinx com 65 UG070 v1 5 March 21 2006 Chapter 2 Digital Clock Managers DCMs Table 2 7 DCM Attributes Continued 2 XILINX DCM Attribute Name Description Values Default Value CLKIN_DIVIDE_BY_2 This attribute allows for the input Boolean FALSE or TRUE FALSE clock frequency to be divided in half when such a reduction is necessary to meet the DCM input clock frequency requirements CLKOUT_PHASE_SHIFT This attribute specifies the phase String NONE or FIXED NONE shift mode or VARIABLE_POSITIVE or VARIABLE CENTER or DIRECT DESKEW ADJUST This affects the amount of delay in String SYSTEM _ the feedback path and should be SYSTEM SYNCHRONOUS SYNCHRONOUS used for source synchronous or interfaces SOURCE_SYNCHRONOUS DFS_FREQUENCY_MODE This specifies the frequency mode String LOW or HIGH LOW of the frequency synthesizer DLL_FREQ
120. 0 9V DIFF SSTL18 II Q DIFF_SSTL18_ll m 500 200 200 x wv 2 wrx DIFF SSTL18 II DIFF SSTL18 Il 200 500 500 200 Pj ga m DIFF_SSTL18_ll DIFF_SSTL18_ll ug070_6_69_071904 Figure 6 71 Differential SSTL 1 8V Class II with Bidirectional Termination 280 www xilinx com Virtex 4 User Guide UG070 v1 5 March 21 2006 2 XILINX DCI Specific Guidelines for Virtex 4 I O Supported Standards Figure 6 72 shows a sample circuit illustrating a valid termination technique for CSE differential SSTL Class II 1 8V with bidirectional DCI termination DIFF SSTL18 Il DCI Ro 20 DIFF SSTL18 Il DCI IOB 2Rypp 2Zg 1000 2Rypy 2Zo 1002 Ro 200 DIFF SSTL18 II DCI Veco 1 8V 2Rygp 2Zg 1002 2Rygw 2Z9 1000 IOB DIFF SSTL18 Il DCI 2Rygp 2Zo 1002 2Rypy 2Zg 1000 Rp 200 E DIFF SSTL18 Il DCI Ro 202 Veco 1 8V CcoO DIFF SSTL18 Il DCI 2Rypp 2Zg 1000 gt 2Rypy 2Zo 1002 ug070_6_70_022406 Figure 6 72 Differential SSTL 1 8V Class II with DCI Bidirectional Termination Virtex 4 User Guide UG070 v1 5 March 21 2006 Table 6 30 lists the differential SSTL 1 8V Class II DC voltage specifications Table 6 30 Differential SSTL 1 8V Class Il DC Voltage Specifications Min Typ Max Veco 1 7 1 8 1 9 Input Parameters VTT Vccox 0 5
121. 00 www xilinx com Virtex 4 User Guide UG070 v1 5 March 21 2006 XILINX Simultaneous Switching Output Limits Step 2 Calculate the Adjacent Bank SSO Average for All Adjacent Bank Pairs Ensure the adjacent bank averages do not exceed 105 of the SSO allowance First calculate the adjacent bank SSO average for Banks 7 and 11 and check against 105 of SSO allowance Adjacent Bank SSO Average 7 11 SSO of bank 7 SSO of bank 11 2 15 80 2 47 5 SSO allowance x 105 gt adjacent bank SSO average 7 11 79 2 gt 47 5 OK Then calculate adjacent bank SSO average for all adjacent bank pairs If the average SSO of two adjacent banks exceeds 105 of the SSO allowance apply ground bounce reduction techniques to one or both of these two banks until the average SSO of all adjacent bank pairs is less than or equal to 105 of the SSO allowance Step 3 Calculate the Package SSO Ensure the package SSO does not exceed the SSO allowance All Bank SSO average Sum of SSO from all banks number of banks available in the package 51 51 0 60 35 40 15 30 12 22 80 0 5 60 14 32 2 SSO allowance gt All Bank SSO average 75 4 gt 32 9 OK If the package SSO exceeds the SSO allowance apply ground bounce reduction techniques to one or more of all I O banks until the all bank SSO average is less than or equal to the SSO allowance Full Device SSO Calculator Virtex 4 User Guide
122. 0000000000000 INIT 05 256 h0000000000000000000000000000000000000000000000000000000000000000 INIT 06 256 h0000000000000000000000000000000000000000000000000000000000000000 INIT 07 256 h0000000000000000000000000000000000000000000000000000000000000000 INIT 08 256 h0000000000000000000000000000000000000000000000000000000000000000 INIT 09 256 h0000000000000000000000000000000000000000000000000000000000000000 INIT 0A 256 h0000000000000000000000000000000000000000000000000000000000000000 INIT 0B 256 h0000000000000000000000000000000000000000000000000000000000000000 INIT 0C 256 h0000000000000000000000000000000000000000000000000000000000000000 INIT 0D 256 h0000000000000000000000000000000000000000000000000000000000000000 INIT 0E 256 h0000000000000000000000000000000000000000000000000000000000000000 INIT 0F 256 h0000000000000000000000000000000000000000000000000000000000000000 D D 1 D D D F D INIT 10 256 h0000000000000000000000000000000000000000000000000000000000000000 INIT 11 256 h0000000000000000000000000000000000000000000000000000000000000000 INIT 12 256 h0000000000000000000000000000000000000000000000000000000000000000 INIT 13 256 h0000000000000000000000000000000000000000000000000000000000000000 INIT 14 256 h0000000000000000000000000000000000000000000000000000000000000000 INIT 15 256 h0000000000000000000000000000000000000000000000000000000000000000 INIT 16 256 h000000000000000000000
123. 0000000000000000 INIT 20 gt X 0000000000000000000000000000000000000000000000000000000000000000 INIT 21 gt X 0000000000000000000000000000000000000000000000000000000000000000 INIT 22 gt X 0000000000000000000000000000000000000000000000000000000000000000 INIT 23 gt X 0000000000000000000000000000000000000000000000000000000000000000 INIT 24 gt X 0000000000000000000000000000000000000000000000000000000000000000 INIT 25 gt X 0000000000000000000000000000000000000000000000000000000000000000 INIT 26 gt X 0000000000000000000000000000000000000000000000000000000000000000 INIT 27 gt X 0000000000000000000000000000000000000000000000000000000000000000 INIT 28 gt X 0000000000000000000000000000000000000000000000000000000000000000 INIT 29 gt X 0000000000000000000000000000000000000000000000000000000000000000 INIT 2A gt X 0000000000000000000000000000000000000000000000000000000000000000 INIT 2B gt X 0000000000000000000000000000000000000000000000000000000000000000 INIT 2C gt X 0000000000000000000000000000000000000000000000000000000000000000 INIT 2D gt X 0000000000000000000000000000000000000000000000000000000000000000 INIT 2E gt X 0000000000000000000000000000000000000000000000000000000000000000 INIT 2F gt X 0000000000000000000000000000000000000000000000000000000000000000 gt gt gt gt gt gt www xilinx com 127 Chapter 4 Block RAM XILI
124. 000000000000000000000000000 INIT 2B 256 h0000000000000000000000000000000000000000000000000000000000000000 INIT_2C 256 h0000000000000000000000000000000000000000000000000000000000000000 INIT 2D 256 h0000000000000000000000000000000000000000000000000000000000000000 INIT 2E 256 h0000000000000000000000000000000000000000000000000000000000000000 INIT 2F 256 h0000000000000000000000000000000000000000000000000000000000000000 INIT 30 256 h0000000000000000000000000000000000000000000000000000000000000000 INIT_31 256 h0000000000000000000000000000000000000000000000000000000000000000 INIT_32 256 h0000000000000000000000000000000000000000000000000000000000000000 INIT_33 256 h0000000000000000000000000000000000000000000000000000000000000000 INIT 34 256 h0000000000000000000000000000000000000000000000000000000000000000 256 h0000000000000000000000000000000000000000000000000000000000000000 256 h0000000000000000000000000000000000000000000000000000000000000000 256 h0000000000000000000000000000000000000000000000000000000000000000 INIT 38 256 h0000000000000000000000000000000000000000000000000000000000000000 INIT 39 256 h0000000000000000000000000000000000000000000000000000000000000000 INIT 3A 256 h0000000000000000000000000000000000000000000000000000000000000000 INIT 3B 256 h0000000000000000000000000000000000000000000000000000000000000000 INIT 3C 256 h0000000000000000000000000000000000000000000000000000000000000000 INIT 3D 256 h000000000000000000000000000000000000
125. 0000000000000000000000000000 INIT 3E 256 h0000000000000000000000000000000000000000000000000000000000000000 INIT_3F 256 h0000000000000000000000000000000000000000000000000000000000000000 D F D D D D D 1 F D D INIT 35 INIT 36 INIT 37 D D D F D 256 h0000000000000000000000000000000000000000000000000000000000000000 INIT 20 256 h0000000000000000000000000000000000000000000000000000000000000000 The next set of INITP xx are for the parity bits INITP_00 256 h0000000000000000000000000000000000000000000000000000000000000000 INITP_01 256 h0000000000000000000000000000000000000000000000000000000000000000 INITP_02 256 h0000000000000000000000000000000000000000000000000000000000000000 INITP_03 256 h0000000000000000000000000000000000000000000000000000000000000000 INITP_04 256 h0000000000000000000000000000000000000000000000000000000000000000 INITP_05 256 h0000000000000000000000000000000000000000000000000000000000000000 INITP_06 256 h0000000000000000000000000000000000000000000000000000000000000000 INITP_07 256 h000000000000000000000000000
126. 0000000000000000000000000000000000000 130 www xilinx com Virtex 4 User Guide UG070 v1 5 March 21 2006 XILINX Additional RAMB16 Primitive Design Considerations RAMB16_inst CASCADEOUTA CASCADEOUTA 1 bit cascade output CASCADEOUTB CASCADEOUTB 1 bit cascade output DOA DOA 32 bit A port data output DOB DOB 32 bit B port data output DOPA DOPA 4 bit A port parity data output DOPB DOPB 4 bit B port parity data output ADDRA ADDRA 15 bit A port address input ADDRB ADDRB 15 bit B port address input CASCADEINA CASCADEINA 1 bit cascade A input CASCADEINB CASCADEINB 1 bit cascade B input CLKA CLKA 1 bit A port clock input CLKB CLKB 1 bit B port clock input DIA DIA 32 bit A port data input DIB DIB 32 bit B port data input DIPA DIPA 4 bit A port parity data input DIPB DIPB 4 bit B port parity data input ENA ENA 1 bit A port enable input ENB ENB 1 bit B port enable input REGCEA REGCEA 1 bit A port register enable input REGCEB REGCEB 1 bit B port register enable input SSRA SSRA 1 bit A port set reset input SSRB SSRB 1 bit B port set reset input WEA WEA 4 bit A port write enable input WEB WEB 4 bit B port write enable input End of RAMB16 inst instantiation Additional RAMB16 Primitive Design Considerations The RAMB16 primitive is n
127. 0000000000000000000000000000000000000 INITP 02 gt X 0000000000000000000000000000000000000000000000000000000000000000 INITP 03 gt X 0000000000000000000000000000000000000000000000000000000000000000 INITP 04 gt X 0000000000000000000000000000000000000000000000000000000000000000 INITP 05 gt X 0000000000000000000000000000000000000000000000000000000000000000 INITP 06 gt X 0000000000000000000000000000000000000000000000000000000000000000 INITP 07 gt X 0000000000000000000000000000000000000000000000000000000000000000 port map CASCADEOUTA gt CASCADEOUTA 1 bit cascade output CASCADEOUTB gt CASCADEOUTB 1 bit cascade output DOA DOA 32 bit A port Data Output DOB DOB 32 bit B port Data Output DOPA gt DOPA 4 bit A port Parity Output DOPB gt DOPB 4 bit B port Parity Output ADDRA gt ADDRA 15 bit A port Address Input ADDRB gt ADDRB 15 bit B port Address Input CASCADEINA gt CASCADEINA 1 bit cascade A input CASCADEINB gt CASCADEINB 1 bit cascade B input 128 www xilinx com Virtex 4 User Guide UGO070 v1 5 March 21 2006 XILINX Block RAM VHDL and Verilog Templates CLKA gt CLKA Port A Clock CLKB gt CLKB Port B Clock DIA gt DIA 32 bit A port DIB gt DIB 32 bit B port DIPA gt DIPA 4 bit A port DIPB gt DIPB 4 bit B port ENA gt E
128. 0000000000000000000000000000000000000000000 INIT 17 256 hn0000000000000000000000000000000000000000000000000000000000000000 INIT 18 256 h0000000000000000000000000000000000000000000000000000000000000000 INIT 19 256 h0000000000000000000000000000000000000000000000000000000000000000 INIT 1A 256 h0000000000000000000000000000000000000000000000000000000000000000 INIT 1B 256 h0000000000000000000000000000000000000000000000000000000000000000 INIT 1C 256 h0000000000000000000000000000000000000000000000000000000000000000 INIT 1D 256 h0000000000000000000000000000000000000000000000000000000000000000 INIT 1E 256 h0000000000000000000000000000000000000000000000000000000000000000 INIT 1F D INIT_21 256 h0000000000000000000000000000000000000000000000000000000000000000 INIT_22 256 h0000000000000000000000000000000000000000000000000000000000000000 INIT_23 256 h0000000000000000000000000000000000000000000000000000000000000000 INIT 24 256 h0000000000000000000000000000000000000000000000000000000000000000 INIT_25 256 h0000000000000000000000000000000000000000000000000000000000000000 INIT 26 256 hn0000000000000000000000000000000000000000000000000000000000000000 INIT 27 256 h0000000000000000000000000000000000000000000000000000000000000000 INIT_28 256 h0000000000000000000000000000000000000000000000000000000000000000 INIT 29 256 hn0000000000000000000000000000000000000000000000000000000000000000 INIT 2A 256 h0000000000000000000000000000000000000
129. 006 XILINX Specific Guidelines for Virtex 4 I O Supported Standards Table 6 27 lists the SSTL2 DC voltage specifications for Class II Table 6 27 SSTL2 DC Voltage Specifications Class ll Min Typ Max Vcco 23 2 5 27 Veer 7 05x Veco 1 13 1 25 1 38 Ver Vrgr NO 1 09 1 25 1 42 Vg 2 Vggr 0 15 1 28 1 40 3 0 Vg Vggr 0 15 0 3 1 1 1 27 VoH Vrer 0 8 1 93 2 03 2 13 VoL Vrgr 0 84 0 36 0 46 0 55 Tox at Voy mA 16 2 Io at Vor mA 16 2 B Notes 1 N must be greater than or equal to 0 04 and less than or equal to 0 04 2 Viy maximum is Vcco 0 3 3 Vy minimum does not conform to the formula 4 Because SSTL2 I DCI uses a controlled impedance driver Voy and Voy are different Complementary Single Ended CSE Differential SSTL2 Class II 2 5V Figure 6 62 shows a sample circuit illustrating a valid termination technique for CSE differential SSTL2 Class II 2 5V with unidirectional termination External Termination Ver 1 25V V 1 25V IOB Hr T 10B DIFF SSTL2 II Rg 250 500 500 Dq vw C Zo D DIFF SSTL2 II Vor 1 25V Vr 1 25V DIFF SSTL2 II Rg 250 500 500 Dd vw C Zo X ug070_6_60_071904 Figure 6 62 Differential SSTL2 Class II Unidirectional Termination Virtex 4 User Guide www xilinx com 273 UG070 v1 5 March 21 2006 Chapter 6 SelectlO Resources XILINX Figure 6 63 sh
130. 006 Chapter 4 Block RAM XILINX Error Status Description The block RAM ECC is able to detect single and double bit errors from the block RAM However only the single bit error can be corrected The ECC logic does not correct the bit in the actual block RAM storage location If the block RAM location containing the bit error is not overwritten then further reads from that location causes the ECC logic to continue to correct the error Table 4 16 is the truth table for the STATUS bits Table 4 16 STATUS Bit Truth Table STATUS 1 0 Description 00 No bit error 01 Single bit error The block RAM ECC macro detects and automatically corrects a single bit error 10 Double bit error The block RAM ECC macro detects a double bit error 11 Undefined not a valid status error Block RAM ECC Attribute In addition to the built in registers in the decode and correct logic the RAMB32 564 ECC primitive allows the use of optional pipeline registers to produce higher performace with one additional latency Valid values for the DO REG attibute are 0 or 1 Block RAM ECC VHDL and Verilog Templates VHDL and Verilog templates are available in the Libraries Guide Block RAM ECC VHDL Template RAMB32 S64 ECC VHDL instance declaration code Library declaration for Xilinx To incorporate this function into the design the following instance declaration needs to
131. 04 www xilinx com Figure 1 22 BUFR Driving Various Logic Resources 39 Chapter 1 Clock Resources XILINX Regional Clock Nets In addition to global clock trees and nets Virtex 4 devices contain regional clock nets These clock trees are also designed for low skew and low power operation Unused branches are disconnected The clock trees also manage the load fanout when all the logic resources are used Regional clock nets do not propagate throughout the whole Virtex 4 device Instead they are limited to only one clock region One clock region contains two independent regional clock nets To access regional clock nets BUFRs must be instantiated A BUFR can drive regional clocks in up to two adjacent clock regions Figure 1 23 BUFRs in the top or bottom region can only access one adjacent region below or above respectively BUFRs vw ug070 1 23 071404 Figure 1 23 BUFR Driving Multiple Regions 40 www xilinx com Virtex 4 User Guide UG070 v1 5 March 21 2006 XILINX VHDL and Verilog Templates VHDL and Verilog Templates The VHDL and Verilog code follows for all clocking resource primitives BUFGCTRL VHDL and Verilog Templates The following examples illustrate the instantiation of the BUFGCTRL module in VHDL Virtex 4 User Guide and Verilog VHDL Template Example BUFGCTRL declaration component BUFGCTRL generic INIT_OUT PRESELECT IO PRESELECT I1 integer
132. 070 v1 5 March 21 2006 X XILINX Input Serial to Parallel Logic Resources ISERDES ISERDES Verilog Instantiation Module ISERDES Description Verilog instantiation template Device Virtex 4 Family PE Se SS SF Sa a SS SS a R Instantiation Section ISERDES U1 O gt data_output Q1 gt Q 0 Q2 gt Q 1 Q3 gt Q 2 Q4 gt Q 3 Q5 gt open Q6 open SHIFTOUT1 gt open SHIFTOUT2 gt open BITSLIP bitslip CEIL gt ce CE2 gt open CLK gt clk CLKDIV gt clkdiv D gt data_input DLYCE gt dlyce DLYINC gt dlyinc DLYRST gt dlyrst OCLK gt open REV gt open SHIFTIN1 gt open SHIFTIN2 gt open SR gt rst BITSLIP Sub Module All ISERDES blocks in Virtex 4 devices contain a Bitslip sub module This sub module is used for word alignment purposes in source synchronous networking type applications Bitslip reorders the parallel data in the ISERDES block allowing every combination of a repeating serial pattern received by the deserializer to be presented to the FPGA fabric This repeating serial pattern is typically called a training pattern training patterns are supported by many networking and telecom standards Bitslip Operation Virtex 4 User Guide By asserting the Bitslip pin of the ISERDES block the incoming serial data stream is reordered at the parallel side This operation is repeated until
133. 1 2006 www xilinx com 167 Chapter 5 Configurable Logic Blocks CLBs XILINX Look Up Table LUT Virtex 4 function generators are implemented as 4 input look up tables LUTs There are four independent inputs for each of the two function generators in a slice F and G The function generators are capable of implementing any arbitrarily defined four input Boolean function The propagation delay through a LUT is independent of the function implemented Signals from the function generators can exit the slice through the X or Y output enter the XOR dedicated gate see Arithmetic Logic enter the select line of the carry logic multiplexer see Fast Lookahead Carry Logic feed the D input of the storage element or go to the MUXF5 In addition to the basic LUTs the Virtex 4 slices contain multiplexers MUXF5 and MUXFX These multiplexers are used to combine up to eight function generators to provide any function of five six seven or eight inputs in a CLB The MUXFX is either MUXF6 MUXF7 or MUXF8 according to the position of the slice in the CLB The MUXFX can also be used to map any function of six seven or eight inputs and selected wide logic functions Functions with up to nine inputs MUXF5 multiplexer can be implemented in one slice see Figure 5 14 page 179 Wide function multiplexers can effectively combine LUTs within the same CLB or across different CLBs making logic functions with even more input variabl
134. 1 and IFF2 in the ILOGIC Both registers are rising edge triggered The second register IFF2 receives an inverted version of the clock The result is that rising edge data is presented to the fabric via the first register output O1 and falling edge data via the second register output Q2 This structure is similar to the Virtex II and Virtex II Pro implementation Figure 7 2 shows a simplified input DDR register and the signals ports associated with OPPOSITE EDGE mode Figure 7 3 shows the timing diagram of the input DDR using the OPPOSITE EDGE mode ug070 7 02 072904 Figure 7 2 Input DDR in OPPOSITE EDGE Mode 312 www xilinx com Virtex 4 User Guide UGO070 v1 5 March 21 2006 XILINX ILOGIC Resources Q1 DOA D2A D4A D6A D8A D10A D12A Q2 D1A D3A D5A D7A D9A D11A ug070_7_03_072904 Figure 7 3 Input DDR Timing in OPPOSITE EDGE Mode SAME EDGE Mode In the SAME_EDGE mode a third register IFF4 clocked by the rising edge clock is placed on the output of the falling edge register Figure 7 4 shows input DDR registers and the signals associated with the SAME EDGE mode ug070 7 04 071404 Figure 7 4 Input DDR in SAME EDGE Mode By adding the third register data is presented into the FPGA fabric on the same clock edge However the additional register causes the data pair to be separated by one clock cycle Figure 7 5 shows t
135. 1 bit synchronous reset WRADDR WRADDR 9 bit write address input WRCLK WRCLK 1 bit write clock input WREN WREN 1 bit write enable input End of RAMB32 S64 ECC inst instantiation Virtex 4 User Guide www xilinx com 161 UGO070 v1 5 March 21 2006 Chapter 4 Block RAM XILINX 162 www xilinx com Virtex 4 User Guide UG070 v1 5 March 21 2006 XILINX Chapter 5 Configurable Logic Blocks CLBs CLB Overview Virtex 4 User Guide The Configurable Logic Blocks CLBs are the main logic resource for implementing sequential as well as combinatorial circuits Each CLB element is connected to a switch matrix to access to the general routing matrix shown in Figure 5 1 A CLB element contains four interconnected slices These slices are grouped in pairs Each pair is organized as a column SLICEM indicates the pair of slices in the left column and SLICEL designates the pair of slices in the right column Each pair in a column has an independent carry chain however only the slices in SLICEM have a common shift chain The Xilinx tools designate slices with the following definitions An X followed by a number identifies a column of slices The number counts up in sequence from the left to the right A Y followed by a number identifies the position of each slice in a pair as well as the CLB row The Y number counts slices starting from the bottom in sequence 0 1 0 1 the first CLB row
136. 16 2 RAMBI6 S1 S36 32 44 RAMB16 S2 S2 2 2 RAMB16 S2 S4 4 RAMBI6 S2 S9 8 1 RAMB16_S2_S18 16 2 RAMBI6 S2 S36 32 44 RAMB16 S4 S4 4 4 RAMB16 S4 S9 8 1 RAMBI16 S4 S18 1642 RAMBI6 S4 S36 32 44 RAMBI6 S9 S9 8 1 8 1 RAMBI6 S9 S18 162 RAMBI6 S9 S36 32 44 RAMBI6 S18 S18 1642 1642 RAMBI6 S18 536 32444 RAMBI6 S36 S36 3244 32444 Figure 4 11 shows the generic single port block RAM primitive DI DIP ADDR DO and DOP are buses RAMB16_SX DI 4 0 DIP 0 ADDRI 0 DO 0 DOP 0 CLK REGCEN ug070 4 11 071204 Figure 4 11 Single Port Block RAM Primitive 134 www xilinx com Virtex 4 User Guide UGO070 v1 5 March 21 2006 XILINX Block RAM Applications Table 4 7 lists all of the available single port primitives for synthesis and simulation Table 4 7 Single Port Block RAM Primitives Primitive Port Width RAMB16_S1 1 RAMB16_S2 2 RAMB16_S4 4 RAMB16_S9 8 1 RAMB16_S18 16 2 RAMB16_S36 32 4 Instantiation of Additional Block RAM Primitives The RAM_Ax templates with x 1 2 4 9 18 or 36 are single port modules and instantiate the corresponding RAMB16_Sx module RAM_Ax_By templates with x 1 2 4 9 18 or 36 and y 1 2 4 9 18 or 36 are dual port modules and instantiate the corresponding RAMB16_Sx_Sy module Block RAM Applications Creating Larger RAM Structures Block RAM columns have special routing to create
137. 16X2S_ 16x2 bit D1 DO A3 A2 A1 A0 O1 O0 RAM32QOS 32x 2 bit D1 D0 A4 A3 A2 A1 A0 O1 O0 RAM16X4S 16x4 bit D3 D2 DI D0 A3 A2 A1 AO 03 O2 O1 OO www xilinx com Virtex 4 User Guide UGO070 v1 5 March 21 2006 XILINX CLB Primitives and Verilog VHDL Examples VHDL and Verilog Instantiations VHDL and Verilog instantiation templates are available as examples see VHDL and Verilog Templates In VHDL each template has a component declaration section and an architecture section Each part of the template should be inserted within the VHDL design file The port map of the architecture section should include the design signal names The RAM_ S templates with 16 32 64 are single port modules and instantiate the corresponding RAM X1S primitive RAM 16D templates are dual port modules and instantiate the corresponding RAM16X1D primitive Port Signals Each distributed RAM port operates independently of the other while reading the same set of memory cells Clock WCLK The clock is used for the synchronous write The data and the address input pins have setup time referenced to the WCLK pin Enable WE The enable pin affects the write functionality of the port An inactive Write Enable prevents any writing to memory cells An active Write Enable causes the clock edge to write the data input signal to the memory location pointed to by the address inputs Address AO A1 A2 A3 A4
138. 2 3 2 3 the second CLB row etc Figure 5 1 shows the CLB located in the bottom left corner of the die Slices X0YO and XOY1 constitute the SLICEM column pair and slices X1Y0 and X1Y1 constitute the SLICEL column pair For each CLB SLICEM indicates the pair of slices labeled with an even number SLICE 0 or SLICE 2 and SLICEL designates the pair of slices with an odd number SLICE 1 or SLICE 3 SLICEM SLICEL Logic or Distributed RAM or Shift Register Logic Only SHIFTIN COUT A SLICE 1 X1Y0 Interconnect to Neighbors SLICE 2 X0Y1 SLICE 0 XOYO Y SHIFTOUT CIN l ug070_5_01_071504 Figure 5 1 Arrangement of Slices within the CLB www xilinx com 163 UG070 v1 5 March 21 2006 Chapter 5 Configurable Logic Blocks CLBs XILINX 164 Slice Description The elements common to both slice pairs SLICEM and SLICEL are two logic function generators or look up tables two storage elements wide function multiplexers carry logic and arithmetic gates These elements are used by both SLICEM and SLICEL to provide logic arithmetic and ROM functions SLICEM supports two additional functions storing data using distributed RAM and shifting data with 16 bit registers SLICEM shown in Figure 5 2 page 166 represents a superset of elements and connections found in all slices SLICEL is shown in Figure 5 3 page 167 CLB Slice Configurations Table 5 1 summarizes
139. 2 XILINX Shift Registers SRLs Primitives and Verilog VHDL Example Templates for the SHIFT_REGISTER_16_C module are provided in VHDL and Verilog code as an example VHDL Template Module SHIFT_REGISTER_C_16 Description VHDL instantiation template CASCADABLE 16 bit shift register with enable Device Virtex 4 Family SRLC16E Components Declarations component SRLC16E INIT bit vector X 0000 jus port D in std logic CE in std logic CLK in std logic AO in std_logic Al in std_logic A2 in std_logic A3 in std_logic Q out std logic Q15 out std logic Jus end component Architecture Section Attributes for Shift Register initialization 0 by default attribute INIT string attribute INIT of U SRLC16E label is 0000 ShiftRegister Instantiation U_SRLC16E SRLC16E port map D gt insert input signal CE gt insert Clock Enable signal optional CLK gt insert Clock signal AO gt insert Address 0 signal Al gt insert Address 1 signal A2 gt insert Address 2 signal A3 gt insert Address 3 signal Q gt insert output signal Q15 gt insert cascadable output signal Virtex 4 User Guide www xilinx com UGO070 v1 5 March 21 2006 209 Chapter 5 Configurable Logic Blocks CLBs XILINX Verilog Template Module SHIFT_REGISTER_16 Des
140. 2 www xilinx com Virtex 4 User Guide UG070 v1 5 March 21 2006 XILINX Virtex 4 SelectlO Primitives Output Drive Strength Attributes For LVTTL and LVCMOS output buffers OBUF OBUFT and IOBUF the desired drive strength in mA can be specified with the DRIVE attribute The allowed values for the DRIVE attribute are e DRIVE 2 e DRIVE 4 e DRIVE 6 e DRIVE 8 e DRIVE 12 Default e DRIVE 16 e DRIVE 24 The DRIVE attribute uses the following syntax in the UCF file INST lt I O_BUFFER_INSTANTIATION_NAME gt DRIVE lt DRIVE_VALUE gt Lower Capacitance I O Attributes To lower the effective input capacitance some I O resources do not have differential driver circuits LVDS_25 LVDSEXT_25 LVDS_25_DCI LVDSEXT_25_DCI ULVDS_25 and LDT_25 Using these I Os improves the signal integrity of high speed clock inputs Differential inputs and all output standards other than these are still supported by low capacitance I Os Refer to Clock Capable I O in Chapter 1 for further information The allowed values for the CAPACITANCE attribute are e DONT CARE Default e NORMAL e LOW The CAPACITANCE attribute uses the following syntax in the UCF file INST I O BUFFER INSTANTIATION NAME CAPACITANCE CAPACITANCE VALUE PULLUP PULLDOWN KEEPER for IBUF OBUFT and IOBUF When using 3 state output OBUFT or bidirectional IOBUF buffers the output can have a weak pull up resistor a we
141. 21 2006 Chapter 6 SelectlO Resources Table 6 38 VO Compatibility Continued XILINX Veco VREF Termination Type Lower Capacitance IOB O Standard Output Input Input Output Input Output Input HSTL III 0 9 N R N R Yes Yes HSTL IV 0 9 N R N R Yes Yes HSTL_I Note 2 0 75 N R N R Yes Yes HSTL_II 0 75 N R N R Yes Yes DIFF HSTL II N R N R N R Yes Yes LVCMOS15 N R N R N R Yes Yes LVDCI 15 N R Series N R Yes Yes HSLVDCI 15 1 5 Veco 2 Series N R Yes Yes LVDCI_DV2_15 N R Series N R Yes Yes GTLP_DCI 1 Single Single Yes Yes HSTL III DCI m 0 9 N R Single Yes Yes HSTL IV DCI 0 9 Single Single Yes Yes HSTL I DCI 0 75 N R Split Yes Yes HSTL II DCI 0 75 Split Split Yes Yes DIFF HSIL II DCI N R Split Split Yes Yes GTL DCI 1 2 1 2 0 8 Single Single Yes Yes GTLP 1 N R N R Yes Yes N R Note 2 GTL 0 8 N R N R Yes Yes Notes See 3 3V I O Design Guidelines for more detailed information Differential inputs and inputs using Vpgp are powered from VccAux However pin voltage must not exceed Veco due to the presence of clamp diodes to Veco N R no requirement RSDS 25 has the same DC specifications as LVDS_25 All information pertaining to LVDS_25 is applicable to RSDS 25 I O standard is selected using the IOSTANDARD attribute gue o Mr 3 3V I O Design Guidelines To achieve maximum performance in
142. 255 for VARIABLE CENTER mode incremented beyond 255 for VARIABLE POSITIVE mode or decremented beyond 0 and incremented beyond 1023 for DIRECT mode www xilinx com 75 UGO070 v1 5 March 21 2006 76 Chapter 2 Digital Clock Managers DCMs XILINX The DCM is phase shifted beyond the absolute range of the phase shift delay line In this case the phase shift overflow signal will be assert High when the phase shift in time ns exceeds the xFINE SHIFT RANGE 2 in the VARIABLE CENTER mode the FINE SHIFT RANGE in the VARIABLE POSITIVE mode or exceeds 0 to FINE SHIFT RANGE in the DIRECT mode The phase shift overflow signal can toggle once it is asserted The condition determining if the delay line is exceeded is calibrated dynamically Therefore at the boundary of exceeding the delay line it is possible for the phase shift overflow signal to assert and de assert without a change in phase shift Once asserted it will remain asserted for at least 40 CLKIN cycles If the DCM is operating near the FINE SHIFT RANGE limit do not use the phase shift overflow signal as a flag to reverse the phase shift direction When the phase shift overflow is asserted de asserted then asserted again in a short phase shift range it can falsely reverse the phase shift direction Instead use a simple counter to track the phase shift value and reverse the phase shift direction PSINCDEC only when the counter reaches a previously determined maximum minim
143. 257 UGO070 v1 5 March 21 2006 Chapter 6 SelectlO Resources XILINX Table 6 18 lists the HSTL Class IV DC voltage specifications Table 6 18 HSTL Class IV DC Voltage Specifications Min Typ Max Veco 1 40 1 50 1 60 Vper 8 0 90 z VTT E Vcco Vie Vggg 0 1 s 7 Vic Vussc d Vou Veco 04 VoL 0 4 Tox at Voy mA 8 Tor at Vor mA 48 Notes 1 Vor and Vog for lower drive currents are sample tested 2 Per EIA JESD8 6 The value of Vggp is to be selected by the user to provide optimum noise margin in the use conditions specified by the user HSTL Class 1 8V Figure 6 49 shows a sample circuit illustrating a valid termination technique for HSTL Class I 1 8V External Termination Vr 0 9V IOB HSTL_I_18 HSTL_I_18 Rp Zo 500 x X Vper 0 9V IOB IOB Voco 1 8V 2Rygp 2Zg 1002 HSTL I DCI 18 HSTL I DCI 18 DJ Q 2 gt _ XI Ver 0 9V 2Rypy 2Zo 1002 a e L ed ug070 6 47 071904 Figure 6 49 HSTL Class 1 8V Termination 258 www xilinx com Virtex 4 User Guide UGO070 v1 5 March 21 2006 XILINX Specific Guidelines for Virtex 4 I O Supported Standards Table 6 19 lists the HSTL Class I 1 8V DC voltage specifications Table 6 19 HSTL Class I 1 8V DC Voltage Specifications Min Typ Max Veco 1
144. 3 DDR MUX ug070 7 23 080104 Figure 7 23 Output DDR in SAME EDGE Mode Using this scheme data can now be presented to the IOB on the same clock edge Presenting the data to the IOB on the same clock edge avoids setup time violations and allows the user to perform higher DDR frequency with minimal register to register delay as opposed to using the CLB registers The additional register is used to maintain an alternating bits output of DATA 1 and DATA 2 on the DDR multiplexer Figure 7 24 shows the timing diagram of the output DDR using the SAME EDGE mode C CE D1 D2 oQ ___ D1A D2A DIB D2B DiC D2C D10 ug070_7_24_080104 Figure 7 24 Output DDR Timing in SAME_EDGE Mode 346 www xilinx com Virtex 4 User Guide UG070 v1 5 March 21 2006 X XILINX OLOGIC Resources Clock Forwarding Output DDR can forward a copy of the clock to the output This is useful for propagating a clock and DDR data with identical delays and for multiple clock generation where every clock load has a unique clock driver This is accomplished by tying the D1 input of the ODDR primitive Low and the D2 input High Xilinx recommends using this scheme to forward clocks from the FPGA fabric to the output pins Output DDR Primitive ODDR Virtex 4 User Guide Figure 7 25 shows the ODDR primitive block diagram Table 7 12 lists the ODDR port signals Table 7 13 describes
145. 32 bit 64 bit UG070_5_29 071504 All clock enable CE and clock CLK inputs are connected to one global clock enable and one clock signal per submodule If a global static or dynamic length mode is not required the SRLC16E primitive can be cascaded without multiplexers www xilinx com Virtex 4 User Guide UG070 v1 5 March 21 2006 XILINX Shift Registers SRLs Primitives and Verilog VHDL Example Initialization in VHDL or Verilog Code A shift register can be initialized in VHDL or Verilog code for both synthesis and simulation For synthesis the attribute is attached to the 16 bit shift register instantiation and is copied in the EDIF output file to be compiled by Xilinx Alliance Series tools The VHDL code simulation uses a generic parameter to pass the attributes The Verilog code simulation uses a defparam parameter to pass the attributes The Virtex 4_SRL16E shift register instantiation code examples in VHDL and Verilog illustrate these techniques VHDL and Verilog Templates Virtex 4_SRL16E vhd and v files are not a part of the documentation Port Signals Clock CLK Either the rising edge or the falling edge of the clock is used for the synchronous shift operation The data and clock enable input pins have set up times referenced to the chosen edge of CLK Data In D The data input provides new data one bit to be shifted into the shift register Clock Enable CE optional The clock enable pi
146. 41 FIFO Port Descriptions 240 sc0 2senedoegued ey bee teda ot nae sues 142 FIEQ Oe CN fs Pm 143 lI fie EUST 143 Operating Mode ees eher nine ode e eer ub PRU ue RR epe ra e Redde puta 143 Standard Mode ete teda epe dB t eeepc md ed eda BRAS 143 Virtex 4 User Guide www xilinx com 9 UGO070 v1 5 March 21 2006 X XILINX First Word Fall Through FWFT Mode 0 6 cece cece eee eee 143 Status Flags o roepe r e n nese oe einer wee cde a E 143 Enipty Flag xai key eae ee ieee eee ee rra e ad 143 Almost Empty Flag Oude die Sane dees den gak e eU Ee ps C d ta tou Cae a 144 Read Error Flag ees teescmebe peus ba ere ee boa vee esie de st 144 Full Flag i i bRIS DUE S CERO PE D EV E eDES easiness ee ERR Y EE Red 144 Write Error Flags secos cope etas eia eb npe ee a e erp aee 144 Almost Pull Flag 5 autho d rase Er bc reed dece is eu doce eda aa 144 FIFO Attributes ez iA Ee e e e EE De HC HE OA AS 145 FIFO Almost Full Empty Flag Offset Range 0 0 0 0 cece eee ene 145 FIFO VHDL and Verilog Templates 0 0 00 e cece eee ee 146 BIFO VEIDE Tei late scsi cle a ier ta due a det md dandi drei ea an c Ong ale 146 FIFO Verilog Template piersi ccce ese eere ERO Seeded is eee Lae oes 147 FIFO Timing Models and Parameters 0 00 00 e cece eee eee 148 FIFO Timing Characteristics 0 0 6 cc ene eee 150 Case 1 Writing to an Empty FIFO 2 6 cee eens 150 Case 2 Writing to a
147. 5 XC4VLX25 XC4VSX25 XCAVSX35 XCAVFX12 XC4VFX20 XC4VFX40 and XC4VFX60 The behavior of a DCI 3 state outputs is as follows If a LVDCI or LVDCI_DV2 driver is in 3 state the driver is 3 stated If a driver with single or split termination is in 3 state the driver is 3 stated but the termination resistor remains The following section lists actions that must be taken for each DCI I O standard Virtex 4 User Guide www xilinx com 225 UG070 v1 5 March 21 2006 Chapter 6 SelectlO Resources XILINX Conventional DCI Usage Examples e Figure 6 14 provides examples illustrating the use of the HSTL I DCI HSTL_II_DCI HSTL_III_DCI and HSTL_IV_DCI I O standards e Figure 6 15 provides examples illustrating the use of the SSTL2_I_DCI and SSTL2 II DCI I O standards e Figure 6 16 provides examples illustrating the use of the LVDS 25 DCI and LVDSEXT 25 DCI I O standards HSTL I HSTL Il HSTL Ill HSTL IV Vcco 2 Vcco 2 DCI Transmit Conventional Vccol Vcco Receive DC R R gt rU zo gt Virtex 4 Virtex 4 l CN I DCI r Conventional voo joe Transmit d DCI Receive zc gt Virtex 4 a le Veco R DCI Transmit H DCI Receive gt Virtex 4 pel Bidirectional 2R Virtex 4 Virtex 4 DOG DO Reference Resistor VRN VRP R Zg VRN VRP R Zo VRN VRP R Zg VRN VRP R Zg Recommended 500 500 500 Zo Note
148. 57 R READ FIRST mode 113 REFCLK 331 341 regional clock buffers 19 34 regional clocks clock buffers 37 clock nets 40 REV 309 S SelectIO IBUF 229 IBUFDS 230 IBUFG 229 IBUFGDS 230 IOBUF 230 IOBUFDS 231 Virtex 4 User Guide UGO070 v1 5 March 21 2006 XILINX OBUF 229 OBUFDS 231 OBUFT 230 OBUFTDS 231 Simultaneous Switching Output SSO 295 Slew Rate SLEW 232 SSTL 268 CSE Differential SSTL Class II 1 8V 279 CSE Differential SSTL2 Class II 2 5V 273 SSTL18 Class I 1 8V 276 SSTL18 Class II 1 8V 277 SSTL2 Class I 2 5V 269 SSTL2 Class II 2 5V 270 T Temperature Sensing Diode 387 TDN 387 TDP 387 W WRITE_FIRST mode 112 Virtex 4 User Guide www xilinx com 391 UG070 v1 5 March 21 2006 EZ XILINX 392 www xilinx com Virtex 4 User Guide UG070 v1 5 March 21 2006
149. 6 3 and PCIX DC Voltage Specifications Parameter Typ Max Vcco 33 3 5 VREF H B Ver Vig 0 5 x Veco 1 65 Veco 0 5 Vir 03 x Veco 0 99 1 08 Vou 0 9 x Veco z Vor 0 1 Veco 0 36 Iou at Voy mA Note 1 IoL at VoL mA Note 1 Notes 1 Tested according to the relevant specification Table 6 9 details the allowed attributes that can also be applied to the PCI33 3 PCI66 3 and PCIX I O standards Table 6 9 Allowed Attributes of the PCI33 3 PCI66 3 and PCIX I O Standards Attributes IOSTANDARD Primitives IBUF IBUFG OBUF OBUFT PCI33 3 PCI66 3 and PCIX IOBUF CAPACITANCE LOW NORMAL DONT CARE 244 www xilinx com Virtex 4 User Guide UG070 v1 5 March 21 2006 XILINX Specific Guidelines for Virtex 4 I O Supported Standards GTL Gunning Transceiver Logic The Gunning Transceiver Logic GTL standard is a high speed bus standard JESD8 3 invented by Xerox Xilinx has implemented the terminated variation for this standard This standard requires a differential amplifier input buffer and an open drain output buffer The negative terminal of the differential input buffer is referenced to the Vpgr pin A sample circuit illustrating a valid termination technique for GTL with external parallel termination and unconnected Vcco is shown in Figure 6 35 IRE Vata 1 2V0 Vqp2 12V IOB Rp Zg 500 Rp Zo 500
150. 7 1 8 1 9 Vpr 2 0 8 0 9 1 1 Vus 2 Vcco x 0 5 m View 0 1 B Vu Vent Von Voco 04 z VoL 0 4 Top at Voy mA 8 E Ir at Vor mA 8 z Notes 1 Vor and Vog for lower drive currents are sample tested 2 Per EIA JESD8 6 The value of Vggp is to be selected by the user to provide optimum noise margin in the use conditions specified by the user HSTL Class II 1 8V Figure 6 50 shows a sample circuit illustrating a valid termination technique for HSTL Class II 1 8V with unidirectional termination External Termination UPS UAE ROSE ET E ANTES Vr 0 9V Vr 0 9V wB Rp Zg 500 Rp Zg 500 M re e DCI IOB IOB 2Rypp 2Zo 1002 a 2Rypp 2Zg 1002 HSTL_II_DCI_18 HSTL_II_DCI_18 Xt aH Veer 0 9V 2Rypy 2Zo 1000 E E 2Rvan 2Zo 1000 E E ug070_6_48_071904 Figure 6 50 HSTL Class II 1 8V with Unidirectional Termination Virtex 4 User Guide www xilinx com 259 UG070 v1 5 March 21 2006 Chapter 6 SelectlO Resources XILINX Figure 6 51 shows a sample circuit illustrating a valid termination technique for HSTL Class II 1 8V with bidirectional termination External Termination Vr 0 9V Vr 0 9V IOB IOB HSTL Il 18 HSTL Il 18 Rp Zg 502 Rp Zg 500 gt x 2 3 Vper 0 9V L 0 9V DCI IOB IOB Veco 1 8V Veco 1 8V 2Rygp 2Zg 1002 2Rygp 2Zg 1002 HSTL
151. 80 CLKFB CLK270 CLK2X CLK2X180 RST CLKDV CLKFX CLKFX180 PSINCDEC PSEN PSCLK DADDR 6 0 ine DO 15 0 OBUF UGO70 2 09 071204 Figure 2 9 Board Level Clock Using OBUF with External Feedback IBUFG DCM ADV BUFG RST PSINCDEC PSEN PSCLK DADDR 6 0 CLKO CLK90 CLK180 CLK270 CLK2X CLK2X180 CLKDV CLKFX CLKFX180 LOCKED DO 15 0 Voc i ODDR GND UG070_2_10_071204 Figure 2 10 Board Level Clock with Internal Feedback Board Deskew with Internal Deskew www xilinx com Some applications require board deskew with internal deskew to interface with other devices These applications can be implemented using two or more DCM The circuit shown in Figure 2 11 can be used to deskew a system clock between multiple Virtex devices in the same system Virtex 4 User Guide UG070 v1 5 March 21 2006 XILINX Application Examples IBUFG i IBUFG Virtex 4 FPGA DCM_ADV CLKIN CLKO CLK90 CLK180 CLK270 CLK2X CLK2X180 CLKDV CLKFX CLKFX180 RST PSINCDEC PSEN PSCLK DADDR 6 0 DI 15 0 DWE DEN DCLK LOCKED DO 15 0 DCM ADV CLKO CLK90 CLK180 CLK270 CLK2X CLK2X180 CLKDV CLKFX CLKFX180 CLKIN CLKFB RST PSINCDEC PSEN PSCLK DADDR 6 0 DI 15 0 DWE DEN DCLK LOCKED DO 15 0 Vcc BUFG A ODDR D1 D2 gt LGND Q
152. 93 UG070 v1 5 March 21 2006 Chapter 5 Configurable Logic Blocks CLBs XILINX Slice SRL Timing Characteristics Figure 5 25 illustrates the timing characteristics of a 16 bit shift register implemented in a Virtex 4 slice LUT configured as SRL CLK Shift In DI Address Data Out D TREGxB k uss wes x DXX DXX DXCXDXCX DXX DX 0X8 UGO70 5 25 080204 Figure 5 25 Slice SRL Timing Characteristics Clock Event 1 Shift In During a Write Shift In operation the single bit content of the register at the address on the ADDR inputs is changed as data is shifted through the SRL The data written to this register is reflected on the X Y outputs synchronously if the address is unchanged during the clock event If the ADDR inputs are changed during a clock event the value of the data at the addressable output D is invalid e Attime Twss before clock event 1 the write enable signal SR becomes valid high enabling the SRL for the Write operation that follows e At time Tps before clock event 1 the data becomes valid 0 at the DI input of the SRL and is reflected on the X Y output after a delay of length Tgg after clock event 1 Since the address 0 is specified at clock event 1 the data on the DI input is reflected at the D output because it is written to register 0 Clock Event 2 Shift In e At time Tps before clock event 2 the data becomes valid 1 at the DI input of the SRL and is
153. B Rypp Zg 502 HSTL IIl DCI 18 HSTL Ill DCI 18 D1 0Q 200 144 Vper 11V ug070_6_54_071904 Figure 6 56 HSTL Class III 1 8V Termination Table 6 22 lists the HSTL Class III 1 8V DC voltage specifications Table 6 22 HSTL Class Ill 1 8V DC Voltage Specifications Min Typ Max Veco 1 7 1 8 19 Veer 2 z 1 1 VTT Veco Xin Vreer t01 E Vir E E Veug 04 Vou Veco 0 4 z E VoL 2 04 log at Voy mA 8 Io at Vor mA 24 B T Notes 1 Vor and Vog for lower drive currents are sample tested 2 Per EIA JESD8 6 The value of Vggp is to be selected by the user to provide optimum noise margin in the use conditions specified by the user 264 www xilinx com Virtex 4 User Guide UGO070 v1 5 March 21 2006 XILINX Specific Guidelines for Virtex 4 I O Supported Standards HSTL Class IV 1 8V Figure 6 57 shows asample circuit illustrating a valid unidirectional termination technique for HSTL Class IV 1 8V External Termination iOB Vr 1 8V Vy 18V IOB HSTL_IV_18 HSTL_IV_18 Rp Zg 500 Rp Z 500 Dd DCI IOB 7 IOB Rygp Zg 502 HSTL IV DCI 18 Rygp Zg 500 HSTL IV DCI 18 Vper 1 1V ug070_6_55_071904 Figure 6 57 HSTL Class IV 1 8V with Unidirectional Termination Figure 6 58 shows a sample circuit illustrating a valid bidirectional termination technique for
154. BUEGGCTRLE dated nde ee e dte testet epe qa 101 PMGD to PMG D iet dnce ette Rene ee once dr b e e eg de tet rl ene dent 101 Application Examples eed cene PER IOLER SLE RO RO FRUI RUD EIC RR en d 101 DCM and a Single PMCD ieeessesesee eee ee ene re reris 101 DEM and Parallel PMCDS ox ptr ERCP DE EE er e Ue des 101 IBUFG BUFG and PMCD 0 he 102 PMCD for Further Division of Clock Frequencies lssssseseeess 103 VHDL and Verilog Templates and the Clocking Wizard 104 VHDL Templat 00 2 mte ek E RR RR cages bbe RE E E P ER EA Rp ee ke 107 Verilog Template 5 tacts eene pete EE iere 108 Chapter 4 Block RAM Block RAM SUIDiaby cux lt i3 54 0003 EN RICH RATHER ECCE gU CU HL Epl 109 Additional Virtex 4 Block RAM Features 0 0 cc cece ne 109 Block RAM Introduction usssssseeee teen nee e eens 110 Synchronous Dual Port and Single Port RAMS 05 110 Data FlOW momens iadan hc 8s e x GeERRLGROIRGPGAMU EEG REG PER evi HERES 110 ReadOperation abc pete eet UEPEN HOHER APR bese ER HUNE ege 112 Write Operation sie Verdes d stented tia testae nt va bd ee ea a does 112 Operating Modes is eipscetee ees ete e bete eR UM ULP V XR bers Sey Vo ee 112 WRITE FIRST or Transparent Mode Default n on nunnana nannan nrn 112 READ FIRST or Read Before Write Mode eee 113 NO CHANGE Mod cca 335 24 tereti ce T OR C QC de e e d 113 Conflict Avoidance i c co
155. BUFGCTRL_X Y lid integer locations of BUFGCTRL BUFGMUX_VIRTEX4 module declaration module BUFGMUX_VIRTEX4 O IO I1 S output input input input O I0 Il S parameter INIT OUT 1 b0 parameter PRESELECT IO TRUE parameter PRESELECT I1 FALSE endmodule Example BUFGCTRL instantiation BUFGMUX_VIRTEX4 U BUFGMUX VIRTEXA4 O user 0 IO user i0 Il user i1 S user s Declaring synthesis synthesis synthesis synthesis constraints in Verilog attribute INIT OUT of U BUFGMUX VIRTEXA is 0 attribute PRES attribute PRES attribute LOC of U_BUFGMUX_VIRTEX4 is BUFGCTRL_X Y I ECT IO of U BUFGMUX VIRTEXA is FALSI ECT I1 of U_BUFGMUX_VIRTEX4 is FALSI H I E x where is valid integer locations of BUFGCTRL Declaring Constraints in UCF File INST INST INST INST U BUFGMUX VIRTEXA4 INIT OUT 0 U BUFGMUX VIRTEXA4 PRESELECT IO FALSE U BUFGMUX VIRTEXA4 PRESELECT I1 FALSE U BUFGMUX VIRTEXA4 LOC BUFGCTRL_X Y where is valid integer locations of BUFGCTRL Virtex 4 User Guide UGO070 v1 5 March 21 2006 www xilinx com 47 Chapter 1 Clock Resources XILINX BUFIO VHDL and Verilog Templates The following examples illustrate the instantiation of the BUFIO module in VHDL and Verilog VHDL Template Example BU
156. CE CLK Q15 UGO70 5 12 071504 Figure 5 12 Simplified Shift Register and Cascadable Shift Register Shift Register Data Flow Shift Operation The shift operation is a single clock edge operation with an active High clock enable feature When enable is High the input D is loaded into the first bit of the shift register and each bit is shifted to the next highest bit position In a cascadable shift register configuration such as SRLC16 the last bit is shifted out on the Q15 output The bit selected by the 4 bit address appears on the Q output Dynamic Read Operation The Q output is determined by the 4 bit address Each time a new address is applied to the 4 input address pins the new bit position value is available on the Q output after the time delay to access the LUT This operation is asynchronous and independent of the clock and clock enable signals Static Read Operation If the 4 bit address is fixed the Q output always uses the same bit position This mode implements any shift register length from one to 16 bits in one LUT Shift register length is N 1 where N is the input address The Q output changes synchronously with each shift operation The previous bit is shifted to the next position and appears on the Q output www xilinx com Virtex 4 User Guide UGO070 v1 5 March 21 2006 XILINX CLB Overview Shift Register Summary e A shift operation requires one clock edge e Dynamic length read operations
157. CLKDV output is connected to CLKA of PMCD to allow further frequency division e The CLKO feedback clock is connected to CLKB and the RST DEASSERT CLK attribute is set to CLKB These connections and settings ensure synchronous PMCD outputs DCM PMCD CLKIN CLKO CLKFB gt CLKB CLKA1D8 gt 1 128 Reset CLKDV reset 16 RST Reset CLKB1 RST LOCKED CLKDV_DIVIDE 16 RST_DEASSERT_CLK CLKB EN_REL FALSE UGO070 3 11 071404 Figure 3 11 DCM to PMCD for Clock Frequency Division Figure 3 12 illustrates an example of dividing clock frequencies using two PMCDs in series Note the following guidelines Virtex 4 User Guide www xilinx com 103 UGO070 v1 5 March 21 2006 Chapter 3 Phase Matched Clock Dividers PMCDs XILINX A dedicated local connection exists from the CLKA1D8 output of each PMCD to the CLKA and CLKB inputs of the other PMCD within the same tile group of two Thus only CLKA1D8 can directly connect two PMCDs in series PMCD GCLK PMen BUFG IOB CLKA CLKA1D8 CLKA CLKA1D8 f o4 RST RST REL REL RST_DEASSERT_CLK CLKA RST_DEASSERT_CLK CLKA EN_REL FALSE EN_REL FALSE UG070_3_12_071404 Figure 3 12 PMCD to PMCD for Clock Frequency Division VHDL and Verilog Templates and the Clocking Wizard The VHDL Template page 107 and Verilog Template page 108 are also available in the Libraries Guide for all primitives In addition VHD
158. CM component is used except for DO 15 0 e DO 7 0 pins of Virtex 4 DCM ADV DCM PS components map to Status 7 0 of the Virtex II or Virtex II Pro DCMs DO 15 8 of DCM ADV DCM PS components are not available when using Virtex II or Virtex II Pro DCM components 92 www xilinx com Virtex 4 User Guide UG070 v1 5 March 21 2006 XILINX Chapter 3 Phase Matched Clock Dividers PMCDs PMCD Summary The Phase Matched Clock Dividers PMCDs are one of the clock resources available in the Virtex 4 architecture PMCDs provide the following clock management features Virtex 4 User Guide UG070 v1 5 March 21 2006 Phase Matched Divided Clocks The PMCDs create up to four frequency divided and phase matched versions of an input clock CLKA The output clocks are a function of the input clock frequency divided by 1 CLKA1 divided by 2 CLKA1D2 divided by 4 CLKA1D4 and divided by 8 CLKA1D8 CLKA1 CLKA1D2 CLKA1D4 and CLKA1D8 output clocks are rising edge aligned to each other but not to the input CLKA Phase Matched Delay Clocks PMCDs preserve edge alignments phase relations or skews between the input clock CLKA and other PMCD input clocks Three additional inputs CLKB CLKC and CLKD and three corresponding delayed outputs CLKB1 CLKC1 and CLKD1 are available The same delay is inserted to CLKA CLKB CLKC and CLKD thus the delayed CLKA1 CLKB1 CLKC1 and CLKD1 outputs maintain edge alignments
159. CTRL can also be rising edge sensitive and held at High prior to the input switching In some applications the conditions previously described are not desirable Asserting the IGNORE pins will bypass the BUFGCTRL from detecting the conditions for switching between two clock inputs In other words asserting IGNORE causes the mux to switch the inputs at the instant the select pin changes IGNORED causes the output to switch away from the I0 input immediately when the select pin changes while IGNORE1 causes the output to switch away from the I1 input immediately when the select pin changes Selection of an input clock requires a select pair SO and CEO or 1 and CE1 to be asserted High If either S or CE is not asserted High the desired input will not be selected In normal operation both S and CE pairs all four select lines are not expected to be asserted High simultaneously Typically only one pin of a select pair is used as a select line while the other pin is tied High The truth table is shown in Table 1 4 Table 1 4 Truth Table for Clock Resources CEO S0 CE1 S1 e 1 1 0 X I0 1 1 X 0 I0 0 X 1 1 n X 0 1 1 n 1 1 1 1 Old Input Notes 1 Old input refers to the valid input clock before this state is achieved 2 For all other states the output becomes the value of INIT OUT and does not toggle Although both S and CE are used to select a desired output each one of these pins behaves sli
160. D is the serial high speed data input port of the ISERDES This port works in conjunction with all the Virtex 4 I O resources to accommodate the desired I O standards High Speed Clock for Strobe Based Memory Interfaces OCLK The OCLK clock input synchronizes data transfer in strobe based memory interfaces ISERDES Attributes Table 8 2 summarizes all the applicable ISERDES attributes A detailed description of each attribute follows the table For more information on applying these attributes in UCF VHDL or Verilog code refer to the Xilinx ISE Software Manual Table 8 2 ISERDES Attributes i ar Default Attribute Name Description Value Value BITSLIP ENABLE Allows the user to use the Bitslip sub String TRUE or FALSE FALSE module or bypass it See BITSLIP_ENABLE Attribute DATA RATE Enables incoming data stream to be String SDR or DDR DDR processed as SDR or DDR data See DATA RATE Attribute DATA WIDTH Defines the width of the serial to parallel Integer 2 3 4 5 6 7 8 or 10 4 converter The legal value depends on the If DATA_RATE DDR value DATA RATE attribute SDR or DDR See is limited to 4 6 8 or 10 DATA_WIDTH Attribute If DATA_RATE SDR value is limited to 2 3 4 5 6 7 or 8 Virtex 4 User Guide www xilinx com 359 UGO070 v1 5 March 21 2006 Chapter 8 Advanced SelectlO Logic Resources XILINX Table 8 2 SER
161. DCI 4 IOB IOB Veco 2 5V Veco 2 5V DIFF SSTL2 Il DCI 2Rygp 2Zg 1002 2Rygp 2Zg 1002 t Xt 2 HX T 2Rypn 2Zg 1002 2Rypy 2Zg 1002 DIFF SSTL2 Il DCI DIFF SSTL2 Il DCI 2 9 2 03 E Veco 2 5V Mong z 2Y cCoO DIFF_SSTL2_II_DCI DIFF SSTL2 Il DCI 2Rygp 2Zo 1002 2Rygw 2Zg 1000 2Rypp 2Zg 1000 2Rygw 2Zg 1000 ug070 6 63 071904 Figure 6 65 Differential SSTL2 2 5V Class Il with DCI Bidirectional Termination Table 6 28 lists the differential SSTL2 Class II DC voltage specifications Table 6 28 Differential SSTL2 Class Il DC Voltage Specifications Min Typ Max Veco 2 3 2 5 2 7 Input Parameters Ver Veco x 0 5 Vin DO 0 30 Veco 0 30 Vip DC 0 3 Veco 0 60 Vip AC 0 62 Veco 0 60 Vix AC 0 95 1 55 Output Parameters Vox AC 1 0 1 5 Notes 1 Vi DC specifies the allowable DC excursion of each differential input 2 Vip DC specifies the input differential voltage required for switching 3 Vix AC indicates the voltage where the differential input signals must cross 4 Vox AC indicates the voltage where the differential output signals must cross Virtex 4 User Guide UGO070 v1 5 March 21 2006 www xilinx com 275 Chapter 6 SelectlO Resources SSTL18 Class 1 8V XILINX Figure 6 66 shows a sample circuit illustrating a valid termination technique fo
162. DCM ADV X0Y10 DCM ADV X0YI11 DCM ADV X0Y12 DCM ADV X0Y13 DCM ADV X0Y14 DCM ADV X0Y15 DCM ADV X0Y16 DCM ADV X0Y17 DCM ADV X0Y18 DCM ADV X0Y19 Virtex 4 User Guide www xilinx com 53 UGO070 v1 5 March 21 2006 Chapter 2 Digital Clock Managers DCMs XILINX DCM Primitives Three DCM primitives are available DCM_BASE DCM_PS and DCM_ADV See Figure 2 2 DCM_BASE DCM_ADV PSINCDEC PSEN CLK2X180 CLK2X180 PSCLK CLKDV CLKDV DADDR 6 0 DI 15 0 CLKFX DWE CLKFX180 ae LOCKED CLKFX CLKFX180 LOCKED 7 PSDONE cae DO 15 0 DRDYL UGO070 2 02 080204 Figure 2 2 DCM Primitives 54 www xilinx com Virtex 4 User Guide UG070 v1 5 March 21 2006 XILINX DCM Primitives DCM_BASE Primitive The DCM_BASE primitive accesses the basic frequently used DCM features and simplifies the user interface ports The clock deskew frequency synthesis and fixed phase shifting features are available to use with DCM_BASE Table 2 2 lists the available ports in the DCM_BASE primitive Table 2 2 DCM_BASE Primitive Available Ports Port Names Clock Input CLKIN CLKFB Control and Data Input RST Clock Output CLKO CLK90 CLK180 CLK270 CLK2X CLK2X180 CLKDV CLKFX CLKFX180 Status and Data Output LOCKED DCM PS Primitive The DCM PS primitive accesses all DCM features and ports available in DCM BASE plus additional ports used by
163. DDR is 10 1 b0 1 b0 1 b0 364 www xilinx com Virtex 4 User Guide UGO070 v1 5 March 21 2006 XILINX synthesis synthesis synthesis synthesis synthesis synthesis synthesis synthesis synthesis synthesis synthesis BUFIO bufiol Input Serial to Parallel Logic Resources ISERDES INIT O4 of data chan i S 1 b0 INTERFACE TYPE of data chan is NETWORKING IOBDELAY of data chan is NONE IOBDELAY_TYPE of data_chan is DEFAULT IOBDELAY VALUE of data chan is 0 NUM CE of data chan is SERDES MODE of data chan SRVAL O1 of data chan SRVAL O2 of data chan SRVAL O3 of data chan SRVAL O4 of data chan O iobclk I iserdes clkout jor is is is is 1 is SLAVE 1 Db0 1 Db0 1 Db0 1 b0 To get a 1 10 deserialization factor in DDR mode set the clock divide factor to BUFR bufr1 O clkdiv CE 1 Db1 CLR 1 b0 I iobclk Jer 5 synthesis BUFR DIVIDE of bufrl1 is endmodule ISERDES Latencies The input to output latencies for the ISERDES blocks depend on the DATA RATE DATA WIDTH and SERDES MODE attributes The latency reported here is the number of slow clock CLKDIV cycles necessary after a bit has been sampled by the fast clock CLK for the bit to appear on the Q output Table 8 4 summarizes the various ISERDES 5n latency values
164. DEC D C 90 D C ug070 2 21 071504 Figure 2 21 Phase Shift Example Variable Clock Event 1 At TpmcckK psen before clock event 1 PSEN is asserted PSEN must be active for exactly one clock period otherwise a single increment decrement of phase shift is not guaranteed Also the PSINCDEC value at Tpycck psIncDEc before clock event 1 determines whether it is an increment logic High or a decrement logic Low Clock Event 2 At Tpucko PsDONE after clock event 2 PSDONE is asserted to indicate one increment or decrement of the DCM outputs PSDONE is High for exactly one clock period when the phase shift is complete The time required for a complete phase shift will vary As a result PSDONE must be monitored for phase shift status www xilinx com Virtex 4 User Guide UGO070 v1 5 March 21 2006 XILINX DCM Timing Models Status Flags The example in Figure 2 22 shows the behavior of the status flags in the event of a phase shift overflow and CLKIN CLKFB CLKFX failure cN UL CLKFB 1 F CLKFX DO 0 DO 1 257 260 Cycles DO 2 esci _ K esN PSDONE DO 3 ug070_2_22_071504 Figure 2 22 Status Flags Example e Clock Event 1 Prior to the beginning of this timing diagram CLKO not shown is already phase shifted at its maximum value At clock event 1 PSDONE is asserted However since the DCM has reached its maximum phase shift capability no phase adjust
165. DES Attributes Continued sts Default Attribute Name Description Value Value INTERFACE_TYPE Chooses the ISERDES use model See String MEMORY or MEMORY INTERFACE TYTE Attribute NETWORKING IOBDELAY Applies delay to combinatorial or String NONE IBUF NONE registered paths both or neither See IFD or BOTH TOBDELAY Attribute IOBDELAY TYPE Sets the type of delay See Input Delay String DEFAULT FIXED DEFAUIT Element IDELAY or VARIABLE IOBDELAY VALUE Specifies the initial delay See Input Delay Integer 0 to 63 0 Element IDELAY NUM_CE Defines the number of clock enables See Integer 1 or 2 2 NUM_CE Attribute SERDES_MODE Defines whether the ISERDES module is a String MASTER or MASTER master or slave when using width expansion See SERDES_MODE Attribute SLAVE BITSLIP_ENABLE Attribute The BITSLIP_ENABLE attribute enables the Bitslip sub module The possible values are TRUE and FALSE default When set to TRUE the Bitslip sub module responds to the BITSLIP signal When set to FALSE the Bitslip sub module is bypassed See BITSLIP Sub Module DATA_RATE Attribute The DATA_RATE attribute defines whether the incoming data stream is processed as single data rate SDR or double data rate DDR The allowed values for this attribute are SDR and DDR The default value is DDR DATA_WIDTH Attribute The DATA_WIDTH at
166. DLYCE L gt DLYRST gt Serial to Parallel Converter cov C SHIFTIN1 2 SHIFTOUT1 2 gt Cc gt BITSLIP Module Bitslip ug070 8 01 072904 Figure 8 1 SERDES Block Diagram 356 www xilinx com Virtex 4 User Guide UGO070 v1 5 March 21 2006 XILINX Input Serial to Parallel Logic Resources ISERDES ISERDES Primitive Figure 8 2 shows the ISERDES primitive BITSLIP co CE1 d gt CE2 gt d ECT d d CLKDIV DLYCE cS DLYING o E DLYRST at Q2 V V gt Q3 ie V Q4 S SHIFTINI B S SHIFTIN2 d Se d SHIFTOUT1 TFB gt SHIFTOUT2 ug070 8 02 072904 Figure 8 2 SERDES Primitive Table 8 1 lists the available ports in the ISERDES primitive Table 8 1 ISERDES Port List and Definitions Port Name Type Width Description O Output 1 Combinatorial output See Combinatorial Output O O1 Q6 Output 1 each Registered outputs See Registered Outputs O1 to O6 SHIFTOUTI Output 1 Carry out for data width expansion Connect to SHIFTIN1 of slave IOB See ISERDES Width Expansion SHIFTOUT2 Output 1 Carry out for data width expansion Connect to SHIFTIN2 of slave IOB See ISERDES Width Expansion BITSLIP Input 1 Invokes the Bitslip operation See Bitslip Operation BITSLIP CE1 Input 1 each Clock enabl
167. DR RDADDR 9 bit data address input RDCLK RDCLK 1 bit read clock input RDEN RDEN 1 bit read enable input SSR SSR 1 bit synchronous reset WRADDR gt WRADDR 9 bit write address input WRCLK WRCLK 1 bit write clock input WREN WREN 1 bit write enable input Ve End of RAMB32 S64 ECC inst instantiation Block RAM ECC Verilog Template RAMB32 S64 ECC Verilog RAMB32 S64 ECC To incorporate this function into the design Verilog the following instance declaration needs to be placed instance in the body of the design code The instance name declaration RAMB32 S64 ECC inst and or the port declarations ug code within the parenthesis can be changed to properly reference and connect this function to the design All inputs and outputs must be connected Cut code below this line gt RAMB32 S64 ECC Virtex 4 512 x 64 Error Correction Block RAM Virtex 4 User Guide RAMB32 64 ECC DO REG 0 Optional output registers 0 or 1 SIM COLLISION CHECK ALL Collision check enable ALL WARNING ONLY GENERATE X ONLY or NONE RAMB32 S64 ECC inst DO DO 64 bit output data STATUS STATUS 2 bit status output DI DI 64 bit data input RDADDR RDADDR 9 bit data address input RDCLK RDCLK 1 bit read clock input RDEN RDEN 1 bit read enable input SSR SSR
168. DR inputs of the block RAM e At time Tncck EN before clock event 1 enable is asserted High at the EN input of the block RAM enabling the memory for the READ operation that follows e At time Tncko po after clock event 1 the contents of the memory at address 00 become stable at the DO pins of the block RAM Clock Event 2 Write Operation During a write operation the content of the memory at the location specified by the address on the ADDR inputs is replaced by the value on the DI pins and is immediately reflected on the output latches in WRITE FIRST mode EN enable is High e At time Tgcck Appr before clock event 2 address OF becomes valid at the ADDR inputs of the block RAM e At time TrpcKk py before clock event 2 data CCCC becomes valid at the DI inputs of the block RAM Virtex 4 User Guide 137 UGO070 v1 5 March 21 2006 www xilinx com Chapter 4 Block RAM XILINX e At time TrccK wen before clock event 2 write enable becomes valid at the WEN following the block RAM e At time Tgcko poafter clock event 2 data CCCC becomes valid at the DO outputs of the block RAM Clock Event 4 SSR Synchronous Set Reset Operation During an SSR operation initialization parameter value SRVAL is loaded into the output latches of the block RAM The SSR operation does NOT change the contents of the memory and is independent of the ADDR and DI inputs e At time TrccK ssp before clock event 4 the synchronous set res
169. DT 25 and ULVDS 25 It replaces the Virtex II Pro LVDS 25 DT LVDSEXT 25 DT LDT 25 DT and ULVDS 25 DT The on chip input differential termination in Virtex 4 devices provides major advantages over the external resistor by removing the stub at the receiver completely and therefore greatly improving signal integrity e Consumes less power than DCI termination e Does not use VRP VRN pins DCI e Supports LDT and ULVDS not supported by DCI termination The Vcco of the I O bank must be connected to 2 5V 5 to provide 100 of effective differential termination DIFF TERM is only available for inputs and can only be used with a bank voltage of Vcco 2 5V The Differential Termination Attribute DIFF TERM section outlines using this feature LVDS and Extended LVDS Low Voltage Differential Signaling Low Voltage Differential Signaling LVDS is a very popular and powerful high speed interface in many system applications Virtex 4 I Os are designed to comply with the EIA TIA electrical specifications for LVDS to make system and board design easier With the use of an LVDS current mode driver in the IOBs the need for external source termination in point to point applications is eliminated and with the choice of an extended mode Virtex 4 devices provide the most flexible solution for doing an LVDS design in an FPGA Extended LVDS provides a higher drive capability and voltage swing 350 750 mV making it ideal for long distance or cable
170. Data Parity Buses DIP A B and DOP A B 00000000eeeeeeeeeee sees 131 Optional Output Registers erennere nnie nee eens 131 Independent Read and Write Port Width 0 e cece eee 131 RAMB16 Port Mapping Design Rules 0 66 c cece cece eee eee 132 Cascadeable Block RAM 1 6 c cc eee eens 132 Byte Write Enable 24e eerie e a de te d eI ed died ree Pate b ree eons 132 Additional Block RAM Primitives ssessssee eese 133 Instantiation of Additional Block RAM Primitives 000 135 Block RAM Applications ssssssssssssss eee eee ee 135 Creating Larger RAM Structures 0 eee eens 135 Block RAM Timing Model 00 0 suse 135 Block RAM Timing Parameters 066 6 ananena ennnen raara eens 136 Block RAM Timing Characteristics anuna ananuna nennen cee eens 137 Clock Event 1 i 0c peti ted ERU de td eee eG oe eee See rx ar des 137 Clock Event za cues tues Ga ne acu rb sei dye rcp dase cV d ans 137 Clock Event 4 skeccezet emeu ee E V etn omega ne etal wig d teet 138 Clock Event 5 idee emi bee drei Eder e aE EE pera theme atlanta 138 Block RAM Timing Model sssssssssseeeeee e 139 Built in FIFO SUpport cs Lex Ete gu a od KE ede dl e Rt ie o ee RE dou 139 EMPTY Latengy eiae aer I ae puedes Pee Eden etd dete etg 140 Top Level View of FIFO Architecture ee esee 141 FIFO Primitive e iiri ee tiene E EREXIT ED E Ur eect kie ecu qe a ed 1
171. Distributed RAM and Memory Available in SLICEM only sess 169 Read Only Memory ROM es rapsa sssi ta vna n 173 Shift Registers Available in SLICEM only s s 173 Shift Register Data Flow osse EE PEE i bode SOUS TEE REN deridet eed 176 Multiplexers 2 2 6 58 dtp tele peer pde agenda aedes pae er E t clades Gea 177 Designing Large Multiplexers lisse en 179 Fast Lookahead Carry Logie ci iia bee cod ecg ete eet eer pede Cer pene erede 184 Asithimetie Eogle io reet es tace E e bae Pee eee bet bep ded 185 CLB Slice Timing Models 4 4 nnna nunnana naera e Reb Ree ERU C 185 General Slice Timing Model and Parameters 0 0000 e ee eee 186 Timing Parameters i 2c ecco sa wle Er ques p rhe rate wend ede cb ew laden dab te 186 Timing Characteristics rere eee der P ae duce races 188 10 www xilinx com Virtex 4 User Guide UG070 v1 5 March 21 2006 lt XILINX Slice Distributed RAM Timing Model and Parameters Available in SLICEM only 0 0000s 189 Distributed RAM Timing Parameters sees ene 190 Distributed RAM Timing Characteristics ceeseeeeeeeee ee 190 Slice SRL Timing Model and Parameters Available in SLICEM only 192 Slice SRE Timing Parameters ce eine tte tein Cite rk RE E ETE ES 193 Slice SRL Timing Characteristics scele een 194 Slice Carry Chain Timing Model and Parameters 00000 195 Slice Carry Chain Timing
172. Divided clock input Clocks delay element deserialized data Bitslip sub module and CE unit See Divided Clock Input CLKDIV D1 D6 Input 1 each Parallel data inputs See Parallel Data Inputs D1 to D6 OCE Input 1 Output data clock enable See Output Data Clock Enable OCE REV Input 1 Reverse SR pin Not available in the OSERDES block SHIFTIN1 Input 1 Carry input for data width expansion Connect to SHIFTOUT1 of slave OSERDES See OSERDES Width Expansion SHIFTIN2 Input 1 Carry input for data width expansion Connect to SHIFTOUT2 of slave OSERDES See OSERDES Width Expansion SR Input 1 Set Reset This pin only functions as an asynchronous Reset in the OSERDES block T1 to T4 Input 1 each Parallel 3 state inputs See Parallel 3 state Inputs T1 to T4 TCE Input 1 3 state clock enable See 3 state Signal Clock Enable TCE Data Path Output OQ The OQ portis the data output port of the OSERDES module Data at the input port D1 will appear first at OQ This port connects the output of the data parallel to serial converter to the data input of the IOB 3 state Control Output TQ This port is the 3 state control output of the OSERDES module When used this port connects the output of the 3 state parallel to serial converter to the control 3 state input of the IOB High Speed Clock Input CLK This high speed clock input drives the serial side of the parallel to se
173. E INVERT CLK DOB REG FALSE Invert clock on A port output registers TRUE or FALSE RAM EXTENSION A NONE UPPER LOWER or NONE when cascaded RAM EXTENSION B NONE UPPER LOWER or NONE when cascaded READ WIDTH A 0 Nalid values are 1 2 4 9 18 or 36 READ WIDTH B 0 Valid values are 1 2 4 9 18 or 36 SIM COLLISION CHECK ALL Collision check enable ALL WARNING ONLY Set Reset value f Set Reset value WRITE FIRS WRITE FIRS 2 2 SRVAL A 36 h000000000 SRVAL B 36 h000000000 WRITE MODE A WRITE FIRST WRITE MODE B WRITE FIRST WRITE WIDTH A 0 Nalid values are 1 WRITE WIDTH B 0 Nalid values are 1 GENERATE X ONLY or NONE or A port output for B port output T READ FIRST or NO CHANGE T READ FIRST or NO CHANGE 4 9 18 or 36 4 9 18 or 36 Virtex 4 User Guide UGO070 v1 5 March 21 2006 www xilinx com 129 Chapter 4 Block RAM XILINX The following INIT_xx declarations specify the initial contents of the RAM INIT 00 256 h0000000000000000000000000000000000000000000000000000000000000000 INIT 01 256 h0000000000000000000000000000000000000000000000000000000000000000 INIT 02 256 h0000000000000000000000000000000000000000000000000000000000000000 INIT 03 256 h0000000000000000000000000000000000000000000000000000000000000000 INIT 04 256 h000000000000000000000000000000000000000000000000000
174. ELAYCTRL RST RST REFCLK RDY RDY IDELAYCTRL RST Replicated for all IDELAYCTRL sites L REFCLK RDY IDELAYCTRL Auto generated by mapper tool ug070_7_17_080104 Figure 7 17 Instantiate IDELAYCTRL Without LOC Constraints RDY Connected Instantiating IDELAYCTRL with Location LOC Constraints The most efficient way to use the IDELAYCTRL module is to define and lock down the placement of every IDELAYCTRL instance used in a design This is done by instantiating the IDELAYCTRL instances with location LOC constraints The user must define and lock placement of all ISERDES and IDELAY components using the delay element IOBDELAY TYPE attribute set to FIXED or VARIABLE Once completed IDELAYCTRL sites can be chosen and LOC constraints assigned Xilinx strongly recommends using IDELAYCTRL with a LOC constraint Virtex 4 User Guide www xilinx com 335 UGO070 v1 5 March 21 2006 Chapter 7 SelectlO Logic Resources XILINX Location Constraints Each IDELAYCTRL module has XY location coordinates X row Y column To constrain placement IDELAYCTRL instances can have LOC properties attached to them The naming convention for IDELAYCTRL placement coordinates is different from the convention used in naming CLB locations This allows LOC properties to transfer easily from array to array There are two methods of attaching LOC properties to IDELAYCTRL instances 1 Insert LOC constraints i
175. ESS_LSB SELECT_PROCESS_MSB process SELECT_ begin case SELECT_I 2 downto 0 is when 000 gt DATA MSB lt DATA I when 001 gt DATA MSB lt DATA I when 010 gt DATA MSB lt DATA I when 011 gt DATA MSB lt DATA I when 100 gt DATA MSB lt DATA I when 101 gt DATA MSB lt DATA I when 110 gt DATA MSB lt DATA I when 111 gt DATA MSB lt DATA I when others DATA MSB X end case end process SELECT PROCESS MSB MUXF7 instantiation U MUXF7 MUXF7 port map IO gt DATA LSB I1 gt DATA MSB S gt SELECT I 3 O gt DATA O Jur end MUX 16 1 SUBM arch T E I E T E E JT I DATA I 8 9 10 11 12 13 14 15 Virtex 4 User Guide UG070 v1 5 March 21 2006 www xilinx com 213 Chapter 5 Configurable Logic Blocks CLBs XILINX Module Verilog Template MUX 16 1 SUBM Description Multiplexer 16 1 Device Virtex 4 Family J eieteiedi seen Sea ee ae Sas Sea Sena es SSS eae aan edlen ded Eu module MUX 16 1 SUBM DATA I input 15 0 DATA I input 3 0 SELECT I output DATA O wire 2 0 SELECT reg DATA LSB reg DATA MSB assign SEL ECT 2 0 always SELECT case SELECT 3 b000 3 b001 3 b010 3 b011 3 b101 3 b110 3 b111 default SELECT I lU
176. ET BUFGCTRL Clock D gt Tiopi NET El Ite Illu ee ee a ug070 4 13 080204 Figure 4 13 Block RAM Timing Model Built in FIFO Support Virtex 4 User Guide A large percentage of FPGA designs use block RAMs to implement FIFOs In the Virtex 4 architecture dedicated logic in the block RAM enables users to easily implement synchronous or asynchronous FIFOs This eliminates the need for additional CLB logic for counter comparator or status flag generation and uses just one block RAM resource per FIFO Both standard and first word fall through FWFT modes are supported The supported configurations are 4K x 4 2K x 9 1K x 18 and 512 x 36 The block RAM can be configured as first in first out FIFO memory with common or independent read and write clocks Port A of the block RAM is used as a FIFO read port and Port B is a FIFO write port Data is read from the FIFO on the rising edge of read clock and written to the FIFO on the rising edge of write clock Independent read and write port width selection is not supported in FIFO mode without the aid of external CLB logic The FIFO offers a very simple user interface The design relies on free running write and read clocks of identical or different frequencies up to the specified maximum frequency limit The design avoids any ambiguity glitch or metastable problems even when the two frequencies are completely unrelated The write operation is synchronous writing the
177. EWE 1 0 MUXF5 gt F5 S XMUX ADDRESS F4 DO FS BX C gt e DATA_IN or Address CLK C gt SR C gt Write Enable UGO070 5 22 071504 Figure 5 22 Simplified Virtex 4 SLICEM Distributed RAM Virtex 4 User Guide www xilinx com UGO070 v1 5 March 21 2006 189 Chapter 5 Configurable Logic Blocks CLBs XILINX Distributed RAM Timing Parameters Table 5 6 shows the timing parameters for the distributed RAM in SLICEM for a majority of the paths in Figure 5 22 Table 5 6 Distributed RAM Timing Parameters Parameter Function Description Sequential Delays for Slice LUT Configured as RAM Distributed RAM TsHCKO CLK to X Time after the Clock CLK of a Write operation that the data written to the distributed RAM is stable on the X output of the slice Tsuckors CLK to F5 output WE Time after the Clock CLK of a Write operation that the data written to active the distributed RAM is stable on the F5 output of the slice Setup and Hold for Slice LUT Configured as RAM Distributed RAM Tyg Setup time before clock edge The following descriptions are for setup times only T H Hold time after clock edge Tps Tpug BX BYconfiguredasdata Time before the clock that data must be stable at the BX BY input of the input DI slice Tas TAH F G Address inputs Time before the clock that address signal
178. Error Status 160 FIFO 117 operating modes NO_CHANGE 113 READ FIRST 113 WRITE FIRST 112 ports 119 synchronous clocking 114 BLVDS 285 BU BU BU BU BU BU BU C FG 25 FGCE 26 FGCTRL 22 FGMUX 27 FGMUX VIRTEX4 29 with CE 31 FIO 35 FR 37 CLB 163 array size by device 165 distributed RAM 169 maximum distributed RAM 165 number of flip flops 165 number of LUTs by device 165 number of slices by device 165 register latch configuration 169 slice description 164 SLICEL 163 SLICEM 163 Virtex 4 User Guide UGO070 v1 5 March 21 2006 CLK2X 59 CLKDV 60 CLKFB 56 CLKFX 60 clock capable I O 35 clock forwarding 347 clock regions 34 clock tree 32 clocking wizard 83 clocks global clock buffers 20 21 I O clock buffer 35 regional clock buffers 34 37 regions 33 resources 23 combinatorial input path 311 configuration DCM 69 CSE differential 248 D HSTL Class II 252 HSTL Class II 1 8V 261 LVPECL 285 SSTL Class II 1 8V 279 SSTL2 Class II 2 5V 273 DCI 218 defined 218 DCLK 57 DCM 51 allocation in device 53 attributes 62 65 clock deskew 51 67 clocking wizard 83 configuration 69 DCM to PMCD 100 DCM ADV 55 DCM BASE 55 DCM PS 55 design guidelines 67 deskew 71 dynamic reconfiguration 52 76 frequency synthesis 51 71 location 52 output ports 59 phase shifting 51 72 89 ports 56 timing models 88 DDR IDDR 311 ODDR 342 delay element S
179. FCLK RDY IDELAYCTRL RST RST e REFCLK RDY po H i IDELAYCTRL RDY signal ignored RST Replicated for all IDELAYCTRL sites REFCLK RDY IDELAYCTRL RST Auto generated by mapper tool ug070 7 16 080104 Figure 7 16 Instantiate IDELAYCTRL Without LOC Constraints RDY Unconnected 2 When RDY port is connected an AND gate of width equal to the number of clock regions is instantiated and the RDY output ports from the instantiated and replicated IDELAYCTRL instances are connected to the inputs of the AND gate The tools assign the signal name connected to the RDY port of the instantiated IDELAYCTRL instance to the output of the AND gate The VHDL and Verilog use models for instantiating an IDELAYCTRL primitive without LOC constraints with the RDY port connected are provided 334 www xilinx com Virtex 4 User Guide UG070 v1 5 March 21 2006 XILINX ILOGIC Resources VHDL Use Model Only one instance of IDELAYCTRL primitive is instantiated The RDY port is connected dlyctrl IDELAYCTRL port map RDY rdy REFCLK refclk RST rst di Verilog Use Model Only one instance of IDELAYCTRL primitive is instantiated The RDY port is connected IDELAYCTRL dlyctrl RDY rdy REFCLK refclk RST rst ie The resulting circuitry after instantiating the IDELAYCTRL components is illustrated in Figure 7 17 Instantiated by user REFCLK REFCLK RDY ID
180. FIO declaration component BUFIO port O out std_ulogic I in std_ulogic es end component Example BUFIO instantiation U_BUFIO BUFIO Port map O gt user_o I0 gt user i Jor Declaring constraints in VHDL file attribute LOC string attribute LOC of U BUFIO label is BUFIO_X Y where is valid integer locations of BUFIO Verilog Template Example BUFIO module declaration module BUFIO O I output O input I endmodule Example BUFIO instantiation BUFIO U BUFIO O user 0 I user i Declaring constraints in Verilog synthesis attribute LOC of U BUFIO is BUFIO_X Y where is valid integer locations of BUFIO 48 www xilinx com Virtex 4 User Guide UGO070 v1 5 March 21 2006 XILINX VHDL and Verilog Templates Declaring Constraints in UCF File INST U BUFIO LOC BUFIO_X Y where is valid integer locations of BUFIO BUFR VHDL and Verilog Templates The following examples illustrate the instantiation of the BUFR module in VHDL and Verilog VHDL Template Example BUFR declaration component BUFR generic BUFR_DIVIDE string BYPASS port O out std ulogic CE in std ulogic CLR in std ulogic I in std ulogic end component Example BUFR instantiation U BUFR BUFR Port map O user o CE user ce CLR user clr I gt user i ee Declaring constraints in VHDL file
181. GCTRL design example Figure 1 14 shows the asynchronous mux timing diagram V IGNORE1 D GE Vpp S1 Asynchronous MUX Design Example 11 11 o o 10 10 5o 50 v CEO DD IGNOREO Vpp lt _ lt ug070 1 13 082704 Figure 1 13 Asynchronous Mux with BUFGCTRL Design Example Tgocko o 4 TBccko o mia r o if LI Li a xL Il hs at 10 Begin l1 UGO70 1 14 033005 Figure 1 14 Asynchronous Mux Timing Diagram In Figure 1 14 e The current clock is from I0 e Sis activated High e The Clock output immediately switches to I1 e When Ignore signals are asserted High glitch protection is disabled 30 www xilinx com Virtex 4 User Guide UG070 v1 5 March 21 2006 XILINX BUFGMUX_VIRTEX4 with a Clock Enable Global Clocking Resources A BUFGMUX_VIRTEX4 with a clock enable BUFGCTRL configuration allows the user to choose between the incoming clock inputs If needed the clock enable is used to disable the output Figure 1 15 illustrates the BUFGCTRL usage design example and Figure 1 16 shows the timing diagram CE GND IGNORE1 CE1 S1 BUFGMUX_VIRTEX4 CE Design Example SO CEO GND IGNOREO ug070 1 15 071304 Figure 1 15 BUFGMUX VIRTEXA with a CE and BUFGCTRL 1 2 P 10 DG DOCU gt dl poc LT PNE ELlclc c Ell l ee E pl S TBCCCK CE CE 4 TBcckO O
182. GO070 v1 5 March 21 2006 338 Chapter 7 SelectlO Logic Resources XILINX INST dlyctrl 2 LOC IDELAYCTRL_X0Y1 INST dlyctrl n LOC IDELAYCTRL XnYn The circuitry that results from instantiating the IDELAYCTRL components is shown in Figure 7 18 REFCLK REFCLK RDY rdy_1 IDELAYCTRL_1 rst_1 RST REFCLK rdy_2 IDELAYCTRL_2 i REFCLK RDY rdy_n IDELAYCTRL_n RST ug070_7_18_080104 Figure 7 18 Instantiate IDELAYCTRL with LOC Constraint Instantiating IDELAYCTRL With and Without LOC Constraints There are cases where the user instantiates an IDELAYCTRL module with a LOC constraint but also instantiates an IDELAYCTRL module without a LOC constraint In the case where an IP Core is instantiated with a non location constrained IDELAYCTRL module and also wants to instantiate an IDELAYCTRL module without a LOC constraint for another part of the design the implementation tools will perform the following Instantiate the LOC IDELAYCTRL instances as described in the section Instantiating IDELAYCTRL with Location LOC Constraints Replicate the non location constrained IDELAYCTRL instance to populate with an IDELAYCTRL instance in every clock region without a location constrained IDELAYCTRL instance in place The signals connected to the RST and REFCLK input ports of the non location constrained IDELAYCTRL instance are connected to the corresponding input ports of the replicated IDELAYCTRL instances
183. Guide UG070 v1 5 March 21 2006 2 XILINX Built in Block RAM Error Correction Code Cascading FIFOs to Increase Width As shown in Figure 4 23 the Virtex 4 FIFO can be cascaded to add width to the design CLB logic is used to implement the AND OR gates The maximum frequency can be limited by the logic gate feedback path 512 x 72 FIFO DOUT lt 35 0 gt DIN lt 35 0 gt DIN lt 35 0 gt DOUT lt 35 0 gt WREN RDEN RDEN WRCLK WRCLK Ear RDCLK RDCLK FIFO 44 AFULL l DOUT lt 71 36 gt DIN lt 71 36 gt DIN lt 35 0 gt DOUT lt 35 0 gt WREN WREN RDEN WRCLK EMPTY RDCLK piro yo AFULL zi ug070 4 24 071204 Figure 4 23 Cascading FIFO by Width Built in Block RAM Error Correction Code Virtex 4 User Guide Two vertically adjacent block RAMs can be configured as a single 512 x 64 RAM with built in Hamming error correction using the extra eight bits in the 72 bit wide RAM The operation is transparent to the user The eight protection bits are generated during each write operation and are used during each read operation to correct any single error or to detect but not correct any double error Two status outputs indicate the three possible read results No error single error corrected double error detected The read operation does not correct the error in the memory array it only presents corrected data on DO This error
184. HSTL Class IV 1 8V Virtex 4 User Guide www xilinx com 265 UGO070 v1 5 March 21 2006 Chapter 6 SelectlO Resources XILINX External Termination xls SS SS Vir 1 8V VaedV uem OS IOB 10B HSTL_IV_18 HSTL_IV_18 Rp Zg 502 Rp Zg 500 C zo x l Veer 1 1V DCI IOB 7 IOB Veco 1 8V Veco 1 8V Ry ap Zo 502 Rypp Zo 509 HSTL IV DCI 18 HSTL IV DCI 18 tO gt Vgge 1 1V ug070 6 56 071904 Figure 6 58 HSTL Class IV 1 8V with Bidirectional Termination 266 www xilinx com Virtex 4 User Guide UG070 v1 5 March 21 2006 XILINX Specific Guidelines for Virtex 4 I O Supported Standards Table 6 23 lists the HSTL Class IV 1 8V DC voltage specifications Table 6 23 HSTL Class IV 1 8V DC Voltage Specifications Min Typ Max Veco 17 1 8 19 Veer 2 1 1 2 Vas Vcco E Va Var 0 1 g V z B Vee Vou Veco 0 4 Vai E 0 4 Top at Voy mA 8 E Ir at Vor mA 48 E Notes 1 Vor and Voy for lower drive currents are sample tested 2 Per EIA JESD8 6 The value of Vggp is to be selected by the user to provide optimum noise margin in the use conditions specified by the user Table 6 24 details the allowed attributes that can be applied to the HSTL I O standards Table 6 24 Allowed Attributes of the HSTL I O Standards Primitives Attributes
185. High or Low Figure 1 8 illustrates the relationship of BUFGMUX and BUFGCTRL A LOC constraint is available for BUFGMUX and BUFGCTRL GND IGNORE1 S CE1 1 Vpp BUFGMUX SO CEO IGNOREO Vpp GND ug070 1 08 071304 Figure 1 8 BUFGMUX as BUFGCTRL Since the BUFGMUX uses the CE pins as select pins when using the select the setup time requirement must be met Violating this setup time may result in a glitch Switching conditions for BUFGMUX are the same as the CE pins on BUFGCTRL Figure 1 9 illustrates the timing diagram for BUFGMUX Virtex 4 User Guide www xilinx com 27 UGO070 v1 5 March 21 2006 Chapter 1 Clock Resources XILINX T BCCCK_CE SoD a ee a BCCKO_O begin H p BCCKO O Figure 1 9 BUFGMUX Timing Diagram In Figure 1 9 e The current clock is IO e Sis activated High e If1I0 is currently High the multiplexer waits for I0 to deassert Low e Once I0 is Low the multiplexer output stays Low until I1 transitions High to Low e When Il transitions from High to Low the output switches to I1 e If Setup Hold are met no glitches or short pulses can appear on the output BUFGMUX 1 is rising edge sensitive and held at High prior to input switch Figure 1 10 illustrates the timing diagram for BUFGMUX 1 A LOC constraint is available for BUFGMUX and BUFGMUX 1 TBCCCK CE S Ce oe Oe ee oe os S eee 4 H o Sal M TBCCKO_
186. IDELAY U1 O data_output I data input C clkdiv CE INC RST dlyrst Set IOBDELAY TYPE attribute to FIXED for Fixed Delay Mode synthesis attribute IOBDELAY TYPE of Ul is FIXED Set IOBDELAY VALUE attribute to 31 for center of delay element synthesis attribute IOBDELAY VALUE of U1 is 31 synthesis translate off defparam U1 lIOBDELAY TYPE FIXED defparam U1 lIOBDELAY VALUE 31 synthesis translate on Variable Delay Mode The following code shows how to instantiate the IDELAY module in variable delay mode IDELAYCTRL must also be instantiated when operating in this mode see IDELAYCTRL Overview page 330 VHDL Code for Variable Delay Mode The IDELAYCTRL primitive must be instantiated in conjunction with the IDELAY primitive when used in Variable Delay Mode Module IDELAY Description VHDL instantiation template Variable Delay Mode Device Virtex 4 Family Components Declarations Component Declaration for IDELAY should be placed after architecture statement but before begin keyword component IDELAY synthesis translate off generic IOBDELAY TYPE string DEFAULT DEFAULT FIXED VARIABLE IOBDELAY VALUE integer 0 0 to 63 jut synthesis translate on port O out STD LOGIC I in STD LOGIC C in STD LOGIC CE in STD LOGIC 328 www xilinx com Virtex 4 User Gu
187. IFF_HSTL_II_DCI DIFF HSTL Il DCI 2Rypp 2Zo 1002 2Rypy 2Zg 1002 im ug070 6 43 071904 Table 6 16 lists the differential HSTL Class II DC voltage specifications Table 6 16 Differential HSTL Class Il DC Voltage Specifications Min Typ Max Veco 1 40 1 50 1 60 Ver Veco x 0 5 Vin DC 0 30 Veco 0 30 Vorrr DC 0 20 Veco 0 60 Vem DC 0 68 0 90 Voprrr AC 0 40 Veco 0 60 Vx Crossover 0 68 z 0 90 Notes 1 Common mode voltage Vey Vp Vp Vn 2 2 Crossover point Vy where Vp Vy 0 AC coupled 254 www Xilinx com Virtex 4 User Guide UGO070 v1 5 March 21 2006 XILINX Specific Guidelines for Virtex 4 I O Supported Standards HSTL Class Ill Figure 6 46 shows a sample circuit illustrating a valid termination technique for HSTL Class III External Termination IOB IOB HSTL_III l HSTL_III Rp Zo 500 rj X Veer 0 9V EENES he I E ei L DCI DES IOB IOB Rygp Zo 502 HSTL_III_DCI HSTL_III_DCI ug070_6_44_071904 Figure 6 46 HSTL Class III Termination Table 6 17 lists the HSTL Class III DC voltage specifications Table 6 17 HSTL Class Ill DC Voltage Specifications Min Typ Max Vaco 1 40 1 50 1 60 Vea x 0 90 VTT S Vcco V Viep 0 1 V E E Vggr 9 1 Vou Veco 04 ie E VoL 2 0 4 Tox at Voy mA 8
188. ILINX ILOGIC Resources Components Declarations Component Declaration for IDELAY should be placed after architecture statement but before begin keyword component IDELAY synthesis translate_off generic IOBDELAY_TYPE string DEFAULT DEFAULT FIX VARIABLE IOBDELAY VALUE integer 0 0 to 63 synthesis translate on port O out STD LOGIC I in STD LOGIC C in STD LOGIC CE in STD LOGIC INC in STD LOGIC RST in STD LOGIC js end component Component Attribute specification for IDELAY should be placed after architecture declaration but before the begin keyword Architecture Section attribute IOBDELAY TYPE string attribute IOBDELAY VALUE integer Component Instantiation for IDELAY should be placed in architecture after the begin keyword Instantiation Section Ul IDELAY synthesis translate off generic map IOBDELAY TYPE DEFAULT Set to DEFAULT for Zero Hold Time Mode IOBDELAY VALUE gt 0 0 to 63 synthesis translate on port map O gt data output I data input C gt open CE open INC open RST open Virtex 4 User Guide UGO070 v1 5 March 21 2006 www xilinx com 325 Chapter 7 SelectlO Logic Resources XILINX Verilog for Zero Hold Time Delay Mode Module IDELAY Description Verilog instantiation template
189. IVIDE D value to produce a new CLKFX frequency e Allow dynamic adjustment of PHASE SHIFT value to produce a new phase shift This feature can be used with the fixed variable or direct phase shift modes to set a specific phase shift value The following steps are required when using DRPs to load new M and D values e Subtract the desired M and D values by one For example if the desired M D 9 4 then load M D 8 3 e Hold DCM in reset assert RST signal and release it after the new M and D values are written The CLKFX outputs can be used after LOCKED is asserted High again www xilinx com Virtex 4 User Guide UG070 v1 5 March 21 2006 XILINX Connecting DCMs to Other Clock Resources in Virtex 4 Devices Connecting DCMs to Other Clock Resources in Virtex 4 Devices Most DCM functions require connection to dedicated clock resources including dedicated clock I O IBUFG clock buffers BUFGCTRLs and PMCD These clock resources are located in the center column of the Virtex 4 devices This section provides guidelines on connecting the DCM to dedicated clock resources IBUFG to DCM Virtex 4 devices contain either 16 or 32 clock inputs These clock inputs are accessible by instantiating the IBUFG component Each top and bottom half of a Virtex 4 device contains eight or 16 IBUFGs Any of the IBUFG in top or bottom half of the Virtex 4 device can drive the clock input pins CLKIN CLKFB PSCLK or DCLK of a DCM located in the
190. L and Verilog files are generated by the Clocking Wizard in the ISE software The Clocking Wizard sets appropriate DCM and single parallel PMCD configurations 104 The Clocking Wizard is accessed using the Xilinx ISE software in the Project Navigator Refer to the Xilinx Software Manuals for more information on Xilinx ISE software 1 5 6 From the Project Navigator menu select Project gt New Source The New Source window appears Enter a file name and select IP CoreGen and Architecture Wizard Click Next The Select Core Type window appears Select Clocking gt Single DCM_ADV click next The New Source Information window appears Click Finish The Xilinx Clocking Wizard starts Figure 3 13 and Figure 3 14 show the settings in the Clocking Wizard for using the DCM with the PMCD To access further information on available settings choose the More Info button in each window www xilinx com Virtex 4 User Guide UG070 v1 5 March 21 2006 XILINX VHDL and Verilog Templates and the Clocking Wizard ug070 3 13 071204 Figure 3 13 Xilinx Clocking Wizard General Setup PMCD Virtex 4 User Guide www xilinx com 105 UG070 v1 5 March 21 2006 Chapter 3 Phase Matched Clock Dividers PMCDs Z XILINX ug070 3 14 071204 Figure 3 14 Xilinx Clocking Wizard Phase Matched Clock Divider PMCD 106 www xilinx com Virtex 4 User Guide UGO070 v1 5 March 21 2006 XILINX VHDL and Verilog
191. LICE S1 outputs from slices S1 and S3 MUXF7 combines the two MUXF6 SLICE S2 outputs from slices SO and S1 MUXF6 combines the two MUXF5 SLICE SO outputs from slices SO and S2 CLB a LC Y ug070 5 13 071504 Figure 5 13 MUXF5 and MUXFX Multiplexers 178 www xilinx com Virtex 4 User Guide UGO070 v1 5 March 21 2006 XILINX CLB Overview Designing Large Multiplexers 4 1 Multiplexer Each Virtex 4 slice has a MUXF5 to combine the outputs of the two LUTs and an extra MUXFX Figure 5 14 illustrates a valid combinatorial function with up to nine inputs or a 4 1 MUX in one slice 4 OUT_F5 4 S_F5 Any Slice UG070_5_14_071504 Figure 5 14 LUTs and MUXF5 in a Slice Virtex 4 User Guide www xilinx com 179 UG070 v1 5 March 21 2006 Chapter 5 Configurable Logic Blocks CLBs XILINX 8 1 Multiplexer Slice S0 and 1 have a MUXF6 MUXF6 is designed to combine the outputs of two MUXF5 resources Figure 5 15 illustrates a combinatorial function up to 18 inputs or an 8 1 MUX in the slices SO and S2 or in the slices S1 and S3 Slice S2 or S3 OUT F6 Slice SO or S1 UG070 5 15 071504 Figure 5 15 LUTs and MUXF5 and MUXF6 in Two Slices 16 1 Multiplexer Slice S2 has a MUXF7 MUXF7 is designed to combine the outputs of two MUXF6 Figure 5 16 illustrates a combinatorial function up to 35 inputs or
192. LL Output Almost all entries in FIFO memory have been filled Synchronous to WRCLK The offset for this flag is user configurable EMPTY Output FIFO is empty No additional read can be performed Synchronous to RDCLK ALMOSTEMPTY Output Almost all valid entries in FIFO have been read Synchronous with RDCLK The offset for this flag is user configurable RDCOUNT Output The FIFO data read pointer It is synchronous with RDCLK The value will wrap around if the maximum read pointer value has been reached WRCOUNT Output The FIFO data write pointer It is synchronous with WRCLK The value will wrap around if the maximum write pointer value has been reached WRERR Output When the FIFO is full any additional write operation generates an error flag Synchronous with WRCLK RDERR Output When the FIFO is empty any additional read operation generates an error flag Synchronous with RDCLK 142 www xilinx com Virtex 4 User Guide UGO070 v1 5 March 21 2006 XILINX FIFO Operations FIFO Operations Reset Reset is an asynchronous signal to reset all read and write address counters and must be asserted to initialize flags after power up Reset does not clear the memory nor does it clear the output register When reset is asserted High EMPTY and ALMOST_EMPTY will be set to 1 FULL and ALMOST_FULL will be reset to 0 The reset signal must be High for at least three read clock and write c
193. LOGIC have a common clock and synchronous or asynchronous set and reset SR and REV signals Table 7 1 and Table 7 2 describe the operation of SR in conjunction with REV For each storage element in the OLOGIC block the SRVAL attributes are independent Synchronous or asynchronous set reset SRTYPE can not be set individually for each storage element in an OLOGIC block Most of the control signals have optional inverter Any inverter placed on a control input is automatically absorbed www xilinx com Virtex 4 User Guide UG070 v1 5 March 21 2006 XILINX OLOGIC Resources Figure 7 20 illustrates the various logic resources in the OLOGIC block Ti zl gt TIINV L rFF1 TFFDDRI r 1 rrF2 EE ES TFFDDRA T2INV TFF1 TFFDDR TFF2 TFFDDRB TCE d gt TCEINV CLK1INV CLK gt ELK2INV D1 gt oFF1OFFDDR OFF2 D2 OFFDDRA E OFFTOFFDDR OFF2 OFFDDRA gt OCEINV SR d gt SRINV REV gt REVINV Figure 7 20 OLOGIC Block Diagram ug070_7_20_080104 This section of the documentation discusses the various features available using the OLOGIC resources All connections between the OLOGIC resources are managed in Xilinx software Virtex 4 User Guide www xilinx com 343 UG070 v1 5 March 21 2006 Chapter 7
194. LVCMOS33 and LVCMOS25 I O standards Table 6 3 Allowed Attributes for the LVCMOS33 and LVCMOS25 I O Standards Primitives Attributes IBUF IBUFG OBUF OBUFT IOBUF IOSTANDARD LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS25 LVCMOS25 IVCMOS25 CAPACITANCE LOW NORMAL DONT CARE DRIVE UNUSED 2 4 6 8 12 16 24 2 4 6 8 12 16 24 SLEW UNUSED FAST SLOW FAST SLOW www xilinx com 239 UGO070 v1 5 March 21 2006 Chapter 6 SelectlO Resources 240 XILINX Table 6 4 details the allowed attributes that can be applied to the LVCMOS18 and LVCMOS15 I O standards Table 6 4 Allowed Attributes for the LVCMOS18 and LVCMOS15 I O Standard Primitives Attributes IBUFABUFG OBUF OBUFT IOBUF IOSTANDARD LVCMOS18 LVCMOS18 LVCMOS18 LVCMOS15 LVCMOS15 LVCMOS15 CAPACITANCE LOW NORMAL DONT_CARE DRIVE UNUSED 2 4 6 8 12 16 2 4 6 8 12 16 SLEW UNUSED FAST SLOW FAST SLOW LVDCI Low Voltage Digitally Controlled Impedance Using these I O buffers configures the outputs as controlled impedance drivers The receiver of LVDCI is identical to a LVCMOS receiver Some I O standards such as LVTTL IVCMOS etc must have a drive impedance that matches the characteristic impedance of the driven line Virtex 4 devices provide a controlled impedance output driver to provide series termination without external source termination resistors The impedance is set by the common
195. LVDS links The output AC characteristics of the LVDS extended mode driver are not within the EIA TIA specifications The LVDS extended mode driver is intended for situations requiring higher drive capabilities to produce an LVDS signal within the EIA TIA specification at the receiver www xilinx com Virtex 4 User Guide UGO070 v1 5 March 21 2006 XILINX Specific Guidelines for Virtex 4 I O Supported Standards Transmitter Termination The Virtex 4 LVDS transmitter does not require any external termination Table 6 33 lists the allowed attributes corresponding to the Virtex 4 LVDS current mode drivers Virtex 4 LVDS current mode drivers are a true current source and produce the proper EIA TIA compliant LVDS signal Receiver Termination LVDS 25 DCI LVDSEXT 25 DCI Usage LVDS 25 DCI and LVDSEXT 25 DCI provide split termination for the P and N inputs only VRP and VRN should connect to 50 Qresistors Equivalently it provides 100 Q differential impedance between the LVDS inputs Figure 6 73 and Figure 6 74 are examples of differential termination for an LVDS receiver on a board with 50 O transmission lines External Termination 4 IOB IOB LVDS_25 Dd C Zo pq LVDS 25 RpIFF 2Zg 1000 hk ug070_6_71_071904 Figure 6 73 LVDS_25 Receiver Termination DCI r IOB IOB Veco 2 5V l 2Rypp 2Z9 1000 D1 Q 2 LVDS 25 ed E 2Rygy 229
196. N2 ISERDES c Slave Data internal 6 9 SERDES MODE SLAVE ug070 8 03 072604 Figure 8 3 Block Diagram of ISERDES Width Expansion Guidelines for Expanding the Serial to Parallel Converter Bit Width 4 Both ISERDES modules must be adjacent master and slave pairs Set the SERDES MODE attribute for the master ISERDES to MASTER and the slave ISERDES to SLAVE see SERDES MODE Attribute The user must connect the SHIFTIN ports of the MASTER to the SHIFTOUT ports of the SLAVE The SLAVE only uses the ports D3 to D6 as an input Verilog Instantiation Template to use Width Expansion Feature The following Verilog code uses the width expansion feature in DDR mode with a deserialization factor of 1 10 362 Module serial parallel converter Description Verilog instantiation template for a serial to parallel converter function using the ISERDES Device Virtex 4 Family VIL P MM EIL P Bg M M P P P MPPCGMPOUEMEPP P M OUML ML B MP M P PL P P ALUEILLA timescale 1ps 1ps module serial parallel converter Din clk in rst J www xilinx com Virtex 4 User Guide UG070 v1 5 March 21 2006 2 XILINX Input Serial to Parallel Logic Resources ISERDES input Din input input rst clk_in wire iserdes_clkout wire iobclk wire clkdiv wire shiftdatal wire shiftdata2 wire 9 0 data internal Instantiate ISERDES for forwarded clock ISERDES fwd clk
197. NA 1 bit A port ENB gt ENB 1l bit B port REGCEA gt REGCEA 1 bit A port REGCEB gt REGCEB 1 bit B port SSRA gt SSRA 1 bit A port SSRB gt SSRB 1 bit B port WEA gt WEA 4 bit A port WEB gt WEB 4 bit B port End of RAMB16 inst instantiation RAMB16 Verilog Template RAMB16 Verilog the following instance instance in the body of the de declaration RAMB_inst and or th code connect this function and outputs must be c lt Cut code below this line gt RAMB16 Virtex 4 16k 2k Parity Par Nirtex 4 User Guide RAMB16 DOA REG 0 Optional output registers on DOB REG 0 Optional output registers on INIT A 36 h000000000 Initial values on Data Input Data Input parity Input parity Input Enable Input Enable Input register enable input register enable input Synchronous Set Reset Input Synchronous Set Reset Input Write Enable Input Write Enable Input To incorporate this function into the design declaration needs to be placed sign code The instance name e port declarations within the parenthesis can be changed to properly reference and to the design All inputs onnected amatizable Block RAM A port 0 or 1 B port 0 or 1 A output port INIT B 36 h000000000 Initial values on B output port INVERT CLK DOA REG FALSE Invert clock on A port output registers TRUE or FALS
198. NX INIT 30 gt X 0000000000000000000000000000000000000000000000000000000000000000 INIT 31 gt X 0000000000000000000000000000000000000000000000000000000000000000 INIT 32 gt X 0000000000000000000000000000000000000000000000000000000000000000 INIT 33 gt X 0000000000000000000000000000000000000000000000000000000000000000 INIT 34 gt X 0000000000000000000000000000000000000000000000000000000000000000 INIT 35 gt X 0000000000000000000000000000000000000000000000000000000000000000 INIT 36 gt X 0000000000000000000000000000000000000000000000000000000000000000 INIT 37 gt X 0000000000000000000000000000000000000000000000000000000000000000 INIT 38 gt X 0000000000000000000000000000000000000000000000000000000000000000 INIT 39 gt X 0000000000000000000000000000000000000000000000000000000000000000 INIT 3A gt X 0000000000000000000000000000000000000000000000000000000000000000 INIT 3B gt X 0000000000000000000000000000000000000000000000000000000000000000 INIT 3C gt X 0000000000000000000000000000000000000000000000000000000000000000 INIT 3D gt X 0000000000000000000000000000000000000000000000000000000000000000 INIT 3E gt X 0000000000000000000000000000000000000000000000000000000000000000 INIT 3F gt X 0000000000000000000000000000000000000000000000000000000000000000 INITP 00 gt X 0000000000000000000000000000000000000000000000000000000000000000 INITP 01 gt X 000000000000000000000000000
199. O These two primitives work in conjunction with the Virtex 4 I O resource by setting the IOSTANDARD attribute to the desired standard Refer to Chapter 6 I O Compatibility Table 6 38 for a complete list of possible I O standards Global Clock Buffers Virtex 4 User Guide There are 32 global clock buffers in every Virtex 4 device Each half of the die top bottom contains 16 global clock buffers A global clock input can directly connect from the P side of the differential input pin pair to any global clock buffer input in the same half either top or bottom of the device Each differential global clock pin pair can connect to either a differential or single ended clock on the PCB If using a single ended clock then the P side of the pin pair must be used because a direct connection only exists on this pin For pin naming conventions please refer to the Virtex 4 Packaging Specifications A single ended clock connected to the N side of the differential pair results in a local route and creates additional delay If a single ended clock is connected to a differential pin pair then the other side N side typically can not be used as another single ended clock pin However it can be used as a user I O A device with 16 global clock pins can be connected to 16 differential or 16 single ended board clocks A device with 32 global clock pins can be connected to 32 clocks under these same conditions Global clock buffers allow
200. O UG070_1_10_082504 Figure 1 10 BUFGMUX_1 Timing Diagram In Figure 1 10 e The current clock is IO e Sis activated High e IfIO is currently Low the multiplexer waits for IO to be asserted High e Once I0 is High the multiplexer output stays High until I1 transitions Low to High e When Il transitions from Low to High the output switches to I1 e IfSetup Hold are met no glitches or short pulses can appear on the output 28 www xilinx com Virtex 4 User Guide UG070 v1 5 March 21 2006 XILINX Global Clocking Resources BUFGMUX_VIRTEX4 BUFGMUX_VIRTEX4 is a clock buffer with two clock inputs one clock output and a select line This primitive is based on BUFGCTRL with some pins connected to logic High or Low Figure 1 11 illustrates the relationship of BUFGMUX_VIRTEX4 and BUFGCTRL IGNORE1 CE1 S1 GND Vpp BUFGMUX_VIRTEX4 5o 50 Wan CEO GND IGNOREO ug070 1 11 071304 Figure 1 11 BUFGMUX_VIRTEX4 as BUFGCTRL BUFGMUX_VIRTEX4 uses the S pins as select pins S can switch anytime without causing a glitch The Setup Hold time on S is for determining whether the output will pass an extra pulse of the previously selected clock before switching to the new clock If 5 changes as shown in Figure 1 12 prior to the setup time Tgcccx s and before I0 transitions from High to Low then the output will not pass an extra pulse of I0 If S changes following the hold time for S then the output will pas
201. OP A B Data Output Parity Bus REGCE A B Output Register Enable CASCADEINL A B Cascade input pin for 32K x 1 mode CASCADEOUT A B Cascade output pin for 32K x 1 mode Notes 1 The Data Parity Buses DIP A B and DOP A B section has more information on Data Parity pins Virtex 4 User Guide UGO070 v1 5 March 21 2006 www xilinx com 111 Chapter 4 Block RAM XILINX Read Operation The read operation uses one clock edge The read address is registered on the read port and the stored data is loaded into the output latches after the RAM access time Write Operation A write operation is a single clock edge operation The write address is registered on the write port and the data input is stored in memory Operating Modes There are three modes of a write operation The read during write mode offers the flexibility of using the data output bus during a write operation on the same port Output mode is set during device configuration These choices increase the efficiency of block RAM memory at each clock cycle Three different modes are used to determine data available on the output latches after a write clock edge WRITE_FIRST READ_FIRST and NO_CHANGE Mode selection is set by configuration One of these three modes is set individually for each port by an attribute The default mode is WRITE_FIRST WRITE_FIRST or Transparent Mode Default In WRITE_FIRST mode the input data is simultaneo
202. PERFORMANCE MODE attribute allows the choice of optimizing the DCM either for high frequency and low jitter or for low frequency and a wide phase shift range The attribute values are MAX SPEED and MAX RANCGE The default value is MAX SPEED When set to MAX SPEED the DCM is optimized to produce high frequency clocks with low jitter However the phase shift range is smaller than when MAX RANGE is selected When set to MAX RANGE the DCM is optimized to produce low frequency clocks with a wider phase shift range The DCM PERFORMANCE MODE affects the following specifications DCM input and output frequency range phase shift range output jitter DCM TAP CLKIN CLKFB PHASE CLKOUT PHASE and duty cycle precision The Virtex 4 Data Sheet specifies these values For most cases the DCM PERFORMANCE MODE attribute should be set to MAX SPEED default Consider changing to MAX RANGE only in the following situations e The frequency needs to be below the low frequency limit of the MAX SPEED setting e A greater absolute phase shift range is required www xilinx com Virtex 4 User Guide UGO070 v1 5 March 21 2006 XILINX DCM Attributes FACTORY JF Attribute The Factory JF attribute affects the DCMs jitter filter characteristics This attribute controls the DCM tap update rate Factory JF must be set to a specific value depending on the DLL FREQUENCY MODE setting The default value is FOFO corresponding to DLL FREQUENCY MODE LOW de
203. Parameters cies 197 Slice Carry Chain Timing Characteristics cese 197 CLB Primitives and Verilog VHDL Examples 0005 198 Distributed RAM Primitives 0 0 0 0 cc ccc en 198 VHDL and Verilog Instantiations 6666s 199 Port SEDAS cc tesla ed onde oid aha ances stares cette ear qeetitqeb eden oberen qe endende dra fece 199 Clock WGOLEK Lace ha Ge ted wade ead eee eae 199 Enables WE 21 3 e Reed rit estere n e tete dee c ee Mou Sees Mn ey 199 Address AO A1 A2 A3 A4 AB llle mnn 199 pica s Dirken ri a IPP TT E BP E S 199 Data Out O SPO and DPO 2 nent teen reen 199 Inverting Control Pins RE eger Re Rh xk ee eee ee Bente ena 199 Global Set Reset GSR i ccc ccc cence ee hh hu hh hh hin 199 Attributes o xe ceed eon estate d tete metui ni eae ee me Ed unde ens 200 Content Initialization INIT 0 0 een eee eee eens 200 Initialization in VHDL or Verilog Codes 6 6 ccc eee eee 200 Location Constraints cic ee eee eee bebe ee eee eh 200 Creating Larger RAM Structures 0 eee eet ee ene eens 201 VHDL and Verilog Templates 0 ect eee nes 201 Shift Registers SRLs Primitives and Verilog VHDL Example 203 SRL Primitives and Submodules 0 00 ccc cence teenies 203 Initialization in VHDL or Verilog Code 6 6 eens 205 Port Sigmalls 14 eR prp de Rete RE He ER Eee Ete dee tLe d eredi 205 TOG dque vvv 205 Data
204. RMAL LOW NORMAL DONT CARE DONT CARE CSE Differential IVPECL Low Voltage Positive Emitter Coupled Logic LVPECL is a very popular and powerful high speed interface in many system applications Virtex 4 I Os are designed to comply with the EIA TIA electrical specifications for 2 5V LVPECL to make system and board design easier Virtex 4 User Guide UGO070 v1 5 March 21 2006 www xilinx com 285 Chapter 6 SelectlO Resources 2 XILINX LVPECL Transceiver Termination The Virtex 4 LVPECL transmitter and receiver requires the termination shown in Figure 6 77 illustrating a Virtex 4 LVPECL transmitter and receiver on a board with 50 Q transmission lines The LVPECL driver is composed of two LVCMOS drivers that when combined with the three resistor output termination circuit form a compliant LVPECL output LVPECL 25 IOB LVPECL 25 IOB LVPECL 25 Dj Data in ug070 6 75 071904 Figure 6 77 LVPECL Transmitter Termination Table 6 37 summarizes all the possible LVPECL I O standards and attributes supported Table 6 37 Available LVPECL Primitives Primitives Attributes IBUFDS IBUFGDS OBUFDS OBUFGDS IOBUFDS IOSTANDARD LVPECL CAPACITANCE LOW NORMAL NORMAL LOW NORMAL DONT_CARE DONT_CARE Rules for Combining I O Standards in the Same Bank The following rules must be obeyed to combine different input output and bi directional s
205. Resources synthesis translate_on port O out STD LOGIC I in STD LOGIC C in STD LOGIC CE in STD LOGIC INC in STD LOGIC RST in STD LOGIC Jos end component Component Attribute specification for IDELAY should be placed after architecture declaration but before the begin keyword Architecture Section attribute IOBDELAY TYPE string attribute IOBDELAY VALUE integer Component Instantiation for IDELAY should be placed in architecture after the begin keyword Instantiation Section Ul IDELAY synthesis translate off generic map IOBDELAY TYPE FIXED Set to FIXED for Fixed delay mode IOBDELAY VALUE gt 31 Set the delay value equal to the center of the delay element synthesis translate on port map O gt data output I data input C gt clkdiv CE gt open INC gt open RST gt dlyrst Verilog Code for Fixed Delay Mode The IDELAYCTRL primitive must be instantiated in conjunction with IDELAY primitive when used in Fixed Delay Mode Module IDELAY Description Verilog instantiation template Fixed Delay Mode Device Virtex 4 Family 1 Virtex 4 User Guide www xilinx com 327 UG070 v1 5 March 21 2006 Chapter 7 SelectlO Logic Resources XILINX Instantiation Section
206. Resources describes the data serializer deserializer SERDES An I O tile contains two IOBs two ILOGICs and two OLOGICs Figure 6 1 shows a Virtex 4 I O tile ILOGIC Chapter 7 or ISERDES OLOGIC Chapter 7 ILOGIC Chapter 7 or ISERDES Chapter 8 ug070 6 01 071104 Figure 6 1 Virtex 4 I O Tile Virtex 4 User Guide www xilinx com 215 UGO070 v1 5 March 21 2006 Chapter 6 SelectlO Resources XILINX SelectlO Resources Introduction All Virtex 4 FPGAs have configurable high performance SelectIO drivers and receivers supporting a wide variety of standard interfaces The robust feature set includes programmable control of output strength and slew rate and on chip termination using Digitally Controlled Impedance DCI All banks can support 3 3V I O Each IOB contains both input output and 3 state SelectIO drivers These drivers can be configured to various I O standards Differential I O uses the two IOBs grouped together in one tile e Single ended I O standards LVCMOS LVTTL HSTL SSTL GTL PCI e Differential I O standards LVDS LDT LVPECL BLVDS CSE Differential HSTL and SSTL Each Virtex 4 I O tile contains two IOBs and also two ILOGIC blocks and two OLOGIC blocks as described in Chapter 7 SelectIO Logic Resources Figure 6 2 shows the basic IOB and its connections to the internal logic and the device Pad DIFFO_IN PAD DIFFO_OUT I JY Pibour oL I
207. STL_II_DCI 2Rypp 2Zo 1002 2Rypp 2Zg 1000 4o 2 D3 4 E 2Rygw 2Zo 1002 2Rypy 2Zo 1002 Voco 15V Voco 15V DIFFAISTIILDG aR yap 2Zg 1000 2Rygp 2Zo 1002 D14 0 29 P 41 4 E 2Rypn 2Zg 1000 4 2Rypy 2Zo 1000 DIFF HSTL Il DCI ug070 6 41 071904 Figure 6 43 Differential HSTL 1 5V Class Il DCI Unidirectional Termination Figure 6 44 shows a sample circuit illustrating a valid termination technique for differential HSTL Class II 1 5V with bidirectional termination External Termination DIFF HSTL Il DIFF HSTL Il IOB v 0 75V Vr 0 75V 50Q DIFF HSTL Il Figure 6 44 Differential HSTL 1 5V Class II Bidirectional Termination Virtex 4 User Guide UGO070 v1 5 March 21 2006 Q 20 www xilinx com Vr 0 75V 500 DIFF HSTL II DIFF HSTL II DIFF HSTL II ug070 6 42 071904 253 Chapter 6 SelectlO Resources XILINX Figure 6 45 shows a sample circuit illustrating a valid termination technique for differential HSTL Class II 1 5V with bidirectional DCI termination DCI IOB DIFF HSTL Il DCI DIFF HSTL Il DCI 2Rypp 2Zg 1002 2Rygw 2Zg 1000 DIFF HSTL Il DCI DIFF HSTL Il DCI Voco 1 5V 2Rypp 2Zg 1002 2Rygw 2Zg 1000 Figure 6 45 Differential HSTL 1 5V Class II DCI Bidirectional Termination Veco 15V D
208. SelectlO Logic Resources XILINX 344 Combinatorial Output Data and 3 State Control Path The combinatorial output paths create a direct connection from the FPGA fabric to the output driver or output driver control These paths is used when 1 There is direct unregistered connection from logic resources in the FPGA fabric to the output data or 3 state control 2 The pack I O register latches into IOBs is set to OFF Output DDR Overview ODDR Virtex 4 devices have dedicated registers in the OLOGIC to implement output DDR registers This feature is accessed when instantiating the ODDR primitive DDR multiplexing is automatic when using OLOGIC No manual control of the mux select is needed This control is generated from the clock There is only one clock input to the ODDR primitive Falling edge data is clocked by a locally inverted version of the input clock All clocks feeding into the I O tile are fully multiplexed i e there is no clock sharing between ILOGIC or OLOGIC blocks The ODDR primitive supports the following modes of operation e OPPOSITE_EDGE mode e SAME EDGE mode The SAME_EDGE mode is new for the Virtex 4 architecture This new mode allows designers to present both data inputs to the ODDR primitive on the rising edge of the ODDR clock saving CLB and clock resources and increasing performance This mode is implemented using the DDR CLK EDGE attribute It is supported for 3 state control as well The follo
209. TATE WIDTH integer 4 VF port OQ out std ulogic SHIFTOUT1 out std ulogic SHIFTOUT2 out std ulogic TO out std ulogic CLK in std ulogic CLKDIV in std ulogic D1 in std ulogic D2 in std ulogic D3 in std ulogic D4 in std ulogic D5 in std ulogic D6 in std ulogic OCE in std ulogic REV in std ulogic SHIFTIN1 in std ulogic SHIFTIN2 in std ulogic 384 www xilinx com Virtex 4 User Guide UGO070 v1 5 March 21 2006 2 XILINX Output Parallel to Serial Logic Resources OSERDES SR in std_ulogic T1 in std ulogic T2 in std ulogic T3 in std ulogic T4 in std ulogic TCE in std ulogic end component Example OSERDES instantiation U OSERDES Port map OQ user oq SHIFTOUT1 gt user shiftoutl SHIFTOUT2 user shiftout2 TO gt user tq OSERDES CLK user clk CLKDIV user clkdiv D1 gt user dl D2 gt user_d2 D3 gt user_d3 D4 gt user d4 D5 gt user_d5 D6 gt user_d6 OCE gt user_oce REV gt user_rev SHIFTIN1 gt user shiftinl SHIFTIN2 gt user shiftin2 SR gt user sr T1 gt user t1 T2 gt user t2 T3 user t3 T4 gt user t4 TCE user tce OSERDES Verilog Template Example OSERDES module declaration module OSERDES OQ SHIFTOUT1 SHIFTOUT2 TQ CLK D4 D5 D6 OCE REV SHIFTIN1 SHIFTIN2 SR T1
210. THE ENTIRE RISK AS TO ITS FUNCTION AND IMPLEMENTATION IS WITH YOU YOU ACKNOWLEDGE AND AGREE THAT YOU HAVE NOT RELIED ON ANY ORAL OR WRITTEN INFORMATION OR ADVICE WHETHER GIVEN BY XILINX OR ITS AGENTS OR EMPLOYEES XILINX MAKES NO OTHER WARRANTIES WHETHER EXPRESS IMPLIED OR STATUTORY REGARDING THE SPECIFICATION INCLUDING ANY WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE TITLE AND NONINFRINGEMENT OF THIRD PARTY RIGHTS IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL INDIRECT EXEMPLARY SPECIAL OR INCIDENTAL DAMAGES INCLUDING ANY LOST DATA AND LOST PROFITS ARISING FROM OR RELATING TO YOUR USE OF THE SPECIFICATION EVEN IF YOU HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES THE TOTAL CUMULATIVE LIABILITY OF XILINX IN CONNECTION WITH YOUR USE OF THE SPECIFICATION WHETHER IN CONTRACT OR TORT OR OTHERWISE WILL IN NO EVENT EXCEED THE AMOUNT OF FEES PAID BY YOU TO XILINX HEREUNDER FOR USE OF THE SPECIFICATION YOU ACKNOWLEDGE THAT THE FEES IF ANY REFLECT THE ALLOCATION OF RISK SET FORTH IN THIS AGREEMENT AND THAT XILINX WOULD NOT MAKE AVAILABLE THE SPECIFICATION TO YOU WITHOUT THESE LIMITATIONS OF LIABILITY The Specification is not designed or intended for use in the development of on line control equipment in hazardous environments requiring fail safe controls such as in the operation of nuclear facilities aircraft navigation or communications systems air traffic control life support or weapons systems H
211. Templates and the Clocking Wizard VHDL Template Example PMCD Component Declaration compon gene Jg port IE end component Example PMCD instantiation U_PMCD ent PMCD ric EN REL RST DEASSERT CLK CLKA1 CLKA1D2 CLKA1D4 CLKA1D8 CLKB1 CLKC1 CLKD1 CLKA CLKB CLKC CLKD REL RST PMCD Port map CLKA1 gt user clkal1 user clkai1g32 user clkai1d4 user clkai1d8 CLKA1D2 gt CLKA1D4 gt CLKA1D8 gt CLKB1 gt CLKC1 gt CLKD1 gt CLKA gt CLKB gt CLKC gt CLKD gt REL gt RST gt boolean string out std_ulogic out std_ulogic out std_ulogic out std_ulogic out std_ulogic out std_ulogic out std_ulogic in std ulogic in std ulogic in std ulogic in std ulogic in std ulogic in std ulogic user clkb1 user clkc1 user clkd1 user clka user clkb user clkc user clkd user rel user rst FA Cy Virtex 4 User Guide UG070 v1 5 March 21 2006 www xilinx com 107 Chapter 3 Phase Matched Clock Dividers PMCDs XILINX Verilog Template Example PMCD module declaration module PMCD CLKA1 CLKA1D2 CLKA1D4 CLKA1D8 CLKA CLKB CLKC CLKD REL RST output CLKA1 output CLKA1D2 output CLKA1D4 output CLKA1D8 output CLKB1 output CLKC1 output CLKD1 input CLKA input CLKB input CLKC input CLKD input REL input RST parameter EN_REL FALSE
212. The user either declares the LOC constraints in the VHDL design file or in the UCF file Declaring LOC constraints in the VHDL file attribute loc string attribute loc of dlyctrl 1 1abel is IDELAYCTRL X0Y0 attribute loc of dlyctrl 2 1abel is IDELAYCTRL XOY1 attribute loc of dlyctrl n label is IDELAYCTRL XnYn Declaring LOC constraints in the UCF file INST dlyctrl 1 LOC IDELAYCTRL X0Y0 INST dlyctrl 2 LOC IDELAYCTRL X0Y1 INST dlyctrl n LOC IDELAYCTRL XnYn Verilog Use Model Multiple instances of IDELAYCTRL primitives are instantiated Each instance has its own RST and RDY signal to allow for partial reconfiguration The REFCLK signal is common to all instances IDELAYCTRL dlyctrl 1 RDY rdy 1 REFCLK refclk RST rst 1 Jur IDELAYCTRL dlyctrl 2 RDY rdy 2 REFCLK refclk RST rst 2 IDELAYCTRL dlyctrl n RDY rdy n REFCLK refclk RST rst n The user either declares the LOC constraints in the Verilog design file or in the following UCF file Declaring LOC constraints in the Verilog file synthesis attribute loc of dlyctrl 1 is IDELAYCTRL X0YO synthesis attribute loc of dlyctrl 2 is IDELAYCTRL_XOY1 synthesis attribute loc of dlyctrl N is IDELAYCTRL XnYn Declaring LOC constraints in the UCF file INST dlyctrl 1 LOC IDELAYCTRL X0Y0 Virtex 4 User Guide www xilinx com 337 U
213. UENCY_MODE This specifies the frequency mode String LOW or HIGH LOW of the DLL DUTY_CYCLE_CORRECTION This controls the DCM Boolean TRUE or FALSE TRUE 1X outputs CLKO CLK90 CLK180 and CLK270 to exhibit a 50 50 duty cycle Leave this attribute set at the default value DCM_PERFORMANCE_MODE Allows selection between String MAX_SPEED or MAX_SPEED maximum frequency minimum MAX RANGE jitter and low frequency maximum phase shift range FACTORY JF DLL FREQUENCY MODE LOW BIT VECTOR FOFO default FOFO DLL FREQUENCY MODE HIGH default FOFO PHASE SHIFT This specifies the phase shift Integer 255 to 1023 0 numerator The value range depends on CLKOUT_PHASE_SHIFT and clock frequency STARTUP_WAIT When this attribute is set to TRUE Boolean FALSE or TRUE FALSE the configuration startup sequence waits in the specified cycle until the DCM locks 66 www xilinx com Virtex 4 User Guide UG070 v1 5 March 21 2006 X XILINX DCM Design Guidelines DCM Design Guidelines This section provides a detailed description on using the Virtex 4 DCM and design guidelines Clock Deskew The Virtex 4 DCM offers a fully digital dedicated on chip clock deskew The deskew feature provides zero propagation delay between the source clock and output clock low clock skew among output clock signals distributed throughout the device and advanced clock domain control The deskew feature also functi
214. ULL Clock to full output FULL Time after WRCLK that the Full signal is stable at the FULL outputs of the FIFO TECKO_RDERR Clock to read error RDERR Time after RDCLK that the Read Error signal is output stable at the RDERR outputs of the FIFO Trcko wRERRU Clock to write error WRERR Time after WRCLK that the Write Error signal is output stable at the WRERR outputs of the FIFO Tgcko RDCOUNT Clock to read pointer output RDCOUNT Time after RDCLK that the Read pointer signal is stable at the RDCOUNT outputs of the FIFO TECKO_WRCOUNT Clock to write pointer WRCOUNT Time after WRCLK that the Write pointer signal is output stable at the WRCOUNT outputs of the FIFO Reset to Out TECO_AEMPTY Reset to almost empty AEMPTY Time after reset that the Almost Empty signal is output stable at the ALMOSTEMPTY outputs of the FIFO Trco AFULL Reset to almost full AFULL Time after reset that the Almost Full signal is stable output at the ALMOSTFULL outputs of the FIFO TECO_EMPTY Reset to empty output EMPTY Time after reset that the Empty signal is stable at the EMPTY outputs of the FIFO 148 www xilinx com Virtex 4 User Guide UG070 v1 5 March 21 2006 XILINX Table 4 14 FIFO Timing Parameters Continued FIFO Timing Models and Parameters Control Parameter Function Signal Description TECO_FULL Reset to full output FULL Time after reset that the Full
215. V Select Vpgg to provide the optimum noise margin in specific use conditions Table 6 6 HSLVDCI Input DC Voltage Specifications Standard Min Typ Max VREF Vcco 2 Vid VREF 0 1 2 Vit VREF 0 1 Table 6 7 details the allowed attributes that can be applied to the LVDCI HSLVDCI and LVDCI DV2 I O standards Table 6 7 Allowed Attributes of the LVDCI HSLVDCI and LVDCI DV2 I O Standards Primitives Attributes IBUF IBUFG OBUF OBUFT IOBUF IOSTANDARD LVDCI 15 LVDCI 18 LVDCI 25 LVDCI 33 LVDCI DV2 15 LVDCI DV2 18 LVDCI DV2 25 HSLVDCI 15 HSLVDCI 18 HSLVDCI 25 HSLVDCI 33 CAPACITANCE LOW NORMAL DONT CARE UGO070 v1 5 March 21 2006 www xilinx com 243 Chapter 6 SelectlO Resources PCIX PCI33 PCI66 Peripheral Component Interface The PCI standard specifies support for 33 MHz 66 MHz and 133 MHz PCI bus applications It uses an LVTTL input buffer and a push pull output buffer This standard does not require the use of a reference voltage Vpgp or a board termination voltage Vyr However it does require 3 3V input output source voltage Vcco XILINX A PCI undershoot overshoot specification could require Vcco to be regulated at 3 0V as discussed in Regulating Vcco at 3 0V page 293 This is not necessary if overshoot and undershoot are controlled by careful design Table 6 8 lists the DC voltage specifications Table 6 8 PCIS33 3 PCI6
216. Virtex 4 User Guide UGO070 v1 5 March 21 2006 XILINX XILINX Xilinx is disclosing this Specification to you solely for use in the development of designs to operate on Xilinx FPGAs Except as stated herein none of the Specification may be copied reproduced distributed republished downloaded displayed posted or transmitted in any form or by any means including but not limited to electronic mechanical photocopying recording or otherwise without the prior written consent of Xilinx Any unauthorized use of this Specification may violate copyright laws trademark laws the laws of privacy and publicity and communications regulations and statutes Xilinx does not assume any liability arising out of the application or use of the Specification nor does Xilinx convey any license under its patents copyrights or any rights of others You are responsible for obtaining any rights you may require for your use or implementation of the Specification Xilinx reserves the right to make changes at any time to the Specification as deemed desirable in the sole discretion of Xilinx Xilinx assumes no obligation to correct any errors contained herein or to advise you of any correction if such be made Xilinx will not assume any liability for the accuracy or correctness of any engineering or technical support or assistance provided to you in connection with the Specification THE SPECIFICATION IS PROVIDED AS IS WITH ALL FAULTS AND
217. Virtex 4 devices several 3 3V I O design guidelines and techniques are highlighted in this section This includes managing overshoot undershoot with termination techniques regulating Vcco at 3 0V with a voltage regulator using external bus switches reviewing configuration methods and other design considerations I O Standard Design Rules Overshoot Undershoot Undershoot and overshoot voltages on I Os operating at 3 3V should not exceed the absolute maximum ratings of 0 3V to 4 05V respectively when Vcco is 3 75V These absolute maximum limits are stated in the absolute maximum ratings table in Table 6 38 of the Virtex 4 Data Sheet However the maximum undershoot value is directly affected by 290 www xilinx com Virtex 4 User Guide UGO070 v1 5 March 21 2006 XILINX Rules for Combining I O Standards in the Same Bank the value of Vcco Table 6 38 describes the worst case undershoot and overshoot at different Vcco levels The voltage across the gate oxide at any time must not exceed 4 05V Consider the case in which the I O is either an input or a 3 stated buffer as shown in Figure 6 78 The gate of the output PMOS transistor Py and NMOS transistor N is connected essentially to Veco and ground respectively The amount of undershoot allowed without overstressing the PMOS transistor Py is the gate voltage minus the gate oxide limit or Veco 4 05V Similarly the absolute maximum overshoot allowed without overstr
218. WRITE WIDTH B gt 0 Valid values are 1 2 4 9 18 or 36 INIT 00 gt X 0000000000000000000000000000000000000000000000000000000000000000 INIT 01 gt X 0000000000000000000000000000000000000000000000000000000000000000 INIT 02 gt X 0000000000000000000000000000000000000000000000000000000000000000 INIT 03 gt X 0000000000000000000000000000000000000000000000000000000000000000 INIT 04 gt X 0000000000000000000000000000000000000000000000000000000000000000 INIT 05 gt X 0000000000000000000000000000000000000000000000000000000000000000 INIT 06 gt X 0000000000000000000000000000000000000000000000000000000000000000 INIT 07 gt X 0000000000000000000000000000000000000000000000000000000000000000 INIT 08 gt X 0000000000000000000000000000000000000000000000000000000000000000 INIT 09 gt X 0000000000000000000000000000000000000000000000000000000000000000 INIT 0A gt X 0000000000000000000000000000000000000000000000000000000000000000 INIT 0B gt X 0000000000000000000000000000000000000000000000000000000000000000 INIT 0C gt X 0000000000000000000000000000000000000000000000000000000000000000 INIT 0D gt X 0000000000000000000000000000000000000000000000000000000000000000 INIT OE gt X 0000000000000000000000000000000000000000000000000000000000000000 INIT OF gt X 0000000000000000000000000000000000000000000000000000000000000000 INIT 10 gt
219. X PCI33 PCI66 Peripheral Component Interface 00 0 eee 244 GTL Gunning Transceiver Logic sssseeeeeeeeeee eens 245 GIL_DGl Usage satis bite gae Pes laa e rx E eer Sa ee a 245 GTLP Gunning Transceiver Logic Plus 6 06 c cece ene eee 246 12 www xilinx com Virtex 4 User Guide UG070 v1 5 March 21 2006 X XILINX GILP_DCI Usage esns esis ep enian tin ea RE been tede Era 246 HSTL High Speed Transceiver Logic 6 c cece ee eee 248 HSTL I HSTL IIL HSTL I 18 HSTL III 18Usage eene 248 HSTL I DCI HSTL III DCI HSTL I DCI 18 HSTL III DCI 18Usage 248 HSTL IL HSTL_IV HSTL II 18 HSTL IV 18Usage eene 248 HSTL II DCI HSTL IV DCI HSTL II DCI 18 HSTL IV DCI 18Usage 248 DIFE FISTL IT DIFF HSTE M 18 ose DRYER XD Dex eR REG nM RC 248 DIFF HSTL II DCI DIFF HSTL II DCI 18 eeeeee 248 HSETLECIl assT xue er tto tret repos de RA etn eines 249 ASU Class 22r tke leeds dates RPEEE RU TO ER DECORA Eae d 250 Complementary Single Ended CSE Differential HSTL Class II 252 ESTE Class M ees ee REERDTCERLDCCE and Se eR es ee 255 HSTLClass IV eet rebate oh eser toe Guta pa ri dcs EUH ab ae ape V 256 HSTL ClassI 1 8V iii sseceket e ete eRexee e 9 a Er RO a whee RO Red 258 HSTE Class IL 18V ties asus gare eU need e ta RA E RE ARR Ene 259 Complementary Single Ended CSE Differential HSTL Class II 1 8V 261 HASTE Cla
220. X 16 1 SUBM MUX 32 1 SUBM The corresponding submodules have to be synthesized with the design The submodule MUX 16 1 SUBM is provided as an example in VHDL and Verilog VHDL Template Module MUX 16 1 SUBM Description Multiplexer 16 1 Device Virtex 4 Family library IEEE use IEEE std logic 1164 all library UNISIM use UNISIM VCOMPONENTS ALL entity MUX 16 1 SUBM is port DATA I in std logic vector 15 downto 0 SELECT I in std logic vector 3 downto 0 DATA O out std logic end MUX 16 1 SUBM architecture MUX 16 1 SUBM arch of MUX 16 1 SUBM is Component Declarations component MUXF7 port I0 in std logic I1 in std logic S in std logic O out std logic end component signal DATA MSB std logic signal DATA LSB std logic begin SELECT PROCESS LSB process SELECT I DATA I begin case SELECT I 2 downto 0 is www xilinx com Virtex 4 User Guide UGO070 v1 5 March 21 2006 2 XILINX Multiplexer Primitives and Verilog VHDL Examples when 000 gt DATA LSB lt DATA when 001 gt DATA_LSB lt DATA_ when 010 gt DATA LSB lt DATA_ when 011 gt DATA_LSB lt DATA_ when 100 gt DATA LSB lt DATA when 101 gt DATA LSB lt DATA when 110 gt DATA LSB lt DATA when 111 gt DATA_LSB lt DATA_ when others gt DATA_LSB lt X end case end process SELECT_PROC
221. X0Y6 PMCD X0Y7 one tile 94 www xilinx com Virtex 4 User Guide UG070 v1 5 March 21 2006 XILINX PMCD Primitives Ports and Attributes PMCD Primitives Ports and Attributes Figure 3 2 illustrates the PMCD primitive The VHDL and Verilog template section includes an example of a PMCD instantiation template CLKA1 CLKA1D2 CLKA1D4 CLKA1D8 ug070_3_02_071404 Figure 3 2 PMCD Primitive Table 3 2 lists the port names and description of the ports Table 3 2 PMCD Port Description Port Name Direction Description CLKA Input CLKA isa clock input to the PMCD The CLKA frequency can be divided by 1 2 4 and 8 CLKB Input CLKB CLKC and CLKD are clock inputs to the PMCD These clock are not divided by CLKC the PMCD however they are delayed by the PMCD to maintain the phase alignment CLKD and phase relationship at the input clocks RST Input RST is the reset input to the PMCD Asserting the RST signal asynchronously forces all outputs Low Deasserting RST synchronously allows all outputs to toggle REL Input REL is the release input to the PMCD Asserting the REL signal releases the divided output synchronous to CLKA CLKA1 Output The CLKA1 output has the same frequency as the CLKA input It is a delayed version of CLKA CLKA1D2 Output The CLKA1D2 output has the frequency of CLKA divided by two CLKA1D2 is rising edge aligned to CLKA1 CLKA1D4 Outpu
222. X180 The CLK2X180 output clock provides a clock with the same frequency as the DCM s CLK2X only phase shifted by 180 Frequency Divide Output Clock CLKDV The CLKDV output clock provides a clock that is phase aligned to CLKO with a frequency that is a fraction of the effective CLKIN frequency The fraction is determined by the CLKDV_DIVIDE attribute Refer to the CLKDV_DIVIDE Attribute for more information Frequency Synthesis Output Clock CLKFX The CLKFX output clock provides a clock with the following frequency definition CLKFX frequency M D x effective CLKIN frequency In this equation M is the multiplier numerator with a value defined by the CLKFX_MULTIPLY attribute D is the divisor denominator with a value defined by the CLKFX_DIVIDE attribute Specifications for M and D as well as input and output frequency ranges for the frequency synthesizer are provided in the Virtex 4 Data Sheet The rising edge of CLKFX output is phase aligned to the rising edges of CLK0 CLK2X and CLKDV When M and D to have no common factor the alignment occurs only once every D cycles of CLKO Frequency Synthesis Output Clock 180 CLKFX180 The CLKFX180 output clock provides a clock with the same frequency as the DCM s CLKFX only phase shifted by 180 Status and Data Output Ports Locked Output LOCKED The LOCKED output indicates whether the DCM clock outputs are valid i e the outputs exhibit the proper frequency and phas
223. Xilinx recommends proper I O termination and performing IBIS simulation Source Termination and LVDCI_ 33 In general the I O drivers should match the board trace impedance to within 10 to minimize overshoot and undershoot Source termination is often used for unidirectional interfaces The DCI feature has built in source termination on all user output pins It compensates for impedance changes due to voltage and or temperature fluctuations and can match the reference resistor values Assuming the reference resistor values are the same as the board trace impedance the output impedance of the driver will closely match with the board trace The LVDCI_33 standard is used to enable the DCI features for 3 3V I O operations As shown in Figure 6 79 the OBUF_LVDCI_33 primitive is used to implement the source termination function in Virtex 4 output drivers The pull up resistor connected to VRN and the pull down resistor connected to VRP determine the output impedance of all the output drivers in the same bank The Virtex 4 Digitally Controlled Impedance DCI section has more details on using DCI Since the LVDCI_33 standard does not offer input termination source termination must be implemented on the driver side Figure 6 79 shows the recommended external source termination resistors to be incorporated on the external device side The total impedance of the LVTTL LVCMOS driver added to the series termination resistor Ry must match the board t
224. YPE FIXED IOBDELAY VALUE 0 Combinatorial Tii D pin to O pin propagation delay no Delay Tipp D pin to O pin propagation delay IOBDELAY TYPE DEFAULT D pin to O pin propagation delay IOBDELAY_TYPE FIXED IOBDELAY_VALUE 0 Sequential Delays TIDLO D pin to O1 pin using flip flop as a latch without Delay TipLop D pin to O1 pin using flip flop as a latch IOBDELAY TYPE DEFAULT D pin to O1 pin using flip flop as a latch IOBDELAY TYPE FIXED IOBDELAY VALUE 0 Ticko CLK to Q outputs TicE19 CE1 pin to O1 using flip flop as a latch propagation delay Tro SR REV pin to OO TO out 320 www xilinx com Virtex 4 User Guide UG070 v1 5 March 21 2006 XILINX ILOGIC Resources Input Delay Element IDELAY Every ILOGIC block contains a programmable absolute delay element called IDELAY IDELAY is a 64 tap wraparound delay element with a fixed guaranteed tap resolution see Virtex 4 Data Sheet It can be applied to the combinatorial input path registered input path or both IDELAY allows incoming signals to be delayed on an individual basis The delay element is calibrated to provide an absolute delay value TIDELAYRESOLUTION independent of process voltage and temperature variation Three modes of operation are available e Zero hold time delay mode IOBDELAY_TYPE DEFAULT This mode of operation allows backward compatibility for designs using the zero hold
225. _II_DCI_18 HSTL_II_DCI_18 2Rygw 2Zg 1002 i VREF 0 9V 2RyRN 2Z9 1000 gt 544775 E 4 ug070 6 49 071904 Figure 6 51 HSTL Class II 1 8V with Bidirectional Termination 260 www xilinx com Virtex 4 User Guide UG070 v1 5 March 21 2006 XILINX Specific Guidelines for Virtex 4 I O Supported Standards Table 6 20 lists the HSTL Class IT 1 8V DC voltage specifications Table 6 20 HSTL Class Il 1 8V DC Voltage Specifications Min Typ Max Vcco 1 7 1 8 1 9 Veer 2 0 9 Vir Veco x 0 5 VH Var 0 1 E Va Vgrr 0 1 Vou Veco 0 4 VoL 0 4 Tox at Voy mA 16 Ior at Vor mA 16 Notes 1 Vor and Vog for lower drive currents are sample tested 2 Per EIA JESD8 6 The value of Vggp is to be selected by the user to provide optimum noise margin in the use conditions specified by the user Complementary Single Ended CSE Differential HSTL Class II 1 8V Figure 6 52 shows a sample circuit illustrating a valid termination technique for differential HSTL Class II 1 8V with unidirectional termination External Termination Vr 0 9V Vr 0 9V IOB IOB DIFF_HSTL_II_18 5b sja q IED X DIFF HSTL Il 18 Vr 0 9V Vr 0 9V DIFF HSTL Il 18 sid suc X C Zo A ug070 6 50 71904 Figure 6 52 Differential HSTL 1 8V Class Il Unidirectional Termination Vir
226. a 16 1 MUX ina Virtex 4 CLB 180 www xilinx com Virtex 4 User Guide UGO070 v1 5 March 21 2006 XILINX CLB Overview Slice S3 OUT_F Slice SO T7771 UGO70 5 16 071504 Figure 5 16 LUTs and MUXF5 MUXF6 and MUXF7 in One CLB Virtex 4 User Guide www xilinx com 181 UGO070 v1 5 March 21 2006 Chapter 5 Configurable Logic Blocks CLBs XILINX 32 1 Multiplexer Slice S3 of each CLB has a MUXF8 Combinatorial functions of up to 68 inputs or a 32 1 MUX fit in two CLBs as shown in Figure 5 17 The outputs of two MUXF7 are combined through dedicated routing resources between two adjacent CLBs in a column MUXF8 Slice S3 MUXF6 Slice S1 Slice S2 MUXF6 Slice SO OUT_F8 Slice S3 D MUXF6 Slice S1 Slice S2 D MUXF6 Slice SO UGO070 5 17 071504 Figure 5 17 MUXF8 Combining Two Adjacent CLBs www xilinx com Virtex 4 User Guide 182 UGO070 v1 5 March 21 2006 XILINX DATA O DATA 1 DATA 2 DATA 3 DATA 4 DATA 5 DATA 6 DATA 7 SELECT 0 SELECT 1 SELECT Wide Input Multiplexer Summary CLB Overview Each LUT can implement a 2 1 multiplexer In each slice the MUXF5 and two LUTs can implement a 4 1 multiplexer The MUXF6 and two slices can implement a 8 1 multiplexer The MUXF7 and the four slices of any CLB can
227. able submodules www xil inx com Virtex 4 User Guide UG070 v1 5 March 21 2006 X XILINX Multiplexer Primitives and Verilog VHDL Examples Table 5 17 Available Submodules Submodule Multiplexer Control Input Output MUX_2_1_SUBM 2 1 SELECT_I DATA I 1 0 DATA O MUX 4 1 SUBM 4 1 SELECT I 1 0 DATA_I 3 0 DATA O MUX 8 1 SUBM 81 SELECT I 2 0 DATA I E0 DATA O MUX 16 1 SUBM 16 1 SELECT I 3 0 DATA I 15 0 DATA O MUX 32 1 SUBM 32 1 SELECT I 4 0 DATA I 31 0 DATA O Port Signals Data In DATA The data input provides the data to be selected by the SELECT I signal s Control In SELECT _l The select input signal or bus determines the DATA I signal to be connected to the output DATA O For example the MUX 4 1 SUBM multiplexer has a 2 bit SELECT I bus and a 4 bit DATA I bus Table 5 18 shows the DATA I selected for each SELECT I value Table 5 18 Selected Inputs SELECT 1 0 DATA O 0 0 DATA I 0 01 DATA_I 1 1 0 DATA I 2 i1 DATA I 3 Data Out DATA O The data output O provides the data value 1 bit selected by the control inputs Multiplexer Verilog VHDL Examples Multiplexers are used in various applications These are often inferred by synthesis tools when a case statement is used see the following example Comparators encoder decoders and wide input combinatorial functions are optimized when they are based on one lev
228. ak pull down resistor or a weak keeper circuit For input IBUF buffers the input can have either a weak pull up resistor or a weak pull down resistor This feature can be invoked by adding the following possible constraint values to the relevant net of the buffers e PULLUP e PULLDOWN e KEEPER Virtex 4 User Guide www xilinx com 233 UGO070 v1 5 March 21 2006 Chapter 6 SelectlO Resources XILINX Differential Termination Attribute The differential termination DIFF TERM attribute is designed for the Virtex 4 supported differential input I O standards It is used to turn the built in termination resistor on or off The allowed values for the DIFF TERM attribute are e TRUE e FALSE Default The DIFF_TERM attribute uses the following syntax in the UCF file INST I O BUFFER INSTANTIATION NAME DIFF TERM DIFF TERM VALUE Virtex 4 I O Resource VHDL Verilog Examples The following examples are VHDL and Verilog syntaxes to declare a standard for Virtex 4 I O resources The example uses IOBUF VHDL Template Example IOBUF component declaration component IOBUF generic CAPACITANCE string DONT CARE DRIVE integer fo 12 TOSTANDARD string LVCMOS25 SLEW string SLOW port O out std ulogic IO inout std ulogic T 9 an std_ulogic T omn std ulogic Ju end component Example IOBUF instantiation U IOBUF IOBUF Port map O user o IO use
229. am Clock Event 1 e At time T sccK_BITSLIP before CLKDIV Event 1 the Bitslip signal is asserted High On the next CLKDIV cycle the ISERDES can perform a Bitslip operation e Bitslip must be asserted for exactly one CLKDIV cycle Holding the Bitslip pin High for multiple CLKDIV cycles will produce incorrect results Clock Event 2 e At time Trscko o after CLKDIV Event 2 at the next CLKDIV cycle after Bitslip has been held High a new output is available on the O1 to Q6 bus Virtex 4 User Guide www xilinx com 373 UGO070 v1 5 March 21 2006 Chapter 8 Advanced SelectlO Logic Resources XILINX Output Parallel to Serial Logic Resources OSERDES 374 The Virtex 4 OSERDES is a dedicated parallel to serial converter with specific clocking and logic resources designed to facilitate the implementation of high speed source synchronous interfaces Every OSERDES module includes a dedicated serializer for data and 3 state control Both Data and 3 state serializers can be configured in SDR and DDR mode Data serialization can be up to 6 1 10 1 if using OSERDES Width Expansion 3 state serialization can be up to 4 1 Figure 8 1 shows a block diagram of the OSERDES highlighting all the major components and features of the block 3 State Parallel to Serial Converter CLK CLKDIV l Data Parallel to Serial Converter Output Driver ug070 SERDES 01 072904 Figure 8 10 OSERDES Block Diagram Data
230. ameters Figure 5 26 illustrates a carry chain in a Virtex 4 slice Some elements of the Virtex 4 slice have been omitted for clarity Only the elements relevant to the timing paths described in this section are shown Virtex 4 User Guide www xilinx com 195 UGO070 v1 5 March 21 2006 Chapter 5 Configurable Logic Blocks CLBs XILINX COUT CYMUXG FXINA D gt MUXFX FXINB C gt D Q FF LAT G CE CLK SR REV inputs F inputs D Q FF LAT CE CLK SH REV BX C gt CE C gt e CLK C gt SR C gt C IN ug070 5 26 071504 Figure 5 26 Simplified Virtex 4 Slice Carry Chain Diagram 196 www xilinx com Virtex 4 User Guide UGO070 v1 5 March 21 2006 XILINX CLB Slice Timing Models Slice Carry Chain Timing Parameters Table 5 8 shows the slice carry chain timing parameters for a majority of the paths in Figure 5 26 Table 5 8 Slice Carry Chain Timing Parameters Parameter Sequential Delays for Slice LUT Configured as Carry Chain Function Description Tpxcy BX BY input to Cour Propagation delay from the BX BY inputs of the slice to Coty output of TBycv output the slice Tpyp Cry input to Cour Propagation delay from the Cjy input of the slice to Cour output of the output slice Tranpcy F G input to Cour Propagation del
231. ameters with DCM on the Virtex 4 Data Sheet reflects the setup hold and clock to out times when the DCM is in system synchronous mode Source Synchronous Setting When DESKEW ADJUST is set to source synchronous mode the DCM feedback delay element is set to zero As shown in Figure 2 4 in source synchronous mode the DCM clock feedback delay element is set to minimize the sampling window This results in a www xilinx com Virtex 4 User Guide UGO070 v1 5 March 21 2006 X XILINX DCM Design Guidelines more positive hold time and a longer clock to out compared to system synchronous mode The source synchronous switching characteristics section in the Virtex 4 Data Sheet reflects the various timing parameters for the source synchronous design when the DCM is in source synchronous mode Characteristics of the Deskew Circuit e Eliminate clock distribution delay by effectively adding one clock period delay Clocks are deskewed to within CLKOUT_PHASE specified in the Virtex 4 Data Sheet e Eliminate on chip as well as off chip clock delay e No restrictions on the delay in the feedback clock path e Requires a continuously running input clock e Adapts to a wide range of frequencies However once locked to a frequency large input frequency variations are not tolerated e Does not eliminate jitter The deskew circuit output jitter is the accumulation of input jitter and any added jitter value due to the deskew circuit e The co
232. an half the die All clock regions are 16 CLBs tall 8 CLBs up and 8 CLBs down Virtex 4 User Guide Center Column Logic Resources UG070_1_17_071304 Figure 1 17 Clock Regions www xilinx com 33 UG070 v1 5 March 21 2006 Chapter 1 Clock Resou rces Table 1 6 Virtex 4 Clock Regions Device Number of Clock Regions LX Family XCAVLX15 8 XCAVLX25 12 XC4VLX40 16 XCAVLX60 16 XC4VLX80 20 XCAVLX100 24 XC4VLX160 24 XC4VLX200 24 SX Family XCAVSX25 8 XCAVSX35 12 XCAVSX55 16 FX Family XCAVFX12 8 XCAVFX20 8 XC4VFX40 12 XCAVFX60 16 XC4VFX100 20 XCAVFX140 24 Regional Clocking Resources Regional clock networks are a set of clock networks independent of the global clock network Unlike global clocks the span of a regional clock signal is limited to three clock regions These networks are especially useful for source synchronous interface designs XILINX To understand how regional clocking works it is important to understand the signal path of a regional clock signal The Virtex 4 regional clocking resources and network consist of the following paths and components Clock Capable I O I O Clock Buffer BUFIO Regional Clock Buffer BUFR Regional Clock Nets 34 www xilinx com Virtex 4 User Guide UGO070 v1 5 March 21 2006 XILINX Regional Clocking Resources Clock Capable I O In a typical clock region there ar
233. ard requires a differential amplifier input buffer and a push pull output buffer HSTL I HSTL Ill HSTL 18 HSTL ll 18 Usage HSTL I uses Vcco 2 as a parallel termination voltage Vrr HSTL III uses Veco asa parallel termination voltage Vyr HSTL I and HSTL III are intended to be used in unidirectional links HSTL l DCI HSTL Ill DCI HSTL DCI 18 HSTL Ill DCI 18 Usage HSTL I DCI provides on chip split thevenin termination powered from V coo creating an equivalent parallel termination voltage Vy of Vcco5 2 HSTL I DCI and HSTL III DCI are intended to be used in unidirectional links HSTL ll HSTL IV HSTL Il 18 HSTL IV 18 Usage HSTL II uses Vcco 2 as a parallel termination voltage Vy HSTL IV uses Vcco asa parallel termination voltage Vr HSTL II and HSTL IV are intended to be used in bidirectional links HSTL ll DCI HSTL IV DCI HSTL Il DCI 18 HSTL IV DCI 18 Usage HSTL II DCI provides on chip split thevenin termination powered from Vcco creating an equivalent termination voltage of Vcco 2 HSTL_IV_ DCI provides single termination to Vcco Vrr HSTL II DCI and HSTL_IV_ DCI are intended to be used in bidirectional links DIFF HSTL l DIFF HSTL Il 18 Differential HSTL class II pairs complimentary single ended HSTL II type drivers with a differential receiver Differential HSTL Class II is intended to be used in bidirectional links Differential HSTL can also be used for differential clock and DQS signals in memor
234. are asynchronous Q output e Static length read operations are synchronous Q output e The data input has a setup to clock timing specification e Inacascadable configuration the Q15 output always contains the last bit value e The Q15 output changes synchronously after each shift operation Multiplexers Virtex 4 function generators and associated multiplexers can implement the following e 4 1 multiplexer in one slice e 8 1 multiplexer in two slices e 16 1 multiplexer in one CLB element 4 slices e 32 1 multiplexer in two CLB elements 8 slices 2 adjacent CLBs Wide input multiplexers are implemented in one level of logic or LUT and by dedicated MUXEFEX These multiplexers are fully combinatorial Each Virtex 4 slice has one MUXF5 multiplexer and one MUXFX multiplexer The MUXFX multiplexer implements the MUXF6 MUXF7 or MUXES according to the slice position in the CLB as shown in Figure 5 13 Each CLB element has two MUXF6 multiplexers one MUXF7 multiplexer and one MUXF8 multiplexer MUXFX are designed to allow LUT combinations of up to 16 LUTs in two adjacent CLBs Any LUT can implement a 2 1 multiplexer Examples of multiplexers are shown in the Designing Large Multiplexers section Virtex 4 User Guide www xilinx com 177 UGO070 v1 5 March 21 2006 Chapter 5 Configurable Logic Blocks CLBs XILINX MUXF8 combines SLICE S3 the two MUXF7 outputs Two CLBs MUXF6 combines the two MUXF5 S
235. arger devices have 32 clock inputs Table 1 1 summarizes the number of clock inputs available for different Virtex 4 devices Table 1 1 Number of Clock I O Inputs by Device Device Number of Clock I O Inputs XC4VLX15 XCAVLX25 16 XCAVSX25 XCAVSX35 XCAVFX12 XC4VFX20 XC4VEX40 XC4VEX60 XCAVLX40 XC4VLX60M XCAVLX80 XC4VLX100 32 XC4VLX160 XC4VLX200 XC4VSX55 XCAVFX1000 XCAVFX140 Notes 1 The XC4VLX40 and XC4VLX60 in the FF668 package only have 16 clock input pins 2 The XC4VFX100 in the FF1152 package only has 16 clock input pins Clock inputs can be configured for any I O standard including differential I O standards Each clock input can be either single ended or differential All 16 or 32 clock inputs can be differential if desired When used as outputs global clock input pins can be configured for any output standard except LVDS and HT output differential standards Each global clock input pin supports any single ended output standard or any CSE output differential standard www xilinx com Virtex 4 User Guide 20 UGO070 v1 5 March 21 2006 XILINX Global Clocking Resources Global Clock Input Buffer Primitives The primitives in Table 1 2 are different configurations of the input clock I O input buffer Table 1 2 Clock Buffer Primitives Primitive Input Output Description IBUFG I O Input clock buffer for single ended I O IBUFGDS I IB O Input clock buffer for differential I
236. associated with slices and configurable logic blocks CLBs The following sections correspond to specific switching characteristics sections in the Virtex 4 Data Sheet e General Slice Timing Model and Parameters CLB Switching Characteristics e Slice Distributed RAM Timing Model and Parameters Available in SLICEM only CLB Distributed RAM Switching Characteristics e Slice SRL Timing Model and Parameters Available in SLICEM only CLB SRL Switching Characteristics e Slice Carry Chain Timing Model and Parameters CLB Application Switching Characteristics www xilinx com 185 UGO070 v1 5 March 21 2006 Chapter 5 Configurable Logic Blocks CLBs XILINX General Slice Timing Model and Parameters A simplified Virtex 4 slice is shown in Figure 5 20 Some elements of the Virtex 4 slice are omitted for clarity Only the elements relevant to the timing paths described in this section are shown C gt FX FXINA MUXFX FXINB C gt cy LUT a Ya CO FF LAT CHE mm D inputs gt BY CF gt e C gt F5 Lo x LUT ir D Q Lo XQ inputs gt FF LAT BX gt CE D gt CLK LL 5 SR D gt UG070_5_20_071504 Figure 5 20 Simplified Virtex 4 General SliceL SliceM Timing Parameters Table 5 5 shows the general slice timing parameters for a majority of th
237. ation at any time When accessing the same memory location from both ports the user must however observe certain restrictions specified by the clock to clock set up time window There are two fundamentally different situations The two ports either have a common clock synchronous clocking or the clock frequency or phase is different for the two ports asynchronous clocking Virtex 4 User Guide www xilinx com 113 UG070 v1 5 March 21 2006 Chapter 4 Block RAM 114 XILINX Asynchronous Clocking Asynchronous clocking is the more general case where the active edges of both clocks do not occur simultaneously There are no timing constraints when both ports perform a read operation When one port performs a write operation the other port must not read or write access the same memory location by using a clock edge that falls within the specified forbidden clock to clock setup time window If this restriction is ignored a read operation could read unreliable data perhaps a mixture of old and new data in this location a write operation could result in wrong data stored in this location There is however no risk of physical damage to the device The clock to clock setup timing parameter is specified together with other block RAM switching characteristics in the Virtex 4 Data Sheet Synchronous Clocking Synchronous clocking is the special case where the active edges of both port clocks occur simultaneously Ther
238. atizable Block RAM Virtex 4 User Guide RAMB16 inst RAMB16 generic map DOA REG gt 0 Optional output registers on the A port 0 or 1 DOB REG gt 0 Optional output registers on the B port 0 or 1 INIT A gt X 000000000 Initial values on A output port INIT B gt X 000000000 Initial values on B output port INVERT CLK DOA REG gt FALSE Invert clock on A port output registers TRUE or FALSE Virtex 4 User Guide www xilinx com 125 UGO070 v1 5 March 21 2006 Chapter 4 Block RAM XILINX INVERT_CLK_DOB_REG gt FALSE Invert clock on B port output registers TRUE or FALSE RAM_EXTENSION_A gt NONE UPPER LOWER or NONE when cascaded RAM_EXTENSION_B gt NONE UPPER LOWER or NONE when cascaded READ_WIDTH_A gt 0 Valid values are 1 2 4 9 18 or 36 READ_WIDTH_B gt 0 Valid values are 1 2 4 9 18 or 36 SIM_COLLISION_CHECK gt ALL Collision check enable ALL WARNING_ONLY GENERATE_X_ONLY or NONE SRVAL_A gt X 000000000 Port A ouput value upon SSR assertion SRVAL_B gt X 000000000 Port B ouput value upon SSR assertion WRITE_MODE_A gt WRITE_FIRST WRITE_FIRST READ_FIRST or NO_CHANGE WRITE MODE B gt WRITE FIRST WRITE FIRST READ FIRST or NO CHANGE WRITE WIDTH A gt 2 Valid values are 1 2 4 9 18 or 36
239. ay from the F G inputs of the slice to Coy output of the lGANDCv output slice using FAND product Topcvr F G input to Cour Propagation delay from the F G input of the slice to Coyr output of the TopcvG output slice Topx F G input to Propagation delay from the F G inputs of the slice to XMUX YMUX Topy XMUX YMUX output output of the slice using XOR sum Setup Hold for Slice LUT Configured as Carry Chain Tyg Setup time before clock edge Tyxn Hold time after clock edge The following descriptions are for setup times only Temck TckciN Cry Data inputs DI Time before Clock CLK that data from the Cyy input of the slice must be stable at the D input of the slice sequential elements configured as a flip flop Figure 5 27 shows the worst case path Slice Carry Chain Timing Characteristics Figure 5 27 illustrates the timing characteristics of a slice carry chain implemented in a Virtex 4 slice 1 2 3 Lc ZR M GREC DP 2 l ToiNcK CIN DATA lnck SR Y N RESET YQ OUT ug070_5_27_080204 Figure 5 27 Slice Carry Chain Timing Characteristics e Attime Tcincx before clock event 1 data from Cyy input becomes valid high at the D input of the slice register This is reflected on either the XQ or YQ pin at time Toxo after clock event 1 Virtex 4 User Guide UG070 v1 5 March 21 2006 www xilinx com 197 Chapter 5 Config
240. be placed in the architecture body of the design code The instance name RAMB32 S64 ECC inst and or the port declarations after the gt assignment can be changed to properly connect this function to the design All inputs and outputs must be connected In addition to adding the instance declaration a use delaration statement for the UNISIM v components library needs to be added before the entity declaration This library contains the primitives and points to the models that will be used for component declarations for all Xilinx primitives simulation Copy the following two statements and paste them before the Entity declaration unless they already exists Library UNISIM use UNISIM vcomponents all Cut code below this line and paste into the architecture body gt RAMB32 564 ECC Virtex 4 512 x 64 Error Correction Block RAM Virtex 4 User Guide 160 www xilinx com Virtex 4 User Guide UGO070 v1 5 March 21 2006 XILINX Built in Block RAM Error Correction Code RAMB32 S64 ECC inst RAMB32 S64 ECC inst generic map DO REG gt 0 Optional output registers 0 or 1 SIM COLLISION CHECK ALL Collision check enable ALL WARNING ONLY GENERATE X ONLY or NONE port map DO DO 64 bit output data STATUS gt STATUS 2 bit status output DI DI 64 bit data input RDAD
241. ble 9 14 and Table 9 15 Changes to the entire System Monitor Calibration System Monitor VHDL and Verilog Design Example sections 02 01 05 1 2 In Chapter 1 revised Global Clock Buffers Clock Regions and Clock Capable I O sections In Chapter 4 Block RAM revised Reset page 143 description and Table 4 13 In Chapter 6 SelectIO Resources removed the device configuration section The Virtex 4 Configuration Guide describes this information in detail Edited SSTL Stub Series Terminated Logic page 268 Replaced LVDS_25_DCI with LVDCI_25 in Compatible example page 286 Added rule 7 to DCI in Virtex 4 Hardware page 225 Added Simultaneous Switching Output Limits page 295 Removed Chapter 9 System Monitor 04 11 05 1 3 Chapter 1 Revised Table 1 1 page 20 Figure 1 14 and BUFR Attributes and Modes section including Figure 1 21 page 38 Chapter 2 Revised FACTORY_JF value in Table 2 7 page 65 Added Phase Shift Overflow section Clarified global clock discussion in Global Clock Buffers Clock Regions and Clock Capable I O Chapter 4 Added Built in Block RAM Error Correction Code section Revised Figure 4 6 and Figure 4 8 page 118 Chapter 5 Revised Table 5 1 and Table 5 2 page 165 Chapter 6 Revised Table 6 29 page 278 Chapter 7 Revised REFCLK Reference Clock and added Table 7 10 page 331
242. bmodules leeeeeeeeeeeeee ene 212 Chapter 6 SelectlO Resources I O Tile Overview ssssssssss ess I e 215 SelectIO Resources Introduction 00 cece eee eese 216 SelectIO Resources General Guidelines 0 cece eee eee 216 Virtex 4 I O Bank Rules 2 0 cc RR RR RR en 216 9 9 V I O SUDDORU do edet bead oud ee names eg ere igiene a ded beca a aiee 217 Reference Voltage Vggg Pins 2 e 217 Output Drive Source Voltage Vcco Pins ce eee 217 Virtex 4 Digitally Controlled Impedance DCI 00000000 218 Introd ction en veh ete e dor eee Recette pe RR eben eed and 218 Xiltnx DEL env ac cases pte yy eve OR EY ACPA e CERA Hee de ie eed 218 Controlled Impedance Driver Source Termination leeeeeeeees 219 Controlled Impedance Driver with Half Impedance Source Termination 220 Input Termination to VCCO Single Termination sees 220 Input Termination to VCCO 2 Split Termination eese 221 Driver with Termination to Vcco Single Termination sees 222 Driver with Termination to Vcco 2 Split Termination 223 DCIdiVirtex 4 Hardware eus tod een ttes eg did etel ia E eiad 225 DCI Usage Examples priores praeerant e t Pie et Paten draaid tena 226 Virtex 4 SelectIO Primitives lsusuesessssssssseesss ee 228 IBUF and IBUFG eres ER RR rr egre an REY RU CR oe ae oec es 229 2 0 ge cU 229 9101 9 UT 230
243. c Reconfiguration chapter of the Virtex 4 Configuration Guide for more information If the dynamic reconfiguration port is not used using DCM_BASE or DCM_PS instead of DCM ADV is strongly recommended Table 2 5 DCM Status Mapping to DO Bus DO Bit Status Description DO 0 Phase shift overflow Asserted when the DCM is phase shifted beyond the allowed phase shift value or when the absolute delay range of the phase shift delay line is exceeded DO 1 CLKIN stopped Asserted when the input clock is stopped CLKIN remains High or Low for one or more clock cycles When CLKIN is stopped the DO 1 CLKIN stopped status will assert within nine CLKIN cycles When CLKIN is restarted CLKO will start toggling and DO 1 will deassert within nine clock cycles DO 2 CLKFX stopped Asserted when CLKFX stops The DO 2 CLKFX stopped status will assert within 257 to 260 CLKIN cycles after CLKFX stopped CLKFX will not resume and DO 2 will not deassert until the DCM is reset DO 3 CLKFB stopped Asserted when the feedback clock is stopped CLKFB remains High or Low for one or more clock cycles The DO 3 CLKFB stopped status will assert within six CLKIN cycles after CLKFB is stopped CLKPB stopped will deassert within six CLKIN cycles when CLKFB resumes after being stopped momentarily An occasionally skipped CLKFB will not affect the DCM operation However stopping CLKFB for a long time can result in the DCM losing LOCKED When LOCKED is lost
244. can be synchronous or asynchronous Virtex 4 devices can set INITO and INIT1 independent of SRHIGH and SRLOW 168 www xilinx com Virtex 4 User Guide UGO070 v1 5 March 21 2006 2 XILINX CLB Overview LUT G Output Attribute INIT1 INITO SRHIGH SRLOW BY D gt d e LUT F Output gt XQ CEC B Attribute INIT1 CLK coo INITO 7 SRHIGH SR Cc SRLOW Reset Type BX mH SYNC ASYNC ug070 5 04 071504 Figure 5 4 Register Latch Configuration in a Slice The configuration options for the set and reset functionality of a register or a latch are as follows No set or reset Synchronous set Synchronous reset Synchronous set and reset Asynchronous set preset Asynchronous reset clear Asynchronous set and reset preset and clear Distributed RAM and Memory Available in SLICEM only Multiple left hand LUTs in SLICEMs can be combined in various ways to store larger amounts of data The function generators LUTs in SLICEM can be implemented as a 16 x 1 bit synchronous RAM resource called a distributed RAM element RAM elements are configurable within a CLB to implement the following Single Port 16 x 4 bit RAM Single Port 32 x 2 bit RAM Single Port 64 x 1 bit RAM Dual Port 16 x 2 bit RAM Distributed RAM modules are synchronous write resources A synchronous read can be implemented with a storage element
245. chronous with PSCLK The PSINCDEC input signal is used to increment or decrement the phase shift factor when PSEN is activated As a result the output clocks will be shifted The PSINCDEC signal is asserted High for increment or deasserted Low for decrement This input must be tied to ground when the CLKOUT_PHASE_SHIFT attribute is set to NONE or FIXED Phase Shift Enable Input PSEN The phase shift enable PSEN input signal must be synchronous with PSCLK A variable phase shift operation is initiated by the PSEN input signal It must be activated for one period of PSCLK After PSEN is initiated the phase change is gradual with completion indicated by a High pulse on PSDONE There are no sporadic changes or glitches on any output during the phase transition From the time PSEN is enabled until PSDONE is flagged the DCM output clock moves bit by bit from its original phase shift to the target phase shift The phase shift is complete when PSDONE is flagged PSEN must be tied to ground when the CLKOUT_PHASE_SHIFT attribute is set to NONE or FIXED Figure 2 6 shows the timing for this input Dynamic Reconfiguration Data Input DI 15 0 The dynamic reconfiguration data DI input bus provides reconfiguration data for dynamic reconfiguration When not used all bits must be assigned zeros See the Dynamic Reconfiguration chapter of the Virtex 4 Configuration Guide for more information Dynamic Reconfiguration Address Input DADDR 6 0 The dy
246. ck Input Ports serine mentina edie Ph edie Ra tear estet eerie desta 56 Source Clock Input CLKIN eeseeeeeeeeeee mh rn 56 Feedback Clock Input CLKFB 1 ee eee eens 56 Phase Shift Clock Input PSCLK 0 6 e 57 Dynamic Reconfiguration Clock Input DCLK 0 0 0 6 cece ee eee 57 Control and Data Input Ports 0 0 06 58 Reset Input RST scr cc se datra ee pex er eae diesel hy aue e e due E Ree eels Beale wine da 58 Phase Shift Increment Decrement Input PSINCDEC 00 00 c ee eee 58 Phase Shift Enable Input PSEN 0 ccc rn 58 Dynamic Reconfiguration Data Input DI 15 0 0 0 ee eee 58 Dynamic Reconfiguration Address Input DADDR 6 0 00000 58 Dynamic Reconfiguration Write Enable Input DWE 0 0000 c eee eens 59 Dynamic Reconfiguration Enable Input DEN 6 2 6 6c cece ee eee 59 Clock Output Ports roret ae iia eat Hee elk 59 Tx Output Clock CEKO o nodes ertt glare tte edited eee etd cdi 59 1x Output Clock 90 PhaseShift CLK90 csse 59 1x Output Clock 180 Phase Shift CLK180 sisse 59 1x Output Clock 270 Phase Shift CLK270 c l 59 2x Output Glock CE K2X err eC Reb a e E ete end aniseed c tease due 59 2x Output Clock 180 Phase Shift CLK2X180 lessen 60 Frequency Divide Output Clock CLKDV sssseeeeeeeee ee 60 Frequency Synthesis Output Clock CLKFX 2 6 cece een 60 Frequency S
247. clock enable signal becomes a valid high The ISERDES can begin sampling data starting on the first clock edge after the CLKDIV rising edge CLK Event 1 e At time T spcK_p before CLK event 1 the input data becomes valid at the ISERDES D input pin For 8 1 SERDES the eighth data on the bus is sampled at CLK event 2 This process is repeated for subsequent incoming data CLKDIV Event 2 e At time Trscko Qo after CLKDIV event 2 two CLKDIV cycles after the first data is sampled into ISERDES the data appears on the D1 D8 bus Reset Event 1 At Reset event 1 the O1 to Q6 outputs asynchronously become zero ISERDES VHDL and Verilog Instantiation Template VHDL and Verilog instantiation templates are available in the Libraries Guide for all primitives and submodules In VHDL each template has a component declaration section and an architecture section Each part of the template should be inserted within the VHDL design file The port map of the architecture section should include the design signal names ISERDES VHDL Instantiation Module ISERDES Description VHDL instantiation template Device Virtex 4 Family Component Declaration for ISERDES should be placed 368 www xilinx com Virtex 4 User Guide UG070 v1 5 March 21 2006 X XILINX Input Serial to Parallel Logic Resources ISERDES after architecture statement but before begin keyword component ISERDES synthesis translat
248. compliance with many industry standards Chapter 7 describes the register structures dedicated for sending and receiving SDR or DDR data This chapter covers additional new Virtex 4 resources Input serial to parallel converters ISERDES and output parallel to series converters OSERDES support very fast I O data rates and allow the internal logic to run up to ten times slower than the I O The Bitslip sub module can re align data to word boundaries detected with the help of a training pattern Input Serial to Parallel Logic Resources ISERDES The Virtex 4 ISERDES is a dedicated serial to parallel converter with specific clocking and logic features designed to facilitate the implementation of high speed source synchronous applications The ISERDES avoids the additional timing complexities encountered when designing deserializers in the FPGA fabric ISERDES features include Virtex 4 User Guide UGO070 v1 5 March 21 2006 Dedicated Deserializer Serial to Parallel Converter The ISERDES deserializer enables high speed data transfer without requiring the FPGA fabric to match the input data frequency This converter supports both single data rate SDR and double data rate DDR modes In SDR mode the serial to parallel converter creates a 2 3 4 5 6 7 or 8 bit wide parallel word In DDR mode the serial to parallel converter creates a 4 6 8 or 10 bit wide parallel word Digitally Controlled Delay Element
249. correction code ECC configuration option is available with almost all block RAM pairs as long as the lower RAM is instantiated in an even numbered row However the ECC configuration cannot use the one block RAM immediately above or below the Virtex 4 PowerPC 405 blocks The functionality of the block RAM is changed when using the ECC mode e The two block RAM ports still have independent address clocks and enable inputs but one port is a dedicated write port and the other is a dedicated read port e DO represents the read data after correction e DO stays valid until the next active read operation e Simultaneous reading and writing even with asynchronous clocks is allowed but requires careful clock timing if read and write addresses are identical e The READ FIRST or WRITE FIRST modes of the normal block RAM operation are not applicable to the ECC configuration www xilinx com 157 UGO070 v1 5 March 21 2006 Chapter 4 Block RAM XILINX Top Level View of the Block RAM ECC Architecture Figure 4 24 shows the top level view of a Virtex 4 block RAM in ECC mode RDADDR 8 0 BRAM 64 bit 512 x 36 64 ECC DI 63 0 Encode 64 DO 63 0 Decode Data Out STATUS 1 0 E Correct rdaddr WRADDR 8 0 wradar ug070 4 ECC1 030705 Figure 4 24 Top Level View of Block RAM ECC Block RAM ECC Primitive Figure 4 25 shows RAMB32 564 ECC the block RAM ECC primitive RAMB32 S64 ECC DI lt 63 0 gt DO lt 63 0 g
250. cription Verilog instantiation template Cascadable 16 bit Shift Register with Clock Enable Device Virtex 4 Family SRLC16E defparam SRLC16E U_SRLC16E D js Multiplexer Primitives and Verilog VHDL Examples This section provides generic VHDL and Verilog reference code implementing multiplexers These submodules are built from LUTs and the dedicated MUXF5 MUXF6 MUXF7 and MUXF8 multiplexers To automatically generate large multiplexers using these dedicated elements use the CORE Generator Bit Multiplexer and Bus Multiplexer modules For applications such as comparators encoder decoders or case statement in VHDL or Verilog these resources offer an optimal solution Multiplexer Primitives and Submodules Four primitives are available for access to the dedicated MUXFX in each slice In the example shown in Table 5 16 MUXF7 is available only in slice S2 Table 5 16 MUXFX Resources Primitive Slice Control Input Output MUXF5 S0 S1 S2 S3 S 10 I1 O MUXF6 S0 S1 S 10 I1 O MUXF7 S2 S I0 I1 O MUXF8 S3 S 10 I1 O In addition to the primitives five submodules to implement multiplexers from 2 1 to 32 1 are provided in VHDL and Verilog code Synthesis tools can automatically infer these primitives MUXF5 MUXF6 MUXF7 and MUXF8 however the submodules described in this section use instantiation of the new MUXFX to guarantee an optimized result Table 5 17 lists avail
251. d voltage lOStandard SF363 and FFG68 Packages 3 3V LVCMOS33_2_slow 68 LVCMOS33_4_slow 41 LVCMOS33_6_slow 29 LVCMOS33_8_slow 22 LVCMOS33_12_slow 15 LVCMOS33_16_slow 11 LVCMOS33_24_slow 7 LVCMOS33 2 fast 40 LVCMOS33 4 fast 24 LVCMOS33 6 fast 17 LVCMOS33 8 fast 13 LVCMOS33 12 fast 10 LVCMOS33 16 fast 8 LVCMOS33 24 fast 5 LVDCI 3350 Q 13 HSLVDCI 33 50 Q 13 LVTIL2 slow 68 LVTILA slow 41 LVTTL6 slow 29 LVTTL8_slow 22 LVTTL12_slow 15 LVTTL16_slow 11 LVTTL24_slow 7 LVTTL2_fast 40 LVTTL4_fast 24 LVTTL6_fast 17 LVTTL8_fast 13 LVTTL12_fast 10 LVTTL16_fast 8 LVTTL24_fast 5 PCI33 3 PCI66 3 PCIX 9 Virtex 4 User Guide www Xilinx com 301 UGO070 v1 5 March 21 2006 Chapter 6 SelectlO Resources XILINX Table 6 42 Non Sparse Chevron Simultaneously Switching Output Limits per Equivalent Vcco GND Pair Continued Votage fOSundad EE 3 3V GTL 4 GTL_DCI 4 GTLP 4 GTLP_DCI 4 Equivalent Vcco GND Pairs Non Sparse Chevron Since ground pins and Vcco pins are connected to common structures inside the package the number of effective Vcco GND pin pairs in a bank can differ from the number of physical Vcco GND pin pairs Table 6 43 shows the number of equivalent Veco GND pin pairs in each bank of each non sparse chevron package Some of the numbers are not integers as these banks share GND pins with other
252. d Average Calculation of S80 304 Calculation of Full Device SSO eeseeeeeeeee eh 306 Full Device SSO Example 5 eer boas enc geen bale au erp eis 306 Full Device SSO Calculator 0 0 0 0 cee tence n 307 Other SSO Assumptions isses en 308 LVDCI and HSLVDCI Drivers irsi rusiya etek e E e O 308 Bank MR CCP Lc 308 Chapter 7 SelectlO Logic Resources Introduction Libere EO UE du ERE RE adea Es 309 IEOGIC Reso xces LuLerrIRRRRD RR ERBEN IRR ERE RE Le RR enia ded 309 Combinatorial Input Path 0 0 nee eee 311 Input DDR Overview IDDR 0 0 ccc ccc cece eee eee 311 OPPOSITE EDGE Mode 0 0 ccc cc e e c re 312 SAME EDGE Mode 0 ccc ee eee ee e c ren 313 SAME EDGE PIPELINED Mode 0 0 ccc cece e 314 Input DDR Primitive DDR sese 315 IDDR VHDL and Verilog Templates lssssseeeeeeeeeeeee 316 IDDR VHDL Template ei Ryu E dere de et deir needles 316 IDDR Verilog Template cs pg eioi eaa oane ioina m n 317 ILOGIC Timing Models 0 5 2 ss004 cee s0o b e 9 e eO RR 318 ILOGIC Timing Characteristics 6 0 nn 318 ILOGIC Timing Characteristics DDR 1 ete eee 318 Input Delay Element IDELAY sssssseeeee III 321 IDELAY Primitives iyasa eiaa Rb Ro Rc RR e Rr e RU 321 TIDEL AY POE 2d P Ren d hele buh co ce t eng e btt cR trea a e 322 IDELAY Attrib tes 2 ibo eh Rc e eae ec ea ge eed e es 323 IDBEAX TINING uei eroe erp edere eer E tee
253. e OBUFDS O l o utput to Device Pads Input from FPGA OB ug070_6_22_071904 Figure 6 22 Differential Output Buffer Primitive OBUFDS OBUFTDS Figure 6 23 shows the differential 3 state output buffer primitive OBUFTDS 3 state Input o Output to Device Pads Input from FPGA OB ug070_6_23_071904 Figure 6 23 Differential 3 state Output Buffer Primitive OBUFTDS IOBUFDS Figure 6 24 shows the differential input output buffer primitive IOBUFDS T 3 state Input 1io 1O Input to from from FPGA 6 lonl device pad O Output to FPGA ug070_6_24_071904 Figure 6 24 Differential Input Output Buffer Primitive IOBUFDS Virtex 4 User Guide www xilinx com 231 UG070 v1 5 March 21 2006 Chapter 6 SelectlO Resources XILINX Virtex 4 SelectlO Attributes Constraints Access to some Virtex 4 I O resource features e g location constraints input delay output drive strength and slew rate is available through the attributes constraints associated with these features For more information a Constraints Guide is available on the Xilinx web site with syntax examples and VHDL Verilog reference code This guide is available inside the Software Manuals at http www support xilinx com support software manuals htm Location Constraints The location constraint LOC must be used to specify the I O location of an instantiated I O primitive T
254. e The SRVAL single port or SRVAL_A and SRVAL B dual port attributes define output latch values when the SSR input is asserted The width of the SRVAL SRVAL A and SRVAL B attribute is the port width as shown in Table 4 5 These attributes are hex encoded bit vectors and the default value is 0 This attribute is not available when the optional output register attribute is set www xilinx com 123 UGO070 v1 5 March 21 2006 Chapter 4 Block RAM XILINX 124 Table 4 5 Port Width Values Port Data Width DOP Bus DO Bus INIT SRVAL 1 NA lt 0 gt 1 2 NA lt 1 0 gt 2 4 NA lt 3 0 gt 4 9 lt 0 gt lt 7 0 gt 1 8 9 18 lt 1 0 gt lt 15 0 gt 2 16 18 36 lt 3 0 gt lt 31 0 gt 4 32 36 Optional Output Register On Off Switch DO A B REG This attribute sets the number of pipeline register at A B output of RAMB16 The valid values are 0 default or 1 Clock Inversion at Output Register Switch INVERT CLK DO A B REG When set to TRUE the clock input to the pipeline register at A B output of RAMB16 is inverted The default value is FALSE Extended Mode Address Determinant RAM EXTENSION AJB This attribute determines whether the block RAM of interest has its A B port as UPPER LOWER address when using the cascade mode Refer to the Cascadable Block RAM section When the block RAM is not used in cascade mode the default value is NONE Read Width READ WIDTH A B
255. e After a reset the DCM samples several thousand clock cycles to achieve lock After the DCM achieves lock the LOCKED signal is asserted High The DCM timing parameters section of the Virtex 4 Data Sheet provides estimates for locking times To guarantee an established system clock at the end of the start up cycle the DCM can delay the completion of the device configuration process until after the DCM is locked The STARTUP WAIT attribute activates this feature The STARTUP WAIT Attribute description provides further information Until the LOCKED signal is asserted High the DCM output clocks are not valid and can exhibit glitches spikes or other spurious movement In particular the CLK2X output appears as a 1x clock with a 25 75 duty cycle Phase Shift Done Output PSDONE The phase shift done PSDONE output signal is synchronous to PSCLK At the completion of the requested phase shift PSDONE pulses High for one period of PSCLK This signal also indicates a new change to the phase shift can be initiated The PSDONE output signal is not valid if the phase shift feature is not being used or is in fixed mode 60 www xilinx com Virtex 4 User Guide UGO070 v1 5 March 21 2006 XILINX DCM Ports Status or Dynamic Reconfiguration Data Output DO 15 0 The DO output bus provides DCM status or data output when using dynamic reconfiguration Table 2 5 Further information on using DO as the data output is available in the Dynami
256. e stopped during a Low or a High phase and must be restored with the same input clock period frequency During this time LOCKED stays High and remains High when the clock is restored Thus a High on LOCKED does not necessarily mean that a valid clock is available When stopping the input clock CLKIN remains High or Low for one or more clock cycles one to nine more output clock cycles are still generated as the delay line is flushed When the output clock stops the CLKIN stopped DO 1 signal is asserted When the clock is restarted the output clock cycles are not generated for one to eight clocks while the delay line is filled Similarly the DO 1 signal is deasserted once the output clock is generated The most common case is two or three clocks CLKIN can be restarted with any phase relationship to the previous clock If the frequency has changed the DCM requires a reset The DO 1 is forced Low whenever LOCKED is Low When the DCM is in the locking process DO 1 status is held Low until LOCKED is achieved 68 www xilinx com Virtex 4 User Guide UGO070 v1 5 March 21 2006 XILINX DCM Design Guidelines Output Clocks Any or all of the DCM s nine clock outputs can be used to drive a global clock network The fully buffered global clock distribution network minimizes clock skew caused by loading differences By monitoring a sample of the output clock CLKO the deskew circuit compensates for the delay on the routing network ef
257. e Virtex 4 Configuration Guide for more information Virtex 4 User Guide www xilinx com 57 UGO070 v1 5 March 21 2006 Chapter 2 Digital Clock Managers DCMs XILINX 58 Control and Data Input Ports Reset Input RST The reset RST input pin resets the DCM circuitry The RST signal is an active High asynchronous reset Asserting the RST signal asynchronously forces all DCM outputs Low the LOCKED signal all status signals and all output clocks after some propagation delay When the reset is asserted the last cycle of the clocks can exhibit a short pulse and a severely distorted duty cycle or no longer be deskewed with respect to one another while deasserting Low Deasserting the RST signal starts the locking process at the next CLKIN cycle To ensure a proper DCM reset and locking process the RST signal must be held until the CLKIN and CLKEFB signals are present and stable for at least three clock cycles The time it takes for the DCM to lock after a reset is specified in the Virtex 4 Data Sheet as LOCK_DLL for a DLL output and LOCK_FX for a DFS output These are the CLK and CLKFX outputs described in Clock Output Ports The DCM locks faster at higher frequencies The worse case numbers are specified in the Virtex 4 Data Sheet In all designs the DCM must be held in reset until CLKIN is stable Phase Shift Increment Decrement Input PSINCDEC The phase shift increment decrement PSINCDEC input signal must be syn
258. e are no timing constraints when both ports perform a read operation When one port performs a write operation the other port must not write into the same location unless both ports write identical data When one port performs a write operation the other port can reliably read data from the same location if the write port is in READ_FIRST mode DATA_OUT will then reflect the previously stored data If the write port is in either WRITE_FIRST or in NO_CHANGE mode then the DATA OUT on the read port would become invalid unreliable Obviously the mode setting of the read port does not affect this operation www xilinx com Virtex 4 User Guide UG070 v1 5 March 21 2006 XILINX Additional Block RAM Features in Virtex 4 Devices Additional Block RAM Features in Virtex 4 Devices Optional Output Registers Address Register Memory D Q DI Array Latches The optional output registers improve design performance e by eliminating routing delay to the CLB flip flops for pipelined operation These output registers have programmable clock inversion as in CLB flip flops An independent cloc k enable input is provided for these output registers As a result the output data registers hold the value independent of the input register operation Figure 4 5 shows the optional output register common to both ports Write IL Strobe Read Strobe Latch JL Enable L D Q Register
259. e desired values and the LOCKED signal is asserted 1 2 cw T A E a el eed Ld L4 1l RST aeos L ae A E e a a LT LS eoo tt E T ee ee cd AES exe Lif lifr bi ti PLS LI LE cxx FLTLFLELEL i LLL LL Pe RSRSASRS PUP OO _ e exe ee Leet qz T1 r o ERR LOCKED LL Tq DLL ug070 2 19 083105 Figure 2 19 RESET LOCK Example e Prior to Clock Event 1 Prior to clock event 1 the DCM is locked All clock outputs are in phase with the correct frequency and behavior e Clock Event 1 Some time after clock event 1 the reset signal is asserted at the RST pin While reset is asserted all clock outputs become a logic zero The reset signal is an asynchronous reset Note the diagram is not shown to scale For the DCM to operate properly the reset signal must be asserted for at least three CLKIN periods e Clock Event 2 Clock event 2 occurs a few cycles after reset is asserted and deasserted At clock event 2 the lock process begins At time LOCK_DLL after clock event 2 if no fixed phase 88 www xilinx com Virtex 4 User Guide UG070 v1 5 March 21 2006 XILINX DCM Timing Models shift was selected then all clock outputs are stable and in phase LOCKED is also asserted to signal completion Fixed Phase Shifting In Figure 2 20 the DCM outputs the correct frequency However the clock outputs are not in phase with the desired clock phase The clock outputs ar
260. e inputs See Clock Enable Inputs CE1 and CE2 CE2 CLK Input 1 High speed clock input Clocks serial input data stream See High Speed Clock Input CLK CLKDIV Input 1 Divided clock input Clocks delay element deserialized data Bitslip sub module and CE unit See Divided Clock Input CLKDIV Virtex 4 User Guide www xilinx com 357 UGO070 v1 5 March 21 2006 Chapter 8 Advanced SelectlO Logic Resources XILINX Table 8 1 ISERDES Port List and Definitions Continued Port Name Type Width Description D Input 1 Serial input data from IOB See Serial Input Data from IOB D DLYCE Input 1 Enable IDELAY increment decrement function The DLYCE port is the same as the CE port in the IDELAY primitive See IDELAY Ports DLYINC Input 1 Increment decrement number of tap delays in IDELAY The DLYINC port is the same as the INC port in the IDELAY primitive See IDELAY Ports DLYRST Input 1 Reset IDELAY to pre programmed value If no value programmed reset to 0 The DLYRST port is the same as the RST port in the IDELAY primitive See IDELAY Ports OCLK Input 1 High speed clock input for memory applications See High Speed Clock for Strobe Based Memory Interfaces OCLK REV Input 1 Reverse SR pin Not available in the ISERDES block SHIFTIN1 Input 1 Carry input for data width expansion Connect to SHIFTOUT1 of master IOB See ISERDES W
261. e must be set to an integer value to produce a CLKDV output with a 50 50 duty cycle For non integer CLKDV DIVIDE values the CLKDV output duty cycle is shown in Table 2 6 Table 2 6 Non Integer CLKDV DIVIDE CLKDV Duty Cycle in CLKDV DIVIDE Value High Frequency Mode High Pulse Low Pulse Value 1 5 1 3 2 5 2 5 3 5 3 7 4 5 4 9 5 5 5 11 6 5 6 13 7 5 7 15 CLKFX MULTIPLY and CLKFX DIVIDE Attribute The CLKFX MULTIPLY attribute sets the multiply value M of the CLKFX output The CLKFX DIVIDE attribute sets the divisor D value of the CLKFX output Both control the CLKFX output making the CLKFX frequency equal the effective CLKIN source clock frequency multiplied by M D The possible values for M are any integer from two to 32 The possible values for D are any integer from one to 32 The default settings are M 4 and D 1 CLKIN_PERIOD Attribute The CLKIN_PERIOD attribute specifies the source clock period in nanoseconds The default value is 0 0 ns 62 www xilinx com Virtex 4 User Guide UG070 v1 5 March 21 2006 XILINX DCM Attributes CLKIN DIVIDE BY 2 Attribute The CLKIN DIVIDE BY 2 attribute is used to enable a toggle flip flop in the input clock path to the DCM When set to False the effective CLKIN frequency of the DCM equals the source clock frequency driving the CLKIN input When set to True the CLKIN frequency is divided by two before it reaches the rest of the DCM Thus
262. e paths in Figure 5 20 Table 5 5 General Slice Timing Parameters Parameter Function Description Combinatorial Delays Tito F G inputs to X Y outputs Propagation delay from the F G inputs of the slice through the look up tables LUTs to the X Y outputs of the slice Tips F G inputs to F5 output Propagation delay from the F G inputs of the slice through the LUTs and MUXF5 to the F5 output of the slice Tripsx F G inputs to XMUX Propagation delay from the F G inputs of the slice through the output LUTs and MUXFS to the XMUX output of the slice 186 www xilinx com Virtex 4 User Guide UG070 v1 5 March 21 2006 XILINX CLB Slice Timing Models Table 5 5 General Slice Timing Parameters Continued Parameter Function Description Tir6y FxquA Pxiv inputs to Propagation delay from the FyryA Fxmpg inputs through FEMUX YMUX output to the YMUX output of the slice Trnarx Trnpex Fxoina F xine inputs to FX Propagation delay from the Fxrna Fxmpg inputs through FEMUX output to the FX output of the slice Sequential Delay s Tcko FF Clock CLK to XO YO Time after the clock that data is stable at the XQ YQ outputs of outputs the slice sequential elements configured as a flip flop TCKLO Latch Clock CLK to Time after the clock that data is stable at the XQ YQ outputs of XQ YQ outputs the slice sequential elements configured as a latch Setup and Hold for Sl
263. e phase shifted to appear sometime later than the input clock and the LOCKED signal is asserted 1 a 11 d co 1 Ll F cudgos 0101 CLK2X Lock Ti LOCKED ug070 2 20 083105 Figure 2 20 Phase Shift Example Fixed e Clock Event 1 Clock event 1 appears after the desired phase shifts are applied to the DCM In this example the shifts are positive shifts CLKO and CLK2X are no longer aligned to CLKIN However CLKO and CLK2X are aligned to each other while CLK90 and CLK180 remain as 90 and 180 versions of CLKO The LOCK signal is also asserted once the clock outputs are ready Virtex 4 User Guide www xilinx com 89 UGO070 v1 5 March 21 2006 Chapter 2 Digital Clock Managers DCMs XILINX Variable Phase Shifting In Figure 2 21 the CLKO output is phase shifted using the dynamic phase shift adjustments in the synchronous user interface The PSDONE signal is asserted for one cycle when the DCM completes one phase adjustment After PSDONE is deasserted PSEN can be asserted again allowing an additional phase shift to occur As shown in Figure 2 21 all the variable phase shift control and status signals are synchronous to the rising edge of PSCLK ae 1 FUL Led LL ceo li LJ L MiLo J L 2 1 T PSCLK PSEN gt TpMCCK PSEN D e _ PSDONE Toucco Pspone l TDMCCK_PSINCDEC PSINC
264. e rising edges and falling edges of C as well as meeting the register setup time relative to both clock edges e At time Torck before Clock Event 1 rising edge of C the 3 state signal T1 becomes valid high at the T1 input of 3 state register 1 and is reflected on the TQ output at time Tock after Clock Event 1 Clock Event 2 e At time Torck before Clock Event 2 falling edge of C the 3 state signal T2 becomes valid high at the T2 input of 3 state register 2 and is reflected on the TQ output at time Tocko after Clock Event 2 no change at the TQ output in this case Clock Event 9 e Attime Tosgcy before Clock Event 9 rising edge of C the SR signal configured as synchronous reset in this case becomes valid high resetting 3 state Register 1 reflected at the TO output at time Tg after Clock Event 9 no change at the TO output in this case and resetting 3 state Register 2 reflected at the TQ output at time Trg after Clock Event 10 no change at the TO output in this case Virtex 4 User Guide www xilinx com 353 UGO070 v1 5 March 21 2006 Chapter 7 SelectlO Logic Resources XILINX 354 www xilinx com Virtex 4 User Guide UG070 v1 5 March 21 2006 lt XILINX Chapter 6 Advanced SelectIO Logic Resources Introduction The Virtex 4 I O functionality is described in Chapter 6 through Chapter 8 of this user guide Chapter 6 covers the electrical characteristics of input receivers and output drivers and their
265. e stable at the ADDR inputs of the block RAM TRDCK_DI Time before the clock that data must be stable at the DI inputs of the block RAM Data inputs DI TRCKD_DI Time after the clock that data must be stable at the DI inputs of the block RAM Tncck EN Time before the clock that the enable signal must be stable at the EN input of the block RAM Enable EN Tnckc EN Time after the clock that the enable signal must be stable at the EN input of the block RAM TRCCK SSR Time before the clock that the synchronous set reset signal must Synchronous be stable at the SSR input of the block RAM SSR TRCKC SSR Set Reset Time after the clock that the synchronous set reset signal must be stable at the SSR input of the block RAM TRCCK_WEN Time before the clock that the write enable signal must be stable at the WEN input of the block RAM Write Enable WEN TRCKC_WEN Time after the clock that the write enable signal must be stable at the WEN input of the block RAM TRCCK_REGCE Time before the clock that the register enable signal must be Optional Output BH stable at the REGCE input of the block RAM TnCKC REGCE Register Enable Time after the clock that the register enable signal must be stable at the REGCE input of the block RAM Sequential Delays TRCKO_DO Clock to Output CLK to Time after the clock that the output data is stable at the DO Max DO outputs of the block RAM without output register TRCKO_DO Clock to Output CLK to Time after the clock that
266. e two clock capable I O pin pairs there are exceptions in the center column Clock capable I O pairs are regular I O pairs where the LVDS output drivers have been removed to reduce the input capacitance All global clock inputs are clock capable I Os i e they do not have LVDS output drivers There are four dedicated clock capable I O sites in every bank When used as clock inputs clock capable pins can drive BUFIO and BUFR They can not directly connect to the global clock buffers When used as single ended clock pins then as described in Global Clock Buffers the P side of the pin pair must be used because a direct connection only exists on this pin I O Clock Buffer BUFIO The I O clock buffer BUFIO is a new clock buffer available in Virtex 4 devices The BUFIO drives a dedicated clock net within the I O column independent of the global clock resources Thus BUFIOs are ideally suited for source synchronous data capture forwarded receiver clock distribution BUFIOs can only be driven by clock capable I Os located in the same clock region BUFIOs can drive the two adjacent I O clock nets for a total of up to three clock regions as well as the regional clock buffers BUFR BUFIOs cannot drive logic resources CLB block RAM etc because the I O clock network only reaches the I O column BUFIO Primitive BUFIO is simply a clock in clock out buffer There is a phase delay between input and output Figure 1 18 shows the BUFIO
267. e use conditions specified by the user Virtex 4 User Guide www xilinx com 249 UGO070 v1 5 March 21 2006 Chapter 6 SelectlO Resources XILINX HSTL Class ll Figure 6 40 shows a sample circuit illustrating a valid termination technique for HSTL Class II 1 5V with unidirectional termination External Termination IOB Vr 0 75V Vr ON saan EE IOB HSTL Il Rp T a Legere DCI IOB IOB 2Rypp 2Zo 1002 2Rygp 2Zo 1002 MST ies HSTL_II_DCI 09 aH Vngr 0 75V 2Rvan 2Zo 1000 E 2Rygw 2Zo 1000 L ug070 6 38 071904 Figure 6 40 HSTL 1 5V Class Il Unidirectional Termination Figure 6 41 shows a sample circuit illustrating a valid termination technique for HSTL Class II 1 5V with bidirectional termination 250 www xilinx com Virtex 4 User Guide UG070 v1 5 March 21 2006 XILINX Specific Guidelines for Virtex 4 I O Supported Standards External Termination Ten Vr 0 75V Vtr 0 75V og HSTL Il HSTL Il Rp Zg 502 Rp Zg 500 gt X 20 ms Vper 0 75V DCI IOB IOB 2Rypp 2Zo 1002 2Rypp 2Zo 1002 HSTL II DCI HSTL II DCI gt 52 XH Veer 0 75V 2Rypy 2Zg 1002 i Veer 0 75V E E 2Rygw 2Zg 1000 4 ug070 6 39 071904 Figure 6 41 HSTL 1 5V Class Il Bidirectional Termination Virtex 4 User Guide www xilinx com 251 UGO070 v1 5 March 21
268. eGen and Architecture Wizard Click Next The Select Core Type window appears Select Clocking gt Single DCM_ADV click next The New Source Information window appears Click Finish The Xilinx ais Wizard starts 14 to Figure 2 18 show the settings available in the Clocking Wizard e 2 14 ade the general settings for the DCM After choosing the Advanced button the window shown i in i Big e 2 15 provides the advanced setting choices The windows in ure 2 16 and F e 2 17 show the settings for the global buffers using the previously selected DCM clock outputs as CLKFX or CLKFX180 is selected the Clock Frequency Synthesizer window shown in Figure 2 18 appears This window provides the CLKFX jitter calculation To access further i uide on available settings choose the More Info button in each window m J I I IN Iv r I ug070 2 14 071404 Figure 2 14 Xilinx Clocking Wizard General Setup 84 www xilinx com Virtex 4 User Guide UGO070 v1 5 March 21 2006 XILINX VHDL and Verilog Templates and the Clocking Wizard ug070 2 15 071504 Figure 2 15 Xilinx Clocking Wizard Advanced ug070 2 16 071504 Figure 2 16 Xilinx Clocking Wizard Clock Buffers Virtex 4 User Guide www xilinx com 85 UGO070 v1 5 March 21 2006 Chapter 2 Digital Clock Managers DCMs S XILINX co CLK2X CLKFX OUT eux a co ug070 2 17 071504 Figure 2 17 Xilinx Clocking Wizard View Edit B
269. e_off generic BITSLIP_ENABLE string FALSE TRUE FALSE DATA_RATE string DDR SDR DDR DATA_WIDTH integer 4 2 3 4 5 6 7 8 10 INTERFACE_TYPE string MEMORY MEMORY NETWORKING IOBDELAY string NONE NONE IBUF IFD BOTH IOBDELAY_TYPE string DEFAULT DEFAULT FIXED VARIABLE IOBDELAY_VALUE integer 0 0 to 63 NUM_CE integer 2 1 2 SERDES_MODE string MASTER MASTER SLAVE synthesis translate on port O out STD LOGIC Q1 out STD LOGIC Q2 out STD LOGIC Q3 out STD LOGIC Q4 out STD LOGIC Q5 out STD LOGIC Q6 out STD LOGIC SHIFTOUT1 out STD LOGIC SHIFTOUT2 out STD LOGIC BITSLIP in STD LOGIC CE1 in STD LOGIC CE2 in STD LOGIC CLK in STD LOGIC CLKDIV in STD LOGIC D in STD LOGIC DLYCE in STD LOGIC D D LYINC in STD LOGIC LYRST in STD LOGIC OCLK in STD LOGIC REV in STD LOGIC SHIFTIN1 in STD LOGIC SHIFTIN2 in STD LOGIC SR in STD LOGIC Ja end component Component Attribute specification for ISERDES should be placed after architecture declaration but before the begin keyword attribute BITSLIP_ENABLE string attribute DATA_RATE string attribute DATA_WIDTH integer attribute INTERFACE TYPE string attribute IOBDELAY string attribute IOBDELAY_TYPE string attribute IOBDELAY VALUE
270. ead until EMPTY is asserted The Almost Full and Almost Empty offsets can also be used in unstoppable block transfer applications to signal that a new block of data can be written or read When setting the offset ranges in the design tools use hexadecimal notation FIFO VHDL and Verilog Templates VHDL and Verilog templates are available in the Libraries Guide FIFO VHDL Template FIFO16 To incorporate this function into the design the VHDL following instance declaration needs to be placed in instance the architecture body of the design code The instance declaration name FIFO16 inst and or the port declarations code after the gt assignment can be changed to properly connect this function to the design All inputs and outputs must be connected Library In addition to adding the instance declaration a use declaration statement for the UNISIM v components library needs for to be added before the entity declaration This Xilinx library contains the component declarations for all primitives Xilinx primitives and points to the models that will be used for simulation Copy the following two statements and paste them before the Entity declaration unless they already exists Library UNISIM use UNISIM vcomponents all lt Cut code below this line and paste into the architecture body gt FIFO16 Virtex 4 Block RAM Asynchrnous FIFO Virtex 4 User Guide FIFO16 inst FIFO16 generic map
271. easserts when the number of empty spaces in the FIFO is greater than the ALMOST FULL OFFSET value and is synchronous to WRCLK Table 4 11 shows the number of clock cycles to assert or deassert each flag Table 4 11 Clock Cycle Latency for Flag Assertion and Deassertion Assertion Deassertion Clock Cycle Latency Standard FWFT Standard FWFT EMPTY 0 0 3 4 FULL 1 1 3 3 ALMOST EMPTY 1 1 3 3 136 FULL 1 1 3 3 READ ERROR 0 0 0 0 WRITE ERROR 0 0 0 0 Notes 1 Depending on the time between read and write clock edges the Almost Empty and Almost Full flags can deassert one cycle later www xilinx com Virtex 4 User Guide UGO070 v1 5 March 21 2006 XILINX FIFO Attributes FIFO Attributes Table 4 12 lists the FIFO16 attributes The size of the asynchronous FIFO can be configured by setting the DATA_WIDTH attribute The FIFO VHDL and Verilog Templates section has examples for setting the attributes Table 4 12 FIFO16 Attributes Attribute Name Type Values Default Notes ALMOST_FULL_OFFSET 12 bit See Table 4 13 Setting determines ALMOST_FULL HEX condition Must be set using hexadecimal notation ALMOST_EMPTY_OFFSET 12 bit See Table 4 13 Setting determine ALMOST_EMPTY HEX condition Must be set using hexadecimal notation FIRST WORD FALL THROUGH Boolean FALSE FALSE If TRUE during a write of the 1st TRUE word the word appears at the FIFO
272. ecrement operation begins on the next positive clock cycle When CE is lowered the increment decrement operation ceases on the next positive clock cycle IDELAY is a wrap around programmable delay element When the end of the delay element is reached tap 63 a subsequent increment function will return to tap 0 The same applies to the decrement function decrementing below zero moves to tap 63 The increment decrement operation is summarized in Table 7 7 Table 7 7 Increment Decrement Operations Operation RST CE INC Reset to IOBDELAY_VALUE 1 x x Increment tap count 0 1 1 Decrement tap count 0 1 0 Virtex 4 User Guide UG070 v1 5 March 21 2006 www xilinx com XILINX ILOGIC Resources Table 7 7 ncrement Decrement Operations Continued Operation RST CE INC No change 0 0 x Notes 1 RST takes precedence over CE and INC IDELAY Attributes Table 7 8 summarizes the IDELAY attributes Table 7 8 IDELAY Attribute Summary IDELAY Attribute Description Value Default Value IOBDELAY TYPE Sets the type of tap delay String DEFAULT FIXED or DEFAUIT VARIABLE IOBDELAY VALUE Specifies the initial tap setting Integer 0 to 63 0 IOBDELAY_TYPE Attribute The IOBDELAY_TYPE attribute sets the type of delay used The attribute values are DEFAULT FIXED and VARIABLE When set to DEFAULT the zero hold time delay element is selected This delay elemen
273. ed RAM Single Port 16 x 1 can be used also for RAM16X1S 1 Device Virtex 4 Family I 4 eene er Se Sa a en a a ee ee eee Dese Distributed RAM Instantiation RAM16X1S U RAM16X1S D insert input signal WE insert Write Enable signal WCLK insert Write Clock signal A0 insert Address 0 signal Al insert Address 1 signal 202 www xilinx com Virtex 4 User Guide UG070 v1 5 March 21 2006 X XILINX Shift Registers SRLs Primitives and Verilog VHDL Example A2 insert Address 2 signal A3 insert Address 3 signal O insert output signal Shift Registers SRLs Primitives and Verilog VHDL Example This section provides generic VHDL and Verilog submodules and reference code examples for implementing from 16 bit up to 64 bit shift registers These submodules are built from 16 bit shift register primitives and from dedicated MUXF5 MUXF6 MUXF7 and MUXF8 multiplexers SRL Primitives and Submodules Virtex 4 User Guide Eight primitives are available that offer optional clock enable CE inverted clock CLK and cascadable output Q15 combinations Table 5 13 lists all of the available primitives for synthesis and simulation Table 5 13 Shift Register Primitives Primitive Length Control Address Inputs Output SRL16 16 bits CLK A3 A2 A1 A0 Q SRL16E 16 bits CLK CE A3 A2 A1 A0 Q SRL16_1 16 bits CLK A3 A2 A1 A0 Q SRL16E_1 16 bits CLK CE A3 A2
274. ee IDELAY 321 www xilinx com differential termination 282 DIFF TERM 234 282 diode temperature sensing 387 E Error Correction Code ECC 157 F FIFO 139 architecture 141 attributes 145 cascading 156 FWFT mode 143 operating modes 143 ports 142 primitive 141 standard mode 143 status flags 143 timing parameters 148 G GCLK 32 global clocks clock buffers 19 20 clock I O inputs 20 GSR defined 121 GTL 245 defined 245 GTL_DCI 245 GTLP 246 GTLP_DCI 246 H HSTL 248 defined 248 class I 249 class I 1 8V 258 class II 250 class II 1 8V 259 class III 255 class III 1 8V 264 class IV 256 class IV 1 8V 265 CSE differential HSTL class II 252 259 261 DIFF HSTL 267 389 X XILINX HyperTransport LDT 284 I O standards 216 bank rules 286 compatibility 288 differential I O 216 single ended I O 216 I O tile 215 ILOGIC 215 IOB 215 OLOGIC 215 IBUF 229 PULLUP PULLDOWN KEEPER 233 IBUFDS 230 IBUFG 21 229 IBUFGDS 21 230 IDDR 311 OPPOSITE_EDGE mode 312 ports 315 primitive 315 SAME_EDGE mode 313 SAME_EDGE_PIPELINED mode 314 IDELAY 321 defined 321 355 attributes 323 delay mode fixed 321 variable 321 zero hold time 321 IDELAYCTRL 330 increment decrement 322 ports 322 primitive 321 reset 322 switching characteristics 323 timing 323 IDELAYCTRL 330 instantiating 333 335 RDY port 334 location 333 primitive 330 REFCLK 330 341 ILOGIC 215 309 IDDR 311 SR 309 swi
275. eiver Termination 00 ccc cece eee ence hrs 286 Rules for Combining I O Standards in the Same Bank 286 3 3V I O Design Guidelines 0 000 290 I O Standard Design Rules oer e pp a eet pene ee la cata gee 290 Mixing Techniques e etc ree e Hoa iet i eb Ped HR deae eee ee ident 293 SUMMARY xke d ebd eolequ tee pda ser qr dd oui ia Dados tar bine vedi ua 294 Simultaneous Switching Output Limits 0 0 0000 e eee 295 Sparse Chevron Packages sssssseesssee eee 295 Nominal PCB Specifications 0 6 6 cece eee 295 PCB Constructions ee ed aea ie ide cett este werd esee tese buds eee dite ar asc 295 Signal Return Current Management liess enn 295 koad Traces 24 director pate dede e Qe e e ede Me ee MD esc 296 Power Distribution System Design csse 296 Nominal SSO Limit Table Sparse Chevron l iislllleeeeeeeeeeee 296 Equivalent Vcco GND Pairs Sparse Chevron 6 6 0 0 cece eee eee 297 Virtex 4 User Guide www xilinx com 13 UG070 v1 5 March 21 2006 X XILINX Nominal SSO Limit Tables Non Sparse Chevron 0 000 e cece eens 298 Equivalent Vcco GND Pairs Non Sparse Chevron 1 0 66 cee cee eee 302 Actual SSO Limits versus Nominal SSO Limits cc cece ences 302 Electrical Basis of SSO Noise 0 0 c ccc nett e n 302 Parasitic Factors Derating Method PFDM 000 0200000 303 Weighte
276. el of LUTs and dedicated MUXFX resources of the Virtex 4 CLBs VHDL and Verilog Instantiation Virtex 4 User Guide The primitives MUXF5 MUXF6 and so forth can be instantiated in VHDL or Verilog code to design wide input functions The submodules MUX_2_1_SUBM MUX_4_1_SUBM and so forth can be instantiated in VHDL or Verilog code to implement multiplexers However the corresponding submodule must be added to the design directory as hierarchical submodule For example if a module www xilinx com 211 UGO070 v1 5 March 21 2006 Chapter 5 Configurable Logic Blocks CLBs XILINX 212 is using the MUX_16_1_SUBM the MUX_16_1_SUBM vhd file VHDL code or MUX_16_1_SUBM v file Verilog code must be compiled with the design source code The submodule code can also be copied into the designer source code VHDL and Verilog Submodules VHDL and Verilog submodules are available to implement multiplexers up to 32 1 They illustrate how to design with the MUXFX resources When synthesis infers the corresponding MUXFX resource s the VHDL or Verilog code is behavioral code case statement Otherwise the equivalent case statement is provided in comments and the correct MUXFX are instantiated However most synthesis tools support the inference of all of the MUXEX The examples are guidelines for designing other wide input functions The available submodules are MUX 2 1 SUBM behavioral code MUX 4 1 SUBM MUX 8 1 SUBM MU
277. emperature Sensors General information on these devices is available from Maxim at http www maxim ic com Links to the specific data sheets for these devices e http pdfserv maxim ic com ds en MAX1617 pdf e http www maxim ic com quick view2 cfm qv pk 3000 e http pdfserv maxim ic com en ds MAX6627 M A X6628 pdf The PC Board Layout section of these data sheets include important design considerations Virtex 4 User Guide www xilinx com 387 UGO070 v1 5 March 21 2006 Chapter 9 Temperature Sensing Diode XILINX National Semiconductor LM83 or LM86 These National Semiconductor devices are triple diode input and local digital temperature sensors with a two wire interface General information on these devices is available at the National Semiconductor website http www national com Links to the specific data sheets for these devices e http www national com ds LM LMS83 pdf e http www national com ds LM LMS86 pdf The Application Hints section of these data sheets include important design considerations 388 www xilinx com Virtex 4 User Guide UG070 v1 5 March 21 2006 Index A asynchronous clocking 114 distributed RAM 170 FIFO 110 117 139 global set reset 121 mux 30 set reset in register or latch 169 Bitslip 371 See ISERDES 356 372 guidelines for use 373 operation 371 timing 373 block RAM 109 defined 110 asynchronous clocking 114 ECC 157 Primitive 158
278. er 0 IO user i0 Il1 user i1 S0 user s Declaring constraints in Verilog synthesis attribute LOC of U BUFGMUX is BUFGCTRL_X Y where is valid integer locations of BUFGCTRL Declaring Constraints in UCF File INST U BUFGMUX LOC BUFGCTRL_X Y where is valid integer locations of BUFGCTRL BUFGMUX_VIRTEX4 VHDL and Verilog Templates The following examples illustrate the instantiation of the BUFGMUX_VIRTEX4 module in VHDL and Verilog VHDL Template Example BUFGMUX_VIRTEX4 declaration component BUFGMUX_VIRTEX4 port O out std ulogic I0 in std ulogic I1 in std ulogic S in std ulogic end component Example BUFGMUX_VIRTEX4 instantiation U_BUFGMUX_VIRTEX4 BUFGMUX_VIRTEX4 Port map O gt user_o IO gt user i0 Il gt user i1 S gt user s 46 www xilinx com Virtex 4 User Guide UGO070 v1 5 March 21 2006 2 XILINX VHDL and Verilog Templates Declaring constraints in VHDL file attribute attribute attribute attribute attr attr attr attr ibute ibute ibute ibute where Verilog Tem plate Example INIT OUT integer PRESELECT IO boolean PRESELECT I1 boolean LOC string INIT OUT of U BUFGMUX VIRTEX4 label is 0 PRESELECT IO of U BUFGMUX VIRTEX4 label is FALSE PRESELECT I1 of U BUFGMUX VIRTEX4 label is FALSE LOC o is va f U BUFGMUX VIRTEX4 label is
279. eration is synchronous with a clock input CLK and an optional clock enable as shown in Figure 5 9 A dynamic read access is performed through the 4 bit address bus A 3 0 The configurable 16 bit shift register cannot be set or reset The read is asynchronous however a storage element or flip flop is available to implement a synchronous read By placing this flip flop the shift register performance is improved by decreasing the delay into the clock to out value of the flip flop However an additional clock latency is added Any of the 16 bits can be read out asynchronously by varying the LUT address This is useful in making smaller shift registers less than 16 bits For example when building an 8 bit shift register simply set the addresses to the 8th bit Virtex 4 User Guide www xilinx com 173 UGO070 v1 5 March 21 2006 Chapter 5 Configurable Logic Blocks CLBs XILINX SHIFTIN D SRLC16 m SHIFT REG A 8 0 4 Seo A 4 1 D L 7 Output Q MC15 Registered WS DI Output D BY T WSG optional CE SR we CLK TT CK Y SHIFTOUT Q15 UGO70 5 09 071504 Figure 5 9 Shift Register Configurations Figure 5 10 is an equivalent representation of the shift register Bx BY 16 bit Shift Register or WE SHIFT_OUT D CLK Address UG070_5_10_071504 Figure 5 10 Representation of a Shift Register An additional dedicated connection between shift
280. erent Complementary Single Ended CSE Differential SSTL Class ll 1 8V Figure 6 69 shows a sample circuit illustrating a valid termination technique for differential SSTL Class II 1 8V with unidirectional termination External Termination V 0 9V V 0 9V IOB Tr LE 10B DIFF SSTL18 Il Rs 200 502 502 Hw C Zo Dx l DIFF SSTL18 Il Vr 0 9V Vr 0 9V DIFF SSTL18 Il ug070 6 67 071904 Figure 6 69 Differential SSTL 1 8V Class II Unidirectional Termination Virtex 4 User Guide www xilinx com 279 UGO070 v1 5 March 21 2006 Chapter 6 SelectlO Resources XILINX Figure 6 70 shows a sample circuit illustrating a valid termination technique for CSE differential SSTL Class II 1 8V with unidirectional DCI termination DCI IOB 10B Voco 18V Voco 1 8V DIFF SSTL18 Il DCI 2Rypp 2Zg 1000 2Rypp 2Zg 1000 Ry 200 2Rypy 2Zg 1000 2Aypn 7229 1000 pier ssi 18 Il DCI e Veco 18V Voco 1 8V ul Te SB Em 2Rygp 2Zg 1000 t KOH 2Rypy 2Zo 1000 4 2Rypy 2Zg 1000 Ro 20Q E VRN 0 VRN 0 ug070 6 68 071904 Figure 6 70 Differential SSTL 1 8V Class II Unidirectional DCI Termination Figure 6 71 shows a sample circuit illustrating a valid termination technique for CSE differential SSTL Class II 1 8V with bidirectional termination External Termination IOB IOB V 0 9V CCO Veco
281. eries N R Yes Yes LVDS_25_DCI 2 5 N R N R Split No Yes LVDSEXT_25_DCI N R N R Split No Yes SSTL2_I_DCI 1 25 N R Split Yes Yes SSTL2 II DCI 1 25 Split Split Yes Yes DIFF SSTL2 II DCI N R Split Split Yes Yes 288 www xilinx com Virtex 4 User Guide UGO070 v1 5 March 21 2006 XILINX Rules for Combining I O Standards in the Same Bank Table 6 38 VO Compatibility Continued Vcco VREF Termination Type Lower Capacitance IOB I O Standard Output Input Input Output Input Output Input HSTL III 18 1 1 N R N R Yes Yes HSTL IV 18 1 1 N R N R Yes Yes HSTL I 18 0 9 N R N R Yes Yes HSTL II 18 0 9 N R N R Yes Yes Note 2 DIFF HSTL II 18 N R N R N R Yes Yes SSTL18 I 0 9 N R N R Yes Yes SSTL18 II 0 9 N R N R Yes Yes DIFF SSTL18 II N R N R N R Yes Yes LVCMOS18 N R N R N R Yes Yes LVDCI 18 N R Series N R Yes Yes HSLVDCI 18 a Vcco 2 Series N R Yes Yes LVDCI DV2 18 N R Series N R Yes Yes HSTL III 18 DCI 1 1 N R Single Yes Yes HSTL IV 18 DCI 1 1 Single Single Yes Yes HSTL I 18 DCI d 0 9 N R Split Yes Yes HSTL II 18 DCI 0 9 Split Split Yes Yes DIFF HSTL III 18 DC N R Split Split Yes Yes SSTL18 I DCI 0 9 N R Split Yes Yes SSTL18 II DCI 0 9 Split Split Yes Yes DIFF SSTL18 II DCI N R Split Split Yes Yes Virtex 4 User Guide www xilinx com 289 UG070 v1 5 March
282. ers SRLs Primitives and Verilog VHDL Example Fully Synchronous Shift Registers All shift register primitives and submodules do not use the register s available in the same slice s To implement a fully synchronous read and write shift register output pin Q must be connected to a flip flop Both the shift register and the flip flop share the same clock as shown in Figure 5 31 FF Q Synchronous SRLC16E Output Write Enable P Q15 UGO070 5 31 071504 Figure 5 31 Fully Synchronous Shift Register This configuration provides a better timing solution and simplifies the design Because the flip flop must be considered to be the last register in the shift register chain the static or dynamic address should point to the desired length minus one If needed the cascadable output can also be registered in a flip flop Static Length Shift Registers Virtex 4 User Guide The cascadable16 bit shift register implements any static length mode shift register without the dedicated multiplexers MUXF5 MUXF6 Figure 5 32 illustrates a 40 bit shift register Only the last SRLC16E primitive needs to have its address inputs tied to 0111 Alternatively shift register length can be limited to 39 bits address tied to 0110 and a flip flop can be used as the last register In an SRLC16E primitive the shift register length is the address input 1 www xilinx com 207 UG070 v1 5 March 21 2006 Chapter 5 Configurable L
283. ers must be used in the software either by using IOSTANDARD attributes or instantiations in the HDL code 3 External reference resistors must be connected to multipurpose pins VRN and VRP in the bank These two multipurpose pins cannot be used as regular user I Os Refer to the Virtex 4 pinout tables for the specific pin locations Pin VRN must be pulled up to Veco by its reference resistor Pin VRP must be pulled down to ground by its reference resistor 4 The value of the external reference resistors should be selected to give the desired output impedance If using GTL DCI HSTL DCI or SSTL DCII O standards then the external reference resistors should be 50 Q The values of the reference resistors must be within the supported range 20 Q 100 Q Follow the DCI I O banking rules a Vggpmust be compatible for all of the inputs in the same bank b Veco must be compatible for all of the inputs and outputs in the same bank c No more than one DCI I O standard using single termination type is allowed per bank d No more than one DCI I O standard using split termination type is allowed per bank e Single termination and split termination controlled impedance driver and controlled impedance driver with half impedance can co exist in the same bank 7 The following packages to not support DCI in Banks 1 and 2 SF363 FF668 FF676 FF672 and FF1152 8 Inaddition the following devices do not support DCI in Banks 1 and 2 XC4VLX1
284. es Storage Elements The storage elements in a Virtex 4 slice can be configured as either edge triggered D type flip flops or level sensitive latches The D input can be driven directly by a LUT output via the DX or DY multiplexer or by the slice inputs bypassing the function generators via the BX or BY input The control signals clock CLK clock enable CE and set reset SR are common to both storage elements in one slice All of the control signals have independent polarity Any inverter placed on a control input is automatically absorbed The clock enable signal CE is active High by default If left unconnected the clock enable defaults to the active state In addition to clock CLK and clock enable CE signals each slice has set and reset signals SR and BY slice inputs SR forces the storage element into the state specified by the attribute SRHIGH or SRLOW SRHIGH forces a logic High when SR is asserted SRLOW forces a logic Low When SR is used an optional second input BY forces the storage element into the opposite state via the REV pin The reset condition is predominant over the set condition See Figure 5 4 The truth tables for SR are described in ILOGIC Resources in Chapter 7 The initial state after configuration or global initial state is defined by a separate INITO and INIT1 attribute By default setting the SRLOW attribute sets INITO and setting the SRHIGH attribute sets INIT1 For each slice set and reset
285. es an RST waveform when EN_REL FALSE CLKA RST_DEASSERT_CLK CLKA EN_REL FALSE RST All CLK Outputs A 4 RST asynchronously asserts After RST is registered All output clocks forced Low all output clocks start toggling Deasserted RST is registered TRENT Figure 3 5 RST Waveform Example The release REL signal affects PMCD outputs in the following manner Virtex 4 User Guide UG070 v1 5 March 21 2006 Asserting REL synchronously starts the divided outputs toggling REL is synchronous to CLKA Asserting REL must meet the setup time to CLKA REL assertion does not affect the delayed clock outputs REL is necessary when multiple PMCDs are used together and all PMCDs divided outputs should toggle in phase REL is enabled with the EN_REL attribute The default value of this attribute is FALSE Set to TRUE only if multiple PMCDs are used together or if other external synchronization is needed RST must be deasserted before REL can have any effect The REL input is positive edge sensitive Once REL is asserted the input has no further effect until another reset www xilinx com 99 Chapter 3 Phase Matched Clock Dividers PMCDs XILINX 100 Figure 3 6 illustrates the interaction between the RST and REL signals is rupe RST CLKA1 REL CLKA1D 2 4 8 A Deasserted RST l e Release is synchronized is registered Divided output clocks start toggling Delayed outp
286. essing the NMOS transistor N is the gate voltage plus the gate oxide limit or Ground 4 05V Ground Clamp Diode Dg Output Driver Input Buffer lt SSS SS SS nm em SS SSS SS SS SS ES R E Veco Vcco 3 a l Po I l I I I ld Power External I Clamp Pin I I Diode I Dp l l l l l 2 t T e t l l l l l l l No l l l l I l l l l l I l I l l I l I l l I l PEOPPPET LETC BND J ug070_6_76_072704 Figure 6 78 Virtex 4 I O 3 State Output Driver Table 6 39 Absolute Maximum Undershoot and Overshoot Veco V Maximum Undershoot V Maximum Overshoot V 3 75 0 30 4 05 3 6 0 45 4 05 3 45 0 60 4 05 3 3 0 75 4 05 3 0 1 05 4 05 The clamp diodes offer protection against transient voltage beyond approximately Veco 0 5V and Ground 0 5V The voltage across the diode increases proportionally to the current going through it Therefore the clamped level is not fixed and can vary depending on the board design The absolute maximum I O limits might be exceeded even if the clamp diode is active The IBIS models contain the voltage current characteristics of the I O drivers and clamp diodes Virtex 4 User Guide www xilinx com 291 UGO070 v1 5 March 21 2006 292 Chapter 6 SelectlO Resources XILINX To verify overshoot and undershoot are within the I O absolute maximum specifications
287. et signal becomes valid High at the SSR input of the block RAM e At time TrcKo po after clock event 4 the SRVAL 0101 becomes valid at the DO outputs of the block RAM Clock Event 5 Disable Operation Deasserting the enable signal EN disables any write read or SSR operation The disable operation does NOT change the contents of the memory or the values of the output latches e At time Tncck EN before clock event 5 the enable signal becomes valid Low at the EN input of the block RAM e After clock event 5 the data on the DO outputs of the block RAM is unchanged 138 www xilinx com Virtex 4 User Guide UG070 v1 5 March 21 2006 XILINX Built in FIFO Support Block RAM Timing Model Figure 4 13 illustrates the delay paths associated with the implementation of block RAM This example takes the simplest paths on and off chip these paths can vary greatly depending on the design This timing model demonstrates how and where the block RAM timing parameters are used e NET Varying interconnect delays Tiop Pad to I output of IOB delay e Tyjoop O input of IOB to pad delay e TgccKko_o BUFGCTRL delay FPGA Block RAM Tiop NET TRDCK DI Tipp NET TRock_ADDR Data r Address Write Enable gt Tiop NET TRacck wEN Topi NET TRcCK EN Tigpi NET TRock_sSsR Enable p gt Synchronous r Set Reset TRcoKo_po NET Tioop e TBccko o N
288. et to 0 the Xilinx ISE tools will not implement the design RAMB16 Port Mapping Design Rules The Virtex 4 block RAM can be configurable to various port widths and sizes Depending on the configuration some data pins and address pins are not used Table 4 2 page 120 shows the pins used in various configurations In addition to the information in Table 4 2 the following rules are useful to determine port connections 1 If the DI A B pins are less than 32 bits wide concatenate 32 DI_BIT_WIDTH logic zeros to the front of DI A B If the DIP A B pins are less than 4 bits wide concatenate 4 DIP BIT WIDTH logic zeros to the front of DIP A B DIP A B is unconnected when not in use DO A B pins must be 32 bits wide However valid data are only found on pins 0 to DO BIT WIDTH DOPIA B pins must be 4 bits wide However valid data are only found on pins 0 to DO BIT WIDTH DOP A B is unconnected when not in use ADDR A B pins must be 15 bits wide However valid addresses for non cascadable block RAM are only found on pins 13 to pins 14 address width The remaining pins including pin 14 should be tied to logic 0 Cascadeable Block RAM To use the cascadeable block RAM feature 1 2 Two RAMBI6 primitives must be instantiated Set the RAM EXTENSION A and RAM EXTENSION B attribute for one RAMB16 to UPPER and another to LOWER Connect the upper RAMB16 s CASCADEINA and CASCADEINB ports to t
289. ew to the Virtex 4 block RAM solution Data Parity Buses DIP A B and DOP A B The data parity buses are additional pins used for data parity with incoming data into the block RAM The block RAM does not generate the parity bits for incoming data These are supplied by the user If not supplying parity bits the pins can be used for incoming data Optional Output Registers Optional output registers can be used at either or both A B output ports of RAMB16 The choice is made using the DO A B REG attribute There is also an option to invert the clocks for either or both of the A B output registers using the INVERT CLK DO A B REG attribute The two independent clock enable pins are REGCE A B When using the optional output registers at port A B the synchronous set reset SSR pin of ports A B can not be used Figure 4 5 shows a optional output register Independent Read and Write Port Width Virtex 4 User Guide To specify the port widths designers must use the READ WIDTH A B and WRITE WIDTH A B attributes The following rules should be considered e Designing a single port block RAM requires the port pair widths of one write and one read to be set e g READ WIDTH A and WRITE WIDTH A www xilinx com 131 UGO070 v1 5 March 21 2006 Chapter 4 Block RAM XILINX Designing a dual port block RAM requires all port widths to be set When using these attributes if both write ports or both read ports are s
290. fault Factory JF must be manually set to FOFO when DLL FREQUENCY MODE HIGH The ISE software will issue a warning if FACTORY JF is not set as stated PHASE SHIFT Attribute The PHASE SHIFT attribute determines the amount of phase shift applied to the DCM outputs This attribute can be used in both fixed or variable phase shift mode If used with variable mode the attribute sets the starting phase shift When CLKOUT PHASE SHIFT VARIABLE POSITIVE the PHASE SHIFT value range is 0 to 255 When CLKOUT PHASE SHIFT VARIABLE CENTER or FIXED the PHASE SHIFT value range is 2255 to 255 When CLKOUT PHASE SHIFT DIRECT the PHASE SHIFT value range is 0 to 1023 The default value is 0 Refer to the Phase Shifting section for information on the phase shifting operation and its relationship with the CLKOUT PHASE SHIFT and PHASE SHIFT attributes STARTUP WAIT Attribute The STARTUP WAIT attribute determines whether the DCM waits in one of the startup cycles for the DCM to lock The possible values for this attribute are True and False The default value is False When STARTUP WAIT is set to True and the LCK cycle BitGen option is used then the configuration startup sequence waits in the startup cycle specified by LCK cycle until the DCM is locked Table 2 7 DCM Attributes CLKDV DIVIDE DCM Attribute Name Description Values Default Value This attribute controls CLKDV such Real 2 0 that the source clock is divided by 15 2 0 2 5 3
291. fectively eliminating the delay from the external input port to the individual clock loads within the device All DCM outputs can drive general interconnect however these connections are not suitable for critical clock signals It is recommended that all clock signals should be within the global or regional clock network Refer to Chapter 1 Clock Resources for more information on using clock networks Output pin connectivity carries some restrictions The DCM clock outputs can each drive an OBUF a global clock buffer BUFGCTRL or they can route directly to the clock input of a synchronous element To use dedicated routing the DCM clock outputs must drive BUFGCTRLs on the same top or bottom half of the device If the DCM and BUFGCTRL are not on the same top or bottom half local routing is used and the DCM might not deskew properly Do not use the DCM output clock signals until after activation of the LOCKED signal Prior to the activation of the LOCKED signal the DCM output clocks are not valid DCM During Configuration and Startup During the FPGA configuration the DCM is in reset and starts to lock at the beginning of the startup sequence A DCM requires both CLKIN and CLKFB input clocks to be present and stable when the DCM begins to lock If the device enters the configuration startup sequence without an input clock or with an unstable input clock then the DCM must be reset after configuration with a stable clock The following s
292. fferent phase shift multiply M or divide D from the currently configured settings Figure 2 1 shows a simplified view of the Virtex 4 center column resources including all DCM locations Table 2 1 summarizes the availability of DCMs in each Virtex 4 device DCMs Top Half PMCDs Top Half I Os BUFGCTRLs Top Half Virtex 4 Center Column BUFGCTRLs Bottom Half I Os PMCDs Bottom Half DCMs Bottom Half UG070_2_01_071204 Figure 2 1 DCM Location 52 www xilinx com Virtex 4 User Guide UG070 v1 5 March 21 2006 XILINX DCM Summary Table 2 1 Available DCM Resources Device Available DCMs Site Names XC4VLX15 4 Bottom Half XCAVSX25 DCM ADV X0Y0 DCM ADV X0Y1 XCAVEX12 XCAVEX20 Top al DCM ADV X0Y2 DCM ADV X0Y3 XC4VLX25 XCAVLX40 XCAVLX60 8 Bottom Half XCAVSX35 XCAVSX55 DCM ADV X0Y0 DCM ADV XOYI DCM ADV X0Y2 XC4VEX40 Top Half DCM_ADV_X0Y3 DCM ADV X0Y4 DCM ADV X0Y5 DCM ADV X0Y6 DCM ADV X0Y7 XCAVLX80 XCAVLX100 12 Bottom Half XCAVLX160 XCAVLX200 DCM ADV X0Y0 DCM ADV X0YI XCAVEX60 XCAVEX100 DCM ADV X0Y2 DCM ADV X0Y3 DCM ADV X0Y4 DCM ADV X0Y5 Top Half DCM ADV X0Y6 DCM ADV X0Y7 DCM ADV X0Y8 DCM ADV XO0Y9 DCM ADV X0Y10 DCM ADV XO0Y11 XC4VFX140 20 Bottom Half DCM_ADV_X0Y0 DCM_ADV_XOY1 DCM_ADV_X0Y2 DCM_ADV_X0Y3 DCM_ADV_X0Y4 DCM ADV XO0YS5 DCM ADV X0Y6 DCM ADV X0Y7 DCM ADV X0Y8 DCM ADV X0Y9 Top Half
293. g RDCLK edge is close to the rising WRCLK edge AFULL could be deasserted one WRCLK period later Clock Event 3 and Clock Event 4 Read Operation and Deassertion of Almost FULL Signal Three write clock cycles after the fourth data is read from the FIFO the Almost FULL pin is deasserted to signify that the FIFO is not in the almost FULL state The example in Figure 4 19 reflects both standard and FWFT modes Clock event 3 is with respect to read clock while clock event 4 is with respect to write clock Clock event 4 appears three write clock cycles after clock event 3 e Read enable remains asserted at the RDEN input of the FIFO e At time Trcko po after clock event 3 RDCLK data 03 becomes valid at the DO outputs of the FIFO e At time Trcko Arurr after clock event 4 RDCLK Almost FULL is deasserted at the AFULL pin www xilinx com 153 UGO070 v1 5 March 21 2006 Chapter 4 Block RAM X XILINX There is minimum time between a rising read clock and write clock edge to guarantee that AFULL will be deasserted If this minimum is not met the deassertion of AFULL can take an additional write clock cycle Case 4 Reading From An Empty or Almost Empty FIFO Prior to the operations performed in Figure 4 20 the FIFO is almost completely empty In this example the timing diagram reflects standard mode For FWFT mode data at DO appears one read clock cycle earlier 1 2 3 4 week Ji LJ LT LT LILL LS_ WREN RDCLK
294. ghtly different When using CE to switch clocks the change in clock selection can be faster than when using S Violation in Setup Hold time of the CE pins causes a glitch at the clock output On the other hand using the S pins allows the user to switch between the two clock inputs without regard to Setup Hold times It will not result in a glitch See the discussion of BUFGMUX VIRTEX4 The CE pin is designed to allow backward compatibility from Virtex II and Virtex II Pro FPGAs www xilinx com 23 UGO070 v1 5 March 21 2006 Chapter 1 Clock Resources XILINX The timing diagram in Figure 1 2 illustrates various clock switching conditions using the BUFGCTRL primitives Exact timing numbers are best found using the speed specification I L 771 J VEL I jo puc M NEN EP EC ERI RERO pm lBccck cE 6E Lp TERT o qd LR a a IGNOREO Lp IGNORE1 MdH TBCCKO O TEcckoo l TBCCKO O oS e e pcc p L at lO Begin I1 Begin 10 UG070_1_02_082704 Figure 1 2 BUFGCTRL Timing Diagram Before time event 1 output O uses input I0 At time Tgccck cr before the rising edge at time event 1 both CEO and 50 are deasserted Low At about the same time both CE1 and S1 are asserted High At time Tpccko o after time event 3 output O uses input I1 This occurs after a High to Low transition of I0 event 2 followed by a High to Low transition of I1
295. gic Resources ISERDES Luuusuueue 355 ISERDES Primitive vero py EE RA aN Seek REP Heb ee ee Sam 357 ISERDES Potts iic miiti oii EE EEEE ERR e IRURE A E E E AA AT CERE RA 358 Combinatorial O tp t OQ es eres eeke e HEEL E EU eee ees 358 Registered Outputs Q1 toQ6 poina siei ee eee tenet eens 358 Bitslip Operation BITSLIP neisa ccc cee eee e eee eee 358 Clock Enable Inputs CE1 and CE2 0 ect e ees 358 High Speed Clock Input CLK 2 cece nnn 359 Divided Clock Input CLKDIV sedis ieii cece cece eee 359 Serial Input Data from IOB D 1 cee nnn 359 High Speed Clock for Strobe Based Memory Interfaces OCLK 54 359 ISERDES Attributes 0 0 0 ccc e n 359 BITSLIP ENABLE Attribute ccc lh 360 DATA RATE Attribute 2 rirani ta ert era ek X UR Ya Ug E x ae 360 DATA WIDTH Attribute 0 ee e e e mn 360 INTERFACE TYPE Attribute 2 0 ccc hen 360 IOBDELAY Attribute llseeeeeeee cc eee e ata 361 NUM_CE Attribute eie ue ara pi beds broke a uev ERE qa e 361 SERDES MODE Attribute 2 0 0 ce ee c c lh 361 ISERDES Width Expansion 2 o e be eR Er e rper ie 361 Guidelines for Expanding the Serial to Parallel Converter Bit Width 362 Verilog Instantiation Template to use Width Expansion Feature 362 ISERDES Latencies i 2aacogo emer RR RETR ED RAO RESTE 365 ISERDES Timing Model and Parameters 0 00 000 eese 366 Timing Character
296. gic is dedicated for FIFO use only DIN DO wrclk rdclk wren rden reset ug070 4 14 080204 Figure 4 14 Top Level View of FIFO in Block RAM FIFO Primitive Figure 4 15 shows the FIFO16 Primitive FIFO16 DI 31 0 DO 31 0 DIP 3 0 DOP 3 0 RDEN WRCOUNT 1 1 0 RDCLK RDCOUNTT 1 0 WREN FULL WRCLK EMPTY RST ALMOSTFULL ALMOSTEMPTY RDERR WRERR ug070 4 15 071204 Figure 4 15 FIFO16 Primitive Virtex 4 User Guide www xilinx com 141 UGO070 v1 5 March 21 2006 Chapter 4 Block RAM XILINX FIFO Port Descriptions Table 4 10 lists the FIFO I O port names and descriptions Table 4 10 FIFO I O Port Names and Descriptions Port Name Direction Description DI Input Data input DIP Input Parity bit input WREN Input Write enable When WREN 1 data will be written to memory When WREN 0 write is disabled WRCLK Input Clock for write domain operation RDEN Input Read enable When RDEN 1 data will be read to output register When RDEN 0 read is disabled RDCLK Input Clock for read domain operation RESET Input Asynchronous reset of all FIFO functions flags and pointers DO Output Data output synchronous to RDCLK DOP Output Parity bit output synchronous to RDCLK FULL Output All entries in FIFO memory are filled No additional write enable is performed Synchronous to WRCLK ALMOSTFU
297. gnal names The single port templates are e RAM 165 e RAM 325 e RAM 645 The dual port templates are e RAM 16D Templates for the RAM 165 module are provided in VHDL and Verilog code as examples VHDL Template Module RAM 16S Description VHDL instantiation template Distributed RAM Single Port 16 x 1 can be used also for RAM16X1S_1 Device Virtex 4 Family Components Declarations Virtex 4 User Guide www xilinx com 201 UG070 v1 5 March 21 2006 Chapter 5 Configurable Logic Blocks CLBs XILINX component RAM16X1S generic INIT bit vector X 0000 port D in std logic WE in std logic WCLK in std logic AO in std_logic Al in std_logic A2 in std_logic A3 in std_logic 0 out std_logic end component Architecture section Attributes for RAM initialization 0 by default attribute INIT string attribute INIT of U RAM16X1S label is 0000 Distributed RAM Instantiation U RAM16X1S RAM16X1S port map D gt insert input signal WE gt insert Write Enable signal WCLK gt insert Write Clock signal AO gt insert Address 0 signal Al gt insert Address 1 signal A2 gt insert Address 2 signal A3 gt insert Address 3 signal O gt insert output signal Verilog Template Module RAM 16S Ty Description Verilog instantiation template Distribut
298. he CASCADEOUTA and CASCADEOUTS ports of the lower RAMB16 The CASCADEOUT ports for the upper RAMB16 do not require a connection Connect the CASCADEIN ports for the lower RAMB16 to either logic High or Low The data output ports of the lower RAMB16 are not used These pins are unconnected If placing location constraints on the two RAMB16s they must be adjacent If no location constraint is specified the Xilinx ISE software will automatically manage the RAMB16 locations The address pins ADDR A B must be 15 bits wide Both read and write ports must be one bit wide Figure 4 6 shows the cascadeable block RAM Byte Write Enable The following rules should be considered when the following when using the byte write enable feature 132 In x36 mode WE 3 0 is connected to the four user WE inputs In x18 mode WE 0 and WE 2 are connected and driven by the user WE 0 while WE 1 and WE 3 are driven by the user WE 1 www xilinx com Virtex 4 User Guide UGO070 v1 5 March 21 2006 XILINX Additional Block RAM Primitives e Inx9 x4 x2 x1 WE 3 0 are all connected to a single user WE Figure 4 8 shows a byte write enabled block RAM Additional Block RAM Primitives In addition to RAMB16 some added block RAM primitives are available for Virtex 4 designers allowing the implementation of various block RAM sizes with preset configurations The input and output data buses are represented by two buses for 9 bit width
299. he 3 state converter cannot be cascaded Virtex 4 User Guide www xilinx com UGO070 v1 5 March 21 2006 375 Chapter 8 Advanced SelectlO Logic Resources XILINX OSERDES Primitive The OSERDES primitive is shown in Figure 8 11 CLK gt CLKDIV gt D1 gt D2 gt D3 gt D4 gt DS gt D6 gt OCE gt REV gt SHIFTIN1 gt SHIFTIN2 SR gt Ti gt T2 gt oQ TS gt SHIFTOUT1 T4 gt SHIFTOUT2 TCE VVVVVV VVVVVVNVNNN gt TQ ug070 8 19 072604 Figure 8 11 OSERDES Primitive 376 www xilinx com Virtex 4 User Guide UG070 v1 5 March 21 2006 XILINX Output Parallel to Serial Logic Resources OSERDES OSERDES Ports Table 8 7 lists the available ports in the OSERDES primitive Table 8 7 OSERDES Port List and Definitions Port Name Type Width Description OQ Output 1 Data path output See Data Path Output OQ SHIFTOUTI Output 1 Carry out for data width expansion Connect to SHIFTIN1 of master OSERDES See OSERDES Width Expansion SHIFTOUT2 Output 1 Carry out for data width expansion Connect to SHIFTIN2 of master OSERDES See OSERDES Width Expansion TQ Output 1 3 state control output See 3 state Control Output TO CLK Input 1 High speed clock input See High Speed Clock Input CLK CLKDIV Input 1
300. he Almost Empty flag is set when the FIFO contains the number of entries specified by the ALMOST_EMPTY_OFFSET value or fewer The Almost Empty flag warns the user to stop reading It will deassert when the number of entries in the FIFO is greater than the ALMOST_EMPTY_OFFSET value and is synchronous to RDCLK Read Error Flag Once the Empty flag has been asserted any further read attempts will not increment the read address pointer but will trigger the Read Error flag The Read Error flag is deasserted when Read Enable or Empty is deasserted Low The Read Error flag is synchronous to RDCLK Full Flag The Full flag is synchronous with WRCLK and is asserted one WRCLK after there are no more available entries in the FIFO queue Because of this latency it is recommended to use the ALMOST_FULL signal to stop further writing When the FIFO is full the write pointer will be frozen The Full flag is deasserted three write clock cycles after any read operation Write Error Flag Once the Full flag has been asserted any further write attempts will not increment the write address pointer but will trigger the Write Error flag The Write Error flag is deasserted when Write Enable or Full is deasserted Low This signal is synchronous to WRCLK Almost Full Flag The Almost Full flag is set when the FIFO has the number of available empty spaces specified by the ALMOST FULL OFFSET value or fewer The Almost Full flag warns the user to stop writing It d
301. he Virtex 4 architecture Clock Input Ports e Control and Data Input Ports e Clock Output Ports e Status and Data Output Ports Clock Input Ports Source Clock Input CLKIN The source clock CLKIN input pin provides the source clock to the DCM The CLKIN frequency must fall in the ranges specified in the Virtex 4 Data Sheet The clock input signal comes from one of the following buffers 1 IBUFG Global Clock Input Buffer The DCM compensates for the clock input path when an IBUFG on the same edge top or bottom of the device as the DCM is used 2 BUFGCTRL Internal Global Clock Buffer Any BUFGCTRL can drive any DCM in the Virtex 4 device using dedicated global routing A BUFGCTRL can drive the DCM CLKIN pin when used to connect two DCMs in series 3 IBUF Input Buffer When an IBUF drives the CLKIN input the PAD to DCM input skew is not compensated Feedback Clock Input CLKFB The feedback clock CLKFB input pin provides a reference or feedback signal to the DCM to delay compensate the clock outputs and align them with the clock input To provide the necessary feedback to the DCM connect only the CLK0 DCM output to the CLKFB pin When the CLKFB pin is connected all clock outputs will be deskewed to CLKIN When the CLKFB pin is not connected DCM clock outputs are not deskewed to CLKIN However the relative phase relationship between all output clocks is preserved During internal feedback configuration the CLKO
302. he last 10 ns ug070 2 05 071204 Figure 2 5 Fixed Phase Shift Examples In variable mode the phase shift factor is changed by activating PSEN for one period of PSCLK At the PSCLK clock cycle where PSEN is activated the level of PSINCDEC input determines whether the phase shift increases or decreases A High on PSINCDEC increases the phase shift and a Low decreases the phase shift After the deskew circuit increments or decrements the signal PSDONE is asserted High for a single PSCLK cycle This allows the next change to be performed The user interface and the physical implementation are different The user interface describes the phase shift as a fraction of the clock period N 256 The physical implementation adds the appropriate number of buffer stages each DCM TAD to the clock delay The DCM_TAP granularity limits the phase resolution at higher clock frequencies All phase shift modes with the exception of DIRECT mode are temperature and voltage adjusted Hence a Vcc or temperature adjustment will not change the phase shift The DIRECT phase shift is not temperature or voltage adjusted since it directly controls DCM TAP Changing the ratio of Vcc temperature results in a phase shift change proportional to the size of the DCM_TAP at the specific voltage and temperature Interaction of PSEN PSINCDEC PSCLK and PSDONE The variable and direct phase shift modes are controlled by the PSEN PSINCDEC PSCLK and PSDONE ports
303. he possible values for the location constraint are all the external port identifiers e g A8 M5 AM6 etc These values are device and package size dependent The LOC attribute uses the following syntax in the UCF file INST I O BUFFER INSTANTIATION NAME LOC EXTERNAL PORT IDENTIFIER Example INST MY IO LOC R7 lOStandard Attribute The IOSTANDARD attribute is available to choose the values for an I O standard for all I O buffers The supported I O standards are listed in Table 6 38 The IOSTANDARD attribute uses the following syntax in the UCF file INST I O BUFFER INSTANTIATION NAME IOSTANDARD IOSTANDARD VALUE gt The IOSTANDARD default for single ended I O is LVCMOS25 for differential I Os the default is LVDS 25 Output Slew Rate Attributes A variety of attribute values provide the option of choosing the desired slew rate for single ended I O output buffers For LVTTL and LVCMOS output buffers OBUF OBUFT and IOBUF the desired slew rate can be specified with the SLEW attribute The allowed values for the SLEW attribute are e SLEW SLOW Default e SLEW FAST The SLEW attribute uses the following syntax in the UCF file INST lt I O_BUFFER_INSTANTIATION_NAME gt SLEW lt SLEW_VALUE gt By the default the slew rate for each output buffer is set to SLOW This is the default used to minimize the power bus transients when switching non critical signals 23
304. he resulting PMCD outputs CLKA1 CLKB1 CLKC1 and CLKD1 reflect the duty cycle of their corresponding input Virtex 4 User Guide www xilinx com 97 UGO070 v1 5 March 21 2006 Chapter 3 Phase Matched Clock Dividers PMCDs XILINX CLKA1D2 CLKA1D4 CLKA1D8 TPMCCKO CLKIN lt ug070 3 04 071404 Figure 3 4 Matched Clock Phase Reset RST and Release REL Control Signals RST and REL are the control signals for the PMCD The interaction between RST REL and the PMCD input clocks help manage the starting and stopping of PMCD outputs The reset RST signal affects the PMCD clock outputs in the following manner e Asserting RST asynchronously forces all outputs Low e Deasserting RST synchronously allows all outputs to toggle The delayed outputs begin toggling one cycle after RST is deasserted and is registered IfEN_REL FALSE default the divided outputs will also begin toggling one cycle after RST is deasserted and is registered If EN REL TRUE then a positive edge on REL starts the divided outputs toggling on the next positive edge of CLKA e By setting the RST DEASSERT CIK attribute deasserting RST can be synchronized to any of the four input clocks The default value of RST DEASSERT CLK is CLKA see Table 3 3 98 www xilinx com Virtex 4 User Guide UG070 v1 5 March 21 2006 XILINX PMCD Usage and Design Guidelines Figure 3 5 illustrat
305. he timing diagram of the input DDR using the SAME EDGE mode In the timing diagram the output pairs are no longer 0 and 1 Instead the first pair presented is pair 0 and don t care followed by pair 1 and 2 on the next clock cycle Virtex 4 User Guide www xilinx com 313 UGO070 v1 5 March 21 2006 Chapter 7 SelectlO Logic Resources 314 Q1 Q2 DiA D3A D5A D7A D9A DOA D2A Don t care D1A Figure 7 5 SAME EDGE PIPELINED Mode D4A D3A D6A D5A D8A D7A Input DDR Timing in SAME_EDGE Mode D9A XILINX D11A ug070_7_05_072904 In the SAME_EDGE_PIPELINED mode a fourth register IFF3 clocked by the rising edge clock is placed on the output of the two registers Figure 7 6 shows the input DDR registers and the signals involved using the SAME_EDGE_PIPELINED mode E UPS Figure 7 6 ug070_7_06_072904 Input DDR in SAME_EDGE_PIPELINED Mode By adding the additional register data is presented into the FPGA fabric on the same clock edge Unlike the SAME_EDGE mode the additional registers do not cause the data pair to be separated However an additional clock latency is required to remove the separated effect of the SAME_EDGE mode Figure 7 7 shows the timing diagram of the input DDR using the SAME_EDGE_PIPELINED mode The output pairs Q1 and Q2 are presented to the FPGA fabric at the same time
306. he write error signal is asserted deasserted at every write clock positive edge As long as both the write enable and Full signals are true write error will remain asserted 152 www xilinx com Virtex 4 User Guide UG070 v1 5 March 21 2006 X XILINX Virtex 4 User Guide FIFO Timing Models and Parameters Case 3 Reading From a Full FIFO Prior to the operations performed in Figure 4 19 the FIFO is completely full RDEN EM Trcko po I4 Trcko Do DO C9 XC OL OXC ER OX X OXI T FCKO FULL k T FULL m ee AFULL 1 ug070 4 19 071204 Figure 4 19 Reading From a Full FIFO Clock Event 1 and Clock Event 2 Read Operation and Deassertion of Full Signal During a read operation on a full FIFO the content of the FIFO at the first address is asserted at the DO output pins of the FIFO Three write clock cycles later the FULL pin is deasserted when the FIFO is no longer full The example in Figure 4 19 reflects both standard and FWFT modes Clock event 1 is with respect to read clock while clock event 2 is with respect to write clock Clock event 2 appears three write clock cycles after clock event 1 e At time Trcck RDEN before clock event 1 RDCLK read enable becomes valid at the RDEN input of the FIFO e At time Trcko po after clock event 1 RDCLK data 00 becomes valid at the DO inputs of the FIFO e At time Trgcko FULL after clock event 2 WRCLK FULL is deasserted If the risin
307. iate In a source synchronous design set this attribute to SOURCE SYNCHRONOUS The remaining values should only be used after consulting with Xilinx For more information consult the Source Synchronous Setting section DFS FREQUENCY MODE Attribute The DF5 FREQUENCY MODE attribute specifies the frequency mode of the digital frequency synthesizer DFS The possible values are Low and High The default value is Low The frequency ranges for both frequency modes are specified in the Virtex 4 Data Sheet DF5 FREQUENCY MODE determines the frequency range of CLKIN CLKFX and CLKFX180 DLL FREQUENCY MODE Attribute The DLL FREQUENCY MODE attribute specifies either the High or Low frequency mode of the delay locked loop DLL The default value is Low The frequency ranges for both frequency modes are specified in the Virtex 4 Data Sheet DUTY CYCLE CORRECTION Attribute The DUTY CYCLE CORRECTION attribute controls the duty cycle correction of the 1x clock outputs CLK0 CLK90 CLK180 and CLK270 The possible values are True and False The default value is True When set to True the 1x clock outputs are duty cycle corrected to be within specified limits see the Virtex 4 Data Sheet for details It is strongly recommended to always set the DUTY CYCLE CORRECTION attribute to True Setting this attribute to False does not necessarily produce output clocks with the same duty cycle as the source clock DCM PERFORMANCE MODE Attribute The DCM
308. ice Sequential Elements Tyxck Setup time before clock edge Teck Hold time after clock edge Tpick Tckpr BX BY Inputs Time before Clock CLK that data from the BX or BY inputs of the slice must be stable at the D input of the slice sequential elements configured as a flip flop Tgxck Tckrex FxiNA Pxixp Input Time before Clock CLK that data from the Fyqya or Fxpyp inputs of the slice must be stable at the D input of the slice sequential elements configured as a flip flop TcEck TcKcE CE input Time before Clock CLK that the CE Clock Enable input of the slice must be stable at the CE input of the slice sequential elements configured as a flip flop Tsnck Tcksn SR BY inputs Time before Clock CLK that the SR Set Reset and the BY Rev inputs of the slice must be stable at the SR Rev inputs of the slice sequential elements configured as a flip flop Synchronous set reset only Set Reset TRPW Minimum Pulse Width for the SR Set Reset and BY Rev pins TRO Propagation delay for an asynchronous Set Reset of the slice sequential elements From SR BY inputs to XQ YQ outputs FTOG Toggle Frequency Maximum Frequency that a CLB flip flop can be clocked 1 Texy T cz Virtex 4 User Guide UGO070 v1 5 March 21 2006 www xilinx com 187 Chapter 5 Configurable Logic Blocks CLBs XILINX Timing Characteristics Figure 5 21 illu
309. ide UGO070 v1 5 March 21 2006 2 XILINX ILOGIC Resources INC in STD LOGIC RST in STD_LOGIC end component Component Attribute specification for IDELAY should be placed after architecture declaration but before the begin keyword Architecture Section attribute IOBDELAY TYPE string attribute IOBDELAY VALUE integer Component Instantiation for IDELAY should be placed in architecture after the begin keyword Instantiation Section Ul IDELAY synthesis translate off generic map A IOBDELAY TYPE VARIABLE Set to VARIABLE for Variable Delay Mode LE IOBDELAY VALUE gt 0 synthesis translate on port map O gt data output I data input C clkdiv CE gt dlyce INC gt dlyinc RST gt dlyrst Jes Verilog Code for Variable Delay Mode The IDELAYCTRL primitive must be instantiated in conjunction with the IDELAY primitive when used in Variable Delay Mode Module IDELAY Description Verilog instantiation template Variable Delay Mode Device Virtex 4 Family Instantiation Section IDELAY U1 O data_output I data input C clkdiv CE dlyce INC dlyinc Virtex 4 User Guide UGO070 v1 5 March 21 2006 www xilinx com 329 Chapter 7 SelectlO Logic Resources XILINX RST dlyrst Set IOBDELAY TYPE attribute to VARIABLE fo
310. idth Expansion SHIFTIN2 Input 1 Carry input for data width expansion Connect to SHIFTOUT2 of master IOB See ISERDES Width Expansion SR Input 1 Set Reset This pin only functions as an asynchronous Reset in the ISERDES block ISERDES Ports Combinatorial Output O The combinatorial output port O is an unregistered output of the ISERDES module This output can come directly from the data input D or from the data input D via the IDELAY block Registered Outputs Q1 to Q6 The output ports Q1 to Q6 are the registered outputs of the ISERDES module One ISERDES block can support up to six bits i e a 1 6 deserialization Bit widths greater than six up to 10 can be supported see ISERDES Width Expansion Bitslip Operation BITSLIP The BITSLIP pin performs a Bitslip operation synchronous to CLKDIV when asserted active High Subsequently the data seen on the O1 to Q6 output ports will shift as in a barrel shifter operation one position every time Bitslip is invoked DDR operation is different from SDR See BITSLIP Sub Module for more details Clock Enable Inputs CE1 and CE2 Each ISERDES block contains a clock enable module This module functions as a 2 1 serial to parallel converter clocked by CLKDIV The clock enable module is needed specifically for bi directional memory interfaces when ISERDES is configured for 1 4 deserialization in DDR mode When the attribute NUM CE 2 the clock e
311. igh Risk Applications Xilinx specifically disclaims any express or implied warranties of fitness for such High Risk Applications You represent that use of the Specification in such High Risk Applications is fully at your risk 2004 2006 Xilinx Inc All rights reserved XILINX the Xilinx logo and other designated brands included herein are trademarks of Xilinx Inc PowerPC is a trademark of IBM Inc All other trademarks are the property of their respective owners Virtex 4 User Guide www xilinx com UG070 v1 5 March 21 2006 Revision History The following table shows the revision history for this document 08 02 04 Version 1 0 Revision Initial Xilinx release Printed Handbook version 09 10 04 1 1 In Chapter 1 Removed Table 1 6 BUFGMUX VIRTEX4 Attributes Updated Table 1 1 Table 1 2 Table 1 5 the new Table 1 6 Revised Figure 1 2 Figure 1 5 Figure 1 6 Figure 1 7 Figure 1 9 Figure 1 10 Figure 1 13 Figure 1 14 and Figure 1 16 Associated text around these tables and figures were revised In Chapter 2 changes to FACTORY JF Attribute and in Table 2 7 In Chapter 9 System Monitor Changed in Figure 9 4 Figure 9 5 Figure 9 7 Figure 9 8 Figure 9 9 Figure 9 10 Figure 9 21 Figure 9 25 Figure 9 26 and Figure 9 27 Changes to the equation in the Temperature Sensor section The following tables had changes Table 9 3 Table 9 5 Table 9 6 Table 9 9 Table 9 11 Table 9 12 Ta
312. ile the device is operating By default the DONE pin does not go High until the first phase of the impedance adjustment process is complete www xilinx com Virtex 4 User Guide UG070 v1 5 March 21 2006 2 XILINX SelectlO Resources General Guidelines The coarse impedance calibration during first phase of impedance adjustment can be invoked after configuration by instantiating the DCIRESET primitive By toggling the RST input to the DCIRESET primitive while the device is operating the DCI state machine is reset and both phases of impedance adjustment proceed in succession All I Os using DCI will be unavailable until the LOCKED output from the DCIRESET block is asserted This functionality is useful in applications where the temperature and or supply voltage changes significantly from device power up to the nominal operating condition Once at the nominal operating temperature and voltage performing the first phase of impedance adjustment allows optimal headroom for the second phase of impedance adjustment For controlled impedance output drivers the impedance can be adjusted either to match the reference resistors or half the resistance of the reference resistors For on chip termination the termination is always adjusted to match the reference resistors DCI can configure output drivers to be the following types 1 Controlled Impedance Driver Source Termination 2 Controlled Impedance Driver with Half Impedance Source Termi
313. implement a 16 1 and the MUXF8 and two CLBs can implement a 32 1 multiplexer Figure 5 18 summarizes the implementation of a wide input multiplexer The section Multiplexer Verilog VHDL Examples has code for the wide input multiplexers Virtex 4 User Guide UGO070 v1 5 March 21 2006 8 1 MUX DATA 7 0 J S2 8 1 Output DATA 15 8 SELECT 2 0 SELECT 3 8 1 81 amp S3 16 1 MUX Figure 5 18 8 1 and 16 1 Multiplexers www xilinx com 16 1 output CLB UGO70 5 18 071504 183 Chapter 5 Configurable Logic Blocks CLBs XILINX Fast Lookahead Carry Logic Dedicated carry logic provides fast arithmetic addition and subtraction The Virtex 4 CLB has two separate carry chains as shown in the Figure 5 19 The height of the carry chains is two bits per slice The carry chain in the Virtex 4 device is running upward The dedicated carry path and carry multiplexer MUXCY can also be used to cascade function generators for implementing wide logic functions COUT COUT A to SO of the next CLB to CIN of S1 of the next CLB First Carry Chain SLICE S3 SLICE S1 Second Carry Chain SLICE SO ug070 5 19 071504 Figure 5 19 Fast Carry Logic Path 184 www xilinx com Virtex 4 User Guide UG070 v1 5 March 21 2006 XILINX CLB Slice Timing Models Arithmetic Logic The arith
314. in the same slice The distributed RAM and the Virtex 4 User Guide UGO070 v1 5 March 21 2006 www xilinx com 169 Chapter 5 Configurable Logic Blocks CLBs XILINX storage element share the same clock input For a write operation the Write Enable WE input driven by the SR pin must be set High Table 5 3 shows the number of LUTs two per slice occupied by each distributed RAM configuration Table 5 3 Distributed RAM Configuration RAM Number of LUTs 16x1S 1 16x 1D 2 32x1 2 64 x 1S 4 Notes 1 S single port configuration D dual port configuration For single port configurations distributed RAM memory has a common address port for synchronous writes and asynchronous reads For dual port configurations distributed RAM memory has one port for synchronous writes and asynchronous reads and another port for asynchronous reads The function generator LUT has separated read address inputs and write address inputs In single port mode read and write addresses share the same address bus In dual port mode one function generator R W port is connected with shared read and write addresses The second function generator has the A inputs Read connected to the second read only port address and the W inputs Write shared with the first read write port address Figure 5 5 Figure 5 6 and Figure 5 7 illustrate various example distributed RAM configurations occupying one slice RAM 16x18
315. ined to one deeper 32Kx1 memory without any external logic or speed loss e Ports 18 or 36 bits wide can have individual write enable per byte This feature is used for interfacing to an on chip PPC405 microprocessor e Each block RAM contains optional address sequencing and control circuitry to operate as a built in Multi rate FIFO memory The FIFO can be 4K deep and 4 bits wide or 2Kx9 1Kx18 or 512x36 Write and read ports have identical width The two free running clocks can have completely unrelated frequencies asynchronous relative to each other Operation is controlled by the read and write enable inputs Full and Empty outputs signal the extreme conditions without a possibility of errors or glitches Programmable Almost Full and Almost Empty outputs can be used for warning to simplify the external control of the write and read operation especially the maximum clock rate Additional Virtex 4 Block RAM Features e All output ports are latched The state of the output port does not change until the port executes another read or write operation e All inputs are registered with the port clock and have a setup to clock timing specification e All outputs have a read function or a read during write function depending on the state of the WE pin The outputs are available after the clock to out timing interval The read during write outputs have one of three operating modes WRITE_FIRST READ FIRST and NO CHANGE e Awrite operation
316. ing architectural improvements have been implemented e IDELAY provides users control of an adjustable fine resolution input delay element e SAME EDGE output DDR mode e SAME EDGE and SAME EDGE PIPELINED input DDR mode ILOGIC Resources ILOGIC blocks include four storage elements and a programmable absolute delay element shown in Figure 7 1 To build an edge triggered D type flip flop the topmost register IFF1 is used Only this register can optionally be configured as a level sensitive latch The other three registers IFF2 IFF3 and IFF4 are used to build various input DDR registers See Input DDR Overview IDDR page 311 for further discussion on input DDR All ILOGIC block registers have a common clock enable signal CE1 that is active High by default If left unconnected the clock enable pin for any storage element defaults to the active state All ILOGIC block registers have a common synchronous or asynchronous set and reset SR and REV signals The set reset input pin SR forces the storage element into the state specified by the SRVAL attributes When using SR a second input REV forces the storage element into the opposite state The reset condition predominates over the set condition Table 7 1 and Table 7 2 describe the operation of SR in conjunction with REV Virtex 4 User Guide www xilinx com 309 UGO070 v1 5 March 21 2006 Chapter 7 SelectlO Logic Resources XILINX Table 7 1 Truth Table when SRVAL
317. ion DCI also provides drivers with one half of the impedance of the reference resistors This doubling of the reference resistor value reduces the static power consumption through these resistors by a factor of half The DCI I O standards supporting controlled impedance drivers with half impedance are LVDCI_DV2_15 LVDCI_DV2_18 and LVDCI_DV2_25 Figure 6 5 illustrates a controlled driver with half impedance inside a Virtex 4 device The reference resistors R must be 2 x Zg in order to match the impedance of Zp IOB mag T gt 02 70 Virtex 4 DCI UGO070_6_05_071404 Figure 6 5 Controlled Impedance Driver with Half Impedance Input Termination to Veco Single Termination Some I O standards require an input termination to Vcco see Figure 6 6 Vcco IOB R ots o VREF Virtex 4 UG070_6_06_071404 Figure 6 6 Input Termination to Vcco without DCI DCI can also provide input termination to Vcco using single termination The termination resistance is set by the reference resistors Both GTL and HSTL standards are controlled by 50 Q reference resistors The DCI I O standards supporting single termination are GTL DCI GTLP_DCI HSTL III DCI HSTL III DCI 18 HSTL_IV_DCI and HSTL IV DCI 18 www xilinx com Virtex 4 User Guide UGO070 v1 5 March 21 2006 X XILINX SelectlO Resources General Guidelines Figure 6 7 illustrates DCI single termination inside a Virtex 4 device IOB
318. is allowed in the same bank Incompatible example HSTL_IV_DCI input and HSTL III DCI input b No more than one Split Termination type input or output is allowed in the same bank Incompatible example HSTL I DCIinput and HSTL II DCI input The implementation tools enforce the above design rules Virtex 4 User Guide UGO070 v1 5 March 21 2006 www xilinx com 287 Chapter 6 SelectlO Resources Table 6 38 XILINX Table 6 38 summarizes the Virtex 4 supported I O standards l O Compatibility Vcco VREF Termination Type Lower Capacitance IOB O Standard Output Input Input Output Input Output Input LVTTLO N R N R N R Yes Yes LVCMOS33 N R N R N R Yes Yes LVDCI 33 0 N R Series N R Yes Yes HSLVDCI 33 0 3 3 3 3 Vcco 2 Series N R Yes Yes PCIX D N R N R N R Yes Yes PCI33 3 0 N R N R N R Yes Yes PCI66 3 N R N R N R Yes Yes LVDS 25 N R N R N R No Yes LVDSEXT 25 N R N R N R No Yes LDT 25 N R N R N R No Yes ULVDS 25 N R N R N R No Yes RSDS 25 9 N R N R N R No Yes Note 2 BLVDS 25 N R N R N R Yes Yes LVPECL 25 N R N R N R Yes Yes SSTL2 I 1 25 N R N R Yes Yes SSTL2 II 1 25 N R N R Yes Yes DIFF SSTL2 II 2 5 N R N R N R Yes Yes LVCMOS25 N R N R N R Yes Yes LVDCI 25 N R Series N R Yes Yes HSLVDCI 25 Veco 2 Series N R Yes Yes LVDCI_DV2_25 N R S
319. is fully symmetrical and both ports are interchangeable Figure 4 1 illustrates the dual port data flow Table 4 1 lists the port names and descriptions Data can be written to either or both ports and can be read from either or both ports Each write operation is synchronous each port has its own address data in data out clock clock enable and write enable The read operation is synchronous and requires a clock edge There is no dedicated monitor to arbitrate the effect of identical addresses on both ports It is up to the user to time the two clocks appropriately However conflicting simultaneous writes to the same location never cause any physical damage www xilinx com Virtex 4 User Guide UGO070 v1 5 March 21 2006 XILINX CASCADEOUTA Synchronous Dual Port and Single Port RAMs CASCADEOUTB 18 Kbit Block RAM DIA DIPA ADDRA Port A WEA ENA SSRA DIB DIPB ADDRB WEB ENB Port B SSRB CLKB REGCEB CASCADEINA CASCADEINB ug070 4 01 071204 Figure 4 1 Dual Port Data Flows Table 4 1 Dual Port Names and Descriptions Port Name Description DI A B Data Input Bus DIP A BJ Data Input Parity Bus ADDR A B Address Bus WE A B Write Enable EN A B When inactive no data is written to the block RAM and the output bus remains in its previous state SSR A B Set Reset CLK A B Clock Input DO A B Data Output Bus D
320. ised Virtex 4 SX Family FF668 in Table 6 43 Chapter 8 Revised Clock Enable Inputs CE1 and CE2 Chapter 9 Added the Virtex 4 temperature sensing diode Virtex 4 User Guide www xilinx com UG070 v1 5 March 21 2006 Table of Contents Revision History asp ose iia heeded ee Gel we ee ee ae ew Qu teed ard 3 Preface About This Guide Gude Contes ecuador deor han den pa RR RE alc pot BR atl Renae ie bene 17 Additional Documentation 00 0 cence eens 17 Additional Support Resources eee 18 Typographical Conventions sssssssssssse eee 18 Chapter 1 Clock Resources Global and Regional Clocks usus eee 19 Global Clocks 52d so ead Sars a hehe Oe Ra des vue ee ve E YER RE 19 Regional Clocks and I O Clocks 0 2 0 0 000 0 e eee ee 19 Global Clocking Resources i cciewsvicnenauwevevecneceed en eis rea Ye 20 Global Clock Inputs 0350454406695 5 oo dee Re poe ep ales Se dea eee Ree ae 20 Global Clock Input Buffer Primitives 0 6 0 0 cee eee eens 21 Global Clock Buffers 2 0 0 0 0c ccc ec RR RIRs 21 Global Clock Buffer Primitives llle 22 Additional Use Models 12 e hee Decet rete le aba iden CIL MINUS CAR 30 Clock Tree and Nets GCLK sssseseeeeeee cece tenn en eee 32 Clock Regions e pected areata qoaa du oeste E ae ane 33 Regional Clocking Resources 0 60 0c cece ccc eee eee eens 34 Clock Capable T O i coepi Re unt
321. istics 3 5 555 aod edet eet doe b be d eva Ce es 366 ST SDRISERDES ve oie edie eds RAS URP BESS ee Were 367 ISERDES VHDL and Verilog Instantiation Template 0 200 368 ISERDES VHDL Instantiation esne ccc eee hrs 368 ISERDES Verilog Instantiation 2 6 a cierta ne 371 BITSLIP Sub Modull s 4 is rue E dee ons VAR ea VEO Re Vet ee Vee v4 ed FAS 371 Bitslip Operations eer decribdecreospP US up Sederserdu apr ceni data 371 Bitslip Timing Model and Parameters lieeseeeee ee 373 Output Parallel to Serial Logic Resources OSERDES 374 Data Parallel to Serial Converter 0 000 eee nee rs 374 3 State Parallel to Serial Conversion 0 0 0 00 llle 375 OSERDES Primitive 5 1 toeberbiwe ce Sa ede ae ee dE ee 376 OSE RIDES POTS s tree aet o Mesfen teste eres fnb e rer logie e detec enh etel oe ds 377 Data Path Output OQ 4 eden Las etaed cui Pede PH rd der dr bed red 377 3 state Control Output TQ seiss ect cere eens 377 High Speed Clock Input CLK n annuens cee eee ees 377 Divided Clock Input CLKDIV 0 eect eens 378 Parallel Data Inputs D1 to D6 6 ce eee eee 378 Output Data Clock Enable OCE sess nn 378 Parallel 3 state Inputs T1 to T4 0 cee eens 378 3 state Signal Clock Enable TCE 1 0 ccc cece eee nes 378 OSERDES Attributes 12RLOpLe ier 4e4deteideekmiueeredn bade ein be eines 378 DATA RATE OQ Attribute 0 hh han 379 DATA RATE TO
322. k buffer with one clock input and one clock output This primitive is based on BUFGCTRL with some pins connected to logic High or Low Figure 1 3 illustrates the relationship of BUFG and BUFGCTRL A LOC constraint is available for BUFG IGNORE1 VDD cgi GND GND Si BUFG SO CEO IGNOREO GND ug070 1 03 071204 Figure 1 3 BUFG as BUFGCTRL The output follows the input as shown in the timing diagram in Figure 1 4 UST CHEF S NP RNC Lu MES m CP D c ARN Hk TBcCKO O UGO70 1 04 071204 Figure 1 4 BUFG Timing Diagram Virtex 4 User Guide www xilinx com 25 UGO070 v1 5 March 21 2006 Chapter 1 Clock Resources XILINX BUFGCE and BUFGCE_1 Unlike BUFG BUFGCE is a clock buffer with one clock input one clock output and a clock enable line This primitive is based on BUFGCTRL with some pins connected to logic High or Low Figure 1 5 illustrates the relationship of BUFGCE and BUFGCTRL A LOC constraint is available for BUFGCE and BUFGCE_1 BUFGCE as BUFGCTRL IGNORE1 D cup CE BUFGCE GND 1 CE Vop 92 CE CEO GND IGNOREO ug070 1 05 081904 Figure 1 5 BUFGCE as BUFGCTRL The switching condition for BUFGCE is similar to BUFGCTRL If the CE input is Low prior to the incoming rising clock edge the following clock pulse does not pass through the clock buffer and the output stays Low Any level change of CE during the incoming clock High pulse has no effect until the clock transitions Low The out
323. ks 3 3V I O Support The Virtex 4 architecture supports 3 3V single ended I O standards in all banks Reference Voltage Vref Pins Low voltage single ended I O standards with a differential amplifier input buffer require an input reference voltage Vggp Vggp is an external input into Virtex 4 devices Within each I O bank one of every 16 I O pins is automatically configured as a Vggp input if using a single ended I O standard requiring a differential amplifier input buffer Output Drive Source Voltage Vcco Pins Many of the low voltage I O standards supported by Virtex 4 devices require a different output drive voltage Vcco As a result each device often supports multiple output drive source voltages Output buffers within a given Vcco bank must share the same output drive source voltage The following input buffers use the Vcco voltage LVTTL LVCMOS PCI LVDCI and other DCI standards Virtex 4 User Guide www xilinx com 217 UGO070 v1 5 March 21 2006 218 Chapter 6 SelectlO Resources XILINX Virtex 4 Digitally Controlled Impedance DCI Introduction As FPGAs get bigger and system clock speeds get faster PC board design and manufacturing becomes more difficult With ever faster edge rates maintaining signal integrity becomes a critical issue PC board traces must be properly terminated to avoid reflections or ringing To terminate a trace resistors are traditionally added to make the output and or input ma
324. les are given in Table 4 4 www xilinx com Virtex 4 User Guide UGO070 v1 5 March 21 2006 XILINX Block RAM Attributes Table 4 4 Block RAM initialization Attributes Memory Location Attribute From To INIT_00 255 0 INIT 01 511 256 INIT 02 767 512 INIT OE 3839 3584 INIT OF 4095 3840 INIT 10 4351 4096 INIT 1F 8191 7936 INIT 20 8447 8192 INIT 2F 12287 12032 INIT 30 12543 12288 INIT 3F 16383 16128 Content Initialization INITP xx INITP xx attributes define the initial contents of the memory cells corresponding to DIP DOP buses parity bits By default these memory cells are also initialized to all zeros The eight initialization attributes from INITP 00 through INITP 07 represent the memory contents of parity bits Each INITP xx is a 64 digit hex encoded bit vector with a regular INIT xx attribute behavior The same formula can be used to calculate the bit positions initialized by a particular INITP xx attribute Output Latches Initialization INIT INIT A amp INIT B The INIT single port or INIT A and INIT B dual port attributes define the output latches values after configuration The width of the INIT INIT A amp INIT B attribute is the port width as shown in Table 4 5 These attributes are hex encoded bit vectors and the default value is 0 Output Latches Synchronous Set Reset SRVAL SRVAL A amp SRVAL B Virtex 4 User Guid
325. ligned to each other From a clock input CLKA the PMCD derives four output clocks a clock with the same frequency as the original CLKA 1 4 and the frequency Figure 3 3 illustrates the input CLKA and the derived clocks CLKA1 CLKA1D2 CLKA1D4 and CLKA1D8 CLKA1 is a delayed CLKA thus CLKA and CLKA1 are not deskewed CLKA1D2 CLKA1D4 and CLKA1D8 are rising edge aligned to CLKA1 CLKA1 reflects the duty cycle of CLKA 96 www xilinx com Virtex 4 User Guide UG070 v1 5 March 21 2006 XILINX PMCD Usage and Design Guidelines However the divided clocks CLKA1D2 CLKA1D4 and CLKA1D8 will have a 50 50 duty cycle regardless of the CLKA duty cycle CLKA L L i CLKA1 LJ Li Li Li LJ LJ L CLKA1D2 ij EN j CLKA1D4 ERE Lo CLKA1D8 l l l l Tpwiccko_CLKIN ug070 3 03 071404 Figure 3 3 PMCD Frequency Divider Matched Clock Phase A PMCD allows three additional input clocks CLKB CLKC CLKD to pass through the same delay as CLKA Thus the corresponding clock outputs CLKB1 CLKC1 and CLKD1 maintain the same phase relation to each other as well as the CLKA outputs CLKAT CLKA1D2 CLKA1D4 CLKA1D6 and CLKA1DS as their input By matching the delay inserted to all inputs a PMCD preserves the phase relation of its divided clock to other clocks in the design Figure 3 4 illustrates CLKA CLKB CLKC and CLKD with a 90 phase difference and t
326. llustrating a valid unidirectional termination technique for SSTL2 Class II 270 www xilinx com Virtex 4 User Guide UG070 v1 5 March 21 2006 XILINX Specific Guidelines for Virtex 4 I O Supported Standards External Termination IH Vi 1 25V Vat 125V Lou SSTL2 II SSTL2 II Rp Zo 50Q Rp Zo 500 Dd C 53 250 i Vper 1 25V L DCI IOB IOB Veco 2 5V Voco 2 5V 2Rypp 2Zg 1000 2Rypp 2Zg 1000 SSTL2_11_DCI onm Vper 1 25V Ro 25Q REF 2Rypy 2Zo 1000 E 2Rygw 2Zo 1002 ug070 6 58 071904 Figure 6 60 SSTL2 Class II with Unidirectional Termination Virtex 4 User Guide UGO070 v1 5 March 21 2006 www xilinx com 271 Chapter 6 SelectlO Resources XILINX Figure 6 61 shows a sample circuit illustrating a valid bidirectional termination technique for SSTL2 Class II External Termination OB Vaz 1 25V Vyr 1 25V OB SSTL2 II Rp Zo 500 SSTL2 II Rg 250 Rp Zo 500 Rg 250 Xw C Zo Wwv x Veer 1 25V DCI IOB IOB l l 2Rypp 2Zg 1002 i 2Rypp 2Zg 1002 me SSTL2 Il DCI OIDA Veer 1 25V Ro 250 2Rypy 2Zg 1000 E 2Rvan 2Zo 1000 l Veer 1 25V Rg 25Q l ug070_6_59_071904 Figure 6 61 SSTL2 Class ll with Bidirectional Termination 272 www xilinx com Virtex 4 User Guide UG070 v1 5 March 21 2
327. lock cycles to ensure all internal states are reset to the correct values During RESET RDEN and WREN must be held Low Operating Mode There are two operating modes in FIFO functions They differ only in output behavior after the first word is written to a previously empty FIFO Standard Mode After the first word is written into an empty FIFO the Empty flag deasserts synchronously with RDCLK After Empty is deasserted Low and RDEN is asserted the first word will appear at DO on the rising edge of RDCLK First Word Fall Through FWFT Mode After the first word is written into an empty FIFO it automatically appears at DO without asserting RDEN Subsequent Read operations require Empty to be Low and RDEN to be High Figure 4 16 illustrates the difference between standard mode and FWFT mode RDCLK TA RDEN EMPTY DO Sanda uunc cw car cz DO FWE eae WE ws S ug070 4 16 071204 Figure 4 16 Read Cycle Timing Standard and FWFT Modes Status Flags Empty Flag The Empty flag is synchronous with RDCLK and is asserted when the last entry in the FIFO is read When there are no more valid entries in the FIFO queue the read pointer will be frozen The Empty flag is deasserted at three in standard mode or four in FWFT mode read clocks after new data is written into the FIFO Virtex 4 User Guide www xilinx com 143 UGO070 v1 5 March 21 2006 144 Chapter 4 Block RAM XILINX Almost Empty Flag T
328. lock event 1 CE is asserted High e Four clock cycles and Tpgcko o after CE is asserted the output O begins toggling at the divide by three rate of the input I Tggcko o and other timing numbers are best found in the speed specification Note The duty cycle is not 50 50 for odd division The Low pulse is one cycle of I longer e At time event 2 CLR is asserted After Tgrpo crgo from time event 2 O stops toggling e At time event 3 CLR is deasserted e At time Tpncko o after clock event 4 O begins toggling again at the divided by three rate of I www xilinx com Virtex 4 User Guide UGO070 v1 5 March 21 2006 XILINX Clock Capable I O Clock Capable I O BUFR Use Models Regional Clocking Resources BUFRSs are ideal for source synchronous applications requiring clock domain crossing or serial to parallel conversion Unlike BUFIOs BUFRs are capable of clocking logic resources in the FPGAs other than the IOBs Figure 1 22 is a BUFR design example l O Tile 4 I O Tile 4 I O Tile 4 l O Tile 4 I O Tile 4 l O Tile 4 l O Tile 4 O Tile 1 1 0 Tile VO Tile 4 l O Tile 4 I O Tile 4 l O Tile 4 l O Tile 4 l O Tile 4 l O Tile 4 Virtex 4 User Guide UGO070 v1 5 March 21 2006 To Adjacent Region E PCLBs Tile gt CLBs DSP ICLBs l Tile PCLBs Qa 1a E i UJ UJ a o gt 2 SS To Center of Die a sw 95 E ie T O al el a 5 To Adjacent Region ug070 1 22 0802
329. ls I Os not used in FIFO Mode DIA AA 13 0 DO WEA 3 0 EMPTY RD_EN ENA ALMOST_EMPTY SSR SSRA RD_CLK gt CLKA DI DIB AB 13 0 WR EN WEBI 3 0 FULL ALMOST FULL RDCOUNT WRCOUNT WR CLK Logic UGO70 4 07 071204 Figure 4 7 Block RAM Implemented as a FIFO Byte Wide Write Enable Virtex 4 User Guide The byte wide write enable feature of the block RAM gives the capability to write eight bit one byte portions of incoming data There are four independent byte write enable inputs Each byte write enable is associated with one byte of input data and one parity bit All four byte write enable inputs must be driven in all data width configurations This feature is useful when using block RAM to interface with the PPC405 Byte write enable is not available in the Multi rate FIFO Byte write enable is further described in the Additional RAMB16 Primitive Design Considerations section Figure 4 8 shows the byte wide write enable logic When configured for a 36 bit or 18 bit wide data path any port can restrict writing to specified byte locations within the data word If configured in READ FIRST mode the DO bus shows the previous content of the whole addressed word In WRITE FIRST mode with identical Read and Write port widths DO shows only the enabled newly written byte s The other byte values must be ignored In WRITE FIRST mode with different widths for Read and Write ports all data on DO m
330. ls and does not disturb write operations on the other port Similar to the read and write operation the set reset function is active only when the enable pin of the port is active Set reset polarity is configurable active High by default This pin is not available when optional output registers are used Address Bus ADDR A B lt 14 gt The address bus selects the memory cells for read or write The width of the port determines the required address bus width for a single RAMB16 as shown in Table 4 2 Table 4 2 Port Aspect Ratio Port Data Width Port Address Width Depth ADDR Bus DI Bus DO Bus DIP Bus DOP Bus 1 14 16 384 13 0 0 NA 2 13 8 192 13 1 1 0 NA 4 12 4 096 132 3 0 NA 9 11 2 048 13 3 7 0 0 18 10 1 024 134 15 0 1 0 36 9 512 13 5 31 07 3 0 For cascadable block RAM the data width is one bit however the address bus is 15 bits 14 0 The address bit 15 is only used in cascadable block RAM Data and address pin mapping is further described in the Additional RAMB16 Primitive Design Considerations section Data In Buses DI A B lt 0 gt amp DIP A B lt 0 gt Data in buses provide the new data value to be written into RAM The regular data in bus DI and the parity data in bus DIP when available have a total width equal to the port width For example the 36 bit port data width is represented by DI lt 31 0
331. m the number of physical Vcco GND pin pairs Table 6 41 shows the number of equivalent Vcc5 GND pin pairs in each bank of each sparse chevron package Table 6 41 Equivalent Vcco GND Pairs per Bank Sparse Chevron Bank Number 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Package Virtex 4 LX Family FF1148 4 8 8 2 2 29 9 9 09 49 9 9 029 8 8 FF1513 3 1 1422 10 9 9 10 9 10 10 9 09 09 9 9 Virtex 4 SX Family FF1148 418 8 2 2 9 9 9 9 9 9 9 9 8 8 Virtex 4 FX Family FF672 2 2 2 2 2 8 8 8 8 2 Oe Meee eem eee eee egeta te FF1152 4 2 2 2 2 9 9 9 9 8 8 8 amp 1 sss ee ees qm FF1517 3 8 8 2 2 9 9 9 8 9 9 9 9 9 9 FF1704 4 8 8 2 2 9 9 9 10 10 10 10 10 9 9 9 9 Notes 1 These numbers are based on the parc files and device pinout Most of the limitations are based on the availability of GND pins in the vicinity of the bank There are a few instances where the limitation is due to Vcco pins 2 Bank 0 in all devices contains no user I O Therefore SSO analysis is unnecessary for Bank 0 Virtex 4 User Guide www xilinx com 297 UGO070 v1 5 March 21 2006 Chapter 6 SelectlO Resources 298 Nominal SSO Limit Tables Non Sparse Chevron 2 XILINX Table 6 42 provides the guidelines for the maximum number of simultaneously switching outputs allowed per output power gro
332. ment decrement number of tap delays CE Input 1 Enable increment decrement function RST Input 1 Reset delay element to pre programmed value If no value programmed reset to 0 O Output 1 Combinatorial output IDELAY Ports Data Input and Output and O The data input I is driven by its associated IOB i e input from the pin The IDELAY data output O can drive directly to the fabric to the registers in the ILOGIC block or to both Clock Input C All control inputs to IDELAY RST CE and INC are synchronous to the clock input C A clock must be connected to this port when IDELAY is configured in variable mode Module Reset RST The IDELAY reset signal RST resets the delay element to a value set by the IOBDELAY_VALUE attribute If the IOBDELAY_VALUE attribute is not specified a value of 0 is assumed The RST signal is an active High reset and is synchronous to the input clock signal C Increment Decrement Signals CE INC The increment decrement enable signal CE controls when an increment decrement function is to be performed As long as CE remains High IDELAY will increment or decrement by Typgr AYRESOLUTION every clock C cycle The state of INC determines whether IDELAY will increment or decrement INC 1 increments INC 0 decrements synchronously to the clock C If CE is Low the delay through IDELAY will not change regardless of the state of INC When CE is raised the increment d
333. ment is performed Instead the phase shift overflow status pin DO 0 is asserted to indicate this condition e Clock Event 2 One clock cycle after clock event 2 the CLKFX output stops toggling Within 257 to 260 clock cycles after this event the CLKFX stopped status DO 2 is asserted to indicate that the CLKFX output stops toggling e Clock Event 3 One clock cycle after clock event 3 the CLKFB output stops toggling Within 257 to 260 clock cycles after this event the CLKFB stopped status DO 3 is asserted to indicate that the CLKFB output stops toggling e Clock Event 4 One clock cycle after clock event 4 the CLKIN output stops toggling Within 257 to 260 clock cycles after this event DO 1 is asserted to indicate that the CLKIN output stops toggling Virtex 4 User Guide www xilinx com 91 UG070 v1 5 March 21 2006 Chapter 2 Digital Clock Managers DCMs XILINX Legacy Support The Virtex 4 device supports the Virtex II family and Virtex II Pro DCM primitives The mapping of Virtex II or Virtex II Pro DCM components to Virtex 4 DCM ADV components are as follows e CLKIN CLKFB PSCLK PSINDEC PSEN RST CLKO CLK90 CLK180 CLK270 CLK2X CLK2X180 CLKFX CLKFX180 CLKDV PSDONE LOCKED of Virtex 4 primitives DCM_BASE DCM_PS DCM_ADV map to the same corresponding pins of a Virtex II or Virtex II Pro DCM e Dynamic reconfiguration pins of Virtex 4 DCM ADV are not accessible when a Virtex II or Virtex II Pro D
334. metic logic includes an XOR gate that allows a 2 bit full adder to be implemented within a slice In addition a dedicated AND FAND or GAND gate shown in Figure 5 2 improves the efficiency of multiplier implementation CLB Slice Timing Models Virtex 4 User Guide Due to the large size and complexity of Virtex 4 FPGAs understanding the timing associated with the various paths and functional elements has become a difficult and important task Although it is not necessary to understand the various timing parameters to implement most designs using Xilinx software a thorough timing model can assist advanced users in analyzing critical paths or planning speed sensitive designs Three timing model sections are described e Functional element diagram basic architectural schematic illustrating pins and connections e Timing parameters definitions of Virtex 4 Data Sheet timing parameters e Timing Diagram illustrates functional element timing parameters relative to each other Use the models in this chapter in conjunction with both the Xilinx Timing Analyzer software TRCE and the section on switching characteristics in the Virtex 4 Data Sheet All pin names parameter names and paths are consistent with the post route timing and pre route static timing reports Most of the timing parameters found in the section on switching characteristics are described in this chapter All timing parameters reported in the Virtex 4 Data Sheet are
335. mit is calculated for each I O standard Bank SSO Limit ft drivers per Vcco GND pair x 8 Vecg GND pairs Bank SSO Limit 1 10 drivers per Vcco GND pair x 8 Vcco GND pairs 80 drivers Bank SSO Limit 2 8 drivers per Vcco GND pair x 8 Vcco GND pairs 64 drivers Bank SSO Limit 3 18 drivers per Vcco GND pair x 8 Vcco GND pairs 136 drivers The SSO contribution of each I O standard is calculated as SSO Contribution quantity of drivers Bank SSO limit SSO Contribution 1 22 80 27 5 SSO Contribution 2 6 64 9 3 SSO Contribution 3 19 136 14 0 Finally the bank SSO is calculated Bank 1 SSO SSO contribution 1 SSO contribution 2 SSO Contribution 3 27 5 9 3 14 0 50 9 Virtex 4 User Guide www xilinx com 305 UG070 v1 5 March 21 2006 306 Chapter 6 SelectlO Resources XILINX Calculation of Full Device SSO Three separate criteria must be satisfied for a full device design to be within the SSO limit The first criterion ensures the number of simultaneously switching outputs does not exceed the per bank limit The second criterion ensures even distribution of output drivers across the package A final criterion ensures overall power system disturbance in the chip is not excessive The SSO allowance is used in both of the latter two constraints taking into account design specific parameters The criteria are as follows e SSO for any single bank cannot exceed 100 e Average SSO of
336. most Full is asserted at the AFULL output pin of the FIFO Clock Event 2 Write Operation and Assertion of FULL Signal The FULL signal pin is asserted when the FIFO is full e At time Tppcy pr before clock event 2 WRCLK data 04 becomes valid at the DI inputs of the FIFO e Write enable remains asserted at the WREN input of the FIFO e At time Trcko FULL one clock cycle after clock event 2 WRCLK Full is asserted at the FULL output pin of the FIFO If the FIFO is full and a read followed by a write is performed the FULL signal remains asserted Clock Event 3 Write Operation and Assertion of Write Error Signal The write error signal pin is asserted when data going into the FIFO is not written because the FIFO is in a Full state e At time Tppck pr before clock event 3 WRCLK data 05 becomes valid at the DI inputs of the FIFO e Write enable remains asserted at the WREN input of the FIFO e At time Trcko wrerr after clock event 3 WRCLK a write error is asserted at the WRERR output pin of the FIFO Data 05 is not written into the FIFO Clock Event 4 Write Operation and Deassertion of Write Error Signal The write error signal pin is deasserted when a user stops trying to write into a full FIFO e At time Trcck wren before clock event 4 WRCLK write enable is deasserted at the WREN input of the FIFO e At time Trcko wnrnn after clock event 4 WRCLK write error is deasserted at the WRERR output pin of the FIFO T
337. mpletion of configuration can be delayed until after DCM locks to guarantee the system clock is established prior to initiating the device Frequency Synthesis The DCM provides several flexible methods for generating new clock frequencies Each method has a different operating frequency range and different AC characteristics The CLK2X and CLK2X180 outputs double the clock frequency The CLKDV output provides a divided output clock lower frequency with division options of 1 5 2 2 5 3 3 5 4 4 5 5 5 5 6 6 5 7 7 5 8 9 10 11 12 13 14 15 and 16 The DCM also offers fully digital dedicated frequency synthesizer outputs CLKFX and its opposite phase CLKFX180 The output frequency can be any function of the input clock frequency described by M D where M is the multiplier numerator and D is the divisor denominator The frequency synthesized outputs can drive the global clock routing networks within the device The well buffered global clock distribution network minimizes clock skew due to differences in distance or loading Frequency Synthesis Operation Virtex 4 User Guide The DCM clock output CLKFX is any M D factor of the clock input to the DCM Specifications for M and D as well as input and output frequency ranges for the frequency synthesizer are provided in the Virtex 4 Data Sheet Only when feedback is provided to the CLKFB input of the DCM is the frequency synthesizer output phase aligned to the clock outpu
338. n Driver with Termination to Vcco Single Termination Some I O standards e g HSTL Class IV require an output termination to Veco Figure 6 10 illustrates an output termination to Vcco Vcco IOB gt Q Zo Virtex 4 UGO70 6 10 071904 Figure 6 10 Driver with Termination to Vcco without DCI DCI can provide an output termination to Vcco using single termination In this case DCI only controls the impedance of the termination but not the driver Both GTL and HSTL standards need 50 Q external reference resistors The DCI I O standards supporting drivers with single termination are GTL_DCI GTLP_DCI HSTL IV DCI and HSTL IV DCI 18 222 www xilinx com Virtex 4 User Guide UG070 v1 5 March 21 2006 XILINX SelectlO Resources General Guidelines Figure 6 11 illustrates a driver with single termination inside a Virtex 4 device Voco I9 R Zo Virtex 4 DCI UG070_6_11_071904 Figure 6 11 Driver with Termination to Veco Using DCI Single Termination Driver with Termination to Vcco 2 Split Termination Some I O standards such as HSTL Class II require an output termination to Vcco 2 see Figure 6 12 gt qo Zo Virtex 4 UG070_6_12_071904 Figure 6 12 Driver with Termination to Vcco 2 without DCI DCI can provide output termination to Vcco 2 using split termination DCI only controls the impedance of the termination but not the driver Both HSTL and SSTL standards need
339. n Therefore access to PMCD inputs via a BUFGCTRL is limited to eight unique signals Other resources in the clock region will compete for the eight global clock tracks www xilinx com Virtex 4 User Guide UGO070 v1 5 March 21 2006 XILINX Application Examples PMCD to BUFGCTRL A PMCD can drive any BUFGCTRL in the same top bottom half of the chip PMCD to PMCD A dedicated local connection exists from the CLKA1D8 output of each PMCD to the CLKA input of any other PMCD within the same tile group of two Application Examples The Virtex 4 PMCD can be used in a variety of creative and useful applications The following examples show some of the common applications DCM and a Single PMCD A PMCD can be connected to a DCM to further divide a DCM clock Figure 3 7 illustrates this example Note the following guidelines e The DCM feedback CLKFB must be driven by the same frequency as CLKIN for 1X feedback Therefore the PMCD output corresponding to CLKO must be used to drive the CLKFB pin e The RST_DEASSERT_CLK attribute must be set to the PMCD input driven by CLKO When a DCM is connected to a PMCD all output clocks except CLKO and CLK2X are held Low until LOCKED is High Therefore setting RST DEASSERT CLK to the corresponding DCM feedback clock ensures a completed feedback loop Note CLK2X feedback is not supported DCM PMCD e CLKIN CLKA CLKA1 L gt CLKFB CLKB CLKA1D2 RST CLKA1D4
340. n a UCF file 2 Embed LOC constraints directly into HDL design files Inserting LOC Constraints in a UCF File The following syntax is used for inserting LOC constraints in a UCF file INST instance name LOC IDELAYCTRL_X Y Embedding LOC Constraints Directly into HDL Design Files The following syntax is used to embed LOC constraints into a Verilog design file synthesis attribute loc of instance name is IDELAYCTRL_X Y0 In VHDL code the LOC constraint is described with VHDL attributes Before it can be used the constraint must be declared with the following syntax attribute loc string Once declared the LOC constraint can be specified as attribute loc of instance name label is IDELAYCTRL_X Y0O This section describes the VHDL and Verilog use models for instantiating IDELAYCTRL primitives with LOC constraints VHDL Use Model Multiple instances of IDELAYCTRL primitives are instantiated Each instance has its own RST and RDY signal to allow for partial reconfiguration The REFCLK signal is common to all instances dlyctrl 1 IDELAYCTRL port map RDY gt rdy 1 REFCLK gt refclk RST gt rst 1 dlyctrl 2 1DELAYCTRL port map RDY gt rdy 2 REFCLK gt refclk RST gt rst_2 dlyctrl n IDELAYCTRL port map RDY rdy n REFCLK refclk 336 www xilinx com Virtex 4 User Guide UGO070 v1 5 March 21 2006 XILINX ILOGIC Resources RST gt rst_n
341. n addition changing the slew rate from fast to slow and or reducing the current drive could significantly reduce overshoot and undershoot The Virtex 4 PC Board Designers Guide contains additional design information to assist PCB designers and signal integrity engineers Regulating Vcco at 3 0V The following section discusses alternatives for managing overshoot and undershoot for LVTTL LVCMOS33 and PCI applications When Vcco is lowered to 3 0V the power clamp diode turns on at about 3 5V Therefore it limits any overshoot higher than 3 5V before reaching the absolute maximum level of 4 05V In addition instead of 0 3V when Vcco 3 75V the lower absolute maximum limit corresponding to Veco 3 0V is 1 05V In this case the ground clamp diode clips undershoot before reaching the lower absolute maximum limit As a result lowering Vcco to 3 0V addresses the overshoot and undershoot specifications for all supported 3 3 V standards including LVCMOS 33 LVTTL LVDCI 33 and PCI Mixing Techniques Virtex 4 User Guide Either using LVDCI 33 standard or lowering the Vcco to 3 0V is a good approach to address overshoot and undershoot It is also acceptable to combine both methods When Vccois lowered to 3 0V it is not necessary to adjust the reference resistors VRP and VRN The VRP and VRN values should always be the same as the board trace impedance www xilinx com 293 UGO070 v1 5 March 21 2006 Chapter 6 SelectlO Resources
342. n affects shift functionality An inactive clock enable pin does not shift data into the shift register and does not write new data Activating the clock enable allows the data in D to be written to the first location and all data to be shifted by one location When available new data appears on output pins Q and the cascadable output pin Q15 Address AO A1 A2 A3 Address inputs select the bit range 0 to 15 to be read The nth bit is available on the output pin Q Address inputs have no effect on the cascadable output pin Q15 it is always the last bit of the shift register bit 15 Data Out Q The data output Q provides the data value 1 bit selected by the address inputs Data Out Q15 optional The data output Q15 provides the last bit value of the 16 bit shift register New data becomes available after each shift in operation Inverting Control Pins The two control pins CLK CE have an individual inversion option The default is the rising clock edge and active High clock enable Global Set Reset GSR The global set reset GSR signal has no impact on shift registers Virtex 4 User Guide www xilinx com 205 UG070 v1 5 March 21 2006 Chapter 5 Configurable Logic Blocks CLBs XILINX Attributes Content Initialization INIT The INIT attribute defines the initial shift register contents The INIT attribute is a hex encoded bit vector with four digits 0000 The left most hexadecimal digit i
343. n que boe ite se cse QU er MR Regna 323 IDELAY VHDL and Verilog Instantiation Template 0 0 00 cee eee 324 IDELAYCTRL Overview eeren bisier ccc ee te tence en res 330 IDELAYCTRL Primitive 0 0 eee m a 330 IDELAY CT RIG PONS eem Ioco dace e eo di e oae woe tanta er ue eed eoa 330 IDELAYCTRLE Timing i24 n pe P c a d ce ee E ge P eaa 331 IDELAYCTRLELoc tiots 24 dct tm deret ced bee Rc Ib qne BAe eed Marinos i cd 333 IDELAYCTRL Usage and Design Guidelines eseeeeeeeeeeeee 333 OLOGIC Resources e elecce esek Ree rr ERE REA RE SA RE A R Aden 342 Combinatorial Output Data and 3 State Control Path llseleeeesss 344 Output DDR Overview ODDR ssseeeeee e 344 OPPOSITE EDGE Mode 0 0 ccc ce e c rs 344 SAME EDGE MOde 5 2 a Ee Rhea Ram Rte ct pe Rte ole etd 346 Glock Forwarding d eter HE Heber He derer eer dede 347 Output DDR Primitive ODDR lssseseeeeeeee r 347 ODDR VHDL and Verilog Templates 1 2 2 0 occ ence ene ee 348 ODDR VADL Template edis ceed slg ote dla ei ege tegere ue m weasel 348 ODDR Verilog Templates i dae bd aede ett a e acea 349 OLOGIC Timing Models 0 0 6 oc ee 349 Timing Characteristics 2 eet tee Dae eene dace ra ree 350 14 www xilinx com Virtex 4 User Guide UG070 v1 5 March 21 2006 2 XILINX Chapter 8 Advanced SelectlO Logic Resources Introduction corio Ee ibo he d EA dO pct ee eee is vare 355 Input Serial to Parallel Lo
344. nable module is enabled and both 358 www xilinx com Virtex 4 User Guide UGO070 v1 5 March 21 2006 X XILINX Input Serial to Parallel Logic Resources ISERDES CE1 and CE2 ports are available When NUM_CE 1 only CE1 is available and functions as a regular clock enable When CE1 and or CE2 are used as a clock disable not all data stored within the ISERDES chain is frozen Only the first two or four flip flops in the chain are connected to CE1 and CE2 Once CE1 and CE2 are set Low data in these registers fills the rest of the chain In DDR mode the last two bits read into the ISERDES block will be transferred to the even and odd outputs In DDR mode the bit order is dependent on the Bitslip function If the Bitslip function is not applied the last bit is sent to the even outputs and the next to last bit goes to the odd outputs If Bitslip is used this order can be reversed In SDR mode the last bit entered is propagated to all outputs and not dependent on the Bitslip operation High Speed Clock Input CLK The high speed clock input CLK is used to clock in the input serial data stream Divided Clock Input CLKDIV The divided clock input CLKDIV is typically a divided version of CLK depending on the width of the implemented deserialization It drives the output of the serial to parallel converter the delay element the Bitslip sub module and the CE module Serial Input Data from IOB D The serial input data port
345. namic reconfiguration address DADDR input bus provides a reconfiguration address for the dynamic reconfiguration When not used all bits must be assigned zeros The DO output bus will reflect the DCM s status See the Dynamic Reconfiguration chapter of the Virtex 4 Configuration Guide for more information www xilinx com Virtex 4 User Guide UGO070 v1 5 March 21 2006 XILINX DCM Ports Dynamic Reconfiguration Write Enable Input DWE The dynamic reconfiguration write enable DWE input pin provides the write enable control signal to write the DI data into the DADDR address When not used it must be tied Low See the Dynamic Reconfiguration chapter of the Virtex 4 Configuration Guide for more information Dynamic Reconfiguration Enable Input DEN The dynamic reconfiguration enable DEN input pin provides the enable control signal to access the dynamic reconfiguration feature When the dynamic reconfiguration feature is not used DEN must be tied Low When DEN is tied Low DO reflects the DCM status signals See the Dynamic Reconfiguration chapter of the Virtex 4 Configuration Guide for more information Clock Output Ports A DCM provides nine clock outputs with specific frequency and phase relationships When CLKEB is connected all DCM clock outputs have a fixed phase relationship to CLKIN When CLKFB is not connected the DCM outputs are not phase aligned However the phase relationship between all output clocks is preserved
346. nation It can also configure inputs to have the following types of on chip terminations 1 Input termination to Vcco Single Termination 2 Input termination to Vcco 2 Split Termination Thevenin equivalent For bidirectional operation both ends of the line can be DCI terminated permanently 1 Driver with termination to Vcco Single Termination 2 Driver with termination to Vcco 2 Split Termination Thevenin equivalent Alternatively bidirectional point to point lines can use controlled impedance drivers with 3 state buffers on both ends Controlled Impedance Driver Source Termination Virtex 4 User Guide Some I O standards such as LVCMOS must have a drive impedance matching the characteristic impedance of the driven line DCI can provide controlled impedance output drivers to eliminate reflections without an external source termination The impedance is set by the external reference resistors with resistance equal to the trace impedance The DCI I O standards supporting the controlled impedance driver are LVDCI 15 LVDCI 18 LVDCI 25 LVDCI 33 HSLVDCI 15 HSLVDCI 18 HSLVDCI 25 and HSLVDCI 33 Figure 6 4 illustrates a controlled impedance driver in a Virtex 4 device d gt a 2 UGO70 6 04 071404 Figure 6 4 Controlled Impedance Driver www xilinx com 219 UGO070 v1 5 March 21 2006 220 Chapter 6 SelectlO Resources XILINX Controlled Impedance Driver with Half Impedance Source Terminat
347. ns delay elements individual small buffers and control logic The incoming clock drives a chain of delay elements thus the output of every delay element represents a version of the incoming clock delayed at a different point The control logic contains a phase detector and a delay line selector The phase detector compares the incoming clock signal CLKIN against a feedback input CLKFB and steers the delay line selector essentially adding delay to the output of DCM until the CLKIN and CLKFB coincide Frequency Synthesis Separate outputs provide a doubled frequency CLK2X and CLK2X180 Another output CLKDV provides a frequency that is a specified fraction of the input frequency Two other outputs CLKFX and CLKFX180 provide an output frequency derived from the input clock by simultaneous frequency division and multiplication The user can specify any integer multiplier M and divisor D within the range specified in the DCM Timing Parameters section of the Virtex 4 Data Sheet An internal calculator determines the appropriate tap selection to make the output edge coincide with the input clock whenever mathematically possible For example M 9 and D 5 multiply the frequency by 1 8 and the output rising edge is coincident with the input rising edge after every fifth input period or after every ninth output period Phase Shifting The DCM allows coarse and fine grained phase shifting The coarse phase shifting uses the 90 18
348. nt Applied on Delay Element Applied on Value Combinatorial Output Path O Registered Output Path Q1 Q6 INONE No No IBUF Yes No IFD No Yes BOTH Yes Yes NUM CE Attribute The NUM CE attribute defines the number of clock enables CE1 and CE2 used The possible values are 1 and 2 default 1 SERDES MODE Attribute The SERDES MODE attribute defines whether the ISERDES module is a master or slave when using width expansion The possible values are MASTER and SLAVE The default value is MASTER See ISERDES Width Expansion ISERDES Width Expansion Two ISERDES modules are used to build a serial to parallel converter larger than 1 6 In every I O tile there are two ISERDES modules one master and one slave By connecting the SHIFTOUT ports of the master ISERDES to the SHIFTIN ports of the slave ISERDES the serial to parallel converter can be expanded to up to 1 10 DDR and 1 8 SDR Figure 8 3 illustrates a block diagram of a 1 10 DDR serial to parallel converter using the master and slave ISERDES modules Ports Q3 Q6 are used for the last four bits of the parallel interface on the slave ISERDES LSB to MSB Virtex 4 User Guide www xilinx com 361 UGO070 v1 5 March 21 2006 Chapter 8 Advanced SelectlO Logic Resources X XILINX SERDES_MODE MASTER Data Input Q1 S S Q2 ISERDE Q3 Master Q4 Data internal 0 5 5 e Q6 gt SHIFTOUT1 SHIFTOUT2 p SHIFTINI SHIFTI
349. ntended for bidirectional use The driver is identical to LVDCI while the input is identical to HSTL and SSTL By using a Vprr referenced input HSLVDCI allows greater input sensitivity at the receiver than when using a single ended LVCMOS type receiver Sample circuits illustrating both unidirectional and bidirectional termination techniques for an HSLVDCI controlled impedance driver are shown in Figure 6 29 and Figure 6 30 The DCI I O standards supporting a controlled impedance driver with a Vppp referenced input are HSLVDCI_15 HSLVDCI_18 HSLVDCI_25 and HSLVDCI_33 HSLVDCI HSLVDCI Ro Rynw Rypp Zo ug070 6 80 012106 Figure 6 33 HSLVDCI Controlled Impedance Driver with Unidirectional Termination 242 www xilinx com Virtex 4 User Guide UGO070 v1 5 March 21 2006 X XILINX Virtex 4 User Guide Specific Guidelines for Virtex 4 I O Supported Standards HSLVDCI IOB IOB HSLVDCI Ro Rynw RypP Zo D4 O 7e Vngr Vcco 2 Ro Rynw Rynp Zo ug070 6 81 012106 Figure 6 84 HSLVDCI Controlled Impedance Driver with Bidirectional Termination For output DC voltage specifications refer to the LVDCI Voz and Voy entries in Table 6 5 LVCMOS LVDCI and LVDCI_DV2 DC Voltage Specifications at Various Voltage References Table 6 6 lists the input DC voltage specifications when using HSLVDCI Valid values of Veco are 1 5V 1 8V 2 5V and 3 3
350. nts are specified in the Virtex 4 Data Sheet Once locked the DCM can tolerate input clock period variations of up to the value specified by CLKIN PER JITT DLL HF at high frequencies or CLKIN PER JITT DLL LF at low frequencies Larger jitter period changes can cause the DCM to lose lock indicated by the LOCKED output deasserting The user must then reset the DCM The cycle to cycle input jitter must be kept to less than CLKIN CYC JITT DLL LF in the low frequencies and CLKIN CYC JITT DLL HF for the high frequencies Input Clock Changes Changing the period of the input clock beyond the maximum input period jitter specification requires a manual reset of the DCM Failure to reset the DCM produces an unreliable LOCKED signal and output clock It is possible to temporarily stop the input clock and feedback clock with little impact to the deskew circuit as long as CLKFX or CLKFX180 is not used If the input clock is stopped and CLKFX or CLKFX180 is used the CLKFX or CLKFX180 outputs might stop toggling and DO 2 CLKFX Stopped is asserted The DCM must be reset to recover from this event The DO 2 CLKFX stopped status is asserted in 257 to 260 CLKIN cycles after CLKFX is stopped CLKFX does not resume and DO 2 will not deassert until the DCM is reset In any other case the clock should not be stopped for more than 100 ms to minimize the effect of device cooling otherwise the tap delays might change The clock should b
351. o tev MP IOB voco 1 5V 500 2 Rypp Zo 500 DX 2o 5 D4 4 Vngr 1 0V ug070 6 36 071904 Figure 6 38 GTLP DCI Internal Parallel Driver and Receiver Termination Table 6 12 lists the GTLP DC voltage specifications Table 6 12 GTLP DC Voltage Specifications Min Typ Max Vcco Veer N x Vrr 0 88 1 0 1 12 Ver 1 35 1 5 1 65 Vj Veer 0 1 0 98 1 1 Vi Vggp 0 1 0 9 1 02 Vou S VoL 0 3 0 45 0 6 lon at Vou mA E Ior at Vor mA at 0 6V 36 Ior at Vor mA at 0 3V B 48 Notes 1 N must be greater than or equal to 0 653 and less than or equal to 0 68 Table 6 13 details the allowed attributes that can be applied to the GTLP I O standards Table 6 13 Allowed Attributes of the GTLP I O Standards Attributes Input Output Bidirectional IOSTANDARD GTLP and GTLP DCI CAPACITANCE LOW NORMAL DONT CARE Virtex 4 User Guide www xilinx com 247 UGO070 v1 5 March 21 2006 Chapter 6 SelectlO Resources XILINX HSTL High Speed Transceiver Logic The High Speed Transceiver Logic HSTL standard is a general purpose high speed 1 5V or 1 8V bus standard sponsored by IBM EIA JESD8 6 This standard has four variations or classes To support clocking high speed memory interfaces a CSE differential version of this standard was added Virtex 4 I O supports all four classes and the differential version This stand
352. o Agypry after clock event 4 RDCLK almost empty is deasserted at the AEMPTY pin In the case of standard mode AEMPTY deasserts in the same way as in FWFT mode If the rising WRCLK edge is close to the rising RDCLK edge AEMPTY could be deasserted one RDCLK period later Case 2 Writing to a Full or Almost Full FIFO Prior to the operations performed in Figure 4 18 the FIFO is almost completely full In this example the timing diagram reflects of both standard and FWFT modes 1 2 3 4 WRCLK TFCCK_WREN TECCK WREN m WREN I TrFDCK DI TEpck pi lt lt TrDpck DI DI Co 7X jp 7X 0 X 09 XX 4 X j05 X po RDCLK l l l l l l l RDEN TFCKO_FULL l FULL AFULL TFCKO_WERR e TFCKO_WERR gt k WRERR Ik TrFcKO FULL 1 ug070 4 18 071204 Figure 4 18 Writing to a Full Almost Full FIFO Virtex 4 User Guide www xilinx com 151 UGO070 v1 5 March 21 2006 Chapter 4 Block RAM XILINX Clock Event 1 Write Operation and Assertion of Almost FULL Signal During a write operation to an almost full FIFO the Almost FULL signal is asserted e At time Tppcy pr before clock event 1 WRCLK data 00 becomes valid at the DI inputs of the FIFO e At time Trcck wren before clock event 1 WRCLK write enable becomes valid at the WREN input of the FIFO e At time Trcko ArurL one clock cycle after clock event 1 WRCLK Al
353. ock rate by any integer number from 1 to 8 This feature in conjunction with the programmable serializer deserializer in the IOB see Chapter 8 Advanced SelectIO Logic Resources allows source synchronous systems to cross clock domains without using additional logic resources A third type of clocking resource I O clocks are very fast and serve localized I O serializer deserializer circuits see Chapter 8 Advanced SelectIO Logic Resources Virtex 4 User Guide www xilinx com 19 UGO070 v1 5 March 21 2006 XILINX Chapter 1 Clock Resources Global Clocking Resources Global clocks are a dedicated network of interconnect specifically designed to reach all clock inputs to the various resources in an FPGA These networks are designed to have low skew and low duty cycle distortion low power and increased jitter tolerance They are also designed to support very high frequency signals Understanding the signal path for a global clock expands the understanding of the various global clock resources The global clocking resources and network consist of the following paths and components e Global Clock Inputs e Global Clock Buffers e Clock Tree and Nets GCLK e Clock Regions Global Clock Inputs Virtex 4 FPGAs contain specialized global clock input locations for use as regular user I Os if not used as clock inputs The number of clock inputs varies with the device size Smaller devices contain 16 clock inputs while l
354. of ground bounce Table 6 40 omits all I O standards that meet the no limit criteria Only I O standards with nominal SSO limits of eight or less are listed SSO limits for all I O standards are listed in the Virtex 4 SSO calculator available on the Xilinx website at http www xilinx com bvdocs userguides ug070 zip Table 6 41 lists the number of equivalent output Vcco GND pairs for each device package and I O bank Table 6 40 Spare Chevron Simultaneously Switching Output Limits per Equivalent Vcco GND Pair Sparse Chevron Limit Voltage loStandard FF672 FF676 FF1148 FF1152 FF1513 FF1517 FF1760 12V HSILI12 TBD HSTL IV 5 15V HSTL IV DCI 5 HSTL III 18 7 HSTL III DCL 18 7 18V HSTL IV 18 4 HSTL IV DCI 18 4 LVCMOS25 24 fast 6 2 5V LVDCI DV2 25250 7 296 www xilinx com Virtex 4 User Guide UG070 v1 5 March 21 2006 XILINX Simultaneous Switching Output Limits Table 6 40 Spare Chevron Simultaneously Switching Output Limits per Equivalent Vcco GND Pair 1 Sparse Chevron Limit FF672 FF676 FF1148 FF1152 FF1513 FF1517 FF1760 Voltage lOStandard LVCMOS33_24_fast LVTTL_24_slow GTL GTL_DCI GTLP GTLP_DCI 3 3V allaj alaj GC O Equivalent Vcco GND Pairs Sparse Chevron Since ground pins and Vcco pins are connected to common structures inside the package the number of effective Vcco GND pin pairs in a bank can differ fro
355. ogic Blocks CLBs XILINX Q15 SRLC16 Q15 SRLC16 OUT 40 bit SRL 9419 OUT 40 bit SRL Q15 SRLC16 Q15 SRLC16 UGO070 5 32 071504 Figure 5 32 40 bit Static Length Shift Register VHDL and Verilog Instantiation VHDL and Verilog instantiation templates are available for all primitives and submodules In VHDL each template has a component declaration section and an architecture section Each part of the template should be inserted within the VHDL design file The port map of the architecture section should include the design signal names The ShiftRegister C x with x 16 32 or 64 templates are cascadable modules and instantiate the corresponding SRLCXE primitive 16 or submodule 32 or 64 The ShiftRegister 16 template can be used to instantiate an SRL16 primitive VHDL and Verilog Templates In template nomenclature the number indicates the number of bits for example SHIFT REGISTER 16 is the template for the 16 bit shift register A C extension means the template is cascadable The following are templates for primitives e SHIFT REGISTER 16 e SHIFT REGISTER C 16 The following are templates for submodules e SHIFT REGISTER C 32 submodule SRLC32E SUBM e SHIFT REGISTER C 64 submodule SRLC64E SUBM The corresponding submodules have to be synthesized with the design 208 www xilinx com Virtex 4 User Guide UGO070 v1 5 March 21 2006
356. om the input driver to the FPGA fabric This path is used by software automatically when 1 There is a direct unregistered connection from input data to logic resources in the FPGA fabric 2 The pack I O register latches into IOBs is set to OFF Input DDR Overview IDDR Virtex 4 devices have dedicated registers in the ILOGIC to implement input double data rate DDR registers This feature is used by instantiating the IDDR primitive www xilinx com 311 UGO070 v1 5 March 21 2006 Chapter 7 SelectlO Logic Resources XILINX There is only one clock input to the IDDR primitive Falling edge data is clocked by a locally inverted version of the input clock All clocks feeding into the I O tile are fully multiplexed i e there is no clock sharing between ILOGIC or OLOGIC blocks The IDDR primitive supports the following modes of operation e OPPOSITE_EDGE mode e SAME EDGE mode e SAME EDGE PIPELINED mode The SAME EDGE and SAME EDGE PIPELINED modes are new for the Virtex 4 architecture These new modes allow designers to transfer falling edge data to the rising edge domain within the ILOGIC block saving CLB and clock resources and increasing performance These modes are implemented using the DDR CLK EDGE attribute The following sections describe each of the modes in detail OPPOSITE EDGE Mode A traditional input DDR solution or OPPOSITE EDGE mode is accomplished via a single input signal driving two registers IFF
357. ons as a clock mirror of a board level clock serving multiple devices This is achieved by driving the CLKO output off chip to the board and to other devices on the board and then bringing the clock back in as a feedback clock See the Application Examples section Taking advantage of the deskew feature greatly simplifies and improves system level design involving high fanout high performance clocks Clock Deskew Operation Virtex 4 User Guide The deskew feature utilizes the DLL circuit in the DCM In its simplest form the DLL consists of a single variable delay line containing individual small delay elements or buffers and control logic The incoming clock drives the delay line The output of every delay element represents a version of the incoming clock CLKIN delayed at a different point The clock distribution network routes the clock to all internal registers and to the clock feedback CLKFB pin The control logic contains a phase detector and a delay line selector The phase detector compares the incoming clock signal CLKIN against a feedback input CLKFB and steers the delay line selector essentially adding delay to the DCM output until the CLKIN and CLKFB coincide putting the two clocks 360 out of phase thus in phase When the edges from the input clock line up with the edges from the feedback clock the DCM achieves a lock The two clocks have no discernible difference Thus the DCM output clock compensates for the dela
358. or DATA I DATA LSB DATA LSB DATA I DATA LSB DATA I DATA LSB DATA I 3 b100 DATA LSB DATA LSB lt DATA I DATA LSB DATA I DATA LSB DATA I DATA LSB 1 bx endcase always SELECT case SELECT 3 b000 3 b001 3 b010 3 b011 3 b101 3 b110 3 b111 default T or DATA I DATA MSB DATA MSB DATA I DATA MSB DATA I DATA MSB DATA I 3 b100 DATA MSB DATA MSB lt DATA I DATA MSB lt DATA I DATA MSB DATA I DATA MSB 1 bx endcase MUXF7 instantiation MUXF7 U MUXF7 Il1 DATA MSB S SELECT I 3 O DATA O 3 endmodule SELECT I 2 0 DATA I 0 1 2 315 DATA I 4 OY Ul n DATA I 8 9 10 LLI DATA_I 12 131 14 15 IO0 DATA LSB 214 www xilinx com Virtex 4 User Guide UGO070 v1 5 March 21 2006 XILINX Chapter 6 SelectIO Resources l O Tile Overview Input output characteristics and logic resources are covered in three consecutive chapters Chapter 6 SelectIO Resources describes the electrical behavior of the output drivers and input receivers and gives detailed examples of many standard interfaces Chapter 7 SelectIO Logic Resources describes the input and output data registers and their Double Data Rate DDR operation and the programmable input delay IDELAY Chapter 8 Advanced SelectIO Logic
359. otherwise a single phase shift increment decrement is not guaranteed PSDONE is High for exactly one clock period when the phase shift is complete The time required to complete a phase shift operation varies As a result PSDONE must be monitored for phase shift status Between enabling PSEN and PSDONE is flagged the DCM output clocks will gradually change from their original phase shift to the incremented decremented phase shift The completion of the increment or decrement is signaled when PSDONE asserts High After PSDONE has pulsed High another increment decrement can be initiated Figure 2 6 illustrates the interaction of phase shift ports PSEN i PSDONE i Do ug070 2 06 071204 Figure 2 6 Phase Shift Timing Diagram When PSEN is activated after the phase shift counter has reached the maximum value of PHASE SHIFT the PSDONE will still be pulsed High for one PSCLK period some time after the PSEN is activated as illustrated in Figure 2 6 However the phase shift overflow pin STATUS 0 or DO 0 will be High to flag this condition and no phase adjustment is performed Phase Shift Overflow Virtex 4 User Guide The phase shift overflow DO 0 status signal is asserted when either of the following conditions are true The DCM is phase shifted beyond the allowed phase shift value In this case the phase shift overflow signal will be asserted High when the phase shift is decremented beyond 255 and incremented beyond
360. owable power system disturbance It is determined by dividing the user s maximum allowable power system disturbance VpISTURBANCE USER by the nominal maximum power system disturbance VDISTURBANCE USER is usually determined by taking the lesser of input undershoot voltage and input logic low threshold The Third Scaling Factor accounts for the capacitive loading of outputs driven by the FPGA It is based on the transient current impact of every additional picofarad of load capacitance above the assumed nominal For every additional 1 pF of load capacitance over the nominal approximately 9 mV of additional power system disturbance will occur The additional power system disturbance is compared to the nominal power system disturbance and a scale factor is derived from the relationship CLoap usr is the user s average load capacitance 7 www xilinx com 303 UG070 v1 5 March 21 2006 Chapter 6 SelectlO Resources XILINX Example calculations show how each scale factor is computed as well as the SSO allowance The system parameters used in this example are LPDS_USER 1 1 nH VDISTURBANCE_USER 200 mV CLOAD_USER 22 pF First Scaling Factor SF1 Lpps NoM Lpps UsER 1 0 nH 1 1 nH 0 909 Second Scaling Factor SF2 VpistuRBANCE_USER VDISTURBANCE NOM 550 mV 600 mV 0 917 Third Scaling Factor SF3 VprsrURBANCE NOM CroAp usen CtoAp Now X 9 mV pF VpistuURBANCE_NOM 600 mV 22 pF 15 pF x 9 mV pF
361. ows a sample circuit illustrating a valid termination technique for CSE differential SSTL2 Class II 2 5V with unidirectional DCI termination DCI IOB 10B Veco 25V Voco 2 5V DIFF_SSTL2_II_DCI 2Rypp 2Zg 1000 2Rypp 2Zg 1000 2Rypy 2Zg 1000 E 2Rymw 72297 1009 DIFF_SSTL2_II_DCI Ro 25Q Voco 2 5V Veco 25V DIFF SSTL2 Il DCI 2Rygp 2Zg 1000 2Rypp 2Zg 1000 t ZO 2 P41 4 2Rypy 2Zg 1000 E 2Rypy 2Zg 1000 Ro 950 VRN 0 VRN 0 ug070 6 61 071904 Figure 6 63 Differential SSTL2 2 5V Class II Unidirectional DCI Termination Figure 6 64 shows a sample circuit illustrating a valid termination technique for CSE differential SSTL2 Class II 2 5V with bidirectional termination External Termination Vira bee V r 1 25V DIFF SSTL Il 18 DIFF SSTL Il 18 500 P 250 250 Vay 1 25V Vaz 1 25V DIFF_SSTL_II_18 DIFF SSTL Il 18 250 500 500 250 DIFF_SSTL_II_18 DIFF SSTL Il 18 X QO 5 x X ug070_6_62_071904 Figure 6 64 Differential SSTL2 2 5V Class Il with Bidirectional Termination 274 www xilinx com Virtex 4 User Guide UG070 v1 5 March 21 2006 XILINX Specific Guidelines for Virtex 4 I O Supported Standards Figure 6 65 shows a sample circuit illustrating a valid termination technique for CSE differential SSTL2 Class II 2 5V with bidirectional DCI termination DIFF SSTL2 Il
362. phase relations and the skews of the respective inputs A PMCD can be used with other clock resources including global buffers and DCMs Together these clock resources provide flexibility in managing complex clock networks in designs In Virtex 4 devices the PMCDs are located in the center column Figure 3 1 shows a simplified view of the Virtex 4 center column resources The PMCDs are grouped with two PMCDs in one tile The PMCDs in each tile have special characteristics to support applications requiring multiple PMCDs Table 3 1 summarizes the availability of PMCDs in each Virtex 4 device www xilinx com 93 Chapter 3 Phase Matched Clock Dividers PMCDs Table 3 1 Available PMCD Resources Top Half BUFGCTRLs XILINX DCMs PMCDs Top Half I Os Top Half Virtex 4 BUFGCTRLs Bottom Half Bottom Half Bottom Half Center Column I Os PMCDs DCMs UG070_3_01_071304 Figure 3 1 PMCD Location in the Virtex 4 Device Device Available PMCDs Site Names XC4VLX15 0 No PMCDs in these devices XCAVSX25 XCAVFXI2 XC4VFX20 XCAVLX25 XC4VLX40 XC4VLX60 4 Bottom Half XC4VSX35 XCAVSX55 PMCD_X0Y0 PMCD_XOY1 one tile XCAVFX40 Top Half PMCD X0Y2 PMCD_XOY3 one tile XCA4VLX80 XCAVLX100 XC4VLX160 8 Bottom Half XCAVLX200 XCAVFX60 XC4VFX100 XC4VFX140 PMCD_X0Y0 PMCD_XOY1 one tile PMCD_X0Y2 PMCD_XOY3 one tile Top Half PMCD X0Y4 PMCD_XOY5 one tile PMCD
363. possible to the output driver or the input buffer thus eliminating stub reflections Xilinx DCI DCI uses two multi purpose reference pins in each bank to control the impedance of the driver or the parallel termination value for all of the I Os of that bank The N reference pin VRN must be pulled up to Vcco by a reference resistor and the P reference pin VRP must be pulled down to ground by another reference resistor The value of each reference resistor should be equal to the characteristic impedance of the PC board traces or should be twice that value configuration option When a DCI I O standard is used on a particular bank the two multi purpose reference pins cannot be used as regular I Os However if DCI I O standards are not used in the bank these pins are available as regular I O pins The Virtex 4 Packaging Specification gives detailed pin descriptions DCI adjusts the impedance of the I O by selectively turning transistors in the I Os on or off The impedance is adjusted to match the external reference resistors The impedance adjustment process has two phases The first phase compensates for process variations by controlling the larger transistors in the I Os It occurs during the device startup sequence The second phase maintains the impedance in response to temperature and supply voltage changes by controlling the smaller transistors in the I Os It begins immediately after the first phase and continues indefinitely even wh
364. put stays Low when the clock is disabled However when the clock is being disabled it completes the clock High pulse Since the clock enable line uses the CE pin of the BUFGCTRL the select signal must meet the setup time requirement Violating this setup time may result in a glitch Figure 1 6 illustrates the timing diagram for BUFGCE BUFGCE l N gt TaccdK ce BUFGCE CE 1 NY J BUFGCE O cm WE M TBcckO O ug070 1 06 082504 Figure 1 6 BUFGCE Timing Diagram BUFGCE 1 is similar to BUFGCE with the exception of its switching condition If the CE input is Low prior to the incoming falling clock edge the following clock pulse does not pass through the clock buffer and the output stays High Any level change of CE during the incoming clock Low pulse has no effect until the clock transitions High The output stays High when the clock is disabled However when the clock is being disabled it completes the clock Low pulse 26 www xilinx com Virtex 4 User Guide UGO070 v1 5 March 21 2006 XILINX Global Clocking Resources Figure 1 7 illustrates the timing diagram for BUFGCE_1 BUFGCE 1 l T gurges TT n o ooo I BUFGCE_1 0 TN AA T BCCKO_O ug070_1_07_081904 Figure 1 7 BUFGCE 1 Timing Diagram BUFGMUX and BUFGMUX 1 BUFGMUX is a clock buffer with two clock inputs one clock output and a select line This primitive is based on BUFGCTRL with some pins connected to logic
365. r Primitives Primitive Input Output Control BUFGCTRL I0 I1 O CEO CE1 IGNOREO IGNORE S0 S1 BUFG I O BUFGCE I O CE BUFGCE_1 I O CE BUFGMUX I0 I1 O S BUFGMUX 1 I0 I1 O S BUFGMUX_VIRTEX4 I0 11 O S Notes 1 All primitives are derived from a software preset of BUFGCTRL BUFGCTRL The BUFGCTRL primitive shown in Figure 1 1 can switch between two asynchronous clocks All other global clock buffer primitives are derived from certain configurations of BUFGCTRL The ISE software tools manage the configuration of all these primitives BUFGCTRL has four select lines S0 S1 CEO and CE1 It also has two additional control lines IGNOREO and IGNORE1 These six control lines are used to control the input I0 and I BUFGCTRL IGNORE1 CE1 o 10 SO CEO IGNOREO ug070 1 01 071204 Figure 1 1 BUFGCTRL Primitive BUFGCTRL is designed to switch between two clock inputs without the possibility of a glitch When the presently selected clock transitions from High to Low after S0 and S1 change the output is kept Low until the other to be selected clock has transitioned from High to Low Then the new clock starts driving the output The default configuration www xilinx com Virtex 4 User Guide UGO070 v1 5 March 21 2006 XILINX Virtex 4 User Guide Global Clocking Resources for BUFGCTRL is falling edge sensitive and held at Low prior to the input switching BUFG
366. r SSTL Class I 1 8V External Termination IOB IOB SSTL18_ SSTL18 Rg 200 BW D x Veer 0 9V ue ul ae eee L DCI IOB l OB Veco 1 8V z 2Rypp 2Zg 1000 SSTL18 DCI SSTL18 DCI Ok C Zo Ro 20Q Vaer 0 9V E 2Rypy 2Zg 1000 ug070 6 64 071904 Figure 6 66 SSTL18 1 8V Class I Termination 276 www xilinx com Virtex 4 User Guide UG070 v1 5 March 21 2006 XILINX Specific Guidelines for Virtex 4 I O Supported Standards SSTL18 Class II 1 8V Figure 6 67 shows a sample circuit illustrating a valid unidirectional termination technique for SSTL Class II 1 8V External Termination iOB Va 0 9V Vat 0 9V ig SSTL18 Il ee SSTL18 Il Rg 200 P 40 P 0 NN 40 D Veer 0 9V L DCI IOB IOB 2Rypp 2Zo 1002 2Rygp 2Zg 1002 SSTL18 Il DCI SSTL18 Il DCI 1 51 09 2 43 Vac 0 9V Ro 20Q REF 2Rypy 2Zo 1000 2Rypy 2Zo 1002 L ug070_6_65_071904 Figure 6 67 SSTL18 1 8V Class Il Unidirectional Termination Virtex 4 User Guide www xilinx com 277 UG070 v1 5 March 21 2006 Chapter 6 SelectlO Resources XILINX Figure 6 68 shows a sample circuit illustrating a valid bidirectional termination technique for SSTL 1 8V Class II External Termination ioB Vr 0 9V V 0 9V 10B SSTL18 II SSTL418 Il Rg 202 SRp 29 502 Bp Z29 500 Re
367. r Variable Delay Mode synthesis attribute IOBDELAY TYPE of Ul is VARIABLE synthesis attribute IOBDELAY VALUE of U1 is 0 synthesis translate off defparam U1 lIOBDELAY TYPE VARIABLE defparam U1 lIOBDELAY VALUE 0 synthesis translate on IDELAYCTRL Overview If the IDELAY or ISERDES primitive is instantiated with the IOBDELAY_TYPE attribute set to FIXED or VARIABLE the IDELAYCTRL module must be instantiated The IDELAYCTRL module continuously calibrates the individual delay elements IDELAY in its region see Figure 7 15 page 333 to reduce the effects of process voltage and temperature variations The IDELAYCTRL module calibrates IDELAY using the user supplied REFCLK IDELAYCTRL Primitive Figure 7 13 shows the IDELAYCTRL primitive IDELAYCTRL REFCLK RDY RST ug070 7 13 080104 Figure 7 13 IDELAYCTRL Primitive IDELAYCTRL Ports RST Reset The reset input pin RST is an active High asynchronous reset IDELAYCTRL must be reset after configuration and the REFCLK signal has stabilized to ensure proper IDELAY operation A reset pulse width TIDELAYCTRL gpw is required IDELAYCTRL must be reset after configuration B 330 www xilinx com Virtex 4 User Guide UGO070 v1 5 March 21 2006 X XILINX Virtex 4 User Guide ILOGIC Resources REFCLK Reference Clock The reference clock REFCLK provides a time reference to IDELAYCTRL to calibrate all IDELAY modules in the same
368. r deeper sizes consult the Creating Larger RAM Structures section Figure 4 6 shows the block RAM with the appropriate ports connected in the Cascadable mode The Additional Block RAM Features in Virtex 4 Devices section includes further information on cascadeable block RAMs www xilinx com UGO070 v1 5 March 21 2006 115 Chapter 4 Block RAM XILINX DI CASCADEOUT No Connect A DQ DQ A 13 0 A14 WE 3 0 RAM_EXTENSION UPPER 0 Output FF gt CASCADEIN of Top DI b CASCADEOUT of Bottom A 13 0 4 DQ P Alt DQ Optional RAM EXTENSION P Output FF LOWER 1 Ci D D r ij P CASCADEIN WE 3 8 0 Connect to logic High or Low Interconnect 4 Block RAM Figure 4 6 Cascadable Block RAM DO DO Not Used UG070_4_06_033005 116 www xilinx com Virtex 4 User Guide UG070 v1 5 March 21 2006 X XILINX Additional Block RAM Features in Virtex 4 Devices FIFO Support The block RAM can be configured as an asynchronous FIFO different clock on read and write ports or a synchronous FIFO In the FIFO mode the block RAM Port A is the FIFO read port while the block RAM Port B is the FIFO write port The supported configurations are 4K x 4 2K x 9 1K x 18 and 512 x 36 Figure 4 7 shows the block RAM I Os used for the FIFO implementation The Built in FIFO Support section contains further detai
369. r io I user i T gt user t 234 www xilinx com Virtex 4 User Guide UGO070 v1 5 March 21 2006 XILINX Specific Guidelines for Virtex 4 I O Supported Standards Verilog Template Example IOBUF module declaration module IOBUF O IO I T parameter CAPACITANCE DONT CARE parameter DRIVE 12 parameter IOSTANDARD LVCMOS25 parameter SLEW SLOW output O inout IO input I T tri0 GTS glbl GTS or O1 ts GTS T bufifO T1 IO I ts buf B1 O IO endmodule Example IOBUF instantiation IOBUF U IOBUF O user o IO user io I user i T user t Specific Guidelines for Virtex 4 I O Supported Standards The following sections provide an overview of the I O standards supported by all Virtex 4 devices While most Virtex 4 I O supported standards specify a range of allowed voltages this chapter records typical voltage values only Detailed information on each specification can be found on the Electronic Industry Alliance JEDEC web site at http www jedec org Virtex 4 User Guide www xilinx com 235 UGO070 v1 5 March 21 2006 Chapter 6 SelectlO Resources 236 XILINX LVTTL Low Voltage Transistor Transistor Logic The low voltage TTL LVTTL standard is a general purpose EIA JESDSA standard for 3 3V applications using an LVTTL input buffer and a push pull output buffer This standard requires a 3 3V input and output supply voltage
370. r mode the PHASE SHIFT is limited to 255 e If PERIODCLKIN XFINE SHIFT RANGE then the PHASE SHIFT in variable positive mode is limited to 255 In fixed and variable center mode the PHASE SHIFT is limited to 255 e For all previously described cases the direct mode is always limited to 1023 If the phase shift is limited by the FINE SHIFT RANCGE use the coarse grained phase shift to extend the phase shift range or set DCM PERFORAMANCE MODE attribute to MAX RANGE to increase the FINE SHIFT RANGE Figure 2 5 illustrates using CLK90 CLK180 and CLK270 outputs assuming FINE SHIFT RANGE 10 ns www xilinx com 73 UG070 v1 5 March 21 2006 Chapter 2 Digital Clock Managers DCMs XILINX 10 ns 10 ns 10 ns 10 ns For frequency gt 100 MHz period lt 10 ns CLKO PHASE_SHIFT 0 255 covers the c gt 4 whole range of period CLKO 100 MHz For frequency between 50 100 MHz period 10 20 ns At 50 MHz use CLKO PHASE_SHIFT 0 127 for the first 10 ns CLKO 50 MHz Use CLK180 with PHASE_SHIFT 0 127 for the next 10 ns CLK180 50 MHz ml For frequency between 25 50 MHz period 20 40 ns At 25 MHz use CLKO PHASE_SHIFT 0 63 for the first 10 ns CLKO25 mHz j Use CLK90 with PHASE_SHIFT 0 63 for the next 10 ns CLK90 25 MHz EE Use CLK180 with PHASE_SHIFT 0 63 for the next 10 ns CLK1 80 25 MHz EE Use CLK270 with PHASE_SHIFT 0 63 CLK270 25 MHz LL L1 O for t
371. r the GSR signal is deasserted www xilinx com 37 UG070 v1 5 March 21 2006 Chapter 1 Clock Resources XILINX BUFR Attributes and Modes Clock division in the BUFR is controlled in software through the BUFR_DIVIDE attribute Table 1 9 lists the possible values when using the BUFR_DIVIDE attribute Table 1 9 BUFR_DIVIDE Attribute Attribute Name Description Possible Values BUFR DIVIDE Defines whether the output clock is a 1 2 3 4 5 6 7 8 divided version of the input clock BYPASS default Notes 1 Location constraint is available for BUFR The propagation delay through BUFR is different for BUFR_DIVIDE 1 and BUFR DIVIDE BYPASS When set to 1 the delay is slightly more than BYPASS All other divisors have the same delay BUFR_DIVIDE 1 The phase relationship between the input clock and the output clock is the same for all possible divisions except BYPASS The timing relationship between the inputs and output of BUFR when using the BUFR DIVIDE attribute is illustrated in Figure 1 21 In this example the BUFR DIVIDE attribute is set to three Sometime before this diagram CLR was asserted 2 3 4 i Tp rap ouEEBSEMS EDDIE TBRDCK CE p wd d CLR 38 TBRCKO_O TBRDO_CLRO TBRCKO_O lt gt gt lt mi OT OO drlg f UGO070 1 21 030806 Figure 1 21 BUFR Timing Diagrams with BUFR DIVIDE Values In Figure 1 21 e At time Tgrpck cr before c
372. race impedance 10 percent to minimize overshoot and undershoot An IBIS simulation is advised for calculating the exact value needed for Ro Veco 3 3v o Ro Roriver IBUF_LVDCI_33 LVTTL B l LVCMOS Zym DU NypicaN Virtex 4 FPGA I O Device Driver OBUF_LVDCI_33 External Device ug070_6_77_071904 Figure 6 79 Connecting LVTTL or LVCMOS Using the LVDCI_33 Standard www xilinx com Virtex 4 User Guide UG070 v1 5 March 21 2006 XILINX Rules for Combining I O Standards in the Same Bank The connection scheme shown in Figure 6 80 is for a bidirectional bus scenario The signal performance may be degraded by Ro Therefore it is also recommended to verify the Ro value and performance with an IBIS simulation OBUFT LVDCI 33 gt me External Device IBUF LVDCI Virtex 4 FPGA ug070 6 78 071404 Figure 6 80 3 3V I O Configuration When designing with the LVDCI 33 standard e The output drive strength and slew rates are not programmable The output impedance references the VRP and VRN resistors and the output current is determined by the output impedance e If only LVDCI 33 inputs are used it is not necessary to connect VRP and VRN to external reference resistors The implementation pad report does not record VRP and VRN being used External reference resistors are required only if LVDCI 33 outputs are present in a bank e VDCI 33 is compatible with LVTTL and LVCMOS standards only I
373. rameters Clock Event 3 Read Operation and Assertion of Read Error Signal The read error signal pin is asserted when there is no data to be read because the FIFO is in an empty state e Read enable remains asserted at the RDEN input of the FIFO e At time Trcko RDERR after clock event 3 RDCLK read error is asserted at the RDERR output pin of the FIFO e Data 04 remains unchanged at the DO outputs of the FIFO Clock Event 4 Read Operation and Deassertion of Read Error Signal The read error signal pin is deasserted when a user stops trying to read from an empty FIFO e At time Trcck RDEN before clock event 4 RDCLK read enable is deasserted at the RDEN input of the FIFO e At time Trcko RDERR after clock event 4 RDCLK read error is deasserted at the RDERR output pin of the FIFO The read error signal is asserted deasserted at every read clock positive edge As long as both the read enable and empty signals are true read error will remain asserted Case 5 Resetting All Flags Virtex 4 User Guide RST WRCLK ail EM L L_ L L NEP RDCLK L LJ L L L L gt Treco EMPTY EMPTY le _TFco_AEMPTY AEMPTY gt l _ m Trco FuLL FULL __ m Trco AFULL AFULL ug070 4 21 071204 Figure 4 21 Resetting All Flags When the reset signal is asserted all flags are reset e At time Teco Empty after reset RST empty is asserted at the EMPTY output pin of the FIFO e At time Teco AgMpry
374. rch 21 2006 XILINX Global Clocking Resources Clock Regions Virtex 4 devices improve the clocking distribution by the use of clock regions Each clock region can have up to eight global clock domains These eight global clocks can be driven by any combination of the 32 global clock buffers The restrictions and rules needed in previous FPGA architectures are no longer applicable Specifically a clock region is not limited to four quadrants regardless of die device size Instead the dimensions of a clock region are fixed to 16 CLBs tall 32 IOBs and spanning half of the die Figure 1 17 By fixing the dimensions of the clock region larger Virtex 4 devices can have more clock regions As a result Virtex 4 devices can support many more multiple clock domains than previous FPGA architectures Table 1 6 shows the number of clock regions in each Virtex 4 device The logic resources in the center column DCMs IOBs etc are located in the left clock regions The DCMs if used utilize the global clocks in the left regions as feedback lines Up to four DCMs can be ina specific region If used in the same region IDELAYCTRL uses another global clock in that region The DCM companion module PMCD if directly connected to a global clock will also utilize the global clocks in the same region XC4VLX15 has 8 Clock Regions XC4VLX100 has 24 Clock Regions oo NN 2 L EOLBsj BCLBs 8CLBs All clock regions sp
375. receiver has an internal split thevenin termination powered from Vcco creating an equivalent Vyr voltage and termination impedance SSTL2 Il SSTL18 ll Usage Class II signaling uses Vrr Vcco 2 as a parallel termination voltage to a 50 Qresistor at the receiver and transmitter respectively A series resistor 25 Qat2 5V 20 Qat 1 8V must be connected to the transmitter output for a unidirectional link For a bidirectional link 25 Qseries resistors must connected the transmitters of the transceivers SSTL2 Il DCI SSTL18 ll DCI Usage The DCI circuits have a split thevenin termination powered from Vcco and an internal series resistor 25 Q at 2 5V 20 Q at 1 8V For a unidirectional link the series resistance is supplied only for the transmitter A bidirectional link has the series resistor for both transmitters DIFF SSTL2 Il DIFF SSTL18 Il Usage Differential SSTL 2 5V and 1 8V Class II pairs complementary single ended SSTL II type drivers with a differential receiver For a bidirectional link a series resistor must be connected to both transmitters DIFF SSTL2 Il DCI DIFF SSTL18 II DCI Usage Differential SSTL 2 5V and 1 8V Class II pairs complementary single ended SSTL II type drivers with a differential receiver including on chip differential termination For a bidirectional link a series resistor must be connected to both transmitters DCI can be used for unidirectional and bidirectional links 268 www xilinx com Virtex 4 User
376. reflected on the X Y output after a delay of length Tggg after clock event 2 Since the address 0 is still specified at clock event 2 the data on the DI input is reflected at the D output because it is written to register 0 Clock Event 3 Shift In Addressable Asynchronous READ All Read operations are asynchronous to the CLK signal If the address is changed between clock events the contents of the register at that address are reflected at the addressable output X Y outputs after a delay of length Ty o propagation delay through a LUT e At time Tps before clock event 3 the data becomes valid 1 at the DI input of the SRL and is reflected on the X Y output Tggg time after clock event 3 194 www xilinx com Virtex 4 User Guide UGO070 v1 5 March 21 2006 XILINX CLB Slice Timing Models e The address is changed from 0 to 2 some time after clock event 3 The value stored in register 2 at this time is a 0 in this example this was the first data shifted in and it is reflected on the X Y output after a delay of length Ty o Clock Event 16 MSB Most Significant Bit Changes At time Tyrac xp after clock event 16 the first bit shifted into the SRL becomes valid logical 0 in this case on the XB output of the slice via the MC15 output of the LUT SRL This is also applicable for the XMUX YMUX XB YB Cour and F5 outputs at time Twosco Twosx TwosxE and TwosvB after clock event 16 Slice Carry Chain Timing Model and Par
377. rial converters Virtex 4 User Guide www xilinx com 377 UGO070 v1 5 March 21 2006 Chapter 8 Advanced SelectlO Logic Resources Divided Clock Input CLKDIV This divided high speed clock input drives the parallel side of the parallel to serial converters This clock is the divided version of the clock connected to the CLK port Parallel Data Inputs D1 to D6 All incoming parallel data enters the OSERDES module through ports D1 to D6 These ports are connected to the FPGA fabric and can be configured from two to six bits i e a 6 1 serialization Bit widths greater than six up to 10 can be supported see OSERDES Width Expansion Output Data Clock Enable OCE OCE is an active High clock enable for the data path Parallel 3 state Inputs T1 to T4 2 XILINX All parallel 3 state signals enter the OSERDES module through ports T1 to T4 The ports are connected to the FPGA fabric and can be configured as one two or four bits 3 state Signal Clock Enable TCE TCE is an active High clock enable for the 3 state control path OSERDES Attributes The Table 8 8 lists and describes the various attributes that are available for the OSERDES primitive The table includes the default values Table 8 8 OSERDES Attribute Summary OSERDES Attribute DATA_RATE_OQ Description Defines whether data OQ changes at every clock edge or every positive clock Value String SDR or DDR Default Value
378. rocessed as single data rate SDR or double data rate DDR The allowed values for this attribute are SDR and DDR The default value is DDR DATA WIDTH Attribute The DATA WIDTH attribute defines the parallel data input width of the parallel to serial converter The possible values for this attribute depend on the DATA RATE OQ attribute When DATA RATE OQ is set to SDR the possible values for the DATA WIDTH attribute are 2 3 4 5 6 7 and 8 When DATA RATE OQ is set to DDR the possible values for the DATA WIDTH attribute are 4 6 8 and 10 When the DATA WIDTH is set to widths larger than six a pair of OSERDES must be configured into a master slave configuration See OSERDES Width Expansion SERDES MODE Attribute The SERDES MODE attribute defines whether the OSERDES module is a master or slave when using width expansion The possible values are MASTER and SLAVE The default value is MASTER See OSERDES Width Expansion TRISTATE WIDTH Attribute The TRISTATE WIDTH attribute defines the parallel 3 state input width of the 3 state control parallel to serial converter The possible values for this attribute depend on the DATA RATE TO attribute When DATA RATE TO is set to SDR or BUF the TRISTATE WIDTH attribute can only be set to 1 When DATA RATE TO is set to DDR the possible values for the TRISTATE WIDTH attribute are 2 or 4 TRISTATE WIDTH can not be set to widths larger than four Virtex 4 User Guide UGO070 v1
379. rs All limits for controlled impedance DCI I O standards assume a 50Q output impedance For higher reference resistor RR values less drive strength is needed and the SSO limit increases linearly To calculate the SSO limit for a controlled impedance driver with different reference resistors the following formula is used User SSO use Afo SSO Limit for Q Example The designer uses LVDCI 18 driver with 65 Qreference resistors The LVDCI 18 SSO limit for 50 Qimpedance is first taken from Table 6 42 The SSO limit for LVDCI 18 at 50 Qis 11 SSO per Vcco GND pin pair Therefore the SSO limit for LVDCI 18 at 65 Qis SSO Limit LVDCI 18 at 65 Q 65 Q 50 Q x 11 14 3 Bank O Bank 0 in all devices contains only configuration and dedicated signals Since there is no user I O in Bank 0 no SSO analysis is necessary for this bank www xilinx com Virtex 4 User Guide UG070 v1 5 March 21 2006 XILINX Chapter 7 SelectIO Logic Resources Introduction This chapter describes the logic directly behind the I O drivers and receivers covered in Chapter 6 SelectIO Resources Virtex 4 FPGAs contain all of the basic I O logic resources from Virtex II Virtex II Pro FPGAs These resources include the following e Combinatorial input output e 3 state output control e Registered input output e Registered 3 state output control e Double Data Rate DDR input output e DDR output 3 state control In addition the follow
380. rs after clock event 1 Clock Event 2 Read Operation All Read operations are asynchronous in distributed RAM As long as WE is Low the address bus can be asserted at any time The contents of the RAM on the address bus are reflected on the X Y outputs after a delay of length Tj o propagation delay through a LUT The address F is asserted after clock event 2 and the contents of the RAM at address F are reflected on the output after a delay of length Ty o Virtex 4 User Guide www xilinx com 191 UGO070 v1 5 March 21 2006 Chapter 5 Configurable Logic Blocks CLBs XILINX Slice SRL Timing Model and Parameters Available in SLICEM only Figure 5 24 illustrates shift register implementation in a Virtex 4 slice Some elements of the Virtex 4 slice have been omitted for clarity Only the elements relevant to the timing paths described in this section are shown Shift In COUT MUXFX FXINA gt C gt FX FXINB gt Lo Y ADDRESS gt YB G3 C gt G2 C gt YMUX G1 C gt G0 C gt BY DATA_IN or ADDRESS L F5 X ADDRESS gt XMUX F3 gt F2 gt F1L Fo gt L XB SR C gt CLK C gt BX gt e DATA IN or ADDRESS i Shift Out CIN UGO070 5 24 071504 Figure 5 24 Simplified Virtex 4 Slice SRL 192 www xilinx com Virtex 4 User Guide UGO070 v1 5 March 21 2006 XILINX Slice
381. rse vae rp Ea ed ua EY Ter EV PES PS CX RERO 113 Asynchronous Clocking oie vere e em eee e Reg ew ee Ri dece a 114 Synchronous Cl ckibg 1 ree bae Hee eto e e e erede AE E ect 114 Additional Block RAM Features in Virtex 4 Devices suussss 115 Optional Output Registers sisse 115 Independent Read and Write Port Width Selection 0000004 115 Cascadable Block RAM o ccrcisieridrrer reiden e ei err 115 EIEGQ SUpDOEL ui fier set tee tubae ete dat een Gear gael d t eee radius ds 117 Byte Wide Write Enable sssssssssss en 117 Block RAM Library Primitives 0 00 00 ccc ccc eee eee eens 118 Block RAM Port Signals 2i sodio ce eee bebe A ERA Ya E RR 119 Glock CEKNTA B 2 beet v tanana ER E DC E REFS ERAS ERES 119 Enable EN A D i erra c Era e e cre Cet Ee ceto tees 119 Write Enable WELA B eter Re qa y ur p TRE I ER ER PR 119 Register Enable REGCE A B ssssssssseee e 120 Set Reset SSR A B 5er RR RE RETIRER ne pr br Eu 120 Address Bus ADDR A B lt 14 gt sssssssssseeeee I 120 Data In Buses DI A B lt 0 gt amp DIP A B lt 0 gt 0 0 eee eee 120 Data Out Buses DO A B lt 0 gt and DOP A B lt 0 gt 00 00000 121 8 www xilinx com Virtex 4 User Guide UG070 v1 5 March 21 2006 2 XILINX Cascade CASCADEIN A B isssse I een 121 Cascade CASCADEOUT A B isse eee 121 Inverting Control Pins dise
382. rt Address Mapping Canoe 1 N A 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 n 10 9 8 7 6 5 4 3 2 1 0 2 15 14 13 12 1 10 9 8 7 6 5 4 xL 4 7 6 5 4 3 2 1 0 g 1 3 2 1 0 3 2 1 0 16 2 1 0 1 0 3244 0 0 Block RAM Attributes 122 All attribute code examples are shown in the Block RAM VHDL and Verilog Templates section Further information on using these attributes is available in the Additional RAMB16 Primitive Design Considerations section Content Initialization INIT xx INIT xx attributes define the initial memory contents By default block RAM memory is initialized with all zeros during the device configuration sequence The 64 initialization attributes from INIT 00 through INIT 3F represent the regular memory contents Each INIT xx is a 64 digit hex encoded bit vector The memory contents can be partially initialized and are automatically completed with zeros The following formula is used for determining the bit positions for each INIT xx attribute Given yy conversion hex encoded to decimal xx INIT xx corresponds to the memory cells as follows e from yy 1 256 1 e to yy 256 For example for the attribute INIT 1F the conversion is as follows e yy conversion hex encoded to decimal X 1F 31 e from 31 1 256 1 8191 e to31 256 7936 More examp
383. rting Control Pins For each port the five control pins CLK EN WE REGCE and SSR each have an individual inversion option Any control signal can be configured as active High or Low and the clock can be active on a rising or falling edge active High on rising edge by default without requiring other logic resources GSR The global set reset GSR signal of a Virtex 4 device is an asynchronous global signal that is active at the end of device configuration The GSR can also restore the initial Virtex 4 state at any time The GSR signal initializes the output latches to the INIT or to the INIT A and INIT B value see Block RAM Attributes A GSR signal has no impact on internal memory contents Because it is a global signal the GSR has no input pin at the functional level block RAM primitive Unused Inputs Unused Data and or address inputs should be connected to logic 1 Virtex 4 User Guide www xilinx com 121 UGO070 v1 5 March 21 2006 Chapter 4 Block RAM XILINX Block RAM Address Mapping Each port accesses the same set of 18 432 memory cells using an addressing scheme dependent on the width of the port The physical RAM locations addressed for a particular width are determined using the following formula of interest only when the two ports use different aspect ratios END ADDR 1 Width 1 START ADDR Width Table 4 3 shows low order address mapping for each port width Table 4 3 Po
384. rvrecterbFe cir LC duet s 45 Virtex 4 User Guide www xilinx com UGO070 v1 5 March 21 2006 X XILINX Verilog Template sereh sagecuitsueerereette e naa e bei quer aie Baai aTa 46 Declaring Constraints in UCF File 2 0 ce e 46 BUFGMUX_VIRTEX4 VHDL and Verilog Templates 000 46 VHDL Template edad ald aah desc pea saat acetates dye CCP E RD DI hd ee AU ae 46 Verilog Template oeste craba pEWI RA dpb weed pA Ur d eaae rds 47 Declaring Constraints in UCF File essel e 47 BUFIO VHDL and Verilog Templates sssssssseeeeeee 48 VHDL Template 22124 cer d betreut pi c eel et deae pub cte Sedi 48 Verilog Template seres stess erasa seg VR REA Iro er RES oun ebd rte poeti 48 Declaring Constraints in UCF File eeseeeeeeeeeeee teens 49 BUFR VHDL and Verilog Templates occ 49 VHDL Template i corde cbe EC Re UII PC OD b ek ae ed 49 Verilog Template inns sat ageu bv eee bewnered he eee bb dur Pr t eee peas 49 Declaring Constraints in UCF File eee e 50 Chapter 2 Digital Clock Managers DCMs DCM Summary icirss lt c e208 does s eons de LECCE ates Sect deat E arta d 51 DEM Primitives ooo recie es ee tbe Pr ena ed 54 DCM BASE Primitive 3 05 4 6080 5 ee ee ehe RE CP Y RR CERES ER 55 DCM PS Primitive cns rk Rer MEME EE Ded ne node sews 55 DCM ADV Primitive i c Ie Rx Rb RR E c EEG DER RE E A OPERAE d 55 DEM Ports on o ce ice cdi hd tent Pitt Hp deed abere de og 56 Clo
385. s 1 Zo is the recommended PCB trace impedance U90705013 0 1804 Figure 6 14 HSTL DCI Usage Examples 226 www xilinx com Virtex 4 User Guide UGO070 v1 5 March 21 2006 XILINX SelectlO Resources General Guidelines SSTL2 I or SSTL18 I SSTL2 Il or SSTL18 Il Vcco 2 Vcco 2 Conventional Vcco 2 DCI Transmit R Conventional Z Receive Q zo gt Vcco 2 Veco Conventional Transmit DCI Receive DCI Transmit DCI Receive Virtex 4 DCI Bidirectional 252 Virtex 4 Virtex 4 DCI DCI Wim ici vind Naso ata Roma eae Reference Resistor VRN 2 VRP R Zo VRN VRP R Zg Recommended 50 Q0 500 Zo Notes 1 The SSTL compatible 25Q series resistor is accounted for in the DCI buffer and it is not DCI controlled 2 Zo is the recommended PCB trace impedance ug070 6 15 071904 Figure 6 15 SSTL DCI Usage Examples Virtex 4 User Guide www xilinx com 227 UGO070 v1 5 March 21 2006 Chapter 6 SelectlO Resources XILINX LVDS 25 DCI and LVDSEXT 25 DCI Receiver Conventional Conventional Transmit DCI Receive Reference Resistor Recommended Zo Virtex 4 Virtex4 LVDS DCI VRN VRP R Zo NOTE Only LVDS25 DCI is supported Voco 2 5V only ug070 6 16 071904 Figure 6 16 LVDS DCI Usage Examples Virtex 4 SelectlO Primitives The Xilinx software library includes an extensive list of primitives to
386. s an extra pulse If S violates the Setup Hold requirements the output might pass the extra pulse but it will not glitch In any case the output will change to the new clock within three clock cycles of the slower clock The Setup Hold requirements for SO and S1 are with respect to the falling clock edge assuming INIT OUT 0 not the rising edge as for CEO and CE1 Switching conditions for BUFGMUX_VIRTEX4 are the same as the S pin of BUFGCTRL Figure 1 12 illustrates the timing diagram for BUFGMUX_VIRTEX4 ME iu LM cs l J Abes wj E cM I IN of IN 4 ___ Fe Teccko_o I TBccko Oo ug070 1 12 080204 Figure 1 12 BUFGMUX VIRTEXA4 Timing Diagram Other capabilities of the BUFGMUX_VIRTEX4 primitive are e Pre selection of I0 and I1 input after configuration e Initial output can be selected as High or Low after configuration Virtex 4 User Guide www xilinx com 29 UGO070 v1 5 March 21 2006 Chapter 1 Clock Resources XILINX Additional Use Models Asynchronous Mux Using BUFGCTRL In some cases an application requires immediate switching between clock inputs or bypassing the edge sensitivity of BUFGCTRL An example is when one of the clock inputs is no longer switching If this happens the clock output would not have the proper switching conditions because the BUFGCTRL never detected a clock edge This case uses the asynchronous mux Figure 1 13 illustrates an asynchronous mux with BUF
387. s changing Parasitic Factors Derating Method PFDM Virtex 4 User Guide This section describes a method to evaluate whether a design is within the SSO limits when taking into account the specific electrical characteristics of the user s unique system The SSO limits in Table 6 40 and Table 6 42 assume nominal values for the parasitic factors of the system These factors fall into three groups of electrical characteristics e PCB PDS parasitics nominal 1 nH per via e Maximum allowable power system disturbance voltage nominal 600 mV e Capacitive loading nominal 10 pF per load When the electrical characteristics of a design differ from the nominal values the system SSO limit changes The degree of difference determines the new effective limit for the design A figure called SSO Allowance is used as a single derating factor taking into account the combined effect of all three groups of system electrical characteristics The SSO allowance is a number ranging from 0 to 100 and is a product of three scaling factors The First Scaling Factor accounts for the PCB PDS parasitic inductance It is determined by dividing the nominal PCB PDS inductance by the user s PCB PDS inductance Lpps USR The PCB PDS inductance is determined based on a set of board geometries board thickness via diameter breakout trace width and length and any other additional structures including sockets The Second Scaling Factor accounts for the maximum all
388. s must be stable at the F G inputs of the slice LUT configured as RAM Tws Twu WE input SR Time before the clock that the write enable signal must be stable at the WE input of the slice LUT configured as RAM Clock CLK Twc Minimum clock period to meet address write cycle time Distributed RAM Timing Characteristics The timing characteristics of a 16 bit distributed RAM implemented in a Virtex 4 slice LUT configured as RAM are shown in Figure 5 23 1 2 3 4 5 6 7 l Output l WRITE READ WRITE WRITE WRITE READ UGO070 5 23 080204 Figure 5 23 Slice Distributed RAM Timing Characteristics 190 www xilinx com Virtex 4 User Guide UG070 v1 5 March 21 2006 XILINX CLB Slice Timing Models Clock Event 1 Write Operation During a Write operation the contents of the memory at the address on the ADDR inputs are changed The data written to this memory location is reflected on the X Y outputs synchronously e At time Tyg before clock event 1 the write enable signal WE becomes valid high enabling the RAM for the following Write operation e At time T s before clock event 1 the address 2 becomes valid at the F G inputs of the RAM e Attime Tps or Tcycx before clock event 1 the DATA becomes valid 1 at the DI input of the RAM and is reflected on the X XMUX output at time TsficKo after clock event 1 This is also applicable to the XMUX YMUX XB YB Cour and F5 outputs at time Twosco Twosx TwosxRB TwosyB and Tsucko
389. s that can also be applied to the GTL I O standards Table 6 11 Allowed Attributes of the GTL I O Standards Primitives Attributes IBUF IBUFG OBUF OBUFT IOBUF IOSTANDARD GTL and GTL_DCI CAPACITANCE LOW NORMAL DONT_CARE GTLP Gunning Transceiver Logic Plus The Gunning Transceiver Logic Plus or GTL standard is a high speed bus standard JESD8 3 first used by the Pentium Pro Processor This standard requires a differential amplifier input buffer and a open drain output buffer The negative terminal of the differential input buffer is referenced to the Vpgr pin A sample circuit illustrating a valid termination technique for GTL with external parallel termination and unconnected Veco is shown in Figure 6 37 IOB B 1OB Var 15V Vrr 15V Veco Unconnected i ci ia i i a f 25 89 x l aL Vper 1 0V ug070 6 35 071904 Figure 6 37 GTL with External Parallel Termination and Unconnected Vcco GTLP DCI Usage GTL does not require a Veco voltage However for GTLP_DCI Veco must be connected to 1 5V GILP DCI provides single termination to Veco for inputs or outputs 246 www xilinx com Virtex 4 User Guide UGO070 v1 5 March 21 2006 XILINX Specific Guidelines for Virtex 4 I O Supported Standards A sample circuit illustrating a valid termination technique for GTLP_DCI with internal parallel driver and receiver termination is shown in Figure 6 38 Voc
390. s the most significant bit By default the shift register is initialized with all zeros during the device configuration sequence but any other configuration value can be specified Location Constraints Each CLB resource has four slices S0 S1 S2 and S3 As an example in the bottom left CLB resource each slice has the coordinates shown in Table 5 15 Table 5 15 Slice Coordinates in the Bottom Left CLB Resource Slice 3 Slice 2 Slice S1 Slice S0 X1Y1 X0Y1 X1YO X0YO To constrain placement shift register instances can have LOC properties attached to them Each 16 bit shift register fits in one LUT A 32 bit shift register in static or dynamic address mode fits in one slice two LUTs and one MUXF5 This shift register can be placed in SLICEM only A 64 bit shift register in static or dynamic address mode fits in two slices These slices are S0 and S2 Figure 5 30 illustrates the position of the four LUTs in a CLB resource The dedicated CLB shift chain runs from the top slice to the bottom slice The data input pin must either be in slice S0 or in S2 The address selected as the output pin Q is the MUXF6 output D l l l l l l l l l l l i output SRLC64E l l l l l l l l SRLC64E Slice SO CLB FO MICI SI UGO070 5 30 122205 Figure 5 30 Shift Register Placement 206 www xilinx com Virtex 4 User Guide UG070 v1 5 March 21 2006 XILINX Shift Regist
391. same top bottom half of the device DCM to BUFGCTRL Any DCM clock output can drive any BUFGCTRL input in the same top bottom half of the device There are no restrictions on how many DCM outputs can be used simultaneously BUFGCTRL to DCM Any BUFGCTRL can drive any DCM in the Virtex 4 devices However only up to eight dedicated clock routing resources exist in a particular clock region Since the clock routing is accessed via the BUFGCTRL outputs this indirectly limits the BUFGCTRL to DCM connection If eight BUFGCTRL outputs are already accessing a clock region and a DCM is in that region then no additional BUFGCTRL can be used in that region including a connection to the FB pin of the DCM DCM To and From PMCD Refer to the PMCD chapter Phase Matched Clock Dividers PMCDs Application Examples The Virtex 4 DCM can be used in a variety of creative and useful applications The following examples show some of the more common applications Virtex 4 User Guide www xilinx com 7T UGO070 v1 5 March 21 2006 Chapter 2 Digital Clock Managers DCMs Standard Usage 2 XILINX The circuit in Figure 2 7 shows DCM_BASE implemented with internal feedback and access to RST and LOCKED pins This example shows the simplest use case for a DCM IBUFG DCM_BASE CLKO V IBUF CLK90 CLK180 CLK270 CLK2X CLK2X180 V 78 CLKDV CLKFX CLKFX180 LOCKED Figure 2 7 Standard Usage www xilinx com
392. se chevron pinout style is an improvement over previous designs offering lower crosstalk and SSO noise The pinout is designed to minimize PDS inductance and keep I O signal return current paths very closely coupled to their associated I O signal The maximum ratio of I O to Veco GND pin pairs in sparse chevron packages is 8 1 For this reason most of the SSO limits those higher than eight per Vcco GND pair are moot for sparse chevron packages The SSO limits table Table 6 40 reflects this Only I O standards with limits less than eight per Vcco GND pair appear in the table All the other I O standards are designated no limit for the nominal PCB case For boards that do not meet the nominal PCB requirements listed in Nominal PCB Specifications the Virtex 4 SSO calculator is available containing all SSO limit data for all I O standards For designs in nominal PCBs mixing limited and no limit I O standards the Virtex 4 SSO calculator must be used to ensure that I O utilization does not exceed the limit Information on the calculator is available under the Full Device SSO Calculator section Nominal PCB Specifications The nominal SSO tables Table 6 40 and Table 6 42 contain SSO limits for cases where the PCB parameters meet the following requirements In cases where PCB parameters do not meet all requirements listed below the Virtex 4 SSO Calculator must be used to determine the SSO limit according to the physical factors of the
393. ss HT 1 8V iiu ces Re RE AREE ReERA ERR RR ea ake EA 264 HSTL Class IV 1 8V ies cet e Ree hex XR Red 265 SSTL Stub Series Terminated Logic 6c cece eee eens 268 SSTE2 D SSTb18 VU sages 34 i635 ces hae date genase E D eae 268 SSTL2_I_DCI SSTL18_I_DCI Usage 6 cee eee een ene 268 SSTLE2 II SSTEIS IL USage sa it xe er Ee cs ee islet a6 Ree alec 268 SSIL2 II DCLSSTIL18 Il DCI Usage esee 268 DIFF SSTL2 IL DIFF_SSTL18_II Usage seeeeee eee eee 268 DIFF SSTL2 II DCI DIFF SSTLI8 II DCI Usage 1 6 cece ee ee eee 268 SSTI2ClassI 2 V eee RR eek ee ea ee RE RRA 269 SSTL Class IT 2 5V esis hey dock hace Re ON db ER EXPERS EN oh yale Se 270 Complementary Single Ended CSE Differential SSTL2 Class II 2 5V 273 SSTL18 Class I1 1 8V 24 rese siae ehh Ce eer Reed epp arid sakes 276 SSTL18 Class U 1 8V 2 0 ccc e me 277 Complementary Single Ended CSE Differential SSTL Class II 1 8V 279 Differential Termination DIFF TERM Attribute 0 00000 cece eee 282 LVDS and Extended LVDS Low Voltage Differential Signaling 282 Transmitter Termination 0 0 0000 c cc erras 283 Receiver Termination ss resser tere tentene na eee eee hehe 283 HyperTransport Protocol LDT serren 0 cece eee 284 BLVDS Bus LVDS wie secs sew ae RR RERRERAA LERRA ewes CER GRE d a a 285 CSE Differential LVPECL Low Voltage Positive Emitter Coupled Logic 285 LVPECL Transc
394. st 20 LVCMOS18 6 fast 15 LVCMOS18 8 fast 11 LVCMOS18 12 fast 9 LVCMOS18 16 fast 7 LVDCI 18 50 Q 11 LVDCI DV2 1825 Q 5 HSLVDCI 18 50 Q 11 HSITL I 18 16 HSTL I DCI 18 16 HSTL II 18 8 HSTL II DCI 18 8 HSTL III 18 6 HSTL III DCI 18 6 HSITL IV 18 3 HSTL IV DCI 18 3 SSTL18 I 20 SSTL18 I DCI 20 SSTL18 II 13 SSTL18 II DCT 13 DIFF HSTL II 18 8 DIFF HSTL II DCI 18 8 DIFF SSTLIS8 II 12 DIFF SSTL18 II DCI 12 www xilinx com 299 Chapter 6 SelectlO Resources 2 XILINX Table 6 42 Non Sparse Chevron Simultaneously Switching Output Limits per Equivalent Vcco GND Pair Continued Voltage 2 5V 300 Non Sparse Chevron Limit lOStandard SF363 and FF668 Packages LVCMOS25 2 slow 68 LVCMOS25 4 slow 41 LVCMOS25 6 slow 29 LVCMOS25 8 slow 22 LVCMOS25 12 slow 15 LVCMOS25 16 slow 11 LVCMOS25 24 slow 7 LVCMOS25 2 fast 40 LVCMOS25 4 fast 24 LVCMOS25 6 fast 17 LVCMOS25 8 fast 13 LVCMOS25 12 fast 10 LVCMOS25 16 fast 8 LVCMOS25 24 fast 5 LVDCI 25 50 Q 13 LVDCI DV2 2525 Q 6 HSLVDCI 25 50 Q 13 SSTL2_I 15 SSTL2_I_DCI 15 SSTL2 II 10 SSTL2 II DCI 10 DIFF SSTL2 II 10 DIFF SSTL2 II DCI 10 LVPECL 25 8 BLVDS 25 8 www xilinx com Virtex 4 User Guide UG070 v1 5 March 21 2006 XILINX Simultaneous Switching Output Limits Table 6 42 Non Sparse Chevron Simultaneously Switching Output Limits per Equivalent Vcco GND Pair Continue
395. strates the general timing characteristics of a Virtex 4 slice 1 2 3 CEK F WS UC amp KH E Tceck CE rd Tbpick Trxck D FX DATA lt Tsrck SR RESET Tcko I Tcko YQ OUT 1 1 1 UGO70 5 21 080204 Figure 5 21 General Slice Timing Characteristics e At time TcRcK before clock event 1 the clock enable signal becomes valid high at the CE input of the slice register e At time Tpjck or Tpxcy before clock event 1 data from either BX BY FXINA or FXINB inputs become valid high at the D input of the slice register and is reflected on either the XO or YO pin at time Tcxo after clock event 1 e Attime Tanck before clock event 3 the SR signal configured as synchronous reset in this case becomes valid high resetting the slice register This is reflected on the XO or YQ pin at time Toyo after clock event 3 188 www xilinx com Virtex 4 User Guide UG070 v1 5 March 21 2006 XILINX CLB Slice Timing Models Slice Distributed RAM Timing Model and Parameters Available in SLICEM only Figure 5 22 illustrates the details of distributed RAM implemented in a Virtex 4 slice Some elements of the Virtex 4 slice are omitted for clarity Only the elements relevant to the timing paths described in this section are shown COUT MUXFX FXINA C gt gt FXINB gt EEX YMUX ADDRESS 54 T ae BY D gt DATA_IN or Address SLIC
396. support a variety of I O standards available in the Virtex 4 I O primitives The following are five generic primitive names representing most of the available single ended I O standards 228 IBUF input buffer IBUFG clock input buffer OBUF output buffer OBUFT 3 state output buffer IOBUF input output buffer www xilinx com Virtex 4 User Guide UG070 v1 5 March 21 2006 XILINX Virtex 4 SelectlO Primitives These five generic primitive names represent most of the available differential I O standards e IBUFDS input buffer e IBUFGDS clock input buffer e OBUFDS output buffer e OBUFTDS 3 state output buffer e IOBUFDS input output buffer IBUF and IBUFG OBUF Virtex 4 User Guide Signals used as inputs to Virtex 4 devices must use an input buffer IBUF The generic Virtex 4 IBUF primitive is shown in Figure 6 17 IBUF IBUFG Input O Output From device pad into FPGA ug070 6 17 071904 Figure 6 17 Input Buffer IBUF IBUFG Primitives The IBUF and IBUFG primitives are the same IBUFGs are used when an input buffer is used as a clock input In the Xilinx software tools an IBUFG is automatically placed at clock input sites An output buffer OBUF must be used to drive signals from Virtex 4 devices to external output pads A generic Virtex 4 OBUF primitive is shown in Figure 6 18 OBUF Input O Output From FPGA to device pad ug070 6 18 071904 Figure 6 18 Output Buffer
397. t WRADDR lt 8 0 gt RDADDR lt 8 0 gt STATUS lt 1 0 gt ug070 4 ECC 022204 Figure 4 25 RAMB32 S64 ECC Block RAM ECC Primitive 158 www xilinx com Virtex 4 User Guide UGO070 v1 5 March 21 2006 XILINX Built in Block RAM Error Correction Code Block RAM ECC Port Description Table 4 15 lists and describes the block RAM ECC I O port names Table 4 15 Block RAM ECC Port Names and Descriptions Port Name Direction Signal Description DI lt 63 0 gt Input Data input bus WRADDR lt 8 0 gt Input Write address bus RDADDR lt 8 0 gt Input Read address bus WREN Input Write enable When WREN 1 data will be written into memory When WREN 0 write is disabled RDEN Input Read enable When RDEN 1 data will be read from memory When RDEN 0 read is disabled SSR Input Not supported when using the block RAM ECC primitive Always connect to GND WRCLK Input Clock for write operations RDCLK Input Clock for read operations DO lt 63 0 gt Output Data output bus STATUS 1 0 0 Output Error status bus Notes 1 Hamming code implemented in the block RAM ECC logic detects one of three conditions no detectable error single bit error detected and corrected on DO but not corrected in the memory and double bit error detected without correction The result of STATUS 1 0 indicates these three conditions Virtex 4 User Guide www xilinx com 159 UGO070 v1 5 March 21 2
398. t The CLKA1D4 output has the frequency of CLKA divided by four CLKA1D4 is rising edge aligned to CLKA1 Virtex 4 User Guide www xilinx com 95 UG070 v1 5 March 21 2006 Chapter 3 Phase Matched Clock Dividers PMCDs XILINX Table 3 2 PMCD Port Description Continued Port Name Direction Description CLKA1D8 Output The CLKA1D8 output has the frequency of CLKA divided by eight CLKA1DS is rising edge aligned to CLKA1 CLKB1 Output The CLKB1 output has the same frequency as the CLKB input a delayed version of CLKC1 CLKB The skew between CLKB1 and CLKA1 is the same as the skew between CLKB CLKD1 and CLKA inputs Similarly CLKC1 is a delayed version of CLKC and CLKD1 is a delayed version of CLKD Table 3 3 lists the PMCD attributes Table 3 3 PMCD Attributes PMCD Attribute Name Description Values Default Value RST_DEASSERT_CLK This attribute allows the deassertion of the String CLKA RST signal to be synchronous to a selected CLKA CLKB CLKC PMCD input clock or CLKD EN_REL This attribute allows for CLKA1D2 Boolean FALSE CLKA1D4 and CLKA1D8 outputs to be FALSE TRUE released at REL signal assertion Note REL is synchronous to CLKA input PMCD Usage and Design Guidelines This section provides a detailed description for using the Virtex 4 PMCD and design guidelines Phase Matched Divided Clocks A PMCD produces binary divided clocks that are rising edge a
399. t CLKO The internal operation of the frequency synthesizer is complex and beyond the scope of this document As long as the frequency synthesizer is within the range specified in the Virtex 4 Data Sheet it multiplies the incoming frequencies by the pre calculated quotient M Dand generates the correct output frequencies For example assume an input frequency of 50 MHz M 25 and D 8 M and D values do not have common factors and cannot be reduced The output frequency is 156 25 MHz although separate calculations 25 x 50 MHz 1 25 GHz and 50 MHz 8 6 25 MHz seem to produce separate values outside the range of the input frequency www xilinx com 71 UGO070 v1 5 March 21 2006 72 Chapter 2 Digital Clock Managers DCMs XILINX Frequency Synthesizer Characteristics e The frequency synthesizer provides an output frequency equal to the input frequency multiplied by M and divided by D e The outputs CLKFX and CLKFX180 always have a 50 50 duty cycle e Smaller M and D values achieve faster lock times Whenever possible divide M and D by the largest common factor to get the smallest values e g if the required CLKFX 9 6 x CLKIN instead of using M 9 and D 6 use M 3 and D 2 e When CLKFB is connected CLKFX is phase aligned with CLKO every D cycles of CLKO and every M cycles of CLKFX if M D is a reduced fraction Phase Shifting The DCM provides coarse and fine grained phase shifting For coarse phase con
400. t is used to guarantee non positive hold times when global clocks are used without DCMs to capture data pin to pin parameters When set to FIXED the tap delay value is fixed at the number of taps determined by the IOBDELAY VALUE attribute setting This value is preset and cannot be changed after configuration When set to VARIABLE the variable tap delay element is selected The tap delay can be incremented by setting CE 1 and INC 1 or decremented by CE 1 and INC 0 The increment decrement operation is synchronous to C the input clock signal IOBDELAY VALUE Attribute The IOBDELAY VALUE attribute specifies the initial number of tap delays The possible values are any integer from 0 to 63 The default value is zero The value of the tap delay reverts to IOBDELAY VALUE when the tap delay is reset IDELAY Timing Virtex 4 User Guide Table 7 9 shows the IDELAY switching characteristics Table 7 9 Input Delay Switching Characteristics Symbol Description TIDELAYRESOLUTION IDELAY tap resolution Ticeck Tickck CE pin Setup Hold with respect to C TrnccK TICKINC INC pin Setup Hold with respect to C TirstcK TICKRST RST pin Setup Hold with respect to C www xilinx com 323 UG070 v1 5 March 21 2006 Chapter 7 SelectlO Logic Resources XILINX Figure 7 12 shows an IDELAY timing diagram 1 2 et Wk eal tek ted ol ek TL gill sl T Io ICECK liRSTCK RST TL Lo Te I TipELAYRESOLUTION
401. tandards in the same bank 1 286 Combining output standards only Output standards with the same output Veco requirement can be combined in the same bank Compatible example SSTL2 I and LVDCI 25 outputs Incompatible example SSTI2 I output Veco 2 5V and LVCMOS33 output Vcco 3 3V outputs Combining input standards only Input standards with the same input Vcco and input Vppr requirements can be combined in the same bank Compatible example LVCMOS15 and HSTL_IV inputs Incompatible example Virtex 4 User Guide www xilinx com UGO070 v1 5 March 21 2006 2 XILINX Rules for Combining I O Standards in the Same Bank LVCMOSIS input Veco 1 5V and LVCMOSIS input Veco 1 8V inputs Incompatible example HSTL_I_DCI_18 Vggg 0 9V and HSTL IV DCI 18 Vggg 1 1V inputs Combining input standards and output standards Input standards and output standards with the same input Vcco and output Vcco requirement can be combined in the same bank Compatible example LVDS 25 output and HSTL I input Incompatible example LVDS 25 output output Veco 2 5V and HSTL I DCI 18 input input Vcco 1 8V Combining bi directional standards with input or output standards When combining bi directional I O with other standards make sure the bi directional standard can meet the first three rules Additional rules for combining DCI I O standards a Nomore than one Single Termination type input or output
402. tartup cycle dependencies are of note 1 The default value is g LCK cycle NoWait When this setting is used the startup sequence does not wait for the DCM to lock WHen the LCK cycle is set to other values the configuration startup remains in the specified startup cycle until the DCM is locked 2 Before setting the LCK cycle option to a startup cycle in BitGen the DCM s STARTUP WAIT attribute must be set to TRUE 3 Ifthe startup sequence is altered by using the BitGen option do not place the LCK cycle wait for the DCM to lock before the GTS cycle deassert GTS Incorrect implementation will result in the DCM not locking and an incomplete configuration Virtex 4 User Guide www xilinx com 69 UGO070 v1 5 March 21 2006 70 Chapter 2 Digital Clock Managers DCMs XILINX Deskew Adjust The DESKEW_ADJUST attribute sets the value for a configurable variable tap delay element to control the amount of delay added to the DCM feedback path see Figure 2 4 Data Input FF CLK DCM Into the Source BUFG FPGA gt gt gt Regulator Feedback Tap Delays System Synchronous Source Synchronous Default Setting Setting Delay set to zero ug070 2 04 071204 Figure 2 4 DCM and Feedback Tap Delay Elements This delay element allows adjustment of the effective clock delay between the clock source and CLKO to guarantee non positive hold times of IOB input flip flop in the device Adding more delay
403. tch the impedance of the receiver or driver to the impedance of the trace However due to increased device I Os adding resistors close to the device pins increases the board area and component count and can in some cases be physically impossible To address these issues and to achieve better signal integrity Xilinx developed the Digitally Controlled Impedance DCI technology DCI adjusts the output impedance or input termination to accurately match the characteristic impedance of the transmission line DCI actively adjusts the impedance of the I O to equal an external reference resistance This compensates for changes in I O impedance due to process variation It also continuously adjusts the impedance of the I O to compensate for variations of temperature and supply voltage fluctuations In the case of controlled impedance drivers DCI controls the driver impedance to match two reference resistors or optionally to match half the value of these reference resistors DCI eliminates the need for external series termination resistors DCI provides the parallel or series termination for transmitters or receivers This eliminates the need for termination resistors on the board reduces board routing difficulties and component count and improves signal integrity by eliminating stub reflection Stub reflection occurs when termination resistors are located too far from the end of the transmission line With DCI the termination resistors are as close as
404. tching characteristics 320 timing 318 IOB 215 defined 216 ISERDES Bitslip 372 IOBDELAY 361 IOBUF 230 390 PULLUP PULLDOWN KEEPER 233 IOBUFDS 231 ISERDES 355 defined 355 attributes 359 bitslip 356 358 372 BITSLIP ENABLE 360 attribute IDELAY IDELAYCTRL 330 ports 357 358 377 primitive 357 SDR 367 serial to parallel converter 355 362 switching characteristics 366 timing models 366 width expansion 361 L LDT See HyperTransport 284 LVCMOS 238 defined 238 LVDCI 240 defined 240 LVDCI_DV2 241 source termination 292 LVDS 282 defined 282 LVDS_25_DCI 283 LVDSEXT_25_DCI 283 LVPECL 285 defined 285 LVTTL 236 defined 236 N NO_CHANGE mode 113 O OBUF 229 OBUFDS 231 OBUFT 230 PULLUP PULLDOWN KEEPER 233 OBUFTDS 231 ODDR 344 clock forwarding 347 OPPOSITE_EDGE mode 344 ports 347 primitive 347 www xilinx com SAME_EDGE mode 346 OLOGIC 215 342 timing 349 OSERDES 374 parallel to serial converter 374 switching characteristics 381 timing 381 382 P parallel to serial converter 374 DDR 374 SDR 374 PCI 244 PCI33 244 PCI66 244 PCIX 244 PFDM 308 PMCD defined 93 attributes 96 clock frequencies 103 clocking wizard 104 connecting parallel PMCDs 101 connecting to a DCM 101 connecting to other clocks 100 connecting without a DCM 102 control signals reset and release 98 delay clocks 93 divided clocks 93 96 frequency divider 97 location 94 ports 95 primitive 95 PSCLK
405. ter Timing Characteristics Clock Event 1 e At time Toocgcy before Clock Event 1 the ODDR clock enable signal becomes valid High at the OCE input of the ODDR registers enabling them for incoming data Since the OCE signal is common to all ODDR registers care must be taken to toggle this signal between the rising edges and falling edges of C as well as meeting the register setup time relative to both clock edges e At time Topcy before Clock Event 1 rising edge of C the data signal D1 becomes valid high at the D1 input of ODDR register 1 and is reflected on the OQ output at time Tocko after Clock Event 1 Clock Event 2 e Attime Topcy before Clock Event 2 falling edge of C the data signal D2 becomes valid high at the D2 input of ODDR register 2 and is reflected on the OQ output at time Tocko after Clock Event 2 no change at the OQ output in this case Clock Event 9 At time Tosrcx before Clock Event 9 rising edge of C the SR signal configured as synchronous reset in this case becomes valid high resetting ODDR Register 1 reflected at the OQ output at time Tro after Clock Event 9 no change at the OQ output in this case and resetting ODDR Register 2 reflected at the OQ output at time Trg after Clock Event 10 no change at the OQ output in this case Virtex 4 User Guide www xilinx com 351 UGO070 v1 5 March 21 2006 Chapter 7 SelectlO Logic Resources 352 Figure 7 28 illustrates the OLOGIC 3 state register timing
406. terface is very similar to LVDS Virtex 4 IOBs are equipped with LDT buffers Table 6 35 summarizes all the possible LDT I O standards and attributes supported 284 www xilinx com Virtex 4 User Guide UGO070 v1 5 March 21 2006 XILINX Specific Guidelines for Virtex 4 I O Supported Standards Table 6 35 Allowed Attributes of the LDT I O Standard Primitives Attributes IBUFDS IBUFGDS OBUFDS OBUFGDS IOSTANDARD LDT_25 CAPACITANCE LOW NORMAL NORMAL DONT CARE DIFF_TERM TRUE FALSE Unused BLVDS Bus LVDS Since LVDS is intended for point to point applications BLVDS is not an EIA TIA standard implementation and requires careful adaptation of I O and PCB layout design rules The primitive supplied in the software library for bidirectional LVDS does not use the Virtex 4 LVDS current mode driver Therefore source termination is required Figure 6 76 shows the BLVDS transmitter termination BLVDS_25 OB 7 I I Rg w 1650 Rpiy BLVDS 25 DO i UB i 1650 I I Figure 6 76 BLVDS Transmitter Termination Zo 500 IN Rpigr 1000 Zo 500 I INX IOB BLVDS 25 ug070 6 74 071904 Table 6 36 summarizes all the possible BLVDS I O standards and attributes supported Table 6 36 Available BLVDS Primitives Primitives Attributes IBUFDS IBUFGDS OBUFDS OBUFGDS IOBUFDS IOSTANDARD BLVDS 25 CAPACITANCE LOW NORMAL NO
407. tex 4 User Guide www xilinx com 261 UGO070 v1 5 March 21 2006 Chapter 6 SelectlO Resources XILINX Figure 6 53 shows a sample circuit illustrating a valid termination technique for differential HSTL Class II 1 8V with unidirectional DCI termination DCI IOB 1 OB Voco 1 8V Vogo 18V DIFF HSTL Il DCI 18 2Rypn 2Zo 1000 E3 92 b3 4 2Rygy 2297 1000 E Avan 72729 1009 IpIFF_HSTL_II_DCI_18 a E Voco 1 8V Vooo 14V DIFF HSTL Il DCI 18 2Rypp 2Zg 1000 acer D3 020 P14 2Rypy Zo 1000 E 2Ryan 2Zg 1002 L ug070_6_51_071904 Figure 6 53 Differential HSTL 1 8V Class Il DCI Unidirectional Termination Figure 6 54 shows a sample circuit illustrating a valid termination technique for differential HSTL Class II 1 8V with bidirectional termination External Termination IOB 10B Vr 0 9V E TT Viz 0 9V DIFF_HSTL_II_18 DIFF_HSTL_II_18 DIFF_HSTL_II_18 DIFF_HSTL_II_18 DIFF_HSTL_II_18 DIFF_HSTL_II_18 ug070 6 52 071904 Figure 6 54 Differential HSTL 1 8V Class II Bidirectional Termination 262 www xilinx com Virtex 4 User Guide UGO070 v1 5 March 21 2006 X XILINX DCI Specific Guidelines for Virtex 4 I O Supported Standards Figure 6 55 shows a sample circuit illustrating a valid termination technique for differential HSTL Class II 1 8V with bidirectional DCI termination
408. the variable phase shifting feature DCM_PS also has the following available DCM features clock deskew frequency synthesis and fixed or variable phase shifting Table 2 3 lists the available ports in the DCM PS primitive Table 2 3 DCM PS Primitive Available Ports Port Names Clock Input CLKIN CLKFB PSCLK Control and Data Input RST PSINCDEC PSEN Clock Output CLKO CLK90 CLK180 CLK270 CLK2X CLK2X180 CLKDV CLKFX CLKFX180 Status and Data Output LOCKED PSDONE DO 15 0 DCM ADV Primitive The DCM ADV primitive has access to all DCM features and ports available in DCM PS plus additional ports for the dynamic reconfiguration feature It is a superset of the other two DCM primitives DCM ADV uses all the DCM features including clock deskew frequency synthesis fixed or variable phase shifting and dynamic reconfiguration Table 2 4 lists the available ports in the DCM ADV primitive Table 2 4 DCM ADV Primitive Available Ports Port Names Clock Input CLKIN CLKFB PSCLK DCLK Control and Data Input RST PSINCDEC PSEN DADDR 6 0 DI 15 0 DWE DEN Clock Output CLKO CLK90 CLK180 CLK270 CLK2X CLK2X180 CLKDV CLKFX CLKFX180 Status and Data Output LOCKED PSDONE DO 15 0 DRDY Virtex 4 User Guide www xilinx com 55 UG070 v1 5 March 21 2006 DCM Ports 56 Chapter 2 Digital Clock Managers DCMs XILINX There are four types of DCM ports available in t
409. the various attributes available and default values for the ODDR primitive D1 Q D2 ODDR CE ug070_7_25_080104 Figure 7 25 ODDR Primitive Block Diagram Table 7 12 ODDR Port Signals Pon Function Description Name Q Data output ODDR register output DDR C Clock input port The C pin represents the clock input pin CE Clock enable port CE represents the clock enable pin When asserted Low this port disables the output clock on port O D1 and D2 Data inputs ODDR register inputs R Reset Synchronous Asynchronous reset pin Reset is asserted High S Set Synchronous Asynchronous set pin Set is asserted High www xilinx com 347 UGO070 v1 5 March 21 2006 Chapter 7 SelectlO Logic Resources Table 7 13 ODDR Attributes 2 XILINX Attribute Name DDR CLK EDGE Description Sets the ODDR mode of operation with respect to clock edge Possible Values OPPOSITE EDGE default SAME EDGE INIT Sets the initial value for Q port 0 default 1 SRTYPE Set Reset type with respect to clock C ASYNC SYNC default ODDR VHDL and Verilog Templates The following examples illustrate the instantiation of the OSERDES module in VHDL and Verilog ODDR VHDL Template Example ODDR component ODDR component declaration generic DDR CLK EDGE string OPPOSITE EDGE INIT bit E rs SRTYPE string SYNC MF port
410. tics Symbol Setup Hold Description Tospck p Tosckp p D input Setup Hold with respect to CLKDIV Tospck T Tosckp T T input Setup Hold with respect to CLK Tospck r Tosckp T T input Setup Hold with respect to CLKDIV Toscck ocze Tosckc oce OCE input Setup Hold with respect to CLK Toscck rce Tosckc TCE TCE input Setup Hold with respect to CLK Sequential Delays Toscko oo Clock to Out from CLK to OQ Toscko ro Clock to Out from CLK to TO Virtex 4 User Guide www xilinx com 381 UGO070 v1 5 March 21 2006 Chapter 8 Advanced SelectlO Logic Resources XILINX Table 8 11 OSERDES Switching Characteristics Continued Symbol Description Combinatorial Tosco oo Asynchronous Reset to OQ Tosco ro Asynchronous Reset to TO Timing Characteristics In Figure 8 13 the timing of a 2 1 SDR data serialization is illustrated The timing parameter names and behavior do not change for different bus widths including when two OSERDES are cascaded together The same examples apply for DDR mode with the exception that OQ switches at every CLK edge rising and falling 1 2 2 CLKDIV loscck_oce NER SR Tospck p q loscko oa Tosco oa gt p S O D O O ug070_8_22_073004 Figure 8 13 OSERDES 2 1 SDR Data Serialization Timing Diagram Clock Event 1 e At
411. time delay feature in Virtex II and Virtex II Pro devices When used in this mode the IDELAYCTRL primitive does not need to be instantiated see IDELAYCTRL Usage and Design Guidelines for more details e Fixed delay mode IOBDELAY TYPE FIXED In the fixed delay mode the delay value is preset at configuration to the tap number determined by the attribute IOBDELAY VALUE Once configured this value cannot be changed When used in this mode the IDELAYCTRL primitive must be instantiated see IDELAYCTRL Usage and Design Guidelines for more details e Variable delay mode IOBDELAY TYPE VARIABLE In the variable delay mode the delay value can be changed after configuration by manipulating the control signals CE and INC When used in this mode the IDELAYCTRL primitive must be instantiated see IDELAYCTRL Usage and Design Guidelines for more details IDELAY Primitive Virtex 4 User Guide Figure 7 11 shows the IDELAY primitive IDELAY INC RST ug070 7 11 080104 Figure 7 11 IDELAY Primitive Table 7 6 lists the available ports in the IDELAY primitive Table 7 6 IDELAY Primitive Por Direction Size Function Name I Input 1 Serial input data from IOB C Input 1 Clock input www xilinx com 321 UGO070 v1 5 March 21 2006 Chapter 7 SelectlO Logic Resources 322 2 XILINX Table 7 6 IDELAY Primitive Continued rori Direction Size Function Name INC Input 1 Incre
412. tribute defines the parallel data output width of the serial to parallel converter The possible values for this attribute depend on the DATA_RATE attribute When DATA_RATE is set to SDR the possible values for the DATA_WIDTH attribute are 2 3 4 5 6 7 and 8 When DATA RATE is set to DDR the possible values for the DATA WIDTH attribute are 4 6 8 and 10 When the DATA WIDTH is set to widths larger than six a pair of ISERDES must be configured into a master slave configuration See ISERDES Width Expansion INTERFACE TYPE Attribute The INTERFACE TYPE attribute determines whether the ISERDES is configured in memory or networking mode The allowed values for this attribute are MEMORY or NETWORKING The default mode is MEMORY 360 www xilinx com Virtex 4 User Guide UGO070 v1 5 March 21 2006 XILINX Input Serial to Parallel Logic Resources ISERDES When INTERFACE TYPE is set to NETWORKING the Bitslip sub module is available and the OCLK port is unused When set to MEMORY the Bitslip sub module is not available and the OCLK port can be used IOBDELAY Attribute The IOBDEL AY attribute chooses the paths combinatorial or registered where the delay through the delay element is applied The possible values for this attribute are NONE default IBUF IFD and BOTH Table 8 3 summarizes the various output paths used for each attribute value Table 8 3 OBDELAY Attribute Value IOBDELAY Delay Eleme
413. trol the CLKO CLK90 CLK180 and CLK270 outputs are each phase shifted by 1 4 of the input clock period relative to each other Similarly CLK2X180 and CLKFX180 provide a 180 coarse phase shift of CLK2X and CLKFX respectively The coarse phase shifted clocks are produced from the delay lines of the DLL circuit The phase relationship of these clocks is retained when CLKFB is not connected Fine grained phase shifting uses the CLKOUT PHASE SHIFT and PHASE SHIFT attributes to phase shift DCM output clocks relative to CLKIN Since the CLKIN is used as the reference clock the feedback CLKFB connection is required for the phase shifting circuit to compare the incoming clock with the phase shifted clock The rest of this section describes fine grained phase shifting in the Virtex 4 DCM Phase Shifting Operation All nine DCM output clocks are adjusted when fine grained phase shifting is activated The phase shift between the rising edges of CLKIN and CLKPB is a specified fraction of the input clock period or a specific amount of DCM_TAP All other DCM output clocks retain their phase relation to CLKO Phase Shift Range The allowed phase shift between CLKIN and CLKPB is limited by the phase shift range There are two separate phase shift range components e PHASE SHIFT attribute range e FINE SHIFT RANGE DCM timing parameter range In the FIXED VARIABLE POSITIVE and VARIABLE CENTER phase shift mode the PHASE SHIFT attribute is in the n
414. ttp www xilinx com virtex4 Guide Contents Chapter 1 Clocking Resources Chapter 2 Digital Clock Manager DCM Chapter 3 Phase Matched Clock Dividers PMCD Chapter 4 Block RAM and FIFO memory Chapter 5 Configurable Logic Blocks CLBs Chapter 6 SelectIO Resources Chapter 7 SelectIO Logic Resources Chapter 8 Advanced SelectIO Logic Resources Chapter 9 Temperature Sensing Diode Additional Documentation The following documents are also available for download at http www xilinx com virtex4 Virtex 4 User Guide UGO070 v1 5 March 21 2006 Virtex 4 Family Overview The features and product selection of the Virtex 4 family are outlined in this overview Virtex 4 Data Sheet DC and Switching Characteristics This data sheet contains the DC and Switching Characteristic specifications for the Virtex 4 family XtremeDSP Design Considerations This guide describes the XtremeDSP slice and includes reference designs for using DSP48 math functions and various FIR filters Virtex 4 Configuration Guide This all encompassing configuration guide includes chapters on configuration interfaces serial and SelectMAP bitstream encryption boundary scan and JTAG configuration reconfiguration techniques and readback through the SelectMAP and JTAG interfaces www xilinx com 17 Preface About This Guide XILINX e PCB Designers Guide This guide decribes PCB guidelines for the Virtex 4 family It covers SelectIO
415. two adjacent banks cannot exceed 10576 of SSO allowance e Package SSO cannot exceed SSO allowance SSO is computed first on a per I O bank basis Next the average SSO of each adjacent bank pair is computed Finally the average SSO is computed for all banks to determine the effective utilization for the entire package Full Device SSO Example A sample calculation of full device SSO is shown for a Virtex 4 XC4VLX60 FF1148 package The subscript NOM denotes a nominal value while the subscript DES denotes a value for the design under analysis Step 0 Calculate the SSO Allowance SSO Allowance LNom Lpgs X VNOISE_DES VNOISE_NOM X VNotsE_NOM CLoAD_DES CLOAD_NOM X Vcorrr VNoIsE_NOM SSO Allowance 1 0 nH 1 1 nH x 550 mV 600 mV x 600 mV 22 x pF 15 pF x 9 mV pF 600 mV SSO Allowance 75 4 Step 1 Calculate the SSO for Each Individual Bank for Bank 1 Ensure the SSO for each bank does not exceed 100 Bank1 SSO 50 9 lt 10096 Bank2 SSO 50 9 lt 10096 Bank3 SSO 0 lt 100 Bank4 SSO 60 lt 100 Bank5 SSO 35 lt 100 Bank6 SSO 40 lt 100 Bank7 SSO 15 lt 100 Bank8 SSO 30 lt 100 Bank9 SSO 12 lt 100 Bank10 SSO 22 lt 100 Bank11 SSO 80 lt 100 Bank12 SSO 0 lt 100 Bank13 SSO 5 lt 100 Bank14 SSO 60 lt 100 OK If the SSO of any bank exceeds 100 apply ground bounce reduction techniques to the bank until the SSO of all individual banks is less than 1
416. uffer 86 www xilinx com Virtex 4 User Guide UGO70 v1 5 March 21 2006 2 XILINX VHDL and Verilog Templates and the Clocking Wizard ug 070 2 18 071504 Figure 2 18 Xilinx Clocking Wizard Frequency Synthesizer When all the desired settings are selected choose the Finish button 8 The Clocking Wizard closes and the Project Navigator window returns Virtex 4 User Guide UGO070 v1 5 March 21 2006 The Clocking Wizard writes the selected settings into an XAW file The XAW file appears in the Sources in Project window list Select the XAW file In the Processes for Source window double click on View HDL Source or View HDL Instantiation Template The HDL source or instantiation template will be generated These are read only files for inclusion or instantiation in a design To return to the Clocking Wizard double click on the XAW file The Clocking Wizard appears with the previously selected settings These settings can be changed and the XAW file updated to accommodate design changes ww xilinx com 87 Chapter 2 Digital Clock Managers DCMs XILINX DCM Timing Models The following timing diagrams describe the behavior of the DCM clock outputs under four different conditions 1 Reset Lock 2 Fixed Phase Shifting 3 Variable Phase Shifting 4 Status Flags Reset Lock In Figure 2 19 the DCM is already locked After the reset signal is applied all output clocks are stabilized to th
417. uide UGO070 v1 5 March 21 2006 www xilinx com 43 Chapter 1 Clock Resources XILINX Verilog Template Example BUFG module declaration module BUFG O I output O input I endmodule Example BUFG instantiation BUFG U BUFG O user 0o IO user i Jos Declaring constraints in Verilog synthesis attribute LOC of U BUFG is BUFGCTRL_X Y where is valid integer locations of BUFGCTRL Declaring Constraints in UCF File INST U BUFG LOC BUFGCTRL_X Y where is valid integer locations of BUFGCTRL BUFGCE and BUFGCE 1 VHDL and Verilog Templates The following examples illustrate the instantiation of the BUFGCE module in VHDL and Verilog The instantiation of BUFGCE 1 is exactly the same as BUFGCE with exception of the primitive name VHDL Template Example BUFGCI component BUFGCI port O out std ulogic CE in std ulogic I in std ulogic end component declaration Example BUFGCE instantiation U BUFGCE BUFGCE Port map O gt user o CE user ce I gt user i Declaring constraints in VHDL file attribute LOC string attribute LOC of U BUFGCE label is BUFGCTRL_X Y where is valid integer locations of BUFGCTRL 44 www xilinx com Virtex 4 User Guide UGO070 v1 5 March 21 2006 XILINX VHDL and Verilog Templates Verilog Template Example BUFGCE module declaration module BUFGCE O CE I output O input
418. um phase shift value For example if the phase shift must be within 0 to 128 set the counter to toggle PSINCDEC when it reaches 0 or 128 Phase Shift Characteristics e Offers fine phase adjustment with a resolution of 1 256 of the clock period or one DCM_TAP whichever is greater It can be dynamically changed under user control e The phase shift settings affect all nine DCM outputs e Vcc and temperature do not affect the phase shift except in direct phase shift mode e Ineither fixed or variable mode the phase shift range can be extended by choosing CLK90 CLK180 or CLK270 rather than CLKO choosing CLK2X180 rather than CLK2X or choosing CLKFX180 rather than CLKFX Even at 25 MHz 40 ns period the fixed mode coupled with the various CLK phases allows shifting throughout the entire input clock period range e MAX RANGE mode extends the phase shift range e The phase shifting DPS function in the DCM requires the CLKFB for delay adjustment Because CLKFB must be from CLKO the DLL output is used The minimum CLKIN frequency for the DPS function is determined by DLL frequency mode Dynamic Reconfiguration The Dynamic Reconfiguration Ports DRPs can update the initial DCM settings without reloading a new bit stream to the FPGA The Virtex 4 Configuration Guide provides more information on using DRPs Specific to the DCM DRPs can perform the following functions e Allow dynamic adjustment of CLKFX MULTIPLY M and CLKFX D
419. umerator of the following equation Phase Shift ns PHASE SHIFT 256 x PERIODcr KIN Where PERIODczxqn denotes the effective CLKIN frequency In VARIABLE CENTER and FIXED modes the full range of the PHASE SHIFT attribute is always 255 to 255 In the VARIABLE POSITIVE mode the range of the PHASE SHIFT attribute is 0 to 255 In the DIRECT phase shift mode the PHASE SHIFT attribute is the multiplication factor in the following equation Phase Shift ns PHASE SHIFT x DCM_TAP In DIRECT modes the full range of the PHASE SHIFT attribute is 0 to 1023 www xilinx com Virtex 4 User Guide UGO070 v1 5 March 21 2006 2 XILINX Virtex 4 User Guide DCM Design Guidelines The FINE_SHIFT_RANGE component represents the total delay achievable by the phase shift delay line Total delay is a function of the number of delay taps used in the circuit The absolute range is specified in the DCM Timing Parameters section of the Virtex 4 Data Sheet across process voltage and temperature The different absolute ranges are outlined in this section The fixed mode allows the DCM to insert a delay line in the CLKFB or the CLKIN path This gives access to the FINE_SHIFT_RANGE when the PHASE_SHIFT attribute is set to a positive value and FINE_SHIFT_RANGE when the PHASE_SHIFT attribute is set to a negative value Absolute Range Variable Center Mode FINE SHIFT RANGE 2 The variable center mode allows symmetric dynamic sweeps from
420. und pair to avoid the effects of ground bounce Refer to Table 6 43 for the number of equivalent output Vcco GND pairs for each device package and I O bank Table 6 42 Non Sparse Chevron Simultaneously Switching Output Limits per Equivalent Vcco GND Pair Voltage 1 5V Non Sparse Chevron Limit lOstandard SF363 and FF668 Packages LVCMOSIS 2 slow 51 LVCMOSIS 4 slow 31 LVCMOSIS 6 slow 22 LVCMOSIS 8 slow 17 LVCMOSIS 12 slow n LVCMOSIS 16 slow 8 LVCMOSIS 2 fast 30 LVCMOSIS 4 fast 18 LVCMOSIS 6 fast 13 LVCMOSIS 8 fast 10 LVCMOSIS 12 fast 8 LVCMOSIS 16 fast 6 LVDCI 15500 10 LVDCI DV2 15250 5 HSLVDCI 15 50 Q 10 HSTL I 20 HSTL I DCI 20 HSTL II 10 HSTL II DCI 10 HSTL III 8 HSTL III DCI 8 HSTL IV 4 HSTL IV DCI 4 DIFF HSTL II 10 DIFF HSTL II DCI 10 www xilinx com Virtex 4 User Guide UGO070 v1 5 March 21 2006 XILINX Table 6 42 Non Sparse Chevron Simultaneously Switching Output Limits per Equivalent Vcco GND Pair Continued Simultaneous Switching Output Limits Virtex 4 User Guide UG070 v1 5 March 21 2006 Voltage Non Sparse Chevron Limit lOStandard SF363 and FF668 Packages LVCMOS18 2 slow 58 LVCMOS18 4 slow 35 LVCMOS18 6 slow 25 LVCMOS18 8 slow 19 LVCMOS18 12 slow 13 LVCMOS18 16 slow 10 LVCMOS18 2 fast 34 LVCMOS18 4 fa
421. unique PCB PCB Construction e Veco and GND vias should have a drill diameter no less than 11 mils 279 yu e Total board thickness must be no greater than 62 mils 1575 p Signal Return Current Management Virtex 4 User Guide e Traces must be referenced to a plane on an adjacent PCB layer e The reference plane must be either GND or the Vcco associated with the output driver e The reference layer must remain uninterrupted for its full length from device to device www xilinx com 295 UGO070 v1 5 March 21 2006 Chapter 6 SelectlO Resources XILINX Load Traces e All IOB output buffers must drive controlled impedance traces with characteristic impedance of 509 10 e Total capacitive loading at the far end of the trace input capacitance of receiving device must be no more than 10 pF Power Distribution System Design e Designed according to Chapter 4 of the Virtex 4 PCB Design Guide Atleast one decoupling capacitor per Vcco pin see page 42 No less than one of each capacitor value present see page 42 Capacitors mounted within a distance of 1 40 see page 38 Approved solder land patterns see page 35 Figures 4 6 B C and D e Veco and GND planes can not be separated by more than 5 0 mils 152 u Nominal SSO Limit Table Sparse Chevron Table 6 40 provides the guidelines for the maximum number of simultaneously switching outputs allowed per output power ground pair to avoid the effects
422. urable Logic Blocks CLBs XILINX e At time Tsrcx before clock event 3 the SR signal configured as synchronous reset in this case becomes valid high resetting the slice register This is reflected on either the XQ or YO pin at time Tc xo after clock event 3 CLB Primitives and Verilog VHDL Examples Distributed RAM Primitives Four primitives are available from 16 x 1 bit to 64 x 1 bit Three primitives are single port RAM and one primitive is a dual port RAM as shown in Table 5 9 Table 5 9 Single Port and Dual Port Distributed RAM Primitive RAM Size Type Address Inputs RAMI16XIS 16 bits single port A3 A2 A1 A0 RAM32XIS 32 bits single port AA A3 A2 A1 AO RAMO4XIS 64 bits single port A5 A4 A3 A2 A1 AO RAMI6XID 16 bits dual port A3 A2 A1 A0 The input and output data are 1 bit wide However several distributed RAMs can be used to implement wide memory blocks Figure 5 28 shows generic single port and dual port distributed RAM primitives The A and DPRA signals are address busses RAM X1S RAM16X1D D D WE o WE SPO WCLK WCLK R W Port A 0 A 0 DPO DPRA 0 Read Port ug070 5 28 071504 Figure 5 28 Single Port and Dual Port Distributed RAM Primitive As shown in Table 5 10 wider primitives are available for 2 bit 4 bit and 8 bit RAM Table 5 10 Wider Primitives 198 Primitive RAM Size Data Inputs Address Inputs Data Outputs RAM
423. user ce0 CEl user cel IO user i0 Il user i1 IGNOREO user ignoreO0 IGNORE1 user ignorel S0 user s0O S1 user s1 Jus e E Dd Declaring constraints in Verilog synthesis attribute INIT_OUT of U_BUFGCTRL is 0 synthesis attribute PRESELECT_I0 of U BUFGCTRL is FALSE synthesis attribute PRESELECT I1 of U BUFGCTRL is FALSE synthesis attribute LOC of U_BUFGCTRL is BUFGCTRL_X Y where is valid integer locations of BUFGCTRL I Declaring Constraints in UCF File INST U BUFGCTRL INIT OUT 0 INST U BUFGCTRL PRESELECT IO FALSE INST U BUFGCTRL PRESELECT I1 FALSE INST U BUFGCTRL LOC BUFGCTRL_X Y where is valid integer locations of BUFGCTRL 42 www xilinx com Virtex 4 User Guide UGO070 v1 5 March 21 2006 XILINX VHDL and Verilog Templates BUFG VHDL and Verilog Templates The following examples illustrate the instantiation of the BUFG module in VHDL and Verilog VHDL Template Example BUFG declaration component BUFG port O out std_ulogic I in std_ulogic end component Example BUFG instantiation U BUFG BUFG Port map O user o IO gt user i Declaring constraints in VHDL file attribute LOC string attribute LOC of U BUFG label is BUFGCTRL_X Y where is valid integer locations of BUFGCTRL Virtex 4 User G
424. usly written into memory and stored in the data output transparent write as shown in Figure 4 2 CLK Loo uf NA NASZ N7 KH WE Data In Address Data Out ENABLE DISABLED READ WRITE z WRITE READ MEM bb 1111 MEM cc 2222 ug070 4 02 071204 Figure 4 2 WRITE FIRST Mode Waveforms 112 www xilinx com Virtex 4 User Guide UGO070 v1 5 March 21 2006 XILINX Synchronous Dual Port and Single Port RAMs READ_FIRST or Read Before Write Mode In READ_FIRST mode data previously stored at the write address appears on the output latches while the input data is being stored in memory read before write See Figure 4 3 we A OX 94 Ay Ne LM UN en WE Data In Address Data Out ENABLE DISABLED READ i WRITE i WRITE READ MEM bb 1111 MEM cc 2222 ug070 4 03 071204 Figure 4 3 READ FIRST Mode Waveforms NO CHANGE Mode In NO CHANGE mode the output latches remain unchanged during a write operation As shown in Figure 4 4 data output is still the last read data and is unaffected by a write operation on the same port NO CHANGE mode is not supported in 32K x 1 RAM configuration Data In XXXX 1111 2222 XXXX Address Data Out ENABLE l DISABLED READ WRITE WRITE READ MEM bb 1111 MEM cc 2222 dd ug070 4 04 071204 Figure 4 4 NO CHANGE Mode Waveforms Conflict Avoidance Virtex 4 block RAM memory is a true dual port RAM where both ports can access any memory loc
425. ust be ignored www xilinx com 117 UGO070 v1 5 March 21 2006 Chapter 4 Block RAM XILINX DI DO A 13 0 A14 RAM EXTENSION NONE 0 WE Control 4 WE 3 0 Z UGO070 4 08 033005 Figure 4 8 Byte Wide Write Enable In Block RAM Block RAM Library Primitives RAMB16 is the block RAM library primitive It is the basic building block for all block RAM configurations Other block RAM primitives and macros are based on this primitive Some block RAM attributes can only be configured using this primitive e g pipeline register cascade etc See the Block RAM Attributes section 118 www xilinx com Virtex 4 User Guide UG070 v1 5 March 21 2006 XILINX Block RAM Port Signals Figure 4 9 illustrates all the I O ports of the block RAM primitive RAMB16 CASCADEOUTA CASCADEOUTB CASCADEINA CASCADEINB ug070_4_09_071204 Figure 4 9 Block RAM Port Signals RAMB16 Block RAM Port Signals Each block RAM port operates independently of the other while accessing the same set of 18K bit memory cells Clock CLK A B Each port is fully synchronous with independent clock pins All port input pins have setup time referenced to the port CLK pin The output data bus has a clock to out time referenced to the CLK pin Clock polarity is configurable rising edge by default Enable EN A B The enable pin affects the read write and set reset functionalit
426. ut Q2 input C input CE input D triO0 GSR input R input S parameter parameter parameter parameter endmodule Example IDD IDDR U IDDR Q1 user q1 Q2 user a2 C user c CE user ce D user d R user r S user s 1 1 glbl GSR DDR_CLK_EDGE OPPOSITE_EDGE INIT_Q1 1 b0 INIT Q2 1 b0 SRTYPE SYNC R instantiation Virtex 4 User Guide UG070 v1 5 March 21 2006 www xilinx com 317 Chapter 7 SelectlO Logic Resources XILINX ILOGIC Timing Models This section describes the timing associated with the various resources within the ILOGIC block ILOGIC Timing Characteristics Figure 7 9 illustrates ILOGIC register timing When IDELAY is used Trpoc is replaced by Trpockr Ge UN M XSF KF NTF NIYI SS lipock licE1CK P rf CE1 i l isRck SR EM TNI l Tickg k Ticka am NYT NY ug070 7 09 072904 Figure 7 9 ILOGIC Input Register Timing Characteristics Clock Event 1 e Attime Tjcgicy before Clock Event 1 the input clock enable signal becomes valid high at the CE1 input of the input register enabling the input register for incoming data e Attime Typocy before Clock Event 1 the input signal becomes valid high at the D input of the input register and is reflected on the Q1 output of the input register at time TicKg after Clock Event 1 Clock Event 4 e At time Tyspcy before Clock
427. ut clocks start toggling UGO070 3 06 071404 Figure 3 6 REL Waveform Example Connecting PMCD to other Clock Resources In most applications the PMCD will be used with other clock resources including dedicated clock I O IBUFG clock buffers BUFGCTRLs DCMs and an MGT clock Additionally PMCD inputs and outputs can be connected to the general interconnects This section provides guidelines on connecting a PMCD to clock resources using dedicated routing IBUFG to PMCD Virtex 4 devices contain 16 or 32 global clock I Os These clock I Os are accessible by instantiating the IBUFG component Each top and bottom half of the center column contains eight or 16 IBUFGs Any of the IBUFGs in the top or bottom half can drive the clock input pins CLKA CLKB CLKC or CLKD of a PMCD located in the same top bottom half The routing from multiple IBUFGs to PMCD inputs are not matched DCM to PMCD Any DCM clock output can drive any PMCD input in the same top bottom half of the device A DCM can drive parallel PMCDs in the same group of two It is not advisable to drive parallel PMCDs with DCMs in different groups of two on the same top bottom half because there can be significant skew between PMCD outputs This skew is caused by the skew between inputs of PMCDs in different groups BUFGCTRL to PMCD Any BUFGCTRL can drive any Virtex 4 PMCD However only up to eight dedicated global clock routing resources exist in a particular clock regio
428. various clock signal sources to access the global clock trees and nets The possible sources for input to the global clock buffers include e Global clock inputs e Digital Clock Manager DCM outputs e Phase Matched Clock Divider PMCD outputs e Rocket IO Multi Gigabit Transceivers e Other global clock buffer outputs e General interconnect The global clock buffers can only be driven by sources in the same half of the die top bottom All global clock buffers can drive all clock regions in Virtex 4 devices The primary secondary rules from Virtex II and Virtex II Pro FPGAs do not apply However only eight different clocks can be driven in a single clock region A clock region 16 CLBs is a branch of the clock tree consisting of eight CLB rows up and eight CLB rows down A clock region only spans halfway across the device The clock buffers are designed to be configured as a synchronous or asynchronous glitch free 2 1 multiplexer with two clock inputs Virtex 4 devices have more control pins to provide a wider range of functionality and more robust input switching The following subsections detail the various configurations primitives and use models of the Virtex 4 clock buffers www xilinx com 21 UG070 v1 5 March 21 2006 22 Chapter 1 Clock Resources XILINX Global Clock Buffer Primitives The primitives in the table below are different configurations of the global clock buffers Table 1 3 Global Clock Buffe
429. wider deeper blocks with minimal routing delays Wider or deeper RAM structures are achieved with a smaller timing penalty than is encountered when using normal routing resources The Xilinx CORE Generator program offers the designer an easy way to generate wider and deeper memory structures using multiple block RAM instances This program outputs VHDL or Verilog instantiation templates and simulation models along with an EDIF file for inclusion in a design Block RAM Timing Model This section describes the timing parameters associated with the block RAM in Virtex 4 devices illustrated in Figure 4 12 The switching characteristics section in the Virtex 4 Data Sheet and the Timing Analyzer TRCE report from Xilinx software are also available for reference Virtex 4 User Guide www xilinx com 135 UGO070 v1 5 March 21 2006 Chapter 4 Block RAM 2 XILINX Block RAM Timing Parameters Table 4 8 shows the Virtex 4 block RAM timing parameters Table 4 8 Block RAM Timing Parameters Parameter Function Control Signal Setup and Hold Relative to Clock CLK Description TrxCK_x Setup time before clock edge and Trcx x x Hold time after clock edge TRCCK_ADDR Time before the clock that address signals must be stable at the ADDR inputs of the block RAM Address inputs ADDR TRCKC_ADDR Time after the clock that address signals must b
430. wing sections describe each of the modes in detail OPPOSITE EDGE Mode In OPPOSITE EDGE mode two output registers are used to clock data from the FPGA fabric at twice the throughput of a single rising edge clocking scheme Both registers are rising edge triggered A second register receives an inverted version of the clock Both register outputs are then multiplexed and presented to the data input or 3 state control input of the IOB This structure is similar to the Virtex II and Virtex II Pro implementation The simplified output DDR registers and the signals associated with the OPPOSITE EDGE mode are shown in Figure 7 21 www xilinx com Virtex 4 User Guide UG070 v1 5 March 21 2006 XILINX OLOGIC Resources DDR MUX ug070_7_21_080104 Figure 7 21 Output DDR in OPPOSITE_EDGE Mode The timing diagram of the output DDR using the OPPOSITE_EDGE mode is shown in Figure 7 22 CE D2 D2A D2B D2C D2D oa ___ D1A D2A DIB D2B D1c D2C D1D ug070 7 22 080104 Figure 7 22 Output DDR Timing in OPPOSITE EDGE Mode Virtex 4 User Guide www xilinx com 345 UGO070 v1 5 March 21 2006 Chapter 7 SelectlO Logic Resources XILINX SAME EDGE Mode In SAME EDGE mode a third register OFF3 or TFF3 clocked by a rising edge clock is placed on the input of the falling edge register The output DDR registers and the signals associated with the SAME EDGE mode are shown in Figure 7 2
431. wo clock nets in the adjacent clock regions up to three clock regions Unlike BUFIOs BUFRs can drive the I O logic and logic resources CLB block RAM etc in the existing and adjacent clock regions BUFRs can be driven by either the output from BUFIOs or local interconnect In addition BUFR is capable of generating divided clock outputs with respect to the clock input The divide values are an integer between one and eight BUFRs are ideal for source synchronous applications requiring clock domain crossing or serial to parallel conversion There are two BUFRs in a typical clock region two regional clock networks The center column does not have BUFRs BUFR Primitive Virtex 4 User Guide BUFR is a clock in clock out buffer with the capability to divide the input clock frequency CE CLR ug070 1 20 071204 Figure 1 20 BUFR Primitive Table 1 8 BUFR Port List and Definitions Port Name Type Width Definition O Output 1 Clock output port CE Input 1 Clock enable port Cannot be used in BYPASS mode CLR Input 1 Asynchronous clear for the divide logic and sets the output Low Cannot be used in BYPASS mode I Input 1 Clock input port Additional Notes on the CE Pin When CE is asserted deasserted the output clock signal turns on off four input clock cycles later When global set reset GSR signal is High BUFR does not toggle even if CE is held High The BUFR output toggles four clock cycles afte
432. x encoded bit vector Table 5 11 shows the length of the INIT attribute for each primitive Table 5 11 INIT Attributes Length Primitive Template INIT Attribute Length RAM16X1S RAM_16S 4 digits RAM32XI1S RAM 32S 8 digits RAM64X1S RAM_64S 16 digits RAM16X1D RAM_16S 4 digits Initialization in VHDL or Verilog Codes Distributed RAM structures can be initialized in VHDL or Verilog code for both synthesis and simulation For synthesis the attributes are attached to the distributed RAM instantiation and are copied in the EDIF output file to be compiled by Xilinx Alliance Series tools The VHDL code simulation uses a generic parameter to pass the attributes The Verilog code simulation uses a defparam parameter to pass the attributes The distributed RAM instantiation templates in VHDL and Verilog illustrate these techniques VHDL and Verilog Templates Location Constraints The CLB has four slices S0 51 52 and S3 As an example in the bottom left CLB the slices have the coordinates shown in Figure 5 1 Distributed RAM instances can have LOC properties attached to them to constrain placement The RAM16X1S primitive fits in any LUT of slices S0 or S2 For example the instance U_LRAM16 is placed in slice X0YO with the following LOC properties INST U RAM16 LOC SLICE X0YO Distributed RAM placement locations use the slice location naming convention allowing LOC properties to transfer easily
433. y interface designs DIFF HSTL II DCI DIFF HSTL Il DCI 18 Differential HSTL class II pairs complimentary single ended HSTL II type drivers with a differential receiver including on chip differential termination Differential HSTL Class II is intended to be used in bidirectional links Differential HSTL can also be used for differential clock and DOS signals in memory interface designs 248 www xilinx com Virtex 4 User Guide UGO070 v1 5 March 21 2006 XILINX Specific Guidelines for Virtex 4 I O Supported Standards HSTL Class Figure 6 39 shows a sample circuit illustrating a valid termination technique for HSTL Class I External Termination ELA IOB Vrp20 75V 5g HSTL I HSTL I Rp Zo 500 Vper 0 75V x X IOB IOB Veco 15V E 2Rypp 2Zg 1002 HSTL_I_DCI HSTL I DCI Vper 0 75V 2Rypy 2Zg 1000 ug070 6 37 071904 Figure 6 39 HSTL Class I Termination Table 6 14 lists the HSTL Class I DC voltage specifications Table 6 14 HSTL Class I DC Voltage Specifications Min Typ Max Veco 1 40 1 50 1 60 Vas 0 68 0 75 0 90 Vos B Veco x 05 VH V er 0 1 a E Vir Vrer 0 1 Vou Veco 04 P Yr E z 0 4 Tox at Voy mA 8 Tor at Vor mA 8 Notes 1 Vor and Voy for lower drive currents are sample tested 2 Per EIA JESD8 6 The value of Vggp is to be selected by the user to provide optimum noise margin in th
434. y in the clock distribution network effectively removing the delay between the source clock and its loads The size of each intrinsic delay element is a DCM_TAP see the AC Characteristics table in the Virtex 4 Data Sheet Figure 2 3 illustrates a simplified DLL circuit Clock Distribution Network Variable CLKOUT Delay Line ug070 2 03 071204 Figure 2 83 Simplified DLL Circuit To provide the correct clock deskew the DCM depends on the dedicated routing and resources used at the clock source and feedback input An additional delay element see Deskew Adjust is available to compensate for the clock source or feedback path The Xilinx ISE tools analyze the routing around the DCM to determine if a delay must be inserted to compensate for the clock source or feedback path Thus using dedicated routing is required to achieve predictable deskew www xilinx com 67 UGO070 v1 5 March 21 2006 Chapter 2 Digital Clock Managers DCMs XILINX Input Clock Requirements The clock input of the DCM can be driven either by an IBUFG IBUFGDS IBUF BUFGMUx or a BUFGCNTL Since there is no dedicated routing between an IBUF and a DCM clock input using an IBUF causes additional input delay that is not compensated by the DCM The DCM output clock signal is essentially a delayed version of the input clock signal It reflects any instability on the input clock in the output waveform The DCM input clock requireme
435. y of the port Ports with an inactive enable pin keep the output pins in the previous state and do not write data to the memory cells Enable polarity is configurable active High by default Write Enable WE A B To write the content of the data input bus into the addressed memory location both EN and WE must be active within a set up time before the active clock edge The output latches are loaded or not loaded according to the write configuration WRITE_FIRST Virtex 4 User Guide www xilinx com 119 UGO070 v1 5 March 21 2006 Chapter 4 Block RAM XILINX READ FIRST NO CHANGE When inactive a read operation occurs and the contents of the memory cells referenced by the address bus reflect on the data out bus regardless of the write mode attribute Write enable polarity is configurable active High by default Register Enable REGCE A B The register enable pin REGCE controls the optional output register When the RAM is in register mode REGCE 1 registers the output into a register at a clock edge The polarity of REGCE is configurable active High by default Set Reset SSR A B The SSR pin forces the data output latches to contain the value SRVAL see Block RAM Attributes page 122 The data output latches are synchronously asserted to 0 or 1 including the parity bit In a 36 bit width configuration each port has an independent SRVALJA B attribute of 36 bits This operation does not affect RAM memory cel
436. ynthesis Output Clock 180 CLKFX180 sese 60 Status and Data Output Ports 6 eee nn 60 Locked Output LOCKED ciens piane naei ee aiae ie renee hn 60 Phase Shift Done Output PSDONE 1 ce eee ene 60 Status or Dynamic Reconfiguration Data Output DO 15 0 lesse 61 Dynamic Reconfiguration Ready Output DRDY 6 eee 61 DCM Attributes assetto PURA er eS apr qer PR PES pepe resle 62 CLKDV DIVIDE Attribute lsseeeeeee RII ne 62 6 www xilinx com Virtex 4 User Guide UGO070 v1 5 March 21 2006 X XILINX CLKFX_MULTIPLY and CLKFX_DIVIDE Attribute 0 0 0 0 cc eee eee 62 CLKIN PERIOD Attribute 2 0 0 00 00 ee een n teen ene eee 62 CLKIN_DIVIDE_BY_2 Attribute 0 0 ccc ence ene n eens 63 CLKOUT PHASE SHIFT Attribute 0 0 0 e eee 63 CLK FEEDBACK Attribute 2 0 0 0 0c ccc cnt ele 63 DESKEW ADJUST Attribute 0 0 0 cece ene m rn 64 DFS_FREQUENCY_MODE Attribute 0 0 ccc ccc ene 64 DLL FREQUENCY MODE Attribute 2 0 0 0 oaan ccc cee eens 64 DUTY CYCLE CORRECTION Attribute 0 0 00 64 DCM PERFORMANCE MODE Attribute 0 00 0 64 FACTORY JF Attribute ee eR ER EA Ry Ye RRERRR ARS YXER Eger 65 PHASE SHIFT Attribute ssseeeeeee RI e 65 STARTUP WAIT Attribute 2 0 0 0 0 ccc RR e 65 DCM Design Guidelines te a heb ER Erg doctae Keg Ein Wachee tri lied 67 Clock Deskew etr ai Ad etl bee ee ee Eder ees 67 Clock Deskew Operation

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