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DM5804/DM6804 User's Manual - RTD Embedded Technologies, Inc.

1. OUT CR amp H4 POINT TO COUNTER 4 MODE REGISTER TABLE 5 1 OUT DR amp H22 COUNTER 4 MODE LSB OUT DR amp HOB COUNTER 4 MODE MSB Put the hex number 2710 decimal 10 000 in counter 4 load register OUT CR amp HC POI TO COUNTER 4 LOAD REGISTER TABLE 5 1 OUT DR amp H10 COUNTER 4 LSB OUT DR amp H27 COUNTER 4 MSB Next set up the counter 5 mode register see Figure 5 2 These are the settings we will use Gating Control no gating Source Edge rising edge Count Source Selection TCN 1 Count Control disable special gate reload from load count repetitively binary count count down Output Control TC toggled VALUE HEX 0022 OUT CR amp H5 POI TO COUNTER 5 MODE REGISTER TABLE 5 1 OUT DR amp H22 COUNTER 5 MODE LSB OUT DR amp HO COUNTER 5 MODE MSB Put the hex number 1F4 decimal 500 in counter 5 load register OUT CR amp HD POINT TO COUNTER 5 LOAD REGISTER TABLE 5 1 OUT DR amp HF4 COUNTER 5 LSB OUT DR amp H1 COUNTER 5 MSB OUT IRQCLR 0 CLEAR INTERRUPT STATUS OUT CR amp H7B LOAD amp ARM COUNTERS 1 2 4 amp 5 TABLE 5 2 The main program is IRO INP STAT AND 1 IF IRQ lt gt 1 GOTO MAIN OUT IROCLR O OUT CR H83 OUT CR H63 OUT CR H11 LSB 1 MSB 1 LSB 2 MS
2. OPERATING MODE A B C D E F G H J K L CM7 SPECIAL GATE 0 0 0 0 0 0 0 0 0 0 0 0 CM6 RELOAD SOURCE 0 0 0 0 0 0 1 1 1 1 1 1 CM5 REPITITION 0 0 0 1 1 1 0 0 0 1 1 1 CM13 15 GATE CONTROL 000 LVL EDG 000 LVL EDG 000 LVL EGD 000 LVL EDG Count to TC Once X X X Count to TC Twice X X X Countto TC repeatedly X X X X X X Gate Input Inactive x x x Count while gate active X X X X Count once on gate edge X X Count twice on gate edge X x No Hardware retriggering x x X x x X x x x x x x Reload from Load on TC X X X X X X Alternate Load Hold on TC X X X X X X Gate Controlled Load Hold Gate Retrigger Counter Table 11 Counter Modes A L OPERATING MODE CM7 SPECIAL GATE CM6 RELOAD SOURCE CM5 REPITITION CM13 15 GATE CONTROL Count to TC Once Count to TC Twice Countto TC repeatedly Gate Input Inactive Count while gate active Count once on gate edge Count twice on gate edge No Hardware retriggering Reload from Load on TC Alternate Load Hold on TC Gate Controlled Load Hold Gate Retrigger Counter Table 12 Counter Modes M X SPECIFICATIONS SUBJECT TO CHANGE WITHOUT NOTICE Copyright 2000 Celeritous Technical Services Corp 13 Rev E Tuesday September 25 800 687 6510 806 793 0708 FAX 806 793 0710 http www celeritous com Celeritous Technical Services
3. CONTROL WORD 15 D Dg Ds D D D D Do PAJ PA PCP PCy DD gt PCS PCy PB PB 231256 12 Operating Modes MODE 1 Strobed Input Output This functional configuration provides a means for transferring I O data to or from a specified port in conjunction with strobes or handshaking signals In mode 1 Port A and Port B use the lines on Port C to generate or accept these handshaking signals 10 Mode 1 Basic functional Definitions e Two Groups Group A and Group B e Each group contains one 8 bit data port and one 4 bit control data port e The 8 bit data port can be either input or output Both inputs and outputs are latched e The 4 bit port is used for control and status of the 8 bit data port intel Input Control Signal Definition STB Strobe Input A low on this input loads data into the input latch IBF Input Buffer Full F F A high on this output indicates that the data has been loaded into the input latch in essence an ac knowledgement IBF is set by STB input being low and is reset by the rising edge of the RD input INTR Interrupt Request A high on this output can be used to interrupt the CPU when an input device is requesting service INTR is set by the STB is a one IBF is a one and INTE is a one It is reset by the falling edge of RD This procedure allows an input device to re quest service from the CPU by simply
4. 231256 22 MODE 0 BASIC OUTPUT WR D Dy CS A1 AQ OUTPUT p we 231256 23 21 82C55A WAVEFORMS Continued MODE 1 STROBED INPUT INTR INPUT FROM _ _ PERIPHERAL 231256 24 MODE 1 STROBED OUTPUT INTR OUTPUT we 231256 25 22 intel 82C55A WAVEFORMS Continued MODE 2 BIDIRECTIONAL DATA FROM 8080 TO 8255 INTR PERIPHERAL c A ee dD a i ur Spare OATA FROM PERIPHERAL TO 8255 DATA FROM 8255 TO PERIPHERAL DATA FROM 8255 TO 8080 231256 26 Note Any sequence where WR occurs before ACK AND STB occurs before RD is permissible INTR IBF e MASK e STB e RD OBF e MASK e ACK e WR WRITE TIMING READ TIMING Ag 1 CS Ap 1 CS DATA BUS DATA BUS LS HIGH IMPEDANCE HIGH IMPEDANCE 231256 28 231256 27 A C TESTING INPUT OUTPUT WAVEFORM A C TESTING LOAD CIRCUIT 24 DEVICE UNDER O Ver TEST 0 45 I QC 150 pF 231256 29 231256 30 A C Testing Inputs Are Driven At 2 4V For A Logic 1 And 0 45V i For A Logic O Timing Measurements Are Made At 2 0V For A Vexr Is Set At Various Voltages During Testing To Guarantee Logic 1 And 0 8 For A Logic 0 The Specification C_ Includes Jig Capacitance 23 APPENDIX D WARRANTY AND RETURN POLICY Return Policy If you wish to ret
5. Transfers the two 4 bit Port C digital input and digital output data groups Port C Upper and Port C Lower between the board and an external device A read transfers data from the external device through P2 and into PPI Port C a write transfers the written data from Port C through P2 to an external device 4 3 BA 3 8255 PPI Control Word Write Only When bit 7 of this word is set to 1 a write programs the PPI configuration The table below shows the control words for the 16 possible Mode 0 Port I O combinations Mode Set FI vr dU ERE o oce oer ag Port C Lower 1 active 0 output Mode Select 1 input 00 mode 0 01 mode 1 Port B 10 mode 2 0 output 1 input Port A l 0 output Mode Select 1 input 0 modeo 1 mode 1 4 4 When bit 7 of this word is set to 0 a write can be used to individually program the Port C lines D7 D6 D5 D4 D3 D2 D1 DO Set Reset Bit Set Reset Function Bit Bit Select 0 set bit to 0 0 active 000 PCO 1 set bit to 1 001 PC1 010 PC2 011 PC3 100 PC4 101 2 PC5 110 PC6 111 2 PC7 For example if you want to set Port C bit 0 to 1 you would set up the control word so that bit 7 is 0 bits 1 2 and 3 are 0 this selects PCO and bit 0 is 1 this sets PCO to 1 The control word is set up like this 0 X X X 0 0 0 1 Sets PCO to 1 written to BA
6. 1 disable increment Scaler Control 0 binary division 1 BCD division Compare 2 Enable 0 disabled 1 enabled Compare 1 Enable 0 disabled 1 enabled Time of Day Mode FOUT Source 0000 F1 0001 SRC 1 0010 SRC 2 0011 SRC 3 0100 SRC 4 0101 SRC 5 0110 GATE 1 0111 GATE 2 1000 GATE 3 1001 GATE 4 1010 GATE 5 1011 F1 1100 F2 1101 F3 1110 F4 1111 F5 00 TOD disabled 01 TOD enabled 5 input 10 TOD enabled 6 input 11 TOD enabled 10 input Fig 5 1 Master Mode Register Bit Assignments oO ee 5 6 T CR amp H2 POI TO COUNTER 2 MODE REGISTER TABLE DR H22 COUNTER 2 MODE LSB T DR amp HO COUNTER 2 MODE MSB the hex number 1F4 decimal 500 in counter 2 load register T CR amp HA POI TO COUNTER 2 LOAD REGISTER TABLE DR amp HF4 COUNTER 2 LSB DR amp H1 COUNTER 2 MSB Count Source Selection Counter Control 0000 TCN 1 0 disable special gate 0001 SRC 1 1 enable special gate 0010 SRC 2 0011 SRC 3 0 reload from load 0100 SRC 4 1 reload from load or 0101 SRC 5 hold 0110 GATE 1 except in mode X 0111 2 GATE 2 which reloads only 1000 GATE 3 from load 1001 GATE 4 1010 GATE 5 0 count once 1011 F1 1 count repetitively 1100 F2 1101 F3 0 binary count 1110 F4 1 BCD count 1111
7. BaseAddress 7 0 Clear DM5804 interrupt Port 20 20 Send EOI command to 8259 end Saving the Startup Interrupt Mask Register IMR and Interrupt Vector The next step after writing the ISR is to save the startup state of the interrupt mask register and the interrupt vector that you will be using The IMR is located at I O port 21H The interrupt vector you will be using is located in the interrupt vector table which is simply an array of 256 bit 4 byte pointers and is located in the first 1024 bytes of memory Segment 0 Offset 0 You can read this value directly but it is a better practice to use DOS function 35H get interrupt vector Most C and Pascal compilers provide a library routine for reading the value of a vector The vectors for the hardware interrupts are vectors 8 through 15 where IRQO uses vector 8 IRQ1 uses vector 9 and so on Thus if the DM5804 will be using IRQ3 you should save the value of interrupt vector 11 Before you install your ISR temporarily mask out the IRQ you will be using This prevents the IRQ from requesting an interrupt while you are installing and initializing your ISR To mask the IRQ read in the current IMR at I O port 21H and set the bit that corresponds to your IRQ remember setting a bit disables interrupts on that IRQ while clearing a bit enables them The IMR is arranged so that bit 0 is for IRQO bit 1 is for IRQI and so on See the paragraph entitled Interrupt Mask Regis
8. Hex 654321 Hex 654321 m m mm 5361218 T 56020 50829 552 228 5761240 mE m 592125 me 508120 T T 616 068 0014101 744 288 011101 872 368 1000 3E8 111101 6241270 001110 752 QF0 011110 880 370 1008 3F0 111110 632 278 760 2F8 011111 888 378 10 0 closed 1 open 288 2C0 5641240 2D0 2D8 1016 3F8 111111 1 5 Fig 1 5 Base Address Switch S1 Pull up Pull down Resistors on Digital I O Lines The 8255 programmable peripheral interface provides 24 parallel TTL CMOS compatible digital I O lines which can be interfaced with external devices The lines are divided into four groups eight Port A lines four Port C Lower lines eight Port B lines and four Port C Upper lines You can install and connect pull up or pull down resistors for any or all of these four groups of lines You may want to pull lines up for connection to switches This will pull the line high when the switch is disconnected Or you may want to pull down lines connected to relays which control turning motors on and off These motors turn on when the digital lines controlling them are high To use the pull up pull down feature you must first install 10 kilohm resistor packs in any or all of the four locations around the 8255 labeled PA PB PCL and PCH PA and PB take 10 pin packs an
9. September 25 Intel 82C55A Programmable Peripheral Interface Data Sheet Reprint intel 82C55A CHMOS PROGRAMMABLE PERIPHERAL INTERFACE m Compatible with all Intel and Most W Control Word Read Back Capability Other Microprocessors W Direct Bit Set Reset Capability W High Speed Zero Wait State 2 A DC Dri bilit m Operation with 8 MHz 8086 88 and m poi Capability oral T O bionda Available in 40 Pin DIP and 44 Pin PLCC m 24 Programmable I O Pins OR LS EN m piid m Available in EXPRESS m Low Power CHMOS Standard Temperature Range W Completely TTL Compatible Extended Temperature Range The Intel 82C55A is a high performance CHMOS version of the industry standard 8255A general purpose programmable I O device which is designed for use with all Intel and most other microprocessors It provides 24 O pins which may be individually programmed in 2 groups of 12 and used in 3 major modes of operation The 82C55A is pin compatible with the NMOS 8255A and 8255A 5 In MODE 0 each group of 12 I O pins may be programmed in sets of 4 and 8 to be inputs or outputs In MODE 1 each group may be programmed to have 8 lines of input or output 3 of the remaining 4 pins are used for handshaking and interrupt control signals MODE 2 is a strobed bi directional bus configuration The 82C55A is fabricated on Intel s advanced CHMOS III technology which provides low power consumption with performance equal to or greater than the equivalent NMOS produ
10. esi A no eee tete n node ite e deity en ie 10 yA Input capacitance SINE a LL AE 10 pF Output capacitance G OUTJ eQ FS TMEIZ une ee de ii 20 pF Une Am9513A Five 16 bit timer counters Binary or BCD up or down counting Programmable operating modes sseeneneem emen 24 Counter input SOUIGE anneer enevennenenn External clock 6 9 MHz max on board 5 MHz clock external gate input or adjacent counter output Gouriter oUtpuls He id Available externally used as PC interrupts or internally cascaded to adjacent counter Counter gate SOUFCE nunnnnennnnnnnnennnnnnnnnnnnnnnnnnnnnennnennnnnnnnnannennnnennnnnnnnn nn External input counter output or software control Miscellaneous Inputs Outputs 5 volts digital ground PC bus sourced External interrupt input Frequency output Additional gate inputs Current Requirements POI IS PERDRE tits 220 mA max P2 Connector 50 pin right angle header Size 3 55 L x 3 775 W x 0 6 H 90mm x 96mm x 16mm A 3 A 4 APPENDIX B P2 CONNECTOR PIN ASSIGNMENTS B 2 sact OQO Gare our our GATE2 SRC2 src3 O GATE3 outa OUT3 GATE4 1003 srca sRcs 3 GATES DIGITAL GND 15 OUTS EXTINT ADGA DIGITAL GND PIN 1 FOUT DIGITAL GND DIGITAL GND 2 62 DIGITAL GND PA7 3 PC7 PA6 5 PC6 PA5 27 PC5 PA4 PC4 Pas 6963 Pcs PA2 83 PC2 Par 55 PC1 Pao 67 PCO PB7 PB6 PB5 PB4 PB3 PB2 PB1 PBO 12 VOLTS 47 48 5
11. while Port C is divided into two portions as required by the Port A and Port B definitions All of the output registers including the status flip flops will be reset whenever the mode is changed Modes may be combined so that their functional definition can be tailored to almost any I O structure For instance Group B can be programmed in Mode 0 to monitor simple switch closings or display computa tional results Group A could be programmed in Mode 1 to monitor a keyboard or tape reader on an interrupt driven basis ADDRESS BUS CONTROL BUS DATA BUS MODE 0 PB PB PC3PCo PCZ PC PAPA MODE 1 B zz i A Jo Jeo PB PB CONTROL CONTROL PAP OR 1 0 OR 1 0 TPA MODE 2 B LA A P8 PB vo A PA PA ES CONTROL Ed 231256 5 Figure 5 Basic Mode Definitions and Bus Interface 82C55A CONTROL WORD GROUP B PORT C LOWER 1 INPUT 0 OUTPUT PORTB 1 INPUT 0 OUTPUT MODE SELECTION 0 MODEO 1 MODE 1 PORT C UPPER 1 INPUT 0 OUTPUT PORTA 1 INPUT 0 OUTPUT MODE SELECTION 00 MODE O 01 MODE 1 1X MODE 2 MODE SET FLAG 1 ACTIVE 231256 6 Figure 6 Mode Definition Format The mode definitions and possible mode combina tions may seem confusing at first but after a cursory review of the complete device operation a simple logical I O approach will surface The design of the 82C55A has t
12. www celeritous com 5 Chan 16 bit 20MHz Counter Timer SOURCE WR BATA Y ARM COMMAND X care AAN ARA OTO RR AAA RA COUNT VALUE La Nez X ER N 1 y N N 1 Y n 2 A M K 2 rm X K K 1 X X 1 L X ca ine TC OUTPUT TOGGLE OUTPUT X HOLD REG L X N X K X L COUNTER MODE X WAVEFORMS Figure 28 CTS9513 Counter Mode X Representative Waveforms MoDE X HARDWARE SAVE Mode X is a hardware edge triggered strobe counter with the capability of reading the counter value without interrupting the count As shown in Figure 28 once the counter is ARMed a valid gate edge starts the counter Once triggered the counter will count to TC regardless of the state of the Gate line Gate edges received prior to TC will store the current count in the Hold register Once the counter has reached TC the counter will stop until a subsequent gate edge is received Gate edges applied to an unarmed counter have no effect X2 Input LOW Level 5 Volts Output LOW Level O lg 4m 04 Volts Output HIGH Level lo 4mA 24 Voli Input Leakage Current 10 10 HA Supply Current No Load F osc2 7ZMHz 20 mA oos IDD Statie o 10 MA Cp PinCapacitance 5 1 o 10 pF Table 12 CTS9513 Electrical Characteristics SPECIFICATIONS SUBJECT TO CHANGE WITHOUT NOTICE Copyright 2000 Celeritous Technical Services Corp 23 Rev E Tuesday
13. 3 X don t care Set Reset Function Bit Set PCO Bit Select 000 PCO BA 4 Am9513A Data Register Read Write Accesses the Am9513A data register See data sheet included in Appendix C for more information on the operation of the Am9513A IMPORTANT Because of the bus release time of the Am9513A AMD recommends you insert a small delay between software accesses to the chip BA 5 Am9513A Command Register Read Write Accesses the Am9513A command register See data sheet included in Appendix C for more information on the operation of the Am9513A IMPORTANT Because of the bus release time of the Am9513A AMD recommends you insert a small delay between software accesses to the chip 4 5 BA 6 IRQ Enable Write Only Enables and disables interrupt generation Writing a 1 enables interrupt generation writing a 0 disables interrupt generation 0 0 0 0 0 0 0 D7j D6 D5 D4 Ds D2 D1 DO Interrupt Enable Disable 0 interrupt disabled 1 interrupt enabled BA 7 Interrupt Status Clear Read Write A read shows the status of the interrupt bit 0 only as defined below A write clears the interrupt data written is irrelevant Each time the interrupt status bit goes high a write should follow to clear the bit X X X X X X X Interrupt Status 0 2 no interrupt 1 interrupt has occurred 4 6 Programming the DM5804 This section gives you some general information about progra
14. 3308 34th St Lubbock Texas 79410 CTS9513 2 5 Chan 16 bit 20MHz Counter Timer SOURCE WR DATA X ARM COMMAND Y ON ARRAY COUNT VALUE a e 3 Ya yra fne om bu yo Ca Va E TC OUTPUT TOGGLE OUTPUT COUNTER MODE I WAVEFORMS Figure 18 CTS9513 Counter Mode Representative Waveforms SOURCE WR DATA K ARM COMMAND y A OOO COUNT VALUE L 1 X L 2 y e X 1 K H Kaa k La ot Qmd O x hi E TC OUTPUT TOGGLE OUTPUT X COUNTER MODE J WAVEFORMS Figure 19 CTS9513 Counter Mode J Representative Waveforms MODE I HARDWARE TRIGGERED DELAYED PULSE STROBE Mode is similar to Mode G with the exception that the counter is active only after receipt of an ARM command and a valid Gate Edge As illustrated in Figure 18 the counter will count to TC reload from the Hold Register count to TC then disarm itself Once a valid Gate edge has been received the gate line has no further action on the counter MODE J VARIABLE DUTY CYCLE RATE GENERATOR WITH No HARDWARE GATING This mode is used primarily for generation of variable duty cycle waveforms Once armed the counter will count repeatedly until disarmed The counter will count to the first TC reload automatically from the Hold register count to the next TC reload automatically from the Load register and repeat the cycle If the toggle output mode is selected the output wil
15. Corp 3308 34th St Lubbock Texas 79410 CTS9513 2 5 Chan 16 bit 20MHz Counter Timer SOURCE WR DATA X ARM COMMAND y cate NARRA COUNT VALUE L 1 ji L 2 Y L 3 Y ES y TC OUTPUT TOGGLE OUTPUT COUNTER MODE A WAVEFORMS Figure 10 CTS9513 Counter Mode A Representative Waveforms SOURCE WR DATA y ARM COMMAND COUNT VALUE L 1 je Yous Xo Xoo A 2 la ar ta TC OUTPUT TOGGLE OUTPUT COUNTER MODE B WAVEFORMS Figure 11 CTS9513 Counter Mode B Representative Waveforms Mode A Software Triggered Strobe with no Gating As shown in Figure 10 The counter is only active after receipt of an ARM command On reaching TC the counter automatically reloads from the Load register and disarms awaiting the next software ARM command MODE B SOFTWARE TRIGGERED STROBE WITH LEVEL GATING In Mode B illustrated in Figure 11 the counter is only active when both an ARM command has been received and the selected Gate line is active The counter will halt counting when the gate line is de asserted and resume counting when the gate line is re asserted until the counter reaches TC When the counter reaches TC the timer will reload from the load register and disarm automatically until a new ARM command is received SPECIFICATIONS SUBJECT TO CHANGE WITHOUT NOTICE Copyright 2000 Celeritous Technical Services Corp Rev E Tuesday September 25 800 687 65
16. IRQ An ISR is different than standard routines that you write First on entrance the processor registers should be pushed onto the stack BEFORE you do anything else Second just before exiting your ISR you must clear the interrupt status of the DM5804 and write an end of interrupt command to the 8259 controller Finally when exiting the ISR in addition to popping all the registers you pushed on entrance you must use the IRET instruction and not a plain RET The IRET automatically pops the flags CS and IP that were pushed when the interrupt was called If you find yourself intimidated by interrupt programming take heart Most Pascal and C compilers allow you to identify a procedure function as an interrupt type and will automatically add these instructions to your ISR with one important exception most compilers do not automatically add the end of interrupt command to the procedure you must do this yourself Other than this and the few exceptions discussed below you can write your ISR just like any other routine It can call other functions and procedures in your program and it can access global data If you are writing your first ISR we recommend that you stick to the basics just something that will convince you that it works such as incrementing a global variable NOTE If you are writing an ISR using assembly language you are responsible for pushing and popping registers and using IRET instead of RET There are a few cautions you mu
17. Load Register Selected OPOD CTS9513 2 5 Chan 16 bit 20MHz Counter Timer 6 No Retriggering 7 F1 source selected 8 Positive true input polarity 9 No Gating The Counter Mode Register must be loaded while the counter is disarmed Table 10 summarizes the Counter Mode Register bit assignments Output Control Bits CMO 2 The counter output may be configured to be disabled programmed to follow the counter terminal count or to toggle its state at each terminal count The output logic for each counter is shown in Figure 8 The output may be disabled by either placing it in a high impedance state or in a low impedance state to ground The outputs may also be hardware inhibited with the line In the Terminal count mode the output may be programmed to output an active high or active low pulse which is equal to one count source clock period In the output toggle mode the output changes state whenever the counter reaches a terminal count The output state may be initialized with the SET and CLEAR counter commands C7 C6 C5 C4 C3 C2 C1 C0 Command Register Bit Load Data Pointer Commands G 1 4 Group Pointer E1 2 Element Pointer Reserved Counter 1 Mode Register Counter 2 Mode Register Counter 3 Mode Register Counter 4 Mode Register Counter 5 Mode Register Reserved Alarm Register 1 Control Cycle Reserved Counter 1 Load Register Counter 2 Load Register Counter 3 Load Register Counter 4 Loa
18. OUTPUT POL OUTPUT LOW OUTPUT INHIBIT TRISTATE CNTL Figure 7 Counter Output Section Block Diagram SPECIFICATIONS SUBJECT TO CHANGE WITHOUT NOTICE Copyright 2000 Celeritous Technical Services Corp 11 Rev E Tuesday September 25 Celeritous Technical Services Corp 3308 34th St Lubbock Texas 79410 800 687 6510 806 793 0708 FAX 806 793 0710 CTS9513 2 5 Chan 16 bit 20MHz Counter Timer http www celeritous com F2 F3 FA Im 4 BITS lo 4 BITS F5 A E TET FREQUENCY BCD SCALING BINARY SCALING Fi CLK IN CLK IN F2 CIK 10 CIK 16 F3 CLK 100 CLK 256 F4 CLK 1000 CLK 4096 F5 CLK 10000 CLK 65536 Figure 8 CTS9513 Counter Internal Prescaler Block Diagram Mope V FSK ERROR An error in implementing the special gate function prevents the implementation of Mode V FSK Generator The gate level is supposed to control whether the counter is reloaded from the LOAD or HOLD register to determine the output rate generator frequency and allow switching between two frequencies to produce Frequency Shift Keying FSK modulation When programmed for Mode V the current device Revision will reload only from the HOLD register regardless of the state of the GATE input This appears to be a general problem with the special gate function that controls reloading of the counter from the Load or Hold reg
19. PLCC 44 OTHER PRODUCTS Celeritous Technical Service specializes in the creation of replacements for discontinued and obsolete ICs Using the latest in ASIC technology and EDA Design Tools Celeritous Technical can provide rapid high quality cost effective form fit and function replacements for obsolete digital ICs Visit us on the web at http www celeritous com for more information on our products and services SPECIFICATIONS SUBJECT TO CHANGE WITHOUT NOTICE Copyright 2000 Celeritous Technical Services Corp RevE Tuesday September 25 800 687 6510 806 793 0708 FAX 806 793 0710 http www celeritous com Celeritous Technical Services Corp 3308 34th St Lubbock Texas 79410 DEVICE DESCRIPTION The CTS9513 is a custom high speed ASIC implementation of the AMD AM9513 System Timing Controller The 9513 has long been the most versatile counter timer peripheral device featuring far more flexibility than competing timing devices such as the Intel 8253 8254 Motorola 6840 or others A large installed base of devices and software drivers already exists The principal limitation of the AM9513 was its maximum frequency limitation of 7 Mhz imposed by its late 1970 s NMOS LSI design The CTS9513 shatters this barrier with a 20 MHz maximum clock speed and much lower power consumption due to its CMOS construction The CTS9513 Counter Timer is capable of a wide variety of applications including but not limited to Event C
20. TO CHANGE WITHOUT NOTICE Copyright 2000 Celeritous Technical Services Corp 10 RevE Tuesday September 25 Celeritous Technical Services Corp 800 687 6510 806 793 0708 x 3308 34th St FAX 806 793 0710 CTS9513 2 Lubbock Texas 79410 http www celeritous com 5 Chan 16 bit 20MHz Counter Timer TJ Table 9 CTS9513 Time of Day Data Format CM15 CMl4 CMI13 CM12 CM11 CM10 CM9 CM8 CM7 CM6 CM5 CM4 CM3 CM2 CM1 CMO GCTL3 GCTL2 GCTL1 EDGE SRCL8 SRC1 4 SRCI 2 SRC1 1 GATE RELOAD REPEAT COUNT DIR outa OUT2 OUT Gate Control Edge 000 No Gating Mode 0000 TC N 1 001 Active High TC N 1 0 Rising 0001 Source 1 001 Active High on TC 010 Active High Level 1 Falling 0010 Source 2 010 TC Toggled GateN 1 011 Active High Level GateN 1 0011 Source 3 011 Illegal 100 Active High Level GateN 0100 Source 4 100 Inactive Output High Z 101 Active Low Level GateN 0101 Source 5 101 Active Low on TC 110 Active High Edge GateN 0110 Gate 1 110 Illegal 111 Active Low Edge GateN 111 Illegal 1000 2 Gate 3 1001 2 Gate 4 1010 2 Gate 5 1011 F1 1100 F2 1101 F3 1110 F4 1111 F5 Table 10 CTS9513 Counter Mode and Auxiliary Counter Mode Register Bit Assignments INT CLEAR INT MODE OUTPUT SET COUNTER TC OUTPUT CLEAR TC TOGGLE COMPARATOR ALARM EN
21. The result is a 1 Hz clock which is used to clock counter 3 Counter 3 counts the 1 Hz pulses The count value from counter 3 is displayed on the screen This value should start at 0 and increment once each second 5 MHz COUNTER 1 COUNTER 2 DIVIDER 10 000 DIVIDER 500 COUNTER 3 The first lines of the program clear the screen and set up the base address of the DM5804 The address in the variable BA must match the setting of the base address switch S1 on the board The factory setting of S1 is 300 hex 768 decimal CLS INPUT ENTER BASE ADDRESS IN DECIMAL BA The next section of the program sets up the computer screen CLS CLEAR SCREEN DIM RESULT AS LONG DIMENSION VARIABLE RESULT AS A LONG INTEGER KEY 1 ON TURN F1 KEY ON OCATE 2 25 PRINT DM5804 COUNTER DEMO PROGRAM OCATE 10 31 PRINT COUNTER 3 VALUE OCATE 24 2 PRINT F1 QUIT The next section of the program sets up the address for the DM5804 registers These addresses are defined at the beginning of Chapter 4 PA BA 0 ADDRESS FOR 8255 PORT A PB BA 1 ADDRESS FOR 8255 PORT B PC BA 2 ADDRESS FOR 8255 PORT C CW BA 3 ADDRESS FOR 8255 CONTROL WORD DR BA 4 ADDRESS FOR AM9513A COUNT
22. charge provided that the product is returned shipping prepaid to RTD Embedded Technologies All replaced parts and products become the property of RTD Embedded Technologies Before returning any product for repair customers are required to contact the factory for an RMA number THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY PRODUCTS WHICH HAVE BEEN DAMAGED AS A RESULT OF ACCIDENT MISUSE ABUSE such as use of incorrect input voltages improper or insufficient ventilation failure to follow the operating instructions that are provided by RTD Embedded Technologies acts of God or other contingencies beyond the control of RTD Embedded Technologies OR AS A RESULT OF SERVICE OR MODIFICATION BY ANYONE OTHER THAN RTD Embedded Technologies EXCEPT AS EXPRESSLY SET FORTH ABOVE NO OTHER WAR RANTIES ARE EXPRESSED OR IMPLIED INCLUDING BUT NOT LIMITED TO ANY IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE AND RTD Embedded Technologies EXPRESSLY DISCLAIMS ALL WARRANTIES NOT STATED HEREIN ALL IMPLIED WARRANTIES INCLUDING IMPLIED WARRANTIES FOR MECHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE LIMITED TO THE DURATION OF THIS WARRANTY IN THE EVENT THE PRODUCT IS NOT FREE FROM DE FECTS AS WARRANTED ABOVE THE PURCHASER S SOLE REMEDY SHALL BE REPAIR OR REPLACEMENT AS PROVIDED ABOVE UNDER NO CIRCUMSTANCES WILL RTD Embedded Technologies BE LIABLE TO THE PURCHASER OR ANY USER FOR ANY DAMAGES INCLUD ING ANY INCIDENTA
23. first source edge following a valid gate edge in hardware triggered or enabled modes In gate controlled modes which inhibit counting the counter is suspended for any valid source edges that occur after de assertion of the gate line CTS9513AXI 2 ERRATA Although tested extensively to ensure full compliance with the original AM9513Axx device functions and operating modes several functional anomalies have come to our attention Both current and potential users of this device should take note of these Devices Affected All 1996 97 98 99 and 2000 devices manufactured to date Planned Action There are no immediate plans to correct these defects until further testing can be completed to detect any further anomalies MM14 MM13 MM12 MM11 MM10 MM9 MM15 0000 Divide by 16 0001 Divide by 1 0010 Divide by 2 0011 Divide by 3 0100 Divide by 4 0101 Divide by 5 1111 Divide by 16 MM8 SCALE POINT FGATE1 DIV1 8 DIV1 4 DIV1 2 DIV1 1 FOUT1 8 FOUT1 4 FOUT1 2 FOUT1 1 COMP2 COMP1 TOD2 TOD1 Work Arounds There is no current work around for these problems for existing designs CRYSTAL OSCILLATOR The CTS9513 does not incorporate a crystal oscilla tor and must be driven from an external TTL compati ble oscillator source COMMAND DATA READ WRITE DATA LATCH In this implementation of the 9513 data being written to the device is not latched on the rising trailing edge
24. in your DM5804 package RTD Embedded Technologies Inc offers a full line of board accessories Call your local distributor or our main office for more information about these accessories and for help in choosing the best items to support your board s application Accessories for the DM5804 include the TB50 terminal board and XB50 prototype terminal board for prototype development and easy signal access the DM14 extender board for testing your module and XT50 twisted pair wire flat ribbon cable assembly for external interfacing Using This Manual This manual is intended to help you install your new board and get it running quickly while also providing enough detail about the board and its functions so that you can enjoy maximum use of its features even in the most complex applications We assume that you already have an understanding of data acquisition and control principles and that you can customize the example software or write your own applications programs When You Need Help This manual and the example programs in the software package included with your board provide enough information to properly use all of the board s features If you have any problems installing or using this board contact our Technical Support Department 814 234 8087 during regular business hours eastern standard time or eastern daylight time or send a FAX requesting assistance to 814 234 5218 When sending a FAX request please include your company s name a
25. lower C3 CO The control word register can be both written and read as shown in the address decode table in the pin descriptions Figure 6 shows the control word format for both Read and Write operations When the control word is read bit D7 will always be a logic 1 as this implies control word mode information Ports A B and C The 82C55A contains three 8 bit ports A B and C All can be configured in a wide variety of functional characteristics by the system software but each has its own special features or personality to further enhance the power and flexibility of the 82C55A Port A One 8 bit data output latch buffer and one 8 bit input latch buffer Both pull up and pull down bus hold devices are present on Port A Port B One 8 bit data input output latch buffer Only pull up bus hold devices are present on Port B Port C One 8 bit data output latch buffer and one 8 bit data input buffer no latch for input This port can be divided into two 4 bit ports under the mode control Each 4 bit port contains a 4 bit latch and it can be used for the control signal outputs and status signal inputs in conjunction with ports A and B Only pull up bus hold devices are present on Port C See Figure 4 for the bus hold circuit configuration for Port A B and C 82C55A In o 5 POWER SUPPLIES vo PA PAQ Gnd GROUP A CONTROL ro PC PCa BIDIRECTIONAL DAT
26. outputs 3 Status of the counter interrupt outputs When reporting the status of the counter output the status bit reflects the exact state of the output pin regardless of how the output pin state or toggle is programmed Dx High Impedance Read Data Read Command Write Data Write Command Illegal Table 3 CTS9513 Bus Control Line States SPECIFICATIONS SUBJECT TO CHANGE WITHOUT NOTICE Copyright 2000 Celeritous Technical Services Corp Rev E Tuesday September 25 800 687 6510 806 793 0708 FAX 806 793 0710 http www celeritous com MODE CONTROL 16 BIT LOAD REGISTER Figure 5 CTS9513 Counter Groups 1 amp 2 Celeritous Technical Services Corp 3308 34th St Lubbock Texas 79410 SOURCE FREO GATE TCN 1 INPUT MUX CONTROL INT INT CNTL OUTPUT OUT CNTL TERM COUNT COUNTER CONTROL When an output low impedance to ground output is programmed the Status bit reflects and Active High status When the output is programmed for a high impedance output or is externally inhibited the status register reflects an active low output Table 7 summarizes the status register bit assignments Master Mode Commands The Master Mode registers are 16 bit read Write registers used to set counter parameters not associated with individual counters These parameters include setting the data bus width prescaling factors Time of day functions and data p
27. register and repeat as long as the Gate line is asserted While the Gate line is deasserted the counter is inhibited On the active going edge of the gate signal the counter is reloaded from the Load register resetting the counter and resume counting on the second valid source edge following the Gate edge If a valid Gate Edge is received prior to the counter reaching TC the counter value will be saved in the Hold register and the counter reloaded from the Load register retriggering or resetting the counter The counter in insensitive to the Gate level and gate actions do no inhibit the counter as in Mode Q SPECIFICATIONS SUBJECT TO CHANGE WITHOUT NOTICE Copyright 2000 Celeritous Technical Services Corp 21 Rev E Tuesday September 25 800 687 6510 806 793 0708 FAX 806 793 0710 http www celeritous com Celeritous Technical Services Corp 3308 34th St Lubbock Texas 79410 CTS9513 2 5 Chan 16 bit 20MHz Counter Timer SOURCE WR DATA X ARM COMMAND Y care BA A A AM AAN ANN pre dci xj COUNT VALUE L 1 Yr tX CTS WU Te ET TC OUTPUT TOGGLE OUTPUT COUNTER MODE S WAVEFORMS Figure 26 CTS9513 Counter Mode S Representative Waveforms SOURCE WR DATA y ARM COMMAND y AN AAA ARR COUNT VALUE H 1 Y H 2 y 2 Y 2 y 1 Y H fua Y H 2 Y gt y 2 y 1 y L Kia qun Y En y 1 X H y H 1 TC OUTPUT TOGGLE OUTPUT Y COUNTER MODE V WA
28. shows the major device elements consisting of e five counter groups e internal frequency prescaler which divides down the primary external clock source from clock input X2 e external FOUT clock prescalers which provide prescaled or divided outputs from a variety of sources e the Bus interface e Master mode register and e the status register Not shown are the extended set registers power on reset circuitry or internal control lines The counter group block diagrams are shown in Figures 5 and 6 Counter groups 1 and 2 as shown in Figure 5 have an additional programmable alarm register and 16 bit comparator for implementation of time of day and alarm functions Counter Groups All of the counter groups have a 16 bit counter and four programmable registers The primary and auxiliary counter mode register controls the count source gating and counting modes input and output polarities binary or BCD counting and other parameters Load Register The Load register is the primary register used for storing count up or count down values which may be automatically reloaded into the counter for repetitive counting Hold Register The Hold register may be used for storing the instantaneous count value without disturbing the count process for reading by the host system It may also be used in certain count modes for storing alternate count values and alternately counting the load and hold register values to generate complex wavef
29. storage and a new CS and IP are loaded from a table that exists in the lowest 1024 bytes of memory This table is referred to as the interrupt vector table and each entry is called an interrupt vector Once the new CS and IP are loaded from the interrupt vector table the processor begins executing the code located at CS IP When the interrupt routine is completed the CS IP and flags that were pushed on the stack when the interrupt occurred are now popped from the stack and execution resumes from the point where it was interrupted Using Interrupts in Your Programs Adding interrupts to your software is not as difficult as it may seem and what they add in terms of performance is often worth the effort Note however that although it is not that hard to use interrupts the smallest mistake will often lead to a system hang that requires a reboot This can be both frustrating and time consuming But after a few tries you ll get the bugs worked out and enjoy the benefits of properly executed interrupts In addition to reading the following paragraphs study the source code included on your DM5804 program disk in the interrupt programs for a better understanding of interrupt program development Writing an Interrupt Service Routine ISR The first step in adding interrupts to your software is to write the interrupt service routine ISR This is the routine that will automatically be executed each time an interrupt request occurs on the specified
30. strobing its data into the port INTE A Controlled by bit set reset of PC4 INTE B Controlled by bit set reset of PC 82C55A MODE 1 PORT A CONTROL WORD D Dg Ds Da Dz D D Do B BORED Plo 7 IBF 1 INPUT 0 OUTPUT INTRA RD 2 7 uo CONTROL WORD D Dg Ds D4 Dz D D Do XD DI INTR 231256 13 Figure 8 MODE 1 Input IBF INTR AD INPUT FROM LL LL Ll PERIPHERAL I tes 231256 14 Figure 9 MODE 1 Strobed Input 11 82C55A Output Control Signal Definition OBF Output Buffer Full F F The OBF output will go low to indicate that the CPU has written data out to the specified port The OBF F F will be set by the rising edge of the WR input and reset by ACK Input being low ACK Acknowledge Input A low on this input informs the 82C55A that the data from Port A or Port B has been accepted In essence a response from the peripheral device indicating that it has received the data output by the CPU INTR Interrupt Request A high on this output can be used to interrupt the CPU when an output device has accepted data transmitted by the CPU INTR is set when ACK is a one OBF is a one and INTE is a one It is reset by the falling edge of WR INTE A Controlled by bit set reset of PCg INTE B Controlled by bit set reset of PC CONTROL WORD D Dg Ds D D D D Dg Lo Io XD 1 eur 0 O
31. the extended Master Mode register functions FOUT Enable Bit MM12 The FOUT output may be enabled or disabled and placed in a low impedance state to ground under software control Bus Width Bit MM13 When set this bit places the device into a 16 bit external data bus mode When cleared the external data bus is set to 8 bits and registers are loaded 8 bits at a time least significant word first SPECIFICATIONS SUBJECT TO CHANGE WITHOUT NOTICE Copyright 2000 Celeritous Technical Services Corp RevE Tuesday September 25 800 687 6510 806 793 0708 FAX 806 793 0710 http www celeritous com Celeritous Technical Services Corp 3308 34th St Lubbock Texas 79410 Data Pointer Sequencing Bit MM14 When cleared this bit enables automatic sequencing of the data pointer as defined by the data pointer commands When set the data pointer contents may only be changed by command Scaling Bit MM15 This bit determines whether the internal frequency prescaler operates as a BCD or Binary Divider Figure 6 illustrates the internal 16 bit prescaler and its outputs COUNTER REGISTERS Load Register The load register is a read write counter register used to store the counter initial value The load register value can be transferred into the counter each time the counter reaches a terminal count A terminal count is defined as that period of time the counter value would have been zero if an external value had not b
32. the next register READING REGISTERS Reading from a device register follows the write sequence very closely requiring a write to the command register to set the appropriate data pointer followed by a read or reads from the data port Several items should be noted when reading from the device registers 1 The data pointer should always be reloaded before reading from the data port if the prior command was anything but a LOAD DATA POINTER command in order to update the Read data pre fetch latch 2 A LOAD DATA POINTER command should be issued to the device prior to reading a HOLD register following a hardware triggered SAVE of the counter contents to the HOLD register COMMANDS COUNTER COMMANDS Counter commands are divided into two main groups Those commands which directly affect counter operation often shortcuts to programming specific register functions and those associated with indirectly addressing the counters internal registers Counter control commands can be further subdivided into those commands which affect individual counter operation and those which affect the overall device operation Table 4 Lists the commands associated with indirect addressing of the counter internal registers These commands point the data port to the appropriate internal register in order to read or write to them Table 5 Lists the commands associated with controlling the actions of individual counters They are made up basically o
33. 0 Count Control Bits CM3 7 Whenever the counter reaches a TC the counter automatically reloads the counter from the Load or Hold Register Which register the counter loads from whether the counter counts repeatedly or once whether the counter counts binary or BCD and whether the counter is under hardware control is controlled by the Count control Bit CM3 controls whether the counter counts in Binary or BCD fashion Bit CM4 determines whether the counter counts up or down Bit CM5 determines whether the counter counts once and disarms itself or will continue counting and reloading the counter until commanded to disarm Bit CM6 determines the source from which the counter will be reloaded The actions of CM6 depend on the gating control settings If CM6 is cleared the counter reloads from the Load Register at TC If CM6 is set the counter may reload from either the Load or the hold register depending on the gating mode It may alternate with the Load register or be controlled from the gate to reload from the load or hold register Bit CM7 controls whether hardware retriggering of the counter is enabled Its actions depend on the settings of CM5 CM6 and the gating controls If some type of gating is enabled and CM7 is cleared hardware retriggering is disabled When CM7 is set hardware retriggering is enabled and the counter is retriggered any time an active gate edge is received When retriggered the counter value is saved in t
34. 00200r00n0onssnnsonsonsonsnnnnnnen 5 1 EXAMPLE Counting Program Using Timer Counters 1 2 and 3 sse 5 3 EXAMPLE Setting Up the Am9513A as a Frequency Counter essent nennen 5 8 APPENDIX A DM5804 SPECIFICATIONS ssur0u0suenesoronesssnnenesnssnsnnenssanenennssnennsnnsanenesssnnennsnnee A 1 APPENDIX B P2 CONNECTOR PIN ASSIGNMENTS 2 ur20r0u0020020020n0000000000n00000n0000nn0nenne00000 B 1 APPENDIX C COMPONENT DATA SHEETS asen sossen sono enesconsenveneonensencensenenseonenseneeneonenn C 1 APPENDIX D WARRANTY sten n nen D 1 1 1 1 2 1 3 1 5 1 6 1 7 2 1 3 1 5 1 5 2 5 3 List of Illustrations Board Layout Showing Factory Configured Settings eene envennvenvennvenvennvenvennerseeenveneeenvennn 1 3 Interrupt Channel Select Jumper P3 eese heiter Riesen 1 4 Pulling Down the Interrupt Request Line sees eene en nere nenne rentre 1 4 Interrupt Source Select Jumper Phronia eie oe E e nennen nennen trennen enr en rennen ne 1 5 Base Address S witch ST socer Ai 1 6 Port A and Port B Pull up Pull down Resistor Circuitry essent 1 6 Adding Pull ups and Pull downs to Some Digital VO Lines esee 1 7 PZI O Conn ctor Pin Assignments ere prete tee e y dete PE nde eee eerte 2 4 DM5804 Block Diagram ear edente du Mies eie REN ee aset ge even 3 3 Master Mode Register Bit Assignments nnen ons enneenvenvennvennerseenverse
35. 10 806 793 0708 FAX 806 793 0710 http www celeritous com Celeritous Technical Services Corp 3308 34th St Lubbock Texas 79410 CTS9513 2 5 Chan 16 bit 20MHz Counter Timer SOURCE WR DATA y ARM COMMAND Y care AA AAN COUNT VALUE L 1 y L 2 Y L 3 Y Eat y Fi y 1 y L y TC OUTPUT TOGGLE OUTPUT y COUNTER MODE C WAVEFORMS Figure 12 CTS9513 Counter Mode C Representative Waveforms SOURCE WR DATA Y ARM COMMAND y COCOON rn a ED COUNT VALUE L 1 Kea fra o a a e aa as d TC OUTPUT TOGGLE OUTPUT X COUNTER MODE D WAVEFORMS Figure 13 CTS9513 Counter Mode D Representative Waveforms MODE C HARDWARE TRIGGERED STROBE In Mode C as shown in Figure 12 the counter is active only after receipt of an ARM command and the application of a Gate edge to the selected gate line Once a Gate edge is sensed the counter will count until it reaches TC Subsequent gate actions have no further effect on the counter action The counter will remain inactive until receipt of a new ARM command and Gate MopE D RATE GENERATOR WITH NO HARDWARE GATING Mode D illustrated in Figure 13 is commonly used as a programmable frequency source as it continues to count repetitively until receipt of a DISARM command Once ARMed the counter counts to TC automatically reloads the counter from the Load register and begins counting again The waveform produced
36. 5 MODE 2 Bidirectional NOTE Any sequence where WR occurs before ACK and STB occurs before RD is permissible INTR IBF e MASK e STB e RD OBF e MASK e ACK e WR 14 82C55A MODE 2 AND MODE 0 INPUT CONTROL WORD D Dg Ds D Dz D D Dy DEVE MODE 2 AND MODE 1 OUTPUT INTRA EA CONTROL WORD aoe D Dg D D Da D D Do PDT 88 IBFA OBF RD PC2 fe ACK WR INTR MODE 2 AND MODE 0 OUTPUT CONTROL WORD D Dg Dg D Dz Dz D D LO PPP je ve PCzo 12 INPUT 0 OUTPUT WR gt Q MODE 2 AND MODE 1 INPUT CONTROL WORD D Dg Ds D D3 Dz D Do PP DPE DI RD _ 9 WR a 231256 21 Figure 16 MODE 1 4 Combinations 15 82C55A Mode Definition Summary MODE 2 GROUP A ONLY MODE 0 MODE 1 IN OUT IN OUT IN OUT IN OUT IN OUT IN OUT IN OUT IN OUT IN OUT IN OUT IN OUT IN OUT IN OUT IN OUT IN OUT IN OUT IN OUT IN OUT IN OUT IN OUT IN OUT IN OUT IN OUT IN OUT IN OUT IN OUT IN OUT IN OUT IN OUT IN OUT IN OUT IN OUT IN OUT IN OUT IN OUT INTRg INTRg IN OUT IBFg OBFg IN OUT STBg ACKg IN OUT INTRA INTRA IN OUT STBA 1 0 IN OUT IBF 1 0 IN OUT VO ACKA IN OUT 1 0 OBFA MODE 0 OR MODE 1 ONLY Special Mode Combination Considerations There are several combinat
37. A BUS 8 817 INTERNAL DATA BUS ro PC3 PCo WR 0 GROUP 8 CONTROL 231256 3 Figure 3 82C55A Block Diagram Showing Data Bus Buffer and Read Write Control Logic Functions RESET o EXTERNAL INTERNAL lt o PORT A DATA IN PIN INTERNAL DATA OUT WR Vcc RESET pt EXTERNAL lt Ho PORT B C PIN INTERNAL DATA WR NOTE 231256 4 Port pins loaded with more than 20 pF capacitance may not have their logic level guaranteed following a hardware reset Figure 4 Port A B C Bus hold Configuration intel 82C55A OPERATIONAL DESCRIPTION Mode Selection There are three basic modes of operation that can be selected by the system software Mode 0 Basic input output Mode 1 Strobed Input output Mode 2 Bi directional Bus When the reset input goes high all ports will be set to the input mode with all 24 port lines held at a logic one level by the internal bus hold devices see Figure 4 Note After the reset is removed the 82C55A can remain in the input mode with no addi tional initialization required This eliminates the need for pullup or pulldown devices in all CMOS de signs During the execution of the system program any of the other modes may be selected by using a single output instruction This allows a single 82C55A to service a variety of peripheral devices with a simple software maintenance routine The modes for Port A and Port B can be separately defined
38. B 2 RESULT OCATE 12 PRINT USING PRINT Hz ON KEY 1 GOTO MAIN toll H H 2 2 tg tg MSB 1 GOSUB QUIT To gurit KEY 1 ND OEF E CHECK IF INTERRUPT STATUS 1 CLEAR INTERRUPT STATUS DISARM amp SAVE COUNTERS 1 amp 2 TABLE 5 2 LOAD amp ARM COUNTERS 1 amp 2 TABLE 5 2 POINT TO COUNTER 1 HOLD REGISTER TABLE 5 1 READ COUNTER 1 LSB READ COUNTER 1 MSB READ COUNTER 2 LSB READ COUNTER 2 MSB x 256 ESR U2 256 2 4 MSB 2 256 3 RESULT 5 12 APPENDIX A DM5804 DM6804 SPECIFICATIONS A 2 DM5804 DM6804 Characteristics Typical 25 C Interface cpuModule amp other PC 104 form factor compatible Switch selectable base address I O mapped Jumper selectable interrupts Digital VO mE CMOS 82C55 Optional NMOS 8255 iINumber of llnes e de a lia 24 Eogic compatibility ccc 2 2 ee Hr ee TTL CMOS Configurable with optional I O pull up pull down resistors High level output voltage eese 4 2V min Low level output voltage nnen ennene ennen mene 0 45V max High level input voltage nnen nennnnnnenenennnennenrenenneneneneeen 2 2V min 5 5V max Low level input voltage nnen ennnnnneneeeenneneeeeenennneneenenn 0 3V min 0 8V max Input load CUfTeritu xs
39. CTS9513 does not provide an internal crystal oscillator and must be driven from an external source X1 should be left open X2 X2 should be connected to an external TTL source and pulled up to VCC FOUT Frequency Divider Outputs The FOUT line is generated by internally programmable counters The clock source for these counters may be any of the external GATE or SOURCE inputs as well as any of the internally prescaled clock outputs SOURCE1 5 Count Source Inputs Source inputs 1 5 provide external clock source lines which may be routed to any of the internal counters or the FOUT divider The active count edge for the source is programmed at the counter Table 1 Absolute Maximum Ratings SPECIFICATIONS SUBJECT TO CHANGE WITHOUT NOTICE Copyright 2000 Celeritous Technical Services Corp Rev E Tuesday September 25 Celeritous Technical Services Corp 800 687 6510 806 793 0708 CTS9513 2 3308 34th St FAX 806 793 0710 Lubbock Texas 79410 http www celeritous com 5 Chan 16 bit 20MHz Counter Timer PLCC 44 Package Pinouts A Pin Signal Pin Signal 1 VCC 23
40. Counters 1 and 2 are used to count the SRC1 input for 1 second intervals NOTE For this program to operate properly a jumper must be connected between OUTS pin 16 and GATEI pin 2 at I O connector P2 5MHz COUNTER 4 DIVIDER 10 000 COUNTER 5 DIVIDER 500 COUNTER 1 INTERRUPT STATUS BIT TRIGGER The first lines of the program clear the screen and set up the base address of the DM5804 The address in the variable BA must match the setting of the base address switch S1 on the board The factory setting of S1 is 300 hex 768 decimal CLS INPUT ENTER BASE ADDRESS IN D OCATE 2 25 ECIMAL BA OCATE 24 2 PRINT F1 QUIT ON VARIABLE RESULT The next section of the program sets up the computer screen CLS CLEAR SCREEN DIM RESULT AS DOUBLE DIMENSI KEY 1 ON TURN F1 KEY ON PRINT DM5804 FREQUENCY COUNTER DEMO PROGRAM The next section of the program sets up the address for the DM5804 registers These addresses are defined at the beginning of Chapter 4 PA BA 0 PB BA 1 PC BA 2 CW BA 3 DR BA 4 CR BA 5 IROEN BA 6 STAT BA 7 IROCLR BA 7 Next you must enable status generation OUT IROEN 1 OUT CR amp HFF ADDRESS ADDRESS ADDRESS ADDRESS ADDRESS ADDRESS FOR
41. D3 15 26 D 13 waveforms D4 16 25 GATE 5A D12 D0 15 Data Bus D5 17 24 GATE 4A D11 D0 15 form a bi directional 16 bit data bus for d B d een exchanging programming and status informa tion with a host processor or system These DI 19 22 GATE 2A D9 lines act as inputs to the counter when CS GATE Ax Lo 25 eit E ss and WR are asserted and as outputs when Figure 2 CTS9513 DIP 40 Package Pinouts RD and CS are asserted While CS is de asserted these lines are placed in a high impedance state SPECIFICATIONS SUBJECT TO CHANGE WITHOUT NOTICE Copyright 2000 Celeritous Technical Services Corp Rev E Tuesday September 25 800 687 6510 806 793 0708 FAX 806 793 0710 http www celeritous com Celeritous Technical Services Corp 3308 34th St Lubbock Texas 79410 On power up the data bus is configured for 8 bit transfers The data bus may be reconfig ured for 16 bit by programming Master Mode register Bit 13 If D8 15 are not used they should be pulled up ICS Chip Select Input The chip select line is an active low l O control signal used to enable the device for read and write operations IWR Write Input The write line is an active low I O control signal which is used to transfer information from the data bus to one of the internal command or data registers IRD Read Input The read line is an active low I O control signal which is used to transfer information from one of the internal data o
42. D8 ili 39 2 OUT2 24 VSS L J 3 NC 25 D9 m F 4 OUT1 26 D10 g E 5 GATE1 27 D11 i y 6 X1 28 D12 1 N 7 X2 29 D13 E 8 FOUT 30 D14 7 9 NC 31 D15 a ee 10 C D 32 NC A euer Elie 11 WR 33 SOURCE5 18 28 12 CS 34 SOURCE4 13 RD 35 SOURCE3 Figure 3 PLCC 44 Outline 14 NC 36 SOURCE2 15 DO 37 SOURCE CTSC9513A x A xX Sri Plastic DIP 40 P 19 D4 41 OUT5 Plastic PLCC 44 J 20 DS 42 OUT4 Temperature Range 21 D6 43 GATE2 22 D7 44 OUT3 Industrial 40 85 C Table 2 PLCC 44 Pinouts Maximum Clock Speed 20 MHz 2 VEC 1 O 40 OUT 3 Table 2 CTS9513 Ordering Information OUT 2 2 39 GATE 2 GATE1 5 Counter Gate Inputs Our es 3 en Gate inputs are used to control counter GATE 1 4 37 our 5 behavior Any gate may be routed to one of three internal counters They may also be e Ma used as clock or count input sources for the x2 6 35 GATE 4 internal counters or FOUT divider The GATE n 3d SANE lines may be programmed for use as counter a enables counter triggers or inhibits Individ C D 8 33 SOURCE 1 ual counters may be programmed for active WE y 4 SORER 9 polarity as well as to be level or edge sensitive to the GATE line cs 10 31 SOURCE 3 D m Sl euen di OUT1 5 Counter Outputs _ m OUT1 5 are associated with individual Be La 29 SOURCE 2 counters Outputs are tri state and may be D1 13 n E programmed by the counter for output polarity initialized to a given state and programmed for is 1A Er pulse square wave or complex duty cycle
43. DMS5804 DM6804 User s Manual O AD RTD Embedded Technologies Inc Real Time Devices Accessing the Analog World BDM 610010019 Rev A DM5804 DM6804 User s Manual RTD Embedded Technologies INC 103 Innovation Blvd State College PA 16803 0906 Phone 1 814 234 8087 FAX 1 814 234 5218 E mail sales rtd com techsupport rtd com web site http www rtd com Revision History Rev A New manual naming method Published by RTD Embedded Technologies Inc 103 Innovation Blvd State College PA 16803 0906 Copyright 1999 2002 2003 by RTD Embedded Technologies Inc All rights reserved Printed in U S A The RTD Logo is a registered trademark of RTD Embedded Technologies cpuModule and utilityModule are trademarks of RTD Embedded Technologies PhoenixPICO and PheonixPICO BIOS are trademarks of Phoenix Technologies Ltd PS 2 PC XT PC AT and IBM are trademarks of International Business Machines Inc MS DOS Windows Windows 95 Windows 98 and Windows NT are trademarks of Microsoft Corp PC 104 is a registered trademark of PC 104 Consortium All other trademarks appearing in this document are the property of their respective owners Table of Contents INTRODUCTION aus a T T 1 1 Ain9513 A Tirmer Countet see n eet hr t tte e e ea dende dede sug cust a dad beende aalst genen i 3 Digital VO ssi intento ep nem Re EE eo om d etre de etn i 3 What Comes With Your Board edet TR dende twins Ck e
44. ER DATA REGISTER CR BA 5 ADDRESS FOR AM9513A COUNTER CONTROL REGISTER IROEN BA 6 ADDRESS FOR INTERRUPT ENABLE STAT BA 7 ADDRESS TO READ INTERRUPT STATUS IROCLR BA 7 ADDRESS TO CLEAR INTERRUPT STATUS BIT Now reset the Am9513A timer counter chip see Table 5 2 OUT CR amp HFF AM9513A MASTER RESE 5 3 Table 5 1 Load Data Pointer Commands Element Cycle Hold Cycle Mode Load Hold Hold Register Register Register Register Counter 1 Counter 2 Counter 3 Counter 4 Counter 5 Master Mode Register 17 Alarm 1 Register 07 Alarm 2 Register OF Status Register 1F NOTE All codes are in hex Next set up the Am9513A master mode register see Figure 5 1 These are the settings we will use Scaler Control binary division Data Pointer Control disable increment Data Bus Width 8 bits FOUT Gate FOUT on FOUT Divider divide by 16 FOUT Source Fl see Figure 5 3 Compare 2 Enable disabled Compare 1 Enable disabled Time of Day Mode disabled VALUE HEX 4000 OUT CR H17 POINT TO MASTER MODE REGISTER TABLE 5 1 OUT DR amp HO MASTER MODE LSB OUT DR amp H40 MASTER MODE MSB Next set up the counter 1 mode register see Figure 5 2 These are the settings we will use Gating Control no gating Source Edge rising edge Count Source Sele
45. F5 0 count down 1 count up Source Edge 0 count on rising edge 1 count on falling edge Output Control 000 inactive output low 001 active high terminal pulse count 010 TC toggled 011 not used Gating Control 000 no gating 001 active high TCN 1 100 inactive output high impedance 010 active high level gate N 101 active low terminal pulse count 1 110 not used 011 active high level gate N 1 111 not used 100 active high level gate N 101 active low level gate N 110 active high edge gate N 111 active low edge gate N Fig 5 2 Counter Mode Register Bit Assignments Next set up the counter 3 mode register see Figure 5 2 These are the settings we will use Gating Control no gating Source Edge rising edge Count Source Selection TCN 1 Count Control disable special gate reload from load count repetitively binary count count up Output Control TC toggled VALUE HEX 002A OUT CR amp H3 POINT TO COUNTER 3 MODE REGISTER TABLE 5 1 OUT DR amp H2A COUNTER 3 MODE LSB OUT DR amp HO COUNTER 3 MODE MSB 5 7 X2 BCD BCD Scaling MM15 1 MM15 1 Binary Scaling MM15 0 With On board With On board eed 5 MHz C
46. FOR FOR FOR FOR FOR 8255 PORT A 8255 PORT B 8255 PORT C 8255 CONTROL WORD AM9513A COUNTER DATA REGI STER AM9513A COUNTER CONTROL R EGISTER ADDRESS FOR INTERRUPT ENABLE ADDRESS O RE AD INTERRUPT STATUS ADDRESS AM9513A O CLE AR INTERRUPT STATUS BIT Now reset the Am9513A timer counter chip see Table 5 2 MAST ER RESET Next set up the Am9513A master mode register see Figure 5 1 These are the settings we will use Scaler Control binary division Data Pointer Control enable increment Data Bus Width 8 bits FOUT Gate FOUT on FOUT Divider divide by 16 FOUT Source Fl see Figure 5 3 Compare 2 Enable disabled Compare 1 Enable disabled Time of Day Mode disabled VALUE HEX 0000 OUT CR amp H17 POINT TO MASTER MODE REGISTER TABLE 5 1 OUT DR amp HO MASTER MODE LSB OUT DR amp HO MASTER MODE MSB Next set up the counter mode register see Figure 5 2 These are the settings we will use Gating Control active low gate n Source Edge rising edge Count Source Selection SRC1 Count Control disable special gate reload from load count repetitively binary count count up Output Control active high TC VALUE HEX A129 OU
47. G REGISTER PROGRAMMING Data Bus Operation Table 3 summarizes the l O control signal and data status during bus reads and writes to the CTS9513 The interface control logic assumes that e RD and WR are never active simultaneously e RD WR C D are ignored unless CS is asserted Register Programming Accessing and writing to a specific data or command register from the data port is as follows Set Data Pointer 1 Select the appropriate data pointer value to access the desired register example Counter group 1 Mode register 0x01 2 Write LOAD DATA POINTER command to primary command address write 0x0001 to device address 0x01 to set data pointer to Counter Group 1 Mode register This points the data port to the Group 1 mode register and set the word pointer to 1 indicating a least significant word is expected WRITING TO REGISTERS Write Data to Register 1 If the 16 bit transfer mode is selected the next write to the Primary Data Port Device Address 0x00 will write data to the Counter mode register 2 If the 8 bit transfer mode is selected the next write to the Primary Data Port Address will expect the least significant word of the register value followed by a CTS9513 2 5 Chan 16 bit 20MHz Counter Timer write of the most significant word to the data port The internal word pointer is automatically incremented 3 If an automatic sequence command has been given the data pointer will automatically be sequenced to
48. J and K the counter cycles through the load count reloads from the hold at the first TC and counts to the second TC Unlike Modes J and K however the counter is only active after being ARMed and after a valid gate edge is received As shown in Figure 21 the gate edge initiates one count cycle and is disregarded for the rest of the cycle After one count cycle Load and Hold the counter stops until another gate edge is received SPECIFICATIONS SUBJECT TO CHANGE WITHOUT NOTICE Copyright 2000 Celeritous Technical Services Corp 19 Rev E Tuesday September 25 800 687 6510 806 793 0708 FAX 806 793 0710 http www celeritous com Celeritous Technical Services Corp 3308 34th St Lubbock Texas 79410 CTS9513 2 5 Chan 16 bit 20MHz Counter Timer SOURCE WR DATA y ARM COMMAND Y care AAN L 1 ae y ol a X COUNT VALUE TC OUTPUT TOGGLE OUTPUT COUNTER MODE N WAVEFROMS Figure 22 CTS9513 Counter Mode N Representative Waveforms SOURCE WR DALA X ARM COMMAND Y care AAA BAUM AQ QUA L 1 y L 2 y mi y N 1 y COUNT VALUE K L y L 1 Y L 2 X M i 1 Y L K L 1 TC OUTPUT TOGGLE OUTPUT COUNTER MODE O WAVEFORMS Figure 23 CTS9513 Counter Mode O Representative Waveforms MopE N SOFTWARE TRIGGERED STROBE WITH LEVEL GATING AND HARDWARE RETRIGGERING In Mode N once ARMed the counter is active only as long at the selected Gate line is as
49. Jumper P4 S1 Base Address Factory Setting 300 hex 768 decimal One of the most common causes of failure when you are first trying your board is address contention Some of your computer s I O space is already occupied by internal I O and other peripherals When the DM5804 board attempts to use I O address locations already used by another device contention results and the board does not work To avoid this problem the DM5804 has an easily accessible DIP switch S1 which lets you select any one of 64 starting addresses in the computer s I O Should the factory setting of 300 hex 768 decimal be unsuitable for your system you can select a different base address simply by setting the switches to any value shown in Table 1 2 The table shows the switch settings and their corresponding decimal and hexadecimal in parentheses values Make sure that you verify the order of the switch numbers on the switch 1 through 6 before setting them When the switches are pulled forward they are OPEN or set to logic 1 as labeled on the DIP switch package When you set the base address for your board record the value in the table inside the back cover Figure 1 5 shows the DIP switch set for a base address of 300 hex 768 decimal Table 1 2 Base Address Switch Settings S1 Base Base Base Base Address Switch Address Switch Address Switch Address Switch Decimal Setting Decimal Setting Decimal Setting Decimal Setting Hex 654321 Hex 654321
50. L OR CONSEQUENTIAL DAMAGES EXPENSES LOST PROFITS LOST SAVINGS OR OTHER DAMAGES ARISING OUT OF THE USE OR INABILITY TO USE THE PRODUCT SOME STATES DO NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR CONSUMER PRODUCTS AND SOME STATES DO NOT ALLOW LIMITATIONS ON HOW LONG AN IMPLIED WARRANTY LASTS SO THE ABOVE LIMITATIONS OR EXCLUSIONS MA Y NOT APPLY TO YOU THIS WARRANTY GIVES YOU SPECIFIC LEGAL RIGHTS AND YOU MAY ALSO HAVE OTHER RIGHTS WHICH VARY FROM STATE TO STATE D 3 RTD Embedded Technologies Inc 103 Innovation Blvd State College PA 16803 0906 USA Our website www rtd com D 4
51. O Clear MM14 enable data pointer sequencing 1 1 1 0 0 1 1 O Clear MM12 gate on FOUT 1 1 1 0 0 1 1 1 Clear MM13 enter 8 bit bus mode O Enable prefetch for write operations ojo ojo 1 1 1 1 1 1 Disable prefetch for write operations 1 1 1 1 1 1 1 1 Master reset Not to be used for asynchronous operations Put the hex number 2710 decimal 10 000 in counter 1 load register OUT CR amp H9 POINT TO COUNTER 1 LOAD REGISTER TABLE 5 1 OUT DR amp H10 COUNTER 1 LSB OUT DR amp H27 COUNTER 1 MSB Next set up the counter 2 mode register see Figure 5 2 These are the settings we will use Gating Control no gating Source Edge rising edge Count Source Selection TCN 1 Count Control disable special gate reload from load count repetitively binary count count down Output Control TC toggled VALUE HEX 0022 5 5 FOUT Divider 0000 divide by 16 0001 divide by 1 0010 divide by 2 0011 divide by 3 0100 divide by 4 0101 divide by 5 0110 divide by 6 0111 divide by 7 1000 divide by 8 1001 divide by 9 1010 divide by 10 1011 divide by 11 1100 divide by 12 1101 divide by 13 1110 divide by 14 1111 divide by 15 FOUT Gate 0 FOUT on 1 FOUT off low Z to gnd Data Bus Width 0 8 bit bus 1 16 bit bus Data Pointer Control 0 enable increment
52. T CR amp H1 POINT TO COUNTER 1 MODE REGISTER TABLE 5 1 OUT DR amp H29 COUNTER 1 MODE LSB OUT DR amp HA1 COUNTER 1 MODE MSB Put the hex number 0000 decimal 0 in counter 1 load register OUT CR amp H9 POI TO COUNTER 1 LOAD REGISTER TABLE 5 1 OUT DR amp HO COUNTER 1 LSB OUT DR amp HO COUNTER 1 MSB Next set up the counter 2 mode register see Figure 5 2 These are the settings we will use Gating Control no gating Source Edge rising edge Count Source Selection TCN 1 Count Control disable special gate reload from load count repetitively binary count count up Output Control active high TC VALUE HEX 0029 OUT CR H2 POINT TO COUNTER 2 MODE REGISTER TABLE 5 1 OUT DR H29 COUNTER 2 MODE LSB OUT DR amp HO COUNTER 2 MODE MSB Put the hex number 0000 decimal 0 in counter 2 load register OUT CR HA POINT TO COUNTER 2 LOAD REGISTER TABLE 5 1 OUT DR amp HO COUNTER 2 LSB OUT DR amp HO COUNTER 2 MSB Next set up the counter 4 mode register see Figure 5 2 These are the settings we will use Gating Control no gating Source Edge rising edge Count Source Selection Fl Count Control disable special gate reload from load count repetitively binary count count down Output Control TC toggled VALUE HEX 0B22
53. UT 10 INPUT OUTPUT 1 0 1 1 INPUT OUTPUT 11 INPUT INPUT 1 1 0 0 INPUT INPUT 12 OUTPUT OUTPUT 1 1 0 1 INPUT INPUT 18 OUTPUT INPUT 1 1 1 0 INPUT INPUT 14 INPUT OUTPUT 1 1 1 1 INPUT INPUT 15 INPUT INPUT MODE 0 Configurations CONTROL WORD 0 D D Ds D D D D Dy Di PA PAY PC PC PC PC PB PB CONTROL WORD 2 D Dg D D D D D D PAPA PC PC PC PC P8 PB CONTROL WORD 1 D De D D D D D Dy 07 0 CONTROL WORD 43 D Dg Ds D D D Dy Do DD 5 PAPA PC PC 4 AS ee Pc 8 P8 P8 231256 10 intel MODE 0 Configurations Continued 82C55A CONTROL WORD 4 D D D D D D Ds D CONTROL WORD 8 D Ds Dy D DD PAPAS 82C55A PC PC DD D Dy 4 PC PC P8 PB CONTROL WORD 5 CONTROL WORD 49 D Dg Dg D D 82C55A CONTROL WORD 46 CONTROL WORD 10 B2C55A PB PB CONTROL WORD 7 PAPA 82C55A PC PC DD 4 i CL CPC E ppp CONTROL WORD 11 PB PR 231256 11 82C55A MODE 0 Configurations Continued CONTROL WORD 12 D Dg D D Dz D D Do SES 4 I 4L rc Pc PC3PCy PB PBy CONTROL WORD 14 by De Ds Oy Dy Dy D Do DD CONTROL WORD 413 D De Ds D Dz Dj D D 0 0
54. UTPUT CONTROL WORD D De Ds Dy D D D Do DDP 23125615 Figure 10 MODE 1 Output OBF INTR OUTPUT we 231256 16 Figure 11 MODE 1 Strobed Output 12 intel Combinations of MODE 1 82C55A Port A and Port B can be individually defined as input or output in Mode 1 to support a wide variety of strobed I O applications CONTROL WORD D Dg Dy D Dz Dz D Dy aaa P657 1 INPUT 0 OUTPUT WR 0 PORT A STROBED INPUT PORT B STROBED OUTPUT WR 3 CONTROL WORD D De Ds D Dz D D Do ES PCy 5 1 INPUT 0 OUTPUT RD gt o PORT A STROBED OUTPUT PORT B STROBED INPUT 231256 17 Figure 12 Combinations of MODE 1 Operating Modes MODE 2 Strobed Bidirectional Bus l O This functional configuration provides a means for com municating with a peripheral device or structure on a single 8 bit bus for both transmitting and receiving data bidirectional bus 1 0 Handshaking signals are provided to maintain proper bus flow discipline in a similar manner to MODE 1 Interrupt generation and enable disable functions are also available MODE 2 Basic Functional Definitions Used in Group A only One 8 bit bi directional bus port Port A and a 5 bit control port Port C e Both inputs and outputs are latched The 5 bit control port Port C is used for control and status for
55. VEFORMS Figure 27 CTS9513 Counter Mode V Representative Waveforms MODE S GATE CONTROLLED STROBE In Mode S once ARMed the counter will count to TC twice and disarm During this time the State of the Gate line determines whether the counter is loaded from the Load or Hold Register The Gate line does not affect or initiate the counter in this Mode Its only action is a level sensitive selection of the Load or Hold Register as a counter reload source As shown in Figure 26 at each TC in the cycle if the Gate line is high the counter will be reloaded from the Hold Register If it is Low the counter is reloaded from the Load Register MoDE V FREQUENCY SHIFT KEYING Mode V is similar to mode S in that the Gate line act to select which register the counter is reloaded from but counts continuously once armed If the Toggled output is used the output may be used to switch between two frequencies determined by the Load and Hold Count values and the state of the Gate line as shown in Figure 27 This is used in Frequency Shift Keying FSK applications NOTE This mode does not function correctly in current devices Please see the ERRATA section for more information Copyright 2000 Celeritous Technical Services Corp 22 SPECIFICATIONS SUBJECT TO CHANGE WITHOUT NOTICE Rev E Tuesday September 25 Celeritous Technical Services Corp 800 687 6510 806 793 0708 CTS9 51 3 2 3308 34th St FAX 806 793 0710 Lubbock Texas 79410 http
56. VOLTS PIN 49 12 VOLTS DIGITAL GND P2 Mating Connector Part Numbers Manufacturer Part Number 1 746094 0 3425 7650 B 3 B 4 C 1 APPENDIX C COMPONENT DATA SHEETS AMD Am9513A System Timing Controller Data Sheet Reprint 800 687 6510 806 793 0708 FAX 806 793 0710 http www celeritous com Celeritous Technical Services Corp 3308 34th St Lubbock Texas 79410 FUNCTIONS Five 16 bit programmable up down counters Programmable Pulse Generation Programmable Delay Generator Pulse Measurement Event Counting Frequency Measurement System Synchronization Real Time Clock APPLICATIONS e Computer System Timing Real Time Clock with Alarm Watchdog Timer Programmable System Bus Clock Wait State Generation e Data Acquisition Programmable Converter Clock Pulse Measurement Frequency Counter Event Counter e ATE Programmable Stimulus Generator Timing Extremes Generator e Laser Systems Timing Sequencer Programmable Delay Generator External Equipment Synchronization Burst Mode Generator e Industrial Process Control Pulse Frequency Sensor conversion System Timing Synchronization EXTENDED FEATURES e Up to 20 MHz Maximum input frequency e Lower Power STANDARD AM9513 FEATURES Five independent 16 bit counters Up Down Binary BCD Counting Internal Binary BCD Prescaling One Shot Continuous Outputs Software External triggering Tri state Outputs Programmable output polarities Programmabl
57. able BIT RESET INTE is RESET Interrupt disable Note All Mask flip flops are automatically reset during mode selection and device Reset intel Operating Modes Mode 0 Basic Input Output This functional con figuration provides simple input and output opera tions for each of the three ports No handshaking is required data is simply written to or read from a specified port MODE 0 BASIC INPUT 82C55A Mode 0 Basic Functional Definitions Two 8 bit ports and two 4 bit ports Any port can be input or output Outputs are latched e Inputs are not latched e 16 different Input Output configurations are pos sible in this Mode tig gt INPUT tag gt ate CS A1 A0 tur 231256 8 MODE 0 BASIC OUTPUT D D taw CS A1 AU OUTPUT twe twa 231256 9 82C55A MODE 0 Port Definition intel A B GROUP A GROUP B Da Dz D4 Do PORTA UBER 4 PORT B LONEN 0 0 0 0 OUTPUT OUTPUT 0 OUTPUT OUTPUT 0 0 0 1 OUTPUT OUTPUT 1 OUTPUT INPUT 0 0 1 0 OUTPUT OUTPUT 2 INPUT OUTPUT 0 0 1 1 OUTPUT OUTPUT 3 INPUT INPUT 0 1 0 0 OUTPUT INPUT 4 OUTPUT OUTPUT 0 1 0 1 OUTPUT INPUT 5 OUTPUT INPUT 0 1 1 0 OUTPUT INPUT 6 INPUT OUTPUT 0 1 1 1 OUTPUT INPUT 7 INPUT INPUT 1 0 0 0 INPUT OUTPUT 8 OUTPUT OUTPUT 1 0 0 1 INPUT OUTPUT 9 OUTPUT INPUT 1 0 1 0 INPUT OUTP
58. aken into account things such as effi cient PC board layout control signal definition vs PC layout and complete functional flexibility to support almost any peripheral device with no external logic Such design represents the maximum use of the available pins Single Bit Set Reset Feature Any of the eight bits of Port C can be Set or Reset using a single OUTput instruction This feature re duces software requirements in Control based appli cations When Port C is being used as status control for Port A or B these bits can be set or reset by using the Bit Set Reset operation just as if they were data output ports 82C55A CONTROL WORD BIT SET RESET 1 SET O RESET BIT SELECT 1 o BIT SET RESET FLAG 0 AcTIvE 231256 7 Figure 7 Bit Set Reset Format intel When the 82C55A is programmed to operate in mode 1 or mode 2 control signals are provided that can be used as interrupt request inputs to the CPU The interrupt request signals generated from port C can be inhibited or enabled by setting or resetting the associated INTE flip flop using the bit set reset function of port C Interrupt Control Functions This function allows the Programmer to disallow or allow a specific 1 O device to interrupt the CPU with out affecting any other device in the interrupt struc ture INTE flip flop definition BIT SET INTE is SET Interrupt en
59. ata Bus Port A 0 1 1 0 0 Data Bus Port B 1 0 1 0 0 Data Bus Port C 1 1 1 0 0 Data Bus Control Disable Function X X X X 1 Data Bus 3 State X X 1 1 0 Data Bus 3 State PC7_4 10 13 11 13 15 I O PORT C PINS 4 7 Upper nibble of an 8 bit data output latch buffer and an 8 bit data input buffer no latch for input This port can be divided into two 4 bit ports under the mode control Each 4 bit port contains a 4 bit latch and it can be used for the control signal outputs and status signal inputs in conjunction with ports A and B PCo 3 14 17 16 19 1 0 PORT C PINS 0 3 Lower nibble of Port C PBo 7 18 25 20 22 I O PORT B PINS 0 7 An 8 bit data output latch buffer and an 8 24 28 bit data input buffer Vec 26 29 SYSTEM POWER 5V Power Supply D7 0 27 34 30 33 O DATA BUS Bi directional tri state data bus lines connected to 35 38 system data bus RESET 35 39 RESET A high on this input clears the control register and all ports are set to the input mode WR 36 40 WRITE CONTROL This input is low during CPU write operations PA7_4 37 40 41 44 I O PORT A PINS 4 7 Upper nibble of an 8 bit data output latch buffer and an 8 bit data input latch NC 1 12 No Connect 23 34 intel 82C55A FUNCTIONAL DESCRIPTION General The 82C55A is a programmable peripheral interface device designed for use in Intel microcomputer sys tems lts function is that of a general purpose I O component to interface peri
60. ate buffer to G ground for buffer ground G for multiple interrupt applications interrupt channels disabled D Selects the interrupt source EXTINT Sets the base address 300 hex 768 decimal u u 5 9 gt gt te Fig 1 1 Board Layout Showing Factory Configured Settings P3 Interrupt Channel Select Factory Setting G Connected Interrupt Channels Disabled This header connector shown in Figure 1 2 lets you connect an interrupt source selected on P4 to an interrupt channel IRQ2 through IRQ7 IRQ10 11 12 14 and 15 can only be used if you have the DM6804 with the AT connector J6 installed To connect the interrupt source selected on P4 to an IRQ channel you must install a jumper across the desired IRQ channel Figure 1 2a shows the factory setting and Figure 1 2b shows IRQ3 selected 0233723250 ob ON DEE paste aS eh P3 P3 5 5 o o Fig 1 2a IRQ Disabled Fig 1 2b IRQ3 Selected Fig 1 2 Interrupt Channel Select Jumper P3 The leftmost pair of pins on P3 labeled G are provided so that you can install a jumper which connects a 1 kilohm pull down resistor to the output of a high impedance tri state driver which carries the interrupt request signal This pull down resistor drives the interrupt request line low whenever interrupts are not active So whenever an interrupt request is made the tri state buffer is enabled forcing the output high and causing an interrupt You can monitor the interrup
61. binary or BCD and hardware or software gating these timer counters can be easily tailored for a wide variety of applications The timer counters are clocked by an on board 5 MHz crystal The source gate and output for each timer counter is available at the P2 I O connector Digital VO The DM3804 has 24 TTL CMOS compatible digital 1 O lines which can be directly interfaced with external devices or signals to sense switch closures trigger digital events or activate solid state relays These lines are provided by the on board 8255 programmable peripheral interface chip Pads for installing and activating pull up or pull down resistors are included on the board Installation procedures are given at the end of Chapter 1 Board Settings AT Bus Comnector J6 DM6804 The DM6804 is exactly the same as the DM5804 except for the addition of the AT bus connector J6 This allows you to stack the module with CPU s that have the AT bus connectors and access the AT interrupts What Comes With Your Board You receive the following items in your DM5804 package e DM5804 interface board with stackthrough bus header Software and diagnostics diskette with BASIC Turbo Pascal and Turbo C source code User s manual If any item is missing or damaged please call Real Time Devices Customer Service Department at 814 234 8087 If you require service outside the U S contact your local distributor Board Accessories In addition to the items included
62. can be a square wave if the Toggle output mode is specified The Gate line has no effect on the counter action SPECIFICATIONS SUBJECT TO CHANGE WITHOUT NOTICE Copyright 2000 Celeritous Technical Services Corp Rev E Tuesday September 25 800 687 6510 806 793 0708 FAX 806 793 0710 http www celeritous com Celeritous Technical Services Corp 3308 34th St Lubbock Texas 79410 CTS9513 2 5 Chan 16 bit 20MHz Counter Timer SOURCE WR DATA ji ARM COMMAND X care A X L 2 Y L 3 X K 2 K K l y COUNT VALUE L 1 K y K 1 y zie ji 2 y 1 y L y L 1 TC OUTPUT TOGGLE OUTPUT COUNTER MODE E WAVEFORMS Figure 14 CTS9513 Counter Mode E Representative Waveforms SOURCE WR DATA y ARM COMMAND X care A AA AO COUNT VALUE L 1 N L 1 y L 2 y L 3 Y 2 y 1 Y L y L 1 y L 2 X L 3 X TC OUTPUT TOGGLE OUTPUT COUNTER MODE F WAVEFORMS Figure 15 CTS9513 Counter Mode F Representative Waveforms MODE E RATE GENERATOR WITH LEVEL GATING Mode E is similar to Mode D in that the counter will count repetitively after being ARMed and as long as the selected Gate line is asserted As shown in Figure 14 this allows gating of the pulse train or square wave on and off from an external source via the gate line Mope F NoN RETRIGGERABLE ONE SHOT Mode F is similar to Mode C with the exception that the counter may be retriggered without receip
63. ct The 82C55A is available in 40 pin DIP and 44 pin plastic leaded chip carrier PLCC packages POWER TM SUPPLIES 820554 ano vo p PA7 PAG GROUP A CA o KE SELL verbe UPPER i a a PE BIDIRECTIONAL DATA BUS D7 09 gt ser INTERNAL ene DATA BUS vo LA ore Ke cardo LOWER gI vo P87 PBO 82C55A 231256 1 Figure 1 82C55A Block Diagram 231256 2 Figure 2 82C55A Pinout Diagrams are for pin reference only Package sizes are not to scale October 1995 Order Number 231256 004 u 2 A 32055 intel Table 1 Pin Description Symbol Pin Number Type Name and Function ymmo Dip pLcc YP PA3_o 1 4 2 5 O PORT A PINS 0 3 Lower nibble of an 8 bit data output latch buffer and an 8 bit data input latch RD READ CONTROL This input is low during CPU read operations cs CHIP SELECT A low on this input enables the 82C55A to respond to RD and WR signals RD and WR are ignored otherwise GND 7 8 System Ground A1 0 8 9 9 10 ADDRESS These input signals in conjunction RD and WR control the selection of one of the three ports or the control word registers A4 Ao RD WR CS Input Operation Read 0 0 0 1 0 Port A Data Bus 0 1 0 1 0 Port B Data Bus 1 0 0 1 0 Port C Data Bus 1 1 0 1 0 Control Word Data Bus Output Operation Write 0 0 1 0 0 D
64. ction Fl Count Control disable special gate reload from load count repetitively binary count count down Output Control TC toggled VALUE HEX 0B22 OUT CR amp Hl POINT TO COUNTER 1 MODE REGISTER TABLE 5 1 OUT DR amp H22 COUNTER 1 MODE LSB OUT DR amp HOB COUNTER 1 MODE MSB 5 4 Table 5 2 Am9513A Command Summary Command Code C7 C6 C5 C4 C3 C2 C1 Command Description Load data pointer register with contents of E amp G fields E 000 0 0 E2 E1 G4 G2 G1 G 110 E 8 G fields described in Appendix C 0 1 S5 S4 S3 S2 S1 Arm counting for all selected counters 1 0 S5 S4 S3 S2 S1 Load contents of specified source into all selected counters 1 1 S5 S4 S3 S2 S1 Load amp arm all selected counters 1 0 0 S5 S4 S3 S2 S1 Disarm amp save all selected counters 0 1 S5 S4 S3 S2 S1 Save all selected counters in hold register 1 1 0 S5 S4 S3 S2 S1 Disarm all selected counters 1 1 1 0 1 N4 N2 N1 Set toggle out high for counter N 001 2 N 2 101 1 1 1 0 0 N4 N2 N1 Clear toggle out low for counter N 001 2N 2 101 1 1 1 1 0 N4 N2 N1 Step counter N 001 2N 101 1 1 1 0 1 0 0 O Set MM14 disable data pointer sequencing 1 1 1 0 1 1 1 0 Set MM12 gate off FOUT 1 1 1 0 1 1 1 1 Set MM13 enter 16 bit bus mode 1 1 1 0 0 0 0
65. d CL and CH take 6 pin packs Figure 1 6 shows a blowup of PA and PB O Ai pou preter mee rome Fig 1 6 Port A and Port B Pull up Pull down Resistor Circuitry After the resistor packs are installed you must connect them into the circuit as pull ups or pull downs Locate the three hole pads on the board near the resistor packs They are labeled G for ground on one end and V for Vcc on the other end The middle hole is common PA is for Port A PB for Port B CL is for Port C Lower and CH is for Port C Upper Figure 1 6 shows a blowup of the pads for Port A and Port B To operate as pull ups solder a jumper wire between the common pin middle pin of the three and the V pin For pull downs solder a jumper wire between the common pin middle pin and the G pin For example Figure 1 7 shows Port A lines with pull ups Port C Lower with pull downs and Port C Upper with no resistors Fig 1 7 Adding Pull ups and Pull downs to Some Digital I O Lines 1 7 CHAPTER 2 BOARD INSTALLATION The DM5804 is easy to install in your cpuModule or other PC 104 based system This chapter tells you step by step how to install and connect the board After you have installed the board and made all of your con nections you can turn your system on and run the 5804DIAG board diagnostics program included on your example software disk to verify that your board is working 2 1 2 2 Board Installation Keep the b
66. d Register Counter 5 Load Register Reserved Alarm Register 2 Control Cycle Reserved Counter 1 Hold Register Counter 2 Hold Register Counter 3 Hold Register Counter 4 Hold Register Counter 5 Hold Register efjojojojeolo ofjojojojojojojojojojojojojojojojojo efjojojojeolo ofjojojojojojojojojojojojojojojojojo efjojojojolo ofjojojojojojojojojojojojojojojojojo Ria e aja le rajejojojojojojojojojojojojojojojojo olololololo ofjo j r rje rjieje jojojojojojojojo ele jeje ol Oo RR RR ol ol ol ole RRR ol ololo rjieajojojea e ol ol RR ol ol eje ojoje e ojo jojo BO RO O H Oo RO Oo Ro RB Oo Ro Ro PR onmjie Reserved Master Mode Register Control Cycle o jo jo 1 1 0 0 O Reserved o jo jo 1 1 JO O 1 Hold Register Cycle o jo jo 1 1 O 1 O Hold Register Cycle o jo jo 1 1 0 1 1 Hold Register Cycle 0 jo jo 1 1 1 0 O Hold Register Cycle 0 o jO 1 1 1 jO 1 Hold Register Cycle 0 O jo jl 1 1 O Reserved o jo Jo 1 1 1 1 1 Status Register Table 4 CTS9513 Data Pointer Commands SPECIFICATIONS SUBJECT TO CHANGE WITHOUT NOTICE Copyright 2000 Celeritous Technical Services Corp 8 Rev E Tuesday September 25 800 687 6510 806 793 0708 FAX 806 793 0710 http www celeritous com Celeritous Technical Services Corp 3308 34th St Lubbock Texas 7941
67. d Register Value 4 Disarm itself and reload the counter with the Load register Value This produces a waveform as illustrated in Figure 16 in which the counter can in TC mode produce a pair of pulses with the first pulse delay controlled by the Load count value and the delay between the pulses determined by the Hold register count If the Toggle Output mode is selected the output produced is a pulse width determined by the Hold count and an initial delay determined by the Load count This is the more common use of this mode of operation MoDE H SOFTWARE TRIGGERED DELAYED PULSE ONE SHOT WITH HARDWARE GATING Mode H is similar to Mode G with the exception that the counter is active only after receipt of an ARM command and a valid Gate input As shown in Figure 17 the counter counts only as long as the Gate line is asserted and suspended while the Gate line is de asserted Tas in Mode G the counter counts to TC using the Load register value reloads from the hold register and counts to a second TC Once the counter reaches the second TC the counter disarms itself and awaits another ARM command This mode allows extension of either the initial delay or the delayed pulse width by use of the Gate SPECIFICATIONS SUBJECT TO CHANGE WITHOUT NOTICE Copyright 2000 Celeritous Technical Services Corp Rev E Tuesday September 25 800 687 6510 806 793 0708 FAX 806 793 0710 http www celeritous com Celeritous Technical Services Corp
68. d can interrupt the processor when one of the four interrupt sources is enabled through the jumper settings on P3 and P4 By using this interrupt you can write software that effectively deals with real world events Interrupt Request Lines To allow different peripheral devices to generate interrupts on the same computer the PC bus has eight different interrupt request IRQ lines A transition from low to high on one of these lines generates an interrupt request which is handled by the PC s interrupt controller The interrupt controller checks to see if interrupts are to be acknowledged from that IRQ and if another interrupt is already in progress it decides if the new request should supersede the one in progress or if it has to wait until the one in progress is done This prioritizing allows an interrupt to be interrupted if the second request has a higher priority The priority level is based on the number of the IRQ IRQO has the highest priority IRQ1 is second highest and so on through IRQ7 which has the lowest Many of the IRQs are used by the standard system resources IRQO is used by the system timer IRQ1 is used by the keyboard IRQ3 by COM2 IRQ4 by COMI and IRQ6 by the disk drives Therefore it is important for you to know which IRQ lines are available in your system for use by the DM5804 board 8259 Programmable Interrupt Controller The chip responsible for handling interrupt requests in the PC is the 8259 Programmable Interru
69. d to retrieve the most significant byte MSB C 96 amp a b c a b c a b amp c a b c oe MOD DIV AND OR sca a bMODc a bDIVc a bANDc a bORc MOD AND OR BASIK a bMODc a bANDc a bORc Many compilers have functions that can read write either 8 or 16 bits from to an I O port For example Turbo Pascal uses Port for 8 bit port operations and PortW for 16 bits Turbo C uses inportb for an 8 bit read of a port and inport for a 16 bit read Be sure to use only 8 bit operations with the DM5804 4 7 Clearing and Setting Bits in a Port When you clear or set one or more bits in a port you must be careful that you do not change the status of the other bits You can preserve the status of all bits you do not wish to change by proper use of the AND and OR binary operators Using AND and OR single or multiple bits can be easily cleared in one operation To clear a single bit in a port AND the current value of the port with the value b where b 255 2 Example Clear bit 5 in a port Read in the current value of the port AND it with 223 223 255 25 and then write the resulting value to the port In BASIC this is programmed as V INP PortAddress V V AND 223 OUT PortAddress V To set a single bit in a port OR the current value of the port with the value b where b 2 Example Set bit 3 in a port Read in the current value of the port OR it with 8 8 2 and then write the resulting value to the port In Pa
70. e counting SPECIFICATIONS SUBJECT TO CHANGE WITHOUT NOTICE Copyright 2000 Celeritous Technical Services Corp RevE Tuesday September 25 Celeritous Technical Services Corp 800 687 6510 806 793 0708 CTS9 51 3 2 3308 34th St FAX 806 793 0710 Lubbock Texas 79410 http www celeritous com 5 Chan 16 bit 20MHz Counter Timer SOURCE WR DATA y ARM COMMAND Y GATE A COUNT VALUE L 1 y L 2 K ate N 1 X N Y L y L 1 y us X 1 X L Y L 1 X L 2 X TC OUTPUT TOGGLE OUTPUT y COUNTER MODE Q WAVEFORMS Figure 24 CTS9513 Counter Mode Q Representative Waveforms SOURCE WR DATA y ARM COMMAND care EIEIO AAA AQ QA AN COUNT VALUE L 1 Y L 2 y rk Y N 2 ji N 1 y N y L K L 1 Y en 1 1 y 4 Y L 1 if L 2 TC OUTPUT TOGGLE OUTPUT Y COUNTER MODE R WAVEFORMS Figure 25 CTS9513 Counter Mode R Representative Waveforms MODE Q RATE GENERATOR WITH MODE R RETRIGGERABLE ONE SHOT SYNCHRONIZATION Mode R as shown in Figure 25 begins counting only after receipt of an ARM command and a valid active Gate edge The counter will count once to TC and stop The counter will remain inactive until receipt of a subsequent valid Gate edge Mode Q provides a continuous rate generator which may be externally gated or synchronized to an external event via the Gate input As shown in Figure 24 once an ARM command is received the counter will continuously count to TC reload the Load
71. e gate polarities edges Time of Day Alarm Functions Programmable Internal External Counter Source Fully AM9513 Hardware Software Compatible Dual count registers on each counter CTS9513 2 5 Chan 16 bit 20MHz Counter Timer Figure 1 CTS9513 DIP 40 Package CTS9513 OVERVIEW For two decades the most flexible counter timer peripheral device available was the Advanced Micro Devices AM9513 Counter Timer Until discontinued in 1995 the AM9513 was a leading device in industrial and scientific timing controllers lts only limitation was its 7 Mhz maximum clock speed until NOW Building on over two decades of successful use as the most flexible programmable counter timer device the CTS9513 breaks the old limitations of the AM9513 in a new technology device with over 3 times the speed of the venerable 9513 with 16 bit counters Sporting up to a 20 MHz maximum Input clock the CTS9513 allows timing resolutions of 50 ns and gate pulses as short as 50nS This opens up a whole new range of capabilities and applications for this device The CTS9513 is an ideal solution for direct replacement or new designs With its CMOS construction it consumes far less power and runs much cooler than the original NMOS device Due to its ASIC construction it can not be obsoleted The CTS9513 is Hardware and Software compatible with the AM9513 allowing use of your present software drivers Standard Packaging for the CTS9513 is the DIP 40
72. e signal pin on the I O connector and the low side is connected to any DIGITAL GND Running the 5804DIAG Diagnostics Program Now that your board is ready to use you will want to try it out An easy to use menu driven diagnostics program 5804DIAG is included with your example software to help you verify your board s operation You can also use this program to make sure that your current base address setting does not contend with another device 2 4 CHAPTER 3 HARDWARE DESCRIPTION Thischapterdescribesthefeatures ofthe DM5804 hardware Themajorcircuitsarethetimer counters and the digital I O lines Thischapteralsodescribes the hardware selectable interrupts 31 3 2 The DM5804 has two major circuits thetimer counters and the digital I O lines Figure3 1 shows the block diagram ofthe board This chapter describes the hardware which makes up the major circuits and hardware selectableinterrupts DIGITAL I O PULL UP DOWN RESISTORS LJ LJ PC BUS FOUT SOURCE c o m O Lu z 2 Q O 9 AM9513A GATE CONTROL 45 VOLTS DIGITAL GROUND Fig 3 1 0 DM804 Block Diagram Am9513A Timer Counters TheAm9513A System Timing Controller contains five general purpose 16 bittimer counterswhichare capable of performing many differenttypes of counting sequencing and timing functions The Am95 13A supports up or downcountinginbinaryor BCD with hardware or software gating of each counter Its 24modes of operation are d
73. een transferred into the counter In all operating modes the value in either the load or hold register is transferred into the counter when the counter reaches terminal count Hold Register The hold register is a read write dual purpose register In some operating modes the hold register may be used to store counter instantaneous values on command without disturbing the counter action for readout by the host Other operating modes allow the hold register to be used as storage for counter values in a fashion similar to the Load register The counter may be loaded from the Hold register at terminal count or alternately loaded from the Load and Hold register at terminal count Alarm Register Counters 1 and 2 contain an additional 16 bit Alarm register and corresponding 16 bit comparator When the value in the counter matches the value stored in the Alarm register the output pin for the counter goes true The output remains true as long as the counter value matches the Alarm register value The output may be programmed for active high or active low by the counter mode register COUNTER MODE REGISTER Each counter group contains a mode control register which controls the counter behavior gating and output active states and polarities and counter source The counter mode register is initialized at power up to all zeroes This translates to an initial counter mode of Output Low impedance to Ground Count Down Count Binary Count Once
74. eese essen sento setae ta stato setas ta stesso neos senses eene 3 1 Am9513A Timer COUnters seers neii are AN 3 3 Digital VO Programmable Peripheral Interface eese eene nenne enne 3 3 Int rr pts AI 3 4 CHAPTER 4 BOARD OPERATION AND PROGRAMMING rsunsonssnssonsnnsnnssnssnnsnnsnnsnnsnnnnnn 4 1 Defining the VO Map traten Ee en eire bei er t pte ee eter 4 3 BA 0 PPI Port A Digital I O Read Write esses eene enne nne nennen ner en nennen enne tene enne 4 3 BA 1 PPI Port B Digital VO Read Write ooooonccnnnnonconnconconnonnnonncnnnonoranncnncnn non corn non nc ener nennen ener 4 3 BA 2 PPI Port C Digital VO Read Write esses eene tenen nennen enne nenen enne tenen 4 3 BA 3 8254 PPI Control Word Write Only nona vennevenneenseeennerenveeneeeeneernnvennerenneenseeennerenveeenne 4 4 BA 4 Am9513A Data Register Read Write noen onse ener eee eene nennen enter en nnne nennen 4 5 BA 5 Am9513A Command Register Read Write eese eene enne enne entere nennen 4 5 BA 6 IRO Enable Write Only iiie ettet tete t epe ere he Ee WP eee FECE E HERE PAX a nissen 4 6 BA 7 Interrupt Status Clear Read Write seriis iiinis sses e er esi kapi Toata R EETAS Ee S Ea 4 6 Programming the DMS 804 ici io ias Pee 4 7 Clearing and Setting Bits in Port iier eerte ER ER DI Heel ua 4 8 Initializing th amp m95134A one eene a leenen AT
75. es 11 12 summarize the counter modes and the associated settings of the counter mode bits CM5 7 and CM13 15 Figures 10 through 28 illustrate the counter modes All representative waveforms assume counting down on rising source edges A TC mode and Toggled output waveform are shown in each waveform For waveforms which disarm automatically on TC the software ARM command is shown in conjunction with C7 C6 C5 C4 C3 C2 C1 CO Command Register Bit C7 C6 C5 C4 C3 C2 C1 CO Command Register Bit 1 1 1 fo fo o Jo Io Clear MM14 Enable Data Pointer Sequencing 55 54 53 52 51 S1 5 Counter Group Select Ec Pup ed er EEE 1 1 1 JO 0 1 1 1 Clear MM13 Enable 8 bit Bus Mode 1 1 1 0 1 JO JO 0 SetMM14 Disable Data Pointer Sequencing 0 JO 1 55 S4 S3 S2 S1 Arm Selected Counters 1H fo Ti 1 1 lo setMMI2 FOUT Gate OM 9 f1 jo 155154 53 52 51 Load Selected Counters i i fo hh Setmm13 Enable 16 bit Bus Mode 0 1 1 55 S4 S3 S2 S1 Load and Arm Selected Counters 1h h lo jo fo o Originally Reserved 1 0 0 S5 S4 S3 S2 S1 Disarm and Save Selected Counters 1 1 1 1 jo 1 1 JO Originally Reserved 1 J0 1 55 S4 S3 S2 S1 Save selected counters to Hold Registers 1 1 1 1 JO 1 1 l Orig Reserved 1 1 fo S5 S4 S3 S2 S1 Disarm Selected Counters 1 1 1 1 1 fo JO O Enable W
76. etailed in the Am95 13A Data Sheet reprint from AMD included in Appendix C TheAm9513Aisstructured with a series ofinternal registers that set the mode of operation for each counter Theseregisters arefully described in Appendix C Anyofthe counters canbe internally cascaded to create a counter ofup to 80 bits For example two cascaded counters form a32 bit counter for longer counting capability Rarelyis it practical to cascade more than three counters Cascading is described in Appendix C Chapter3 of the Am9513A data sheet Thetimer counters are driven by an on board 5 MH zcrystal oscillator Digital I O Programmable Peripheral Interface The programmable peripheral interface PPD is used for digital I O functions Thishigh performanceTTL CMOS compatible chip has 24 digital I O lines divided into two groups of 12 lines each Group A Port A 8 lines and Port C Upper 4 lines Group B Port B 8 lines and Port C Lower 4 lines 33 All three ports A B and C are available at the I O connector P2 You canuse these ports in one of these three PPI operating modes Mode 0 Basic input output Lets you use simple input and output operation for a port Datais written to or read fromthe specified port Mode 1 Strobed input output Lets you transfer I O data from Port A or Port B in conjunctionwith strobesor handshakingsignals Mode2 Strobed bidirectional input output Lets you communicate bidirectionallywith an externa
77. f the ARM DISARM LOAD SAVE CLEAR SET and STEP commands ARM Command A counter must be ARMed before it can commence counting Once ARMed a counter may be programmed to begin counting immediately or to await a hardware trigger to initiate counting SPECIFICATIONS SUBJECT TO CHANGE WITHOUT NOTICE Copyright 2000 Celeritous Technical Services Corp Rev E Tuesday September 25 800 687 6510 806 793 0708 FAX 806 793 0710 http www celeritous com Celeritous Technical Services Corp 3308 34th St Lubbock Texas 79410 CTS9513 2 5 Chan 16 bit 20MHz Counter Timer SOURCE 1 5 GATE 1 5 CLK IN i 24 BIT PRESCALH L e INT 1 COUNTER 1 BUFFEH INT 2 COUNTER 2 FOUT 16 BIT STATUS REGISTER 16 BIT MASTER MODE REGISTER 16 BIT COMMAND REGISTER BUS MUX BUS CONTROL UA o ggg g Ble OUT 2 INT 3 COUNTER 3 COUNTER 4 OUT 4 INT COUNTER 5 OUT 5 Figure 4 CTS9513 Counter Block Diagram DISARM Command The DISARM command halts and disables any further counting regardless of any hardware gating or triggering While DISARMed a counter may be reloaded SAVEd or incremented or decremented using the STEP Command LOAD Command The LOAD command is used to load the counter with the value stored in ei
78. f your control word will vary depending on how you want to configure your I O lines Use the control word description in the previous I O map section to help you program the right value In the example below a decimal value of 128 sets up the 8255 so that all I O lines are Mode 0 outputs 1 0 0 0 0 0 0 0 D7 D6 D5 D4 Da D2 D1 Do Digital I O Operatiois Once the 8255 is initialized you can use the digital I O line to control or monitor external devices 4 9 Interrupts What Is an Interrupt An interrupt is an event that causes the processor in your computer to temporarily halt its current process and execute another routine Upon completion of the new routine control is returned to the original routine at the point where its execution was interrupted Interrupts are very handy for dealing with asynchronous events events that occur at less than regular intervals Keyboard activity is a good example your computer cannot predict when you might press a key and it would be a waste of processor time for it to do nothing while waiting for a keystroke to occur Thus the interrupt scheme is used and the processor proceeds with other tasks Then when a keystroke does occur the keyboard interrupts the processor and the processor gets the keyboard data places it in memory and then returns to what it was doing before it was interrupted Other common devices that use interrupts are modems disk drives and mice Your DM5804 boar
79. he Hold register and the counter reloaded from the Load register If no gating is enabled and CM7 is cleared the gate input has no effect on counting If CM7 is set then the Gate input controls whether the counter is reloaded from the Load or Hold Register CTS9513 2 5 Chan 16 bit 20MHz Counter Timer Count Source Bits CM8 12 The count source determines which source is used as an input to the counter There are 20 possible count sources 16 of which may be selected with bits CM8 12 Additional Count sources may be specified with the extended registers Figure 8 illustrates the internal 24 bit prescaler whose outputs may be used as count sources Gating Control Bits CM13 15 Gating control determines whether the counter is hardware gated or not When gating is disabled the counter will continue as long as the counter is armed If any gating mode is enabled the counter action is determined by some hardware gate condition Gating of the counter may be controlled from the gate line associated with the counter or gate lines associated with adjacent counters Gating on the line associated with the counter may be programmed for edge or level sensitive active high or active low The counter may also be gated by the TC output of the previous counter The gating control logic is outlined in Figure 7 COUNTER MODES Counter modes continue as in the 9513 to retain their mode designations A X with modes M P T U and V reserved Tabl
80. igital VO DIGITAL Simple program that shows how to read and write the digital I O lines 4 14 CHAPTER 5 EXAMPLES OF Am9513A APPLICATIONS This chapter steps through some example programs to help you understand how the Am9513A registers are programmed The data pointer register and command registers are summarized in tables The master mode and counter mode register bit assignments are also included as well as the frequency scaler ratios 5 1 5 2 This chapter provides a more detailed look at some example programs using the Am9513A for counting and timing functions If you are unfamiliar with the Am9513A and how it is programmed walking through these examples and the other example programs included on your DM5804 disk may be the best way to understand the many registers and their operation so that you can successfully develop your own programs for your specific applications IMPORTANT Because of the bus release time of the Am9513A AMD recommends you insert a small delay between software accesses to the chip EXAMPLE Counting Program Using Timer Counters 1 2 and 3 This BASIC program COUNT on the example disk shows you how to program the Am9513A s timer counters 1 2 and 3 to perform a simple counting function In this example counter 1 is used to divide the on board 5 MHz clock by 10 000 The output from counter 1 5 MHz 10 000 500 Hz is used to clock counter 2 Counter 2 is used to divide this 500 Hz clock by 500
81. in Max Conditions taw Address Stable Before WR 0 ns twa Address Hold Time After WR T 20 ns Ports A amp B 20 ns Port C tww WR Pulse Width 100 ns tpw Data Setup Time Before WR T 100 ns two Data Hold Time After WR T 30 ns Ports A 8 B 30 ns Port C 19 82C55A OTHER TIMINGS Symbol Parameter PROSA C pale Test Min Max onditions twp WR 1 to Output 350 ns UR Peripheral Data Before RD 0 ns tun Peripheral Data After RD 0 ns tAK ACK Pulse Width 200 ns ter STB Pulse Width 100 ns tps Per Data Before STB High 20 ns tp Per Data After STB High 50 ns tAD ACK 0 to Output 175 ns tkp ACK 1 to Output Float 20 250 ns twos WR 1 to OBF 0 150 ns tAOB ACK Oto OBF 1 150 ns teip STB 0 to IBF 1 150 ns tRIB RD 1toIBF 0 150 ns tRIT RD Oto INTR 0 200 ns ts r STB 1toINTR 1 150 ns ta t ACK 1to INTR 1 150 ns twiT WR Oto INTR 0 200 ns see note 1 tres Reset Pulse Width 500 ns see note 2 NOTE 1 INTR may occur as early as WR 2 Pulse width of initial Reset pulse after power on must be at least 50 uSec Subsequent Reset pu minimum The output Ports A B or C may glitch low during the reset pulse but all port pins will be held at a logic one level after the reset pulse 20 ses may be 500 ns intel gt 82C55A WAVEFORMS MODE 0 BASIC INPUT INPUT C A1 A0 D D
82. ions of modes possible For any combination some or all of the Port C lines are used for control or status The remaining bits are either inputs or outputs as defined by a Set Mode command During a read of Port C the state of all the Port C lines except the ACK and STB lines will be placed on the data bus In place of the ACK and STB line states flag status will appear on the data bus in the PC2 PC4 and PC6 bit positions as illustrated by Figure 18 Through a Write Port C command only the Port C pins programmed as outputs in a Mode 0 group can be written No other pins can be affected by a Write Port C command nor can the interrupt enable flags be accessed To write to any Port C output pro grammed as an output in a Mode 1 group or to 16 change an interrupt enable flag the Set Reset Port C Bit command must be used With a Set Reset Port C Bit command any Port C line programmed as an output including INTR IBF and OBF can be written or an interrupt enable flag can be either set or reset Port C lines programmed as inputs including ACK and STB lines associated with Port C are not affected by a Set Reset Port C Bit command Writing to the corresponding Port C bit positions of the ACK and STB lines with the Set Reset Port C Bit command will affect the Group A and Group B interrupt enable flags as illus trated in Figure 18 Current Drive Capability Any output on Port A B or C can sink or sou
83. ister depending on the state of the gate MODE J ERROR The counters will not allow a count of 1 to be set in the load and or hold registers COUNTER SAVE ERRORS Due to the asynchronous nature of this part and to an extent the original AMD AM9513 we have seen errors in the saved counter data when a counter save command is issued This occurs when the write strobe rising edge for a save command occurs simul taneously with a counter clock edge and the counter tries to save the current count while also trying to in crement or decrement the counter The only solid solution we have found for this proble is for the bus clock to also be the master clock or to be phased locked to it in order for the timing of bus read write cycles to be deterministic with respect to the counter clock edges COUNTER MODE REGISTER TC 1 onl GATE INPUT MUX GATE 1 gt ae AND POLARITY EDGE AND CANETA SELECT LEVEL GATE QQ CONTROL J COUNTER GATE EN Figure 9 CTS9513 Counter Gating Input Logic Block Diagram SPECIFICATIONS SUBJECT TO CHANGE WITHOUT NOTICE Copyright 2000 Celeritous Technical Services Corp 12 RevE Tuesday September 25 Celeritous Technical Services Corp 800 687 6510 806 793 0708 3308 34th St FAX 806 793 0710 CTS9513 2 Lubbock Texas 79410 http www celeritous com 5 Chan 16 bit 20MHz Counter Timer
84. itializing the Am9513A The Am9513A has a sophisticated internal architecture which is programmed through a series of internal registers These internal registers are accessed by writing to and reading from only two I O port locations the Data Register port at BA 4 and the Control Register port at BA 5 In our example programs we follow these steps to initialize the Am9513A 1 Send a master reset to the Am9513A 2 Point to and set up the master mode register 3 Point to and set up counter 1 mode register 4 Point to counter 1 load register and load desired value 5 Point to and set up counter 2 mode register 6 Point to counter 2 load register and load desired value 11 Point to and set up counter 5 mode register 12 Point to counter 5 load register and load desired value 13 Load and arm counters The examples on the disk and in Chapter 5 will aid you in programming the Am9513A for your application These tools and the data sheet in Appendix C provide a comprehensive description of timer counter operation IMPORTANT Because of the bus release time of the Am9513A AMD recommends you insert a small delay between software accesses to the chip Initializing the 8255 Before you can use the digital I O lines on your DM5804 the 8255 PPI must be initialized This step must be executed every time you start up reset or reboot your computer The 8255 is initialized by writing the appropriate control word to I O port BA 3 The contents o
85. l device through Port A Handshakingis similar to Model These modes are detailed inthe 8255 Data Sheet reprinted from Intel in Appendix C Interrupts The DM5804 hasfour jumper selectableinterrupt sources PC3 whichis the INTRA signal from the 8255 PPI PCO which is the INTRB signal from the 8255 PPI OUTS the output from Am9513A timer counter 5 and EXTINT anexternal interruptyou canroute onto the board through I O connector P2 Chapter 1 tells you howto set thejumpers on the interrupt header connectors P3 and P4 and Chapter 4 describes howto program interrupts CHAPTER 4 BOARD OPERATION AND PROGRAMMING This chapter shows you how to program your DM5804 It provides a complete description of the I O map and a description of programming operations to aid you in programming The example programs included on the disk in your board package are listed at the end of this chapter These programs written in Turbo C Turbo Pascal and BASIC include source code to simplify your applications programming Chapter 5 contains examples for setting up the timer counters for specific applications 4 1 4 2 Defining the I O Map The I O map for the DM5804 is shown in Table 4 1 below As shown the board occupies eight consecutive I O port locations The base address designated as BA can be selected using DIP switch S1 as described in Chapter 1 Board Settings This switch can be accessed without removing the board from the connector The foll
86. l have an on or off time equal to the load count and off on time equal to the hold count As shown in Figure 19 SPECIFICATIONS SUBJECT TO CHANGE WITHOUT NOTICE Copyright 2000 Celeritous Technical Services Corp RevE Tuesday September 25 800 687 6510 806 793 0708 FAX 806 793 0710 http www celeritous com Celeritous Technical Services Corp 3308 34th St Lubbock Texas 79410 CTS9513 2 5 Chan 16 bit 20MHz Counter Timer SOURCE WR DATA y ARM COMMAND Y care BA COUNT VALUE L 1 y L 2 y 55 y 1 y H ji H 1 Y y 1 y k y L 1 L 2 Y TOGGLE OUTPUT y y Figure 20 CTS9513 Counter Mode K Representative Waveforms DATA y ARM COMMAND y AN ARRA ARO COUNT VALUE L 1 x L 2 Y TS y 1 Y H Y H 1 x een Y 1 X L y L 1 X L 2 Y L 3 y TOGGLE OUTPUT y y COUNTER MODE L WAVEFORMS Figure 21 CTS9513 Counter Mode L Representative Waveforms MoDE K VARIABLE DUTY CYCLE RATE GENERATOR WITH LEVEL GATING Mode K is similar to Mode J with the exception that the counter is enabled only after being ARMed and when the selected Gate line is asserted When the Gate line is deasserted the counter stops This allows the gate to modulate the duty cycle of either state as illustrated in Figure 20 MODE L HARDWARE TRIGGERED DELAYED PULSE ONE SHOT Mode L is used often as an externally triggered delayed pulse generator where the delay and pulse width are both programmable Like Modes
87. llustrates the Time of day storage configuration In short Counter 2 bits 8 15 form a two digit BCD Hours counter Bits 0 7 form a two digit BCD Minutes counter Counter 1 bits Bits 8 15 form a two digit BCD seconds counter Bits 4 7 form a tenth second counter and Bits 0 3 form a division factor for the input source for divide by 5 6 or 10 Comparator Enable Bits MM2 3 The two 16 bit comparators on counters 1 and 2 may be used in any mode When enabled the output of the comparators are routed to the output of the counter The output will be asserted when the comparison between the counter and alarm register contents are true It will remain asserted as long as the counter and alarm register remain the same In the Time of Day mode the comparators operate in conjunction such that the output of the counter 2 comparator is asserted only when both comparators 1 and 2 are true the comparator 1 output will continue to operate normally FOUT Source Bits MM4 7 Fifteen different sources may be routed to the input of the FOUT divider including the five SOURCE inputs five GATE inputs and five of the internal divided frequencies derived from the X1 input Additional Sources may be programmed using the extended Master mode register functions FOUT1 Divider Bits MM8 11 FOUT may be divided by 1 to 16 Master mode bits MM8 11 allow programming of the FOUT divider from 1 to 16 inclusive Higher order division factors are programmed through
88. lock 5 MHz Clock sw oso smi F1 10 500 kHz F1 16 312 5 kHz F1 100 50 kHz F1 256 19 53 kHz F1 1000 F1 4096 1 221 khz 3x d F1 10 000 500 Hz F1 65 536 76 3 Hz Fig 5 3 Frequency Scaler Ratio Put the hex number 0000 in counter 3 load register OUT CR HB POINT TO COUNTER 3 LOAD REGISTER TABLE 5 1 OUT DR amp HO COUNTER 3 LSB OUT DR amp HO COUNTER 3 MSB OUT CR amp H67 LOAD amp ARM COUNTERS 1 2 amp 3 TABLE 5 2 The main program is OUT CR HA4 SAVE COUNTER 3 IN HOLD REGISTER TABLE 5 2 OUT CR amp H13 POINT TO COUNTER 3 HOLD REGISTER TABLE 5 1 LSB INP DR READ COUNTER 3 LSB MSB INP DR READ COUNTER 3 MSB RESULT LSB MSB 256 COMBINE LSB amp MSB OCATE 12 37 PRINT USING RESULT ON KEY 1 GOSUB QUIT GOTO MAIN To quit KEY 1 OFF END 5 8 Fi F2 F3 F4 F5 EXAMPLE Setting Up the Am9513A as a Frequency Counter This program FCOUNT on the example disk shows you how to program the Am9513A as a simple frequency counter In this example counter 4 is used to divide the on board 5 MHz clock by 10 000 The output from counter 4 5 MHz 10 000 500 Hz is used to clock counter 5 Counter 5 is used to divide this 500 Hz clock by 500 The result is a 1 Hz output which is used to gate counter 1 This 1 Hz output is also used to trigger the interrupt status bit The program monitors this status bit to determine when to read counters 1 and 2
89. mming and the DM5804 board Chapter 5 provides some specific programming examples and the Am9513A data sheet in Appendix C provides detailed programming information for all 24 operating modes of the Am9513A These tools will help you as you use the example programs included with the board All of the program descriptions in this section use decimal values unless otherwise specified The DM5804 is programmed by writing to and reading from the correct I O port locations on the board These I O ports were defined in the previous section Most high level languages such as BASIC Pascal C and C and of course assembly language make it very easy to read write these ports The table below shows you how to read from and write to 1 O ports using some popular programming languages tanguage Rea wie BASIC Data INP Address OUT Address Data Data inportb Address outportb Address Data Turbo Pascal Data Port Address Port Address Data mov dx Address mov dx Address Assembly in al dx re out dx a In addition to being able to read write the 1 O ports on the DM5804 you must be able to perform a variety of operations that you might not normally use in your programming The table below shows you some of the operators discussed in this section with an example of how each is used with Pascal C and BASIC Note that the modulus operator is used to retrieve the least significant byte LSB of a two byte word and the integer division operator is use
90. nd address your name your telephone number and a brief description of the problem You can also contact us through our E mail address techsupportOrtd com CHAPTER 1 BOARD SETTINGS The DM5804 has jumper and switch settings you can change if necessary for your application The board is factory configured with the most often used settings The factory settings are listed and shown on a diagram in the beginning of this chapter Should you need to change these settings use these easy to follow instruc tions before you install the board in your system Note that by installing resistor packs at four locations around the 8255 PPI and soldering jumpers in the desired locations on the associated pads you can configure your 8255 digital VO lines to be pulled up or pulled down This procedure is explained at the end of this chapter Factory Configured Switch and Jumper Settings Table 1 1 lists the factory settings of the user configurable jumper and switches on the DM5804 Figure 1 1 shows the board layout and the locations of the factory set jumpers The following paragraphs explain how to change the factory settings Pay special attention to the setting of S1 the base address switch to avoid address contention when you first use your board in your system Table 1 1 Factory Settings Switch Factory Settings Jumper Function Controlled Jumpers Installed Connects one of the four sources selected on P4 to an interrupt channel pulls tri st
91. ne eges e ep eate EE bren iii i 3 Board Accessories tee REOR UR RETIRER PESE RR ERE nn EXE ARS ER nee i 3 Using This Manual 5e zee 2 II alitas Ie tem ei uA m nn ARR IT i 3 When You Need Helpman e Her rer Ear gto adds e e t PERRO E ee eco asoci i 4 CHAPTER 1 BOARD SETTINGS ene oonooncensesreoreoncenseer ven veovenneoneenenovennenneonensrensenneenseereenense 1 1 Factory Configured Switch and Jumper Settings nennen en vennvenvennvenvennveneenneenverseeneeenveenven snee veenvenneen 1 3 P3 Interrupt Channel Select Factory Setting G Connected Interrupt Channels Disabled 1 4 P4 Interrupt Source Select Factory Setting EXTINT aanneem eee nre nre nennen 1 4 S1 Base Address Factory Setting 300 hex 768 decimal oneven ennen econo ee onvennevenneeenenen 1 5 Pull up Pull down Resistors on Digital I O Lines esee nennen nennen nennen trennen nenne 1 6 CHAPTER 2 BOARD INSTALLATION cesse essere enata sento tns tosta sts sone soosis stissa 2 1 Board Installation u mare Rammstein nenn deelen en e ea eee e IR a nn RR V MR RET ERN 2 3 External VO Connect Ons seen A E E iba 2 3 Connecting the Timer Counters and Digital VO essere eee nennen enne 2 4 Running the 5804DIAG Diagnostics Program annen envennvene eene eneeenverneenveenvenveenvenveenvenneenvennennveenveenvenneen 2 4 CHAPTER 3 HARDWARE DESCRIPTION esee ee
92. o ead eem i ne eias 4 9 Initializing the A AAA eU ede n E e ea p rr eR ee RR RH 4 9 Digital V O Opera onsa 5r tei Be Ri Ras E ERE AREE 4 0 Hp IM S 4 10 What Isan Interrupt 5 eet t eroe ente RR eo ie ATi am esr ten euet ete dend 4 10 Interrupt Request Lanes unte eeu tr a t ee en RED Gb rie dere 4 10 8259 Programmable Interrupt Controller essere nennen nennen nennen trennen 4 10 Interrupt Mask Register IMR re eo e eic i e PEE EE RHET EEE ERR sin 4 10 End of Interrupt EOD Command esses esent nnne E E a treten enne nennen enne 4 10 What Exactly Happens When an Interrupt Occurs enne envenseenv nennen nennen nennen 4 11 Using Interrupts in Your Programs 5 eee reete d D e HER HERR e RE ERE pute Porti be bep ee iin 4 11 Writing an Interrupt Service Routine ISR annen eneen ens ennennvennernerenvenevenvenveenenennvenneen 4 11 Saving the Startup Interrupt Mask Register IMR and Interrupt Vector nennen 4 12 Restoring the Startup IMR and Interrupt Vector ennen onvenvennvenvennveneeenveneeeneesneenveennvenneen 4 13 Common Interrupt Mistakes nit teet o e sn I eR T hinein 4 13 Example Programs a e derde IE 4 14 Cand Pascal Programs t et ett EO e tei teste bee Pen e e eh Blei BEE 4 14 BASIC Programs assi RIA APR IRA RERO AH IER ee hdi 4 14 CHAPTER 5 EXAMPLES OF Am9513A APPLICATIONS 20r20s00n0
93. oard in its antistatic bag until you are ready to install it in your cpuModule or other PC 104 based system When removing it from the bag hold the board at the edges and do not touch the components or connectors Before installing the board in your system check the jumper and switch settings Chapter 1 reviews the factory settings and how to change them If you need to change any settings refer to the appropriate instructions in Chapter 1 Note that incompatible jumper settings can result in unpredictable board operation and erratic response The DM5804 comes with a stackthrough P1 connector The stackthrough connector lets you stack another board on top of your DM5804 plugging it into the data bus through the pins on the non component side of the board To install the board follow the procedures described in the computer manual and the steps below 1 Turn OFF the power to your system 2 Touch the metal rack to discharge any static buildup and then remove the board from its antistatic bag 3 Select the appropriate standoffs for your application to secure the board when you install it in your system two sizes are included with the board 4 Holding the board by its edges orient it so that the P1 bus connector s pin 1 lines up with pin 1 of the expansion connector onto which you are installing the board 5 After carefully positioning the board so that the DM5804 s bus connector is resting on the expansion connector gently and e
94. of the write strobe Data in this device is latched into the command and control registers on the low level of the write strobe This means that the data must be stable up until shortly before the rising edge of the write strobe This appears to be an artifact of the way the 8 bit sequential write mode was implemented in order to correctly increment the byte pointer and latch the data on the one write strobe To date we have only seen this create a problem in one instance on an ISA bus Counter Timer instrumentation card where the ISA bus decoding was incorrectly implemented In that instance a delay in de asserting the chip select was causing the leading edge of a write strobe for another l O device to appear prior to the trailing edge of the Chip Select signal This was interpreted as another valid write to the 9513 device causing invalid data to be written to the device MM7 MM6 MM5 MM4 MM3 MM2 MM1 MMO FOUT Source Select Comparator Time of Day Mode Mode 00 Disabled 00 TOD Disabled 01 Comparator 1 On 01 TOD Enabled 5 10 Comparator 2 On 10 TOD Enabled 6 11 Both On 11 TOD Enabled 10 0000 F1 001 Source 1 0010 Source 2 0011 Source 3 0100 Source 4 0101 Source 5 0110 Gate 1 0111 Gate 2 1000 Gate 3 1001 Gate 4 1010 Gate 5 1011 F1 1100 F2 1101 F3 1110 F4 1111 F5 Table 8 Master and Auxiliary Master Mode Register Definitions SPECIFICATIONS SUBJECT
95. ointer sequencing The primary Master Mode Register is identical in function to the original 9513 device The auxiliary Master Mode Register is used to program extended features of the CTS9513 Ifthe auxiliary register is not programmed the device behaves as an original 9513 device Table 8 summarizes the primary and auxiliary Master Mode Register bit assignments On Power up the Master Mode register is cleared to all zeros resulting in the following default conditions 1 Time of Day disabled Alarm Comparators Disabled FOUT source is F1 FOUT divider set for divide by 16 FOUT enabled Data Bus 8 bits Data Pointer Sequencing enabled Frequency scaling Binary ONOoOBR WP Time of Day Bits MMO 1 Bits MMO and MM1 control the Time of day functions for counters 1 and 2 When enabled additional counter logic is enabled to allow the two counters to operate as a 24 hour clock Counters 1 and two must be programmed for BCD counting To initialize the time appropriate values are loaded in the Counter Load registers To read the time a SAVE command is issued to Counters 1 and 2 and the values read from the Hold registers CTS9513 2 SOURCE FREQ INPUT MUX ERE ao GATE 16 BIT HOLD REGISTER La ann CONTROL SNTE Y COUNTER OUTPUT OUT CONTROL IG BEE COUNTER CNTL ry MODE CONTROL 16 BIT LOAD REGISTER TERM COUNT Figure 6 CTS9513 Counter Groups 3 5 Table 9 i
96. or Mode 2 Figure 18 Interrupt Enable Flags in Modes 1 and 2 17 82C55A ABSOLUTE MAXIMUM RATINGS Ambient Temperature Under Bias 0 Cto 70 C Storage Temperature 65 C to 150 C Supply Voltage 0 5to 8 0V Operating Voltage 4Vto 7V Voltage on any Input GND 2V to 6 5V Voltage on any Output GND 0 5V to Vcc 0 5V Power Dissipation oooooooo o 1 Watt D C CHARACTERISTICS intel NOTICE This is a production data sheet The specifi cations are subject to change without notice WARNING Stressing the device beyond the Absolute Maximum Ratings may cause permanent damage These are stress ratings only Operation beyond the Operating Conditions is not recommended and ex tended exposure beyond the Operating Conditions may affect device reliability TA 0 C to 70 C Voc 5V 10 GND OV TA 40 C to 85 C for Extended Temperture Symbol Parameter Min Max Units Test Conditions ViL Input Low Voltage 0 5 0 8 V ViH Input High Voltage 2 0 Vcc V VoL Output Low Voltage 0 4 V loL 2 5 mA VoH Output High Voltage 3 0 V lou 2 5 mA Voc 0 4 V lou 100 pA lit Input Leakage Current 1 pA Vin Vcc to OV Note 1 lOFL Output Float Leakage Current 10 pA Vin Vcc to OV Note 2 IDAR Darlington Drive Current 2 5 Note 4 mA Port
97. orms Counter Outputs Each of the counters has a single dedicated output pin which is programmable for polarity tri state low Z to ground and a variety of output modes as described later This flexibility allows operation in a variety of bus and processor architectures Source Inputs Each counter group may be programmed for a variety of count sources including any of the five source input lines any of the internal prescaler outputs or SPECIFICATIONS SUBJECT TO CHANGE WITHOUT NOTICE Copyright 2000 Celeritous Technical Services Corp Rev E Tuesday September 25 800 687 6510 806 793 0708 FAX 806 793 0710 http www celeritous com Celeritous Technical Services Corp 3308 34th St Lubbock Texas 79410 the output of the previous counter allowing counter concatenation and FOUT divided outputs Gate Inputs Gate inputs are used for external hardware triggering or synchronization of the counters Each counter may be programmed to be gated from its own gate line or the gate lines from the previous or next counter The gate lines may also be programmed to be level or edge sensitive and respond to active high or low signals The gate line may be used to either initiate one or more count sequences or used as a count enable line allowing the counter to count only while the gate line is held active Another mode allows the counter to be reloaded from the load or hold register depending on the state of the gate line PROGRAMMIN
98. ounting Event Sequencing Programmable pulse generation Programmable delay generation Frequency counting Frequency synthesis Real Time Clock Alarm Clock Functions Watchdog Timing Retriggerable Pulse Generation Non Retriggerable Pulse Generation Waveform Analysis Interrupt Generation Pulse burst generation The user has control over key features such as Output Polarities Output Impedance Input Trigger Edge Polarities Hardware gating triggering Software gating triggering Count Up Down BCD Binary Counting Real time count register read Internal counter concatenation up to 80 bits Programmable frequency source selection Programmable internal clock pre scaling CTS9513 2 5 Chan 16 bit 20MHz Counter Timer FEATURES BACKWARDS COMPATIBLE The CTS9513 maintains backwards compatibility with most AM9513 features allowing continued use of your existing software drivers Data may be transferred in 8 or 16 bit increments All internal data paths in the CTS9513 are 16 bit All 9513 commands registers and modes are supported PACKAGING Figure 2 illustrates the DIP 40 Package pinout of the device which conforms to the original AM9513 pinouts Table 2 summarizes the pinouts of the PLCC 44 package illustrated in Figure 3 which conform to the original AM9513 PLCC pinouts SIGNALS The following signal names and description conform to the original AM9513 device VCC 5 Volt Power Supply vss Ground X1 The
99. owing sections describe the register contents of each address used in the I O map Table 4 1 DM5804 I O Map Address Register Description Read Function Decimal Program Port A digital output 8255 PPI Port A Read Port A digital input lines lines BA 0 Program Port B digital output 8255 PPI Port B Read Port B digital input lines lines BA 1 Program Port C digital output 8255 PPI Port C Read Port C digital input lines lines BA 2 8255 PPI Control Word Reserved Program PPI configuration Am9513A Data Word Read data register Program data register Am9513A Control Word Read control register Program control register Enable and disable interrupt IRQ Enable Reserved generation BA 6 Interrupt Status Clear Read status of interrupt Clear interrupt BA Base Address BA 0 PPI Port A Digital VO Read Write Transfers the 8 bit Port A digital input and digital output data between the board and an external device A read transfers data from the external device through P2 and into PPI Port A a write transfers the written data from Port A through P2 to an external device BA 1 PPI Port B Digital I O Read Write Transfers the 8 bit Port B digital input and digital output data between the board and an external device A read transfers data from the external device through P2 and into PPI Port B a write transfers the written data from Port B through P2 to an external device BA 2 PPI Port C Digital I O Read Write
100. pheral equipment to the microcomputer system bus The functional configu ration of the 82C55A is programmed by the system software so that normally no external logic is neces sary to interface peripheral devices or structures Data Bus Buffer This 3 state bidirectional 8 bit buffer is used to inter face the 82C55A to the system data bus Data is transmitted or received by the buffer upon execution of input or output instructions by the CPU Control words and status information are also transferred through the data bus buffer Read Write and Control Logic The function of this block is to manage all of the internal and external transfers of both Data and Control or Status words It accepts inputs from the CPU Address and Control busses and in turn issues commands to both of the Control Groups Group A and Group B Controls The functional configuration of each port is pro grammed by the systems software In essence the CPU outputs a control word to the 82C55A The control word contains information such as mode bit set bit reset etc that initializes the func tional configuration of the 82C55A 82C55A Each of the Control blocks Group A and Group B accepts commands from the Read Write Control Logic receives control words from the internal data bus and issues the proper commands to its as sociated ports Control Group A Port A and Port C upper C7 C4 Control Group B Port B and Port C
101. pt Controller To use interrupts you will need to know how to read and set the 8259 s interrupt mask register IMR and how to send the end of interrupt EOI command to the 8259 Interrupt Mask Register IMR Each bit in the interrupt mask register IMR contains the mask status of an IRQ line bit O is for IRQO bit 1 is for IRQ1 and so on If a bit is set equal to 1 then the corresponding IRQ is masked and it will not generate an interrupt If a bit is clear equal to 0 then the corresponding IRQ is unmasked and can generate interrupts The IMR is programmed through port 21H For all bits 0 IRQ unmasked enabled 1 IRQ masked disabled End of Interrupt EOI Command After an interrupt service routine is complete the 8259 interrupt controller must be notified This is done by writing the value 20H to I O port 20H 4 10 What Exactly Happens When an Interrupt Occurs Understanding the sequence of events when an interrupt is triggered is necessary to properly write software interrupt handlers When an interrupt request line is driven high by a peripheral device such as the DM5804 the interrupt controller checks to see if interrupts are enabled for that IRQ and then checks to see if other interrupts are active or requested and determines which interrupt has priority The interrupt controller then interrupts the proces sor The current code segment CS instruction pointer IP and flags are pushed on the stack for
102. r command registers to the data bus C D Control Data Port Select Input The C D line is used in conjunction with the CS RD and WR to select which internal command or data register is being written to or read from The C D line selects between the command and data register sets as summarized in Table 3 FUNCTIONAL DESCRIPTION SYSTEM LEVEL The CTS9513 is addressed by the external system through two address locations Counter and com mand data are written to individual counters through a sequence of indirectly addressing the internal com mand or data register through the command port address followed by a write to the data port address which points to the indirectly addressed register location Data is transferred through either two 8 bit transfers or a single 16 bit transfer Pointer sequencing for 8 bit transfers is automatic and is transferred as least significant byte first most significant byte second Rapid programming of the CTS9513 may be accomplished by use of the auto increment feature of the data pointer This feature is enabled by setting Master Mode Register bit 14 MM14 When enabled the data pointer may be sequenced through a single counter group all counter group registers all counter group Hold registers only or just the control group registers CTS9513 2 5 Chan 16 bit 20MHz Counter Timer INTERNAL CONFIGURATION Overview A simplified block diagram of the CTS9513 is shown in Figure 4 This diagram
103. rce 2 5 mA This feature allows the 82C55A to directly drive Darlington type drivers and high voltage displays that require such sink or source current intel Reading Port C Status In Mode 0 Port C transfers data to or from the pe ripheral device When the 82C55A is programmed to function in Modes 1 or 2 Port C generates or ac cepts hand shaking signals with the peripheral de vice Reading the contents of Port C allows the pro grammer to test or verify the status of each pe ripheral device and change the program flow ac cordingly There is no special instruction to read the status in formation from Port C A normal read operation of Port C is executed to perform this function 82C55A INPUT CONFIGURATION 1 0 1 0 IBFA INTEA INTRA INTEg IBF INTRg GROUP A GROUP B OUTPUT CONFIGURATIONS D De Ds D4 D3 Do Di Do OBFA INTEA 1 0 1 0 INTRA INTEg OBFg INTRB GROUP A GROUP B Figure 17a MODE 1 Status Word Format D Dg Ds Da D3 Do Dy Do OBFA INTE IBFA INTE INTRA GROUP A GROUP B Defined By Mode 0 or Mode 1 Selection Figure 17b MODE 2 Status Word Format Interrupt Enable Flag Position Alternate Port C Pin Signal Mode INTE B PC2 ACKg Output Mode 1 or STBg Input Mode 1 INTE A2 PC4 STBa Input Mode 1 or Mode 2 INTE A1 PC6 ACK Output Mode 1
104. renvenveenvenveenvenvereneennvenn 5 6 Counter Mode Register Bit Assignments ennen onver vennvenvennvenvennveneernvenveesvennvenveenveennvenveen 5 7 Frequency Scaler Ratio uet RAS HERE ite Buen 5 8 iii iv INTRODUCTION The DM5804 dataModule M timer counter and digital I O board turns your IBM PC compatible cpuModuleTM or other PC 104 computer into a high performance timing counting and control system Ultra compact for embed ded and portable applications the DM5804 features Five general purpose 16 bit timer counters in an Am9513A chip 24 timer counter modes of operation Binary or BCD up or down counting On board 5 MHz crystal 24 TTL CMOS 8255 based digital I O lines which can be configured with pull up or pull down resistors Operation from 5 volts only BASIC Turbo Pascal and Turbo C source code diagnostics program The following paragraphs briefly describe the major functions of the board A more detailed discussion of board functions is included in Chapter 3 Hardware Operation and Chapter 4 Board Operation and Programming The board setup is described in Chapter 1 Board Settings Am9513A Timer Counter The versatile Am9513A general purpose timer counter provides a variety of timing sequencing and counting functions The Am9513A chip contains five 16 bit timer counters which can be used individually or internally cascaded to form a counter of up to 80 bits With 24 operating modes up or down counting in
105. rite Pre Fetch 1 1 10 1 JO JO 1 Disable Write Pre Fetch N4 N2 N1 N1 4 Counter Group Select 001 N 1 1 1 H jO l 0 fOrigReserved 101 1 1 1j 1 O 1 1 Orig Reserved 1 1 1 1 1 1 0 0 Orig Reserved 1 1 1 JO 0 N4 N2 N1 Clear Selected Counter Toggle Out 1 1 1 1 1 1 JO 1 Orig Reserved 1 1 1 JO 1 N4 N2 N1 Set Selected Counter Toggle Out 1 1 1 1 1 1 1 0 Orig Reserved 1 1 1 1 fo N4 N2 N1 Step Selected Counter up down by CM3 1 1 1 Jl 1 1 l 1 Master Reset Table 5 Counter Action Related Commands Table 6 Device Level Commands SPECIFICATIONS SUBJECT TO CHANGE WITHOUT NOTICE Copyright 2000 Celeritous Technical Services Corp Rev E Tuesday September 25 800 687 6510 806 793 0708 FAX 806 793 0710 http www celeritous com Celeritous Technical Services Corp 3308 34th St Lubbock Texas 79410 CTS9513 2 5 Chan 16 bit 20MHz Counter Timer Comparator Reflects actual state of Interrupt Output Counter Output Status Byte Reflects Actual State of Output Table 7 Status Register a Write pulse Repetitive waveforms do not show the write pulse or ARM command The letters L and H are used in the figures to denote Load and Hold register values and the letters K and N to denote arbitrary counter values In all cases the counter begins counting on the first count source edge following the Write pulse in software triggered modes and the
106. rse there are ways around this problem such as those which involve checking to see if any DOS functions are currently active when your ISR is called but such solutions are well beyond the scope of this discussion The second major concern when writing your ISR is to make it as short as possible in terms of execution time Spending long periods of time in your ISR may mean that other important interrupts are being ignored Also if you spend too long in your ISR it may be called again before you have completed handling the first run This often leads to a hang that requires a reboot Y our ISR should have this structure Push any processor registers used in your ISR Most C and Pascal interrupt routines automatically do this for you Put the body of your routine here Clear the interrupt bit on the DM5804 by writing any value to BA 7 Issue the EOI command to the 8259 interrupt controller by writing 20H to port 20H Pop all registers pushed on entrance Most C and Pascal interrupt routines automatically do this for you The following C and Pascal examples show what the shell of your ISR should be like In C void interrupt ISR void Your code goes here Do not use any DOS functions outportb BaseAddress 7 0 Clear DM5804 interrupt outportb 0x20 0x20 Send EOI command to 8259 In Pascal Procedure ISR Interrupt begin Your code goes here Do not use any DOS functions Port
107. s A B C Rext 5000 Vext 1 7V IPHL Port Hold Low Leakage Current 50 300 pA Vour 1 0V Port A only IPHH Port Hold High Leakage Current 50 300 pA Vour 3 0V Ports A B C IPHLO Port Hold Low Overdrive Current 350 pA Vour 0 8V IPHHO Port Hold High Overdrive Current 350 pA Vour 3 0V lec Vec Supply Current 10 mA Note 3 IccsB Vec Supply Current Standby 10 pA Voc 5 5V Vin Voc or GND Port Conditions If I P Open High O P Open Only With Data Bus High Low CS High Reset Low Pure Inputs Low High NOTES 1 Pins A4 Ao CS WR RD Reset 2 Data Bus Ports B C 3 Outputs open 4 Limit output current to 4 0 mA 18 intel CAPACITANCE Ta 25 C Voc GND OV 82C55A Symbol Parameter Min Max Units Test Conditions Cin Input Capacitance 10 pF Unmeasured pins C I O Capacitance 20 F returned to GND Mp lob R fe 1 MHz NOTE 5 Sampled not 100 tested A C CHARACTERISTICS Ta 0 to 70 C Vec 5V 10 GND OV Ta 40 C to 85 C for Extended Temperature BUS PARAMETERS READ CYCLE Symbol Parameter 820534 2 Units Test Min Max Conditions tAR Address Stable Before RD 0 ns TRA Address Hold Time After RD T 0 ns AR RD Pulse Width 150 ns tap Data Delay from RD 120 ns tDF RDT to Data Floating 10 75 ns try Recovery Time between RD WR 200 ns WRITE CYCLE Symbol Parameter ee Units a M
108. scal this is programmed as V Port PortAddress V VOR 8 Port PortAddress V Setting or clearing more than one bit at a time is accomplished just as easily To clear multiple bits in a port AND the current value of the port with the value b where b 255 the sum of the values of the bits to be cleared Note that the bits do not have to be consecutive Example Clear bits 2 4 and 6 in a port Read in the current value of the port AND it with 171 171 255 2 2 2 and then write the resulting value to the port In C this is programmed as v inportb port address v v amp 171 outportb port_address v To set multiple bits in a port OR the current value of the port with the value b where b the sum of the individual bits to be set Note that the bits to be set do not have to be consecutive Example Set bits 3 5 and 7 in a port Read in the current value of the port OR it with 168 168 25 25 27 and then write the resulting value back to the port In assembly language this is programmed as mov dx PortAddress in al dx or al 168 out dx al Often assigning a range of bits is a mixture of setting and clearing operations You can set or clear each bit individually or use a faster method of first clearing all the bits in the range then setting only those bits that must be set using the method shown above for setting multiple bits in a port The following example shows how this two s
109. serted Counting begins only after the gate line is asserted after the counter is ARMed If the Gate line remains asserted the counter will count to TC reload automatically from the load register and disarm itself until receipt of a new ARM command If the gate is deasserted prior to the counter reaching TC the counter will halt When the Gate line is reasserted on a halted counter the count value is transferred to the Hold register and the next valid count source edge will cause the counter to reload from the Load register and begin counting again effectively retriggering the counter as shown in Figure 22 One application of this mode is to measure the delay between two successive gate edges by reading the remainder count value from the hold register MODE O SOFTWARE TRIGGERED STROBE WITH EDGE GATING AND HARDWARE RETRIGGERING Mode O is similar to Mode N in that the counter must be ARMed and a valid Gate edge must be received to start the counter Unlike most other modes however each time a valid gate edge is received prior to the counter reaching TC will cause the counter to be retriggered by reloading the counter from the load register on the first valid source edge following a valid gate edge If the counter is allowed to reach TC is automatically reloads from the Load register and disarms itself The counter is insensitive to gate edges while disarmed and while counting The counter is sensitive only to a valid gate edge whil
110. st consider when writing your ISR The most important is do not use any DOS functions or routines that call DOS functions from within an ISR DOS is not reentrant that is a DOS function cannot call itself In typical programming this will not happen because of the way DOS is written But what about when using interrupts Then you could have a situation such as this in your program If DOS function X is being executed when an interrupt occurs and the interrupt routine makes a call to DOS function X then function X is essentially being called while it is already active Such a reentrancy attempt spells disaster because DOS functions are not written to support it This is a complex concept and you do not need to understand it Just make sure that you do not call any DOS functions from within your ISR The one wrinkle is that unfortunately it is not obvious which library routines included with your compiler use DOS functions A rule of thumb is that routines which write to the screen or check the status of or read the keyboard and any disk I O routines use DOS and should be avoided in your ISR The same problem of reentrancy exists for many floating point emulators as well meaning you may have to avoid floating point real math in your ISR Note that the problem of reentrancy exists no matter what programming language you are using Even if you are writing your ISR in assembly language DOS and many floating point emulators are not reentrant Of cou
111. t of a new ARM Command As shown in Figure 15 Once the counter has been ARMed and a valid Gate edge has been received the counter will count once to TC and reload the counter from the Load register It will remain inactive until receipt of another Gate edge While counting subsequent gate edges are disregarded SPECIFICATIONS SUBJECT TO CHANGE WITHOUT NOTICE Copyright 2000 Celeritous Technical Services Corp 16 Rev E Tuesday September 25 800 687 6510 806 793 0708 FAX 806 793 0710 http www celeritous com Celeritous Technical Services Corp 3308 34th St Lubbock Texas 79410 CTS9513 2 5 Chan 16 bit 20MHz Counter Timer SOURCE WR DATA y ARM COMMAND 1 care A RR COUNT VALUE L 1 y L 2 y L 3 y y 2 y 1 Y H y H 1 y H 2 Y H 3 Y y 2 y 1 y 5 Lua TC OUTPUT TOGGLE OUTPUT COUNTER MODE G WAVEFORMS Figure 16 CTS9513 Counter Mode G Representative Waveforms SOURCE WR DATA y ARM COMMAND X GATE AAA AAA Du COUNT VALUE L 1 Y L 2 y er y 2 y 1 y H Y H 1 y H 2 K die Y 2 Y 1 y L y L 1 TOGGLE OUTPUT X Y COUNTER MODE H WAVEFORMS Figure 17 CTS9513 Counter Mode H Representative Waveforms MODE G SOFTWARE TRIGGERED DELAYED PULSE ONE SHOT In Mode G once the counter has been ARMed the counter will 1 Countto TC with the Load register value 2 Reload itself automatically from the Hold Register 3 Count to TC with the Hol
112. t status through bit 0 in the status word I O address location BA 7 After the interrupt has been serviced the clear command returns the IRQ line low disabling the tri state buffers and pulling the output low again Figure 1 3 shows this circuit Because the interrupt request line is driven low only by the pull down resistor you can have two or more boards which share the same IRQ channel You can tell which board issued the interrupt request by monitoring each board s IRQ status bit NOTE When you use multiple boards that share the same interrupt only one board should have the G jumper installed The rest should be disconnected Whenever you operate a single board the G jumper should be installed CLK IRQ STATUS INTERRUPT REGISTER INTERRUPT Fig 1 8 Pulling Down the Interrupt Request Line P4 Interrupt Source Select Factory Setting EXTINT This header connector shown in Figure 1 4 lets you connect one of four interrupt sources for interrupt genera tion These sources are PC3 which is the INTRA signal from the 8255 PPI PCO which is the INTRB signal from the 8255 PPI OUTS the output from Am9513A timer counter 5 and EXTINT an external interrupt you can route onto the board through the P2 I O connector To connect an interrupt source place the jumper across the desired set of pins Note that only ONE interrupt source can be activated at a time PC3 PCO OUT5 EXTINT P4 Fig 1 4 Interrupt Source Select
113. tep operation is done Example Assign bits 3 4 and 5 in a port to 101 bits 3 and 5 set bit 4 cleared First read in the port and clear bits 3 4 and 5 by ANDing them with 199 Then set bits 3 and 5 by ORing them with 40 and finally write the resulting value back to the port In C this is programmed as 4 8 v inportb port address v v amp 199 v v 40 outportb port_address v A final note Don t be intimidated by the binary operators AND and OR and try to use operators for which you have a better intuition For instance 1f you are tempted to use addition and subtraction to set and clear bits in place of the methods shown above DON T Addition and subtraction may seem logical but they will not work if you try to clear a bit that is already clear or set a bit that is already set For example you might think that to set bit 5 of a port you simply need to read in the port add 32 25 to that value and then write the resulting value back to the port This works fine if bit 5 is not already set But what happens when bit 5 is already set Bits O to 4 will be unaffected and we can t say for sure what happens to bits 6 and 7 but we can say for sure that bit 5 ends up cleared instead of being set A similar problem happens when you use subtraction to clear a bit in place of the method shown above Now that you know how to clear and set bits we are ready to look at the programming steps for the DM5804 board functions In
114. ter IMR earlier in this chapter for help in determining your IRQ s bit After setting the bit write the new value to I O port 21H 4 12 With the startup IMR saved and the interrupts on your IRQ temporarily disabled you can assign the interrupt vector to point to your ISR Again you can overwrite the appropriate entry in the vector table with a direct memory write but this is a bad practice Instead use either DOS function 25H set interrupt vector or if your compiler provides it the library routine for setting an interrupt vector Remember that vector 8 is for IRQO vector 9 is for IRQ1 and so on If you need to program the source of your interrupts do that next For example if you are using the program mable interval timer to generate interrupts you must program it to run in the proper mode and at the proper rate Finally clear the bit in the IMR for the IRQ you are using This enables interrupts on the IRQ Restoring the Startup IMR and Interrupt Vector Before exiting your program you must restore the interrupt mask register and interrupt vectors to the state they were in when your program started To restore the IMR write the value that was saved when your program started to I O port 21H Restore the interrupt vector that was saved at startup with either DOS function 35H get interrupt vector or use the library routine supplied with your compiler Performing these two steps will guarantee that the interrupt status of yo
115. the 8 bit bi directional bus port Port A Bidirectional Bus I O Control Signal Definition INTR Interrupt Request A high on this output can be used to interrupt the CPU for input or output oper ations Output Operations OBF Output Buffer Full The OBF output will go low to indicate that the CPU has written data out to port A ACK Acknowledge A low on this input enables the tri state output buffer of Port A to send out the data Otherwise the output buffer will be in the high impedance state INTE 1 The INTE Flip Flop Associated with OBP Controlled by bit set reset of PCg Input Operations STB Strobe Input A low on this input loads data into the input latch IBF Input Buffer Full F F A high on this output indicates that data has been loaded into the input latch INTE 2 The INTE Flip Flop Associated with IBF Controlled by bit set reset of PCy 13 82C55A In e CONTROL WORD Dg Ds D Dz D D EDUC Do B Piza 1 INPUT 0 OUTPUT D PORTB 1 INPUT 0 OUTPUT gt GROUP 8 MODE 0 MODEO 1 MODE 1 231256 18 Figure 13 MODE Control Word 231256 19 Figure 14 MODE 2 DATA FROM CPU TO 82C55A WR OBF INTR dl E e T E IBF tes l to el to S CD te F et nig RD DATA FROM DATA FROM PERIPHERAL TO 82C55A 82C55A TO PERIPHERAL DATA FROM 82C55A TO 8080 231256 20 Figure 1
116. ther the associated Load or Hold register It may also serve as an automatic retrigger of the counter once the counter is loaded SAVE Command The SAVE command is used to save the contents of the counter while counting continues This allows the counter value to be read without interfering with the counter Subsequent SAVE commands will overwrite any previous contents of the Hold register CLEAR Command The CLEAR command is used to reset the counter output toggle to initialize it to a low state This command is only active if the output toggle is programmed It is inactive if a Terminal Count output is specified SET Command The SET command is used to set the counter output toggle to initialize it to a high state This command is only active if the output toggle is programmed It is inactive if a Terminal Count output is specified STEP Command The STEP Command increments of decrements the selected counter by one depending on the operating mode Master Mode Commands A number of commands directly affect the Master Mode Register without having to write to it directly These commands affect primarily the modes of the data path data pointer sequencing enabling the divided FOUT output clocks and clearing of latched interrupt outputs from the counters Table 6 summarizes these commands REGISTER DEFINITIONS STATUS REGISTER The 16 bit Status Register indicates the 1 Status of the internal word pointer 2 Status of the counter
117. ur computer is the same after running your program as it was before your program started running Common Interrupt Mistakes Remember that hardware interrupts are numbered 8 through 15 even though the corresponding IRQs are numbered 0 through 7 Two of the most common mistakes when writing an ISR are forgetting to clear the interrupt status of the DM5804 and forgetting to issue the EOI command to the 8259 interrupt controller before exiting the ISR 4 13 Example Programs Included with the DM5804 is a set of example programs that demonstrate the use of many of the board s features These examples are in written in C Pascal and BASIC Also included is an easy to use menu driven diagnostics program 804DIAG which is especially helpful when you are first checking out your board after installation C and Pascal Programs These programs are source code files so that you can easily develop your own custom software for your DM5804 Timer Counter INTRPTS Shows how to generate interrupts and read the digital VO lines COUNT Shows how to use the Am9513A as a simple counter Digital VO DIGITAL Simple program that shows how to read and write the digital I O lines BASIC Programs These programs are source code files so that you can easily develop your own custom software for your DM5804 Timer Counter COUNT Shows how to use the Am9513A as a simple counter FCOUNT Shows how to create a frequency counter using the Am9513A D
118. urn a product to the factory for service please follow this procedure Read the Limited Warranty to familiarize yourself with our warranty policy Contact the factory for a Return Merchandise Authorization RMA number Please have the following available Complete board name Board serial number A detailed description of the board s behavior List the name of a contact person familiar with technical details of the problem or situation along with their phone and fax numbers address and e mail address if available List your shipping address Indicate the shipping method you would like used to return the product to you We will not ship by next day service without your pre approval Carefully package the product using proper anti static packaging Write the RMA number in large 1 letters on the outside of the package Return the package to RTD Embedded Technologies Inc 103 Innovation Blvd State College PA 16803 0906 USA D 2 LIMITED WARRANTY RTD Embedded Technologies Inc warrants the hardware and software products it manufactures and produces to be free from defects in materials and workmanship for one year following the date of shipment from RTD Embedded Technologies INC This warranty is limited to the original purchaser of product and 1s not transferable During the one year warranty period RTD Embedded Technologies will repair or replace at its option any defective products or parts at no additional
119. venly press down on the board until it is secured on the connector NOTE Do not force the board onto the connector If the board does not slide into place remove it and try again Wiggling the board or exerting too much pressure can result in damage to the DM5804 or to the module it is being stacked with 6 After the board is installed connect the cable to I O connector P2 on the board When making this connec tion note that there is no keying to guide you in orientation You must make sure that pin 1 of the cable is connected to pin 1 of P2 pin 1 is marked on the board with a small square For twisted pair cables pin 1 is the dark brown wire for standard single wire cables pin 1 is the red wire 7 Make sure all connections are secure External I O Connections Figure 2 1 shows the DM5804 s P2 I O connector pinout Refer to this diagram as you make your I O connec tions 2 3 SRC1 OUT2 GATE2 SRC3 OUT4 GATE4 SRC5 DIGITAL GND EXTINT FOUT DIGITAL GND PA7 PA6 PAS PA4 PA3 PA2 PA1 PAO PB7 PB5 PB3 PB1 12 VOLTS 12 VOLTS O OJO OJO I OO DE BO 309 OS DS Se 9 G9 E SIE G3 6 G3 G0 UE Oe GITAL GND GITAL GND GITAL GND 5 VOLTS DIGITAL GND Fig 2 1 P2 I O Connector Pin Assignments Connecting the Timer Counters and Digital I O For all of the digital connections the high side of an external signal source or destination device is connected to the appropriat

DM5804/DM6804 User's Manual - RTD Embedded Technologies, Inc.

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