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SERVICE MANUAL 2031 DISK DRIVE

1. 2031036 01 DEMO DISKETTE C 1540041 01 IEEE TO IEEE INTERFACE CABLES 2 905080 01 TO IEEE INTERFACE CABLES 4 1 320101 01 TROUBLESHOOTING GUIDE NOTE Always check for latest ROM ECO upgrade If socketed IC is suspected bad be sure to check socket with ohmmeter SYMPTOM POSSIBLE SOLUTION No LED s on power up Is Power cord plugged into wall outlet correctly Is Power cord plugged into the disk drive correctly Check line fuse Check power switch Check clock on 6502 pin 37 Check 5 and 12 volt lines Error LED flashes on power up Check all RAM and ROM locations Error LED stays on all the time Check 6502 microprocessor Check ROMs Check 12V Check 6502 logic gates Drive motor runs continuously and red LED stays on Check ROM Check drive motor PCB Drive motor runs continuously and red LED stays off Drive motor runs continuously Check VR2 5V Regulator Check Power Transformer Check 6522s Check motor control PCB After the drive warms up the motor runs continuously Loads programs with red LED flashing Check drive speed Check stepper motor Check ROMs Check drive alignment Loading is intermittent Does not load wh
2. The Clock Circuits Crystal Y1 outputs a 16 MHz clock signal This is input to UC6 on pin 8 UC6 is configured as a 16 frequency divider The output of UC6 pin 12 is 1 MHz clock signal used as the system clock Phase O for the microprocessor UE7 is a programmable counter 16 15 14 13 that outputs varying frequency clock used to compensate for difference in recording area sector for sectors on inner tracks Trks 1 2 3 as compared to sectors on out most tracks Trks 33 34 35 The area sector for inner tracks is less than the area sector for out most tracks so the recording clock frequency is increased when writing on inner tracks to keep the flux density constant This clock output is on pin 12 of UE7 Tracks Clock Frequency Divide By 1 17 1 2307 MHz 13 18 24 1 1428 MHz 14 25 30 1 0666 MHz 15 31 35 1 MHz 16 20 2031 LP CIRCUIT THEORY Wm UE ch si 35 Sy 4 PR 2 3 7 3 E Ger m 5 i A55 N E haj I a N 4 zer 27 i TE 1 4 5 Microprocessor Control of RAM and ROM UAB4 and UABB are 8192 x 8 bit ROMS that store the Disk Operating System DOS UABA resides at memory locations 5 UABB resides at memory locations EO00 FFFF 087 decodes the addresses output from the
3. suyo 941 10301 sum 13A sum Q3H u DUO LL 1 Uld THA dejiejueo 0 w jeddsis pZ uo pue puj W 15 w LHYDNHS 11140844 39NVISIS3U 17 PARTS LIST INTERGRATED CIRCUITS 1A LM 2917N TRANSISTORS 01 GE 7941 sub GE 7947 Q2 M10060 0 IN4148 CAPACITORS All values in microfarads C1 4 7 50V Tant 015 35V 5 047 50V 47 50V Tant 1 50V 1 35V 220 16V Elect 47 50V fant 50V Assy 25181 ONLY 100 1 909 1 1 8W 10K 196 596 1W Trim Pot Rectangle 3 4 in SHUGART SERVO BOARD COMMODORE PART 731414701 5 CRS CR4 CR3 CR2 CRI t o 5 COMPONENT LOCATIONS MOTOR CONTROL PCB ASSEMBLY P N 25129 COMPONENT LOCATIONS MOTOR CONTROL PCB ASSEMBLY P N 25181 12 R9 RIG RI7 RIO RII YEL IN RI3 RIS R8 R3 2 CR 4 CR3 CRI RI CR4 5 0 ESE 2 1 2 aj 2 m O i m w 2 gt 2 I lt H IN z o o i BRN NOTE ASSEMBLY P N 25181 BLC INCLUDES C9 ON COLLECTOR OF Q1 RTN 8 5
4. 1 t 1 t U 1 m Jun 1 A i 211018 UM asc 8 9 P mi OQ m Ie YB jaj Hai ud 7 CZY m EP et zi fi EHE 4 91 wa t A BER p uM z it m cz oem gig idi cz 2 i 2 8 EE A t 4 11 D 1 k DL T 462 z 1 55 8 Oa i sa w o E i 5 go s 005 33 7 an 1 2 1 1 un Su awn LI 4 1 1 gt TS S2 dt 2237 1 1 1 43 22 o PGA 259 m Li n 1 1 fl 4 a d 1 1 1 1 V LEJ Pa i 1 1 tr n 4 83 OL j 31 U I 5 7X 74 5 OED 5 7 1 1 LI zem 1 i i EE 1 1 x 8 z 22 3 8 1 2 545 a det Ta PNN aia E i 5 t 622 5 NI my M1 26 EM Supe L L0 1 1 t 1 Ur 75 cao 1 LI I TR w 5 anga Nm i OW DOR PERRE 2 a p ox a e M MANN Imm 73 A gt ala 3 y HER 1540 41 2031 LP POWER SUPPLY ASSEMBLY PARTS LIST FUSE HOLDER 903614 01
5. 2031 LP CIRCUIT THEORY Ndoo A The Power Supply The input AC voltage is controlled by switch 1 SW1 Disk circuit protection is provided by fuse 1 F1 If SWT is closed the AC voltage input is applied to the primary winding of transformer one T1 T1 steps down the AC input voltage into two smaller AC voltages The top secondary AC output approx 16VRMS is converted to DC by the Full Wave Bridge Rectifier CR1 The DC output of CR1 is regulated at 12VDC by VR1 The bottom secondary AC output of T1 approx 9VRMS is converted to DC by the Full Wave Bridge Rectifier CR3 The DC output of CR3 is regulated at 5VDC by VR2 High frequency filtering is provided by C1 and C3 for the 12VDC supply and C4 C60 C6 8 10 19 22 31 etc for the 5VDC supply Low frequency filtering is provided by C51 and C2 for the 12VDC supply and C52 and C5 for the 5VDC supply Reset Logic The 2031 disk drive is automatically reset on power up by UF1 a 555 timer when triggered by the 5V applied at pin 8 A reset can also be set by the IFC line on the IEEE Interface The output pulse width is determined by the values of R43 and C36 The pulse width 1 1 x R43 x C36 5 seconds The output on pin of is an active high It is inverted by UC1 to active A low output at UC1 pin 10 resets the unit and initializes all the microprocessor logic 19 2031 LP CIRCUIT THEORY 4 v lt 4 4 mid
6. LL 924 994 4 Mr 584 kos 1 888411 we 9 J gt LO 4222 Lay ar ED 16 IF 235 CH c Na 928 UD to TIL EN 524 812 hz LD er 22420 x I L 222 X 199 110 NEN HER 2 8 L G usn B 8 SLNIOd 1531 i 28 N LN3WNDITV SL g 9 x NGN won 190 EN 8 n RO zu 1555 155 50 il tto C 2 pd 39IA3Q GHVOB OPOLEOCH A181INASSV 82d PLEASE NOTE Commodore part numbers are provided for reference only and do not indicate the availability of parts from Commodore Industry standard parts Resistors Capacitors Connectors should be secured locally Approved cross references for TTL chips Transistors etc are available in manual form through the Service Department order part 314000 01 Unique or non standard parts will be stocked by Commodore and are indicated on the parts list by a Vendor Name and part number have been provided for your convenience in ordering custom or unique parts INTEGRATED CIRCUITS 75161 Transceiver 74LS14 7406 7406 74LS139 75160 Transceiver 7415164 7415133 741502 7415193 74 586 311 741504 2114 Static RAM 6502 Microprocessor 6522 6522 7415245 7415165 7415
7. R W 2 E ES 4024 5 lt om t ERASE 90 When is being read from the disk is induced into the R W coil by the magnetic fields on 38 CN the disk causing current flow which is detected by the read amplifiers Current flow through the R W coil will forward bias either CR12 CR14 depending on the direction Q1 and CR16 must be for ward biased The first amplifier UbR senses this current flow from the R W coil one of the inputs amplifies it L2 L3 L4 L5 and C39 act as a low pass filter suppressing noise the amplified output U3R is a differential amplifier which amplifies the difference of the two input signals from the filter section U2R is a peak detector The output of U2R will pulse high when a 17 is read This signal is the reconstruction of data recorded The time domain filter U3N times out when a 895 u 51 bit has been read so unwanted 1 bits are not added to the actual data The one shot ge 3 N generates the correct data pulse width ai at Th r a Write Amplifier Circuits A E 33 fa 2 eo During a write operation pin 4 of U6N must be high This forward biases Q1 and CR16 If pin oF Son 5 of USN goes low 04 and CR15 become forward biased passing current flow through R W co RAO I 1 If Q goes low Q5 and CR13 become forward biased passing current flow through R W 2 W
8. 0000 07FF This memory is used for processor stack operations general processor housekeeping user program storage and 4 temporary buffer areas UbJ U5K 06 decode the addresses output from the processor when selecting RAM U6J also decodes the address selection of the VIAs U3J and U3H The Clock Circuit The clock circuit outputs a 16 MHz clock signal at U4C pin 11 This is input to 040 on pin 5 U4D is configured as a 16 frequency divider The output of U4D pin 7 is a 1 MHz clock signal used as the system clock Phase O for the microprocessor The 16 MHz clock signal is also used for the vary ing frequency clock circuit see Sheet 1 The Power Supply THE CHASSIS When the switch is closed the AC voltage input is applied to the primary winding of the transformer Circuit protection is provided by a 5 amp fuse The transformer steps down the AC input voltage into two smaller AC voltages One secondary output approx 16VRMS is applied at connector P3 pins 1 and 4 the other secondary output approx 9VRMS is applied at P3 pins 2 and 3 THE PCB The 16VRMS AC applied between pins 1 and 4 is converted to DC by the full wave bridge rectifier CR1 The DC output is regulated at 12VDC by VR2 High frequency filtering is pro vided by C6 low frequency filtering by C2 and C4 The 9VRMS AC applied between pins 2 and 3 is converted to DC by the full wave bridge rectifier CR2 The DC output is regulated at BVDC by VR1
9. 05 C 901437 01 C 901435 01 901493 01 901494 01 901521 01 325502 01 901521 02 901521 01 901521 17 901521 30 901521 15 901521 45 901522 03 901521 54 901522 06 901521 28 901521 12 901521 18 901521 40 901521 06 901521 21 901521 26 901523 01 901522 06 901521 24 901521 26 901521 01 901521 06 901521 32 901510 01 901522 01 901523 04 901523 08 901523 08 1N5226B 3 3V 500mW Zener Sub HZ3C 2 3 3V 500mW Zener Sub HZ4A 1 3 3V 500mW Zener Sub 1N4148 Signal 1N5131B 5 1V 500mW Zener HZ5C 2 5 1V 500mW Zener 1N4002 Signal 1N4148 Signal RESISTORS All Values are in ohms 1 4 5 unless noted otherwise 22K 91 1 4W 1 680 9 1K 1 4W 196 2 2K 220 PCB ASSEMBLY 1540033 RESISTORS Continued 360 8 2K 470 22K 360 150 1 4W 196 470 R39 42 680 1 5K 2 2K 100 1 4W 196 470 470 150 2 2K 680 2 4K 1M 5 1K Electrolytic Elect Ceramic Electrolytic Elect Ceramic Tantalum Ceramic Tantalum 20 Ceramic 5 Ceramic Tantalum Tantalum 20 Ceramic Ceramic Ceramic 5 Ceramic 5 Ceramic Ceramic Ceramic Efectrolytic Ceramic Ceramic Ceramic Ceramic Ceramic Etectrolytic Electrolytic Ceramic Ceramic Ceramic Tantalum Tantalum Ceramic Electrolytic Ceramic Ceramic Header Assy Molex 5271 04A Header Assy 5049 04AG Rt Angle Cnnct IEEE C 903206 01 Header Assy Molex 3094 03A
10. BEZEL Brown 31410401 ALP R W HEAD ASSEMBLY 1 R W Head 2 Load Arm w Pad 3 Metal Band 31410501 ALP STEPPER MOTOR ASSEMBLY 1 Stepper Motor w Harness 2 Stepper Pulley 31410601 ALP D C MOTOR 1 Pulley Wheel w Spring 2 Plastic Housing 9 31410901 ALP HOUSING SPINDLE ASSEMBLY 1 Housing Base 2 Spindle Assy 3 L R Guide Shafts 31411001 ALP DRIVE BELT 31411101 ALP EJECT ASSEMBLY 1 Eject Plate 2 Eject Spring 31411201 ALP HARDWARE 1 Assorted Screws 2 Zero Stop Tab 31417401 UNIV Replacement Load Pad ALPS DRIVE ASSEMBLIES 1540 1541 2031 LP R W BLU Y J3 EL BLU WHT ELA RED YELN RED MOTOR CONTROL P C B Luv gsm READ WRITE HEAD ASSEMBLY une MOTOR ON 7 12 RETURN BLU gt MOTOR RETURN lt GRY TACH DC MOTOR gt YELSTACH MOTOR CONTROL PCB FUNCTION STEP MOTOR 5 gt e e XV N OMe 8 Le Kon DC MOTOR CONTROL PCB TRANISTOR ORG 3 PUR 54444141 21 4 2443 DIODE 2 BRN BLU 5 4 LED RED BLK 33 34 AOS 4189070 82 MviL OIL S 10 SIS8H GH A9L 72 2 O OJEE 15159 vu AGE 471070 5022 103SIS2H H AOS 2 5389 10151599 cH J LvO0O O 22 Mb L 1
11. Header Assy 3094 15A Header Assy 3094 06A Header Assy 3094 Inductor 2 24H Ferrite Bead inductor 1004H Inductor 22 Inductor 1004H Inductor 22uH Ferrite Bead Voltage Regulator 12V 1 5 LM340 Voltage Regulator LM323 Crystal Module 16 MHz C 325566 01 Shield Box 4022048 01 Shield Cap 4022047 01 29 PCB ASEMBLY 1540033 BOARD LAYOUT o WZ Son T 5 0 Q 313 o w S iljes 374 Ze 823 7 tzu 053 5 882 2 n 1 z z 1 1 i T Q 12 Volt I amp fo d gy tu 2 A a o 0 ve 9 t Bla 17774 1 2418 x 25 YCH qM 1 g 479 7 9 t zu 9 i ne 2 Gzy CUM W 2145 7 553 M A 012 2 0 ICH gvi m IF 5119 zd 220 892 982 14989 i zr3 m 989 LH 2 ery ma 1 1 1 n Ei 4 gy u r tr NN te m GH 5 oo SE 151 15 15 7 1 gt s 589 NM PRE e 8 T gt 4 tt 4 9182 H 022 22 092 LPI Ir oo 77 oo 841823 nr PEE ei ml Lg 1 11 ul n 87 1 1 mi E 4 WIYJ ot N pM
12. ROCKER SWITCH 904509 01 POWER CNNCT FILTER 903467 03 sub 325552 01 FUSE SLOW BLO 250V 1 0A 903556 16 POWER TRANSFORMER 1540009 02 2031 LOW PROFILE POWER SUPPLY SHIELD WIRE _ GREEN YELLOW 1 540002 01 E 5 BLUE 3 BLACK 9 TO 11 V 3 6 BLUE INPUT 4 ORANGE VOLT 10 11 TO 17 V VOLT 10 1 WHITE 7 ORANGE PRIMARY SECONDARY TRANSFORMER TOP wb HARNESS ASSEMBLY DRAWING HARNESS FROM DISK 5 SA __ C 9 5 31 RESISTANCE CHECKS LOW PROFILE ALPS DRIVE BROWN RED BLACK 32 OHMS END TO CENTERTAP STEPPER MOTOR 64 OHMS END TO END YELLOW ORANGE RED YELLOW MOTOR COIL 17 OHMS TACH COIL TACH COIL 175 OHMS AT REST SPINDLE MOTOR GREY COIL 135 190 OHMS IN MOTION BLUE R W COIL R W END TO END 32 4 OHMS RED R W END TO CENTERTAP 16 3 OHMS HITE ERASE w ERASE COIL END TO END 10 5 OHMS COIL YELLOW 32 O PARTS LIST 32551901 Alps Drive Black 32551902 Alps Drive Brown 31410001 ALP DOOR HUB ASSEMBLY 7 31410701 ALP MOTOR CONTROL PCB 1 Door Assy w Spring 2 Hub Collet Assy 3 Arm Support Assy ASSEMBLY 1 Motor Control PCB 2 Harness Assy 31410101 ALP LEFT DISK GUIDE ASSEMBLY 8 31410801 ALP TENSION PULLEY ASSEMBLY 1 Diskette Guide 2 LED Assy w Harness 3 Write Protect Assy 31410201 ALP RIGHT DISK GUIDE 31410301 ALP FRONT BEZEL Black 31410302 ALP FRONT
13. see Sheet 4 The MTR output on pin 12 controls the spindle motor refer to the motor control schematic on page 18 The write protect switch WPS is monitored at pin 14 of U3J and the red activity LED is controlled at pin 13 Varying Frequency Clock The DSO and DS1 outputs of U3J pins 15 and 16 are input at pins 1 and 15 of U5M U5M is a programmable counter 16 15 14 13 that outputs a varying frequency clock used to com pensate for the difference in recording area sector for sectors on inner tracks Trks 1 2 3 as com pared to sectors on out most tracks Trks 33 34 35 The area sector for inner tracks is less than the area sector for outer tracks so the recording clock frequency is increased when writing on inner tracks to keep the flux density constant This clock output is on pin 12 of UbM and is used to clock the data from the read amplifier circuits Tracks Clock Frequency Divide By 1 17 1 2307 MHz 13 18 24 1 1428 MHz 14 25 30 1 0666 MHz 15 31 35 1 MHz 16 Read Write Control Logic During a write operation U3L converts parallel data into serial data The output on pin 9 is input to gate UGM pin 5 U6M outputs the serial data on pin 6 at the clock rate determined by the input signal on pin 4 The output clocks the D flip flop U5N see Sheet 4 The outputs of U5N O and Q drive the write amplifiers During a read operation data from the read amplifiers is applied to the CLR input of counter U2N The outputs C
14. 01SISSH L LH AGE 4701 onA on29 3 98112 8tLvNI 72182 GAOZ 103SISGH LHA 39 0 048 10151 1 8 1 103SIS2H OLH GLLLWSZ 10SISUEJ 20 089 0 03515 6H 98 2052 401818461 20 GOGL 1035159 84 GELZISZ 03515061 LO 0008 4015159 9H 890 Auo 4 544 JOENAS L 2 Su GH Ld NO OHOLOW 18 CA cu 13A ino NI HOLOW O HOWL WEE 1no HOLOW O ong CHO 7149 0 poyi L u 21 JILVIN3HOS QHVOS H0LOW SdlV
15. 6 aaa aa aaa aaa saisis esses senate nennen BLOCK DIAGRAM DEVICE NUMBER CHANGE 1 40 44 12 4 OVERVIEW 1 2 1 4 14 866 reris eris enean HiGH PROFILE BOARD LAYOUT 0 4 1 221 5 2 1 4 lt ense nnne PCB PARTS LIST 6 6 UPGRADE NOTES 2 1 1 02 47 4 44 lt CIRCUIT THEORY SCHEMATIC POWER SUPPLY PARTS amp WIRING DIAGRAM SHUGART DRIVE PARTS 1 anise nnn nnns 10 11 11 15 16 17 18 18 19 29 30 30 31 32 33 33 34 2031 DISK DRIVE PRODUCT SPECIFICATION GENERAL DESCRIPTION MAXIMUM STORAGE MEDIA INPUT OUTPUT CONTROLLER MEMORY DATA TRANSFER RATE FILE TYPES COMPUTERS MEDIA COMPATIBILITY POWER REQUIREMENTS POWER CONSUMPTION The 2031 is a single drive 5 1 4 inch floppy disk unit It uses a 35 track 48 single headed drive High profile Shugart drive assembly Low profile Alps drive assem
16. 74 9602 One Shot 592 555 Timer 7400 7415193 2364 2364 ROM 741504 7411500 7415191 7415193 741574 592 741504 741542 741510 741504 741500 7406 TRANSISTORS CR2 CR3 4 CR6 9 CR10 CR11 16 CR17 CR18 19 2N4401 2N4400 2N4403 1 5 A 50V Bridge Rectifier 4 200V Bridge Rectifier 1 4005 1N4005 1N5231 5 1 V Zener 1N4148 1 5226 13 3 V Zener Germanium 1N270 901494 01 901521 30 901522 06 901522 06 901521 18 901493 01 901521 28 901521 15 901521 21 901521 26 901521 32 901523 04 901521 02 901453 04 C 901435 01 C 901437 01 C 901437 01 901521 46 PARTS LIST PCB ASSEMBLY 72031040 01 RESISTORS All Values are ohms 1 4 W 596 unless noted otherwise 1 5K 1K 680 220 2K 9 09K 1 4 W 196 1K 180 270 47 2 2K 1M 4 7K 6 19K 1 4 W 1 CAPACITORS 901521 12 901521 06 901510 01 901523 08 901523 01 901522 04 901521 26 C 901484 05 C 901484 03 901521 02 901521 01 901521 40 901521 26 901521 06 901523 08 901521 02 901521 17 901521 24 901521 02 901521 01 901522 06 900756 01 900755 01 Low Leak Elect Low Leak Elect Low Leak Elect Ceramic Ceramic Ceramic Ceramic Ceramic Ceramic Ceramic Ceramic Ceramic Ceramic Ceramic Low Leak Elect Low Leak Elect Tantalum Ceramic Ceramic Ceramic Ceramic Ceramic Ceramic Ceramic Ceramic Ceramic Ceramic Ceramic RT Angle CNNCT IEEE Header R W Head CNNCT Head
17. D WIRE GREEN YELLOW TRANSFORMER WIRING DIAGRAM ASSEMBLY DRAWING OOO O PARTS LIST 95055000 Shugart Drive Assembly 31414001 SHU DOOR HUB ASSEMBLY 1 Door Assy w Frame 2 Hub Collet Assy 31414101 SHU LEFT DISK GUIDE 31414201 SHU RIGHT DISK GUIDE 31414301 SHU FRONT BEZEL 31414401 SHU R W HEAD ASSEMBLY 1 R W Head w Harness 2 Load Arm w Pad 31414501 SHU STEPPER MOTOR ASSEMBLY 1 Stepper Motor w Harness 31414601 SHU D C MOTOR 31414701 SHU MOTOR CONTROL PCB 31414801 SHU HOUSING SPINDLE ASSY 1 Housing Base 2 Spindle Assy 3 L R Guide Shafts 31414901 SHU DRIVE BELT 31415001 SHU WRITE PROTECT SWITCH 31415101 SHU HARDWARE 1 Assorted Screws 31415201 SHU CAM ACTIVATOR 903820 03 UNIV LAMP HOLDER SET SHUGART DRIVE ASSEMBLY 2031HP 2040 4040 16 peioeuuoosip eq pinoys ejqpo eu pue Bnjd eu sjueureinseejy swyo G LL 81M 85213 SWUO GL M AM DEJQ 09 _ LHM GL 811M 9JIM 109 swyo 848625 M XOLIQ 09 M Y sum WIE uo 10128uuoo sjueura1nsee N NYD 161601 swyo G6L GEL eipuids uezo 191014 SIPUICS 1591 SWYO 42 M
18. High frequency filtering is provided by C5 low frequency filtering by C1 and C3 SCHEMATIC 2031038 SHEET 3 of 4 6 MHZ IT gt 5 55 8 on e n u X 5 mod ol ala 4 N St 2165 jor bina UU 3 O MUS 4 A w O c a m ou o 9 ar M gt um 9 gt 9 E I a 05 741 504 T LSO4 USJ 24 2031 HP CIRCUIT THEORY Stepper Motor Control Circuits U1P converts STPO and STP1 into outputs that create a binary four count The outputs YO Y1 Y2 SCHEMATIC 2031038 SHEET 4 of 4 from U1P are inverted by U1N The outputs of the inverters drive the transistors of U1L The current output from these transistors drive the individual phase coils in the stepper motor and return 9 to the 12VDC supply CR6 CR9 suppress the CEMF developed by the motor coils Read Amplifier Circuits Hn When data is recorded on the disk a 1 bit is represented on the disk by a change in direction of AG 8 magnetic flux caused by a change in direction of current passed through the R W coil in the R W ava SPs head When a O bitis to be recorded no change in current flow direction occurs causing the direc tion of the magnetic flux to remain the same on the disk 3 R W HEAD UJ Q R W 1 8 2 5 Qu
19. SERVICE MANUAL 2031 DISK DRIVE HIGH AND LOW PROFILE MODELS DEC 1985 PN 314011 01 Commodore Business Machines Inc 1200 Wilson Drive West Chester Pennsylvania 19380 U S A Commodore makes no expressed or implied war ranties with regard to the information contained herein The information is made available solely on an as is basis and the entire risk as to quality and accuracy is with the user Commodore shall not be liable for any consequential or incidental damages in connection with the use of the information con tained herein The listing of any available replace ment part herein does not constitute in any case a recommendation warranty or guaranty as to quality or suitability of such replacement part Reproduction or use without expressed permission of editorial or pictorial content in any matter is prohibited This manual contains copyrighted and proprietary information No part of this publication may be reproduced stored in a retrieval system or transmitted in any form or by any means electronic mechanical photocopying recording or otherwise without the prior written permis sion of Commodore Electronics Limited Copyright 1985 by Commodore Electronics Limited All rights reserved Dieses Handbuch wurde gescannt bearbeitet und ins PDF Format konvertiert von R diger Schuldes schuldes itsm uni stuttgart de c 2003 CONTENTS Title SPECIFICATIONS 1 1 1
20. The output of the tachometer is rectified by CR1 CR4 1 monitors the output of the rectifier and adjusts the bias to O2 which changes the bias and Q4 to regulate motor current for a constant velocity VR1 is a manual speed adjust ment The speed can be adjusted by watching the 60Hz strobe as the adjustment is made or loading the system test from the diagnostic disk 27 IEEE interface 2031 LP CIRCUIT THEORY All of the signals on the interface are controlled by the I O device UAB1 Eight parallel bi directional data lines PAO PA7 are used as the parallel data bus for the interface UA2 is an octal bus transceiver used to provide communication on the general purpose interface bus GPIB between operating units of the system The data transfer and bus management signals are communicated by UA3 thus com pleting the 16 line interface of the IEEE 488 bus DAV EOI DAC RFD SRQ ATN REN IFC Data Valid End or Identify Data Not Accepted Not Ready For Data Service Request Attention Remote Enable Interface Clear DAV low signifies data is valid on the data bus CBM always sets low while the last data byte is being transferred DAC is low when data is being read and returned high after the last data byte is read RFD is low until all receivers are ready to accept data then the line will go high Not implemented in BASIC but available to the CBM user The host sets the sign
21. al low while sending commands on the data bus REN is held low by the bus controller and the host has this pin per manently grounded The host sends its internal reset signal as IFC low to initialize all devices 28 PLEASE NOTE Commodore part numbers are provided for reference only and do not indicate the availability of parts from Commodore Industry standard parts Resistors Capacitors Connectors should be secured locally Approved cross references for TTL chips Transistors etc are available in manual form through the Service Department order part 314000 01 Unique or non standard parts will be stocked by Commodore and are indicated on the parts list by a Vendor Name and part number have been provided for your convenience in ordering custom or unique parts INTEGRATED CIRCUITS CR5 CR6 11 CR12 CR13 16 CR17 19 6522 VIA ROM COOO SDFFF EOOO SFFFF 6522 VIA 6502 CPU 75160 Transceiver 75161 Transceiver 741500 TMM2016 RAM 741504 741500 741542 741514 7415133 7415245 74177 7415197 7406 7415164 7415165 7415139 7415191 741574 741502 7415193 555 Timer 7406 74LS10 74LS193 74LSOO 741574 74LS86 9602 One Shot 7417 311 OP AMP 592 592 25 673 25C945 Sub 25 1815 250467 Sub 25 2120 25 733 Sub 25 1015 1 5 Bridge Rectifier 1N4002 Signal 4 A Bridge Rectifier 1N4002 Signal PARTS LIST C 901437 01 C 901484 03 C 901484
22. and D are shaped by the NOR gate U2M U2M outputs the serial data on pin 1 then it is converted to parallel data by U2K The output of U2K is latched by U3K The serial bits are counted by UBL When 8 bits have been counted U6K pin 6 goes low 054 pin 6 goes high and U6K pin 8 goes low indicating byte is ready to be read by the processor U2L monitors the parallel output of U2K When all 8 bits 1 the output pin 9 goes indicating a sync bit has been read SHEET 1 of 4 SCHEMATIC 2031038 gt 8 9 Y RSS Q2 ALL FU ES 52 icsi 2115 5 BYTE READ READ WRITE LOGIC 2031 HP CIRCUIT THEORY IEEE interface All of the signals on the interface are controlled by the I O device U3H Eight parallel bi directional data lines PAO PA7 are used as the parallel data bus for the interface U1S is an octal bus transceiver used to provide communication on the general purpose interface bus GPIB between operating units of the system The data transfer and bus management signals are communicated by U1A thus com pleting the 16 line interface of the IEEE 488 bus DAV Data DAV low signifies data is valid on the data bus Valid EOI End or CBM always sets low while the last data byte is being Identify transferred DAC Data Not DAC is low when data is being read and returned high after the last Accepted data byte is read RFD Not Ready RFD is low until all receivers ar
23. ay the 12VDC supply WPS ACT LED Write Protect Switch Connector P6 connects the control circuits to the W P switch and activity light UCD4 a 6522 VIA monitors the state of the write protect sensor on pin 14 and controls the red activity LED on pin 13 25 2031 LP CIRCUIT THEORY Stepper Motor Control Circuits The stepper motor is controlled by two outputs on port B of UCD4 the 6522 VIA STPO and STP1 These two lines are converted by UE2 to a binary four count to drive the four phases of the stepper motor Outputs YO Y1 Y2 and from UE2 are inverted by UF2 The outputs of the inverters drive Q4 Q7 The current output from these transistors drives the individual phase coils in the stepper motor and returns to the 12VDC supply CR13 CR16 suppress the CEMF developed by the motor coils 26 2031 LP CIRCUIT THEORY 12V P5 BRN PIN 2 Q3 R3 C1 R6 GND P5 BLK PIN 1 1 TACH O CR14CR2 IN R4 O4 MOTOR GRN C5 2 OUT A m CR O MOTOR TACH WENT our YEL R2 R10 VRI MOTORC 17 RE ON P5 ORG PIN 3 RS Spindle Motor Control Circuits MTR output from UF2 pin 8 is passed through current driver UG4 to the motor control PCB When MTR is Q1 is biased off and Q2 and Q4 are biased on allowing current flow through the spindle motor coil Attached to the shaft of the spindle motor is an inductive tachometer that generates low level AC voltages as the motor spins
24. bly It is an intelligent device containing its own microprocessor RAM ROM and operating systems software 170K of data formatted 35 tracks 5 1 4 inch floppy disk Single sided single density soft sectored double density can be used but not needed IEEE interface MOS 6502 microprocessor 1 MHz clock 2K RAM 16K ROM Internal 4OK Bytes sec 488 Bus 1 2K Bytes sec Program sequential relative random access and user PET 4000 series 8000 series B128 1541 4040 120 Volts AC 60Hz integral power supply with external 1 Amp fuse 40 Watts maximum BLOCK DIAGRAM STEPPER SPINDLE R W HEAD MOTOR MOTOR olo A A LIL H H 4241 SPINDLE MOTOR SPEED CONTROL B PCB WRITE PROTECT SENSOR SPINDLE STEPPER READ IEEE DRIVE DRIVE WRITE INTER CIRCUITS CIRCUITS CIRCUITS AD ATN ACTIVITY CLK LED DATA LED SUPPLY LP ONLY POWER POWER ON CARE AND MAINTENANCE e DO NOT use MAGNETIZED tools when repairing or adjusting a disk drive DO NOT place disk drive near any device which generates noise e g motors radios televisions e DO NOT stack drives upon each other or in any way inhibit air flow around the unit HEAT BUILD UP can cause disk failures Periodically CLEAN the read write head with 90 alcohol and a cotton swab CHECK load pad for excess wear Clean or replace as n
25. e ready to accept data then the line For Data will go high SRQ Service Not implemented in BASIC but available to the CBM user Request ATN Attention The host sets the signal low while sending commands on the data bus REN Remote REN is held low by the bus controller and the host has this pin per Enable manently grounded IFC interface The host sends its internal reset signal as IFC low to initialize all Clear devices Reset Logic The 2031 disk drive is automatically reset on power up by 035 a 555 timer when triggered by the 5V applied at pin 8 A reset can also be set by the IFC line on the IEEE interface The output pulse width is determined by the values of R43 and C36 The pulse width 1 1 x RA3 x C36 1 second The output on pin of U3S is an active high It is inverted by to active low low output at U3A pin 2 resets the unit and initializes all of the microprocessor logic SCHEMATIC 2031038 SHEET 2 of 4 2 IEEE INTERFACE APPEL DEVICE SELECTION POWER ON RESET 12 2031 HP CIRCUIT THEORY Microprocessor Control of RAM and ROM U5F and U5H are 8192 x 8 bit ROMS that store the Disk Operating System DOS U5F resides at memory locations C000 DFFF resides at memory locations E000 FFFF U5J decode the addresses output from the microprocessor when selecting these ROMS U3B C D and E are 2114 Static RAMS 24 x 4 They reside at memory locations
26. ecessary e Take the following precautions when handling a diskette ALWAYS store a diskette in its jacket Use ONLY felt tip pens when writing on the label of a diskette Do not bend or physically damage a diskette Do not place a diskette in the area of a magnetic field Do not attempt to clean a diskette Do not touch the exposed area of a diskette DIAGNOSTIC an and d ADJUSTMENT procedures fort the 2031 outlined i in detail i in the e Version K 3 0 diagnostic package Commodore Part 31405201 This Kit contains a manual that outlines E testing adjustment and d alignment procedures a and Version 3 0 and 3 5 5 diagnostic p program disks DEVICE NUMBER CHANGE The 2031 drive is shipped from the factory set for device 8 The channel may be hardware altered to device 9 10 or 11 Channel selection is changed on the main logic board by LIFTING the diodes at locations CR 17 18 and or CR 19 The following chart indicates the selected device ADDRESS LOW PROFILE HIGH PROFILE 9 CR 19 CR 19 10 CR 17 CR 18 11 CR 19 amp 17 CR 19 amp 18 The diode locations are indicated on the appropriate schematic OVERVIEW The drive is itself an independent memory device The drive is composed of a media clamp rotating mechanism a head positioning mechanism and an eject mechanism All positioning operations ex cluding insertion and removal of the diskette are controlled by the internal guide mechanism Cl
27. en hot or LED Check ROMs flashed 3 times Searches with LED flashing continuously Check ROMs Searching with no red LED Check 6522s logic gates Message of FILE NOT FOUND is displayed Clean drive head w alcohol Check 0 stop adjustment Check alignment Drive fails to read Check the 311 9602 and 592s There are two 12 volt sources for stepper output and read circuit make sure both are good TROUBLESHOOTING GUIDE Continued SYMPTOM POSSIBLE SOLUTION Fails to format disk Stepper Motor does not step forward Drive speed will not stabilize Will not save when the drive heats up Locks up when loading Fails the performance test and displays a 21 read error Fails the performance test and displays a 27 read error Passes performance test to track 18 then displays 21 read errors Passes the performance test but will not load certain programs Check components related to connector P7 Check 65228 Check write circuits Check 6502 65225 stepper logic Check DC motor Check 6502 microprocessor Check IEEE interface components Check ROM Check test diskette Check Drive Motor Check stop adjust Check read write head Check stepper motor 6 Nid IZN INAS 1 wen Ten 2 8 29 sin 9 B 5 BAR g Ter din vin Ju WEZ 5 192 Paar n n ven Mi i
28. er PWR CNNCT Choke 1004H Choke 224H Inductor 2 24H Voltage Regulator LM323 Voltage Regulator LM340 Crystal 16 MHz Shield Box Shield Cap 903206 01 900556 02 4022048 01 4022047 01 2031 HP UPGRADE NOTES A design error was present in the original 2031 High Profile Single Disk Drive The write circuit was modified to correct the problem however it is possible that some units still need to be revised Revision to correct write circuit 1 Lift Diodes CR13 amp CR15 as shown 2 Install Transistors solder the Collector Lead to Diodes 3 Solder the Center Leads Transistors together to R40 Resistor as shown Use 20 AWG wire for mechanical strength 4 Solder Emitter Leads to feed thru 5 Change R31 amp R32 from 2 7KQ to 1 5K0 SOLDER COLLECTOR LEAD TO DIODE ANODE Q4 AND Q5 SOLDER BASE 2N4403 LEADS TO RESISTOR AL o gt NZ M 10 2031 HP CIRCUIT THEORY Microprocessor VIA Logic U3J is a VIA Versatile Interface Adapter During a write operation the microprocessor passes the data to be recorded to Port A of U3J The data is loaded into the shift register U3L It is converted from parallel to serial data and output to the write amplifier circuit During a read operation serial data is received from the read amplifier circuit The stepper motor is controlled by two outputs on port B of U3J STPO and STP1 A binary four count is developed from these two lines by U1P
29. hen a write operation occurs the ERASE coil is energized by forward biasing CR11 This demagnetizes ce u z the outer edges of the track preventing data on one track from bleeding into the next track 2 e o z x 2 o Power Up Down Write Protection IP a al de 5 m TW ME ui J gt 50 This circuit prevents erroneous data from being written on the disk during power up down sequences 4 J u During a power up the 12VDC supply is not applied to the R W coils and amplifier circuits before ACO R S the processor has control of the logic During a power down the 12VDC supply is removed from o ge n A the R W coils and amplifier circuits before the processor loses control of the logic E Q3 acts as series pass transistor biased to regulate the 12 output to the R W coils and amplifier 118 circuits Q2 is a feedback amplifier monitoring the 5VDC supply CR17 develops a precise reference ot voltage for Q2 L1 and C45 delay the 12VDC supply r lt 2 2 E 15 DL 33w 2031 HP POWER SUPPLY ASSEMBLY PARTS LIST FUSE HOLDER ROCKER SWITCH POWER CONNECT FILTER FUSE SLOW BLO 250V 5A POWER TRANSFORMER 904507 01 903467 03 903555 15 320939 01 2031 HIGH PROFILE POWER SUPPLY 12031002 01 01 ORANGE 02 YELLOW 03 BROWN PWR CONN FUSE 04 GRAY y o BLUE WHITE CONNECTOR SHIEL
30. microprocessor when selecting these ROMS UB2 is a 2048 x 8 bit RAM UB2 resides at memory locations 0000 07FF This memory is used for processor stack operations general processor housekeeping user program storage and 4 tem porary buffer areas UA4 UB6 UB7 and UB8 decode the addresses output from the processor when selecting RAM UB8 also controls the chip select line of the VIA UCD4 21 2031 LP CIRCUIT THEORY 5 Ld 4 i 4 t be 2 Read Write Control Logic UCD4 is a VIA Versatile Interface Adapter During a write operation the microprocessor passes the data to be recorded to Port A of UCD4 The data is then loaded into 003 which converts the parallel data into serial data The output on pin 9 is input to gate UF5 pin 4 UF5 outputs the serial data on pin 6 at the clock rate determined by the input signal on pin 5 The output clocks the D flip flop UF6 The outputs of UF6 Q and Q drive the write amplifiers During a read operation data from the read amplifiers is applied to the CLR Input of counter The outputs C and D are shaped by the NOR gate UE5 UE5 outputs the serial data on pin 1 then itis converted to parallel data by UD2 The output of UD2 is latched by UC3 The serial bits are counted by when 8 bits have been counted pin 12 goes low UC1 pin 6 goes high and pin 8 goes low indicating byte is ready to be read by the processor UC2 moni
31. osing the front door causes the media clamp mechanism to operate Two operations are performed in the following order a The diskette is centered b The diskette is clamped and retained between the spindle and the hub The spindle and hub rotate at 300 r p m through a closed loop control circuit employing a D C motor tachometer It is important that the relationship between the head and the media is maintained correctly during operation For this purpose a pressure pad is used to hold and press down the media about 12g from the opposite side of the head This head assembly is coupled to a four phase step ping motor which performs the track positioning One step of the stepping motor corresponds to a 1 2 track movement The control circuit on the logic board selects the direction and number of steps to the desired track The Read Write head uses a glass bonded ferrite ceramic head Track to track erasing is accomplish ed by the straddle erase method The surface of the Read Write head is mirror ground to minimize wear of the head and media Also the head is designed in such a way that the maximum signal can be obtained from the media surface The spindle drive motor operates on 12VDC and turns the spindle through a belt drive at 300 revolutions per minute The speed of the drive motor is controlled by a feedback signal from a tachometer which is housed in the drive motor assembly The feedback signal controls a servo amp that supplies
32. so unwanted 1 bits are not added to the actual data The one shot UG3 generates the correct data pulse width so the read write logic circuits can convert it to parallel for processor control 23 2031 LP CIRCUIT THEORY VF i WG WIC pz Write Amplifier Circuits During a write operation 064 must be high This forward biases Q3 and CRY If Q of UF6 pin 9 goes Q8 and CR7 become forward biased passing current flow through R W 1 If goes low 011 and CR10 become forward biased passing current flow through R W 2 When a write operation occurs the ERASE coil is energized by forward biasing Q10 This demagnetizes the outer edges of the track preventing data on one track from bleeding into the next track 24 2031 LP CIRCUIT THEORY SV Power Up Down Write Protection This circuit prevents erroneous data from being written on the disk during power up down sequences During a power up the 12VDC supply is not applied to the R W coils and amplifier circuits before the processor has control of the logic During a power down the 12VDC supply is removed from the R W coils and amplifier circuits before the processor loses control of the logic Q1 acts as a series pass transistor biased to regulate the 12VF output to the R W coils and amplifier circuits Q2 is a feedback amplifier monitoring the 5VDC supply CR5 develops a precise reference voltage for Q2 L7 and C12 del
33. the 12VDC drive current FLASH CODE The 2031 upon power up goes through its own internal diagnostic If an electronic problem is detected it is indicated by a FLASH CODE The LED s will blink a set number of times pause and then flash again until the problem is corrected Number of Flashes B Possible Failure Circuitry associated with these components can also cause the failure code Therefore it should be suspected as the next possible defect CASEWORK ACCESSORY PARTS LIST 2031 LOW PROFILE PLASTIC CASEWORK 2031 TOP CASE IVORY C 1540014 05 1540 41 2031 BOTTOM CASE IVORY C 1540015 00 SHIELD COVER 1540013 01 LED ASSEMBLY 2 lt aan BARA 1540003 01 SELF ADHESIVE FOOT lt shes C 950150 02 POWER esee ssh enema ruens nn nnn 903508 04 USER S MANUAL C 1540042 01 2031 HIGH PROFILE METAL CASEWORK REPLACEMENT CASEWORK FOR METAL UNITS IS NO LONGER AVAILABLE POWER 903501 01 USER S MANUAL
34. tors the parallel out put of UD2 when all 8 bits are 1 the output pin 9 goes low indicating a sync bit has been read 22 2031 LP CIRCUIT THEORY PEAK DETECTOR DIFFERENTIATOR Read Amplifier Circuits When data is recorded on the disk a 1 bit is represented on the disk by a change in direction of magnetic flux caused by a change in direction of current passed through the R W coil in the R W head When a O bit is to be recorded no change in current flow direction occurs causing the direc tion of the magnetic flux to remain the same on the disk R W HEAD R W 1 COM R W 2 ERASE When data is being read from the disk CEMF is induced into the R W coil by the magnetic fields on the disk causing current flow which is detected by the read amplifiers Current flow through the R W coil will forward bias either CR6 or CR11 depending on the direction Q3 and CR9 must be forward biased The first amplifier UH7 senses this current flow from the R W coil on of the inputs and amplifies it L8 L9 L10 L11 and C16 act as a low pass filter suppressing noise on the amplified output UHB is a differential amplifier which amplifies the difference of the two input signals from the filter section is a peak detector The output of will pulse high when a 1 is read This signal is the reconstruction of data recorded The time domain filter times out when a 1 bit has been read

SERVICE MANUAL 2031 DISK DRIVE

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