Texas Instruments ADS61xx User's Manual
Contents
1. Qty Reference Not Part Foot Print Part Number Manufacturer Installed 5 C1 C5 C8 C52 33 uF TANT_B B45196H2336M209 Kemet 54 5 2 9 30 56 10 uF 805 ECJ 2FB0J106K Panasonic C57 3 C3 C6 C31 1 603 ECJ 1VB1A105K Panasonic 43 C4 C7 0 1 uF 603 ECJ 1VB1C104K Panasonic 11 29 32 35 53 55 66 67 70 72 74 C75 C77 C79 C81 C83 C85 87 89 C92 4 C71 C73 C82 C84 10 uF 805 ECJ 2FB1A106K Panasonic 1 C76 18 pF 603 ECJ 1VC1H180J Panasonic 1 C80 0 22 uF 603 ECJ 1VB1A224K Panasonic 1 C86 10 TANT A 491 106 010 2 C90 C91 27 pF 603 GRM1885C2A270JA01D Murata 1 C93 0 01 603 C0603C103K1RACTU Kemet 0 JP1 Not HEADER 2 5 JUMPER2 NO PART installed 5 JP2 JP6 Jumper 1x3 SMT Short pin 5 JUMPER NO PART 1 and 2 with 0 Q 1 JP8 Jumper 1x3 SMT Short 5 JUMPER NO PART 2 and 3 with 0 Q 2 J1 J4 HEADER 4x2 hdr4X2 100ctr 90131 0124 Molex 4 J2 J3 J7 JP7 HMTSW 103 07 G S 240 HDR THVT 1x3 100 M HMTSW 103 07 G S 240 Samtec 1 96 HMTSW 103 07 G S 240 HDR_THVT_1x3_100_M HMTSW 103 07 G S 240 Samtec 1 J5 SMD3P_BRIDGE Short pin smd_bridge_0603 NO PART 1 and 2 with 0 Q J8 J9 J15 SMA SMA THVT 320x320 142 0701 201 Johnson Components 1 J10 CONN QTH 30X2 D A conn QTH 30X2 D A QTH 060 02 F D A Samtec 4 J11 13 J16 J20 RED Banana Jack ST 351A ALLIED ELECTRONICS 2 J12 J2. uie excite censet 26 11 deus ua iit 27 12 Breakout Board Schematic Sheet 28 List of Tables 1 Breakout Board Pin 5 5 ERES E REN EUN EE UR REN 8 2 SV 9 3 Surtace MountdJurmpers ee eiu e S vow e I DULL I LU 9 4 ADS61xx Frequently Used nnne 12 5 Bill of Materials eco kun ME xa E E ER 21 List of Figures SLAU206B September 2007 Revised April 2008 Submit Documentation Feedback User s Guide l UT S SLAU206B September 2007 Revised April 2008 1 Overview This user s guide gives a general overview of the evaluation module EVM and provides a general description of the features and functions to be considered while using this module This manual is applicable to the ADS6122 ADS6123 AD
3. 14 5 2 Coherent Input Frequency 15 6 Physical 16 6 1 PCB Layout eee a 16 6 2 21 6 3 EVM 5 23 5 _ ___ 29 SLAU206B September 2007 Revised 2008 Table of Contents 3 Submit Documentation Feedback 4 5 INSTRUMENTS www ti com List of Figures 1 SPC Interface Screen 10 2 cel Mm 16 3 GOMPOMENT SIGS Mem D 17 4 Ground Plane 18 5 __ _______ _______________ GE FREE 19 6 Bottom Side areas 20 7 EVM Schematic Sheet 1 23 8 EVM Schematic Sheet 2 24 9 EVM Schematic Sheet RUNE clas e RA 25 10
4. 32 31 9 M 34 33 af 36 35 013 38 aZ 9 012 40 39 J2 5 42 41 2 Ter onm a 2 i 48 47 1 e 5 6 9 50 49 7 8 D1 Do d 52 51 9 10 02 54 53 e 1L ee 12 D3 gt gt 56 55 13 14 04 58 57 15 16 05 60 59 17 18 06 19 20 07 e 62 61 21 22 08 e 64 63 23 ee 24 09 66 65 25 ee 26 010 68 67 21 28 011 D7 10 69 4 20 30______ pto 12 71 31 32 013 14 13 9 4 14 4 05 X gt 76 15 5 35 365 Bae 78 77 2 2 138 80 79 2 39 40 D3 82 81 D2 84 83 2 40PIN IDC 7 GND DATA_OUT 90 89 i 92 91 9 2 94 93 5 96 95 9 98 97 100 99 9 5 102 101 5 104 103 2 106 105 108 107 2 110 109 5 2 112 111 5 5 114 113 5 i 116 115 4 5 118 117 2 120 119 5 G2 G1 G4 G3 9 G6 G5 G8 G7 9 Figure 12 Breakout Board Schematic Sheet 6 28 SLAU206B September 2007 Revised April 2008 Submit Documentation Feedback EVALUATION BOARD KIT IMPORTANT NOTICE Texas Instruments TI provides the enclosed product s under the following conditions This evaluation board kit is intended for use for ENGINEERING DEVELOPMENT DEMONSTRATION OR EVALUATION PURPOSES ONLY and is not considered by TI to be a finished end
5. 2s Complement Straight Binary CMOS DDR LVDS Powerdown OFF Powerdown On No Course Gain 3 5 dB Course Gain INT Reference EXT Reference Bit Wise LVDS Only Byte Wise Test Mode None Multiple Options SLAU206B September 2007 Revised April 2008 Submit Documentation Feedback TEXAS INSTRUMENTS www ti com Connecting to FPGA Platforms 4 Connecting to FPGA Platforms The ADS61xx ADS61B23 EVM provides several connection options to mate the EVM to various FPGA development platforms and FPGA based capture boards 41 TSW1100 Using the accompanying CMOS breakout board users can easily mate 5 TSW1100 capture board to the ADS61xx ADS61B23 EVM Simply connect the breakout board to the J2 Channel 2 connector on the TSW1100 From an orientation standpoint the Xilinx FPGA faces the ADC when correctly configured Before using the TSW1100 to capture ADC data for the first time users should update the TSW1100 Supported_ADCs ixt file They should explore the accompanying ADS61xx ADS61B23 software CD replace the installed TSW1100 Supported ADC txt file with the one found on the this file adds TSW1100 support for both the ADS612x and ADS614x Finally users should ensure that the ADC61xxEVM is configured in CMOS output mode In addition the TSW1100 represents a load greater than 5 pF and as such users should consider boosting the CMOS drive strength by using the S
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7. This section covers signal tone analysis which yields ADC data sheet figures of merit such as signal to noise ratio SNR and spurious free dynamic range SFDR Hardware Selection To reveal the true performance of the ADC under evaluation great care should be taken in selecting both the ADC signal source and ADC clocking source Analog Input Signal Generator When choosing the quality of the ADC analog input source consider both harmonic distortion performance of the signal generator and the noise performance of the source In many cases the harmonic distortion performance of the signal generator is inferior to that of the ADC and additional filtering is needed if users expect to reproduce the ADC SFDR numbers found in the data sheet Users can easily evaluate the harmonic distortion of the signal generator by hooking it directly to a spectrum analyzer measuring the power of the output signal and comparing that to the power of the integer multiples of the output signal frequency If the harmonic distortion is worse than the ADC under evaluation the ADC digitizes the performance of the signal generator and the true SFDR of the ADC is masked To alleviate this it is recommended that users provide additional LC filtering after the signal generator output Another important metric when deciding on a signal generator is its noise performance As with the distortion performance if the noise performance is worse than that of the ADC under ev
8. 2 2 6 Jumper Selections The EVM features several jumpers whose functions are described in Table 2 The EVM also features surface mount jumpers in cases where either the signal integrity is important or the functions are rarely used Table 3 summarizes these options 8 SLAU206B September 2007 Revised April 2008 Submit Documentation Feedback 5 INSTRUMENTS www ti com Circuit Description Table 2 Jumpers Description Reference Designator Default Selection Optional Selection Parallel mode SEN pin 5 6 Offset binary CMOS output Multiple choices voltage bias SEN control J2 2 3 EVM controlled 1 2 USB or FPGA controlled ADC control mode J3 2 3 Parallel mode 1 2 serial mode Parallel mode SCLK pin J4 1 2 0 dB Gain Int Ref Multiple choices voltage bias ADS61xx ADS61B23 J5 1 2 ADS61xx ADS61B23 powered on 2 3 ADS61xx ADS61B23 power down powered off SDATA control 96 1 2 USB or FPGA controlled 2 3 EVM controlled SCLK control J7 2 3 EVM controlled 2 3 USB or FPGA controlled Table 3 Surface Mount Jumpers Description Reference Designator Default Selection Optional Selection JP1 Probe point for CDCP1803 output Clock input path selection JP2 1 2 transformer coupled path 2 3 CDCP1803 path Clock input path selection 1 2 transformer coupled path 2 3 CDCP1803 path Clock input path selection JP4 1 2 transformer coupled path 2 3 CDCP1803 pat
9. safety critical applications such as life support where a failure of the TI product would reasonably be expected to cause severe personal injury or death unless officers of the parties have executed an agreement specifically governing such use Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications and acknowledge and agree that they are solely responsible for all legal regulatory and safety related requirements concerning their products and any use of TI products in such safety critical applications notwithstanding any applications related information or support that may be provided by TI Further Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in such safety critical applications TI products are neither designed nor intended for use in military aerospace applications or environments unless the TI products are specifically designated by TI as military grade or enhanced plastic Only products designated by TI as military grade meet military specifications Buyers acknowledge and agree that any such use of TI products which TI has not designated as military grade is solely at the Buyer s risk and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use TI products are neither designed nor intended for use in automotive applications or environments unless the s
10. square wave When selecting a sinusoidal clocking source it has been shown that phase noise has a direct impact on jitter performance Consequently great scrutiny should be applied to the phase noise performance of the clocking signal generator has found that high Q monolithic crystal filters can improve the phase noise of the signal generator and these filters become essential elements of the evaluation setup when high ADC input frequencies are being evaluated SLAU206B September 2007 Revised April 2008 Submit Documentation Feedback 5 INSTRUMENTS www ti com ADC Evaluation 5 2 Coherent Input Frequency Selection Typical ADC analysis requires users to collect the resulting time domain data and perform a Fourier transform to analyze the data in the frequency domain A stipulation of the Fourier transform is that the signal must be continuous time however this is impractical when looking at a finite set of ADC samples usually collected from a logic analyzer Consequently users typically apply a window function to minimize the time domain discontinuities that arise when analyzing a finite set of samples For ADC analysis window functions have their own frequency signatures or lobes that distort both SNR and SFDR measurements of the ADC uses the concept of coherent sampling to work around the use of a window function The central premise of coherent sampling entails that the input signal into the ADC is carefully
11. the USB drivers When prompted users should allow the Windows operating system to search for device drivers and it should automatically find the Tl ADC SPI interface drivers See Figure 1 Note Before plugging in the USB cable for the first time install the ADC SPI software The software installs the drivers necessary for USB communication TI SPI Interface Register Interface 4055525 27 45 45 47 ADSEIX lt ADSEIX Address Byte Data Byte 55 5 Load Script ADS61XX FREQUENTLY USED REGISTERS __2sCOMPLEMENT FINE GAIN LVDS CURRENT CMOS 25 4 5m wocouRsEGAN TEST MODE NONE Figure 1 ADC SPC Interface Screen SLAU206B September 2007 Revised April 2008 Submit Documentation Feedback 1 INSTRUMENTS www ti com ADC SPI Control Interface 3 2 3 3 3 3 1 3 3 2 Setting Up the EVM for ADC SPI Control Users who wish to use the ADC SPI interface must supply 5 VDC to J20 which provides power to the USB circuit By default the EVM comes with the ADC configured in parallel mode In order to use the SPI interface to control the ADC modes of operation users must move several jumpers Move jumper J3 to short positions 1 2 which places the ADC into serial operation mode Move jumper J7 to short positions 1 2 which allows the USB circuit to control SCLK e Move jumper J6
12. to short positions 1 2 which allows the USB circuit to control Move jumper J2 to short positions 1 2 which allows the USB circuit to control SEN Using the ADC SPI Interface Software Once the software is installed and the USB cable is connected three primary modes of operating the software are available Register Writes SPI Register Write Using a Script File and ADS61 xx ADS61B23 Frequently Used Registers SPI Register Writes The most basic mode of operation allows full control of writing to individual register addresses In the top left corner of the interface screen Figure 1 select the ADS61xx ADC from the ADC SPI Protocol drop down list Next type the Address Bytes s in hexadecimal hex and Data Byte s in hex which can be found in the device data sheet When you are ready to send this command to the ADC press Enter on your keyboard The graph indicator is updated with the patterns sent to the ADC The default inputs to both the Address Byte s and Data Byte s fields are hex inputs as designated by the small x in the control Users can change the default input style by clicking on the x to binary decimal octal or hex Multiple register writes can be written simply by changing the contents of the Address Byte s and Data Byte s field and pressing Enter again SPI Register Write Using a Script File For situations where the same multiple registers must be written on a frequent basis users can ea
13. 03 ERJ 3GEYJ103V Panasonic 1 R50 2 21 603 ERJ 3EKF2211V Panasonic 1 R51 47 603 ERJ 3EKF4R71V Panasonic 0 R52 Not 10 kQ 603 ERJ 3EKF1002V Panasonic installed R53 1 5 kQ 603 ERJ 3EKF1501V Panasonic 0 R21 R54 R62 R64 Not 00 603 ERJ 3GEYOROOV Panasonic installed 2 R55 R56 26 7 Q 603 ERJ 3EKF26R7V Panasonic 2 R58 R60 130 0 603 ERJ 3EKF1300V Panasonic 2 59 61 8250 603 ERJ 3EKF82R5V Panasonic 1 R65 00 1206 ERJ S080R00V Panasonic 1 SW1 SW PUSHBUTTON SW RESET PTS635 PTS635SL43 C amp K Switch 3 TP1 TP3 TP6 Test Point Black testpoint 5001 Keystone 3 TP2 5 Test Point White testpoint 5002 Keystone 0 7 9 TESTPOINT 5002 Keystone installed 2 T1 72 TC4 1W XFMR_TC4 1W TC4 1W Mini Circuits 1 T3 1 1 XFMR_TC4 1W TC1 1T Mini Circuits 1 U1 ADS614X QFN32 Tl 1 U2 CDCP1803 mlf_qfn_24 CDCP1803RGET Tl 1 U10 TPS73233 DBV5 TPS73233DBVT Tl 1 U11 THS4509 QFN16 THS4509RGTT TI 1 U13 93 66 TSSOP8 93C66B Microchip 1 U14 FT245BM PQFP32 FT245BM Future Technology Devices 1 Y1 6 0000MHz smd_csm 7_xtal ECS 60 32 5PDN TR ECS 4 MP2 SA machine ph 4 40 x PMS 440 0038 PH Building Fasteners 4 MP3 Stand off hex 5 4 40THR 1902C Keystone Electronic 22 SLAU206B September 2007 Revised April 2008 Submit Documentation Feedback Physical Description X TEXAS INSTRUMENTS www ti com dii D F 66r ASL ASL any JON 6 9 8 0 6
14. 14 BLK Banana Jack ST 351B ALLIED ELECTRONICS 1 J17 CONN USB TYP B FEM conn usb typb fem 897 30 004 90 000 Milmax 5 L1 L3 L8 L9 68 603 MI0603J680R 10 Steward 1 10 1 k at 100 MHz 805 BLM21AG102SN1D Murata 6 R3 R5 R9 R11 1 603 ERJ 3EKF1001V Panasonic R14 5 R6 R10 R15 R18 10 603 ERJ 3EKF1002V Panasonic R35 4 R7 R26 R57 00 603 ERJ 3GEYOROOV Panasonic Ree 8 R8 R12 R13 R17 1000 603 ERJ 3EKF1000V Panasonic R19 R20 R40 R44 1 R16 100 603 ERJ 3EKF10ROV Panasonic 2 R22 R25 2000 603 ERJ 3EKF2000V Panasonic 2 R23 R24 390 603 RC0603FR 0739RL Panasonic 0 R27 R28 Not 1210 603 ERJ 3EKF1210V Panasonic installed 5 R29 R31 R38 4990 603 ERJ 3EKF49R9V Panasonic R46 R47 1 R30 60 4 603 ERJ 3EKF6042V Panasonic 2 R32 R34 100 603 ERJ 3EKF10ROV Panasonic 1 Remove R66 for the ADS61B23 EVM SLAU206B September 2007 Revised April 2008 Submit Documentation Feedback 21 13 TEXAS INSTRUMENTS Physical Description www ti com Table 5 Bill of Materials continued Qty Reference Not Part Foot Print Part Number Manufacturer Installed 0 R33 Not 2000 402 2 2000 Panasonic installed R36 R48 348 0 603 ERJ 3EKF3480V Panasonic R37 R45 Not 499 Q 603 ERJ 3EKF4990V Panasonic installed R39 R43 6980 603 ERJ 3EKF69R8V Panasonic R41 R42 Not 200 Q 603 ERJ 3EKF2000V Panasonic installed 1 R49 10 kQ 6
15. 6 SvH 19 ov JON 002 WHO 0 ZHS 9 0 _ 002 any ii 6 6v sir d NV 5 9 2 31045 3Ineged MOL L OL Seu AS SSA 2 31045 3 whoo Figure 7 EVM Schematic Sheet 1 002 ecu any NIV NI TWNOIS er Z T 31945 3 lt 6 3 EVM Schematics 23 SLAU206B September 2007 Revised April 2008 Submit Documentation Feedback www ti com X TEXAS INSTRUMENTS Physical Description MCN WOS un os E Z 3ungs A 90195 a To SdL gt AL JON WHO 0 HS NAS VOd4 a A Z 3ungg To zal SH 004 00 21 YHS d id W td d YHS YHS d d id YHS HS YHS HS VHS YHS HS HS dino 1o d d ela zia iei 5885885 tc 883888 941 OL x WNI
16. ADS61xx ADS61B23EVM User s Guide TEXAS INSTRUMENTS Literature Number SLAU206B September 2007 Revised April 2008 02068 5 2007 Revised 2008 Submit Documentation Feedback TEXAS INSTRUMENTS Contents 1 OVER 5 1 1 ADS61xx ADS61B23 EVM Quick Start Procedure 5 2 PP 6 2 1 Schematic Diagram eter 6 2 2 ADC Circuit FUNCTION iiss sie ems 6 3 ADC SPI Control Interface nn spam 10 3 1 Installing the ADC SPI Control Software 10 3 2 Setting Up the EVM for ADC SPI 11 3 3 Using the ADC SPI Interface Software nnm nennen 13 4 Connecting to FPGA Platforms Irene oen aee eia ere aus edie aea oan dav ee Russa aae uaa ieu 13 4 1 ES W110 O M 1 4 2 13 5 ADG Eval atiON e 14 5 1 Hardware Selection
17. HS4509 used on this EVM is pinout compatible with the THS4508 54511 54513 and THS4520 Users can easily interchange the amplifier on this EVM and pick the appropriate amplifier based on common mode range power supplies and frequency of operation Contact your local Texas Instruments sales representative for assistance in selection of these amplifiers 2 2 4 ADC Clock Input Connect a filtered low phase noise clock input to 49 A transformer T3 provides the conversion from single ended clock signal into a differential clock signal The EVM also provides a clock distribution path using the CDCP1803 The CDCP1803 provides for a 1 3 LVDS fanout helpful when clocking multiple ADCs from the same clocking source Users selecting this input path should use a low jitter square wave input In addition the CDCP1803 jitter performance makes this a valid clocking solution only for input frequencies in the first Nyquist zone as jitter degrades SNR for frequencies much above the first Nyquist zone To use this path change jumper JP8 to short 1 2 and JP2 and to short pins 2 3 2 2 5 ADC Digital Outputs The ADS61xx ADS61B23 ADC parallel digital outputs are brought to J10 a high density Samtec connector Several options are available in processing the ADC data 1 The mating logic analyzer breakout board can capture the ADC data using a logic analyzer Users who choose this option should use the companion breakout b
18. LHS 89 219 pie LHS anov Xvi9sav 555 290 4 5 5 9 5 WHO 0 5 YHS 9 001 gt gt vivds SHS 2 3ungg Hi 4 1 T1VIH3S OL ord 001 1 5 8H 3ungg AG 32VAH31NI TITIV3Vd OL 9H Submit Documentation Feedback SLAU206B September 2007 Revised April 2008 8 EVM Schematic Sheet 2 igure F 24 9 8 o o o 2 any 629 HS 000K 528 19H dni E WHINE JON 612 A9L any 90 MOL L 748 804 MOL L LoL 424 JON dni 919 X TEXAS INSTRUMENTS www ti com Z I 31045 Z T 31045 Figure 9 EVM Schematic Sheet 3 25 SLAU206B September 2007 Revised April 2008 Submit Documentation Feedback Physical Description SH2 012 013 P 8 2 012 013 SH2 D10_D11_P SH2 010 011 M SH2 SH2 SH2 SH2
19. Microsoft Corporation Samtec is a trademark of Samtec Inc Xilinx Virtex are trademarks of Xilinx Inc All other trademarks are the property of their respective owners SLAU206B September 2007 Revised April 2008 5 Submit Documentation Feedback 5 INSTRUMENTS Circuit Description www ti com 2 2 1 2 2 2 2 1 2 2 2 2 2 3 Circuit Description Schematic Diagram The schematic diagram for the EVM is in Section 6 3 ADC Circuit Function The following sections describe the function of individual circuits See the relevant data sheet for device operating characteristics ADC Operational Mode By default the ADC is configured to operate in parallel mode operation because jumper J3 asserts a 3 3 V state to the ADC reset pin Consequently the SW1 reset pushbutton must be pressed only when the device is configured in serial operation mode Because the ADC is in parallel operation mode voltages are used to set the ADC configuration modes Users can use the EVM silkscreen to set the operation modes EVM Power Connections Power is supplied to the EVM by banana jack sockets Separate connections are provided for a 3 3 V digital buffer supply J11 and 3 3 V analog supply J13 however by default these are shorted together using R65 0 0 resistor Consequently users can supply power to either J11 J13 to power the ADC The separate connections allow users to separate analog and digital supplies
20. PI Control software In many cases the boosting of the drive strength is not required to perform valid data captures when using the TSW1100 this is an optional step 42 TSW1200 The ADS61xx ADS61B23 natively plugs into the TSW1200 FPGA platform In most circumstances the TSW1200 functions as deserializer However the Virtex 4 FPGA can be reprogrammed to allow ultimate in flexible solution prototyping For users wishing to apply FPGA control over the ADS61 xx ADS61B23 SPI interface move the surface mount jumpers into the following positions e Move the jumper J2 SEN to the 1 2 position and remove R7 and populate R62 with a 0 Q resistor Move the jumper J7 SCLK to the 1 2 position and remove R20 while installing the 0 Q resistor to R63 e Move the jumper on J6 SDATA to the 1 2 position and remove R19 while installing the 0 Q resistor to R64 e Remove R18 Move the jumper on J3 to position 1 2 to configure the ADC into the SPI operation mode serial interface mode SLAU206B September 2007 Revised April 2008 13 Submit Documentation Feedback 5 INSTRUMENTS ADC Evaluation www ti com 5 5 1 ADC Evaluation This section describes how to set up a typical ADC evaluation system that is similar to what uses to perform testing for data sheet generation Consequently the information in this section is generic in nature and is applicable to all high speed high resolution ADC evaluations
21. S6124 ADS6125 ADS6142 ADS6143 ADS6144 ADS6145 and ADS61B23 which collectively are referred to as ADS61xx and ADS61B23 The ADS61xx ADS61B23 EVM provides a platform for evaluating the low power single channel ADS61xx ADS61B23 12 and 14 bit analog to digital converters ADC and the ADS61B23 12 bit ADC with buffered analog input under various signal reference and supply conditions This document should be used in combination with the respective ADC data sheet 1 1 ADS61xx ADS61B23 EVM Quick Start Procedure Using the quick start procedure many users can begin evaluating the ADC in a short time The quick start procedure uses the default conditions of the EVM as shipped from the factory In addition the quick start guide configures the ADC in a CMOS offset binary data format Users who have modified the board may find the quick start procedure to be ineffective 1 Supply 3 3 V to J11 while connecting the return to a shorted J11 and J14 Power on the device Confirm jumper 6 is shorted 1 2 and jumpers J2 J3 and J7 have positions 2 3 shorted Use the silkscreen to confirm jumper J1 is set to Offset Binary CMOS output Use the silkscreen to confirm jumper J4 is set to OdB Gain Int Ref Supply a 1 dBFS filtered low phase noise 10 MHz CW tone into J8 Supply a filtered low phase noise clock to 9 Use the accompanying breakout board and monitor the digital output see Table 1 NOOR WN Windows is a registered trademark of
22. SH3 SH3 SH2 SH2 SH2 SH2 SH2 SH2 SH2 SH2 26 D8 D9 P D8 D9 M CLKOUTP CLKOUTM 06 07 P 06 D7 M D4 D5 P D4 D5 M D2 D3 P D2 D3 M DO D1 P DO Di M TEXAS INSTRUMENTS www ti com FPGA SDATA SH2 FPGA SEN SH2 FPGA SCLK SH2 CONN QTH 30X2 D A Figure 10 EVM Schematic Sheet 4 SLAU206B September 2007 Revised April 2008 Submit Documentation Feedback X TEXAS INSTRUMENTS www ti com Physical Description 999 990 AQL AQL any 999 A 99 55 EEZELSdL any 49 NI WAG e VAE E any NI GAG e E NI OAE Figure 11 EVM Schematic Sheet 5 m angg 290 AS AS oer 27 SLAU206B September 2007 Revised April 2008 Submit Documentation Feedback 5 INSTRUMENTS Physical Description www ti com CONN_QSH_30X2 D A 2 1 4 3 J 6 41 5 9 8 1 9 10 9 12 11 2 14 13 16 15 4 18 17 5 20 19 9 22 21 24 23 26 25 28 21 9 30 29
23. aluation the ADC digitizes the performance of the source Noise can be broken into two components broadband noise and close in phase noise Broadband noise can be improved by the LC filter added to improve distortion performance however the close in phase noise typically cannot be improved by additional filtering Therefore when selecting an analog signal source it is important to review the manufacturer s phase noise plots and take care to choose a signal generator with the best phase noise performance Clock Signal Generator Equally important in the high performance ADC evaluation setup is the selection of the clocking source Most modern ADCs the ADS61xx ADS61 B23 included accept either a sinusoidal or a square wave clock input The key metric in selecting a clocking source is selecting a source with the lowest jitter This becomes increasingly important as the ADC input frequency fin increases because the ADC SNR evaluation setups can become jitter limited t as shown by the following equation SNR dBc 20 log 2x x fin x t rms In theory a square wave source with femtosecond jitter would be ideal for an ADC evaluation setup However in practical terms most commercially available square wave generators offer jitter measured in picoseconds which is too great for high resolution ADC evaluation setups Therefore most evaluation setups rely on the ADC internal clock buffer to convert a sinusoidal input signal into a ultralow jitter
24. by removing R65 When using the amplifier evaluation path connect the positive rail to J20 and the negative rail to J16 The voltages depend on the coupling method and connection to the ADC If the ADC is not supplied to the amplifier and the amplifier is connected to the ADC in a dc coupled fashion set J20 to 4 V and J16 to 1 V In ac coupled configurations where the ADC biases the ADC inputs connect J20 to 5 V and J16 to GND The ADC SPI interface and CDCP1803 also are powered through J20 which should be set to 5 V for operation of those circuits ADC Analog Inputs The EVM is configured to accept a single ended input source and convert it to an ac coupled differential signal using a transformer The inputs to the ADC must be dc biased which is accomplished by using the ADC VCM output The input is provided by the SMA connector J8 Using SMA input J10 users can evaluate the ADC using a THS4509 amplifier which converts a single ended input into a differential signal while providing 10 dB of signal gain Users should enable the amplifier path by connecting JP7 1 2 and by shorting positions 2 3 on both surface mount jumpers JP5 and JP6 At low input frequencies the ADC represents high input impedance and R38 R46 and C76 form a low pass filter with a 3 db cutoff frequency of 70 MHz Users can change these component values depending on the bandwidth of the signal they are digitizing to band limit the input noise into the ADC U
25. chosen such that when a continuous time signal is reconstructed from a finite sample set no time domain discontinuities exist To achieve this the input frequency must be an integer multiple of the ratio of the ADC sample rate f and the number of samples collected from the logic analyzer N The ratio of f to N is typically referred to as the fundamental frequency f Determining the ADC input frequency is a two step process First the users select the frequency of interest for evaluating the ADC then they divide this by the fundamental frequency This typically yields a non integer value which should be rounded to the nearest odd preferably prime integer Once that integer or frequency bin fbin has been determined users multiply this with the fundamental frequency to obtain a coherent frequency to program into their ADC input signal generator The procedure is summarized as follows fbin Odd_round fuesirea fr Coherent frequency f x fbin SLAU206B September 2007 Revised April 2008 15 Submit Documentation Feedback Physical Description 6 6 1 Physical Description This section describes the physical characteristics and PCB layout of the EVM PCB Layout The EVM is constructed on a four layer 0 062 inch thick PCB using FR 4 material The individual layers are shown in Figure 2 through Figure 6 The layout features a split ground plane however similar performance can be obtained with careful layout u
26. h Analog input path JP5 1 2 transformer coupled input path 2 3 THS4509 path Analog input path JP6 1 2 transformer coupled input path 2 3 THS4509 path THS4509 power down JP7 2 3 THS4509 powered down 1 2 THS4509 powered on CDCP1803 power down JP8 2 3 CDCP1803 powered down 1 2 CDCP1803 powered on SLAU206B September 2007 Revised April 2008 Submit Documentation Feedback 5 INSTRUMENTS www ti com ADC SPI Control Interface 3 3 1 TI ADC SPI Control Interface This section describes the software features accompanying the EVM kit The ADC SPI control software provides full control of the SPI interface allowing users to write to any of the ADC registers found in the ADC data sheet For most ADS61xx ADS61 B23 performance evaluations users do not need to use the SPI control software to get evaluation results Users only need to use the ADC SPI control software when the desired feature is inaccessible because the ADC is in parallel interface mode Installing the ADC SPI Control Software The ADC SPI control software can be installed on a personal computer by running the setup exe file located on the CD This file installs the graphical user interface GUI along with the USB drivers needed to communicate to the USB port that resides on the EVM After the software is installed and the USB cable has been plugged in for the first time the user is prompted to complete the installation of
27. lacing measurement probes near these devices during operation please be aware that these devices may be very warm to the touch Mailing Address Texas Instruments Post Office Box 655308 Dallas Texas 75265 Copyright 2007 2008 Texas Instruments Incorporated IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries reserve the right to make corrections modifications enhancements improvements and other changes to its products and services at any time and to discontinue any product or service without notice Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete All products are sold subject to Tl s terms and conditions of sale supplied at the time of order acknowledgment TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with Tl s standard warranty Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty Except where mandated by government requirements testing of all parameters of each product is not necessarily performed TI assumes no liability for applications assistance or customer product design Customers are responsible for their products and applications using Tl components To minimize the risks associated with customer products and applications customers should provide adequate design and operating safeguards
28. oard and Table 1 for the connection details Users lacking access to a logic analyzer can use the TSW1100 to capture the digital data See the connection guidelines in Section 4 1 2 Users can create their own digital interface board which directly interfaces to the ADC In this case they design their mating digital interface board with the Samtec part number QSO 060 01 F D A which is the companion part number to the EVM connector SLAU206B September 2007 Revised April 2008 7 Submit Documentation Feedback 5 INSTRUMENTS Circuit Description www ti com Table 1 Breakout Board Pin Assignments J4 PIN 25 ADS6142 43 44 45 DESCRIPTION 1 GND GND 2 CLK CLK 3 GND GND 4 NC NC 5 GND GND 6 NC Data bit 0 LSB 7 GND GND 8 NC Data bit 1 9 GND GND 10 Data bit 0 LSB Data bit 2 11 GND GND 12 Data bit 1 Data bit 3 13 GND GND 14 Data bit 2 Data bit 4 15 GND GND 16 Data bit 3 Data bit 5 17 GND GND 18 Data bit 4 Data bit 6 19 GND GND 20 Data bit 5 Data bit 7 21 GND GND 22 Data bit 6 Data bit 8 23 GND GND 24 Data bit 7 Data bit 9 25 GND GND 26 Data bit 8 Data bit 10 27 GND GND 28 Data bit 9 Data bit 11 29 GND GND 30 Data bit 10 Data bit 12 31 GND GND 32 Data bit 11 MSB Data bit 13 MSB 33 GND GND 34 NC NC 35 GND GND 36 NC NC 37 GND GND 38 NC NC 39 GND GND 40 NC NC
29. onable protection against radio frequency interference Operation of this equipment in other environments may cause interference with radio communications in which case the user at his own expense will be required to take whatever measures may be required to correct this interference EVM WARNINGS AND RESTRICTIONS It is important to operate this EVM within the input voltage range of 0 3 V to 3 6 V and the output voltage range of 0 3 V to 3 6 V Exceeding the specified input range may cause unexpected operation and or irreversible damage to the EVM If there are questions concerning the input range please contact a field representative prior to connecting the input power Applying loads outside of the specified output range may result in unintended operation and or possible permanent damage to the EVM Please consult the EVM User s Guide prior to connecting any load to the EVM output If there is uncertainty as to the load specification please contact a TI field representative During normal operation some circuit components may have case temperatures greater than 50 The is designed to operate properly with certain components above 25 as long as the input and output ranges are maintained These components include but are not limited to linear regulators switching transistors pass transistors and current sense resistors These types of devices can be identified using the EVM schematic located in the EVM User s Guide When p
30. pecific products are designated by as compliant with ISO TS 16949 requirements Buyers acknowledge and agree that if they use any non designated products in automotive applications TI will not be responsible for any failure to meet such requirements Following are URLs where you can obtain information on other Texas Instruments products and application solutions Products Applications Amplifiers amplifier ti com Audio www ti com audio Data Converters dataconverter ti com Automotive www ti com automotive DSP dsp ti com Broadband www ti com broadband Clocks and Timers www ti com clocks Digital Control www ti com digitalcontrol Interface interface ti com Medical www ti com medical Logic logic ti com Military www ti com military Power Mgmt power ti com Optical Networking www ti com opticalnetwork Microcontrollers microcontroller ti com Security www ti com security RFID www ti rfid com Telephony www ti com telephony and ZigBee Solutions www ti com Iprf Video amp Imaging www ti com video Wireless www ti com wireless Mailing Address Texas Instruments Post Office Box 655303 Dallas Texas 75265 Copyright 2008 Texas Instruments Incorporated
31. product fit for general consumer use Persons handling the product s must have electronics training and observe good engineering practice standards As such the goods being provided are not intended to be complete in terms of required design marketing and or manufacturing related protective considerations including product safety and environmental measures typically found in end products that incorporate such semiconductor components or circuit boards This evaluation board kit does not fall within the scope of the European Union directives regarding electromagnetic compatibility restricted substances RoHS recycling WEEE FCC CE or UL and therefore may not meet the technical requirements of these directives or other related directives Should this evaluation board kit not meet the specifications indicated in the User s Guide the board kit may be returned within 30 days from the date of delivery for full refund THE FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY SELLER TO BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES EXPRESSED IMPLIED OR STATUTORY INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE The user assumes all responsibility and liability for proper and safe handling of the goods Further the user indemnifies TI from all claims arising from the handling or use of the goods Due to the open construction of the product it is the user s responsibility to take any and all appropriate precautions wi
32. sily use a text editor to create a script file containing all ADC register writes An example script file is located in the Wnstall Directory Script Files ADS6145 LVDS CourseGain txt Users who wish to take advantage of writing their own script files should start by using the ADS6145 LVDS CourseGain txt as a template file When ready to write the contents of the script file to the ADC users can press the Load Script button and they will be prompted for the file location of their script file The commands are sent to the ADC when the user acknowledges the selection of the file 3 3 21 ADS61xx Frequently Used Registers For ease of use several buttons have been added that allow one click register writes of commonly used features found in Table 4 These are found in the ADS61xx tab as these commands are specific to the ADS61xx ADC only The software writes to the ADC both the contents of the associated address and data when the button is clicked When the ADS61xx Reset button is pressed it issues a software reset to the ADC and it resets the button values to match the contents inside of the ADC The graph indicator plots the SPI commands written to the ADC when a button has been depressed SLAU206B September 2007 Revised April 2008 11 Submit Documentation Feedback ADC SPI Control Interface 12 TEXAS INSTRUMENTS www ti com Table 4 ADS61xx Frequently Used Registers Default Value Alternate Value ADS61xx Reset
33. sing a common ground plane TEXAS INSTRUMENTS www ti com 3 34 COARSE enpr INT RE 3 548 COARSE EXT faloa GAIN REF gt es ry T L lt ign T vu alse GAIN INT REF FPS xe Figure 2 Top Silkscreen 1 eoe J10 DATA OUT CaN 120 SLAU206B September 2007 Revised April 2008 Submit Documentation Feedback 5 INSTRUMENTS www ti com Physical Description Figure 3 Component Side SLAU206B September 2007 Revised April 2008 17 Submit Documentation Feedback 18 Physical Description TEXAS INSTRUMENTS www ti com SX 00000000 OO OO 00000 00000000 e 0 0 0 0 0 0 Figure 4 Ground Plane 1 SLAU206B September 2007 Revised April 2008 Submit Documentation Feedback 5 INSTRUMENTS www ti com Physical Description SX 00000000 OO OO 00000 00000000 e 0 0 0 0 0 0 Figure 5 Power Plane 1 SLAU206B September 2007 Revised April 2008 19 Submit Documentation Feedback 5 INSTRUMENTS Physical Description www ti com 9000000990000 Figure 6 Bottom Side 20 SLAU206B September 2007 Revised April 2008 Submit Documentation Feedback l TEXAS INSTRUMENTS www ti com 6 2 Bill of Materials Table 5 Bill of Materials Physical Description
34. sing an excessively high cutoff frequency degrades the SNR of the system Before beginning evaluation of the amplifier path a user must choose whether to dc couple or ac couple the amplifier path In dc coupled system replace C75 and C77 with 0 Q resistors and remove R37 and R45 Use the ADC to set the CM input of the amplifier by ensuring that R21 is populated with a 0 Q resistor Because the ADC has a common mode voltage of 1 5 V and because the THS4509 is not a rail to rail amplifier adjust VCC to 4 and to 1 V which can be done by applying the respective voltages to J20 and J16 For an ac coupled system use the voltage divider R37 and R45 to set the common mode input of the amplifier which should be set to the midpoint of the amplifier supply Alternatively users can leave R37 and R45 unpopulated and the amplifier sets its own common voltage to VCC VEE 2 Capacitors C75 and C77 provide ac coupling of the system and the ADC inputs then can be biased by the R41 and R42 combination Another ac coupled approach not supported on this EVM is to use a transformer at the outputs of the THS4509 In this case the transformer provides for ac coupling and the inputs of the ADC be biased by feeding the ADC VCM to the transformer center tap on the secondary SLAU206B September 2007 Revised April 2008 Submit Documentation Feedback 5 INSTRUMENTS www ti com Circuit Description Note that the T
35. th regard to electrostatic discharge EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR ANY INDIRECT SPECIAL INCIDENTAL OR CONSEQUENTIAL DAMAGES TI currently deals with a variety of customers for products and therefore our arrangement with the user is not exclusive TI assumes no liability for applications assistance customer product design software performance or infringement of patents or services described herein Please read the User s Guide and specifically the Warnings and Restrictions notice in the User s Guide prior to handling the product This notice contains important safety information about temperatures and voltages For additional information on 5 environmental and or safety programs please contact the TI application engineer or visit www ti com esh No license is granted under any patent right or other intellectual property right of TI covering or relating to any machine process or combination in which such TI products or services might be or are used FCC Warning This evaluation board kit is intended for use for ENGINEERING DEVELOPMENT DEMONSTRATION OR EVALUATION PURPOSES ONLY and is not considered by TI to be a finished end product fit for general consumer use It generates uses and can radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to part 15 of FCC rules which are designed to provide reas
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