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ST & T UPSD3212C User's Manual

1. DATA BUS 4 8 bit PWMO PWM3 CPU rd wr Data Registers 4 load 8 bit PWM0 PWM3 4 Comparators Registers 4 4 3 Port4 4 16 bit Prescaler 8 bit 7 H 4 5 CPU rd wr p Register Comparators 4 Port4 6 B2h B1h 1 PWMCON bit7 PWML 8 bit Counte fosc 2 PWMCON 645 PWME 106647 68 163 uPSD3212A uPSD3212C uPSD3212CV Table 49 PWM SFR Memory Map SFR Bit NEN Name Reset Comment Addr 99 5 PWM PWMCON PWML PWMP PWME CFG4 CFG3 CFG2 CFG1 Control Polarity PWMO A2 PWMO Output Duty Cycle PWM1 PWM1 Output Duty Cycle PWM2 A4 PWM2 Output Duty Cycle PWM3 PWM3 Output DE Cycle 4 ESSE Prescaler 0 Low 8 bit BE deeds 2 Prescaler 1 PWMCON Register Definition PWML PWM 0 3 polarity control CFG3 CFG0 PWM 0 3 Output 0 Open PWMP PWM 4 polarity control Drain 1 Push Pull PWM enable 0 disabled 1 CFG4 4 Output 0 Open Drain 1 enabled Push Pull 69 163 uPSD3212A uPSD3212C uPSD3212CV Programmable Period 8 bit PWM The PWM 4 channel can be programmed to pro PWM pulse width time while vide a PWM output with variable pulse width a
2. 65 PULSE WIDTH MODULATION 67 4 channel PWM Unit PWM 0 3 67 Programmable Period 8 bit 70 PWM 4 Channel 71 FGINTERFACE Mem 72 Serial Status Register S2STA 74 Data Shift Register 52 74 Address Register 652 75 USB HARDWARE eR eles een Ex eae ee da au pu sns x 76 USB related registers eR est nace aa gee 76 TranscelVer e ex e RM h an Sa ek 83 Receiver 85 External USB Pull Up 86 PSD ese bere ROS 88 Functional 88 4 163 uPSD3212A uPSD3212C uPSD3212CV In System Programming 90 DEVELOPMENT SYSTEM Ru a dene a
3. V 1HOd ST139OHOVN LNdLNO 91 1808 OL SO 1 3 SualSIS3t TOYLNOS SWILNNY 5103135 Wvus AYALLVE LIS59L 194135 Wvus 5103135 224 AALSA LW NYW 301935 SHOLOAS 2 uo 1008 AHONSIN SHOLOAS 8 HSV14 LIJAZLS 3158193 1 Lad 0 19 SIU sna SLV 0V sng 2208 107431 89 163 uPSD3212A uPSD3212C uPSD3212CV In System Programming ISP Using the JTAG signals on Port C the entire PSD MODULE device can be programmed or erased without the use of the MCU The primary Flash memory can also be programmed in system by the MCU executing the programming algorithms out of the secondary memory or SRAM The sec ondary memory can be programmed the same way by executing out of the primary Flash memo ry The PLD or other PSD MODULE Configuration blocks can be programmed through the JTAG port or a device programmer Table 80 indicates which programming methods can program different func tional blocks of the PSD MODULE Table 80 Methods of Programming Different Functional Blo
4. Timer 0 Interrupt priority level PTO External Interrupt IntO priority level DP External Interrupt Int1 priority level 0 37 163 uPSD3212A uPSD3212C uPSD3212CV Table 23 Description of the IPA Bits T NEN x s wa _ _ _ _ 2nd USART Interrupt priority level 2 Interrupt priority level PUSB USB Interrupt priority level How Interrupts are Handled The interrupt flags are sampled at S5P2 of every machine cycle The samples are polled during fol lowing machine cycle If one of the flags was in a set condition at S5P2 of the preceding cycle the polling cycle will find it and the interrupt system will generate an LCALL to the appropriate service rou tine provided this H W generated LCALL is not blocked by any of the following conditions Aninterrupt of equal priority or higher priority level is already in progress Thecurrent machine cycle is no in the executio instructiog i access to the interrupt priority or interrupt enable registers The polling cycle is repeated with each machine cycle and the values polled are the values that were present at S5P2 of the previous machine cy cle Note If an interrupt flag is active but being re sponded to for one of the above mentioned condi tions if the flag is still inactive when the blocking condition is removed the denied interrup
5. tLLWL tRLRH gt l RD tRHDZ tAVLL 4 tRLDV gt tLLAX2 tRLAZ PORT 2 P2 0 to P2 3 or A8 A11 from DPH A8 A11 from PCH 07088 Table 118 External Clock Drive with the MCU Module Variable Oscillator 40MHz Oscillator 1 tcLcL 24 to 40MHz Max Note 1 Conditions in addition to those in Table 109 page 133 Vcc 4 5 to 5 5V Vss for Port 0 ALE and PSEN output is 100pF for other outputs is 80pF Table 119 External Clock Drive with the 3V MCU Module Variable Oscillator 24MHz Oscillator Symbol 1 1 tcLcL 8 to 24MHz tRLRH Oscillator period Note 1 Conditions in addition to those in Table 110 page 133 Vcc 3 0 to 3 6V Vss for Port 0 ALE and PSEN output is 100pF for devices and 50pF for devices C for other outputs is 80pF for 5V devices and 50pF for devices 142 163 uPSD3212A uPSD3212C uPSD3212CV Figure 73 External Data Memory WRITE Cycle ALE EH gt tWHLH PSEN N 4 tWLWH gt PORT 0 INSTR IN PORT 2 A8 A11 from PCH AI07089 Variable Oscillator Symbol Parameter 1 tcLcL 24 to 40MHz tRLRH RD pulse width ns aaa a DIA IS COMPAR gt NE tWLWH d s tRHDZ Data float after RD ns Address to valid data
6. 20 NUN digest ves Low Reset 0 1V hysteresis 23 2 27 XTAL Open Bias Voltage Vcc min for Flash Erase SRAM PSD Data Retention Logic 0 Input Current 0 45 1 2 3 4 0 4 2 1 20 HA 138 163 nm rm N lt uPSD3212A uPSD3212C uPSD3212CV Test Condition in addition to those in Table 110 page 133 Parameter Logic 1 10 0 Transition Current VIN 3 5 Ports 1 2 3 4 2 5V for Port 4 pin 21 ITL SRAM PSD Standby Current SRAM PSD Idle Current IDLE Vstey input Vcc VsrBY 0 1 10 20 XTAL Feedback Resistor XTAL1 Vcc FB Current XTAL1 XTAL2 Vss Input Leakage Current Vss lt VIN lt Vcc 1 0 45 lt Vout lt Vcc 10 Vcc 3 6V LVD logic disabled LVD logic enabled Active 12MHz Vcc 3 6V 235 Idle 12MHz 7 24 2 gt EN Hj PLD TURBO On Operating Supply Current During Flash memory WRITE Erase Only Read only f 0MHz f 0MHz Note 1 Ipp Power down Mode is measured with 2 XTAL1 Vss XTAL2 not connected RESET Vcc Port 0 Vcc all other pins are disconnected PLD not in Turbo mode 3 Icc_cPu active mode is measured with 4 XTAL1 driven with tci cH t
7. 2 ua c uama mam lt EXTERNAL CHIP SELECTS PORT D com 2 2 PORT D 5 07435 Note 1 Ports is not available in the 52 package 107 163 uPSD3212A uPSD3212C uPSD3212CV Decode PLD DPLD The DPLD shown in Figure 55 is used for decod ing the address for PSD MODULE and external components The DPLD can be used to generate the following decode signals 4 Sector Select FSO FS3 signals for the primary Flash memory three product terms each Figure 55 DPLD Logic Array INPUTS 1 0 PORTS PORT A B C 20 MCELLAB FB 7 0 FEEDBACKS 8 MCELLBC FB 7 0 FEEDBACKS 8 PGRO PGR7 15 012 6 PD 2 1 2 OUTPUT PSEN RD WR ALE2 2 RD BSY Note 1 Port A inputs are not available in the 52 pin package 2 Inputs from the MCU module 108 163 2 Sector Select CSBOOTO CSBOOT 1 signals for the secondary Flash memory three product terms each 1 internal SRAM Select 50 signal two product terms 1 internal CSIOP Select signal selects the PSD MODULE registers 2 internal Peripheral Select signals Peripheral Mode CSBOOTO CSBOOT 1 gt FSO 3 FS1 4 PRIMARY FLASH MEMORY SECTOR 7 52 SELECTS FS3 ST
8. Nous we owe e wmmua _ 144 163 uPSD3212A uPSD3212C uPSD3212CV Figure 74 Input to Output Disable Enable INPUT INPUT TO OUTPUT ENABLE DISABLE 02863 Conditions Max 42 CPLD Input Pin Feedback to CPLD Combinatorial Output 20 d ns erre T eef erme eere C E Pulse Width NAN DA C Note 1 Fast Slew Rate output available PD2 PD1 Decrement times by given amount 2 tpp for MCU address and control signals refers to delay from pins on Port 0 Port 2 RD WR and ALE to CPLD combinatorial output 80 pin package only Table 124 CPLD Combinatorial Timing 3V Devices Turbo Slew Parameter Conditions Aloc Off rate CPLD Input Pin Feedback to CPLD Combinatorial Output CPLD Register Clear or Preset Delay CPLD Register Clear or Preset Pulse Width CPLD Array Delay Any macrocell Note 1 Fast Slew Rate output available and PD2 PD1 Decrement times by given amount CPLD Input to CPLD Output Disable 2 tpp for MCU address and control signals refers to delay from pins on Port 0 Port 2 RD WR PSEN and ALE to CPLD combinatorial output 80 pin package onl
9. 8 tISCCH tISCCL Clock TCK PC1 Low Time except for PLD tisccFP Clock TCK PC1 Frequency PLD only tisccHP Clock TCK PC1 High Time PLD only Clock PC1 Low Time PLD only Note 1 For non PLD Programming Erase or in ISC By pass Mode 2 For Program or Erase PLD only 154 163 uPSD3212A uPSD3212C uPSD3212CV Table 142 ISC Timing 3V Devices Symbol Parameter Conditions tisccF Clock TCK PC1 Frequency except for PLD tisccH Clock TCK PC1 High Time except for PLD Note 1 tisccL Clock TCK PC1 Low Time except for PLD Note 1 tisccrP Clock TCK PC1 Frequency PLD only tisccHP Clock TCK PC1 High Time PLD only Clock PC1 Low Time PLD only Note 1 For non PLD Programming Erase or in ISC By pass Mode 2 For Program or Erase PLD only Figure 83 Module AC Measurement Waveform Points 106650 Note AC inputs during testing are driven at 0 5 for logic 1 and 0 45V for a logic 0 Timing measurements are made at for a logic 1 and max for a logic 0 Figure 84 PSD MODULE AC Float I O Waveform VLOAD 0 1V 0 1V Reference Points VLOAD 0 1V VoL 0 1V 0 2 Vcc 0 1V 106651 Note For timing purposes Port is considered to be no longer floating when 100mV change from load voltage oc
10. INLNH PO INLNH Power On Reset Warm Reset RESET 107437 Table 137 Reset Timing 5 Devices Symbol Parameter Conditions Unit tNLNH RESET Active Low Time 150 Note 1 Reset RESET does not reset Flash memory Program or Erase cycles Table 138 Reset RESET Timing 3V Devices Symbol Parameter Conditions Unit tNLNH RESET Active Low Tim Um 300 hes C S Le dde i RESET High to Operational Device Note 1 Reset RESET does not reset Flash memory Program or Erase cycles Table 139 Definitions Timing BV Devices Symbol Parameter Conditions Typ Unit tBVBH Detection to Output High Note 1 20 us V Off Detection to V Output Note 1 timing is measured at Vcc ramp rate of 2ms Table 140 VsrByoN Timing Devices Symbol Parameter Conditions Typ Unit tBVBH Detection to Output High Note 1 20 us V Off Detection to V Output Note 1 timing is measured at Vcc ramp rate of 2ms 572 153 163 uPSD3212A uPSD3212C uPSD3212CV Figure 82 ISC Timing lisccH tisccL TDI TMS ISC OUTPUTS TDO ISC OUTPUTS TDO Table 141 ISC Timing 5V Devices Symbol Parameter tiscpsu tiscPH tiscpzv tiscpco gt INK tiscpvz _ A 102865 Conditions
11. PASS 101369 Data Toggle Checking Toggle DQ6 is a method of determining whether a Pro gram or Erase cycle is in progress or has complet ed Figure 49 shows the Data Toggle algorithm When the MCU issues a Program instruction the embedded algorithm begins The MCU then reads the location of the byte to be programmed in Flash memory to check status The Toggle Flag Bit 006 this location toggles each time the MCU reads this location until the embedded algorithm is complete The MCU continues to read this loca tion checking the Toggle Flag Bit DQ6 and mon itoring the Error Flag Bit DQ5 When the Toggle Flag Bit DQ6 stops toggling two consecutive reads yield the same value and the Error Flag Bit DQ5 remains 0 the embedded algorithm is complete If the Error Flag DQ5 is 1 the MCU should test the Toggle Flag Bit DQ6 again since the Toggle Flag Bit DQ6 may have changed simultaneously with the Error Flag Bit DQ5 see Figure 49 The Error Flag Bit DQ5 is set if either an internal time out occurred while the embedded algorithm attempted to program the byte or if the MCU at tempted to program 1 to a bit that was erased not erased is logic 07 It is suggested as with all Flash memories to read the location again after the embedded ming algorithm Aa completed byte that was byte that was When using Data Togg
12. for Port 0 ALE and PSEN output is 100pF C for other outputs is 80pF 2 Interfacing the uPSD321x Devices to devices with float times up to 20ns is permissible This limited bus contention does not cause any damage to Port 0 drivers 140 163 uPSD3212A uPSD3212C uPSD3212CV Table 117 External Program Memory AC Characteristics with the 3V MCU Module Variable Oscillator 24MHz Oscillator 1 tcLcL 8 to 24MHz Symbol Parameter tLHLL ALE pulse width 2tcLcL 40 ns wasa L z p e Input instruction hold after PSEN __ Input instruction float after PSEN 32 _____ Bec 6 Note 1 Conditions in addition to those Table 110 page 133 Vcc 3 0 to 3 6V Vss for Port 0 ALE and PSEN output is 100pF for devices and 50pF for devices C for other outputs is 80pF for 5V devices and 50pF for devices 2 Interfacing the uPSD321x Devices to devices with float times up to 35ns is permissible This limited bus contention does not cause any damage to Port 0 drivers ww C com ST 141 163 uPSD3212A uPSD3212C uPSD3212CV Figure 72 External Data Memory READ Cycle ALE EHE gt tWHLH PSEN 4 tLLDV
13. 2 2 22 2 Relative Offset hp oe lee ences dled eee eee Jump Instructions rr m ee eee Machine WAN a uPSD3200 HAR E MCU MODULE DISCRIPTION 28 Special Function Registers 28 INTERRUPT SYSTEM hunai aaa a mx ru EE RM 34 External IMO eerie rel de nad ee dome sas Ner 34 TimerQ and 1 Interrupts x ry rfr sm 34 Timer2 kk es 34 C ERIT TEE ETT E TTE TT TTL 34 ee 34 USB interrupt locis sr i TE TERR 34 USART Interrupt 22 2 cr e i rf Ee ace IG dere uper 36 Interrupt Priority Structure rr eG oe eee 36 Interrupts Enable Structure 36 How Interrupts are 38 POWER SAVING 39 DIEA DICE 39 Power Down Mode 2 2 2 39 Power Control
14. NN ECAN NEEXETX I NEEEMU General Oportpin port pin UART Transmit Interrupt 0 input Timer 0 gate Interrupt 1 input Timer 1 gate lt ____ to ____ vo General VO portpin General pin bit Pulse Width Modulation PWM0 General port output 0 10 163 Signal In Out q uPSD3212A uPSD3212C uPSD3212CV Signal In Out Alternate P4 4 PWM1 O General WO port pin 45 PWM2 23 lO General WO port pin S bit Pulse Width Modulati n output 2 PWM3 General I O port pin 8 bit Pulse Width Modulation output 3 PWM4 General I O port pin Programmable 8 bit Pulse Width modulation output 4 Pull up resistor required 3V Reterence Voltage inputtor ADG UAR wami WR WRITE signal external bus PSEN signal external bus RESET 368 1 2 2 4e Oscilator input pin for system stock I E E WN BES a General VO port pin PLD Macro cell outputs Latched Address Out 0 PB2 78 General I O port pin PLD Macro cell outputs 11 163 uPSD3212A uPSD3212C uPSD3212CV
15. Table 63 Description of the UIEN Bits SUSPNDI Enable SUSPND Interrupt RSTE 21 Reset also resets the CPU PSD Modules when bit is RSTFIE Enable RSTF USB Bus Reset Flag Interrupt C o resum ww com ST 4 77 163 uPSD3212A uPSD3212C uPSD3212CV Table 64 USB Interrupt Status Register UISTA OE8h SUSPND o RSTF TXD1F EOPF RESUMF Table 65 Description of the UISTA Bits USB Suspend Mode Flag SUSPND To save power this bit should be set if a 3ms constant idle state is detected on USB bus Setting this bit stops the clock to the USB and causes the USB module to enter Suspend Mode Software must clear this bit after the Resume flag RESUMF is set while this Resume Interrupt Flag is serviced Reserved USB Reset Flag This bit is set when a valid RESET signal state is detected on the and D lines When the RSTE bit in the UIEN Register is set this reset detection will also generate an internal reset signal to reset the CPU and other peripherals including the USB module RSTF TXDOF EndpointO Data Transmit Flag This bit is set after the data stored in Endpoint 0 transmit buffers has been sent and an ACK handshake packet from the host is received Once the next set of data is ready in the transmit buffers s
16. uPSD3212A uPSD3212C uPSD3212CV Flash Programmable System Devices with 8032 MCU with USB and Programmable Logic FEATURES SUMMARY FAST 8 BIT 8032 MCU 40MHz at 5 0V 24MHz at 3 3V Core 12 clocks per instruction DUAL FLASH MEMORIES WITH MEMORY MANAGEMENT Place either memory into 8032 program address space or data address space READ while WRITE operation for In Application Programming and EEPROM emulation Single voltage program and erase 100K minimum erase cycles 15 year retention CLOCK RESET AND SUPPLY MANAGEMENT SRAM is Battery Backup age supervisor Programmable Watchdog Timer PROGRAMMABLE LOGIC GENERAL PURPOSE 16 macrocells Implements state machines glue logic and so forth COMMUNICATION INTERFACES 2 Master Slave bus controller Two 5 with independent baud rate Six I O ports with up to 46 I O pins 8032 Address Data bus available on TQFP80 package 5 outputs 8 bit resolution USB v1 1 low speed 1 5Mbps 3 endpoints UPSD32124 only December 2004 Figure 1 Packages TQFP52 T 52 lead Thin Quad Flat l ad Thin Quad Flat JTAG IN SYSTEM PROGRAMMING Program the entire device in as little as 10 seconds A D CONVERTER Four channels 8 bit resolution 10us TIMERS AND INTERRUPTS Three 8032 standard 16 bit timers 10 Interrupt sources
17. 06630 ww comsr 85 163 uPSD3212A uPSD3212C uPSD3212CV External USB Pull Up Resistor The USB system specifies a pull up resistor on the tive is defined for low speed devices with an inte D pin for low speed peripherals The USB grated cable The chip is specified for the 7 5kQ Spec 1 1 describes a 1 5kQ pull up resistor to a pull up This eliminates the need for an external 3 3V supply An approved alternative method is a 3 3V regulator or for a pin dedicated to providing 7 5kQ pull up to the USB Vcc supply This alterna a 3 3V output from the chip Figure 42 USB Data Signal Timing and Voltage Levels 106631 Differential Data Lines Consecutive Transitions N TpERIOD TJR1 Paired Transitions N TpERIoDp TJR2 106632 86 163 uPSD3212A uPSD3212C uPSD3212CV Figure 44 Differential to EOP Transition Skew and EOP Width lt gt Crossover Crossover Point Extended Differential Data Lines Diff Data to SEO Skew Source Width Receiver Width 2 Figure 45 Differential Data Jitter 4 1 Crossover Ponts V Differential Data Lines Transitions 1 Paired Transitions 106633 106634 87 163 uPS
18. 88 163 ANN D 16Kbit SRAM The SRAM s can be protected from a power failure by connecting Decode PLD DPLD that decodes address for selection of memory blocks in the PSD Module Configurable ports Port A B C and D that can be used for the following functions MCU I Os PLD l Os Latched MCU address output and Special function I Os Note 1 0 ports may be configured as open drain outputs Built in JTAG compliant serial port allows full chip In System Programmability ISP With it you can program a blank device or reprogram a device in the factory or the field Internal page register that can be used to expand the 8032 MCU Module address space by a factor of 256 Internal programmable Power Management Unit PMU that supports a low power mode called Power down Mode The PMU can automatically detect a lack of the 8032 CPU core activity and put the PSD Module into Power down Mode Erase WRITE cycles OT mi imum e 1 CO Data 5 year minimum for Main Flash memory Boot PLD and Configuration bits uPSD3212A uPSD3212C uPSD3212CV Figure 46 PSD MODULE Block Diagram Lad 29 48d 08d 0Vd uaavo1 AYOWAW HSV14 8 LHOd 9 V 1HOd 1
19. 774 81 163 uPSD3212A uPSD3212C uPSD3212CV The USCL 8 bit Prescaler Register for USB is at Note USB works ONLY with the MCU Clock fre E1h The USCL should be loaded with a value that quencies of 12 24 36MHz The Prescaler val results in a clock rate of 6MHz for the USB using ues for these frequencies are 0 1 and 2 the following formula USB clock input fosc 2 Prescaler register value 1 Where fosc is the MCU clock input frequency 77 USB 5 Memory JS t Comments B 7 6 5 UDT1 4 UDT1 3 2 1 UDT1 0 E SB Data Xmit 7 6 5 UDTO 4 UDTO 3 2 1 23 0 SUSPND S RSTF TXDOF RXDOF RXD1F B UIEN SUSPNDIE RSTE RSTFIE TXDOIE RXDOIE TXD1IE Enable 5 Endpt0 mm SB UCON1 TSEQ1 EP12SEL FRESUM TP1SIZ3 TP1SIZ2 TP1SIZ1 TP1SIZO x s EC UCON2 SOUT 2 STALL2 STALL L d 53 n RP0SIZ3 RP0SIZ0 iens n UADR USBEN UADD6 UADD5 UADD4 UADD3 UADD2 UADD1 UADDO Address Register UDRO UDRO 7 UDRO 6 UDR0 5 UDRO 4 UDR0 3 UDR0 2 UDRO 1 UDR0 0 82 163 USB Physical Layer Characteristics The fol lowing section
20. 112 PORTS PSD 113 General Port 113 Port Operating 114 MCU Exe ted RESUME ITEMS 114 PEDI OMOd0e e ine RR mer m 114 Address Out Mode e p ERG 114 Peripheral ere e Ex Ge cue ER REUS RR tee edn de 114 JTAG In System Programming 5 114 Port Configuration Registers PCR 116 Port Data Registers uU I Su s S u ligu Ep Reus pa en Rose Rua E RUE Ee 117 Ports A and B Functionality and Structure 118 Port C Functionality and 119 Port D Functionality and 120 External Chip Select sls ee eee 121 POWER MANAGEMENT 122 PLD Power 124 174 5 163 uPSD3212A uPSD3212C uPSD3212CV PSD Chip Select Input
21. 2m JTAG pin JTAG pin General I O port pin General I O port pin General I O port pin JTAG pin General I O port pin General I O port pin 1 2 3 4 5 1 Alternate PLD Macro cell outputs PLD inputs SRAM stand by voltage in put SRAM battery on indicator 4 JTAG pins are dedicated pins PLD CLKIN Aa ES L KW Eu uos JTAG pin RES 52 PIN PACKAGE PORT The 52 pin package members of the uPSD321x Devices have the same port pins as those of the 80 pin package except Port 0 0 7 external address data bus ADO AD7 Port 2 P2 0 P2 3 external address bus A8 A11 12 163 General I O port pin 2 Clock input to PLD and APD PLD I O Chip select to PSD Module Port A PAO PA7 Port D PD2 Bus control signal RD WR PSEN ALE Pin 5 requires a pull up resistor 2kQ for 3V devices 7 5kQ for 5V devices for all devices ARCHITECTURE OVERVIEW Memory Organization The uPSD321x Devices s standard 8032 Core has separate 64KB address spaces for Program mem ory and Data Memory Program memory is where the 8032 executes instructions from Data memory is used to hold data variables Flash memory can be mapped in either program or data space The Flash memory consists of two flash memory blocks the main Flash 512Kbit and the Second ary Flash 128Kbit Except during flash memory programmi
22. PLD x from graph using Freq PLD 0 8 x 2 5mA MHz x 2MHz 0 15 x 1 5mA MHz x 2MHz 24mA 4 0 45 24 mA 28 45 20mA x 40 28 45 x 40 250 x 60 11 38 150A 19 53 This is the operating power with Flash memory Erase Program cycles progress Calculation is based on all I O pins being disconnected and lout 0mA 129 163 uPSD3212A uPSD3212C uPSD3212CV MAXIMUM RATING Stressing the device above the rating listed in the plied Exposure to Absolute Maximum Rating con Absolute Maximum Ratings table may cause per ditions for extended periods may affect device manent damage to the device These are stress reliability Refer also to the STMicroelectronics ratings only and operation of the device at these or SURE Program and other relevant quality docu any other conditions above those indicated in the ments Operating sections of this specification is not im Table 105 Absolute Maximum Ratings Symbol Parameter Lead Temperature during Soldering 20 seconds max 235 Input and Output Voltage Q or Hi Z 0 5 6 5 0 5 Device Programmer Supply Voltage 0 5 Electrostatic Discharge Voltage Human Body Model 2 2000 Note 1 IPC JEDEC J STD 020A 2 JEDEC Std JESD22 A114A 1 100 R1 1500 R2 500 ww com ST 130 163 572 CHARACTERISTICS Susceptibility test are performed
23. Table 31 PASFS 94H 4 Bits are reserved ESS ST om 41 163 uPSD3212A uPSD3212C uPSD3212CV PORT Type and Description Figure 17 PORT Type and Description Part 1 RESET Schmitt input with internal pull up CMOS compatible interface NFC 400ns WR On chip oscillator XTAL2 On chip feedback resistor Stop in the power down mode External clock input available CMOS compatible interface 51 Bidirectional port Schmitt input Address Output Push Pull CMOS compatible interface 107438 42 163 Figure 18 PORT Description 2 In Function 3 05 4 lt 7 3 1 0 gt 2 lt 7 4 gt 2 i uPSD3212A uPSD3212C uPSD3212CV Bidirectional port with internal pull ups Schmitt input CMOS compalible interface Bidirectional port with internal pull ups Schmitt input CMOS compalible interface Analog input option Bidirectional I O port with internal pull ups Schmitt input TTL compatible interface Bidirectional port USB USB Schmitt input TTL compatible interface AI07428b 43 163 uPSD3212A uPSD3212C uPSD3212CV OSCILLATOR The oscillator circuit of the uPSD321x Devices is a ment to complete the oscillator circuit Both are single stage inverting amplifier
24. Unchanged Note 1 The SR cod and PeriphMode Bits in the VM Register are always cleared to 0 on Power on RESET or Warm RESET 126 163 uPSD3212A uPSD3212C uPSD3212CV PROGRAMMING IN CIRCUIT USING THE JTAG SERIAL INTERFACE The JTAG Serial Interface pins TMS TCK TDI TDO are dedicated pins on Port C see Table 103 All memory blocks primary and secondary Flash memory PLD logic and PSD MODULE Configuration Register Bits may be programmed through the JTAG Serial Interface block A blank device can be mounted on a printed circuit board and programmed using JTAG The standard JTAG signals IEEE 1149 1 are TMS TCK TDI and TDO Two additional signals TSTAT and TERR are optional JTAG extensions used to speed up Program and Erase cycles By default on a blank device as shipped from the factory or after erasure four pins on Port C are the basic JTAG signals TMS TCK TDI and TDO Standard JTAG Signals At power up the standard JTAG pins are inputs waiting for a JTAG serial command from an exter nal JTAG controller device such as FlashLINK or Automated Test Equipment When the enabling command is received TDO becomes an output and the JTAG channel is fully functional The same command that enables the JTAG channel may optionally enable the two additional JTAG sig nals TSTAT and TERR The RESET input to the uPS3200 should be active during JTAG programming The ge puts the MCU mad T Mag PSD Module is
25. sample ba sis during product characterization Functional EMS Electromagnetic Susceptibility Based on a simple running application on the product toggling 2 LEDs through I O ports the product is stressed by two electromagnetic events until a failure occurs indicated by the LEDs ESD Electro Static Discharge positive and neg ative is applied on all pins of the device until a functional disturbance occurs This test conforms with the IEC 1000 4 2 Standard FTB A burst of Fast Transient voltage positive and negative is applied to Vpp and Vss through a 100pF capacitor until a functional disturbance oc curs This test conforms with the IEC 1000 4 2 Standard A device reset allows normal operations to be re sumed The test results are given in Table 106 based on the EMS levels and classes defined in Application Note AN1709 Designing Hardened Software To Avoid Noise Problems EMC characterization and optimization are per formed at component level with a typical applica tion environment simplified MCU software It should be note erf highly depender s oth software in Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for the user s application Table 106 EMS Test Results V Voltage limits to be applied on any I O pin to FESD induce a functional disturbance Vpp
26. 2 3 gt Rn SRAM SELECT 1 CSIOP DECODER SELECT PSELO PERIPHERAL I O SELECT 07436 Complex CPLD The CPLD can used implement system logic functions such as loadable counters and shift reg isters system mailboxes handshaking protocols state machines and random logic The CPLD can also be used to generate External Chip Select ECS1 ECS2 routed to Port D Although External Chip Select ECS1 ECS2 can be produced by any Output Macrocell OMC these External Chip Select ECS1 ECS2 on Port D do not consume any Output Macrocells OMC As shown in Figure 54 the CPLD has the following blocks m 20 Input Macrocells m 16 Output Macrocells m Allocator Product Term Allocator Figure 56 Macrocell and Port PRODUCT TERMS FROM OTHER MACROCELLS MCU ADDRESS DATA BUS uPSD3212A uPSD3212C uPSD3212CV m AND Array capable of generating up to 137 product terms m Four I O Ports Each of the blocks are described in the sections that follow The Input Macrocells IMC and Output Macrocells are connected to the PSD MODULE inter nal data bus and can be directly accessed by the MCU This enables the MCU software to load data into the Output Macrocells OMC or read data from both the Input and Output Macrocells IMC and OMC This feature allows efficient implementation of sys tem logic and eliminates the nee
27. CSI PD2 124 Input CIOCK onere ense ES ERE p TEE SiS 124 Input Control Signals 124 RESET TIMING AND DEVICE STATUS RESET 126 Warm 22 tet 126 Pin Register and PLD Status RESET 126 PROGRAMMING IN CIRCUIT USING THE JTAG SERIAL INTERFACE 127 Standard JTAG Signals 0 5 eve 127 JTAG Extensions casu RR RUNE es as 127 Security Flash memory 127 INITIAL DELIVERY q rece s 127 AC DC PARAMETERS oie 9 sasa e wx awa woa 128 MAXIMUM RATING ium Le n tar sua 130 CHARACTERISTICS 131 Functional EMS Electromagnetic 131 Designing Hardened Software To Avoid Noise Problems 131 Absolute Maximum Ratings Electrical Sensitivity 131 AND PARVENSA FS EM UEM 0
28. Flat Package Mechanical Data o VW atau O 158 163 uPSD3212A uPSD3212C uPSD3212CV Figure 90 TQFP80 80 lead Plastic Thin Quad Flat Package Outline Note Drawing is not to scale 159 163 uPSD3212A uPSD3212C uPSD3212CV Table 145 TQFP80 80 lead Plastic Thin Quad Flat Package Mechanical Data 5 j d c 160 163 uPSD3212A uPSD3212C uPSD3212CV PART NUMBERING Table 146 Ordering Information Scheme Example uPSD 3 2 1 2 C V 24 U 6 T Device Type uPSD Microcontroller PSD Family 3 8032 core PLD Size 2 16 Macrocells SRAM Size 1 2K bytes Main Flash Memory Size 2 64K bytes IP Mix USB PWM ADC 2 UARTs Supervisor Reset Out Reset In LVD WD C PWM ADC 2 UARTs Supervisor Reset E In LVD C Operating Voltage blank Vcc 4 5 to 5 5V V Vcc 3 0 to 3 6V Speed 24 24MHz 40 40MHz Package T 52 pin TQFP U 80 pin TQFP Temperature Range 6 40 to 85 C Shipping Option T Tape and Reel Packing For other options or for more information on any aspect of this device please contact the ST Sales Office nearest you 161 163 uPSD3212A uPSD3212C uPSD3212CV REVISION HISTORY Table 147 Document
29. M1 M0 0 1 16 bit Timer Counter TH1 and TL1 are cascaded There is no prescaler M1 M0 1 0 8 bit auto reload Timer Counter TH1 holds a value which is to be reloaded into TL1 each time it overflows M1 M0 1 1 Timer Counter 1 stopped Gating control when set Timer Counter 0 is enabled only while pin is High control pin is set When cleared Timer 0 is enabled whenever control bit is set Timer or Counter selector cleared for timer operation input from internal system clock set for counter operation input from input pin M1 M0 0 0 13 bit Timer Counter TH0 with TL0 as 5 bit prescaler M1 M0 0 1 16 bit Timer Counter TH0 and TL0 are cascaded There is no prescaler M1 M0 1 0 8 bit auto reload Timer Counter TH0 holds a value which is to be reloaded into TL0 each time it overflows 1 0 1 1 TLO is 8 bit Timer Counter controlled by the standard 0 control bits THO is an 8 bit timer only controlled by Timer 1 control bits 49 163 uPSD3212A uPSD3212C uPSD3212CV Mode 0 Putting either Timer into Mode 0 makes itlook like an 8048 Timer which is an 8 bit Counter with a divide by 32 prescaler Figure 22 shows the Mode 0 operation as it applies to Timer 1 In this mode the Timer register is configured as a 13 bit register As the count rolls over from all 1s to all Os it sets the Timer Interrupt Flag counted input is enabled to the Time
30. and Battery on Indicator PC4 are all configured using PSDsoft Express Configura tion Sector Select and SRAM Select Sector Select 50 83 CSBOOTO SRAM Select 50 DPLD They gi them in PSDsoft ply to the equations for theSe Signa 1 Primary Flash memory and Seconda Flash memory Sector Select signals must not be larger than the physical sector size 2 Any primary Flash memory sector must not be mapped in the same memory space as another Flash memory sector 3 Asecondary Flash memory sector must notbe mapped in the same memory space as another secondary Flash memory sector 4 SRAM I O and Peripheral I O spaces must not overlap 5 secondary Flash memory sector overlap a primary Flash memory sector In case of overlap priority is given to the secondary Flash memory sector 102 163 6 SRAM I O and Peripheral I O spaces overlap any other memory sector Priority is given to the SRAM I O or Peripheral I O Example 250 is valid when the address is in the range of 8000h to BFFFh CSBOOTO is valid from 8000h to 9FFFh and RSO is valid from 8000h to 87FFh Any address in the range of RSO always accesses the SRAM Any address in the range of CSBOOTO greater than 87FFh and less than 9FFFh automatically addresses secondary Flash memory segment 0 Any address greater than 9FFFh accesses the primary Flash memory seg ment 0 You can see that half of the primary Fla
31. and a clock line SCL1 as shown in Figure 39 Depending on the configuration the SDA1 and SCL1 lines may re quire pull up resistors These lines also function as I O port lines if the 122 bus is not enabled The system is unique because data transport clock generation address recognition and bus control arbitration are all controlled by hardware The serial I O has complete autonomy in byte handling and operates in 4 modes m Master transmitter m Master receiver Figure 39 Block Diagram of the I C Bus Serial I O 7 7 SDA1 BON Table 50 Serial Control Register S2CON Slave Address 0 Shift Register Arbitration and Sync Logic m Slave transmitter m Slave receiver These functions are controlled by the SFRs see Tables 50 51 and Table 52 page 73 S2CON the control of byte handling and the operation of 4 mode S2STA the contents of its register may also be used as a vector to various service routines S2DAT data shift register S2ADR slave address register Slave address recognition is performed by On Chip H W 0 107430 72 163 uPSD3212A uPSD3212C uPSD3212CV Table 51 Description of the S2CON Bits smo Rien 7 CR2 This bit along with Bits CR1and CRO determines the serial clock frequency when SIO is in the Master Mode Enable When 0 the is disabled SDA and SCL outputs are in the
32. date a table of up to 256 entries numbered 0 through 255 The number of the desired entry is loaded into the Accumulator and the Data Pointer is set up to point to the beginning of the table Then MOVC A DPTR copies the desired table entry into the Accumula tor The other MOVC instruction works the same way except the Program Counter PC is used as the table base and the table is accessed through a subroutine First the number of the desired en try is loaded into the Accumulator and the subroutine is called MOV ENTRY NUMBER CALL TABLE The subroutine TABLE would look like this TABLE MOVC RET The table itself immediately follows the RET re turn instruction is Program Memory This type of table can have up to 255 entries numbered 1 through 255 Number 0 cannot be used because at the time the MOVC instruction is executed the PC contains the address of the RET instruction An entry numbered 0 would be the RET opcode it self Table 10 Data Transfer Instruction that Access External Data Memory Space Address Width 1 4 4 8 bits VEI 2 C WALT 2 8 bits Ri A WRITE external 16 bits MOVX A DPTR READ external RAM 16 bits MOVX WRITE external Table 11 Table READ Instruction _ _ _ A A DPTR READ program memory A DPTR MOVC A
33. other pins are disconnected Icc would be slightly higher if a crystal oscillator is used approximately 1mA lcc Idle Mode is measured with XTAL1 driven with tci cH tcHcL 5ns Vss 0 5V Vcc 0 5V XTAL2 not connected Port 0 Vcc all other pins are disconnected See Figure 68 page 128 for the PLD current calculation current OmA pins are disconnected 137 163 uPSD3212A uPSD3212C uPSD3212CV Table 115 DC Characteristics 3V Devices Test Condition in addition to those in Table 110 page 133 Input High Voltage Ports 1 2 3 4 Bits 7 6 5 4 3 1 0 A B C 3 0V Vcc 3 6V 0 7Vcc D XTAL1 RESET 3 0V Vcc 3 6V 2 0 Input High Voltage Ports 1 2 3 4 Bits 7 6 5 4 3 1 0 XTAL 1 3 0V Vcc 3 6V Vss 0 5 RESET Input Low Voltage E Ports A B C D 3 0V Vcc 3 6V 0 5 Input Low Voltage _ Port 4 Bit 21 3 0V lt Vcc lt 3 6V 0 lo 200A Output Low Voltage Voc 3 0V Ports A B C D lot 4mA Voc 3 0V Output Low Voltage __ ea Ports 1 2 3 4 WR RD lot 100A 34200 20 Voc 3 0 lt lt ES om Output High Voltage Ports A B C D 1mA Voc 3 0 Output High Voltage 20 1 2 3 4 WR RD loH IOHA Output High Voltage Port 0 loH
34. the microcontroller restarts after 3 machine cycles in all cases er Down Mode Table 25 son NAM E DIR C I e Disable Table 26 Pin Status During Idle and Power down Mode Bit Register Name Miti EX IDLE 00 Power Ctrl 39 163 uPSD3212A uPSD3212C uPSD3212CV Table 27 Description of the PCON Bits Sms Fa SMOD Double Baud Data Rate Bit UART SMOD1 Double Baud Data Rate Bit 2nd UART LVREN LVR Disable Bit active High ADSFINT Enable ADC Interrupt Received Clock Flag UART 2 1 Transmit Clock Flag UART 2 PD Activate Power down Mode High enable Activate Idle Mode High enable Note 1 See the T2CON register for details of the flag description PORTS MCU MODULE The MCU Module has five ports Port0 Port1 Port2 Port3 and Port 4 Refer to the PSD Module section on ports A B C and D Ports and P2 are dedicated for the external address and data bus and is not available in the 52 pin package de vices Port1 Port3 are the same as in the standard 8032 WWW BOT Table 28 I O Port Functions tional special peripheral functions see Table 28 All ports are bi directional Pins of which the alter native function is not used may be used as normal bi directional I O The use of Port1 Port4 pins as alternative func tions are carried out automatically by the uPSD321x Devices provided the a
35. the user specifies to the as sembler the actual destination address the same way as the other jumps as a label or a 16 bit con stant There is no Zero Bit in the PSW The JZ and JNZ instructions test the Accumulator data for that con dition The DJNZ instruction Decrement and Jump if Not Zero is for loop control To execute a loop N times load a counter byte with N and terminate the loop with a DJNZ to the beginning of the loop as shown below for 10 MOV COUNTER 10 LOOP begin loop end loop DJNZ COUNTER LOOP continue The CJNE instruction Compare a Equal can also ble 9 page 21 Tyo respec erand field of the instruction The jump is executed only if the two bytes are not equal In the example of Table 9 page 21 Shifting a BCD Number One Digits to the Right the two bytes were data in R1 and the constant 2Ah The initial data in R1 was 2Eh Table 14 Conditional Jump Instructions Operation JNZ rel Jump if A z 0 uPSD3212A uPSD3212C uPSD3212CV Every time the loop was executed R1 was decre mented and the looping was to continue until the R1 data reached 2Ah Another application of this instruction is in greater than less than comparisons The two bytes in the operand field are taken as unsigned integers If the first is less than the second then the Carry Bit is set 1 If the first is greater than or equal to the second then the Carry Bit is cleared Machine
36. uPSD3212A uPSD3212C uPSD3212CV Port Configuration Registers PCR Each Port has a set of Port Configuration Regis ters PCR used for configuration The contents of the registers can be accessed by the MCU through normal READ WRITE bus cycles at the addresses given in Table 81 page 92 The addresses in Ta ble 81 are the offsets in hexadecimal from the base of the CSIOP register The pins of a port are individually configurable and each bit in the register controls its respective pin For example 0 in a register refers to Bit O of its port The three Port Configuration Registers PCR shown in Table 92 are used for setting the Port configurations The default Power up state for each register in Table 92 is 001 Control Register Any bit reset to 0 in the Con trol Register sets the corresponding port pin to MCU Mode and 1 sets it to Address Out Mode The default mode is MCU I O Only Ports and B have an associated Control Register Direction Register The Direction Register in conjunction with the output enable except for Port D controls the direction of data flow in the Ports Any bit set to 1 in the Direction Register causes the corresponding pin to be an output and any bit set to 0 causes it to be an input The de fault mode for all port pins is input Figure 61 page 118 and Figure 62 show the Port ams 19 and C respectiv Ports A B and C note rection
37. ue of a constant can follow the opcode in Program memory Example mov A 6 Indexed addressing Only Program memory can be accessed with indexed addressing and it can only be read This addressing mode ed for reading logk rog A 16 bit base re T to the base of the up with the table entry eee The address of the table entry in Program memory is formed by add ing the Accumulator data to the base pointer see Figure 13 Example movc A DPTR Figure 13 Indexed Addressing ACC DPTR 1E73h Program Memory 3Eh Al06643 uPSD3212A uPSD3212C uPSD3212CV Arithmetic Instructions The arithmetic instructions is listed in Table 4 page 18 The table indicates the addressing modes that can be used with each instruction to access the lt byte gt operand For example the ADD A lt byte gt instruction can be written as ADD a 7FH direct addressing ADD indirect addressing ADD a R7 register addressing ADD A 127 immediate constant Note Any byte in the internal Data Memory space can be incremented without going through the Ac cumulator One of the INC instructions operates on the 16 bit Data Pointer The Data Pointer is used to generate 16 bit addresses for external memory so being able to increment it in one 16 bit operations is a useful feature The MUL AB instruction multiplies the Accumula tor by the data in the B register and puts
38. 10ms Figure 20 RESET Configuration USB Reset 50ms 8Mhz uPSD3212A uPSD3212C uPSD3212CV before it is released On initial power up the LVR is enabled default After power up the LVR can be disabled the LVREN Bit in the PCON Reg ister Note The LVR logic is still functional in both the Idle and Power down Modes The reset threshold m 5V operation 4V 0 25 m 3 3 operation 2 5V 0 2V This logic supports approximately 0 1V of hystere sis and 1 5 noise cancelling delay Watchdog Timer Overflow The Watchdog Timer generates an internal reset when its 22 bit counter overflows See Watchdog Timer section for details USB Reset The USB reset is generated by a detection on the USB bus RESET signal A single end zero on its upstream port for 4 to 8 times will set RSTF Bit in UISTA register If Bit 6 RSTE of the UIEN Regis ter is set the detection will also generate the RESET signal to reset the CPU and other periph erals in the MCU PSD_RST Active Low AI07429b 45 163 uPSD3212A uPSD3212C uPSD3212CV WATCHDOG TIMER The hardware Watchdog Timer WDT resets the uPSD321x Devices when it overflows The is intended as a recovery method in situations where the CPU may be subjected to a software upset To prevent a system reset the timer must be reloaded in time by the application software If the processor suffers a hardware software malfunction
39. 133 PACKAGE MECHANICAL 157 PART NUMBERING eru E nex t NE 161 REVISION HISTOHY ele eR al a hug IRE 162 6 163 SUMMARY DESCRIPTION The uPSD321x Series combines a fast 8051 based microcontroller with a flexible memory structure programmable logic and a rich periph eral mix including USB to form an ideal embedded controller At its core is an industry standard 8032 MCU operating up to 40MHz A JTAG serial interface is used for In System Pro gramming ISP in as little as 10 seconds perfect for manufacturing and lab development The USB 1 1 low speed interface has one Control Endpoint and two Interrupt endpoints suitable for HID class drivers The 8032 core is coupled to Programmable Sys tem Device PSD architecture to optimize the 8032 memory structure offering two independent banks of Flash memory that can be placed at vir tually any address within 8032 program or data ad dress space and easily paged beyond 64K bytes using on chip programmable decode logic Figure 2 Block Diagram 3 16 bit Timer Counters uPSD3212A uPSD3212C uPSD3212CV Dual Flash memory banks provide a robust solu tion for remote product updates in the field through In Application Programming IAP Dual Flash banks also support EEPROM emulation eliminat ing the n
40. 150 75 ns UNE jar 362 mar __ __ L TL 3 Note 1 Conditions in addition to those in Table 109 page 133 Vcc 4 5 to 5 5V Vss for Port 0 ALE and PSEN output is 100pF for other outputs is 80pF tLLDV ALE to valid data in 143 163 uPSD3212A uPSD3212C uPSD3212CV Table 121 External Data Memory AC Characteristics with the 3V MCU Module 24MHz Oscillator 12246 Symbol Parameter CLCL Unit i Min tRLRH RD pulse width 70 T mw mean _____ x 5 5 5 5 ALE to valid data in 133 ns Address to valid data in 155 ns Address valid to WR RD 67 4tcLcL 97 5 fw hex _____ mar 2 Z Eri I Note 1 Conditions Ay PI pag 33 389 0 to 3 6 Vss d fo fo PSEN output is 100pF for 5V MEA th 6 for ag digo Table 122 A D Analog Specification TestCondition Mi Typ Uni Analog Power Supply Input Voltage Range Vss y Current Following between __ ee
41. 25 64 x fosc In the uPSD321x Devices the baud rates Modes 1 and 3 are determined by the Timer 1 overflow rate Using Timer 1 to Generate Baud Rates When Timer 1 is used as the baud rate generator the baud rates in Modes 1 and 3 are determined by the Timer 1 overflow rate and the value of SMOD as follows see Table 45 page 59 Mode 1 3 Baud Rate 29 32 x Timer 1 overflow rate The Timer 1 Interrupt should be disabled in this application The Timer itself can be configured for either timer or counter operation and in any of its 3 running modes In the most typical applica tions it is configured for timer operation in the Auto reload Mode high nibble of TMOD 0010B In that case the baud rate is given by the formula Mode 1 3 Baud Rate 29 32 x fosc 12 x 256 TH1 One can achieve very low baud m by leaving the AYAY figuring the Time bit Eme ble of TMOD 0001B and using the Timer 1 Interrupt to do a 16 bit software reload Figure 22 page 50 lists various commonly used baud rates and how they can be obtained from Timer 1 Using Timer Counter 2 to Generate Baud Rates In the uPSD321x Devices Timer 2 select ed as the baud rate generator by setting TCLK and or RCLK see Figure 22 50 Timer Counter 2 Control Register T2CON Note The baud rate for transmit and receive can be simultaneously different Setting RCLK and or TCLK pu
42. 39 174 3 163 uPSD3212A uPSD3212C uPSD3212CV DIES np rer wag 39 Power Down Mode 39 PORTS MCU 40 PORT Type and 42 OSCILLATOR mu mra ngo Pa 44 SUPERVISORY 22222 24 RR RR E e gr rx DR E 45 External Reset iE RA EXER Ru ah que ANSA ANE RARE Mis 45 Low Vpp Voltage 45 Watchdog Timer Overflow 45 USB Heset iesus s uka dna RR awas 45 WATCHDOG Ime ETT ERE PE RR e 46 TIMER COUNTERS TIMER 0 1 AND 2 48 and Timer 1 ze Ikl2emn Qasa lx ue melee de erg x x e sce ee 48 EE 51 STANDARD SERIAL INTERFACE 55 Multiprocessor 55 Serial Port Control Register M DR 56 maroro C COM 9 L lues X
43. 4V TA 25 C fosc 40MHz uPSD3212A uPSD3212C uPSD3212CV Software Recommendations The software flowchart must include the management of run away conditions such as Corrupted program counter Unexpected reset Critical data corruption e g control registers Prequalification trials Most of the common fail ures unexpected reset and program counter cor ruption can be reproduced by manually forcing a low state on the RESET pin or the oscillator pins for 1 second To complete these trials ESD stress can be ap plied directly on the device over the range of spec ification values When unexpected behavior is detected the software can be hardened to prevent unrecoverable errors occurring see Application Note AN1015 Absolute Maximum Ratings Electrical Sensitivity Based on three different tests ESD LU and DLU and using specific measurement methods the product is stressed in order to determine its perfor mance in terms of electrical sensitivity For more details refer to the Application Note AN1181 Electro Static ESD Electro Static ischarges positive tive pulse sepa rated b the pins each sa J ombination The t ber of supply pins in ds ph 3 parts n1 supply pin The Hu man Body Model is simulated see Table 107 This test conforms to JESD22 A114A Stan dard Level Class off confor
44. Program and Data spaces are combined into one memory space that allows the primary Flash memory sec ondary Flash memory and SRAM to be accessed by either Program Select Enable PSEN or READ Strobe RD For example to configure the prima ry Flash memory in Combined space Bits b2 and 54 of the VM Register are set to 1 see Figure 52 SRAM 107433 107434 104 163 Register The 8 bit Page Register increases the addressing capability of the MCU Core by a factor of up to 256 The contents of the register can also be read by the MCU The outputs of the Page Register PGRO PGR7 are inputs to the DPLD decoder and can be included in the Sector Select 50 253 CSBOOT0 CSBOOT1 and SRAM Select RSO equations Figure 53 Page Register uPSD3212A uPSD3212C uPSD3212CV If memory paging is not needed or if not all 8 page register bits are needed for memory paging then these bits may be used in the CPLD for general logic Figure 53 shows the Page Register The eight flip flops in the register are connected to the internal data bus 00 07 The MCU can write to or read from the Page Register The Page Register can be accessed at address location CSIOP EOh INTERNAL PSD MODULE SELECTS AND LOGIC 105799 105 163 uPSD3212A uPSD3212C uPSD3212CV PLDS The PLDs bring programmable logic functionality to the uPSD After specifying the logic for the PLDs in PSDsoft Express the lo
45. TCLK1 1 It will be described in conjunction with the serial port Figure 23 Timer Counter Mode 2 8 bit Auto reload Interrupt 106623 Table 40 Timer Counter 2 Control Register T2CON ACE NE NACE EXF2 RCLK TCLK EXEN2 CP RL2 51 163 uPSD3212A uPSD3212C uPSD3212CV Table 41 Timer Counter 2 Operating Modes Input Clock Clock T2MOD T2CON P1 1 R DECN EXEN T2EX External RL2 P1 0 T2 ofif o o x x reload upon overflow reload upon overfiow overflow reload et eee 1 Upcounting Up counting EXE bit Timer Counter 16 bit only up counting OSC Capture Capture TH1 TL2 fosc 24 RCAP2H Overflow Interrupt Baud Rate Request TF2 fosc 12 Generator Extra External Interrupt 2 Table 42 Description the T2CON Bits Note 4 SW edge by software TF2 LK Timer 2 External Flag set when either a capture or reload is caused by a negative transition on T2EX and EXEN2 1 When Timer 2 Interrupt is enabled EXF2 1 will cause the CPU to vector to the Timer 2 Interrupt routine EXF2 must be cleared by software Receive Clock Flag UART 1 When set causes the serial port to use Timer 2 overflow pulses for its receive clock in Modes 1 and 3 TCLK 0 causes Timer 1 overflow to be used for the receive clock Transmit Clock Flag UA
46. The Pulse Width Register defines the pulse duration or the Pulse Width while the Period Register defines the period of the PWM When the PWM 4 channel is enabled the register values are loaded into the Comparator Registers and are compared to the uPSD3212A uPSD3212C uPSD3212CV Counter output When the content of the counter is equal to or greater than the value in the Pulse Width Register it sets the PWM 4 output to low with PWMP Bit 0 When the Period Register equals to PWM4 Counter the Counter is cleared and the PWM 4 channel output is set to logic level beginning of the next PWM pulse The Period Register cannot have a value of 00 and its content should always be greater than the Pulse Width Register The Prescaler1 Register Pulse Width Register and Period Register can be modified while the PWM 4 channel is active The values of these reg isters are automatically loaded into the Prescaler Counter and Comparator Registers when the cur rent PWM 4 period ends The PWMCON Register Bits 5 and 6 controls the enable disable and polarity of the PWM 4 channel Figure 38 PWM 4 With Programmable Pulse Width and Frequency Defined by Period Register PWM4 Defined by Pulse Width Register Switch Level RESET Counter 107090 71 163 uPSD3212A uPSD3212C uPSD3212CV INTERFACE The serial port supports the twin line 12 con sisting of a data line SDA1
47. The Accumulator can be used as a 16 bit register with B Register as shown in Figure 6 B Register The B Register is the 8 bit general purpose register used for an arithmetic operation such as multiply division with the Accumulator see Figure 7 Stack Pointer The Stack Pointer Register is 8 bits wide It is incremented before data is stored during PUSH and CALL executions While the stack may reside anywhere in on chip RAM the Stack Pointer is initialized to 07h after reset This causes the stack to begin at location 08h see Fig ure 8 Program Counter The Program Counter is a 16 bit wide which consists of two 8 bit registers PCH and PCL This counter indicates the address of the next instruction to be executed In RESET state the program counter has reset routine address PCH 00h PCL 00h Program Statu E Word PSW corgi its current state of t d Selec to 1Fh to Bank3 The PSW is de scribed in Figure 9 page 15 It contains the Carry Flag the Auxiliary Carry Flag the Half Carry for BCD operation the general purpose flag the Register Bank Select Flags the Overflow Flag and Parity Flag Carry Flag CY This flag stores any carry or not borrow from the ALU of CPU after an arithmetic operation and is also changed by the Shift Instruc tion or Rotate Instruction Auxiliary Carry Flag AC After operation this is set when there is a carry from Bit 3 of ALU or there is no borr
48. UDTO 2 UDTO 1 UDTO O USB Data Xmit E UISTA SUSPND RSTF TXDOF RXD1F RESUMF Hi 2 UIEN SUSPNDIE RSTE TXDOIE RXDOIE TXD1IE EOPIE oo Poenum UCONO TSEQO STALLO TXOE 5123 05122 05121 TPOSIZO USB Xmit Control UCON1 TSEQ1 EP12SEL FRESUM TP1SIZ3 TP1SiZ2 TP1SIZ1 TP1SIZ0 USB Xmit Control Register USTA RSEQ SETUP RPOSIZ1 RPOSIZO o 00 E UADR USBEN UADD6 UADD5 UADD4 UADD3 UADD2 UADD1 UADDO E 2 UDRO UDRO 7 UDRO 6 UDR0 5 UDRO 4 UDR0 3 UDR0 2 UDRO 1 UDR0 0 USB Data Recv B Register 31 163 uPSD3212A uPSD3212C uPSD3212CV Table 17 PSD Module Register Address Offset CSIOP Bit Register Name Addr Register Name Comments Otte COCO REE Bian Data In Port A In Port A Reads Portpinsasinput Port pins as Reads Portpinsasinput oo Control Port A Configure pin between I O or Out Mode Bit 0 selects T 04 Data Out Port Latched data for output to Port pins Output Mode 06 Direction Port Configures Port pin as input or output Bit 0 selects input Configures Port pin between CMOS Open Drain or Slew rate Drive 0 selects CMOS E 5 Reads latched value on Input Macrocells EEN Enable Out Reads the statu
49. and WRITE Strobe WR CNTLO High during Power up for maximum security of the data contents and to remove the possibility of a byte being written on the first edge of WRITE Strobe WR CNTLO Any WRITE cycle initiation is locked when is below VI ko READ Under typical conditions the MCU may read the primary Flash memory or the secondary Flash memory using READ operations just as it would a ROM or RAM device Alternately the MCU may use READ operations to obtain status information about a Program or Erase cycle that is currently in progress Lastly the MCU may use instructions to read special data from these memory blocks The following sections describe these READ functions READ Memory Contents Primary Flash memo ry and secondary Flash memory are placed in the READ Mode after Power up chip reset or a Reset Flash instruction see Table 82 page 95 The MCU can read the memory contents of the pri mary Flash memory or the secondary Flash mem ory by using READ operations any time the READ operation is not part of an instruction READ Memory primary Flash m 3 specific WRITE READ opera tion see Table 82 During the READ operation address Bits and AO must be 0 1 and 0 respectively while Sector Select 50 53 or CSBOOTO CSBOOT 1 designates the Flash memory sector whose protection has to be veri fied The READ operation produces Oth if the Flash memory sector is protected or OOh
50. as shown in Figure 61 The two ports can be configured to perform one or more of the following functions m MCU I O Mode m CPLD Output Macrocells McellAB7 McellABO can be connected to Port A or Port B McellBC7 McellBCO can be connected to Port B or Port C Figure 61 Port A and Port B Structure DATA OUT REG G RT MACROCELL OUTPUTS ADDRESS MCU DATA BUS m ES ENABLE PRODUCT TERM OE V CPLD INPUT DATA OUT PORT A OR B PIN AL7 0 OUTPUT MUX lt ADDRESS READ MUX CPLD Input Via the Input Macrocells IMC m Address output Provide latched address output as per Table 91 page 115 m Open Drain Slew Rate pins PA3 PAO and can be configured to fast slew rate pins PA7 PA4 and PB7 PB4 can be configured to Open Drain Mode m Peripheral Mode Port A only 80 pin package OUTPUT SELECT DATA IN Q cana ST INPUT MACROCELL 06605 118 163 Port Functionality and Structure Port C can be configured to perform one or more of the following functions see Figure 62 uPSD3212A uPSD3212C uPSD3212CV Open Drain Port C pins can be configured in Open Drain Mode m MCU IO Mode Battery Backup features PC2 can be m CPLD Output McellBC7 McellBCO outputs configured for a battery input supply Voltage can be connected to Port B or Port C Standby m CPLD Input via the Input Mac
51. buffered meaning it can commence reception of a second byte before a previously received byte has been read from the register However if the first byte still has not been read by the time reception of the second byte is complete one of the bytes will be lost The serial port receive and transmit registers are both accessed at Special Function Register SBUF or SBUF2 for the second serial port Writing to SBUF loads the transmit register and reading SBUF accesses a physically separate receive register The serial port can operate in 4 modes Mode 0 Serial data enters and exits through RxD TxD outputs the shift clock 8 bits are trans mitted received LSB first The baud rate is fixed at 1 12 the fosc Mode 1 10 bits are transmitted through TxD or received through RxD a start Bit 0 8 LSB first and a Stop Bit 1 Bit goes into 675 SCON bau e Mode 2 11 bits are transmitted through TxD or received through RxD start Bit 0 8 data bits LSB first a programmable 9th data bit and a Stop Bit 1 On Transmit the 9th data bit TB8 in SCON can be assigned the value of 0 or 1 Or for example the Parity Bit P in the PSW could be moved into TB8 On receive the 9th data bit goes into RB8 in Special Function Register SCON while the Stop Bit is ignored The baud rate is pro grammable to either 1 32 or 1 64 the oscillator fre quency uPSD3212A uPS
52. byte containing the low 8 bits of the destina tion address When the instruction is executed these 11 bits are simply substituted for the low 11 bits in the PC The high 5 bits stay the same Hence the destination has to be within the same 2K block as the instruction following In all cases the p cifi tion address to rm th label as 16 bit constant The assembler will put the destination address into correct format for the given instruction If the format required by the instruction will not support the distance to the specified destination address a Destination out of range message is written into the List file The A DPTR instruction supports case jumps The destination address is computed at ex ecution time as the sum of the 16 bit DPTR regis ter and the Accumulator Typically DPTR is set up with the address of a jump table In a 5 way branch for ex ample an integer 0 through 4 is loaded into the Accumulator The code to be exe cuted might be as follows MOV DPTR ZJUMP TABLE MOV A INDEX NUMBER RLA JMP A DPTR 24 163 The RL A instruction converts the index number 0 through 4 to an even number on the range 0 through 8 because each entry in the jump table is 2 bytes long JUMP TABLE AJMP CASE 0 AJMP CASE 1 AJMP CASE 2 AJMP CASE 3 AJMP CASE 4 Table 13 shows a single CALL addr instruction but there are two of them LCALL and ACALL which differ in the format i
53. can only be assigned to Port in the 52 pin package 2 Port PCO PC1 PC5 and PC6 are assigned to JTAG pins and are not available as macrocell outputs 110 163 Product Term Allocator The CPLD has a Product Term Allocator PSDsoft uses the Product Term Allocator to borrow and place product terms from one macrocell to anoth er The following list summarizes how product terms are allocated McellABO McellAB7 all have three native product terms and may borrow up to six more McellBCO McellBC3 all have four native product terms and may borrow up to five more McellBC4 McellBC7 all have four native product terms and may borrow up to six more Each macrocell may only borrow product terms from certain other macrocells Product terms al ready in use by one macrocell are not available for another macrocell If an equation requires more product terms than are available to it then external product terms are required which consume other Output Macro cells OMC If external product terms are used extra delay is added for the equation that required the extra product terms Figure 57 CPLD Output Macrocell PT b ALLOCATOR UH AND ARRAY PLD INPUT BUS v 4 PT CLK CLKIN FEEDBACK FB PORT INPUT I PROGRAMMABLE uPSD3212A uPSD3212C uPSD3212CV This is called product term expansion PSDsoft Express performs this expansion as needed Load
54. describes the uPSD321x Devices compliance to the Chapter 7 Electrical section of the USB Specification Revision 1 1 The section contains all signaling and physical layer specifica tions necessary to describe a low speed USB function Low Speed Driver Characteristics The uPSD321x Devices use a differential output driver to drive the Low Speed USB data signal onto the USB cable The output swings between the differ ential high and low state are well balanced to min imize signal skew The slew rate control on the driver minimizes the radiated noise and cross talk on the USB cable The driver s outputs support three state operation to achieve bi directional half duplex operation The uPSD321x Devices driver Figure 40 Low Speed Driver Signal Waveforms uPSD3212A uPSD3212C uPSD3212CV tolerates a voltage on the signal pins of 0 5V to 3 6V with respect to local ground reference without damage The driver tolerates this voltage for 10 0us while the driver is active and driving and tolerates this condition indefinitely when the driver is in its high impedance state A low speed USB connection is made through an unshielded untwisted wire cable a maximum of 3 meters in length The rise and fall time of the sig nals on this cable are well controlled to reduce RFI emissions while limiting delays signaling skews and distortions The uPSD321x Devices driver reaches the specified static signal levels with smooth rise and fall times res
55. eee a a alee ek eed EE 91 PSD MODULE REGISTER DESCRIPTION AND ADDRESS 92 PSD MODULE DETAILED 93 MEMORY BLOCKS wt tia 2e ela wae ere eg rh Rage as ee ee Pee 93 Primary Flash Memory and Secondary Flash memory Description 93 Memory Block Select 93 Instructions 5 1 3936 0 EE Eo Rs 94 Power down Instruction and Power up Mode 96 iic im 96 Programming Flash Memory 98 Erasing Flash Memory seria EST 100 Specific 2 4 44 4 ORE 101 ETT 102 Sector Select and SRAM 102 Page Register cash Sa rds OG eee ahaa d da edo dos Ead E 105 PLDS prm 106 The Turbo Bit in PSD 106 Decode PLR Tm ES qu ELTE 108 Complex PL We Tum 2 pm 109 Output 110 Product Term 111 Input Macrocells
56. if the sector is not protected The sector protection status for all NVM blocks primary Flash memory or secondary Flash mem can also be read by the MCU accessing the Flash Protection registers in PSD I O space See 96 163 Flash Memory Sector Protect page 101 for regis ter definitions Reading the Erase Program Status Bits The Flash memory provides several status bits to be used by the MCU to confirm the completion of an Erase or Program cycle of Flash memory These status bits minimize the time that the MCU spends performing these tasks and are defined in Table 83 page 97 The status bits can be read as many times as needed For Flash memory the MCU can perform a READ operation to obtain these status bits while an Erase or Program instruction is being executed by the embedded algorithm See Programming Flash Memory page 98 for details Data Polling Flag DQ7 When erasing or pro gramming in Flash memory the Data Polling Flag Bit DQ7 outputs the complement of the bit being entered for programming writing on the DQ7 Bit Once the Program instruction or the WRITE oper ation is completed the true logic value is read on the Data Polling Flag Bit DQ7 in a READ opera tion Data Polling is effective after the fourth WRITE pulse for a Program instruction or after the sixth WRITE pulse for an Erase instruction It must be performed at the address being within the Flash ma n m
57. input OR gate whose inputs come from the CPLD AND Array enable product term and the Direction Register If the enable product term of any of the Array outputs are not defined and that port pin is not defined as a CPLD output in the PSDsoft then the Direction Register has sole control of the buffer that drives the port pin The contents of these registers can be altered by the MCU The Port Data Buffer PDB feedback path allows the MCU to check the contents of the registers Ports A B and C have embedded Input Macro cells IMC The Input Macrocells IMC can be configured as latches registers or direct inputs to the PLDs The latches and registers are clocked by Address Strobe ALE or a product term from the PLD AND Array The outputs from the Input Macrocells IMC drive the PLD input bus and can be read by MCU See Input Macrocell page 112 Port Operating Modes The I O Ports have several modes of operation Some modes can be defined using PSDsoft some by the MCU writing to the Control Registers in CSIOP space and some by both The modes that can only be defined using PSDsoft must be pro grammed into the device and cannot be enangad unless the i dynamically at ruWti Address Input and Peripheral Modes a are fo only modes that must be defined before program ming the device All other modes can be changed by the MCU at run time See Application No
58. is active the contents of the receive shift register are shifted to the left one position The value that comes in from the right is the value that was sampled at the RxD pin at 55 2 of the same machine cycle As data bits come in from the right 15 shift out to the left When the that was initially loaded into the right most position arrives at the left most po sition in the shift register it flags the RX Control block to do one last shift and load SBUF At S1P1 of the 10th machine cycle after the WRITE to SCON that cleared RI RECEIVE is cleared as RI is set 59 163 uPSD3212A uPSD3212C uPSD3212CV Figure 28 Serial Port Mode 0 Waveforms Shift TxD Shift Clock Clear RI More About Mode 1 Ten bits are transmitted through TxD or received through RxD a start Bit 0 8 data bits LSB first and a Stop Bit 1 On receive the Stop Bit goes into RB8 in SCON In the uPSD321x Devices the baud rate is deter mined by the Timer 1 or Timer 2 overflow rate Figure 29 page 61 shows a simplified functional diagram of the serial port in Mode 1 and associat ed timings for transmit receive Transmission is initiated by any instruction that uses SBUF as a inati egiste to SBUF signal sition of the transmit 9 alert Control unit that a transmission is requested Transmission actually commences at S1P1 of the machine cycle following the next rollover in the vide by 16
59. is disabled and the ADSF Interrupt takes over as INT1 INT1 must be configured as if it is an edge interrupt input The INP1 pin p3 3 is available for general func ADC S or Timer1 gate H C com Ladder Resistor Decod Conversion Complete Successive Interrupt Approximation Circuit 106627 65 163 uPSD3212A uPSD3212C uPSD3212CV Table 46 ADC SFR Memory Map Bit DOREM Name SFR Reg 8 bit ASCL Prescaler for ADC clock ADAT ADATS ADATA ADATS E ADATO p ei ADC Control Table 47 Description of the ACON Bits ADEN ADC Enable Bit A ADC shut off and consumes no operating current enable ADC Reserved ADS1 ADSO Analog channel select 0 0 Channel0 0 Channel1 ACH1 1 Channel2 ACH2 1 Channel3 ACHS 66 163 PULSE WIDTH MODULATION PWM The PWM block has the following features m Four channel 8 bit PWM unit with 16 bit prescaler m 8 bit unit with programmable frequency and pulse width m PWM Output with programmable polarity 4 channel PWM Unit PWM 0 3 The 8 bit counter of a PWM counts module 256 i e from 0 to 255 inclusive The value held the 8 bit counter is compared to the contents of the Special Function Register PWM 0 3 of the corre sponding PWM The polarity of the PWM outputs is programmable and selected by the PWML Bit in PWMCON register Provided the con
60. is required for the ADC logic Appropriate values need to be load ed into the prescaler based upon the main MCU clock frequency prior to use The processing of conversion starts when the Start Bit ADST is set to 1 After one cycle it is cleared by hardware The register ADAT contains the results of the A D conversion When conver sion is completed the result is loaded into the ADAT the A D Conversion Status Bit ADSF is set to 1 The block ARA RJ Figure 35 ADU A Figure 35 A D Block Diagram AVREF M ACHO 1 2 matically when conversion is completed cleared when A D conversion is in process The ASCL should be loaded with a value that re sults in a clock rate of approximately 6MHz for the ADC using the following formula see Table 48 page 66 ADC clock input fosc 2 Prescaler register value 1 Where fosc is the MCU clock input frequency The conversion time for the ADC can be calculat ed as follows ADC Conversion Time 8 clock 8bits Clock 10 67usec at 6MHz ADC Interrupt The ADSF Bit the register is set to 1 when the A D conversion is complete The status bit can be driven by the MCU or it can be config ured to generate a falling edge interrupt when the conversion is complete The ADSF Interrupt is enabled by setting the ADS FINT Bit in the PCON register Once the bit is set the external INT1 Interrupt
61. memory m SRAM The Memory Select signals for these blocks origi nate from the Decode PLD DPLD and are user defined in PSDsoft Express Primary Flash Memory and Secondary Flash memory Descripti The primary ran ANA 2 tors 16KBytes each Secondar ory is divided into 2 sectors 8KBytes each Each sector of either memory block can be separately protected from Program and Erase cycles Flash memory may be erased on a sector by sec tor basis Flash sector erasure may be suspended while data is read from other sectors of the block and then resumed after reading During a Program or Erase cycle in Flash memory the status can be output on Ready Busy PC3 This pin is set up using PSDsoft Express Configu ration uPSD3212A uPSD3212C uPSD3212CV Memory Block Select Signals The DPLD generates the Select signals for all the internal memory blocks see PLDs page 106 Each of the eight sectors of the primary Flash memory has a Select signal FSO FS3 which can contain up to three product terms Each of the 2 sectors of the secondary Flash memory has a Se lect signal CSBOOTO CSBOOT 1 which can con tain up to three product terms Having three product terms for each Select signal allows a given sector to be mapped in Program or Data space Ready Busy PC3 This signal can be used to output the Ready Busy status of the Flash memo ry The output on Ready Busy PC3 is a 0 Busy when Flash memory is being writte
62. polling sequence determines which request is serviced Thus within each priority level there is a second priority structure determined by the polling se quence Interrupts Enable Structure Each interrupt source can be individually enabled or disabled by setting or clearing a bit in the inter enable special function register IE and IEA All interrupt source can also be globally disabled by the clearing Bit EA in IE see Table 19 Please see Tables 20 21 22 and 23 for individual bit de scriptions ____ CO ASI ____ Int1 Table 19 SFR Register 9 lowest SFR Reg Bit Register Name Comments 2 Interrupt Enable 23 2 Interrupt 36 163 uPSD3212A uPSD3212C uPSD3212CV Table 20 Description of the IE Bits Disable all interrupts 0 no interrupt with be acknowledged 1 each interrupt source is individually enabled or disabled by setting or clearing its enable bit 8 qme T Enable Timer 2 Interrupt Table 21 Description of the IEA Bits m ma wes _ _ x s ws _ _ _ _ m MWNA DDIT C __ ___ Table 22 Description the IP nn 4 S Timer 1 Interrupt priority level
63. received data in the Flash memory sector that was being erased is invalid Resume Sector Erase Suspend Sector Erase instruction was previously executed the erase cycle may be resumed with this instruction The Resume Sector Erase instruction consists of writing O30h to any address while an appropriate Sector Select 50 53 or CSBOOTO CSBOOT 1 is High See Table 82 page 95 Specific Features Flash Memory Sector Protect Each primary and secondary Flash memory sector can be sepa rately protected against Program and Erase cy cles Sector Protection provides additional data security because it disables all Program or Erase cycles This mode can be activated through the JTAG Port or a Device Programmer Sector protection can be selected for each sector using the PSDsoft Express Configuration pro gram This automatically protects selected sectors when the device is programmed through the JTAG Port or a Device Programmer Flash memory sec tors can be unprotected to allow updating of their contents using the JTAG Port a Device grammer The MCU can read but cannot change the sector protection bits Any attempt to program or erase a protected Flash memory sector is ignored by the device The Verify operation results in a READ of the protected data This allows a guarantee of the retention of the Pro tection status The sector protection status can be read by the MCU through the Flash memory protection r
64. register but also by the output enable product term from the PLD AND Array If the out put enable product term is not active the Direction Register has sole control of a given pin s direction An example of a configuration for a Port with the three least significant bits set to output and the re mainder set to input is shown in Table 95 Since Port D only contains two pins shown in Figure 64 page 121 the Direction Register for Port D has only two bits active Drive Select Register The Drive Select Register configures the pin driver as Open Drain or CMOS for some port pins and controls the slew rate for the other port pins An external pull up resistor should be used for pins configured as Open Drain A pin can be configured as Open Drain if its corre sponding bit in the Drive Select Register is set to 1 The default pin drive is CMOS 116 163 Note The slew rate is a measurement of the rise and fall times of an output A higher slew rate means a faster output response and may create more electrical noise A pin operates in a high slew rate when the corresponding bit in the Drive Reg ister is set to 1 The default rate is slow slew Table 96 page 117 shows the Drive Register for Ports A B C and D It summarizes which pins can be configured as Open Drain outputs and which pins the slew rate can be set for Table 92 Port Configuration Registers PCR Register Name Port MCU Access Control WRITE R
65. the Bulk Erase instruction the Flash memory does not accept any instructions Flash Sector Erase The Sector Erase instruc tion uses six WRITE operations as described in Table 82 page 95 Additional Flash Sector Erase codes and Flash memory sector addresses can be written subsequently to erase other Flash memory sectors in parallel without further coded cycles if the additional bytes are transmitted in a shorter time than the time input new out period The status of the internal timer can be monitored through the level of the Erase Time out Flag Bit 003 If the Erase Time out Flag DQ3 is 0 the Sector Erase instruction has been received and the time out period is counting If the Erase Time out Flag DQ3 is 1 the time out period has expired and the embedded algorithm is busy erasing the Flash memory sector s Before and during Erase time out any instruction other than Suspend Sector Erase and Resume Sector Erase instructions abort the cycle that is currently in progress and reset the device to READ Mode During a Sector Erase the memory status may be checked by reading the Error Flag Bit DQ5 the Toggle Flag Bit DQ6 and the Data Polling Flag Bit DQ7 as detailed in Programming Flash Memory page 98 100 163 During execution of the Erase cycle the Flash memory accepts only RESET and Suspend Sec tor Erase instructions Erasure of one Flash mem ory sector may be suspen
66. the soft ware will fail to reload the timer This failure will re sult in a reset upon overflow thus preventing the processor running out of control In the Idle Mode the watchdog timer and reset cir cuitry remain active The WDT consists of a 22 bit counter the Watchdog Timer RESET WDRST SFR and Watchdog Key Register WDKEY Since the WDT is automatically enabled while the processor is running the user only needs to be concerned with servicing it The 22 bit counter overflows when it reaches 4194304 The increments once every machine cycle This means the user must reset the WDT at least every 4194304 machine cycles 1 258 seconds at 40 2 To reset the WDT the user must write value between 00 7EH to the WDRST register The value that is written to the WDRST is loaded to the 7MSB of the 22 bit counter This allows the user to pre loaded the counter to an initial value to generate a flexible Watchdog time out period Writing a 00 to WDRST clears the counter The watchdog timer is controlled by the watchdog key register WDKEY Only pattern 01010101 55 disables the watchdog timer The rest of pattern combinations will keep the watchdog timer enabled This security key will prevent the watch dog timer from being terminated abnormally when the function of the watchdog timer is needed In Idle Mode the oscillator continues to run To prevent the WDT from resetting the processor while
67. this E MOS Made signal High disables the Flash memory SRAM m CPLD Output External Chip Select ECS1 and CSIOP ECS2 Port D pins can be configured in PSDsoft Express as input pins for other dedicated functions m as input to the macrocells flip flops and APD counter Figure 63 Port D Structure DATA OUT REG DATA OUT PORT D PIN OUTPUT MUX ECS 2 1 MCU DATA BUS ENABLE PRODUCT TERM OE CPLD INPUT 06606 120 163 External Chip Select The CPLD also provides two External Chip Select ECS1 ECS2 outputs on Port D pins that can be used to select external devices Each External Chip Select 51 52 consists of one product Figure 64 Port D External Chip Select Signals POLARITY BIT PLD INPUT BUS CPLD AND ARRAY ENABLE OE ENABLE OE uPSD3212A uPSD3212C uPSD3212CV term that can be configured active High or Low The output enable of the pin is controlled by either the output enable product term or the Direction Register See Figure 64 DIRECTION REGISTER 106607 121 163 uPSD3212A uPSD3212C uPSD3212CV POWER MANAGEMENT PSD MODULE offers configurable power sav ing options These options may be used individu ally or in combinations as follows The primary and secondary Flash memory and SRAM blocks are built with power management technology In addition to using sp
68. to the high nibble of the Accumulator and the ones digit to the low nibble uPSD3212A uPSD3212C uPSD3212CV Table 5 Logical Instructions peration Dr id Reg imm X X X _ AAA X X x gt C wawe mcer x _ _ X x gt X X x gt X messem won mews _ bble A Accumulator on 19 163 uPSD3212A uPSD3212C uPSD3212CV Data Transfers Internal RAM Table 6 shows the menu of in structions that are available for moving data around within the internal memory spaces and the addressing modes that can be used with each one The MOV dest src instruction allows data to be transferred between any two internal RAM or SFR locations without going through the Accumulator Remember the Upper 128 bytes of data RAM can be accessed only by indirect ad dressing and SFR space only by direct address ing Note uPSD321x Devices the stack resides in on chip RAM and grows upwards The PUSH in struction first increments the Stack Pointer SP then copies the byte into the stack PUSH and POP use only direct addressing to identify the byte being saved or restored but the stack itself is ac cessed by indirect addressing using the SP regis ter This means the stack can go into t
69. with two external interrupt pins Single Supply Voltage 4510 5 5V 3 0 to 3 6V 1 163 uPSD3212A uPSD3212C uPSD3212CV Table 1 Device Summary 8032 Vcc Bus V armo ww com ST 2 163 uPSD3212A uPSD3212C uPSD3212CV TABLE OF CONTENTS FEATURES SUMMARY 24 1 SUMMARY 7 52 PIN 12 ARCHITECTURE OVERVIEW en cade ede TERT S 13 Memory Organization s El fi E RA A Ex mE e PDT Program 2 2 Data memory scel I XR Tr RENE EUR UR RAM uyapi usa khas 2 2 5 4 SFR EEUU Addressing Modes 2 2 Arithmetic Instructions 2 Rr Logical Instructions Poked ou dene Data Transfers cer e xe lera wawa xe dm ET Boolean
70. 0 00 34 56 78 12 2 00 00 12 56 78 34 A 2Dh 00 00 12 34 78 56 2 00 00 12 34 56 78 Table 9 Shifting Number One Digit to the Right 2A 2Eh MO 0 loop for R1 2 2 LOOP MOV A R1 XCHD A R0 SWAP A MOV R1 A DEC R1 DEC RO CNJE R1 2Ah LOOP loop for R1 2Dh loop for R1 2Ch loop for R1 2 2Bh CLR A XCH A 2Ah 2B 2C 2D 2E ACC 00 12 34 56 78 78 00 12 34 58 78 76 00 12 34 58 78 67 00 12 34 58 67 67 00 12 34 58 67 67 00 12 34 58 67 67 00 12 34 58 67 67 00 12 38 45 67 45 00 18 23 45 67 23 08 01 23 45 67 01 08 01 23 45 67 00 00 01 23 45 67 08 21 163 uPSD3212A uPSD3212C uPSD3212CV External RAM Table 10 shows a list of the Data Transfer instructions that access external Data Memory Only indirect addressing can be used The choice is whether to use a one byte address Ri where can be either RO or of the se lected register bank two byte address Note In all external Data RAM accesses the Ac cumulator is always either the destination or source of the data Lookup Tables Table 11 shows the two instruc tions that are available for reading lookup tables in Program Memory Since these instructions access only Program Memory the lookup tables can only be read not updated The mnemonic is MOVC for move constant The first MOVC instruction in Table 11 can accommo
71. 212A uPSD3212C uPSD3212CV that have a port architecture which is different from Ports 0 4 in the MCU Module The PSD Module communicates with the CPU Core through the internal address data bus 0 15 00 07 and control signals RD PSEN ALE RESET The user defines the De coding PLD in the PSDsoft Development Tool and can map the resources in the PSD Module to any program or data address space Port 3 UART Port 1 Timers and Intr 2 2nd UART Port 3 Port 1 8032 Core 12 3 Timer Counters 256 Byte SRAM 2 UARTs Interrupt MCU MODULE 4 PWM Dedicated USB Pins Reset Logic USB amp LVD amp WDT Transceiver 8032 Internal Bus Port 0 2 Ext 0 15 xi Bus RD PSEN Secondary gt Port D GPIO AI07426b 27 163 uPSD3212A uPSD3212C uPSD3212CV MCU MODULE DISCRIPTION This section provides a detail description of the MCU Module system functions and Peripherals including m Special Function Registers Timers Counter Interrupts PWM Supervisory Function LVD and Watchdog USART Power Saving Modes Bus On chip Oscillator ADC Ports Table 15 SFR Memory Map Special Function Registers A map of the on chip memory area called the Spe cial Function Register SFR space is shown in Ta ble 15 Note In
72. 8 Bit 7 Bit 0 Hardware Fixed 00h FFh SP Stack Pointer could be in 00h FFh 06638 Figure 9 PSW Program Status Word Register uPSD3212A uPSD3212C uPSD3212CV MSB PSW Carry Flag Auxillary Carry Flag General Purpose Flag LSB evlac rojRsi Rso ov P Reset Value oon Parity Flag Bit not assigned Overflow Flag Register Bank Select Flags to select Bank0 3 106639 program memory consists two Flash ory 64KByte Main Flash and 16KByte of Second ary Flash The Flash memory can be mapped to any address space as defined by the user in the PSDsoft Tool It can also be mapped to Data memory space during Flash memory update or programming After reset the CPU begins execution from loca tion 0000h As shown in Figure 10 each interrupt is assigned a fixed location in Program Memory The interrupt causes the CPU to jump to that loca tion where it commences execution of the service routine External Interrupt 0 for e 4 signed to locatio rn going to be used 8 tine 20 location 0003h If the interrupt is not going used its service location is available as general purpose Program Memory The interrupt service locations are spaced at 8 byte intervals 0003h for External Interrupt O 000Bh for Timer 0 0013h for External Interrupt 1 001Bh for Timer 1 and so forth If an interrupt ser vice routine is short enough as is often the cas
73. A PG READ program memory at A PC 22 163 Boolean Instructions The uPSD321x Devices contain a complete Bool ean single bit processor One page of the inter nal RAM contains 128 addressable bits and the SFR space can support up to 128 addressable bits as well All of the port lines are bit addressable and each one can be treated as a separate single bit port The instructions that access these bits are not just conditional branches but a complete menu of move set clear complement OR and AND instructions These kinds of bit operations are not easily obtained in other architectures with any amount of byte oriented software The instruction set for the Boolean processor is shown in Table 12 All bits accesses are by direct addressing Bit addresses 00h through 7Fh are in the Lower 128 and bit addresses 80h through FFh are in SFR space Note how easily an internal flag can be moved to a port pin MOV C FLAG 1 0 In this example FLAG is the name of any addres sable bit in the Lower 128 SFR space line the LSB of Port 1 in this case is set or cleared depending on whether the Flag Bit is 1 or 0 Accumulator of th 5 refer to Carry assemble as Carry specific instructions CLR C etc The Car ry Bit also has a direct address since it resides in the PSW register which is bit addressable Note The Boolean instruction set
74. AD Timing 5 Devices Symbol Parameter Conditions Ad a tRLQV PA RD to Data Valid tDVQV PA Data In to Data Out Valid tRHQZ PA RD to Data High Z Note 1 Any input used to select Port A Data Peripheral Mode 2 Data is already stable on Port A Table 134 Port A Peripheral Data Mode READ Timing 3V Devices Symbol Parameter tAVQV PA Address Valid to Data Valid tSLQV PA CSI Valid to Data Valid tRLQV PA RD to Data Valid tDVQV PA Data In to Data Out Valid 7 to Data High Z Note 1 Any input used to select Port A Data Peripheral Mode 2 Data is already stable on Port A 151 163 uPSD3212A uPSD3212C uPSD3212CV Figure 80 Peripheral I O WRITE Timing ALE N A D BUS ADDRESS DATA OUT tWLQV lt gt tWHQZ P tDVQV Wi VII N DATA OUT 06611 Table 135 Port A Peripheral Data Mode WRITE Timing 5 Devices Symbol Parameter tWLQV PA WR to Data Propagation Delay Data to Port A Data Propagation Delay twHQZ PA WR Invalid to Port A Tri state Note 1 Data stable Port 0 pins to data on Port A Table 136 Port Parameter tWLQV PA WR to Data Propagation Delay twHOZ PA WR Invalid to Port A Tri state Note 1 Data stable on 0 pins to data on Port A 152 163 uPSD3212A uPSD3212C uPSD3212CV Figure 81 Reset RESET Timing Vcc
75. Cycles A machine cycle consists of a sequence of six states numbered S1 through S6 Each state time lasts for two oscillator periods Thus a machine cycle takes 12 oscillator periods or 1s if the oscil lator frequency is 12MHz Refer to Figure 14 page 26 Each state is divided into a Phase 1 half and a Phase 2 half State Sequence in uPSD321x Devic es shows that retrieve execute sequences in states and phases for various kinds of instructions Normally two program retrievals are generated during each machine cycle even if the instruction being executed does not require it If the instruc tion being executed does not need more code bytes the CPU simply ignores the extra retrieval and the Program Counter is not incremented Execution of a one cycle instruction Figure 1 of the machine page 26 begins dyrin cycle i into the Instruc tio 545479 retri occurs during S4 esa ching cycler Execution is complete at the end of State 6 of this machine cycle The instructions take two machine cycles to execute No program retrieval is generated dur ing the second cycle of a MOVX instruction This is the only time program retrievals are skipped The retrieve execute sequence for MOVX instruc tion is shown in Figure 14 page 26 d Dn ne mm Accumulator only DUNZ e e Deorementandjumpifnotzero X X CJNE lt byte gt data rel Jump if byte z data lt lt 25 163
76. D is enabled used and should be set to zero 1 input to the PLD AND Array is connected Every change of CLKIN Bit 4 PLD Array clk PD1 the PLD when Turbo Bit is 0 2 CLKIN 1 input to PLD AND Array is disconnected saving power 0 2 on CLKIN PD1 input to the PLD macrocells is connected Bit 5 PLD MCell clk off 1 CLKIN PD1 input to PLD macrocells is disconnected saving power Not used and should be set to zero mE Not used and should be set to zero 124 163 uPSD3212A uPSD3212C uPSD3212CV Table 100 Power Management Mode Registers PMMR2 X Not used and should be set to zero X Not used and should be set to zero il x PLD Array on R input to the PLD AND Array is connected Bit 2 off WR input to PLD AND Array is disconnected saving power RD input to the PLD AND Array is connected Bit 3 1 off RD input to PLD AND Array is disconnected saving power lI II 5 0 PSEN input to the PLD AND Array is connected Bit 4 1 off PSEN input to PLD AND Array is disconnected saving power 0 ALE input to the PLD AND Array is connected Bit 5 off ALE input to PLD AND Array is disconnected saving power X Not used and should be set to zero X Not used and should be set to zero Note The bits of this register are cleared to zero following Power up Subsequent RESET puls
77. D3212A uPSD3212C uPSD3212CV PSD MODULE m The PSD Module provides configurable Program and Data memories to the 8032 CPU MCU In addition it has its own set of O ports and a PLD with 16 macrocells for general logic implementation m Ports and D are general purpose programmable ports that have a port architecture which is different from the ports in the MCU Module m The PSD Module communicates with the MCU Module through the internal address data bus 0 15 00 07 and control signals RD WR PSEN ALE RESET The user defines the Decoding PLD in the PSDsoft Development Tool and can map the resources in the PSD Module to any program or data address space Figure 46 shows the functional blocks in the PSD Module Functional Overview 512Kbit Flash memory This is the main Flash memory It is divided into 4 sectors 16KBytes each that can be accessed with user specified addresses Secondary 128Kbit Flash boot memory It is divided into 2 sectors 8KBytes each that can be accessed with user specified addresses This secondary memory bringsgs execute cod concurrently an external battery CPLD with 16 Output Micro Cells OMCs and up to 20 Input Micro Cells IMCs The CPLD may be used to efficiently implement a variety of logic functions for internal and external control Examples include state machines loadable shift registers and loadable counters
78. D3212C uPSD3212CV Mode 3 11 bits are transmitted through TxD or received through RxD a Start Bit 0 8 data bits LSB first a programmable 9th data bit and a Stop Bit 1 In fact Mode 3 is the same as Mode 2 in all respects except baud rate The baud rate in Mode 3 is variable In all four modes transmission is initiated by any instruction that uses SBUF as a destination regis ter Reception is initiated in Mode 0 by the condi tion RI 2 0 and REN 1 Reception is initiated in the other modes by the incoming start bit if REN 1 Multiprocessor Communications Modes 2 and 3 have a special provision for multi processor communications In these modes 9 data bits are received The 9th one goes into RB8 Then comes a Stop Bit The port can be pro grammed such that when the Stop Bit is received the serial port interrupt will be activated only if RB8 lt 1 This feature is enabled by setting Bit SM2 in SCON A way to use this feature in multi proces Sor systems is as follows When the master processor wants to transmit a block of data to one of several slaves it first sends out an address byte which identifies the target slave An address byte differs from a data byte in t the 9th bit is T inan byte and 0 in a slave will be interrupt yte however will cH slave can exam ine the byte and see if it is being ad dressed The addressed slave will clear its SM2 Bit and prepare to receive the data bytes
79. Drive Register uPSD3212A uPSD3212C uPSD3212CV Register Bits are not set writing to the macrocell loads data to the macrocell flip flops See PLDs page 106 OMC Mask Register Each OMC Mask Register Bit corresponds to an Output Macrocell OMC flip flop When the OMC Mask Register Bit is set to a 1 loading data into the Output Macrocell flip flop is blocked The default value is 0 or un blocked Input Macrocells IMC The Input Macrocells IMC can be used to latch or store external inputs The outputs of the Input Macrocells IMC are rout ed to the PLD input bus and can be read by the MCU See PLDs page 106 Enable Out The Enable Out register can be read by the MCU It contains the output enable values for a given port 1 indicates the driver is out put mode A 0 indicates the driver is in tri state and the pin is in input mode Bit 2 Bit 1 Port A Note 1 NA Not Applicable Table 97 Port Data Registers Slew Slew Rate Data Out A B C D WRITE READ READ outputs of macrocells Output Macrocell WRITE loading macrocells flip flop Mask Macrocell WRITE READ prevents loading into a given macrocell Input Macrocell READ outputs of the Input Macrocells Enable Out READ the output enable control of the port driver 117 163 uPSD3212A uPSD3212C uPSD3212CV Ports and B Functionality and Structure Ports A and B have similar functionality and struc ture
80. EAD A B C D WRITE READ Drive Select A B C D WRITE READ Note 1 See Table 96 page 117 for Drive Register Bit definition Table 93 Port Pin Direction Control Output Enable P T Not Defined Direction Register Bit Port Pin Mode 0 Input 94 gt Port Pin Direction Control Output Enable P T Defined Direction Output Enable Register Bit P T Port Pin Mode Input s Cj em 7 Jom Table 95 Port Direction Assignment Example Bit7 Bit6 Bit4 Bit2 Bit1 Bit 0 0 0 0 1 1 1 Port Data Registers The Port Data Registers shown in Table 97 are used by the MCU to write data to or read data from the ports Table 97 shows the register name the ports having each register type and MCU access for each register type The registers are described below Data In Port pins are connected directly to the Data In buffer In MCU Input Mode the pin in put is read through the Data In buffer Data Out Register Stores output data written by the MCU in the MCU I O Output Mode The con tents of the Register are driven out to the pins if the Direction Register or the output enable product term is set to 1 The contents of the register can also be read back by the MCU Output Macrocells OMC The CPLD Output Macrocells OMC occupy a location in the MCU s address space The MCU can read the output of the Output Macrocells OMC If the OMC Mask Table 96 Drive Register Pin Assignment
81. Function Registers Sixteen address in the SFRs space are both byte and bit addressable The bit addressable SFRs are those whose address ends in Oh and 8h The bit addresses in this area are 80h to FFh Table 3 RAM Address Byte Address Byte Address in Hexadecimal in Decimal 1 FFh 255 30h 48 msb Bit Address Hex 156 rr re o r6 rr rers pre p pre p p on sr e eo sc es se or ee s e 5 lt lt 2Ah 57 56 55 153 52 P er e s se e eo am sr se sc 5 ss or se ss se o e an ar se o se o on or e s se 5 se ere 5 rps pep pepe or ue o o 2m or os is os os 1Fh 31 Register Bank 3 18h 24 17h 23 Register Bank 2 10h 16 OFh 15 Register Bank 1 08h 8 07h 7 Register Bank 0 00h 0 16 163 Addressing Modes The addressing modes in uPSD321x Devices in struction set are as follows Direct addressing Indirect addressing Register addressing Register specific addressing Immediate constants addressing Indexed addressing 1 Direct addressing In a direct addressing the operand is specified by an 8 bit address field in the instruction Only internal Data RAM and SFRs 80 RAM can be directly addr
82. JTAG compliant and can be used for In System Programming ISP For more information on the JTAG Port see PROGRAMMING IN CIR CUIT USING THE JTAG SERIAL INTERFACE page 127 uPSD3212A uPSD3212C uPSD3212CV Figure 60 Peripheral I O Mode 00 07 DATA BUS REGISTER 7 PA0 PA7 02886 MCU I O PLD I O McellAB Outputs No McellBC Outputs Yes Additional Ext CS Outputs No PLD Inputs Yes Yes tes e UAI C re JTAG ISP Note 1 JTAG pins TMS TCK TDI TDO are dedicated pins 2 Port is not available in the 52 pin package 3 On pins PC2 PC3 PC4 and PC7 only Table 90 Port Operating Mode Settings Control Register Direction Register Defined PSDsoft Setting Setting VM Register Setting 1 output MCU I O Declare pins only 0 input Note 1 N A PLD I O Logic equations Address Declare pins onl Port A B P y Peripheral I O Logic equations M Port A PSELO amp 1 PIO Bite Note N A Not Applicable Note 1 The direction of the Port A B C and D pins are controlled by the Direction Register ORed with the individual output enable product term from the CPLD AND Array Table 91 Port Latched Address Output Assignments Port A PA3 PAO Port PA7 PA4 Port B PB3 PBO Port B PB7 PB4 Address a3 a0 Address a7 a4 Address a3 a0 Address a7 a4 115 163
83. KIN PD1 from the APD Unit All memories enter Standby Mode and are drawing standby current However the PLD and I O ports blocks do not go into Standby Mode because you don t want to have to wait for the logic and I O to wake up before their outputs can change See Table 98 for Power down Mode effects on PSD MODULE ports uPSD3212A uPSD3212C uPSD3212CV Typical standby current is of the order of microamperes These standby current values assume that there are no transitions on any PLD input Other Power Saving Options The PSD MOD ULE offers other reduced power saving options that are independent of the Power down Mode Except for the SRAM Standby and PSD Chip Se lect Input CSI PD2 features they are enabled by setting bits in and PMMR2 Figure 66 Enable Power down Flow Chart RESET Enable APD Set PMMRO Bit 1 1 OPTIONAL Disable desired inputs to PLD by setting PMMRO bits 4 and 5 and PMMR2 bits 2 through 6 Yes PSD Module in Power Down Mode 06609 Table 98 Power down 5 Ports Port Function Pin Level MCU I O No Change PLD Out No Change Address Out Undefined Peripheral Tri State 123 163 uPSD3212A uPSD3212C uPSD3212CV PLD Power Management The power and speed of the PLDs are controlled by the Turbo Bit Bit 3 in PMMRO see Table 99 By setting the bit to 1 the Turbo Mode is off and the PLDs consume the specifi
84. Memory Note 1 X Not guaranteed value can be read either 1 or 0 2 007 000 represent the Data Bus bits 07 00 3 FS0 FS3 and CSBOOTO CSBOOT are active High 97 163 uPSD3212A uPSD3212C uPSD3212CV Programming Flash Memory Flash memory must be erased prior to being pro grammed A byte of Flash memory is erased to all 15 FFh and is programmed by setting selected bits to 0 The MCU may erase Flash memory all at once or by sector but not byte by byte Howev er the MCU may program Flash memory byte by byte The primary and secondary Flash memories re quire the MCU to send an instruction to program a byte or to erase sectors see Table 82 Once the MCU issues a Flash memory Program or Erase instruction it must check for the status bits for completion The embedded algorithms that are invoked support several means to provide status to the MCU Status may be checked using any of three methods Data Polling Data Toggle or Ready Busy PC3 Data Polling Polling on the Data Polling Flag Bit DQ7 is a method of checking whether a Program or Erase cycle is in progress or has completed Figure 48 shows the Data Polling algorithm When the MCU issues a Program instruction the embedded algorithm begins The MCU then reads the location of the byte to be programmed in Flash memory to check status The Data Polling Flag Bit 007 of this location becomes the complement of 7 ofthe original data byte to be prog r
85. Note 1 Class description A Class is STMicroelectronics internal specification All of its limits are higher than the JEDEC specifications This means when a device belongs to Class it exceeds the JEDEC standard Class B strictly covers all of the JEDEC criteria International standards ww com ST 132 163 AND 5 This section summarizes the operating surement conditions and the DC and AC charac teristics of the device The parameters in the DC and AC Characteristic tables that follow are de rived from tests performed under the Measure Table 109 Operating Conditions 5V Devices Parameter uPSD3212A uPSD3212C uPSD3212CV ment Conditions summarized in the relevant tables Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parame ters Supply Voltage Table 110 Operating Conditions 3V Devices Parameter Symbol Voc Supply Voltage Ambient Operating Temperature Commercial Ambient Operating Temperature Industrial A Table 111 AC Signal Letter Symbols for Signal Letters Avava DI YI c eA DOT Input Output M Output Macrocell MN Note Example Time from Address Valid to ALE Invalid Symbol
86. ON loH 1pA Low Voltage RESET 0 1V hysteresis XTAL Open Bias Voltage XTAL1 XTAL2 loL 3 2mA for Flash Erase and SRAM PSD Standby Voltage SRAM PSD Data Retention 1 Logic 0 Input Current 0 45 Ports 1 2 3 4 Port 4 pin 21 Logic 1 10 0 Transition Current Vin 3 5V Ports 1 2 3 4 2 5V for Port 4 pin 21 Only on 136 163 uPSD3212A uPSD3212C uPSD3212CV Test Condition in addition to those in Table 109 page 133 EE PSD Standby Current PSD Idle Current IDLE VsTBY fiw Vcc gt RESET Pull up Current VIN Vss XTAL Feedback Resistor XTAL1 Vcc Current XTAL1 XTAL2 Vss m Output Leakage Current 0 45 lt VouT lt Vcc Vcc 5 5V Power down Mode LVD logic disabled LVD logic enabled Active 12MHz Vcc 5V Idle 12MHz Symbol Parameter AWAY NR Jl PLD TURBO a f PLD Only PLD_TURBO On f OMHz Operating Supply Current During Flash memory 15 Flash WRITE Erase memory PLD PLD AC Base Base Note 4 mA mA Note 1 Ipp Power down Mode is measured with XTAL1 Vss XTAL2 not connected RESET Vcc Port 0 Vcc all other pins are disconnected PLD in Turbo Mode lcc cPu active mode is measured with XTAL1 driven with tci cH tcHcL 5ns Vss 0 5V Voc 0 5 XTAL2 not connected RESET Vss Port 0 Vcc all
87. OT 1 is High ww com ST 94 163 uPSD3212A uPSD3212C uPSD3212CV Table 82 Instructions 50 53 or Instruction CSBOOTO 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 CSBOOT1 Read 5 READ RD RA READ Sector AAh 55h 90h Read status Protection 8 11 X555h XAAAh 555 Program a Flash AAh 55h A0h Byte 11 X555h XAAAh 555 PA Flash Sector AAh 55h 80h 55h 30h 717 555 555 AAh Flash AAh 55h 80h 55h 10h Erase X555h X555h AAh X555h XAAAh X555h 2 Sector BOho 9 XXXXh 30h Erase XXXXh Note 1 All bus cycles are WRITE bus cycles except the ones with the Read label 2 All values are in hexadecimal 3 X Don t care Addresses of the form in this table must be even addresses 4 RA Address of the memory location to be read 5 RD Data READ from location RA during the READ cycle 6 Address of the memory location Addr are latched on the falling 6089 trobe WR CNTLO 7 PA is an ev g QNS 8 PD Data w ed fy 5 1 on th Strob relie 9 SA Address of S 10 verified The Se the sector to erased or verified must be Active High 10 Sector Select FS0 FS3 or CSBOOTO CSBOOT1 signa
88. RT 1 When set causes the serial port to use Timer 2 overflow pulses for its transmit clock in Modes 1 and 3 TCLK 0 causes Timer 1 overflow to be used for the transmit clock Timer 2 External Enable Flag When set allows a capture or reload to occur as a result of a negative transition on T2EX if Timer 2 is not being used to clock the serial port EXEN2 0 causes Time 2 to ignore events at T2EX Start stop control for Timer 2 A logic 1 starts the timer 1 Timer or Counter Select for Timer 2 Cleared for timer operation input from internal System clock tcpu set for external event counter operation negative edge triggered Capture Reload Flag When set capture will occur on negative transition of T2EX if CP RL2 EXEN2 1 When cleared auto reload will occur either with Tlmer 2 overflows or negative transitions 2 when EXEN2 1 When either RCLK RCLK1 1 TCLK TCLK 1 this bit is ignored and timer is forced to auto reload on Timer 2 overflow Note 1 The RCLK1 and TCLK1 Bits in the PCON Register control UART 2 and have the same function as RCLK and TCLK 52 163 uPSD3212A uPSD3212C uPSD3212CV Figure 24 Timer 2 in Capture Mode Timer 2 Interrupt Transition Detector T2EX pin Control EXEN2 106625 Figure 25 2 Auto Reload Mode 2 Interrupt Transition Detector T2EX pin Control EXEN2 06626 53 163 uPSD3212A
89. Revision History Updates port information Table 30 interface information Figure 30 Table 44 remove 04 Mar 03 programming guide PSD Module information Table 82 PLD information Figure 55 electrical characteristics Table 114 115 131 132 02 Sep 03 Update references for Product Catalog 03 Feb 04 Reformatted correct package dimensions Table 145 02 July 04 Reformatted add EMC characteristics information Table 106 107 108 04 Nov 04 Updates per requested data brief changes Figure 3 4 Table 1 2 113 Add USB feature to document Figure 2 3 4 15 16 18 20 40 41 42 43 44 45 Table 03 Dec 04 1 2 15 16 18 19 21 23 24 25 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 146 ww com ST 162 163 uPSD3212A uPSD3212C uPSD3212CV ww com ST Information furnished is believed to be accurate and reliable However STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics Specifications mentioned in this publication are subject to change without notice This publication supersedes and replaces all information previously supplied STMicroelectronics products are not authorized for use as critical components in l
90. Serial Buffer 2nd UART Ctrl Register E 2 Serial Buffer Pot2 2 PWM NM Polarity PWMO PWMO Output Duty Cycle PWM1 PWM1 Output Duty Cycle 29 163 uPSD3212A uPSD3212C uPSD3212CV E EMi Ie zm Ri Pes tame Peg Name Comments PWM2 PWM2 Output Duty Cycle PWM3 PWM3 Output Duty WORST 2 Reset Interrupt Enable 2nd Interrupt PWM4P PWM 4 Pulse AE WDKEY Watch Dog Register Prescaler 0 com 5 Ses 2 Priority SL 1 C8 T2CON EXF2 RCLK EXEN2 CP RL2 Tiere Control 221 efe ae eload low efem rts tan ve or atus o 30 163 uPSD3212A uPSD3212C uPSD3212CV Bit Register Name SFR T q IEFI IOI IIIIIx III IIIIIFIXU EATA C 2 DC S2CON CRO Bus Control Reg 2 S2STA Stop Intr TX Md Bbusy Blost Bus Status Register 00 Accumulator 8 bit Prescaler for USB logic uDTt4 DTI 2 0074 USB Data UDTO UDTO 7 UDTO 6 UDTO 5 UDTO 4 UDTO 3
91. T 71 70 VREF 69 GND 68 RESET 66 PB7 64 P1 7 ADC3 63 PSEN 62 WR 61 P1 6 ADC2 1 P1 5 ADC1 P3 3 EXINT1 2 P1 4 ADCO PD1 CLKIN 3 P1 3 TXD1 ALE 4 A11 5 P1 2 RXD1 JTAG TDO 6 A10 JTAG TDI 7 P1 1 TX2 UsB 1 8 A9 PCA TERR 9 P1 0 T2 USB 10 A8 11 12 XTAL2 GND 13 XTAL1 PC3 TSTAT 14 AD7 2 15 P3 7 SCL1 JTAG TCK 16 AD6 NC 2 17 P3 6 SDA1 P4 7 PWM4 18 AD5 P4 6 PWM3 19 P3 5 T1 JTAG TMS 20 AD4 O O 21 22 P4 5 PWM2 23 5 24 P4 4 PWM1 25 4 26 LL P4 3 PWMO 27 LL 28 GND 29 T 31 2 321 P4 0 33 PA1 34 35 ADO 36 AD1 37 1 38 AD3 39 P3 4 TO 40 107424 Note 1 Pull up resistor required pin 8 2 for devices 7 5 for 5V devices 2 9 163 uPSD3212A uPSD3212C uPSD3212CV Table 2 80 Pin Package Pin Description External Bus ADO VO Multiplexed Address Data bus A1 D1 eeren x A ar sm ro ferao onen sr 0 confi L WWW kaa ASCOT TOT oe _ 7
92. Table 41 page 52 which are se lected by bits in the T2CON as shown in Table 42 page 52 In the Capture Mode there are two options which are selected by Bit 2 in T2CON if EXEN2 0 then Timer 2 is a 16 bit tim er or counter which upon overflowing sets Bit TF2 the Timer 2 overflow bit which can be used to gen erate an interrupt If EXEN2 1 then Timer 2 still does the above but with the added feature that a uPSD3212A uPSD3212C uPSD3212CV 1 to 0 transition at external input T2EX causes the current value in the Timer 2 registers TL2 and TH2 to be captured into registers RCAP2L RCAP2H respectively In addition the transition at T2EX causes Bit EXF2 in T2CON to be set and EXF2 like TF2 can generate an interrupt The Cap ture Mode is illustrated in Figure 24 page 53 In the Auto reload Mode there are again two op tions which are selected by bit EXEN2 in T2CON If 2 0 then when Timer 2 rolls over it not only sets TF2 but also causes the Timer 2 regis ters to be reloaded with the 16 bit value in regis ters RCAP2L and RCAP2H which are preset by software If EXEN2 1 then Timer 2 still does the above but with the added feature that 1 10 0 transition at external input T2EX will also trigger the 16 bit reload and set EXF2 The Auto reload Mode is illustrated in Standard Serial Interface UART Figure 25 page 53 The Baud Rate Gen eration Mode is selected by RCLK RCLK1 and or TCLK
93. Timer 0 Timer 1 Timer 2 PWM Units USART 8 bit ADC Interface USB Interface Note Interrupt or RESET terminates the Idle Mode Power Down Mode System Clock Halted LVD Logic Remains Active SRAM contents remains unchanged The SFRs retain their value until a RESET is asserted Note The only way to exit Power down Mode is a RESET Maintain Data Maintain Data Power down uPSD3212A uPSD3212C uPSD3212CV Power Control Register The Idle and Power down Modes are activated by software via the PCON register see Tables 26 and Table 27 page 40 Idle Mode The instruction that sets is the last in struction executed in the normal operating mode before Idle Mode is activated Once in the Idle Mode the CPU status is preserved in its entirety Stack pointer Program counter Program status word Accumulator RAM and All other registers maintain their data during Idle Mode There are three ways to terminate the Idle Mode Activation of any enabled interrupt will cause 0 to be cleared by hardware terminating Idle mode The interrupt is serviced and following return from interrupt instruction RETI the next instruction to be executed will be the one which follows the instruction that wrote a logic 1 to PCON O External hardware reset the hardware reset is required to be active for two machine cycle to complete the RESET operation internal reset
94. Typical If external battery is attached Sink Source Current VoL 0 25V 8 0 15V max lot 4 max Ports A B C and D 3 9V min 2 2 6V loH min PLD Macrocells For registered or 180pA with LVD 100HA with LVD gt 3 A mA PLD Inputs Inputs from pins macrocell feedback or MCU addresses PLD Outputs Output to pins or internal feedback PLD Propagation Delay Typical PLD input to output Turbo Mode 135 163 uPSD3212A uPSD3212C uPSD3212CV Table 114 DC Characteristics 5V Devices Test Condition in addition to those in Table 109 page 133 Input High Voltage Ports 1 2 3 4 Bits 7 6 5 4 3 1 0 XTAL1 4 5V lt Vcc lt 5 5V RESET oD A Ports A 4 5V lt Vee lt 55V Input Low Voltage Ports 1 2 3 4 Bits 7 6 5 4 3 1 0 XTAL1 4 5V lt Vcc lt 5 5V RESET Low IL1 lt lt 200A Output Low Voltage Vcc 4 5V Ports A B C D lo 8mA Vcc 4 5V Output Low Voltage Vott Ports 1 2 3 4 WR RD loL 1 6mA Output Low Voltag EE 3 ui e VU LX Output High Voltage Ports A B C D loH 2 Voc 4 5V V Output High Voltage _ OH 80pA on Ports 1 2 3 4 WR RD Output High Voltage Port 0 in _ lext Bus Mode ALE PSEN 80HA Output High Voltage VsTBY
95. Zt 855 4 33 163 uPSD3212A uPSD3212C uPSD3212CV INTERRUPT SYSTEM There are interrupt requests from 10 sources as follows see Figure 16 page 35 m INTO External Interrupt 2nd USART Interrupt Timer 0 Interrupt Interrupt INT1 External Interrupt or ADC Interrupt Timer 1 Interrupt USB Interrupt USART Interrupt Timer 2 Interrupt External IntO The INTO can be either level active or transition active depending on Bit ITO in register TCON The flag that actually generates this interrupt is Bit IEO in TCON When an external interrupt is generated the corresponding request flag is cleared by the hardware when the service routine is vectored to only if the interrupt was transition activated the interrupt was level activated then the interrupt request flag remains set until the requested interrupt is actually generated Then it has to deactivate the request before the interrupt service routine is qe else another Timer 0 and 1 Timer 0 Timer 1 Interrupts are generated by and TF1 which are set by an overflow of their respective Timer Counter registers except for Timer 0 in Mode 3 These flags are cleared by the internal hardware when the interrupt is serviced Timer 2 Interrupt 2 Interrupt is generated by TF2 which is set by an overflow of Timer 2 This flag has to be cleared by the software not by
96. able the PLDs This is a good alternative to using the APD Unit There is a slight penalty in memory access time when PSD Chip Select Input CSI PD2 makes its initial transition from deselected to selected The PMMRs can be written by the MCU at run time to manage power The PSD MODULE supports blocking bits in these registers that are set to block designated signals from reaching both PLDs Current consumption of the PLDs is directly related to the composite Unit is descri detail T frequency of the eir inputs see Built in logic Address 50 wdyshviag cdn be achieved by the MCU for activity If there is no activity for a certain time period MCU is asleep the APD Unit initiates Power down Mode if enabled Figure 65 APD Unit APD EN PMMRO 1 1 TRANSITION DETECTION ALE DETECT DISABLE FLASH SRAM 122 163 blocking signals that are used DPLD CPLD logic equations DISABLE BUS INTERFACE CSIOP SELECT FLASH SELECT SRAM SELECT POWER DOWN PDN SELECT 06608 The PSD MODULE has Turbo Bit in PMMRO This bit can be set to turn the Turbo Mode off the default is with Turbo Mode turned on While Turbo Mode is off the PLDs can achieve standby current when no PLD inputs are changing zero DC cur rent Even when inputs do change significant power can be saved at lower frequencies AC cur rent
97. ammed The MCU continues Data Polling Fla ror Flag Bit 2005 DQ7 matches b7 of the original dia and the Er ror Flag Bit DQ5 remains 0 the embedded algo rithm is complete If the Error Flag Bit DQ5 is 1 the MCU should test the Data Polling Flag Bit 007 again since the Data Polling Flag Bit DQ7 may have changed simultaneously with the Error Flag Bit DQ5 see Figure 48 The Error Flag Bit DQ5 is set if either an internal time out occurred while the embedded algorithm attempted to program the byte or if the MCU at tempted to program 1 to a bit that was erased not erased is logic 07 It is suggested as with all Flash memories to read the location again after the embedded program ming algorithm has completed to compare the 98 163 byte that was written to the Flash memory with the byte that was intended to be written When using the Data Polling method during an Erase cycle Figure 48 still applies However the Data Polling Flag Bit 097 is until the Erase cy cle is complete A 1 on the Error Flag Bit DQ5 in dicates a time out condition on the Erase cycle a 0 indicates no error The MCU can read any loca tion within the sector being erased to get the Data Polling Flag Bit DQ7 and the Error Flag Bit DQ5 PSDsoft Express generates ANSI C code func tions which implement these Data Polling algo rithms Figure 48 Data Polling Flowchart READ DQ5 amp DQ7 at VALID ADDRESS
98. are shown alongside each instruction al Data Memory Sga ki i Vu P ECOL SANE miu s x x lt X Jo x X 20 163 First pointers R1 and RO are set up to point to the two bytes containing the last four BCD digits Then aloop is executed which leaves the last byte loca tion 2EH holding the last two digits of the shifted number The pointers are decremented and the loop is repeated for location 2DH The CJNE in struction Compare and Jump if Not equal is a loop control that will be described later The loop executed from LOOP to CJNE for R1 2EH 2DH 2CH and 2BH At that point the digit that was orig inally shifted out on the right has propagated to lo cation 2AH Since that location should be left with Os the lost digit is moved to the Accumulator uPSD3212A uPSD3212C uPSD3212CV Table 7 Shifting a BCD Number Two Digits to the Right using direct MOVs 14 bytes 2A 2B 2C 2D 2E ACC MOV 2 00 12 34 56 78 78 MOV 2Eh 2Dh 00 12 34 56 56 78 MOV 2Dh 2Ch 00 12 34 34 56 78 MOV 2Ch 2Bh 00 12 12 34 56 78 MOV 2 0 00 00 12 34 56 78 Table 8 Shifting Number Two Digits to the Right using direct XCHs 9 bytes 2A 2B 2C 2D 2E ACC CLR A 00 12 34 56 78 00 A 2Bh 0
99. ble if unused from other Output Macrocells OMC The polarity of the product term is controlled by the XOR gate The Output Macrocell OMC can im plement either sequential logic using the flip flop element or combinatorial logic The multiplexer selects between the sequential or combinatorial logic outputs The multiplexer output can drive a port pin and has a feedback path to the AND Array inputs The flip flop in the Output Macrocell OMC block can be configured as a D T JK or SR type in PS Dsoft The flip flop s clock preset and clear inputs may be driven from a product term of the AND Ar ray Alternatively CLKIN PD1 can be used for the clock input to the flip flop The flip flop is clocked on the rising edge of CLKIN PD1 The preset and clear are active High inputs Each clear input can use up to two product terms Table 88 Output Macrocell Port and Data Bit Assignments Output Port Macrocell Assignment Native Product Terms Maximum Borrowed Product Terms Data Bit for Loading or Reading McellABO Port AO BO 3 6 DO McellAB2 McellAB3 McellAB4 Port A2 B2 Port A3 B3 5 V W BU pou _ _ NN MEN rs ww Y canna as SOT ee 16 poem McellAB6 McellAB7 Port A6 B6 Port A7 B7 Port Port B1 2 Port B2 C2 Port B3 C3 McellBCO McellBC1 McellBC2 McellBC3 McellBC4 McellBC5 McellBC6 McellBC7 Note 1 Mcell ABO McellAB7
100. blocked from writing to the associated Output Macrocells For example suppose McellABO are being used for a state machine You would not want a MCU write to McellAB to over write the state machine registers Therefore you would want to load the Mask Register for McellAB Mask Macrocell AB with the value OFh The Output Enable of the OMC The Output Macrocells block can be connected to an O port pin as a PLD output The output enable of each port pin driver is controlled by a single prod uct term from the AND Array ORed with the Direc tion Register output The pin is enabled upon Power up if no output enable equation is defined and if the pin is declared as a PLD output in PSD soft Express If the Output Macrocell OMC output is declared as an internal node and not as a port pin output in the PSDabel file the port pin can be used for other Figure 58 Input Macrocell AND ARRAY PLD INPUT BUS FEEDBACK I O functions The internal node feedback can be routed as an input to the AND Array Input Macrocells IMC The CPLD has 20 Input Macrocells IMC one for each pin on Ports A and B and four on Port C The architecture of the Input Macrocells IMC is shown in Figure 58 The Input Macrocells IMC are individually configurable and can be used as a latch register or to pass incoming Port signals prior to driving them onto the PLD input bus The outputs of the Input Ma
101. cHcL 518 Vss 0 5V 0 5V XTAL2 not connected RESET Vss Port 0 Vcc all other pins are disconnected Icc would be slightly higher if a crystal oscillator is used approximately 1mA 5 cPu Idle Mode is measured with 6 XTAL1 driven with tci cH tcHcL 5ns Vss 0 5V Vcc 0 5V XTAL2 not connected Port 0 Vcc 7 all other pins are disconnected 8 See Figure 68 page 128 for the PLD current calculation 9 current all I O pins are disconnected 139 163 uPSD3212A uPSD3212C uPSD3212CV Figure 71 External Program Memory READ Cycle tLHLL lt lt ALE N tAVLL E tPLPH tLLIV tPLIV PSEN tPXAV tPXIZ PORT 0 INSTR A0 A7 tAVIV 2 A8 A11 A8 A11 106848 Table 116 External Program Memory Characteristics with MCU Module Variable Oscillator 40MHz Oscillator 1 tcLcL 24 to 40MHz Symbol Parameter miss PANGAN LAY gt k lii ALE Low to valid instruction in 9 m few __ Input instruction float after PSEN Address valid after PSEN 2 Address to valid instruction in Address float to 5 Note 1 Conditions in addition to those in Table 109 page 133 Vcc 4 5 to 5 5V Vss
102. cks of the PSD MODULE Functional Block JTAG Programming Device Programmer Primary Flash Memory Secondary Flash Memory Secondary Flash Memory ww com 90 163 DEVELOPMENT SYSTEM The uPSD3200 is supported by PSDsoft a Win dows based software development tool Win dows 95 Windows 98 Windows NT PSD MODULE design is quickly and easily produced in a point and click environment The designer does not need to enter Hardware Description Language HDL equations unless desired to define PSD MODULE pin functions and memory informa tion The general design flow is shown in Figure 47 PSDsoft is available from our web site the ad Figure 47 PSDsoft Express Development Tool Define PSD Pin and Node Functions Point and click definition of PSD pin functions internal nodes and MCU system memory map Access HDL is available if needed MCU Firmware with PSD Module Configuration A composite object file is created containing MCU firmware and PSD configuration OBJ FILE PSD Programmer FlashLINK JTAG Point and click definition of combin atorial and registered logic in CPLD uPSD3212A uPSD3212C uPSD3212CV dress is given on the back page of this data sheet or other distribution channels PSDsoft directly supports a low cost device pro grammer from ST FlashLINK JTAG The pro grammer may be purchased through your local distributo
103. compared to when Turbo Mode is on When the Turbo Mode is on there is a significant DC cur rent component and the AC component is higher Automatic Power down APD Unit and Power down Mode The APD Unit shown in Figure 65 page 122 puts the PSD MODULE into Pow er down Mode by monitoring the activity of Ad dress Strobe ALE If the APD Unit is enabled as Soon as activity on Address Strobe ALE stops a four bit counter starts counting If Address Strobe ALE AS remains inactive for fifteen clock periods of CLKIN PD1 Power down PDN goes High and the PSD MODULE enters Power down Mode as discussed next Power down Mode By default if you enable the APD Unit Power down Mode is automatically en abled The device enters Power down Mode if Ad dress Strobe ALE remains inactive for fifteen periods of CLKIN PD1 The following should be kept in mind when the PSD MODULE is in Power down Mode If Address Stro ALE starts 1 the PSD M on Operating MO returns to normal Operating mode if either PSD Chip Select Input CSI PD2 is Low or the RESET input is High The MCU address data bus is blocked from all memory and PLDs Various signals can be blocked prior to Power down Mode from entering the PLDs by setting the appropriate bits in the PMMR registers The blocked signals include MCU control signals and the common CLKIN PD1 Note Blocking CLKIN PD1 from the PLDs does not block CL
104. contain zeros This condition flags the TX Control unit to do one last shift and then de 62 163 activate SEND and set TI This occurs at the 11th divide by 16 rollover after WRITE to SUBF Reception is initiated by a detected 1 10 0 transi tion at RxD For this purpose RxD is sampled at a rate of 16 times whatever baud rate has been es tablished When a transition is detected the di vide by 16 counter is immediately reset and 1FFH is written to the input shift register At the 7th 8th and 9th counter states of each bit time the bit detector samples the value of R D The value accepted is the value that was seen in at least 2 of the 3 samples If the value accepted during the first bit time is not 0 the receive circuits are reset and the unit goes back to looking for an other 1 to 0 transition If the Start Bit proves valid it is shifted into the input shift register and recep tion of the rest of the frame will proceed As data bits come in from the right 15 shift out to the left When the Start Bit arrives at the left most position in the shift register which in Modes 2 and 3 is a 9 bit register it flags the RX Control block to do one last shift load SBUF and 8 and set The signal to load SBUF and RB8 to set will be generated if and only if the following con ditions are met at the time the final shift pulse is generated RI 0 and d 9th data bit 1 ins
105. counter Thus the bit times are syn chronized to the divide by 16 counter not to the WRITE to SBUF signal The transmission begins with activation of SEND which puts the start bit at One bit time later DATA is activated which enables the output bit of the transmit shift register to TxD The first shift pulse occurs one bit time after that As data bits shift out to the right zeros are clocked in from the left see Figure 30 page 61 When the MSB of the data byte is at the output position of the shift register then the 1 that was initially loaded into the 9th position is just to the left of the MSB and all positions to the left of that contain ze ros This condition flags the TX Control unit to do one last shift and then deactivate SEND and set TI This occurs at the 10th divide by 16 rollover af ter WRITE to SBUF Reception is initiated by a detected 1 10 0 transi tion at RxD For this purpose RxD is sampled at a 60 163 Write to SBUF ee Send SSP L f fL RxD Data Out N X 01 X 02 X D3 X D4 X 05 X X 07 l f l T L s3P1 L seP1 Write to SCON A RI EO M4S o V Receive _______ ____ Shift n n nm mn mnm m RxD Data In 021 092 023 004 095 098 Mee 68 rL TL Transmit Receive 106825 rate of 16 times whatever baud rate has been 5 tablished When a tran
106. covers the clock from the incoming Table 60 USB Address Register UADR OEEh UN USBEN VAYN li Table 61 Description of the UADR Bits 0 Co orm USB data stream and is able to track jitter and fre quency drift according to the USB specification The SIE also translates the electrical USB signals into bytes or signals Depending upon the device USB address and the USB endpoint Address the USB data is directed to the correct endpoint on SIE interface The data transfer of this H W could be of type control or interrupt The device s USB address and the enabling of the endpoints are programmable in the SIE configura tion header USB related registers The USB block is controlled via seven registers in the memory UADR UCONO UCON1 UCON2 UISTA UIEN and USTA Three memory locations on chip which communi cate the USB block are m USB endpointO data transmit register UDTO m USB endpointO data receive register UDRO m USB endpoint1 data transmit register UDT1 USB Function Enable Bit When USBEN is clear the USB module will not respond to any tokens from host ESET clears this bit RESET clears these bits UADDS6 to R W Specify the USB address of the device UADDO 76 163 uPSD3212A uPSD3212C uPSD3212CV Table 62 USB Interrupt Enable Register UIEN OE9h DEBERE EE GEN 0
107. crocells IMC can be read by the MCU through the internal data bus The enable for the latch and clock for the register are driven by a multiplexer whose inputs are a product term from the CPLD AND Array or the MCU Address Strobe ALE Each product term output is used to latch or clock four Input Macro cells IMC Port inputs 3 0 can be controlled by one product term and 7 4 by another Configurations for the Input Macrocells IMC are specified by equations written in PSDsoft see Ap plication Note AN1 171 Outputs of the Input Mac rocells IMC can be read by the MCU via the IMC buffer See PORTS PSD MODULE page 113 DIRECTION REGISTER PIN PORT DRIVER INPUT MACROCELL 106603 112 163 572 PORTS PSD MODULE There are four programmable I O ports Ports A B C and D in the PSD MODULE Each of the ports is eight bits except Port D which is 3 bits Each port pin is individually user configurable thus al lowing multiple functions per port The ports are configured using PSDsoft Express Configuration or by the MCU writing to on chip registers in the CSIOP space Port A is not available in the 52 pin package The topics discussed in this section are m General Port architecture Port operating modes Port Configuration Registers PCR Port Data Registers Individual Port functionality General Port Architecture The general architecture of the Port bloc
108. curs and begins to float when a 100mV change from the loaded or level occurs lot and gt 20mA 155 163 uPSD3212A uPSD3212C uPSD3212CV Figure 85 External Clock Cycle 0 2 0 1 0 45 Figure 86 Recommended Oscillator Circuits CRYSTAL OSCILLATOR DRIVING FROM EXTERNAL SOURCE ca XTAL2 C1 External Oscillator XTAL1 Signal Note C1 C2 30pF 10pF for crystals or crystal osci manufactufer fo For ceramic resonators contact resonator manufacturer Oscillation circ Figure 87 PSD MODULE AC Measurement I O Figure 88 PSD MODULEAC Measurement Waveform Load Circuit XTAL2 XTAL1 e ceramic resonator have their own Que components 2 01 V Device Under Test 3 0V Test Point ov C 30 pF Including Scope and Jig Capacitance 1031040 1031030 Table 143 Capacitance Output Capacitance for input Note Sampled only 100 tested 1 Typical values are for TA 25 C and nominal supply voltages 156 163 uPSD3212A uPSD3212C uPSD3212CV PACKAGE MECHANICAL INFORMATION Figure 89 TQFP52 52 lead Plastic Thin Quad Flat Package Outline Note Drawing is not to scale 57 157 163 uPSD3212A uPSD3212C uPSD3212CV Table 144 52 52 lead Plastic Thin Quad
109. d i 10 ANL A lt byte gt will leave the Accumulator holding 00010001B The addressing modes that can be used to access the byte operand are listed in Table 5 The ANL A byte instruction may take any of the forms ANL A 7FH direct addressing ANL A R1 indirect addressing ANL A R6 register addressing ANL A 53H immediate constant Note Boolean operations can be performed on any byte in the internal Data Memory space with out going through the Accumulator The XRL byte data instruction for example offers quick and easy way to invert port bits as in XRL P1 0FFH 18 163 Accumulator only If the operation is in response to an interrupt not using the Accumulator saves the time and effort to push it onto the stack in the service routine Rotate instructiong C A etc shift the Ac right For a left rotatio to th B position For a rotation 158 rolls the MSB position The SWAP A instruction interchanges the high and low nibbles within the Accumulator This is a useful operation in BCD manipulations For exam ple if the Accumulator contains a binary number which is known to be less than 100 it can be quick ly converted to BCD by the following code MOVE B 10 DIV AB SWAP ADD Dividing the number by 10 leaves the tens digit in the low nibble of the Accumulator and the ones digit in the B register The SWAP and ADD instruc tions move the tens digit
110. d to connect the data bus to the AND Array as required in most standard PLD macrocell architectures TO OTHER I O PORTS CPLD MACROCELLS PLD INPUT BUS PT PRESET MCU DATA IN PRODUCT TERM ALLOCATOR PORTS LATCHED ADDRESS OUT PIN Ep 5 Pi IC 1 p POLARITY SELECT lt PR DI LD PT D T gt CLOCK COMB GLOBAL SELECT G CLOCK WYWYW PLD INPUT BUS CLOCK SELECT SELECT MACROCELL TO 1 0 PORT ALLOC CPLD OUTPUT PT OUTPUT ENABLE OE MACROCELL FEEDBACK PORT INPUT PT INPUT LATCH GATE CLOCK 106602 109 163 uPSD3212A uPSD3212C uPSD3212CV Output Macrocell OMC Eight of the Output Macrocells OMC are con nected to Ports A and B pins and are named as McellABO McellAB7 The other eight macrocells are connected to Ports B and C pins and are named as McellBCO McellBC7 If an McellAB out put is not assigned to a specific pin in PSDsoft the Macrocell Allocator block assigns it to either Port A or B The same is true for a McellBC output on Port B or C Table 88 shows the macrocells and port assignment The Output Macrocell OMC architecture is shown in Figure 57 As shown in the figure there are native product terms available from the AND Array and borrowed product terms availa
111. ded in order to read data from another Flash memory sector and then resumed Suspend Sector Erase When a Sector Erase cycle is in progress the Suspend Sector Erase in struction can be used to suspend the cycle by writ ing OBOh to any address when an appropriate Sector Select 50 53 or CSBOOTO CSBOOT1 is High See Table 82 page 95 This allows reading of data from another Flash memory sector after the Erase cycle has been suspended Sus pend Sector Erase is accepted only during an Erase cycle and defaults to READ Mode A Sus pend Sector Erase instruction executed during an Erase time out period in addition to suspending the Erase cycle terminates the time out period The Toggle Flag Bit DQ6 stops toggling when the internal logic is suspended The status of this bit must be monitored at an address within the Flash memory sector being erased The Toggle Flag Bit 006 stops toggling between 0 1us and 15 af ter the Suspend Sector Erase instruction has been executed The Flash memory is then automatically set to READ Mode n Suspend Sector r ction was exe cuted We o g S r Ffash memory sector that was being erased outputs invalid data Reading from a Flash sector that was being erased is valid The Flash memory cannot be programmed and only responds to Resume Sector Erase and Reset Flash instructions READ is an operation and is allowed Ifa Reset Flash instruction is
112. des are de scribed in the following text harduer ndn processor to routine Ls Timer 1 Run Control Bit Set cleared by software to turn Timer Counter on or off 5 TFO Timer 0 Overflow Flag Set by hardier on Timer Counter overflow Cleared by hardware when processor vectors to interrupt routine Timer 0 Run Control Bit Set cleared by software to turn Timer Counter on or off 3 IE1 Interrupt 1 Edge Flag Set by hardware when external interrupt edge detected Cleared when interrupt processed 2 Interrupt 1 Type Control Bit Set cleared by software to specify falling edge low level triggered external interrupt 1 IEO Interrupt 0 Edge Flag Set by hardware when external interrupt edge detected Cleared when interrupt processed ITO Interrupt O Type Control Bit Set cleared by software to specify falling edge low level triggered external interrupt Table 38 TMOD Register TMOD 48 163 uPSD3212A uPSD3212C uPSD3212CV Table 39 Description of the TMOD Bits m ter on 7 4 1 Timer 0 Gating control when set Timer Counter 1 is enabled only while pin is High TR1 control pin is set When cleared Timer 1 is enabled whenever TR1 control bit is set Timer or Counter selector cleared for timer operation input from internal system clock set for counter operation input from T1 input pin M1 M0 0 0 13 bit Timer Counter TH1 with TL1 as 5 bit prescaler
113. dge Response Flag ACK_REP This bit is set when the receiver transmits the not acknowledge signal This bit is reset when the receiver transmits the acknowledge signal Mode Flag bit is set when plays role the Slave Mode otherwise this bit is reset Note 1 Interrupt Flag Bit INTR S2STA Bit 5 is cleared by Hardware as reading S2STA register 2 Interrupt Flag INTR can occur in below case Table 55 Data Shift Register S2DAT7 S2DAT6 S2DAT5 S2DAT4 S2DAT3 S2DAT2 S2DAT1 S2DAT0 74 163 57 uPSD3212A uPSD3212C uPSD3212CV Address Register S2ADR This 8 bit register may be loaded with the 7 bit the unit to specify the start stop detection time slave address to which the controller will respond to work with the large range of MCU frequency val when programmed as a slave receive transmitter ues supported For example with a system clock The Start Stop Hold Time Detection and System of 40MHz Clock registers Tables 57 and 58 are included in Table 56 Address Register Note SLA6 to SLAO Own slave address 57 Start Stop Hold Time Detection Register S2SETUP Register Name Reset Value S2SETUP LE E control the start stop hold time detection for the multi master module in Slave Mode Table 58 System Cock of 40MHz S1SETUP Number of Sample S2SETUP Register Clock fosc 2 gt Value 50ns 50ns When Bit 7 enable bit 0 the
114. e in control applications it can reside entirely within that 8 byte interval see Figure 10 Longer service routines can use a jump instruction to skip over subsequent interrupt locations if other interrupts are in use Data memory The internal data memory is divided into four phys ically separated blocks 256 bytes of internal RAM 128 bytes of Special Function Registers SFRs areas and 2K bytes XRAM PSD in the PSD ule has a battery ba k data tof e h e ba RAM Four register banks each 8 registers wide occupy locations 0 through 31 in the lower RAM area Only one of these banks may be enabled at a time The next 16 bytes locations 32 through 47 con tain 128 directly addressable bit locations The stack depth is only limited by the available internal RAM space of 256 bytes XRAM PSD The 2K bytes of XRAM PSD resides in the PSD Module and can be mapped to any address space through the DPLD Decoding PLD as defined by the user in PSDsoft Development tool The XRAM that allow the of a power lost Port C PC2 pin This pin must be configured in PSDSoft to be bat tery back up Figure 10 Interrupt Location of Program Memory 008Bh Interrupt Location 0013h 8 Bytes 000Bh 0003h Reset 0000h 106640 15 163 uPSD3212A uPSD3212C uPSD3212CV SFR The SFRs can only be addressed directly in the address range from 80h to Table 15 page 28 gives an overview of the Special
115. e time out pe riod Some instructions are structured to include READ operations after the initial WRITE opera tions The instruction must be followed exactly Any in valid combination of instruction bytes or time out between two consecutive bytes while addressing Flash memory resets the device logic into READ Mode Flash memory is read like a ROM device The Flash memory supports the instructions sum marized in Table 82 page 95 Flash memory m Erase memory by chip or sector Suspend or resume sector erase Program a Byte RESET to READ Mode Read Sector Protection Status These instructions are detailed in Table 82 For ef ficient decoding of the instructions the first two bytes of an instruction are the coded cycles and are followed by an instruction byte or confirmation byte The coded cycles consist of writing the data AAh to address X555h during the first cycle and data 55h to address XAAAh during the second cle Address signals A15 A12 are Don t Care dur ing the instruction WRITE cycles However the appropriate Sector Select 50 53 or CSBOOT0 CSBOOT1 must be selected The primary and secondary Flash memories have the same instruction set The Sector Select signals determine which Flash memory is to receive and execute the instruction The primary Flash memo ry is selected if any one of Sector Select 50 FS3 is High and the secondary Flash memory is selected if any one of Sector Select CSBOOTO CSBO
116. ecial silicon design methodology power management technology puts the memories into Standby Mode when address data inputs are not changing zero DC current As soon asatransition occurs on an input the affected memory wakes up changes and latches its outputs then goes back to standby The designer does nothave to do anything special to achieve Memory Standby Mode when no inputs are changing it happens automatically The PLD sections can also achieve Standby Mode when its inputs are not changing as described in the sections on the Power Management Mode Registers PMMR As with the Power Management Mode the Automatic Power Down APD block allows the PSD MODULE to reduce to standby current automatically The APD Unit can also block MCU address data signals from reaching the memories and PLDs The APD Once in Power down Mode all address data signals are blocked from reaching memory and PLDs and the memories are deselected internally This allows the memory and PLDs to remain in Standby Mode even if the address data signals are changing state externally noise other devices on the MCU bus etc Keep in mind that any unblocked PLD input signals that are changing states keeps the PLD out of Standby Mode but not the memories PSD Chip Select Input CSI PD2 can be used to disable the internal memories placing them in Standby Mode even if inputs are changing This feature does not block any internal signals or dis
117. ed standby current when the inputs are not switching for an extended time of 70ns The propagation delay time is in creased by 10ns for device after the Turbo is set to 1 turned off when the inputs change at a composite frequency of less than 15MHz When the Turbo Bit is reset to 0 turned on the PLDs run at full power and speed The Turbo Bit affects the PLD s DC power AC power and prop agation delay When the Turbo Mode is off the uPSD3200 input clock frequency is reduced by 5MHz from the maximum rated clock frequency Blocking MCU control signals with the bits of PMMR2 see Table 100 page 125 can further reduce PLD AC power consumption SRAM Standby Mode Battery Backup The SRAM in the PSD MODULE supports a battery backup mode in which the contents are retained in the event of a power loss The SRAM has Voltage Standby PC2 that can be connected to an external battery When Vcc becomes lower than VsrBy then the SRAM automatically connects to Voltage Standby PC2 power source The SRAM Standby Current Istpy is typically 0 5 The SRAM data retention voltage mum The Batt of V routed to PC4 T j te has dropped below VsTBv PSD Chip Select Input CSI PD2 PD2 of Port D can be configured in PSDsoft Ex press as PSD Chip Select Input CSI When Low the signal selects and enables the PSD MODULE Flash memory SRAM and I O blocks for READ or WRITE operation
118. eed for external EEPROM chips General purpose programmable logic PLD is in cluded to build an endless variety of glue logic saving external logic devices The PLD is config ured using the software development tool PSD soft Express available from the web at www st com psm at no charge The uPSD321x also includes supervisor functions such as a programmable watchdog timer and low voltage reset 1st Flash Memory 64K Bytes 16K Bytes SRAM 2K Bytes 8 GPIO Port A 80 pin only General Purpose Logic 16 Macrocells 8032 Address Data Control Bus 80 pin device only Dedicated Pins Al10428b 7 163 uPSD3212A uPSD3212C uPSD3212CV Figure 3 52 Connections 46 VREF 144 RESET 141 P1 7 ADC3 140 P1 6 ADC2 PD1 CLKIN 1 P1 5 ADC1 PC7 2 P1 4 ADC0 JTAG TDO 3 P1 3 TXD1 JTAG TDI 4 P1 2 RXD1 UsB 1 5 P1 1 T2X PCA TERR 6 P1 0 T2 USB 7 Vcc 8 XTAL2 GND 9 XTAL1 PCS TSTAT 10 P3 7 SCL1 2 11 P3 6 SDA1 JTAG TCK 12 P3 5 T1 JTAG TMS 13 P3 4 TO P4 7 PWM4 14 T P31 TXD 24 EXINTO 25 Om ST 107423 Note 1 Pull up resistor required on pin 5 2 for devices 7 5 for 5V devices 8 163 uPSD3212A uPSD3212C uPSD3212CV Figure 4 TQFP80 Connections 179 P3 2 EXINTO 78 1 177 P3 1 TXDO 176 2 75 P3 0 RXDO 80 PBO 74 73 PB4 72 5
119. efnor r Duri ar 5 Data Polling Flag Bit DQ7 outputs a 0 After completion of the cycle the Data Polling Flag Bit DQ7 outputs the last bit programmed it is a 1 after erasing byte to be programmed is in a protected Flash memory sector the instruction is ignored the Flash memory sectors to be erased are protected the Data Polling Flag Bit DQ7 is reset to 0 for about 1001 and then returns to the previous addressed byte No erasure is performed Toggle 006 The Flash memory offers an other way for determining when the Program cycle is completed During the internal WRITE operation and when either the 50 53 CSBOOTO CSBOOT1 is true the Toggle Flag Bit 006 tog gles from 0 to 1 and 1 to 0 on subsequent attempts to read any byte of the memory When the internal cycle is complete the toggling stops and the data READ on the Data Bus 00 07 is the addressed memory byte The device is now accessible for a new READ or WRITE operation The cycle is finished when two successive Reads yield the same output data The Toggle Flag Bit DQ6 is effective after the fourth WRITE pulse for a Program instruction or after the sixth WRITE pulse for an Erase instruction Ifthe byte to be programmed belongs to a protected Flash memory sector the instruction is ignored the Flash memory sectors selected for erasure are protected the To
120. egis ters in the CSIOP block See Tables 84 and 85 uPSD3212A uPSD3212C uPSD3212CV Reset Flash The Reset Flash instruction con sists of one WRITE cycle see Table 82 page 95 It can also be optionally preceded by the standard two WRITE decoding cycles writ ing AAh to 555h and 55h to AAAh It must be ex ecuted after Reading the Flash Protection Status or Flash ID An Error condition has occurred and the device has set the Error Flag Bit DQ5 to 1 during a Flash memory Program or Erase cycle The Reset Flash instruction puts the Flash memo ry back into normal READ Mode If an Error condi tion has occurred and the device has set the Error Flag Bit DQ5 to 1 the Flash memory is put back into normal READ Mode within a few milliseconds of the Reset Flash instruction having been issued The Reset Flash instruction is ignored when it is is sued during a Program or Bulk Erase cycle of the Flash memory The Reset Flash instruction aborts any on going Sector Erase cycle and returns the Flash memory to the normal READ Mode within a few milliseconds Table 84 Sector Protection Security Bit Definition Flash Protection Register not used ps VAM WAP 25972 224 so h 0 Prot Note Bit Definitions Secci Prot 1 Primary Flash memory or secondary Flash memory Sector lt i gt is write protected Secci Prot 0 Primary Flash memory or secondary Flash
121. en data is being written to the second ary Flash memory TSTAT and TERR can be configured as open pu type signals during an ISC ENABLE com Pfptection jen V pe cannot be vedi CORE through JTAG When using JTAG Port only a Full Chip Erase command is allowed All other Program Erase and Verify commands are blocked Full Chip Erase returns the part to a non secured blank state The Security Bit can be set in PSDsoft Express Configuration All primary and secondary Flash memory sectors can individually be sector protected against era sures The sector protect bits can be set in PSD soft Express Configuration INITIAL DELIVERY STATE When delivered from ST the uPSD321x Devices have all bits in the memory and PLDs set 1 The code configuration and PLD logic are loaded using the programming procedure Information for programming the device is available directly from ST Please contact your local sales representa tive 127 163 uPSD3212A uPSD3212C uPSD3212CV AC DC PARAMETERS These tables describe the AD and DC parameters of the uPSD321x Devices gt DC Electrical Specification gt Timing Specification m PLD Timing Combinatorial Timing Synchronous Clock Mode Asynchronous Clock Mode Input Macrocell Timing m Module Timing READ Timing WRITE Timing Power down and RESET Timing The following are issues concer
122. es do not clear the registers Table 101 APD Counter Operation APD Enable Bit ALE Level APD Counter Not Counting 0 X gt after 15 Clocks 125 163 uPSD3212A uPSD3212C uPSD3212CV RESET TIMING AND DEVICE STATUS AT RESET Upon Power up the PSD MODULE requires a Re set RESET pulse of duration tNLNH Po after Vcc is steady During this period the device loads in ternal configurations clears some of the registers and sets the Flash memory into operating mode After the rising edge of Reset RESET the PSD MODULE remains in the Reset Mode for an addi tional period topn before the first memory access is allowed The Flash memory is reset to the READ Mode upon Power up Sector Select 50 53 and CSBOOT0 CSBOOT1 must all be Low WRITE Strobe WR CNTLO High during Power on RESET for maximum security of the data contents and to remove the possibility of a byte being writ ten on the first edge of WRITE Strobe WR Any Flash memory WRITE cycle initiation is prevented automatically when Vcc is below VI ko Figure 67 Reset RESET Timing Ve min Vcc tNLNH PO Power On Reset RESET Warm RESET Once the device is up and running the PSD MOD ULE can be reset with a pulse of a much shorter duration tNLNH The same topn period is needed before the device is operational after a Warm RE SET Figure 67 shows the timing of the Power up and Warm RESET P
123. essed Example mov A A RAM SE Figure 11 Direct Addressing Program Memory 106641 2 Indirect addressing In indirect addressing the instruction specifies a register which contains the address of the operand Both internal and ex ternal RAM can be indirectly addressed The ad dress register for 8 bit addresses can be or R1 of the selected register bank or the Stack Pointer The address register for 16 bit addresses can only be the 16 bit data pointer register DPTR Example mov R1 40 H R1 lt 40H Figure 12 Indirect Addressing Program Memory ssh RI 55 106642 3 Register addressing The register banks containing registers R0 through R7 can be ac cessed by certain instructions which carry a 3 bit register specification within the opcode the in struction Instructions that access the registers this way are code efficient since this mode elimi nates an address byte When the instruction is ex ecuted one of four banks is selected at execution time by the two bank select bits in the PSW Example mov PSW 0001000B select Bank0 mov A 30H mov R1 4 Register specific addressing Some in structions are specific to a certain register For ex ample some instructions always operate on the Accumulator or Data Pointer etc so no address byte is needed to point it The opcode itself does that 5 Immediate constants addressing The val
124. fosc 32 SM1 SM0 8 bit UART Baud rate variable Enables the multiprocessor communication features in Mode 2 and 3 In Mode 2 or 3 if SM2 is set to 1 RI will not be activated if its received 8th data bit RB8 is 0 In Mode 1 if SM2 1 RI will be activated if a valid Stop Bit was not received In Mode 0 SM2 should be 0 4 REN Enables serial reception Set by software to enable reception Clear by software to disable reception KNEE The 8th data bit that will be transmitted in Modes 2 and 3 Set or clear by software as desired In Modes 2 and 3 this bit contains the 8th data bit that was received In Mode 1 5 2 0 8 is the Snap Bit that was received In Mode 0 RB8 is not used Transmit Interrupt Flag Set by hardware at the end of the 8th bit time in Mode 0 or at the beginning of the Stop Bit in the other modes in any serial transmission Must be cleared by software Receive Interrupt Flag Set by hardware at the end of the 8th bit time in Mode 0 or halfway through the Stop Bit in the other modes in any serial reception except for 5 2 Must be cleared by software 4 57 163 uPSD3212A uPSD3212C uPSD3212CV Baud Rates The baud rate in Mode 0 is fixed Mode 0 Baud Rate fosc 12 The baud rate in Mode 2 depends on the value of Bit SMOD 0 which is the value on reset the baud rate is 1 64 the oscillator frequency If SMOD 1 the baud rate is 1 32 the oscillator frequency Mode 2 Baud Rate
125. g Please see the dedicated interrupt control registers for the USB peripheral for more information uPSD3212A uPSD3212C uPSD3212CV Figure 16 Interrupt System Interrupt IE Priority Sources 074270 35 163 uPSD3212A uPSD3212C uPSD3212CV USART Interrupt The USART Interrupt is generated by RI Receive Interrupt OR TI Transmit Interrupt When the USART Interrupt is generated the corresponding request flag must be cleared by the software The interrupt service routine will have to check the various USART registers to determine the source and clear the corresponding flag Both USART s are identical except for the additional interrupt controls in the Bit 4 of the additional interrupt control registers A7H B7H Interrupt Priority Structure Each interrupt source can be assigned one of two priority levels Interrupt priority levels are defined by the interrupt priority special function register IP and IPA 0 low priority 1 high priority Table 18 Priority Levels 0 highest IntO 2nd USART A low priority interrupt may be interrupted by a high priority interrupt level interrupt A high priority interrupt routine cannot be interrupted by any oth er interrupt source If two interrupts of different pri ority occur simultaneously the high priority level request is serviced If requests of the same priority are received simultaneously an internal
126. ggle Flag Bit 006 toggles to 0 for about 100 5 and then returns to the previous addressed byte Error Flag DQ5 During a normal Program or Erase cycle the Error Flag Bit DQ5 is to 0 This Table 83 Status Bit Functional Block uPSD3212A uPSD3212C uPSD3212CV bit is set to 1 when there is a failure during Flash memory Byte Program Sector Erase or Bulk Erase cycle In the case of Flash memory programming the Er ror Flag Bit DQ5 indicates the attempt to program a Flash memory bit from the programmed state 0 to the erased state 1 which is not valid The Error Flag Bit DQ5 may also indicate a Time out condition while attempting to program a byte In case of an error in a Flash memory Sector Erase or Byte Program cycle the Flash memory sector in which the error occurred or to which the pro grammed byte belongs must no longer be used Other Flash memory sectors may still be used The Error Flag Bit DQ5 is reset after a Reset Flash instruction Erase Time out Flag DQ3 The Erase Time out Flag Bit DQ3 reflects the time out period al lowed between two consecutive Sector Erase in structions The Erase Time out Flag Bit DQ3 is reset to 0 after a Sector Erase cycle for a time pe riod of 1000 20 unless an additional Sector Erase instruction is decoded After this time peri od or when the additional Sector Erase instruction is decoded the Erase Time out Flag Bit DQ3 is set to 1 Flash
127. gic is pro grammed into the device and available upon Pow er up Table 87 DPLD and CPLD Inputs Input Source MCU Address Bus MCU Control Signals RESET Power down Port A Input 7 Macrocells PC7 PC4 PC2 74 Po MCELLBC FB7 FBO Ready Busy Note 1 These inputs are not available in the 52 pin package Port B Input Macrocells Port C Input Macrocells Port D Inputs Page Register Macrocell AB Feedback Macrocell BC Feedback Flash memory Program Status Bit 106 163 The PSD MODULE contains two PLDs the De code PLD DPLD and the Complex PLD CPLD The PLDs are briefly discussed in the next few paragraphs and in more detail in Decode PLD DPLD page 108 and Complex PLD CPLD page 109 Figure 54 page 107 shows the configuration of the PLDs The DPLD performs address decoding for Select signals for PSD MODULE components such as memory registers and ports The CPLD can be used for logic functions such as loadable counters and shift registers state ma chines and encoding and decoding logic These logic functions can be constructed using the Out put Macrocells OMC Input Macrocells IMC and the AND Array The CPLD can also be used to generate External Chip Select ECS1 ECS2 signals The AND Array is used to form product terms These product terms are specified using PSDsoft The PLD input signals consist of internal MCU sig nals and external
128. hardware Itis also generated by the T2EX signal Timer 2 External Interrupt P1 1 which is controlled 34 163 1 EXEN2 EXF2 Bits in the T2CON register Interrupt The interrupt of the is generated by Bit INTR in the register S2STA This flag is cleared by hardware External Inti The INT1 can be either level active or transition active depending on Bit IT1 in register TCON The flag that actually generates this interrupt is Bit IE1 in TCON When an external interrupt is generated the corresponding request flag is cleared by the hardware when the service routine is vectored to only if the interrupt was transition activated the interrupt was level activated then the interrupt request flag remains set until the requested interrupt is actually generated Then it has to deactivate the request before the interrupt service routine is completed or else another interrupt will be generated The ADC can take over the External INT1 to generate an interrupt on conversion being completed d when packet or nBlpoint1 or USB Interrupt endpoint2 has transmitted a packet when the suspend or resume state is detected and every EOP received When the USB Interrupt is generated the corresponding request flag must be cleared by software The interrupt service routine will have to check the various USB registers to determine the source and clear the corresponding fla
129. he Upper 128 bytes of RAM if they are implemented but not into SFR space The Data Transfer instructions include a 16 bit MOV that can be used to initialize the Data Pointer DPTR for look up tables in Program Memory Table 6 Data Transfer Instructio The A byte instruction causes the Accu mulator and ad dressed byte to exchange data The XCHD instruction is similar but only the low nibbles are involved in the exchange To see how XCH and XCHD can be used to facilitate data manipulations consider first the problem of shifting and 8 digit BCD number two digits to the right Table 8 page 21 shows how this can be done using XCH instructions To aid in under standing how the code works the contents of the registers that are holding the BCD number and the content of the Accumulator are shown alongside each instruction to indicate their status after the in struction has been executed After the routine has been executed the Accumu lator contains the two digits that were shifted out on the right Doing the routine with direct MOVs uses 14 code bytes The same operation with XCHs uses only 9 bytes and executes almost twice as fast To right shift by an odd number of digits a one digit must be executed Table 9 page 21 shows a sample of code that will right shift a BCD number one digit using the XCHD in struction Again the contents of the registers hold ing the number and of the accumulator
130. high impedance state START Flag When this bit is set the SIO H W checks the status of the and generates a START condition if the bus free If the bus is busy the SIO will generate a repeated START condition when this bit is set STOP Flag With this bit set while in Master Mode a STOP condition is generated When a STOP condition is detected on the bus the hardware clears the STO Flag Note This bit have to be set before 1 cycle interrupt period of STOP That is if this bit is set STOP condition in Master Mode is generated after 1 cycle interrupt period This bit is set when address byte was received Must be cleared by software Acknowledge enable signal If this bit is set an acknowledge low level to SDA is returned during the acknowledge clock pulse on the SCL line when Own slave address is received A data byte is received while the device is programmed to be a Master Receiver A data byte is received while the device is a selected Slave Receiver When this bit is reset no acknowledge is returned SIO release SDA line as high during the acknowledge clock pulse These two bits along with the CR2 Bit determine the serial clock frequency when SIO is in the Master Mode 73 163 uPSD3212A uPSD3212C uPSD3212CV Serial Status Register S2STA S2STA is a Read only register The contents of 3 A data byte has been received or transmitted this register may be used as a vector to a
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132. in Register PLD Status at RESET Table 102 shows the I O pin register PLD sta tus during Power on RESET Warm RESET and Power down Mode PLD outputs are always valid during Warm RESET and they are valid in Power on RESET the internal Configuration bits are loaded This loading is completed typically long before the Vcc ramps up to operating level Once the PLD is active the state of the outputs are de termined by the PLD equations tNLNH Warm Reset 107437 Table 102 Status During RESET Warm RESET Power down Mode Power down Mode Port Configuration Power on RESET MCU I O Input mode Valid after internal PSD PLD Output configuration bits are loaded Address Address Out Tri stated Warm RESET Input mode Unchanged Depends on inputs to PLD Valid addresses are blocked in PD Mode Tri Wistaed defined Tri stated LE stated Tri stated Power on RESET Warm RESET Power down Mode PMMROandPMMR2 and PMMR2 Cleared to 0 to 0 by internal Macrocells flip flop status Power on REBET Initialized based on the selection in PSDsoft Configuration menu VM Register All other registers Unchanged Depends on re and pr Depends on re and pr equations equations Initialized based on the selection in PSDsoft Configuration menu Cleared to 0 Cleared to 0 Unchanged Unchanged
133. in Idle the user should always set up a timer that will periodically exit Idle service the and re enter Idle Mode Table 32 Watchdog Timer Register 0 7100 7 to Enable disable Watchdog Timer WDKEYO 01010101 55h disable watchdog timer Others enable watchdog timer 46 163 uPSD3212A uPSD3212C uPSD3212CV Watchdog reset pulse width depends on the clock frequency The reset period is Tfosc x 12 x 222 The RESET pulse width is Tfosc x 12 x 215 Figure 21 RESET Pulse Width Reset pulse width about 10ms 40Mhz about 50ms 8Mhz E Reset period 1 258 second at 40Mhz about 6 291 seconds at 8Mhz 106823 Table 34 Watchdog Timer Clear Register WDRST 0A6H MESE T Table 35 Description the WDRST Bits This value is loaded to the 7 most significant bits of the 22 bit counter For example MOV WDRST 1EH Note The Watchdog Timer WDT is enabled at power up or reset and must be served or disabled 47 163 uPSD3212A uPSD3212C uPSD3212CV TIMER COUNTERS TIMER 0 TIMER 1 AND TIMER 2 The uPSD321x Devices has three 16 bit Timer Counter registers Timer 0 Timer 1 and Timer 2 All of them can be configured to operate either as timers or event counters and are compatible with standard 8032 architecture In the Timer function the register is incremented every machine cycle Thus one can think
134. in a Pierce oscilla operated in parallel resonance tor configuration see Figure 19 The circuitry be _ XTAL1 is the high gain amplifier input and XTAL2 tween XTAL1 XTAL2 is basically an inverter is the output To drive the uPSD321x Devices ex ramic resonator can be used as the feedback ele XTAL2 left open circuit Figure 19 Oscillator XTAL1 XTAL2 XTAL1 XTAL2 8 to 40 MHz ES External Clock ees IM 106620 44 163 57 SUPERVISORY There are four ways to invoke a reset and initialize the uPSD321x Devices mg Viathe external RESET pin m Via the internal LVR Block m Via Watch Dog timer m Via USB bus reset signalling The RESET mechanism is illustrated in Figure 20 Each RESET source will cause an internal reset signal active The CPU responds by executing an internal reset and puts the internal registers in a defined state This internal reset is also routed as an active low reset input to the PSD Module External Reset The RESET pin is connected to a Schmitt trigger for noise reduction A RESET is accomplished by holding the RESET pin LOW for at least 1ms at power up while the oscillator is running Refer to AC spec on other RESET timing requirements Low Vpp Voltage Reset An internal reset is generated by the LVR circuit when the Vpp drops below the reset threshold Af ter Vpp reaching back up to the reset threshold the RESET signal will remain asserted for
135. includes ANL and ORL operations but not the XRL Exclusive OR operation An XRL operation is simple to im plement in software Suppose for example it is re quired to form the Exclusive OR of two bits C bit 1 XRL bit2 The software to do that could be as follows MOV C JNB bit2 OVER CPL C OVER continue First Bit 1 is moved to the Carry If bit2 0 then C now contains the correct result That is Bit 1 XRL bit2 bit1 if bit2 0 On the other hand if bit2 1 C now contains the complement of the correct result It need only be inverted CPL C to complete the operation This code uses the JNB instruction one of a series of bit test instructions which execute a jump if the 572 uPSD3212A uPSD3212C uPSD3212CV addressed bit is set JC JB JBC or if the ad dressed bit is not set JNC JNB In the above case Bit 2 is being tested if bit2 0 the CPL C instruction is jumped over JBC executes the jump if the addressed bit is set and also clears the bit Thus a flag can be tested and cleared in one operation All the PSW bits are directly addressable so the Parity Bit or the gen eral purpose flags for example are also available to the bit test instructions Relative Offset The destination address for these jumps is speci fied to the assembler by a label or by an actual ad dress Program memory How ever the destination address assembles to a relative offset byte This i
136. ing and Reading the Output Macrocells OMC The Output Macrocells OMC block oc cupies a memory location in the MCU address space as defined by the CSIOP block see PORTS PSD MODULE page 113 The flip flops in each of the 16 Output Macrocells OMC can be loaded from the data bus by a MCU Load ing the Output Macrocells OMC with data from the MCU takes priority over internal functions As such the preset clear and clock inputs to the flip flop can be overridden by the MCU The ability to load the flip flops and read them back is useful in such applications as loadable counters and shift registers mailboxes and handshaking protocols Data can be loaded to the Output Macrocells on the trailing edge of WRITE Strobe WR edge loading or during the time that WRITE Strobe WR is active level loading The method of loading is specified in PSDsoft Express Config uration DIRECTION REGISTER MACROCELL 5 DRIVER ALLOCATOR FF D T JK SR INPUT MACROCELL 106617 111 163 uPSD3212A uPSD3212C uPSD3212CV The OMC Mask Register There is one Mask Register for each of the two groups of eight Output Macrocells OMC The Mask Registers can be used to block the loading of data to individual Out put Macrocells OMC The default value for the Mask Registers is 00h which allows loading of the Output Macrocells OMC When a given bit in a Mask Register is set to a 1 the MCU is
137. inputs from the I O ports The put signals are shown in Table 87 The Turbo Bit in PSD MODULE The PLDs can minimize power consumption by switching off when inputs remain unchanged for extended time of ab Resetting the Turbo 0 automatically laces Xhe i stan if no inputs are changing Turning Turbo Mode off increases propagation delays while reducing power con sumption See POWER MANAGEMENT page 122 on how to set the Turbo Bit Additionally five bits are available in 2 to block MCU control signals from entering the PLDs This reduces power consumption and can be used only when these MCU control signals are not used in PLD logic equations Each of the two PLDs has unique characteristics suited for its applications They are described in the following sections uPSD3212A uPSD3212C uPSD3212CV Figure 54 PLD Diagram PAGE REGISTER DATA BUS DECODE PLD 4 PRIMARY FLASH MEMORY SELECTS H SECONDARY NON VOLATILE MEMORY SELECTS SRAM SELECT CSIOP SELECT gt PERIPHERAL SELECTS YYYYYYYY o 2 m 5 OUTPUT MACROCELL FEEDBACK DIRECT MACROCELL ACCESS FROM MCU DATA BUS gt amp 16 OUTPUT MCELLAB 1 MACROCELL MACROCELL TO PORTAORB 8 PT lt MCELLBC o TO PORT B ORC 8 20 INPUT MACROCELL E PORT gt m u m
138. k is shown in Figure 59 Individual Port architectures are shown in Figure 61 page 118 to Figure 64 page 121 In general once the purpose for a Figure 59 General Port Architecture uPSD3212A uPSD3212C uPSD3212CV port pin has been defined that pin is no longer available for other purposes Exceptions are not ed As shown in Figure 59 the ports contain an output multiplexer whose select signals are driven by the configuration bits in the Control Registers Ports A and B only and PSDsoft Express Configuration Inputs to the multiplexer include the following m Output data from the Data Out register m Latched address outputs m CPLD macrocell output External Select ECS1 ECS2 from the CPLD The Port Data Buffer is a tri state buffer that allows only one source at a time to be read The Port Data Buffer PDB is connected to the Internal Data Bus for feedback and can be read by the MCU The Data Out and macrocell outputs Direc tion and Control Registers and port pin input are all connected to the Port Data Buffer PDB DATA OUT REG LI LCS T DAY WR WA LU ADDRESS PORT PIN 1 MACROCELL OUTPUTS READ MUX o 2 m lt lt 2 o ENABLE OUT DIR REG ENABLE PRODUCT TERM OE INPUT MACROCELL CPLD INPUT 106604 ky 113 163 uPSD3212A uPSD3212C uPSD3212CV The Port pin s tri state output driver enable is con trolled by a two
139. l not cause a reload from RCAP2H RCAP2L to TH2 TL2 Thus when Timer 2 is in use as a baud rate generator can be used as an extra external interrupt if de sired It should be noted that when Timer 2 is running TR2 1 in timer function in the Baud Rate Gen erator Mode one should not try to READ or WRITE TH2 or TL2 Under these conditions the timer is being incremented every state time and the results of a READ or WRITE may not be accu rate The RC registers may be read but should not be written to because a WRITE might overlap a reload and cause WRITE and or reload errors Turn the timer off clear TR2 before accessing the Timer 2 or RC registers in this case uPSD3212A uPSD3212C uPSD3212CV Table 45 Timer 1 Generated Commonly Used Baud Rates Timer 1 Mode 0 Max 1MHz 12MHz NEN n gt 19 2K 11 059MHz EE 9 6K 11 059MHz Lo p m pq 2 4K 11 059MHz Lm o9 More About Mode 0 Serial data enters and exits through RxD TxD outputs the shift clock 8 bits are transmitted received 8 data bits LSB first The baud rate is fixed at 1 12 the fosc Figure 27 page 56 shows a simplified functional diagram of the serial port in Mode 0 timing Transmission insti uses SBUF as a destination register The to SBUF signal at S6P2 also loads 1 into the 9th position of the transmit shift register and tel
140. le method after Erase cycle Figure 49 still applies the Toggle Flag Bit DQ6 toggles until the cycle 15 complete A 1 on the Error Flag Bit DQ5 indi cates a time out condition on the Erase cycle a 0 uPSD3212A uPSD3212C uPSD3212CV indicates no error The MCU can read any location within the sector being erased to get the Toggle Flag Bit DQ6 and the Error Flag Bit DQ5 PSDsoft Express generates ANSI C code tions which implement these Data Toggling algo rithms Figure 49 Data Toggle Flowchart READ DQ5 amp DQ6 PASS 101370 99 163 uPSD3212A uPSD3212C uPSD3212CV Erasing Flash Memory Flash Bulk Erase The Flash Bulk Erase instruc tion uses six WRITE operations followed by a READ operation of the status register as de scribed in Table 82 If any byte of the Bulk Erase instruction is wrong the Bulk Erase instruction aborts and the device is reset to the READ Flash memory status During a Bulk Erase the memory status may be checked by reading the Error Flag Bit DQ5 the Toggle Flag Bit DQ6 and the Data Polling Flag Bit DQ7 as detailed in Programming Flash Memory page 98 The Error Flag Bit DQ5 re turns a 1 if there has been an Erase Failure max imum number of Erase cycles have been executed It is not necessary to program the memory with 00h because the PSD MODULE automatically does this before erasing to OFFh During execution of
141. ls the TX Control block to commence a transmission The internal timing is such that one full machine cycle will elapse between WRITE to SBUF and activation of SEND SEND enables the output of the shift register to the alternate out put function line of RxD and also en able SHIFT CLOCK to the alternate output func tion line of TxD SHIFT CLOCK is low during S3 54 and 55 of every machine cycle and high dur ing S6 S1 and S2 At S6P2 of every machine cy cle in which SEND is active the contents of the transmit shift are shifted to the right one position As data bits shift out to the right zeros come in from the left When the MSB of the data byte is at the output position of the shift register then the 1 that was initially loaded into the 9th position is just N N to the left of the MSB and all positions to the left of that contain zeros This condition flags the TX Control block to do one last shift and then vate SEND and set T1 Both of these actions occur at S1P1 Both of these actions occur at S1P1 of the 10th machine cycle after WRITE to SBUF Receptigrrisgrrti the condition REN 1 1 5 ft ext ine cycle the RX trol uites t S 1711010 the receive shift register and in the next clock phase activates RECEIVE RECEIVE enables SHIFT CLOCK to the alternate output function line of SHIFT CLOCK makes transitions at and S6P1 of every machine cycle in which RECEIVE
142. ls are active High and are defined in PSDsoft Express 11 Only address Bits 11 0 are used in instruction decoding 12 No Unlock or instruction cycles are required when the device is in the READ Mode 13 The RESET Instruction is required to return to the READ Mode after reading the Sector Protection Status or if the Error Flag Bit DQ5 goes High 14 Additional sectors to be erased must be written at the end of the Sector Erase instruction within 80us 15 The data is 00h for an unprotected sector and 01h for a protected sector In the fourth cycle the Sector Select is active and 1 0 1 0 16 system may perform READ and Program cycles non erasing sectors read the Sector Protection Status when in the Suspend Sector Erase Mode The Suspend Sector Erase instruction is valid only during a Sector Erase cycle 17 The Resume Sector Erase instruction is valid only during the Suspend Sector Erase Mode 18 The MCU cannot invoke these instructions while executing code from the same Flash memory as that for which the instruction is intended The MCU must retrieve for example the code from the secondary Flash memory when reading the Sector Protection Status of the primary Flash memory 95 163 uPSD3212A uPSD3212C uPSD3212CV Power down Instruction and Power up Mode Power up Mode The PSD MODULE internal logic is reset upon Power up to the READ Mode Sector Select 50 53 and CSBOOTO CSBOOT 1 must be held Low
143. memory Sector i is not write protected Table 85 Sector Definition Secondary Flash Protection rr Note Bit Definitions Sec lt i gt _Prot 1 Secondary Flash memory Sector lt i gt is write protected Sec lt i gt _Prot 0 Secondary Flash memory Sector lt i gt is not write protected Security_Bit 0 Security Bit in device has not been set 1 Security Bit in device has been set 101 163 uPSD3212A uPSD3212C uPSD3212CV SRAM The SRAM is enabled when SRAM Select 50 from the DPLD is High SRAM Select RS0 can contain up to two product terms allowing flexible memory mapping The SRAM can be backed up using an external battery The external battery should be connected to Voltage Standby PC2 If you have external battery connected to the uPSD3200 the contents of the SRAM are retained in the event of a power loss The contents of the SRAM are re tained so long as the battery voltage remains at 2V or greater If the supply voltage falls below the bat tery voltage an internal power switchover to the battery occurs can be configured as an output that indicates when power is being drawn from the external bat tery Battery on Indicator is High with the supply voltage falls below the battery volt age and the battery on Voltage Standby PC2 is supplying power to the internal SRAM SRAM Select RS0 Voltage Standby PC2
144. mma ble to either 1 16 or 1 32 the CPU clock frequency in Mode 2 Mode 3 may have a variable baud rate generated from Timer 1 Figure 31 page 63 and Figure 33 page 64 show a functional diagram of the serial port in Modes 2 and 3 The receive portion is exactly the same as in Mode 1 The transmit portion differs from Mode 1 only in the 9th bit of the transmit shift register Transmission is initiated by any instruction that uses SBUF as a destination register The WRITE to SBUF signal also loads 8 into the 9th bit po sition of the transmit shift register and flags the TX Control unit that a transmission is requested Transmission commences at S1P1 of the machine cycle following the next roll over in the divide by 16 counter Thus the bit times are synchronized to the divide by 16 counter not to the WRITE to signal The transmission begins with activation of SEND which puts the start bit at TxD One bit time later DATA is activated which enables the output bit of the transmit shift register to pulse occurs i gt 32 63 9664 irg shift clocks a 1 the Stop it into the 9th bit posi tion of the shift register There after only zeros are clocked in Thus as data bits shift out to the right zeros are clocked in from the left When TB8 is at the out put position of the shift register then the Stop Bit is just to the left of TB8 and all positions to the left of that
145. ms to IEC 1000 4 2 Note 1 Data based on characterization results not tested in production Table 107 ESD Absolute Maximum Ratings Symbol Parameter E static discharge voltage Human ESD HBM Body Model Note 1 Data based on characterization results not tested in production ae E 131 163 uPSD3212A uPSD3212C uPSD3212CV LU 3 complementary static tests are required on 10 parts to assess the latch up performance A supply overvoltage applied to each power supply pin and a current injection applied to each input output and configurable pin are performed on each sample This test conforms to the EIA JESD 78 IC Latch up Standard see Table 108 For more details refer to the Application Note AN1181 DLU Electro static discharges one positive then one negative test are applied to each pin of 3 samples when the micro is running to assess the latch up performance in dynamic mode Power supplies are set to the typical values the oscillator is connected as near as possible to the pins of the micro and the component is put in reset mode This test conforms to the 1000 4 2 and SAEJ1752 3 Standards see Table 108 For more details refer to the Application Note AN1181 Table 108 Latch up and Dynamic Latch up Electrical Sensitivities Level Symbol Paramet Static Latch up Class 25 C DU Dynamic Latch up Class 5V 25 C fosc 40MHz
146. n to or when Flash memory is being erased The output is a 1 Ready when no WRITE or Erase cycle is in progress Memory Operation The primary Flash memory and secondary Flash memory are addressed through the MCU Bus The MCU can access these memories in one of two ways MCU can execute a typical bus WRITE or READ operation The MCU can execute a specific Flash memory instruction that consists of several WRITE and READyo This involves j rng to special la emory to invoke an embedded algorithm These instructions are summarized in Table 82 Typically the MCU can read Flash memory using READ operations just as it would read a ROM de vice However Flash memory can only be altered using specific Erase and Program instructions For example the MCU cannot write a single byte di rectly to Flash memory as it would write a byte to RAM To program a byte into Flash memory the MCU must execute a Program instruction then test the status of the Program cycle This status test is achieved by a READ operation or polling Ready Busy PC3 93 163 uPSD3212A uPSD3212C uPSD3212CV Instructions An instruction consists of a sequence of specific operations Each received byte is sequentially de coded by the PSD MODULE and not executed as a standard WRITE operation The instruction is ex ecuted when the correct number of bytes are prop erly received and the time between two consecutive bytes is shorter than th
147. n which the subroutine address is given to the CPU CALL is a generic mnemonic which can be used if the programmer does not care which way the address is encoded The LCALL instruction uses the 16 bit address for mat and the subroutine can be anywhere in the 64K Program Memory space The ACALL instruc tion uses the 11 bit format and the subroutine must be in the same 2K block as the instruction fol lowing the ACALL In any case the programmer specifies the subrou tine address to the assembler in the same way as a label or as a 16 bit constant The assembler will the address into c rmat for the giv i RET instruction which returns execution to the instruction following the CALL RETI is used to return from an interrupt service routine The only difference between RET and RETI is that RETI tells the interrupt control system that the interrupt in progress is done If there is no interrupt in progress at the time RETI is executed then the RETI is functionally identical to RET Table 13 Unconditional Jump Instructions Return from subroutine RETI Return from Interrupt Table 14 shows the list of conditional jumps avail able to the uPSD321x Devices user All of these jumps specify the destination address by the rela tive offset method and so are limited to a jump dis tance of 128 to 127 bytes from the instruction following the conditional jump instruction Impor tant to note however
148. nable control signal can be defined by a product term from the PLD or by resetting the corresponding bit in the Direction Register to 0 The corresponding bit in the Direction Register must not be set to 1 if the pin is defined for PLD input signal in PSDsoft The PLD I O Mode is specified in PSDsoft by declaring the port pins and then writing an equation assigning the PLD O to a port Address Out Mode Address Out Mode can be used to drive latched MCU addresses on to the port pins These port pins can in turn drive external devices Either the output enable or the corresponding bits of both the Direction Register must 5 Out Mode This un time See Table utput pin assign ments on Ports B for various MCUs Peripheral Mode Peripheral I O Mode can be used to interface with external peripherals In this mode all of Port A Serves as a tri state bi directional data buffer for the MCU Peripheral I O Mode is enabled by set ting Bit 7 of the VM Register to 1 Figure 60 page 115 shows how Port A acts as a bi di rectional buffer for the MCU data bus if Peripheral Mode is enabled An equation for PSELO and or PSEL1 must be written in PSDsoft The buffer is tri stated when PSELO or PSEL1 is low not ac tive The PSEN signal should be in the PSEL equations to disable the buffer when PSEL resides in the data space JTAG In System Programming ISP Port C is
149. nd period The PWM the Period Register defines the period of the PWM The input clock to 4 has a 16 bit Prescaler an 8 the Prescaler is fosc 2 The PWM 4 channel is as bit Counter a Pulse Width Register and a Period signed to Port 4 7 Register The Pulse Width Register defines the Figure 37 Programmable PWM 4 Channel Block Diagram 8 bit PWM4 8 bit PWM4 Load CPU RD WR 16 bit Prescaler Register Register Register B4h B3h 14 PWMCON 5 PWME DATA BUS CPU RD WR 8 bit PWM4P 8 bit PWMAW Register Register Period Width 8 bit PWM4 omparator 8 bit PWM4 Comparatg OAT 8 bit Counter Clock Reset Port 4 7 PWMCON Bit 6 PWMP 107091 70 163 PWM 4 Channel Operation The 16 bit Prescaler1 divides the input clock fosc 2 to the desired frequency the resulting clock runs the 8 bit Counter of the PWM 4 chan nel The input clock frequency to the PWM 4 Counter is f PWM4 fosc 2 Prescaler1 data value 1 When the Prescaler1 Register B4h is set to data value 0 the maximum input clock frequency to the PWM 4 Counter is fosc 2 and can be as high as 20MHz The PWM 4 Counter is a free running 8 bit counter The output of the counter is compared to the Compare Registers which are loaded with data from the Pulse Width Register PWM4W ABh and the Period Register PWMAP AAh
150. ng or update Flash memory can only be read not written to A Page Register is used to access memory beyond the 64K bytes address Figure 5 Memory Map and Address Space uPSD3212A uPSD3212C uPSD3212CV space Refer to the PSD Module for details on mapping of the Flash memory The 8032 core has two types of data memory in ternal and external that can be read and written The internal SRAM consists of 256 bytes and in cludes the stack area The SFR Special Function Registers occupies the upper 128 bytes of the internal SRAM the reg isters can be accessed by Direct addressing only Another 2K bytes resides in the PSD Module that can be mapped to any address space defined by the user MAIN FLASH EXT RAM INT RAM SFR FF SECONDARY FLASH Indirect Direct 64KB Addressing ddressing 2KB WINN ST Direct Addressing 0 Flash Memory Space Internal RAM Space External RAM Space 256 Bytes MOVX 107425 13 163 uPSD3212A uPSD3212C uPSD3212CV Registers The 8032 has several registers these are the Pro gram Counter PC Accumulator A B Register B the Stack Pointer SP the Program Status Word PSW General purpose registers RO to R7 and DPTR Data Pointer register Accumulator The Accumulator is the 8 bit gen eral purpose register used for data operation such as transfer temporary saving and conditional tests
151. ning the parame ters presented Inthe DC specification the supply current is given for different modes of operation The AC power component gives the PLD Flash memory and SRAM mA MHz specification Figures 68 and 69 show the PLD mA MHz as a function of the number of Product Terms PT used Inthe PLD timing parameters add the required delay when Turbo Bit is 0 Figure 68 PLD Frequency Consumption 5V range SI 0 5 10 HIGHEST COMPOSITE FREQUENCY AT PLD INPUTS MHz 15 20 25 02894 Icc mA 128 163 HIGHEST COMPOSITE FREQUENCY INPUTS MHz 15 20 25 AI03100 uPSD3212A uPSD3212C uPSD3212CV Table 104 PSD MODULE Example Typ Power Calculation at Vcc 5 0V Turbo Mode Off Conditions MCU Clock Frequency Highest Composite PLD input frequency 95 Flash memory Access 8096 SRAM access lt 1596 access 5 additional power above Operational 5 95 Normal 40 Power down Mode 60 Number of product terms used from fitter report 45 PT of total product terms 45 182 24 7 Calculation using typical values Icc total Icc MCUactive x MCUAactive Icc PSDactive x PSDactive Ipp pwrdown x pwrdown N NBA NDL Icc PSDactive lcc ac Icc dc flash x 2 5mA MHz x Freq ALE x 1 5mA MHz x Freq ALE
152. number of sample slo is 1EA ignore Bit 6 to Bit 0 luci oon NA COM __ sss _ O Required Start Stop Hold Time 3EA 150ns 12 Fast Mode Start Stop hold time specification 128EA 6000ns Table 59 System Clock Setup Examples S1SETUP System Clock S2SETUP Register Number of Sample Required Start Stop Hold Time 40MHz fosc 2 gt 50ns 30MHz fosc 2 gt 66 6ns 20MHz fosc 2 gt 100ns 8MHz fosc 2 gt 250ns 75 163 uPSD3212A uPSD3212C uPSD3212CV USB HARDWARE The characteristics of USB hardware are as fol lows m Complies with the Universal Serial Bus specification Rev 1 1 m Integrated SIE Serial Interface Engine FIFO memory and transceiver m Low speed 1 5Mbit s device capability m Supports control endpointO and interrupt endpoint1 and 2 m USB clock input must be 6MHz requires MCU clock frequency to be 12 24 36MHz The analog front end is an on chip generic USB transceiver It is designed to allow voltage levels equal to Vpp from the standard logic to interface with the physical layer of the Universal Serial Bus It is capable of receiving and transmitting serial data at low speed 1 5Mb s The SIE is the digital front end of the USB block This module recovers the 1 5MHz clock detects the USB sync word and handles all low level USB protocols and error checking The bit clock recov ery circuit re
153. ny Endpoint 1 or Endpoint 2 directed IN token RESET clears this bit resume the forced resume to be between 10ms and 15ms Setting this bit will not cause the RESUMF Bit to set uPSD3212A uPSD3212C uPSD3212CV Table 70 USB Control Register UCON2 OECh MES ON Table 71 Description of the UCON2 Bits 710 705 see SOUT F ee out is used to automatically respond to the OUT of a control READ transfer o s nw Table 72 USB Endpoint0 Status Register USTA 0EDh 7 8 p x Table 73 Description of the USTA Bits b wig be ith e E received for SETUP SETUP Token Detect Bit This bit is set when the received token packet is a SEPUP token PID b1101 5 IN IN Token Detect Bit This bit is set when the received token packet is an IN token 4 OUT OUT Token Detect Bit This bit is set when the received token packet is an OUT token RPOSIZ3 to RPOSIZO EN The number of data bytes received in a DATA packet Table 74 USB Data Receive Register UDRO OEFh o _ NEN QE NAE XN NN Table 75 USB COUP Data Transmit Register Table 76 USB Endpoint1 Data Transmit Register UDT1 OE6h LEER NE S UU i t h j UDT1 7 UDT1 6 UDT1 5 UDT1 4 UDT1 3 UDT1 2 UDT1 1 UDT1 0
154. of it as counting machine cycles Since a machine cycle consists of 6 CPU clock periods the count rate is 1 6 of the CPU clock frequency or 1 12 of Oscilla tor Frequency fosc In the Counter function the register is increment ed in response to a 1 10 0 transition at its corre sponding external input pin TO or T1 In this function the external input is sampled during S5P2 of every machine cycle When the samples show high in one cycle a low in the next cy cle the count is incremented The new count value appears in the register during S3P1 of the cycle Table 36 Control Register TCON Y Y following the one in which the transition was de tected Since it takes 2 machine cycles 24 fosc clock periods to recognize a 1 10 0 transition the maximum count rate is 1 24 of the fosc There are no restrictions on the duty cycle of the external in put signal but to ensure that a given level is sam pled at least once before it changes it should be held for at least one full cycle In addition to the Timer or Counter selection Timer 0 and Timer 1 have four operating modes from which to select Timer 0 and Timer 1 The Timer or Counter function is selected by control bits C T in the Special Function Register TMOD These Timer Counters have four operat ing modes which are selected by bit pairs M1 in TMOD Modes 0 1 and 2 are the same for Timers Counters Mode 3 is different The four op erating mo
155. oftware must clear this flag To enable the next data packet transmission TXOE must also be set If TXDOF Bit is not cleared a NAK handshake will be returned in the next IN transactions RESET clears this bit Endpoint1 Endpoint2 Data Transmit Flag This bit is shared by Endpoints 1 and Endpoints 2 It is set after the data stored in the shared Endpoint 1 Endpoint 2 transmit buffer has been sent and an ACK handshake packet from the host is received Once the next set of data is ready in the transmit buffers software must clear this flag To enable the next data packet transmission TX1E must also be set If TXD1F Bit is not cleared a handshake will be returned in the next IN transaction RESET clears this bit TXD1F EOPF RESUMF End of Packet Flag This bit is set when a valid End of Packet sequence is detected on the D and D line Software must clear this flag RESET clears this bit Resume Flag This bit is set when USB bus activity is detected while the SUSPND Bit is set Software must clear this flag RESET clears this bit m ta Receive Flag is ter the USB m iv ditta packet and cad with han t t clear this flag 3 RXD0F after all of the received data has been read Software must also set RXOE Bit to one to enable the next data packet reception If RXDOF Bit is not cleared a NAK handshake will be returned in the next OUT transaction RESET clears this bit E 78 163 uPSD3212A
156. ort D 00 01 11 02 03 0 2 4 E2 Reads Port pin as input MCU I O Input Mode Selects mode between MCU I O or Address Out Stores data for output to Port pins MCU I O Output Mode Configures Port pin as input or output Configures Port pins as either CMOS or Open Drain on some pins while selecting high slew rate on other pins Reads Input Macrocells Reads the status of the output enable to the Port driver READ reads output of macrocells AB WRITE loads macrocell flip flops READ reads output of macrocells BC WRITE loads magrocelLflip flops omm M acrocells AB Blocks writing to Output Macrocells BC Read only Primary Flash Sector Protection Read only PSD MODULE Security and Secondary Flash memory Sector Protection Power Management Register 0 Power Management Register 2 Page Register Places PSD MODULE memory areas in Program and or Data space on an individual basis PSD MODULE DETAILED As shown in Figure 15 page 27 the PSD MOD ULE consists of five major types of functional blocks m Memory Block m PLD Blocks m O Ports m Power Management Unit PMU JTAG Interface functions each block are described following sections Many of the blocks perform multiple functions and are user configurable MEMORY BLOCKS The PSD MODULE has the following memory blocks m Primary Flash memory m Secondary Flash
157. ot up and later swap the primary and secondary Flash memories This is easily done with the VM Register by using PSDsoft Express Configuration to configure it for Boot up and hav ing the MCU change it when desired Table 86 de scribes the VM Register Bit 2 Primary FL_Code Bit 1 Bit 0 Secondary Code SRAM Code Bit 4 Eo Bit 6 Bit 5 Primary if FL_Data can t used used access Flash memory memory 1 1 enable access PIO Mode not used not used Flash memory 0 RD can t access Secondary Flash memory 1 RD access Secondary Flash 0 can t access Flash memory 0 PSEN can t access SRAM 0 PSEN can t access Secondary Flash memory 1 access SRAM 1 PSEN access Secondary Flash memory ww com 103 163 uPSD3212A uPSD3212C uPSD3212CV Separate Space Mode Program space is sepa rated from Data space For example Program Se lect Enable PSEN is used to access the program code from the primary Flash memory while READ Strobe RD is used to access data from the sec ondary Flash memory SRAM and Port blocks This configuration requires the VM Register to be set to OCh see Figure 51 Figure 51 Separate Space Mode Primary Flash Memory 50 53 50 53 3 VM REG 1 VM REG BIT 2 REG 0 Combined Space Modes The
158. ow from Bit 4 of ALU Register Bank Select Flags RSO RS1 This flags select one of four bank 00 07H bankO 08 0Fh bank1 10 17h bank2 17 1Fh bank3 in Internal RAM Overflow Flag OV This flag is set to 1 when an overflow occurs as the result of an arithmetic oper ation involving signs An overflow occurs when the result of an addition or subtraction exceeds 127 7Fh or 128 80h The CLRV instruction clears the overflow flag There is no set instruction When the BIT instruction is executed Bit 6 of memory is copied to this flag 14 163 Parity Flag P This flag reflects on number of Ac cumulator s 1 If the number of Accumulator s 1 is odd 0 otherwise 1 The sum of adding Accumulator s 1 to P is always even RO R7 General purpose 8 bit registers that are locked in the lower portion of internal data area Data Pointer Register Data Pointer Register is 16 bit wide which consists of two 8bit registers DPH and DPL This register is used as a data pointer for the data transmission with external data memory in the PSD Module Figure 6 8032 MCU Registers Accumulator B Register Stack Pointer PCL Program Counter 5 Program Status Word General Purpose Register 3 Data Pointer Register AI06636 Two 8 bit Registers can be used as a BA 16 bit Registers 106637 Figure 8 Stack Pointer Stack Area 30h FFh Bit 15 Bit
159. r eod 56 tion Note AN1153 for more details on System Programming ISP The uPSD321x Devices supports JTAG In Sys tem Configuration ISC commands but Boundary Scan The PSDsoft Express software tool and FlashLINK JTAG programming cable im plement the JTAG In System Configuration ISC commands Table 103 JTAG Port Signals Port C Pin JTAG Signals Description PCO TMS Mode Select TSTAT Status optional TERR Error Flag optional Secor JTAG Extensions TSTAT and TERR are two JTAG extension signals enabled by ISC_ENABLE command received over the four standard JTAG signals TMS TCK TDI and TDO They are used to speed Program and Erase cycles by indicating status on uPDS signals instead of having to scan the status out se rially using the standard JTAG channel See cation Note AN1 153 TERR indicates if an error has occurred when erasing a sector or programming a byte in Flash memory This signal goes Low active when an Error condition occurs and stays Low until an ISC_CLEAR command is executed or a Re set RESET pulse is received after an ISC DISABLE command TSTAT behaves the same as Ready Busy de scribed in Ready Busy PC3 page 93 TSTAT is High when the PSD MODULE device is in READ Mode primary and secondary Flash memory con tents can be read TSTAT is Low when Flash memory Program or Erase cycles are in progress and also wh
160. r representative The uPSD3200 is also supported by third party device programmers See our web site for the current list Choose PSD GENERATE C CODE SPECIFIC TO PSD FUNCTIONS USER S CHOICE OF 8032 MCU FIRMWARE 5 COMPILER LINKER FORMAT J OBJ FILE AVAILABLE FOR 3rd PARTY PROGRAMMERS 07432 91 163 uPSD3212A uPSD3212C uPSD3212CV PSD MODULE REGISTER DESCRIPTION AND ADDRESS OFFSET Table 81 shows the offset addresses to the PSD MODULE registers relative to the CSIOP base ad dress The CSIOP space is the 256 bytes of ad dress that is allocated by the user to the internal Table 81 Register Address Offset Register Name PSD MODULE registers Table 81 provides brief descriptions of the registers in CSIOP space The following section gives a more detailed descrip tion Description Data In Control e 4 Data Out 3 N 5 A L Drive Select Input Macrocell k Enable Out B Output Macrocells AB Output Macrocells BC Mask Macrocells s Mask Macrocells B Primary Flash Protection Secondary Flash memory Protection PMMR0 PMMR2 Page lt lt a A m Note 1 Other registers that are not part of the ports 92 163 PortB Port P
161. r to x and xAx 149 163 uPSD3212A uPSD3212C uPSD3212CV Table 131 Program WRITE and Erase Times 5V Devices Parameter Flash Program Flash Bulk Erase pre programmed Flash Bulk Erase not pre programmed Sector Erase pre programmed Sector Erase not pre programmed Program Erase Cycles per Sector Sector Erase Time out DQ7 Valid to Output 207 000 Valid Data Polling Note 1 Programmed to all zero before erase 2 The polling status 007 is valid ta7vav time units before the data byte DQ0 DQ7 is valid for reading Table 132 Program WRITE and Erase Times 3V Devices Symbol Parameter Flash Program Flash Bulk Erase pre programmed __ Flash Bulk Erase not pre programmed Sector Erase pre programmed twHav2 Sector Erase not pre pr ore we MAN DIII COMES rear Erase Note 1 Programmed to all zero before erase 2 The polling status 007 is valid ta7vav time units before the data byte DQ0 DQ7 is valid for reading 150 163 uPSD3212A uPSD3212C uPSD3212CV Figure 79 Peripheral I O READ Timing A D BUS tavav A n z U U Ys lt lt gt tRHOZ tpvov DATA ON PORT A 106610 Table 133 Port A Peripheral Data Mode RE
162. r when TR1 1 and either GATE 0 or INT1 1 Setting GATE 1 allows the Timer to be controlled by external in put INT1 to facilitate pulse width measurements TR1 is a control bit in the Special Function Regis ter TCON TCON Control Register GATE is in TMOD Figure 22 Timer Counter Mode 0 13 bit Counter The 13 bit register consists of all 8 bits of TH1 and the lower 5 bits of TL1 The upper 3 bits of TL1 are indeterminate and should be ignored Setting the run flag does not clear the registers Mode 0 operation is the same for the Timer 0 as for Timer 1 Substitute TRO TFO and INTO for the corresponding Timer 1 signals in Figure 22 There are two different GATE Bits one for Timer 1 and one for Timer O Mode 1 Mode 1 is the same as Mode 0 except that the Timer register is being run with all 16 bits Interrupt 106622 50 163 Mode 2 Mode 2 configures the Timer register as an 8 bit Counter TL1 with automatic reload as shown in Figure 23 Overflow from TL1 not only sets TF1 but also reloads TL1 with the contents of TH1 which is preset by software The reload leaves TH1 unchanged Mode 2 operation is the same for Timer Counter 0 Timer 2 Like Timer 0 and 1 Timer 2 can operate as either an event timer or as an event counter This is se lected by Bit C T2 in the special function register T2CON see Table 40 It has three operating modes Capture Auto reload and Baud Rate Generator see
163. rocells IMC PC4 can be configured a Battery on Indicator VBATON indicating when Vcc is less than Vpar Port C does not support Address Out Mode and therefore no Control Register is required m In System Programming ISP JTAG pins TMS TCK TDI TDO are dedicated pins for device programming See PROGRAMMING IN CIRCUIT USING THE JTAG SERIAL INTERFACE page 127 for more information on JTAG programming Figure 62 Port C Structure DATA OUT WR ES PORT C PIN 1 SPECIAL FUNCTION gt OUTPUT E MUX MCELLBC 7 0 READ MUX WAN DDE ENABLE OUT MCU DATA BUS 3 DIR REG ENABLE PRODUCT TERM INPUT MACROCELL CPLD INPUT SPECIAL FUNCTION Note 1 ISP or battery back up CONFIGURATION 06618 119 163 uPSD3212A uPSD3212C uPSD3212CV Port D Functionality and Structure Port D has two I O pins only one in the m CPLD Input direct input to the CPLD no 52 pin package See Figure 63 and Figure Input Macrocells IMC 64 page 121 This port does not support Address Slew rate pins can be set up for fast slew Out Mode and therefore no Control Register is re rate quired Of the eight bits in the Port D registers only Bits 2 and 1 are used to configure pins PD2 and Port D can be configured to perform one or more of the following functions mE mg PSD Chip Select Input CSI PD2 Driving
164. s A High on PSD Chip Select In put CSI PD2 disables the Flash memory and SRAM and reduces power consumption Howev er the PLD and I O signals remain operational when PSD Chip Select Input CSI PD2 is High Input Clock CLKIN PD1 can be turned off to the PLD to save AC power consumption CLKIN PD1 is an input to the PLD AND Array and the Output Macrocells During Power down Mode if CLKIN is not being used as part of the PLD logic equation the clock should be disabled to save AC power CLKIN PD1 is disconnected from the PLD AND Array or the Macrocells block by setting Bits 4 or 5 to a 1 in PMMRO Input Control Signals The PSD MODULE provides the option to turn off the MCU signals WR RD PSEN and Address Strobe 2 to the PLD to save AC power sumption see Table 101 page 125 These con trol signals are inputs to the PLD AND Array ing Power down ny of them are not bei PED logic equation these disabled to save ected from the AND Array by setting Bi 2 3 4 5 and 6 to a 1 in PMMR2 Table 99 Power Management Mode Registers x Not used and should be set to zero 0 off off Automatic Power down Bit 1 APD Enable a Power down 0 PLD Turbo Mode is PLD Turbo off Turbo Mode is off saving power uPSD3200 operates at 5MHz below the maximum rated clock frequency APD is disabled AP
165. s go into SBUF and RI is activated At this time whether the above conditions are met or not the unit goes back to looking for a 1 to 0 transition in RxD uPSD3212A uPSD3212C uPSD3212CV Figure 29 Serial Port Mode 1 Block Diagram Timer1 Overflow Overflow Timer2 Internal Bus SBUF Zero Detector Shift Tx Control Start Data Tx Clock Send Serial Port Interrupt Load SBUF Shift RI Rx Control Rx Clock Start 1 to 0 Transition Detector Internal Bus 06826 Figure 30 Serial Port Mode 1 Waveforms Tx Clock Write to SBUF Send Data Shift TxD T1 Rx Clock RxD Bit Detector Sample Times Shift RI Transmit Start Bit X DL X X 53 X D4 X Ds X X 07 Y Stop Bit 7 7 7 3 16 Reset n n n m TL TL Start Bit X Di X D2 X D3 X X Ds X X 57 Y Stop Bit TL TL TL TL N T TL Receive 106843 61 163 uPSD3212A uPSD3212C uPSD3212CV More About Modes 2 and 3 Eleven bits are transmitted through TxD or received through RxD a Start Bit 0 8 data bits LSB first a pro grammable 9th data bit and a Stop Bit 1 On transmit the 9th data bit TB8 can be assigned the value of 0 or 1 On receive the data bit goes into RB8 in SCON The baud rate is progra
166. s a signed two s complement offset byte which is added to the PC in two s complement arithmetic if the jump is executed The range of the jump is therefore 128 to 127 Program Memory bytes relative to the first byte fol lowing the instruction Table 12 Boolean Instructions opon ECONS 23 163 uPSD3212A uPSD3212C uPSD3212CV Jump Instructions Table 13 shows the list of unconditional jump in structions The table lists a single add in struction but in fact there are three SJMP LJMP and AJMP which differ in the format of the desti nation address JMP is a generic mnemonic which can be used if the programmer does not care which way the jump is en coded The SJMP instruction encodes the destination ad dress as a relative offset as described above The instruction is 2 bytes long consisting of the op code and the relative offset byte The jump dis tance is limited to a range of 128 to 127 bytes relative to the instruction following the SJMP The LJMP instruction encodes the destination ad dress as a 16 bit constant The instruction is 3 bytes long consisting of the opcode and two ad dress bytes The destination address can be any where in the 64K Program Memory space The AJMP instruction encodes the destination ad dress as an 11 bit constant The instruction is 2 bytes long consisting of the opcode which itself contains 3 of the 11 address bits followed by an other
167. s for PW No Longer a Valid Logic Level Pulse Width Note Example Time from Address Valid to ALE Invalid 133 163 uPSD3212A uPSD3212C uPSD3212CV Figure 70 Switching Waveforms Key WAVEFORMS INPUTS OUTPUTS STEADY INPUT MAY CHANGE FROM HI TO LO MAY CHANGE FROM LO TO HI DON T CARE OUTPUTS ONLY STEADY OUTPUT WILL BE CHANGING FROMHI TO LO WILL BE CHANGING LO TO HI CHANGING STATE UNKNOWN CENTER LINE IS TRI STATE 103102 134 163 uPSD3212A uPSD3212C uPSD3212CV Table 113 Major Parameters Parameters Conditions 5V Test 3 3V Test Operating Voltage y UU 4 5 to 5 5 3 0 to 3 6 Operating Temperature 1 40 to 85 40 to 85 C MCU Frequency 12MHz min for USB 1 Min 40 Max 1 Min 24 Max MHz 8MHz min for Active Current Typical 25 C operation 80 Flash and 24MHz MCU clock 12MHz MCU clock 15 SRAM accesses 45 PLD 12MHz PLD input 72 6MHz PLD input 21 product terms used PLD Turbo frequency 4MHz ALE frequency 2MHz ALE mode Off Idle Current Typical CPU halted but some peripherals 24MHz MCU clock 12MHz MCU clock active 25 C operation 45 PLD 12MHz PLD input 25 1MHz PLD input 7 product terms used PLD Turbo frequency frequency mode Off 3 gt Standby Current Typical Power down Mode requires reset to exit mode without Low Voltage Detect LVD Supervisor SRAM Backup Current
168. s of the output enable control to the Port pin driver Port A Bit 0 indicates pin is in input mode O CUN EE EN 7 7 0005 Input Einer Const A ptt pt Drive Port Drive Port C Enable Out Enable x Only Bit 1 and Port D 2 are used Output Macrocells AB 32 163 uPSD3212A uPSD3212C uPSD3212CV Bit Register Name Register Name 1 Mask Macrocells Mask Macrocells BC Primary Flash Protection Security Bit 1 device is secured Secondary Flash Protection Security Bit Control PLD E Sec0_ Prot Prot PLD PLD PLD APD Mcells array power Turbo enable consumption PLD PLD PLD PLD Blocking array inputs to Cntl2 Cntl1 array array array array 1 FL Boot FL Boot SR data data code code code Y A m Qm i i er 9050 9 Sec3 Sec2 0 1 sector Prot Prot Prot Prot is protected Periph 8032 Program mode and Data Space e 8
169. service in Master Mode even if arbitration is lost routine This optimized the response dime of the ack_int software and consequently that of the IC bus The 4 A data byte has been received or transmitted status codes for all possible modes of the 12 bus as selected slave interface oe gen i 5 Astop condition is received as selected slave This flag is set and an interrupt is generated after receiver or transmitter stop int any of the following events occur Data Shift Register S2DAT 1 Own slave address has been received during AA 1 ack int S2DAT contains the serial data to be transmitted Me data which has just been received The MSB 2 The general call address has been received Bit 7 is transmitted or received first that is data while GC S2ADR 0 1 and AA 1 shifted from right to left Table 53 Serial Status Register S2STA j pum OO STOP INTR BBUSY BLOST ACK_REP Table 54 Description of the S2STA Bits E ow STOP Stop Flag This bit is set when a STOP condition is received EE INTR 2 Interrupt Flag This bit is set when an 122 Interrupt condition is requested Au WN X fe A Bus Busy Flag This bit is set when the bus is being used by another master otherwise this bit is reset 2 BLOST Bus Lost Flag This bit is set when the master loses the bus contention otherwise this bit is reset Acknowle
170. sh memory segment 0 and one fourth of secondary Flash memory segment 0 cannot be accessed in this example Note An equation that defined FS1 to anywhere in the range of 8000h to BFFFh would notbe valid Figure 50 shows the priority levels for all memory components Any component on a higher level can overlap and has priority over any component on a lower level Components on the same level must not overlap Level one has the highest priority and level 3 has the lowest Figure 50 Priority Level of Memory I O ponents in the PSD E Highest Priority Level 1 or Peripheral 1 Level 2 Secondary Non Volatile Memory Level 3 Primary Flash Memory Lowest Priority 028670 Memory Select Configuration Program Data Spaces The MCU Core has separate ad dress spaces for Program memory and Data memory Any of the memories within the PSD MODULE can reside in either space or both spac es This is controlled through manipulation of the VM Register that resides in the CSIOP space The VM Register is set using PSDsoft Express to have initial value can subsequently be changed by the MCU so that memory mapping can be changed on the fly Table 86 Register Bit 3 Secondary Data uPSD3212A uPSD3212C uPSD3212CV For example you may wish to have SRAM and pri mary Flash memory in the Data space at Boot up and secondary Flash memory in the Program space at Bo
171. sition is detected the di vide by 16 counter is immediately reset and 1FFH is written into the input shift register Resetting the divide by 16 counter aligns its roll overs with the boundaries of the incoming bit times The 16 states of the counter divide each bit time into 16ths At the 7th 8th and 9th counter states of each bit time the bit detector samples the value of RxD The value accepted is the value that was nin atleast 2 of the 3 This is done for noise t a cepted during the bit circuits are reset and the unit goes back to looking for an other 1 to 0 transition This is to provide rejection of false start bits If the start bit proves valid it is shifted into the input shift register and reception of the re set of the rest of the frame will proceed As data bits come in from the right 15 shift out to the left When the start bit arrives at the left most position in the shift register which in Mode 1 9 bit register it flags the RX Control block to do one last shift load SBUF and 8 and set The signal to load SBUF and RB8 and to set will be generated if and only if the following conditions are met at the time the final shift pulse is generat ed 1 R120 and 2 Either SM2 0 or the received Stop Bit 1 If either of these two conditions is not met the re ceived frame is irretrievably lost If both conditions are met the Stop Bit goes into 8 the 8 data bit
172. ssociated SFR 40 163 2 Bits 0 1 2nd UART Bits 2 3 ADC Bits 4 7 UART Bits 0 1 Interrupt Bits 2 3 Timers Bits 4 5 Bits 6 7 The following SFR registers Tables 29 30 31 are used to control the mapping of alternate functions onto the I O port bits Port 1 alternate functions are controlled using the P1SFS register except for Timer 2 and the 2nd UART which are enabled by their configuration registers P1 0 to P1 3 are default to GPIO after reset Port 3 pins 6 and 7 have been modified from the standard 8032 These pins that were used for READ and WRITE control signals are now GPIO 29 P1SFS H uPSD3212A uPSD3212C uPSD3212CV bus pins The READ and WRITE pins are assigned to dedicated pins Port 3 and Port 4 alternate functions are trolled using the PSSFS and P4SFS Special Func tion Selection registers After a reset the pins default to GPIO The alternate function is enabled if the corresponding bit in the PXSFS register is setto 1 Other Port alternative functions UART Interrupt and Timer Counter are enabled by their configuration register and do not require setting of the bits R3SFS CNN Port 1 7 NUM Port 1 6 1 5 Port 1 4 1 ACH3 1 2 1 1 1 ACHO Bits Reserved Bits Reserved Table 30 P3SFS 93H 0 Port 3 7 0 Port 3 6 1 SCL 1 SDA from unit from unit
173. t will not be serviced In other words the fact that the inter rupt flag was once active but not serviced is not re membered Every polling cycle is new The processor acknowledges an interrupt request by executing a hardware generated LCALL to the appropriate service routine The hardware gener ated LCALL pushes the contents of the Program Counter on to the stack but it does not save the PSW and reloads the PC with an address that de pends on the source of the interrupt being vec tored to as shown in Table 24 38 163 Execution proceeds from that location until the RETI instruction is encountered The RETI instruc tion informs the processor that the interrupt routine is no longer in progress then pops the top two bytes from the stack and reloads the Program Counter Execution of the interrupted program continues from where it left off Note A simple RET instruction would also return execution to the interrupted program but it would have left the interrupt control system thinking an interrupt was still in progress making future inter rupts CO ector able 24 resses 1st USART 0023h Timer 2 EXF2 002Bh POWER SAVING MODE Two software selectable modes of reduced power consumption are implemented see Table 25 Idle Mode The following Functions are Switched Off CPU Halted The following Function Remain Active During ldle Mode External Interrupts
174. tSA tHA INPUT tCOA REGISTERED OUTPUT 102859 147 163 uPSD3212A uPSD3212C uPSD3212CV Table 127 CPLD Macrocell Asynchronous Clock Mode Timing 5V Devices Turbo Slew rie Off Rate Symbol Parameter Conditions Maximum Frequency I tsa t External Feedback Maximum Frequency Internal Feedback fonra 1 Maximum Frequency Pipelined Data VtcHA tcLA E s m x eek Table 128 CPLD Macrocell Asynchronous Clock Mode Timing Devices Symbol Parameter Conditions uu Maximum Frequency External Feedback 1 tsa tcoa 21 7 AME VU X Pipelined Data i af N N O rum he reme eek we E E eas Ss a NE EIN E 148 163 uPSD3212A uPSD3212C uPSD3212CV Figure 78 Input Macrocell Timing Product Term Clock PT CLOCK INPUT OUTPUT 103101 Table 129 Input Macrocell Timing 5 Devices Parameter Conditions Note 1 Inputs from WW Table 130 Input Macro Symbol Parameter Input Setup Time ts m Note 1 Inputs from Port A B and C relative to register latch clock from the PLD ALE latch timings refe
175. tart Data Tx Clock Send Load SBUF Shift RI Rx Control Rx Clock Start 1 to 0 Transition Detector Internal Bus 06846 Figure 34 Serial Port Mode 3 Waveforms Tx Clock Write to SBUF Send Data Shift TxD TI Stop Bit Generator Rx Clock RxD Bit Detector Sample Times Shift RI 64 163 S1P1 Transmit Start Bit X Dt X 02 X X X Ds X X 57 X 188 Y Stop Bit 16 Reset Start Bit X D2 X D3 X X D5 X 06 X 07 X RBS Stop Bit Receive 06847 uPSD3212A uPSD3212C uPSD3212CV ANALOG TO DIGITAL CONVERTOR ADC The analog to digital A D converter allows con version of an analog input to a corresponding 8 bit digital value The A D module has four analog in puts which are multiplexed into one sample and hold The output of the sample and hold is the in put into the converter which generates the result via successive approximation The analog supply voltage is connected to AVREF of ladder resis tance of A D module The A D module has two registers which are the control register ACON and A D result register ADAT The register ACON shown in Table 46 and Table 47 page 66 controls the operation of the A D converter module To use analog inputs I O is selected by P1SFS register Also an 8 bit prescal er ASCL divides the main system clock input down to approximately 6MHz clock that
176. te AN1171 for more detail Table 89 page 115 summarizes which modes are available on each port Table 92 page 116 shows how and where the different modes are configured Each of the port operating modes are described in the following sections MCU I O Mode In the MCU I O Mode the MCU uses the Ports block to expand its own ports By setting up the CSIOP space the ports on the PSD MODULE are mapped into the MCU address space The ad dresses of the ports are listed in Table 81 page 92 A port pin can be put into MCU I O Mode by writing 0 to the corresponding bit in the Control Regis ter The MCU I O direction may be changed writing to the corresponding bit in the Direction Register or by the output enable product term See Peripheral Mode page 114 When the pin 114 163 setto must b t R 45 is configured as an output the content of the Data Out Register drives the pin When configured as an input the MCU can read the port input through the Data In buffer See Figure 59 page 113 Ports C and D do not have Control Registers and are in MCU Mode by default They can be used for PLD I O if equations are written for them PS Dabel PLD I O Mode The PLD I O Mode uses a port as an input to the CPLD s Input Macrocells IMC and or as an out put from the CPLD s Output Macrocells OMC The output can be tri stated with a control signal This output e
177. tents of a PWM 0 3 register is greater than the counter val ue the corresponding PWM output is set HIGH with PWML 2 0 When the contents of this regis ter is less than or equal to the counter value the corresponding PWM output is set LOW with PWML 0 The pulse width ratio is therefore de uPSD3212A uPSD3212C uPSD3212CV fined by the contents of the corresponding Special Function Register PWM 0 3 of a PWM By load ing the corresponding Special Function Register PWM 0 3 with either OOH or FFH the PWM out put can be retained at a constant HIGH or LOW level respectively with PWML 0 For each PWM unit there is a 16 bit Prescaler that are used to divide the main system clock to form the input clock for the corresponding PWM unit This prescaler is used to define the desired repeti tion rate for the PWM unit SFR registers B2h are used to hold the 16 bit divisor values The repetition frequency of the PWM output is giv en by fPWMg fosc prescalerO 2 x 256 And the input clock frequency to the PWM counters is fosc 2 prescaler data value 1 See PORTS MCU Module page 40 for more information on how to configure the Port 4 pin as PWM output ww com ST 67 163 uPSD3212A uPSD3212C uPSD3212CV Figure 36 Four Channel 8 bit PWM Block Diagram
178. ter UCON1 OEBh EINE KU TSEQt EP12SEL FRESUM TP1SIZ3 TP1SIZ2 TP1SIZ1 TP1SIZO Table 69 Description of the UCON1 Bits EP12SEL 15123 to TP1SIZO 80 163 1 2 Transmit Data 0 1 This bit determines which type of data packet DATA1 will be sent during the next IN transaction directed to Endpoint 1 or Endpoint 2 Toggling of this bit must be controlled by software RESET clears this bit Endpoint 1 Endpoint 2 Transmit Selection 0 1 1 2 This bit specifies whether the data inside the registers UDT1 are used for Endpoint 1 or Endpoint 2 If all the conditions for a successful Endpoint 2 USB response to a hosts IN token are satisfied TXD1F 0 TX1E 1 STALL2 0 and EP2E 1 except that the EP12SEL Bit is configured for Endpoint 1 the USB responds with a NAK handshake packet RESET clears this bit Endpoint1 Endpoint2 Transmit Enable This bit enables a transmit to occur when the USB Host Controller send an IN token to Endpoint 1 or Endpoint 2 The appropriate endpoint enable bit EP1E or EP2E Bit in the UCON2 register should also be set Software should set the TX1E Bit when data is ready to be transmitted It must be cleared by software when no more data needs to be transmitted If this bit is 0 or TXD1F is set the USB will respond with handshake to a
179. that will be coming The slaves that weren t being ad dressed leave their SM2s set and go on about their business ignoring the coming data bytes 5 2 has no effect in Mode 0 and in Mode 1 can be used to check the validity of the Stop Bit In a Mode 1 reception if SM2 1 the Receive Inter rupt will not be activated unless a valid Stop Bit is received 55 163 uPSD3212A uPSD3212C uPSD3212CV Serial Port Control Register The serial port control and status register is the Special Function Register SCON SCON2 for the second port shown in Figure 27 This register see Tables 43 and 44 contains not only the mode Figure 27 Serial Port Mode 0 Block Diagram Serial Port Interrupt Rx Clock LL gt R1 R Load SBUF Read SBUF Table 43 Serial Port Control Register SCON Internal Bus Write to SBUF Tx Control S6 Tx Clock T Rx Control WAW EE E ec AST ee Internal Bus selection bits but also the 9th data bit for transmit and receive TB8 and 8 and the Serial Port In terrupt Bits TI and RI RxD P3 0 Alt Output Function 22 Shift gt Clock TxD P3 1 Alt Output Function Receive unction Shift 106824 56 163 uPSD3212A uPSD3212C uPSD3212CV Table 44 Description of the SCON Bits SM1 SM0 Shift Register Baud rate fosc 12 SM1 SMO 8 bit UART Baud rate variable SM1 SMO 8 bit UART Baud rate fosc 64
180. the 16 bit product into the concatenated B and Accumulator registers The DIV AB instruction divides the Accumulator by the data in the B register and leaves the 8 bit quo tient in the Accumulator and the 8 bit remainder in the B register of er erations divi i its n 2 shifts to perform the Shot leaves the B COE the ihe that were shifted out The DAA instruction is for BCD arithmetic opera tions In BCD arithmetic ADD and ADDC instruc tions should always be followed by a DAA operation to ensure that the result is also in BCD Note DAA will not convert a binary number to BCD The DAA operation produces a meaningful result only as the second step in the addition of two BCD bytes 17 163 uPSD3212A uPSD3212C uPSD3212CV Table 4 Arithmetic Instructions LL m rons nes WE IT 1 Accumulator only Addressing Modes meme ces x ox p x T INC DPTR DPTR DPTR 1 Data Pointer only MUA AB BASBxA _ _ Accumulator B only Ini A B DIV AB Mod Accumulator and B only Decimal ee Logical Instructions Table 5 page 19 shows list of uPSD321x Devic es logical instructions The instructions that per form Boolean operations AND OR Exclusive OR NOT on bytes operation on a bit by bit basis Th 00110101B an
181. the SFRs not all of the addresses are oc cupied Unoccupied addresses are not implement ed on the chip READ accesses to these addresses will in general return random data and WRITE accesses will have no effect User soft ware should write 05 to these unimplemented lo cations we we un cie Jes COMS i _ K TEN me s Pm rum wer Pam me mes uw Le L Note 1 Register can bit addressing 28 163 uPSD3212A uPSD3212C uPSD3212CV Table 16 List of all SFR _ _ T ELE I peser CL EC T Soo Rose Tor 00 Power out SR Control sz fea mo 00 Timer 0 Low Euge quc P1 NEEDED egister EJ E I Register IA ASCL ADAT7 ADAT6 5 4 ADAT2 ADAT1 B ACON LL ADEN NN ADS ADSO ADSF ADC Data Register ADC Control Register 8 bit Prescaler for ADC clock Serial Control Register
182. the received frame is irretrievably lost and RI is not set If both conditions are met the received 9th data bit goes into RB8 and the first 8 data bits go into SBUF One bit time later whether the above conditions were met or not the unit goes back to looking for a 1 to 0 transition at the RxD input uPSD3212A uPSD3212C uPSD3212CV Figure 31 Serial Port Mode 2 Block Diagram Phase2 Clock 1 2 fosc Internal Bus Write BE C 5 TxD 0 1 Zero Detector hos Start EE Data Tx Control Tx Clock Interrupt Rx Clock RI Load SBUF 1 to 0 Transition Start Rx Control Shift Detector 1FFh ix me Hasa Input x Register Read SBUF M Bus Interna AI06844 Figure 32 Serial Port Mode 2 Waveforms Tx Clock Write to SBUF Send S1P1 Data _ _ ____ Transmit Shift L Fm Start Bit TxD X D2 X D3 X D4 X 05 X D6 X 07 StopBit Th Stop Bit 16 Reset cock mn m R n n n n n n n n n Start Bit RxD Detector Receive Sample Times HHL Shift 06845 63 163 uPSD3212A uPSD3212C uPSD3212CV Figure 33 Serial Port Mode 3 Block Diagram Overflow Timer2 Overflow Internal Bus Zero Detector m Tx Control TI S
183. tion Figure 45 page 87 USB Data Transition Rise Time Notes 2 3 4 USB Data Transition Fall Time Notes 2 3 4 tRFM Rise Fall Time Matching VCRS Output Signal Crossover Volt age 1 3 Note 1 Voc 5V 10 Vss OV TA 0 to 70 C 2 Level guaranteed for range of Vcc 4 5V to 5 5V 3 With RPU external idle resistor 7 5 2 D to Vcc 4 50pF 75ns to 350pF 300ns 5 Measured crossover point of differential data signals 6 USB specification indicates 330ns 84 163 Receiver Characteristics The uPSD321x Devices has differential input ceiver which is able to accept the USB data signal The receiver features an input sensitivity of at least 200mV when both differential data inputs are in the range of at least 0 8V to 2 5V with respect to its local ground reference This is the common mode range as shown in Figure 41 The receiver Figure 41 Minimum Differential Sensitivity volts 00 02 04 06 08 10 12 14 1 6 uPSD3212A uPSD3212C uPSD3212CV tolerates static input voltages between 0 5V to 3 8V with respect to its local ground reference without damage In addition to the differential re ceiver there is a single ended receiver for each of the two data lines The single ended receivers have a switching threshold between 0 8V and 2 0V TTL inputs Differential Input Sensitivity Over Entire Common Mode Range 18 2022 24 26 28 30 32 Common Mode Input Voltage volts
184. ts Timer into its Baud Rate Generator Mode The RCLK and TCLK Bits in the T2CON register configure UART 1 The RCLK1 and TCLK1 Bits in the PCON register configure UART 2 58 163 The Baud Rate Generator Mode is similar to the Auto reload Mode in that a roll over in TH2 causes the Timer 2 registers to be reloaded with the 16 bit value in registers RCAP2H and RCAP2L which are preset by software Now the baud rates in Modes 1 and 3 are deter mined at Timer 2 s overflow rate as follows Mode 1 3 Baud Rate Timer 2 Overflow Rate 16 The timer can be configured for either timer or counter operation In the most typical applica tions it is configured for timer operation C T2 0 Timer operation is a little different for Timer 2 when it s being used as a baud rate generator Normally as a timer it would increment every ma chine cycle thus at the 1 6 the CPU clock frequen Cy In the case the baud rate is given by the formula Mode 1 3 Baud Rate fosc 32 x 65536 RCAP2H RCAP2L where RCAP2H RCAP2L is the content of RC2H and RC2L taken as a 16 bit unsigned inte ger Timer 2 also be used as the Baud Rate Generating Mode This mode is valid only if RCLK TCLK 1 in T2CON or in PCON Note A roll over in TH2 does not set TF2 and will not generate an interrupt Therefore the Timer in upt does have tp d when Timer 2 is in E e e de ransition in T2EX will set EXF2 but wil
185. uPSD3212A uPSD3212C uPSD3212CV Figure 14 State Sequence in uPSD321x Devices 26 163 1 p p2 1 52 53 54 55 56 2 1 2 1 2 1 p2 Read next opcode and Read opcode discard a 1 Byte 1 Cycle Instruction e g INC A Read 2nd Byte Read opcode b 2 Byte 1 Cycle Instruction e g ADD A adrs Read next opcode and Read opcode discard c 1 Byte 2 Cycle Instruction e g INC DPTR AST Read opcode AYAYM nw TIS 1 Byte 2 Cycle MOVX Instruction 81 52 53 54 55 56 p 2 1 p2 pl p2 2 Read next opcode Read next opcode Read next opcode and discard Read next opcode Read next opcode and discard HEHEHEHEHE No Fetch YO No Fetch Read next opcode COO Ea Data Access External Memory 106822 uPSD3200 HARDWARE DESCRIPTION The uPSD321x Devices has a modular architec ture with two main functional modules the MCU Module and the PSD Module The MCU Module consists of a standard 8032 core peripherals and other system supporting functions The PSD Mod ule provides configurable Program and Data mem ories to the 8032 CPU core In addition it has its own set of I O ports and PLD with 16 macrocells for general logic implementation Ports and D are general purpose programmable ports Figure 15 uPSD321x Devices Functional Modules uPSD3
186. uPSD3212C uPSD3212CV Mode 3 Timer 1 in Mode 3 simply holds its count The effect is the same as setting TR1 0 Timer 0 in Mode 3 establishes TLO and THO as two separate counters The logic for Mode 3 on Timer 0 is shown in Figure 26 TLO uses the Timer 0 trol Bits C T GATE TRO INTO and TFO THO is locked into a timer function counting machine cy cles and takes over the use of TR1 and TF1 from Timer 1 Thus THO now controls the Timer 1 In terrupt Mode 3 is provided for applications requiring an extra 8 bit timer on the counter With Timer 0 in Mode 3 an uPSD321x Devices can look like it has three Timer Counters When Timer 0 is in Mode 3 Timer 1 can be turned on and off by switching it out of and into its own Mode 3 or can still be used by the serial port as a baud rate generator or in fact in any application not requiring an interrupt Figure 26 Timer Counter Mode 3 Two 8 bit Counters Control Interrupt Control TRI Interrupt Al06624 54 163 STANDARD SERIAL INTERFACE UART The uPSD321x Devices provides two standard 8032 UART serial ports The first port is connected to pin P3 0 RX and P3 1 TX The second port is connected to pin P1 2 RX and P1 3 TX The op eration of the two serial ports are the same and are controlled by the SCON and SCON registers The serial port is full duplex meaning it can trans mit and receive simultaneously It is also receive
187. uPSD3212C uPSD3212CV Table 66 USB Endpoint0 Transmit Control Register UCONO OEAh HEBES GENE NEED Table 67 Description of the UCONO Bits w sma mw EndpointO Data Sequence 0 1 DATA1 TSEQO This bit determines which type of data packet DATA or DATA1 will be sent during the next IN transaction Toggling of this bit must be controlled by software RESET clears this bit EndpointO Force Stall Bit This bit causes Endpoint 0 to return a STALL handshake when polled by STALLO R W either an IN or OUT token by the USB Host Controller The USB hardware clears this bit when a SETUP token is received RESET clears this bit EndpointO Transmit Enable This bit enables a transmit to occur when the USB Host Controller sends an IN token to Endpoint 0 Software should set this bit when data is ready to be transmitted It must be cleared by software when no more Endpoint 0 data needs to be transmitted If this bit is 0 or the TXDOF is set the USB will respond with handshake to any Endpoint 0 IN tokens RESET clears this bit EndpointO receive enable This bit enables a receive to occur when the USB Host Controller sends an OUT token to Endpoint 0 Software should set this bit when data is be It must cleared by softy h TPOSIZ3 to TPOSIZO 79 163 uPSD3212A uPSD3212C uPSD3212CV Table 68 USB 2 Transmit Control Regis
188. ulting in segments between low speed devices and the ports to which they are connected One Bit Time 1 Mb s Signal pins Driver pass output Signal Rins Vge min Vss 106629 ky 83 163 uPSD3212A uPSD3212C uPSD3212CV Table 78 Transceiver DC Characteristics um _____ _ v Differential Input Sensitivity 3 D 0 CM Var peers m Y Le peememeem Data Line D Leakage OV lt D D lt 3 3 Lm erem tutem wz Om Om Note 1 Voc 5V 10 Vss OV TA 0 to 70 C 2 Level guaranteed for range of Vcc 4 5V to 5 5V 3 With external idle resistor 7 5 2 D to Table 79 Transceiver AC Characteristics tDRATE Low Speed Data Rate Ave bit rate 1 5Mb s 1 596 1 4775 1 5225 Mbit s 1 m tDJR1 Receiver Data Jitter Tolerance o a 5 wava 70 C tDJR2 y 2 f 4 transitido J Figure 43 page 86 tDEOP Differential to EOP Transition Skew Figure 44 page 870 100 tEOPR1 EOP Width at Receiver Rejects as 5 6 tEOPR2 EOP Width at Receiver Accepts as 675 i ition 5 i 7 next transition tUDJ1 Differential Driver Jitter Figure 45 page 87 m tUDJ2 Differential Driver Jitter To paired transi
189. y 145 163 uPSD3212A uPSD3212C uPSD3212CV Figure 75 Synchronous Clock Mode Timing PLD tcH tcL CLKIN gt 4 gt gt REGISTERED OUTPUT 102860 Table 125 CPLD Macrocell Synchronous Clock Mode Timing 5V Devices Conditions Max is rate Unit Maximum Frequency 1 ts tco 40 0 MHz External Feedback Maximum Maximum Frequency Pipelined Data E Input Setup Time ___ I au DIMUS WW SE Ei 1 Fast Slew Rate output available on PA3 ee and PD2 PD1 Decrement times by given amount 2 CLKIN tcLcL tcH tc 146 163 uPSD3212A uPSD3212C uPSD3212CV Table 126 CPLD Macrocell Synchronous Clock Mode Timing 3V Devices PT Turbo Slew Max Aloc rate 22 2 8 5 Parameter Conditions Maximum Frequency 1 External Feedback 40 0 1 tcH tcL Clock Input 25 Minimum Clock Period Note 1 Fast Rate output available 2 1 times by given amount 2 CLKIN tcH tcL Maximum Frequency Figure 76 Asynchronous RESET Preset REGISTER OUTPUT Al02864 Figure 77 Asynchronous Clock Mode Timing Product Term Clock tCHA tCLA gt lt gt CLOCK

ST & T UPSD3212C User's Manual

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ST &amp; T UPSD3212C User's Manual

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ST & T UPSD3212C User's Manual