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Oracle CPU-56T User's Manual

1. These eight bits These three bytes are identify the consecutively numbered architecture type Figure 26 32 bit 4 byte Host ID ID PROM The ID PROM contains specific information on the individual machine including the serial number date of manufacture and assigned Ethernet address The following table lists these commands SPARC CPU 56T 101 OpenBoot Firmware Displaying System Information Table 19 Commands to Display System Information Command Description banner Displays system banner enet addr Displays the Ethernet address idprom Displays ID PROM contents formatted traps Displays a list of SPARC trap types version Displays version and date of the boot PROM show devs Displays a list of all device tree nodes devalias Displays a list of all device aliases 102 SPARC CPU 56T Resetting the System OpenBoot Firmware Resetting the System If your system needs to be reset there are two possibilities e Software reset For this type of reset use the command reset at the Forth command line e Button power on reset In both cases the system begins with the initialization procedures If the system is reset via a button power on reset the power on self test is executed before the initialization if the NVRAM configuration variable lt diag switch gt is set true SPARC CPU 56T 103 OpenBoot Firmware Activating OpenBoot Help Activating OpenBoot Help 104 The Forth Monitor contains an online help whic
2. 98 SPARC CPU 56T Diagnostics OpenBoot Firmware probe scsi all The actual response depends on the devices on the SCSI buses Note A terminal message as answer to the command probe scsi all can take up to two minutes ok probe scsi all pei 1f 0 scsi 2 Target 6 Unit 0 Disk Removable Read Only Device SONY CD ROM CDU 8012 3 1a pei lf pci 4 1 scsi 2 Target 3 Unit 0 Disk FUJITSU M2952ESP SUN2 1G2545 ok Single Device To test a single installed device enter test lt device specifier gt This executes the self test device method of the specified device node Group of Devices Clock To test a group of installed devices enter test all All devices below the root node of the device tree are tested The response depends on the devices having a self test method If a device specifier option is supplied at the command line all devices below the specified device tree node are tested To test the clock function enter ok watch clock Watching the seconds register of the real time clock chip It should be ticking once a second Type any key to stop 22 ok SPARC CPU 56T 99 OpenBoot Firmware Diagnostics The system responds by incrementing a number every second Press any key to stop the test Network To monitor the network connection enter ok watch net Internal loopback test succeeded Transceiver check Using Onboard transceiver Link Up passed Using Onboard transceiver
3. Name EN TIM1 EN MOD32 EN TIM2 Description Controls timer 1 0 Timer disabled 1 Timer enabled Switches between two 16 bit wide timers and one 32 bit wide timer 0 16 bit mode enabled 1 32 bit mode enabled Reserved Controls timer 2 0 Timer disabled 1 Timer enabled Reserved Default 02 00 0 0002 Access r w r w r w This register is used to control the status bits of both timers in the Timer Status register Address 1FF F160 0141 Table 36 Timer Clear Control Register Bit 0 7 5 Name CLR TIM1 CLR TIM2 Timer Status Register The Timer Status register is used to recognize timer underrun conditions 124 Description Clears the status bits of timer 1 in the Timer Status register 0 Timer 1 status bits stay as they are 1 Timer 1 status bits will be cleared Reserved Clears the status bits of timer 2 in the Timer Status register 0 Timer 2 status bits stay as they are 1 Timer 2 status bits will be cleared Reserved Access WwW SPARC CPU 56T System Configuration Registers Maps and Registers Address 1FF F160 0144 5 Table 37 Timer Status Register Bit Name Description Default Access 0 STAT TIM1 Indicates an underrun of timer 1 This can only occur if 0 r timer 1 is enabled and the initial value is greater than 0 0 No underrun of timer 1 has occurred 1 An underrun of timer 1 has occurred 1 ERR TIM1 Indicates that more than one timer u
4. Wind River Systems and design WindView WinRouter and Xmath are registered trademarks or service marks of Wind River Systems Inc Envoy M the Tornado logo Wind River M and Zinc are trademarks or service marks of Wind River Systems Inc Sony is a registered trademark of Sony Corporation Japan Ethernet is a trademark of Xerox Corporation Service Availability Mis a trademark of the Service Availability Forum PowerQUICCT Mis a trademark of Motorola Inc Other product names mentioned herein may be trademarks and or registered trademarks of their respective companies SPARC CPU 56T N a Lu e gt am 2 O Off World Wide Web www fci com 24 hour access to on line manuals driver updates and application notes is provided via SMART our SolutionsPLUS customer support program that provides current technical and services information The Americas Force Computers Inc 4211 Starboard Drive Fremont CA 94538 Tel 1 510 624 5300 Fax 1 510 624 5301 Email support fci com 224548 420 000 AA SPARC CPU 56T Headquarters Europe Force Computers GmbH Lilienthalstr 15 D 85579 Neubiberg M nchen Tel 49 89 608 14 0 Fax 49 89 609 77 93 Email support de fci com Asia Force Computers Japan K K Shibadaimon MF Bldg 4F Shiba Daimon 2 1 16 Minato ku Tokyo 105 0012 Tel 81 03 3437 3948 Fax 81 03 3437 3968 Email support de fci com SPARC CPU 56T Con
5. Link Up Looking for Ethernet packets is a good packet X is a bad packet Type any key to stop The system monitors the network traffic It displays a dot each time it receives a valid packet and displays an X each time it receives a packet with an error which can be detected by the network hardware interface IDE Devices 100 The following is an example output obtained after enterring probe ide ok probe ide Device 0 Primary Master Not Present Device 1 Primary Slave Not Present Device 2 Secondary Master Removable ATAPI Model TOSHIBA CD ROM XM 6702B Device 3 Secondary Slave Not Present ok SPARC CPU 56T Displaying System Information OpenBoot Firmware Displaying System Information The Forth Monitor provides several commands to display system information such as the system banner the Ethernet address for the Ethernet controller the contents of the ID PROM and the version number of the OpenBoot firmware Ethernet Address and Host ID In order to see the Ethernet address and host ID enter the following command at the OpenBoot prompt ok banner The figures below explain how the CPU board s Ethernet address and the host ID are determined FOA A ee 47 40 39 32 31 24 23 16 15 Loo y y These three bytes always These three bytes are remain 00 80 42 consecutively numbered Figure 25 48 bit 6 byte Ethernet Address Byte Byte 3 2 1 0 32 25 24 16 15 8 7 0
6. Network Equipment Building Standards Nonmaskable Interrupt Nonvolatile Random Access Memory OpenBoot Diagnostics PCI Bus Module Printed Circuit Board Peripheral Component Interconnect SPARC CPU 56T Abbreviation PCIO PHY PIE PLCC PLL PMC POST PROM R RIC ROM RTB RTC RTOS SDRAM SELV SPD SRAM STP TPE UART UIC USB UTP VME Revision History Order No 220306 220306 SPARC CPU 56T Rev AA AB Description Peripheral Component Interconnect Input Output Physical Layer PCI Interrupt Engine Plastic Leadless Chip Carrier Phase Locked Loop PCI Mezzanine Card Power On Self Test Programmable Read Only Memory Reset Interrupt Clock Controller Read Only Memory Rear Transition Board Real Time Clock Real Time Operating System Synchronous DRAM Safety Extra Low Voltages Serial Presence Detect Static Random Access Memory Shielded Twisted Pair Twisted Pair Ethernet Universal Asynchronous Receiver Transmitter UPA Interrupt Connector Universal Serial Bus Unshielded Twisted Pair Versa Module Eurocard Date Description May 2003 Preliminary Manual September 2003 Final release version 17 18 Order No 223146 224548 Rev AA AA Date April 2004 November 2004 Description Corrected number of SUN patch for audio support Now it reads 109896 17 added note to abort reset key description corrected feature list of FRctrl Solar
7. Note The Ethernet 1 interface is also accessible as Ethernet 3 via the IOBP CPU 56 Both interfaces can not be accessed at the same time The selection is made automatically by OpenBoot when booting the board and cannot be reversed anymore until the board is rebooted SCSI Two SCSI interfaces 1 and 2 are available via two mini 68 pole SCSI4 connectors Their pinout is given below SPARC CPU 56T 61 Controls Indicators and Connectors 62 SCSIx_D12 SCSIx_D13 SCSIx_D14 SCSIx_D15 SCSIx_DP1 SCSIx_DO SCSIx_D1 SCSIx_D2 SCSIx_D3 SCSIx_D4 SCSIx_D5 1 SCSIx_D6 SCSIx_D7 SCSIx_DPO GND DIFFSENSE TERMPWR TERMPWR n c GND SCSIx_ATN GND SCSIx_BSY SCSIx_ACK SCSIx_RST 94 88 SCSIx_MSG SCSIx_SEL SCSIx_CD SCSIx_REQ SCSIx_lO SCSIx_D8 SCSIx_D9 SCSIx_D10 SCSIx_D11 1 2 3 4 5 6 1 8 9 Figure 12 SCSI 1 2 Connector Pinouts SCSIx_D12 SCSIx_D13 SCSIx_D14 SCSIx_D15 SCSIx_DP1 SCSIx_DO SCSIx_D1 SCSIx_D2 SCSIx_D3 SCSIx D4 SCSIx_D5 SCSIx_D6 SCSIx_D7 SCSIx_DPO GND GND TERMPWR TERMPWR n c GND SCSIx_ATN GND SCSIx_BSY SCSIx ACK SCSIx_RST SCSIx_MSG SCSIx_SEL SCSIx_CD SCSIx_REQ SCSIx_IO SCSIx_D8 SCSIx_D9 SCSIx_D10 SCSIx_D11 Front Panel Note By default the SCSI termination is switched ON for SCSI interface 1 and 2 It can be switched OFF via switches For details see section Switch Settings SPARC CPU 56T On Board Connect
8. PMC3_1044 PMC3_1045 PMC3_1047 SCSI3_D14 SCSI3_D12 SCSI3_PAR1 SCSI3_D13 SCSI3_D1 SCSI3_D15 SCSI3_D7 SCSI3_D4 SCSI3_TPWR SCSI3_D6 SCSI3_PARO SCSI3_REQ SCSI3_CD SCSI3_MSG SCSI3_D8 GND 5V Figure 21 I O Board P2 VMEbus Connector Pinout Rows C D OONOORWNH On Board Connectors SPARC CPU 56T Devices Features and Data Paths Block Diagram usa and daras cd tela pda allan da 73 UltraSPARC lli Processor 0 00 cece eens una nn nn nn nn nn nen 75 Interrupt Controller end 76 PG BS A en a Re ee Die 77 Ethernet Controller ur en A ee iaa 77 SCSI Controller ss etek vse A IN hs A 8 77 SENTINEL64 PCI to PCI Bridge 0 000 ccc eee eee eee nennen 77 PGI to VME Bridge 4 sagen satan a ada Aa ig Deren 77 PCE BUS Bi in 79 Ethernet Controller ai Jawa oka a a Beas A Ghee a eels Gist eal 79 SOUTNDAGE eA 33 A A ha ele 79 POO e Gon O ar A A A A A qlee Wa tad wee ae 79 EBus Interface ooo tcc tect a ee al ae eier er ee ae 79 Media Independent Interface 2220e2s Henne een een een een een nenn 80 VSBilnterf ces zu ea ae ke aan Maas aan ee ae eee AA 80 EBus a en 81 FPGA ica ee ea ae Maine 81 Watchdog sense ee ran A A a 81 Timer ad dios 82 Temperature Sensor Control 00sec enn nennen nenn 82 Eocal 126 ISAC sn Ain 82 Ethernet Interface 1 3 Switching 0 cece nenne nennen 83 LED and Switch Control e ene nee E e eee eee nenn 83 Reset C
9. Serial controller on the EBus Serial interface B Serial controller on the EBus Serial interface C Serial controller on the EBus Serial interface D System Configuration register on the EBus PCIO configuration registers 113 Maps and Registers System Configuration Registers Overview of System Configuration Registers 114 System Configuration Registers The CPU board implements a set of system configuration registers via the field programmable gate array FPGA which is accessible via the EBus The CPU Board System Configuration registers are used to control the on board functions and to receive status information of the board It is subdivided into 16 areas with 16 Bytes each provided with a special function or reserved for future use In the following an overview of the System Configuration registers in the CPU board address space is given Every register is described separately in the following chapters The table below shows an overview of all registers in the CPU board address space Table 25 CPU Board System Configuration Register Address Map Address Range in PA lt 40 0 gt 1FF F160 010016 1FF F160 010016 1FF F160 011016 1FF F160 011016 1FF F160 0111 6 1FF F160 011216 1FF F160 011316 1FF F160 012016 1FF F160 012016 1FF F160 013016 1FF F160 013016 1FF F160 0131 6 1FF F160 01341g 1FF F160 014016 1FF F160 014016 1FF F160 014116 1FF F160 014416 Size 16 Byte 1 Byte 16 Byte 1 Byte 1 Byte 1
10. net cdrom from which you want to boot Use the commands probe scsi and probe ide to examine the system for boot devices Check the SCSI cable for proper termination Check also switch SW 3 of the board for correct SCSI bus termination SPARC CPU 56T Battery Exchange SPARC CPU 56T 139 Battery Exchange Battery Exchange Battery Exchange The battery provides data retention of seven years summing up all periods of actual data use Force Computers therefore assumes that there usually is no need to exchange the battery except for example in case of long term spare part handling Caution e Board System damage Incorrect exchange of lithium batteries can result in a hazardous explosion Therefore exchange the battery as described in this chapter e Data loss If the battery does not provide enough power anymore the RTC is initialized and the data in the NVRAM is lost Therefore exchange the battery before seven years of actual battery use have elapsed e Data loss Exchanging the battery always results in data loss of the devices which use the battery as power backup Therefore back up affected data before exchanging the battery e Data loss If installing another battery type than is mounted at board delivery may cause data loss since other battery types may be specified for other environments or may have a shorter lifetime Therefore only use the same type of lithium battery as is already installed Exchange Procedur
11. 6 IP_ACFAIL 7 IP_SYSFAIL Reset Register Maps and Registers Description Default Access Reflects if a temperature interrupt is pending 0 r 0 No temperature interrupt is pending The temperature senors did not detect a temperature that exceeds the actual limit 1 The temperature interrupt is pending The temperature sensor has detected a temperature above the actual limit Reserved 02 r Reflects if a timer 1 interrupt is pending 0 r 0 No timer 1 interrupt is pending 1 The timer 1 interrupt is pending Reflects if a timer 2 interrupt is pending 0 r 0 No timer 2 interrupt is pending 1 The timer 2 interrupt is pending Reflects if a interrupt from the VMEbus ACFAIL signal 02 r w is pending 0 No ACFAIL interrupt is pending 1 The ACFAIL interrupt is pending The interrupt can be cleared by writing a 1 to this bit Reflects if a interrupt from the VMEbus SYSFAIL signal 02 r w is pending 0 No SYSFAIL interrupt is pending 1 The SYSFAIL interrupt is pending The interrupt can be cleared by writing a 1 to this bit The reset register is used to identify the last occurred reset If all bits are cleared 0 the last reset was a power on reset Only one reset status bit can be active at the same time Every reset clears the previous reset status bit Address 1FF F160 01D4 Table 42 Reset Status Register Bit Name 0 RST KEY 1 RST SW SPARC CPU 56T Description Default Access Reflects whether
12. Interface N N N N N N N N N NNN N Introduction SPARC CPU 56T Introduction Alias disk24 disk23 disk22 disk21 disk20 tape 2 or tape20 tape21 cdrom 2 SCSI Device Disk SCSI target ID 4 Disk SCSI target ID 3 Disk SCSI target ID 2 Disk SCSI target ID 1 Disk SCSI target ID 0 First tape drive SCSI target ID 4 Second tape drive SCSI target ID 5 CD ROM partition f SCSI target ID 6 OpenBoot Firmware SCSI Interface N N N N N N N The following table lists device aliases available for other devices Table 15 OpenBoot Aliases for Miscellaneous Devices Alias cdrom 3 disk 3 disk33 disk32 disk31 disk30 ide ebus flash flash prog floppy keyboard mouse net net2 net3 pci ttya SPARC CPU 56T Device CD ROM partition f on board IDE secondary master Disk on board IDE primary master Disk on board IDE secondary slave Disk on board IDE secondary master Disk on board IDE primary slave Disk on board IDE primary master on board IDE EBus Flash EPROM Flash EPROM programming mode Floppy disk Keyboard Mouse Ethernet 1 interface via front panel Ethernet interface 2 Ethernet 3 interface via IOBP Primary PCI bus Serial interface A 93 OpenBoot Firmware Introduction Alias Device ttyb Serial interface B tyyc Serial interface C tyyd Serial interface D vme VME OBDIAG OBDIAG stands for OpenBoot Diagnostics and is an additional diagnostics drop
13. ausschlie lich SELV Kreise Sicherheitskleinspannungsstromkreise an e Die L nge des mit dem Board verbundenen Twisted Pair Ethernet Kabels darf 100 m nicht berschreiten Falls Sie Fragen haben wenden Sie sich bitte an Ihren Systemadministrator Batterie Muss eine Lithium Batterie auf dem Board ausgetauscht werden siehe Appendix Battery Exchange beachten Sie die folgenden Sicherheitshinweise e Fehlerhafter Austausch von Lithium Batterien kann zu lebensgef hrlichen Explosionen f hren Verwenden Sie deshalb nur den Batterietyp der auch bereits eingesetzt wurde und befolgen Sie die Installationsanleitung SPARC CPU 56T 25 e Verwenden Sie die Batterien l nger als sieben Jahre kann dies zu Datenverlusten f hren Tauschen Sie deshalb die Batterie aus bevor sieben Jahre reiner Betrieb vor ber sind e Der Austausch der Batterie bringt immer einen Datenverlust bei den Komponenten mit sich die sich durch die Batterie die Stromversorgung sichern Sichern Sie deshalb vor dem Batterieaustausch Ihre Daten Umweltschutz Entsorgen Sie alte Batterien und oder Boards stets gem der in Ihrem Land g ltigen Gesetzgebung wenn m glich immer umweltfreundlich 26 SPARC CPU 56T Introduction Features oscars oo anida asno dante on 28 Standard Compliance oii u un un eee eee nn 30 Ordering Information rs O wee ee 31 Pr duet NOoMmencl t ret Ts eset koala dee A A dC 31 Order NuMberstvas tara daa E de der 31 SPARC CP
14. between the different operation modes of LED 2 Address 1FF F160 0110 Table 28 LED Control Register 2 Bit Name 4 0 LED_DISPLAY 7 5 Reserved LED Control Register 3 Description Default Access User LED mode r w 000002 OFF 000012 Green 000102 Red 00011 Weak red 001012 Slow blinking green 1 2 Hz 001102 Slow blinking red 00111 Slow blinking weak red 010012 Blinking green 1 Hz 01010 Blinking red 01011 Blinking weak red 01101 Fast blinking green 2 Hz 011102 Fast blinking red 011112 Fast blinking weak red 00000 IDE activity 10011 IDE 1 2 Ethernet activity 11000 Ethernet 1 11001 Ethernet 2 110102 Ethernet 3 110112 Ethernet 4 111002 Ethernet 1 3 11101 Ethernet 2 4 11111 Ethernet 1 2 3 4 At all other values the LED is OFF These bits are always zero r This register is used to switch between the different operation modes of LED 3 118 SPARC CPU 56T System Configuration Registers Address 1FF F160 0112 Table 29 LED Control Register 3 Bit 4 0 7 5 Name LED_DISPLAY Reserved LED Control Register 4 This register is used to switch between the different operation modes of LED 4 SPARC CPU 56T Maps and Registers Description Default VME activity 000002 000002 Red Universe II asserted VME SYSFAIL signal to the VMEbus Green Universe II accesses the VMEbus as master OFF No VME SYSFAIL asserted and no activity of Uni
15. bit mode 000016 r w 000016 Timer disabled 000116 Timer run out time is 10 us FFFFje Timer run out time is 655 35 ms 31 16 TIMER1 INIT Initialization time of timer 1 in 16 bit mode 000016 r w 000016 Timer disabled 000116 Timer run out time is 10 us FFFFje Timer run out time is 655 35 ms 31 0 TIMER1 INIT Initialization time of timer 1 in 32 bit mode 0000000016 r w 0000 000016 Timer disabled 0000 000116 Timer run out time is 10 us FFFE FFFFjg Timer run out time is 42949 67295 s Timer Counter Status Register The following four registers are used to read the current timer value of both timers The 32 bits are also distributed as big endian To obtain the correct timer status when reading all two or four bytes of a timer an 16 or 32 bit access is necessary 126 SPARC CPU 56T System Configuration Registers Maps and Registers Address 1FF F160 014C 1FF F160 014F Table 39 Timer Counter Status Register Bit Name 15 0 TIMER2 VALUE 31 16 TIMER1 VALUE 31 0 TIMER1 VALUE Interrupt Registers Description Default Current value of timer 2 in 16 bit mode 000016 000016 Timer 2 is not running 000116 Timer 2 will initialize again during the next 10 us 7FFFje Timer 2 needs 327 67 ms until next initialization FFFFj6 Timer 2 needs 655 35 ms until next initialization Current value of timer 1 in 16 bit mode 000016 000016 Timer 1 is not running 000116 Timer 1 will initialize again during the nex
16. c 3 PMC3_1012 n c 4 PMC3_1016 n c 5 PMC3_1019 n c 6 PMC3_1023 n c 7 PMC3_1026 n c 8 PMC3_1030 n c 9 PMC3_1033 n c 10 PMC3_1037 n c 11 PMC3_1040 GND 12 AC97_RSTH 5V 13 AC97_SYNC n c 14 AC97_BITCLK n c 15 SCSI3_DO n c 16 SCSI3_DO n c 17 SCSI3_D3 n c 18 SCSI3_D2 n c 19 SCSI3_D5 n c 20 SCSI3_D5 n c 21 SCSI3_ATN GND 22 SCSI3_ACK n c 23 DIFFSENSE n c 24 SCSI3_RST n c 25 SCSI3_BSY n c 26 SCSI3_BSY n c 27 SCSI3_IO n c 28 SCSI3_D11 n c 29 SCSI3_D10 n c 30 SCSI3_D10 GND 31 SCSI3_D9 5V 32 Figure 20 I O Board P2 VMEbus Connector Pinout Rows Z B SPARC CPU 56T 69 Controls Indicators and Connectors 70 OONOORWNH c PMC3_103 PMC3_106 PMC3_1010 PMC3_1013 PMC3_1017 PMC3_1020 PMC3_1024 PMC3_1027 PMC3_1031 PMC3_1034 PMC3_1038 PMC3_1041 AC97_SDATAOUT AC97_SDATAIN 3 3V SCSI3_D14 SCSI3 D12 SCSI3_PAR1 SCSI3_D13 SCSI3_D1 SCSI3_D15 SCSI3_D7 SCSI3_D4 SCSI3_TPWR SCSI3_D6 SCSI3_PARO SCSI3_REQ SCSI3_CD SCSI3_MSG SCSI3_D8 SCSI3_SEL SCSI3_SEL ZABCD D PMC3_104 PMC3_107 PMC3_1011 PMC3 1014 PMC3_1018 PMC3_1021 PMC3_1025 PMC3_1028 PMC3_1032 PMC3_1035 PMC3_1039 PMC3_1042
17. devices attached to them e Serial Presence Detects SPDs e On board temperature sensor e Board Information Blocks BIBs BIBs are used for internal purposes only and are therefore not further described in this guide All other devices are I2C bus slaves and are identified by unique addresses which are given in the table below Device I2C Bus 12C Bus Slave Address Temperature sensor MAX1617 2 0011 0002 SPD CPU 56 PROM Bank 1 4 24C04 Serial EPROM 2 1010 00x2 SPD MEM 550 PROM Bank 1 4 24C04 Serial EPROM 2 1010 01x2 SPARC CPU 56T EBus Ethernet Interface 1 3 Switching Devices Features and Data Paths As mentioned earlier in this guide Ethernet interface 1 is available via front panel and Ethernet interface 3 via the CPU board s IOBP Only one of both interfaces can be active at the same time The selection which interface is active is made at board reset by the FPGA s internal logic It depends on the Miscellaneous Control Register bits 5 to 7 and on which Ethernet interface provides a link The Miscellaneous Control Register is set by OpenBoot while booting the board For information on how to change the default setting refer to the SPARC CPU 56 T OpenBoot Enhancements Programmer 5 Guide which is available via the Force Computers S M A R T service By default the selection is made as described in the following table Link at Interface 1 Link at Interface 3 Activated Ethernet Interface Yes Yes 1 Yes No 1 No Yes 3
18. e Universe Ethernet Controller The used Ethernet controller is an Intel 82540 It corresponds to Ethernet interface 2 available via the front panel and supports 10 100 1000BaseT Ethernet Further important features are e Integrated PHY in a small package uBGA196 e Compatibility with IEEE 802 3 Ethernet e DMA capability e Interrupt generation SCSI Controller The used SCSI controller is a LSI53C1010 It supports two dual U2W LVD SCSI buses with a SCSI data transfer rate of up to 160 MByte s for each channel Both SCSI interfaces are available via the front panel Two interrupts are generated by the SCSI controller for interrupting the main processor Both SCSI interfaces have an on board termination which can be enabled and disabled via on board switches By default the SCSI termination is enabled SENTINEL64 PCI to PCI Bridge The SENTINEL64 PCI To PCI bridge is used to connect the primary PCI bus A to the secondary PCI bus B For details about the SENTINEL64 device refer to the SENTINEL64 Reference Guide available via the Force Computers S M A R T server PCI to VME Bridge The used PCI To VME bridge is a Tundra Universe II device Its main features are e Fully compliant to VME64 bus standard SPARC CPU 56T 77 Devices Features and Data Paths PCI Bus A 78 e Integral FIFOs for write posting to maximize bandwidth utilization e Programmable DMA controller with linked list mode e CPU or peripheral boards functio
19. in driver program which serves as an NVRAM configuration feature It allows to test the hardware by calling OBDIAG when the OpenBoot firmware is present and the lt ok gt prompt has appeared During the start up sequence of the CPU OpenBoot searches for the presence of devices on all expansion buses and evaluates their characteristics such as device ID device type vendor ID and revision ID In order to test the hardware OBDIAG requires selftest methods for the discovered devices If OBDIAG does not find any selftest methods in the device nodes it looks for its own selftest methods Executing OBDIAG There are two different methods to execute OBDIAG a Via Script b Manually Via Script In order to execute OBDIAG via script set two configuration variables by enterring setenv mfg mode chamber setenv diag switch true Now a script of additional diagnostic tests is executed automatically after each POST from OBDIAG provided that POST has been running without failure during hardware power on Manually In order to execute OBDIAG manually enter the following command at the ok prompt obdiag 94 SPARC CPU 56T Introduction OpenBoot Firmware When OBDIAG is called the lt obdiag gt test prompt appears and you can now choose the required test You can run single tests a number of tests all tests or all tests with exceptions If the test has passed successfully a short test comment will appear on screen In order to return to
20. of the air circulating around the board and not to the actual component temperature e Board damage Operating the board in a chassis without forced air cooling may lead to board damage When operating the board make sure that forced air cooling is available e Board damage High humidity and condensation on the board surface causes short circuits Do not operate the board outside the specified environmental limits Make sure the board is completely dry and there is no moisture on any surface before applying power Do not operate the board below 0 C Table 5 Environmental Requirements Feature Operating Non Operating Temperature 0 C to 50 C 40 C to 85 C Forced airflow 300 LFM linear feet per minute Temp change 0 5 C min 1 0 C min Rel humidity 5 to 95 non condensating at 40 C 5 to 95 non condensating at 40 C Altitude 300 m to 3 000 m 300 m to 13 000 m Vibration 10 to 15 Hz 2 mm amplitude 5 mm amplitude 15 to 150 Hz 28 58 SPARC CPU 56T Requirements Installation Feature Operating Non Operating Shock 58 11 ms halfsine 15g 11 ms halfsine Free fall 100 mm 3 axes 1 200 mm all edges and corners packed state Power Requirements The board power requirements depend on the installed hardware accessories In the following table you will find typical examples of power requirements without any accessories installed If you want to install accessories on the board the load of the respectiv
21. parameter is set to true To set specific parameters use the setenv command as follows setenv lt configuration_parameter gt lt value gt The configuration parameters in the following table are involved in the boot process Table 17 OpenBoot Configuration Parameters Parameter Default Value Description auto boot true If true automatic booting after power on or reset boot device disk Device from which to boot boot file empty string File to boot diag switch false If true run in diagnostic mode test results are shown boot up takes longer If false normal mode short boot up diag device net Device from which to boot in diagnostic mode diag file empty string File to boot in diagnostic mode When booting an operating system or another stand alone program and neither a boot device nor a filename is supplied the boot command of the Forth monitor takes the omitted values from the NVRAM configuration parameters If the parameter lt diag switch gt is false the parameters lt boot device gt and lt boot file gt are used Otherwise the OpenBoot firmware uses the parameters lt diag device gt and lt diag file gt for booting SPARC CPU 56T 97 OpenBoot Firmware Diagnostics Diagnostics The Forth Monitor includes several diagnostic routines These on board tests let you check devices such as network controller SCSI devices floppy disk system memory clock keyboard and audio User installed devices can be tested if t
22. shining red When the key is pressed for a period shorther than 0 5 s an abort is generated which is indicated by the LED 1 shining weak red Note An abort should only be triggered if an application under Solaris or OpenBoot hangs Do not trigger an abort to enter OpenBoot or to bypass the diagnostic routine during power up After triggering an abort the board is in diagnostic mode and the OpenBoot ok prompt appears In this mode you can diagnose what caused the program to hang However the board is not fully initialized and therefore is not fully functional To regain the full functionality you need to trigger a reset Connectors The board provides the following connectors at its front panel e Serial SPARC CPU 56T 59 Controls Indicators and Connectors Front Panel e Keyboard Mouse e Ethernet e SCSI Serial I O Two serial RS 232 interfaces A and B are available via two Mini D Sub 9 connectors Their pinouts are given below 6 SERA_DSR 6 091 SERA_DCD 1 7 SERA_RTS 99 SERA_RXD 2 8 SERA_CTS 99 SERA TXD 3 9 SERA_RI 9 99 SERA_DTR 4 u Ol5 GND 5 Figure 5 Serial A Connector Pinout 7 SERBRTS 99 SERB_RXD 8 SERB CTS O SERB_TXD 9 SERB_RI 5V 9 99 A zen DTR Figure 6 Serial B Connector Pinout He DSR 6 69 SERB_DCD The signal provided by pin 9 of serial interface B depends on the value of the OpenBoot variable tty rs422 enable If it is set to true pin 9 holds 5V and serves as power feed for t
23. signaling level is set accordingly This is illustrated in the figure below ES sv A 3 3V Figure 2 Location of PMC Voltage Keys By default PMC slots 3 and 4 have a signaling level of 3 3V and PMC slot 2 has a signaling level of 5V A description of how to change the signalling level for a PMC slot is given in the following installation procedure Note A 66 MHz PCI bus configuration requires that the signaling level and therefore the VI O voltage is 3 3 V SPARC CPU 56T Hardware Accessories Installation Installation Procedure Remove I O board If neccessary change signalling level Install PMC module Reinstall I O board Note To ensure proper EMC shielding either operate each PMC slot with a blind panel or with a PMC module installed If the SPARC CPU 56T is upgraded with PMC modules ensure that the blind panels are stored in a safe place in order to be used again when removing the respective PMC module Processor PMC modules are only supported in non monarch mode Removing I O Board 1 Remove the 14 screws from I O board which fix it to CPU board SPARC CPU 56T 41 Installation Hardware Accessories 2 Carefully remove I O board from CPU board by unplugging it from PMC connectors Changing Signaling Level 1 Remove screw which fixes the voltage key to IO board Voltage Key L yo Screw 2 Remove voltage key 3 Place voltage key into hole which corresponds to desir
24. 0 Status of Ethernet interface 1 0 Disabled 1 Enabled Default Access 02 r w 02 r w 02 r w 02 r Ww 12 r SPARC CPU 56T System Configuration Registers Bit Name Description 6 ETH3 EN Status of Ethernet interface 3 0 Disabled 1 Enabled 7 Reserved Always zero User LED Control Registers The following registers control front panel LED related features LED Control Register 1 Maps and Registers Default Access 02 Y 02 Y This register is used to switch between the different operation modes of LED 1 Address 1FF F160 0110 Table 27 LED Control Register 1 Bit Name Description 4 0 LED_DISPLAY Board status 000002 Red Board reset Weak red Board abort during reset access Green Board running Blinking red weak red No PCI activity within the last two seconds Blinking green No boot code found Weak red 12V power supply on the VME backplane is not available User LED mode 001002 LED is OFF 000012 LED shines green 000102 LED shines red IDE activity 100112 IDE 1 2 Ethernet activity 110002 Ethernet 1 11001 Ethernet 2 11010 Ethernet 3 110112 Ethernet 4 111002 Ethernet 1 3 111013 Ethernet 2 4 11111 Ethernet 1 2 3 4 At all other values the LED is OFF 7 5 These bits are always zero SPARC CPU 56T Default Access 000002 r w 117 Maps and Registers LED Control Register 2 System Configuration Registers This register is used to switch
25. 000 eens 50 Installing Sol tisa 2 2a BEG A A a ii 51 Solaris Driver Package athens ana Sa ee EN AA i 52 FREgEIE Sro ma a o ar as e 53 FREVME nasser aA V ead Ade a ee at OHS 53 SPARC CPU 56T 33 34 AA RE a ee 54 FRCctrl FR platmod ara A IAS beware GAY Ma ei aig eee Aye es 55 SPARC CPU 56T Action Plan Action Plan In order to install the board the following steps are necessary and will be described in further detail in the sections of this chapter Start Installation Check whether requirements are met Hardware accessories to be installed YES enanas o Vv __ Check switch settings M Y a beard y M Install hardware accessories Check switch settings Configure backplane Install board Install Solaris Install Solaris Driver Package Installation Finished SPARC CPU 56T Installation 35 Installation Requirements Requirements In order to meet the environmental requirements the CPU board has to be tested in the system in which it is to be installed Before you power up the board calculate the power needed according to your combination of board upgrades and accessories Environmental Requirements Caution 36 The environmental conditions must be tested and proven in the used system configuration The conditions refer to the surrounding of the board within the user environment Note Operating temperatures refer to the temperature
26. 0UT signals on lower and higher slots on backplane where no board is plugged to ensure that daisy chain is not interrupted If configured accordingly the CPU board recognizes automatically whether it is plugged into slot 1 of the VMEbus backplane or in any other slot This auto configuration feature requires SW4 2 to be set to the OFF position The VMEbus system controller is enabled via auto configuration if the CPU board is plugged into slot 1 Otherwise it is disabled Caution Damage of the Board or Other VMEbus Participants A If more than one system controller is active in the VMEbus system the board or other VMEbus participants can be damaged Therefore always ensure that only one CPU board is configured to be system controller in the VMEbus system 48 SPARC CPU 56T Board Installation Installation Installing the CPU Board Procedure 1 Check system documentation for all important steps to be taken before switching off power 2 Take those steps 3 Switch off power 4 Plug board into system slot on left hand side Note Make sure all other boards which are plugged into the system are to the right of the system board 5 Fasten board with screws 6 Plug interface cables into front panel connectors if applicable 7 Switch on power Removing the CPU Board Procedure 1 Check system documentation for all important steps to be taken before switching off power 2 Take those steps 3 Switch off power SPARC C
27. 160 0131 Table 33 Watchdog Timer Trigger Register Bit Name Description Access 2 0 1 Reserved w 3 WDOG TRIG This bit is used to trigger the watchdog timer If the watchdog is w enabled through the switch SW1 3 the software must set this bit within the time period configured in the Watchdog Control register If a watchdog interrupt is pending it will be cleared by triggering the watchdog 0 The watchdog timer is not triggered 1 The watchdog timer is triggered 7 4 1 Reserved w 122 SPARC CPU 56T System Configuration Registers Maps and Registers Watchdog Timer Status Register The Watchdog Timer Status register reflects the watchdog timer status Address 1FF F160 0134 Table 34 Watchdog Timer Status Register Bit Name Description Default Access 0 STAT WDOG This bit reflects the status of the watchdog timer 02 r 0 The watchdog timer has not reached the interrupt time 1 The watchdog timer has exceeded the interrupt time It is necessary to trigger the watchdog timer 7 1 0 Reserved 00000002 r Timer Registers The timer can be used as two independent 16 bit countdown timers with a timer interval of 10 us and a total maximum run out time of 655 35 ms Two independent interrupts are possible which can be enabled or disabled refer to Interrupt Registers section A counter read back register set is also available which always shows the correct timer value Both timers can also be used as one 32 bit cou
28. 6 001 8000 000016 001 8FFF FFFF16 001 9000 000016 001 9FFF FFFF16 Size 256 MByte 256 MByte 256 MByte 256 MByte UltraSPARC lli Internal CSR Space The UltraSPARC IIi internal configuration space registers CSR are used for the configuration of the peripheral parts of the CPU e g the PCI bus module PBM the I O memory management unit IOM and the interrupt unit Table 22 UltraSPARC Ili Internal CSR Space Physical Address Range 1FE 0000 0000165 1FE 0000 01FF16 1FE 0000 020016 1FE 0000 03FF16 1FE 0000 040016 1FE 0000 1FFF16 1FE 0000 200016 1FE 0000 5FFF16 1FE 0000 600016 1FE 0000 9FFF16 1FE 0000 A00016 1FE 0000 A7FF 16 1FE 0000 A80016 1FE 0000 EFFF 6 1FE 0000 F00015 1FE 00FF F018 5 1FE 00FF F02016 1FE 00FF F02846 1FE 0OFF FFFF 1FE 0100 000015 1FE 0100 00414 PCI Bus Address Map Size 512 Byte 512 Byte 7 KByte 16 KByte 12 KByte 2 KByte 22 KByte 23 MByte 8 Byte 4 KByte 65 Byte Maps and Registers Bank Memory Location DIMM Type 4 SPARC MEM 550 DIMM 2 6 DIMM3 7 Description PBM IOM PCI interrupt engine PIE PBM PIE IOM PIE Memory control unit MCU PIE MCU PBM The PCI bus address space is divided into areas for the different PCI accesses e g configuration access I O access or memory access These areas are distributed to the PCI devices on the SPARC CPU 56 The address allocation of the devices is made dynamically during the
29. 94 VME64 Extensions Draft Standard Draft 1 8 Jun 13 1997 Spartan XC520XL FPGA specifications 19 Safety Notes EMC The text in this chapter is a translation of the Sicherheitshinweise chapter This section provides safety precautions to follow when installing operating and maintaining the board We intend to provide all necessary information to install and handle the board in this Installation Guide However as the product is complex and its usage manifold we do not guarantee that the given information is complete If you need additional information ask your Force Computers representative The board has been designed to meet the standard industrial safety requirements It must not be used except in its specific area of office telecommunication industry and industrial control Only personnel trained by Force Computers or persons qualified in electronics or electrical engineering are authorized to install remove or maintain the board The information given in this manual is meant to complete the knowledge of a specialist and must not be taken as replacement for qualified personnel The board has been tested in a Standard Force Computers system and found to comply with the limits for a Class A digital device in this system pursuant to part 15 of the FCC Rules respectively EN 55022 Class A These limits are designed to provide reasonable protection against harmful interference when the system is operated in a commercial
30. 99 Group Of DEVICES nr una er E Ina a wea pada a ek 99 Clock acacia aa eae ide ae ae TAA Dede ee ae eee eet 99 NetWork enas a aA lo Gear geecd ake 100 IDE DEVICES isn ee a a A Seale ia 100 Displaying System Information ooooocoroccnn nn nn nn nn 101 Ethernet Address andiHostID 2 22 232 0 ee A ER ee Bl 101 ID PROM Hu a oda tik eet eee Leda deed Paid Pag a ad oe dered deere Sant 101 Resetting the System nr 103 Activating OpenBoot Help cece cece ee eee eee eee eee nun 104 SPARC CPU 56T 87 OpenBoot Firmware Introduction Introduction CORE 88 The OpenBoot firmware consists of the Common Operations and Reset Environment CORE the power on selftest POST the OpenBoot Diagnostics OBDIAG and the OpenBoot itself as well as support for the VxWorks real time operating system RTOS The OpenBoot firmware is subject to changes For the newest version and how to upgrade refer to the SMART service accessible via the Force Computers World Wide Web site www forcecomputers com Note The appearance of the on screen output shown in the examples can differ from the appearance of the output on your monitor according to your device tree CPU architecture For more information on the OpenBoot firmware see the OpenBoot 4 x Manual Set CORE is responsible for setting up proper environments for booting purposes It first initializes the system to a status where different firmware can be loaded from CORE au
31. Byte 1 Byte 16 Byte 1 Byte 16 Byte 1 Byte 1 Byte 1 Byte 16 Byte 1 Byte 1 Byte 1 Byte Access r w r w r w r w r w r w r w WwW Default 0016 0016 0016 0016 0016 0016 0816 FF16 0016 0016 FF16 0016 Description Function Unit Miscellaneous Control Miscellaneous Control register Function Unit Display LED 1 Control register LED 2 Control register LED 3 Control register LED 4 Control register Function Unit External Failure External Failure Status register Function Unit Watchdog Watchdog Control register Watchdog Trigger register Watchdog Status register Function Unit Timer Timer Control register Timer Clear Control register Timer Status register SPARC CPU 56T System Configuration Registers Address Range in PA lt 40 0 gt 1FF F160 014816 1FF F160 014916 1FF F160 014A 16 1FF F160 014B 16 1FF F160 014C 16 1FF F160 014D 46 1FF F160 014E16 1FE F160 014F 46 1FF F160 018016 1FF F160 018016 1FF F160 018416 1FF F160 01D014 1FF F160 01D414 1FF F160 01E016 1FF F160 01E016 1FF F160 01E14 1FF F160 01E216 1FF F160 01E316 1FF F160 01EF16 1FF F160 01F016 1FF F160 01FEx6 1FF F160 01FF16 Size 1 Byte 1 Byte 1 Byte 1 Byte 1 Byte 1 Byte 1 Byte 1 Byte 16 Byte 1 Byte 1 Byte 16 Byte 1 Byte 16 Byte 1 Byte 1 Byte 1 Byte 1 Byte 1 Byte 16 Byte 1 Byte 1 Byte Access r w r w r w r w r w r w r w r w Miscellaneous Control Registe
32. E IDE2 e Parallel PAR Serial SERC SERD e USB 1 and 2 USB1 USB2 e 10 100 1000 Mbit Ethernet 4 ETH4 e Floppy FDC e USB 3 and 4 USB3 USB4 e SUN or PS 2 keyboard mouse interface KBD PC A 4 ETH4_MDO ETH3_TX 1 2 GND ETH3_TX END 2 3 MTH4_MDO ETH3_RX VME RTRY 3 4 GND ETH3_RX VMEA24 4 5 ETH4_MD1 PAR_INITH VMEA25 5 6 GND PAR_SLCT VMEA26 6 7 ETH4_MD1 PAR_PE VMEA27 7 8 GND PAR_AFD VMEA28 8 9 ETH4_MD2 PAR_ERR VMEA29 9 GND PAR_SELIN VME A30 ETH4_MD2 PAR_DO VME A31 GND PAR_D1 GND ETH4_MD3 PAR_D2 5V GND PAR_D3 VME D16 ETH4_MD3 PAR_D4 VME D17 GND PAR_D5 VME D18 ETH4_V2P5 PAR_D6 VME D19 GND PAR_D7 VME D20 SMB_CLK IDE2_D7 VME D21 GND IDE2_D6 VME D22 SMB_DAT IDE2_D5 VME D23 GND IDE2_D4 GND KBD_RDETECT IDE2_D3 VME D24 GND IDE2_D2 VME D25 KBD_RKBD6 IDE2_D1 VME D26 GND IDE2_DO VME D27 KBD_RMSE7 IDE2_DREQ VME D28 GND IDE2_IOR VME D29 KBD_RMSE4 IDE2_DACK VME D30 GND IDE2_A1 VME D31 KBD_RKBD5 IDE2_AO GND GND IDE2_CSOH 5V Figure 18 CPU Board P2 VMEbus Connector Pinout Rows Z B SPARC CPU 56T 67 Controls Indicators and Connectors On Board Connectors 1 SERC_RXD SERC_DTR 1 2 SERC_TXD SERC_DSR 2 3 SERC_RTS SERC_DCD 3 4 SERC_CTS SERC_RI 4 5 SERD_RXD SERD_DTR 5 6 SERD_TXD SERD_DSR 6 7 SERD_RTS SERD_DCD 7 8 SERD_CTS SERD_RI 8 9 USB1 USB3 9 USB1 USB3 USB2 USB4 USB2 USB4 3 3V local Reserved Reset_To_IOBP Reset_
33. E_SYSFAIL Description Enables the watchdog timer interrupt 0 Watchdog timer interrupt is disabled 1 Watchdog timer interrupt is enabled This bit is always zero Enables the Temperature Interrupt 0 Temperature interrupt is disabled 1 Temperature interrupt is enabled This bit is always zero Enables the timer 1 interrupt 0 Timer 1 interrupt is disabled 1 Timer 1 interrupt is enabled Enables the timer 2 interrupt 0 Timer 2 interrupt is disabled 1 Timer 2 interrupt is enabled Enables the interrupt of the deassertion of the VMEbus ACFAIL signal 0 ACFAIL interrupt is disabled 1 ACFAIL interrupt is enabled Enables the interrupt of the deassertion of the VMEbus SYSFAIL signal 0 SYSFAIL interrupt is disabled 1 SYSFAIL interrupt is enabled Interrupt Pending Status Register This register reflects whether a certain interrupt is pending Address 1FF F160 0184 Table 41 Interrupt Pending Status Register Bit Name 0 IP_WDT 1 Reserved 128 Description System Configuration Registers Default 0 0 0 0 0 02 02 Reflects if a Watchdog Timer Interrupt is pending 0 No Watchdog timer interrupt is pending 1 The Watchdog timer interrupt is pending Reserved Access r w r w r w r w r w r w r w r w Default Access 0 r SPARC CPU 56T System Configuration Registers Bit Name 2 IP_TEMP 3 Reserved 4 IP_TIMER1 5 IP_TIMER2
34. From_lOBP PAR_ACK Reserved PAR_BSY FDC_DENSEL PAR_STB FDC_DENSENSE IDE2_ACT FDC_INDEX IDE2_D8 FDC_DRVSELO IDE2_D9 FDC_DRVSEL1 IDE2_D10 FDC_MTRO IDE2_D11 FDC_DIR IDE2_D12 FDC_STEP IDE2_D13 FDC_WDATA IDE2_D14 FDC_WRGATE IDE2_D15 FDC_TARCKO IDE2_lOW FDC_WRPROT IDE2_IORDY FDC_RDATA IDE2_INT FDC_HEADSEL IDE2_CBLID FDC_DISKCHG IDE2_A2 GND IDE2_CS1 5V Figure 19 CPU Board P2 VMEbus Connector Pinout Rows C D I O Board P1 carries standard VME signals and is therefore not further described in this guide P2 connector carries standard VME signals as well as the following Force Computers specific signals e Sound AC97_ e SCSI3 SCSI3_ e PMC3 PMC3_ 68 SPARC CPU 56T On Board Connectors Z PMC3_101 GND PMC3_108 GND PMC3_1015 GND PMC3_1022 GND PMC3_1029 10 GND 11 PMC3_1036 12 GND 13 PMC3_1043 14 GND 15 PMC3_1046 16 GND 17 SCSI3_D3 18 GND 19 SCSI3_D2 20 GND 21 SCSI3_ATN 22 GND 23 SCSI3_ACK 24 GND 25 SCSI3_RST 26 GND 27 SCSI3_IO 28 GND 29 SCSI3_D11 30 GND 31 SCSI3_D9 32 GND WOONDORWHN ZABCD Controls Indicators and Connectors A B PMC3_IO2 5V 1 PMC3_IO5 GND 2 PMC3_IO9 n
35. HERNET4 IOBP CPU 56 fregei0 FRCvme The FRCvme is a set of drivers which handles the Universe II device The following functions are supported e Master windows SPARC CPU 56T 53 Installation Board Installation e Slave windows e Interrupts DMA controller e VME arbiter e Mailboxes Additionally the FRCvme package provides a common programming interface for application and driver development For more detailed information and board specific notes refer to the Solaris Driver Package Installation and Reference Guide and the Solaris VMEbus Driver Programmer s Guide FRCflash FRCctrl 54 The Solaris 2 x flash memory driver provides access to the flash memory device Depending on the CPU board s switch settings the flash memory is accessible as one user flash or is divided into a boot and a user section The following table shows the effects the different CPU board switch settings have on the flash segmentation and the flash write protection Table 10 Flash Segmentation and Write Protection SW1 1 Setting SW1 2 Setting Flash Segmentation Write Protection Boot from OFF OFF 16 MByte user flash write protected PLCC PROM ON OFF 16 MByte user flash not PLCC PROM write protected OFF ON 1 MByte boot flash 15 MByte user Flash memory device flash write protected ON ON 1 MByte boot flash 15 MByte user Flash memory device flash not write protected The FRCctrl driver contains the sysconfig device driver which offers
36. No No 1 LED and Switch Control The FPGA internal logic is responsible for e Control of front panel LEDs Readback of switches SW1 4 Reset Control The FPGA handles all resets and distributes them to the CPU Possible reset sources are listed in the following table Table 12 Reset Sources Reset Source Watchdog reset Front panel key Two pin connector on CPU board s IOBP VMEbus SPARC CPU 56T Description On expiry the watchdog timer can generate a reset Depending on the time the key is pressed either a reset or a board abort is issued By shortcutting this connector a reset is issued Two directions are possible the VMEbus resets the CPU board or the CPU board resets the VME bus 83 Devices Features and Data Paths EBus Reset Source Description Power up reset If one or more on board voltages are not within their thresholds a reset is issued PMC reset A PMC module in non monarch mode can reset the CPU board PLCC PROM and Flash Memory Device The following memory devices are connected to the EBus e One PLCC PROM with 1 MByte address space e One flash memory device with 16 MByte address space The PLCC PROM is the device from which the CPU board boots by default The 16 MByte flash memory device can be used as e User flash memory of 16 MBytes e Boot flash memory of 1 MByte with the remaining 15 MBytes used as user flash memory The selection between both operation modes is made via on b
37. P IO 56 PMC Modules The I O board allows to install three PMC modules compliant to IEEE P1386 Note The used PMC modules must be compliant with the safety regulations of the country where the equipment is installed The corresponding PMC slots are PMC slots 2 3 and 4 The following figure shows which PMC connectors are assigned to each PMC slot SPARC CPU 56T 39 Installation Hardware Accessories 40 I me nn e SA 1111111111111 PMC slot 2 supports a 64 bit data bus width with a maximum frequency of 33 MHz and is attached to PCI bus B PMC slots 3 and 4 support a 64 bit data bus width with a maximum frequency of 66 MHz and are attached to PCI bus C If a 32 bit PMC module is mounted into PMC slots 3 and 4 the Sentinel64 PCI to PCI bridge dynamically detects the 32 bit bus and changes its transfer size to 32 bit for this PMC module If a 64 bit PMC module is mounted into PMC slots 3 and 4 burst transfers between all 64 bit PCI devices on PCI bus B and C will be 64 bit PCI transfers Note If a 33 MHz PMC module is mounted into PMC slots 3 and 4 the whole PCI bus C will run with 33 MHz only This may result in performance degradation The signaling level of each PMC slot is determined via a voltage key which has to be installed into one of two holes that belong to each PMC slot One hole corresponds to a signalling level of 5V the other to a signaling level of 3 3V Depending on the hole the voltage key is installed into the
38. PCI configuration cycles after reset in OpenBoot The allocation depends on the availibility of PCI devices I O board PMC module SPARC CPU 56T 111 Maps and Registers Physical Memory Map The PCI device PCIO part of the UltraSPARC Ili chip set must be available at power up for booting and has a fixed PCI address space It has an interface to the EBus where the boot PROM is located Additionally it has an interface to the MII bus from where the twisted pair Ethernet interfaces are generated Table 23 PCI Bus Address Map Address Range in PA lt 40 0 gt Size Description 1FE 0100 010016 1FE 01FF FFFF 1 24 MByte 256 Byte PCI bus configuration space 1FE 0200 000016 1FE 02FF FFFF 6 24 MByte PCI bus I O space 1FE 0300 000016 LFE FFFF FFFF 6 4 GByte 48 MByte Reserved 1FF 0000 000016 1FF FFFF FFFF 1 4 GByte PCI bus memory space 1FF F000 000016 1FF F17F FFFF 6 24 MByte PCI bus memory space for the PCIO 2 1FF F180 000015 IFF FFFEFFFFjg 256 MByte 24 MByte PCI bus memory space PCIO 2 Address Map The PCIO 2 has an address space of 24 MByte in total It is divided into e 16 MByte for the boot PROM or flash memory on the EBus CS0 e Seven address spaces for other EBus devices CS1 CS7 e g RTC NVRAM the System Configuration registers or a serial controller e The PCIO 2 System Configuration registers The detailed memory map is given in the following table Memory areas which are not covered in the table
39. PU 56T 49 Installation Board Installation 4 Remove interface cables if applicable 5 Unfasten screws 6 Remove board Powering Up We recommend to use a terminal when powering up the CPU board The advantage of using a terminal is that you do not need any frame buffer monitor or keyboard for initial power up Note Before powering up check the Requirements section for installation prerequisites and requirements e Ifan unformatted floppy disk resides in a floppy drive connected to the CPU board during power up the CPU board does not boot and the OpenBoot prompt does not appear e Check the consistency of the switch settings Switch Settings table Power Up Procedure 1 Connect a terminal to front panel serial I O interface A marked as SER A 2 Switch on system The monitor will display information about the OpenBoot booting process 3 Enter OpenBoot commands if applicable PLCC PROM and Flash Memory Device By default the CPU board boots from the 1 MByte PLCC PROM which is not writeable and contains the OpenBoot firmware Alternatively a 16 MByte flash memory device can be enabled with SW1 2 to store user applications and to boot from it 50 SPARC CPU 56T Board Installation Installation Installing Solaris The CPU board is designed to run with Solaris 8 2 02 or higher with the 64 bit kernel and with Solaris 9 Pay attention to the guidelines in this section before and during Solaris ins
40. Parameters 0 e eee eet 97 Table 18 Diagnostic ROUTINES 2 ei ak oe eS AA Ail Ee ee OO e Mel e Os e 2 98 Table 19 Commands to Display System Information 00 cece eee 102 Maps and Registers Table 20 UltraSPARC Ili Main Address Map 000 cece cence eens 110 Table 21 Main Memory Address Map 0 eee e cee ene 110 Table 22 UltraSPARC Ili Internal CSR Space 00 eens 111 Table 23 PGI Bus Address Map susi Ne ke 112 Table 24 PGIO 2 Address Map sy nz an A a A i eee N AS 112 Table 25 CPU Board System Configuration Register Address Map 000ce eee eee eee 114 Table 26 Miscellaneous Control Register 0 0 00 ccc cece eee eens 116 Table 27 LED Control Register 1 cece nennen en 117 Table 28 LED Control Register 2 ccc cece nennen nenn 118 SPARC CPU 56T 11 Table 29 Table 30 Table 31 Table 32 Table 33 Table 34 Table 35 Table 36 Table 37 Table 38 Table 39 Table 40 Table 41 Table 42 Table 43 Table 44 Table 45 Table 46 Table 47 Table 48 Table 49 LED Control Register 44 cei ptr ra Pt ae a A a 119 LED Control Register 4 o oooccccccccccccccc nennen nennen nn 120 External Failure Register 20 0 0 cece nennen nennen nennen 120 Watchdog Timer Control Register 0 cece eee teens 122 Watchdog Timer Trigger Register 0 cece eects 122 Watchdog Timer Status Register oooococcccccccccccrn ee
41. ROM ESD SPARC CPU 56T Description Possibly dangerous situation slight injuries to people or damage to objects possible Dangerous situation injuries to people or severe damage to objects possible Start of a procedure End of a procedure Description Ball Grid Array Board Information Block Base Board Management Controller Column Address Select Control Status Register Direct Memory Access Dynamic Random Access Memory Error Correction Code Electrically Erasable Programmable Read Only Memory Erasable Programmable Read Only Memory Electrostatic Sensitive Device 15 16 Abbreviation F FAE FIFO FPGA IBMU ICMB ICT IDE IEC IOBP IOM IPMB IPMI ISO JTAG LCA LDO LED LVD LVTTL MAC MCU MII NEBS NMI NVRAM O OBDIAG P PBM PCB PCI Description Field Application Engineers First In First Out Field Programmable Gate Array Intelligent Board Management Unit Intelligent Chassis Management Bus In Circuit Test Integrated Drive Electronics International Electric Code Input Output Back Panel I O Memory Management Unit Intelligent Platform Management Bus Intelligent Platform Management Interface International Organization for Standardization Joint Test Access Group Load Controller Assembly Local Data Output Light Emitting Diode Low Voltage Differential Low Voltage Transistor Transistor Logic Media Access Control Layer Memory Control Unit Media Independent Interface
42. Reserved Access r Default Access r WwW 12 r w 000002 r w SPARC CPU 56T System Configuration Registers Address 1FF F160 01FF Table 49 I2C 2 Register Bit 0 7 3 SPARC CPU 56T Name PC DATAIN2 PC CLK2 PC DATAOUT2 Maps and Registers Description Default This register bit reflects the current status of the PC 2 data line 0 PC 2 dataline is 0 1 PC 2 dataline is 1 This bit corresponds to the PC clock line and must be set by software to toggle the IC clock 0 PC 2 clock is 0 1 PC 2 clock is 1 This bit is used by software to write to the PC 1 dataline 0 The PC 2 dataline is driven low 1 The PC 2 dataline is driven high by an external pull up Reserved 000002 Access r r w r w 135 136 A Troubleshooting SPARC CPU 56T Error List Troubleshooting A typical VMEbus system is highly sophisticated This chapter can be taken as an error list for detecting erroneous system configurations and strange behaviors It cannot replace a serious and sophisticated presales and postsales support during application development If it is not possible to fix a problem with the help of this chapter contact your local sales representative or Field Application Engineer FAE for further support Problem Board does not work Board does not work LED1 is OFF and LED3 shines weak red Board does not start LED1 blinks green and LED3 is OFF VME transf
43. SPARC CPU 56T Reference Guide P N 224548 Revision AA November 2004 Copyright The information in this publication is subject to change without notice Force Computers GmbH reserves the right to make changes without notice to this or any of its products to improve reliability performance or design Force Computers GmbH shall not be liable for technical or editorial errors or omissions contained herein nor for indirect special incidental or consequential damages resulting from the furnishing performance or use of this material This information is provided as is and Force Computers GmbH expressly disclaims any and all warranties express implied statutory or otherwise including without limitation any express statutory or implied warranty of merchantability fitness for a particular purpose or non infringement This publication contains information protected by copyright This publication shall not be reproduced transmitted or stored in a retrieval system nor its contents used for any purpose without the prior written consent of Force Computers GmbH Force Computers GmbH assumes no responsibility for the use of any circuitry other than circuitry that is part of a product of Force Computers GmbH Force Computers GmbH does not convey to the purchaser of the product described herein any license under the patent rights of Force Computers GmbH nor the rights of others CopyrightO 2004 by Force Computers GmbH All righ
44. U 56T 27 Introduction Features Features The SPARC CPU56 is a high performance VME single board computer based on the 650 Mhz UltraSPARC Ili processor It provides 512 MByte on board SDRAM memory Important features are e Two Wide Ultra3 SCSI interfaces via front panel and one via I O board s IOBP e Two 10 100 1000 BaseT Ethernet interfaces via front panel e One 10 100 BaseT interface via front panel or CPU board s IOBP e Two serial RS 232 interfaces via front panel e Two RS 232 RS 454 interfaces via CPU board s IOBP e Three USB interfaces via CPU board s IOBP e Optional on board hard disk e Keyboard Mouse interface via front panel or CPU board s IOBP e Floppy disk and parallel interface via CPU board s IOBP e Three PMC slots on I O board e Solaris 8 9 and VxWorks support 28 SPARC CPU 56T Features Introduction CPU Board Two SCSI Two Ethernet Kbd Mouse Two Serial interfaces Interfaces Interface Interfaces Up to two On board UltraSPARC Ili GByte ee Processor SDRAM Figure 1 Function Blocks SPARC CPU 56T 29 Introduction Standard Compliances Standard Compliances The CPU board was designed to comply with the standards listed below Table 1 Standard Compliances Standard Description TEC 68 2 1 2 3 13 14 Climatic environmental requirements TEC 68 2 6 27 32 Mechanical environmental requirements EN 609 50 UL 1950 predefined Force system Legal safety requirements UL 94V 0 1 EN 55022 EMC requi
45. aay Ai A A Aa 101 SPARC CPU 56T 13 Using this Guide This Reference Guide is intended for users qualified in electronics or electrical engineering Users must have a working understanding of Peripheral Component Interconnect PCD VMEbus and telecommunications Conventions Notation 57 0000000016 or 0x00000000 00002 or 0b0000 x n 0 75 Bold Courier Courier Bold Italics File gt Exit lt text gt text Note Description All numbers are decimal numbers except when used with the notations described below Typical notation for hexadecimal numbers digits 0 through F e g used for addresses and offsets Same for binary numbers digits are 0 and 1 Generic use of a letter Generic use of numbers Decimal number Used to emphasize a word Used for on screen output Used to characterize user input For references table and figure descriptions Notation for selecting a submenu Notation for variables and keys Notation for buttons and optional parameters Repeated item example A1 A2 A3 A12 Omission of information from example command that is not necessary at the time being Ranges e g 0 4 means one of the integers 0 1 2 3 and 4 used in register description tables Logical OR No danger encountered Pay attention to important information SPARC CPU 56T Notation Abbreviations Abbreviation B BGA BIB BMC C CAS CSR DMA DRAM E ECC EEPROM EP
46. al device or module read the respective documentation Make sure that the board is connected to the VME backplane via all assembled connectors and that power is available on all power pins Power Up If an unformatted floppy disk resides in a floppy drive connected to the VME board during power up the VME board does not boot and the OpenBoot prompt does not appear Therefore never boot the VME board with an unformatted floppy disk residing in a floppy drive connected to the VME board Operation While operating the board ensure that the environmental and power requirements are met To ensure that the operating conditions are met forced air cooling is required within the chassis environment High humdity and condensation on the surface cause short circuits Only operate the board above 0 C Make sure the board is completely dry and there is no moisture on any surface before applying power Replacement Expansion Only replace or expand components or system parts with those recommended by Force Computers Otherwise you are fully responsible for the impact on EMC or any possible malfunction of the product SPARC CPU 56T 21 Check the total power consumption of all components installed see the technical specification of the respective components Ensure that any individual output current of any source stays within its acceptable limits see the technical specification of the respective source RJ 45 Connector The RJ 45 con
47. al disks using the Forth Monitor enter ok boot disk or ok boot disk 2 To retrieve a list of all device alias definitions enter at the Forth Monitor command prompt devalias The following table lists device aliases available for SCSI devices Table 14 OpenBoot Aliases for SCSI Devices Alias SCSI Device SCSI Interface disk Disk SCSI target ID 0 1 diskf Disk SCSI target ID f 1 diske Disk SCSI target ID e 1 diskd Disk SCSI target ID d 1 SPARC CPU 56T 91 OpenBoot Firmware Alias diskc diskb diska disk9 disk8 disk7 disk6 disk5 disk4 disk3 disk2 disk1 disk0 tape or tape0 tapel cdrom scsi 2 disk 2 disk2f disk2e disk2d disk2c disk2b disk2a disk29 disk28 disk27 disk26 disk25 92 SCSI Device Disk SCSI target ID c Disk SCSI target ID b Disk SCSI target ID a Disk SCSI target ID 9 Disk SCSI target ID 8 Disk SCSI target ID 7 Disk SCSI target ID 6 Disk SCSI target ID 5 Disk SCSI target ID 4 Disk SCSI target ID 3 Disk SCSI target ID 2 Disk SCSI target ID 1 Disk SCSI target ID 0 First tape drive SCSI target ID 4 Second tape drive SCSI target ID 5 CD ROM partition f SCSI target ID 6 SCSI2 Default disk SCSI target ID 0 Disk SCSI target ID f Disk SCSI target ID e Disk SCSI target ID d Disk SCSI target ID c Disk SCSI target ID b Disk SCSI target ID a Disk SCSI target ID 9 Disk SCSI target ID 8 Disk SCSI target ID 7 Disk SCSI target ID 6 Disk SCSI target ID 5 SCSI
48. ales gee SA Seeds inde Se 51 Solaris DriVer Package treat reis rt dde tad tia eats 52 ERGO nn re 53 ERCYMeN ii AA A ee Ad A E e a E a 53 A AN 54 ERA o o o a eee A A ab 54 ERGplatnod Avice ee ee Pe a ed Cas Pee DE Pa Pu tes 55 Controls Indicators and Connectors Front Panel Zune bee eta 57 LEDS adas aaa as re a eam ame eres 58 A a o da 59 GonNetlers uta da te dine eed 59 neela IMa Ses th des 2 dba eat CAND la aaa an eds ad La tado o e dla po Y aaa DSO Un Me LG a roo de OC dd rd 60 Keyboard Mouse vr ee o Abla ae 60 Ethernet 222m A A A A di a cia 61 S GSU O E EES E 61 On Board Connectors an ernennen 63 PMC Pr tp is a a da 63 Memory Module eite rA o ia A MELISSA 64 DES e e ele e 65 NAME a rte ant nie eli ros vine o a A ee 66 GPU Board iia a A EN a Aa Een 66 VO Board a tie eee eek e la a a A 68 SPARC CPU 56T 4 Devices Features and Data Paths BIOCK Diagramm ir a na 73 UltraSPARC IF Processor an da as ee 75 Interrupt Controller sita cda sa ei 76 PELBUSA ns a a A 77 Ethernet Controller esias p a Se ae Rl ee Se ia ba 77 SOSIGoOntroller ssh ove Per di it ii io dado 77 SENTINEL64 PCI to PCI Bridge 0oooocccoccccorcr een nennen nennen nennen 77 PCI to VMEBridge n ideea i nennen E aea a i a a a a n nn 77 POLBUS Bio adi a A A a a a cade rad 79 Ethernet Controller cio ai 8 an a a a a a ele 79 So thbridge A dl 79 PGIO 2 Controller riea a a a ta Oe ee ee 79 EBus Interface muii na tn ln 79 Media Independent Interfac
49. an be avoided by installing the Solaris Driver Package FRCcpu56pm SPARC CPU 56T 51 Installation Board Installation For audio I O and IDE ATA 100 support you have to install Solaris patches The following table provides details Table 8 Solaris Patches Supported Device Solaris Version Patch Audio 1 O if applicable 8 109896 17 or newer 9 Currently not supported A patch will be available in the near future IDE ATA 100 8 108974 31 or newer 9 112954 03 or newer Solaris Driver Package 52 Force Computers provides a Solaris driver package which supports the following devices and features of the CPU board Universe II PCI to VMEbus bridge On board flash memory Temperature sensors LEDs and watchdog Intel 82540EM GBit Ethernet device CPU 56 platform mode friver for IDE device error handling If you wish to use one of these devices you need to install the Force Computers Solaris Driver Package Version 2 20 For a detailled description of how to install and use it refer to the Solaris Driver Package Rel 2 20 Installation and Reference Guide which can be downloaded from the Force Computers S M A R T server The following table shows which driver has to be installed for a particular device Table 9 Devices and Their Appropriate Drivers Device Driver Name Intel 8254xEM GBit Ethernet controller FRCgei Universe II PCI to VMEbus bridge FRCvme On board flash memory FRCflash Temperature sensors LEDs and watchdog FRCct
50. are reserved for the EBus Table 24 PCIO 2 Address Map Address Range in PA lt 40 0 gt Size EBus CS Description 1FF F000 000015 1FF FOOF FFFF 16 1 MByte 0 PLCC PROM on the EBus if SW1 1 is OFF and if bit 0 of the Miscellaneous Control register is set to 0 1FF F010 000016 1FEFOFE FFFFig 15 MByte 0 Reserved for the EBus if SW1 1 is OFF and if bit 0 of the Miscellaneous Control register is set to 0 1FF F000 000016 1FF FOOF FFFF 6 1 MByte 0 Boot section of flash memory on the EBus if SW1 1 is ON or if bit 0 of the Miscellaneous Control register is set to 1 112 SPARC CPU 56T Physical Memory Map Address Range in PA lt 40 0 gt 1FF F010 000016 1FF F100 600016 1FF F110 000016 1FF F130 010016 1FF F130 020016 1FF F130 030016 1FF F130 040016 1FE F160 010016 1FE F170 000016 SPARC CPU 56T 1FF FOFF FFFF 6 1FF F100 7FFF16 1FF F11F FFFF16 1FE F130 010816 1FE F130 020816 1FE F130 030816 1FE F130 040816 1FF F160 01FF 16 1FF F17E FFFF1 Size 15 MByte 8 KByte 1 MByte 8 Byte 8 Byte 8 Byte 8 Byte 256 Byte 1 MByte EBus CS 0 Maps and Registers Description User flash memory on the EBus if SW1 1 is ON or if bit 0 of the Miscellaneous Control register is set to 1 RTC NVRAM on the EBus PLCC PROM mirror area independent of SW2 1 and bit 0 of the Miscellaneous Control register Serial controller on the EBus Serial interface A
51. be ide all 2 222 2 cee eee beeen 98 PrODE SCSI xs tata ds da 98 probe scsi all o oo o ooooooo ooo 98 PS 2 splitter adapter cable 60 R Resetting the board o o o o 59 S SCSI termination oooooooo 77 Secondary PCI bus ooo oooo ooo 79 Set nV ech ee EE ee eer he E ee 95 SNOW deVS 1 ee ee ens 102 T Temperature sensor 02 eee 82 testadll ana Hoek ead Ran 95 V VELSIONS 6 eee eee alaia 95 WwW watch clock 0 00 cee eee ee eee 98 SPARC CPU 56T 143 Watch net seoa bho ed ern 98 144 SPARC CPU 56T Product Error Report Present Date Affected Product Affected Documentation O Hardware O Software O Systems O Hardware O Software O Systems Error Description This Area to Be Completed by Force Computers Date PR Responsible Dept O Marketing O Production O Eng Board O Eng Systems Send this report to the nearest Force Computers headquarter listed on the address page SPARC CPU 56T 145
52. bieten gew hrleisten Das Board arbeitet im Hochfrequenzbereich und erzeugt St rstrahlung Bei unsachgem em Einbau und anderem als in diesem Handbuch beschriebenen Betrieb k nnen St rungen im Hochfrequenzbereich auftreten Warnung Dies ist eine Einrichtung der Klasse A Diese Einrichtung kann im Wohnbereich Funkst rungen verursachen In diesem Fall kann vom Betreiber verlangt werden angemessene Ma nahmen durchzuf hren Wenn Sie das Board ohne PMC Modul verwenden schirmen Sie freie Steckpl tze mit einer Blende ab um einen ausreichenden EMV Schutz zu gew hrleisten Wenn Sie Boards in Systeme einbauen schirmen Sie freie Steckpl tze mit einer Blende ab Schaltereinstellungen Das ndern der mit reserved gekennzeichneten Schalter kann zu St rungen im Betrieb des Boards f hren Andern Sie die Schaltereinstellungen der mit reserved SPARC CPU 56T 23 gekennzeichneten Schalter nicht da diese Schalter mit produktionsrelevanten Funktionen belegt sein k nnen die im normalen Betrieb St rungen ausl sen k nnten Das ndern der Schaltereinstellungen w hrend des laufendes Betriebs kann das Board besch digen Pr fen und ndern Sie die Schaltereinstellungen bevor Sie das Board installieren Installation Elektrostatische Entladung und unsachgem er Ein und Ausbau des Boards kann Schaltkreise besch digen oder ihre Lebensdauer verk rzen Beachten Sie deshalb die folgenden Punkte e Ber hren Sie das Board
53. ction set and supports up to 4 GByte of memory Important features are 650 MHz frequency Four way superscalar processor 64 bit data paths 64 bit address arithmetic 41 bit virtual addressing 16 KByte instruction cache 16 KByte non blocking primary data cache 512 KByte second level cache Sensors for observing CPU on die temperature SPARC CPU 56T 75 Devices Features and Data Paths Interrupt Controller Interrupt Controller 76 The UltraSPARC Ili provides a 6 bit wide interrupt vector for 63 interrupt sources The UPA interrupt concentrator UIC provides the inputs for all necessary interrupts It monitors all interrupts using a round robin scheme with 33 MHz converts them to a device own vector and transmits this vector to the processor The PCI interrupts engine PIE reflects every vector in one state bit From the state bit a new vector is generated and transmitted to the processor s execution unit If more than one interrupt state bit is active the transmitting sequence of the new interrupt vector is priority controlled Every interrupt routed to the interrupt controller can be enabled or disabled separately in the interrupt source and in the processor SPARC CPU 56T PCI Bus A Devices Features and Data Paths PCI Bus A PCI bus A is the primary PCI bus It runs at 33 MHz and is 32 bit wide The following devices are connected to it e Ethernet controller e SCSI controller e SENTINEL64 PCI to PCI bridge
54. d 4 Status Register 0 ccc nent eens 131 Board Configuration Status Register 1 0 0 cece nennen ernennen 132 Board Configuration Status Register 2 1 0 0 0 6 cece er 133 Hardware Revision Register 0 cece eee nett nett nets 133 12G Registers a dades 134 SPARC CPU 56T 107 Maps and Registers Interrupt Map Interrupt Map The following table lists all interrupt sources their vectors from the UIC to the PIE their vectors from the PIE to the processor s execution unit and the respective priority Interrupt Source RIC Vector CPU Internal Offset Priority Vector VME ACFAIL SYSFAIL rising 1716 7C816 0816 6 edge Audio 2416 7E316 2316 8 Ethernet interface 2 1616 7D816 1816 6 Ethernet interface 4 1516 7C216 0216 5 Floppy interface 2916 7E716 2716 8 IDE interface 1 1F 46 7E416 2416 7 IDE interface 2 1F 16 7E416 2416 7 Parallel interface 2216 7E216 2216 2 Ethernet interface 1 3 2116 7E116 2116 3 USB interface OF 16 7CA 16 0416 7 PMC1 A 3916 7CD16 0D16 4 PMC1B 0316 7D216 1216 3 PMCIC 0C16 7D516 1516 4 PMC1 D 0B16 7D616 1616 3 PMC2 A 1D46 7C616 0616 5 PMC2 B 1C16 7DD 16 1D16 4 PMC2 C 0C16 7D516 1516 4 PMC2 D 0B16 7D616 1616 3 PMC3 A 2816 7E616 2616 7 PMC3 B 1B16 7DE 46 1E 6 3 PMC3 C 2A16 7E816 2816 2 PMC3 D 1A16 7CF 16 OF 16 1 PMC4 A 0E16 7D416 1416 6 PMC4 B 3816 7C916 0916 5 PMC4 C 1916 7DF 16 1F 16 1 108 SPARC CPU 56T Interrupt Map Maps and Registers Interrupt Source RIC Vecto
55. dest address map vaddr show memory map information for the virtual address x addr display the 64 bit number from location addr 1 addr display the 32 bit number from location addr w addr display the 16 bit number from location addr c addr display the 8 bit number from location addr x addr n place on the stack the 64 bit data at location addr SPARC CPU 56T Activating OpenBoot Help 1 addr n we addr n c addr n x n addr 1 n addr w n addr c n addr ok SPARC CPU 56T place place place store store store store on the stack the on the stack the on the stack the the 64 bit value the 32 bit value the 16 bit value OpenBoot Firmware 32 bit data at location addr 16 bit data at location addr 8 bit data at location addr n at location addr n at location addr n at location addr the 8 bit value n at location addr 105 106 Maps and Registers InterrupE Map 2 22 20 ln ang 108 Physical Memory Map occcoccccc nun nennen nennen anna nn nn nn 110 UltraSPARC Ili Physical Address Memory Map 0ccoccccccccccc een 110 Memory Address Map ce ressisssrrisrsi nii nennen een een een 110 UltraSPARC Ili Internal CSR Space ooocccccccccr ernennen nenn nennen 111 PCI Bu s Address Ma 4 4 4322 bee AG eee ar ea Be ee 111 PGIO 2 Address Mapr ii le ten eg deinen 112 System Configuration Registers 0 ce eee eee eee nn nun nn 114 Overview o
56. dule connectors P8 and P9 PMC2_1033 PMC2 1034 PMC2_1035 PMC2_1036 PMC2_1037 PMC2_1038 PMC2_1039 PMC2_1040 PMC2_1041 PMC2 1042 PMC2_1043 PMC2_1044 PMC2_1045 PMC2_1046 PMC2_1047 n c n c n c nic n c n c n c n c n c hc n c n c n c n c n c n c n c SPARC CPU 56T On Board Connectors Controls Indicators and Connectors Figure 15 Location of Memory Module Connectors IDE The CPU board provides one IDE connector which provides access to IDE1 EE IDE Connector Its pinout is given below SPARC CPU 56T 65 Controls Indicators and Connectors IDE1_RST IDE1_D7 IDE1_D6 IDE1_D5 IDE1_D4 IDE1_D3 IDE1_D2 IDE1_D1 IDE1_Do GND IDE1_DREQ IDE1_lOW IDE1_lOR IDE1_IORDY IDE1_DACK IDE1 INT IDE1_A1 IDE1_AO IDE1_CSo IDE1_ACT 5V GND Figure 16 IDE Connector Pinout GND IDE1_D8 IDE1_D9 IDE1_D10 IDE1_D11 IDE1_D12 IDE1_D13 IDE1_D14 IDE1_D15 KEY GND GND GND IDE1_CSEL GND n c IDE1_CBLID IDE1_A2 IDE1_CS1 GND 5V fc On Board Connectors Both the CPU board and the I O board provide the VME connectors P1 and P2 P2 P1 carries standard VME signals and is therefore not further described in this guide P1 Figure 17 Location of VME Connectors CPU Board 66 SPARC CPU 56T On Board Connectors Controls Indicators and Connectors P2 carries the following Force Computers specific signals 10 100Mbit Ethernet 3 ETH3 e ID
57. dware Revision Register The Hardware Revision register is used to identify current PCB and FPGA revision SPARC CPU 56T Maps and Registers Default Access 02 r 02 r 02 r Default Access 1 r 00000007 r 133 Maps and Registers Address 1FF F160 01EF Table 47 Hardware Revision Register Bit 7 0 Name HW REVISION I2C Registers The PC registers implemented in the FPGA are used to access the local PC bus for the SPD BIBs and temperature sensors Address 1FF F160 01FE Table 48 I2C 1 Register Bit 0 7 3 134 Name I2C DATAINI 12C CLK1 12C DATAOUTI System Configuration Registers Description Status of the Board 0016 PCB revision 1 0 and FPGA revision 046 0116 PCB revision 1 0 and FPGA revision 116 0216 PCB revision 1 0 and FPGA revision 276 1016 PCB revision 1 1 and FPGA revision 1046 1116 PCB revision 1 1 and FPGA revision 1146 1216 PCB revision 1 2 and FPGA revision 1216 1316 FE16 Reserved FF16 No valid hardware revision Description This register bit reflects the current status of the PC 1 data line 0 PC 1 dataline is 0 1 PC 1 dataline is 1 This bit corresponds to the IC clock line and must be set by software to toggle the I2C clock 0 PC 1 clock is 0 1 PC 1 clock is 1 This bit is used by software to write to the PC dataline 0 The PC 1 dataline is driven low 1 The PC 1 dataline is driven high by an external pull up
58. e 22 22e2s seen een een nennen een nenn 80 USBilntert ces na ds a aa a o nz a e are AR len O 80 EBUS ia eh A A eae Se ee A A 81 EPGA Tots tU OA e ad at da de e e Sek A a e A Me AS EEEN 81 Watchdog sae veers wwe ee A ee dad eee aa 81 TimMer Beeps a o ld o age ss 82 Temperature Sensor Control 0 0 cece e ened 82 EoCal IAC MSH AG 6 vie a a A aia cease Gees bated ir 82 Ethernet Interface 1 3 Switching 0 c cece eee 83 LED and Switch Gontrol 2 sec ence ss tr ad deeetaae ed 83 Reset Control s 24 0 22 2 05d aad etnies in Sd ee a Goenka 83 PLCC PROM and Flash Memory Device 0 0000 cee cece nett eens 84 Real Time Clock and NVRAM 0 0c ccc cece ne ee ee nee ent ent n eee een eens 84 senal Control a ee a Ne yee ee cyte ease naan ado 84 PG BUS Coda 86 5 OpenBoot Firmware SPARC CPU 56T 7 GORE Workflow 237 2 2a ta ad aa tan 89 CORE GommandS iii AA Mew Ve ea en re er nd ae 90 POST A a Gina Rae ee ee ee Gate 90 OPENBO0t A cd LO 90 Optional Boot Parameters iis A A IS Leaded e en 91 Boot Devices scroll aaa pid ae Daa seele 91 OBDIAG Han er Naar eed eee ae Se ee Ll ee 94 Executing OBDIAG u Mena ar ana ie aed a 94 Terminating OBDIAG 22 na a A uc A Re nee 95 OBDIAG CommandS s 22 3 aan ana A ee 95 VXWOFkS SUPPO iii a a ea Fr 96 NVRAM Boot Parameters oococooccoccoc eee eee eee 97 Diagnostics stes cnn erin cue Redan e iaa ea 98 SCSIBUS do ra do Musca ol che 98 A
59. e 1 If battery is covered by I O board remove I O board first Caution PCB and battery holder damage Removing the battery with a screw driver may damage the PCB or the battery holder To prevent this damage do not use a screw driver to remove the battery from its holder 2 Exchange battery 3 When installing new battery ensure that battery connectors fit sockets on CPU board 140 SPARC CPU 56T Battery Exchange Battery Exchange 4 Install battery in such a way that the dot marked on top of battery covers dot marked on chip 5 If necessary reinstall I O board SPARC CPU 56T 141 Index A Aborting the board o oo ooooo o o 59 B banner u a a a una rn 101 Board register OVervieW 114 Boot parameters 2 2 2 2220er 97 C CPU features o ooooooooooo om ooo 75 D devalias u a da Bene a e 102 E O 95 H Hard disk ws pr aoe Re ee Ge as 45 Ha RO tee Pee cen O 95 l Interrupt concept 2222er 76 Interrupt sources 2 22 2202 een 108 Interrupt vectors o oo oooooooo ooo 108 IOBPS ui er ee ds 38 142 SPARC CPU 56T bE DEVICES 10 ls 82 L LED stall ir iia 58 M Memory modules o ooo 44 O OBDIAG ra E tals eee A GA 94 OpenBoot Device aliases 91 P PMC modules 0 00 cece eee nenn 39 Primary PCI bus 2200005 77 PriNteNnVS o vos eee ee eee 95 probe ide 2 eee eee ees 98 pro
60. e die bei Einbau Betrieb und Wartung des Boards zu beachten sind Wir sind darauf bedacht alle notwendigen Informationen die f r die Installation und den Betrieb erforderlich sind in diesem Handbuch bereit zu stellen Da es sich jedoch bei dem Board um ein komplexes Produkt mit vielf ltigen Einsatzm glichkeiten handelt k nnen wir die Vollst ndigkeit der im Handbuch enthaltenen Informationen nicht garantieren Falls Sie weitere Informationen ben tigen sollten wenden Sie sich bitte an die f r Sie zust ndige Gesch ftsstelle von Force Computers Das Board erf llt die f r die Industrie geforderten Sicherheitsvorschriften und darf ausschliesslich f r Anwendungen in der Telekommunikationsindustrie und im Zusammenhang mit Industriesteuerungen verwendet werden Einbau Wartung und Betrieb d rfen nur von durch Force Computers ausgebildetem oder im Bereich Elektronik oder Elektrotechnik qualifiziertem Personal durchgef hrt werden Die in diesem Handbuch enthaltenen Informationen dienen ausschliesslich dazu das Wissen von Fachpersonal zu erg nzen k nnen es aber in keinem Fall ersetzen EMV Das Board wurde in einem Force Computers Standardsystem getestet Es erf llt die f r digitale Ger te der Klasse A g ltigen Grenzwerte in einem solchen System gem den FCC Richtlinien Abschnitt 15 bzw EN 55022 Klasse A Diese Grenzwerte sollen einen angemessenen Schutz vor St rstrahlung beim Betrieb des Boards in Gewerbe sowie Industriege
61. e accessory has to be added to that of the board For information on the accessories power requirements refer to the documentation delivered together with the respective accessory or consult your local Force Computers representative for further details The power supply has to meet the requirements given in the tables below Table 6 Power Requirements Requirement 5V 12V Minimum Voltage 4 88V 11 64V Typical Voltage 5V 12V Maximum Voltage 5 25V 12 6V Typical Current 6A 1 5A Maximum Current 7A 1 63A Typical Power Requirement 30W 18W Maximum Power Requirement 35W 20W Note The CPU board only powers up ifthe 5V and 12V supply voltages are stable and within their limits This complies to the VMEbus specification However there are systems which are not fully VMEbus compliant The power supplies of these systems do not turn on the 12V supply ifthe 5V supply has not been loaded before Use a VMEbus board which loads the 5V in these systems to avoid a power up deadlock situation SPARC CPU 56T 37 Installation Hardware Accessories Hardware Accessories The following upgrades and accessories are available e IOBPs for CPU and I O Board e PMC modules e Memory modules e Hard Disk e SCSI U160 cable e RS 422 serial cable e PS2 splitter cable IOBPs for CPU and I O Board 38 As separate price list items two IOBPs are available for the SPARC CPU 56T One is called SPARC IOBP IO 56 and is connected to the I O board It is avai
62. e following main features e Watchdog e Timer e Temperature sensor control e Two local PC interfaces Ethernet interface 1 3 switching e LED and switch control e Reset control Watchdog The CPU board s watchdog is implemented inside the FPGA It is used to reset the board after a configured time if no software trigger occurred If enabled in the Interrupt Enable Control register an interrupt will be generated before the watchdog timer runs out The watchdog can be enabled by setting SW1 3 to ON It starts with the first trigger of the watchdog trigger bit in the Watchdog Trigger register After the watchdog was started it is not possible to stop it anymore The Watchdog Timer Control Register allows to specify the time after which an interrupt is generated and after which a reset is issued For both values between 125 ms up to 1 hour in 15 steps are possible The value of each following step is increased by a factor of between 1 5 and 3 To be compatible to the predecessor board SPARC CPU 54 the time after which a reset is issued after a reset is set to 2 5 s and the time after which an SPARC CPU 56T 81 Devices Features and Data Paths EBus Timer interrupt is generated is set to 1 25s Once the watchdog timer is running it is only possible to reduce the watchdog run out time The FPGA contains two timers which can be used as two independent 16 bit count down timers with a timer interval of 10 us and a maximum run o
63. e row variant of I O board s IOBP 31 Introduction 32 Order No 120456 111332 120454 109045 107257 Accessory SPARC IOBP IO 56 3 ACC CABLE SCSI U160 ACC CABLE RS422 SPARC MEM 550 1024 ACC CABLE KBDMSE 540 Ordering Information Description Three row variant of I O board s IOBP SCSI 3 to SCSI 4 adapter cable RS232 to RS422 serial adapter cable Memory module with 1 GByte memory Splitter cable for PS2 SUN keyboard mouse SPARC CPU 56T Installation Action Plan usa ae la 35 Requirements out u re a AAA 36 Environmental Requirements 22222 e2n nennen nennen een nn 36 Power REQUIFEMENIS ssi irera een a eier 37 Hardware Accessories casi ies cece a an a a aa ne nn 38 IOBPs for CPU and I O Board een een nennen nn 38 PMG Modules 2 2 rss a Se Ie A RN a eE IRRE E 39 installati n Procura 25 2 22 BS AS Ba Br DEE nE een 41 Memory Modules Fu ee ea re a Be ein 44 A AS 45 SCS U TOO Cale a a a a O ae 45 RS 422 Cable descartar a u Dina ale Ben ee vecees 45 PS 2 Splitter Gable 22 4 een lei Blasien 45 Switch Settings ren A A cee eE 46 Board Installation vies u 0000 0000 0 a nn nn a a an 48 Backplane Configuration oooooooccooccnr nennen nennen een nennen nennen ren 48 Installing the GRU BoArdi oi en a Ri ne 49 Removing the CPU Board cocida aaa a a as 49 Powering Up ca A atrial get en A ee endear aerate 50 PLCC PROM and Flash Memory Device 0
64. ead the switch settings of switches 1 and 2 Address 1FF F160 01E0 Table 43 Switch 1 and 2 StatusRegister Bit Name Switch Setting Functionality Default 0 sw1 1 Flash memory write protection 12 0 ON Flash memory writing enabled 1 OFF Flash memory writing disabled 1 SW1 2 Boot device selection 12 0 ON Boot from Flash memory 1 OFF Boot from PLCC PROM 2 SW1 3 Watchdog enabling 12 0 ON Watchdog enabled 1 OFF Watchdog disabled 130 Access r SPARC CPU 56T System Configuration Registers Maps and Registers Bit Name Switch Setting Functionality Default Access 3 SW1 4 Reset Abort key enabling 12 r 0 ON Reset Abort key disabled 1 OFF Reset Abort key enabled 4 SW2 1 User defined Switch 12 r 0 ON 1 OFF 5 SW2 2 User defined Switch 1 r 0 ON 1 OFF 6 SW2 3 User defined switch 1 r 0 ON 1 OFF 7 SW2 4 User defined switch 12 r 0 ON 1 OFF Switch 3 and 4 Status Register This register is used to read the switch settings of switch SW3 and SW4 Address 1FF F160 01E1 Table 44 Switch 3 and 4 Status Register Bit Name Switch Setting Functionality Default Access 0 SW3 1 Enable termination for SCSI 1 1 r 0 ON Termination disabled 1 OFF Termination enabled 1 SW3 2 Enable termination for SCSI 2 1 r 0 ON Termination disabled 1 OFF Termination enabled 2 SW3 3 Enable termination for SCSI 3 avaliable on I O 1 r board 0 ON Termination disabled 1 OFF Termination e
65. ed signalling level sv o 3 3V Note The signaling levels of PMC slots 3 and 4 must be equal Otherwise they are automatically set to 3 3V 42 SPARC CPU 56T Hardware Accessories Installation 4 Fix voltage key to I O board by fastening screw Voltage Key Screw LL Caution PMC Module Damage If the power consumption of the PMC module exceeds 7 5W the board and the PMC module are damaged Make sure that the total power consumption at 12V 5V and 3 3V level does not exceed 7 5W 2 Make sure standoffs of PMC module cover mounting holes of I O board 3 Place screws delivered with PMC into mounting holes SPARC CPU 56T 43 Installation Hardware Accessories 4 Fasten screws Reinstalling I O Board 1 Plug I O board onto PMC connectors of CPU board 2 Fix it by fastening the 14 screws which you previously have removed Memory Modules The main memory capacity is adjustable via installation of a Force Computers memory module Currently the SPARC MEM 550 is available for the CPU 56T It provides 1 GByte memory Before installing the memory module you have to remove the I O board and afterwards you have to reinstall it How this is done is described in the previous section PMC Modules The memory module has to be installed into the connectors P8 and P9 44 SPARC CPU 56T Hardware Accessories Installation The actual memory module installation procedure is described in the SPARC MEM 550 I
66. efault Access 11 r 1 r 1 r Default Access 00 r 00 r 02 r SPARC CPU 56T System Configuration Registers Bit Name 5 PMC3 4 VIO 6 FKBD MSE PRE SENT 7 RKBD MSE PRE SENT Description This bit is set to 1 if the PMC modules 3 and 4 are configured with a VI O of 5V if applicable 0 PMC3 4 have a VI O of 3 3V 1 PMC3 4 have a VI O of 5V This bit shows which type of keyboard mouse is plugged into the front connector 0 No SUN style keyboard mouse or a PS 2 style keyboard mouse is plugged into the front connector 1 A SUN style keyboard mouse is plugged into the front connector This bit shows which type of keyboard mouse is plugged into the rear connector 0 No SUN style keyboard mouse or a PS 2 style keyboard mouse is plugged into the rear connector 1 A SUN style keyboard mouse is plugged into the rear connector Board Configuration Status Register 2 This register gives information about additional board conditions Address 1FF F160 01E3 Table 46 Board Configuration Status Register 2 Bit Name 0 PMC_EREADY 7 1 Description This bit shows the initialization status of a non monarch processor PMC module PMC_EREADY is a wired OR signal of all PMC modules 0 At least one of the PMC modules has not completed its initialization cycle 1 All PMC modules have completed their initialization and are able to respond to configuration cycles from the host processor Reserved Har
67. environment The board generates and uses radio frequency energy and if not installed properly and used in accordance with this Installation Guide may cause harmful interference to radio communications Operating the system in a residential area is likely to cause harmful interference in which case the user will be required to correct the interference at his own expense To ensure proper EMC shielding always operate the board with the blind panel or with PMC module installed If boards are integrated into open systems always cover empty slots Switch Settings 20 Switches marked as reserved might carry production related functions and can cause the board to malfunction if their setting is changed Therefore only change settings of switches not marked as reserved SPARC CPU 56T Setting resetting the switches during operation causes board damage Therefore check and change switch settings before you install the board Installation Electrostatic discharge and incorrect board installation and removal can damage circuits or shorten their life Therefore Touching the board or electronic components in a non ESD protected environment causes component and board damage Before touching boards or electronic components make sure that you are working in an ESD safe environment When plugging the board in or removing it do not press or pull on the front panel but use the handles Before installing or removing an addition
68. er 2 the LED can be programmed to be red green or OFF Furthermore it can be programmed to be blinking green or blinking red with different blinking frequencies By default the LED is OFF Ethernet Activity Depending on LED control register 2 settings the LED indicates activity of Ethernet interfaces 1 to 4 or a combination of these SPARC CPU 56T Front Panel Controls Indicators and Connectors LED Description 3 VME Bus Activity default Red Universe II asserted VME SYSFAIL signal to the VMEbus Green Universe II accesses the VMEbus as master OFF No SYSFAIL signal asserted and no Universe PCI to VME bridge activity Ethernet Activity Depending on LED control register 3 settings the LED indicates activity of Ethernet interfaces 1 to 4 or a combination of these User LED Mode Via LED control register 3 the LED can be programmed to be OFF green or red 4 User LED Mode default Via LED control register 4 the LED can be programmed to be red green or OFF Furthermore it can be programmed to be blinking green or blinking red with different blinking frequencies By default the LED is OFF Ethernet Activity Depending on LED control register 4 settings the LED indicates activity of Ethernet interfaces 1 to 4 or a combination of these Key The front panel of the CPU board provides one key RE R SoM 1003 2004 en This key has two functions When pressed longer than 0 5 s a reset is generated which is indicated by the LED 1
69. ers have failures SPARC CPU 56T Possible Reason The 5V backplane voltage is too low The 12V backplane voltage is missing or too low No OpenBoot code was found There are no or more than one board in the VME system configured as slot 1 VME connectors defect VMEbus timeout too short Solution Check that all backplane voltages are within their specific ranges Check that power supply is capable to drive the respective loads Check that all backplane voltages are within their specific ranges Check that the power supply is capable to drive the respective loads Insert a valid PLCC OpenBoot PROM and set switch 1 2 to OFF If you are sure to have a valid OpenBoot code in the flash memory set the switch 1 2 to ON Check all boards for their slot 1 configuration Only one board must be configured as slot 1 Set switch SW4 1 of the board to OFF for an automatic slot 1 detection Check VME Pl and P2 connectors for bent or broken pins Adjust bend pins if possible or replace board Increase the timeout of the Bus Timer The VMEbus handles abnormal bus cycles by asserting the BERR signal The timeout should be longer than the longest expected bus cycle 137 Troubleshooting 138 Problem Board does not boot Possible Reason Wrong boot device SCSI bus not terminated Error List Solution Check the OpenBoot property boot device This property must be set to the device disk
70. erved VME Slot 1 Detection SW4 1 OFF default Automatic VMEbus slot 1 detection enabled SW4 1 ON and SW4 2 OFF VME slot 1 function enabled SW4 1 ON and SW4 2 ON VME slot 1 function disabled External VMEbus SYSRESET function OFF default VMEbus SYSRESET generates on board RESET ON VMEbus SYSRESET does not generate on board RESET VMEbus SYSRESET generation OFF default On board reset is driven to VMEbus SYSRESET ON On board reset is not driven to VMEbus SYSRESET 47 Installation Board Installation Board Installation Caution Board Damage Installing the board into a powered system may damage this and other boards in the system Only install the board into a non powered system Backplane Configuration If the CPU board is plugged into slot 1 and configured accordingly with switch SW4 refer to Switch Settings table the board acts as IACK daisy chain driver Plugged in any other slot the board closes the IACKIN IACKOUT path If one board is missing in this daisy chain an active backplane will be able to automatically transfer the signals to the next board in the chain If the board is not plugged into an active backplane jumpers on the backplane will transmit the signals The jumpers have to be set manually Configuration Procedure 1 Remove jumpers connecting BG3IN and BG3OUT signals from empty slot on backplane where the CPU board is to be plugged into backplane 2 Assemble jumpers for BG3IN and BG3
71. f System Configuration Registers 22 2eesnneenen nennen een nn 114 Miscellaneous Control Register 0 0 nennen nenn 115 User LED Control Registers vio a a m RA RR 117 LED Control Register 1 a ata dt ia 117 LED ControlsRegister 2 cil anne ll A 118 LED Control Register 3 Aare eee eae aed 118 LED Control Register 4 0 cc ccc anne nennen nn 119 External Failure Status Register 0 cece ec tenet eee nee 120 Watchdog TimerRegisters 2 20 eas a 2 22 nn RES nn la Ge oes Lad 121 Watchdog Timer Control Register 0 0 0 cece ect etna 121 Watchdog Timer Trigger Register o oocooooccoocccoorc eens 122 Watchdog Timer Status Register 00 c cece eee 123 TimerRegisters aiii AA eee grees 123 Timer Control Register rassaa i e a a aea ene nennen nen 123 Timer Clear Control Register 0 ccc nennen nn nennen nen 124 Timer Status Register monaco reese er entida t tato ire 124 Timer Initial Control Registers ooooocccccccccco teen eens 125 Timer Counter Status Register 0 o 126 Interrupt Register usa a ia EDER A ee 127 SPARC CPU 56T Interrupt Enable Control Register 00 00 nett eens 127 Interrupt Pending Status Register 0 0 eee eee eee 128 Reset Register e Kr Nae AAR Se ME ee one Rel aloud ds 129 Board Status Registers a an ns ee ae ge Ba A i A Rn 130 Switch 1 and 2 Status Register 0 0 e eee nern nenn 130 Switch 3 an
72. h can be activated by entering the command help Entering help creates the following screen output ok help Enter help command name or help category name for more help Use ONLY the first word of a category description Examples help select or help line Main categories are Numeric output Radix number base conversions Arithmetic Memory access Line editor System and boot configuration parameters Select I O devices Floppy eject Power on reset Diag diagnostic routines Resume execution File download and boot Nvramrc making new commands permanent ok A list of all available help categories is displayed These categories may also contain subcategories To get help for special Forth words or subcategories enter help lt name gt The online help shows you the Forth word the parameter stack before and after execution of the Forth word before after and a short description The online help of the Forth monitor is located in the boot PROM This means that an online help is not available for all Forth words Typical examples for how to get help for special Forth words or subcategories are given below ok help power reset all reset machine simulates power cycling power off Power Off ok ok help memory dump addr length display memory at addr for length bytes fill addr length byte fill memory starting at addr with byte move src dest length copy length bytes from src to
73. he ACC CABLE RS 422 cable connected to this interface If the OpenBoot variable tty rs422 enable is set to false pin 9 holds the signal SERB_RI and the serial interface B is a standard RS 232 interface Keyboard Mouse 60 A SUN type keyboard mouse can be connected via an 8 pin Mini DIN connector Its pinout is given below GND 3 GND 5V DC 5 Mouse In Keyboard Out 6 8 Keyboard In Mouse Out Sense 5V DC Figure 7 SUN Type Keyboard Mouse Connector Pinout Noo ORAN If you use an PS 2 splitter adapter cable two PS 2 interfaces are available One PS 2 interface can be used for connecting a keyboard the second for connecting a mouse Their respective pinouts are given below 1 2 Keyboard Data 3 eX 4 nc 2 GND 5 En 6 Vcc Keyboard Clock n c Figure 8 PS 2 Keyboard Connector Pinout SPARC CPU 56T Front Panel Controls Indicators and Connectors 1 2 Mouse Data ER 4 nc 2 GND 5 EN 6 Vcc Mouse Clock 0 n c 6 Figure 9 PS 2 Mouse Connector Pinout Ethernet Ethernet 1 and 2 are available via two RJ 45 connectors Ethernet 1 is of type 10 100BaseT and Ethernet 2 of type 10 100 1000BaseT The respective pinouts are given below ETH1_TX ETH1_TX ETH1_RX al 1 NC Me ETH1_RX 8 Figure 10 Ethernet 1 Connector Pinout ETH2_MDIO ETH2_MDIO ETH2_MDI1 4 ETH2_MDI2 ETH2_MDI2 ETH2 MDI1 118 ETH2_MDI3 ETH2_MDI3 Figure 11 Ethernet 2 Connector Pinout
74. heir firmware includes a self test routine The table below lists several diagnostic routines Table 18 Diagnostic Routines Command Description probe scsi Identifies devices connected to the on board SCSI controller probe scsi all lt device path gt Performs probe SCSI on all SCSI controllers installed in the system below the specified device tree node If lt device path gt is omitted the root node is used test lt device specifier gt Executes the specified device s self test method lt device specifier gt may be a device path name or a device alias Example test net test network connection test all lt device specifier gt Tests all devices that have a built in self test method and that reside below the specified device tree node If lt device specifier gt is omitted the root node is used watch clock Monitors the clock function watch net Monitors network connection via primary Ethernet probe ide Identifies devices connected to IDE bus probe ide all lt device path gt Performs probe ide on all IDE buses installed in the system below the specified device tree If lt device path gt is omitted the root node is used SCSI Bus To check the on board SCSI 1 or SCSI 2 for connected devices enter Ok probe scsi Primary UltraSCSI bus Target 1 Unit 0 Disk WDIGTL WDE9100 ULTRA2 1 21 Secondary UltraSCSI bus ok All SCSI Buses To check all SCSI buses installed in the system enter the following
75. is driver Corrected typical and maximum power consumption values for 5V SPARC CPU 56T For further information refer to Company ALI Corporation Force Computers IEEE Standards Department Intel LSI Logic Maxim STMicroelectroni cs National Semiconductor PCI Special Interest Group PICMGPCI Special Interest Group SUN Tundra VITA Xilinx SPARC CPU 56T www ali com tw forcecomputers com ieee com intel com Isilogic com maxim ic com st com national com pcisig com picmg org pcisig com sun com tundra com vita com xilinx com Other Sources of Information Document ALI M1535D Southbridge documentation SPARC IOBP CPU 56 Installation Guide SPARC IOBP IO 56 Installation Guide SPARC MEM 550 Installation Guide ACC CABLE SCSI U160 Installation Guide ACC CABLE RS422 Installation Guide IEEE P1386 Standard Mechanics for a Common Mezzanine Card Family CMC Intel 82540 Ethernet controller specifications Intel LXT971 PHY device specifications 53C1010 SCSI controller specifications MAX1617 temperature sensor specifications M48T35AV RTC NVRAM specifications PC87307 PC97307 Plug and Play Compatible Super I O Preliminary Specification March 1998 PCI Local Bus Specification Rev2 1 PCI Local Bus Specification Rev2 2 UltraSPARCIli Processor specifications SUN SME2300 PCIO 2 controller documentation Universe II documentation VME64 Standard ANSI VITA 1 19
76. lable in two variants which differ in the number of VME connector rows the three row variant SPARC IOBP IO 56 3 and the five row variant SPARC IOBP IO 56 5 Both IOBPs provide the following interfaces e SCSI on SPARC IOBP IO 56 3 only single ended SCSI e Audio e PMC user I O For details about this IOBP and its installation refer to the SPARC IOBP IO 56 Installation Guide The second IOBP is called SPARC IOBP CPU 56 and is connected to the CPU board It is available in two variants which also differ in the number of VMEconnector rows the three row variant SPARC IOBP CPU 56 3 and the five row variant SPARC IOBP CPU 56 5 The interfaces available via both IOBP variants are e IDE e 10 100Base TX e Parallel e Two USB e Two serial RS 232 and RS 422 SPARC CPU 56T Hardware Accessories Installation Note On the IOBP CPU 56 3 the RS 232 signals are limited to RXD TXD RTS and CTS On the IOBP CPU 56 5 the additional signals DTR DSR DCD and RI are available In addition to these interfaces the five row variant IOBP CPU 56 5 provides e Keyboard mouse interface SUN or PS 2 style e Third USB interface e Floppy interface e 10 100 1000 Base TX Ethernet For details about this IOBP and its installation refer to the SPARC IOBP CPU 56 Installation Guide Caution Board Damage Using the board together with IOBPs for which it is not designed may destroy the board Only use the board together with the IOBP CPU 56 or IOB
77. ll SCSI BUSES iio as a daa vd 98 Single DEVICE irian aa a ia e i a a rege ie een 99 Group of DevViCeS ar ine nr ber 99 e a ae Te E E ee LEERE cea EN 99 NStWOTK metiniai nuras ner a ei lt era 100 IDE DEVICES sucia a a ta ee heed en ee reden Ben 100 Displaying System Information 0000 cece eee nennen nn nenn 101 Ethernet Address and Host ID occoccccccccc nennen nennen nennen nenn 101 ID PROM aa ii ea es a een 101 Resetting the System us nn ieee wreak eci eter eee 103 Activating OpenBoot Help oooooooconcccnc ence eee eee 104 Maps and Registers INTGrFUDU Maps da i Bie vats einer ei eee aes 108 Physical Memory Map ican ar a a 110 UltraSPARC Ili Physical Address Memory Map 00 cece eect ee ttn eee eee 110 Mem ry Address Map 4 43228282 Aaa eA Aken YO ARG bo Aga Agee Aga oes ane 110 SPARC CPU 56T UltraSPARC Ili Internal CSR Space ooocccccccccnc nennen ernennen nn 111 PEI Bus Address Maps ios 2028 42 a ae a ne aie en nnd 111 PGIO 2 Address Mapi reii a Ti gaa ee ae ee Dee een 112 System Configuration Registers 0 ce cece eee eee eee nennen 114 Overview of System Configuration Registers 0c cette eens 114 Miscellaneous Control Register 00 c cece eens 115 User LED Control Registers 0 0 eee een nenn 117 LED Control Register 1 eera e a a aln aE nent nennen 117 FED Gontrol Registen2 N eset Sak Be a a e nr 118 LED Control Register 3 scou
78. low and a reference to this table can be found in the description column UltraSPARC Ili Physical Address Memory Map The main address map gives an overview of the whole address space of the UltraSPARC Ili CPU This address range is used for the main memory and the PCI bus Each defined address space is divided into subspaces which are described in the next sections Table 20 UltraSPARC Ili Main Address Map Physical Address Range PA lt 40 0 gt Size Description Access 000 0000 000016 001 FFFF FFFFj6 8 GByte Main memory Cacheable 002 0000 00001 amp 007 FFFE FFFFj amp Reserved Cacheable 008 0000 000016 1FB FFFF FFFF 6 Reserved Noncacheable 1FC 0000 000015 1FD FFFE FFFF 6 8 GByte Reserved do not use Noncacheable 1FE 0000 00001 IFF FFFEFFFFjg 8 GByte PCI bus processor Noncacheable subsystem memory clock control and ECU Memory Address Map The main memory address range is divided between on board memory and the MEM 550 memory modules Two banks of 256 MByte and four banks of 256 MByte result in a total amount of up to 2 GB main memory Table 21 Main Memory Address Map Physical Address Range PA lt 41 0 gt Size Bank Memory Location DIMM Type 000 0000 000016 000 0FFF FFFF 16 256 MByte 0 On board memory DIMM 0 000 8000 000016 000 8FFF FFFF 16 256 MByte 2 DIMM 1 110 SPARC CPU 56T Physical Memory Map Physical Address Range PA lt 41 0 gt 001 0000 000015 001 0FFF FFFF16 001 1000 000015 001 1FFF FFFF1
79. n CORE Commands POST In order to change or interrupt the boot process in CORE the following commands can be executed e Skip POST lt Control gt lt P gt e Enter user interface lt Control gt lt U gt e User default NVRAM variables for this run lt Control gt lt N gt e Turn on messages if lt diag switch gt is set to true lt Control gt lt M gt At hardware power on or button power on the CORE firmware executes POST if the NVRAM configuration parameter lt diag switch gt was set to true beforehand The extents of certain tests executed within in the POST depend on the state of the configuration parameter lt diag level gt You choose between minimal or maximal testing by setting this configuration parameter to min or max If the NVRAM configuration parameter lt diag switch gt is true for each test a message is displayed on a terminal connected to the serial I O interface A If the system does not work correctly error messages will be displayed which indicate the problem After POST the OpenBoot firmware boots an operating system or enters the Forth monitor if the NVRAM configuration parameter lt auto boot gt is false OpenBoot 90 Booting the system is the most important function of the OpenBoot firmware Booting is the process of loading and executing a stand alone program such as the operating system After the system is powered on it usually boots automatically after it has passed POST which occ
80. n een en 133 I2G Register ani ee Bere rege dab 134 AppendixA Troubleshooting AppendixB Battery Exchange Index SPARC CPU 56T 9 Product Error Report 10 SPARC CPU 56T Tables Introduction Table 1 Standard Compliances vs ieiiiis diorr iid ani CEN a n p nennen nennen 30 Table 2 Product Nomenclature ee r a A A a E Oe E nennen rennen nenn 31 Table 3 Board Ordering Information 0 0 00 c cece een nennen nn nennen 31 Table 4 Board Accessories Ordering Information 0 0 0 cece eee ee eee 31 Installation Table 5 Environmental Requirements 0 0 cece eee een een 36 Table 6 Power Requirements viii ae a Se Ga ee tae dee ee 37 Table 7 Switch Settings vicio aan RAR gees 46 Table 8 Solaris P tches a o i ay Be ee 52 Table 9 Devices and Their Appropriate Drivers 0 cece een een ren 52 Table 10 Flash Segmentation and Write Protection 0 cece cece cee nee tne tenes 54 Controls Indicators and Connectors Table 11 Description of Front Panel LEDS 0 eee eens 58 Devices Features and Data Paths Table 12 Reset SOUPCES ara ria e ee dilo 83 OpenBoot Firmware Table 13 Boot Parametros naar Bel a dei 91 Table 14 OpenBoot Aliases for SCSI Devices 0 0 ccc cc cee tne tenet nes 91 Table 15 OpenBoot Aliases for Miscellaneous Devices 0 0c ccc cece teen etn 93 Table 16 OBDIAG Commands aiii Cada ye aa Cada ee adits daa ae ger alee 95 Table 17 OpenBoot Configuration
81. nabled 3 SW3 4 Reserved 1 r 0 ON 1 OFF SPARC CPU 56T 131 Maps and Registers Bit 5 4 Name SW4 2 and SW4 1 SW4 3 SW4 4 System Configuration Registers Switch Setting Functionality VME Slot 1 Detection 002 SW4 2 ON and SW4 1 ON VME slot 1 function 102 SW4 2 OFF and SW4 1 ON VME slot 1 function 01 SW4 1 OFF Automatic VMEbus slot 1 detection enabled External VMEbus SYSRESET function 0 ON VMEbus SYSRESET does not generate board reset 1 OFF VMEbus SYSRESET generates board reset VMEbus SYSRESET generation 0 ON board reset is not driven to VMEbus SYSRESET 1 OFF board reset is driven to VMEbus SYSRESET Board Configuration Status Register 1 This register reflects the hardware configuration of the CPU board Address 1FF F160 01E2 132 Table 45 Board Configuration Status Register 1 Bit 1 0 3 2 Name IO PRESENT IOBP PRESENT PMC1 2 VIO Description These bits show whether an I O board is plugged on the CPU board if applicable 0 No I O board present 1 I O board present 2 Reserved 3 Reserved These bits are showing which type of the IOBP CPU is plugged at the rear side of the CPU board 0 No IOBP CPU present 1 IOBP CPU 3 present 2 IOBP CPU 5 present 3 Reserved This bit is set to 1 if the PMC modules 1 and 2 are configured with a VI O of 5V if applicable 0 PMC1 2 have a VI O of 3 3V 1 PMC1 2 have a VI O of 5V D
82. nderruns without 0 r clearance have occurred It is a status for a missed timer underrun and can only occur if timer 1 is enabled and the initial value is greater than 0 0 No more than one timer underruns of timer 1 have occurred 1 More than one timer underruns of timer 1 have occurred 2 3 Reserved 00 r 4 STAT TIM2 Indicates an underrun of timer 2 This can only occur if 0 r timer 2 is enabled the initial value is greater than 0 and if the 16 bit mode is enabled 0 No underrun of timer 2 has occurred 1 An underrun of timer 2 has occurred 5 ERR TIM2 Indicates that more than one timer underruns without 02 r clearance have occurred It is a status for a missed timer underrun and can only occur if timer 2 is enabled the initial value is greater than 0 and if the 16 bit mode is enabled 0 No more than one timer underruns of timer 2 have occurred 1 More than one time underrun of timer 2 has occurred 6 7 Reserved Reserved 002 r Timer Initial Control Registers The following four registers are used to set up the run out time of both timers The 32 bits are distributed as big endian which means the first register 1FF F160 0148 represents the bits 31 24 and so on SPARC CPU 56T 125 Maps and Registers System Configuration Registers Address 1FF F160 0148 1FF F160 014B Table 38 Timer Initial Control Registers Bit Name Description Default Access 15 0 TIMER2 INIT Initialization time of timer 2 in 16
83. nector on the front panel must only be used for twisted pair Ethernet TPE connections Connecting a telephone to such a connector may destroy your telephone as well as your board Therefore e Clearly mark TPE connectors near your working area as network connectors e Only connect TPE bushing of the system to safety extra low voltage SELV circuits Make sure that the length of the electric cable connected to a TPE bushing does not exceed 100 meter If you have further questions ask your system administrator Battery If a lithium battery on the board has to be exchanged see Appendix Battery Exchange observe the following safety notes e Wrong battery exchange may result in a hazardous explosion and board damage Therefore always use the same type of lithium battery as is installed and make sure the battery is installed as described e Exchanging the battery after seven years of actual battery use have elapsed results in data loss Therefore exchange the battery before seven years of actual battery use have elapsed e Exchanging the battery always results in data loss of the devices which use the battery as power backup Therefore back up affected data before exchanging the battery Environment Always dispose of used batteries and or old boards according to your country s legislation if possible in an environmentally acceptable way 22 SPARC CPU 56T Sicherheitshinweise Dieser Abschnitt enth lt Sicherheitshinweis
84. nectors keys and LEDs available on the front panel of the CPU board pmo O oo A gt TE Im UWA NIAmMm Figure 4 CPU Board s Front Panel SPARC CPU 56T 57 Controls Indicators and Connectors Front Panel LEDs 58 All four LEDs available at the front panel are multi purpose LEDs Depending on the values contained in the LED control registers 1 to 4 they indicate either the board status or different network activities Furthermore all LEDs can be operated in user LED mode For details about the LED control registers refer to chapter Maps and Registers Table 11 Description of Front Panel LEDs LED 1 Description Board Status default Red Board reset Weak red on pressing the RST key Board abort Weak red during operation 12V power supply on VME backplane not within its limits Green Board running Blinking red weak red No PCI activity within last two seconds Blinking green No boot code found Blinking weak red 5V power supply on VME backplane not within its limit IDE Activity Depending on LED control register 1 settings the LED indicates the activity of IDE 1 or IDE 2 Ethernet Activity Depending on LED control register 1 settings the LED indicates activity of Ethernet interfaces 1 to 4 or a combination of these User LED Mode Via LED control register 1 the LED can be programmed to be OFF green or red User LED Mode default Via LED control regist
85. nen 60 Figure 7 SUN Type Keyboard Mouse Connector Pinout 0c cece eee es 60 Figure 8 PS 2 Keyboard Connector Pinout ooococccccccccor eens 60 Figure 9 PS 2 Mouse Connector Pinout 0 00 teens 61 Figure 10 Ethernet 1 Connector Pinout 00 0 nenne nennen 61 Figure 11 Ethernet 2 Connector Pinout 0 0 c cece tenes 61 Figure 12 SCSI 1 2 Connector Pinouts 0 0 teens 62 Figure 13 Location of PMC Connectors 00 ccc nennen 63 Figure 14 PMC I O Connector Pn24 Pinout 0 0 0 cee tenes 64 Figure 15 Location of Memory Module Connectors 0 cc cece eects 65 Figure 16 IDE Connector Pinout an San weeds a erence OLA ae GN Ge a a 66 Figure 17 Location of VME Connectors 0 0 c nennen nenne nennen nn nn 66 Figure 18 CPU Board P2 VMEbus Connector Pinout Rows Z B 1 ee 67 Figure 19 CPU Board P2 VMEbus Connector Pinout Rows C D 0c eee ee 68 Figure 20 1 O Board P2 VMEbus Connector Pinout Rows Z B 1 cece eee eee 69 Figure 21 I O Board P2 VMEbus Connector Pinout Rows C D 0 eee 70 Devices Features and Data Paths Figure 22 CPU Board Block Diagram sereisas egani cece ete eens 73 Figure 23 I O Board Block Diagram 0 0 cece tenet eee 74 OpenBoot Firmware Figure 24 OpenBoot CORE Overview 00 cece tenet eee eens 88 Figure 25 48 bit 6 byte Ethernet Address 0 0 0 cece tenes 101 Figure 26 32 bit 4 byte HOost lD 20000
86. ning as both master and slave in the e Sustained transfer rates up to 60 70 Mbytes s Note When operating the board in system slot 1 the system clock is disabled while the board is in reset This is a limitation of the Universe II device SPARC CPU 56T PCI Bus B Devices Features and Data Paths PCI Bus B PCI bus B runs at 33 MHz and is 64 bit wide It is the secondary PCI bus of the CPU board and has the following devices attached to it Ethernet controller Southbridge PCIO 2 controller PMC module Ethernet Controller The Ethernet controller used at PCI bus B is the same as is used at PCI bus A Southbridge The used Southbridge is an ALI M1535D It provides the following interfaces Two IDE channels with ATA 100 Parallel interface Floppy disk interface PS 2 keyboard mouse interface SUN keyboard mouse interface via two serial interfaces PCIO 2 Controller The used PCIO 2 controller is a SUN SME2300 It is a single chip I O subsystem using a single PCI load and providing the following interfaces Expansion bus EBus interface Four USB interfaces Media Independent Interface MII EBus Interface The PCIO 2 controller acts as EBus controller of the attached EBus A description of all devices attached to the EBus is given below SPARC CPU 56T 79 Devices Features and Data Paths PCI Bus B Media Independent Interface Two on board Intel LXT971 PHY devices are connected to the MII They transform
87. ns 123 Timer Control Register 2 00 cece cee ene nennen 124 Timer Clear Control Register 0 0 cece ene eens 124 Timer Status Register 0 cece ccc nenn nennen nennen nenn 125 Timer Initial Control Registers 0 nennen 126 Timer Counter Status Register 0 teens 127 Interrupt Enable Control Register 222222222 seeneneee nennen nennen nenn 128 Interrupt Pending Status Register 0 0 cece nennen nennen nn 128 Reset Status Register 02 cece nent eee eens 129 Switch 1 and 2 StatusRegister 0 0 ccc teen eee 130 Switch 3 and 4 Status Register 0 0 cece teen ees 131 Board Configuration Status Register 1 ccc cece eee eens 132 Board Configuration Status Register 2 1 0 2 2 ccc eee ees 133 Hardware Revision Register 0 cece eee een een een nenn 134 LOT Register vii een ee OPAMP ew ad Gee AN yee OAR 134 120 2 Regist A A it 135 SPARC CPU 56T Figures Introduction Figure 1 Function Blocks e A A ed EA EA 29 Installation Figure 2 Location of PMC Voltage Keys ooocccccccccoccc een nennen nennen en 40 Figure 3 Location of Switches on Board s Top Side 0 eee eee rn 46 Controls Indicators and Connectors Figure 4 GPU Board s Front Panel ns re Br eee en 57 Figure 5 Serial A Connector Pinout 00 seen nennen nenn nenn 60 Figure 6 Serial B Connector Pinout ooocccccccccccccn nennen nen
88. nstallation Guide which is delivered together with the memory module Hard Disk A hard disk is available for the CPU board on request It can be connected to the IDE1 interface which is accessible via an on board connector Before installing the hard disk you have to remove the I O board and afterwards you have to reinstall it How this is done is described in the previous section PMC Modules The actual installation of the hard disk is described in the Installation Guide delivered together with the hard disk SCSI U160 Cable The SCSI U160 cable is available as accessory kit called ACC CABLE SCSI U160 It provides a SCSI U160 cable with a length of three meters which has one SCSI 3 and one SCSI 4 connector at its ends It can be used to connect SCSI devices to the CPU board For details refer to the ACC CABLE SCSI U160 Installation Guide which is delivered together with the accessory kit RS 422 Cable The RS 422 cable is available as accessory kit called ACC CABLE RS 422 and provides a serial cable with a length of 2 6 meters that has one male DSub9 RS 422 and one female mini DSub9 RS 232 connector at its ends It allows to connect RS 422 devices to the serial B interface of the CPU board For details refer to the ACC CABLE RS 422 Installation Guide which is delivered together with the accessory kit PS 2 Splitter Cable The PS 2 splitter cable can be connected to the SUN type keyboard mouse c
89. ntdown timer with a timer interval of 10 us and a total run out time of 42949 67295 s or 11h 55min 49 s and 672 95 ms In this mode only one interrupt is available and possible The timer counts down from its initial value to zero in intervals of 10 us The initial value can be set by software from 1 to 65535 in the 16 bit mode or to 4294967295 in the 32 bit mode which results in a timer period of 10 us to 655 35 ms in 16 bit mode or 42949 67295 s in 32 bit mode If the timer has reached zero an interrupt is generated if enabled and the timer loads his initial value to count down again The timer has eleven registers in total The first register is used to control the timer mode one register is used to clear timer overruns one register is used to read the timer overrun status four registers are used for setting the initial timer values and the last four registers are used to read the current value of the countdown timers Timer Control Register This register is used to set up the timer If the timer is set to zero the timer is off and no interrupts are generated However the Timer Status register will not be cleared The normal timer tolerance is 100 ppm During the first countdown after the timer activation however the timer tolerance is increased to 10 ps SPARC CPU 56T 123 Maps and Registers System Configuration Registers Address 1FF F160 0140 Table 35 Timer Control Register Bit 0 7 5 Timer Clear Control Register
90. o the main menu lt cr gt obdiag gt setenv diag continue 0 diag continue 0 Hit any key to return to the main menu lt cr gt obdiag gt test 2 Hit the spacebar to interrupt testing Testing pcit1f 0 ebusel SUBTEST vendor id test SUBTEST device id test SUBTEST mixmode read SUBTEST e2 class test SUBTEST status reg walkl SUBTEST line size walkl SUBTEST latency walkl SUBTEST line walkl SUBTEST pin test SUBTEST dma reg test SUBTEST dma func test Selftest at pei lf 0 eb usel es a Sere Se eee See passed Hit any key to return to the main menu lt cr gt obdiag gt exit lt cr gt ok VxWorks Support ThePLCC PROM delivered together with the CPU board contains support for the real time operating system VxWorks 5 4 from WindRiver Systems A VxWorks booter bootrom hex image is provided as dropin named bootrom In order to execute it enter at the CORE command prompt execute bootrom To automatically start the VxWorks booter at power up enter set kernel bootrom 96 SPARC CPU 56T NVRAM Boot Parameters OpenBoot Firmware NVRAM Boot Parameters The OpenBoot firmware holds its configuration parameters in NVRAM To see a list of all available configuration parameters enter at the Forth Monitor prompt printenv As you can see in the list the default setting is for the CPU board to boot the operating system automatically If this is not the case ensure that the lt auto boot gt
91. oard switches Whether to boot from the PLCC PROM or the flash memory device is determined by switch SW1 2 After booting the whole PLCC PROM is switched off regardless of the position of switch SW 1 2 Switch SW1 1 is used to enable write protection of the flash memory device If this switch is OFF default the flash memory device is write protected In order to copy the PLCC PROM content to the flash memory device switch SW1 1 must be switched ON and switch SW1 2 must be set to OFF Real Time Clock and NVRAM The CPU board provides the M48T35AV with an real time clock RTC and a non volatile RAM NVRAM which offers the following features e 32 KByte ultra low power CMOS SRAM e Byte wide accessible real time clock e Long life lithium carbon mono fluoride battery e Year 2000 compliant RTC with own crystal Serial Controller The CPU board provides four independent full duplex serial I O interfaces They are implemented via the Quad Enhanced Serial Communication Controller 16C554 by Texas Instruments 84 SPARC CPU 56T EBus Devices Features and Data Paths The device offers the following features e Four independent full duplex serial channels e Four independent baud rate generators e Hardware handshake support RTS CTS DTR DTS RI DCD e Interrupt controlled Interface 1 and 2 are available on the front panel via two micro DSub connectors The interfaces 3 and 4 are routed to the SPARC IOBP CPU 56 via the P2 connecto
92. oder elektrische Komponenten in einem nicht ESD gesch tzten Bereich kann dies zu einer Besch digung des Boards f hren Bevor Sie Boards oder elektronische Komponenten ber hren vergewissern Sie sich dass Sie in einem ESD gesch tzten Bereich arbeiten e Dr cken Sie beim Ein oder Ausbau des Boards nicht auf die Frontplatte sondern benutzen Sie die Griffe e Lesen Sie vor dem Ein oder Ausbau von zus tzlichen Ger ten oder Modulen das dazugeh rige Benutzerhandbuch e Vergewissern Sie sich dass das Board ber alle Stecker an die VME Backplane angeschlossen ist und alle Spannungskontakte mit Strom versorgt werden Booten Befindet sich w hrend des Bootens eine unformatierte Diskette in einem mit dem VME Board verbundenen Diskettenlaufwerk bootet das VME Board nicht und die OpenBoot Eingabeaufforderung erscheint nicht Booten Sie deshalb niemals das VME Board wenn sich eine unformatierte Diskette in einem mit dem VME Board verbundenen Diskettenlaufwerk befindet Betrieb 24 Achten Sie darauf dass die Umgebungs und die Leistungsanforderungen w hrend des Betriebs eingehalten werden e Um zu gew hrleisten dass die Anforderungen w hrend des Betriebs eingehalten werden ist eine Luftk hlung notwendig e Betreiben Sie das Board nur innerhalb der angegebenen Grenzwerte f r die relative Luftfeuchtigkeit und Temperatur da durch hohe Luftfeuchtigkeit Kurzschl sse SPARC CPU 56T entstehen k nnen Stellen Sie vor dem Ein
93. onnecter of the CPU board or its IOBP It allows to operate a PS 2 style keyboard and mouse SPARC CPU 56T 45 Installation Switch Settings Caution Board Damage Setting resetting the switches during operation causes board damage Therefore check and change switch settings before you install the board The CPU board provides four configuration switches SW1 SW2 SW3 and SW4 NE 46 Switch Settings Figure 3 Location of Switches on Board s Top Side Table 7 Switch Settings Switch sw1 SW2 SW3 No 1 1 4 Description Flash memory write protection OFF default Flash memory writing disabled ON Flash memory writing enabled Boot device selection OFF default Boot from PLCC PROM ON Boot from flash memory device Enable watchdog OFF default Watchdog disabled ON Watchdog enabled Enable reset abort key OFF default reset abort key enabled ON reset abort key disabled User defined switches For detailed information refer to section Switch 1 and 2 Status Register Enable Termination for SCSI 1 OFF default Termination enabled ON Termination disabled SPARC CPU 56T Switch Settings Switch SW4 SPARC CPU 56T No 1 2 Installation Description Enable termination for SCSI 2 OFF default Termination enabled ON Termination disabled Enable termination for SCSI 3 on I O board if applicable OFF default Termination enabled ON Termination disabled Res
94. ontrol esse ccc eacewiiaiie a a anna 83 PLCC PROM and Flash Memory Device oocccoccccccccc teens 84 SPARC CPU 56T 71 72 Real Time Clock and NVRAM Serial Controller PCIBusC SPARC CPU 56T Block Diagram Block Diagram Memory UIC Module Connector On board Memory UltraSPARC lli 650 MHz Ethernet Intel 82540 SCSI Symbios 5301010 SENTINEL64 PCI to PCI Bridge PCI Bus B 64 Bit 33 Mhz Devices Features and Data Paths Interrupt Controller Ethernet Intel 82540 NVRAM RTC PLCC PROM for OpenBoot Flash Memory Quad Serial Controller PCIO 2 Controller SUN SME2300 4xUSB MII EBus 0 EBus 8 bit FPGA South Bridge ALI M1535D Connectors Serial C D TL 16554 I O Board Figure 22 CPU Board Block Diagram SPARC CPU 56T 73 Devices Features and Data Paths Block Diagram SS N y M q 4 Connectors PN31 PN33 PCIBus C N 64 bit 66 MHz Sn N M N SENTINEL64 3 F Connectors PCI To PCI Bridge PN21 PN24 Ultra160 xXx SCSI 2 53C1000 IR N PCIBus B 64 bit 33 Mhz Connectors a M N 2 PMC Connectors Pn01 Pn04 CPU board Figure 23 I O Board Block Diagram 74 SPARC CPU 56T UltraSPARC lli Processor Devices Features and Data Paths UltraSPARC lli Processor The UltraSPARC Ili processor is based on the SPARC V9 architecture with VIS instru
95. ors Controls Indicators and Connectors On Board Connectors The following connectors are on board e PMC e Memory module IDE e VME PMC The I O board provides the following PMC connectors PMC Connectors Corresponding PMC Slot Pn31 Pn33 PMC 4 Pn21 Pn24 PMC 3 Pn11 Pn13 PMC 2 SI NN SA Figure 13 Location of PMC Connectors The connectors corresponding to PMC slots 2 and 4 are standard and are therefore not described in this guide The PMC connectors corresponding to PMC slot 3 provide the additional connector Pn24 SPARC CPU 56T 63 Controls Indicators and Connectors Pn24 AAA PMC 3 On Board Connectors It carries user I O signals that are routed to the I O board s IOBP There they are available via an on board PMC connector For details refer to the SPARC IOBP IO 56 Installation Guide The pinout of Pn24 is given below 1 PMC2_101 3 PMC2_102 5 PMC2_103 7 PMC2_104 9 PMC2_105 11 PMC2_106 13 PMC2_107 15 PMC2_108 17 PMC2_109 19 PMC2_1010 21 PMC2_1011 23 PMC2_1012 25 PMC2_1013 27 PMC2_1014 29 PMC2_1015 31 PMC2 1016 33 PMC2 1017 35 PMC2 1018 37 PMC2 1019 39 PMC2 1020 41 PMC2_1021 43 PMC2_1022 45 PMC2 1023 47 PMC2_1024 49 PMC2_1025 51 PMC2 1026 53 PMC2 1027 55 PMC2 1028 57 PMC2 1029 59 PMC2 1030 61 PMC2_1031 63 PMC2 1032 Figure 14 PMC I O Connector Pn24 Pinout Memory Module 64 The CPU board provides the memory mo
96. ot possible to stop the watchdog The watchdog timer can be configured to reset the board after a certain time interval which can vary between 125 ms and 1 hour After reset the time is set to 2 5 s for the reset and to 1 25 s for the interrupt which is compatible to the SPARC CPU 54 Watchdog Timer Control Register The Watchdog Timer Control register is used to set the time out for the watchdog timer Note If the watchdog is running you can only change the watchdog time to a smaller value SPARC CPU 56T 121 Maps and Registers System Configuration Registers Address 1FF F160 0130 Table 32 Watchdog Timer Control Register Bit Name Description Default Access 4 0 WDOG LENGTH These bits are used to set the time out for the 010002 r w watchdog timer The tolerance of the time delay is 100ppm or 10 ms 10 ms whichever is greater The values given below indicate Time after which reset is initiated Time after which interrupt is triggered 00000 125 ms 62 ms 00010 250 ms 125 ms 001002 500 ms 250ms 001102 1 s 500 ms 010002 2 5 s 1 25ms 010102 5s 3 s 011002 10 s 8 s 011102 30 s 25 s 100002 1 min 50 s 100102 3 min 2 min 101002 5 min 4 min 101102 10 min 8 min 110002 20 min 18 min 110102 30 min 25 min 111002 60 min 50 min 111112 Watchdog timer off 7 5 These bits are always zero Watchdog Timer Trigger Register The Watchdog Timer Trigger register is used to trigger the watchdog timer Address 1FF F
97. r SPARC CPU 56T 85 Devices Features and Data Paths PCI Bus C PCI Bus C PCI Bus C has the following devices attached to it 86 SENTINEL64 PCI To PCI bridge PMC 2 PMC slot 3 providing 64 bit 66 MHz PMC 3 PMC slot 4 providing 64 bit 66 MHz SCSI device Ultra 160 LVD supporting 64 bit 66 MHz The data width provided by PCI bus C is 64 bit The bus speed depends on the PMC modules installed into slot 3 and 4 If no PMC modules are installed or only PMC modules which support 66 MHz the bus speed is 66 MHz In all other cases the bus speed is 33 MHz SPARC CPU 56T OpenBoot Firmware Introduell n u 2 ea 88 CORE ee ae ee en ee ee se 88 GORE WorkllOW ar ne a en nal iaa weeds 89 GORE Commands a an lee en ee ee ee 90 POST 2 A A ee A ieee te EA 90 OpenB ot 3 224 ANA AA e 90 Optional Boot Parameters o occcccococcccc een nennen nennen nenn 91 BOOT DEVICES A N ee een 91 OBDIAG a ep a a N A ae SE ER O rk else 94 Executing OBDIAG cia a ara HA Da ara DER 94 Terminating OBDIAGs at sashes ee ri 95 OBDIAG Commands iii ici een a eis a ea a Aled a ew ad aaa awa we 95 VXxWOorks SUPPOr re se ee re ya ne Rd Ba ERDE SA rn AAA NNS 96 NVRAM Boot Parameters o oocooccoococ nenn nenn nennen nenne 97 Diagnostics en 98 SCSI BUS use a in a nn a a gat Rabe aioe an laa ese 98 AINESCSI BUSES zur rc ha ed AGS he kl Atle i ek kas te be ik ee Be Sh feds See ee 98 SINGIE DEVICE as ana a A A Rh A EN a Oot nas
98. r Default 0016 0016 0016 0016 0016 0016 0016 0016 0046 0046 0046 FFis FFi 0046 0046 0016 0016 0016 Maps and Registers Description Timer 1 Init Control register U Timer 1 Init Control register L Timer 2 Init Control register U Timer 2 Init Control register L Timer 1 Counter Status register U Timer 1 Counter Status register L Timer 2 Counter Status register U Timer 2 Counter Status register L Function Unit Interrupt Interrupt Enable Control register Interrupt Pending Status register Function Unit Reset Reset Status register Function Unit Board Status Switch 1 and 2 Status register Switch 3 and 4 Status register Board Configuration 1 Status register Board Configuration 2 Status register Hardware Revision Status register Function Unit I2C register I2C register 1 I2C register 2 The Miscellaneous Control register is used to switch between the PLCC Boot PROM and the flash memory and to select availability of Ethernet interface 1 SPARC CPU 56T 115 Maps and Registers Address 1FF F160 0100 System Configuration Registers Table 26 Miscellaneous Control Register Bit 3 4 5 7 116 Name TSOP EN PS 2 BACK SER2_RS422E N ETH1 3CTRL ETH1 EN Description Used to switch between PLCC PROM access and flash memory access in the address space for CSO After reset this bit is cleared 0 0 If SW1 2 is OFF the PLCC PROM is available in the CS0 address
99. r CPU Internal Offset Priority Vector PMC4 D 0916 7D716 1716 1 PS 2 keyboard 2B16 7E916 2916 4 PS 2 mouse 2C16 7EA16 2A16 4 SCSI interface 1 2016 7E016 2016 3 SCSI interface 2 1416 7D916 1946 4 SCSI interface 3 OD 16 70516 0516 5 Serial interface 1 2D16 7EB16 2B16 7 Serial interface 2 0416 7Dl1i6 1116 4 Serial interface 3 0A16 7C716 0716 2 Serial interface 4 011g 7D316 1316 1 SUN keyboard 1016 7CA16 0A16 2 SUN mouse 0716 7C016 0016 7 Temperature sensor 11 16 7DB16 1B 16 1 Timer 1 Timer 2 0616 7D016 1046 6 VME_N 0 1816 7CCi6 OC 16 6 VME_N 1 1E16 7DC16 1Ci 6 VME_N 2 0516 7Cl16 0116 5 VME_N 3 1316 7DA16 1A16 3 VME_N 4 0216 7C316 0316 2 VME_NI 5 0016 7CEx6 0Ex6 2 VME_N 6 1216 7CB16 0B16 1 VME_N 7 1716 7C816 0816 6 Watchdog timer 2516 7E516 2516 8 SPARC CPU 56T 109 Maps and Registers Physical Memory Map Physical Memory Map The UltraSPARC Ili has a 41 bit wide physical address range This address range is divided into some specified areas for e g the main memory or the PCI bus Each area is subdivided into other areas e g the main memory area is subdivided into the different memory module areas with the memory banks Some areas are subdivided further down to one register with one byte i e the System Control registers in the EBus area are byte oriented The tables on the following pages describe the areas with the related address maps If an address map is subdivided into other areas a separate table is available be
100. re Register Bit Name 1 0 0 2 TEMP_STAT 120 Description Default Access Reserved 00 r This bit reflects the state of the temperature sensor 0 r output 0 The temperature sensor did not detect a temperature outside of the specified range 1 The temperature sensor has detected a temperature outside of the specified range SPARC CPU 56T System Configuration Registers Bit Name 5 3 0 6 STAT ACFAIL 7 STAT SYSFAIL Description Reserved This bit reflects the state of the VMEbus low active ACFAIL signal i e whether a failure of the power supply occurred 0 The ACFAIL signal is inactive high 1 The ACFAIL signal is active low This bit reflects the state of the VMEbus low active SYSFAIL signal i e whether a failure of the power supply occurred 0 The SYSFAIL signal is inactive high 1 The SYSFAIL signal is active low Watchdog Timer Registers The watchdog timer is used to reset the board after a defined time interval if no software trigger occurred Before the watchdog timer runs out an interrupt will be generated if it is enabled in the Interrupt Enable Control register To enable the watchdog switch SW1 3 must be set to ON For details refer to section Switch Settings on page 46 Maps and Registers Default 0002 0 0 Access The watchdog starts with the first trigger of the watchdog trigger bit in the Watchdog Trigger register After the watchdog is enabled it is n
101. rements on system level EN 55024 FCC Part 15 Class A ANSI IPC_A 610 Rev B Class 2 Manufacturing requirements ANSI IPC R 700B ANSI J 001 003 ISO 8601 Y2K compliance 30 SPARC CPU 56T Ordering Information Ordering Information Introduction When ordering board variants hard and software upgrades use the order numbers given below Product Nomenclature In the following table you find the key for the product name extensions used for board variants Table 2 Product Nomenclature SPARC CPU 56T xxx ccc Lyyy zz XXX ccc Lyyy ZZ Order Numbers SDRAM capacity in MByte CPU speed in MHz L2 cache in KByte Flash memory size in MByte The table below is an excerpt from the board s ordering information Ask your local Force Computers representative for the current ordering information Table 3 Board Ordering Information Order No SPARC CPU 56T 111328 512 650 L512 16 Description 512 MByte SDRAM 650 MHz CPU frequency 512 KByte L2 cache and 16 MByte flash memory The table below is an excerpt from the board s accessories ordering information Ask your local Force Computers representative for the current ordering information Table 4 Board Accessories Ordering Information Order No Accessory 111330 SPARC IOBP CPU 56 3 111331 SPARC IOBP CPU 56 5 120455 SPARC IOBP IO 56 5 SPARC CPU 56T Description Three row variant of CPU board s IOBP Five row variant of CPU board s IOBP Fiv
102. rl IDE device error handling FRCplatmod SPARC CPU 56T Board Installation Installation Further information on these drivers is given in the following sections FRCgei The assignment of the driver s instance number to an Intel 8254xEM GBit Ethernet device can be viewed by booting with the OpenBoot command boot v Each device is shown with the driver name and instance number during the Solaris boot up The other way to obtain the instance number of the Ethernet devices is to look into the file etc path_to_inst In order to do so type the following grep fciprb etc path_to_inst A typical output could be pci 1f 0 ethernet 2 1 frcgei pci 1f 0 pci ethernet 1 0 frcgei The first part in quotation marks specifies the hardware node name in the device tree The number specifies the instance number and the third part also in quotation marks specifies the driver name The following table shows how the hardware node names are assigned to a label on the front panel and the IOBP CPU 56 Label Location Hardware Node ETHERNET1 3 CPU front panel or Standard Solaris eri Ethernet device IOBP CPU 56 ETHERNET2 CPU front panel pei 1 0 pci 4 ethernet 1 ETHERNET4 IOBP CPU 56 pci 1 0 ethernet 2 The following table shows how the driver instance numbers are typically assigned to Ethernet devices on the CPU board Label Location Driver Instance Number ETHERNET1 3 CPU front panel or IOBP CPU 56 eri0 ETHERNET2 CPU front panel fregeil ET
103. schalten des Stroms sicher dass sich auf dem Board kein Kondensat befindet und betreiben Sie das Board nicht unter 0 C Wenn Sie das Board in Gebieten mit starker elektromagnetischer Strahlung betreiben stellen Sie sicher dass das Board mit dem System verschraubt ist und das System durch ein Geh use abgeschirmt wird Stellen Sie sicher dass Anschl sse und Kabel des Boards w hrend des Betriebs nicht versehentlich ber hrt werden k nnen Austausch Erweiterung Verwenden Sie bei Austausch oder Erweiterung nur von Force Computers empfohlene Komponenten und Systemteile Andernfalls sind Sie f r m gliche Auswirkungen auf EMV oder Fehlfunktionen des Produktes voll verantwortlich berpr fen Sie die gesamte aufgenomme Leistung aller eingebauten Komponenten siehe die technischen Daten der entsprechenden Komponente Stellen Sie sicher dass die Stromaufnahme jedes Verbrauchers innerhalb der zul ssigen Grenzwerte liegt siehe die technischen Daten des entsprechenden Verbrauchers RJ 45 Stecker Der RJ 45 Stecker auf der Frontblende darf nur f r Twisted Pair Ethernet TPE Verbindungen verwendet werden Beachten Sie dass ein versehentliches Anschlie en einer Telefonleitung an einen solchen TPE Stecker sowohl das Telefon als auch das Board zerst ren kann Beachten Sie deshalb die folgenden Hinweise e Kennzeichnen Sie TPE Anschl sse in der N he Ihres Arbeitsplatzes deutlich als Netzwerkanschl sse e Schlie en Sie an TPE Buchsen
104. space If SW1 2 is ON the flash memory is available in the CS0 address space 1 The flash memory is available in the CS0 address space Note You can only write a 1 to this bit After doing so it can not be cleared anymore to 0 Used to switch between a rear connected and a front connected PS 2 keyboard mouse 0 Front panel PS 2 keyboard mouse is enabled 1 Rear panel PS 2 keyboard mouse is enabled Used to enable the voltage supply for the RS 422 cable connected to the serial B interface 0 Voltage supply is disabled The ring indicator of the serial B interface can be used 1 Voltage supply is enabled The ring indicator of the serial interface B cannot be used These bits are always zero These bits determine whether Ethernet interface 1 at the front panel or Ethernet interface 3 via IOBP is active The selection is made by OpenBoot or VxWorks at board start up Per default the selection is done automatically and depends on which Ethernet interface has a link If both or no interfaces have a link Ethernet interface 1 is preferred 0002 No change of current status 0x12 Ethernet interface 1 is enabled 0102 Ethernet interface 3 is enabled 1x1 Selection is made automatically with preference of interface 1 1102 Selection is made automatically with preference of interface 3 Note You can only write a 1 to each of these bits After doing so the respective bit can not be cleared anymore to
105. t 10 us 7FFF 6 Timer 1 needs 327 67 ms until next initialization FFFFj6 Timer 1 needs 655 35 ms until next initialization Current value of timer 1 in 32 bit mode 0000 000016 0000 000016 Timer 1 is not running 0000 000116 Timer 1 will initialize again during the next 10 us 0000 7FFF1 Timer 1 needs 327 67 ms until next initialization FFFF FFFFj6 Timer 1 needs 42949 67295 s until next initialization Access r r The interrupt registers are used to distribute all possible failures or status information to the UPA interrupt concentrator UIC The registers are the central areas to enable the interrupts and read back the status of a pending interrupt Interrupts are cleared in different ways The VME ACFAIL and SYSFAIL interrupts which detect the deassertion of the respective signals are cleared by writing a 1 to the respective bits in the Interrupt Pending Status Register All other interrupts are cleared by setting clearing bits in their respective control registers In order to clear the timer 1 interrupt for example the bit CLR_TIM1 in the Timer Clear Control register must be set to 1 Interrupt Enable Control Register This register is used to enable or disable the interrupt sources SPARC CPU 56T 127 Maps and Registers Address 1FF F160 0180 Table 40 Interrupt Enable Control Register Bit Name 0 IE WDT 1 Reserved 2 TE TEMP 3 Reserved 4 IE_TIMER1 5 IE_TIMER2 6 IE_ACFAIL 7 I
106. t nl A ieee Wa ideas Pau Hees CAR eer 118 LED Control Register 4 0 0 cece nent nennen 119 External Failure Status Register 0 cece cece 120 Watchdog Timer Registers ui A be dae ban Pee Taga needa 121 Watchdog Timer Control Register 0 eee eee eens 121 Watchdog Timer Trigger Register 0 cece rr 122 Watchdog Timer Status Register 0 0 ete teens 123 Timer Registers eoa aa a hte tein dees ee 123 Timer Control Register 0 cece cece nennen nenn 123 Timer Clear Control Register 0 c ccc tenet eens 124 Timer Status Register 2 N see So dated ay a DA cad ee ea 124 Timer Initial Control Registers 0 0c cc nent nn 125 Timer Counter Status Register 00 cece nee ees 126 Interrupt Registers stat A Lee dae AO RD a a RENNRS 127 Interrupt Enable Control Register 00 06 eee eens 127 Interrupt Pending Status Register 0 eee eens 128 Reset Register coercitiva Tv kad ere 129 Board Status Registers s iaeei danii iaaa a aiin aa anne nennen nen 130 Switch 1 and 2 Status Register ooooococccccoor nennen nern nennen nenn 130 Switch 3 and 4 Status Register 0 cece nennen nern nennen nenn 131 Board Configuration Status Register 1 esesnsnsnne nennen nennen een nn 132 Board Configuration Status Register 2 ueessnneenn nennen nennen nennen 133 Hardware Revision Register 2222eeee nennen een een ee
107. tallation Note Solaris versions prior to version 8 2 2 are not supported The CPU board runs with 64 bit kernel only The following devices of the CPU board are not supported by the Solaris operating system e Universe II PCI to VMEbus bridge e On board flash memory e Temperature sensors LEDs timers and watchdog e Intel 82540EM Ethernet device e IDE device error handling If you wish to use one of these devices you need to install the Force Computers Solaris Driver Package Details will be given in the following sections If you want to use PS 2 keyboard and mouse you have to customize the following software groups during the Solaris installation e Developer system support e End user system support e Core system support The customization consists of selecting PS 2 keyboard and mouse device drivers Root 64 Bit under drivers for SME support 64 Bit The remaining software groups do not require customization Note During installation make sure that the 64 bit support is enabled If Solaris is already installed and you want to have PS 2 support afterwards you have to install the SUNWkmp2x for 64 bit package Note During the Solaris installation you may get the following Solaris error message Could not reset the IDE core of SouthBridge If this happens try to install Solaris from another CD ROM drive or from a SCSI CDROM drive After the Solaris installation has finished this Solaris error message c
108. tents Using this Guide Other Sources of Information Safety Notes Sicherheitshinweise 1 Introduction Features 1 A A Gals cle OS ets aoe es as eee A 28 Standard Compliance lt c00 o osocococccnicras arca ese han 30 Ordering Information wiii rd dan 31 Pr duet NOomentl f re a A en A OBS oh 31 Order NuMberstvas ars ana AN aaa da aan 31 2 Installation Acton Pla u AS AI 35 Requirements A ees ins tetas 36 Environmental Requirements 2 ec c a en Weed bed gee eb ween gece abe bes 36 Power Requirements ias 37 Hardware Accessories 0 cece eee eee eee eens 38 IOBPs for CPU and I O Board cc nennen nennen 38 PMG MOdUuleS 000 Ge bad A CAG See Gade ee utes Bead Ge aa Riedl 39 Installation Procedur 000 A en an le a ea ene 41 Memory Modules ss see aa Ae A ee 44 Hard Disk ts da see ee Gr a 45 SCSI U160 Cable ivonne A PAA Chea eee Eee ales 45 SPARC CPU 56T 5 RS2422 Cable 4 4 4284 1 enaena EA hr a a a ARA adi 45 PS 2 Splitter Cable 2 2 22 ws ae AA AA Rene eat dae de 45 Switch Settings as ma a a aan 46 Board Installation za as alerts 48 Backplane Configuration 0 c cnet nennen 48 Installing the GRU Board ar ans a aay eee Mara eier 49 Removing the CPU Board a a a teen nent eens 49 Powering UD zn Ba Deni ead made Mardis een peas Woe A Mee eee Aaa pane er 50 PLCC PROM and Flash Memory Device 0000 cece eect eee teed 50 Installing Solaris 3a A Mes bee
109. the MII into a 10 100BaseT Ethernet interface which is available either via front panel or via IOBP Important features of the PHY device are e Support for ISO IEC 8802 3 Ethernet e Support for Shielded Twisted Pair STP and Unshielded Twisted Pair UTP category 5 cables of up to 100 meters length e Operation in half duplex and full duplex mode possible e Speed adjustion either manually or via auto negotiation USB Interfaces 80 Four USB channels are provided with each channel supporting 1 5 MBit s and 12 MBit s All USB interfaces provide auto resume from power managed suspended state The USB interfaces 1 2 and 3 are routed to the CPU board s IOBP where they are available via three front connectors USB interface 4 is unused The USB interfaces provide the host controllers for USB transfers and a four port integrated hub The host controller manages the control and data flow It also provides connection management and provides status information The hub enables tiered star topology to provide multiple connections SPARC CPU 56T EBus Devices Features and Data Paths EBus The EBus is a generic slave 8 bit wide Direct Memory Access DMA bus pseudo ISA bus to which the following devices are connected e Field Programmable Gate Array FPGA e PLCC PROM and flash memory device Real time clock and NVRAM e Quad serial controller FPGA The used FPGA is a Spartan XCS20XL device made by XILINX It provides th
110. the following features e Sets all user LEDs e Accesses the temperature sensor devices To enable the temperature sensors set the OpenBoot environment variable env monitor before booting To do so enter at the prompt setenv env monitor enabled SPARC CPU 56T Board Installation Installation e Enables and triggers watchdog functions To enable the watchdog set switch SW1 3 to ON Increases the volume of a headphone if applicable FRCplatmod This driver ensures proper error handling for IDE devices It should be installed immediately after the Solaris installation has been completed If this driver is not installed the system may send error messages or can panic in case of IDE error handling SPARC CPU 56T 55 56 Controls Indicators and Connectors Front Panel iscsi 2 daria a weed 57 A ae Deren oh Re le eka wae sie yond Kerne 58 KV ee En N ne 59 GONNECIOS een nee da E AAA AA See ee as rer 59 Seal OT ae ne een A wae EA AA E gar aaa eed 60 Keyboard Mouse ria na ra Renee 60 ENE ee a de ee ft io ados 61 SON ENE A aed aaa 61 On Board Connectors u nu en en aan 63 PMG PEPA A 63 Memory M dulo a rar Hr A eee ee a a 64 IDE ica a A a a a daria 65 MM E a eco ld Gasca tule hs 66 A A wate a warned eis Wan kn Snead Sead ee ea ne 66 V O Board ia na Ea Aaa E E TE aa SER TESTER TELSHER HAFEN 68 SPARC CPU 56T Front Panel Controls Indicators and Connectors Front Panel The following figure shows the con
111. the last reset has been generated by the 02 r front panel reset key 0 Front panel reset key has not been pressed 1 Front panel reset key has been pressed Reflects whether the last reset has been generated 02 r through software inside the processor 0 No software reset has occurred 1 Software reset has occurred 129 Maps and Registers System Configuration Registers Bit Name Description 2 RST WD Reflects whether the last reset has been generated through a watchdog timer time out condition 0 No watchdog timer reset has been triggered 1 The watchdog timer reset has been triggered 3 RST RTB Reflects whether the last reset has been generated through a push button reset on the board s IOBP 0 No push button reset from the CPU board s IOBP has been triggered 1 Push button reset from the CPU board s IOBP has been triggered 4 RST VME Reflects whether the last reset has been generated through a VMEbus reset 0 No VMEbus reset has been triggered 1 VMEbus reset has been triggered 5 RST PMC Reflects wheather the last reset has been generated through a PMC module 0 No PMC reset has been triggered 1 PMC reset has been triggered 7 6 0 Reserved Board Status Registers Default Access 02 r 02 r 02 r 02 r 002 r The Board Status registers are used to identify the current configuration of the board The switch settings can be read from two registers Switch 1 and 2 Status Register This register is used to r
112. the main menu hit the enter key Terminating OBDIAG In order to terminate OBDIAG and return to OpenBoot enter exit The OpenBoot prompt will then reappear OBDIAG Commands Apart from testing the hardware you can also call several commands which can be seen in the ODBIAG main menu The following table provides an overview of these commands Table 16 OBDIAG Commands Command Description exit Exits obdiag tool help Prints this help information setenv Sets diagnostic configuration variable to new value printenvs Prints values for diagnostic configuration variables versions Prints selftests library and obdiag tool versions test all Tests all devices displayed in the main menu test 1 2 5 Tests devices 1 2 and 5 except 2 5 Tests all devices except for devices 2 and 5 what 1 2 5 Prints some selected properties for devices 1 2 and 5 OBDIAG provides a brief excerpt of the OpenBoot configuration variables The values of the variables are displayed after entering the following command printenvs You can decide whether the chosen test will either stop at the occurrence of the first error or continue to test the hardware It is also possible to run the test more than once or produce a detailed print out of the test The example below shows the detailed print out of an OBDIAG test Example SPARC CPU 56T 95 OpenBoot Firmware Introduction obdiag gt setenv diag verbosity 2 diag verbosity 2 Hit any key to return t
113. tomatically transfers control to its clients such as OpenBoot VxWorks Chorus Booter during power up Furthermore it provides a unified interface for using public CORE functions Thus the CORE unifies system initialization and minimizes modifications within the upper level firmware Basic System Initialization Running from CORE with bPOST PROM Running from Memory Operating System Figure 24 OpenBoot CORE Overview SPARC CPU 56T Introduction OpenBoot Firmware Additionally CORE is designed to reach the following goals e Ability to use I O devices including serial port flash floppy and net early on the cold boot sequence of a firmware client e Basic system tests that can replace existing POST in min mode e System testing may be done using the POST drop in in max mode e Error recovery from exceptions which currently do not exist in OpenBoot and from any fatal conditions during flash update e Developing standard validation test suites that could prevent major bugs in CORE and clients e Sample client codes that could facilitate any client porting CORE Workflow The following figure describes the workflow of CORE Power On Switch gt NO FALSE S ig gt TRUE bPOST MIN lt diag level gt gt MAX CORE Controls YES User Interface NO NO E g FALSE cPOST If no activity detected for 10 sec SPARC CPU 56T 89 OpenBoot Firmware Introductio
114. ts reserved The Force logo is a trademark of Force Computers GmbH IEEE is a registered trademark of the Institute for Electrical and Electronics Engineers Inc PICMG CompactPCI and the CompactPCI logo are registered trademarks and the PICMG logo is a trademark of the PCI Industrial Computer Manufacturers Group AdvancedTCA and ATCA are trademarks of the PCI Computer Manufacturers Group MS DOS Windows950 Windows980 Windows20000 Windows NT Windows Server 20030 and Windows XP are registered trademarks and the logos are a trademark of the Microsoft Corporation Intel and Pentium are registered trademarks and the Intel logo is a trademark of the Intel Corporation SPARCO is a registerd trademark the SPARC logo is a trademark and Ultra SPARCO is a registered trademark of SPARC International Inc PowerPC is a registered trademark and the PowerPC logo is a trademark of International Business Machines Corporation AltiVec is a registered trademark and the AltiVec logo is a trademark of Motorola Inc Solaris is a trademark of SUN Microsystems Inc Linux Kernel is a free system kernel developed under the GNU General Public License GoAhead is a registered trademark of GoAhead Software Inc and SelfReliant and Self Availability are trademarks of GoAhead Software Inc LynxOS and BlueCat are registered trademarks of LynuxWorks Inc Tornado VxWorks Wind WindNavigator Wind River Systems
115. urs without user intervention If necessary you can explicitly initiate the boot process from the OpenBoot command prompt Automatic booting uses the default boot device specified in the nonvolatile RAM NVRAM User initiated booting either uses the default boot device or one specified by the user In order to boot the system from the default boot device with default settings enter the following command at the Forth monitor prompt ok ok boot The boot command has the following format SPARC CPU 56T Introduction OpenBoot Firmware boot lt device specifier gt lt filename gt lt bootoption gt Optional Boot Parameters Table 13 Boot Parameters Parameter lt device specifier gt lt filename gt lt bootoption gt Boot Devices Description Name full path or alias of the boot device Typical values are cdrom disk floppy net or tape Name of program to be booted The filename parameter is relative to the root of the selected device If no filename is specified the boot command uses the value of the boot file NVRAM parameter The NVRAM parameters used for booting are described in the following section Bootoption may be one of the following a Prompts interactively for device and name of boot file h Halts after loading program r Reconfigures Solaris device drivers after changing hardware configuration v Prints verbose information during boot procedure To explicitly boot from the intern
116. ut time of 655 35 ms Two independent interrupts are possible which can be enabled or disabled with the Interrupt Enable Control register One counter read back register set is also available which shows the correct timer values Both timers can be combined to run as one 32 bit count down timer with a timer interval of 10 us and a total run out time of 42949 67295 s or 11 h 55 min 49 s and 672 95 ms In this mode only one interrupt is possible The timer counts down from its initial value to zero in steps of 10 us The initial value can be set by software from 1 to 65535 in 16 bit mode or from 1 to 4294967295 in the 32 bit mode which results in a timer period of 10 us to 655 35 ms in the 16 bit mode or of 10 us to 42949 67295s in the 32 bit mode If the timer has reached zero an interrupt is generated if enabled and the timer loads its initial value to count down again A detailed description of all registers related to the timers is given in the chapter Maps and Registers Temperature Sensor Control The on board temperature sensor device MAX1617 measures the temperatures of the CPU board and the CPU If the measured temperatures is not within a pre defined range between lower and upper temperature bit 2 is set in the External Failure Register and if enabled an interrupt is generated Local I2C Interface 82 Two separate PC buses are available on the CPU board Both are implemented in the Xilinx FPGA and have the following
117. verse User LED mode 001002 OFF 000012 Green 000102 Red Ethernet activity 110002 Ethernet 1 110012 Ethernet 2 11010 Ethernet 3 11011 gt Ethernet 4 11100 Ethernet 1 3 111013 Ethernet 2 4 11111 Ethernet 1 2 3 4 At all other values the LED is OFF These bits are always zero r Access r w 119 Maps and Registers Address 1FF F160 0113 System Configuration Registers Table 30 LED Control Register 4 Bit Name 4 0 LED_DISPLAY 7 5 Description Default Access User LED mode r w 000002 OFF 000012 Green 000102 Red 00011 Weak red 00101 Slow blinking green 1 2 Hz 00110 Slow blinking red 001112 Slow blinking weak red 010012 Blinking green 1 Hz 01010 Blinking red 01011 Blinking weak red 01101 Fast blinking green 2 Hz 011102 Fast blinking red 011112 Fast blinking weak red 00000 Ethernet activity 11000 gt Ethernet 1 11001 Ethernet 2 11010 Ethernet 3 110112 Ethernet 4 11100 Ethernet 1 3 111013 Ethernet 2 4 11111 Ethernet 1 2 3 4 At all other values the LED is OFF These bits are always zero r External Failure Status Register The External Failure Status register is used to receive information of external failure conditions Overheating or power supply problems All failure conditions can also be configured as an interrupt refer to Interrupt Registers section Address 1FF F160 0120 Table 31 External Failu

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