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National Instruments PC-LPM-16/PnP User's Manual

1. C487 ae lE R544 ala Ow o Li OV Li r UUUUUUUUUUUUUUUUUA E c ce 3 co i C63 aa 0 OS x ce U00000 6000 re lt co 9 2 0000000 R49 OO Q 0C57 ZZ l ASL JareL in e UUUUUUUUUU HCT688 QL8X12B 000000000007 om E 65 UPON n 628 0000000 R3 U14 026 LPM 16 x NATIONAL INSTRUMENTS 10 s 020 S51 U jMCI40918 0000000 e FO e BCA Z0 CD NEAN SN S 04 O0 O00 ORODCAG I Tol fol f as 5 2 Um c5 C46 0 0 0 0 00000000 C49 0 00000000000000 000000000 0 Ue3 00000001 ce c 83527 01 70 A ASS 000000 OOOOOOO Q 31 ce MS7200L2 D Sp2l3v ce r20o0000000000000000 0000000 5228ASN Li cbe 000000000 00 O 1 1 W3 2 Switch U26 W2 W1 5 Serial Number 6 Assembly Number 7 Product N
2. D 29 Table D 3 Bipolar Input Mode A D Conversion Values D 30 PC LPM 16 PnP User Manual Viii National Instruments Corporation About This Manual This manual describes the mechanical and electrical aspects of the PC LPM 16PnP and contains information concerning its installation operation and programming The PC LPM 16PnP is a low cost low power analog input digital and timing I O board for the IBM PC XT PC AT Personal System 2 Models 25 and 30 and laptop compatible computers This manual also applies to the PC LPM 16 a non Plug and Play board The boards are identical in functionality programming and performance except for the differences listed in Appendix C Using Your PC LPM 16 Non PnP Board Organization of This Manual The PC LPM 16 PnP User Manual is organized as follows National Instruments Corporation Chapter 1 Introduction describes the PC LPM 16 PnP lists what you need to get started software programming choices and optional equipment and explains how to unpack the PC LPM 16 PnP Chapter 2 Installation and Configuration describes the installation and configuration of the PC LPM 16PnP Chapter 3 Theory of Operation includes an overview of the PC LPM 16PnP board and explains the operation of each functional unit making up the board This chapter also explains the basic operation of the PC LPM 16PnP ci
3. Address Base address 08 hex Type Read and write Word Size 8 bit Bit Map 7 6 4 3 2 1 0 D7 D6 D5 D4 D3 D2 DI DO Bit Name Description 7 0 D lt 7 0 gt A D Conversion Data Bits 7 through 0 8 bit counter 0 contents National Instruments Corporation D 19 PC LPM 16 PnP User Manual Appendix D Register Level Programming Counter 1 Data Register Use the Counter 1 Data Register to load and read back contents of MSM82C53 counter 1 Address Base address 09 hex Type Read and write Word Size 8 bit Bit Map 7 6 5 4 3 2 1 0 D7 D6 DS D4 D3 D2 DI D0 Bit Name Description 7 0 D lt 7 0 gt A D Conversion Data Bits 7 through 0 8 bit counter 1 contents Counter 2 Data Register Use the Counter 2 Data Register to load and read back contents of MSM82C53 counter 2 Address Base address OA hex Type Read and write Word Size 8 bit Bit Map 7 6 5 4 3 2 1 0 D7 D6 DS D4 D3 D2 DI D0 Bit Name Description 7 0 D lt 7 0 gt A D Conversion Data Bits 7 through 0 8 bit counter 2 contents PC LPM 16 PnP User Manual D 20 National Instruments Corporation AppendixD Register Level Programming Counter Mode Register The Counter Mode Register determines the operation mode for each of the three counters on the MSM82C53 chip The Counter Mode Register selects the counter involved the counter s read load mode its operation mode that is
4. Absolute max ratings A 2 0 1 GQ in parallel with 40 pF typ 200 kHz typ 20 us max at all ranges 0 1 LSB rms for all ranges 15 min 5 000 V 42 5 mV 20 ppm C max 15 ppm 1 000 h typ 8 input and 8 output TTL 1 8 bit input port 1 8 bit output port 7 0 V with respect to DGND voltage input rating 0 5 V with respect to DGND National Instruments Corporation Digital logic levels Timing 1 0 Number of channels Resolution Compatibility Input logic low voltage Input logic high voltage Output logic low voltage at output current 2 4 0 mA Output logic high voltage at output current 1 0 mA Base clocks available Max source frequency Min source pulse duration Min pulse duration Data transfers National Instruments Corporation A 3 Appendix A Specifications E Level Minimum Maximum Input low voltage 08 Input high voltage 2V 5 0 V Input low current 10 pA Vin 0 V Input high current 10 pA Vin 5 V Level Minimum Maximum Output low voltage 0 4 V Mout 4 mA Output high voltage 37 V gut 4 mA 3 counter timers 1 dedicated to analog input 16 bits TTL gate and source pulled high with 4 7 kQ resistors 0 8 V max 2 2 V min 0 45 V max 3 7 V min 1 MHz 0 01 96 8 MHz 60 ns 50 ns Programmed I O PC LPM 16 PnP Use
5. 0 5 LSB max Differential nonlinearity 1 0 LSB max For more information on nonlinearity and quantization error see the Explanation of Analog Input Specifications section Offset error after calibration 1 0 LSB typ 2 0 LSB max National Instruments Corporation A 1 PC LPM 16 PnP User Manual Appendix A Specifications Note Gain error relative to calibration reference After calibration Oto 5 V and 5 V range All other ranges 1 0 LSB typ 2 0 LSB max 2 0 of reading typ 4 0 max LSB refers to the least significant bit of a 12 bit conversion value in the preceding specifications LSB is equivalent to 2 44 mV in the 10 V range 0 to 10 V or 5 V and 1 22 mV in the 5 V ranges 0 to 5 V or 2 5 V Digital 1 0 PC LPM 16 PnP User Manual Amplifier Characteristics Input impedance Dynamic Characteristics Bandwidth Gain 3 4 Settling time to 1 0 LSB for full scale step System noise Stability Recommended warm up Onboard calibration reference Temperature coefficient Long term stability Number of channels Compatibility Configuration
6. Table 4 1 Signal Connection Descriptions Continued Pin Signal Reference Description 40 EXTCONV DGND External Convert Signal This input signal externally initiates an A D conversion 41 OUTO DGND Output of Counter 0 This signal outputs the programmed waveform of counter 0 42 GATEO DGND Counter 0 Gate Input This signal controls the starting interruption and restarting of counter 0 43 OUTI DGND Output of Counter 1 This signal outputs the programmed waveform of counter 1 44 GATEI DGND Counter 1 Gate Input This signal controls the starting interruption and restarting of counter 1 45 CLKI DGND Counter 1 Clock Input This pin is the clock input for counter 1 46 OUT2 DGND Counter 2 Output This pin is the output of counter 2 47 GATE2 DGND Counter 2 Gate Input This signal controls the starting interruption and restarting of counter 2 48 CLK2 DGND Counter 2 Clock Input This pin is the clock input for counter 2 49 5 V DGND 5 Volts This is the 5 VDC power supply from the computer bus This power line has a 1 0 A self resetting fuse in series 50 DGND N A Digital Ground This pin is connected to the digital ground signal Note An asterisk indicates that the signal is active low PC LPM 16 PnP User Manual 4 4 National Instruments Corporation Chapter 4 Signal Connections The connector pins can be grouped into categories of analog input signal pins digita
7. Interrupt Interface Scanning Counter Connector Y EXTCONV MSM82C53 A D Timing Figure 3 3 Analog Input and Data Acquisition Circuitry Block Diagram 3 4 National Instruments Corporation Chapter3 Theory of Operation Analog Input Circuitry The analog input circuitry consists of an input multiplexer a Jumper selectable gain stage and a 12 bit sampling ADC The 12 bit output is sign extended to 16 bits before it is stored in a 256 word deep FIFO memory The input multiplexer stage is made up of a CMOS analog input multiplexer and has 16 analog input channels channels 0 through 15 With the input multiplexer stage input overvoltage protection of 45 V is available powered on or 35 V powered off The PC LPM 16PnP uses a successive approximation analog to digital converter ADC Software selectable gains of 0 5 1 and 2 for the input signal combined with the ADC s fixed input range of 5 V yield four useful analog input signal ranges 0 to 10 V 5 V 0 to 5 V and 2 5 V When an A D conversion is complete the ADC clocks the result into the A D FIFO The A D FIFO is 16 bits wide and 256 words deep This FIFO serves as a buffer to the ADC and has two benefits First any time an A D conversion is complete the A D FIFO saves the value for later reading and the ADC can start a new conversion Secondly the A D FIFO can collect up to 2
8. DAQ PC LPM 16 PnP User Manual Multifunction I O Board for the PC November 1996 Edition Part Number 320287C 01 Copyright 1990 1996 National Instruments Corporation All Rights Reserved Internet Support support natinst com E mail info natinst com FTP Site ftp natinst com Web Address http www natinst com Bulletin Board Support BBS United States 512 794 5422 BBS United Kingdom 01635 551422 BBS France 01 48 65 15 59 E Fax on Demand Support 512 418 1111 lt lt gt Telephone Support U S Tel 512 795 8248 Fax 512 794 5678 lt International Offices Australia 03 9879 5166 Austria 0662 45 79 90 0 Belgium 02 757 00 20 Canada Ontario 905 785 0085 Canada Qu bec 514 694 8521 Denmark 45 76 26 00 Finland 09 527 2321 France 01 48 14 24 24 Germany 089 741 31 30 Hong Kong 2645 3186 Israel 03 5734815 Italy 02 413091 Japan 03 5472 2970 Korea 02 596 7456 Mexico 5 520 2635 Netherlands 0348 433466 Norway 32 84 84 00 Singapore 2265886 Spain 91 640 0085 Sweden 08 730 49 70 Switzerland 056 200 51 51 Taiwan 02 377 1200 U K 01635 523545 National Instruments Corporate Headquarters 6504 Bridge Point Parkway Austin TX 78730 5039 Tel 512 794 0100 Important Information Warranty Copyright Trademarks The PC LPM 16 and PC LPM 16PnP are warranted against defects in materials and workmanship for a period of one year from the date of shipment as evidenced by
9. OUT 5 l OUT GATE H GATE l f GATE j 4 3 2 1 0 OUT n 4 l GATE l 4 3 2 1 4 3 2 1 0 OUT n 4 l Note n is the value set in the counter Figures in these diagrams refer to counter values 174 National Instruments Corporation B 11 PC LPM 16 PnP User Manual PC LPM 16 PnP User Manual 5 82 53 Data Sheet Reading of Counter Values All 82C53 counting is down counting the counting being in steps of 2 in mode 3 Counter values can be read during counting by 1 direct reading and 2 counter latching read on the fly Direct reading Counter values can be read by direct reading opera tions Since the counter value read according to the timing of the RD and CLK signals is not guaranteed it is necessary to stop the counting by a gate input signal or to interrupt the clock input temporarily by an external circuit to ensure that the counter value is correctly read Counter latching In this method the counter value is latched by writing a counter latch command thereby enabling a stable value to be read without effecting the counting in any way at all An example of a counter latching program is given below Counter latching executed for counter 1 Read Load 2 byte setting MVIA 0100xxxx Denotes counter latching OUT n3 Write in control word address n3 The counter value at this point is latched IN n1 Reading of the LSB of the counter
10. negative of or minus ohms per percent plus or minus positive of or plus square root of 5 VDC source signal G 1 PC LPM 16 PnP User Manual Glossary A A AC ACH A D ADC AI AIGATE AIGND AISENSE ANSI AOGND ASIC AWG BBS BCD BIOS cm CMOS PC LPM 16 PnP User Manual amperes alternating current analog input channel signal analog to digital A D converter analog input analog input gate signal analog input ground signal analog input sense signal American National Standards Institute analog output ground signal application specific integrated circuit American Wire Gauge bulletin board support binary coded decimal basic input output system or built in operating system Celsius centimeter complementary metal oxide semiconductor G 2 National Instruments Corporation CTR DAQ DC DMA EISA ESP FIFO ft VO IoL National Instruments Corporation Glossary counter data acquisition direct current direct memory access Extended Industry Standard Architecture Engineering Software Package farads first in first out feet hour hexadecimal hertz input output current output high current output low G 3 PC LPM 16 PnP User Manual Glossary ISA LED LSB MB MSB PC RAM rms S 5 5 SCANCLK SCXI SISOURCE STARTSCAN PC LPM 16 PnP User Manual Industry Standard Architecture light emittin
11. Figure 4 4 EXTCONV Signal Timing General Purpose Timing Signal Connections and General Purpose Counter Timing Signals The general purpose timing signals include the GATE CLK and OUT signals for the three MSM82C53 counters except CLK of counter 0 is not available on the I O connector You can use the counter timers for general purpose applications such as pulse and square wave generation event counting and pulse width time lapse and frequency measurement For these applications user signals sent from the I O connector on the CLK and GATE pins go to the counters and the counters are user programmable for various operations The single exception is counter 0 which has an internal 1 MHz clock Chapter 3 Theory of Operation briefly describes the MSM82C53 counter timer For detailed information on this counter timer see Appendix B MSM82C53 Data Sheet For pulse and square wave generation program a counter to generate a timing signal at its OUT output pin For event counting program a counter to count the rising or falling edges applied to any of the MSM82C53 CLK inputs You can then read the counter value to determine the number of edges that have occurred You can gate the counter operation on and off during event counting Figure 4 5 shows connections for a typical event counting operation where a switch is used to gate the counter on and off National Instruments Corporation 4 9 PC LPM 16 PnP User Manual Chapter4 S
12. If you are a register level programmer refer to Appendix D Register Level Programming for software configuration information Board Configuration Plug and Play PC LPM 16 PnP User Manual The PC LPM 16PnP is fully compatible with the industry standard Intel Microsoft Plug and Play Specification version 1 0a A Plug and Play system arbitrates and assigns resources through software freeing you from manually setting switches and jumpers These resources include the board base I O address and interrupt channels Each PC LPM 16PnP is configured at the factory to request these resources from the Plug and Play Configuration Manager The Configuration Manager receives all of the resource requests at startup compares the available resources to those requested and assigns the available resources as efficiently as possible to the Plug and Play boards Application software can query the Configuration Manager to determine the resources assigned to each board without your involvement The Plug and Play software is installed as a device driver or as an integral component of the computer BIOS 2 2 National Instruments Corporation Non Plug and Play National Instruments Corporation Chapter2 Installation and Configuration Base 1 0 Address and Interrupt Selection You can configure your PC LPM 16PnP to use base addresses in the range of 100 to FFF0 hex The PC LPM 16PnP occupies 16 bytes of address space and must be located on a 16 by
13. Program counter 0 High output of counter 0 enables the EXTCONV signal Write 34 to the Counter Mode Register to force OUTO high enable EXTCONV Writing 30 to the Counter Mode Register forces OUTO low which disables the EXTCONV and stops the data acquisition operation Select the analog input channel Write to Command Register 1 to select the analog input channel The SCANEN bit must be set for data acquisition operation on a single channel See Command Register 1 bit descriptions earlier in this appendix for analog input channel bit descriptions Clear the A D circuitry Before starting the data acquisition operation empty the A D FIFO to clear any old A D conversion results Write 0 to the A D Clear Register and read the A D FIFO Low and High B yte registers to empty the FIFO Ignore the data Start and service the data acquisition operation Clear the DISABDAQ bit in Command Register 2 to start the data acquisition sequence a Write 0 to Command Register 2 to enable the A D conversion b The next EXTCONV signal initiates an A D conversion The operation must be serviced by reading the A D FIFO Register every time an A D conversion result becomes available To D 33 PC LPM 16 PnP User Manual Appendix D Register Level Programming service the data acquisition perform the following sequence until you have read the desired number of conversion results 1 Read the Status Register 2 Ifthe DAVAIL bit is set r
14. 4 8 signal descriptions table 4 3 to 4 4 timing connections 4 8 to 4 12 data acquisition timing connections 4 8 to 4 9 general purpose timing signal connections 4 9 to 4 12 single channel data acquisition 3 7 software installation 2 2 software programming choices 1 2 to 1 4 LabVIEW and LabWindows CVI application software 1 2 to 1 3 NI DAQ driver software 1 3 to 1 4 register level programming 1 4 specifications analog input A 1 to A 2 ADC errors figure A 6 amplifier characteristics A 2 differential nonlinearity A 5 dynamic characteristics A 2 explanation A 4 to A 6 input characteristics 1 integral nonlinearity A 5 relative accuracy A 4 to A 5 stability A 2 system noise A 5 transfer characteristics A 1 to A 2 bus interface A 4 digital I O A 2 to 3 environment A 4 physical A 4 power requirements A 4 timing I O A 3 square wave generation 4 9 Status Register 1 D 10 to D 12 Status Register 2 D 13 switch settings See configuration system noise A 5 National Instruments Corporation 1 7 Index T technical support E 1 to E 2 theory of operation analog input circuitry 3 5 to 3 6 block diagram 3 4 block diagram 3 2 data acquisition timing circuitry 3 6 to 3 7 block diagram 3 5 data acquisition rates 3 7 multichannel scanning data acquisition 3 7 single channel data acquisition 3 7 digital I O circuitry 3 8 functional overview 3 1 PC I O channel interface circuitry 3
15. C 11 bits ARNG lt 1 0 gt D 9 BCD D 23 CALEN D 8 D 28 CNTINT D 11 CNTINTEN D 5 CONVPROG D 10 D lt 7 0 gt Counter 0 Data Register D 19 Counter 1 Data Register D 20 Counter 2 Data Register D 20 Digital Input Register D 25 Digital Output Register D 24 D lt 15 8 gt D 16 DATAERR OVERFLOW D 11 DAVAIL D 12 D 28 D 35 DISABDAQ D 7 D 33 EXTINT D 11 EXTINTEN D 5 FIFOINTEN D 5 D 35 lt 2 0 gt D 23 MA lt 3 0 gt D 5 to D 6 D 34 OVERFLOW D 13 D 28 D 32 D 34 OVERRUN D 13 REVID D 10 RL lt 1 0 gt D 22 SC lt 1 0 gt D 21 SCANEN D 4 D 33 D 34 to D 35 SCANORDER D 7 block diagram of PC LPM 16PnP 3 2 PC LPM 16 PnP User Manual 1 2 board configuration See configuration bulletin board support E 1 bus interface specifications A 4 C cables custom 1 5 to 1 6 CALEN bit D 8 D 28 calibration autocalibration 3 5 to 3 6 programming A D calibration D 27 CLK signal counter block diagram 3 10 general purpose timing and counter timing 4 9 to 4 12 timing requirements for GATE and CLK input signals 4 11 to 4 12 CLK signal table 4 4 CLK2 signal table 4 4 CNTINT bit D 11 CNTINTEN bit D 5 Command Register 1 D 4 to D 6 Command Register 2 D 7 to D 8 Command Register 3 D 9 configuration PC LPM 16 C 4 to C 12 analog input jumper settings C 10 to C 12 bipolar input selection 1 5 V C 10 to C 11 bipolar input selection 2 2 5 V C 11 unipolar input selection 1 0 to
16. Output Delay Time after gate TODG 120 ns rudi Output Delay Time after clock TOD 150 ns Note Timing measured at V 0 8V and Vy 2 2V for both inputs and outputs TIME CHART Write Timing 168 National Instruments Corporation B 5 PC LPM 16 PnP User Manual Appendix B 5 82 53 Data Sheet 1 O MSM82C53 2RS GS JS Read Timing VALID HIGH IMPEDANCE HIGH IMPEDANCE Clock amp Gate Timing 169 PC LPM 16 PnP User Manual B 6 National Instruments Corporation 1 O MSM82C53 2RS GS JS DESCRIPTION OF PIN FUNCTIONS Pin Symbol Name Input output Function Three state 8 bit bidirectional data bus used when writing control words and count values and reading count values upon reception of WR and RD signals from CPU Bidirectional data bus input output CLKO 2 GATEO 2 Chip select input Address input Clock input Gate input Appendix B MSM82C53 Data Sheet Data transfer with the CPU is enabled when this pin is at low level When at high level the data bus Do thru D gt is switched to high impedance state where neither writing nor reading can be executed Internal registers however remain unchanged Data can be transferred from MSM82C53 to CPU when this pin is at low level Data can be transferred from CPU to MSM82C53 when this pin is at low level Counter output SYSTEM INTERFACING 170 COUNTER 0 One of the three intern
17. a quantity often mistakenly assumed to be exactly 1 2 LSB Although quantization uncertainty is ideally 1 2 LSB it can be different for each possible digital code and is actually the analog width of each code Thus it is more specific to use relative accuracy as a measure of linearity than it is to use what is normally called nonlinearity because relative accuracy ensures that the PC LPM 16 PnP User Manual A 4 National Instruments Corporation Appendix A Specifications sum of quantization uncertainty and A D conversion error does not exceed a given amount Integral nonlinearity in a ADC is an often ill defined specification that is supposed to indicate a converter s overall A D transfer linearity The manufacturers of the ADC chips used by National Instruments specify their integral nonlinearity by stating that the analog center of any code will not deviate from a straight line by more than 1 LSB This specification is misleading because although a particularly wide code s center may be found within 1 LSB of the ideal one of its edges may be well beyond 1 LSB thus the ADC would have a relative accuracy of that amount National Instruments tests its boards to ensure that they meet all three linearity specifications defined in this appendix specifications for integral nonlinearity are included primarily to maintain compatibility with a convention of specifications used by other board manufacturers Relative accuracy however is
18. gt l Connector EXTINT Interrupt Interface Digital lt VO 4 FROM A D FIFO PC LPM 16 PnP User Manual Figure 3 1 PC LPM 16PnP Block Diagram 3 2 National Instruments Corporation Chapter3 Theory of Operation PC 1 0 Channel Interface Circuitry Pis PC I O Channel National Instruments Corporation Address Bus Control Lines N Data Bus N The PC I O channel interface circuitry consists of an address bus a data bus interrupt lines and several control and support signals The components making up the PC LPM 16PnP PC I O channel interface circuitry are shown in Figure 3 2 Address Decoder Plug and Regi Play Circuitry gt Register Selects gt Timing Interface gt Read amp Write Signals Data Buffers p Internal Data Bus Plug and Play Interrupt Control Interrupt Requests Figure 3 2 PC 1 0 Interface Circuitry Block Diagram The circuitry consists of Plug and Play address decoders data buffers channel interface timing control circuitry and interrupt control circuitry The circuitry monitors address lines SA4 through SA15 to generate the board enable signal and uses lines SAO through SA3 plus timing signals to generate the onboard register select signals and read write signals The data buffe
19. 10 V C 11 unipolar input selection 2 0 to 5 V C 12 base I O address selection C 5 to C 9 example switch settings figure C 7 PC bus interface factory settings table C 6 National Instruments Corporation switch settings with corresponding base I O address table C 8 to C 9 block diagram revised C 4 interrupt selection C 9 to C 10 disabling interrupts figure C 10 IRQS factory setting figure C 10 overview C 4 to C 5 parts locator diagram revised C 5 PC LPM 16PnP See also installation base I O address and interrupt selection 2 3 Plug and Play compatibility 2 2 to 2 3 Configuration and Status Register Group Command Register 1 D 4 to D 6 Command Register 2 D 7 to D 8 Command Register 3 D 9 overview D 3 register map D 1 Status Register 1 D 10 to D 12 Status Register 2 D 13 CONVPROG bit D 10 Counter 0 Data Register description D 19 programming multiple A D conversions on single channel D 30 to D 32 Counter 1 Data Register D 20 Counter 2 Data Register D 20 counter block diagram 3 10 Counter Mode Register D 21 to D 23 counter timing See general purpose timing and counter timing Counter Timer MSM82C53 Register Group Counter 0 Data Register D 19 D 30 to D 32 Counter 1 Data Register D 20 Counter 2 Data Register D 20 Counter Mode Register D 21 to D 23 overview D 18 programming D 36 National Instruments Corporation 1 3 Index register map D 2 Timer Interrupt Cle
20. 3 to 3 4 block diagram 3 3 timing I O circuitry 3 9 to 3 10 counter block diagram 3 10 time lapse measurement 4 10 Timer Interrupt Clear Register D 24 timing connections 4 8 to 4 12 data acquisition timing connections 4 8 to 4 9 general purpose timing signal connections 4 9 to 4 12 pins 4 8 timing I O circuitry 3 9 to 3 10 counter block diagram 3 10 timing I O specifications A 3 two s complement format 3 5 U unipolar input selection 1 0 to 10 V C 11 unipolar input selection 2 0 to 5 V C 12 unpacking the PC LPM 16PnP 1 6 UP function support for note D 35 PC LPM 16 PnP User Manual
21. 8 Timing Connections itt UE E RO RR e ns 4 8 Data Acquisition Timing Connections sese 4 8 General Purpose Timing Signal Connections and General Purpose Counter Timing Signals sse 4 0 Appendix A Specifications Appendix B MSM82C53 Data Sheet Appendix C Using Your PC LPM 16 Non PnP Board Appendix D Register Level Programming Appendix E Customer Communication PC LPM 16 PnP User Manual vi National Instruments Corporation Table of Contents Glossary Index Figures Figure 1 1 The Relationship between the Programming Environment NI DAQ and Your Hardware essen 1 4 Figure 3 1 PC LPM 16PnP Block Diagram eee 3 2 Figure3 2 PC I O Interface Circuitry Block Diagram eee 3 3 Figure 3 3 Analog Input and Data Acquisition Circuitry Block Diagram 3 4 Figure 3 4 Digital I O Circuitry Block Diagram see 3 8 Figure 3 5 Timing I O Circuitry Block Diagram see 3 9 Figure 3 6 Counter Block Diagram esee 3 10 Figure 4 1 PC LPM 16PnP I O Connector Pin Assignments 4 2 Figure 4 2 Analog Input Signal Connections sess 4 6 Figure 4 3 Analog Input Signal Connections sese 4 7 Figure 4 4 EXTCONV Signal Timing eee 4 0 Figure 4 5 Event Counting Applicat
22. Cables National Instruments currently offers a cable termination accessory the CB 50 for use with the PC LPM 16 PnP This kit includes a terminated 50 conductor flat ribbon cable and a connector block Signal input and output wires can be attached to screw terminals on the connector block and connected to the PC LPM 16 PnP I O connector The CB 50 is useful for the initial prototyping of an application or in situations where PC LPM 16 PnP interconnections are frequently changed Once you develop a final field wiring scheme however you may want to develop your own cable This section contains information and guidelines for the design of custom cables The PC LPM 16 PnP I O connector is a 50 pin male ribbon cable header connector The following list gives recommended part numbers for use with your PC LPM 16 PnP board Electronic Products Division 3M part number 3596 5002 T amp B Ansley Corporation part number 609 5007 National Instruments Corporation 1 5 PC LPM 16 PnP User Manual Chapter 1 Introduction The mating connector for the PC LPM 16 PnP is a 50 position polarized ribbon socket connector with strain relief National Instruments uses a polarized keyed connector to prevent inadvertent upside down connection to the PC LPM 16 PnP Recommended manufacturer part numbers for this mating connector are as follows Electronic Products Division 3M part number 3425 7650 T amp B Ansley Corporation part num
23. L Output Voltage VoL loL 4mA 0 45 v ImA 3 7 H Output Voltage VOH Input Leak Current to OSViN Vcc Vcc 4 5V to 5 5V 10 10 uA Output Leak Current 0 lt Vout lt Ta 40 C to 85 10 10 uA CS 2 Vee 0 2V Standby Supply Current Iccs Vin 2 Vcc 0 2V 100 uA ViL S0 2V Operating Supply Current Ice tcLK 125 ns 0pF 8 mA 167 Appendix B MSM82C53 Data Sheet a 1 O MSM82C53 2RS GS JS AC CHARACTERISTICS Veg 4 5V 5 5V Ta 40 85 C MSM82C53 2 Parameter Symbol Min Max Unit Conditions Address Set up Time before reading TAR 30 ns 150pF Address Hold Time after reading TRA 0 m Read Read Pulse Width TRR 150 ns cycle Read Recovery Time TRVR 200 ns Address Set up Time before writing TAW 0 ns Address Hold Time after writing TWA i 20 ns Write Pulse Width TWW 150 ns Write Data Input Set up Time before writing TDW 100 ns cycle Data Input Hold Time after writing Two 20 ns Write Recovery time TRVW 200 ns Clock Cycle Time TCLK 125 D C ns Clock Pulse Width TPWH 60 ns Clock L Pulse Width TPWL 60 ns Clock H Gate Pulse Width Tow 50 ns Hm L Gate Pulse Width TGL 50 timing Gate Input Set up Time before clock TGS 50 ns Gate Input Hold Time after clock TGH 50 ns Output Delay Time after reading TRD 120 ns ee Floating Delay Time after TDF 5 90
24. LPM 16PnP maintains the required accuracy without trimpot adjustments Data Acquisition Timing Circuitry PC LPM 16 PnP User Manual A data acquisition operation refers to the process of carefully timing the interval between successive A D conversions This interval is called the sample interval The data acquisition timing circuitry consists of various clocks and timing signals that perform this timing The PC LPM 16PnP can perform two types of data acquisition single channel data acquisition and multichannel scanning data acquisition Multichannel scanning data acquisition uses a counter to automatically switch between analog input channels during a data acquisition operation Data acquisition timing consists of signals that initiate a data acquisition operation and generate scanning clocks Sources for these signals are supplied mainly by timers on the PC LPM 16PnP board One of the three counters of the onboard MSM82C53 is reserved for this purpose You can initiate an A D conversion by a falling edge on the counter 0 output OUTO of the MSM82C53 onboard counter timer chip or by a rising edge on EXTCONV input The sample interval timer is a 16 bit down counter that uses the onboard 1 MHz clock to generate sample intervals from 20 to 65 535 Ls see Timing I O Circuitry later in this chapter for more timing information Each time the sample interval timer reaches zero it generates a pulse and reloads with the programmed sample inte
25. PnP Board PC LPM 16 PnP User Manual possible switch settings the corresponding base I O address and the base I O address space used for that setting Table C 3 Switch Settings with Corresponding Base 1 0 Address and Base 1 0 Address Space Switch Setting Base I O Address Base I O Address hex Space Used hex A9 A8 A7 A6 AS 0 1 0 0 0 100 100 10F 0 1 0 0 120 120 13F 0 1 0 1 O 140 140 14F 0 1 0 1 1 160 160 16 0 1 1 0 O 180 180 18F 0 1 1 0 1 1A0 1A0 1AF 0 1 1 1 O0 1C0 1C0 1CF 0 1 1 1 1 1 1E0 1EF 1 0 0 0 O 200 200 20F 1 0 0 0 1 220 220 22F 1 0 0 1 0 240 240 24F 1 0 0 1 1 260 260 26F 1 0 1 0 0 280 280 28F 1 0 1 O 1 2A0 2 0 2 1 0 1 1 O 2C0 2C0 2CF 1 O 1 1 2E0 2 0 2 1 1 0 0 0 300 300 30F 1 1 0 O 320 320 32F C 8 National Instruments Corporation Appendix C Using Your PC LPM 16 Non PnP Board Table C 3 Switch Settings with Corresponding Base 1 0 Address and Base 1 0 Address Space Continued Switch Setting Base I O Address Base I O Address hex Space Used hex A9 A8 A7 A6 AS 1 1 0 1 0 340 340 34F 1 1 0 1 1 360 360 36 1 1 1 0 O 380 380 38 1 1 1 O 1 3A0 3A0 3AF 1 1 1 1 O 3C0 3C0 3CF 1 1 1 1 1 3E0 3E0 3EF Note Base I O address values hex 000 through OFF are reserved for system use Base I O address values hex 100 through 3FF are available on the I O channel Interrupt Selection The PC
26. by using the leading edge of the gate input as a trigger the counter output is switched to L level by the next clock after the gate input trigger This L level status is maintained during the set count value and is switched back to H level when the terminal count is reached Once counting has been started there is no inter ruption until the terminal count is reached even if the gate input is switched to L level in the mean time And although counting continues even if a new count value is written during the counting counting is started at the new count value if another trigger is applied by the gate input o Mode 2 rate generator The counter output is switched to H level by the mode setting When the gate input is at H level counting is started by the next clock after the count value has been written And if the gate input is at L level counting is started by using the rising edge of the gate input as a trigger after the count value has been set An L level output pulse appears at the counter output during a single clock duration once every n clock inputs where n is the set count value If a new count value is written during while counting is in progress counting is started at the new count value following output of the pulse currently being counted And if the gate input is switched to L level during counting the counter output is forced to switch to H level the counting being
27. can also download the latest instrument drivers updates and example programs Forrecorded instructions on how to use the bulletin board and FTP services and for BBS automated information call 512 795 6990 You can access these services at United States 512 794 5422 Up to 14 400 baud 8 data bits 1 stop bit no parity United Kingdom 01635 551422 Up to 9 600 baud 8 data bits 1 stop bit no parity France 01 48 65 15 59 Up to 9 600 baud 8 data bits 1 stop bit no parity FTP Support To access our FTP site log on to our Internet host ftp natinst com as anonymous and use your Internet address such as Joesmith anywhere com as your password The support files and documents are located in the support directories National Instruments Corporation E 1 PC LPM 16 PnP User Manual Fax on Demand Support Fax on Demand is a 24 hour information retrieval system containing a library of documents on a wide range of technical information You can access Fax on Demand from a touch tone telephone at 512 418 1111 E Mail Support currently U S only You can submit technical support questions to the applications engineering team through e mail at the Internet address listed below Remember to Include your name address and phone number so we can contact you with solutions and suggestions support natinst com Telephone and Fax Support National Instruments has branch offices all over the world Use the list below to find the
28. desired valve to the UP DOWN bit in Command Register 2 if the UP IDOWN bit is not currently set to its proper value Then write MA 3 0 with SCANEN set to load the scan counter Then write MA lt 3 0 gt with SCANEN cleared to enable scanning For example if the UP DOWN bit is 0 and MA lt 3 0 gt is 0011 and SCANEN is first set then cleared analog input channels 3 through 0 are sampled alternately during subsequent data conversions If SCANEN is set and 1s not cleared with MA 3 0 still set to 0011 only analog input channel 3 is sampled during the subsequent data conversions See the Programming Multiple A D Conversions with Channel Scanning section later in this appendix for more information D 4 National Instruments Corporation Command Register 1 Appendix D Register Level Programming Continued 6 CNTINTEN 5 EXTINTEN 4 FIFOINTEN 3 0 MA lt 3 0 gt National Instruments Corporation Counter Interrupt Enable Bit With this bit the counter 2 output can cause interrupts The power on value is 0 If this bit is set an interrupt occurs when counter 2 output makes a low to high transition Clear this interrupt by writing to the Timer Interrupt Clear Register If this bit is cleared interrupts from counter 2 output are ignored External Interrupt Enable Bit This bit enables and disables the generation of an interrupt when the EXTINT signal on the I O connector is asserted low externally The
29. factory configured for the 5 V input range Four ranges are available for analog input bipolar 5 V bipolar 2 5 V unipolar 0 to 10 V and unipolar 0 to 5 V Jumpers W1 and W2 control the input range for all 16 analog input channels Bipolar Input Selection 1 5 V Select the bipolar 5 V input configuration by setting jumpers W1 and W2 as shown in Figure C 5 PC LPM 16 PnP User Manual C 10 National Instruments Corporation Appendix C Using Your PC LPM 16 Non PnP Board W1 W2 A A B Figure C 5 Bipolar Input 5 V Jumper Configuration Factory Setting Bipolar Input Selection 2 2 5 V Select the bipolar 2 5 V input configuration by setting jumpers W1 and W2 as shown in Figure C 6 UJ O W1 W2 A A B B Figure C 6 Bipolar Input 2 5 V Jumper Configuration Unipolar Input Selection 1 0 to 10 V Select the unipolar 0 to 10 V input configuration by setting Jumpers W1 and W2 as shown in Figure C 7 W1 W2 A A B B Figure C 7 Unipolar Input 0 to 10 V Jumper Configuration National Instruments Corporation C 11 PC LPM 16 PnP User Manual Appendix C Using Your PC LPM 16 Non PnP Board Installation PC LPM 16 PnP User Manual Unipolar Input Selection 2 0 to 5 V Select the unipolar 0 to 5 V input configuration by using the same setting as the 5 V range setting shown in Figure C 5 You can use this setting because the ADC is 12 bit Therefore 12 bit resolution da
30. gate hold time gate high level gate low level output delay from clock output delay from gate 125 ns min 60 ns min 60 ns min 60 ns min 60 ns min 60 ns min 60 ns min 60 ns min 60 ns min Figure 4 7 General Purpose Timing Signals The GATE and OUT signals in Figure 4 7 are referenced to the rising edge of the CLK signal PC LPM 16 PnP User Manual 4 12 National Instruments Corporation Specifications Appendix This appendix lists the PC LPM 16PnP specifications These specifications are typical at 25 C unless otherwise specified The operating temperature range is 0 to 70 C PC LPM 16PnP Board Analog Input Input Characteristics Number of channels 16 single ended Type of ADC esent nes Successive approximation Resolution Z sa apani iaia as 12 bits 1 in 4 096 Max sampling 50 kS s Input signal ranges 5 V 2 5 V 0 to 10 V or 0 to 5 V software selectable Input coupling DC Overvoltage protection 45 V powered on 35 V powered off Inputs protected ACH lt 0 15 gt FIFO buffer size o oo eee 256 S Data tr nsits Interrupts programmed 1 Transfer Characteristics Relative accuracy 1 0 LSB typ 1 5 LSB max Integral nonlinearity
31. gt Input Voltage Range 00 0to 10 V 10 5 V 0to5 V 11 42 5 V The power on value for ARNG lt 1 0 gt is 10 National Instruments Corporation D 9 PC LPM 16 PnP User Manual Appendix D Register Level Programming Status Register 1 Status Register 1 indicates the status of the current A D conversion The bits in this register determine if a conversion is being performed if data is available if any errors have been found and the interrupt status Address Base address 00 hex Type Read only Word Size 8 bit Bit Map 7 6 4 3 2 1 0 REVID x x CONVPROG EXTINT CNTINT DATAERR DAVAIL OVERFLOW Bit Name Description 7 REVID Revision ID Bit This bit identifies the board revision If this bit is cleared the board is arevision A legacy PC LPM 16 board If this bit is set the board is a revision B or later PC LPM 16 board The revision B board has one more bit in Command Register 2 to disable the data acquisition operation This bit is always set for the PC LPM 16PnP board 6 5 X Don t care bits CONVPROG Conversion Progress Status Bit When an A D conversion is in progress or the auto calibration operation of the ADC is in progress this bit is set Otherwise it 1s cleared PC LPM 16 PnP User Manual D 10 National Instruments Corporation Status Register 1 Appendix D Register Level Programming Continued Bit Name 3 EXTINT 2 CNTINT 1 DATAERR OVERFLOW National Instruments Co
32. have problems with them To make it easy for you to contact us this manual contains comment and configuration forms for you to complete These forms are in Appendix E Customer Communication at the end of this manual Xii National Instruments Corporation Chapter Introduction This chapter describes the PC LPM 16 PnP lists what you need to get started software programming choices and optional equipment and explains how to unpack the PC LPM 16 PnP About the PC LPM 16 PnP The PC LPM 16 PnP is a low cost low power analog input digital and timing I O board for the PC The board contains a 12 bit successive approximation self calibrating ADC with 16 analog inputs 8 lines of TTL compatible digital input and 8 lines of digital output The PC LPM 16 PnP also contains two 16 bit counter timer channels for timing I O The low cost of a PC LPM 16 PnP based system makes it ideal for laboratory work in industrial and academic environments The board s low power consumption and small size make the PC LPM 16 PnP especially suitable for laptop computers The multichannel analog input is useful in signal analysis and data logging The 12 bit ADC is useful in high resolution applications such as chromatography temperature measurement and DC voltage measurement You can use the 16 TTL compatible digital I O lines for switching external devices such as transistors and solid state relays for reading the status of external
33. multiplexers and operational amplifier further limits the data acquisition rate After the input multiplexers switch channels the amplifier must be able to settle to the new input signal value to within 12 bit accuracy before performing an A D conversion or else it will not achieve 12 bit accuracy The maximum data acquisition rate for both single channel and multichannel operation is 50 kS s The signal will settle to 1 LSB for any range if you do not exceed a signal sampling frequency of 50 kS s If you exceed the recommended data acquisition rate the analog input circuitry may not perform at 12 bit accuracy If you exceed this rate an error condition called overrun occurs and you will lose some conversion data This recommended rate of 50 kS s assumes that voltage levels on all the channels included in the scan sequence are within range and are driven by low impedance sources Signal levels outside the ranges on the channels included in the scan sequence adversely affect the input settling time Similarly channels driven by high impedance signal sources should be allowed for greater settling time National Instruments Corporation 3 7 PC LPM 16 PnP User Manual Chapter3 Theory of Operation Digital 1 0 Circuitry The PC LPM 16PnP has 16 digital I O lines that are TTL compatible Pins DIN O 7 of the I O connector are digital input lines and pins DOUT lt 0 7 gt are digital output lines These lines are monitored or driven by t
34. output is switched to H level by the mode setting Counting is started and the gate input used in the same way as in mode 1 The counter output is identical to the mode 4 out put The various roles of the gate input signals in the above modes are summarized in the following table Rising Edge H Level Counting possible put appears one clock earlier in mode 2 and that pulses are not repeated in mode 4 Counting is L Level Falling Edge Counting not possible Start of counting Retriggering Counting not possible ti ibl Counter output forced to H level Counting possible Start of counting Counting not possible tart of countin Counter output forced to H level s g Counting possible Counting not possible Counting possible Start of counting Retriggering 4 2 1 1 4 3 2 1 0 2 1 0 OUT GATE H f WR n 4 j I oe as GATE 4 4 4 4 3 2 1 0 GATE OUT GATE j l J 4 3 2 4 3 2 1 OUT 4 173 PC LPM 16 PnP User Manual B 10 National Instruments Corporation Appendix B MSM82C53 Data Sheet a 1 O MSM82C53 2RS GS JS WR l 4 J n 2 J 4 3 2 1 4 3 2 1 2 1 2 OUT GATE H l l J GATE j l I 4 3 2 1 4 4 3 2 1 OUT n 4 l wa 6 2 f Lin 3 f 4 2 4 2 4 2 4 2 3 2 3 3 OUT GATE H J l GATE l j 5 4 2 5 2 5 4 2 5 2 5 4
35. receipts or other documentation National Instruments will at its option repair or replace equipment that proves to be defective during the warranty period This warranty includes parts and labor The media on which you receive National Instruments software are warranted not to fail to execute programming instructions due to defects in materials and workmanship for a period of 90 days from date of shipment as evidenced by receipts or other documentation National Instruments will at its option repair or replace software media that do not execute programming instructions if National Instruments receives notice of such defects during the warranty period National Instruments does not warrant that the operation of the software shall be uninterrupted or error free A Return Material Authorization RMA number must be obtained from the factory and clearly marked on the outside of the package before any equipment will be accepted for warranty work National Instruments will pay the shipping costs of returning to the owner parts which are covered by warranty National Instruments believes that the information in this manual is accurate The document has been carefully reviewed for technical accuracy In the event that technical or typographical errors exist National Instruments reserves the right to make changes to subsequent editions of this document without prior notice to holders of this edition The reader should consult National Instruments if error
36. restarted by the rising edge of the gate input Mode 3 square waveform rate generator The counter output is switched to H level by the mode setting Counting is started in the same way as described for mode 2 above The repeated square wave output appearing at the counter output contains half the number of counts as the set count value If the set count value n is an odd number the repeated square wave output consists of only n 1 2 clock inputs at level and n 1 2 clock inputs at L level If a new count value is written during counting the new count value is reflected immediately after the 5 82 53 Data Sheet PC LPM 16 PnP User Manual Appendix B 5 82 53 Data Sheet change H to L or L to H in the next counter output to be executed The counting opera tion at the gate input is done the same as in mode 2 Mode 4 software trigger strobe The counter output is switched to H level by the mode setting Counting is started in the same way as described for mode 0 A single L pulse equiva lent to one clock width is generated at the counter output when the terminal count is reached This mode differs from 2 in that the L level out O MSMB82C53 2RS GS JS stopped when the gate input is switched to L level and restarted from the set count value when switched back to H level Mode 5 hardware trigger strobe The counter
37. technical support number for your country If there is no National Instruments office in your country contact the source from which you purchased your software to obtain support CS S Q lt gt Telephone Fax Australia 03 9879 5166 03 9879 6277 Austria 0662 45 79 90 0 0662 45 79 90 19 Belgium 02 757 00 20 02 757 03 11 Canada Ontario 905 785 0085 905 785 0086 Canada Quebec 514 694 8521 514 694 4399 Denmark 45 76 26 00 45 76 26 02 Finland 09 527 2321 09 502 2930 France 01 48 14 24 24 01 48 1424 14 Germany 089 741 31 30 089 714 60 35 Hong Kong 2645 3186 2686 8505 Israel 03 5734815 03 5734816 Italy 02 413091 02 41309215 Japan 03 5472 2970 03 5472 2977 Korea 02 596 7456 02 596 7455 Mexico 5 520 2635 5 520 3282 Netherlands 0348 433466 0348 430673 Norway 32 84 84 00 32 84 86 00 Singapore 2265886 2265887 Spain 91 640 0085 91 640 0533 Sweden 08 730 49 70 08 730 43 70 Switzerland 056 200 51 51 056 200 51 55 Taiwan 02 377 1200 02 737 4644 U K 01635 523545 01635 523154 Technical Support Form Photocopy this form and update it each time you make changes to your software or hardware and use the completed copy of this form as a reference for your current configuration Completing this form accurately before contacting National Instruments for technical support helps our applications engineers answer your questions more efficiently If you are using any National Instruments hardware or software products related to this problem in
38. the following steps Write 00 hex to the Command Register 2 Write 80 hex to the Command Register 1 Write 34 hex to the Counter Mode Register Write 00 hex to the Timer Interrupt Clear Register Write 00 hex to the A D Clear Register Read from A D FIFO High Byte and Low Byte Registers and ignore the data UA cd CIS en D 26 National Instruments Corporation Appendix D Register Level Programming This sequence leaves the PC LPM 16 PnP circuitry in the following state Counter 0 output is high Multichannel scan is disabled All interrupts are disabled Analog input circuitry is initialized to channel 0 The A D FIFO is cleared For additional details concerning the 5 82 53 counter timer see Appendix B M M62C53 Data Sheet Programming the A D Calibration The ADC is a self calibration converter and a self calibration cycle adjusts positive linearity and full scale errors To start a self calibration cycle perform the following steps l Write 01 to Command Register 2 to enable the self calibration cycle Read Command Register 2 to start the self calibration cycle and ignore the result of the reading Read the Status Register and check the CONVPROG bit After starting the self calibration checking this bit can detect the completion of the self calibration cycle A one in this bit indicates the calibration is in progress and zero indicates the completion of the calibration After t
39. to Command Register 1 only when the analog input channel scanning mode or interrupt mode needs to be changed To enable the data acquisition operation clear the CALEN bit of Command Register 2 Program the Sample Interval Counter counter 0 Counter 0 of the MSM82C53 counter timer is used as the sample interval counter A low to high transition on OUTO counter 0 output initiates a conversion You can program counter 0 to generate a pulse once every N us N is referred to as the sample interval that is the time between successive A D conversions N can be between 20 and 65 535 The sample interval is equal to the period of the timebase clock used by counter 0 multiplied by N A 1 MHz clock is internally connected to CLKO the clock used by counter 0 Use the following programming sequence to program counter 0 the sample interval counter All writes are 8 bit write operations All values given are hexadecimal a Write 34 to the Counter Mode Register select counter 0 mode 2 b Write the least significant byte of the sample interval to the Counter 0 Data Register c InStep a writing to the Counter Mode Register forces OUTO to high To finish programming counter 0 you must also write the most significant byte However this writing starts the counting so perform this writing in step 4 Clear the A D circuitry Before starting the data acquisition operation empty the A D FIFO to clear out any old A D conversion re
40. value setting must conform with the Read Load format set in advance Note that the internal counters are reset to during control word setting The counter value OOOOH can t be read If the two bytes LSB and MSB are written at this stage RLO and RL1 1 1 take note of the following precaution Although the count values may be set in the three counters in any sequence after the control word has been set in each counter count values must be set consecutively in the LSB MSB order in any one counter 171 National Instruments Corporation 1 0 MSM82C53 2RS GS JS e Example of control word and count value setting Counter 0 Read Load LSB only Mode 3 Binary count count value 3H Counter 1 Read Load MSB only Mode 5 Binary count count value AAOOH Counter 2 Read Load LSB and MSB Mode 0 BCD count count value 1234 MVI A 1EH QUT n3 Counter 0 control word setting MVI A ean OUT n3 Counter 1 control word setting MVI A B1 n i QUT n3 Counter 2 control word setting A 03H OUT Counter 0 count value setting MVI A AAH OUT n1 Counter 1 count value setting MV A 34H OUT n2 Counter 2 count value setting MV A 12H LSB then MSB OUT n2 Notes nO Counter 0 address n1 Counter 1 address n2 Counter 2 address n3 Control word register address e The minimum and maximum count values which can be counted in each mode are listed below Mode vin Max
41. 56 A D conversion values before losing any information thus giving the software some extra time 256 times the sample interval to catch up with the hardware If the A D FIFO stores more than 256 values without the A D FIFO being read an error condition called A D FIFO Overflow occurs and A D conversion information is lost The A D FIFO generates a signal that indicates when it contains conversion data You can read the signal state from the PC LPM 16PnP Status Register 1 The output from the ADC is in two s complement format In unipolar input mode 0 to 10 V or 0 to 5 V input range configuration the data from the ADC is interpreted as a 12 bit positive number ranging from 0 to 4 095 In bipolar input mode 5 or 2 5 V input range configuration the data from the ADC is interpreted as a two s complement number ranging from 2 048 to 2047 The ADC s output is always sign extended to 16 bits by board circuitry so that data values read from the FIFO are 16 bits wide The ADC on the PC LPM 16PnP includes calibration circuitry that makes it possible to minimize zero full scale and linearity errors The National Instruments Corporation 3 5 PC LPM 16 PnP User Manual Chapter 3 Theory of Operation ADC goes through a self calibration cycle under software control To properly use this ADC auto calibration feature you need an accurate input stage that does not introduce significant offset and gain errors The analog input stage on the PC
42. 6 non PnP only writing to this register clears the data FIFO and loads a single conversion into the FIFO After writing to the A D Clear Register it is necessary to read both the High and Low Byte FIFOs The data that is read back should be ignored Address Base address 01 hex Type Write only Word Size 8 bit Bit Map Not applicable no bits used National Instruments Corporation D 17 PC LPM 16 PnP User Manual Appendix D Register Level Programming PC LPM 16 PnP User Manual Counter Timer MSM82C53 Register Group The five registers making up the Counter Timer Register Group access the onboard MSM82C53 counter timer The 5 82 53 has three counters counter 0 counter 1 and counter 2 Counter 0 controls onboard data acquisition timing and all three counters are available for general purpose timing functions The 5 82 53 has three independent 16 bit counters and one 8 bit Mode Register The Mode Register sets the mode of operation for each of the three counters Writing to the Timer Interrupt Clear Register clears the interrupt request asserted when a low pulse is detected on the output of counter 2 Bit descriptions for the registers in the Counter Timer Register Group are given in the following pages D 18 National Instruments Corporation Appendix D Register Level Programming Counter 0 Data Register Use the Counter 0 Data Register to load and read back contents of MSM82C53 counter 0
43. CLK2 GATE2 OUT2 j I O Connector Plug and Play Interrupt Interface Counter Timer Figure 3 5 Timing 1 0 Circuitry Block Diagram The 5 82 53 contains three independent 16 bit counter timers and one 8 bit Mode Register As shown in Figure 3 5 you can use counter 0 for data acquisition timing and counters and 2 are free for general use You can program all three counter timers to operate in several useful timing modes The programming and operation of the MSM82C53 is presented in detail both in Appendix B MSM amp 2C53 Data Sheet and Appendix D Register Level Programming The timebase for counter 0 uses a 1 MHz clock generated from an onboard oscillator You must externally supply the timebases for counters 1 and 2 through the 50 pin I O connector Figure 3 6 diagrams the 16 bit counters in the MSM82C53 National Instruments Corporation PC LPM 16 PnP User Manual Chapter3 Theory of Operation PC LPM 16 PnP User Manual Counter Figure 3 6 Counter Block Diagram Each counter has a clock input pin a gate input pin and an output pin labeled CLK GATE and OUT respectively The MSM82CS53 counters are numbered zero through two and their GATE CLK and OUT pins are labeled GATEN CLKN and where N is the counter number 3 10 National Instruments Corporation Chapter Signal Connections This chapter describes how to ma
44. DIP switch to set the base I O address Jumper W3 selects the interrupt level Jumpers W1 and W2 configure the analog input circuitry The DIP switch and jumpers are shown in the parts locator diagram in Figure C 1 The PC LPM 16 is factory configured to a base I O address of hex 260 and to interrupt level 5 These settings shown in Table C 1 are suitable for most systems However if your system has other hardware at this base I O address or interrupt level you need to change these settings on the PC LPM 16 as described in the following pages or on the other hardware Record your settings in the Hardware and Software Configuration Form in Appendix E Customer Communication PC LPM 16 PnP User Manual C 4 National Instruments Corporation Appendix C Using Your PC LPM 16 Non PnP Board O or aH LOO e exu D ELE cnc 11 9 ura 900 001 y Us x 00009 in ow Og LTE Gb R3RARS CH S N ee 55005 929 UA 2 Hs e9200 CO C 05 R9 A o z725 MC cx ES my 590S D nL nega of OOC 0000 pRES 10 cogo 9 0 0 oo 9 c20 C 00 00000000 no duc 3 0096 0 9 gee oo SS S208 SOR OC O rq gt gt 0 bL 0 00 00 0 0 0 39 0
45. Interrupt level of other boards Other Products Computer make and model Microprocessor Clock frequency or speed Type of video board installed Operating system version Operating system mode Programming language Programming language version Other boards in system Base I O address of other boards DMA channels of other boards Interrupt level of other boards Documentation Comment Form National Instruments encourages you to comment on the documentation supplied with our products This information helps us provide quality products to meet your needs Title PC LPM 16 PnP User Manual Edition Date November 1996 Part Number 320287C 01 Please comment on the completeness clarity and organization of the manual If you find errors in the manual please record the page numbers and describe the errors Thank you for your help Name Title Company Address Phone Mail to Technical Publications Fax to Technical Publications National Instruments Corporation National Instruments Corporation 6504 Bridge Point Parkway 512 794 5678 Austin TX 78730 5039 Glossary Prefix Meaning Value p pico 10712 n nano 107 u micro 1076 m milli 1073 k kilo 103 M mega 106 G giga 10 Symbols degrees I 5 V National Instruments Corporation
46. LPM 16 connects to any one of the six interrupt lines of the computer I O channel A jumper selects the interrupt line on one of the double rows of pins located above the I O slot edge connector on the PC LPM 16 see Figure C 1 To use the PC LPM 16 interrupt capability select an interrupt line and place the jumper in the appropriate position to enable that particular interrupt line The interrupt lines that the PC LPM 16 hardware supports are IRQ lt 3 7 gt and IRQ9 Note Using interrupt line 6 is not recommended The diskette drive controller uses interrupt line 6 on most IBM PC and compatible computers After you select an interrupt level place the interrupt jumper on the appropriate pins to enable the interrupt line The interrupt jumper setting is W3 The default interrupt line is IRQ5 which you select by placing the jumper on the pins in row 5 as shown in Figure C 3 To change to another line remove the jumper from IRQ5 and place it on the new pins National Instruments Corporation C 9 PC LPM 16 PnP User Manual Appendix C Using Your PC LPM 16 Non PnP Board Figure C 3 Interrupt Jumper Setting IRQ5 Factory Setting If you do not want to use interrupts set the jumper on W3 as shown in Figure C 4 This setting disables the PC LPM 16 from asserting an interrupt line on the computer I O channel Figure C 4 Interrupt Jumper Setting for Disabling Interrupts Analog Input Jumper Settings The PC LPM 16 is
47. M 16PnP Assembly Number 181215 01 183527X 02 183527X 01 I O Space Required 32 bytes 16 bytes 16 bytes I O Base Address Uses switches Uses switches Plug and Play Selection compatible I O Base Address Located on 32 byte Located on 32 byte Located on 16 byte Alignment boundary boundary boundary IRQ Selection Uses jumpers Uses jumpers Plug and Play compatible Gain Selection Selectable with Software selectable jumpers Selectable with jumpers National Instruments Corporation C 1 PC LPM 16 PnP User Manual Appendix C Using Your PC LPM 16 Non PnP Board Table C 1 Comparison of Characteristics Continued Functional Changes Legacy PC LPM 16 Revised PC LPM 16 PC LPM 16PnP Data FIFO Size 16 words 512 words 256 words Dummy reads to A D Required Not required but Not required but and FIFO high byte allowed allowed and low byte registers after clearing data FIFO ADC FIFO Data Low byte before Low byte must be Low byte must be Reading Order high byte preferred read before high read before high byte byte Overflow Error Bit Location Status Register 1 bit 1 Status Register 1 bit 1 Status Register 2 bit 1 Overrun Error Bit Location Not implemented Not implemented Status Register 2 bit 0 Data Error Bit Not implemented Not implemented Status Register 1 Location bit 1 5 and 12 V Sup
48. P D 26 to D 27 input multiplexer 3 5 installation See also configuration PC LPM 16 C 12 PC LPM 16PnP hardware 2 1 software 2 2 unpacking 1 6 integral nonlinearity A 5 interrupt programming A D D 35 National Instruments Corporation interrupt selection PC LPM 16 C 9 to C 10 disabling interrupts figure C 10 IRQS factory setting figure C 10 PC LPM 16PnP 2 3 I O connector exceeding maximum ratings warning 4 1 pin assignments figure 4 2 J jumper settings See configuration L LabVIEW and LabWindows CVI application software 1 2 to 1 3 M lt 2 0 gt bits D 23 MA lt 3 0 gt bits D 5 to D 6 0 34 manual See documentation MSMS82C53 Counter Timer integrated circuit See also Counter Timer MSM82C53 Register Group data acquisition timing 3 9 data sheet B 1 to B 12 timing I O circuitry 3 9 multichannel data acquisition 3 7 multiple A D conversions programming on single input channel using Counter 0 D 30 to D 32 using external timing D 33 to D 34 with channel scanning D 34 to D 35 multiplexer input 3 5 NI DAQ driver software 1 3 to 1 4 National Instruments Corporation Index 0 operation of PC LPM 16PnP See theory of operation OUT signal counter block diagram 3 10 general purpose timing and counter timing 4 9 to 4 12 timing specifications for OUT output signals 4 11 to 4 12 OUTO signal table 4 4 OUT signal table 4 4 signal table 4 3 OUT2
49. P PnP Plug and Play means that the board is fully compatible with the industry standard Plug and Play ISA Specification All bus related configuration is performed through software freeing you from manually configuring jumpers or switches to set the product s base address and interrupt level Plug and Play systems automatically arbitrate and assign system resources to a PnP product Abbreviations acronyms metric prefixes mnemonics symbols and terms are listed in the Glossary National Instruments Documentation The PC LPM 16 PnP User Manual is one piece of the documentation set for your DAQ or SCXI system You could have any of several types of manuals depending on the hardware and software in your system Use the manuals you have as follows Getting Started with SCXI If you are using SCXI this is the first manual you should read It gives an overview of the SCXI system and contains the most commonly needed information for the modules chassis and software e Your SCXI hardware user manuals If you are using SCXI read these manuals next for detailed information about signal connections and module configuration They also explain in greater detail how the module works and contain application hints e Your DAQ hardware documentation This documentation has detailed information about the DAQ hardware that plugs into or is connected to your computer Use this documentation for hardware National Instruments Corporatio
50. Remarks po fs e aera ditto in other modes dob ll 2 2 o teannotte counted 3 2 1 executes 10001H count eee eee kee IEEE Mode Definition Mode 0 terminal count The counter output is set to L level by the mode setting f the count value is then written in the counter with the gate input at H level that is upon completion of writing the MSB when there are two bytes the clock input counting is started When the terminal count is reached the output is switched to H level and is maintained in this status until the control word and count value are set again Counting is interrupted if the gate input is switched to L level and restarted when switched back to H level When Count Values are written during counting the operation is as follows 172 National Instruments Corporation B 9 Appendix B 1 byte Read Load When the new count value is written counting is stopped immediately and then restarted at the new count value by the next clock 2 byte Read Load When byte 1 LSB of the new count value is written counting is stopped immediately Counting is restarted at the new count value when byte 2 MSB is written Mode 1 programmable one shot The counter output is switched to H level by the mode setting Note that in this mode counting is not started if only the count vatue is written Since counting has to be started in this mode
51. SCANEN is set a single analog channel specified by MA lt 3 0 gt is sampled during the entire data acquisition operation See the Programming Multiple A D Conversions with Channel Scanning section later in this appendix for the correct sequence involved in setting the SCANEN bit D 6 National Instruments Corporation Command Register 2 Appendix D Register Level Programming Command Register 2 contains only one bit that enables the auto calibration operation of the ADC Address Base address 07 hex Type Read and write Word Size 8 bit Bit Map 7 6 5 3 2 1 0 0 0 0 0 SCANORDER DISABDAQ CALEN Bit Name Description 7 3 0 Reserved bits These bits must be set to zero for future board compatibility 2 SCANORDER Scan Order Bit TIf this bit is cleared the scan order is from the channel in Command Register 1 MA lt 3 0 gt to channel 0 The power on value is 0 If this bit is set the scan order begins with channel 0 and ends with the channel number in MA lt 3 0 gt This bit is cleared upon power up To ensure proper scanning this bit should be correctly programmed before writing to the SCANEN and Channel Selection bits in Command Register 1 This bit is only present on the PC LPM 16PnP cP Note The UP function is not yet supported by NI DAQ NI DAQ will support the UP function in a future release 1 DISABDAQ National Instruments Corporation Disable Data Acquisition Bit Thi
52. This appendix contains a manufacturer data sheet for the MSM82C53 CMOS programmable interval timer OKI Semiconductor This timer is used on the PC LPM 16PnP board Copyright O OKI Semiconductor 1995 Reprinted with permission of copyright owner All rights reserved OKI Semiconductor Data Book Microprocessor Eight Edition January 1995 National Instruments Corporation B 1 PC LPM 16 PnP User Manual Appendix B MSM82C53 Data Sheet OKI semiconductor MSM82C53 2RS GS US CMOS PROGRAMMABLE INTERVAL TIMER GENERAL DESCRIPTION The MSM82C53 2RS GS JS is programmable universal timers designed for use in microcomputer syste ms Based on silicon gate CMOS technology it requires a standby current of only 1004A max when the chip is in the nonselected state During timer operation power consumption is still very low with only 8 mA max at 8 MHz of current required The device consists of three independent counters and can count up to a maximum of 8 MHz MSM82C53 2 The timer features six different counter modes and binary count BCD count functions Count values can be set in byte or word units and all functions are freely programmable FEATURES Maximum operating frequency of 8 MHz MSMB2C53 2 Six counter modes abailable for each counter High speed and low power consumption achieved Binary and decimal counting possible through silicon gate CMOS technology 24 pin Plastic DIP DIP24 P 600 Completely s
53. al counters or the control word regis ter is selected by 1 combination These two pins are normally connected to the two lower order bits of the address bus Supply of three clock signals to the three counters incorpo rated in MSM82C53 Control of starting interruption and restarting of counting in the three respective counters in accordance with the set control word contents Output of counter output waveform in accordance with the set mode and count value ADDRESS BUS 16 bits CONTROL BUS DATA BUS COUNTER 1 COUNTER 2 OUT GATE CLK OUTGATECLK OUT CLK National Instruments Corporation B 7 PC LPM 16 PnP User Manual Appendix B PC LPM 16 PnP User Manual 5 82 53 Data Sheet DESCRIPTION OF BASIC OPERATIONS O MSMB82C53 2RS GS JS Data transfers between the internal registers and the external data bus is outlined in the following table x denotes not specified DESCRIPTION OF OPERATION 82C53 functions are selected by a control word from the CPU In the required program sequence the control word setting is followed by the count value setting and execution of the desired timer operation Control Word and Count Value Program Each counter operation mode is set by control word programming The control word format is out lined below D7 06 D5 D4 D3 02 D DO ser sco mr mo wo eco Select Read Load ME CONSE Count
54. al programming language The LabVIEW Data Acquisition VI Library a series of VIs for using LabVIEW with National Instruments DAQ hardware is included with LabVIEW The LabVIEW Data Acquisition VI Library is functionally equivalent to the NI DAQ software LabWindows CVI features interactive graphics a state of the art user interface and uses the ANSI standard C programming language The LabWindows CVI Data Acquisition Library a series of functions for using LabWindows CVI with National Instruments DAQ hardware is 1 2 National Instruments Corporation Chapter 1 Introduction included with the NI DAQ software kit The LabWindows CVI Data Acquisition Library is functionally equivalent to the NI DAQ software Using LabVIEW or LabWindows CVI software will greatly reduce the development time for your data acquisition and control application NI DAQ Driver Software The NI DAQ driver software is included at no charge with all National Instruments DAQ hardware NI DAQ is not packaged with signal conditioning or accessory products NI DAQ has an extensive library of functions that you can call from your application programming environment These functions include routines for analog input A D conversion buffered data acquisition high speed A D conversion analog output D A conversion waveform generation timed D A conversion digital I O counter timer operations SCXI RTSI calibration messaging and acquiring data to extended mem
55. ame National Instruments Corporation Figure C 1 PC LPM 16 Parts Locator Diagram PC LPM 16 PnP User Manual Appendix C Using Your PC LPM 16 Non PnP Board Base 1 0 Address Selection The base I O address for the PC LPM 16 is determined by the switches at position U26 see Figure C 2 The switches are set at the factory for the base I O address hex 260 This factory setting is used as the default base I O address value by National Instruments software packages for use with the PC LPM 16 The PC LPM 16 uses the base I O address space hex 260 through 26F with the factory setting See Table C 2 for the board factory settings Table C 2 PC Bus Interface Factory Settings PC LPM 16 Board Default Settings Hardware Implementation Base I O Address Hex 260 U26 Interrupt Level Interrupt level 5 W3 Row 5 selected factory setting Analog Input Bipolar input W1 B C selected 5 V W2 B C factory setting Verify that this base I O address space is not already used by other equipment installed in your computer Note If any equipment in your computer already uses this base I O address space you must change the base I O address of the PC LPM 16 or of the other device PC LPM 16 PnP User Manual If you change the PC LPM 16 base I O address you must make a corresponding change to any software packages you use with the PC LPM 16 For more information about the I O address
56. ample interval counter of A D conversion Write and read operations to the MSM82C53 are 8 bit operations For general programming details refer to Appendix B MSM82C53 Data Sheet PC LPM 16 PnP User Manual D 36 National Instruments Corporation Appendix Customer Communication For your convenience this appendix contains forms to help you gather the information necessary to help us solve your technical problems and a form you can use to comment on the product documentation When you contact us we need the information on the Technical Support Form and the configuration form if your manual contains one about your system configuration to answer your questions as quickly as possible National Instruments has technical assistance through electronic fax and telephone systems to quickly provide the information you need Our electronic services include a bulletin board service an FTP site a Fax on Demand system and e mail support If you have a hardware or software problem first try the electronic support systems If the information available on these systems does not answer your questions we offer fax and telephone support through our technical support centers which are staffed by applications engineers Electronic Services Bulletin Board Support National Instruments has BBS and FTP sites dedicated for 24 hour support with a collection of files and documents to answer most common customer questions From these sites you
57. any of the six operation modes of the MSM82C53 and the counting mode binary or BCD The Counter Mode Register is an 8 bit register Bit descriptions for each of these bits are included in Appendix B M M62C53 Data Sheet Address Base address OB hex Type Write only Word Size 8 bit Bit Map 7 6 5 4 3 2 1 0 scl SC0 RL1 RLO M2 MI MO BCD Bit Name Description 7 6 SC lt 1 0 gt Counter Select Bits These bits select the counter on which the command operates SC1 SCO Operation 0 0 Select counter 1 0 1 Select counter 2 1 0 Select counter 3 1 1 Read back command National Instruments Corporation D 21 PC LPM 16 PnP User Manual Appendix D Register Level Programming Counter Mode Register Continued 5 4 RL lt 1 0 gt Read Write Select Bits These bits select data written to or read from a counter or these bits send a Counter Latch command RL1 RLO Operation 0 0 Counter Latch command 0 1 Read and write least significant byte only 1 0 Read and write most significant byte only 1 1 Read and write least significant byte then most significant byte The Counter Latch command latches the current count of the register selected by SC1 and SCO The next read from the selected counter returns the latched data PC LPM 16 PnP User Manual D 22 National Instruments Corporation Counter Mode Register AppendixD Register Level Pro
58. ar Register D 24 custom cables 1 5 to 1 6 customer communication xii E 1 to E 2 D D lt 7 0 gt bits Counter 0 Data Register D 19 Counter 1 Data Register D 20 Counter 2 Data Register D 20 Digital Input Register D 25 Digital Output Register D 24 D lt 15 8 gt bits D 16 data acquisition timing circuitry 3 6 to 3 7 block diagram 3 5 data acquisition rates 3 7 multichannel scanning data acquisition 3 7 single channel data acquisition 3 7 data acquisition timing connections 4 8 to 4 9 EXTCONV signal timing figure 4 9 DATAERR OVERFLOW bit D 11 DAVAIL bit A D interrupt programming D 35 analog input circuitry programming D 28 description D 12 DGND signal table 4 3 4 4 differential nonlinearity A 5 digital I O circuitry programming D 35 theory of operation 3 8 Digital I O Register Group Digital Input Register D 25 Digital Output Register D 24 overview D 24 register map D 2 digital I O signal connections 4 6 to 4 7 port connections figure 4 7 specifications and ratings 4 6 digital I O specifications A 2 to A 3 DIN lt 0 7 gt signal description table 4 3 PC LPM 16 PnP User Manual Index digital I O circuitry 3 8 programming digital I O circuitry D 35 DISABDAQ bit D 7 D 33 documentation conventions used in manual x xi National Instruments documentation xi xii organization of manual ix x related documentation xii DOUTS lt 0 7 gt signal description table 4 3 digi
59. be scanned where N can be 1 through 15 Also 0 through N can be scanned Programming scanned multiple A D conversions involves the same sequence of steps as single channel data acquisition operations except that the SCANEN bit is cleared in Command Register 1 When the SCANEN bit is cleared in Command Register 1 the analog channel select bits MA 3 0 select the highest numbered channel in the scan sequence For example if MA lt 3 0 gt is 0011 binary that is channel 3 is selected and the SCANEN bit is cleared and the D 34 National Instruments Corporation Appendix D Register Level Programming UP DOWN bit in Command Register 2 is cleared the software uses the following scan sequence channel 3 channel 2 channel 1 channel 0 channel 3 channel 2 channel 1 channel 0 channel 3 and so on Perform the following steps to select the analog input channel 1 Program the UP DOWN bit in Command Register 2 if the bit is not already set to the desired value Common Register 2 must always be programmed before Command Register 1 7C Note The UP function is not yet supported by NI DAQ NI DAQ will support the UP function in a future release 2 Write the configuration value indicating the highest channel number in the scan sequence to Command Register 1 You must set the SCANEN bit during this first write to Command Register 1 3 Write the same configuration value again to Command Register 1 The SCANEN bit howev
60. ber 609 5041CE The following are the standard ribbon cables 50 conductor 28 AWG stranded that can be used with these connectors Electronic Products Division 3M part number 3365 50 T amp B Ansley Corporation part number 171 50 Unpacking Your PC LPM 16 PnP board is shipped in an antistatic package to prevent electrostatic damage to the board Electrostatic discharge can damage several components on the board To avoid such damage in handling the board take the following precautions Ground yourself via a grounding strap or by holding a grounded object e Touch the antistatic package to a metal part of your computer chassis before removing the board from the package Remove the board from the package and inspect the board for loose components or any other sign of damage Notify National Instruments if the board appears damaged in any way Do not install a damaged board into your computer Never touch the exposed pins of connectors PC LPM 16 PnP User Manual 1 6 National Instruments Corporation Chapter Installation and Configuration This chapter describes the installation and configuration of the PC LPM 16PnP For information on installing and configuring the PC LPM 16 a non PnP board refer to Appendix C Using Your PC LPM 16 Non PnP Board Hardware Installation You can install the PC LPM 16PnP in any available expansion slot in your computer The following are general installa
61. blished process procedure or equipment used to monitor or safeguard human health and safety in medical or clinical treatment Table of Contents About This Manual Organization of This Manual cre iter cie e t ent ix Conventions Used in This Manual sese enne enne x National Instruments Documentation esses eene xi Related Documentation ercsi re ee eriein iee xii Customer Communication u xii Chapter 1 Introduction About the PC LPM 10 PnP ecce teens cti deren rendere et onere cea Guss 1 1 What You Need to Get Started esses eene 1 2 Software Programming Choices n nee 1 2 LabVIEW and LabWindows CVI Application Software 1 2 NI DAQ Driver Software ener enne enne enne 1 3 Register Level PrOPr mminB nenne 1 4 Optional Equipment u n ea ea phe Ne ette recede t e op dina 1 5 Custom Cables e teer ete ee aree eren reve co ee me eet 1 5 Unpacking quy nere kit AiG EPOD DR bn ep itp 1 6 Chapter 2 Installation and Configuration Hardware Installation 2 ehe tetro tee pn 2 1 Software Installation t et eer RR UO e ERREUR 2 2 Board Configuration n rrt i e ere i ee ERO D ri tete de itc e shoes 2 2 Plug nd Playc S AF et ea
62. clude the configuration forms from their user manuals Include additional pages if necessary Name Company Address Fax Phone Computer brand Model Processor Operating system include version number Clock speed MHz RAM MB Display adapter Mouse yes no Other adapters installed Hard disk capacity MB Brand Instruments used National Instruments hardware product model Revision Configuration National Instruments software product Version Configuration The problem is List any error messages The following steps reproduce the problem PC LPM 16 PnP Hardware and Software Configuration Form Record the settings and revisions of your hardware and software on the line to the right of each item Complete a new copy of this form each time you revise your software or hardware configuration and use this form as a reference for your current configuration Completing this form accurately before contacting National Instruments for technical support helps our applications engineers answer your questions more efficiently National Instruments Products DAQ hardware Interrupt level of hardware DMA channels of hardware Base I O address of hardware Programming choice NI DAQ LabVIEW or LabWindows CVI version Other boards in system Base I O address of other boards DMA channels of other boards
63. computer Timing Connections PC LPM 16 PnP User Manual Pins 38 through 48 of the I O connector are connections for timing I O signals The timing input and output of the PC LPM 16PnP is designed around an MSM82C53 counter timer integrated circuit All three counters of the circuit are available at the I O connector One of these counters counter 0 is used for data acquisition timing Pin 39 carries an external signal that can be used for data acquisition timing in place of counter 0 Pins 38 and 41 through 48 carry general purpose timing signals These signals are explained in the General Purpose Timing Signal Connections and General Purpose Counter Timing Signals section later in this chapter Data Acquisition Timing Connections Counter 0 on the MSM82C53 counter timer is used as a sample interval counter in timed A D conversions In addition to counter 0 EXTCONV can externally time conversions See Appendix D Register Level Programming for the programming sequence needed to enable this input Figure 4 4 shows the timing requirements for the EXTCONV input An A D conversion is initiated by a rising edge on the EXTCONV The data from this conversion is latched into the FIFO memory within 20 us The EXTCONV input is a TTL compatible signal 4 8 National Instruments Corporation Chapter 4 Signal Connections EXTCONV VIH tint 20 us min tint A D interval A D Conversion Starts within 800 ns of this Edge
64. cquisition sample interval is too small sample rate is too high If OVERRUN is set one or more conversions was skipped If OVERRUN is cleared no overrun condition has occurred To clear this bit write to the A D Clear Register D 13 PC LPM 16 PnP User Manual Appendix D Register Level Programming Analog Input Register Group The three registers that make up the Analog Input Register Group control the analog input circuitry and can be used to read the FIFO Reading the FIFO Register returns stored A D conversion results Writing to the A D Clear Register clears the data acquisition circuitry Bit descriptions for the registers making up the Analog Input Register Group are given on the following pages PC LPM 16 PnP User Manual D 14 National Instruments Corporation Appendix D Register Level Programming A D FIFO Low Byte Register and A D FIFO High Byte Register 7 The 13 bit A D conversion results are sign extended to 16 bit data in two s complement format and are stored in a 16 word deep A D FIFO buffer Two 8 bit registers the A D FIFO Low Byte Register and the A D FIFO High Byte Register must be read to return an A D conversion value stored in the A D FIFO The A D FIFO Low Byte Register which must be read first contains the low byte of the 16 bit value and the A D FIFO High Byte Register contains the high byte of the 16 bit value Note The A D FIFO Low Byte Register MUST be read first The value read is
65. d The frequency of the input signal then equals the count value divided by the gate period Figure 4 6 shows the connections for a frequency measurement application You could also use a second counter to generate the gate signal in this application CLK TED e GAE Counter T ENG Connector PC LPM 16PnP Figure 4 6 Frequency Measurement Application 4 7 kQ resistors pull up the GATE and CLK pins to 5 V Figure 4 7 shows the timing requirements for the GATE and CLK input signals and the timing specifications for the OUT output signals The following specifications and ratings apply to the 5 82 53 I O signals e Absolute maximum voltage input rating 0 5 to 7 0 V with respect to DGND National Instruments Corporation 4 11 PC LPM 16 PnP User Manual Chapter 4 Signal Connections MSMS82C53 digital input specifications referenced to DGND Viqr input logic high voltage Vj input logic low voltage Input load current 2 2 V min 0 8 V max 10 0 LA max MSMS82C53 digital output specifications referenced to DGND Voy output logic high voltage Voy output logic low voltage output source current at Voy oj output sink current at VoL 3 7 V min 0 45 V max 1 0 mA max 4 0 mA max clock period clock high level clock lowlevel gate setup time
66. de n er EAE HARE PEE ns 2 2 Base I O Address and Interrupt Selection sss 2 3 i eR re E SERERE EUER 2 3 Chapter 3 Theory of Operation Functional Overview 2 antonio eb chs p 3 1 PC I O Channel Interface Circuitry eese enne ene 3 3 Analog Input and Data Acquisition 3 4 National Instruments Corporation V PC LPM 16 PnP User Manual Table of Contents Analog Anput CYrcuity u e RA tete lee e hls 3 5 Data Acquisition Timing Circuitry oe eee ene 3 6 Single Channel Data Acquisition 3 7 Multichannel Scanning Data Acquisition eese 3 7 Data Acquisition Rates teet et teet ees 3 7 Digital D O Cure untty neto tono nero EDIDI GORDON Oben 3 8 Timne VO CITCUIL soca seg ses eme Rosa ha ire Per nee eer 3 9 Chapter 4 Signal Connections s 4 1 Signal Connection Descriptions u u unus yn ia eene nennen enne nnns 4 3 Analog Input Signal Connections 4 5 Connections for Signal Sources a 4 5 Digital I O Signal Connections nunana 4 6 Power Connecti nS ptr e te te itt tipi E 4 7 Power R ting ei eh Ie e eta a bia ma 4
67. digital logic and for generating interrupts You can use the counter timers to synchronize events generate pulses and measure frequency and time The PC LPM 16 PnP used in conjunction with your computer is a versatile cost effective platform for laboratory test measurement and control National Instruments Corporation 1 1 PC LPM 16 PnP User Manual Chapter 1 Introduction What You Need to Get Started To set up and use your PC LPM 16 PnP board you will need the following 1 PC LPM 16 PnP board LJ PC LPM 16 PnP User Manual L One of the following software packages and documentation NI DAQ for PC Compatibles LabVIEW for Windows LabWindows CVI for Windows Your computer Software Programming Choices There are several options to choose from when programming your National Instruments DAQ and SCXI hardware You can use LabVIEW LabWindows CVI NI DAQ or register level programming LabVIEW and LabWindows CVI Application Software PC LPM 16 PnP User Manual LabVIEW and LabWindows CVI are innovative program development software packages for data acquisition and control applications LabVIEW uses graphical programming whereas LabWindows CVI enhances traditional programming languages Both packages include extensive libraries for data acquisition instrument control data analysis and graphical data presentation LabVIEW features interactive graphics a state of the art user interface and a powerful graphic
68. e low byte of 16 bit data and the second reading returns the high byte Reading the Low and High Byte A D FIFO Registers removes the A D conversion result from the A D FIFO The DAVAIL bit indicates whether one or more A D conversion results are stored in the A D FIFO If the DAVAIL bit is cleared the A D FIFO is empty and reading the A D FIFO Register returns meaningless data When an A D conversion is initiated the DAVAIL bit should be set after 20 us If you use EXTCONV for A D timing the DAVAIL bit should be set 20 us after a rising edge in EXTCONV An A D FIFO overflow condition occurs if you initiate more than 256 conversions and store them in the A D FIFO before reading the A D FIFO Register If this condition occurs the OVERFLOW bit is set in the Status Register 2 to indicate that one or more A D conversion results have been lost because of FIFO overflow Write to the A D Clear Register to reset this error flag PC LPM 16 PnP User Manual D 28 National Instruments Corporation Appendix D Register Level Programming A D FIFO Output Binary Modes The A D conversion result stored in the A D FIFO is a 16 bit two s complement value It is made of 13 bit magnitude and 3 bit sign extension If the analog input range is unipolar 0 to 10 V or unipolar 0 to 5 V use the positive values only making the resolution 12 bit If the analog input range is 5 V or 2 5 V you can divide the result by two to yield a 12 bit resolution read
69. ead the A D FIFO Low Byte Register first then read the A D FIFO High Byte Register to get the result Interrupts can also be used to service the data acquisition operation This topic is discussed under A D Interrupt Programming later in this appendix An overflow error condition may occur during a data acquisition operation This error condition is reported through the Status Register and the OVERFLOW bit should be checked every time the Status Register is read to check the DA VAIL bit An overflow condition occurs if more than 256 A D conversions have been stored in the A D FIFO since the A D FIFO was last read that is the A D FIFO is full and cannot accept any more data This condition occurs if the software loop reading the A D FIFO Register is not fast enough to keep up with the A D conversion rate When an overflow occurs you lose at least one A D conversion result An overflow condition has occurred if you clear the OVERFLOW bit in the Status Register Reset the OVERFLOW bit in the Status Register by writing to the A D Clear Register Programming Multiple A D Conversions with Channel Scanning PC LPM 16 PnP User Manual The data acquisition programming sequences given earlier in this appendix are for programming the PC LPM 16PnP for multiple A D conversions on a single input channel You can also program the PC LPM 16 PnP for scanning analog input channels during the data acquisition operation Analog channels N through 0 can
70. ence D 28 theory of operation 3 5 to 3 6 National Instruments Corporation 1 1 Index analog input Jumper settings PC LPM 16 C 10 to C 12 bipolar input selection 1 5 V C 10 to C 11 bipolar input selection 2 2 5 V C 11 unipolar input selection 1 0 to 10 V C 11 unipolar input selection 2 0 to 5 V C 12 Analog Input Register Group A D Clear Register D 17 A D FIFO Low Byte Register and A D FIFO High Byte Register D 15 to D 16 overview D 14 register map D 1 analog input signal connections 4 5 to 4 6 connections for signal sources 4 5 to 4 6 exceeding input signal range warning 4 5 input ranges and maximum ratings for lt 0 15 gt 4 5 pins 4 5 analog input specifications A 1 to A 2 ADC errors figure A 6 amplifier characteristics 2 differential nonlinearity A 5 dynamic characteristics A 2 explanation A 4 to A 6 input characteristics A 1 integral nonlinearity A 5 relative accuracy A 4 to A 5 stability A 2 system noise A 5 transfer characteristics A 1 to A 2 analog to digiter converter ADC 3 5 ARNG I 0 bits D 9 PC LPM 16 PnP User Manual Index base I O address selection PC LPM 16 C 5 to C 9 example switch settings figure C 7 PC bus interface factory settings table C 6 switch settings with corresponding base I O address table C 8 to C 9 PC LPM 16PnP 2 3 BCD bits D 23 bipolar input selection 1 5 V C 10 to C 11 bipolar input selection 2 2 5 V
71. er CS 0 1 1 1 CD BCD RD 1 WR 0 Select Counter SCO SC1 Selection of set counter ESEJE o caumar pommin coina scion 3 e I INNEN e Read Load RL1 RLO Count value Reading Loading format setting Counter Latch operation lt Latch operation Reading Loading of Least Significant byte LSB Reading Loading of Most Significant byte MSB Reading Loading of LSB followed by MSB B 8 ae o o o 0 omom counersowrting ENENKNENNENEEEK TI DI NENNEN Data bus from counter 0 Reading Data bus from counter 1 Reading Data bus from counter 2 Reading Data bus in high impedance status e Mode M2 M1 MO setting mea on Terminal Cou 1 Moss 1 iProgramnabio _ o ae Geneon 1 Moe 3 waw Geri x o Mose 4 Software v 9 1 Mose 5 Herder Sel x denotes not specified Operation waveform mode BCD Operation count mode setting ES Binary Count 16 bits Binary BCD Count 4 decades Binary Coded Decimal After setting Read Load Mode and BCD in each counter as outlined above next set the desired count value in some Modes counting is started immediately after the count value has been written This count
72. er must be cleared during the second write to Command Register 1 Use either counter 0 or EXTCONV to control the scanning interval A D Interrupt Programming You can use an interrupt to service the data acquisition operation To use the conversion interrupt set the FIFOINTEN bit in Command Register 1 If this bit is set an interrupt is generated whenever the DAVAIL bit in the Status Register is set Clear this interrupt condition by reading the FIFO which empties its contents Programming the Digital 1 0 Circuitry DINO through DIN7 pins 22 through 29 of the I O connector are dedicated digital input lines They are monitored by the Digital Input Register An 8 bit reading of the Digital Input Register returns the current state of these digital input lines DOUTO through DOUT7 pins 30 through 37 of the I O connector are dedicated digital output lines These lines are always driven by the Digital Output Register An 8 bit writing to the Digital Output Register drives the new digital value to these lines At startup all of the digital output lines are initiated to zero state National Instruments Corporation D 35 PC LPM 16 PnP User Manual Appendix D Register Level Programming Programming the MSM82C53 Counter Timer Counters 0 1 and 2 of the MSM82C53 counter timer except the signal of counter 1 are available for general purpose timing applications Counter 0 has a fixed 1 MHz clock input and can be used as the s
73. example ACH lt 0 7 gt stands for ACHO through ACH7 Bold text denotes menus menu items or dialog box buttons or options and error messages Bold italic text denotes a note caution or warning Italic text denotes emphasis a cross reference or an introduction to a key concept Text in this font denotes text or characters that are to be literally input from the keyboard sections of code programming examples and syntax examples This font is also used for the proper names of disk drives paths directories programs subprograms subroutines device names functions operations variables filenames and extensions and for statements and comments taken from program code NI DAQ refers to the NI DAQ software for PC compatibles unless otherwise noted x National Instruments Corporation About This Manual Non PnP Non PnP non Plug and Play means that the board requires you to manually configure the product s base address and interrupt level with switches and jumpers You must perform this configuration before installing the board into your computer PC PC refers to the IBM PC XT PC AT Personal System 2 Models 25 and 30 and laptop compatible computers PC LPM 16 PnP PC LPM 16 PnP refers to both the Plug and Play and the non Plug and Play versions of the board PC LPM 16PnP PC LPM 16PnP refers to the Plug and Play version of the board PC LPM 16 PC LPM 16 refers to the non Plug and Play version of the board Pn
74. fully observe the polarity to avoid shorting the signal source output National Instruments Corporation 4 5 PC LPM 16 PnP User Manual Chapter4 Signal Connections ACH lt 0 15 gt Signal Source Operational E Amplifier 9 Measured Input Multiplexer Voltage PC LPM 16PnP 2 AIGND AUN Connector Figure 4 2 Analog Input Signal Connections Digital 1 0 Signal Connections See Table 4 1 for the digital I O pin descriptions The following specifications and ratings apply to the digital I O lines Absolute maximum 7 0 V with respect to DGND voltage input rating 0 5 V with respect to DGND Digital input compatibility TTL compatible Input current high or low level 10 HA e Digital output compatibility TTL compatible Output current source capability 8 mA at Vog 2 7 V Output current sink capability 6 mA at Vor 0 5 V PC LPM 16 PnP User Manual 4 6 National Instruments Corporation Chapter 4 Signal Connections gt 22 DIN 0 Digital TTL Signal Input 29 DIN 7 45V lt w x Debounced um Port 19 NV Digital Output Port 30 DOUT 0 I O Connector PC LPM 16PnP Complex switch circuitry is not shown here in order to simplify the figure Figure 4 3 Analog Input Signal Connections Figure 4 3 shows the connections of t
75. g diode least significant bit meter megabytes of memory most significant bit personal computer random access memory root mean square seconds samples scan clock signal Signal Conditioning eXtensions for Instrumentation SI counter clock signal start scan signal G 4 National Instruments Corporation TTL VDC VI VIH VIL VOH VOL National Instruments Corporation transistor transistor logic volts volts direct current virtual instrument volts input high volts input low volts in volts output high volts output low G 5 Glossary PC LPM 16 PnP User Manual Numbers 5 V signal table 4 4 12 V signal table 4 3 12 V signal table 4 3 A ACH lt 0 15 gt signal description table 4 3 input ranges and maximum ratings 4 5 A D calibration programming D 27 A D Clear Register D 17 A D FIFO clearing D 30 output binary modes D 29 to D 30 bipolar input mode A D conversion values table D 30 unipolar input mode A D conversion values table D 29 overflow condition D 28 D 32 D 34 theory of operation 3 5 A D FIFO High Byte Register D 15 to D 16 A D FIFO Low Byte Register D 15 to D 16 A D interrupt programming D 35 ADC analog to digiter converter 3 5 ADC errors figure A 6 AIGND signal table 4 3 analog input circuitry block diagram 3 4 programming D 27 A D FIFO output binary modes D 29 to D 30 clearing the circuitry D 30 programming sequ
76. gramming Continued 3 1 M 2 0 0 BCD National Instruments Corporation Counter Mode Select Bits These bits select the counting mode of the selected counter The following table lists six available modes and the corresponding bit settings Refer to Appendix B M M82C53 Data Sheet for additional information M2 1 MO Mode 0 0 0 Mode 0 Interrupt on terminal count 0 0 1 Mode 1 Hardware retriggerable one shot 0 1 0 Mode 2 Rate generator 0 1 1 Mode 3 Square wave mode 1 0 0 Mode 4 Software retriggerable strobe 1 0 1 Mode 5 Hardware retriggerable strobe Binary Coded Decimal Select Bit If BCD is set the selected counter keeps count in BCD If BCD is cleared the selected counter keeps count in 16 bit binary D 23 PC LPM 16 PnP User Manual Appendix D Register Level Programming Timer Interrupt Clear Register Write to the Timer Interrupt Clear Register to clear the interrupt request asserted when a low pulse is detected on the counter 2 output Address Base address 06 hex Type Write only Word Size 8 bit Bit Map Not applicable no bits used Digital 1 0 Register Group The Digital I O Register Group contains two registers the Digital Output Register and the Digital Input Register The Digital Output Register drives the eight digital output lines of the I O connector The Digital Input Register returns the digital state of the eight digital inpu
77. hat is the A D FIFO is full and cannot accept any more data This condition occurs if the software loop reading the A D FIFO Register is not fast enough to keep up with the A D conversion rate When an overflow occurs at least one A D conversion result is lost An overflow condition has occurred if the OVERFLOW bit in the Status Register is set Clear the OVERFLOW bit in the Status Register by writing to the A D Clear Register To stop the A D conversion sequence write 34 to the Counter 0 Mode Register This stops the generation of pulses on OUTO D 32 National Instruments Corporation Appendix D Register Level Programming Programming Multiple A D Conversions Using External Timing You can use the external timing signal EXTCONV for multiple A D conversions A low to high transition of EXTCONV initiates an A D conversion Software can also initiate a data acquisition operation Setting the DISABDAQ bit in Command Register 2 disables the EXTCONV signal Clearing the DISABDAQ bit in Command Register 2 enables the EXTCONV signal and starts the data acquisition operation To use the EXTCONV signal the OUTO of counter 0 must be driven high Otherwise EXTCONV is disabled Each of these programming steps is explained as follows l National Instruments Corporation Disable the A D conversion Writing 2 to Command Register 2 to set the DISABDAQ bit disables the A D conversion The pulse on the EXTCONV line is ignored
78. he individual register description includes the address type word size and bit map of the register The register bit map shows a diagram of the register with the MSB bit 7 for an 8 bit register shown on the left and the LSB bit 0 shown on the right Each bit is represented by a square with the bit name inside An asterisk after the bit name indicates that the bit is inverted negative logic In many of the registers several bits are labeled with an X indicating don t care bits When reading a register these bits may appear set or cleared but should be ignored because they have no significance When writing to a register setting or clearing these bit locations has no effect on the PC LPM 16PnP hardware Take special note of the bits labeled reserved for future use The board may not function if you don t write the designated value to these register bits The bit map field for some write only registers states not applicable no bits used Writing to these registers causes an event to occur on the PC LPM 16PnP such as clearing the analog input circuitry The data is ignored when writing to these registers therefore any bit pattern will suffice For a detailed bit description of each register concerning the MSM82C53 chip on the PC LPM 16 PnP refer to Appendix B MSM82C53 Data Sheet Configuration and Status Register Group The three registers making up the Configuration and Status Register Group allow general control a
79. he Digital Input Register or the Digital Output Register respectively Reading the Digital Input Register returns the current state of the DIN lt 0 7 gt lines Writing to the Digital Output Register drives the new value onto the DOUT lt 0 7 gt lines The external device may drive the EXTINT signal to indicate the readiness of data transfer Digital Input Register Digital Output Register c 1 lt O A Status Register 1 Plug and Play Interrupt Figure 3 4 Digital 1 0 Circuitry Block Diagram PC LPM 16 PnP User Manual 3 8 Interface EXTINT Connector DIN lt 0 7 gt DOUT lt 0 7 gt National Instruments Corporation Chapter3 Theory of Operation Timing 1 0 Circuitry The PC LPM 16PnP uses an MSM82C53 Counter Timer integrated circuit for data acquisition timing and for general purpose timing I O functions Three counters on the circuit are available for general use but the board can use only one of them counter 0 internally for data acquisition timing Figure 3 5 shows a block diagram of both groups of timing I O circuitry A D Conversion Logic P dis OUTO c c lt OUTO GATEO 1 MHz Clock 8 M CLK1 GATE1 OUT1 CTR RD WR LL GATE0 CLK1 GATE1 OUT1 OUT1 CLK2 GATE2 OUT2 MSM82C53
80. he digital input port and digital output port Digital input applications include receiving TTL signals and sensing external device states such as the switch in Figure 4 3 Digital output applications include sending TTL signals and driving external devices such as the LED shown in Figure 4 3 Power Connections Pin 49 of the I O connector supplies 5 V from the computer I O channel power supply Pin 20 of the I O connector supplies 12 V from the computer I O channel power supply The 12 V is supplied from the computer I O power supply with a resistor in series These pins are referenced to DGND and can be used to power external digital circuitry The 5 V supply at the I O connector has a 1 0 A protection fuse in series The 12 V supply at the I O connector has a 0 5 A protection National Instruments Corporation 4 7 PC LPM 16 PnP User Manual Chapter 4 Signal Connections Power Rating fuse in series Both fuses are self resetting simply remove the circuit causing the heavy current load and the fuse will reset itself The following table shows the maximum current for each power line at the I O connector Power Line Maximum Current 5 V self resetting fuse at 1 0 A 1 0A 12 V self resetting fuse at 0 5 A 0 5 A 12V 5 0 mA The actual current available from these signals may be less depending on your computer Notice also that any current drawn from these lines adds to the power requirements from the
81. he self calibration cycle write 0 to Command Register 2 to enable the A D conversion The ADC should be calibrated after the reference has stabilized although you may recalibrate it later to adjust to changes over time or temperature Programming the Analog Input Circuitry This section describes the analog input circuitry programming sequence and explains the A D conversion results and how to clear the analog input circuitry National Instruments Corporation D 27 PC LPM 16 PnP User Manual Appendix D Register Level Programming Analog Input Circuitry Programming Sequence 1 Initiate an A D conversion A low to high transition on OUTO or on EXTCONV initiates A D conversion Clear the CALEN bit in Command Register 2 to enable counter 0 and the EXTCONV When an A D conversion is initiated the ADC stores the result in the A D FIFO at the end of its conversion cycle If EXTCONV initiates the conversion OUTO must be set high 2 Read the A D conversion result Read the A D FIFO Register to get the A D conversion results Before you read the A D FIFO however you must read the Status Register to determine whether the A D FIFO contains any results To read the A D conversion results complete the following steps Read the Status Register 8 bit read b Ifthe DAVAIL bit is set bit 0 read the A D FIFO Low Byte Register first then read the A D FIFO High Byte Register to get the result The first reading returns th
82. ignal Connections GATE Debounced Switch Counter PC LPM 16 PnP User Manual yo Connector PC LPM 16PnP Complex switch circuitry is not shown here in order to simplify the figure Figure 4 5 Event Counting Application with External Switch Gating Perform pulse width measurement by level gating to trigger the counter Apply the pulse to be measured to the counter GATE input Load the counter with the known count and program it to count down while the signal at the GATE input is high The pulse width equals the counter difference loaded value minus read value multiplied by the CLK period For time lapse measurement program a counter to be edge gated Apply an edge to the counter GATE input to start the counter You can program the counter to start counting after receiving a low to high edge The time lapse since receiving the edge equals the counter value difference loaded value minus read value multiplied by the CLK period For frequency measurement program a counter to be level gated and count the number of falling edges in a signal applied to a CLK input The gate signal you apply to the counter GATE input is of known 4 10 National Instruments Corporation Chapter 4 Signal Connections duration In this case program the counter to count falling edges at the CLK input while the gate is applie
83. ing Also if you want the full 13 bit resolution can be used with the bipolar ranges Notice however that in Appendix A Specifications LSB refers to the least significant bit of a 12 bit conversion value Table D 2 shows input voltage versus A D conversion values for the 0 to 10 V input range Table D 3 shows input voltage versus A D conversion values for 5 to 5 V input range Table D 2 Unipolar Input Mode A D Conversion Values Input Voltage A D Conversion Result Range 0 to 10 V Decimal Hex 0 0 0000 2 5 1 024 0400 5 0 2 048 0800 7 5 3 072 0C00 9 9976 4 095 National Instruments Corporation D 29 PC LPM 16 PnP User Manual Appendix D Register Level Programming Table D 3 Bipolar Input Mode A D Conversion Values Input Voltage A D Conversion Result A D Conversion Result Range 5 to 5 V Divided by 2 13 bit values 12 bit values Decimal Hex Decimal Hex 5 0 4 096 F000 2 048 F800 2 5 2 048 F800 1 024 FC00 0 0 0000 0 0000 2 5 2 048 0800 1 024 0400 4 9976 4 095 OFFF 2 047 07 Clearing the Analog Input Write to the A D Clear Register to clear the analog input circuitry which leaves the analog input circuitry in the following state Analog input error flag OVERFLOW is cleared Pending interrupt requests are cleared To empty the A D FIFO before starting any A D conversions perform two 8 bit read
84. ing the PC LPM 16 PnP K gt Note If you plan to use a programming software package such as NI DAQ LabVIEW or LabWindows CVI with your PC LPM 16 PnP you need not read this appendix Base Address For information on the base address see Chapter 2 Installation and Configuration Register Map The register map for the PC LPM 16 PnP is given in Table D 1 This table gives the register name the register address offset from the board s base address the type of the register read only write only or read and write and the size of the register in bits Table 0 1 PC LPM 16 PnP Register Map Register Name Offset Address Type Size Hex Configuration and Status Register Group Command Register 1 0 Write only 8 bit Command Register 2 7 Read and write 8 bit Command Register 3 3 Write only 8 bit Status Register 1 0 Read only 8 bit Status Register 2 1 Read only 8 bit Analog Input Register Group A D FIFO Low Byte Register 2 Read only 8 bit A D FIFO High Byte Register 3 Read only 8 bit A D Clear Register 1 Write only 8 bit National Instruments Corporation D 1 PC LPM 16 PnP User Manual Appendix D Register Level Programming Table 0 1 PC LPM 16 PnP Register Map Continued Register Name Offset Address Type Size Hex Counter Timer MSM82C53 Register Group Counter 0 Data Register 8 Read and write 8 bit Counter 1 Data Register 9 Read and write 8 bit Counter 2 Data Registe
85. ion with External Switch Gating 4 10 Figure 4 6 Frequency Measurement Application sse 4 11 Figure 4 7 General Purpose Timing Signals sse 4 12 Figure Al ADCO Errors eem edm dde me des A 6 Figure C 1 PC LPM 16 Parts Locator Diagram see C 5 Figure C 2 Example Base I O Address Switch Settings sss C 7 Figure C 3 Interrupt Jumper Setting IRQ5 Factory Setting ss C 10 Figure C 4 Interrupt Jumper Setting for Disabling Interrupts C 10 Figure C 5 Bipolar Input 5 V Jumper Configuration Factory Setting C 11 Figure C 6 Bipolar Input 2 5 V Jumper Configuration a C 11 Figure C 7 Unipolar Input 0 to 10 V Jumper Configuration C 11 National Instruments Corporation Vii PC LPM 16 PnP User Manual Table of Contents Tables Table 4 1 Signal Connection Descriptions 4 3 Table C 1 Comparison of Characteristics esee C 1 Table C 2 PC Bus Interface Factory Settings essere C 7 Table C 3 Switch Settings with Corresponding Base I O Address and Base I O Address Space esee C 9 Table D 1 PC LPM 16 PnP Register Map eee eene D 1 Table D 2 Unipolar Input Mode A D Conversion Values
86. ite to and read from the various registers on the board The following programming instructions are language independent that is they tell you to write a value to a given register to set or clear a bit in a given register or to detect whether a given bit is set or cleared without presenting the actual code Register Programming Considerations The PC LPM 16 PnP can only be used for 8 bit I O transfers so all the I O read and write operations are 8 bit operations Several write only registers on the PC LPM 16 PnP contain bits that control several independent pieces of the onboard circuitry In the set or clear instructions provided you should set or clear specific register bits without changing the current state of the remaining bits in the register However writing to these registers affects all register bits simultaneously You cannot read these registers to determine which bits have been set or cleared in the past therefore you should maintain a software copy of the write only registers You can then read this software copy to determine the status of the write only registers To change the state of a single bit without disturbing the remaining bits set or clear the bit in the software copy and then write the software copy to the register Initializing the PC LPM 16 PnP PC LPM 16 PnP User Manual You must initialize the PC LPM 16 PnP hardware for the circuitry to operate properly To initialize the PC LPM 16 PnP hardware complete
87. ke input and output signal connections to your PC LPM 16PnP board via the I O connector 1 0 Connector Figure 4 1 shows the pin assignments for the PC LPM 16PnP I O connector This connector is located on the back panel of the board and is accessible from the back of your computer after you have properly installed the board Installation instructions are in Chapter 2 Installation and Configuration Warning Connections that exceed any of the maximum ratings of input or output signals on the PC LPM 16PnP can damage the board and the computer This includes connecting any power signals to ground and vice versa Each signal description in this section includes information about maximum input ratings National Instruments is NOT liable for any damages resulting from any such signal connections National Instruments Corporation 4 1 PC LPM 16 PnP User Manual Chapter4 Signal Connections AIGND AIGND ACHO ACH8 ACH1 ACH9 ACH2 ACH10 ACH3 ACH11 ACH4 ACH12 ACH5 ACH13 ACH6 ACH14 ACH7 ACH15 DGND 12V 12 V DIN0 DIN1 DIN2 DIN3 DIN4 DIN5 DIN6 DIN7 DOUTO DOUT1 DOUT2 DOUT3 DOUT4 DOUT5 DOUT6 DOUT7 OUT1 EXTINT EXTCONV OUTO GATEO OUT1 GATE1 CLK1 OUT2 GATE2 CLK2 45V DGND Figure 4 1 PC LPM 16PnP 1 0 Connector Pin Assignments PC LPM 16 PnP User Manual 4 2 National Instruments Corporation Signal Connection Descriptions Chapte
88. l I O signal pins and timing I O signal pins Signal connection guidelines for each of these groups follow Analog Input Signal Connections Pins 3 through 18 are analog input signal pins for the ADC Pins 1 and 2 are analog common signals You can use these pins for a general analog power ground tie to the PC LPM 16PnP Pins 3 through 18 are tied to the 16 single ended analog input channels of the input multiplexer through 4 7 kQ series resistors These resistors limit input current to the multiplexer Pin 40 triggers conversions slightly after this signal makes alow to high transition You can only use this pin to cause conversions not as a monitor to detect conversions caused by the onboard sample interval timer Refer to Figure 4 4 for more information about EXTCONV timing The following input ranges and maximum ratings apply to inputs ACH lt 0 15 gt Input signal range Bipolar input 5 or 2 5 V Unipolar input 0 to 10 V or 0 to5 V Maximum input voltage rating 45 V powered on 35 V powered off Warning Exceeding the input signal range even on unused analog input channels distorts other input signals Exceeding the maximum input voltage rating can damage your board and the computer National Instruments is NOT liable for any damages resulting from such signal connections Connections for Signal Sources Figure 4 2 shows how to connect a signal source to your PC LPM 16PnP When you connect grounded signal sources care
89. l Programming The final option for programming any National Instruments DAQ hardware is to write register level software Writing register level programming software can be very time consuming and inefficient and is not recommended for most users Even if you are an experienced register level programmer consider using NI DAQ LabVIEW or LabWindows CVI to program your National Instruments DAQ hardware Using the NI DAQ LabVIEW or LabWindows CVI software is as easy and as flexible as register level programming and can save weeks of development time PC LPM 16 PnP User Manual 1 4 National Instruments Corporation Chapter 1 Introduction Optional Equipment National Instruments offers a variety of products to use with your PC LPM 16 PnP board including cables connector blocks and other accessories as follows e Cables and cable assemblies shielded and ribbon Connector blocks shielded and unshielded with 50 pin screw terminals SCXI modules and accessories for isolating amplifying exciting and multiplexing signals for relays and analog output With SCXI you can condition and acquire up to 3 072 channels Low channel count signal conditioning modules boards and accessories including conditioning for strain gauges and RTDs simultaneous sample and hold circuitry and relays For more specific information about these products refer to your National Instruments catalogue or call the office nearest you Custom
90. lug and Play PC LPM 16 board refer to Appendix C Using Your PC LPM 16 Non PnP Board 2 3 PC LPM 16 PnP User Manual Chapter Theory of Operation This chapter includes an overview of the PC LPM 16PnP board and explains the operation of each functionalunit making up the board This chapter also explains the basic operation of the PC LPM 16PnP circuitry Functional Overview The following are the major components making up the PC LPM 16PnP e PC I O channel interface circuitry Analog input and data acquisition circuitry Digital I O circuitry Timing I O circuitry You can execute data acquisition functions by using the analog input circuitry and some of the timing I O circuitry The internal data and control buses interconnect the components The theory of operation for each of these components is explained in the remainder of this chapter The block diagram in Figure 3 1 shows a functional overview of the PC LPM 16PnP National Instruments Corporation 3 1 PC LPM 16 PnP User Manual Chapter3 Theory of Operation PC I O Channel Interface 256 Word FIFO 12 Bit Sampling ADC Y Plug and Play PC I O Channel MSM82C53 Input Mux 16 Channel Single Ended A Scanning Counter EXTCONV A D Timing GATE lt 0 2 gt 3 4 CLK lt 1 2 gt 2 OUT lt 0 2 gt 3
91. ming 0 DAVAIL Data Available Bit This bit indicates whether conversion output is available If this bit is set the ADC is finished with the last conversion and the result can be read from the FIFO This bit is cleared if the FIFO is empty Writing to the ADCLR Register sets this bit on the PC LPM 16 only You need a FIFO low and high bytes reading to completely empty the PC LPM 16 FIFO On the PC LPM 16PnP the DAVAIL bit always exactly represents whether data is in the FIFO PC LPM 16 PnP User Manual D 12 National Instruments Corporation Status Register 2 Appendix D Register Level Programming Status Register 2 contains supplementary error information This register is only on the PC LPM 16PnP Address Ol hex Type Read only Word Size 8 bit Bit Map 6 5 3 2 1 0 X X X X OVERFLOW OVERRUN Bit Name Description 7 2 x Don t care bits 1 OVERFLOW Overflow Bit This bit indicates if an overflow error has occurred If this bit is cleared no error was encountered If this bit is set the A D FIFO has overflowed because the data acquisition servicing operation could not keep up with the sampling rate To clear this bit write to the A D Clear Register 0 OVERRUN Overrun Bit This bit indicates whether an A D National Instruments Corporation conversion was initiated before the previous A D conversion was complete OVERRUN is an error condition that will occur if the data a
92. much more useful Differential nonlinearity is a measure of deviation of code widths from their theoretical value of 1 LSB The width of a given code is the size of the range of analog values that can be input to produce that code ideally 1 LSB A specification of 1 LSB differential nonlinearity ensures that no code has a width of 0 LSBs that is no missing codes and that no code width exceeds 2 LSBs System noise is the amount of noise seen by the ADC when there is no signal present at the input of the board The amount of noise that is reported directly without any analysis by the ADC is not necessarily the amount of real noise present in the system unless the noise is 20 5 LSB rms Noise that is less than this magnitude produces varying amounts of flicker and the amount of flicker seen is a function of how near the real mean of the noise is to a code transition If the mean is near or at a transition between codes the ADC flickers evenly between the two codes and the noise is seen as very nearly 0 5 LSB If the mean is near the center of a code and the noise is relatively small very little or no flicker is seen and the noise is reported by the ADC as nearly 0 LSB From the relationship between the mean of the noise and the measured rms magnitude of the noise the character of the noise can be determined National Instruments has determined that the character of the noise in the PC LPM 16PnP is fairly Gaussian so the noise specificati
93. n PC LPM 16 PnP User Manual About This Manual installation and configuration instructions specification information about your DAQ hardware and application hints Software documentation Examples of software documentation you may have are the LabVIEW LabWindows CVI documentation sets and the NI DAQ documentation After you set up your hardware system use either the application software LabVIEW or LabWindows CVI or the NI DAQ documentation to help you write your application If you have a large complicated system it is worthwhile to look through the software documentation before you configure your hardware Accessory installation guides or manuals If you are using accessory products read the terminal block and cable assembly installation guides They explain how to physically connect the relevant pieces of the system Consult these guides when you are making your connections SCXI Chassis User Manual If you are using SCXI read this manual for maintenance information on the chassis and for installation instructions Related Documentation The following document contains information that you may find helpful as you read this manual Your computer user or technical reference manual Customer Communication PC LPM 16 PnP User Manual National Instruments wants to receive your comments on our products and manuals We are interested in the applications you develop with our products and we want to help if you
94. n extended two s complement result of a 13 bit A D conversion Values made up of D lt 15 0 gt therefore range from 4096 to 4095 decimal F000 to OFFF hex Two s complement mode is useful for bipolar analog input readings because the values read reflect the polarity of the input signal In unipolar mode only the positive value is used Low Byte 7 0 D lt 7 0 gt A D Conversion Data Bits 7 through 0 These bits contain the low byte of the 16 bit sign extended two s complement result of a 12 bit A D conversion Note The ADC resolution is actually 13 bits not 12 bits NI DAQ only returns a 12 bit value and the PC LPM 16 PnP boards are tested only to 12 bit accuracy However by writing register level programming you can use the full 13 bits The ADC always returns values from 4 096 to 4 095 For unipolar mode if you want 12 bit resolution instead of 13 bit you should ignore any negative value giving a range of 0 to 4 095 For bipolar mode you can divide the value returned by the ADC by two giving a range of 2 048 to 2 047 Refer to the A D FIFO Output Binary Modes section in this appendix for more information about 13 and 12 bit conversions PC LPM 16 PnP User Manual D 16 National Instruments Corporation Appendix D Register Level Programming A D Clear Register Write to this register to reset the ADC This operation clears the data FIFO All error bits in the Status Register are cleared as well For the PC LPM 1
95. nd monitoring of the PC LPM 16 PnP A D circuitry Command Register 1 and Command Register 2 contain bits that control the operation modes of the A D circuitry and enable or disable the interrupt operations Command Register 3 sets the board input range The Status Register reports the A D conversion status A D conversion error and the interrupt status Bit descriptions for the registers in the Configuration and Status Register Group are given on the following pages National Instruments Corporation D 3 PC LPM 16 PnP User Manual Appendix D Register Level Programming Command Register 1 Command Register 1 indicates the input channel to be read and the interrupt enable bits Address Base address 00 hex Type Write only Word Size 8 bit Bit Map 7 6 5 4 3 2 1 0 SCANEN CNTINTEN EXTINTEN FIFOINTEN MA3 MA2 MAI MAO Bit Name Description 7 SCANEN Scan Enable Bit This bit enables or disables PC LPM 16 PnP User Manual multichannel scanning during data acquisition The power on value is 1 If this bit is cleared analog channels MA 3 0 through 0 are sampled alternately If this bit is set a single analog channel selected by MA 3 0 is sampled during the entire data acquisition operation In order to perform single channel sampling the UP DOWN bit in Command Register 2 must be clear before setting SCANEN to 1 To set up a scanning mode two consecutive writings of this register are necessary First write the
96. of your computer refer to your computer s technical reference manual C 6 National Instruments Corporation AppendixC Using Your PC LPM 16 Non PnP Board Each switch in U26 corresponds to one of the address lines A9 through 5 Slide the switch to the side labeled A9 to 5 to select a binary value of zero for the corresponding address bit Slide the switch to the side of the switch labeled ON to select a binary value of one for the corresponding address bit Figure C 2 shows two possible switch settings Slide to this side for 0 A Slide to this side for 1 Slide to this side for 0 Slide to this side for 1 b Switches Set to Base I O Address of Hex 260 Factory Setting Figure C 2 Example Base 1 0 Address Switch Settings The PC LPM 16 decodes the five LSBs of the address A4 through AO to select the appropriate PC LPM 16 register To change the base I O address 1 Remove the plastic cover on U26 2 Slide each switch to the desired position 3 Checkeachswitch to verify that the switch is pressed entirely to the side 4 Replace the plastic cover Note the new PC LPM 16 base I O address for use when configuring the PC LPM 16 software in the Hardware and Software Configuration Form in Appendix E Customer Communication Table C 3 lists the National Instruments Corporation C 7 PC LPM 16 PnP User Manual Appendix C Using Your 1 16 Non
97. onable control Under the copyright laws this publication may not be reproduced or transmitted in any form electronic or mechanical including photocopying recording storing in an information retrieval system or translating in whole or in part without the prior written consent of National Instruments Corporation LabVIEW NI DAQ DAQ STC and SCXI are trademarks of National Instruments Corporation Product and company names listed are trademarks or trade names of their respective companies WARNING REGARDING MEDICAL AND CLINICAL USE OF NATIONAL INSTRUMENTS PRODUCTS National Instruments products are not designed with components and testing intended to ensure a level of reliability suitable for use in treatment and diagnosis of humans Applications of National Instruments products involving medical or clinical treatment can create a potential for accidental injury caused by product failure or by errors on the part of the user or application designer Any use or application of National Instruments products for or involving medical or clinical treatment must be performed by properly trained and qualified medical personnel and all traditional medical safeguards equipment and procedures that are appropriate in the particular situation to prevent serious injury or death should always continue to be used when National Instruments products are being used National Instruments products are NOT intended to be a substitute for any form of esta
98. ons given are the amounts of pure Gaussian noise required to produce our readings National Instruments Corporation A 5 PC LPM 16 PnP User Manual Appendix A Specifications To illustrate these definitions Figure A 1 shows a portion of the analog input to digital output transfer curve for an ideal ADC overlaid on the transfer curve of a hypothetical typical ADC As shown in Figure A 1 the relative accuracy is the deviation of the code transition voltage from the center of the code for an ideal ADC expressed in terms of LSBs Notice that in this case an ideal ADC has a relative accuracy of 1 2 LSB because this definition of relative accuracy encompasses both nonlinearity and quantization uncertainties Integral nonlinearity is the worst case deviation of the center of the code from the ideal center expressed in terms of LSBs Finally the differential nonlinearity is deviation of a code width from ideal code width expressed in terms of LSBs Output Code LSB Input Voltage LSBs KEY Practical ADC analog input to digital output curve Ideal ADC analog input to digital output curve Cigeai Center of code1 for ideal ADC actual Center of code1 for practical ADC INL error INLe Cactual Cideal Relative Accuracy Maximum Rel Re2 DNL error Vacuar Vigeai Figure A 1 ADC Errors PC LPM 16 PnP User Manual A 6 National Instruments Corporation Appendix MSM82C53 Data Sheet
99. ory NI DAQ has both high level DAQ I O functions for maximum ease of use and low level DAQ I O functions for maximum flexibility and performance Examples of high level functions are streaming data to disk or acquiring a certain number of data points An example of a low level function is writing directly to registers on the DAQ device NI DAQ does not sacrifice the performance of National Instruments DAQ devices because it lets multiple devices operate at their peak performance NI DAQ also internally addresses many of the complex issues between the computer and the DAQ hardware such as programming interrupts and DMA controllers NI DAQ maintains a consistent software interface among its different versions so that you can change platforms with minimal modifications to your code Whether you are using conventional programming languages LabVIEW or LabWindows CVI your application uses the NI DAQ driver software as illustrated in Figure 1 1 National Instruments Corporation 1 3 PC LPM 16 PnP User Manual Chapter 1 Introduction Conventional Programming Environment PC Macintosh or Sun SPARCstation LabVIEW LabWindows CVI PC Macintosh or PC or Sun Sun SPARCstation SPARCstation NI DAQ Driver Software Personal Computer or Workstation DAQ or SCXI Hardware Figure 1 1 The Relationship between the Programming Environment NI DAQ and Your Hardware Register Leve
100. ply Nonresettable Self resetting Self resetting Fuses 12 V Supply Power 15 mA typ 15 mA typ Requirements Performance Specification Changes INL 1 LSB max 0 5 LSB max 0 5 LSB max Gain Error 2 8 V or 3 LSB typ 2 LSB typ 2 LSB typ to 10 V Range 7 LSB max 4 LSB max 4 LSB max Calibration Time 700 us typ 10 ms typ 10 ms typ Overvoltage 45 V 35 V 35 V Protection or Analog Input Powered Off PC LPM 16 PnP User Manual C 2 National Instruments Corporation Table C 1 Appendix C Using Your PC LPM 16 Non PnP Board Comparison of Characteristics Continued Functional Changes Legacy PC LPM 16 Revised PC LPM 16 PC LPM 16PnP Interrupt Enable Disable Control Delay Between Rising EXTCONV Edge and A D Conversion Through Command Register 1 2 4 us Through Command Register 1 800 ns max Through Plug and Play BIOS or NI DAQ Configuration Utility 800 ns max To determine which PC LPM 16 board you have refer to the Assembly Number row in Table C 1 and compare it to the assembly number displayed on your circuit board see Figure C 1 National Instruments Corporation C 3 PC LPM 16 PnP User Manual Appendix C Using Your PC LPM 16 Non PnP Board Configuration and Installation of the PC LPM 16 non PnP Board Configuration The PC LPM 16 contains three jumpers and one DIP switch to configure the PC bus interface and analog input settings Use the
101. power on value is 0 When this bit is set the external interrupt is enabled The external device that asserts this signal is responsible for keeping EXTINT low until the interrupt is acknowledged and is then responsible for releasing it EXTINT is pulled up to 5 V on the board First In First Out Interrupt Enable Bit This bit enables and disables the interrupt generation when A D conversion results are available The power on value is 0 If FIFOINTEN is set an interrupt is generated whenever an A D conversion can be read from the FIFO Channel Select Bits 3 through 0 These four bits select which of the 16 input channels are read The power on value is 0000 The analog input multiplexer depends on these four bits to select the input channel The input channel is selected as follows MA lt 3 0 gt Selected Channel 0000 0 0001 1 0010 2 0011 3 D 5 PC LPM 16 PnP User Manual Appendix D Register Level Programming Command Register 1 Continued PC LPM 16 PnP User Manual MA lt 3 0 gt Selected Channel 0100 4 0101 5 0110 6 0111 jj 1000 8 1001 9 1010 10 1011 11 1100 12 1101 13 1110 14 1111 15 If SCANEN is cleared analog channels MA lt 3 0 gt through channel 0 are sampled Sampling order whether from channel 0 to MA lt 3 0 gt or from MA lt 3 0 gt to channel 0 is determined by the SCANORDER bit in Command Register 2 If
102. r A Read and write 8 bit Counter Mode Register B Write only 8 bit Timer Interrupt Clear Register 6 Write only 8 bit Digital I O Register Group Digital Output Register 4 Write only 8 bit Digital Input Register 3 Read only 8 bit PC LPM 16PnP only Register Size The PC LPM 16 PnP registers are 8 bit registers To transfer 16 bit data you need two consecutive I O read or write operations For example to read the 16 bit A D conversion result read the low byte of FIFO first then the high byte of FIFO Register Descriptions Table D 1 divides the PC LPM 16 PnP registers into four different register groups A bit description of each of the registers making up these groups is included later in this appendix The Configuration and Status Register Group controls the overall operation of the PC LPM 16 PnP and the D A circuitry The Analog Input Register Group reads output from the successive approximation ADC The Counter Timer Register Group accesses the onboard MSMS82C53 counter timer integrated circuit The Digital I O Register Group consists of the digital output and input registers PC LPM 16 PnP User Manual D 2 National Instruments Corporation Appendix D Register Level Programming Register Description Format The remainder of this appendix discusses each of the PC LPM 16 PnP registers in the order shown in Table D 1 Each register group is introduced followed by an individual register description T
103. r Manual Appendix A Specifications Bus Interface Power Requirement Note Physical Environment 5 VDC t1090 sse 50 mA typ 12 VDE CE5 96 ie te trt eet tette 15 mA typ 12 VDC 55496 sioe sheet 15 mA typ These numbers do not include an additional 1 A from the 5 V power supply The 50 pin I O connector can draw 0 5 A from the 12 V supply Dimensions rarse 11 0 by 9 9 cm 4 4 by 3 9 in C 0 nhector sii 50 pin D male ribbon cable connector Operating temperature 0 to 70 C Storage temperature 55 to 150 C Relative humidity 5 to 90 noncondensing Explanation of Analog Input Specifications Relative accuracy is a measure of the linearity of an ADC However relative accuracy is a tighter specification than a nonlinearity specification Relative accuracy indicates the maximum deviation from a straight line for the analog input to digital output transfer curve If a ADC has been calibrated perfectly then this straight line is the ideal transfer function and the relative accuracy specification indicates the worst deviation from the ideal that the ADC permits A relative accuracy specification of 1 LSB is roughly equivalent to but not the same as a 1 2 LSB nonlinearity or integral nonlinearity specification because relative accuracy encompasses both nonlinearity and variable quantization uncertainty
104. r4 Signal Connections Table 4 1 Signal Connection Descriptions Pin Signal Reference Description 1 2 AIGND lt 0 15 gt AGND Analog Input Ground The pins are connected to the analog input ground signal ACH lt 0 15 gt signals should be referenced to AIGND Analog Input Channels 0 through 15 These channels are single ended DGND N A Digital Ground This pin supplies the reference for the digital signals at the I O connector as well as the 5 VDC supply 20 12V DGND 12 VDC Power Supply Output Pin The maximum current is 5 0 mA 21 12 V DGND 12 VDC Power Supply from the Computer Bus This power line has a 0 5 A self resetting fuse in series 22 29 DIN lt 0 7 gt DGND Digital Input Data Lines These signals are TTL compatible digital input lines DIN7 is the MSB DINO the LSB 30 37 38 DOUT lt 0 7 gt OUTI DGND DGND Digital Output Data Lines These signals are TTL compatible digital output lines is the MSB DOUTO the LSB Output of Counter 1 This signal outputs the inverted programmed waveform of counter 1 39 EXTINT DGND External Interrupt This pin is used for input of the external interrupt signal National Instruments Corporation 4 3 PC LPM 16 PnP User Manual Chapter4 Signal Connections
105. rcuitry Chapter 4 Signal Connections describes how to make input and output signal connections to your PC LPM 16PnP board via the I O connector Appendix A Specifications lists the specifications of the PC LPM 16PnP Appendix B MSM82C53 Data Sheet contains a manufacturer data sheet for the MSM82C53 CMOS programmable interval timer OKI Semiconductor ix PC LPM 16 PnP User Manual About This Manual Appendix C Using Your PC LPM 16 Non PnP Board describes the differences between the PC LPM 16PnP and the PC LPM 16 non PnP boards the PC LPM 16 board configuration and installing the PC LPM 16 into your computer Appendix D Register Level Programming describes in detail information related to register level programming the PC LPM 16 PnP Appendix E Customer Communication contains forms you can use to request help from National Instruments or to comment on our products The Glossary contains an alphabetical list and description of terms used in this manual including abbreviations acronyms metric prefixes mnemonics and symbols The Index lists topics covered in this manual including the page number where the topic can be found Conventions Used in This Manual bold bold italic italic monospace NI DAQ PC LPM 16 PnP User Manual The following conventions are used in this manual Angle brackets containing numbers separated by an ellipsis represent a range signal or port for
106. removed from the A D FIFO thereby freeing space to store another A D conversion value The A D FIFO is empty after reading all the values it contains The Status Register should be checked before the A D FIFO Register is read If the A D FIFO contains one or more A D conversion values the DAVAIL bit is set in the Status Register and the external device can read the A D FIFO Register to retrieve a value If the DAVAIL bit is cleared the A D FIFO is empty in which case reading the A D FIFO Register returns meaningless information The values returned by reading the A D FIFO Registers are available in two s complement binary format When the analog input range is unipolar any small negative value returned from FIFO should be explained as zero Address A D FIFO Low Byte Register Base address 02 hex A D FIFO High Byte Register Base address 03 hex Type Read only Word Size 8 bit Bit Map Two s complement binary mode High Byte 6 5 4 3 2 1 0 D15 D14 D13 D12 D11 D10 D9 D8 Sign and Sign Extension Bits Low Byte T 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 DO National Instruments Corporation D 15 PC LPM 16 PnP User Manual Appendix D Register Level Programming A D FIFO Low Byte Register and A D FIFO High Byte Register Continued Bit Name Description High Byte 7 0 D lt 15 8 gt A D Conversion Data Bits 15 through 8 These bits contain the high byte of the 16 bit sig
107. rporation Description External Interrupt Status Bit This bit reflects the status of the EXTINT signal on the I O connector If the EXTINTEN bit in Command Register 1 is set and this bit is cleared the external EXTINT signal has caused the current interrupt When the interrupt caused by the EXTINT signal is served your external device should drive EXTINT to inactive state logic high or undrive it Counter Interrupt Bit This bit reflects the interrupt status caused by the counter 2 output signal If the CNTINTEN bit in Command Register 3 is set a low to high transition on counter 2 output sets this bit and generates an interrupt request Clear this bit by writing to the CNTINTCLR Register Data Error Overflow Bit This bit indicates if an overflow or overrun error has occurred On the PC LPM 16PnP this bit 1s the data error bit If this bit is cleared no error was encountered If this bit is set the A D FIFO has overflowed because the data acquisition servicing operation could not keep up with the sampling rate or an A D conversion was initiated before the previous A D conversion was complete To distinguish between the overflow and overrun error conditions examine the OVERFLOW and OVERRUN bits in Status Register 2 Clear this bit by writing to the A D Clear Register On the PC LPM 16PnP this bit only indicates that an overflow has occurred D 11 PC LPM 16 PnP User Manual Appendix D Register Level Program
108. rs control the direction of data transfer on the bidirectional data lines based on whether the transfer is a read or write operation The interrupt control circuitry routes any enabled interrupts to the selected interrupt request line The PC LPM 16PnP has six interrupt 3 3 PC LPM 16 PnP User Manual Chapter3 Theory of Operation request lines available IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 and IRQ9 The PC LPM 16PnP generates interrupts in three different situations Whenan A D conversion generates data that can be read from FIFO e When an active low level signal is detected on the EXTINT line e When a rising edge signal is detected on counter 2 output The PC LPM 16PnP individually enables and clears each one of these interrupts For more detailed information on generating interrupts externally see the EXTINTEN bit of the Command Register 1 description in Appendix D Register Level Programming Analog Input and Data Acquisition Circuitry PC I O Channel PC LPM 16 PnP User Manual The PC LPM 16PnP has 16 channels of analog input with 12 bit A D conversion Using the timing circuitry the PC LPM 16PnP can also automatically time multiple A D conversions Figure 3 3 shows a block diagram of the analog input and data acquisition circuitry PC I O Channel FIFO Interface Input Mux 250 vord 16 Channel Single Ended 16 A D RD ACH lt 0 15 gt CONVAVAIL
109. rval count This operation continues until you reprogram the counter As stated in Appendix D Register Level Programming only counter 0 is required for data acquisition operations The software must keep track of the number of conversions that have occurred and turn off counter 0 after it receives the required number of conversions 3 6 National Instruments Corporation Chapter3 Theory of Operation Single Channel Data Acquisition During single channel data acquisition the channel select bits in Command Register select the analog input channel before data acquisition begins This multiplexer setting remains constant during the entire data acquisition process therefore all A D conversion data is read from a single channel Multichannel Scanning Data Acquisition Multichannel data acquisition is performed when you enable scanned data acquisition A scan counter on the board controls multichannel scanning For multichannel scanning operations the scan counter decrements from the highest channel which you select through channel 0 Thus the board can scan any number of channels from 2 to 16 Notice that the same analog input range is used for all channels in the scan sequence Data Acquisition Rates The maximum data acquisition rate number of samples per second is determined by the conversion period of the ADC plus the acquisition time of its track and hold stage During multichannel scanning the settling time of the input
110. s are suspected In no event shall National Instruments be liable for any damages arising out of or related to this document or the information contained in it EXCEPT AS SPECIFIED HEREIN NATIONAL INSTRUMENTS MAKES NO WARRANTIES EXPRESS OR IMPLIED AND SPECIFICALLY DISCLAIMS ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE CUSTOMER S RIGHT TO RECOVER DAMAGES CAUSED BY FAULT OR NEGLIGENCE ON THE PART OF NATIONAL INSTRUMENTS SHALL BE LIMITED TO THE AMOUNT THERETOFORE PAID BY THE CUSTOMER NATIONAL INSTRUMENTS WILL NOT BE LIABLE FOR DAMAGES RESULTING FROM LOSS OF DATA PROFITS USE OF PRODUCTS OR INCIDENTAL OR CONSEQUENTIAL DAMAGES EVEN IF ADVISED OF THE POSSIBILITY THEREOF This limitation of the liability of National Instruments will apply regardless of the form of action whether in contract or tort including negligence Any action against National Instruments must be brought within one year after the cause of action accrues National Instruments shall not be liable for any delay in performance due to causes beyond its reasonable control The warranty provided herein does not cover damages defects malfunctions or service failures caused by owner s failure to follow the National Instruments installation operation or maintenance instructions owner s modification of the product owner s abuse misuse or negligent acts and power failure or surges fire flood accident actions of third parties or other events outside reas
111. s bit is used to disable the data acquisition operation The power on value is 0 Upon startup this bit is cleared and as a result the data acquisition operation is enabled Writing a one to this bit disables both A D conversion source signals OUTO and EXTCONV D 7 PC LPM 16 PnP User Manual Appendix D Register Level Programming Command Register 2 Continued Bit Name Description 0 CALEN Calibration Enable Bit If this bit is set the auto calibration of the 12 bit ADC is enabled The power on value is 0 To start the auto calibration first write one to this bit then read this register The result of the reading is ignored An auto calibration lasts about 10 ms By checking the CONVPROG bit of the Status Register the completion of auto calibration can be detected After the auto calibration you must clear this bit for the A D conversion operation PC LPM 16 PnP User Manual D 8 National Instruments Corporation Appendix D Register Level Programming Command Register 3 Command Register 3 contains other range setting configuration bits Address 05 hex Type Write only Word Size 8 bit Bit Map 7 6 4 3 2 1 0 0 0 0 0 0 0 ARNG lt 1 gt ARNG lt 0 gt Bit Name Description 7 2 0 Reserved Bits These bits must be set to zero 1 0 ARNG lt 1 0 gt Analog Input Voltage Range These bits control the analog input voltage range setting as follows ARNG lt 1 0
112. s on the A D FIFO Registers and ignore the data read This operation guarantees that the A D conversion results read from the A D FIFO are from the initiated conversions rather than leftover results from previous conversions To clear the analog input circuitry and the A D FIFO e Write 0 to the A D Clear Register 8 bit write Programming Multiple A D Conversions on a Single Input Channel Using Counter 0 PC LPM 16 PnP User Manual This manual refers to a sequence of timed A D conversions as a data acquisition operation Counter 0 of 5 82 53 is used as the sample interval counter In a data acquisition operation counter 0 continuously generates the conversion pulses The software keeps track of the number of conversions that have occurred and turns off counter 0 D 30 National Instruments Corporation Appendix D Register Level Programming after getting the required number of conversions The number of conversions in a single data acquisition operation in this case is unlimited Counter 0 is clocked by a 1 MHz clock upon start up Each of these programming steps is explained as follows 1 National Instruments Corporation Select the Analog Input Channel Write to Command Register to select the analog input channel The SCANEN bit must be set for data acquisition operations on a single channel See the Command Register 1 bit descriptions earlier in this appendix for analog input channel bit patterns Write
113. signal table 4 4 OVERFLOW bit description D 13 register level programming D 28 D 32 D 34 OVERRUN bit D 13 P PC I O channel interface circuitry 3 3 to 3 4 block diagram 3 3 PC LPM 16 compared with PC LPM 16PnP C 1 to C 3 characteristics table C 1 to C 2 performance specification changes table C 2 to C 3 configuration See configuration installation C 12 PC LPM 16PnP See also theory of operation custom cables 1 5 to 1 6 features 1 1 optional equipment 1 5 requirements for getting started 1 2 software programming choices 1 2 to 1 4 LabVIEW and LabWindows CVI application software 1 2 to 1 3 NI DAQ driver software 1 3 to 1 4 register level programming 1 4 unpacking 1 6 physical specifications A 4 PC LPM 16 PnP User Manual Index Plug and Play compatibility 2 2 to 2 3 power connections 4 7 power rating table 4 8 power requirement specifications A 4 programming See register level programming pulse and square wave generation 4 9 pulse width measurement 4 10 R register level programming D 26 to D 36 See also registers A D calibration D 27 A D interrupt programming D 35 analog input circuitry D 27 A D FIFO output binary modes D 29 to D 30 clearing the circuitry D 30 programming sequence D 28 compared with application software 1 4 digital I O circuitry D 35 initializing PC LPM 16 PnP D 26 to D 27 MSM82C53 counter timer D 36 multiple A D conversions on single inp
114. sults You must do this after programming the counters in case any spurious edges were caused D 31 PC LPM 16 PnP User Manual Appendix D Register Level Programming PC LPM 16 PnP User Manual during the programming Write 0 to the A D Clear Register to empty the FIFO 8 bit write then read the low and high bytes from the A D FIFO PC LPM 16 only 4 Start and service the data acquisition operation To start the data acquisition operation write the most significant byte of the sample interval to the Counter 0 Data Register This enables counter 0 to start counting When the data acquisition operation starts service the operation by reading the A D FIFO Register every time an A D conversion result becomes available Perform the following sequence until you have read the desired number of conversion results a Read the Status Register 8 bit read b Ifthe DAVAIL bit is set bit 0 read the A D FIFO Register to get the result You can also use interrupts to service the data acquisition operation This topic is discussed in the A D Interrupt Programming section later in this appendix An overflow error condition may occur during a data acquisition operation This error condition is reported through the Status Register and the overflow should be checked every time the Status Register is read An overflow condition occurs if more than 256 A D conversions have been stored in the A D FIFO since the A D FIFO was last read t
115. t lines of the I O connector Bit descriptions for the register in the Digital I O Register Group follow Digital Output Register Write to the Digital Output Register to control the eight digital output lines of the I O connector The pattern contained in the Digital Output Register is driven onto the eight digital output lines of the I O connector Address Base address 04 hex Type Write only Word Size 8 bit Bit Map 7 6 5 4 3 2 1 0 D7 D6 DS D4 D3 D2 DI D0 Bit Name Description 7 0 D lt 7 0 gt 8 Bit Output Data 7 through 0 These eight bits control the digital output lines DOUT 0 through DOUT 7 PC LPM 16 PnP User Manual D 24 National Instruments Corporation Appendix D Register Level Programming Digital Input Register Read the Digital Input Register to return the logic state of the I O connector s eight digital input lines Address Base address 05 hex Type Read only Word Size 8 bit Bit Map 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 DI D0 Bit Name Description 7 0 D lt 7 0 gt 8 Bit Input Data Bit These eight bits represent the logic state of the digital input lines DIN 0 through DIN 7 National Instruments Corporation D 25 PC LPM 16 PnP User Manual Appendix D Register Level Programming Programming Considerations Following are programming instructions for operating the circuitry on the PC LPM 16 PnP To program the PC LPM 16 PnP you must wr
116. ta is obtained in both the 0 to 5 V signal range and the 0 to 5 V signal range while keeping the input configuration for 5 V input range The jumper configuration for the 0 to 5 V and 5 V input signal ranges is the same The software handles the distinction between the two ranges You can install the PC LPM 16 in any available 8 bit or 16 bit expansion slot in your computer To optimize the board noise performance install the board away from the video card and leave a slot vacant on each side of the PC LPM 16 if possible After you make any necessary changes with the jumper and switch settings you are ready to install the PC LPM 16 The following are general installation instructions but consult your computer user manual or technical reference manual for specific instructions and warnings 1 Turn off and unplug your computer 2 Remove the top cover or access port to the I O channel 3 Remove the expansion slot cover on the back panel of the computer 4 Insert the PC LPM 16 board into any 8 bit or 16 bit slot It may be a tight fit but do not force the board into place 5 Screw the mounting bracket of the PC LPM 16 board to the back panel rail of the computer Replace the cover Plug in and turn on your computer The PC LPM 16 is installed C 12 National Instruments Corporation Appendix Register Level Programming This appendix describes in detail information related to register level programm
117. tal I O circuitry 3 8 programming digital I O circuitry D 35 E electronic support services 1 to E 2 e mail support E 2 environment specifications A 4 equipment optional 1 5 event counting 4 9 to 4 10 with external switch gating figure 4 10 EXTCONV signal data acquisition timing circuitry 3 6 data acquisition timing figure 4 9 description table 4 4 programming multiple A D conversions D 33 to D 34 EXTINT bit D 11 EXTINT signal description table 4 3 digital I O circuitry 3 8 EXTINTEN bit D 5 F fax and telephone support E 2 FaxBack support E 2 FIFOINTEN bit D 5 D 35 frequency measurement 4 10 to 4 11 FTP support E 1 fuse self resetting table 4 8 PC LPM 16 PnP User Manual 1 4 G GATE signal counter block diagram 3 10 general purpose timing and counter timing 4 9 to 4 12 timing requirements for GATE and CLK input signals 4 11 to 4 12 GATE signal table 4 4 GATE signal table 4 4 GATE2 signal table 4 4 general purpose timing and counter timing 4 9 to 4 12 event counting 4 9 to 4 10 frequency measurement 4 10 to 4 11 pulse and square wave generation 4 9 pulse width measurement 4 10 specifications and ratings for MSM82C53 T O signals 4 11 to 4 12 time lapse measurement 4 10 timing requirements for GATE and CLK input signals 4 11 to 4 12 timing specifications for OUT output signals 4 11 to 4 12 H hardware installation 2 1 initializing PC LPM 16 Pn
118. tatic operation MSM82C53 2RS Three independent 16 bit down counters 28 pin Plastic QFJ28 P S450 3V to 6V single power supply MSMB82C53 2J8 932 pin V Plastic SOP SSOP32 P 430 VK MSM82C53 2GS VK FUNCTIONAL BLOCK DIAGRAM COUNTER COUNTER COUNTER 0 1 2 INTERNAL BUS 8 DATA CONTROL BUS WORD BUFFER REGISTER H S 165 PC LPM 16 PnP User Manual B 2 National Instruments Corporation Appendix B MSM82C53 Data Sheet a O MSM82C53 2RS GS JS PIN CONFIGURATION Top View 24 pin Plastic DIP 32 pin Plastic SOP NC denotes connected 28 Plastic 166 National Instruments Corporation B 3 PC LPM 16 PnP User Manual Appendix B PC LPM 16 PnP User Manual B 4 National Instruments Corporation 5 82 53 Data Sheet 1 O MSM82C53 2RS GS JS Limits Parameter ABSOLUTE MAXIMUM RATINGS MSM82C53 2JS input Voltage Respect to GND 0 5 to Veg 0 5 Output Voltage ae 0 5 to Vec 0 5 Temperature i 55 to 150 MSMB2C53 2RS MSM82C53 2GS Ssupply Voltage OPERATING RANGES Supply Voltage 3to6 Vit 0 2V Vin Voc 0 2V frequency 2 6 MHz Operating Temperature 40 to 85 RECOMMENDED OPERATING CONDITIONS Supply Voltage ee lt _ ee DC CHARACTERISTICS Parameter Symbol Conditions Min Typ Max Unit
119. te boundary Therefore valid addresses include 100 110 120 FFE0 FFF0 hex This selection is software configured and does not require you to manually change any settings on the board The PC LPM 16PnP can use interrupt channels 3 4 5 6 7 and 9 There are different ways to assign the base address to your board For Windows 95 the base address and interrupt should be set automatically However if you want to view or change these settings you can set the board resources using the Device Manager Windows 95 will automatically allocate resources but these can be changed in the Device Manager a Click the right mouse button My Computer to bring up system properties b Select Device Manager c Select Data Acquisition Devices d Select the PC LPM 16 You can change address and interrupt settings on the Resources page For Windows 3 10 3 11 you can use the NI DAQ Configuration Utility formerly WDAQCONF to assign the board resources If a standard configuration utility is present in the system you will not be able to modify the board resources You can use a standard configuration utility like Intel ISA Configuration Utility ICU ICU dynamically assigns the base address to your board when you boot up the computer You can also lock the board resources when you use ICU For additional information on ICU contact Intel Corporation for a copy of Plug and Play Specification version 1 0a To configure the non P
120. tion instructions but consult your computer user manual or technical reference manual for specific instructions and warnings 1 Turn off and unplug your computer 2 Remove the top cover or access port to the I O channel 3 Remove the expansion slot cover on the back panel of the computer 4 Insert the PC LPM 16PnP board into any 8 bit or 16 bit slot It may be a tight fit but do not force the board into place 5 Screw the mounting bracket of the PC LPM 16PnP board to the back panel rail of the computer Replace the cover Plug in and turn on your computer The PC LPM 16PnP is installed National Instruments Corporation 2 1 PC LPM 16 PnP User Manual Chapter 2 Installation and Configuration Software Installation If you are using NI DAQ refer to your NI DAQ release notes to install your driver software Find the installation section for your operating system and follow the instructions given there If you are using LabVIEW refer to your LabVIEW release notes to install your application software After you have installed LabVIEW refer to the NI DAQ release notes and follow the instructions given there for your operating system and LabVIEW If you are using LabWindows CVI refer to your LabWindows CVI release notes to install your application software After you have installed LabWindows CVI refer to the NI DAQ release notes and follow the instructions given there for your operating system and LabWindows CVI
121. ut channel using Counter 0 D 30 to D 32 using external timing D 33 to D 34 with channel scanning D 34 to D 35 overview D 26 registers Analog Input Register Group A D Clear Register D 17 A D FIFO Low Byte Register and A D FIFO High Byte Register D 15 to D 16 overview D 14 Configuration and Status Register Group Command Register 1 D 4 to D 6 Command Register 2 D 7 to D 8 Command Register 3 D 9 PC LPM 16 PnP User Manual overview D 3 Status Register 1 D 10 to D 12 Status Register 2 D 13 Counter Timer MSM82C53 Register Group Counter 0 Data Register D 19 D 30 to D 32 Counter Data Register D 20 Counter 2 Data Register D 20 Counter Mode Register D 21 to D 23 overview D 18 programming D 36 Timer Interrupt Clear Register D 24 Digital I O Register Group Digital Input Register D 25 Digital Output Register D 24 overview D 24 register map D 1 to D 2 relative accuracy A 4 to A 5 REVID bit D 10 RL lt 1 0 gt bits D 22 S sample interval timer 3 6 SC lt 1 0 gt bits D 21 SCANEN bit description D 4 programming multiple A D conversions D 33 D 34 to D 35 SCANORDER bit D 7 signal connections analog input signal connections 4 5 to 4 6 connections for signal sources 4 5 to 4 6 digital I O signal connections 4 6 to 4 7 I O connector exceeding maximum ratings warning 4 1 pin assignments figure 4 2 power connections 4 7 to 4 8 National Instruments Corporation power rating table
122. value latched from counter 1 ni Counter 1 address B A Reading of MSB from counter MOV C A a B 12 O MSM82C53 2RS GS JS Example of Practical Application e 82C53 used as a 32 bit counter 82C53 2 CLK1 OUT Use counter 1 and counter 2 Counter 41 mode 0 upper order 16 bit counter value Counter 2 mode 2 lower order 16 bit counter value This setting enables counting up to a maximum of 232 175 National Instruments Corporation Using Your PC LPM 16 Non PnP Board Appendix This appendix describes the differences between the PC LPM 16PnP and the PC LPM 16 non PnP boards the PC LPM 16 board configuration and installing the PC LPM 16 into your computer Differences between the PC LPM 16PnP and the PC LPM 16 The PC LPM 16PnP is a Plug and Play upgrade from a legacy board the PC LPM 16 A National Instruments egacy product refers to an older board with switches and jumpers used to set the addresses The original board has been replaced with a backwards compatible revised PC LPM 16 This revised board has the same functionality as the Plug and Play version except for the base address and interrupt selection but differs somewhat from the legacy board The following list compares the specifications and functionality of the newer boards with the obsolete board Table C 1 Comparison of Characteristics Functional Changes Legacy PC LPM 16 Revised PC LPM 16 PC LP

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