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Intel STL2 User's Manual

1. rrrnrnnnnnrnnnnnrnnnnnnnannrrnnnnnrnnnnnnnennrnnnnnnrnnnnnnnennrnnnnnnnnnnne 2 5 1 1 2 Dual Processor Operation eseu ee AEN ENEE Nee 2 6 deltas PEASTO le in ae ne Arenas Aunt arnested antas de 2 6 1 1 4 Processor Bus Termination Regulation Power 2 6 1 1 5 KE lie Elei Re 2 6 1 16 APIC EE 2 6 1 47 ee EE 2 6 1 2 ServerWorks ServerSet III LE Chpeset ke 2 7 2 une Te a a PN ae Se EM ee a ee ee ee 2 7 1 4 PCO Subsystem E 2 8 1 4 1 64 bit 66 MHz PCI SUbsystemuasuusdnesamsemhkanismmedrendmd kennel 2 8 1 4 2 32 bit 33 MHz PCI Gubevestem keen 2 10 1 5 Chipset Support Components EE 2 15 1 5 1 Legacy I O Super I O National PC97317VUL rnnrrrrnnnnnnnnrnnnnnrrrrnnnnnnnnrrnnnnrrrnnnn 2 15 1 5 2 BIOS EAS EE 2 17 1 1 3 External Device Connectors se vssscctiecs ects vos ccst scoot ate aseaten on aets eee 2 17 1 6 Interrupt Fon EE 2 17 16 11 Defa lt OAPI vene 2 17 1 6 2 Extended Eeer 2 17 BN EE 2 20 1 6 4 Relationship between PCI IRQ and PCI Device cc cccceeeeeeeeeeeeeeeeeeeeeeeteeeenaaees 2 20 3 Server Management sudaletlslennenttleukmnledmeideeleimnnnesh je 3 23 3 1 Baseboard Management Controller cece cc ceeeeeeee eter ee eeeeeneeeeeeeeeeetececaaeeeeeeeeeeneee 3 23 Ee EE EE 3 24 OG EU EE eae songs Hato asta attend es el a tee ae Setet 3 27 34 IG AIK Mode 2 3 28 Revision 1 0 iii Table of Contents STL2 Server Board TPS 3 5 Wake Om LAN en EE 3 28 4 Basic Input Output System BIOS rrrnnnnnnnnnnnnnvvvnnnnnnnnnnnnnnnnn
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3. General purpose I O pins e Plug and Play functions e A power management controller The STL2 server board provides the connector interface for the floppy dual serial ports parallel port PS 2 mouse and the PS 2 keyboard Upon reset the SIO reads the values on strapping pins to determine the boot up address configuration Revision 1 0 2 15 STL2 Server Board Architecture Overview STL2 Server Board TPS 2 5 1 1 Serial Ports Two 9 pin connectors in D Sub housing are provided for serial port A and serial port B Both ports are compatible with 16550A and 16450 modes and both are re locatable Each serial port can be set to one of four different COM x ports and each can be enabled separately When enabled each port can be programmed to generate edge or level sensitive interrupts When disabled serial port interrupts are available to add in cards 2 5 1 2 Parallel Port The STL2 baseboard provides a 25 pin parallel port connector The SIO provides an IEEE 1284 compliant 25 pin bi directional parallel port BIOS programming of the SIO registers enables the parallel port and determines the port address and interrupt When disabled the interrupt is available to add in cards 2 5 1 3 Floppy Port The FDC in the SIO is functionally compatible with floppy disk controllers CMOS 765B and 82077AA The baseboard provides the 24 MHz clock termination resistors and chip selects All other FDC functions are integrated into the SIO including
4. Ignored after checking address parity Support for 8 bit transfers only for all registers in its device register space Support for 32 bit transfers only for the external ROM EEPROM Support for transfers from system memory Defaults to Memory Read Will respond to DAC if PCI Address matches the MBAR 63 12 RE OD NOE Revision 1 0 2 9 STL2 Server Board Architecture Overview STL2 Server Board TPS 7 Defaults to Memory Write The extensions to memory commands memory read multiple memory read line and memory write and invalidate work with the cache line size register to give the cache controller advance knowledge of the minimum amount of data to expect The decision to use either the memory read line or memory read multiple commands is determined by a bit in the configuration space command register for this device 2 4 1 1 2 SCSI Bus The SCSI data bus is 8 or 16 bits wide with odd parity generated per byte SCSI control signals are the same for either bus width To accommodate 8 bit devices on the 16 bit Wide SCSI connector the AIC 7899 assigns the highest arbitration priority to the low byte of the 16 bit word This way 16 bit targets can be mixed with 8 bit if the 8 bit devices are placed on the low data byte For 8 bit mode the unused high data byte is self terminated and does not need to be connected During chip power down all inputs are disabled to reduce power consumption 2 4 2 32 bit 33 MHz PCI Subsystem The 32
5. Jumpers and Connectors STL2 Server Board TPS Table 5 1 Jumper Block 1J15 Settings Jumper Pin Jumper Position What it does at system reset Numbers 1 CMOS clear Open Protect Preserves the contents of CMOS Closed Erase Clears CMOS Password protected Open Normal Preserves the password Closed Disable Disables the password 7 8 Reserved Open Not Used No function 9 10 BIOS Recovery Boot Open Normal BIOS Recovery Boot disabled Normal operation Closed Recovery Boot If this jumper is set BIOS recovery will be attempted from a bootable BIOS recovery floppy diskette 2 3 4 5 6 Open Not Used No function 7 8 11 12 Closed Spare Provides a spare jumper 5 1 1 1 Clearing and Changing a Password Clear and change a password as follows Power off the system unplug the power cord and remove the chassis panel N Use needle nose pliers or your fingers to remove the spare jumper from pins 11 12 on jumper block 1J15 Reinstall the jumper on pins 3 4 Password Disable of jumper block 1J15 Reinstall the chassis panel plug in the power cord s and power on the system While waiting for POST to complete press the F2 key to enter BIOS setup This automatically clears all passwords provided you save and exit the BIOS setup Power off the system unplug the power cord s and remove the chassis panel Remove the Password Disable jumper from pins 3 4 and store the jumper on pins 11 12 Replace the chassis pa
6. 3 28 STL2 Server Board TPS Basic Input Output System BIOS 4 Basic Input Output System BIOS This section describes BIOS embedded software for the STL2 board set The BIOS contains standard PC compatible basic input output I O services standard Intel server features plus the STL2 system specific hardware configuration routines and register default settings embedded in Flash read only memory ROM This section also describes BIOS support utilities not ROM resident that are required for system configuration and flash ROM update The BIOS is implemented as firmware that resides in the flash ROM Support for applicable baseboard peripheral devices SCSI NIC and video adapters which is also loaded into the baseboard flash ROM is not specified in this document Hooks are provided to support adding BIOS code for these adapters the binaries must be obtained from the peripheral device manufacturers and loaded into the appropriate locations 4 1 BIOS Overview The term BIOS as used in the context of this section refers to the system BIOS the BIOS Setup and option ROMs for on board peripheral devices that are contained in the system flash System BIOS controls basic system functionality using stored configuration values The terms flash ROM system flash and BIOS flash may be used interchangeably in this section The term BIOS Setup refers to the flash ROM resident setup utility that provides the user with control of configuration
7. Only Description System Memory XXX KB Display Only Indicates the total capacity of the basic memory Extended Memory XXXXXX KB Display Only Indicates the total capacity of the extended memory DIMM 1 Status Display Only PCI Device Po Refer to PCI Device Submenu DIMM 8 Status Display Only DIMM 4 Status Display Only Clear DIMM Errors Clears the DIMM group error status information DIMM Error Pause Enabled If enabled the POST operation pauses if a DIMM Disabled error occurs Note 1 Possible Values Normal None or Error DIMM Row Error Di DIMM 2 Status Display Only Di Di 4 36 STL2 Server Board TPS Basic Input Output System BIOS Table 4 7 Peripheral Configuration Submenu Selections Choices or Display Only Description Serial Port 1 COM 1 Disabled Disables serial port 1 or selects the base 3F8 IRQ3 address and interrupt IRQ for serial port 3F8 IRQ4 1 2F8 IRQ3 2F8 IRQ4 3E8 IRQ3 3E8 IRQ4 2E8 IRQ3 2E8 IRQ4 Auto Serial Port 2 COM 2 Disabled Disables serial port 2 or selects the base 3F8 IRQ3 address and interrupt IRQ for serial port 3F8 IRQ4 2 2F8 IRQ3 2F8 IRQ4 3E8 IRQ3 3E8 IRQ4 2E8 IRQ3 2E8 IRQ4 Auto Parallel Port Disabled Disables the parallel port or selects the 378 IRQ5 base address and interrupt IRQ for the 378 IRQ7 Parallel port 278 IRQ5 278 IRQ7 3BC IRQ5 3BC IRQ7 Auto Parallel Mode Output only Selects the parallel port operation
8. STL2 Server Board TPS Table 4 12 Secure Mode Submenu Selections Choices or Description Display Only Secure Mode Timer Disabled Period of keyboard and mouse inactivity before secure 1 Min mode is activated and a password is required gain 2 Min access 5 Min 10 min 30 min 1 hr 2 hr Secure Mode HotKey Disabled Enables Disables the ability to lock the system with a Enabled lt CTRL gt lt ALT gt lt key gt combination The key can be selected and submenu appears when enabled A password is required to gain access Secure Mode Boot Disabled Enables Disables secure boot The system will boot as Enabled normal but a password is required to access the system using any PS 2 device Floppy Write Protect Disabled Enables Disables floppy drive write protection If Enable enabled a password is required to write to a floppy 4 2 2 7 System Hardware Menu Selections Table 4 13 Server Menu Selections Choices or Description Display Only Wake On Events See Wake On Events submenu AC Link Power On Selects power retention mode if AC power is lost a Last State regained Stay Off Error Log Initialization Press Enter Select to clear the system Error Log If Clear OK then display System Event Log Cleared If Clear failed then display System Event Log Not Cleared Console Redirection linge cts See Console Redirection Submenu Assert NMI on PERR Disabled Enables PCI PERR support Enabled Table 4 14 Wake On
9. 1 0 4 31 Basic Input Output System BIOS STL2 Server Board TPS 4 2 2 1 Entering Setup Utility During POST operation the user is prompted to enter Setup using the F2 function key as follows Press lt F2 gt to enter Setup After the F2 key is pressed a few seconds might pass before Setup is entered while POST finishes test and initialization functions that must be completed before Setup can be entered When Setup is entered the Main Menu options page is displayed 4 2 2 2 Keyboard Command Bar The bottom portion of the screen provides a list of commands that are used for navigating the Setup utility These commands are displayed at all times for every menu and submenu Each Setup menu page contains a number of features Except those used for informative purposes each feature is associated with a value field This field contains user selectable parameters Depending on the security option chosen and in effect via password a menu feature s value can be changeable or not If a value is cannot be changed due to insufficient security privileges or other reasons the feature s value field is inaccessible The Keyboard Command Bar supports the following F1 Help Pressing F1 on any menu invokes the general Help window This window describes the Setup key legend The up arrow down arrow Page Up Page Down Home and End keys scroll the text in this window Enter Execute Command The Enter key is used to activate submenus when the
10. 2 SCSI Transfer Speeds cccciccescs cece ceeeiceeecdegect cedeteeeecbecuesstencanevanenveaveestetesede cose ENEE 2 9 Table 2 3 Embedded SCSI Supported PCI Commande urrrrrrrvrvrvvrvrrvrrrrrrrrrrrvrrrrrrrrrrrrrrrerenr 2 9 Table 2 4 Video Controller Supported PCI Commande rrnnnnvrrrnnnnnnnnnnnnnnrrrnnnnnnnnnnnnnnnrrnnnnn 2 13 Table 2 5 Standard VGA Modes scisvccssens Svcs cxsacccacadecawtendacacatadatved caaneadetabeasedcnancadstadaieedtacatans 2 13 Table 2 6 STL2 PGI IDS ersetze rege emnene kn EE REE deans eas eens Menuet veneers 2 20 Table 4 1 Setup Utility Screen eg cececenetsh scene eae EEN NEE SE EEEEENREEEEN SEENEN SEENEN 4 31 Table 4 2 Main Menu Selections ccccccccccccccceceeeeceeceeeeeceeeececceceeeeeceeeeeeeceseeeeeeeeeseeeeeeess 4 34 Table 4 3 Primary Master and Slave Adapters Submenu Selections rrrrnnnnnnnonnnnnvrrrnnnn 4 35 Table 4 4 Processor Settings Submenu Selections rrrrrrrnnnrrrrnnnnnnnnnnnnnnvrrnnnnnnnnnnnnnnvrrnnnnne 4 35 Table 4 5 Advanced Menu Selections nneneeeeeeeee eneee n ennnen nnen nnen n ennenen nennen 4 36 Table 4 6 Memory Reconfiruation Submenu Gelechons 4 36 Table 4 7 Peripheral Configuration Submenu Selections wrrrrrrrrrrrrrrrvrrrrrrrrrrrrrrrrrrrrrrrrren 4 37 Table 4 8 PCI Device Submenu Gelectons eneee eeen ennnen ennnen nenne nennen ennnen 4 38 Table 4 9 Option ROM Submenu Gelechons 4 38 Table 4 10 Numlock Submenu Selections eenen ennenen ennnen nennen 4
11. 2 1 ESTE EMGO SSG 8 86 8 2 2 Ensure Host Computer and Accessory Module Certifications xrrrrnnvrrrrnnnnnnnnrn 8 86 8 2 3 Prevent Power Supply Overload AEN 8 87 8 2 4 Place Battery Marking on Computer 8 87 8 2 5 Use Only for Intended Applications ke 8 88 8 2 6 Installation Precautions seed seat sce gsca ceases erg eaereciawlt pone a eraeawntaetd Sea peanut ae ba teenies 8 88 8 3 Environmental Limits EE 8 88 8 3 1 System Office Environment s uvvnvanruddsaneurekvanmahukentdiuikniitnde 8 88 8 3 2 System ENVirOnimentall TESTNG EE 8 89 Revision 1 0 v List of Figures STL2 Server Board TPS List of Figures Figure 1 1 Figure 2 1 Figure 2 2 Figure 2 3 Figure 2 4 Figure 5 1 Figure 5 2 Figure 5 3 Figure 5 4 vi STL2 Server Board Block Diagram NEE 1 3 Embedded NIC PCI Signals E 2 11 Video Controller POLSIGNAS Lun Eech EE deed eg 2 12 STL2 Baseboard Interrupt Routing Diagram PIC model 2 18 STL2 Baseboard Interrupt Routing Diagram Symmetric mode ssnssseesssseenee 2 19 STL2 Server Board Jumper and Connector Locations ssseseessseeserrreeeserrreee 5 61 I O Back Panel Connectors AEN 5 62 Diskette Drive Connector Pin Diagram rrrrnrnnnnnvrrrnnnnnnnnnnnnnnvrrrnnnnennnnrrnnnnrnnnnene 5 70 IDE Connector Pin Diagram WEE 5 74 STL2 Server Board TPS List of Tables List of Tables Table 2 1 STL2 Server Board Supported Processors rrrrrrrnnrrrrrnnnnnnnnrrnnnvrrrnnnnnnnrenrnnnnrrrnnnne 2 5 Table 2
12. Connectors I O Back Panel location key for Figure 5 1 Dom gt USB connectors Serial port 2 connector Serial port 1 connector NMI switch 5 62 STL2 Server Board TPS Jumpers and Connectors Parallel port connector Keyboard connector Mouse connector Video connector Network connector romm 5 1 Jumper Blocks Jumpers on several jumper blocks of the STL2 server board are used to set the system configuration The jumpers are small plastic encased conductors shorting plugs that slip over two jumper pins on a jumper block On the STL2 server board the following jumper blocks are user configurable The figure below shows the default settings for the STL2 jumper blocks e 1J15 CMOS and Password Clear e 5E1 Processor Frequency e 1L4 Configuration 6A Chassis Intrusion CMOS Password Clear Chassis Intrusion 8 Location 1J15 Location 6A 6 2 4 6 8 10 12 1 3 5 7 8 9 CPU Clock Frequency Location 5E1 Configuration Jumper Location 1L4 2 4 6 8 10 12 5 1 1 Setting CMOS Password Clear Jumper Block 1J15 Setting a jumper on system board jumper block 1J15 enables the user to clear the CMOS or to clear a forgotten password See the above figure for the location of the jumper block location The following table lists the factory default settings for jumper block 1J15 which are indicated in bold typeface Procedures for setting the jumper on the block follow the table Revision 1 0 5 63
13. Enables option ROM expansion for the on board LAN Disabled option ROM PCI Slot 1 Enabled Disables Enables the expansion of the option ROM for devices Disabled in PCI slot 1 PCI Slot 2 Enabled Disables Enables the expansion of the option ROM for devices Disabled in PCI slot 2 PCI Slot 3 Enabled Disables Enables the expansion of the option ROM for devices Disabled in PCI slot 3 PCI Slot 4 Enabled Disables Enables the expansion of the option ROM for devices Disabled in PCI slot 4 PCI Slot 5 Enabled Disables Enables the expansion of the option ROM for devices Disabled in PCI slot 5 PCI Slot 6 Enabled Disables Enables the expansion of the option ROM for devices Disabled in PCI slot 6 PCI Slot 7 Enabled Disables Enables the expansion of the option ROM for devices Disabled in PCI slot 7 Table 4 10 Numlock Submenu Selections Choices or Description Display Only Numlock Ca Selects the power on state for Numlock On Key Click Disabled Disables or enables keyclick Enabled 4 38 STL2 Server Board TPS Basic Input Output System BIOS Choices or Description Display Only Keyboard Auto repeat Rate 2 sec Selects key repeat rate 6 sec 10 sec 13 3 sec 18 5 sec 21 8 sec 26 7 sec 30 sec Keyboard Auto repeat Delay 0 25 sec Selects delay before key repeat 0 5 sec 0 75 sec 1 sec 4 2 2 6 Security Menu Selections Table 4 11 Security Menu Selections Choices or Description Display Only Supervisor Password is Clear D
14. Events Submenu Selections Choices or Description Display Only Wake On LAN Enabled Enables Disables Wake on LAN support Disabled Wake On Ring Enabled Enables Disables Wake on Ring support 4 40 STL2 Server Board TPS Basic Input Output System BIOS Table 4 15 Console Redirection Submenu Selections Serial Port Address Disabled If enabled the console will be redirected Serial Port 2 3F8h IRQ4 to this port Serial Port 2 2F8h IRQ3 If console redirection is enabled this address must match the settings of serial port 2 Baud Rate 57 6K Enables the specified baud rate 19 2K Flow Control No Flow Control Selects flow control XON OFF Console Connection Direct Indicate whether the console is connected Via Modem directly to the system or if a modem is used to connect 4 2 2 8 Boot Menu Selections Boot Menu options allow the user to select the boot device The following table is an example of a list of devices ordered in priority of the boot invocation Items can be re prioritized by using the up and down arrow keys to select the device Once the device is selected use the plus key to move the device higher in the boot priority list Use the minus key to move the device lower in the boot priority list Table 4 16 Boot Menu Selections Boot Time Diagnostic Screen Disabled Enabled Enable Disable boot time diagnostic screen Splash screen is displayed over the diagnostic screen when is option is
15. bit 33 MHz 5V keyed PCI includes the following embedded devices and connectors Four 32 bit 33 MHz 5V keyed PCI expansion slots Integrated Intel EtherExpress PRO100 10 100 megabit PCI Ethernet controller Intel 82559 Integrated ATI Rage IIC video controller with 4 MB of on board SGRAM e 1IB6566 South Bridge I O APIC PCI to ISA bridge IDE controller USB controller and power management 32 bit PCI features include Bus speed up to 33 MHz 5 V signaling environment e Burst transfers up to a peak of 132 MBps e 8 16 or 32 bit data transfers e Plug and Play ready e Parity enabled 2 4 2 1 Network Interface Controller NIC The STL2 server board includes a 10Base T 100Base TX network controller that is based on the Intel 82559 Fast Ethernet PCI Bus Controller This device is similar in architecture to its predecessor Intel 82558 No external devices are required to implement an embedded network subsystem other than TX RX magnetics two status LEDs and a connector Status LEDs are not included on the external NIC connector but there is a jumper head 6A where status LEDs may be connected The STL2 server board provides the ability to disable the embedded NIC in the BIOS Setup option When disabled it is not visible to the operating system STL2 Server Board TPS STL2 Server Board Architecture Overview The 82559 is a highly integrated PCI LAN controller for 10 or 100 Mbps Fast Ethernet netwo
16. error Some error messages are preceded by the string Error to highlight that the system might be malfunctioning All POST errors and warnings are logged in the system event log unless it is full Table 4 26 POST Error Messages and Codes 0200 Failure Fixed Disk hard disk error 0210 Stuck Key Keyboard connection error 0211 Keyboard error Keyboard failure 0212 Keyboard Controller Failed Keyboard Controller Failed 0213 Keyboard locked Unlock key switch Keyboard locked 0220 Monitor type does not match CMOS Run SETUP Monitor type does not match CMOS 4 52 STL2 Server Board TPS Basic Input Output System BIOS 0230 System RAM Failed at offset System RAM error Offset address 0231 Shadow RAM Failed at offset Shadow RAM Failed Offset address 0232 Extend RAM Failed at address line Extended RAM failed Offset address 0251 System CMOS checksum bad Default configuration CMOS checksum error used 0B51 CPU 2 with error taken offline Failed CPU 2 because an error was detected OB5F Forced to use CPU with error An error detected in the entire CPU 0B60 DIMM group 1 has been disabled Memory error memory group 1 failed 0B1B PCI System Error on Bus Device Function PCI system error in Bus device Function 0B61 DIMM group 2 has been disabled Memory error memory group 2 failed 0B50 CPU 1 with error taken offline Failed CPUtt1 because an error was detected OB7C The error occurred during redundant power module The
17. error occurred while retrieving the power confirmation information 0B80 BMC device chip failed 0B90 BMC Platform Information Area corrupted BMC device chip failed 0B91 BMC update firmware corrupted F RTE 0B92 Internal Use Area of BMC FRU corrupted SROM storing chassis information failed Available for use except for FRU command and EMP function 0B1C PCI Parity Error in Bus Device Function PCI system error in Bus device Function Revision 1 0 4 53 Basic Input Output System BIOS STL2 Server Board TPS 0B93 BMC SDR Repository empty BMC device chip failed 0B94 IPMB signal lines do not respond SMC Satellite Management Controller failed Available for use except for the access function to SMC via IPMB 0B95 BMC FRU device failure SROM storing chassis information failed pi Available for use except for FRU command and EMP function 0897 emesi le Some SMBus device chip raed mr is SMBus device Fordel le Warning IRQ not configured 8503 Incorrect memory speed in location XX XX Non PC133 DIMMs have been installed in slots XX XX A beep code is a series of individual beeps on the PC speaker each of equal length The following table describes the error conditions associated with each beep code and the corresponding POST check point code as seen by a port 80h card For example if an error occurs at checkpoint 22h a beep code of 1 3 1 1 is generated The beep codes 1 1 1 1 1 5 1 1 1 5
18. feature immediately Spanish changes to the language BIOS Italian selected 4 34 Hard Disk Pre Delay Disabled Delays first access to disk to 3 Seconds ensure the disk is initialized by the STL2 Server Board TPS Basic Input Output System BIOS Table 4 3 Primary Master and Slave Adapters Submenu Selections Choices or Display Only Description Auto Select the type of device that is attached to the None IDE channel CD ROM If User is selected the user will need to enter the ATAPI Removable parameters of the IDE device cylinders heads IDE Removable and sectors Other ATAPI User Mult Sector Transfers Disable Specifies the number of sectors that are 2 Sectors transferred per block during multiple sector 4 Sectors transfers 8 Sectors 16 Sectors LBA Mode Control Disabled Enable Disable Logical Block Addressing instead Enabled of cylinder head sector addressing 32 Bit I O Disabled Enable Disable 32Bit IDE data transfers Enabled Transfer Mode Standard Select the method of moving data to and from Fast PIO 1 the hard drive If Type Auto is select optimum Fast PIO 2 transfer mode will be selected Fast PIO 3 Fast PIO 4 FPIO 3 DMA 1 FPIO 4 DMA 2 Ultra DMA Mode Disabled Enable Disable Ultra DMA mode If Type Auto is Enabled select optimum transfer mode will be selected Table 4 4 Processor Settings Submenu Selections he ee eee Only Description XXX Display Only Indicates the processor speed XXX Di
19. no arbitration or interrupts rb AD 31 0 L ck CIREID DL L t gt PAR gt FRAME L gt TRoY L tp IRDY L gt STOP L gt DEVSEL L r IDSEL Rage IIC PCI CLK AG RSTL gt PERR L ch SERR L PCIINT L Figure 2 2 Video Controller PCI Signals STL2 Server Board TPS STL2 Server Board Architecture Overview 2 4 2 2 2 Video Controller PCI Commands The Rage IIC supports the following PCI commands Table 2 4 Video Controller Supported PCI Commands id Rage te Support ee Command Type Target Master 2 4 2 2 3 Video Modes The Rage IIC supports all standard IBM VGA modes The following tables show the standard resolutions that this implementation supports including the number of colors and the refresh rate Table 2 5 Standard VGA Modes Revision 1 0 2 13 STL2 Server Board Architecture Overview STL2 Server Board TPS 2 4 2 3 IB6566 South Bridge The IB6566 South Bridge is a PCI device that provides multiple PCI functions in a single package PCI to ISA bridge PCI IDE interface PCI USB controller and power management controller Each function within the IB6566 South Bridge has its own set of configuration registers Once configured each appears to the system as a distinct hardware controller sharing the same PCI bus interface On the STL2 baseboard the primary role of the IB6566 South Bridge is to provide the gateway to all PC compatible I O devices and features The STL2 se
20. selected feature is a submenu or to display a pick list if a selected feature has a value field or to select a subfield for multi valued features like time and date If a pick list is displayed the Enter key will undo the pick list and allow another selection in the parent menu ESC Exit The ESC key provides a mechanism for backing out of any field This key will undo the pressing of the Enter key When the ESC key is pressed while editing any field or selecting features of a menu the parent menu is re entered When the ESC key is pressed in any submenu the parent menu is re entered When the ESC key is pressed in any major menu the exit confirmation window is displayed and the user is asked whether changes can be discarded T Select Item The up arrow is used to select the previous value in a pick list or the previous feature in a menu item s option list The selected item must then be activated by pressing the Enter key J Select Item The down arrow is used to select the next value in a menu item s option list or a value field s pick list The selected item must then be activated by pressing the Enter key 4 32 STL2 Server Board TPS Basic Input Output System BIOS lt gt Select Menu The left and right arrow keys are used to move between the major menu pages The keys have no affect if a submenu or pick list is displayed F5 Change Value The minus key and the F5 function key are used to change the value of the cur
21. the SCSI Utility The user can access the Adaptec SCSI Utility when the system is powered on or rebooted To run the Adaptec SCSI utility perform the following procedure 1 Power on or reboot the system 2 Atthe message to Press Ctrl A to run SCSI Utility press Ctrl A 3 Choose the host adapter that needs to be configured 4 The SCSI utility starts When the Adaptec SCSI Utility detects more than one AIC 78xx host adapter it displays a selection menu listing the bus and device number of each adapter When the selection menu appears select the channel that should be configured as follows Bus Device Channel Selected SCSI Adapter 01 04 A AIC7899 01 04 B AIC7899 Note Internal SCSI Connector When the adapter is selected the following options display EE Configure View Host Adapter Settings Configure host adapter and device settings SCSI Disk Utilities The utility scans the SCSI bus for SCSI devices and reports a description of each device Run these utilities before configuring SCSI devices To format a disk verify disk media or display a list of devices and their SCSI IDs select SCSI Disk Utilities To configure the adapter or a device select Configure View Host Adapter Settings 4 8 2 Adaptec SCSI Utility Configuration Settings The following keys are active for all Adaptec SCSI Utility screens 4 56 STL2 Server Board TPS Basic Input Output System BIOS HE EE Displays opti
22. the system BIOS the STL2 can boot in recovery mode To place STL2 into recovery mode move the boot option jumper jumper block 1J15 pins 9 10 to the recovery boot position By default and for normal operation pins 9 and 10 are not jumpered Recovery mode requires at least 8 MB of RAM in the first DIMM socket and drive A must be set up to support a 3 5 1 44 MB floppy drive Note the system requires 64 MB to boot This is the mode of last resort used only when the main system BIOS will not come up In recovery Revision 1 0 4 47 Basic Input Output System BIOS STL2 Server Board TPS mode operation PHLASH in non interactive mode only automatically updates only the main system BIOS PHLASH senses that STL2 is in recovery mode and automatically attempts to update the system BIOS Before powering up the system the user must obtain a bootable diskette that contains a copy of the BIOS recovery files This is created by running the crisdisk bat from the compressed recovery file distributed with the BIOS Note During recovery mode video will not be initialized and many high pitched beep tones will be heard The entire process takes two to four minutes When the process is completed the tones will stop The user may see a Checksum error on the first boot after updating the BIOS This is normal and should correct itself after the first boot If a failure occurs it is most likely that of the system BIOS ROM file is corrup
23. values stored in battery backed CMOS configuration RAM The System Setup Utility SSU which also provides this functionality is discussed in a separate document BIOS Setup is closely tied with the system BIOS and is considered a part of BIOS Phoenix Phlash PHLASH EXE is used to load predefined areas of flash ROM with Setup BIOS and other code data The following is the break down of the STL2 product ID string 4 byte board ID STL2 e 1 byte board revision starting from 0 3 byte OEM ID 86B for standard BIOS 4 byte build number e 1 3 byte describing build type D for development A for Alpha B for Beta Pxx for production version xx 6 byte build date in yymmdd format 4 bytes time in hhmm format Revision 1 0 4 29 Basic Input Output System BIOS STL2 Server Board TPS 4 1 1 System BIOS The system BIOS is the core of the flash ROM resident portion of the BIOS The system BIOS provides standard PC BIOS services and support for some new industry standards such as the Advanced Configuration and Power Interface Specification Revision 1 0 and Wired For Management Baseline Specification Revision 2 0 In addition the system BIOS supports certain features that are common across all the Intel servers These include e Security e MPS support Server management and error handling CMOS configuration RAM management e OEM customization e PCI and Plug and Play PnP BIOS interface Console r
24. 05 INTA PIRQ8 24 Slot06 INTA PIRQ9 25 Slot01 INTA PIRQ10 26 SLOT 02 o 04 05 06 01 mr i Toe PIRQ12 28 B gt ein PIRQ13 29 e jo e e efe PIRQ14 30 i PIRQ15 31 Figure 2 4 STL2 Baseboard Interrupt Routing Diagram Symmetric mode Revision 1 0 2 19 STL2 Server Board Architecture Overview STL2 Server Board TPS 2 6 3 PCI Ids The STL2 server board PCI Ids are defined as follows Table 2 6 STL2 PCI IDs Bus Number Device Number Slot ID Signal 23 16 15 11 NB6635 North Bridge 3 0LE 00000b a ATI Rage IIC 00010b P32_AD18 Intel 82559 00011b P32 AD19 Adaptec AIC 7899 00100b P32 AD20 Slot 1 32 bit 00110b P32 AD22 Note Do not change the BUSNUM register Offset 44h in the NB6635 North Bridge 3 0LE from the default value 2 6 4 Relationship between PCI IRQ and PCI Device The relationship between PCI IRQ and PCI devices are defined as follows on the STL2 server board PCIIRQ 11 PCI Slot 1 INTB PCI Slot 2 INTB PCI Slot 3 INTC PCI Slot 4 INTB PCI Slot 5 INTC PCI Slot 6 INTD PCIIRQ 12 PCI Slot 1 INTC PCI Slot 2 INTC PCI Slot 3 INTD PCI Slot 4 INTC PCI Slot 5 INTD PCI Slot 6 INTB PCIIRQ 13 PCI Slot 1 INTD PCI Slot 2 INTD PCI Slot 3 INTB PCI Slot 4 INTC PCI Slot 5 INTD PCI Slot 6 INTB 2 20 STL2 Server Board TPS STL2 Server Board Architecture Overview Revision 1 0 2 21 STL2 Server Board TPS Server Management 3 Server Management This section de
25. 1 3 24 4 48 J JEDEC 1 1 2 7 L LED 5 73 Legacy 2 15 4 40 Logo 4 41 LUN 4 55 M Magic Packet 3 22 Main Menu 4 29 4 30 4 31 4 32 Management Controller 4 51 4 53 Memory 2 5 2 7 2 9 2 13 2 17 3 22 3 24 4 34 4 40 4 50 4 51 4 52 6 75 Message 4 50 Modem 4 39 MPS 4 28 4 34 Multi Processor Specification 4 28 4 34 N NB6635 North Bridge 1 1 2 7 2 20 NMI 3 23 3 24 4 38 5 58 5 73 North Bridge 1 1 2 7 2 20 NVRAM 4 29 4 40 4 41 4 50 P Password 3 23 4 37 4 41 4 51 5 59 5 60 Password Clear 5 59 PERR 3 23 3 24 4 38 5 71 5 72 PGA370 1 1 2 5 2 6 PIC 2 15 2 17 2 18 4 36 4 50 POST 3 22 3 24 3 25 4 29 4 30 4 33 4 34 4 42 4 43 4 44 4 46 4 47 4 49 4 50 4 52 4 53 5 60 5 61 POST Code 4 46 Power Button 3 23 3 24 Power Control 3 22 Power Distribution Board 3 22 Power Down 3 25 Power state 3 25 Power Supply 3 22 5 57 Power on Self Test See POST 3 22 3 24 3 25 4 29 4 30 4 33 4 34 STL2 Server Board TPS 4 42 4 43 4 44 4 46 4 47 4 49 4 50 4 52 4 53 5 60 5 61 PXE 3 23 3 24 4 39 R Real Time Clock See RTC Recovery 4 45 4 49 5 60 5 61 Redirection 4 38 Reset Button 3 23 3 24 RTC 2 15 3 25 4 43 4 51 SC242 2 5 SC242 connector 2 5 SCSI 1 1 2 5 2 8 2 9 2 10 2 20 3 23 4 27 4 28 4 35 4 36 4 37 4 41 4 53 4 54 4 55 5 58 5 68 5 69 6 75 SCSI Connector 4 54 5 68 5
26. 2 Revision 1 0 vii List of Tables STL2 Server Board TPS Table 4 26 POST Error Messages and Codes ANNE EEN 4 52 Table 4 27 Adaptec SCSI Utility Setup Configurations ssssseseeessseeserrrrresserrenrrrrnreserrenne 4 57 Table 5 1 Jumper Block 1215 Settings aars eege Eege 5 64 Table 5 2 Jumper Block 5E1 Settings EE 5 66 Table 5 3 Jumper Block 1J15 Default Getttnge Ak 5 66 Table 5 4 Jumper Block 1L4 Senings EE 5 67 Table 5 5 Jumper Block GA Settings eege ee ieee at eege 5 67 Table 5 6 Main ATX Power Connector Pinot 5 68 Table 5 7 Auxiliary ATX Power Connector Pinot EEN 5 68 Table 5 8 IC Power Connector Pinot 5 68 Table 5 9 Board Fan Connector TEE 5 69 Table 5 10 Processor Fan Connector Pinout tannic niet eegene eege deg 5 69 Table 5 11 Speaker Connector Pinout ere ee ie ahora eee 5 69 Table 5 12 Speaker Connector PMOul c8 snccen ts niet eege Eege 5 69 Table 5 13 Diskette Drive Connector Pinout uk 5 70 Table 5 14 Video Port Connector PnoUauerraamtegadsahetdudearudagneju sein 5 70 Table 5 15 Keyboard and Mouse Connector PinOuts ccccccccccccccecececeeeceeeeeeeeeeeeeeeeeeess 5 71 Table 5 16 Parallel Port Connector Pinouts 2 20 teitet toate tna Aiea 5 71 Table 5 17 Serial Ports COM1 and COM2 Connector Pinouts rrrrrrrnnnnrrrrnnnnnnnnnnnnnnrrnnnnn 5 71 Table 5 18 RJ 45 LAN Connector SIgnal un minvinuidsiineimdldmarmletnddepnubitufe 5 72 Table 51S USB COnnec ENEE eege 5 72 Table 5 20 Ultra SCSI Con
27. 2 1 and 1 5 3 1 are reserved for BMC usage 1 2 2 3 ROM Checksum Error Change system board 1 3 1 1 DRAM Refresh Test Error evo Change memory DIMM s 1 3 1 3 Keyboard Controller Test Error Pe CT Change system board 1 3 3 1 Memory Not Detected No memory Verify DIMM installation Memory Capacity Check Error No memory Verify DIMM installation 1 3 4 1 DRAM Address Test Error Memory address signal failure Change DIMM or M B 353 A Wero og Eros OO change system oar Change GPU or system boar Memory address signal failure Change DIMM or M B 4 54 STL2 Server Board TPS Basic Input Output System BIOS 3 3 1 4 Memory Not Detected Not Detected EE ROM Initialization Error Failure to initialize eene ROM sees erer system board or option BIOS board Video configuration fails Failure to initialize VGA BIOS Change option video board or system board OPTION ROM Checksum Error Failure to initialize Option BIOS Change M B or option board 4 7 Identifying BIOS and BMC Revision Levels The following sections provide information to help identify a system s current BIOS and BMC revision levels 4 7 1 BIOS Revision Level Identification During system POST which runs automatically when the system is powered on the monitor displays several messages one of which identifies the BIOS revision level currently loaded on the system see the following example Phoenix BIOS 4 0 Release 6 0 250A In the example abov
28. 3 24 3 25 Transfer Mode 4 33 Type Code 3 23 U Ultra160 LVD 5 58 Universal Serial Bus 1 2 2 7 2 10 2 14 2 15 2 17 4 35 4 48 5 58 5 68 6 75 6 76 Revision 1 0 Index USB 1 2 2 7 2 10 2 14 2 15 2 17 4 35 4 48 5 58 5 68 6 75 6 76 User Binary 4 44 4 45 Vv Voltage See also Sensor Voltage 3 22 3 23 8 79 8 80 8 82 VRM 1 1 2 6 5 57 6 75 6 76 W Warning 4 52 Windows NT 3 26 6 76 Z zero insertion force socket 2 5 2 6 ZIF socket 2 6
29. 3 MHz 133 MHz 256K 866 MHz 133 MHz 256K 800 MHz 133 MHz 256K 733 MHz 133 MHz 256K 667 MHz 133 MHz 256K Revision 1 0 2 5 STL2 Server Board Architecture Overview STL2 Server Board TPS 2 1 2 Dual Processor Operation The Pentium III processor interface is designed to be MP ready Each processor contains a local APIC section for interrupt handling When two processors are installed both processors must be of identical revision core voltage and bus core speeds 2 1 3 PGA370 Socket The STL2 server board provides two PGA370 sockets These are 370 pin zero insertion force ZIF sockets that a flip chip pin grid array FC PGA package technology processor plugs into 2 1 4 Processor Bus Termination Regulation Power The termination circuitry required by the Intel Pentium III processor bus AGTL signaling environment and the circuitry to set the AGTL reference voltage are implemented directly on the processor The STL2 server board provides VRM 8 4 compliant DC to DC converters to provide processor power VCCP at each PGA370 socket The server board provides an embedded VRM for the primary processor and a VRM socket for the secondary processor These are powered from the 5V supply 2 1 5 Termination Package If a processor is not installed in a PGA370 socket a termination package must be installed in the vacant socket to ensure reliable termination 2 1 6 APIC Bus Interrupt notification and generation for the p
30. 38 Table 4 11 Security Menu Selections ANNE 4 39 Table 4 12 Secure Mode Submenu Selections A 4 40 Table 4 13 Server Menu Selections rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrerrrrrrrrrrrrrrrsrsrersrrsrrssrrsssere 4 40 Table 4 14 Wake On Events Submenu Selections urrrrrrrrrrrrvrrvrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrenr 4 40 Table 4 15 Console Redirection Submenu Selections rrnnrrrrrnnnnnnnnnnnnnrrrrnnnnnnnrnnnnnnrrnnnnne 4 41 Table 4 16 Boot Menu Selections rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrerrrrrerrrrerrrrrrrrrrrrrrrrsrrrssrssssrsene 4 41 Table 4 17 Boot Device Priority Selections ANEN 4 41 Table 4 18 Hard Drive Gelechons eenen nennen nnne nennen nennen nenene 4 42 Table 4 19 Removable Devices Selections rrrrrrrrrrrrrrrrrrvrrrrrrrerrrrrrrrrrrrrrrrrerrrrrrrerrrrrrsrrenr 4 42 Table 4 20 Exit Menu Selections rrrrrrrrrrvrrrrrrrrrvrrrvrvrrrrrrrrrrrrrrrererrerrrrererrrrrrrerrrrrrrrrssrssreer 4 42 Table 4 21 User Binary Area Scan Point Definitions rrrnnnrrrrnnnnnnnnnnnnnnrrrnnnnnnnnnnnnnnnrrrnnnne 4 46 Table 4 22 Format of the User Binary Information Structure rreernnrrrnnnrrrrrnnnnnnnnnnnnnnrrnnnnn 4 47 Table 4 23 Port 80h Code Definition wrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrererrrrrrrrrrrrrrrrrerersrsrrrssreer 4 48 Table 4 24 Standard BIOS Port 80 Codes rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrerrrrrrrrrrrrrrrerererrrrrrrrrrrrrsrenr 4 49 Table 4 25 Recovery BIOS Port 80 CGodes AAA 4 5
31. 4 Setting Processor Frequency Jumper Block 5E1 The jumpers on block 5E1 set the processor speed for the installed processor s The following table lists the settings for jumper block 5E1 Procedures for setting the jumpers follow the table Revision 1 0 5 65 Jumpers and Connectors STL2 Server Board TPS Table 5 2 Jumper Block 5E1 Settings Processor Frequency Jumper Settings MHz 7 8 Nor Jumpered Not Jumpered Junpered Not Jumpered Not Jumpered Not Jumpered Set the processor frequency jumpers as follows 1 Power off the system unplug the power cord 2 From the Jumper Block 5E1 Settings table select the processor frequency matching the installed processor 3 Move the jumpers to the settings shown in the Jumper Block 5E1 Settings table 4 Reinstall the left panel plug in the power cord s and power on the system The following table lists the factory default settings for jumper block 5E1 which are indicated in bold typeface Table 5 3 Jumper Block 1J15 Default Settings Jumper Pin Jumper Position What it does at system reset Numbers Processor Feeney seei open OO aa PrecessorFrequeney See fon 56 Processor Frequency Set Open 78 on pf L t Disabled Disables a3 WHFS Ys Enabled Enables FOC Spread Spec 5 1 2 Setting Configuration Jumper Block 1L4 Setting the jumpers on system board jumper block 1L4 enables the user to configure chassis intrusion sensors o
32. 5 Soft off Only the RTC section of the chip set and the BMC are running in this state The STL2 server board supports sleep states sO s1 s4 and 55 When the server board is operating in ACPI mode the OS retains control of the system and the OS policy determines the entry methods and wake up sources for each sleep state sleep entry and wake up event capabilites are provided by the hardware but are enabled by the OS With future versions of Microsoft Windows 9X that support ACPI the system BIOS supports only sleep states sO s1 and s5 With future versions of Microsoft Windows NT that support ACPI the system BIOS will support sleep states sO s1 s4 and s5 3 4 AC Link Mode The AC link mode allows the system to monitor its AC input power so that if AC input power is lost and then restored the system returns to one of the following preselected settings e Power On Last State Factory Default Setting e Stay Off The AC link mode settings can be changed by running the BIOS Setup Utility 3 5 Wake On LAN Function The remote power on function turns on the system power by way of a network or modem If the system power is set to Off it can be turned on remotely by sending a specific packet from the main computer to the remote system Note The standard default value of the remote power on function is Disabled The Wake on LAN Ring function can changed by setting the option to Enabled in the BIOS Setup Utility
33. 5 3 Diskette Drive Connector Pin Diagram Table 5 13 Diskette Drive Connector Pinout FD DENSEL FD MDAID 5 2 9 SVGA Video Port Table 5 14 Video Port Connector Pinout ER E OG Ko 5 70 STL2 Server Board TPS STL2 Server Board TPS Jumpers and Connectors Signal Deem 5 2 10 Keyboard and Mouse Connectors The keyboard and mouse connectors are functionally equivalent Table 5 15 Keyboard and Mouse Connector Pinouts Keyboard Signal i Mouse Signal KEYDAT MSEDAT FUSED_VCC 5 V FUSED_VCC 5 V KEYCLK MSECLK 5 2 11 Parallel Port Table 5 16 Parallel Port Connector Pinouts STROBE_L ACK_L Data bit 2 SLCT Data bit 3 AUTO_L Data bit 5 INIT_L Data bit 6 SLCTIN_L Data bit 4 ERROR_L 5 2 12 Serial Ports COM1 and COM2 Table 5 17 Serial Ports COM1 and COM2 Connector Pinouts Signal Description Data carrier detected Revision 1 0 5 71 Jumpers and Connectors STL2 Server Board TPS Signal Description Ring indication active 5 2 13 RJ 45 LAN Connector Table 5 18 RJ 45 LAN Connector Signals in Soa Beserpin O OOO TX Transmit data plus the positive signal for the TD differential pair contains the serial output data stream transmitted onto the network SR TX Transmit data minus the negative signal for the TD differential pair contains the same output as pin 1 RX Receive data plus the positive signal for the RD differential pair contains
34. 5 4 IDE Connector Pin Diagram If no IDE drives are present no IDE cable should be connected If a single IDE drive is installed it must be connected at the end of the cable Table 5 22 IDE Connector Pinout GND DD8 1 RESET L 21 3 23 8 Jons IS 5 74 STL2 Server Board TPS Jumpers and Connectors Signal IDEDAK L IGND o DERG DESAT IDESAD IDECSO L GND 5 2 18 32 Bit PCI Connector Table 5 23 32 Bit PCI Connector Pinout B1 12 V A32 AD16 B32 AD17 B2 TCK A33 3 3 V B33 B3 GND A34 FRAME L B34 B4 TDO NC A35 GND B35 B5 5 V A36 TRDY_L B36 INTA L B6 5 V A37 GND B37 ND INTC_L B7 INTB_L A38 STOP_L B38 Signal Pin Signal Pin Signal Pin Signal 5 V B8 INTD L A39 3 3 V B39 LOCK L Reserved B9 PRSNT1 L A40 SDONE B40 PERR L 5 V Reserved A41 SBO L B41 Reserved PRSNT2 L A42 GND B42 GND GND A43 PARITY B43 GND GND A44 AD15 B44 Reserved Reserved A45 3 3 V B45 RST L GND A46 AD13 B46 ADI N 5 V PCICLK A47 AD11 B47 AD12 GNT_L GND A48 GND B48 GND REQ L A49 AD9 B49 PME_L 5 V A50 KEY B50 KEY AD30 AD31 A51 KEY B51 KEY o 3 Revision 1 0 5 75 Jumpers and Connectors STL2 Server Board TPS AD8 AD7 AD5 AD3 GND AD1 REQ64 L ACK64_L 5 2 19 64 Bit PCI Connector Table 5 24 64 Bit PCI Connctor Pinout Pin Signal i Signal i Signal B1 12 V GND B2 TCK AD9 B3 GND KEY
35. 69 SDR 3 21 4 51 SDR Repository 3 21 4 51 SDRAM 1 1 2 7 6 75 6 76 Secure Mode 3 22 3 23 4 37 4 38 SecureBIOS 4 28 Security 3 22 3 23 4 28 4 29 4 31 4 37 Processor 2 5 2 6 3 22 3 23 3 24 3 25 4 32 4 33 4 47 4 48 5 59 5 61 5 62 5 65 SEL 3 21 3 23 3 24 4 51 Sensor 3 21 3 22 Sensor Data Record See SDR Sensor Event 3 21 3 23 3 24 4 38 Sensor Chassis Intrusion 5 58 Sensor Fan 2 6 3 22 3 23 5 65 5 73 Sensor Processor 2 5 2 6 3 22 3 23 3 24 3 25 4 32 4 33 4 47 4 48 5 59 5 61 5 62 5 65 Sensor Temperature 3 22 3 23 4 51 8 82 Sensor Type 3 22 3 23 Sensor Type Code 3 23 Sensor Voltage 3 22 3 23 8 79 8 80 8 82 Serial 1 2 2 16 4 33 4 35 4 39 5 58 5 67 SERR 3 23 3 24 5 71 5 73 Server Management 3 21 Server Menu 4 38 ServerWorks ServerSet III LE chipset 1 1 2 5 2 7 Setup Utility 3 26 4 27 4 28 4 29 4 30 4 41 5 60 SGRAM 1 2 2 10 2 12 Shadow 4 47 4 48 4 49 4 50 4 52 Shutdown 4 49 SMBIOS 4 51 SMI 3 21 3 23 3 25 SMM 4 45 South Bridge 1 1 1 2 2 6 2 7 2 10 2 14 2 15 2 17 2 20 Speaker 5 65 SSU 4 27 4 29 STL2 Server Board EPS Super I O Controller 1 2 System Event Log See SEL System Management Software 3 21 System Setup Utility See SSU T Temperature 3 22 3 23 4 51 8 82 termination circuitry 2 6 Third party instrumentation 1 1 2 8 2 20 4 53 4 54 4 55 Timeout 3 23
36. 7 Sosa nav 20h SOB 2 C SSA re aie SCSI A Vref3 SCSI B Vref1 SCSI B Vref2 EET el o We an mm e RE festes Path messer fosset Soft Power Control Failure bit 5 Interlock Power 7m Power Distribution Board Supply Power supy Faure deeded ott Redundancy Regained bit 0 Chassis Intrusion ID Drive Bay Intrusion bit 1 LAN Leash Lost bit 4 Security Violation Secure Mode Violation Attempt bit 0 92h Memory Error ECC multiple bit error bit 1 ECC single bit error bit 0 3 24 STL2 Server Board TPS Server Management Sensor Type Monitoring Device oi BIOS POST ere Code EEE 95h Log Disable Log Area Reset Cleared bit 2 ECC single bit Error Disable bit 0 96h OEM System Event Hard Reset bit 1 System 97h Critical Interrupt PCI SERR bit 5 PCI PERR bit 4 Front Panel NMI Dump SW bit 0 Button Reset Button bit 2 Sleep Button bit 1 Power Button bit 0 Boot Init User requested PXE boot bit 3 Initiated by power up bit 0 Boot Error PXE Server not found bit 2 No bootable media bit 0 OS S Os Sp kn ACPI State Sleeping in S1 state bit 8 G3 Mechanical Off bit 7 S5 G2 Soft Off bit 5 S4 bit 4 The following table provides a list of System Event Log SEL events supported by the STL2 server board Sensor Type Sensor Type Sensor Specific Code Offset Reseved D I 02h eC Voltage An error occurred at voltage sensors Performance Lags In the single end
37. Architecture Overview 2 4 2 3 3 USB Interface The 1B6566 South Bridge contains a USB controller and USB hub The USB controller moves data between main memory and the two USB connectors provided The STL2 server board provides a dual external USB connector interface Both ports function identically and with the same bandwidth The external connector is defined by Revision 1 0 of the USB Specification 2 4 2 4 Compatibility Interrupt Control The 1B6566 South Bridge provides the functionality of two 82C59 Programmable Interrupt Controller PIC devices for ISA compatible interrupt handling 2 4 2 5 APIC The 1B6566 South Bridge integrates a 16 entry I O APIC that is used to distribute 16 PCI interrupts It also includes an additional 16 entry I O APIC for distribution of legacy ISA interrupts 2 4 2 6 Power Management One of the embedded functions of IB6566 South Bridge is a power management controller The STL2 server board uses this to implement ACPI compliant power management features STL2 supports sleep states 50 s1 s4 and s5 2 5 Chipset Support Components 2 5 1 Legacy I O Super I O National PC97317VUL The National PC97317VUL Super I O Plug and Play Compatible with ACPI Compliant Controller Extender is used on the STL2 server board This device provides the system with e Real time Clock RTC Two serial ports One parallel port e Floppy disk controller FDC e PS 2 compatible keyboard and mouse controller
38. B4 TDO NC KEY B5 5 V CBEO L INTA L B6 5 V 3 3 V INTC L B7 INTB L AD6 5 V B8 INTD_L AD4 Reserved B9 PRSNT1 L GND 5 V Reserved AD2 Reserved PRSNT2_L ADO A GND GND 5V A A GND GND REQ64_L Reserved Reserved 5 V RST_L GND 5 V 5 V PCICLK GND D GNT_L GND CBE7_L GND REQ_L CBE5_L CBE6_L PME_L 5 V 3 3 V CBE4_L GND AD30 AD31 Parity GND AD29 AD62 GND GND AD27 AD60 AD25 AD58 3 3 V GND CBE3 L AD56 Y Y 8 7 5 3 N 1 N N 5 76 STL2 Server Board TPS Jumpers and Connectors Signal i Signal i Signal AD23 AD54 GND 83 V AD21 AD52 AD19 AD50 3 3 V GND AD17 AD48 i CBE2_L AD46 FRAME_L GND GND D GND IRDY_L AD44 TRDY_L 3 3 V AD42 AD43 GND DEVSEL_L 3 3 V AD41 GND STOP_L GND AD40 GND 3 3 V LOCK_L AD38 SDONE PERR_L GND SBO_L 3 3 V AD36 GND SERR_L AD34 PARITY 3 3 V GND AD15 CBE1_L AD32 Reserved AD14 Reserved Reserved GND GND AD12 Reserved GND 5 2 20 Front Panel 24 pin Connector Pinout P23 Table 5 25 Front Panel 24 pin Connector Pinout Pin Description 5 Power LED Cathode 6 Fan Fau LED Cathode 7 Hara Drive Aaiwiy LED Anods 8 Power Faut LED Anode 3 hard Drive Aciwiy LED Cathode 10 Power Faut LED Cabo 3 Power Swich Low Tu 72 NIC Ratviy LED Anods 35 Power Swich GND 14 NIC Activity LED Cathode 15 Reset Switch Low True 5 7 10 11 12 13 14 15 Revision 1 0 5 77 J
39. Disabled Boot Device Priority J See Boot Device Priority KG Submenu Removable Devices See Removable Devices Submenu Table 4 17 Boot Device Priority Selections Boot Priority Device Description ft ATAPI CD ROM Drive Attempts to boot from an ATAPI CD ROM drive Ps P20 Removable Devices Attempts to boot from a removable device P Revision 1 0 4 41 Basic Input Output System BIOS STL2 Server Board TPS Attempts to boot from a hard drive device Intel UNDI PXE 2 0 Attempts to boot from a PXE server T Table 4 18 Hard Drive Selections Description AIC 7899 CH B ID 1 Select the order in which each drive is attempted to be Boot Priority used as the boot device AIC 7899 CH B ID 4 Bootable Add in Cards Note 1 These selections will change depending on the system configuration Gs AIC 7899 CH A ID 9 es Table 4 19 Removable Devices Selections Boot Description Priority 1 Legacy Floppy Drives Select the order in which each removable device is attempted to be used as the boot device Note 1 These selections will change depending on the system configuration 4 2 2 9 Exit Menu Selections The following menu options are available on the Exit menu Use the up and down arrow keys to select an option then press the Enter key to execute the option Table 4 20 Exit Menu Selections CUE BT Exit Saving Changes Exit after writing all modified Setup item values to NVRAM
40. Exit Discarding Changes Exit leaving NVRAM unmodified User is prompted if any of the setup fields were modified Load Setup Defaults Load default values for all SETUP items Discard Changes Read previous values of all Setup items from NVRAM Save Changes Write all Setup item values to NVRAM 4 3 CMOS Memory Definition Only the BIOS needs to know the CMOS map The CMOS map is not defined in the BIOS EPS The CMOS map is available in the NVRAM LST file generated for every BIOS release The CMOS map is subject to change without notice 4 42 STL2 Server Board TPS Basic Input Output System BIOS 4 4 CMOS Default Override The BIOS detects the state of the CMOS default switch If the switch is set to CMOS Clear prior to power on or a hard reset the BIOS changes the CMOS and NVRAM settings to a default state This guarantees the system s ability to boot from floppy Password settings are not affected by CMOS clear The BIOS clears the ESCD parameter block and loads a null ESCD image The boot order information is also cleared when CMOS is cleared via jumper The configuration data for the on board SCSI controllers is not cleared during a clear CMOS event as each device controls its own default settings If the Reset Configuration Data option is enabled in Setup ESCD data and BIOS Boot specification data is cleared and reinitialized in next boot 4 5 Flash Update Utility The BIOS update utility Phoenix Phlash exe loads a f
41. Number E139761 Component side e Battery marking located on the component side of the board in close proximity to the battery holder CE Mark Component side e Australian C Tick Mark Consists of solid circle with white check mark and supplier code N232 Russian GOST Open letter C with the letter P inside the C and the letter T in the mouth of the C Taiwan BSMI Certification mark Two Chinese characters and an 8 digit number 8 2 Installation Instructions CAUTION Follow these guidelines to meet safety and regulatory requirements when installing this board assembly Read and adhere to these instructions and to the instructions supplied with the host computer and associated modules If the instructions for the host computer are inconsistent with these instructions or the instructions for associated modules contact the supplier s technical support to find out how to ensure that the system meets safety and regulatory requirements If the instructions are not followed the user increases safety risk and the possibility of noncompliance with regional laws and regulations 8 2 1 Ensure EMC Before computer integration the host chassis power supply and other modules should pass EMC certification testing In the installation instructions for the host chassis power supply and other modules pay close attention to the following e Certifications e External I O cable shielding and f
42. POST codes occur prior to the video display being initialized To assist in determining the fault a unique beep code is derived from these checkpoints as follows 4 48 STL2 Server Board TPS Basic Input Output System BIOS The 8 bit test point is broken down to four 2 bit groups Each group is made one based 1 through 4 One to four beeps are generated based on each group s 2 bit pattern Example Checkpoint 04Bh will be broken down to 010010 11 And the beep code will be 2 1 3 4 Table 4 24 Standard BIOS Port 80 Codes ae Verify Real Mode po Get Processor type poe Initialize system hardware po o Initialize chipset registers with initial POST values po f Set in POST flag oA Initialize Processor registers B f Enable Processor cache poc Initialize caches to initial POST values ER Initialize UO nr Initialize the local bus IDE 1 fF Initialize Power Management 1 Load alternate registers with initial POST values 1 Restore Processor control word during warm boot 14 Initialize keyboard controller 1 2 2 3 BIOS ROM checksum fF 8254 timer initialization 1A fF 8237 DMA controller initialization LZ Reset Programmable Interrupt Controller 1 3 1 1 Test DRAM refresh 1 3 1 3 Test 8742 Keyboard Controller 24 Set ES segment register to 4GB 28 1 3 3 1 Autosize DRAM system BIOS stops execution here if the BIOS does not detect any usable memory DIMMs AA Ieren 32 testProcessorbussodkegenr ST Dame
43. ROMs may be executed in a large system configuration If user binary code is required at run time it is copied into and executed from option ROM space OC8000H OE7fffH At each scan point during POST the system BIOS determines if the scan point has a corresponding user binary entry point to transfer control to the user binary Presence of a valid entry point in the user binary is determined by examining the bitmap at byte 4 of the user binary header each entry point has a corresponding presence bit in this bitmap If the bitmap has the appropriate bit set an entry point ID is placed in the AL register and execution is passed to the address computed by ADR Byte 5 5 scan sequence During execution the user binary may access 11 bytes of extended BIOS data area RAM EBDA The segment of EBDA can be found at address 40 0e Offset 18h through offset 22h is available for the user binary The BIOS also reserves 8 CMOS bits for the user binary These bits are in an unchecksummed region of CMOS with default values of zero and will always be located in the first bank of CMOS These bits are contiguous but are not in a fixed location Upon entry into the user binary DX contains a token that points to the reserved bits This token is of the following format MSB LSB EE ea a ee E E of bit available 1 Bit offset from start of CMOS of first bit The most significant four bits are equal to the number of CMOS bits avai
44. Reference Manual PC Bus Specification Intelligent Platform Management Bus Communications Protocol Specification VAM 8 4 DC DC Converter Specification Adaptec AIC 7899 PCI Bus Master Dual channel Ultra160 SCSI Host Adapter Chip Data Book Intel 82559 Fast Ethernet Multifunction PCI CardBus Controller Datasheet Intelligent Platform Management Interface IPMI Specification STL2 Server Board EPS A ACPI 2 7 3 23 3 25 3 26 4 49 5 73 Adaptec AIC7899 1 1 2 8 Address 2 9 2 13 2 17 3 25 4 39 4 52 AIC 7899 2 8 2 9 2 10 2 20 4 40 APIC 2 6 2 10 2 14 2 15 2 17 Architecture 2 5 ATT Rage IIC 2 12 2 13 2 20 B Baseboard Management Controller See BMC BIOS 1 2 2 8 2 10 2 14 2 16 2 17 3 21 3 22 3 26 4 27 4 28 4 29 4 32 4 34 4 40 4 41 4 42 4 43 4 44 4 45 4 46 4 47 4 48 4 49 4 50 4 51 4 52 4 53 4 55 5 60 5 61 BIST 3 24 BMC 1 2 2 5 2 14 2 16 3 21 3 23 3 24 3 25 4 51 4 52 4 53 5 62 I Bridge 1 1 2 6 2 7 2 10 2 14 2 15 2 17 2 20 Built in Self Test 3 24 C Certification 8 80 Chassis Intrusion 3 22 3 23 5 59 5 63 5 73 Checksum 4 46 4 52 CMOS 2 16 4 27 4 28 4 29 4 40 4 41 4 42 4 43 4 47 4 48 4 50 5 59 5 60 5 61 CMOS Clear Jumper 5 59 Configuration 2 9 2 13 3 25 4 28 4 29 4 31 4 34 4 35 4 41 4 52 4 54 4 55 5 58 5 59 5 62 5 63 Connection 3 23 4 39 5 66 5 69 5 70 5 71 Connector Drive 5 66 Connecto
45. STL2 Server Board Technical Product Specification Revision 1 0 ntel P September 22 2000 Enterprise Platforms Group Revision History STL2 Server Board TPS Revision History Revision Modifications Number SE 6 20 00 06 O Updated connector reference designators 7 7 00 0 61 Updated silkscreen reference designators to agree with STL2 FAB2 Removed figure 2 3 1B6566 IRQ routing diagram Added BIOS recovery jumper information Corrected grammar spelling errors Updated table 5 1 STL2 Hardware Sensors per recent information 8 24 00 0 7 Updated Section 5 Jumpers and Connectors per modifications to the STL2 Fab3 Silver boards Updated Section 4 2 BIOS Setup per modifications included in BIOS Release 1 1 Added power consumption information to Section 6 2200 Disclaimers Information in this document is provided in connection with Intel products No license express or implied by estoppel or otherwise to any intellectual property rights is granted by this document Except as provided in Intel s Terms and Conditions of Sale for such products Intel assumes no liability whatsoever and Intel disclaims any express or implied warranty relating to sale and or use of Intel products including liability or warranties relating to fitness for a particular purpose merchantability or infringement of any patent copyright or other intellectual property right Intel products are not intended for use in medical life saving or li
46. TC resistor This Intel server board has PTCs on all external ports that provide DC power externally 8 2 2 2 In the United States A certification mark by a Nationally Recognized Testing Laboratory NRTL such as UL CSA or ETL signifies compliance with safety requirements External wiring must be UL Listed and suitable for the intended use Internal wiring must be UL Listed or Recognized and rated for applicable voltages and temperatures The FCC mark Class A for commercial or industrial only or Class B for residential signifies compliance with electromagnetic interference requirements 8 2 2 3 In Canada A nationally recognized certification mark such as CSA or cUL signifies compliance with safety requirements No regulatory assessment is necessary for low voltage DC wiring used internally or wiring used externally when provided with appropriate overcurrent protection Appropriate protection is provided by a maximum 8 Amp current limiting circuit or a maximum approved 5 Amp fuse or positive temperature coefficient PTC resistor This server board has PTCs on all external ports that provide DC power externally 8 2 3 Prevent Power Supply Overload The power supply output must not be overloaded To avoid overloading the power supply the calculated total current load of all the modules within the computer should be less than the maximum output current rating of the power supply If this is not adhered to the power supply may overheat catc
47. VRM connector for support of the secondary processor e ServerWorks ServerSet III LE chipset 133 MHz Front Side Bus Capability NB6635 North Bridge 3 0 LE 1B6566 South Bridge e Support for four 3 3V registered ECC SDRAM DIMMs that are compliant with the JEDEC PC133 specification Support for DIMM sizes 64 MB to 1GB Four DIMM slots allow a maxiumum installed memory of 4GB ECC single bit correction and multiple bit detection e 64 bit 66 MHz 3 3V keyed PCI segment with two expansion connectors and one embedded device Two 64 bit 66 MHz 3 3V keyed PCI expansion slots Integrated on board Adaptec AIC7899 PCI dual port SCSI controller that provides separate Ultra160 and Ultra Wide SCSI channels Revision 1 0 1 1 Introduction STL2 Server Board TPS e 32 bit 33 MHz 5V keyed PCI segment with four expansion connectors and three embedded devices Four 32 bit 33 MHz 5V keyed PCI expansion slots 1B6566 South Bridge which provides IDE and USB controller functions Integrated on board Intel EtherExpress PRO100 10 100megabit PCI Ethernet controller Intel 82559 with an RJ 45 Ethernet connector Integrated on board ATI Rage IIC video controller with 4 MB of on board SGRAM video memory e Compatibility bus segment with three embedded devices Super HO Controller PC97317 that provides all PC compatible I O floppy parallel serial keyboard mouse and Real Time Clock Basebo
48. analog data separator and 16 byte FIFO 2 5 1 4 Keyboard and Mouse Connectors The keyboard controller is functionally compatible with the 8042A The keyboard and mouse connectors are PS 2 compatible 2 5 1 5 Real time Clock The PC97317VUL contains an MC146818 compatible real time clock with external battery backup The device also contains 242 bytes of general purpose battery backed CMOS RAM The real time clock provides system clock and calendar information stored in non volatile memory 2 5 1 6 Plug and Play Functions ISA Data Transfers The PC97317VUL contains all signals for ISA compatible interrupts and DMA channels It also provides ISA control data and address signals to transfer data to from the BMC and the BIOS flash device This ISA subsystem transfers all SIO peripheral control data to the IB6566 South Bridge as well 2 5 1 7 Power Management Controller The PC97317VUL component contains functionality that allows various events to allow the power on and power off of the system This can be from PCI Power Management Events the BMC or the front panel This circuitry is powered from stand by voltage which is present anytime the system is plugged into the AC outlet STL2 Server Board TPS STL2 Server Board Architecture Overview 2 5 2 BIOS Flash The STL2 baseboard incorporates an Intel 5V FlashFile 28F008SA Flash Memory component The 28FO08SA is a high performance 8 Mbit memory that is organized as 1 MB of 8 bits
49. ard Management Controller BMC DS80CH11 that provides monitoring alerting and logging of critical system information including thermal voltage fan and chassis intrusion information obtained from embedded sensors on the server board 8 MB Flash device for system BIOS Dual Universal Serial Bus USB ports One IDE connector e Flash BIOS support for all of the above Extended ATX board form factor 12 x 13 1 4 STL2 Server Board Block Diagram The STL2 server board offers a flat design with the processors and memory subsystems residing on the board The following figure shows the major functional blocks of the STL2 server board The following section describes the major components of the server board STL2 Server Board TPS Introduction STL2 Server Board Block Diagram SS SS 133 MHz System Bus PC133 Registered ECC 2 64bit 66Mhz 3 3V PCI SDRAM DIMMs PCI 64bit 66MHz 2 32bit 33MHz 5V PCI S6 S5 S4 S1 PCI 32bit 33MHz ISA Bus Floppy Keyboard Mouse 2 Serial Ports Parallel Port Figure 1 1 STL2 Server Board Block Diagram Revision10 Mg Introduction STL2 Server Board TPS lt This page intentionally left blank gt STL2 Server Board TPS STL2 Server Board Architecture Overview 2 STL2 Server Board Architecture Overview The architecture of the STL2 server board is based on a design that supports dual processor operation with Intel Pentium Ill proc
50. arp pins on connectors Sharp pins on printed circuit assemblies Rough edges and sharp corners on the chassis Hot components like processors voltage regulators and heat sinks Damage to wires that could cause a short circuit Observe all warnings and cautions that instruct you to refer computer servicing to qualified technical personnel WARNING Do not open the power supply There is risk of electric shock and burns from high voltage and rapid overheating Refer servicing of the power supply to qualified technical personnel 8 3 Environmental Limits 8 3 1 System Office Environment Table 8 2 Office System Environment Summary Operating Temperature 10 C to 35 C with the maximum rate of change not to exceed 10 C per hour lt 47 dBA with one power supply 28 2 C lt 50 dBA with two power supplies 28 2 S O lt 55 dBA with three power supplies 28 2 Operating Shock No errors with a half sine wave shock of 2G with 11 millisecond duration Package Shock System operational after a 30 free fall cosmetic damage may be present 20KV per Intel Environmental Test Specification 8 88 STL2 Server Board TPS Regulatory and Integration Information 8 3 2 System Environmental Testing The system environmental tests include the following Temperature Operating and Non Operating e Humidity Non Operating e Shock Packaged and Unpackaged e Vibration Packaged and Unpackaged AC Voltage Freq am
51. as a multi function device Internally each controller is identical capable of operations using either 16 bit SE or LVD SCSI providing 40 MBps Ultra wide SE or 160 MBps Ultra160 The STL2 server board provides the ability to disable the embedded Ultra160 SCSI Controller in the BIOS Setup option When disabled it will not be visible to the operating system STL2 Server Board TPS STL2 Server Board Architecture Overview Table 2 2 SCSI Transfer Speeds SCSI Port Asynchronous Fast 5 Fast 10 Fast 20 Fast 40 Fast 80 Ultra160 SE ves wooo zl yes yes Les fno tvo ves yes yes ves ue tyes In the STL2 server board implementation channel A provides a 68 pin 16 bit LVD Ultra160 SCSI interface Channel B provides a 68 pin 16 bit Single Ended Ultra Wide SCSI interface Each controller has its own set of PCI configuration registers and SCSI I O registers As a PCI 2 1 2 2 bus master the AIC 7899 supports burst data transfers on PCI up to the maximum rate of 133 MBps using on chip buffers Refer to the AIC 7899 PCI Dual Channel SCSI Multi Function Controller Data Manual for more information on the internal operation of this device and for descriptions of SCSI I O registers 2 4 1 1 1 AIC 7899 Supported PCI Commands The AIC 7899 supports PCI commands as shown in the following table Table 2 3 Embedded SCSI Supported PCI Commands AIC 7899 Support C BE 3 0 _L Command Target Master Memory Write Notes
52. ays the SEL area cleared 3h All Event Logging Disabled Monitor for the entire BMC has been disabled System Event Oh System Reconfigured Setup change has occurred OEM System Boot Event Hard Cold reset has been issued Reset Critical Interrupt Dump switch has been activated Module Board 15h CPU Terminator Missing CPU Terminator is not mounted correctly System Boot Initiated User requested PXE boot PXE Network Booted Automatic boot to diagnostic When the maintenance Utility Booted Boot Error No bootable media Boot Media does not exist PXE Server not found PXE Server is not found C boot completed ESM Pro installed OS has been booted PXE boot completed PXE boot for the express server is finished not supported Diagnostic boot completed Maintenance Utility has been booted not supported 3 26 STL2 Server Board TPS Server Management Sensor Type Sensor Type Sensor Specific Code HE 04h CD ROM boot completed The server has been booted not supported OS Critical Stop 20h Stop during OS load OS stalled during startup Initialization OS stalled during startup System ACPI Power SO GO Working DC is ON State S1 sleeping with system H W S1 Sleep State amp processor context Maintained S4 non volatile sleep S4 Sleep State suspend to disk S5 G2 soft off DC is OFF G3 Mechanical Off AC is OFF Sleeping cannot differentiate SUSC OS has been asserted between S1 S3 without the ins
53. ble host system s refer to Intel s Server Builder website or contact your local Intel representative FCC Class A Title 47 of the Code of Federal Regulations Parts 2 and 15 Subpart B pertaining to unintentional radiators USA ICES 003 Class A Interference Causing Equipment Standard Digital Apparatus Class A including CRC c 1374 Canada CISPR 22 Limits and methods of measurement of Radio Interference Characteristics of Information Technology Equipment International VCCI Class A Implementation Regulations for Voluntary Control of Radio Interference by Data Processing Equipment and Electronic Office Machines Japan EN55022 Limits and methods of measurement of Radio Interference Characteristics of Information Technology Equipment Europe EN55024 Generic Immunity Standard currently compliance is determined via testing to IEC 801 2 3 and 4 Europe 89 336 EEC Compliance to EU EMC Directive via EN55022 amp EN55024 BSMI CNS13438 Class A Taiwan EMC Regulations based on CISPR 22 C tick AS NZS 3548 Australia amp New Zealand EMS Regulations based on CISPR 22 This server board assembly has the following required certification type markings e UL Joint Recognition Mark Consists of small c for Canada followed by a stylized backward UR and followed by a small US USA on component side Revision 1 0 8 85 Regulatory and Integration Information STL2 Server Board TPS e Intel s UL File
54. cated at the top of the screen It displays the various major menu selections available to the user e Main Menu e Advanced Menu Security Menu Revision 1 0 4 33 Basic Input Output System BIOS STL2 Server Board TPS e System Menu s Boot Menu s Exit Menu These and associated submenus are described below 4 2 2 4 Main Menu Selections The following tables describe the available functions on the Main Menu and associated submenus Default values are highlighted Table 4 2 Main Menu Selections System Time Sets the system time hour minutes seconds on 24 hour clock MM DD YYYY Sets the system date month day year Diskette A 1 44 1 25 MB 3 5 Disabled Selects the diskette type Note 1 25 MB 3 5 inch references a 1024 byte sector Japanese media format To support this type of media format requires a 3 5 inch 3 mode diskette drive Diskette B 1 44 1 25 MB 3 5 Disabled Selects the diskette type Note 1 25 MB 3 5 inch references a 1024 byte sector Japanese media format To support this type of media format requires a 3 5 inch 3 mode diskette drive 6 Seconds BIOS before any accesses 9 Seconds 12 Seconds 15 Seconds 21 Seconds 30 Seconds Primary Master Displays IDE device selection Enters submenu if selected Primary Slave Displays IDE device selection Enters submenu if selected submenu if selected Language English US Selects which language BIOS French displays German Note This
55. cedccececeisheiseieteieeecenaveuedeniceneelavaredectieeieenene 5 68 5 2 2 Auxilary ATX Power Connector P34 EEN 5 68 5 2 3 C TEE 5 68 5 2 4 System Fan Connectors P29 P27 BI 5 69 5 2 5 Processor Connectors P12 P36 ansuakenenmnkk esken sacblens tekne ikm 5 69 STL2 Server Board TPS Table of Contents 52 0 Speaker Connector PIT EE 5 69 5 21 Speaker Connector LE 5 69 5 2 8 Diskette Drive Connector PD320 ENEE 5 70 5 29 SVGA Video E 5 70 5 2 10 Keyboard and Mouse CGonnechors ANNE 5 71 Hel Fall Pl ae 5 71 5 2 12 Serial Ports COM1 and COM ENNEN 5 71 5 2 13 RJ45 LAN G nnector mes r mauriuaurasinhuvn ruster Eege re Dee 5 72 52 14 Ee EE 5 72 5 215 Ultra SCS LOM EGO PY ee 5 73 5 2 16 Uliral 60 SCSI Connector P8 deed ees 5 73 5217 IDE Connector P1Y Luske eres 5 74 5218 32 BI PCUCOMMECIOR e Eege Eege 5 75 5219 64 Bit PCI Connector eee added 5 76 5 2 20 Front Panel 24 pin Connector Pinout D331 5 77 6 Power Consumption cies heh ee ee eee 6 81 6 1 Calculated Power Consumption iaiuisksuatuisstddnaninanngaudkdnvdtenie 6 81 6 2 Measured Power Consumption ENNEN 6 82 7 Mechanical Specifications ec ciesiccissesscececedeccscesancacieececesazevasecansecccensesavacsans ccccntesevessantaceess 7 83 8 Regulatory and Integration Information rnnnvvvvnnnnnnnnnnnnnnnnvnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnen 8 85 8 1 Regulatory Compliance EE 8 85 8 2 Installation Instructions icc sc 2ex0sge ectgiekd ees SEENEN AEEE ENEE e 8 86 8
56. e BIOS 6 0 250A is the current BIOS revision level loaded on the system Note Press the Esc key to see the diagnostic messages Note The BIOS Revision Level stated in the example might not reflect the actual BIOS setting in any particular system 4 7 2 BMC Revision Level Identification During system POST which runs automatically when the system is powered on system diagnostics are run Following the memory test diagnostic several messages appear to inform the user that the mouse was detected and system configuration data updated The BMC messages follow these To identify the system s current BMC revision level see the following example Base Board Management Controller Device ID 01 Device Revision 00 IPMI Version 1 0 Firmware Revision 2 00 60 Self Test Result In the example above Firmware Revision 00 60 is the current BMC revision level loaded on the system Note Press the Esc key to see the diagnostic messages Note The Firmware Revision level in the example might not reflect the actual BMC revision level in any particular system Revision 1 0 4 55 Basic Input Output System BIOS STL2 Server Board TPS 4 8 Adaptec SCSI Utility The Adaptec SCSI Utility detects the SCSI host adapters on the server board The Adaptec SCSI Utility is used to e Change default values e Check and or change SCSI device settings that may conflict with those of other devices in the server 4 8 1 Running
57. each There are 16 64 KB blocks The 8 bit flash memory provides 1024K x 8 of BIOS and nonvolatile storage space The flash device is directly addressed as 8 bit ISA memory For more information see the 5 Volt FlashFile Memory 28F008SA x8 Datasheet 2 5 3 External Device Connectors The external I O connectors provide support for a PS 2 compatible mouse and keyboard an SVGA monitor two serial port connectors a parallel port connector a LAN port and two USB connections 2 6 Interrupt Routing The STL2 server board interrupt architecture implements two I O APICs and two PICs through the use of the integrated components in the IB6566 South Bridge component The STL2 server board interrupt architecture allows first and second PCI interrupts to be mapped to compatible interrupt through the PCI Interrupt Address Index Register UO Address OCOOh in the IB6566 South Bridge The STL2 server board supports three interrupt modes s PIC Mode e Virtual Wire Mode e Symmetric Mode The 1B6566 South Bridge uses integrated logic to map 16 PCI interrupts to EISA ISA In default or Extended APIC configurations each PCI interrupt can be independently routed to one of the 11 EISA interrupts The interrupt mapping logic for PCI interrupts is disabled when the make bit in the corresponding I O APIC redirection table entry is disabled clear This interrupt routing mechanism allows a clean transition from PIC mode to an APIC during operating system b
58. edirection Resource allocation support BIOS setup is embedded in flash ROM and provides the means to configure on board hardware devices and add in cards For more information refer to Section 4 2 Setup Utility 4 1 2 Flash Update Utility The system BIOS and the setup utility are resident in partitioned flash ROM The device is in circuit reprogrammable On the STL2 platform 1 MB of flash ROM is provided The STL2 BIOS does not support a SecureBlOS feature like some server products from Intel This is because the addition of SecureBlOS increases boot time and complexities and does not provide compelling benefits for the STL2 platform The Phoenix Phlash Utility may be used to reprogram the BIOS operational code located in the flash ROM A BIOS image is provided on a diskette in the form of a binary file that is read by the Phoenix Phlash Utility Baseboard revisions may create hardware incompatibilities and may require different BIOS code 4 1 2 1 System Flash ROM Layout The flash ROM contains system initialization routines BIOS strings BIOS Setup and run time support routines The exact layout is subject to change as determined by Intel A 16 KB user block is available for user ROM code and another 128KB block is available for custom logos The flash ROM also contains compressed initialization code for on board peripherals such as SCSI NIC and video controllers The BIOS image contains all the BIOS components at appropriate loca
59. ent functions with ACPI control registers built in The IB6566 South Bridge provides a number of GPIO pins 2 3 Memory The STL2 server board contains four 168 pin DIMM sockets Memory is partitioned as four banks of registered SDRAM DIMMs each of which provides 72 bits of noninterleaved memory 64 bit main memory plus ECC The STL2 server board supports up to four 3 3V registered ECC SDRAM DIMMs that are compliant with the JEDEC PC133 specification A wide range of DIMM sizes are supported including 64 MB 128 MB 256 MB 512 MB and 1GB DIMMs The minimum supported memory configuration is 64 MB using one DIMM The maximum configurable memory size is 4 GB using four DIMMs Note Neither PC 100 DIMMs nor non ECC DIMMs can be used DIMMs may be installed in one two three or four DIMM slots and must be populated starting with the lowest numbered slot and filling the slots in consecutive order Empty memory slots between DIMMs are not supported Although the STL2 server board architecture allows the user to mix various sizes of DIMMS Intel recommends that module and DRAM vendors not be mixed in the same server system Revision 1 0 2 7 STL2 Server Board Architecture Overview STL2 Server Board TPS System memory begins at address 0 and is continuous flat addressing up to the maximum amount of DRAM installed exception system memory is noncontiguous in the ranges defined as memory holes using configuration registers The server board
60. er Board Measured Power Consumption 6 82 STL2 Server Board TPS Mechanical Specifications 7 Mechanical Specifications The diagram on the following page shows the mechanical specifications of the STL2 server board All dimensions are in inches Connectors are dimensioned to pin 1 Revision 1 0 7 83 Mechanical Specifications STL2 Server Board TPS lt This page intentionally left blank gt 7 84 STL2 Server Board TPS Regulatory and Integration Information 8 Regulatory and Integration Information 8 1 Regulatory Compliance The STL2 server board complies with the following safety standard requirements Table 8 1 Safety Regulations Regulation Title UL 1950 CSA950 Bi National Standard for Safety of Information Technology Equipment including Electrical Business Equipment USA and Canada EN 60950 The Standard for Safety of Information Technology Equipment including Electrical Business Equipment European Community IEC60 950 The Standard for Safety of Information Technology Equipment including Electrical Business Equipment International EMKO TSE 74 SEC 207 94 Summary of Nordic deviations to EN 60950 Norway Sweden Denmark and Finland EU Low Voltage Directive 73 23 ECC Compliance to EU LV Directive via EN60 950 IEC 60950 The STL2 server board has been tested and verified to comply with the following EMC regulations when installed in a compatible Intel host system For information on Intel compati
61. ere to the following requirements e To allow detection by BIOS and protection from run time memory managers the user binary must have an option ROM header i e 55AAh size The system BIOS performs a scan of the user binary area at predefined points during POST Mask bits must be set within the user binary to inform the BIOS which entry points exist 4 44 STL2 Server Board TPS Basic Input Output System BIOS The system state must be preserved by the user binary all registers including extended and MMX stack contents and nonuser binary data space etc The user binary code must be relocatable The user binary is located within the first 1 MB of memory The user binary code must not make any assumptions about the value of the code segment The user binary code is always executed from RAM and never from flash The user binary must not hook critical interrupts must not reprogram the chip set and must not take any action that affects the correct functioning of the system BIOS The user binary ROM must be checksummed The checksum byte must be placed in the last byte position of the 16K ROM The BIOS copies the user binary into system memory before the first scan point If the user binary reports that it does not contain run time code it is located in conventional memory 0 640 KB Reporting that the user binary has no run time code has the advantage of not using limited option ROM space therefore more option
62. essors and the ServerWorks ServerSet III LE chipset The STL2 server contains embedded devices for video NIC SCSI and IDE The STL2 server board also provides support for server management and monitoring hardware and interrupt control that supports dual processor and PC AT compatible operation The section provides an overview of the following STL2 subsystems e Pentium Ill processor subsystem e SeverWorks ServerSet III LE chipset Memory e PCI Subsystem e Chipset Support Components BMC server management controller 2 1 Intel Pentium Ill Processor Subsystem The STL2 server board is designed to accommodate one or two Intel Pentium III processors for the PGA370 socket The Pentium III processor for the PGA370 socket is the next member of the P6 family in the Intel IA 32 processor line This processor uses the same core and offers the same performance as the Intel Pentium III processor for the SC242 connector but utilizes a new package technology called flip chip pin grid array or FC PGA This package utilizes the same 370 pin zero insertion force socket PGA370 used by the Intel Celeron processor The STL2 server board utilizes Pentium III PGA370 socket processors which interface with the front side bus at 133 MHz 2 1 1 Supported Processor Types The table below summarizes the processors that are planned to be supported on the STL2 server board Table 2 1 STL2 Server Board Supported Processors FSB Frequency 93
63. ette Insert the blank formatted floppy diskette in the floppy drive 4 From a MS DOS prompt or from the MS DOS prompt window run the crisdisk bat file from the directory you created on your hard drive Follow the instructions on the screen to create the BIOS recovery floppy diskette Power off the STL2 system unplug the power cord and remove the chassis panel Remove the spare jumper from pins 11 12 on jumper block 1J15 Reinstall the jumper on pins 9 10 BIOS Recovery of jumper block 1J15 Insert the BIOS recovery floppy diskette into the diskette drive Reinstall the chassis panel plug in the power cord s and power on the system MW 4 Dm 0 The screen will remain blank while the BIOS Recovery is performed A number of beeps will occur during the BIOS update The floppy drive access light will not turn off when the BIOS recovery is completed Allow four minutes for the BIOS recovery to complete If a POST card is installed in a PCI slot during the BIOS recovery you can tell that the BIOS recovery is complete when code EC is displayed When the BIOS Recovery is complete itis safe to power off the system 11 Power off the system unplug the power cord s and remove the chassis panel 12 Remove the BIOS Recovery jumper from pins 9 10 and store the jumper on pins 11 12 13 Replace the chassis panel plug in the power cord s and power on the system 14 Perform a CMOS clear following the BIOS recovery 5 1 1
64. event mode even if SCSI is available for a different mode event An error occurred at fan sensors 04h Physical Security 05h SE Drive Bay Intrusion Front cover has been opened or closed Oth Oth 03h Processor area intrusion Side Chassis cover has been opened or closed 04h System has been LAN cable has unplugged from LAN been plugged Revision 1 0 3 25 Server Management STL2 Server Board TPS Sensor Type Sensor Type Sensor Specific Code Offset Platform Security 06h 00h Secured Mode Violation Power sleep switch has been Violation Attempt Attempt activated while in Secure Mode 3h Pre boot Password Violation Bad Password at PXE Boot network boot Password Processor 07h IERR CPU IERR has occurred Thermal Trip CPU Thermal Trip has occurred FRB1 BIST Failure BIST Error has occurred 04h FRB3 Processor FRB3 Timeout has been detected Startup Initialization failure CPU didn t start Processor disabled A processor has been Disabled Memory OCh Correctable ECC ECC 1 bit error occurred Uncorrectable ECC ECC 2 bit error occurred POST Memory Resize 0Eh POST Memory Resize Displays the total amount of memory after memory failure POST Error OFh POST Error POST Error occurred Event Logging 00h Correctable Memory Error Displays ECC single bit error Disabled Logging Disabled monitoring disabled th Event Type Logging Disabled Monitoring of a certain event type has been disabled 2h Log Area Reset Cleared Displ
65. fe sustaining applications Intel may make changes to specifications and product descriptions at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them This document contains information on products in the design phase of development Do not finalize a design with this information Revised information will be published when the product is available Verify with your local sales office that you have the latest datasheet before finalizing a design The STL2 platform may contain design defects or errors known as errata which may cause the product to deviate from published specifications Current characterized errata are available on request Copyright O Intel Corporation 2000 Other brands and names are the property of their respective owners STL2 Server Board TPS Table of Contents Table of Contents ST e ET sd Lee eee 1 1 EN VR Cie see 1 1 1 2 e Ee 1 1 1 3 STL2 Server Board Feature Overview ENNEN 1 1 1 4 STL2 Server Board Block Diagram uussamvaagsenserauaisGeranautesmnueneeeen 1 2 2 STL2 Server Board Architecture Overview rrrnnnnnnnnnnnnnnvnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnvnnnnnnn 2 5 2 1 Intel Pentium Ill Processor Subsystem AEN 2 5 1 1 1 Supported Processor Tvpes
66. filler or JMP to a RETF JMP ErrRet i JMP ErrRet JMP ErrRet JMP ErrRet 4 5 2 2 Scan Point Definitions The table below defines the bitmap for each scan point indicating when the scan point occurs and which resources are available RAM stack binary data area video and keyboard Table 4 21 User Binary Area Scan Point Definitions Near pointer to the user binary extension structure mask bit is O if Not applicable Not applicable this structure is not present Instead of a jump instruction the scan address offset 5 contains an OCB followed by a near pointer This scan occurs minedas ane after video initialization KK e This scan occurs immediately before video initialization This scan occurs on POST error On entry BX contains the 10h Yes Yes number of the POST error This final scan occurs immediately prior to the INT 19 for normal 20h Yes Yes boot and allows one to completely circumvent the normal INT 19 boot if desired This scan occurs immediately before the normal option ROM scan This scan occurs immediately following the option ROM area 4 46 STL2 Server Board TPS Basic Input Output System BIOS Table 4 22 Format of the User Binary Information Structure Bit 0 1 if mandatory user binary 0 if not mandatory If a user binary is mandatory it will always be executed If a platform supports a disabling of the user binary scan through Setup this bit will override Setup setting Bit 1 1 if runtime p
67. h fire or damage the insulation that separates hazardous AC line circuitry from low voltage user accessible circuitry and result in a shock hazard If the load drawn by a module cannot be determined by the markings and instructions supplied with the module contact the module supplier s technical support 8 2 4 Place Battery Marking on Computer There is insufficient space on this server board to provide instructions for replacing and disposing of the battery The following warning must be placed permanently and legibly on the host computer as near as possible to the battery WARNING Danger of explosion if battery is incorrectly replaced Replace with only the same or equivalent type recommended by the manufacturer Dispose of used batteries according to the manufacturer s instructions Revision 1 0 8 87 Regulatory and Integration Information STL2 Server Board TPS 8 2 5 Use Only for Intended Applications This product was evaluated for use in ITE computers that will be installed in offices schools computer rooms and similar locations The suitability of this product for other product categories other than ITE applications such as medical industrial alarm systems and test equipment may require further evaluation 8 2 6 Installation Precautions During the installation and testing of the board the user should observe all warnings and cautions in the installation instructions To avoid injury be aware of the following Sh
68. iltering e Mounting grounding and bonding requirements e Keying connectors when mismating of connectors could be hazardous If the host chassis power supply and other modules have not passed applicable EMC certification testing before integration EMC testing must be conducted on a representative sample of the newly completed computer 8 2 2 Ensure Host Computer and Accessory Module Certifications The host computer and any added subassembly such as a board or drive assembly including internal or external wiring should be certified for the region s where the end product will be used Marks on the product are proof of certification Certification marks are as follows 8 86 STL2 Server Board TPS Regulatory and Integration Information 8 2 2 1 In Europe The CE marking signifies compliance with all relevant European requirements If the host computer does not bear the CE marking obtain a supplier s Declaration of Conformity to the appropriate standards required by the European EMC Directive and Low Voltage Directive Other directives such as the Machinery and Telecommunications Directives may also apply depending on the type of product No regulatory assessment is necessary for low voltage DC wiring used internally or wiring used externally when provided with appropriate overcurrent protection Appropriate protection is provided by a maximum 8 Amp current limiting circuit or a maximum 5 Amp fuse or positive temperature coefficient P
69. isplay only Once set this can be disabled by setting it to a null string or by clearing password jumper on system board User Password is Clear Display only Once set this can be disabled by setting it to a null string or by clearing password jumper on system board Set Supervisor Password Press Enter Supervisor password controls access to the setup utility When the lt Enter gt key is pressed the user is prompted for a password press ESC key to abort Once set this can be disabled by setting it to a null string or by clearing password jumper on system board Set User Password Press Enter When the lt Enter gt key is pressed the user is prompted for a password press ESC key to abort Once set this can be disabled by setting it to a null string or by clearing password jumper on system board Password on Boot Disabled Disables or enables password entry on boot Enabled Fixed Disk Boot Sector Normal Write protects boot sector on hard disk Write Protect Diskette Access User Controls access to diskette drives Supervisor Secure Mode See Secure Mode Submenu Submenu can only be entered if supervisor and user password is set Power Switch Mask Masked Determines whether power switch will function Unmasked from front panel Option ROM Menu Mask Unmasked Determines whether on board SCSI Option ROM Masked will allow the user to enter adapter configuration with lt CTRL gt A Revision 1 0 4 39 Basic Input Output System BIOS
70. lable minus one This field is equal to seven since eight CMOS bits are available The 12 least significant bits define the position of the CMOS bit in the real time clock RTC This is a bit address rather than a byte address The CMOS byte location is 1 8th of the 12 bit number and the remainder is the starting bit position within that byte For example if the 12 bit number is 0109h user binary can use bit 1 of CMOS byte 0108h 8 or 021h It should be noted that the bits available to the user binary may span more than one byte of CMOS i e a value of 07084h indicates that the upper nibble of byte 10h and the lower nibble of byte 11h are reserved for the user binary Revision 1 0 4 45 Basic Input Output System BIOS STL2 Server Board TPS The following code fragment shows the header and format for a user binary db 55h OAAh 20h 16KB USER Area MyCode PROC FAR MUST be a FAR procedure db CBh Far return instruction db 04h Bit map to define call points a 1 in any bit specifies that the BIOS is called at that scan point in POST db CBh First transfer address used to point to user binary extension structure dw Word Pointer to extension structure dw 0 Reserved JMP ErrRet This is a list of 7 transfer addresses one for each JMP ErrRet bit in the bitmap 5 Bytes must be used for each JMP Start JMP to maintain proper offset for each entry Unused entry JMP s should be filled with 5 byte
71. mode Bi directional EPP ECP DMA1 ECP DMA3 Diskette Controller Disabled Disables Enables the floppy disk controller Enabled Disabled Disabled prevents any installed PS 2 Enabled mouse from functioning but frees up Auto Detect IRQ12 Enabled forces the PS 2 mouse port to be enabled regardless if a mouse is present Auto Detect enables the PS 2 mouse only if present OS Controlled is displayed if the OS controls the mouse SCSI Controller Disabled Disables Enables on board SCSI controller Enabled Frees resources LAN Controller Disabled Disables Enables on board LAN controller Enabled Frees resources VGA Controller Enabled Disables Enables on board Video Disabled controller Frees resources USB Controller Disabled Enables Disables on board USB controller Enabled Frees resources Revision 1 0 4 37 Basic Input Output System BIOS STL2 Server Board TPS Table 4 8 PCI Device Submenu Selections Feature Choices or Display Only Description User Setting PCI IRQ1 through PCI IRQ14 Disabled Specify which PIC IRQ a certain PCI IRQ Auto Select maps to IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ9 IRQ10 IRQ11 IRQ12 Table 4 9 Option ROM Submenu Selections Choices or Description Display Only EN Enabled Disables Enables option ROM expansion for the on board Disabled SCSI option ROM This must be enable if a boot device is connected to the on board device Onboard LAN Enabled Disables
72. ne ong wo Shor beeps on checksum are faa Sewon mm rac_ Setup PowerManagenent SSCS BE __ Enable hardvareiierupis SSCS AD femes pa Che ay eck S ERR WT Ip AA Sean torF2key stoke SOS PRC eer ST ET Ieren ST s B2 POST done prepare to boot Operating Stew 85 __ Display MatiBoctmena SSCS B6 Check password passwords checked before opion ROM sen rer AoPiinaizaton Be __ Ceargibalcescrpiortabe SSCS BC Ceearparty checkers SSCS aE __ Gear screen osten SSCS SCT Geekvusandbadupemndes foo Tatodestwin Ne OOOO roa Foreedshatdows SSS ST Tree SOS DO Tester SSCS ST oomme De Pendnginemuptemor SOS Ds mtaizeopionoMemr Ds Smusemnemr O DA Extended BiockWave Po eom O Revision 1 0 4 51 Basic Input Output System BIOS STL2 Server Board TPS Table 4 25 Recovery BIOS Port 80 Codes Reason Initialize chip set O el mee ee e mepes O CP E0 E3 ooo Initialize timer E4 ooo Initialize system I O E6 Validate checksum Go to BIOS E7 E8 Eo a Peompiatominialeaten OO meere OOOO c meem OOOO mme GT Ieper SOS Fa EC m E5 ooo Check forced recovery boot m D m el nm CH 7 nm 6 Boot mini DOS Boot full DOS OT 7 N 4 6 2 POST Error Codes and Messages The following table defines POST error codes and their associated messages The BIOS prompts the user to press a key in case of a serious
73. nector le EE 5 73 Table 5 21 Ultra160 SCSI Connector ees Ss Setter das eet ee edd ede Geta et 5 73 Table 5 22 1DE G nnscbrPnodaaaaa4r4aduaaauasdasdtmdrandrtduddaddriisdude 5 74 Table 5 23 32 Bit PCI Connector Pinout testen eet ee edd ee 5 75 Table 5 24 64 Bit PCI Connector Pinout EE 5 76 Table 5 25 Front Panel 24 pin Connector Pinot Auen 5 77 Table 6 1 STL2 Server Board Calculated Power Consumpton 6 81 Table 6 2 STL2 Server Board Measured Power Consumpton 6 82 Table 8 1 Safety Regulations EE 8 85 Table 8 2 Office System Environment Gumman ke 8 88 viii STL2 Server Board TPS Introduction 1 Introduction 1 1 Purpose This document provides an architectural overview of the STL2 server board including the board layout of major components and connectors and an overview of the server board s feature set 1 2 Audience This document is written for technical personnel who want a technical overview of the STL2 server board Familiarity with the personal computer Intel server architecture and the PCI local bus architecture is assumed 1 3 STL2 Server Board Feature Overview The STL2 server board provides the following features e Dual Intel Pentium III processor support Support for one or two identical Intel Pentium III processors for the PGA370 socket which utilizes a new package technology called the Flip Chip Pin Grid Array FC PGA package One embedded VRM for support of the primary processor and one
74. nel plug in the power cord s and power on the system o mm Jm mF Y 0 To specify a new password run the BIOS Setup Utility as described earlier in this section 5 1 1 2 Clearing CMOS Clear CMOS as follows Power off the system unplug the power cord and remove the chassis panel 2 Use needle nose pliers or your fingers to remove the spare jumper from pins 11 12 on jumper block 1J15 3 Position the jumper over pins 1 2 on jumper block 1J15 4 Replace the chassis panel plug in the power cable s and power on the system 5 64 STL2 Server Board TPS Jumpers and Connectors 5 After POST completes power down the system unplug the power cable s and remove the chassis panel Remove the jumper from pins 1 2 and store the jumper on pins 11 12 Replace the chassis panel and connect system cables Power on the system press F2 at the prompt to run the BIOS Setup utility and select Get Default Values at the Exit menu 5 1 1 3 Perfoming a BIOS Recovery Boot In the event of BIOS corruption the following procedure may be used to perform a BIOS Recovery 1 Obtain the BIOS update file package from Intel s iBL or http support intel com web site 2 A file called crisis zip is one of the files included with each STL2 BIOS release file package Unzip the crisis zip file to a directory on your hard drive 3 Obtain a blank formatted floppy diskette the floppy diskette should not be a bootable DOS disk
75. nnnnnnnnnnnnnnnnevnnnnnnnnnnnnnnnneen 4 29 Aide BIOS OVE EE 4 29 21 SVSEM BLOS sanse eee 4 30 4 1 2 Flash Update Utility aar 4 30 42 gt Setup Utility EE 4 31 4 2 1 Configuration Utilities Cvernvlew ENNEN 4 31 4 2 2 Setup Utility Operation WEE 4 31 43 CMOS Memory DelnitiOn 4 22 cifaan ea decane ee SES 4 42 AA CMOS Default Override mu na edmnrgstak me dkae EEN fa egoeimikamet teten 4 43 45 E RE ele DR EE 4 43 4 5 1 Loading the System BIOS EE 4 43 GT Re ee e E 4 44 4 5 3 Language DEES eege skogs ee ed ae ee 4 47 4 5 4 Recovery Mode ee eege edd Eege eegen 4 47 4 6 Error Messages and Error Codes AEN 4 48 261 POST 00068 Lardal 4 48 4 6 2 POST Error Codes and Messages ENNEN 4 52 4 7 Identifying BIOS and BMC Revision Level 4 55 4 7 1 BIOS Revision Level Identification AAA 4 55 4 7 2 BMC Revision Level Identification rrrrnnnnnnnnnnnnnrrrrnnnnnnnrnnnnnnrrrnnnnnnnnrrrnnnnrrnnnnn 4 55 4 8 Adaptec SCSI LN gesuegt ege eege Ee 4 56 4 6 41 RUNDINGANE SCS RE 4 56 4 8 2 Adaptec SCSI Utility Configuration Settings rrnvrrrrnnnnnnnnnnnnnvrrrrnnnnnnnrnnnnnnrrnnnnn 4 56 4 8 3 Exiting Adaptec SCSI Utility ee 4 58 5 Jumpers and Connectors eiesrge iegegee eege eege deeg geed nenna 5 61 51 Jumper ee E 5 63 5 1 1 Setting CMOS Password Clear Jumper Block 18 5 63 5 1 2 Setting Configuration Jumper Block 714 ENNEN 5 66 5 1 3 Setting Configuration Jumper Block GA 5 67 62 Komedie 5 67 5 2 1 Main ATX Power Connector P33 csiciccc
76. nt processing of receive data e On chip counters for network management e Autodetect and autoswitching for 10 or 100 Mbps network speeds Support for both 10 Mbps and 100 Mbps networks full or half duplex capable with back to back transmit at 100 Mbps Revision 1 0 2 11 STL2 Server Board Architecture Overview STL2 Server Board TPS e Integrated physical interface to TX magnetics The magnetics component terminates the 100Base TX connector interface A flash device stores the network ID Support for Wake on LAN WOL 2 4 2 2 Video Controller The STL2 server board includes an ATI Rage IIC video controller 4 MB video SGRAM and support circuitry for an embedded SVGA video subsystem The Rage IIC 64 bit VGA Graphics Accelerator contains a SVGA video controller clock generator BitBLT engine and RAMDAC Two 512K x 32 SGRAM chips provide 4 MB of 10ns video memory The SVGA subsystem supports a variety of modes up to 1280 X 1024 resolution and up to 16 7 Million colors It also supports analog VGA monitors single and multi frequency interlaced and non interlaced up to 100 Hz vertical refresh frequency The STL2 server board provides a standard 15 pin VGA connector and external video blanking logic for server management console redirection support 2 4 2 2 1 Video Controller PCI Signals The Rage IIC supports a minimal set of 32 bit PCI signals because it never acts as a PCI master As a PCI slave the device requires
77. ons for a configurable parameter Selects an option SC The following table shows the normal settings for the Adaptec SCSI Utility and provides a place to record any changes made to these settings Table 4 27 Adaptec SCSI Utility Setup Configurations ee 0e Display Only SCSI Bus Interface Definitions Res Host Adapter SCSI ID amer Boor SOSO Boot LUN Ware Mi Initiate Wide Negotiation Send Start Unit Command Include in BIOS Scan Cep Reset SCSI Bus at IC Initialization Enabled Display lt Ctrl A gt Messages During BIOS Initialization Enabled Extended BIOS Translation for DOS Drives gt 1 Gbyte Enabled Verbose Silent Mode Verbose Host Adapter BIOS Configuration Utility Reserves BIOS Enabled Space Domain Validation Enabled Support Removable Disks Under BIOS as Fixed Disks Disabled BIOS Support for Int13 Extensions Enabled Notes 1 No effect if BIOS is disabled Revision 1 0 4 57 Basic Input Output System BIOS STL2 Server Board TPS 2 Do not remove media from a removable media drive if it is under BIOS control 4 8 3 Exiting Adaptec SCSI Utility To exit the Adaptec SCSI Utility the user presses the Esc key several times until a message prompts him her to exit If changes have been made the user is prompted to save them before exiting 4 58 STL2 Server Board TPS Basic Input Output System BIOS lt This page intentionally left blank gt Revision 1 0 4 59 STL2 Server Board TPS J
78. oot 2 6 1 Default I O APIC The 1B6566 South Bridge integrates a 16 entry I O APIC which is used to distribute 16 PCI interrupts 2 6 2 Extended I O APIC An additional 16 entry I O APIC is integrated in the IB6566 South Bridge to distribute EISA ISA interrupts This additional I O APIC is enabled only when the IB6566 South Bridge is configured to the Extended APIC configuration Revision 1 0 2 17 STL2 Server Board Architecture Overview STL2 Server Board TPS IRQO INTR gt IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 IRQS SCI IRQ10 IRQ1 1 IRQ12 IRQ13 IRQ14 IRQ15 PCIIRQO PCI PCIIRQI Interrupt PCIIRQ2 Router PCIIRQ3 IRQ3 PCIIRQ4 IRQ4 PCIIRQ5 IRQS PCIIRQ6 IRQ6 PCIIRQ7 IRQ7 PCIIRQ8 PCIIRQ9 IRQ9 PCIIRQ10 IRQ10 PCIIRQ11 IRQ11 PCIIRQ12 IRQ12 PCIIRQ13 PCIIRQ14 IRQ14 PCIIRQ15 IRQ15 Figure 2 3 STL2 Baseboard Interrupt Routing Diagram PIC mode 2 18 STL2 Server Board TPS STL2 Server Board Architecture Overview Timer IRQO Keyboard IRQ1 Cascade IRQ2 Serial Port2 ISA IRQ3 Serial Port1 ISA IRQ4 ISA IRQ5 Floppy ISA IRQ6 Parallel ISA IRQ7 RTC IRQ8 SCI ISA IRQQ ISA IRQ10 ISA IRQ11 Mouse ISA IRQ12 Coprocessor Err IRQ13 P IDE ISA IRQ14 Not Used IRQ15 SCSI PORT A PIRQO 16 SCSI PORT B PIRQ1 17 LAN PIRQ2 18 VGA PIRQ3 19 Slot02 INTA PIRQ4 20 Slot03 INTA PIRQ5 21 PIRQ6 22 Slot04 INTA PIRQ7 23 Slot
79. orks ServerSet Ill LE Chipset The ServerWorks ServerSet III LE chipset provides an integrated I O bridge and memory controller and a flexible I O subsystem core PCI targeted for multiprocessor systems and standard high volume servers that are based on the Intel Pentium Ill processor The ServerWorks ServerSet III LE chipset consists of two components e NB6635 North Bridge 3 0LE The NB6635 North Bridge 3 0LE is responsible for accepting access requests from the host processor bus and for directing those accesses to memory or to one of the PCI buses The NB6635 North Bridge 3 0LE monitors the host bus examining addresses for each request Accesses may be directed to a memory request queue for subsequent forwarding to the memory subsystem or to an outbound request queue for subsequent forwarding to one of the PCI buses The NB6635 North Bridge 3 0LE is reponsible for controlling data transfers to and from the memory The NB6635 North Bridge 3 0LE provides the interface for both the 64 bit 66 MHz Revision 2 2 compliant PCI bus and the 32 bit 33 MHz Revision 2 2 compliant PCI bus The NB6635 North Bridge 3 0LE is both a master and target on both PCI buses 1B6566 South Bridge The IB6566 South Bridge controller has several components It can be both a master and a target on the 32 bit 33 MHz PCI bus The 1B6566 South Bridge also includes a USB controller and an IDE controller The IB6566 South Bridge is responsible for many of the power managem
80. p Source Interrupt e AC Surge e Acoustics s ESD Revision 1 0 8 89 Regulatory and Integration Information STL2 Server Board TPS lt This page intentionally left blank gt 8 90 STL2 Server Board TPS Glossary Glossary E FRB EMP Emergency Management Port ESCD Extended System Configuration Data F Field Replaceable Unit HPIB Hot plug Indicator Board IM Intra Module Bus IPMB Intelligent Platform Management Bus FRB Fault Resilient Booting MADP Memory Address and Data Path M Multiple Bit Error M MECC y v N N U Memory Expansion Card Non maskable Interrupt O Operating System P PCI Hot plug PHPC PCI Hot plug Controller P RAMDA Random Access Memory Digital to Analog Converter R SEAN System Setup Utility Universal Serial Bus ZCR Zero Channel RAID S S S R H M 7 B E E SH SM SM S S A T TB M U B B E P S IC M S C E C L U P D S P E C R P E Power Management Event POST Power On Self Test C V M B Revision 1 0 Reference Documents STL2 Server Board TPS Reference Documents ServerWorks ServerSet III LE North Bridge Specification ServerWorks ServerSet III LE South Bridge Specification PCI Local Bus Specification Revision 2 2 USB Specification Revision 1 0 5 Volt Flash File 28F008SAx8 Datasheet AIC 7899 PCI Dual Channel SCSI Multi function Controller Data Manual ATI Rage IIC Technical
81. pecify the functions to perform during the flash process e C Rewrite BIOS e B Rewrite Bootblock e L Clear LOGO area e U Clear user binary e X place hold This file is loaded into the PHLASH program with the b lt bin file gt The disk created by the BIOS EXE program will automatically run phlash s b PLATCXLU BIN command in non interactive mode For a complete list of phlash switches run phlash h Once an update of the system BIOS is complete the user is prompted for a reboot The user binary area is also updated during a system BIOS update User binary can be updated independently of the system BIOS CMOS is cleared when the system BIOS is updated 4 5 2 OEM Customization An OEM can customize the STL2 BIOS for product differentiation The extent of customization is limited to what is stated in this section OEMs can change the BIOS look and feel by adding their own splash screen logo OEMs can manage OEM specific hardware if any by executing their own code during POST by using the User supplied BIOS Code Support 4 5 2 1 User supplied BIOS Code Support A 16 KB region of flash ROM is available to store a user binary The Phoenix Phlash utility allows the OEM or end user to update the user binary region with OEM supplied code and or data At several points throughout POST control is passed to this user binary Intel provides tools and reference code to help OEMs create a user binary The user binary must adh
82. provided in flash for basic system configuration The configuration utilities modify CMOS RAM and NVRAM under direction of the user The BIOS POST routines and the BIOS Plug N Play Auto configuration Manager accomplish the actual hardware configuration The configuration utilities always update a checksum for both areas so that any potential data corruption is detectable by the BIOS before the hardware configuration takes place If data is corrupted the BIOS requests that the user reconfigure the system and reboot 4 2 2 Setup Utility Operation The ROM resident setup utility configures only on board devices The setup utility screen is divided into four functional areas Table 4 1 describes each area Table 4 1 Setup Utility Screen Functional Area Description Keyboard Command Bar Located at the bottom of the screen This bar displays the keyboard commands supported by the setup utility Menu Selection Bar Located at the top of the screen Displays the various major menu selections available to the user The server setup utility major menus are Main Menu Advanced Menu Security Menu System Menu Boot Menu and the Exit Menu Options Menu Each Option Menu occupies the left and center sections of the screen Each menu contains a set of features Selecting certain features within a major Option Menu drops you into submenus Item Specific Help Screen Located at the right side of the screen is an item specific Help screen Revision
83. r 1x 1 GHz 256K processor Memory Four PC133 Registered GB SDRAM DIMMs PCI Connectors 32 bit PCI slots 10W per slot on 5V 64 bit PCI slots 10W per slot 6 06A on 3 3V USB 500mA per connector 1 00A Keyboard Mouse 0 50A SCSI term power Included in board spec fT Fans 3 chassis and 2 1 32A processor Total Current 16 16A 34 0A 1 38A 0 78A Total Power 53 33W 170 0W 16 6W 243 83W Revision 1 0 6 81 Power Consumption STL2 Server Board TPS The total power calculation assumes a system configuration containing dual Pentium III 1 GHz processors with the VRM for both processors supplied by the 5V source four 1 GHz DIMMs all PCI slots containing 10W cards two USB devices keyboard amp mouse three chassis fans and two processor fan heat sinks 6 2 Measured Power Consumption A STL2 FAB 2 server board was configured with dual 866 MHz processors both supplied by the 5V voltage regulation modules VRMs and four 1GB PC133 SDRAM DIMMs Infineon part number HYS72V128320GR The system was configured with Microsoft Windows NT 4 0 Test software utilized during the power consumption measurement consisted of the Hipower test suite used to simulate medium processor activity and the WinMTA memory stress test suite used to simulate high memory activity The STL2 server board measured power consumption including the memory and processor power is listed in the following table Table 6 2 STL2 Serv
84. r Fan 5 65 Connector PCI 5 71 5 72 6 75 Connector Power 5 64 Console Redirect 4 38 4 39 Console Redirection 4 28 4 38 4 39 Controller 1 2 2 8 2 9 2 10 2 12 2 13 2 15 3 21 4 35 4 47 4 50 4 52 Core Component 2 5 D DC to DC converter 2 6 DIMM 1 1 2 7 4 34 4 45 4 51 4 52 5 57 Revision 1 0 Index Index E ECC 1 1 2 7 3 22 3 23 3 24 4 50 8 79 EEPROM 2 9 Emergency Management Port See EMP EMP 3 25 4 51 Environmental Limits 8 82 Error 3 22 3 23 3 24 3 25 4 33 4 34 4 38 4 46 4 50 4 51 4 52 ESM See Enterprise System Management Console 3 24 Ethernet 1 2 2 10 Exit Menu 4 29 4 32 4 40 Fan 3 23 6 75 Fan 2 6 3 22 3 23 5 65 5 73 Fan System 5 65 Fault Resilient Booting See FRB FC PGA 1 1 2 5 2 6 Field Replaceable Unit See FRU Flash ROM 4 28 4 41 4 45 Flip Chip Pin Grid Array 1 1 FRB 3 21 5 62 5 63 Front Panel 3 23 3 24 5 73 Front Panel reset 3 23 3 24 3 25 4 34 4 41 4 47 4 55 5 73 Front Side Bus 1 1 FRU 3 21 4 51 G GPIO 2 7 I PC 3 25 5 64 IB6566 South Bridge 1 1 1 2 2 6 2 7 2 10 2 14 2 15 2 16 2 17 2 20 ICH 2 11 Initialization 3 24 4 38 4 52 4 55 Install 4 48 Intel 82559 1 2 2 10 2 11 2 20 Intel Celeron processor 2 5 Intelligent Platform Management Bus See IPMB Interrupt Controller 2 15 4 47 IPMB 4 51 IRQ 12 2 20 Index ISA 2 14 2 15 2 16 2 17 3 2
85. r enable disable BMC FRB see the above figure for jumper block location The following table lists the factory default settings for jumper block 1L4 5 66 STL2 Server Board TPS Jumpers and Connectors Table 5 4 Jumper Block 1L4 Settings Jumper Position PREGE FEE Closed Disabled Disables FRB Jumper Pin Numbers Side Cover Chassis Intrusion Closed Disabled Disables Chassis Intrusion Sensor sensing Open Enabled Enables Chassis Intrusion sensing ET Front Cover Chassis Intrusion Open Enabled Enables Chassis Intrusion Sensor sensing This jumper may be under as a chassis intrusion switch connector 1 2 3 4 5 6 7 8 9 5 1 3 Setting Configuration Jumper Block 6A Setting the jumpers on system board jumper block 6A enables the user to configure the front cover chassis intrusion sensing Jumper 6A pins 1 2 may also be used as a chassis intrusion switch connector The following table lists the factory default settings for jumper block 6A Table 5 5 Jumper Block 6A Settings Jumper Pin Jumper Position Numbers 2 Front Cover Chassis Open Enabled Enables Chassis Intrusion sensing This Intrusion Sensor jumper may be under as a chassis intrusion switch connector ae Closed Disabled Disables Chassis Intrusion sensing Open Enabled Enables Chassis Intrusion sensing 4 6 No Function Closed Disabled Disables Chassis Intrusion sensing 5 2 Connectors This section provides pin information about the connectors on
86. rent item to the previous value These keys scroll through the values in the associated pick list without displaying the full list F6 Change Value The plus key and the F6 function key are used to change the value of the current menu item to the next value These keys scrolls through the values in the associated pick list without displaying the full list On 106 key Japanese keyboards the plus key has a different scan code than the plus key on the other keyboard but it still has the same effect F9 Setup Defaults Pressing the F9 key causes the following to appear Setup Confirmation Load default configuration now Yes No If Yes is selected and the Enter key is pressed all Setup fields are set to their default values If No is selected and the Enter key is pressed or if the ESC key is pressed the user is returned to where s he was before the F9 key was pressed without affecting any existing values F10 Save and Exit Pressing F10 causes the following message to appear Setup Confirmation Save Configuration changes and exit now Yes NO If Yes is selected and the Enter key is pressed all changes are saved and Setup is exited If No is selected and the Enter key is pressed or the ESC key is pressed the user is returned to where s he was before the F10 key was pressed without affecting any existing values 4 2 2 3 Menu Selection Bar The Menu Selection Bar is lo
87. resence required other than SMM user binary portion SMM user binary will always be present in runtime irrespective of setting of this bit 0 if not required in runtime and can be discarded at boot time Bit 7 2 reserved for future expansion 1 Ofh Reserved for future expansion If this structure is not present bit 0 of the scan point structure is not set the system BIOS assumes that the user binary is not mandatory bit 0 in User Binary Information Structure assumed cleared and it is required in run time bit 1 in User Binary Information Structure assumed set 4 5 2 3 OEM Splash Screen A 128 KB region of Flash ROM is available to store the OEM logo in compressed format The BIOS will contain the standard Intel logo Using the Phoenix Phlash utility this region can be updated with an OEM supplied logo image The OEM logo must fit within 640 X 480 size If an OEM logo is flashed into the system it will override the built in Intel logo Intel supplies utilities that will compress and convert a 16 color bitmap file into a logo file suitable for Phoenix8 Phlash 4 5 3 Language Area The system BIOS language area can be updated only by updating the entire BIOS The STL2 platform supports English Spanish French German and Italian Intel provides translations for all the strings in five languages These languages are selectable using Setup 4 5 4 Recovery Mode In the case of a corrupt or an unsuccessful update of
88. resh copy of the BIOS into flash ROM The loaded code and data include the following e On board video BIOS network controller BIOS and SCSI BIOS BIOS Setup utility e User definable flash area user binary area e OEM logo splash screen When running Phoenix Phlash in interactive mode the user may choose to update a particular flash area Updating a flash area takes a file or series of files from a hard or floppy disk and loads it in the specified area of flash ROM Note The Phoenix Phlash utility must be run without the presence of a 386 protected mode control program such as Windows or EMM386 Phoenix Phlash uses the processor s flat addressing mode to update the flash part 4 5 1 Loading the System BIOS The BIOS update utility PHLASH loads a new copy of the BIOS into Flash ROM The loaded code and data include the following e On board Video BIOS and SCSI BIOS BIOS Setup Utility e Quiet Boot Logo Area When running PHLASH in interactive mode the user may choose to update a particular Flash area Updating a flash area loads a file or a series of files from a hard or floppy disk into the specified area of Flash ROM Revision 1 0 4 43 Basic Input Output System BIOS STL2 Server Board TPS To manually load a portion of the BIOS the user must specify which data file s to load The choices include e PLATCBLU BIN e PLATCXLU BIN e PLATCXXX BIN e PLATCXLX BIN e PLATCXXU BIN The last three letters s
89. rks As a PCI bus master the 82559 can burst data at up to 132 MBps This high performance bus master interface can eliminate the intermediate copy step in RX TX frame copies resulting in faster frame processing The network OS communicates with the 82559 using a memory mapped I O interface PCI interrupt connected directly to the ICH and two large receive and transmit FIFOs The receive and transmit FIFOs prevent data overruns or underruns while waiting for access to the PCI bus and also enable back to back frame transmission within the minimum 960ns inter frame spacing The figure below shows the PCI signals supported by the 82559 gt ADB1 0 ak BEB 0LL Ak PAR gt FRAME L lt Troy LU gt Roy LU gt STOP L gt DEVSEL L AG DSEL REQ L a ENT LU a _PCI_CLK _ _ DST L gt PERRL q SERR gt Pci INTL i82559 NIC Figure 2 1 Embedded NIC PCI Signals 2 4 2 1 1 Supported Network Features The 82559 contains an IEEE MII compliant interface to the components necessary to implement an IEEE 802 3 100Base TX network connection The STL2 supports the following features of the 82559 controller e Glueless 32 bit PCI Bus Master Interface Direct Drive of Bus compatible with PCI Bus Specification revision 2 1 2 2 e Chained memory structure with improved dynamic transmit chaining for enhanced performance e Programmable transmit threshold for improved bus utilization e Early receive interrupt for concurre
90. rocessors is done using an independent path between local APICs in each processor and the I O APIC located in the IB6566 South Bridge component 2 1 7 Boxed Processors The Intel Pentium III processor for the PGA370 socket is offered as an Intel boxed processor Intel boxed processors are intended for system integrators who build systems from a server board and standard components 2 1 7 1 Boxed Process Fan Heatsinks The boxed Pentium III processor for the PGA370 socket will be supplied with an unattached fan heatsink that has an integrated clip Clearance is required around the fan heatsink to ensure unimpeded airflow for proper cooling Note that the airflow of the fan heatsink is into the center and out of the sides of the fan heatsink The boxed processor thermal solution must be installed by a system integrator to secure the thermal cooling solution to the processor after it is installed in the 370 pin ZIF socket The boxed processor s fan heatsink requires a 12V power supply A fan power cable is attached to the fan and connects to processor fan headers on the STL2 server board STL2 Server Board TPS STL2 Server Board Architecture Overview The boxed processor fan heatsink will keep the processor core at the recommended junction temperature as long as airflow through the fan heatsink is unimpeded It is recommended that the air temperature entering the fan inlet be below 45 C measured at 0 3 inches above the fan hub 2 2 ServerW
91. rver board uses the following IB6566 South Bridge features e PCI interface IDE interface USB interface e PC compatible timer counters and DMA controllers e Baseboard Plug and Play support General purpose I O e Power management APIC and 82C59 interrupt controller Host interface for AT compatible signaling e Internal only ISA bus no ISA expansion connectors bridge for communication with Super I O BIOS flash and BMC The following sections describe each supported feature as used on the STL2 server board 2 4 2 3 1 PCI Interface The IB6566 South Bridge fully implements a 32 bit PCI master slave interface in accordance with Revision 2 2 of the PCI Local Bus Specification On the STL2 server board the PCI interface operates at 33 MHz using the 5V signaling environment 2 4 2 3 2 PCI Bus Master IDE Interface The 1B6566 South Bridge acts as a PCI based enhanced IDE 32 bit interface controller for intelligent disk drives that have disk controller electronics on board The server board includes a single IDE connector featuring 40 pins 2 x 20 that support a master and a slave device The IDE controller provides support for an internally mounted CD ROM The IDE controller has the following features e PIO and DMA transfer modes Mode 4 timings e Transfer rates up to 33 MBps e Buffering for PCI IDE burst transfers e Master slave IDE mode Support for up to two devices STL2 Server Board TPS STL2 Server Board
92. scribes the features of the server management subsystem for the STL2 server board The server management subsystem consists of the BIOS hardware and firmware features built into the server board These features provide hardware monitoring control and logging to improve the reliability availability and serviceability of the server system The server management subsystem conforms to the IPMI Intelligent Platform Management Interface v1 0 specification IPMI defines a standardized abstracted message based interface between system management software and the platform management hardware The following comprise the major elements of the server management architecture for the STL2 server board Baseboard Management Controller BMC e Sensors Sensor Data Record SDR Repository amp System Event Log SEL Field Replaceable Unit FRU Information 3 1 Baseboard Management Controller The STL2 server management functionality is concentrated in the Baseboard Management Controller BMC The BMC is comprised of a Dallas Semiconductor DS80CH11 or equivalent microcontroller and associated circuitry located on the STL2 server board The BMC and associated circuits are powered from a 5V DC standby voltage which remains active when system power is switched off but the AC power source is still on and connected A major function of the BMC is to autonomously monitor system management events and log the occurrence in the nonvolatile System E
93. splay Only Indicates the CPUID of the installed processor Display Only Indicates the cache RAM size installed processor size Processor 1 Status Display Oniy Processor 2 Status Display Only Clear Processor Errors Clears the processor error information o Processor Error Pause Enabled If enabled the POST operation pauses if a Disabled processor error occurs Processor Serial Number Disabled Disables Enables Processor Serial Number NM Enabled Note 1 Possible Values Normal None or Error Revision 1 0 4 35 Basic Input Output System BIOS STL2 Server Board TPS 4 2 2 5 Advanced Menu Selections The following tables describe the menu options and associated submenus available on the Advanced Menu Please note that MPS 1 4 1 1 selection is no longer configurable The BIOS will always build MPS 1 4 tables Table 4 5 Advanced Menu Selections Choices or Display Only Description Memory Reconfiguration Refer to Memory Reconfiguration Submenu Peripheral Configuration Refer to Peripheral Reconfiguration Submenu Refer to Option ROM Submenu It Disables Enables the Option ROM BIOS on Option ROM the PCI Bus Refer to Numlock Submenu Reset Configuration Data No Clears the Extended System Configuration Yes Data if selected Installed O S Other Selects the type of operating system that will PnP O S be used most Table 4 6 Memory Reconfiruation Submenu Selections Choices or Display
94. supports both base conventional and extended memory 2 4 PCI I O Subsystem The expansion capabilities of the STL2 server board meet the needs of file and application servers for high performance I O by providing two PCI bus segments in the form of one 64 bit 66 MHz bus segment and one 32 bit 33 MHz bus segment Each of the PCI buses comply with Revision 2 2 of the PCI Local Bus Specification 2 4 1 64 bit 66 MHz PCI Subsystem The 64 bit 66 MHz 3 3V keyed PCI segment includes the following embedded devices and connectors Two 64 bit 66 MHz 3 3V keyed PCI expansion slots that can support 66 MHz 64 32 bit cards or 33 MHz 64 32 bit cards e Integrated Adaptec AIC 7899 PCI dual port SCSI controller providing separate Ultra160 and Ultra Wide SCSI channels 64 bit PCI features include Bus speed up to 66 MHz 3 3 V signaling environment e Burst transfers up to a peak of 528 Megabytes per second MBps e 8 16 32 or 64 bit data transfers e Plug and Play ready e Parity enabled Note If a 33 MHz PCI board is installed into one of the 64 bit PCI slots the bus speed for the 66 MHz PCI slots and SCSI controller is decreased to 33 MHz 2 4 1 1 Ultra160 Ultra WideSCSI Controller The STL2 server board includes an Adaptec AIC 7899 This is an embedded dual function PCI SCSI host adapter on the 64 bit 66 MHz PCI bus The AIC7899 contains two independent SCSI controllers that share a single PCI bus master interface
95. t or missing After a successful update power down the system and remove the jumper from pins 9 10 Power up the system Verify that the BIOS version number matches the version of the entire BIOS used in the original attempt to update 4 6 Error Messages and Error Codes The system BIOS displays error messages on the video screen Prior to video initialization beep codes inform the user of errors POST error codes are logged in the event log The BIOS displays POST error codes on the video monitor Following are definitions of POST error codes POST beep codes and system error messages 4 6 1 POST Codes The BIOS indicates the current testing phase during POST after the video adapter has been successfully initialized by writing a 2 digit hex code to I O location 80h If a Port 80h card Postcard is installed it displays this 2 digit code on a pair of hex display LEDs Table 4 23 Port 80h Code Definition Phoenix check point port 80 code The table below contains the port 80 codes displayed during the boot process A beep code is a series of individual beeps on the PC speaker each of equal length The following table describes the error conditions associated with each beep code and the corresponding POST check point code as seen by a port 80h card For example if an error occurs at checkpoint 22h a beep code of 1 3 1 1 is generated The means there is a pause between the sequence that delimits the sequence Some
96. the STL2 server board Revision 1 0 5 67 Jumpers and Connectors 5 2 1 5 2 2 5 2 3 5 68 Main ATX Power Connector P33 STL2 Server Board TPS Table 5 6 Main ATX Power Connector Pinout Wire color COM 5 VDC COM 5 VDC COM PWR GD 5 VSB 12 VDC COM PS ON_L COM COM COM N C 5 VDC 5 VDC 5 VDC COM Auxilary ATX Power Connector P34 Signal Wire Cote Blue Black Green Black Black Black N C Table 5 7 Auxiliary ATX Power Connector Pinout Pin Signal Wire Color 7 fewe Is 6 om eek TC Power Connector P37 Table 5 8 FC Power Connector Pinout Signal Feda IC Data STL2 Server Board TPS 5 2 4 System Fan Connectors P29 P27 P11 e System Fan 1 P11 e System Fan 2 P27 System Fan 3 P29 Table 5 9 Board Fan Connector Pinout Pin Signal 5 2 5 Processor Connectors P12 P36 Primary Processor Fan 1 P36 Secondary Processor Fan 2 P12 Table 5 10 Processor Fan Connector Pinout 5 2 6 Speaker Connector P31 Table 5 11 Speaker Connector Pinout Pin gei 5 2 7 Speaker Connector P25 Table 5 12 Speaker Connector Pinout Pin Siora SPEAKER GND 3 N C Revision 1 0 Jumpers and Connectors 5 69 Jumpers and Connectors 5 2 8 Diskette Drive Connector P20 18 34 OOO OOOO OF Or EM 0000 OD Or Or Or 0 00000000 O O O O 17 Figure
97. the serial input data stream received from the network Na PO EE E RX Receive data minus the negative signal for the RD differential pair contains the same input as pin 3 TEEN ESEE 5 2 14 USB Connectors Table 5 19 USB Connectors 5 VDC 1 5 VDC USB_P1_N USB_PO_N 3 USB_P1_P USB PO P 2 ES 5 72 STL2 Server Board TPS 5 2 15 Ultra SCSI Connector P9 Table 5 20 Ultra SCSI Connector Pinout Kiel Signal GND TERMPWR 5 2 16 TERMPWR NC SCD12_L SCD13_L SCD14_L SCD15_L SCDPH_L SCDO_L SCD1_L SCD2_L SCD3_L SCD4_L SCD5_L SCD6_L SCD7_L SCDP_L SCDAP12 SCDAP13 SCDAP14 SCDAP15 SCDAPHP SCDAPO SCDAP1 SCDAP2 SCDAP3 SCDAP4 SCDAP5 SCDAP6 SCDAP7 SCDAPLP Revision 1 0 Pin TERMPWR TERMPWR SATN L NC GND GND SBSY L Ultra160 SCSI Connector P8 Table 5 21 Ultra160 SCSI Connector Signal Jumpers and Connectors 5 73 Jumpers and Connectors Eai a EA E GE Ea ED EG EN Em Ee E EN Em Em EA A ES 5 2 17 21 DIFFSENSA TRMPWRA TRMPWRA No Connection GND ATNAP GND BSY ACK RSTAP MSGAP SELAP CDAP REQAP IOAP SCDAP8 SCDAP9 SCDAP10 SCDAP11 Pi 49 50 51 52 53 54 55 56 n TRMPWRA TRMPWRA GND GND GND ND ono IDE Connector P19 O O OOOOO OOOO0 O O O O O O 000OMOO00 0O00ODOOOOO O OQ O O OO 1 STL2 Server Board TPS Figure
98. tions The Phoenix Phlash Utility can be used to reprogram the BIOS operational code areas At run time none of the flash blocks is visible at the aliased addresses below 1 MB due to shadowing Intel reserves the right to change the flash map without notice A 64 KB parameter block in the flash ROM is dedicated to storing configuration data that controls extended system configuration data ESCD on board SCSI configuration OEM configuration areas etc The block is partitioned into separate areas for logically different data 4 30 STL2 Server Board TPS Basic Input Output System BIOS Application software must use standard advanced programmable interrupts APIs to access these areas and may not access the data directly 4 2 Setup Utility This section describes the ROM resident setup utility that provides the means to configure the platform The setup utility is part of the system BIOS and allows limited control over on board resources Such as the parallel port and mouse The following topics are covered below e Setup utility operation Configuration CMOS RAM definition e Function of the CMOS clear jumper 4 2 1 Configuration Utilities Overview Configuration of on board devices is done using the setup utility that is embedded in flash ROM Setup provides sufficient configuration functionality to boot a system diskette or CDROM The SSU which is discussed in a separate document is released on diskette or CDROM Setup is always
99. truction to sleep POST Boot monitor timed out Power Down OS WDT shut down after the monitor timeout Timer Interrupt OS WDT monitor timed out SMI Timeout SMI has been asserted for more than ten seconds Q a o bi e CO CH I Oo CH ii Watchdog 2 CH mare CH SMI Timeout F3h EMP F5h 00h Communication Error Communication is unavailable even though the BMC is in communication status Acknowledged TC Bus Device Error Detected vunenee p 3 3 ACPI The Advance Configuration and Power Interface ACPI aware operating system can place the system into a state where the hard drives spin down the sytem fans stop and all processing is halted In this state the power supply is still on and the processors still dissipate some power such that the power supply fan and processor fans are still running Note ACPI requires an operating system that supports this feature The ACPI sleep states discussed below are defined as e s0 Normal running state e s1 Processor sleep state No content is lost in this state and the processor caches maintain coherency Revision 1 0 3 27 Server Management STL2 Server Board TPS e s4 Hibernate or Save to Disk The memory and machine state are saved to disk Pressing the power button or another wakeup event restores the system state from the disk and resumes normal operation This assumes that no hardware changes were made to the system while it was off s
100. umpers and Connectors 5 Jumpers and Connectors STL2 Server Board Jumper and Connector Locations The following figure shows the location of the jumper blocks and connectors on the STL2 Server board A DCD EF amp H Figure 5 1 STL2 Server Board Jumper and Connector Locations Jumper and connector location key for Figure 5 1 Main power connector P33 VRM socket P32 Auxiliary power connector P34 Primary processor P13 Secondary processor P14 Secondary processor heatsink fan connector P36 Power supply signal connector P37 DIMM slots P15 P18 IDE connector P19 Floppy drive connector P20 Two pin speaker connector P31 rr E omnmpomb Revision 1 0 5 61 Jumpers and Connectors NxXxXxS lt 5CHPMDOVOZELD System fan connector FAN3A P29 Battery System fan connector FAN2A P27 Front panel connector P23 Four pin speaker connector P25 Ultra Single Ended SE SCSI connector P9 Ultra160 LVD SCSI connector P8 Configuration jumper block 1L4 Configuration jumper block 1J15 CPU speed jumper block 5E1 33 MHz 32 bit PCI connectors 66 MHz 64 bit PCI connectors Chassis intrusion connector pins 1 2 of 6A System fan connector FAN1 P11 I O ports STL2 Server Board TPS AA Primary processor heatsink fan connector P12 The following diagram shows the location of the connectors on the STL2 server board I O panel Lg O D E db ba Figure 5 2 I O Back Panel
101. umpers and Connectors STL2 Server Board TPS 16 Reserved Reset Switch GND 18 Reserved ACPI Sleep Switch Low True Chassis Intrusion ACPI Sleep Switch GND Reserved NMI to CPU Switch Low True 5 78 STL2 Server Board TPS Jumpers and Connectors lt This page intentionally left blank gt Revision 1 0 5 79 STL2 Server Board TPS Power Consumption 6 Power Consumption 6 1 Calculated Power Consumption The following table shows the calculated power consumption for each of the power supply voltage rails for the STL2 server board These values were calculated using the specifications for the on board components and processors Assumptions for add in card power and other peripherals powered from the server board are included in the table Customers will need to modify the calculated power consumption numbers based on their anticipated usage watts per PCI slot etc Note The following numbers are provided only as an example Actual power consumption will vary depending on the exact configuration temperature voltage level etc Refer to the appropriate system chassis document for more information Table 6 1 STL2 Server Board Calculated Power Consumption SererBoard fasa em oon fom fom Processors 87 VRM efficiency 100 utilization 1 x 667 MHz 256K 4 02A processor 1 x 733 MHz 256K 4 21A processor 1x 800EB MHz 256K 4 78A processor 1x 866 MHz 256K 5 26A processor 1x 933 MHz 256K processo
102. vent Log SEL The events being monitored include over under temperature and over under voltage conditions fan failure or chassis intrusion To enable accurate monitoring the BMC maintains the nonvolatile Sensor Data Record SDR from which sensor information can be retrieved The BMC provides an ISA host interface to SDR sensor information so that software running on the server can poll and retrieve the server s current status The BMC also provides the interface to the monitored information and SEL that System Management Software such as Intel Server Control uses to poll and retrieve the platform status The BMC performs the following functions e Monitors server boad temperature and voltage e Monitors processor presence and controls Fault Resilient Boot FRB Detects and indicates baseboard fan failure e Manages the SEL interface Manages the SDR Repository interface e Monitors the SDR SEL timestamp clock Monitors the system management watchdog timer Monitors the periodic SMI timer Revision 1 0 3 23 Server Management STL2 Server Board TPS Monitors the event receiver Controls secure mode inlucluding video blanding diskett write protect monitoring and fornt panel lock unlock initiation Controls Wake on Lan via Magic Packet support 3 2 Hardware Sensors The following table lists the hardware sensors present on the STL2 server board mm I eermeegd 0 1 ocessormemd EE EE IP E ES A E ewoo 20

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