Intel mPGA604 User's Manual
Contents
1. 8 b 5 3 ego UT fe Du gt a B B A IA SCALE 20 1 j RUT DI TISIST 1 DRAW NGPSHEE 1 1 5 3 mPGA604 Socket Design Guidelines 47 I 6 3 4 3 48 mPGA604 Socket Design Guidelines Appendix A Figure A 10 603 Pin Interposer Assembly Drawing Sheet 4 of 7 8 I 0 V d 3 PER jg NUT N NA U NG SHUI RK y Y TY Vu Haj VI A ji Gi J d J JN JA JJ Je JJ n i Appendix A i J Y J FR IR Fi UI wi W 1118 W W PRIOR ARITIEN CONSEMI OF INTEL NAA gt mat ALI K n JO LNG SA bles 200 p ell Ll COMPONENT HEIGHT D f I UL 18 420 p E L HS Fi 1 e i Wii E 1 NAO L II T HK L NEB K N wm CUT I Nap j j f an LI D LE le mm HON TLM TC RIT H snor EE IDN IN b 10p0 KOT SCALE2. 44 mPGA604 Socket Design Guidelines Appendix A 8 I 6 5 OUT TEIS mie CONTAINS wt AND 11 OR KO 1 TIA WON DO NOT HAVE VENT HOLE AND CHANFER e A T0 THE ASSEMBLY DATA SHEET FOR PIN 1 ORIENTATION OSEO IN CONFIDENCE OUI IRE mp IT CONSENT OF INTEL CORPORATION POUT ONCS NENT PLACENEN BREET UTE T mar DHA Jo 01021149 JA 1 08 18 98 Dn Mi NT ME NIT E HI INL d Ns di HU PIN IKTERPOSER Tynn mn A LEE TI TA cu mp om NH vagy SH mg AH ASIE Tt DR CHANDLER um vun D Sp 7 It AN DIU 1 D P Ou 603 PIN INTE 1 t 1 fera ME AC JM 2 9mm BON TT TE CST El CID Wu Wu Et D 8 4 i i GI mPGA604 Socket Design Guidelines 45 Appendix A Figure A 8 603 Pin Interposer Assembly Drawing Sheet 2 of 7 6 J i 3 Lg B D Du b 9 N 4 3 Kg un ang ON CON NT AR IS AU WO BE DISCLOSED Ua TE PRIOR AR n A pais wr D i TT 9 A 4 9 0 3 2 46 mPGA604 Socket Design Guidelines n Appendix A
3. mPGA604 Socket Design Guidelines Mechanical Requirements 17 intel Mechanical Requirements i This page intentionally left blank 18 mPGA604 Socket Design Guidelines 4 Electrical Requirements Socket electrical requirements are measured from the socket seating plane of the processor test vehicle PTV to the component side of the socket PCB to which it is attached All specifications are maximum values unless otherwise stated for a single socket pin but includes effects of adjacent pins where indicated Pin and socket inductance includes exposed pin from mated contact to bottom of the processor pin field Table 4 1 Electrical Requirements for Sockets Pin Connector to Connector inductance 1 Mat11 loop inductance Lloop lt 4 33nH Refer to Table 4 2 Item 1 2 Mated partial mutual inductance L NA Refer to Table 4 2 Item 2a 3 Maximum mutual capacitance C lt 1pF Refer to Table 4 2 Item 3 4 Maximum Ave Contact Resistance lt 17mQ Refer to Table 4 2 Item 4 Refer to Section 4 1 for more detail Refer to mPGA603 Socket Design Guidelines for electrical parameters with INT3 packages 5 Measurement frequency s for Pin to 400 MHz Pin Connector to Connector capacitance 6 Measurement frequency s for Pin to 1 GHz Dielectric Withstand Voltage 360 Volts RMS Insulation Resistance 800 M Ohms Contact Current Rating Read and record Table 4 2 Definitions 1 Mated loop
4. mPGA604 Socket Design Guidelines 1 1 1 2 1 3 mPGA604 Socket Design Guidelines Introduction Objective This document defines a surface mount Zero Insertion Force ZIF socket intended for workstation and server platforms based on future Intel microprocessors The socket provides I O power and ground contacts The socket contains 604 contacts arrayed about a cavity in the center of the socket with solder balls surface mount features for surface mounting with the motherboard The mPGA604 socket contacts have 50mil pitch with regular pin array to mate with a 604 pin processor package A 604 pin package will be mated with a 603 solder ball socket The dummy pin is a key that allows either the 603 pin processor package or the 604 pin processor package to be used in the same socket Purpose To define functional quality reliability and material that is visual dimensional and physical requirements and design guidelines of the mPG A604 socket in order to provide low cost low risk robust high volume manufacturable HVM socket solution available from multiple sources Scope This design guideline applies to all 604 pin ZIF sockets purchased to the requirements of this design guideline LI intel Introduction This page intentionally left blank 10 mPGA604 Socket Design Guidelines 2 1 2 2 Table 2 1 Note Assembled Component and Pachage Description Information provided in this section is to ensure d
5. PUT 88888068 888968868 389888888 888888868 888888888 88889898988888 TEEN TRASS rrr EF I s minn 888888088 88p0609098896000090000099098888 8899899890999099090008090090896 ni virio Feb ELEEE EEE bee 888888888 988880888 T I pastan Ll Sege Lamaen d naan Eu ud bartia 1 88900 T 3689899099998 898898898 PAL 886858 888 Glais 888888888 i 8 40 2 25 mm RESIST OPENING AD FILE ASE H LU VS JA XT N NAG j HR Sech se NA WU fh Ven Se J HIR j SOLER LET HI Sena Li 8 1 b 5 4 3 mPGA604 Socket Design Guidelines Appendix A Figure A 3 42 5 mm 604 Pin Package Assembly Drawing Sheet 3 of 3 1 i 5 I 3 IR SEALAN I I X DETAIL A SCALE 20 b TI DIMENSION TL A lL A ADD 0 w FOR 300pm WAFERS mPGA604 Socket Design Guidelines 41 Appendix A Figure A 4 mPGA604 Socket Drawing Sheet 1 of 3 Ik WAY OR NOT BE DIS Uu VAR T DIMENSIONS PER INTEL SOCKET DESIGN GUIDE ATION IT 1 VI THE PR p I FT ARE YOK BALLS METER FEM B UGE mm mb v ME LO onp fo PROD BT Dr
6. 4 3 2 Correlation of Measurement and Model Data Inductance 26 4 4 Pin to Pin Capacitance A 27 4 5 Dielectric Withstand Voltage AA 27 4 6 Insulation Resistance eee eee eee eee eee eree eee 27 4 7 Contact Current Hang 27 mPGA604 Socket Design Guidelines 3 gt N Figures Environmental Requirements rrannvnnnnnnnvnnnnnnnnvnnnnnnnnnnnnnnnnennnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnenr 29 5 1 Porosty 1 OS aa mere raie nes see AT enorme 30 5 1 1 Porosity Test Method 30 5 1 2 Porosity Test Criteria aa aaa eee eee eee eee 30 5 2 Plating Rule a 30 5 3 Solvent Resistance sise 30 5 4 Sold rabilItY EE 30 5 5 Bur o LS PE SEE BEEN SSESE DENNE ELERS a 31 Validation Testing Requirements nes 33 6 1 Applicable Documents ss 33 6 2 Testing Facility ee nant 33 6 3 ele aa aah 33 6 4 Socket Design Verification 33 6 5 REPoNING EEE EEE 33 6 6 ele e 33 6 7 Quality Assurance Requirements eee eee eee eee eee eee ee ehe re eee rete tee eter 34 6 8 Socket Test Pani add be 34 6 8 1 Submission of an mPGA604 Socket for Validation Testing 34 6 9 Mechanical Samples unten dush de 34 6 10 Socket Validation Notification sese ee eee es venes eee ee see reze eee teres verte eee reze e rete 34 6 11 Production Lot Definition Nama exceeds Eras ayan nd de 34 6 12 Socket Validation urtis deh te dd du n 34 SELIM LLI 35 Documentation Requirements nes 37 Appendix Aa sha s
7. Typical examples of significant changes include but are not limited to the following Plastic material changes including base material or color contact changes including base material plating material or thickness and design modifications mPGA604 Socket Design Guidelines 33 intel Validation Testing Requirements i 6 7 6 8 6 8 1 6 9 6 10 6 11 6 12 34 Quality Assurance Requirements The OEM s will work with the socket supplier s they choose to ensure socket quality Socket Test Plan Submission of an mPGA604 Socket for Validation Testing The socket supplier s mPGA604 socket will be sent to Intel s independent test facility for socket validation testing The sockets submitted must be per the drawing required in Section 6 4 Refer to Sections 6 11 and 6 12 for production lot definition and number of samples required for validation testing Mechanical Samples A mechanical sample of mPG A604 socket package and heatsink or suitable mockups that approximate size and mass of the planned heatsink will be used during the mated socket validation testing The maximum mass for mPGA604 socket package heatsink is recommended as but not limited to 450g with the stipulation that the requirements of Section 3 1 be met See data sheet and related documentation for further information on heatsinks thermal solutions and mechanical support Socket Validation Notification Upon completion of the testing and receipt of t
8. UT TRAD ABLE LA 42 mPGA604 Socket Design Guidelines Appendix A Figure A 5 mPGA604 Socket Drawing Sheet 2 of 3 l i i i 3 a HEE 7 THIS DRAWING CONTAINS INTI AL INFORMATION IT 15 MAY NOT BE DISI VI THE PR Le SAIS hi pi d D hi H gt 300090 ta El lt 00008 000 0000 00000 OP VIEN I SHONN N ACTUATE HION BOTTOM VIEN ATTACHMENT gt 438 61 AFTER CN 15 DO NOT TOOL TO THS DRAWING mPGA604 Socket Design Guidelines 43 Appendix A Figure A 6 mPGA604 Socket Drawing Sheet 3 of 3 8 i j i m P THIS Wu ATION IT IS VAY NOT BE DIS VI THE PR PIN H IDENTIFIER I MUST RESIDE WITHING ZON G FR D 5 L J ELY AS SHONN LA Ld T ies i I T I IN 4 L I 1 00 000 Ui OG 9009000 0900 I I i d De Lech e t of Le D I lil d up d Um SALE I i i I 1 3 l
9. DR MINGJSHE 191 3 i j T mPGA604 Socket Design Guidelines 49 Appendix A Figure A 12 603 Pin Interposer Assembly Drawing Sheet 6 of 7 i r av d 0 u P 3 Kr wan Fi vn vi eu ORTON I GM MAY WOT BE DISCLOSED I PR RUN EN A CORNE QA VIA ERP Pe UR ul 9 6251 7 f i L I El de ELL NG 1 WER P 4 n i F um tar FL 7 EL D UN SCALE 20 1 AJ um Y DE Y J I a Na BEER La UM sent L EE k 13411 US so EE HAM TULU mer TT sawa cum i H e TN D bn de mi I 6 3 2 50 mPGA604 Socket Design Guidelines Appendix A 3 Bg Fu Pa hH l p 3 k D g 1 DI M T T 8 6 5 1 2 mPGA604 Socket Design Guidelines 51 a intel Appendix A This page intentionally left blank 52 mPGA604 Socket Design Guidelines
10. The mPGA604 socket may contain design defects or errors known as errata which may cause the product to deviate from published specifications Current characterized errata are available upon request Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order Copies of documents which have an order number and are referenced in this document or other Intel literature may be obtained by calling1 800 548 4725 or by visiting Intel s website at http www intel com Intel is a trademark or registered trademark of Intel Corporation or its subsidiaries in the United States and other countries Copyright O 2003 Intel Corporation All rights reserved Other brands and names may be claimed as the property of others 2 mPGA604 Socket Design Guidelines intel Contents 1 Introduction aske 9 1 1 lee naaa Na ANING ANNA LA aina 9 1 2 PUKPOS E 9 1 3 ll e enn Ena 9 Assembled Component and Package Description 11 2 1 Assembled Component Description ee eee never ee eren eee 11 2 2 Package Description mitt nine DA dd dE 11 Mechanical Requirements nenen nenen ene nene ete tone rete teme rete t n tete testet ennenen neee 13 3 1 Mechanical Supports sis 13 3 2 ET E 13 3 2 1 Socket SP 13 8 227 COI eege Siess aesgee giereg eege Eech E ii eege 13 3 3 Cutouts for Package Removal sere re enen ee terre eter eee ee 13 3 4 Socket Standoff Heights 13 3 5 Ma
11. inductance Lloop Refer to Table 4 1 Item 11 The inductance calculated for two conductors considering one forward conductor and one return conductor 2a Mated mutual inductance L Refer to Table 4 1 Item 2 The inductance on a conductor due to any single neighboring conductor Maximum mutual capacitance C Refer to Table 4 1 Item 3 The capacitance between two pins connectors Maximum Average Contact Resistance Refer to Table 4 1 Item 4 The max average resistance target is originally derived from max resistance of each chain minus resistance of shorting bars divided by number of pins in the daisy chain This value has to be satisfied at all time Thus this is the spec valid at End of Line End of Life and etc Socket Contact Resistance The resistance of the socket contact interface resistance to the pin and the entire pin to the point where the pin enters the interposer gaps included Measurement frequency s for Capacitance Capacitively dominate region This is usually the lowest measurable frequency This should be determined from the measurements done for the feasibility Measurement frequency s for Inductance Linear region This is usually found at higher frequency ranges This should be determined from the measurements done for the feasibility mPGA604 Socket Design Guidelines 19 intel Electrical Requirements i 4 1 20 Electrical Resistance Figure 4 1 and F
12. perform port extension after calibration Check to ensure calibration successfully performed Measure the inductance of configuration 4 of the package mounted on the socket which is mounted to the motherboard fixture Figure 4 5 Call this L socket assembly Export data into MDS ADS or capture data at frequency specified in Item 6 of Table 4 1 Measure the inductance of configuration 4 of the package mounted on the socket which is mounted to the motherboard fixture Figure 4 5 Call this L sandwich Measure 30 units The package for 30 units must be chosen from different lots Use 5 different lots 6 units from each lot Export data into MDS ADS or capture data at frequency specified in Item 6 of Table 4 1 Calculate L sandwich For each socket unit calculate Lis La assembly ui Lsandwich It means Fung will be subtracted from each L and the result will be socket assembly compared with spec value for each individual socket unit Correlation of Measurement and Model Data Inductance To correlate the measurement and model data for loop inductance one unit of measured socket assembly socket and shorted test fixture and one unit of measured sandwich shorted test fixture will be chosen for cross sectioning Both units will be modeled based on data from cross sectioning using Ansoft 3D The sandwich inductance will be subtracted from socket assembly inductance for both measured an
13. reliability evaluation methodology which is acceleration factor dependent simplified process flow of this methodology can be seen in Figure 5 1 Figure 5 1 Flowchart of Knowledge Based Reliability Evaluation Methodology Establish the Market Expected Use Environment for the Technology Develop Speculative Stress Conditions Based on Historical Data Content Experts and Literature Search I Freeze Stressing Requirements and Perform Additional Data Turns Perform Stressing to Validate Accelerated Stressing Assumptions and Determine Acceleration Factors A detailed description of this methodology can be found at http developer intel com design packtech 245162 htm The use environment expectations assumed are for desktop processors based on an expected life of 7 to 10 years are listed in Table 5 1 The target failure rates are lt 1 at 7 years and lt 3 at 10 years Table 5 1 Use Conditions Environment Use Environment Speculative Stress Condition 7 Year Life Expectation 10 Year Life Expectation Slow small internal gradient changes due to external ambient temperature cycle or externally heated Temperature Cycle 1500 cycles with a mean AT 40 C 2150 cycles with a mean AT 40 C duration high temperature exposures Tjmax High ambient moisture during low power THB HAST 62 000 hrs at 89 000
14. EM s pick and place Vision systems The base and cover of the socket may be different colors as long as they meet the above requirement Cutouts for Package Removal Recessed cutouts are required in the side of the socket to provide better access to the package substrate and facilitate the manual removal of inserted package Figure A 6 Socket Standoff Height Socket stand off height cover lead in and cover lead in depth must not interfere with package pin shoulder at worst case conditions The processor not the pin shoulder must sit flush on the socket standoffs and the pin field cannot contact the standoffs Figure A 5 mPGA604 Socket Design Guidelines 13 intel Mechanical Requirements i 3 5 3 5 1 3 5 2 3 5 3 Proper seating Markings All markings required in this section must be able to withstand a temperature of 240 C for 40 seconds minimum typical of a reflow profile for solder material used on the socket as well as any environmental test procedure outlined in Section 5 Name m PG A604 font type is Helvetica Bold minimum 6 point This mark shall be molded or Laser Marked into the processor side of the socket housing Manufacturer s insignia font size at supplier s discretion This mark will be molded or laser marked into the socket housing Both marks must be visible when first seated in the motherboard Any request for variation from this marking requires a written description deta
15. NTNUHSADNONTMUHEO MMNNNUNANUNN HAHAAHA MN UIA VU SOIN aNG Ne DU VU v vd ed ed H ed ed H YA 22 EE EE EE Sr e a d gt gt wm wm mm em wm mm H E 18890600 SI De MI D D H 990999000 DEA SIN d D D vw II U I o o oll tl n 7609088 8990000007 Z e Z x u zi ll T J d E I I E Y x K Y II R 000800 8900000007 SER INN 5 I m sil Ul ll o o Wu a O U I N L CO 60 6060606060 L H L LI se Ll GO 0 0 6 0 6 0 00 00 00 00 00 00 ul ul I I D 6 0 09 6 0 GO 60 60 6 0 GO 60 0 0 0 0 60 a nl nos em DOO 09 69 60 6 0 0 0 00 0 0 60 9060606090 U Db e e en e em e e e 2902 000000 c00900 0002 000002 00003 ml gt ee S Ses SS SS ses Figure 4 3 Electrical Resistance Fixtures Superimposed 21 ABCDEFGHJRLMNPRTUUNY mPGA604 Socket Design Guidelines Electrical Requirements L LS LS LA LS LS LS L LS L TU NS UT On J UD OS C PU L A LH O N DO DC Endpoints Edgefingers Hi Edgefingers Low Hi Low l V V I AE29 AE16 A136 A135 A118 A117 AD30 AD16 A138 A137 A116 A117 AC30 AC16 A142 A141 A114 A113 AB29 AB16 A134 A133 A112 A111 AA28 AA16 A132 A131 A110 A109 A102 A101 A108 A107 A130 A129 A108 A107 22 mPGA604 Socket Design Guidelines Table 4 3 Resistance Test F
16. No Plane on this Layer Short all L pins using a solid plane Full Plane on this Layer No Features or NE eg Plane on this Layer Interposer Interposer Shoulder Short all L pins using a solid plane Motherboard Figure 4 5 Inductance and Capacitance Fixture A SIGGGO00000 00000000 BOG 000000 oe 00000000 N E gt ac EE JA IN 28006 AD H6GG5660 R 666666 956060 l 2 EN 6605 T1 TT 12 2930 4 3 1 Design Procedure for Inductance Measurements The measurement equipment required to perform the validation is 1 2 3 Equipment HP8753D Vector Network Analyzer or equivalent Robust Probe Station GTL4040 or equivalent Probes GS1250 amp GSG1250 Air Co Planar or equivalent mPGA604 Socket Design Guidelines 25 intel Electrical Requirements i 4 3 2 26 4 Calibration Cascade Calibration Substrates or equivalent 5 Measurement objects packages sockets motherboards Measurement Steps Equipment Setup Cables should be connected to the network analyzer and to the probes using the appropriate torque wrench to ensure consistent data collection every time the measurement is performed Set VNA Bandwidth 30 OKHz 3 GHz with 801 points Averaging Factor 16 Perform Open Short Load calibration Calibration should be performed at the start of any measurement session Create Calibration Kit if necessary for 1 time Do not
17. as per the European Blue Angel recycling design guidelines Lever Actuation Requirements e Lever closed direction right e Actuation direction called out in Figure A 5 e 135 lever travel max e Pivot point in the center of the actuation area on the top of the socket Figure A 6 Socket Engagement Disengagement Force The force on the actuation lever arm must not exceed 44N to engage or disengage the package into the mPG A604 socket Movement of the cover is limited to the plane parallel to the motherboard The processor package must not be utilized in the actuation of the socket Any actuation must meet or exceed SEMI S8 95 Safety Guidelines for Ergonomics Human Factors Engineering of Semiconductor Manufacturing Equipment example Table R2 7 Maximum Grip Forces Visual Aids The socket top will have markings identifying Pin 1 This marking will be represented by a clearly visible triangular symbol See Figure A 6 Socket BGA Co Planarity The co planarity profile requirement for all solder balls on the underside of the socket is located in Figure A 5 Solder Ball True Position The solder ball pattern has a true position requirement with respect to Datum A B and C see Figure A 5 mPGA604 Socket Design Guidelines intel 3 16 Critical to Function Dimensions The mPG A604 socket shall accept a 604 pin processor pin field All dimensions are metric Asymmetric features are designed to properly align the socket t
18. d modeled data This procedure results in loop inductance for socket pin interposer pin This final result can be compared with the loop inductance from the supplier model mPGA604 Socket Design Guidelines 4 4 4 5 4 6 4 7 Electrical Requirements for the socket The shoulder of the interposer is not included in the electrical modeling If there is any difference between them it will be called the de embedded correction factor Adding the interposer to the socket and then eliminating the contribution of the fixture creates this correction factor because inductance is not linear Pin to Pin Capacitance Pin to pin capacitance shall be measured using configuration 4 with the motherboard not connected and only the measurements with the package mounted on the socket will be taken Capture data at frequency specified in Item 5 of Table 4 1 Dielectric Withstand Voltage No disruptive discharge or leakage greater than 0 5 mA is allowed when subjected to 360 V RMS The sockets shall be tested according to EIA 364 Test Procedure 20A Method 1 The sockets shall be tested unmounted and unmated Barometric pressure shall be equivalent to Sea Level The sample size is 25 contact to contact pairs on each of four sockets The contacts shall be randomly chosen Insulation Resistance The insulation resistance shall be greater than 800 M Ohm when subjected to 500 V DC The sockets shall be tested according to EIA 364 Test Procedure 21 The s
19. elating Flatness of Processor Pin length pin true position and flatness tolerances are controlled by Geometric Dimensioning and Tolerancing GD amp T controls mPGA604 Socket Design Guidelines 11 intel Assembled Component and Pachage Description j This page intentionally left blank 12 mPGA604 Socket Design Guidelines intel 3 3 1 3 2 3 2 1 3 2 2 3 3 3 4 Mechanical Requirements Mechanical Supports A retention system needs to isolate any load in excess of 50 Ibf compressive from the socket during the shock and vibration conditions outlined in Sections 5 The socket must pass the mechanical shock and vibration requirements listed in Sections 5 with the associated heatsink and retention mechanism attached socket can only be attached by the 603 contacts to the motherboard No external i e screw extra solder adhesive etc methods to attach the socket are acceptable Materials Socket Housing Thermoplastic or equivalent UL 94V 0 flame rating temperature rating and design capable of withstanding a temperature of 240 C for 40sec minimum typical of a reflow profile for solder material used on the socket The material must have a thermal coefficient of expansion in the XY plane capable of passing reliability tests rated for an expected high operating temperature mounted on FR4 type motherboard material Color The color of the socket can be optimized to provide the contrast needed for O
20. est data Intel and or the Intel designated test facility will prepare a summary report for the socket supplier and Intel that will provide notification as to whether the socket has passed or failed socket validation testing Production Lot Definition A production lot is defined as a separate process run through the major operations including molding contact stamping contact plating and assembly These lots should be produced on separate shifts or days of the week Lot identification marking needs to be provided to Intel as verification of this process Socket Validation Socket validation must meet or exceed all guidelines called out in this spec which include Visual Inspection CTF Dimensional Verification Electrical Resistance Loop Inductance Pin to Pin Capacitance Contact Current Rating Dielectric Withstand Voltage Insulation Durability Porosity Plating Thickness Solvent Resistance if applicable Solderability Applicable for leaded sockets Post Reliability Visual and use conditions The use conditions target failure rates are lt 1 at 7 years and lt 3 at 10 years Statistical sample sizes taken randomly from multiple lots for each test is required mPGA604 Socket Design Guidelines intel 7 Safety Requirements Design including materials shall be consistent with the manufacture of units that meet the following safety standards e UL 1950 most current editions e CSA 950 most current edition e ENG0 950 most cu
21. he id sa ao s et bad AA 39 Figure 4 1 Methodology for Measuring Total Electrical Resistance 20 Figure 4 2 Methodology for Measuring Electrical Resistance of the Jumper 20 Figure 4 3 Electrical Resistance Fixtures Superimposed 21 Figure 4 4 Inductance Measurement Fixture Cross Section 25 Figure 4 5 Inductance and Capacitance Fixture ccccccceeeesseeeeeeeeseeeeeeeaeeeeeeeeeeeeseeeen 25 Figure 5 1 Flowchart of Knowledge Based Reliability Evaluation Methodology 29 Figure A 1 42 5 mm 604 Pin Package Assembly Drawing Sheet 1 of 3 39 Figure A 2 42 5 mm 604 Pin Package Assembly Drawing Sheet 2 of 3 40 Figure A 3 42 5 mm 604 Pin Package Assembly Drawing Sheet 3 of 3 41 Figure A 4 mPGA604 Socket Drawing Sheet 1 of 3 42 Figure A 5 mPGA604 Socket Drawing Sheet 2 of 3 43 Figure A 6 mPGA604 Socket Drawing Sheet 3 of 3 44 Figure A 7 603 Pin Interposer Assembly Drawing Sheet 1 of 7 45 Figure A 8 603 Pin Interposer Assembly Drawing Sheet 2 of 7 46 Figure A 9 603 Pin Interposer Assembly Drawing Sheet 3 of 7 47 Figure A 10 603 Pin Interposer Assembly Drawing Sheet 4 of 7 48 Figure A 11 603 Pin Interposer Assembly Drawing Sheet 5 of 7 49 Figure A 12 603 Pin Interposer Assembly Draw
22. he minimum plating thickness specified in Section 3 9 3 Solvent Resistance Requirement No damage to ink markings if applicable EIA 364 11A Solderability Applicable for leaded sockets Requirement 95 coverage per ball surface mount feature EIA 364 Test Procedure 52 Class 2 Category 3 Test to be performed on 20 randomly selected contacts per socket five sockets mPGA604 Socket Design Guidelines Environmental Requirements 5 5 Durability Use per EIA 364 test procedure 09B The same package pin field is to be used for Ist and 51st cycles Measure contact resistance when mated in 1st and 51st cycles A spare package pin field is used for 2nd through 50th cycles A pair of new package pin fields to be used for each of the socket samples The package should be removed at the end of each de actuation cycle and reinserted into the socket mPGA604 Socket Design Guidelines 31 Environmental Requirements 32 This page intentionally left blank mPGA604 Socket Design Guidelines intel 6 Validation Testing Requirements This section of the document outlines the tests that must be successfully completed in order for the supplier s socket to pass the design guidelines validation It provides the test plan and procedure required for validation 6 1 Applicable Documents EIA 364 C Electrical Mechanical and Thermal Specification EMTS Thermal Design Guidelines Document Note For details on ordering this documen
23. hrs at state operating voltage 30 C 85 RH 30 C 85 RH High Operating temperature and short BAKE 62 000 hrs at 89 000 hrs at Tjmax mPGA604 Socket Design Guidelines 29 intel Environmental Requirements i Table 5 1 Use Conditions Environment Continued 5 1 5 1 1 5 1 2 5 2 5 3 5 4 30 i Speculative Stress 7 Year Life 10 Year Life Use Environment Condition Expectation Expectation Fast large gradient on off to max Povver Cycle 7 500 cycles 11 000 cycles operating temp povver cycle or internally heated including povver save features Shipping and Handling Mechanical Shock 3 drops axis 6 50g trapezoidal axis profile 1 70 sec Velocity change 11 msec duration pulse Shipping and Handling Random Vibration 10 min axis 3 3 13 gRMS random xis 5 Hz 20 Hz 01 g2 Hz sloping up to 02 g2 Hz 20 Hz 500 Hz 02 g2 Hz Porosity Test Porosity Test Method Use EIA 364 Test Procedure 53A Nitric acid test Porosity test to be performed for 20 contacts randomly selected per socket five sockets Porosity Test Criteria Maximum of two pores per set of 20 contacts as measured per EJA 364 Test Procedure 60 Plating Thickness Measure various plating thickness on contact surface per EIA 364 Test Procedure 48 Method C or Method A Test to be performed using 20 randomly selected contacts per socket five sockets No plating thickness measured shall be less than t
24. igure 4 2 shovv the proposed methodology for measuring the final electrical resistance The methodology requires measuring interposer flush mounted directly to the motherboard fixtures so that the pin shoulder is flush vvith the motherboard to get the averaged jumper resistance Rjumper The Rjumper should come from a good statistical average of 30 package fixtures flush mounted to a motherboard fixture The same measurements are then made with a package fixture mounted on a supplier s socket and both are mounted on a motherboard fixture this provides the Rrota The resistance requirement Ro can be calculated for each chain as will be explained later Figure 4 1 Methodology for Measuring Total Electrical Resistance Figure 4 2 Methodology for Measuring Electrical Resistance of the Jumper Socket Contact Interposer Shorting Bar Interposer Shoulder Interposer Pin Motherboard Interposer Shorting Bar Interposer Shoulder sr i N eg H Motherboard Figure 4 3 shows the resistance test fixtures separately and superimposed The upper figure is the package The next figure is the baseboard There are 48 daisy chain configurations on resistance test board The bottom figure is the two parts superimposed Table 4 3 shows these configurations with the number of pins per each chain and netlist mPGA604 Socket Design Guidelines Electrical Requirements dODON ON TM U Sod ON ON YNI gn DINT NN H4SM0ONV
25. iling size and location to be provided to Intel for approval Lock Closed and Unlock Open Markings The universal symbols for Lock and Unlock are to be marked on the socket in the appropriate positions Clear indicator marks must be located on the actuation mechanism that identifies the lock closed and unlock open positions of the cover as well as the actuation direction These marks should still be visible after a package is inserted into the socket E Lock closed Unlock open Lot Traceability Each socket will be marked with a lot identification code that will allow traceability of all components date of manufacture year and week and assembly location The mark must be placed on a surface that is visible when mounted on a printed circuit board In addition this identification code must be marked on the exterior of the box in which the units ship mPGA604 Socket Design Guidelines 3 7 3 8 3 9 3 9 1 3 9 2 3 9 3 3 9 4 3 9 5 Mechanical Requirements Socket Size The socket size must meet the dimensions as shown in Figure A 5 and Figure A 6 allowing full insertion of the pins in the socket without interference between the socket and the pin field The mPG A604 socket and actuation area must fit within the keep in zone defined in Figure A 6 Socket Package Translation During Actuation The socket shall be built so that the post actuated package pin field displacement will n
26. imensional compatibility of the mPG A604 socket with that of the 604 pin processor package The processor package must be inserted into the mPGA604 socket with zero insertion force when the socket is not actuated Assembled Component Description The assembled component may consist of a heatsink EMI shield clips fan retention mechanism RM and processor package Specific details can be obtained from Thermal Design Guidelines consult your Intel field representative to obtain this document Package Description The outline of the processor package that can be used with the mPG A604 socket is illustrated in Figure A 1 This drawing does not include potential heatsinks since these are used at the OEM s discretion The pin out for the 604 pin processor package is shown in Figure A 2 The pin dimension details base material plating material and plating thickness are shown in Figure A 3 Note the dimensional variation when designing to ensure ZIF The package Critical To Function CTF dimensions are presented in Table 2 1 CTF values are detailed on the processor package drawings and take precedence over all values presented in this document Package Critical To Function CTF Dimensions Dimension Shoulder Diameter Land Solder Fillet Shoulder Inclusion Pin Diameter Shoulder Diameter Protrusion Land Solder Fillet Shoulder Inclusion Pin Length Effective Pin True Position Pattern Relating and Feature R
27. ing Sheet 6 of 7 50 Figure A 13 603 Pin Interposer Assembly Drawing Sheet 7 of 7 51 mPGA604 Socket Design Guidelines intel Tables 2 1 3 1 4 1 4 2 4 4 5 1 mPGA604 Socket Design Guidelines Package Critical To Function CTF Dimensions sss sese ee nanen nene zere eee 11 Socket Critical to Function Dimensions 17 Electrical Requirements for Sockets eee eee eee eee 19 DefiNIONS AA ANENE 19 Resistance Test Fixtures Netlist AA 22 Netlist for FSETV4 Rev 1 Edge Fingers eee eee eee 27 Use Conditions Environment sisi 29 Revision History Revision aa cl eos Im e Initial release of the document October 2003 6 mPGA604 Socket Design Guidelines intel Re Validation Notice to Socket Vendors Any significant change to the socket will require submission of a detailed explanation of the change at least 60 days prior to the planned implementation Intel will review the modification and establish the necessary re validation procedure that the socket must pass Any testing that is required MUST be completed before the change is implemented Typical examples of significant changes include but are not limited to the following plastic material changes including base material or color contact changes including base material plating material or thickness and design modifications For details on validation testing requirements see Section 6 mPGA604 Socket Design Guidelines 7 This page intentionally left blank
28. ixtures Netlist Continued DC Endpoints Daisy of pins per Hi Low Chain chain mPGA604 Socket Design Guidelines Electrical Requirements Edgefingers Hi Edgefingers Low A66 A86 A68 23 intel Electrical Requirements i 4 2 Note 4 3 24 Determination of Maximum Electrical Resistance This section provides a guideline for the instruments used to take the measurements The instrument selection should consider the guidelines in ELA 364 23A 1 These measurements use a 4 wire technique where the instruments provide two separate circuits One is a precision current source to deliver the test current The other is a precision voltmeter circuit to measure the voltage drop between the desired points 2 These separate circuits can be contained within one instrument such as a high quality micro ohmmeter a stand alone current source and voltmeter or the circuits of a data acquisition system 3 Measurement accuracy in Q is specified as 0 1 of reading or 0 1 m Q whichever is greater The vendor is responsible for demonstrating that their instrument s can meet this accuracy 4 Automation of the measurements can be implemented by scanning the chains through the edge or cable test connector using a switch matrix The matrix can be operated by hand or through software 5 Measure Rrota for each daisy chain of package socket motherboard unit 6 Measure Riumper for each daisy chain of 30
29. mPGA604 Socket Design Guidelines Revision 1 0 October 2003 Document Number 254239 001 Notice This document contains information on produets in the design phase of development The information here is subject to change vvithout notice Do not finalize a design vvith this information Contact your local Intel sales office or your distributor to obtain the latest specification before placing your product order INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS EXCEPT AS PROVIDED IN INTEL S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO SALE AND OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE MERCHANTABILITY OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT Intel products are not intended for use in medical life saving or life sustaining applications Intel may make changes to specifications product descriptions and plans at any time without notice All dates are provided for planning purposes only and are subject to change without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them
30. o the motherboard and prevent the socket from being assembled incorrectly to the motherboard Critical to function CTF dimensions are identified in Table 3 1 The CTF values are detailed on the mPG A604 socket drawing in Figure A 5 and Figure A 6 and take precedence over all values presented in this document Dimensional requirements identified in the drawings and in Table 3 1 must be met These dimensions will be verified as part of the validation process Also supplier will provide and maintain Critical Process Parameters controlling these CTFs or will provide direct measurements to meet ongoing quality requirements Table 3 1 Socket Critical to Function Dimensions Dimension Socket Length Socket Width Socket Height Interposer surface from MB Assembled Seating Plane Flatness Ball Diameter True Position of Balls pattern relating Co planarity profile of Balls Actuation Distance Cover Travel Through Cavity X Through Cavity Y Cover Hole Diameter Must guarantee ZIF Cover Hole Countersink Depth Must guarantee ZIF Cover Hole Countersink Diameter Must guarantee ZIF Cover Hole Virtual Condition Pattern Locating Cover Hole Virtual Condition Feature Relating Cover Hole Field Depth wrt Seating Plane Cover Thickness in Hole area Au Thickness Ni Thickness Alignment Post Virtual Condition Contact Depth from Seating Plane
31. ockets shall be tested unmated and unmounted The sample size is 25 contact to contact pairs on each of four sockets The contacts shall be randomly chosen Contact Current Rating Measure and record the temperature rise when the socket is subjected to rated current of 0 8A The sockets shall be tested according to EIA 364 Test Procedure 70A Test Method 1 The sockets shall be mounted on a test board and mated with a package so those 603 pins are connected in series The recommended Test board is the FSET V4 Rev 1 and the recommended package is FSETVS Rev 1 The wiring list is shown below Mount the thermocouple as near to contact N3 or N7 as possible Short the daisy chains by means of the edge fingers if possible Sample size is one socket Table 4 4 Netlist for FSETV4 Rev 1 Edge Fingers Edge Fingers tl A61 Jumpers l A145 A85 A89 A45 A17 A135 A141 A59 A57 A129 A133 A7 A5 A87 A95 A15 A13 A139 A143 A49 A47 A131 A137 A3 A1 A101 A99 A11 A9 mPGA604 Socket Design Guidelines 27 Electrical Requirements 28 This page intentionally left blank mPGA604 Socket Design Guidelines 5 Environmental Requirements Design including materials shall be consistent with the manufacture of units that meet the follovving environmental reference points The reliability targets in this section are based on the expected field use environment for a desktop product The test sequence for new sockets will be developed using the knowledge based
32. ot exceed 1 27 mm Movement will be along the Y direction refer to axes as indicated in Figure A 5 No Z axis travel lift out of the package is allowed during actuation Orientation in Packaging Shipping and Handling Packaging media needs to support high volume manufacturing Contact Characteristics Number of Contacts Total number of contacts 603 Total number of contact holes 604 Base Material High strength copper alloy Contact Area Plating 0 762 um min gold plating over 1 27 um min nickel underplate in critical contact areas area on socket contacts where processor pins will mate is required No contamination by solder in the contact area is allowed during solder reflow Solder Ball Attachment Area Plating 3 81 um min Tin Lead typically 85 5Sn 15Pb Solder Ball Characteristics Tin Lead 63 37 0 596 Sn mPGA604 Socket Design Guidelines 15 intel Mechanical Requirements i 3 9 6 3 10 3 11 3 12 3 13 3 14 3 15 Lubricants For the final assembled product no lubricant is permitted on the socket contacts If lubricants are used elsewhere within the socket assembly these lubricants must not be able to migrate to the socket contacts Material and Recycling Requirements Cadmium shall not be used in the painting or plating of the socket CFCs and HFCs shall not be used in manufacturing the socket It is recommended that any plastic component exceeding 25g must be recyclable
33. package motherboard units Calculate R jumper for each daisy chain There is 30 data for each daisy chain 7 For each socket unit calculate D R Total R jumper R keq N Rreg is the average contact resistance for socket pin Inductance The bottom fixture for the inductance measurement is a ground plane on the secondary side of the motherboard with all pins grounded The component side of the socket PCB does not contain a plane The top fixture is the package which contains pins that will connect to the socket Figure 4 4 shows the inductance measurement fixture cross section and the inductance measurement methodology The first figure shows the entire assembly The second figure shows the assembly without the socket the socket seating plane of the package is directly mounted to the component side of the socket PCB This is used to calibrate out the fixture contribution The materials for the fixture must match the materials used in the processor Note the probe pad features exist on the topside of the top fixture and the shorting plane exists only on the bottom side of the bottom fixture Figure 4 5 presents the inductance and capacitance fixture design mPGA604 Socket Design Guidelines intel Electrical Requirements Figure 4 4 Inductance Measurement Fixture Cross Section eeng Pads Surface 40 mils Interposer No Features or Plane on this Layer Socket i Int rposer Pin Motherboard
34. r OS zan nd veti adi be cates sitat tt te En ER 14 3 5 1 CLA ra aeta aa aaa Ea iaaa 14 3 5 2 Lock Closed and Unlock Open Making 14 3 53 Bee TU E 14 3 6 leg 15 3 7 Socket Package Translation During Actuation eee eee eee eee eee eee eee 15 3 8 Orientation in Packaging Shipping and Handling 15 3 9 Contact e vT le e aaa a min ann nitrate 15 3 9 1 Number of Contacts 15 3 9 2 Bas Materials ss sans sntnenesteratnenntmrenenteanet eretenses 15 3 9 3 Contact Area Plang 15 3 9 4 Solder Ball Attachment Area Plating eee 15 3 9 5 Solder Ball Characteristics rrrnnnee 15 39 6 Biser 16 3 10 Material and Recycling Requirements A 16 3 11 Lever Actuation Requirements eee rene eee 16 3 12 Socket Engagement Disengagement Force 16 833 EE E 16 3 14 Socket BGA Go Planaritys aaa vura kubi rina ndi k do da innt 16 3 15 Solder Ball True Position is 16 3 16 Critical to Function Dimensions 17 Electrical Requirements rmmnansvennnnnnvnnnnnnnnvennnnnnvennnnnnvennnnnnnnnnnnnnnennnnnnnnnnnnnnnennnnnnnnennnnnnenn 19 4 1 Electrical R sistance vracza sdin credit dv dd aies 20 4 2 Determination of Maximum Electrical Resistance sse eee eee eee 24 4 3 INGUGTANCO EE 24 4 3 1 Design Procedure for Inductance Measurements 25
35. rrent edition and amendments e IEC60 950 most current edition and amendments mPGA604 Socket Design Guidelines 35 Safety Requirements 36 This page intentionally left blank mPGA604 Socket Design Guidelines intel 8 Documentation Requirements The socket supplier shall provide Intel with the following documentation e Multi Line Coupled SPICE models for socket e Product design guideline incorporating the requirements of these design guidelines e Recommended board layout guidelines for the socket consistent with low cost high volume printed circuit board technology The test facility shall provide Intel and the supplier with the following document e Validation Testing and Test Report supporting successful compliance with these design guidelines mPGA604 Socket Design Guidelines 37 Documentation Requirements 38 This page intentionally left blank mPGA604 Socket Design Guidelines intel A Appendix A Figure A 1 42 5 mm 604 Pin Package Assembly Drawing Sheet 1 of 3 THERMAL INTERFACE VATER IA mPGA604 Socket Design Guidelines 39 Appendix A Figure A 2 42 5 mm 604 Pin Package Assembly Drawing Sheet 2 of 3 Pme DENTAL mn 15 ISO TAL PRIOR ARTI CONSENT OF 1N me D Hi FP 889988989808681 889888889888881 TITT 888888888 888988968 888888888 Semer mm FH
36. tation contact your Intel field sales representative 6 2 Testing Facility Testing will be performed by Intel s designated test facility 6 3 Funding Socket supplier will fund socket validation testing for their socket Any additional testing that is required due to design modifications will also be at the expense of the supplier 6 4 Socket Design Verification At the earliest possible date a detailed drawing of the socket supplier s mPGA604 socket must be provided to Intel for review This drawing should include all of the features called out in this design guideline marking pinout cam location date code location and explanation etc as well as dimensional and board layout information This drawing will be used to confirm compliance to this design guideline 6 5 Reporting Test reports of the socket validation testing will be provided directly from the independent test facility to Intel Intel will also be given access to contact the test facility directly to obtain socket validation status explanation of test results and recommendations based on the test results 6 6 Process Changes Any significant change to the socket will require submission of a detailed explanation of the change at least 60 days prior to the planned implementation Intel will review the modification and establish the necessary re validation procedure that the socket must pass Any testing that is required MUST be completed before the change is implemented
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