Fujitsu MB15C02 User's Manual
Contents
1. SSOP 20 pin 1 20 Vss Clock 2 19 OSC NC 3 18 NC Data 4 17 OSCour Top LE 5 view 16 TEST fin 6 15 FG PS 7 14 8 13 LD 9 12 R Do 10 11 Vp FPT 20P M03 SSOP 16 pin 1 16 Vss Clock 2 15 OSCin Data 3 14 OSCourt LE 4 13 TEST fin 5 view 12 FC PS 6 11 oP 102198 Do 8 9 16 05 MB15C02 PIN DESCRIPTIONS Descriptions Power supply voltage Clock input for the shift register Schmitt trigger input Data is shifted into the shift register on the rising edge of the clock No connection Serial data input using binary code Schmitt trigger input Load enable signal input Schmitt trigger input When LE is high the data in the shift register is transferred to a latch according to the control bit in the serial data Prescaler input A bias circuit and amplifier are at input port Connection with an external VCO should be done by AC coupling Power saving mode control This pin must be set at at Power ON PS H Normal mode PS L Power saving mode No connection Lock detector signal output When a PLL is locking LD outputs H When a PLL is not locking LD outputs L Charge pump output Phase of the charge pump can be reversed by FC input The Do output may be inverted by FC input The relationship2. 1 0 1 1 1 3 1 4 Power supply voltage V 1 7 18 MB15C02 5 lbo Power Supply Current mA Input frequency power supply current 5 0 4 5 4 0 3 5 3 0 2 5 300 400 500 600 Input frequency MHz Vop 1 0 V 1 3 15 700 800 900 1000 MB15C02 6 Do Charge Pump Power Supply Voltage V ppo vs lo at Vo 0 2 V 5 0 25 4 5 4 0 3 5 3 0 mA 2 5 2 0 1 5 1 0 0 5 0 0 0 8 0 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 V pp vs at Vou V pp 0 2 V 25 b 0 8 0 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 19 MB15C02 7 Spectrum Wave Form ATTEN 10 dB UAUG 16 AMKR 85 50 dB RL 0 dBm 10dB 25 0 kHz e LOCK Frequency 286 0 MHz fr 2 25 kHz e Vpp 1 2V Vp 1 2V 25 G CENTER 286 0000 MHz SPAN 200 0 kHz RBW 1 0 kHz VBW 1 0 kHz SWP 1 00 s ATTEN 10 dB UAUG 50 AMKR 53 84 dB RL 0 dBm 10dB 800 Hz e LOCK Fr
3. FUJITSU MICROELECTRONICS DATA SHEET 0504 21348 3 ASSP Single Serial Input PLL Frequency Synthesizer On Chip prescaler MB15C02 DESCRIPTION The Fujitsu Microelectronics MB15C02 is a serial input Phase Locked Loop PLL frequency synthesizer with a prescaler A 64 65 division is available for the prescaler that enables pulse swallow operation This operates with a supply voltage of 1 0 V min MB15C02 is suitable for mobile communications such as paging systems FEATURES e High frequency operation 220 MHz 1 0 V to 1 5 V 330 MHz 1 2 V to 1 5 V 450 MHz 1 3 V to 1 5 V Single power supply Voo 1 0 to 1 5 V Power saving function Pulse swallow function 64 65 Serial input 14 bit programmable reference divider R 5 to 16 383 Serial input 18 bit programmable divider consisting of Binary 6 bit swallow counter 0 to 63 Binary 12 bit programmable counter 5 to 4 095 Wide operating temperature Ta 20 to 60 C PACKAGES 16 pin Plastic SSOP 20 pin Plastic SSOP 16 5 20 03 1999 2008 FUJITSU MICROELECTRONICS LIMITED rights reserved 1999 2 MB15C02 a s a PIN ASSIGNMENTS
4. 15 02 uses 19 bits of serial data for the programmable divider and 15 bits for the programmable reference divider When more bits of serial data than defined for the target divider are received only the last valid serial data bits are effective To set the divide ratio for the 5 2 dividers it is necessary to supply the Data Clock and LE signals at the timing shown in Figure 5 t 21 us Data setup time te 21 us Data hold time ts gt us Clock pulse width ta 21 us LE setup time to the rising edge of last clock ts 21 us LE pulse width LE t2 t3 gt lt t4 gt Figure 5 Serial data input timing MB15C02 Since the divide rations are unpredictable when the MB15C02 is turned on it is necessary to initialize the divide ratio for both dividers at power on time As shown in Figure 6 after setting the divide ratio for one of the dividers e g programmable reference divider set LE to H level before setting the divide ratio for the other dividers e g programmable divider To change the divide ratio of one of the divider after initialization input the serial data only for that divider the divide ratio for the other divider is preserved Serial data for program Serial data for program Data mable reference divider 1 mable divider 15 clocks 19 clocks Clock LE Control bit Figur
5. 1 2 1 3 Operating frequency Programmable divider 1 0 to 1 5V 1 2 to 1 5V 1 3 to 1 5V Programmable reference divider fin AC coupling Input sensitivit i OSCin AC coupling Input voltage fin and OSCin Except for H level L level Input current fin OSCin and TEST Except for H level ViN Vpp L level Vin GND Output voltage and oP Except for level loH 0 2 mA L level lo 0 2 mA L level lo 0 2 mA High impedance Vour GND to Ve cutoff current Vout 1 Conditions Inputs except for fin and TEST are grounded Outputs are opened Specifying the current flowing in and Vp at operating state under conditions of Vp fin 220 MHz or 330 MHz and OSCIN 12 8 MHz The current at locking state shows lop Supply current P 20 2 Conditions PS Low Inputs except for fin OSCi and TEST are grounded Outputs are opened 3 Condition Ta 25 C 4 Condition Ta 20 to 60 MB15C02 Gi a lt zss ll ll l lll FUNCTION DESCRIPTIONS 1 Pulse Swallow Function The divide ratio can be calculated using the following equation x A x lt fvco Output frequency of external voltage controlled oscillator VCO N Preset divide ratio of binary 12 bit
6. 15 02 circuits are active and provide the normal operation Power saving mode PS L The 15 02 stops any circuits that consume power heavily as well as cause little inconvenience when deactivated and enters the low power dissipation state Do and LD pins take the same state as when the PLL is locked Do pin becomes a high impedance state and the input voltage to the voltage control oscillator VCO is maintained at the same level as in active mode that is locked state according to a time constant of a low pass filter LPF Consequently the output frequency from the VCO fvco is maintained at approximately the lock frequency Applying the intermittent operation by alternating the active and power saving modes and also forcing the phases of fr and fp to synchronize when it switches from stand by to active modes the 15 02 can keep the power dissipation of its entire circuitry to the minimum 2 Programmable divider The fvco input through fin pin is divided by the programmable divider and then output to the phase comparator as fp It consists of a dual modulus prescaler a 6 bit binary swallow counter a 12 bit binary programmable counter and a controller which controls the divide ratio of the prescaler MB15C02 US Divide ratio range Prescaler M 64 M 1 65 Swallow counter 0 to 63 Programmable counter N 5 to 4095 The 15 02 uses the pulse swallow method consequently the divide rat
7. 4006 001 0 10 0 10 004 004 STAND OFF H i 4 0 10 0 50 0 20 4 55 179 REF 020 008 4 1994 FUJITSU LIMITED F16013S 20 4 Dimensions in mm inches Continued 23 24 MB15C02 Continued 20 pins Plastic SSOP 20 03 6 50 0 10 256 004 INDEX 4 40 0 10 6 40 0 20 173 004 252 008 Y Y 0 65 0 12 0 222905 0256 0047 009 2005 5 85 230 1994 FUJITSU LIMITED 200125 20 4 These dimensions do not include resin protrusion 020 a 1 25 2010 008 049 oo Mounting height 0 10 004 fu A EM gt 77 1 0 15 008 Details of A part 006 00 0 10 0 10 004 004 STAND OFF 0 50 0 20 020 008 Dimensions in mm inches MB15C02 MB15C02 MB15C02 FUJITSU MICROELECTRONICS LIMITED Shinjuku Dai Ichi Seimei Bldg 7 1 Nishishinjuku 2 chome Shinjuku ku Tokyo 163 0722 Japan Tel 81 3 5322 3347 Fax 81 3 5322 3387 http jp fujitsu com fml en For further information please contact North and South America
8. and equal to the phase error between fr and fp as shown in Figure 1 fp When FC L Do High Z oR oP 4 High Z When FC H Do E High Z P i High Z High Z High impedance state fp Nch open output Figure 1 Phase comparator input output waveform MB15C02 d Lock detector The lock detector detects the lock and unlock states of the PLL The lock detector outputs when the PLL enters the lock state and outputs L when the PLL enters the unlock state as shown in Figure 2 When PS L the lock detector outputs H compulsorily fr LIL IL dL dL d Figure 2 Phase comparator input output waveforms Lock detector MB15C02 G 4 Setting the Divide Ratio 1 Serial data format The format of the serial data is shown is Figure 3 The serial data is composed of a control bit and divide ratio setting data The control bit selects the programmable divider or programmable reference divider In case of the programmable divider serial data consists of 18 bits 6 bits for the swallow counter and 12 bits for the programmable counter and 1 control bit a
9. OSCour pin open and make connection with OSCin as AC coupling 16 20 Vss Ground pin BLOCK DIAGRAM 15 02 US Clock Data fin C PS Do Programmable reference divider gt gt Intermittent mode control circuit Binary 14 bit reference counter F 14 bit latch Control register uc Im 17 e gt 18 bit shift register 1 18 bit latch Y gt lt Prescaler Binary 6 bit Binary 12 bit swallow programma counter ble counter Lock detector PENNE i Control circuit lt Crystal oscillator circuit gt Phase C i comparator lt gt fp Output control gt circuit Output control gt gt circuit d Charge pump OSCin OSCour TEST oR MB15C02 Gi i ABSOLUTE MAXIMUM RATINGS Parameter Remark Power supply voltage 2 0 Input voltage 0 5 Output voltage 0 5 Output current 10 Storage temperature 125 WARNING Semiconductor devices can be pe
10. could have a serious effect to the public and could lead directly to death personal injury severe physical damage or other loss i e nuclear reaction control in nuclear facility aircraft flight control air traffic control mass transport control medical life support system missile launch control in weapon system or 2 for use requiring extremely high reliability 1 e submersible repeater and artificial satellite Please note that FUJITSU MICROELECTRONICS will not be liable against you and or any third party for any claims or damages arising in connection with above mentioned uses of the products Any semiconductor devices have an inherent chance of failure You must protect against injury damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy fire protection and prevention of over current levels and other abnormal operating conditions Exportation release of any products described in this document may require necessary procedures in accordance with the regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and or US export control laws The company names and brand names herein are the trademarks or registered trademarks of their respective owners Edited Strategic Business Development Dept
11. programmable counter 5 to 4 095 A Preset divide ratio of binary 6 bit swallow counter 0 to 63 fosc Output frequency of the reference frequency oscillator R Preset divide ratio of binary 14 bit programmable reference counter 5 to 16 383 M Preset modulus of dual modulus prescaler 64 2 Circuit Description 1 Intermittent operation The intermittent operation of the MB15C02 refers to the process of activating and deactivating its internal circuit thus saving power dissipation otherwise consumed by the circuit If the circuit is simply restarted from the power saving state however the phase relation between the reference frequency fr and the programmable frequency fp which are the input to the phase comparator is not stable even when they are of the same value This may cause the phase comparator to generate an excessively large error signal resulting in an out of synth lock frequency To preclude the occurrence of this problem the MB15C02 has an intermittent mode control circuit which forces the frequencies into phase with each other when the IC is reactivated thus minimizing the error signal and resultant lock frequency fluctuations The intermittent mode control circuit is controlled by the PS pin Setting pin PS high provides the normal operation mode and setting the pin low provides the power saving mode The 15 02 behavior in the active and power saving modes is summarized below Active mode PS All
12. 0 MHz PS NEN USAGE PRECAUTIONS This device should be transported and stored in anti static containers This is a static sensitive device take proper anti ESD precautions Ensure that personnel and equipment are properly grounded Cover workbenches with grounded conductive mats Always turn the power supply off before inserting or removing the device from its socket Protect leads with a conductive sheet when handling or transporting PC boards with devices ORDERING INFORMATION Parts number Package Remarks 16 pin Plastic SSOP 15 02 1 16 05 20 pin Plastic SSOP 15 2 2 20 03 22 MB15C02 u I n PACKAGE DIMENSIONS 16 pins Plastic SSOP ma These dimensions do not include resin protrusion 16 05 5 00 0 10 197 004 1 2550 Mounting height 049 004 111010 004 1 e i INDEX 440 0 10 6 40 0 20 5 40 213 173 004 252 008 0 65 0 12 0 222055 015328 Details of A part 0256 0047 004 002 7 009
13. FUJITSU MICROELECTRONICS AMERICA INC 1250 E Arques Avenue 5 333 Sunnyvale CA 94085 5401 U S A Tel 1 408 737 5600 Fax 1 408 737 5999 http www fma fujitsu com Europe FUJITSU MICROELECTRONICS EUROPE GmbH Pittlerstrasse 47 63225 Langen Germany Tel 49 6103 690 0 Fax 49 6103 690 122 http emea fujitsu com microelectronics Korea FUJITSU MICROELECTRONICS KOREA LTD 206 KOSMO TOWER 1002 Daechi Dong Kangnam Gu Seoul 135 280 Korea Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LTD 151 Lorong Chuan 05 08 New Tech Park Singapore 556741 Tel 65 6281 0770 Fax 65 6281 0220 http www fujitsu com sg services micro semiconductor FUJITSU MICROELECTRONICS SHANGHAI CO LTD Rm 3102 Bund Center No 222 Yan An Road E Shanghai 200002 China Tel 86 21 6335 1560 Fax 86 21 6335 1605 http cn fujitsu com fmc FUJITSU MICROELECTRONICS PACIFIC ASIA LTD 10 F World Commerce Centre 11 Canton Road Tsimshatsui Kowloon Hong Kong Tel 852 2377 0226 Fax 852 2376 3269 http cn fujitsu com fmc tw Tel 82 2 3484 7100 Fax 82 2 3484 7111 http www fmk fujitsu com All Rights Reserved The contents of this document are subject to change without notice Customers are advised to consult with sales representatives before ordering The information such as descriptions of function and application circuit examples in this document are presented solely for the purpose of reference to s
14. ch for the divider identified by the control bit is enabled and the divide ratio data from the shift register is loaded into the selected counter s Programmable reference divider 14 bit binary programmable reference counter b AND 14 bit latch 14 Data o mr 18 bit shift register Clock o LE o e Y m AND 18 bit latch 1 6 12 s Programmable Prescaler 6 bit binary swallow counter divider Control register Figure 4 The flow of serial data 3 Setting the divide ratio for the programmable divider Columns 0 to A5 of Table 2 1 represent the divide ratio of the swallow counter and columns NO to N11 of Table2 2 represent the divide ratio of programmable counter Table 2 Divide ratio for the programmable divider Table 2 1 Swallow counter divider A Table2 2 Programmable counter divider N Note Less than 5 is prohibited 13 MB15C02 14 4 Setting the divide ratio for the programmable reference divider Columns 13 of Table 3 represent the divide ratio of the programmable reference counter The control bit is set to 1 Table 3 Divide ratio for the programmable reference divider 5 Setting data input timing The
15. e 6 Inputting serial data Setting divisors 16 MB15C02 B TYPICAL CHARACTERISTICS 1 fin Input Sensitivity fin input frequency vs Input sensitivity 20 0 25 10 0 0 0 10 0 S E 20 0 9 30 0 E 40 0 Vo 1 0 V Poem Vpp 1 2 V 50 0 Vo 1 3V Vp 1 5 V 60 0 0 100 200 300 400 500 600 700 800 900 1000 fin input frequency MHz 2 OSC Input Sensitivity OSC N input frequency vs Input sensitivity 20 0 Ta 25 10 0 0 0 10 0 2 D 20 0 c o 8 30 0 40 0 Vpp 1 0 V EL 1 2 V 50 0 Vo 1 3V 15 60 0 0 50 100 150 200 250 300 350 400 450 500 OSC input frequency MHz 3 fin Power Supply Voltage MB15C02 Input frequency MHz MHz 1000 900 800 700 600 500 400 300 200 100 Power supply voltage vs fin input frequency Vfin 2 0 dBm Ta 25 G Power supply voltage V 4 OSCw Power Supply Voltage Input frequency MHz 500 450 400 350 300 250 200 150 100 50 0 9 Power supply voltage vs OSC in input frequency Vfin 2 0 dBm T Ta 25 C
16. equency 286 0 MHz fr 25 kHz e Vpp 1 2V Vp 1 2V 1 Ta 25 C D S 53 84 dB CENTER 286 00000 MHz SPAN 20 00 kHz RBW 100 Hz VBW 100 kHz SWP 3 00 s Test circuit Do W VT to VCO 15 43 T VCO Kv 6 MHz 6800 pF 1 4700 pF T 68000 pF 777 777 777 20 MB15C02 S E E 8 Lock Up Time LOCK Frequency 290 0 MHz to 286 0 MHz fr 25 kHz Voo 1 2 V Ve 1 2 V Ta 25 290 0 MHz 286 0 MHz within 1 kHz 4 00 ms AMKr x 3 99999984 ms A euts N A y 4 00100 MHz LL TN 286 0050 2 i 2 00 AUTA avo i l l kHz div l l 285 9950 MHz 0s 10 0000000 ms LOCK Frequency 286 0 MHz to 290 0 MHz fr 25 kHz Voo 1 2 V Ve 1 2 25 286 0 MHz 290 0 MHz within 1 kHz 6 20 ms AMKr x 6 19999943 ms A euts N A y 4 00082 MHz L 290 0050 MHz 2 00 kHz div 289 9950 MHz 0 0000000 ms Continued 21 MB15C02 Continued LOCK Frequency PS on to 286 0 MHz fr 2 25 kHz e Voo 1 2 Ve 1 2 V Ta 25 PS ON gt 286 0 MHz within 1 kHz 2 00 ms AMKr 1 99999978 ms euts y 680 Hz 286 0050 MHz 2 00 kHz div 285 995
17. how examples of operations and uses of FUJITSU MICROELECTRONICS device FUJITSU MICROELECTRONICS does not warrant proper operation of the device with respect to use based on such information When you develop equipment incorporat ing the device based on such information you must assume any responsibility arising out of such use of the information FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of the use of the information Any information in this document including descriptions of function and schematic diagrams shall not be construed as license of the use or exercise of any intellectual property right such as patent right or copyright or any other right of FUJITSU MICROELECTRONICS or any third party or does FUJITSU MICROELECTRONICS warrant non infringement of any third party s intellectual property right or other right by using such information FUJITSU MICROELECTRONICS assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein The products described in this document are designed developed and manufactured as contemplated for general use including without limitation ordinary industrial use general office use personal use and household use but are not designed developed and manufactured as contemplated 1 for use accompanying fatal risks or dangers that unless extremely high safety is secured
18. ions of the swallow and programmable counters must satisfy the relationship gt The total divide ratio of the programmable divider is calculated as follows Total divide ratio M 1 xA Mx N A MxN A 64xN A When N is set within 5 lt N lt 63 the possible divide ratio A of the swallow counter can take values 0 lt A lt N 1 because N must be greater than For example 0 lt A lt 19 is allowed when 20 but 20 lt lt 63 is not allowed in that case Consequently N gt 64 must be satisfied for the total divider to be set within 0 lt lt 63 The fp and fin have the following relation fp fin 64 x N A 3 Programmable reference divider The programmable reference divider divides the reference oscillation frequency fosc from the crystal oscillator connected between OSCin and OSCout pins or from the external oscillator input taken in directly through OSCin pin and then sends the resultant fr to the phase comparator It consists of a 14 bit binary programmable reference counter When the output from the external oscillator is to be input directly to OSCin pin the connection must be AC coupled and OSCout pin is left open Also to prevent OSCout from malfunctioning its traces on the printed circuit board must be kept minimal or eliminated entirely whenever possible it must be free of any form of load The following divider is used Programmable reference counter R 5 to 16383 The fr and fosc have the following relation fr fo
19. rmanently damaged by application of stress voltage current temperature etc in excess of absolute maximum ratings Do not exceed these ratings RECOMMENDED OPERATING CONDITIONS Parameter Remark For 220 MHz Power supply voltage 330 2 450 2 Input voltage Operating temperature WARNING The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device All of the device s electrical characteristics are warranted when the device is operated within these ranges Always use semiconductor devices within their recommended operating condition ranges Operation outside these ranges may adversely affect reliability and could result in device failure No warranty is made with respect to uses operating conditions or combinations not represented on the data sheet Users considering application outside the listed conditions are advised to contact their representatives beforehand ELECTRICAL CHARACTERISTICS Parameter Power supply current Active Mode MB15C02 For 220 MHz Vpp Vp 1 0 to 1 5 V Ta 20 to 60 C 330 MHz Vp 1 2 to 1 5 V Ta 20 to 60 C For 450 MHz Vp 1 3 to 1 5 V Ta 20 to 60 C Condition Voo 1 0V 220MHz 1 2 330 2 Voo 1 3V 450MHz Power saving current Power sav ing mode 1 0
20. s between the programmable reference divider output fr and the programmable divider output fp are shown below fr gt fp level FC L level FC H fr fp High impedance fr lt fp L level FC L H level FC Power supply for the charge pump Phase comparator output pin for external charge pump Relation between the programmable reference divider output fr and the programmable divider output fp are shown below When FC L fr gt fp oR L level oP L level fr fp dR L level oP High impedance fr lt fp H level High impedance When FC H fr gt fp H level High impedance fr fp pR L level High impedance fr lt fp oR L level oP L level No connection Phase comparator output pin for external charge pump Refer to Pin description for P pin is a Nch open drain output Phase comparator input select pin Test mode select pin Pull down resistor Please set this pin to ground or open usually Continued MB15C02 Continued Descriptions Oscillator output 14 17 5 Connection for external crystal _ 18 NC No connection Programmable reference divider input 15 19 OSC Oscillator input Clock can be input to OSCn from outside In the case please leave
21. s shown in Figure 3 1 In case of the programmable reference divider the serial data consists of 14 divider bits and 1 control bit as shown in Figure 3 2 The control bit is set to 0 to identify the serial data for the programmable divider to 1 to select the serial data for the programmable reference divider Figure 3 Serial data format LSB MSB Direction of data input 1 C A A A A A N N N N N N N N N N N 0 1 2 3 4 5 0 1 2 3 4 5 6 8 9 10 11 Swallow counter gt Programmable counter gt control bit Figure 3 1 Divide ratio for the programmable divider LSB MSB Direction of data input 1 C R R R R R R R R R RR R RR 0 1 2 3 4 5 6 7 8 9 10 11 12 13 Programmable reference counter gt control bit Figure 3 2 Divide ratio for the programmable reference divider MB15C02 2 The flow of serial data Serial data received via data pin in synchronization with the clock input and loaded into shift register which contains the divide ratio setting data and into the control register which contains the control bit The logical product through the AND gate in Figure 4 of LE and the control register output i e control bit is fed to the enable input of the latches Accordingly when LE is set high the lat
22. sc R 4 Phase comparator The phase comparator detects the phase difference between the outputs fr and fp from the dividers and generates an error signal that is proportional to phase difference The outputs from the phase comparator include 1 Do which takes on one of the three states namely L low H high and Z high impedance and is sent to the LPF 2 0 4 LD which indicates the PLL lock or unlock states a Phase comparator The phase comparator detects the phase error between fr and fp then generates an error signal that is proportional to the phase error The roles of the fr and fp supplied to the phase comparator may be reversed by switching the logical input level of pin FC This inverts the logical level of the Do output The logical level of Do output may be selected according to the characteristics of the external LPF and the VCO Refer to Table 1 Table 1 Phase comparator inputs output relationships FC L FC H oR oR MB15C02 b Charge pump The charge pump is available in two forms internal external Internal charge pump output Do External charge pump outputs oR oP c Phase comparator input output waveforms The phase comparator outputs logic levels summarized in Table 1 according to the phase error between fr and fp Note that oP is an Nch open drain output The pulse width of the phase comparator outputs are identical
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