Freescale Semiconductor EETX4K User's Manual
Contents
1. NOTE command write sequence aborted by writing 00 to ESTAT register NOTE command write sequence aborted by writing 00 to ESTAT register Write ECMD register Sector Modify Command 60 Write ESTAT register Clear CBEIF 80 Read ESTAT register Bit Polling for Command Completion Check Figure 4 7 Example Sector Modify Command Flow 4 1 4 Illegal EEPROM Operations The ACCERR flag will be set during the command write sequence if any of the following illegal steps are performed causing the command write sequence to immediately abort 38 M MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Ere s12EETX4KVO voo o4 Writing to an EEPROM address before initializing the ECLKDIV register Writing a byte or misaligned word to a valid EEPROM address Starting a command write sequence while a sector erase abort operation is active Writing to any EEPROM register other than ECMD after writing to an EEPROM address Writing a second command to the ECMD register in the same command write sequence Writing an invalid command to the ECMD register Writing to an EEPROM address after writing to the ECMD register Writing to any EEPROM register other than ESTAT to clear CBEIF after writing to the ECMD register pore Qvo cnp Me A EE 9 Writing a O to the CBEIF flag in the ESTAT register to abort a command write sequence The ACCERR flag will not be set if any EEPROM reg2. s12EETX4KVO voo o4 3 3 5 EPROT EEPROM Protection Register The EPROT register defines which EEPROM sectors are protected against program or erase operations Address Offset 04 7 6 5 4 3 2 1 0 Ni EPOPEN nG yo RNV4 EPDIS EPS2 EPS1 EPSO Reset F F F F F F F F Unimplemented or Reserved Figure 3 6 EEPROM Protection Register EPROT All bits in the EPROT register are readable and writable except for RNV 6 4 which are only readable The EPOPEN and EPDIS bits can only be written to the protected state The EPS bits can be written anytime until bit EPDIS is cleared If the EPOPEN bit is cleared the state of the EPDIS and EPS bits is irrelevant During the reset sequence the EPROT register is loaded from the EEPROM Protection byte at address offset _FFD see Table 3 1 EEPROM Configuration Field To change the EEPROM protection that will be loaded during the reset sequence the EEPROM memory must be unprotected then the EEPROM Protection byte must be reprogrammed Trying to alter data in any protected area in the EEPROM memory will result in a protection violation error and the PVIOL flag will be set in the ESTAT register The mass erase of an EEPROM block is possible only when protection is fully disabled by setting the EPOPEN and EPDIS bits EPOPEN Opens the EEPROM for program or erase 1 The EEPROM sectors not protected are enabled for program or erase 0 The entire EEPROM memory is pr
3. 4 1 3 EEPROM Commands Table 4 1 summarizes the valid EEPROM commands along with the effects of the commands on the EEPROM block Table 4 1 EEPROM Command Description ECMDB Function on EEPROM Memory Erase Verify all memory bytes in the EEPROM block are erased 05 Verif If the EEPROM block is erased the BLANK flag in the ESTAT register will set upon y command completion 28 M MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductoy Inc S12EETX4KVO V00 04 Table 4 1 EEPROM Command Description ECMDB Command Function on EEPROM Memory 20 Program Program a word two bytes in the EEPROM block Sector S40 Erase Erase all four memory bytes in a sector of the EEPROM block Mass Erase all memory bytes in the EEPROM block 41 rase A mass erase of the full EEPROM block is only possible when EPOPEN and EPDIS bits in the EPROT register are set prior to launching the command Abort the sector erase operation 47 Sector Erase The sector erase operation will terminate according to a set procedure The EEPROM Abort sector should not be considered erased if the ACCERR flag is set upon command completion Sector Erase all four memory bytes in a sector of the EEPROM block and reprogram the 60 Modify addressed word NOTE The user should not program an EEPROM word without first erasing the sector in which that word resides 4 1 3 1 Erase Verify Command The erase v
4. In background debug mode BDM the EPROT register is writable If the MCU is unsecured then all EEPROM commands listed in Table 4 1 can be executed If the MCU is secured and is in special single chip mode the only command available to execute is mass erase 4 5 EEPROM Module Security The EEPROM module does not provide any security information to the MCU After each reset the security state of the MCU is a function of information provided by the Flash module see the specific FTX Block Guide 4 5 1 Unsecuring the MCU in Special Single Chip Mode via the BDM Before the MCU can be unsecured in special single chip mode the EEPROM memory must be erased using the following method Reset the MCU into special single chip mode delay while the erase test is performed by the BDM secure ROM send BDM commands to disable protection in the EEPROM module and execute a mass erase command write sequence to erase the EEPROM memory After the CCIF flag sets to indicate that the EEPROM mass operation has completed and assuming that the Flash memory has also been erased reset the MCU into special single chip mode The BDM secure ROM will verify that the Flash and EEPROM memory are erased and will assert the UNSEC bit in the 40 M MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor ING s12EETX4KVO voo o4 BDM status register This BDM action will cause the MCU to override the Flash security state
5. algorithm An example flow to execute the sector modify operation is shown in Figure 4 7 The sector modify command write sequence is as follows 1 Write to an EEPROM memory address to start the command write sequence for the sector modify command The EEPROM address written determines the sector to be erased and word to be reprogrammed while byte address bit O is ignored M MOTOROLA 37 For More Information On This Product Go to www freescale com Block Guide s12EETx4kv if scale Semiconductor Inc 2 Write the sector modify command 60 to the ECMD register 3 Clear the CBEIF flag in the ESTAT register by writing a 1 to CBEIF to launch the sector erase command If an EEPROM sector to be modified is in a protected area of the EEPROM memory the PVIOL flag in the ESTAT register will set and the sector modify command will not launch Once the sector modify command has successfully launched the CCIF flag in the ESTAT register will set after the sector modify operation has completed unless a new command write sequence has been buffered Read ECLKDIV register Clock Register no NOTE ECLKDIV needs to Arten be set once after each reset yes Write ECLKDIV register Read ESTAT register Address Data Command Buffer Empty Check Access Error and Protection Violation Check Write ESTAT register Clear ACCERR PVIOL 30 Write EEPROM Word Address and program Data
6. be programmed is in a protected area of the EEPROM memory the PVIOL flag in the ESTAT register will set and the program command will not launch Once the program command has successfully launched the CCIF flag in the ESTAT register will set after the program operation has completed unless a new command write sequence has been buffered M MOTOROLA 31 For More Information On This Product Go to www freescale com Block Guide s12EETX4kv if scale Semiconductor Inc Read ECLKDIV register Clock Register Written Check no NOTE ECLKDIV needs to be set once after each reset Write ECLKDIV register yes Read ESTAT register Address Data Command Buffer Empty Check Access Error and Protection Violation Check yes Write ESTAT register Clear ACCERR PVIOL 30 Write EEPROM Address 1 and program Data A 3 NOTE command write sequence Write ECMD register d 2 Program Command 20 ETAT register 9 d 3 Write ESTAT register NOTE command write sequence aborted by writing 00 to Clear CBEIF 80 ESTAT register Read ESTAT register Bit Polling for Buffer Empty Check Sequential Programming Decision Bit Polling for Command Completion Check Figure 4 3 Example Program Command Flow 4 1 3 3 Sector Erase Command The sector erase operation will erase both words in a sector of EEPROM memory using an embedded algorithm 32 M MOT
7. bytes up to 4032 bytes L EEPROM Memory Protected Region 64 128 192 256 320 384 448 512 bytes EEPROM Configuration Field 16 bytes 5 FFC FFF Figure 3 1 EEPROM Memory Map M MOTOROLA 15 For More Information On This Product Go to www freescale com Block Guide s12EETX4kv if scale Semiconductor Inc The EEPROM module also contains a set of 12 control and status registers located between EEPROM register address offsets 00 and _0B A summary of the EEPROM module registers is given in Table 3 2 while their accessibility is detailed in section 3 3 Address Offset Table 3 2 EEPROM Register Map Register Name We EEPROM Clock Divider Register ECLKDIV RESERVED1 RESERVED EEPROM Configuration Register ECNFG EEPROM Protection Register EPROT EEPROM Status Register ESTAT EEPROM High Address Register EADDRHI EEPROM Low Address Register EADDRLO EEPROM High Data Register EDATAHI NOTES EEPROM Command Register ECMD RESERVED3 EEPROM Low Data Register EDATALO 1 Intended for factory test purposes only NOTE Register Address EEPROM Control Register Base Address Address Offset where the EEPROM Control Register Base Address is defined at the MCU level and the Address Offset is defined at the EEPROM module level 16 M MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Ere s1
8. ed adr ANG RE AA acad trou Akne qiia 41 4 6 1 EEPROM Reset Sequence 0 0 0c cece eee 41 4 6 2 Reset While EEPROM Command Active eee ees 41 4 7 MENUS A care Fa ae BS ta E aa oe er nuh iiic BTANA etes Sep 41 4 7 1 Description of EEPROM Interrupt Operation 2 000 eee eae 41 4 M MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductoy Inc S12EETX4KVO V00 04 List of Figures Figure 1 1 Module Block Diagram ue deter em Bis eta ed are EE E ERE 12 Figure 3 1 EEPROM Memory Map iis sis See Ee se PED TIT DR ESE PAK ER EP ENT 15 Figure 3 2 EEPROM Clock Divider Register ECLKDIV 0 17 Figile 3 3 RESERVED Tis is e E ascii Oc OX ee OE E ee eaten A 17 Figure 3 4 BESERVED2 creando ete bu qe bm abe iu E bodie a eater EO 18 Figure 3 5 EEPROM Configuration Register ECNFG a 18 Figure 3 6 EEPROM Protection Register EPROT 0 19 Figure 3 7 EEPROM Status Register ESTAT 00 e eee eee 20 Figure 3 8 EEPROM Command Register ECMD 00000 cee ee eee 22 Figure 3 9 BESERVEDS sr ARE EERS GEE EE a aca 22 Figure 3 10 EEPROM Address High Register EADDRHI 00 ss ee ee 23 Figure 3 11 EEPROM Address Low Register EADDRLO eie id ee ee ee 23 Figure 3 12 EEPROM Data High Register EDATAHI 02 23 Figure 3 13 EEPROM Data Low Register EDATALO Ee es ee ee ee 24 Figure 4 1 Determination
9. 2EETX4KVO voo o4 3 3 Register Descriptions 3 3 1 ECLKDIV EEPROM Clock Divider Register The ECLKDIV register is used to control timed events in program and erase algorithms Address Offset 00 7 6 5 4 3 2 1 0 Ne EDIVLD pRDIva Epivs EDIV4 EDIV3 EDIV2 EDIV1 EDIVO RESET 0 0 0 0 0 0 o 9 Unimplemented or Reserved Figure 3 2 EEPROM Clock Divider Register ECLKDIV All bits in the ECLKDIV register are readable bits 6 0 are write once and bit 7 is not writable EDIVLD Clock Divider Loaded 1 Register has been written to since the last reset 0 Register has not been written PRDIV8 Enable Prescalar by 8 1 Enables a prescalar by 8 to divide the oscillator clock before feeding into the clock divider 0 The oscillator clock is directly fed into the ECLKDIV divider EDIV 5 0 Clock Divider Bits The combination of PRDIV8 and EDIV 5 0 effectively divides the EEPROM module input oscillator clock down to a frequency of 150kHz 200kHz The maximum divide ratio is 512 Please refer to section 4 1 1 for more information 3 3 2 RESERVED1 This register is reserved for factory testing and is not accessible Address Offset 01 7 6 5 4 3 2 1 0 VM 8027 41 NU CK at RESTE ERE E t 0 0 0 0 0 0 0 0 eset Unimplemented or Reserved Figure 3 3 RESERVED1 All bits read zero and are not writable M MOTOROLA 17 For More Information On This Product Go to www freescale com Block Guid
10. All EDHI and EDLO bits are readable and writable in special modes 24 M MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Ere s12EETX4KVO voo o4 Section 4 Functional Description 4 1 EEPROM Command Operations Write and read operations are both used for the program erase erase verify sector erase abort and sector modify algorithms described in this section The program erase and sector modify algorithms are controlled by a state machine whose timebase EECLK is derived from the oscillator clock via a programmable divider The command register as well as the associated address and data registers operate as a buffer and a register 2 stage FIFO so that a second command along with the necessary data and address can be stored to the buffer while the first command is still in progress Buffer empty as well as command completion are signalled by flags in the EEPROM status register with interrupts generated if enabled The next sections describe 1 How to write the ECLKDIV register 2 Command write sequences to program erase erase verify sector erase abort and sector modify operations on the EEPROM memory Valid EEPROM commands 4 Effects resulting from illegal EEPROM command write sequences or aborting EEPROM operations 4 1 1 Writing the ECLKDIV Register Prior to issuing any EEPROM command after a reset the user is required to write the ECLKDIV register to divide the o
11. CU instruction sequence to execute built in algorithms including program and erase on the EEPROM memory 1 2 Features e 4K bytes of EEPROM memory divided into 1024 sectors of 4 bytes e Automated program and erase algorithm nterrupts on EEPROM command completion and command buffer empty e Fast sector erase and word program operation e 2 stage command pipeline e Sector erase abort feature for critical interrupt response e Flexible protection scheme to prevent accidental program or erase e Single power supply for all EEPROM operations including program and erase 1 3 Modes of Operation e Program erase and erase verify operations please refer to section 4 1 for details 11 M MOTOROLA For More Information On This Product Go to www freescale com Block Guide s12EETX4kv if scale Semiconductor Inc 1 4 Block Diagram A block diagram of the EEPROM module is shown in Figure 1 1 EEPROM Interface Command Interrupt Command Pipeline Request EEPROM cmd2 cmd1 addr2 addr1 2K 16 Bits data2 data1 l Registers EN sector 1023 Oscillator Clock Clock Divider Figure 1 1 Module Block Diagram 12 M MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Section 2 External Signal Description 2 1 Overview The EEPROM module contains no signals that connect off chip M MOTOROLA For More Information On This Product Go to www freescale c
12. Freescale Semiconductor Inc DOCUMENT NUMBER S12EETXAKVO EETXAK Block Guide VOO 04 Original Release Date 7 JUL 2003 Revised 30 OCT 2003 Motorola Inc Motorola reserves the right to make changes without further notice to any products herein Motorola makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Motorola assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation conseguential or incidental damages Typical parameters which may be provided in Motorola data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts Motorola does not convey any license under its patent rights nor the rights of others Motorola products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur Should Buyer purchase or use Motorola products for any such unintended or unauthorized application Buyer shall indemnify and hold Motorola and its off
13. KDIV needs to be set once after each reset yes Write ECLKDIV register Read ESTAT register Address Data Command Buffer Empty Check Access Error and Protection Violation Check Write ESTAT register Clear ACCERR PVIOL 30 Write EEPROM Address and Dummy Data NOTE command write sequence aborted by writing 00 to ESTAT register NOTE command write sequence aborted by writing 00 to ESTAT register 3 Write ESTAT register Clear CBEIF 80 Bit Polling for Command Completion Check Figure 4 5 Example Mass Erase Command Flow 4 1 3 5 Sector Erase Abort Command The sector erase abort operation will terminate the active sector erase or sector modify operation so that other sectors in an EEPROM block are available for read and program operations without waiting for the sector erase or sector modify operation to complete Anexample flow to execute the sector erase abort operation is shown in Figure 4 6 The sector erase abort command write sequence is as follows M MOTOROLA 35 For More Information On This Product Go to www freescale com Block Guide s12EETX4kv if scale Semiconductor Inc 1 Write to any EEPROM memory address to start the command write sequence for the sector erase abort command The address and data written are ignored 2 Write the sector erase abort command 47 to the ECMD register Clear the CBEIF flag in the ESTAT regi
14. OROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Ere s12EETX4KVO voo o4 An example flow to execute the sector erase operation is shown in Figure 4 4 The sector erase command write sequence is as follows 1 Write to an EEPROM memory address to start the command write sequence for the sector erase command The EEPROM address written determines the sector to be erased while global address bits 1 0 and the data written are ignored 2 Write the sector erase command 40 to the ECMD register Clear the CBEIF flag in the ESTAT register by writing a 1 to CBEIF to launch the sector erase command If an EEPROM sector to be erased is in a protected area of the EEPROM memory the PVIOL flag in the ESTAT register will set and the sector erase command will not launch Once the sector erase command has successfully launched the CCIF flag in the ESTAT register will set after the sector erase operation has completed unless a new command write sequence has been buffered 33 M MOTOROLA For More Information On This Product Go to www freescale com Block Guide s12EETX4kv if scale Semiconductor Inc Read ECLKDIV register Clock Register Written Check NOTE ECLKDIV needs to be set once after each reset Write ECLKDIV register Read ESTAT register Address Data Command Buffer Empty Check Access Error and Protection Violation Check Wr
15. Procedure for PRDIV8 and EDIV Bits 27 Figure 4 2 Example Erase Verify Command Flow ee eee eee 30 Figure 4 3 Example Program Command Flow eee eee eee eee 32 Figure 4 4 Example Sector Erase Command Flow 0 ee ee eee eee 34 Figure 4 5 Example Mass Erase Command Flow ee ee ee ee ke ee 35 Figure 4 6 Example Sector Erase Abort Command FIOW ie ee aaa 37 Figure 4 7 Example Sector Modify Command Flow iii ee EE ee Ee ee ee ee 38 Figure 4 8 EEPROM Interrupt Implementation is ee EE Ee ee ee ee ee eee 42 M MOTOROLA 5 For More Information On This Product Go to www freescale com Block Guide st2EErxakva o fiscale Semiconductor Inc 6 M MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductoy Inc S12EETX4KVO V00 04 List of Tables Table 3 1 EEPROM Configuration Field 0 200 ees 14 Table 3 2 EEPROM Register Map s a sa ctricos 16 Table 3 3 EEPROM Protection Address Range cece eee eee 20 Table 3 4 Valid EEPROM Command List oou ie bs ted it hah bas REDE 22 Table 4 1 EEPROM Command Description ie EE SE ek ee dd ee ee 28 Table 4 2 EEPROM Interrupt SourceS iss se es se ee ees 41 M MOTOROLA 7 For More Information On This Product Go to www freescale com Block Guide st2EErxakva o fiscale Semiconductor Inc 8 M MOTOROLA For More Information On This Produc
16. TOROLA For More Information On This Product Go to www freescale com
17. acy of the functional timings programming or erasing the EEPROM memory cannot be performed if the bus clock runs at less than 1 MHz Programming or erasing the EEPROM memory with EECLK lt 150kHz should be avoided Setting ECLKDIV to a value such that EECLK lt 150kHz can destroy the EEPROM memory due to overstress Setting ECLKDIV to a value such that I EECLK Tbus lt 5us can result in incomplete programming or erasure of the EEPROM memory cells If the ECLKDIV register is written the EDIVLD bit is set automatically If the EDIVLD bit is zero the ECLKDIV register has not been written since the last reset If the ECLKDIV register has not been written to the EEPROM command loaded during a command write sequence will not execute and the ACCERR flag in the ESTAT register will set 26 M MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductoy Inc START S12EETX4KVO V00 04 ALL COMMANDS IMPOSSIBLE PRDIV8 0 reset oscillator_clock gt 12 8MHz PRDIV8 1 PRDCLK oscillator_clock 8 PRDCLK oscillator clock no PRDCLK MHz 5 Tbus ps an integer EDIV 5 0 INT PRDCLK MHz 54 Tbus us yes EDIV 5 0 PRDCLK MHz 5 Tbus ps 1 TRY TO DECREASE Tbus EECLK PRDCLK 1 EDIV 5 0 1 EECLK MHz Tbus us gt 5 AND EECLK gt 0 15MHz EDIV 5 0 gt 4 ALL COMMANDS IMPOSSIBLE Figure 4 1 Determina
18. and the MCU will be unsecured Once the MCU is unsecured BDM commands will be enabled and the Flash security byte may be programmed to the unsecure state 4 6 Resets 4 6 1 EEPROM Reset Sequence On each reset the EEPROM module executes a reset sequence to hold CPU activity while loading the EPROT register from the EEPROM memory according to Table 3 1 4 6 2 Reset While EEPROM Command Active If a reset occurs while any EEPROM command is in progress that command will be immediately aborted The state of a word being programmed or the sector block being erased is not guaranteed 4 7 Interrupts The EEPROM module can generate an interrupt when all EEPROM command operations have completed when the EEPROM address data and command buffers are empty Table 4 2 EEPROM Interrupt Sources Interrupt Source Interrupt Flag Local Enable MORS eU EEPROM Address Data and CBEIF CBEIE I Bit Command Buffers empty ESTAT register ECNFG register CCIF CCIE f All EEPROM commands completed ESTAT register ECNFG register l Bit Vector addresses and their relative interrupt priority are determined at the MCU level 4 7 1 Description of EEPROM Interrupt Operation The logic used for generating interrupts is shown in Figure 4 8 The EEPROM module uses the CBEIF and CCIF flags in combination with the CBIE and CCIE enable bits to generate the EEPROM command interrupt request M MOTOROLA 41 For More Information On Th
19. be buffered behind it If an attempt is made to start anew command write sequence with a sector erase abort operation active the ACCERR flag in the ESTAT register will be set Anew command write sequence may be started after clearing the ACCERR flag if set NOTE The sector erase abort command should be used sparingly since a sector erase operation that is aborted counts as a complete program erase cycle 36 M MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor ING s12EETX4KVO voo o4 Execute Sector Erase Modify Command Flow Read ESTAT register Bit Polling for Command Completion Check Sector Erase Completed Write Dummy EEPROM Address and Dummy Data NOTE command write sequence Ee a aborted by writing 00 to 2 Write ECMD register ESTAT register Sector Erase Abort Cmd 47 NOTE command write sequence aborted by writing 00 to Write ESTAT register ESTAT register g3 3 Clear CBEIF 80 Read ESTAT register Bit Polling for Command Completion Check yes Access yes ac Error Check Write ESTAT register Clear ACCERR 10 Sector Erase or Modify Completed Sector Erase or Modify Aborted Figure 4 6 Example Sector Erase Abort Command Flow 4 1 3 6 Sector Modify Command The sector modify operation will erase both words in a sector of EEPROM memory followed by a reprogram of the addressed word using an embedded
20. bt eer ro elena Du qe C ween be GE 17 3 3 3 RESERVED aaa GAW n bite Qa PT bem dw SRM Gaara ps 18 3 3 4 ECNFG EEPROM Configuration Register a 18 3 3 5 EPROT EEPROM Protection Register 2000 ed eee 19 3 3 6 ESTAT EEPROM Status Register 0 000 eee ees 20 3 3 7 ECMD EEPROM Command Register 20002 cece eee eee 21 3 3 8 RESERVE DO kaaa a A ie teneo seem hav ase pan QURE AR e 22 3 3 9 EADDR EEPROM Address Registers 000 eee eee eee 23 3 3 10 EDATA EEPROM Data Registers 2 ce eee eee eee 23 Section 4 Functional Description 4 1 EEPROM Command Oberatlofis s ss RASSE WERE ete EU ARE treated ae EDGE DER 25 4 1 1 Writing the ECLKDIV Register us sie rearing Renae prac Sn NAG she tes 25 4 1 2 Command Write Sequence s auc dur aa ghee de ER EES Er RE phe Sees 28 4 1 3 EEPROM Commands ts ete m d ee ts Mete ge tale 6 MC 28 4 1 4 Ned EEPROM Op rationS o desc KAN EIS wee xe eR PR RE Dea 38 4 2 A RT DE Ts 40 43 SSOP MOOS aortic EN EE EED SE EE eod esit hee EE EE oe eines 40 M MOTOROLA 3 For More Information On This Product Go to www freescale com seem vo e gscale Semiconductor Inc Block Guide 44 Background Debug Mode 2 sta ka LR eee NG wa e entes 40 45 EEPROM Module Security red cette tk eX RE atte tone dtt ERE RE ins 40 4 5 1 Unsecuring the MCU in Special Single Chip Mode via the BDM 40 46 MESS Suum Decet on por aer
21. e s12eerxa vo e fiscale Semiconductor Inc 3 3 3 RESERVED2 This register is reserved for factory testing and is not accessible Address Offset 02 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 W He Ho Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 3 4 RESERVED2 All bits read zero and are not writable 3 3 4 ECNFG EEPROM Configuration Register The ECNFG register enables the EEPROM interrupts Address Offset 03 7 6 5 4 3 2 1 0 CBEIE CCIE 2 9 2 0 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 3 5 EEPROM Configuration Register ECNFG CBEIE and CCIE bits are readable and writable while all remaining bits read zero and are not writable CBEIE Command Buffer Empty Interrupt Enable The CBEIE bit enables an interrupt in case of an empty command buffer in the EEPROM module 1 An interrupt will be requested whenever the CBEIF flag see 3 3 6 ESTAT EEPROM Status Register is set 0 Command Buffer Empty interrupt disabled CCIE Command Complete Interrupt Enable The CCIE bit enables an interrupt in case all commands have been completed in the EEPROM module 1 An interrupt will be requested whenever the CCIF flag see 3 3 6 ESTAT EEPROM Status Register is set 0 Command Complete interrupt disabled 18 M MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Ing
22. erify operation will verify that the EEPROM memory is erased An example flow to execute the erase verify operation is shown in Figure 4 2 The erase verify command write sequence is as follows 1 Write to an EEPROM address to start the command write sequence for the erase verify command The address and data written will be ignored 2 Write the erase verify command 05 to the ECMD register 3 Clear the CBEIF flag in the ESTAT register by writing a 1 to CBEIF to launch the erase verify command After launching the erase verify command the CCIF flag in the ESTAT register will set after the operation has completed unless a new command write sequence has been buffered The number of bus cycles required to execute the erase verify operation is equal to the number of words in the EEPROM memory plus 14 bus cycles as measured from the time the CBEIF flag is cleared until the CCIF flag is set Upon completion of the erase verify operation the BLANK flag in the ESTAT register will be set if all addresses in the EEPROM memory are verified to be erased If any address in the EEPROM memory is not erased the erase verify operation will terminate and the BLANK flag in the ESTAT register will remain clear M MOTOROLA 29 For More Information On This Product Go to www freescale com Block Guide s12EETX4kv if scale Semiconductor Inc Read ECLKDIV register Clock Register Written Check NOTE ECLKDIV needs to be
23. icers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part Motorola and AA are registered trademarks of Motorola Inc Motorola Inc is an Egual Opportunity Affirmative Action Employer E Motorola Inc 2001 M MOTOROLA 1 For More Information On This Product Go to www freescale com Block Guide st2EErxakva o fiscale Semiconductor Inc Revision History 2 M MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductoy Inc S12EETX4KVO V00 04 Table of Contents Section 1 Introduction CI NA PA EK 11 1 1 1 ROS SAMY EE ay ER E Se ates pence mara E I iE 11 12 AFECTOS LAER at tek bean eee ge NEWER DER Goh neat aes dere ne en 11 1 35 Modes f Operation Za NAKA A E a ED ag An ee 11 14 Bloc Diagram e ccoo cdas SEER iets EDGE ES een wees 12 Section 2 External Signal Description BUG ENE ER 13 Section 3 Memory Map and Registers ENE s AE EN AR STE PA 14 3 2 Module Memory Maboe tcr osa E AA EDE EE T 14 3 3 Register Descriptions uo is EE SE Nag EE BEE GER EE EI du Be S A E 17 3 3 1 ECLKDIV EEPROM Clock Divider Register ii Aa 17 3 3 2 RESERVED Ms Aa rp NI a
24. is Product Go to www freescale com Block Guide s12EETX4kv if scale Semiconductor Inc CBEIF CBEIE EEPROM Command Interrupt Request CCIF CCIE Figure 4 8 EEPROM Interrupt Implementation For a detailed description of the register bits refer to the EEPROM Configuration register and EEPROM Status register sections see sections 3 3 4 and 3 3 6 respectively 42 M MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Ere s12EETX4KVO voo o4 Index ES Security 40 Stop Mode 40 ACCERR 21 Wait Mode 40 B Background Debug Mode 40 BLANK 21 C CBEIE 18 CBEIF 20 CCIE 18 CCIF 20 CMDB 22 Command Write Sequence 11 E EDIV 17 EDIVLD 17 EPDIS 19 EPOPEN 19 EPS 19 zT Illegal EEPROM Operations 38 K KEYACC 19 p PRDIV8 17 PVIOL 21 R Registers EADDR 23 ECLKDIV 17 ECMD 21 ECNFG 18 EDATA 23 EPROT 19 ESTAT 20 Resets 41 RNV 19 M MOTOROLA 43 For More Information On This Product Go to www freescale com Block Guide st2EErxakva o fiscale Semiconductor Inc 44 M MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductoy Inc Block Guide End Sheet M MOTOROLA For More Information On This Product Go to www freescale com S12EETX4KVO V00 04 45 seem vo e gscale Semiconductor Inc Block Guide FINAL PAGE OF 46 PAGES 46 M MO
25. ister is read during a valid command write sequence The ACCERR flag will also be set if any of the following events occur 1 Launching the sector erase abort command while a sector erase or sector modify operation is active which results in the early termination of the sector erase or sector modify operation see section 4 1 3 5 2 The MCU enters STOP mode and a command operation is in progress The operation is aborted immediately and any pending command is purged see section 4 3 If the EEPROM memory is read during execution of an algorithm CCIF 0 the read operation will return invalid data and the ACCERR flag will not be set If the ACCERR flag is set in the ESTAT register the user must clear the ACCERR flag before starting another command write sequence see section 3 3 6 The PVIOL flag will be set after the command is written to the ECMD register during a command write sequence if any of the following illegal operations are attempted causing the command write sequence to immediately abort 1 Writing the program command if the address written in the command write sequence was in a protected area of the EEPROM memory 2 Writing the sector erase command if the address written in the command write sequence was in a protected area of the EEPROM memory 3 Writing the mass erase command to the EEPROM memory while any EEPROM protection is enabled 4 Writing the sector modify command if the address written in the command
26. isters If the CBEIF flag in the ESTAT register is clear when the first EEPROM array write occurs the contents of the address and data buffers will be overwritten and the CBEIF flag will be set When the CBEIF flag is cleared the CCIF flag is cleared on the same bus cycle by the EEPROM command controller indicating that the command was successfully launched For all command write sequences except sector erase abort the CBEIF flag will set four bus cycles after the CCIF flag is cleared indicating that the address data and command buffers are ready for a new command write sequence to begin For sector erase abort operations the CBEIF flag will remain clear until the operation completes Except for the sector erase abort command a buffered command will wait for the active operation to be completed before being launched The sector erase abort command is launched when the CBEIF flag is cleared as part of a sector erase abort command write sequence Once a command is launched the completion of the command operation is indicated by the setting of the CCIF flag in the ESTAT register The CCIF flag will set upon completion of all active and buffered commands A command write sequence can be aborted prior to clearing the CBEIF flag in the ESTAT register by writing a O to the CBEIF flag and will result in the ACCERR flag in the ESTAT register being set The ACCERR flag in the ESTAT register must be cleared prior to starting a new command write sequence
27. ite ESTAT register Clear ACCERR PVIOL 30 Write EEPROM Sector Address and Dummy Data NOTE command write sequence 2 aborted by writing 00 to ESTAT register NOTE command write sequence 3 aborted by writing 00 to ESTAT register Figure 4 4 Example Sector Erase Command Flow 4 1 3 4 Mass Erase Command The mass erase operation will erase all addresses in an EEPROM block using an embedded algorithm An example flow to execute the mass erase operation is shown in Figure 4 5 The mass erase command write sequence is as follows 1 Write toan EEPROM memory address to start the command write sequence for the mass erase command The address and data written will be ignored 2 Write the mass erase command 41 to the ECMD register 3 Clear the CBEIF flag in the ESTAT register by writing a 1 to CBEIF to launch the mass erase command 34 M MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Iner s12EETX4KVO voo o4 If the EEPROM memory to be erased contains any protected area the PVIOL flag in the ESTAT register will set and the mass erase command will not launch Once the mass erase command has successfully launched the CCIF flag in the ESTAT register will set after the mass erase operation has completed unless a new command write sequence has been buffered Read ECLKDIV register Clock Register Written Check NOTE ECL
28. n This Product Go to www freescale com Freescale Semiconductoy Inc S12EETX4KVO V00 04 3 3 9 EADDR EEPROM Address Registers The EADDRHI and EADDRLO registers are the EEPROM address registers Address Offset 5S 08 7 6 5 4 3 2 1 0 R 0 0 0 0 0 EABHI W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 3 10 EEPROM Address High Register EADDRHI Address Offset 09 7 6 5 4 3 2 1 0 Bi CPP aes A A RE eset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 3 11 EEPROM Address Low Register EADDRLO All EABHI and EABLO bits read zero and are not writable in normal modes All EABHI and EABLO bits are readable and writable in special modes The MCU address bit ABO is not stored in the EADDR registers since the EEPROM block is not byte addressable 3 3 10 EDATA EEPROM Data Registers The EDATAHI and EDATALO registers are the EEPROM data registers Address Offset 0A 7 6 5 4 3 2 1 0 R EDHI w Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 3 12 EEPROM Data High Register EDATAHI M MOTOROLA 23 For More Information On This Product Go to www freescale com Block Guide S12EETxakvonhe scale Semiconductor Inc Address Offset OB 7 6 5 4 3 2 1 0 sa t 0 0 0 0 0 0 0 0 eset Unimplemented or Reserved Figure 3 13 EEPROM Data Low Register EDATALO All EDHI and EDLO bits read zero and are not writable in normal modes
29. om S12EETX4KVO V00 04 Block Guide st2EErxakva o fiscale Semiconductor Inc Section 3 Memory Map and Registers 3 1 Overview This section describes the memory map and registers for the EEPROM module 3 2 Module Memory Map A linear EEPROM memory map is shown in Figure 3 1 The HCS12X architecture actually places the EEPROM memory addresses between logical addresses 0800 and 1000 with 0800 to 0BFF representing 1K byte of paged EEPROM memory and 0C00 to OFFF representing 1K byte of fixed EEPROM memory The EPROT register described in section 3 3 5 can be set to protect the upper region in the EEPROM memory from accidental program or erase The EEPROM addresses covered by this protectable region are shown in the EEPROM memory map The default protection setting is stored in the EEPROM configuration field as described in Table 3 1 Table 3 1 EEPROM Configuration Field EEPROM Memory Size Address Offset bytes Description FFC 1 Reserved EEPROM Protection byte FFD Refer to Section 3 3 5 EPROT EEPROM Protection Register FFE FFF Reserved 14 M MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductoy Inc a ADDRESS OFFSET 00 ADDRESS OFFSET 0B EEPROM BASE 000 _E00 _E40 E80 ECO F00 5 F40 _F80 _FCO EEPROM BASE 5 FFF S12EETX4KVO V00 04 EEPROM Registers 12 bytes EEPROM Memory 3584
30. otected from program and erase RNV 6 4 Reserved Non Volatile Bits The RNV 6 4 bits should remain in the erased state 1 for future enhancements EPDIS EEPROM Protection address range Disable The EPDIS bit determines whether there is a protected area in a specific region of the EEPROM memory ending with address offset _FFF 1 Protection disabled 0 Protection enabled EPS 2 0 EEPROM Protection Address Size The EPS 2 0 bits determine the size of the protected area as shown inTable 3 3 The EPS bits can only be written to while the EPDIS bit is set M MOTOROLA 19 For More Information On This Product Go to www freescale com Block Guide s12EETX4kv if scale Semiconductor Inc Table 3 3 EEPROM Protection Address Range EPS 2 0 Me ange Protected Size 000 FCO FFF 64 bytes 001 F80 FFF 128 bytes 010 F40 FFF 192 bytes 011 F00 5 FFF 256 bytes 100 ECO FFF 320 bytes 101 E80 FFF 384 bytes 110 E40 5 FFF 448 bytes 111 _E00 _FFF 512 bytes 3 3 6 ESTAT EEPROM Status Register The ESTAT register defines the operational status of the module Address Offset 5 05 7 6 5 4 3 2 1 0 E ACCERR 2 BLANK OT ka ET AA GAT A A eset 1 1 0 0 0 0 0 0 Unimplemented or Reserved Figure 3 7 EEPROM Status Register ESTAT CBEIF PVIOL and ACCERR are readable and writable CCIF and BLANK are readable and not writable remaining bits read ze
31. peration The BLANK flag is cleared by the EEPROM module when CBEIF is cleared as part of a new valid command write sequence Writing to the BLANK flag has no effect on BLANK 1 EEPROM block verified as erased 0 EEPROM block verified as not erased 3 3 7 ECMD EEPROM Command Register The ECMD register is the EEPROM command register M MOTOROLA 21 For More Information On This Product Go to www freescale com Block Guide s12EETx4kv if scale Semiconductor Inc Address Offset 06 7 6 5 4 3 2 1 0 ja ER EUR CMDB MEN Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 3 8 EEPROM Command Register ECMD All CMDB bits are readable and writable during a command write sequence while bit 7 reads zero and is not writable CMDB 6 0 Valid EEPROM commands are shown in Table 3 4 Writing any command other than those listed in Table 3 4 sets the ACCERR flag in the ESTAT register Table 3 4 Valid EEPROM Command List CMDB 6 0 Command 05 Erase Verify 20 Word Program 40 Sector Erase 41 Mass Erase 47 Sector Erase Abort 60 Sector Modify 3 3 8 RESERVED3 This register is reserved for factory testing and is not accessible Address Offset 07 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 vla gt Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 3 9 RESERVED3 All bits read zero and are not writable 22 M MOTOROLA For More Information O
32. ro and are not writable CBEIF Command Buffer Empty Interrupt Flag The CBEIF flag indicates that the address data and command buffers are empty so that a new command write sequence can be started The CBEIF flag is cleared by writing a 1 to CBEIF Writing a 0 to the CBEIF flag has no effect on CBEIF Writing a O to CBEIF after writing an aligned word to the EEPROM address space but before CBEIF is cleared will abort a command write sequence and cause the ACCERR flag to be set Writing a O to CBEIF outside of a command write sequence will not set the ACCERR flag The CBEIF flag is used together with the CBEIE bit in the ECNFG register to generate an interrupt request see Figure 4 8 1 Buffers are ready to accept a new command 0 Buffers are full CCIF Command Complete Interrupt Flag 20 M MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Ere s12EETX4KVO voo o4 The CCIF flag indicates that there are no more commands pending The CCIF flag is cleared when CBEIF is clear and sets automatically upon completion of all active and pending commands The CCIF flag does not set when an active commands completes and a pending command is fetched from the command buffer Writing to the CCIF flag has no effect on CCIF The CCIF flag is used together with the CCIE bit in the ECNFG register to generate an interrupt request see Figure 4 8 1 All commands are comple
33. scillator clock down to within the 150kHz to 200kHz range Since the program and erase timings are also a function of the bus clock the ECLKDIV determination must take this information into account If we define e ECLK as the clock of the EEPROM timing control block e Tbus as the period of the bus clock e NT x as taking the integer part of x e g INT 4 323 4 then ECLKDIV register bits PRDIV8 and EDIV 5 0 are to be set as described in Figure 4 1 For example if the oscillator clock frequency is 950kHz and the bus clock frequency is 10MHz ECLKDIV bits EDIV 5 0 should be set to 4 000100 and bit PRDIVS set to 0 The resulting EECLK frequency is then 190kHz As a result the EEPROM program and erase algorithm timings are increased over the optimum target by 200 190 200 x 100 5 If the oscillator clock frequency is 16MHz and the bus clock frequency is 40MHz ECLKDIV bits EDIV 5 0 should be set to 50 110010 and bit PRDIVS set to 1 The resulting EECLK frequency is M MOTOROLA 25 For More Information On This Product Go to www freescale com Block Guide s12EETX4kv if scale Semiconductor Inc then 182kHz In this case the EEPROM program and erase algorithm timings are increased over the optimum target by 200 182 200 x 100 9 NOTE 4 Program and erase command execution time will increase proportionally with the period of EECLK NOTE Because of the impact of clock synchronization on the accur
34. set once after each reset Write ECLKDIV register Read ESTAT register Address Data Command Buffer Empty Check Access Error and Protection Violation Check Write ESTAT register Clear ACCERR PVIOL 30 Write EEPROM Address 1 and Dummy Data Write EGMD register NOTE command write sequence aborted by writing 00 to Erase Verify Command 05 ESTAT register NOTE command write sequence aborted by writing 00 to ESTAT register 3 Write ESTAT register Clear CBEIF 80 Read ESTAT register Bit Polling for Command Completion Check Erase Verify Status EEPROM Memory EEPROM Memory Erased Not Erased Figure 4 2 Example Erase Verify Command Flow 4 1 3 2 Program Command The program operation will program a previously erased word in the EEPROM memory using an embedded algorithm An example flow to execute the program operation is shown in Figure 4 3 The program command write sequence is as follows 1 Write to an EEPROM block address to start the command write sequence for the program command The data written will be programmed to the address written 30 M MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Ere s12EETX4KVO voo o4 2 Write the program command 20 to the ECMD register 3 Clear the CBEIF flag in the ESTAT register by writing a 1 to CBEIF to launch the program command If a word to
35. ster by writing a 1 to CBEIF to launch the sector erase abort command If the sector erase abort command is launched resulting in the early termination of an active sector erase or sector modify operation the ACCERR flag will set once the operation completes as indicated by the CCIF flag being set The ACCERR flag sets to inform the user that the EEPROM sector may not be fully erased and a new sector erase or sector modify command must be launched before programming any location in that specific sector If the sector erase abort command is launched but the active sector erase or sector modify operation completes normally the ACCERR flag will not set upon completion of the operation as indicated by the CCIF flag being set If the sector erase abort command is launched after the sector modify operation has completed the sector erase step the program step will be allowed to complete The maximum number of cycles required to abort a sector erase or sector modify operation is equal to four EECLK periods see section 4 1 1 plus five bus cycles as measured from the time the CBEIF flag is cleared until the CCIF flag is set NOTE Since the ACCERR bit in the ESTAT register may be set at the completion of the sector erase abort operation a command write sequence is not allowed to be buffered behind a sector erase abort command write sequence The CBEIF flag will not set after launching the sector erase abort command to indicate that a command should not
36. t Go to www freescale com Freescale Semiconductor Iner s12EETX4KVO voo o4 M MOTOROLA 9 For More Information On This Product Go to www freescale com Block Guide st2EErxakva o fiscale Semiconductor Inc 10 M MOTOROLA For More Information On This Product Go to www freescale com Block Guide s12EETX4kv if scale Semiconductor Inc Section 1 Introduction 1 1 Overview This document describes the EETX4K module which includes a 4K byte EEPROM Non Volatile memory The EEPROM memory may be read as either bytes aligned words or misaligned words Read access time is one bus cycle for bytes and aligned words and two bus cycles for misaligned words The EEPROM memory is ideal for data storage for single supply applications allowing for field reprogramming without requiring external voltage sources for program or erase Program and erase functions are controlled by a command driven interface The EEPROM module supports both block erase all memory bytes and sector erase 4 memory bytes An erased bit reads 1 and a programmed bit reads O The high voltage required to program and erase the EEPROM memory is generated internally It is not possible to read from the EEPROM block while it is being erased or programmed NOTE An EEPROM word 2 bytes must be erased before being programmed Cumulative programming of bits within a word is not allowed 1 1 1 Glossary Command Write Sequence A three step M
37. ted 0 Command in progress PVIOL Protection Violation Flag The PVIOL flag indicates an attempt was made to program or erase an address in a protected area of the EEPROM memory during a command write sequence The PVIOL flag is cleared by writing a 1 to PVIOL Writing a O to the PVIOL flag has no effect on PVIOL While PVIOL is set it is not possible to launch a command or start a command write sequence 1 A protection violation has occurred 0 No failure ACCERR Access Error Flag The ACCERR flag indicates an illegal access has occurred to the EEPROM memory caused by either a violation of the command write sequence see section 4 1 2 issuing an illegal EEPROM command see Table 3 4 launching the sector erase abort command terminating a sector erase operation early see section 4 1 3 5 or the execution of a CPU STOP instruction while a command is executing CCIF 0 The ACCERR flag is cleared by writing a 1 to ACCERR Writing a O to the ACCERR flag has no effect on ACCERR While ACCERR is set it is not possible to launch a command or start a command write sequence If ACCERR is set by an erase verify operation any buffered command will not launch 1 Access error has occurred 0 No access error detected BLANK Flag indicating the erase verify operation status When the CCIF flag is set after completion of an erase verify command the BLANK flag indicates the result of the erase verify o
38. tion Procedure for PRDIV8 and EDIV Bits M MOTOROLA 27 For More Information On This Product Go to www freescale com Block Guide S12EETXakvo We ES cale Semiconductor Inc 4 1 2 Command Write Sequence The EEPROM command controller is used to supervise the command write sequence to execute program erase erase verify sector erase abort and sector modify algorithms Before starting a command write sequence the ACCERR and PVIOL flags in the ESTAT register must be clear see section 3 3 6 and the CBEIF flag should be tested to determine the state of the address data and command buffers If the CBEIF flag is set indicating the buffers are empty a new command write sequence can be started If the CBEIF flag is clear indicating the buffers are not available a new command write sequence will overwrite the contents of the address data and command buffers A command write sequence consists of three steps which must be strictly adhered to with writes to the EEPROM module not permitted between the steps However EEPROM register and array reads are allowed during a command write sequence The basic command write sequence is as follows Wirite to one address in the EEPROM memory 2 Write a valid command to the ECMD register 3 Clear the CBEIF flag in the ESTAT register by writing a 1 to CBEIF to launch the command The address written in step 1 will be stored in the EADDR registers and the data will be stored in the EDATA reg
39. write sequence was in a protected area of the EEPROM memory If the PVIOL flag is set in the ESTAT register the user must clear the PVIOL flag before starting another command write sequence see section 3 3 6 M MOTOROLA 39 For More Information On This Product Go to www freescale com Block Guide S12EETXakvo df Gi cale Semiconductor Inc 4 2 Wait Mode If a command is active CCIF 0 when the MCU enters the WAIT mode the active command and any buffered command will be completed The EEPROM module can recover the MCU from WAIT if the CBEIF and CCIF interrupts are enabled see section 4 7 4 3 Stop Mode If a command is active CCIF 0 when the MCU enters the STOP mode the operation will be aborted and if the operation is program sector erase mass erase or sector modify the EEPROM array data being programmed or erased may be corrupted and the CCIF and ACCERR flags will be set If active the high voltage circuitry to the EEPROM memory will immediately be switched off when entering STOP mode Upon exit from STOP the CBEIF flag is set and any buffered command will not be launched The ACCERR flag must be cleared before starting a command write sequence see section 4 1 2 NOTE As active commands are immediately aborted when the MCU enters STOP mode it is strongly recommended that the user does not use the STOP command during program sector erase mass erase or sector modify operations 4 4 Background Debug Mode
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