Cypress CY7C1471BV25 User's Manual
Contents
1. 8 5 gt lt lt BBE lt lt lt lt 825858 5 1 558558 8558585556 DQPc C 1 80 DAP DQc C 2 79 DQg DQc E 3 78 DQg Vppa 4 77 Vppa Vss 5 76 Vss DQc L6 75 DQ BYTEC 0922415 DQc 8 73 DQg DQc 9 72 Vss 10 71 Vss 11 70 I 12 69 DQg DQc 13 68 71 NG ji CY7C1471BV25 67 Vss 15 66 NC NC 16 65 Vpp Vss 17 64 22 DQp 18 63 DQp 19 62 DQ Vppo H 20 61 Vss 21 60 Vss DQp L 22 59 1 BYTED DQp 23 58 DQA 24 57 DQ BYTEA DQp 25 56 Vss 26 55 J Vss VDDQ 27 54 Vppa DQp 28 53 1 DQ DQp 29 52 DQPp 30 51 S 9 5 lt lt lt lt x lt gt z gt lt lt lt lt lt lt lt lt lt gt a 92 Document 001 15013 Rev E Page 4 of 302. Cypress Semiconductor Corporation 2007 2008 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product Nor does it convey or imply any license under patent or other rights Cypress products are not warranted nor intended to be used for medical life support life saving critical control or safety applications unless pursuant to an express written agreement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Any Source Code software and or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign United States copyright laws and international treaty provisions Cypress hereby grants to licensee a personal non exclusive non transferable license to copy use modify create derivative works of and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee
3. CY7C1473BV25 100AXI Ordering Code p A Part and Package Type 133 CY7C1471BV25 133AXC 51 85050 100 Thin Quad Flat Pack 14 x 20 x 1 4 mm Pb Free Commercial CY7C1473BV25 133AXC CY7C1471BV25 133BZC 51 85165 165 ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm CY7C1473BV25 133BZC CY7C1471BV25 133BZXC 51 85165 165 ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm Pb Free CY7C1473BV25 133BZXC CY7C1475BV25 183BGC 51 85167 209 ball Fine Pitch Ball Grid Array 14 x 22 1 76 mm CY7C1475BV25 133BGXC 209 ball Fine Pitch Ball Grid Array 14 x 22 x 1 76 mm Pb Free CY7C1471BV25 133AXI 51 85050 100 pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Pb Free Industrial CY7C1473BV25 133AXI CY7C1471BV25 133BZI 51 85165 165 ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm CY7C1473BV25 133BZI CY7C1471BV25 133BZXI 51 85165 165 ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm Pb Free CY7C1473BV25 133BZXI CY7C1475BV25 133BGI 51 85167 209 ball Fine Pitch Ball Grid Array 14 x 22 x 1 76 mm CY7C1475BV25 133BGXI 209 ball Fine Pitch Ball Grid Array 14 x 22 x 1 76 mm Pb Free 100 CY7C1471BV25 100AXC 51 85050 100 Thin Quad Flat Pack 14 x 20 x 1 4 mm Pb Free Commercial CY7C1473BV25 100AXC CY7C1471BV25 100BZC 51 85165 165 ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm CY7C1473BV25 100BZC CY7C1471BV25 100BZXC 51 85165 165 ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm Pb Free CY7C1473BV25 100BZXC C
4. Vss Vss Vss NC Vss Vss Vss DQf DQf G DQc DQc Vppa Vpp Yop Daf H DQc DQc Vss Vss Vss NC Vss Vss Vss Daf Dart J Vppa Dat K NC NC CLK NC CEN Vss NC NC NC NC L DQh Vppa Vpp Vppo M DQh Dah Vss Vss Vss NC Vss Ves Ves 00 N DQh DQh Vppa Voo NC Voo paa E DQh DQh Vss Vss Vss 22 Vss Vss Vss DQa DQa R DQPd DQPh Vppa Vpp Vpp DGPa DGPe T DQd DQd Vss NC NC MODE NC NC Vss poe U DQd nc 144m A A A NC 288M pae V DQd A A A 1 DQd Dad TMS TDI 0 TDO pae Document 001 15013 Rev E Page 7 of 30 Feedback CY7C1471BV25 CY7C1473BV25 CY7C1475BV25 E gt PERFORM Table 1 Pin Definitions Name IO Description Ai Input Address Inputs Used to Select One of the Address Locations Sampled at the rising edge Synchronous of the CLK are fed to the two bit burst counter BWA BWg Input Byte Write Inputs Active LOW Qualified with WE to conduct writes to the SRAM Sampled BWc BWp Synchronous on the r
5. M M W 5 W CHZ DQ ADANA QU2 W DA QUS M tpoH COMMAND WRITE READ STALL READ WRITE STALL NOP READ DESELECT CONTINUE D A1 Q A2 Q A3 D A4 Q A5 DESELECT DON T CARE UNDEFINED Note 22 The IGNORE CLOCK EDGE or STALL cycle Clock 3 illustrates CEN being used to create a pause A write is not performed during this cycle Page 24 of 30 Document 001 15013 Rev E Feedback CY7C1471BV25 CY7C1473BV25 CY7C1475BV25 cypress Switching Waveforms continued 23 24 Figure 10 shows ZZ Mode timing waveform Figure 10 ZZ Mode Timing 77 iz rzzi DESELECT or READ Only 1 s SUPPLY DDZZ NEN ALL INPUTS 72 DON T CARE 23 Device must be deselected when entering ZZ mode See Truth Table on page 11 for all possible signal conditions to deselect the device Notes 24 DGs are in high Z when exiting ZZ sleep mode Document 001 15013 Rev E Page 25 of 30 Feedback Ordering Information CY7C1471BV25 CY7C1473BV25 CY7C1475BV25 Not all of the speed package and temperature ranges are available Please contact your local sales representative or visit www cypress com for actual products offered
6. R A 1 00 5 00 10 00 o o q ra 1500 010 3 gt 2 X 5 2 5 0 15 4x q I SEATING PLANE 51 85165 Document 001 15013 Rev E Page 28 of 30 Feedback CY7C1471BV25 CY7C1473BV25 CY7C1475BV25 2 F CYPRESS PERFORM Figure 13 209 Ball FBGA 14 x 22 x 1 76 mm 51 85167 Package Diagrams continued TOP VIEW E TO T R 2 pH B4 14 005 o mE 1 gt 0 15 4 JT Y SEATING PL FI c T 28 51 85167 Page 29 of 30 Feedback Document 001 15013 Rev E LE CY7C1471BV25 CYPRESS CY7C1473BV25 CY7C1475BV25 PERFORM Document History Page Document Title CY7C1471BV25 CY7C1473BV25 CY7C1475BV25 72 Mbit 2M x 36 4M x 18 1M x 72 Flow Through SRAM with NoBL Architecture Document Number 001 15013 Issue Orig of Date Change Description of Change ud 1024500 See ECN VKN KKVTMP New Data Sheet A 1274731 See VKN AESA Corrected typo in the STALL and DESELECT Cycles waveform B 1562503 See ECN VKN AESA Removed 1 8V IO offering from the data sheet C 1897447 See VKN AESA Added footnote 14 related to IDD D 2082487 See ECN VKN Converted from preliminary to final E 2159486 See VKN PYRS Minor Change Moved to the external web
7. Feedback a a CY7C1471BV25 Z CYPRESS CY7C1473BV25 CY7C1475BV25 PERFORM Pin Configurations continued Figure 2 100 Pin TQFP Pinout 8 m lt o 2 gt lt lt 82 2 S 9898595939 gt 590 3 1 80 2 79 3 78 NC 4 77 Vppo Vss 5 76 Vss 6 75 NC 7 74 DQg 8 73 DQg 9 72 Vss L 10 71 Vss 11 70 12 69 13 68 I 14 67 Vss Vpp 15 66 NC 16 CY7C1473BV25 65 Vpp Vss 17 64 22 18 63 I DQg 19 62 Vppa 20 61 4 Vss 21 60 Vss DQg 22 59 1 DQg 23 58 L DQPg CH 24 57 NC NC 25 56 NC Vss 26 55 J Vss 27 54 Vppo NC L 28 53 NC NC 29 52 NC NC 30 51 NC 88585885 s 9 59856898
8. TDO Identification Register 2 Boundary Scan Register CONTROLLER TCK TMS Performing Reset A RESET is performed by forcing HIGH Vpp for five rising edges of TCK This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating During power up the TAP is reset internally to ensure that TDO comes up in a High Z state Page 13 of 30 Feedback CYPRESS PERFORM TAP Registers Registers are connected between the TDI and TDO balls and enable the scanning of data into and out of the SRAM test circuitry Only one register is selectable at a time through the instruction register Data is serially loaded into the TDI ball on the rising edge of TCK Data is output on the TDO ball on the falling edge of TCK Instruction Register Three bit instructions can be serially loaded into the instruction register This register is loaded when it is placed between the TDI and TDO balls as shown in the TAP Controller Block Diagram on page 13 During power up the instruction register is loaded with the IDCODE instruction It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section When the TAP controller is in the Capture IR state the two least significant bits are loaded
9. 20 21 Figure 8 Read Write Timing 1 2 tcc 3 4 5 6 7 8 9 10 a LEX FEN tcens CENH q ak YA EA UN E E MT D EA m tces lt gt ADVAD A tA Mi CA A WM VA ADDRESS WUA AA NS NT tas lt 17 00 COMMAND WRITE WRITE BURST READ READ BURST WRITE READ WRITE DESELECT D A1 D A2 WRITE Q A3 Q A4 READ D A5 Q A6 D A7 D A2 1 Q A4 1 UNDEFINED Notes 19 For this waveform ZZ is tied LOW 20 When CE is LOW CE is LOW is HIGH and CE is LOW When CE is HIGH CE is HIGH CE is LOW or CE is HIGH 21 Order of the Burst sequence is determined by the status of the MODE 0 Linear 1 Interleaved Burst operations are optional Document 001 15013 Rev E Page 23 of 30 Feedback CY7C1471BV25 CY7C1473BV25 CY7C1475BV25 855 a lt CYPRESS Switching Waveforms continued Figure 9 shows NOP STALL and DESELECT Cycles waveform Figure 9 NOP STALL and DESELECT Cycles 19 20 22 1 2 3 4 5 6 7 8 9 10 V i A M GA m RR w 777 m wo Mii HUI ADDRESS
10. information described in Identification Register Definitions on page 17 TAP Instruction Set Overview Eight different instructions are possible with the three bit instruction register All combinations are listed in Identification Codes on page 17 Three of these instructions are listed as RESERVED and are not for use The other five instructions are described in this section in detail Document 001 15013 Rev E CY7C1471BV25 CY7C1473BV25 CY7C1475BV25 The TAP controller used in this SRAM is not fully compliant to the 1149 1 convention because some of the mandatory 1149 1 instructions are not fully implemented You cannot use the TAP controller to load address data or control signals into the SRAM and you cannot preload the IO buffers The SRAM does not implement the 1149 1 commands EXTEST or INTEST or the PRELOAD portion of SAMPLE PRELOAD rather it performs a capture of the IO ring when these instruc tions are executed Instructions are loaded into the TAP controller during the Shift IR state when the instruction register is placed between TDI and TDO During this state instructions are shifted through the instruction register through the TDI and TDO balls To execute the instruction after it is shifted in the TAP controller must be moved into the Update IR state EXTEST EXTEST is a mandatory 1149 1 instruction which is executed whenever the instruction register is loaded with all 0s EXTEST is not implement
11. NC ADV LD 2 BWa CLK WE OE A A NC NC Vss Vss Vss Vss Vss VDDQ NC DQg Vppo Vpp Vss Vss Vss VDD VDDQ NC DQg Vppa Vpp Vss Vss Vss Vpp DQa F NC DQg Vpp Vss Vss Vss Vpp G NC DQg Vpp Vss Vss Vss Vpp VDDQ NC DQa H NC NC NC Vpb Vee Vss Vss Vpb NC NG ZZ J Vpp Vss Vss Vss Vpp K DQg NC VDDQ Vss Vss Vss Vpp L Vpp Vss Vss Vss Vpp DQg NC Vpp Vss Vss Vss Vpp Vppo DQA NC N DQPg NC VDDQ Vss NC NC NC Vss Vppa NC NC P NC 144M A A A TDI Al TDO A A A 288 R MODE A A A TMS A0 TCK A A A A Document 001 15013 Rev Page 6 of 30 Feedback CY7C1471BV25 CY7C1473BV25 CY7C1475BV25 CYPRESS PERFORM Pin Configurations continued 209 Ball FBGA 14 x 22 x 1 76 mm Pinout CY7C1475BV25 1M x 72 1 2 3 4 5 6 7 8 9 10 11 ADV LD A CE A DQb DQb B BWS BWS NC WE A BWS BWS DQb C DQg BWS BWS 576 CE NC BWS BWS DQb DQb D Vss NC NC G OE NC NC Vss DQb E DQPg DQPc Vpp VDD DQPf
12. TAP operates using JEDEC standard 2 5V IO logic levels The CY7C1471BV25 CY7C1473BV25 and CY7C1475BV25 contain a TAP controller instruction register boundary scan register bypass register and ID register Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature To disable the TAP controller tie LOW Vss to prevent clocking of the device TDI and TMS are internally pulled up and may be unconnected They may alternately be connected to Vpp through a pull up resistor TDO must be left unconnected During power up the device comes up in a reset state which does not interfere with the operation of the device Figure 3 TAP Controller State Diagram TEST LOGIC RESET 0 Y RUN TEST IDLE 4 4 SELECT SELECT 1 DR SCAN IR SCAN 0 0 T 1 1 CAPTURE DR CAPTURE IR 0 0 Y Y SHIF DR 707 707 L gt 1 1 Y 1 1 L EXITI DR Le EXITI IR 0 0 gt gt E S gt a ut E UPDATE DR 4 UPDATE R 1 0 1 0 Y The 0 1 next to each state represents the value of TMS at the rising edge of TCK Document 001 15013 Rev E CY7C1471BV25 CY7C1473BV25 CY7C1475BV25 Test Access Port TAP Test Clock
13. TCK The test clock is used only with the TAP controller All inputs are captured on the rising edge of All outputs are driven from the falling edge of TCK Test Mode Select TMS The TMS input gives commands to the TAP controller and is sampled on the rising edge of TCK You can leave this ball unconnected if the TAP is not used The ball is pulled up inter nally resulting in a logic HIGH level Test Data In TDI The TDI ball serially inputs information into the registers and is connected to the input of any of the registers The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register For information about loading the instruction register see the TAP Controller State Diagram TDI is internally pulled up and can be unconnected if the TAP is unused in an application TDI is connected to the most significant bit MSB of any register See TAP Controller Block Diagram Test Data Out TDO The TDO output ball serially clocks data out from the registers The output is active depending upon the current state of the TAP state machine The output changes on the falling edge of TCK TDO is connected to the least significant bit LSB of any register See Tap Controller State Diagram Figure 4 TAP Controller Block Diagram Bypass Register gt 2 1 0 gt Selection Circuitry Selection Instruction Register Circuitry TDI
14. TDO This operation does not affect SRAM operations SAMPLE Z 010 Captures IO ring contents Places the boundary scan register between TDI and TDO Forces all SRAM output drivers to a High Z state RESERVED 011 Do Not Use This instruction is reserved for future use SAMPLE PRELOAD 100 Captures IO ring contents Places the boundary scan register between TDI and TDO Does not affect SRAM operation This instruction does not implement 1149 1 preload function and is therefore not 1149 1 compliant RESERVED 101 Do Not Use This instruction is reserved for future use RESERVED 110 Do Not Use This instruction is reserved for future use BYPASS 111 Places the bypass register between TDI and TDO This operation does not affect SRAM operation Document 001 15013 Rev E Page 17 of 30 Feedback CY7C1473BV25 CY7C1475BV25 CY7C1471BV25 CYPRESS PERFORM Table 11 Boundary Scan Exit Order 2M x 36 Bit 165 Ball ID Bit 4 165 Ball ID Bit 4 165 Ball ID Bit 4 165 Ball ID C1 21 41 J11 61 B7 D1 22 P2 42 K10 62 B6 3 E1 23 R4 43 J10 63 A6 4 D2 24 P6 44 H11 64 B5 5 E2 25 R6 45 G11 65 A5 6 F1 26 R8 46 F11 66 A4 7 G1 27 P3 47 E11 67 B4 8 F2 2
15. W2 64 N11 92 U8 9 E1 37 T6 65 N10 93 A6 10 E2 38 V3 66 M11 94 D6 11 F1 39 V4 67 M10 95 K6 12 F2 40 U4 68 L11 96 B6 13 G1 41 W5 69 L10 97 K3 14 G2 42 V6 70 P6 98 A8 15 H1 43 W6 71 J11 99 B4 16 H2 44 V5 72 J10 100 B3 17 J1 45 05 73 11 101 18 42 46 U6 74 10 102 4 19 L1 47 W7 75 G11 103 C8 20 L2 48 V7 76 G10 104 C9 21 M1 49 07 77 F11 105 B9 22 M2 50 V8 78 F10 106 B8 23 N1 51 V9 79 E10 107 A4 24 N2 52 W11 80 E11 108 C6 25 P1 53 W10 81 D11 109 B7 26 P2 54 V11 82 D10 110 27 R2 55 V10 83 C11 28 R1 56 U11 84 C10 Page 19 of 30 Feedback Maximum Ratings DC Input Voltage CY7C1471BV25 CY7C1473BV25 CY7C1475BV25 maximum 0098 may impair tie useful life of the 2 ines are not teste Uloullal je VONAGS nnnm nennen Storage 65 to 150 Latch Up 2200 mA Ambient Temperature with Power Applied 55 to 125 Operating Range Supply Voltage on Vpp Relative to GND 0 5V to 3 6V Ambient Supply Voltage on Relative to GND 0 5V to Vpp Range Temperature DC Voltage Applied to Outputs Commercial 0 C to 70 2 5V 5 5 2 5V 5 to in Tri State 111 0 5V to Vp
16. as the Pause DR command BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift DR state the bypass register is placed between the TDI and TDO balls The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board Heserved These instructions are not implemented but are reserved for future use Do not use these instructions Figure 5 TAP Timing 1 2 4 5 6 Test Clock f TCK TOK tTH SL lt 55 TMSH TMS trois SS 0 0 TD trpox Test Data Out XC DON T CARE MM UNDEFINED Document 001 15013 Rev E Page 15 of 30 Feedback j wass 23 CYPRESS PERFORM eA TAP AC Switching Characteristics CY7C1471BV25 CY7C1473BV25 CY7C1475BV25 Over the Operating Range 101 Parameter Description Min Max Unit Clock trcvc TCK Clock Cycle Time 50 ns Clock Frequency 20 MHz tty TCK Clock HIGH Time 20 ns tn TCK Clock LOW Time 20 ns Output Times Clock LOW to Valid 10 ns trp
17. dd WRITE REGISTRY WRITE gt ARRAY gt E U T BWB AND DATA COHERENCY DRIVERS T F CONTROL LOGIC DQPB M E E P R R __ 5 5 A f INPUT g _ REGISTER READ LOGIC 1 2 1 77 SLEEP CONTROL Document 001 15013 Rev E Page 2 of 30 Feedback PERFORM Logic Block Diagram CY7C1475BV25 1M x 72 CY7C1471BV25 CY7C1473BV25 CY7C1475BV25 AO A1 A ADDRESS ME p REGISTER 0 MODE N 1 LZ WRITE ADDRESS REGISTER 1 Lo 0 o 0 e gt T 0 5 E D e u BWa A 3 MEMORY E R FN B Z BW b WRITE ARRAY E E S L 0 00 BW WRITE REGISTRY DRIVERS A i DOPA BWa AND DATA COHERENCY H P S 2 DQ Pb BW CONTROL LOGIC S I R R DQ Pc BWr R N DQ Pd BW g G DQ Pe BWh E DQ Pf DQ Pg DQ Ph WE 4 INPUT INPUT REGISTER 1 4 REGISTER 0 4 A READ LOGIC CE1 22 Sleep Control Document 001 15013 Rev E Page 3 of 30 Feedback gt PERFORM Pin Configurations Figure 1 100 Pin TQFP Pinout
18. for measuring Thermal Resistance thermal impedance 2 28 2 1 1 7 C W Junction to Case according to EIA JESD51 Figure 7 AC Test Loads and Waveforms 2 5V IO Test Load OUTPUT 2 5 OUTPUT 500 5pF I 15380 1 25V INCLUDING a JIG AND SCOPE Document 001 15013 Rev E Page 21 of 30 Feedback CY7C1471BV25 CY7C1473BV25 CY7C1475BV25 1 Switching Characteristics Over the Operating Range Timing reference level is 1 25V when Vppq 2 5V Test conditions shown in a of AC Test Loads and Waveforms on page 21 unless otherwise noted 133 MHz 100 MHz Parameter Description Unit Min Max Min Max iPowER 1 ms Clock 7 5 10 ns Clock HIGH 2 5 3 0 ns Clock LOW 2 5 3 0 ns Output Times Data Output Valid After CLK Rise 6 5 8 5 ns Data Output Hold After CLK Rise 2 5 2 5 ns 2 Clock to Low z 116 17 18 3 0 3 0 ns tcHz Clock to High Z 116 17 18 3 8 4 5 ns toev OE LOW to Output Valid 3 0 3 8 ns toELZ OE LOW to Output Low Z 16 17 18 0 0 ns 2 OE HIGH to Output High Z 16 17 18 3 0 4 0 ns Setup Times tas Address Setup Before CLK Rise 1 5 1 5 ns tats ADV LD Setup Before CLK Rise 1 5 1 5 ns twes WE BW Setup Before CLK Rise 1 5 1 5 ns tcENS CEN Setup B
19. product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement Any reproduction modification translation compilation or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND EXPRESS OR IMPLIED WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Cypress reserves the right to make changes without further notice to the materials described herein Cypress does not assume any liability arising out of the application or use of any product or circuit described herein Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress product in a life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Use may be limited by and subject to the applicable Cypress software license agreement Document 001 15013 Rev E Revised February 29 2008 Page 30 of 30 NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation ZBT is a trademark of Integrated Device Technology Inc All products and company names mentioned in this document ma
20. x lt Table 6 Truth Table for Read Write The read write truth table for CY7C1473BV25 follows 2 8 Function Write No Bytes Written Write Byte a DQ and Write Byte b DQ DQPy Write Both Bytes W r r x Table 7 Truth Table for Read Write The read write truth table for CY7C1475BV25 follows 2 8 Function Read Write No Bytes Written Write Byte X DQ and Write All Bytes sl All BW L Note 8 This table is only a partial listing of the byte write combinations Any combination of BW is valid Appropriate write is based on which byte write is active Document 001 15013 Rev E Page 12 of 30 Feedback CYPRESS PERFORM IEEE 1149 1 Serial Boundary Scan JTAG The CY7C1471BV25 CY7C1473BV25 and CY7C1475BV25 incorporate a serial boundary scan Test Access Port TAP This port operates in accordance with IEEE Standard 1149 1 1990 but does not have the set of functions required for full 1149 1 compliance These functions from the IEEE specification are excluded because their inclusion places an added delay in the critical speed path of the SRAM Note that the TAP controller functions in a manner that does not conflict with the operation of other devices using 1149 1 fully compliant TAPs The
21. 8 P4 48 D10 68 B3 9 G2 29 P8 49 D11 69 A3 10 J1 30 P9 50 C11 70 A2 11 K1 31 P10 51 G10 71 B2 12 L1 32 R9 52 F10 13 J2 33 R10 53 E10 14 M1 34 R11 54 A9 15 1 35 N11 55 B9 16 K2 36 M11 56 A10 17 L2 37 L11 57 B10 18 M2 38 M10 58 A8 19 R1 39 L10 59 B8 20 R2 40 K11 60 7 Table 12 Boundary Scan Exit Order 4M x 18 Bit 165 Ball ID Bit 4 165 Ball ID Bit 4 165 Ball ID Bit 4 165 Ball ID 1 D2 14 R4 27 L10 40 B10 E2 15 P6 28 K10 41 A8 3 F2 16 R6 29 J10 42 B8 4 G2 17 R8 30 H11 43 7 5 J1 18 31 G11 44 B7 6 K1 19 P4 32 F11 45 B6 7 L1 20 P8 33 E11 46 A6 8 M1 21 P9 34 D11 47 B5 9 N1 22 P10 35 C11 48 A4 10 R1 23 R9 36 A11 49 B3 11 R2 24 R10 37 A9 50 12 25 11 38 B9 51 A2 13 P2 26 M10 39 A10 52 B2 Page 18 of 30 Feedback Document 001 15013 Rev E j wass 23 CYPRESS PERFORM Table 13 Boundary Scan Exit Order 1M x 72 CY7C1471BV25 CY7C1473BV25 CY7C1475BV25 Document 001 15013 Rev E Bit 4 209 Ball ID Bit 4 209 Ball ID Bit 4 209 Ball ID Bit 209 Ball ID 1 A1 29 T1 57 U10 85 B11 2 A2 30 T2 58 T11 86 B10 3 B1 31 U1 59 T10 87 11 4 2 32 U2 60 11 88 10 5 C1 33 V1 61 R10 89 A7 6 C2 34 V2 62 P11 90 A5 7 D1 35 W1 63 P10 91 A9 8 D2 36
22. 9 lt lt lt lt lt lt 2 8 lt lt lt lt lt lt lt lt lt E 22 Document 001 15013 Rev E Page 5 of 30 Feedback LL E I j 4 55 PERFORM Pin Configurations continued 165 Ball FBGA 15 x 17 x 1 4 mm Pinout CY7C1471BV25 CY7C1473BV25 CY7C1475BV25 CY7C1471BV25 2M x 36 1 2 3 4 5 6 7 8 9 10 11 NC 576M CE BWc CEN ADV LD A A NC B NC 1G A CE2 BWp BW CLK WE OE A A NC DQPc NC VDDQ Vss Vss Vss Vss Vss VDDQ NC D DQc DQc VppQ Vpp Vss Vss Vss Vpp DQg DQc DQc Vppo Vss Vss Vss Vpp DQg F DQc Vppo Vss Vss Vss VDD DQg G DQc DQc Vppo Vpp Vss Vss Vss VDD DQg H NC NC NC MSS Vea Vss Vss Vop NC NC ZZ J DQp DQp Vpp Vss Vss Vss Vpp VDDQ DQa DQa K DQp DQp Vpp Vss Vss Vss Vpp VDDQ DQa DQa L DQp DQp VDDQ VDD Vss Vss Vss VDD VDDQ DQa DQa M DQp DQp Vss Vss Vss DQa DaPp Vowa Vss NC NC NC Vss NC DOP P NC 144M A A A TDI A1 TDO A A A NC 288M R MODE A A A TMS CY7C1473BV25 AM x 18 1 2 3 4 5 6 7 8 9 10 11 NC 576M BWg
23. ANE 1 JEDEC STD REF 5 026 a a 2 BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION END FLASH Y R0 08 MIN MOLD PROTRUSION END FLASH SHALL 0 0098 0 25 mm PER SIDE 0 7 020 BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 3 DIMENSIONS IN MILLIMETERS 0 60 0 15 m 0 20 MIN 1 00 REF ume DETAIL 51 85050 B Page 27 of 30 Document 001 15013 Rev E Feedback E CY7C1471BV25 CYPRESS CY7C1473BV25 CY7C1475BV25 PERFORM ih Package Diagrams continued Figure 12 165 Ball FBGA 15 x 17 x 1 4 mm 51 85165 BOTTOM VIEW PIN 1 CORNER TOP VIEW k 005 PIN 1 CORNER 2025 4 B 0 45 0 05 165X 1 2 3 4 5 6 y 8 9 10 11 11 10 9 8 7 6 5 4 x 1 i A 0000000000 A TA 0000000000 c m 8 D D E F F H X Q C H 8 I L B L 8 R N N P P R
24. DV LD must be driven LOW after the device is deselected to load a new address for the next operation Single Read Accesses A read access is initiated when the following conditions are satisfied at clock rise m CEN is asserted LOW CE4 CE and CE are ALL asserted active m WE is deasserted HIGH m ADV LD is asserted LOW The address presented to the address inputs is latched into the Address Register and presented to the memory array and control logic The control logic determines that a read access is in progress and allows the requested data to propagate to the output buffers The data is available within 6 5 ns 133 MHz device provided OE is active LOW After the first clock of the read access the output buffers are controlled by OE and the internal control logic OE must be driven LOW to drive out the requested data On the subsequent clock another operation read write deselect can be initiated When the SRAM is Document 001 15013 Rev E deselected at clock rise by one of the chip enable signals the output is tri stated immediately Burst Read Accesses The CY7C1471BV25 CY7C1473BV25 and CY7C1475BV25 has an on chip burst counter that enables the user the ability to supply a single address and conduct up to four reads without reasserting the address inputs ADV LD must be driven LOW to load a new address into the SRAM as described in the Single Read Access section The sequence of the burst counter is determin
25. PERFORM CY7C1471BV25 CY7C1473BV25 CY7C1475BV25 72 Mbit 2M x 36 4M x 18 1M x 72 Flow Through SRAM with NoBL Architecture Features No Bus Latency NoBL architecture eliminates dead cycles between write and read cycles Supports up to 133 MHz bus operations with zero wait states Data transfers on every clock m Pin compatible and functionally equivalent to ZBT devices m Internally self timed output buffer control to eliminate the need to use OE m Registered inputs for flow through operation m Byte Write capability m 2 5V IO supply Vppo m Fast clock to output times 6 5 ns for 133 MHz device m Clock Enable CEN pin to enable clock and suspend operation m Synchronous self timed writes m Asynchronous Output Enable OE m CY7C1471BV25 CY7C1473BV25 available in JEDEC standard Pb free 100 pin Pb free and non Pb free 165 ball FBGA package CY7C1475BV25 available in Pb free and non Pb free 209 ball FBGA package m Three Chip Enables CE4 CEs for simple depth expansion m Automatic power down feature available using ZZ mode or CE deselect m IEEE 1149 1 JTAG Boundary Scan compatible m Burst Capability linear or interleaved burst order m Low standby power Selection Guide Functional Description The CY7C1471BV25 CY7C1473BV25 and CY7C1475BV25 are 2 5V 2M x 36 4M x 18 1M x 72 synchronous flow through burst SRAMs designed specifically to support unlimited true ba
26. Synchronous write sequences DQPy is controlled by BW correspondingly MODE Input Strap Pin Mode Input Selects the Burst Order of the Device When tied to Gnd selects linear burst sequence When tied to Vpp or left floating selects inter leaved burst sequence Vpp Power Supply Power Supply Inputs to the Core of the Device VDDQ IO Power Supply Supply for the IO Circuitry Vss Ground Ground for the Device TDO JTAG serial output Serial Data Out to the JTAG Circuit Delivers data on the negative edge of TCK If the JTAG Synchronous feature is not used this pin must be left unconnected This pin is not available on TQFP packages Page 8 of 30 Feedback Document 001 15013 Rev E P CYPRESS PERFORM Table 1 Pin Definitions continued CY7C1471BV25 CY7C1473BV25 CY7C1475BV25 Name IO Description TDI JTAG serial input Serial Data In to the JTAG Circuit Sampled on the rising edge of TCK If the JTAG feature is Synchronous not used leave this pin floating or connected to Vpp through a pull up resistor This pin is not available on TQFP packages TMS JTAG serial input Serial Data In to the JTAG Circuit Sampled on the rising edge of If the JTAG feature is Synchronous not used this pin can be disconnected or connected to Vpp This pin is not available on TQFP packages JTAG Clock Clock Input to the JTAG Circuitry If the JTAG feature is not used connect this pin to Va
27. Truth Table for Read Write on page 12 The input WE with the selected BW input selectively writes to only the desired bytes Bytes not selected during a Byte Write operation remain unaltered A synchronous self timed write mechanism is provided to simplify the write operations Byte Write capability is Page 9 of 30 Feedback included to greatly simplify read modify write sequences which can be reduced to simple byte write operations CY7C1471BV25 CY7C1473BV25 CY7C1475BV25 Table 2 Interleaved Burst Address Table MODE Floating or Vpp Because the CY7C1471BV25 CY7C1473BV25 First Second Third Fourth CY7C1475BV25 are common IO devices data must not be Address Address Address Address driven into the device while the outputs are active The OE can A1 A0 A1 A0 A1 A0 A1 A0 be deasserted HIGH before presenting data to the DQs and 00 01 10 11 DQPy inputs This tri states the output drivers As a safety precaution DQs and DQPy are automatically tri stated during 01 00 11 10 the data portion of a write cycle regardless of the state of OE 10 11 00 01 Burst Write Accesses 11 10 01 00 The CY7C1471BV25 CY7C1473BV25 and CY7C1475BV25 have an on chip burst counter that makes it possible to supply a single address and conduct up to four Write operations without Table 3 Linear Burst Address Table reasserting the address inpu
28. Y7C1475BV25 100BGC 51 85167 209 ball Fine Pitch Ball Grid Array 14 x 22 x 1 76 mm 7 1475 25 100 209 ball Fine Pitch Ball Grid Array 14 x 22 x 1 76 mm Pb Free CY7C1471BV25 100AXI 51 85050 100 pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Pb Free Industrial CY7C1471BV25 100BZI CY7C1473BV25 100BZI 51 85165 165 ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm CY7C1471BV25 100BZXI CY7C1473BV25 100BZXI 51 85165 165 ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm Pb Free CY7C1475BV25 100BGI CY7C1475BV25 100BGXI 51 85167 209 ball Fine Pitch Ball Grid Array 14 x 22 x 1 76 mm 209 ball Fine Pitch Ball Grid Array 14 x 22 x 1 76 mm Pb Free Document 001 15013 Rev E Page 26 of 30 Feedback CY7C1471BV25 377 CYPRESS CY7C1473BV25 CY7C1475BV25 PERFORM Package Diagrams Figure 11 100 Pin Thin Plastic Quad Flatpack 14 x 20 x 1 4 mm 51 85050 16 00 0 20 14 00 0 10 1 40 0 05 1 80 0 30 0 08 RS I I 8 S8 0 65 12 1 SEE DETAIL A TYP 8X a 30 1 8 Y N 31 50 NER L J 0 20 MAX 1 60 R 0 08 MIN 5 0 20 25 0 2 lt gt N STAND OFF C y 0 05 0 25 Ew H 0 15 MAX GAUGE PL
29. age 10 of 30 Feedback E CY7C1471BV25 CYPRESS CY7C1473BV25 CY7C1475BV25 PERFORM Table 4 Truth Table The truth table for CY7C1471BV25 CY7C1473BV25 and CY7C1475BV25 follows U 2 3 4 5 6 7 Operation Address CE ZZ ADVLD WE BWx OE Deselect Cycle None H X X L L X X X L H Tr State Deselect Cycle None X X H L L X X X L H Tr State Deselect Cycle None X L X L L X X X L L H Tr State Continue Deselect Cycle None X X X L H X X X L L H Tr State Read Cycle External L H L L L H X L L gt H Data Out Q Begin Burst Read Cycle Next X X X L H X X L L gt H Data Out Q Continue Burst NOP Dummy Read External L H L L L H X H L L gt H Tri State Begin Burst Dummy Read Next X X X L H X X H L L gt H Tri State Continue Burst Write Cycle External L H L L L L L X L L gt H Data In D Begin Burst Write Cycle Next X X X L H X L X L L gt H Data In D Continue Burst NOP Write Abort None L H L L L L H X l L gt H Tri State Begin Burst Write Abort Next X X X L H X H X E L gt H Tri State Continue Burst Ignore Clock Edge Stall Current X X X L X X X X H L H Sleep Mode None X X X H X X X X X X Tri State Notes 1 X Don t Care Logic HIGH L Logic LOW L signifies at least one Byte Write Select is active BW Vali
30. ck to back read or write operations without the insertion of wait states The CY7C1471BV25 CY7C1473BV25 and CY7C1475BV25 are equipped with the advanced No Bus Latency NoBL logic required to enable consecutive read or write operations with data transferred on every clock cycle This feature dramatically improves the throughput of data through the SRAM especially in systems that require frequent write read transitions All synchronous inputs pass through input registers controlled by the rising edge of the clock The clock input is qualified by the Clock Enable CEN signal which when deasserted suspends operation and extends the previous clock cycle Maximum access delay from the clock rise is 6 5 ns 133 MHz device Write operations are controlled by two or four Byte Write Select BWy and a Write Enable WE input All writes are conducted with on chip synchronous self timed write circuitry Three synchronous Chip Enables CE3 and an asynchronous Output Enable OE provide easy bank selection and output tri state control To avoid bus contention the output drivers are synchronously tri stated during the data portion of a write sequence For best practice recommendations refer to the Cypress appli cation note AN1064 SRAM System Guidelines Description 133 MHz 100 MHz Unit Maximum Access Time 6 5 8 5 ns Maximum Operating Current 305 275 mA Maximum CMOS Standby Current 120 120 mA Cyp
31. d signifies that the desired Byte Write Selects are asserted see Truth Table for Read Write on page 12 for details Write is defined by BWy and WE See Truth Table for Read Write on page 12 When a write cycle is detected all IOs tri stated even during byte writes The DQs DQPx pins are controlled by the current cycle and the OE signal OE is asynchronous and is not sampled with the clock CEN H inserts wait states e Device powers up deselected with the 1 in a tri state condition regardless of OE m OEis asynchronous and is not sampled with the clock rise It is masked internally during write cycles During a read cycle DQs and DQP tri state when OE is inactive or when the device is deselected and DQs and DQPy data when OE is active N m Document 001 15013 Rev Page 11 of 30 Feedback ge rZ CYPRESS PERFORM Table 5 Truth Table for Read Write The read write truth table for CY7C1471BV25 follows 2 8 CY7C1471BV25 CY7C1473BV25 CY7C1475BV25 Function E Read gt w Write No bytes written Write Byte A DQ Write Byte B DQg and Write Byte C DQc and Write Byte D DQp and DQPp Write All Bytes z
32. ed by the MODE input signal A LOW input on MODE selects a linear burst mode a HIGH selects an interleaved burst sequence Both burst counters use and A1 in the burst sequence and wraps around when incremented sufficiently A HIGH input on ADV LD increments the internal burst counter regardless of the state of chip enable inputs or WE WE is latched at the beginning of a burst cycle Therefore the type of access read or write is maintained throughout the burst sequence Single Write Accesses Write accesses are initiated when these conditions are satisfied at clock rise m CEN is asserted LOW m CE and CE ALL asserted active m WE is asserted LOW The address presented to the address bus is loaded into the Address Register The write signals are latched into the Control Logic block The data lines are automatically tri stated regardless of the state of the OE input signal This allows the external logic to present the data DQs and DQPy On the next clock rise the data presented to DQs and DQPx or a subset for Byte Write operations see Truth Table for Read Write on page 12 for details inputs is latched into the device and the write is complete Additional accesses read write deselect can be initiated on this cycle The data written during the write operation is controlled by BW signals CY7C1471BV25 CY7C1473BV25 CY7C1475BV25 provide Byte Write capability that is described in the
33. ed in this SRAM TAP controller making this device not compliant with 1149 1 The TAP controller does recognize an all 0 instruction When an EXTEST instruction is loaded into the instruction register the SRAM responds as if a SAMPLE PRELOAD instruction is loaded There is one difference between the two instructions Unlike the SAMPLE PRELOAD instruction EXTEST places the SRAM outputs in a High Z state IDCODE The IDCODE instruction causes a vendor specific 32 bit code to load into the instruction register It also places the instruction register between the TDI and TDO balls and enables the IDCODE for shifting out of the device when the TAP controller enters the Shift DR state The IDCODE instruction is loaded into the instruction register during power up or whenever the TAP controller is in a test logic reset state SAMPLE Z The SAMPLE Z instruction connects the boundary scan register between the TDI and TDO pins when the TAP controller is in a Shift DR state It also places all SRAM outputs into a High Z state SAMPLE PRELOAD SAMPLE PRELOAD is a 1149 1 mandatory instruction The PRELOAD portion of this instruction is not implemented so the device TAP controller is not fully 1149 1 compliant When the SAMPLE PRELOAD instruction is loaded into the instruction register and the TAP controller is in the Capture DR state a snapshot of data on the inputs and bidirectional balls is captured in the boundary scan register Be awa
34. efore CLK Rise 1 5 1 5 ns tps Data Input Setup Before CLK Rise 1 5 1 5 ns tcES Chip Enable Setup Before CLK Rise 1 5 1 5 ns Hold Times Address Hold After Rise 0 5 0 5 ns ADV LD Hold After Rise 0 5 0 5 ns twEH WE BWy Hold After CLK Rise 0 5 0 5 ns CEN Hold After CLK Rise 0 5 0 5 ns Data Input Hold After Rise 0 5 0 5 ns Chip Enable Hold After CLK Rise 0 5 0 5 ns 9 from steady state voltage 17 At any supplied voltage and temperature togpz is less than t bus These specifications do not imply a bus contention con High Z before Low Z under the same system conditions 18 This parameter is sampled and not 100 tested Document 001 15013 Rev E LZ and tcr is less than to eliminate bus contention between SRAMs when sharing the same data 15 This part has a voltage regulator internally tpowgg is the time that the power is supplied above Vpp minimum initially before a read or write operation can be initiated tion but reflect parameters guaranteed over worst case user conditions Device is designed to achieve 16 2 and togyz are specified with AC test conditions shown in part b of AC Test Loads and Waveforms on page 21 Transition is measured 200 mV Page 22 of 30 Feedback E 7 1471 25 CYPRESS CY7C1473BV25 CY7C1475BV25 Switching Waveforms Figure 8 shows read write timing waveform 19
35. ising edge of CLK BWe BWe BWy WE Input Write Enable Input Active LOW Sampled on the rising edge of CLK if CEN is active LOW Synchronous This signal must be asserted LOW to initiate a write sequence ADV LD Input Advance Load Input Used to advance the on chip address counter or load a new address Synchronous When HIGH and CEN is asserted LOW the internal burst counter is advanced When LOW a new address can be loaded into the device for an access After being deselected ADV LD must be driven LOW to load a new address CLK Input Clock Input Captures all synchronous inputs to the device CLK is qualified with CEN CLK is Clock only recognized if CEN is active LOW CE Input Chip Enable 1 Input Active LOW Sampled on the rising edge of CLK Used in conjunction Synchronous with and to select or deselect the device Input Chip Enable 2 Input Active HIGH Sampled on the rising edge of CLK Used in conjunction Synchronous with CE and CEs to select or deselect the device Input Chip Enable 3 Input Active LOW Sampled on the rising edge of CLK Used in conjunction Synchronous with and CE to select or deselect the device OE Input Output Enable Asynchronous Input Active LOW Combined with the synchronous logic Asynchronous blockinside the device to control the direction of the IO pins When LOW the IO pins are enabled to behave as outputs When deasserted HIGH IO pins are tri stated and act as inp
36. lt 0 3 Current TTL Inputs f 0 inputs static Notes 12 Overshoot lt Vpp 1 5 pulse width less than 2 Undershoot AC gt 2V pulse width less than tcyc 2 13 Tpower up assumes a linear ramp from OV to Vpp min within 200 ms During this time lt Vpp and Vppo lt 14 The operation current is calculated with 50 read cycle and 50 write cycle Document 001 15013 Rev E Page 20 of 30 Feedback 55 PERFORM Capacitance Tested initially and after any design or process change that may affect these parameters CY7C1471BV25 CY7C1473BV25 CY7C1475BV25 m mn 100 165 FBGA 209 FBGA Parameter Description Test Conditions Max Max Max Unit CADDRESS Address Input Capacitance 25 f 1 MHz 6 6 6 pF Vpp 2 5V CDATA Data Input Capacitance 2 5V 5 5 5 Control Input Capacitance 8 8 8 pF Clock Input Capacitance 6 6 6 pF Cio Input Output Capacitance 5 5 5 pF Thermal Resistance Tested initially and after any design or process change that may affect these parameters n 100 165 209 FBGA Description Test Conditions Package Package Package Unit OJA Thermal Resistance Test conditions follow 24 63 16 3 15 2 C W Junction to Ambient standard test methods and 3 procedures
37. ox TCK Clock LOW to TDO Invalid 0 ns Setup Times truss TMS Setup to TCK Clock Rise 5 ns trois TDI Setup to TCK Clock Rise 5 ns tes Capture Setup to TCK Rise 5 ns Hold Times trusH TMS Hold after TCK Clock Rise 5 ns TDI Hold after Clock Rise 5 ns tcu Capture Hold after Clock Rise 5 ns 2 5V TAP AC Test Conditions Figure 6 2 5V TAP AC Output Load Equivalent Input pulse levels ss Vss to 2 5V 1 25V Input rise and 1ns Input timing reference 1 25V 500 Output reference levels 0 1 25V TDO Test load termination supply voltage 1 25V Zo 500 20pF TAP DC Electrical Characteristics And Operating Conditions 0 lt TA lt 70 Vpp 2 375 to 2 625 unless otherwise noted 11 Parameter Description Test Conditions Min Max Unit Vout Output HIGH Voltage 1 0 mA Vppo 2 5V 2 0 2 Output HIGH Voltage lo 100 uA 2 5V 2 1 V Vout Output LOW Voltage 1 0 mA Vppo 2 5V 0 4 V 2 Output LOW Voltage loj 100 pA Vppg 2 5V 0 2 V Input HIGH Voltage Vppo 2 5V 1 7 Vpp 0 3 V Input LOW Voltage Vppo 2 5V 0 3 0 7 Ix Input Load Current GND lt Vin lt Vppo 5 5 Notes 9 tcs and refer to the setup and hold time requirements of latching data from the boundary scan register 10 Test conditions are specified using the load in AC Test Condi
38. po 0 5V Industrial 40 to 85 C Vpp Electrical Characteristics Over the Operating Range 12 13 Parameter Description Test Conditions Min Max Unit Vpp Power Supply Voltage 2 375 2 625 V IO Supply Voltage For 2 5V IO 2 375 V Output HIGH Voltage For 2 5V IO 1 0 mA 2 0 V VoL Output LOW Voltage For 2 5V IO 1 0 mA 0 4 V Input HIGH Voltagel For 2 5V IO 1 7 0 3 V Vit Input LOW 2 For 2 5V IO 0 3 0 7 Ix Input Leakage Current GND x Vi lt Vppo 5 5 77 Input Current of MODE Input Vss 30 Input 5 Input Current of ZZ Input Vas 5 Input 30 loz Output Leakage Current GND lt x Output Disabled 5 5 Ipp R4l Vpp Operating Supply Vpp Max lour 0 mA 6 5 ns cycle 133 MHz 305 mA Current f fmax l tevc 8 5 ns cycle 100 MHz 275 mA Automatic CE Vpp Max Device Deselected 6 5 ns cycle 133 MHz 170 mA Inputs 1 8 5 ns cycle 100 MHz mA Automatic CE Vpp Max Device Deselected All speeds 120 mA Power Down Vin lt 0 3 or Vin gt Vpp 0 3 Current CMOS Inputs 0 inputs static Automatic CE Vpp Max Device Deselected or 6 5 ns cycle 133 MHz 170 mA pus tac mA 4 Automatic CE Vpp Max Device Deselected All Speeds 135 mA Power Down Vin gt 0 3V or Vy
39. re that the TAP controller clock only operates at a frequency up to 20 MHz while the SRAM clock operates more than an order of magnitude faster Because there is a large difference in the clock frequencies it is possible that during the Capture DR state an input or output may undergo a transition The TAP may then try to capture a signal while in transition metastable state This does not harm the device but there is Page 14 of 30 Feedback no guarantee as to the value that is captured Repeatable results may not be possible To guarantee that the boundary scan register captures the correct signal value make certain that the SRAM signal is stabi lized long enough to meet the TAP controller s capture setup plus hold time tcs plus toy The SRAM clock input might not be captured correctly if there is no way in a design to stop or slow the clock during a SAMPLE PRELOAD instruction If this is an issue it is still possible to capture all other signals and simply ignore the value of the CLK captured in the boundary scan register After the data is captured it is possible to shift out the data by putting the TAP into the Shift DR state This places the boundary scan register between the TDI and TDO balls CY7C1471BV25 CY7C1473BV25 CY7C1475BV25 Note that since the PRELOAD part of the command is not imple mented putting the TAP to the Update DR state while performing a SAMPLE PRELOAD instruction has the same effect
40. ress Semiconductor Corporation Document 001 15013 Rev E 198 Champion Court San Jose CA 95134 1709 408 943 2600 Revised February 29 2008 Feedback Logic Block Diagram CY7C1471BV25 2M x 36 ADDRESS REGISTER ADV LD WRITE ADDRESS CY7C1471BV25 CY7C1473BV25 CY7C1475BV25 REGISTER U T D P 5 0 E T T ADV LD N A BWA WRITE I WRITE REGISTRY pus ARRAY E Dds BWs AND DATA COHERENCY DRIVERS gt 2 f FE E BW CONTROL LOGIC ii R DQPc BW 5 S DOP o WE N E INPUT K E REGISTER READ LOGIC CE2 gt SLEEP 22 CONTROL Logic Block Diagram CY7C1473BV25 4M x 18 AO A1 ADDRESS REGISTER MODE E BURST CLK ADVILD LOGIC CEN d WRITE ADDRESS REGISTER 7 U T D P 5 U D E T T ADVILD N A P MEMORY 5
41. s This pin is not available on TQFP packages NC No Connects Not internally connected to the die 144M 288M 576M and 1G are address expansion pins and are not internally connected to the die Functional Overview The CY7C1471BV25 CY7C1473BV25 and CY7C1475BV25 are synchronous flow through burst SRAMs designed specifi cally to eliminate wait states during write read transitions All synchronous inputs pass through input registers controlled by the rising edge of the clock The clock signal is qualified with the Clock Enable input signal CEN If CEN is HIGH the clock signal is not recognized and all internal states are maintained All synchronous operations are qualified with CEN Maximum access delay from the clock rise is 6 5 ns 133 MHz device Accesses are initiated by asserting all three Chip Enables CE4 CE3 active at the rising edge of the clock If CEN is active LOW and ADV LD is asserted LOW the address presented to the device is latched The access is either a read or write operation depending on the status of the Write Enable WE Use Byte Write Select BWy to conduct Byte Write operations Write operations are qualified by the WE All writes are simplified with on chip synchronous self timed write circuitry Three synchronous Chip Enables CE3 and asynchronous Output Enable OE simplify depth expansion All operations reads writes and deselects are pipelined A
42. tions 1 ns 11 All voltages refer to Vgg GND Document 001 15013 Rev E Page 16 of 30 Feedback Br d z rZ CYPRESS PERFORM Table 8 Identification Register Definitions CY7C1471BV25 CY7C1473BV25 CY7C1475BV25 Instruction Field CY CY gt Description Revision Number 31 29 000 000 Describes the version number Device Depth 28 24 01011 01011 01011 Reserved for internal use Architecture Memory Type 23 18 001001 001001 001001 Defines memory type and architecture Bus Width Density 17 12 100100 010100 110100 Defines width and density Cypress JEDEC ID Code 11 1 00000110100 00000110100 00000110100 unique identification of SRAM vendor ID Register Presence Indicator 0 1 1 Indicates the presence of an ID register Table 9 Scan Register Sizes Register Name Bit Size x36 Bit Size x18 Bit Size x72 Instruction 3 3 3 Bypass 1 1 1 ID 32 32 32 Boundary Scan Order 165FBGA 71 52 Boundary Scan Order 209BGA 110 Table 10 Identification Codes Instruction Code Description EXTEST 000 Captures IO ring contents Places the boundary scan register between TDI and TDO Forces all SRAM outputs to High Z state This instruction is not 1149 1 compliant IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and
43. ts Drive ADV LD LOW to load the GND initial address as described in the Single Write Access section z z When ADV LD is driven HIGH on the subsequent clock rise the Rees IE Chip Enables CE CEs CE3 and WE inputs are ignored A1 0 A1 A1 0 A1 A0 and the burst counter is incremented You must drive the correct BW inputs in each cycle of the Burst Write to write the correct 00 01 10 11 data bytes 01 10 11 00 Sleep Mode 10 11 00 01 The ZZ input pin is an asynchronous input Asserting ZZ places 11 00 01 10 the SRAM power conservation sleep mode Two clock cycles are required to enter into or exit from this sleep mode While in this mode data integrity is guaranteed Accesses pending when entering the sleep mode are not considered valid nor is the completion of the operation guaranteed You must select the device before entering the sleep mode CE CE3 must remain inactive for the duration of tzzpgc after the ZZ input returns LOW ZZ Mode Electrical Characteristics Parameter Description Test Conditions Min Max Unit Ippzz Sleep mode standby current ZZ gt Vpp 0 2V 120 mA 1775 Device operation to ZZ ZZ gt Vpp 0 2V 2tcyc ns tzzREC ZZ recovery time ZZ lt 0 2V 2tcyc ns ZZ active to sleep current This parameter is sampled 2tcyc ns 277 ZZ Inactive to exit sleep current This parameter is sampled 0 ns Document 001 15013 Rev E P
44. ut data pins OE is masked during the data portion of a write sequence during the first clock when emerging from a deselected state when the device has been deselected CEN Input Clock Enable Input Active LOW When asserted LOW the clock signal is recognized by the Synchronous SRAM When deasserted HIGH the clock signal is masked Because deasserting CEN does not deselect the device CEN can be used to extend the previous cycle when required 22 Input ZZ Sleep Input This active HIGH input places the device in a non time critical sleep Asynchronous condition with data integrity preserved For normal operation this pin must be LOW or left floating ZZ pin has an internal pull down DQ IO Bidirectional Data IO Lines As inputs they feed into an on chip data register that is triggered Synchronous by the rising edge of CLK As outputs they deliver the data contained in the memory location specified by the addresses presented during the previous clock rise of the read cycle The direction of the pins is controlled by OE When OE is asserted LOW the pins behave as outputs When HIGH DQ DQPx are placed a tri state condition The outputs are automatically tri stated during the data portion of a write sequence during the first clock when emerging from a deselected state and when the device is deselected regardless of the state of OE IO Bidirectional Data Parity IO Lines Functionally these signals are identical to DQ During
45. with a binary 01 pattern to enable fault isolation of the board level serial test data path Bypass Register To save time when serially shifting data through registers it is sometimes advantageous to skip certain chips The bypass register is a single bit register that can be placed between the TDI and TDO balls This shifts the data through the SRAM with minimal delay The bypass register is set LOW Vas when the BYPASS instruction is executed Boundary Scan Register The boundary scan register is connected to all the input and bidirectional balls on the SRAM The boundary scan register is loaded with the contents of the RAM IO ring when the TAP controller is in the Capture DR state and is then placed between the TDI and TDO balls when the controller is moved to the Shift DR state The EXTEST SAMPLE PRELOAD and SAMPLE Z instructions can be used to capture the contents of the IO ring The Boundary Scan Order tables show the order in which the bits are connected Each bit corresponds to one of the bumps on the SRAM package The MSB of the register is connected to TDI and the LSB is connected to TDO Identification ID Register The ID register is loaded with a vendor specific 32 bit code during the Capture DR state when the IDCODE command is loaded in the instruction register The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift DR state The ID register has a vendor code and other
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