Acorn Products Z80 User's Manual
Contents
1. Now th the B n the second processor switched off BC Microcomputer tential of Cj f f not approx 5V between BC Microcom the secon potential of Also pin 3 and both 1 1 processor 5V between 2 check that there is a po pins 1 and 5 f necessary replacing i ON OFF switch up and pins 1 and 5 le and connectors ON OFF switch down Check that check the ribbon cab switch off the ON OFF swi pin 4 ve puter tch up and pins 1 and 5 tential If not ON OFF switch down Check that there is grou of between 2v and 4 investigate components R2 and adjust it to 5V using the trimm th th or more of Switch off SET EY MAY IP ground of BC Microcomputer and from these supplies fails then the switch a nd and switch there is a TC between Diagnostic Flowcharts Power up BBC Second Processor off Turn BBC off power up Second Processor then power up BBC Ia 280 message displayed Is BBC message displayed Flashing cursor only displayed Master Flowchart Proceasor respond to keyboard ls DNFS ROM in BBC Micro Note The letters in circles refer to the relevant flowcharts which follow2. Does Second Check break reset circuit Replace ICs 1 2 and 3 in turn version 1 02 Fit DNFS ROM 1 0 relurn 10 start Replace in turn 1C1 2 3 BBC Micro fails when 280 Second Processor connected and off Check for bent pin on BEC Micro Tube socket and damaged cable assembly Ribbon cable and connectors OK Replace Tube with known good one Replace IC29 Is HCS present at 6 Check for shorted tracks on host side of Tube IC1 on Z80 PCB 27 TUBE 280 message displayed no response to keyboard Ts Replace DNFS ROM with DNFS version ROM 1 0 or 1 0 higher Is current drawn by 280 PCB gt 800mA 2 Check for hot component and replace Check for temperature sensitive component failure Any temperature sensitive components found and replaced Check Refresh circuits Address data lines DRAMs BAC Microcomputer 32K message displayed Is there 4 9 5 25V across C3 Ts Is Repair there power there power B on P4 of IC1 at BBC Tube from BBC socket Check ribbon cable assembly and connectors Is power at pins 2 and 3 of Tube IC Check tracks and L1 R2 for failure Is there continu ty from p
3. ii When PCS and PCS occur simultaneously this WAIT pulse is generated frequently during data transfer via the Tube Note that in this second case the WAIT signal is produced by the desync logic WAIT is permanently low or high check 7 after pressing BREAK the WAIT signal should go low and then high If not check that 0 is clocking IC16A and B and IC30A and B for HCS PCS WAIT and that the desync circuits are producing the correct WAIT outputs See section 9019 6 3 4 ROM Signal Break On power up the RC network C2 provides a low to high transition of approximately 0 1 second duration to pin 9 of IC19C If power up reset fails and the low to high transition time is found to be incorrect check these component values and replace as necessary After power up pressing and releasing the BREAK key on the host keyboard causes PRST to appear on pin 37 of Tube This is clocked through IC15B by Ml Thus if the CPU is halted for any reason 1 will not be present and a BREAK reset will not be possible i e a successful power up reset is necessary to allow any further resets to work The low signal should clock to monostable IC14 which should produce a signal of approximately 1015 duration not check the values of RC network R7 C8 and
4. tr te 9g 29 Al a Ela pa a E am i Al 9 OTP6 x mE 3 see man pe x 5 ns et 4l 21 a A Z80 PCB Silk Screen 240V NOM 220 260V 50 60 Hz DI y TRI Fi 5 DC 1 04 21 3V9 500mW VRI 1008 C6 gs y SET 5V R5 56R COMMON Power Supply Circuit Diagram 47 General Assembly ond Processor Z80 Sec 280 Second Processor Parts Lists NOTE Items indentified by are normally available as spare parts please contact your supplier for details of availability ITEM PART No DESCRIPTION REMARKS Z80 Second Processor General Assembly SEE PAGE 47 2 201 110 CASE LOWER MOULDING 1 3 201 109 CASE UPPER MOULDING 1 4 201 742 CASE LABEL LOWER 1 REAR 5 201 108 CASE LABEL UPPER 1 7 831 000 POWER SUPPLY ASSEMBLY 8 870 302 MAINS CABLE C W PLUG 1 9 870 040 40 WAY RIBBON CABLE GREY 260mm 1 800 027 40 WAY RIBBON CABLE STRAIN RELIEF 1 800 017 40 WAY RIBBON CABLE CABLE SOCKET 10 880 025 CABLE GROMMET 1 11 800 037 S P E CONNECTOR 1 TOP PALF 12 815 900 FUSE POLDER 1 13 815 901 FUSE HOLDER SHROUD 1 14 815 207 FUSE 20mm x 5mm 250mA 1 SLO BLO 15 805 003 MAINS SWITCH 1 23 882 946 SPIRE NUT No 6 2 24 882
5. 6 3 2 RAS CAS Generator Circuits Both of these are best traced back from the RAM RAS is always present and should be seen at TP8 and also inverted at pin 3 of IC21A If only one appears then check for loading either on the address buffers or on the DRAMS RAS is generated by both IC18A IC17B SUE and CPOP signals respectively independently of each other but both are required to be operating for full RAS ability RAS may therefore be appearing due to only one of the two Dtypes working so check that pins 1 and 2 of both IC20A and IC21A are operating If not check the operation of the Dtypes according to inputs RAS will fail if the CPU is not operating as it requires Ml and MREQ as well as the clock signal The operation of CAS is dependant upon the functioning of RAS and also the correct decoding of a memory access Check that memory RD W or Instruction Fetch 1 signals appear then check that this is properly decoded from IC23B to IC23C via IC20C and not disabled by an incorrect signal from 1C23D 6 3 3 Wait State Generator IC2 pin 24 should predominantly be high WAIT should only be active under two conditions 1 During ROM read TP2 goes low for approximately 0 25sec This is visible as a low on a logic probe applied to IC16A pin 2 after the BREAK key has been pressed
6. ACORN COMPUTER 280 second processor service Manual Z80 SECOND PROC Part No 0409 Issue 2 August 1984 ESSSOR S 015 ERVIC T MANUAL Within this publication the term BBC is used as an abbreviation for British Broadcasting Corporation Copyright Acorn Computers Limited 1984 Neither the whole or any part of the information contained in or the product described in this manual may be adapted or reproduced in any material form except with the prior written approval of Acorn Computers Limited Acorn Computers The product described in this manual and products for use with it are subject to continuous development and improvement All information of a technical nature and particulars of the product and its use including the information and particulars in this manual are given by Acorn Computers in good faith However it is acknowledged that there may be errors or omissions in this manual A list of details of any amendments or revisions to this manual can be obtained upon request from Acorn Computers Technical Enquiries Acorn Computers welcom comments and suggestions relating to the product and this manual All correspondence should be addressed to Technical Enquiries Acorn Computers Limited Newmarket Road Cambridge CB5 8PD All maintenance and service on the product must be carried ou
7. STATUS REGISTER Action required Not full Not full 6 Schematic diagram of Tube registers Read address Read address Read address 1 Read address 2 Read address 3 Read address 4 Read address 5 Read address 6 Read address 7 PARASITE Read address Y Write address 1 Read address 2 Write address 3 Read addresa 4 Write address 5 Read address 6 Write address 7 The following tables register in the Tube show the relative address and type of each firstly for the Host system and secondly for the parasite system second processor Table 1 Host system registers Register 1 flags 24 byte FIFO read only Address Read 000 Status flags and 001 Register 1 010 Register 2 flags 01 Register 2 1 by 100 Register 3 flags 101 Register 3 2 by 110 Register 4 flags 1 Register 4 1 by Address Vrite 000 Status Flags 001 Register 1 1 byt 010 011 Register 2 1 by 100 101 Register 3 110 1 Register 4 Table 2 Parasite system registers te read only te FIFO read only te read only e write only te write only 2 byte FIFO write only 1 byte write only Address Read 000 Status flags and Register 1 flags Al FLPVMJTIO 001 Register 1 1 byte read only 010 Register 2 flags 011 Register 2
8. of spec then set it to 5V exactly using the trimmer which is accessible through a hole in the power supply board See Fig 9 If 5v cannot be obtained and or replace the power supply unit Now remove th resistor connected across reconnect them to the second pro Test the current drawn by the the noise level is out of spec the power supply leads and cessor PCB ensuring correct polarity second processor PCB from the 5V supply The board should draw 600 800mA from the power supply 6 adjust Fig 9 Position of 5V Trimmer Power Supply PCB the current is ero the second processor PCB has gone open ircuit Check fuse 51 and connectors and tracks If the fuse is blown the fault is a short circuit on the PCB the current is higher than it should be measure the voltage the voltage is greater than 5 257 If the voltage is in spec 5 e power supply an ee fig 9 omponents n the second proc d feel then one faulty essor PCB is which of the components is hot WARNING TAKE CARE WPEN CPECKING FOR POT COMPONENTS HOT ENOUGH TO CAUSE INJURY 6 3 10 Checking the Tube power supplies The Tube IC1 is powered both from the B the second processor If eith elu second processor will not work Wi
9. 32 11 00 32 04 04 60 33 37 00 183 906 880 049 820 120 815 007 860 002 815 910 800 200 795 006 794 148 1 1 1 1 1 1 1 4 ho rS NO PO PD No ODOOFNDWDAOCAOO t t OR X CR oO O WO gt 5 PAGE 41 cont d INTEGRATED CIRCUIT 8264 INTEGRATED CIRCUIT 7415123 INTEGRATED CIRCUIT 74574 74 74 INTEGRATED CIRCUIT 741 574 INTEGRATED CIRCUIT 7415132 INTEGRATED CIRCUIT 74LS11 INTEGRATED CIRCUIT 741500 INTEGRATED CIRCUIT 741 532 INTEGRATED CIRCUIT 74504 INTEGRATED CIRCUIT 741 504 INTEGRATED CIRCUIT 7415260 INTEGRATED CIRCUIT 7415133 S H E CONNECTOR THYRISTOR C122F TRANSISTOR 2N3906 INSULATOR CRYSTAL 12MPz FUSE 20mm x 5mm 1 AMP INDUCTOR 2u2 10 FUSE CLIP FASTON TAB ZENER BZY88 5 1 DIODE 1N4148 IC6 13 Ic14 IC15 IC16 18 30 IC19 IC20 IC2 1C22 23 29 IC24 IC25 IC26 IC27 PL1 PALF THl 01 FOR ITEM 45 ya FS1 D3 D1 Acorn Computers Limited Fulbourn Road Cherry Hinton Cambridge 1 4JN England
10. corrected replace it Check for and correct short circuit on PCB To BBC Microcomputer Data Address Control HCS N Reset ROM 1 control NMISERV 280 Second Processor Functional Block Diagram IC 2 c4 tC 240 04 10nf 504 8 0v 8264 1 208 RAM V 22 m 7415123 tsm NMISERV T 7454 I sh w wr 1 7415132 700511 E 2 14 1741500 WA 5 41532 1000pF 104 2 4 12 I t cis a 74 15123 811595 AKI NOT FITTED ov TUBE POWER DOWN SWITCH FITTED 5v R C234 1 25 5 c7 R6 22R 532 1504 5 33pF 220R 3 13 42 gt 5 TKZ K DET 1 gt 4 18 E RN SS Sa ES 19 5312 NP __01 7 2732 A ROM id E c 1 ap ES EN 280 second Processor PCB Circuit Diag m 4 D O ITEM as ITEM 31 E 5 B E85 x3 ITEM 55 ITEN I9 WEM 1 4 TM TEMO TP5 a ITEM A A 29 e ap zx 2 e ew 1 M E rel ne o a ES a fo Es of 7 Ins AP go al TPBO 104
11. 1 byte read only 100 Register 3 flags 101 Register 3 2 byte FIFO read only 110 Register 4 flags 11 Register 4 1 byte read only Address Vrite 000 001 Register 1 24 byte FIFO write only 010 011 Register 2 1 byte write only 100 101 Register 3 2 byte FIFO write only 110 11 Register 4 1 byte write only As can be seen from Fig e g for writing register 1 The system and by NRDS NWDS on the Parasite system s Tube Pinout Diagram Only registers 2 and 4 are simple latches register 3 is a 2 byte FIFO in each direction and register 1 is a 24 byte FIFO from the Parasite 780 to the Post but a simple latch from Post to the Parasit The Tube produces maskable and non maskable interrupts to the Parasite see sections 5 6 and 5 3 and a reset signal section Sub The Z80 IORQ and M1 signals are decoded to detect an I O cycle by the OR gate IC22A which provides the signal which via the De sync circuit initiates the chip select PCS to the Tub The Tube thus I O map the four data registers and four occupies all of the 780 associated status registers reflect addresses 5 10 2 Tube Pinout Host 1 0 Processor system M HD Ho2 HR W HRST HiRQ register sel 6 and Tables 1 and 2 is actually two registers cted is determined by R W on the Post each numbered register one for reading and one vCC
12. after might reset cycle an result signal M1 A monostabl the jj nable t low going pulse of gate IC22C provides he Wait State see timing diagram further two clock cycles after WAIT input on the by the host immediatel therwise corruption of DRAM data latch CIS B synchronises the the beginning of an instruction fetch IC14 nsures th reset Signal to the CPU is a pulse of approx produce a reset without delaying the refresh to the DI losing data The reset to the CPU also Aus duration s clears the ROM bringing the shadow ROM into the memory map The Schmi the delay on Power 5 6 The host processor can interrupt the Z80 with a maskable interrupt terrupt output from the Tube is taken directly to the Tub the capaci tt NAND gate network 1 IC C2 time constant Interrupt Handling The in INT input IORQ outputs go 1 on the data bus DO to D7 of the Z80 low to indicate a After detection of 9C provides a Power Up reset to Diode Dl ensures tor does not apply a reverse voltage to the NAND gate i Down 100ms an interrupt IC The buffer 28 is enabled by latch the CPU M1 vector for the interrupt is expec ufficient to RAMS a nd so IC15A the 780 from chat nput via the an
13. if not at this appears at pin 3 the ty Check the clock signal 6 3 5 Desynchronising Logic a After power up check that PCS is active then either the Tube 1C1 or IC29 has fail side there is a ribbon cable connector faul PCS After pressing BREAK check at pins and 2 of IC22A and th low then appears at pin 21 of Desync logic circuit is faul IC30 and the inverted clock signal at pin 3 Circuit Description logic circuit the Desync check that all led on the seco t With HCS checked to be should always operation of runc i2 Gf C30 reach Pin IC30A and that pin 5 of when HCS is active 6 3 6 NM S ERV tioning correctly B when HCS is high IC30A only produces a low signal 17 of nd PCS Disable HCS el not nd processor or the Host is faulty pin 18 of that a low signal appears simultaneously Check that a at pin 11 of whilst referring to the signals are operating correctly in PCS REO via TE not IC29A check IC2 the address When an active signal appears at pin lines should be seen to address 066H decode through circuit will 1C26 27 to give the prevent disk access uit ERV dire NMIS that NMI rom pin 9 of from IC2 pin Check for broken tracks and replace 6
14. result of plugging in a broken 280 second processor as the majority of faults manifest themselves in this way Normal Operation until BREAK reset attempted system fails Most probably caused by failure IC14 and associated components reset circuit IC15b BBC Microcomputer fails when Z80 Second Processor connected to Tube socket Probable causes are misconnected or damaged plugs sockets and or damaged ribbon cable Tube IC failure or IC29 failed on 280 PCB Diagnostic Flowcharts for the above conditions are given in the Appendix These should be read in conjunction with the following Circuit Checks 6 3 Circuit Checks 6 3 1 Clock Using an oscilloscope check that a 12MHz signal is being generated at pin 13 of IC22D If not check the crystal X1 resistor values and operation of inverters IC24D E Trace the signal to pin 9 of IC17A where it should appear as a clearly defined 6MHz square wave 0 4 should appear from the driver 01 to supply 2 pin 6 Check that the clock signals 4 and appear at all the expected points shown on the circuit diagram If not check for loading caused by failed IC s and track short circuits Pin 11 of 1C19D should also be generating a delayed clock required for the NMISERV circuit If no delayed clock is found check the values of C9 and R9
15. sure that the second processor is disconnected from the mains supply check the mains switch at the rear of the unit Overload protection of the second processor is provided on the second processor 280 board itself Fuse FS1 protects against overcurrent and thyristor Till protects against overvoltage by blowing the fuse ollows The overvoltage protection circuit functions as the rail voltage across 11 exc which is capable of drawing 8 is 5 1V Zener diode rail voltages greater than 5 1V appear across resistor R11 whilst spikes are absorbed by capacitor Cl eeds approximately 1V thyristor amps conducts and blows the 1 1V voltage reaches approximately 6 overcurrent and there is lik high a voltage THl amp fast blow fuse 51 Supply rail cut off is therefore achieved if the If fuse 51 is blown it could be due to either overvoltage or ely to be either a short circuit somewhere or the power supply board is faulty it is supplying too Disconnect the two power supply leads brown and black from the second processor PCB and connec Measure the voltage across the ground which should be in the t a 10 ohm 2 5W resistor between brown lead 5V and the black 50mV nois peak to peak 0 50MPz bandwidth them lead range 4 95 to 5 25V with a maximum of If the voltage is out
16. w p MONAT A Hr N NN E p 25 37 BR PP SP 1 O1 WARNING THE Z80 SECOND PROCESSOR MUST BE EARTHED Important The wires in the mains lead for the Z80 second processor are coloured in accordance with the following code Green and yellow Earth Blue Neutral Brown Live As the colours of the wires may not correspond with the coloured markings identifying the terminals in your plug proceed as follows The wire which is coloured green and yellow must be connected to the terminal in the plug which is marked by the letter E or by the safety earth symbol 4 or coloured green or green and yellow The wire which is coloured blue must be connected to the terminal which is marked with the letter N or coloured black The wire which is coloured brown must be connected to the terminal which is marked with the letter L or coloured red If the socket outlet available is not suitable for the plug supplied the plug should be cut off and the appropriate plug fitted and wired as previously noted The moulded plug which was cut off must be disposed of as it would be a potential shock hazard if it were to be plugged in with the cut off end of the mains cord exposed The moulded plug must be used with the fuse and fuse carrier firmly in place The fuse carrier is of the same basic colour as th
17. 2 Fig 7 Pinout diagram for Tube IC GND ting throughout the possible 256 PAO 1 PCS PDo PD Parasite Second Processor system PNRDS PNWDS PRST PNMI PIRQ DESCR OF PI NS ref Power Supply Data buses Address signals Timing signals Interrupt lines DMA lines GND VCC1 VCC2 VCC3 HD0 7 PDO 7 0 2 2 5 5 42 PR W PNRDS PNWDS DRO DACK Fig 7 OV supply rail Parasite main Host 5V supply 8 bit data bus to 8 bit data bus to processor 3 register select lines 5V supply Parasite secondary supply 2 3v Host processor Parasite rom Post lines from 3 register select Parasite Post chip select Parasite chip select c Host 2 high level signifies valid address bus Post read write lin determines whether read or write register is selected on address specified by PAO 2 and direction of data flow on PDO 7 Parasite read strobe Parasite write strobe Host reset RST Reset RST processor initialises to known state and generates PRST line to parasite Non maskable interrupt active low active low Tube to parasite used by 280 rer Interrupt to Host not second processor Request for DMA transf DMA acknowledge from DMA c
18. 3 7 In Whe that buffer output and power rails 6 3 8 DRAMS The following should be performed for each DRAM in turn terrupt OFE n operating the be read Check the operation of the buffer inpu Dynamic 1 nstruction fetch NMI This should NM Failure of this 5 IC27 appears at pin 4 of IC s 26 and 27 if necessary E um Boot IC28 ts are correctly tied ROM the interrupt vector OFEP from that 1 and high or low of FE Rep ace IC28 RAM IC s y pins and W are all appearing Check the power suppl that RAS CAS buffers becom nabled and providing active address lines to the DRAMS active low is appearing upon request if necessary ERV signal If this occurs 17 appears at pin 5 of check OD clock C21B and that IC21D pin 12 IC15A and IC28 will RO are appearing and that the check tracks mets IC s 6 13 5v to pin 8 and Ov to pin 16 Check then make sure that address at pins 1 and 19 of 1C s 4 and 5 Check that no address lines are shorted together and that all data lines are operating and not tied together 6 3 9 Power Supply Check the 250 mA type T mains fuse unit see section 2 Check for any loose disconnected or broken leads accessible at the rear of the After making
19. 665 SELFTAP PAN HD SCREW No6 x 13mm 3 BLACK 26 890 000 STICK ON FOOT 4 280 PCB Assembly SEE PAGE 41 4 502 103 RESISTOR 10K 1 4W 5 1 R7 5 502 821 RESISTOR 820R 1 4W 5 2 6 502 220 RESISTOR 22R 1 4W 5 1 R8 7 502 221 RESISTOR 220R 1 4W 5 2 R6 9 8 502 122 RESISTOR 1K2 1 4W 5 1 R5 9 502 120 RESISTOR 12R 1W 10 1 R2 10 502 391 RESISTOR 390R 1 4W 5 1 R11 1 502 102 RESISTOR 1K 1 4W 5 1 RI 2 628 101 CAPACITOR 100nF CERAMIC 1 C11 3 613 101 CAPACITOR 10uF 35V TANT 1 C10 4 620 101 CAPACITOR 100uF 6V3 ELEC 5 621 470 CAPACITOR 47uF 10V ELEC 1 6 629 010 CAPACITOR 10nF PLATE CERAMIC 1 C4 7 631 033 CAPACITOR 33pF PLATE CERAMIC 2 5 7 8 630 100 CAPACITOR 1000pF PLATE CERAMIC 1 C8 9 628 470 CAPACITOR DECOUPLER 33 A NOM 47nF 20 631 056 CAPACITOR 56pF PLATE CERAMIC 1 C9 23 800 124 IC SOCKET 24 WAY DIL 1 FOR IC3 24 800 140 IC SOCKET 40 WAY DIL 2 FOR 101 2 26 201 605 INTEGRATED CIRCUIT TUBE 1 101 27 700 080 INTEGRATED CIRCUIT Z80B 1 1 2 CPU 28 201 644 INTEGRATED CIRCUIT BOOT ROM 1 29 738 095 INTEGRATED CIRCUIT 811895 7418795 3 IC4 5 28 Z80 PCB Assembly SEE 31 32 33 34 35 36 37 38 39 AAA 01C0 ho r2 O 50 Si 53 54 55 56 50 104 164 742 123 741 074 748 074 074
20. IT Occurs during reads from the ROM and as result of simultaneous HCS PCS event Enables refresh cycles TP8 RAS Row Address Signal used in ALL memory addressing both for accessing and refreshing TP9 CAS Column Address Signal used only for memory accessing disabled during refresh 6 2 Fault Conditions A Z80 Second Processor failure can usually be related to one of five fault conditions BBC Microcomputer 32k message displayed Predominantly caused by either power failure misconnected or damaged plugs and or interconnecting cable Acorn TUBE 780 64k message displayed no response to Keyboard If this message is displayed the ROM has been copied completely to RAM the ROM disabled and the Boot procedure begun Failure to respond to the keyboard means that the system has crashed due to either hardware or software failure Possible causes may be Software Hardware Incompatible or failed Tube register fault DNFS or Boot ROM 280 fault DRAM error A further consideration is that a component or components may hav becom temperature sensitive and are failing intermittently Check by first replacing 1C2 and in turn then check operation once warm use a freezer spray to locate temperature sensitive components Flashing Cursor in the top left corner of an otherwise blank screen Total Failure This is the most usual
21. S the RAS lines AO to A7 is disabled and IC4 DRAMS The ensures a slight delay in the enabling of the Column to avoid data conflict with the Row buffer is generated from the RAS under certain other conditions If the shadow ROM output enable signal logic 1 on pin The AND gate 1C20C enables or disables the CAS signal CAS is enabled if 1 the memory cycle is a Too Ta d T write cycle WR 1 L low to IC20C pin 11 read cycle and not an instruction fetch MREQ cycle IC18B not preset by 1 RED signal to IC20 CHOP RAS pin 9 or iii the cycle is an instruction fetch this signal being synchronised to the CPOP signal by OR gate 1C23B to s IC20 pin 10 2 Note In this case the E CAS CAS signal will not be generated if the ROM is pied selected WR t 4 08 E Fig 2 RAM read or write cycles 5 7 2 Instruction Fetch Cycles 780 CPU handles an Instruction Fetch differently to other memory read cycles in that the MREQ signal is active for only 1 5 clock cycles instead of 2 In order to allow sufficient access time for the DRAMS in this abbreviated cycle the Instruction Fetch signal Ml is used to generate the RAS and CAS signals a half cycle earlier The OR gate IC23A allows the clock signal through to the D latch IC18A only when M1 is active The output of the D latch SUE is clo
22. cked low and generates the row address latch signal RAS a half clock cycle before the CPOP signal would have done When the CPOP signal arrives after being generated by the MREQ see section 5 7 1 it clears the SUE latch and holds RAS low itself until MREQ becomes inactive SUE i zt c 1 Valid data I i l 1 1 LI i 1 l D l RFSHp28 1 i 1 Wait eyele i i a last ruetion fetch Refresh el Fig 3 Instruction Fetch cycles 5 8 DRAM Refresh After each instruction fetch the Z280 CPU performs a Refresh cycle for the DRAMS in the period while the instruction is being decoded A seven bit refresh address is output onto the address bus A0 to A6 A7 0 for approx 2 clock cycles and the MREQ signal goes low The RFSH signal from the 280 is not used and no other memory con by the CPU Once the MRI and hence trol signals go activ after each time signal goes active RAS as normal the The CAS is not required for a Refresh cycle The Refresh address D latch is incremented 1C18B produces CPOP and is not enabled since none of the conditions listed in section 5 7 lb are true When the shadow ROM is being read disabled bu
23. d ted IORQ M1 and and its inputs are permanently tied to logic 0 or 1 to give a vector address of OFEH into address for the interrupt system Mode 2 5 7 DRAM Control The Z80 Boot th ROM plac High Byte tor of OFFF wi es the Z80 internal interrupt address of OFFH 5 7 1 Read Write Cycles a RAS Whenever a memory cycle occurs is removed by the MREQ signal C17 B edge of the system clock During memory read or write cycles row address causing the row address the row address buffer 1C5 was enabled by CHOP DRAMS Prior to the RAS signal high level on RAS and consequently the low level on the inverted signal Signal CHOP produces th the D latch to be passed enabled to allow the inverter IC25E buffer b CAS The column address Signal by the OR gates is active then th IC23D to the DRAMS sig RAS from 1C21A thus allowing the low order address the preset signal from the 280 signal information to be latched by the EH On the output goes low TP8 via Once RAS goes column address nal to the DRAMS IC23C amp D CAS signal will not be generated low IC5 on the giving an latch next rising giving the the falling edge of through to the IC20A to the RAM
24. e coloured insert in the base of the plug Different manufacturers plugs and fuse carriers are not interchangeable In the event of loss of the fuse carrier the moulded plug MUST NOT be used Either replace the moulded plug with another conventional plug wired as previously described or obtain a replacement fuse carrier from an authorised BBC Microcomputer dealer In the event of the fuse blowing it should be replaced after clearing any faults with a 3 amp fuse that is ASTA approved to BS1362 Not necessarily the same shade of that colour 1 Introduction This manual is intended to provide the information required to diagnose and repair faults on the Z80 second processor a part of the BBC Microcomputer system which was designed by Acorn Computers Ltd of Cambridge England The information contained in this manual is aimed at Acorn dealers and servic ngineers who will be servicing the Z80 second processor on behalf of Acorn Computers Ltd 780 is a trademark of Zilog Inc CP M is a registered trademark of Digital Research Inc The Tube is a trademark of Acorn Computers Limited 2 Packaging and Installation The Z80 second processor is supplied in a two part moulded polystyrene packing which is further packaged within a cardboard sleeve Supplied with the second processor is a DNFS ROM with fitting instruct
25. ed from acting At no time is PCS affected as it would not be possible to the B stop BC processor 5 10 The Tube The Tube IC1 is an Acorn custom IC which provides parallel asynchronous communication between two processor systems the BBC Microcomputer Host and the Z80 second processor Parasite To each processor system it resembles a conventional peripheral device comprising 4 read only and 4 write only 8 bit registers The Z80 accesses these registers via its I O structure Host Tube Parasite Fig 5 Tube concept 5 10 1 Tube Registers Each register has its own status byte with a separate I O address containing Register Full and Data Available flags The status byte for Register 1 contains additional control bits that may be set by the Host computer to enable interrupts or to reset the 780 These control bits may be read but not set by the second processor Fig 6 shows the Tube registers in more detail Write address Y Read address Y Read address 0 Write address 1 Read address 2 Write address 3 y Read address 4 Write address 5 Read address 6 Write address 7 HOST Read address Y Read address 1 Read address 2 Read address 3 Read address 4 Read address 5 Read address 6 Read address 7 Not full Data available Data available Data available Data available
26. erted clock by the DRAM control and the desync logic 5 3 ROM Latch The 280 second processor features a shadow ROM to boot the system upon power up and also to ensure proper handling of NMI interrupts from the host processor via The Tube The ROM is enabled at the proper times by the latch 15 1 After power up the reset signal from IC24F to the 780 is used to clock the latch IC15A and produce the ROM signal On any memory read cycle while the Rom signal TP2 is active IC22B amp C will produce output enable signal to the ROM IC3 pin 20 The initial instructions following RESET are executed from ROM and initiate the copying of ROM into high RAM This is followed by an instruction fetch cycle to memory over 8000H which is detected by the AND gate IC20B and used to clear the ROM latch remove the shadow ROM from the memory map and allow normal running in RAM 2 The NM1 signal to the Z80 processor is used by system software in Disc handling however the 780 interrupt vector to 66H is not compatible with standard CPM which has its default file control block in this area The solution used is to bring the shadow ROM temporarily into the memory map when an instruction fetch from 66H is detected IC26 and a cycle an instruction fetch
27. f which presets the ROM latch rom high RAM IC15A 1C27 provide a clock signal NM SERV during such In the ROM the destination expected by standard CPM 5 4 Wait states x Ld WAIT 0C21C pin amp WAIT request WAIT generalor ready Because of th to the ROM must b t 280 detects WAIT required WAIT applied lasts only one cycle one clock cycle When the OE signal to the generator 16 amp Via clock cycle is fed to above The Wait lengi th RO the NAND gate the WAIT input of the 780 generator requires a the end of the lengthen cycle to clear itsel alling edge of 0 tj 5 5 Reset d memor The 280 e slow access time of the thened by the e ROM is selected Mand this is used to e samples TP7 allows observal latching the ROM in until 66H contains a jump to Once WAIT REQUEST removed requires two rising clock edges to reset WAIT STATE generator boot insertion of a ROM Fig 1 all memory cycles Wait State of the LE2ZLC E OR the tion of the WAIT signal The Z80 second processor may be reset at any time processor via the Tube The Z80 requires that a reset signal should not occur instruction fetch cycle To avoid this from the Tube to
28. in 6 of IC1 to pin 29 of ribbon connector and to BBC Micro Flashing cursor displayed Any damage to ribbon cable or connectors 9 Repair replace as required Repair as required Is Check for current Short circuit on drawn by Z80 supply rail PCB gt 800mA Hot component Check the following circuits in sequence Clock Power up reset Wait ROM enable Desyne logie Interrupt RAS CAS DRAMs Retest at each stage necessary Remove supply leads from potentiometer on PSU 280 PCB connect to give Y with 50mY 100 2 5 W resistor max noise across leads and If unobtainable measure Remove Power Supply Check 250mA mains fuse at rear of unit replace if Check PSU mains switch and wiring ls voltage 4 9 5 50mV max noise resiator and reconnect to PCB Measure current drawn by PCB Is Is Is Current is lesa current current current than 700mA 700mA 100mA aero greater check power rails than 800mA to all power Set 5 adjust voltage replace PSU 1V with Fuse FS blown Replace fuse if fuse blows again check for and correct short un ton Look for and correct open circuit an 280 PCB la voltage zero Measure Any Check for vollage short circuit device which ACTOSE found and is hut and
29. ion sheet a set of reminder cards for the red function keys 7 floppy disks an end user licence Microcomputers fitted with MOS ROMs below version 1 2 a voucher redeemable against replacement supplied Note Care should and a guarantee card For BBC t of lower version ROMs is also be taken when unpacking and repacking this unit to ensure that all items are posit disks which should first be pac ioned correctly especially the floppy ked in plastic bags and laid flat The Z80 Second Processor User Guide and accompanying literature is supplied packed separately A mains power switch is located at the rear of the second processor e is located at the rear of the second A 250mA type T slow blow fus processor Before disconnected from by undoing the rou The mains supply in its holder with the cover screwed home removing this fuse the second processor must be the mains supply Access to the fuse may be gained nd cover with the slot in it using a screwdriver must not be r connected until the fuse is relocated Do not use the second processor in conditions of extreme heat cold humidity or dust or in places subject to vibration Do not block the ventilation under or behind the second processor Ensure that no foreign objects processor are inserted through any openings in the second 3 Specificat
30. ion 3 1 The 780 second processor A second processor for the BBC Microcomputer model B operating through the Tube providing the ability to run sophisticated software under the CP M 2 2 operating system The second processor is housed in a rigid injection moulded thermoplastic case and contains the following A 6MHz Z80B CPU 64K of read write Random Access Memory 4K Read Only Memory shadow ROM providing a boot function on power up and to handle Non Maskable Interrupts NMI from the Host processor via the Tube The Tube a fast asynchronous communication path connecting the second processor to the I O processor BBC Microcomputer A mains operated integral power supply comprising a mains transformer and power supply board 3 2 Power Supply Max AC Input 264V AC MIN AC Input 216V AC Power Rating 14 watts Supply Frequency 47 63Hz Max Output Current 1A at 5V 4 Disassembly and assembly To service the Z80 second processor disconnect it from the BBC Microcomputer and the mains supply and undo the three fixing screws two at the top of the back panel and one underneath the unit nearest the front and equidistant between the two rubber feet The assembly diagram is given in the Appendix The lid can now be removed revealing the transformer and power supply board held in place by six screws and the Z80 PCB It is recommended that the tran
31. ontroller DMA facility is not used by the 780 second processor 5 10 3 Tube Timing Diagram Fig 8 Tube Timing Diagram N B The timing reference for the Post is 0 and R W gives the direction of transfer For the parasite the PCS direction is given by PNRDS or PNWDS and timing by PCS MIN MAX 1 R W SET UP TO 02 35ns 2 TIMING STROBE PULSE WIDTH 110ns 3 ADDRESS SET UP TIME 35ns 4 ADDRESS amp CHIP SELECT POLD TIMES 10ns 5 DATA OUT DELAY TIME 70ns 6 DATA OUT POLD TIME 10ns 7 DATA IN SET UP TIME 50ns 8 DATA IN HOLD TIME 20ns 9 R W POLD TIME 10ns 10 CYCLE TIME 250ns 11 CS SET UP TIME 20ns 6 Fault Finding on the 280 Second Processor 6 1 General a The 780 second processor has three socketed IC s IC 1 3 these may easily be replaced if necessary b Test points are provided on the 780 PCB as follows TP1 CLOCK 6MHz clock signal 0 to pin 6 of 280 processor TP2 ROM disable activate signal to ROM pins 18 amp 20 1 780 generated clock signal indicating instruction fetch cycle Also used in interrupt handling TP4 MREQ goes low to indicate memory addressing TP5 PCS indicates successful parasite chip select to Tube via de sync logic circuit TP6 HCS indicates Post chip select to tube TP7 WA
32. replace if necessary The output of IC14 appears at pin 10 of IC19C from here on the reset function is common to both power up and BREAK as follows The reset signal from IC19C is inverted by IC24F and appears at pin 26 of IC2 CPU reset and also at pin 3 of IC 15A ROM latch so that if 1C15A is functioning correctly a reset should cause a low going pulse to appear at IC2 pin 26 reset active low followed by a low on TP2 ROM This signal must appear at pin 18 of IC3 and requires both MREQ and RD to be both active low to pass IC22C and output enable IC3 on pin 20 and disable CAS at IC21D pin 13 active low ROM signal at IC22C also appears at pin 2 of IC16A which enables WAIT states at pin 24 of IC2 see Wait State Generator above Using an oscilloscope check that all these events occur replacing any failed components After ROM on TP2 has remained low for approximately 0 25s the CPU executes an instruction fetch from high memory M1 and MREQ both go to active low and their inverted signals appear at pins 3 and 5 respectively of IC20B This combined with A15 high should produce a 1 ow at pin 6 which via IC24C will clear IC15A at pin 1 and remove the ROM signal Again check all conditions with an oscilloscope and correct any failed logic
33. sformer and power supply board are not removed unless absolutely necessary To remove the Z80 PCB from the case pull off the two fast on tabs which connect the power supply brown 5v and black Ov leads and remove the four screws which hold the PCB in place 5 Circuit Description A The circuit may be split into a number of sections by their specific function These are dealt with under separate headings Reference should be made where necessary to the block diagram and circuit diagram in the appendix 5 1 CPU The microprocessor used in this unit is a Z80B running at a clock frequency of 6MHz from a crystal oscillator All memory and cycles are performed at full speed with the exception of those to the boot ROM for which a Wait State is inserted by external logic 5 2 Clock A 12MHz crystal controls the frequency of the oscillator formed by the inverters 1C 24D E D type latch IC17A is used to divide the frequency to the required 6MHz Transistor 01 provides an active pull up for the clock signal after inversion by IC 24B to compensate for the high dynamic input current of the Z280 on this signal The NAND gate IC19D and associated network provide a shaped clock signal for the NMI Service Detect logic Since the output of the D latch is inverted before being used as CPU clock then the D output is available for use as an inv
34. t by Acorn Computers authorised dealers Acorn Computers can accept no liability whatsoever for any loss or damage caused by service or maintenance by unauthorised personnel This manual is intended only to assist the reader in the use of this product and therefore Acorn Computers shall not be liable for any loss or damage whatsoever arising from the use of any information or particulars in or any error or omission in this manual or any incorrect use of the product This manual is for the sole use of Acorn Computers authorised dealers and must only be used by them in connection with the product described within First published 1984 Published by Acorn Computers Limited CONTENTS w A JO C1 4 CO P2 ES DADO Appendix Introduction Packaging and Installation Specification Disassembly and Assembly Circuit Description CPU Clock ROM Latch ait States Reset nterrupt Handling RAM Control RAM Refresh esynchronising Logic he Tube Fault Finding on the 280 Second Processor General Fault Conditions Circuit Checks Diagnostic Flowcharts Z80 Second Processor Block Diagram Circuit Diagram Z80 PCB Component Layout Silk Screen Power Supply Unit Circuit Diagram Z80 Second Processor General Assembly Parts Lists General Assembly Z80 PCB Assembly Page
35. t th AND gate 1C20C row address latch signal the CAS signal to the DRAMS is RAS still occurs This has the effect of a refresh cycle to the DRAMS 5 9 Desynchronising Logic To prevent ambiguous events i e a register status change during a status read this circuit produces a WAIT signal to the 780 processor when the PCS and HCS signals occur simultaneously When this happens a low signal from IC29B pin 6 appears at IC30A pin 2 Q on IC30A goes high and via IC29A maintains a logic 1 signal upon pin 12 of IC30B thus by the end of one clock cycle a high is sent from pin 9 of IC30B to disable PCS Simultaneously a WAIT signal is generated for the second processor via IC19A amp B As soon as the WA IT signal HCS TP6 from the Z80 and e is removed the next risin as PCS is still low ae w FES E PCS REQUEST u d GER oY A A res PCS DISABLE 1 30 pia 6 HCS disables PCS until HCS completed Fig 4 Timing Diagram HCS PCS g clock edge removes a sent to the low signal is through IC30B Tube This is then maintained by the low signal upon pin 4 of IC30A until the PCS is complete Thus if PCS TP5 is already running it will continue despite an HCS but if HCS began first then PCS is prevent
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