Dataram 16GB DDR3-1600
Contents
1. PARAMETER Symbol Min Max Unit Internal read command to first data tan 13 125 20 ns CAS to CAS Command Delay teco 4 tok Clock High Level Width tcH avg 0 47 0 53 tex Clock Cycle Time tck 1 25 2 500 ns Clock Low Level Width tol avg 0 47 0 53 tex Data Input Hold Time after DQS Strobe ton 45 ps DQ Input Pulse Width toipw 360 ps DQS Output Access Time from Clock toasck 225 225 ps Write DQS High Level Width toos 0 45 0 55 tck avg Write DQS Low Level Width toasL 0 45 0 55 tck avg DQS Out Edge to Data Out Edge Skew toasa 100 ps Data Input Setup Time Before DQS Strobe tos 10 ps DQS Falling Edge from Clock Hold Time tosH 0 2 tck avg DQS Falling Edge to Clock Setup Time toss 0 2 tck avg Clock Half Period tup minimum of ten or ter ns Address and Command Hold Time after Clock tin 120 ps Address and Command Setup Time before Clock tis 45 ps Load Mode Command Cycle Time tmRD 4 tck DQ to DQS Hold taH 0 38 tck avg Active to Precharge Time tras 35 O tREFI ns Active to Active Auto Refresh Time tre 48 125 ns RAS to CAS Delay trep 13 125 ns Average Periodic Refresh Interval 0 C lt Tease lt 85 C tREFI 7 8 us Average Periodic Refresh Interval 0 C lt Tease lt 95 C tREFI 3 9 us Auto Refresh Row Cycle Time treo 260 ns Row Precharge Time tre 13 125 ns Read DQS Preamble Time tRPRE 0 9 Note 1 tck avg Read2. PARAMETER Symbol Minimum Maximum Unit Temperature non Operating TSTORAGE 55 100 C Ambient Temperature Operating Ta 0 70 C DRAM Case Temperature Operating Tcase 0 95 C Voltage on Vpp relative to Vss Vop 0 4 1 975 V Voltage on Any Pin relative to Vss Vin Vout 0 4 1 975 V Notes DRAM Operating Case Temperature above 85C requires 2X refresh Recommended DC Operating Conditions T O to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Typical Maximum Unit Note Power Supply Voltage Vop 1 425 1 5 1 575 V SPD EEPROM Voltage VDDSPD 3 0 3 3 3 6 V 1 0 Reference Voltage VrerDO 0 49 Voo 0 50 Vpop 0 51 Voo V 1 1 O Reference Voltage VREFCA 0 49 Von 0 50 Vpp 0 51 Vpop V 1 Notes 1 The value of Vrer is expected to equal one half Voo and to track variations in the Voo DC level Peak to peak noise on Vrer may not exceed 1 of its DC value DC Input Logic Levels Single Ended T 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Logical High Logic 1 ViH Dc Vier 0 1 Vpop V Logical Low Logic 0 ViL Dc Vss Vier 0 1 V AC Input Logic Levels Single Ended T O to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Logical High Logic 1 ViH ac Vrer 0 175 V Logical Low Logic 0 ViL ac Vrer 0 175 V A a A AA a A AA A y RA a E E Document 06325 Revision A 1 Apr 14
3. Dataram Corporation O 2014 Page 4 DP DATARAM Optimizing Value and Performance DTM64385E 16GB 240 Pin 2Rx4 Registered ECC DDR3 DIMM Differential Input Logic Levels T 0 to 70 C Voltage referenced to V 0 V PARAMETER Symbol Minimum Maximum Unit Differential Input Logic High ViH DIFF 0 200 DC Vpp AC Vpp 0 4 V Differential Input Logic Low VIL DIFF DC Vss AC Vss 0 4 0 200 V Differential Input Cross Point Voltage relative to VDD 2 Vix 207190 04150 v Capacitance T 25 C f 100 MHz PARAMETER Pin Symb Minimu Maximum Unit ol m Input Capacitance Clock CKO CKO Cck 1 5 2 5 pF Input Capacitance Address BA 2 0 A 15 0 RAS CAS WE Ci 1 5 2 5 pF Input Capacitance Control S 1 0 CKE 1 0 ODT 1 0 Ci 1 5 2 5 pF n DQ 63 0 CB 7 0 DQS 17 0 Input Output Capacitance DQS 17 0 Cio 3 5 pF DC Characteristics Ta 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Note Input Leakage Current li 18 18 pA 1 2 Any input 0 V lt VIN lt VDD Output Leakage Current loL 10 10 yA 2 3 OV lt VOUT lt VDDQ Notes 1 All other pins not under test 0 V 2 Values are shown per pin 3 DQ DQS DQS and ODT are disabled Document 06325 Revision A 1 Apr 14 Dataram Corporation 2014 Page 5 DTM64385E 16GB 240 Pin 2Rx4 Registered ECC DDR3 DIMM lbo Specifications and Conditio
4. DQS Postamble Time trest 0 3 Note 2 tck avg Row Active to Row Active Delay trRD Max 4nCK 6ns ns Internal Read to Precharge Command Delay trtp Max 4nCK 7 5ns ns Write DQS Preamble Setup Time twPRE 0 9 tck avg Write DQS Postamble Time twpsT 0 3 tck avg Write Recovery Time twr 15 ns Internal Write to Read Command Delay twTR Max 4nCK 7 5ns ns Notes 1 The maximum preamble is bound by tLZDQS min 2 The maximum postamble is bound by tHZDQS max Document 06325 Revision A 1 Apr 14 Dataram Corporation 2014 Page 7 yee DTM64385E 1668 240 Pin 2Rx4 Registered ECC DDR3 DIMM IN2IDATARAM Optimizing Value and Performance DATARAM CORPORATION USA Corporate Headquarters P O Box 7528 Princeton NJ 08543 7528 Voice 609 799 0071 Fax 609 799 6734 www dataram com All rights reserved The information contained in this document has been carefully checked and is believed to be reliable However Dataram assumes no responsibility for inaccuracies The information contained in this document does not convey any license under the copyrights patent rights or trademarks claimed and owned by Dataram No part of this publication may be copied or reproduced in any form or by any means or transferred to any third party without prior written consent of Dataram Document 06325 Revision A 1 Apr 14 Dataram Corporation 2014 Page 8
5. Vss 238 SDA NC No Connection 29 Vss 59 A4 89 Vss 119 SA2 149 DQ28 179 Voo 209 DQ44 239 Vss not used 30 DQ24 60 Vpp 90 DQ40 120 Vr 150 DQ29 180 A3 210 DQ45 240 Vz Document 06325 Revision A 1 Apr 14 Dataram Corporation 2014 Page 1 ry DTM64385E Optimizing Value and Performance 16GB 240 Pin 2Rx4 Registered ECC DDR3 DIMM Front view 133 35 i 5 250 I CO T ase 0 374 30 00 4 Tim 1 181 O A A I Ios 0 681 O ODA AAA AAAAAAOANANANAN N NANNAN i Y 5 00 5 175 47 00 0 204 die 1 850 D E a 123 00 a 4 843 g Back view Side view 3 94 Max 0 155 Max a y E 0 157 Min rm o O 1 27 10 ol 0 0500 0 0040 Notes Tolerances on all dime
6. DOS CS DM DQR 43 40 1 0 3 0 1 013 0 DQR 47 44 O 1 0 3 0 1 0 3 0 DQS6 IDQS15 O DQS6 pasi5 O ee Be EE IDOS DOS CS IDQS DAS CS DM IDOS DOS CS DM DQR 51 48 1 0 3 0 DQR 55 52 O 1 0 3 0 1 0 3 0 DQS7 IDQS16 O DQS7 DQS16 O Da It T T IDOS DOS CS IDQS DAS CS DM IDOS DOS CS DM DQR 59 56 1 0 3 0 1 0 3 0 DQR 63 60 O 1 0 3 0 1 0 3 0 All 15 OHMS TO SDRAMS DECOUPLING DQ 63 0 O AM O DARIE3 0 ai VppsppD _____ Serial PD 22 OHMS VoD CBI7 0 O VVy CBR 7 0 s0 m IRSO VREF Da DQS 17 0 O VW O_ DASR 17 0 Si Wr IRS Vv BA 2 0 wM BA 2 0 R SS IDQS 17 0 O WA O DQSR 17 0 A 15 0 WA A 15 0 R VREF_CA IRAS W IRASR CK1 Ve E All SDRAMs GLOBAL SDRAM CONNECTS tie he ltl El 120 skei wr 2 INER OHMS 36 OHMS Bate All 36 OHMS 0 wn a CKE 1 0 R LCLK t 0 LCLK 1 0 2 0 R Oo WV 0 A 15 0 R ODT 1 0 A Q ODT 1 0 R ICK1 RCLK 1 0 Oo RCLK 1 0 IRASR 03 ICASR PARIIN VW ERR_OUT INER aer BACH All 240 OHMS OHMS za All 36 OHMS ICKO IL R CLK 1 0 scL TEMPER UUDE aoe CKE 1 0 R IRESET US ODT 1 0 R MER De RS 1 0 TE SAO SA1 SA2 Document 06325 Revision A 1 Apr 14 Dataram Corporation 2014 Page 3 DP DATARAM Optimizing Value and Performance Absolute Maximum Ratings Note Operation at or above Absolute Maximum Ratings can adversely affect module reliability DTM64385E 16GB 240 Pin 2Rx4 Registered ECC DDR3 DIMM
7. ain signal integrity on the I O signals in a Fly by topology A thermal sensor accurately monitors the DIMM module and can prevent exceeding the maximum operating temperature of 95C Pin Description Front Side Back Side Name Function 1 Vreroo 31 DQ25 61 A2 91 DQ41 121 Vss 151 Vss 181 A1 211 Vss CB 7 0 Data Check Bits 2 Vss 32 Vss 62 Voo 92 Vss 122 DQ4 152 DQS12 182 Voo 212 DQS14 DQ 63 0 Data Bits 3 DQO 33 Das3 63 ck1 93 DQS5 123 DQ5 153 DQs1t2 183 Voo 213 DQS14 DQS 17 0 DQS 17 0 Differential Data Strobes 4 DQ1 34 Das3 64 ck1 94 DQS5 124 Vss 154 Vss 184 CKO 214 Vss CK 1 0 CK 1 0 Differential Clock Inputs 5 Vss 35 Vss 65 Von 95 Vss 125 DQs9 155 DQ30 185 CKO 215 DQ46 CKE 1 0 Clock Enables 6 DQSO 36 DQ26 66 Voo 96 Das2 i26 Dase 156 DQ31 186 Vop 216 DQ47 ICAS Column Address Strobe 7 paso 37 DQ27 67 Vrerca 97 DQ43 127 Vss 157 Vss 187 EVENT 217 Vss IRAS Row Address Strobe 8 Vss 38 Vss 68 Parin 98 Vss 128 DQ6 158 CB4 188 A0 218 DQ52 S 3 0 Chip Selects 9 DQ2 39 CBO 69 VDD es Da4s 129 Da7 159 CBS 189 Vop 219 DQ53 MWE Write Enable 10 DQ3 40 CB1 70 A10 AP 100 DQ49 130 Vss 160 Vss 190 BA1 220 Vss A 15 0 Address Inputs 11 Vss 41 Vss 71 BAO 101 Vss 131 DQ12 161 DQS17 191 Vpp 221 DQS15 BA 2 0 Bank Addresses 12 DQ8 42 DQS8 72 Vop 102 DQS6 132 DQ13 f162 DQS17 192 RAS 222 DQS15 ODT 1 0 On Die Termination Inputs 13 DQ9 l43 DQS8 73 WE 103 DQS6 133 Vss 163 Vss 193 SO 223 Vs
8. ns Ta 0 to 70 C Voltage referenced to Vss 0 V ds Max P PARAMETER Symbol Test Condition Value Unit Operating One Bank Active Ipp0 Operating current One bank ACTIVATE to PRECHARGE 1570 mA Precharge Current Operating One Bank Active Read lop1 epee One bank ACTIVATE to READ to 1740 mA Precharge Current Precharge Power PA Down Current lobo2P Precharge power down current Slow exit 896 mA Precharge Power aR Down Current Ipp2P Precharge power down current Fast exit 896 mA Precharge Standby mm Current Ipp2N Precharge standby current 1260 mA Active Power Down an Current lobo3P Active power down current 1070 mA Active Standby is E Current Ipp3N Active standby current 1070 mA Operating Burst x gt Write Current lpp4W Burst write operating current 2280 mA Operating Burst de Read Current Ibp4R Burst read operating current 2280 mA Burst Refresh me Current Ipp5B Refresh current 4410 mA Self Refresh re ano Current Ipp6 Self refresh temperature current MAX Tc 85 C 560 mA Operating Bank Interleave Read lop7 All bank interleaved read current 3370 mA Current One module rank in this operation the rest in IDD2N All module ranks in this operation Document 06325 Revision A 1 Apr 14 Dataram Corporation O 2014 Page 6 DTM64385E IN2DATARAM Optimizing Value and Performance AC Operating Conditions 16GB 240 Pin 2Rx4 Registered ECC DDR3 DIMM
9. nsions except where otherwise indicated are 13 005 All dimensions are expressed millimeters inches E AE TE VAN AA A EE AAA A Document 06325 Revision A 1 Apr 14 Dataram Corporation O 2014 Page 2 yy DTM64385E Optimizing Value and Performance 16GB 240 Pin 2Rx4 Registered ECC DDR3 DIMM All Devices All SDRAMs All Devices All SDRAMs EVENT SDA IRS1 RSO DQSO Daso Vss IDQS DQS CS DM DOS DOS DQS DAS CS DM IDOS DOS CS DM DQR 3 0 1 0 3 0 1 0 3 0 DQR 7 4 O 1 0 3 0 1 0 3 0 IDQS1 DQS10 O mM past DQS10 O bat It TY DQS DAS CS DM DOS DOS DQS DAS CS DM DOS DOS CS DM DQR 11 8 1 0 3 0 1 0 3 0 DQR 15 12 O 1 0 3 0 1 0 3 0 IDQS2 O IDQS11 O pas2 Dasi1 O DQS DAS CS DM IDOS DOS DQS DAS CS DM IDOS DOS DQR 19 16 1 0 3 0 DQR 23 20 O 1 0 3 0 1 0 3 0 DQS3 DQS12 O Das3 DQS12 O l DQS DAS CS DM IDOS DOS IDOS DOS CS DM DQR 27 24 1 0 3 0 1 0 3 0 DQR 31 28 O 1 0 3 0 DQS8 DQS17 O Pep pass DQS17 O IDQS DAS CS DM IDOS DOS IDQS DAS CS DM IDOS DOS CS DM CBR 3 0 1 0 3 0 1 0 3 0 CBR 7 4 O 1 0 3 0 1 0 3 0 DQS4 DQS13 O DQS4 DQS13 O Da L DQS DAS CS DM IDOS DOS DQS DAS CS DM IDOS DOS CS DM DQR 35 32 1 0 3 0 1 0 3 0 DQR 39 36 O 1 0 3 0 1 0 3 0 IDQS5 IDQS14 O Dass Dasi4 O DQS DAS CS DM IDOS DOS IDQS DAS CS DM IDOS
10. ryt DIM64385E MAA BH Optimizing Value and Performance ry 16GB 240 Pin 2Rx4 Registered ECC DDR3 DIMM Features 240 pin JEDEC compliant DIMM 133 35 mm wide by 30 mm high Operating Voltage 1 5V 0 075 I O Type SSTL_15 On board IC temperature sensor with integrated Serial Presence Detect SPD EEPROM Data Transfer Rate 12 8 Gigabytes sec Data Bursts 8 and burst chop 4 mode ZQ Calibration for Output Driver and On Die Termination ODT Programmable ODT Dynamic ODT during Writes Programmable CAS Latency 6 7 8 9 10 and 11 Bi directional Differential Data Strobe signals SDRAM Addressing Row Col Bank 16 1 1 3 Fully ROHS Compliant Pin Configuration Identification DTM64385E 1Gx72 16GB 2Rx4 PC3 12800R 11 11 E2 Performance range Clock Module Speed CL trep trp 800 MHz PC3 12800 11 11 11 667 MHz PC3 10600 10 10 10 667 MHz PC3 10600 9 9 9 533 MHz PC3 8500 8 8 8 533 MHz PC3 8500 7 7 7 400 MHz PC3 6400 6 6 6 Description DTM64385E is a registered 2Gx72 memory module which conforms to JEDEC s DDR3 PC3 12800 standard The assembly is Dual Rank Each Rank is comprised of eighteen Samsung 1Gx4 DDR3 1600 SDRAMs One 2K bit EEPROM is used for Serial Presence Detect and a combination register PLL with Address and Command Parity is also used Both output driver strength and input termination impedance are programmable to maint
11. s SA 2 0 SPD Address 14 Vos 44 Vss 74 CAS 104 Vss 134 DQS10 164 CB6 194 Vop 224 DQ54 SCL SPD Clock Input 15 DQS1 45 CB2 75 Voo 105 DQ50 135 DQS10 165 CB7 195 ODTO 225 DQ55 SDA SPD Data Input Output 16 DQS1 46 CB3 76 S1 106 DQ51 136 Vss 166 Vss 196 A13 226 Vss EVENT Temperature Sensing 17 Vss 47 Vss 77 ODT1 107 Vss 137 DQ14 167 NC TEST 197 Vpp 227 DQ60 IRESET Reset for register and DRAMs 18 DQ10 48 Vr 78 Voo 108 DQ56 138 DQ15 f168 RESET 198 S3 NC 228 DQ61 PAR_IN Parity bit for Addr Ctrl 19 DQ11 49 Vr 79 S2 NC 109 DQ57 139 Vss 169 CKE1 199 Vss 229 Vss ERR_OUT Error bit for Parity Error 20 Vss 50 CKEO 80 Vss 110 Vss 140 DQ20 170 Voo 200 DQ36 230 DQS16 A12 BC Combination input Addr12 Burst Chop 21 DQ16 51 Voo 81 Da32 111 Das7 141 DQ21 171 A15 201 DQ37 231 DQS16 A10 AP Combination input Addr10 Auto precharge 22 DQ17 52 BA2 82 DQ33 112 DQs7 142 Vss 172 A14 202 Vss 232 Vss Vss Ground 23 Vss 53 Err_Our 83 Vss 113 Vss 143 DQS11 173 Voo 203 DQS13 233 DQ62 Voo Power 24 IDQS2 54 Vpp 84 DQs4 114 DQ58 144 DQS11 174 A12 BC 204 DQS13 234 DQ63 Vons o SPD EEPROM Power 25 DQS2 55 A11 85 DQS4 115 DQ59 145 Vss 175 A9 205 Vss 235 Vss Vrerpa Reference Voltage for DQ s 26 Vss 56 AT 86 Vss 116 Vss 146 DQ22 176 Voo 206 DQ38 236 Voosep VREFCA Reference Voltage for CA 27 DQ18 57 Voo 87 DQ34 117 SAO 147 DQ23 177 A8 207 DQ39 237 SA1 Var Termination Voltage 28 DQ19 58 A5 88 DQ35 118 SCL 148 Vss 178 A6 208
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