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Intel Xeon E3-1105C

1. VID7 VID6 VID5 VID4 VID3 VID2 VID1 VIDO HEX Vcc 0 0 1 1 0 0 0 0 3 0 0 48500 0 0 1 1 0 0 0 1 3 1 0 49000 0 0 1 1 0 0 1 0 3 2 0 49500 0 0 1 1 0 0 1 1 3 3 0 50000 0 0 1 1 0 1 0 0 4 0 50500 0 0 1 1 0 1 0 1 3 5 0 51000 0 0 1 1 0 1 1 0 3 6 0 51500 0 0 1 1 0 1 1 1 3 7 0 52000 0 0 1 1 1 0 0 0 3 8 0 52500 0 0 1 1 1 0 0 1 3 9 0 53000 0 0 1 1 1 0 1 0 3 A 0 53500 0 0 1 1 1 0 1 1 3 B 0 54000 0 0 1 1 1 1 0 0 0 54500 0 0 1 1 1 1 0 1 3 D 0 55000 0 0 1 1 1 1 1 0 3 E 0 55500 0 0 1 1 1 1 1 1 3 F 0 56000 0 1 0 0 0 0 0 0 4 0 0 56500 0 1 0 0 0 0 0 1 4 1 0 57000 0 1 0 0 0 0 1 0 4 2 0 57500 0 1 0 0 0 0 1 1 4 3 0 58000 0 1 0 0 0 1 0 0 4 4 0 58500 0 1 0 0 0 1 0 1 4 5 0 59000 0 1 0 0 0 1 1 0 4 6 0 59500 0 1 0 0 0 1 1 1 4 7 0 60000 0 1 0 0 1 0 0 0 4 8 0 60500 0 1 0 0 1 0 0 1 4 9 0 61000 0 1 0 0 1 0 1 0 4 0 61500 0 1 0 0 1 0 1 1 4 0 62000 0 1 0 0 1 1 0 0 4 C 0 62500 0 I 0 0 1 1 0 1 4 D 0 63000 0 1 0 0 1 1 1 0 4 E 0 63500 0 1 0 0 1 1 1 1 4 0 64000 0 1 0 1 0 0 0 0 5 0 0 64500 0 1 0 1 0 0 0 1 5 1 0 65000 0 1 0 1 0 0 1 0 5 2 0 65500 0 1 0 1 0 0 1 1 5 3 0 66000 0 1 0 1 0 1 0 0 514 0 66500 0 1 0 1 0 1 0 1 5 5 0 67000 0 1 0 1 0 1 1 0 5 6 0 67500 0 1 0 1 0 1 1 1 5 7 0 68000 Intel Xeon and Intel Core Processors Communications Infrastructure Datasheet Volume 1 of 2 84
2. Raw DIMM DRAMDevice DRAM tor Bitysical Tor Row ale DRAM Col Address Page Size Version apacity Technology Organization Devices Device Bits Inside Ranks DRAM Unbuffered Non ECC Supported DIMM Module Configurations 1 GB 1 Gb 128 M X8 8 2 14 10 8 8K A 2 GB 2 Gb 128 M X 16 16 2 14 10 8 16 K 2 GB 1 Gb 128MX8 16 2 14 10 8 8K B 4 GB 2 Gb 256MX8 16 2 15 10 8 8K 8 GB 4Gb 512MX8 16 2 16 10 8 8K 512 MB 1 Gb 64 16 4 1 13 10 8 16 1 2 Gb 128 16 4 1 14 10 8 16 Unbuffered ECC Supported DIMM Module Configurations 1 GB 1 Gb 3 128MX8 9 1 14 10 8 8K D 2 GB 2 Gb 3 256MX8 9 1 15 10 8 8K 2 GB 1 Gb 128MX8 18 2 14 10 8 8K E 4 GB 2 Gb 256M X8 18 2 15 10 8 8K 8 GB 4 Gb 512M X8 18 2 16 10 8 8K Notes 1 DIMM module support is based on availability and is subject to change 2 Interface does not support DDR3L DDR3U DIMMs 3 Supported but not fully validated Intel Xeon and Intel Core Processors For Communications Infrastructure Datasheet Volume 1 of 2 May 2012 24 Document Number 327405 001 Interfaces i n t el 3 1 1 2 SO DIMM Configurations The processor supports SO DIMM and SO DIMM designs Table 3 2 details the SO DIMM modules that are supported However these have not been fully validated Table 3 2 Supported SO DIMM Module Configurations 2
3. Figure 9 6 DDR3 Receiver Eye Mask I Figure 9 7 DDR3 Clock to DQS Skew Timing Waveform CK IMC CK IMC TskEw_ck pos Tskew_ck Das DGS IMC 0 5 Intel Xeon and Intel Core Processors For Communications Infrastructure Datasheet Volume 1 of 2 May 2012 112 Document Number 327405 001 Electrical Specifications n tel Figure 9 8 Figure 9 9 May 2012 PCI Express Receiver Eye Margins LN I g 0 20 40 60 80 100 120 140 160 180 200 Time ps TAP Valid Delay Timing Waveform TCK Tx T17 TDO Clock to Output Delay Ts T15 TDI TMS Setup Time Th T16 TDI TMS Hold Time V 0 5 Note See Table 9 11 for TAP Signal Group DC specifications and Table 9 23 for TAP Signal Group specifications Intel Xeon and Intel Core Processors For Communications Infrastructure Datasheet Volume 1 of 2 Document Number 327405 001 113 n tel Electrical Specifications Figure 9 10 Figure 9 11 9 13 Test Reset TRST Async Input and PROCHOT Timing Waveform Tq T1 CMOS Pulse Width _ PROCHOT Pulse Width T18 TRST Pulse Width THERMTRI P Power Down Sequence THERMTRIPE LTT Vcc 5 THERMTRIP assertion until Voc removal Signal Quality Data transfer requires the clean recep
4. Intel Xeon and Intel Core Processors For Communications Infrastructure May 2012 Datasheet Volume 1 of 2 Document Number 327405 001 85 intel Table 9 1 IMVP7 Voltage Identification Definition Sheet 5 of 8 Electrical Specifications VID7 VID6 VID5 VID4 VID3 VID2 VID1 VIDO HEX Vcc 1 0 0 0 0 0 0 0 8 0 0 88500 1 0 0 0 0 0 0 1 8 1 0 89000 1 0 0 0 0 0 1 0 8 2 0 89500 1 0 0 0 0 0 1 1 8 3 0 90000 1 0 0 0 0 1 0 0 8 4 0 90500 1 0 0 0 0 1 0 1 8 5 0 91000 1 0 0 0 0 1 1 0 8 6 0 91500 1 0 0 0 0 1 1 1 8 7 0 92000 1 0 0 0 1 0 0 0 818 0 92500 1 0 0 0 1 0 0 1 8 9 0 93000 1 0 0 0 1 0 1 0 8 0 93500 1 0 0 0 1 0 1 1 8 0 94000 1 0 0 0 1 1 0 0 8 C 0 94500 1 0 0 0 1 1 0 1 8 D 0 95000 1 0 0 0 1 1 1 0 8 0 95500 1 0 0 0 1 1 1 1 8 0 96000 1 0 0 1 0 0 0 0 9 0 0 96500 1 0 0 1 0 0 0 1 9 1 0 97000 1 0 0 1 0 0 1 0 9 2 0 97500 1 0 0 1 0 0 1 1 9 3 0 98000 1 0 0 1 0 1 0 0 9 4 0 98500 0 0 1 0 1 0 1 9 5 0 99000 1 0 0 1 0 1 1 0 9 6 0 99500 1 0 0 1 0 1 1 1 9 7 1 00000 1 0 0 1 1 0 0 0 9 8 1 00500 1 0 0 1 1 0 0 1 9 9 1 01000 1 0 0 1 1 0 1 0 9 A 1 01500 1 0 0 1 1 0 1 1 9 1 02000 1 0 0 1 1 1 0 0 9 C 1 02500 1 0 0 1 1 1 0 1 9 D 1 03000 1 0 0 1 1 1 1 0 9 E 1 03500 1 0 0 1 1 1 1 1 9 1 04000 1 0 1 0 0 0 0 0 0 1 04500 1 0 1 0 0 0 0 1 A 1 1 05000 1 0 1 0 0 0
5. enne nnns 71 8 2 Memory Reference and 74 8 3 Reset and Miscellaneous 5 mmm mme 74 8 4 PCI Express Based Interface 5 9 5 75 8 amp 5 75 8 0 76 98 7 TAP Signals 76 8 8 Error and Thermal eee eee ee ee eee este eee ens 77 8 9 Power SEQuencGing RR EA Go 78 8 10 Processor Power and Ground Signals mnes 78 8 1 SENSE PINS 79 8 12 Future Compatibility xr pe Panama 79 8 13 Processor Internal Pull Up Pull 79 May 2012 Intel Xeon and Intel Core Processors For Communications Infrastructure Datasheet Volume 1 of 2 Document Number 327405 001 5 gt 9 0 Electrical Specifications 81 Power and Ground Pins u nx EE Do e iR Rote 81 Decoupling Guldellfnes reor rri rr Dre eere ESEI EEES edP E HE EE upaku 81 9 2 1 Voltage Rail Deco
6. Table 3 3 Supported Memory Down Configurations 1 Raw Card Memory DRAM of Pina Kos edi Equivalent Capacity Technology Organization Device Address Inside Page Size Ranks Bits DRAM Unbuffered Non ECC Supported Memory Down Configurations 1 GB 1 Gb 64 M X 16 8 2 13 10 8 8K E 2 GB 2 Gb 128 M X 16 8 2 14 10 8 8K 1 GB 1 Gb 128MX8 8 1 14 10 8 8K 2GB 2 Gb 256M X8 8 1 15 10 8 8K 512 MB 1 Gb 64 M X 16 4 1 13 10 8 8K 1 GB 2 Gb 2 128 M X 16 4 1 14 10 8 8K 2 GB 1 Gb 2 128M X8 16 2 14 10 8 8K F 4 GB 2 Gb 256M X8 16 2 15 10 8 8K 8 GB 4 Gb 512MX8 16 2 16 10 8 8K Unbuffered ECC Supported Memory Down Configurations 1 GB 1 Gb 2 128M X8 9 1 14 10 8 8K 2 GB 2 Gb 256M X8 9 1 15 10 8 8K 2 GB 1 Gb 128MX8 18 2 14 10 8 8K E 4 GB 2 Gb 256M X8 18 2 15 10 8 8K 8 GB 4 Gb 512MX8 18 2 16 10 8 8K Notes 1 Interface does not support memory devices running at DDR3L 1 35 V DDR3U 1 25 V Voltage Levels 2 Supported but not fully validated 3 1 2 System Memory Timing Support The processor supports the following DDR3 Speed Bin CAS Write Latency CWL and command signal mode timings on the main memory interface tCL CAS Latency tRCD Activate Command to READ or WRITE Command delay PRECHARGE Command Period CWL CAS Write Latency Command Signal modes 1n indicates a new command may be issued every clock and 2n indicates a new command may be issued every 2 clocks Command la
7. Raw of of of of Pn s Bits DRAM Unbuffered Non ECC Supported SO DIMM Module Configurations 1 GB 1 Gb 3 4 64 M X 16 8 2 13 10 8 8K i 2 GB 2 Gb 3 4 128 16 8 2 14 10 8 8K 1 GB 1 Gb 3 4 128M X8 8 1 14 10 8 8K 2GB 2 Gb 3 4 256MX8 8 1 15 10 8 8K 512 MB 1 Gb 3 4 64 M X 16 4 1 13 10 8 8 K x 1 GB 2 Gb 3 4 128 MX 16 4 1 14 10 8 8K 2 GB 1 Gb 3 4 128M X8 16 2 14 10 8 8 K F 4 2 Gb 3 4 256 8 16 2 15 10 8 8K 8 GB 4 Gb 3 4 512MX8 16 2 16 10 8 8K Unbuffered ECC Supported SO DI MM Module Configurations 1 GB 1 Gb 3 128M X8 9 1 14 10 8 8K 2 GB 2 Gb 3 256 8 9 1 15 10 8 8K 2 GB 1663 128MX8 18 2 14 10 8 8K E 4 GB 2 Gb 3 256MX8 18 2 15 10 8 8K 8 GB 4 Gb 3 512MX8 18 2 16 10 8 8K Notes DIMM module support is based on availability and is subject to change Interface does not support DDR3L nor DDR3U SO DIMMs Supported but not fully validated on Intel Xeon and Intel Core Processors for Communications Infrastructure Fully Validated on 2nd Generation Intel Core Processor Family Mobile processors Intel Xeon and Intel Core Processors For Communications Infrastructure May 2012 Datasheet Volume 1 of 2 Document Number 327405 001 25 l n tel Interfaces 3 1 1 3 Memory Down Configurations The processor supports the following Memory Down configurations
8. eren 21 2 7 Package 21 2 9 Testability aaa usah shahih ba 21 3 0 Interfaces 23 3 4 System Memory Interface uu uay a re nex RR XX 23 3 1 1 System Memory Configurations 23 3 1 2 System Memory Timing r rr 26 3 1 3 System Memory Organization Modes rr rr 27 3 1 4 Rules for Populating Memory Slots r rr 28 3 1 5 Technology Enhancements of Intel Fast Memory Access Intel FMA 28 3 1 6 D ta Scrambliligr 29 3 1 7 DRAM Clock Generation m emen RTE 29 3 2 PCLEXpresSs Interface triere Sa 29 3 2 1 PCI EXpress Architecture eroe tirer eese ern reve Yi Dn 30 3 2 2 PCI Express Configuration Mechanism rr 32 3 233 PCI Express Port bre Ru ee AE e sd cn 32 3 2 4 PCI Express Lanes Connection memes 34 3 2 5 Configuring PCle Lanes ehe three kk tele rk Rx X sk RE 35 3 2 6 Lane Reversal on PCle mme 36 33 Direct Media Interface 36 3 3 DMI Error ceteri steeds Ex reda Da pet
9. 55 SB_BS 2 SB ECC CB 7 SB MA 15 3 SB SB DIM SA DIM M VREF M VREF DQ D SA DQ S 8 55 _ 3 vss vss SA_ECC SA_ECC SA_ECC SA_ECC _CB 3 CB 2 _CBI7 _CBI6 55 VSS SM_DR AMRST P EF 55 55 5 _ EF vss 55 3 11 SB MA 6 SB 8 2 14 SA CKE SA MA SA BS 2 _ _ _ 5 12 1 0 14 10 11 12 13 14 15 16 17 18 2012 Document Number 327405 001 Intel Xeon and Intel Core Processors For Communications Infrastructure Datasheet Volume 1 of 2 143 intel Processor Ball and Package Information Figure 10 3 Ball Map Bottom View Lower Left Side VSS BPM 4 VSS VSS 5 1 RSVD_2 VSS BPM 2 VSS BPM 3 VSS 6 1 RSVD 4 VSS BPM 7 RSVD_4 VSS VIDSOU T RSVD_1 RSVD_4 55 2 Wy 1 0 237 1 NC PROC_D ETECT My RSVD 1 3 VSS RSVD_3 3 RSVD_5 4 RSVD_1 2 VSS RSVD_5 3 VSS RSVD_2 8 RSVD_5 2 VSS vss RSVD_2 9 RSVD 2 7 RSVD_2 i vss RSVD_2 6 RSVD_2 RSVD_4 RSVD_4 4 TCK VSS
10. Intel Xeon and Intel Core Processors For Communications Infrastructure Datasheet Volume 1 of 2 162 Processor Configuration Registers May 2012 Document Number 327405 001 Processor Configuration Registers n tel Table 11 13 Error Syndrome ERRSYND Sheet 3 of 3 ERRSYND Bit Locator Locator 0x62 38 DQ38 0x64 54 DQ54 0x68 5 DQ5 0x70 52 DQ52 0x80 71 CB7 0x83 22 DQ22 0x85 58 DQ58 0x86 13 DQ13 0x89 28 DQ28 0x8A 41 DQ41 0x8C 48 DQ48 Ox8F 43 DQ43 0x91 37 DQ37 0x92 53 DQ53 0x94 4 004 0 98 20 20920 OxA1 49 DQ49 OxA2 1 201 0 4 17 2017 0xA8 33 DQ33 OxBO 44 DQ44 OxC1 8 008 0 2 24 2024 0 4 40 20940 0xC8 56 DQ56 0xD0 19 DQ19 OxEO 11 DQ11 OxF1 7 207 OxF2 31 DQ31 OxF4 59 DQ59 OxF8 35 DQ35 OxFF Error due to All Other Unrecoverable Multi bit Values errors 88 Intel Xeon and Intel Core Processors For Communications Infrastructure May 2012 Datasheet Volume 1 of 2 Document Number 327405 001 163 n tel Processor Configuration Registers Intel Xeon and Intel Core Processors For Communications Infrastructure Datasheet Volume 1 of 2 May 2012 164 Document Number 327405 001
11. 36 3 3 2 Processor PCH Compatibility 36 3 83 38 DMI HNK DOWN ous auqa eer ter coeur a4 36 3 4 Platform Environment Control Interface rr 37 3 5 Interface ClOCKING eio tities rm eed einai lin Pos es 37 3 5 1 Internal Clocking Requirements r rr meme mene 37 4 0 Technologies encreire o A aO EON EEN RRE o Erini 39 4 1 Intel Virtualization Technology 39 4 1 1 Intel VT x Objectives 39 4 1 2 Intel VI x PaStUF BS cxtnceccccscnicccanssdsetanntinddsmaiancanSegndunteds seseasdncixtadscbantandd 39 4 1 3 Intel VT d Objectives Rae Ya aded 40 Intel Xeon and Intel Core Processors For Communications Infrastructure Datasheet Volume 1 of 2 May 2012 4 Document Number 327405 001 Contents AACA Intel 40 4 1 5 Intel VT d Features Not Supported tenencia three tm ect ain 41 4 2 Intel Hyper Threading Technology 41 4 3 Intel Advanced Vector Extensions Intel AVX ccccccececeecececececeesceseeeeeeeeeaaeees 41 4 4 Intel Advanced Encryption Standard New Instructions Intel AES NI 42 4 4 1 PCLMULQDO Instruction ccc ccc cece HH eme emen enn nnn 42 4 5 Intel 64 Architecture X2APIC
12. CAS Write Latency is the delay in clock cycles between the rising edge of CK where a write command is 5 referenced the first rising strobe edge where the first byte of write data is present The Cw value is determined by the value of the CL CAS Latency setting 6 The system memory clock outputs are differential CLK and CLK the CLK rising edge is referenced at the crossing point where CLK is rising and CLK is falling The system memory strobe outputs are differential DQS and DQS the DQS rising edge is referenced at the 7 crossing point where DQS is rising and DQS is falling and the DQS falling edge is referenced at the crossing point where DQS is falling and DQS is rising 8 This value specifies the parameter after write levelling representing the residual error in the controller after training and does not include any effects from the DRAM itself Intel Xeon and Intel Core Processors For Communications Infrastructure May 2012 Datasheet Volume 1 of 2 Document Number 327405 001 103 intel Electrical Specifications Table 9 18 DDR3 Electrical Characteristics and AC Timings at 1066 MT s Vppo 1 5 V x0 075 V Channel A Symbol Parameter channels Unit Figure Note 9 Max Min System Memory Latency Timings CAS Latency RAS to CAS Delay Pre charge 7 7 7 T Trp Command Period 8 8 Electrical
13. 53 6 3 IMC Power iiec en neu nonien titers 57 6 3 1 Disabling Unused System Memory 57 6 3 2 DRAM Power Management and 57 6 4 PCle Power nenne nna nenne nena nennen nnn 59 6 5 DMI Power eene 59 6 6 Thermal Power sis senes 59 7 0 Thermal Management u 61 7 1 Thermal Design Power and Junction Temperature eterne 61 7 2 Thermal and Power 5 cece cece enna memes 61 7 3 Thermal Management Features 63 7 3 1 Processor Package Thermal Features r rr 63 7 3 2 Processor Core Specific Thermal Features sss nnn 68 7 3 3 Memory Controller Specific Thermal 68 7 3 4 Platform Environment Control Interface 69 8 0 Signal Description soon en ee ced Re da e e ERE YR LE D 71 8 1 System Memory 1
14. Dynamic power down 2 5 4 PCI Express 105 and L1 ASPM power management capability 2 5 5 DMI 105 and L1 ASPM power management capability 2 6 Thermal Management Support Digital Thermal Sensor Intel Adaptive Thermal Monitor THERMTRI and PROCHOT support On Demand Mode Memory Thermal Throttling External Thermal Sensor TS on DIMM and TS on Board Fan speed control with DTS 2 7 Package The processor is available in one package size A 37 5 x 37 5 mm 1284 ball FCBGA package BGA1284 1 016 mm ball pitch 2 8 Testability The processor includes boundary scan for board and system level testability 88 Intel Xeon and Intel Core Processors For Communications Infrastructure May 2012 Datasheet Volume 1 of 2 Document Number 327405 001 21 n tel Product Overview Intel Xeon and Intel Core Processors For Communications Infrastructure Datasheet Volume 1 of 2 May 2012 22 Document Number 327405 001 Interfaces 3 0 3 1 3 1 1 Note Note May 2012 Interfaces This chapter describes the interfaces supported by the processor System Memory Interface System Memory Configurations Supported The Integrated Memory Controller IMC of the processor supports DDR3 protocols with two independent 72 bit wide channels These two memory channels are capable of running speeds up to 1600MT s Each channel consists of 64 data and 8 ECC bits In the dual channel c
15. VSS SENSE voltage and ground They can be used to sense or Analog B measure voltage near the silicon VCCIO SENSE and VSS SENSE VCCIO provide an VCCIO SENSE isolated low impedance connection to the VSS SENSE processor VCCIO voltage and ground They can be Analog used sense measure voltage near silicon VCCSA_VCCSENCE and VCCSA_VSSSENCE provide VCCSA_VCCSENCE an isolated low impedance connection to the VCCSA VSSSENCE processor system agent voltage It can be used to Analog sense measure voltage near the silicon 8 12 Future Compatibility See the appropriate Platform Design Guide for implementation details Table 8 14 Future Compatibility Direction Signal Name Description Buffer Type This pin is for compatibility with future platforms PROC SELECT A pull up resistor to Vcp is required if connected to the DF TVS strap on the PCH Memory Channel A B DIMM DQ Voltage Reference SA DIMM VREFDQ See the appropriate Platform Design Guide for T implementation details These signals used by SB_DIMM_VREFDQ the processor and are for future compatibility only No connection is required Voltage selection for VCCIO This pin must be pulled VCCIO_SEL high on the motherboard when using a dual rail voltage regulator which will be used for future compatibility VCCSA VID 0 Voltage selection for VCCSA his pin must have a pull down resistor to ground 8 13 Processor Internal Pull Up
16. bifurcated When bifurcated the wires which had previously been assigned to lanes 15 8 of the single x16 primary port are reassigned to lanes 7 0 of the x8 secondary controller Function 1 This assignment applies whether the lane numbering is reversed or not Further bifurcation of Port 1 is possible through the third contoller Function 2 to create two x4 PCI Express PCI Express Port Bifurcation When Port 1 is not bifurcated Function 1 and Function 2 are hidden from the discovery mechanism used in PCI enumeration The controls for Port 2 and the associated virtual PCI to PCI bridge can be found in PCI Device 6 which provides an additional x4 Port Intel Xeon and Intel Core Processors For Communications Infrastructure Datasheet Volume 1 of 2 32 May 2012 Document Number 327405 001 Interfaces Figure 3 5 PCI Express PCI Port Bifurcation intel Port 1 PCle Transaction Physical X8 X4 X4 l 1 X8 X8 Port 1a Port 1b X16 Port 1 Port 2 Transaction Physical X4 Port 2 Intel Xeon and Intel Core Processors For Communications Infrastructure May 2012 Document Number 327405 001 Datasheet Volume 1 of 2 33 l n tel Interfaces 3 2 4 PCI Express Lanes Connection Figure 3 6 demonstrates the PCle lanes mapping Figure 3 6 PCle Typical Operation 16 Lanes Mapping BE Ep E
17. Fore Une tes Tere oa Fer 42 5 0 Processor oor ee eae xe RR RR 45 5 MOVGNRVICW ECL rE EEEE EERO RINER 45 5 1 1 SK EGaEUE GS Cu gore seite pe eur ROSE Dd eina n Rr tJ E sa ORO E e Ra ul cn sy NR N 45 6 0 Power Management ooo eb RD ES TA 47 6 1 ACPI States Supported teer oer mata ex Ei EXE 48 6 1 1 System 48 6 1 2 Processor Core Package Idle 48 6 1 3 Integrated Memory Controller States 48 0 1 4 PCle Link States 2 a 49 0 1 5 DMI States isse carrot Ern dra er abr aco aut qaqaqa aqha 49 6 1 6 Interface State 49 6 2 Processor Core Power ener een 49 6 2 1 Enhanced Intel SpeedStep Technology 50 6 2 2 Low Power Idle States eda eene sek EE NENN diets aso ree ats 50 6 2 3 Requesting Low Power Idle States rr 51 6 2 4 Core C SEates dirimere nqa akiwa KR A REERE UC RATE 52 6 2 5 Package C States ru anu n de RENE EN M
18. May 2012 Document Number 327405 001 Electrical Specifications n tel Table 9 1 IMVP7 Voltage Identification Definition Sheet 4 of 8 VID7 VID6 VID5 VID4 VID3 VID2 VID1 VIDO HEX Vcc 0 1 0 1 1 0 0 0 5 8 0 68500 0 1 0 1 1 0 0 1 5 9 0 69000 0 1 0 1 1 0 1 0 5 A 0 69500 0 1 0 1 1 0 1 1 5 B 0 70000 0 1 0 1 1 1 0 0 5 0 70500 0 1 0 1 1 1 0 1 5 D 0 71000 0 1 0 1 1 1 1 0 5 E 0 71500 0 1 0 1 1 1 1 1 5 F 0 72000 0 1 1 0 0 0 0 0 6 0 0 72500 0 1 1 0 0 0 0 1 6 1 0 73000 0 1 1 0 0 0 1 0 6 2 0 73500 0 1 1 0 0 0 1 1 6 3 0 74000 0 1 1 0 0 1 0 0 6 4 0 74500 0 1 1 0 0 1 0 1 6 5 0 75000 0 1 1 0 0 1 1 0 6 6 0 75500 0 1 1 0 0 1 1 1 6 7 0 76000 0 1 1 0 1 0 0 0 6 8 0 76500 0 1 1 0 1 0 0 1 6 9 0 77000 0 1 1 0 1 0 1 0 6 0 77500 0 1 1 0 1 0 1 1 6 0 78000 0 1 1 0 1 1 0 0 6 C 0 78500 0 1 T 0 1 1 0 1 6 D 0 79000 0 1 1 0 1 1 1 0 6 0 79500 0 1 1 0 1 1 1 1 6 0 80000 0 1 1 1 0 0 0 0 7 0 0 80500 0 1 1 1 0 0 0 1 7 1 0 81000 0 1 1 1 0 0 1 0 7 2 0 81500 0 1 1 1 0 0 1 1 7 3 0 82000 0 1 1 1 0 1 0 0 7 4 0 82500 0 1 1 1 0 1 0 1 7 5 0 83000 0 1 1 1 0 1 1 0 7 6 0 83500 0 1 1 1 0 1 1 1 7 7 0 84000 0 1 1 1 1 0 0 0 7 8 0 84500 0 1 1 1 1 0 0 1 7 9 0 85000 0 1 1 1 1 0 1 0 7 0 85500 0 1 1 1 1 0 1 1 7 0 86000 0 1 1 1 1 1 0 0 7 0 86500 0 1 1 1 1 1 0 1 7 D 0 87000 0 1 1 1 1 1 1 0 7 E 0 87500 0 1 1 1 1 1 1 1 7 F 0 88000
19. 100 MHz Processor Memory PCI e DMI 88 Intel Xeon and Intel Core Processors For Communications Infrastructure May 2012 Document Number 327405 001 Datasheet Volume 1 of 2 37 n tel Interfaces Intel Xeon and Intel Core Processors For Communications Infrastructure Datasheet Volume 1 of 2 May 2012 38 Document Number 327405 001 Technologies 4 0 4 1 4 1 1 4 1 2 May 2012 Technologies Intel Virtualization Technology Intel Virtualization Technology Intel VT makes a single system appear as multiple independent systems to software This allows multiple independent operating systems to run simultaneously on a single system Intel VT comprises technology components to support virtualization of platforms based on Intel architecture microprocessors and chipsets Intel Virtualization Technology Intel VT for IA 32 Intel 64 and Intel Architecture Intel VT x added hardware support in the processor to improve the virtualization performance and robustness Intel Virtualization Technology for Directed 1 0 Intel VT d adds chipset hardware implementation to support and improve I O virtualization performance and robustness Intel VT x specifications and functional descriptions are included in the Intel 64 and 1 32 Architectures Software Developer s Manual Volume and is available at http www intel com products processor manuals index htm The Intel
20. 2 Step current is done in 100nS 3 di dt values are for platform testing only This parameter is not tested on Intel silicon Testing should go up to and include 1 Table 9 9 Processor PLL VccpLL Supply DC Voltage and Current Specifications Symbol Parameter Min Typ Max Unit Note VccPLL PLL supply voltage DC AC 18 v specification TOLccPLL VccpLL Tolerance AC DC 5 I CCMAX VCCPLL Max Current for VccPLL Rail 1 2 A Iccrpc vccPLL Thermal Design Current TDC for _ 1 2 3 VccpLL Rail Note Long term reliability cannot be assured in conditions above or below Max Min functional limits Table 9 10 DDR3 Signal Group DC Specifications Sheet 1 of 2 Symbol Parameter Min Typ Max Units Notes1 ViL Input Low Voltage SM VREF 0 1 V 2 4 10 Vin Input High Voltage SM_VREF 0 1 V 3 10 Vi Input Low Voltage Vppo 0 55 V 9 SM DRAMPWROK 0 1 Input High Voltage V Vppo 0 55 0 1 V 9 IH SM DRAMPWROK 009 2 Ron VoL Output Low Voltage RoN R EnM 6 i Vppo Vppo 2 Output High Voltage Row Ros RTERM V 4 6 DDR3 Data Buffer pull u RoN UP DO Resistance PH Sup 23 3 28 2 32 9 Q 5 DDR3 Data Buffer pull down Resistance 21 4 26 8 34 3 Q 5 R DDR3 On die termination equivalent 83 100 117 ODT DQ resistance for data signals 41 5 50 65 DDR3 On die termination DC working point driver set to receive 0 43 Vcc 0 5 Vcc 0 56 Vcc V mode DDR3 Clock Buffer pull u Row uP CK
21. 3 1 5 1 3 1 5 2 3 1 5 3 3 1 5 4 3 1 6 3 1 7 3 2 2012 intel The memory controller has an advanced command scheduler where all pending requests are examined simultaneously to determine the most efficient request to be issued next The most efficient request is picked from all pending requests and issued to system memory Just in Time to make optimal use of Command Overlapping Thus instead of having all memory access requests go individually through an arbitration mechanism forcing requests to be executed one at a time they can be started without interfering with the current request allowing for concurrent issuing of requests This allows for optimized bandwidth and reduced latency while maintaining appropriate command spacing to meet system memory protocol Just in Time Command Scheduling Command Overlap Command Overlap allows the insertion of the DRAM commands between the Activate Precharge and Read Write commands normally used as long as the inserted commands do not affect the currently executing command Multiple commands can be issued in an overlapping manner increasing the efficiency of system memory protocol Out of Order Scheduling While leveraging the Just in Time Scheduling and Command Overlap enhancements the IMC continuously monitors pending requests to system memory for the best use of bandwidth and reduction of latency If there are multiple requests to the same open page these requests wou
22. PCI Express 1 x16 port is mapped to PCI Device 1 One 16 lane Two 8 lane One 8 lane and Two 4 lane PCI Express port PCI Express 1 x4 port is mapped to PCI Device 6 The port may negotiate down to narrower widths Support for x16 x8 x4 x1 widths for a single PCI Express mode 2 5 GT s and 5 0 GT s PCI Express frequencies are supported e Genl Raw bit rate on the data pins of 2 5 Gb s resulting in a real bandwidth per pair of 250 MB s given the 8b 10b encoding used to transmit data across this interface This also does not account for packet overhead and link maintenance Maximum theoretical bandwidth on interface of 4 GB s in each direction simultaneously for an aggregate of 8 GB s when x16 Gen 1 Gen2 Raw bit rate on the data pins of 5 0 Gb s resulting in a real bandwidth per pair of 500 MB s given the 8b 10b encoding used to transmit data across this interface This also does not account for packet overhead and link maintenance Maximum theoretical bandwidth on interface of 8 GB s in each direction simultaneously for an aggregate of 8 GB s when x16 Gen 2 Hierarchical PCI compliant configuration mechanism for downstream devices Traditional PCI style traffic asynchronous snooped PCI ordering PCI Express extended configuration space The first 256 bytes of configuration space aliases directly to the PCI Compatibility configuration space The remaining portion of the fixed 4 KB block of memory mapped sp
23. SA 5 CK SA SB MA SM RC 24 10 1 3 3 3 2 2 0 1 SB CS SB RA SB BS SA CS SA MA SA BS SA MA SB OD SB CS SB c 58 CS 57 T 1 1 0 5 0 2 SB OD SB CS SB MA SA OD SA OD SA MA SA CS SA CS SB_OD E d 28 T 3 3 13 13 SM_RC 5 55 29 gt LE m SA DQ SA DQ SA DQ SA DQ SA SM RC 30 34 38 5 4 33 32 OMP 2 vss SB_DQ VSS SA_DQ SA_DQ SA DQ SA DQ SA DQ SB DQ SB DQ SB DQ SB DQ SB 31 60 35 39 S 4 37 36 S 4 36 32 33 37 SB_DQ SB_DQ SB_DQ SB_DQ SB_DQ SB_DQ SB_DQ d S n m ia SB DQ SB DQ SB DQ SB a SB_DQ SB_DQ SB_DQ SB_DQ SB DQ SB DQ SB DQ SB DQ SB DQ vss vss 50 53 vss 42 45 vss 44 34 vss SB_DQ SB_DQ SB_DQ SB_DQ SB_DQ SB_DQ SB_DQ 35 62 57 55 48 47 41 40 SB_DQ SB DQ SB DQ SB DQ SB SB DQ SB Em w Y AA AB AC AE AK AM AN AP AR AT Intel Xeon and Intel Core Processors For Communications Infrastructure May 2012 Datasheet Volume 1 of 2 Document Number 327405 001 145 n tel Processor Ball and Package Information Package Mechanical nformation The following section contains the mechanical drawings for the processor The processor utilizes a 37 5 x 37 5 mm FC BGA package There are two versions of die available on this package a 4 Core die version and a 2 Core die version The processor SKUs and their corresponding die type are provided in Table 5 1
24. VcRoss Crossing Point Voltage Single Ended 250 550 mV RT 9 4 1 4 5 VcROSS DELTA Variation of Vcnoss Single Ended 140 mV RT 9 4 1 4 8 VMAX Max Output Voltage Single Ended 1 15 V RT 9 4 1 6 Min Output Voltage Single Ended 0 3 V RT 9 4 1 7 DTY CYC Duty Cycle Diff 40 60 96 Avg 9 3 2 Notes T Measurement taken from single ended waveform on a component test board 2 Measurement taken from differential waveform on a component test board 3 Slew rate measured through Vsw ng voltage range centered about differential zero 4 Venoss is defined as the voltage where Clock Clock 5 Only applies to the differential rising edge i e Clock rising and Clock falling 6 The max voltage including overshoot 7 The min voltage including undershoot 8 The total variation of all Vcaoss measurements in any particular system This is a subset of Vcross_minsmax absolute allowed The intent is to limit Vcross induced modulation by setting Vcnoss perra to be smaller than Vcnoss absolute Matching applies to rising edge rate for Clock and falling edge rate for Clock It is measured using a 75 mV window centered on the average cross point where Clock rising meets Clock falling See Figure 17 Differential Clock Differential Measurements on page 121 The median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations 9 11 1 DDR3 AC Specifications The following no
25. mode In order to benefit from x2APIC capabilities a new Operating System and a new BIOS are both needed with special support for the X2APIC mode The x2APIC architecture provides backward compatibility to the xAPIC architecture and forward extendibility for future Intel platform innovations Note Intel x2APIC technology may not be available on all SKUs For more information see the Intel 64 Architecture x2APIC specification at http www intel com products processor manuals 8 Intel Xeon and Intel Core Processors For Communications Infrastructure May 2012 Datasheet Volume 1 of 2 Document Number 327405 001 43 intel Intel Xeon and Intel Core Processors For Communications Infrastructure Datasheet Volume 1 of 2 May 2012 44 Document Number 327405 001 Processor SKUs 5 0 This section details the features of the various SKUs of the Intel Xeon and Intel Processor SKUs Core Processors for Communications Infrastructure The mix of SKUs are chosen to span cost performance temperature environment and power consumption Table 5 1 outlines the processor SKUs available 5 1 Overview 5 1 1 SKU Features Table 5 1 Base Features by SKU Intel Xeon and Intel Core Processors for Communications Infrastructure Intel Xeon Intel Xeon Intel Core a Intel Product Name Processor Processor i3 Processor p E3 1125C E3
26. By default a single x16 controller is enabled When a logic 0 is required on the strap it is recommended that they be pulled down to ground with a 1 K Ohm resistor If the x16 controller is enabled by the hardware strapping and a x8 device is plugged in the controller automatically operates in the x8 mode The same is true for any controller that is connected to a device operating at narrower lane widths Hot plug is not supported on these PCle interfaces If a device is not present at power up it is not detected when it is plugged in after power up Also the strap values are read upon power up and the pre boot software enables the appropriate controller based on the value read on CFG 6 5 Hence if a device of lower lane width than the width of the controller that is enabled is plugged in before power up then it is automatically detected But if a device with higher lane width is plugged in the device is not detected The same is true for the number of controllers enabled If a single controller is enabled at power up then a single device of any width equal to or lower than the width of the controller is detected For example if upon power up the value on CFG 6 5 is 1 1 then the 1x16 controller is enabled A single device of width x16 will be detected upon power up But if two devices of any lower width are plugged in only the device connected to Device 1 Function 0 will be detected Intel Xeon and Intel Core Processors F
27. Core Processors For Communications Infrastructure Datasheet Volume 1 of 2 May 2012 90 Document Number 327405 001 Electrical Specifications intel Table 9 3 Signal Groups Sheet 2 of 3 Signal Group DDR3 Data Signals Type Signals SA DQ 63 0 SB DQ 63 0 Single ended DDR3 Bi directional SA ECC CB 7 0 SB ECC CB 7 0 Differential DDR3 Bi directional DOSL8 0 SA I SB_DQS 8 0 SB_DQS 8 0 DDR3 Compensation Analog Bi directional SM RCOMP 2 0 DDR3 Reference Analog Input SM VREF TAP ITP XDP Single Ended CMOS Input TDI TMS TRST Single Ended CMOS Open Drain Output TDO Single Ended Asynchronous CMOS Bi directional 7 0 Single Ended Asynchronous CMOS Output PRDY Single Ended Asynchronous CMOS Input PREQ Control Sideband Single Ended CMOS Input CFG 17 0 Single Ended Asynchronous GTL Bi directional PROCHOT Single Ended Asynchronous CMOS Output THERMTRIP CATERR SM_DRAMPWROK Single Ended Asynchronous CMOS Input UNCOREPWRGOOD PM SYNC RESET Single Ended Asynchronous Bi directional PECI Voltage Regulator Single Ended CMOS Input VIDALERT Single Ended Open Drain Output VIDSCLK Single Ended CMOS Output VCCSA_VID Single Ended Bn CMOS Input Open vIDSOUT Single Ended Analog Output OCA VCC SENSE VSS SENSE Differential Analog Output VCCIO SENSE V
28. Receiver eye margins are defined into a 2 x 50 reference load A Receiver is characterized by driving it with a signal whose characteristics are defined by the parameters specified in the Express Base Specification 13 The four inherent timing error parameters are defined for the convenience of Rx designers and they are measured during Receiver tolerancing 14 Minimum eye time at Rx pins to yield a 10 12 BER Intel Xeon and Intel Core Processors For Communications Infrastructure May 2012 Datasheet Volume 1 of 2 Document Number 327405 001 107 n tel Electrical Specifications 9 11 3 Miscellaneous AC Specifications Table 9 22 Miscellaneous AC Specifications T Parameter Min Max Unit Figure Notes T1 Asynchronous GTL input pulse width 8 BCLKs 9 10 1 2 3 4 PROCHOT pulse width 500 us 9 10 1 2 3 T5 THERMTRIP assertion until Vcc removed 500 ms 9 11 1 2 3 Notes 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 All AC timing for the Asynchronous GTL signals are referenced to the BCLK rising edge at Crossing Voltage Vcnoss SM_DRAMPWROK are referenced to the BCLK rising edge at 0 5 3 These signals may driven asynchronously 9 11 4 TAP Signal Group AC Specifications Table 9 23 TAP Signal Group AC Specifications T Parameter Min Max Unit Figure Notes T
29. Resistance Pure 20 8 25 8 29 2 Q 5 DDR3 Clock Buffer pull down Resistance 20 8 24 8 31 2 Q 5 DDR3 Command Buffer pull u RoN UP CMD Resistance Purr up 15 8 20 5 23 5 Q 5 Intel Xeon and Intel Core Processors For Communications Infrastructure May 2012 Datasheet Volume 1 of 2 Document Number 327405 001 97 intel Electrical Specifications Table 9 10 DDR3 Signal Group DC Specifications Sheet 2 of 2 Symbol Parameter Min Typ Max Units Notes DDR3 Command Buffer pull down Row DN CMD Resistance p 15 7 19 8 24 0 Q 5 DDR3 Control Buffer pull u Row UP CTL Resistance Pu up 14 9 20 1 23 7 Q 5 DDR3 Control Buffer pull down Input Leakage Current DQ CK 0 75 ov 0 55 lu 0 2 VDDQ mA 0 8 V P DDQ 1 4 Vppq nput Leakage Current CMD CTL 0 85 oV 0 65 lu 0 2 Vppq mA 0 8 V 1 10 HE 1 65 SM_RCOMPO Command COMP Resistance 138 6 140 141 4 8 SM RCOMPI Data COMP Resistance 25 74 26 26 26 Q 8 SM_RCOMP2 ODT COMP Resistance 198 200 202 8 Notes 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 Vi is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low value 3 Vin is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high value 4 Vin and Voy may experience excursions above Vppq However
30. SA_DQ 35 AG36 SB_DQ 54 AE27 VDDQ AF32 VSS AH1 VSS AE28 VDDQ AF33 VSS AH2 VSS AE29 VSS AF34 VSS AH3 VSS AE30 VSS AF35 VSS AH4 VSS AE31 VSS AF36 SB_DQ 51 AH5 VSS AE32 SB_DQS 7 AG1 SA_DQ 6 AH6 vss AE33 SB_DQ 61 AG2 SA DQI7 AH7 SB DQSZ 1 AE34 SB DQ 56 AG3 SA DQI2 AH8 SB_DQS 1 AE35 SB_DQ 57 AG4 SA_DQ 3 AH9 VSS AE36 VSS AG5 SA_DQS 0 AH10 SA_DQS 2 AF1 SA_DQ 1 AG6 VSS AH11 SA_DQS 2 AF2 SA_DQ 5 AG7 SB_DQ 8 12 VSS Intel Xeon and Intel Core Processors For Communications Infrastructure May 2012 Datasheet Volume 1 of 2 Document Number 327405 001 127 n tel Processor Ball and Package Information Ball Signal Ball Signal Ball Signal AH13 SB_DQS 8 AJ18 SB_MA 8 AK23 VDDQ AH14 SB_DQS 8 AJ19 SB_MA 5 AK24 SA_WE AH15 VSS AJ20 VSS AK25 SA_CS 0 AH16 SB_BS 2 21 SB_CK 1 AK26 VDDQ AH17 VDDQ AJ 22 SB_CK 2 AK27 SA_CS 3 AH18 SB_MA 6 AJ23 VSS 28 SA_ODT 3 19 5 MA 4 24 SB_BS 1 AK29 VSS AH20 VDDQ AJ25 SB_BS 0 AK30 SA_DQ 32 AH21 SB_CK 0 26 VSS 1 SA_DQ 36 AH22 SB_CK 0 27 SB_ODT 0 AK32 VSS AH23 VDDQ AJ28 SB_MA 13 AK33 SB_DQ 43 AH24 SB MA 10 AJ29 VSS AK34 SB_DQ 42 AH25 SB_RAS AJ30 SA DQ 33 AK35 SB DQ 47 AH26 VDDQ AJ 31
31. input signal drivers must comply with the signal quality specifications 5 This is the pull up down driver resistance See the processor 1 0 Buffer Models for I V characteristics 6 is the termination on the DIMM and is not controlled by the Processor 7 The minimum and maximum values for these signals are programmable by BIOS to one of the two sets 8 SM_RCOMPx resistance must be provided on the system board with 1 resistors SM_RCOMPx resistors are connected to Vss 9 SM DRAMPWROK must have a maximum of 15ns rise or fall time over 0 55 200mV and the edge must be monotonic 10 SM VREF is defined as Vppo 2 Table 9 11 Control Sideband and TAP Signal Group DC Specifications Symbol Parameter Min Max Units Notes VIL Input Low Voltage Vecio 0 3 2 3 Vin Input High Voltage Vccio 0 7 V 2 3 5 VoL Output Low Voltage Vccio 0 1 V 2 Output High Voltage Vccio 0 9 V 2 5 Ron Buffer on Resistance 23 73 Q Input Leakage Current PROCHOT 0 20 to 2 00 m 4 H TDO 0 20 to 2 00 All other signals in this group 0 20 to 0 50 Notes 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 The Vccio referred to in these specifications refers to instantaneous Vccio 3 See the processor 1 0 Buffer Models for I V characteristics 4 For between 0 V and Measured when the driver is tristated 5 Vin and Vor may e
32. or equivalent while measurements made at 2 5 GT s require a scope with at least 6 2 GHz bandwidth Measurement at 5 0 GT s must de convolve effects of compliance test board to yield an effective measurement at Tx pins 2 5 GT s may be measured within 200 mils of Tx device s pins although de convolution is recommended For measurement setup details see the PCI Express Base Specification At least 10 9 UI of data must be acquired 8 Transmitter jitter is measured by driving the Transmitter under test with a low jitter ideal clock and connecting the DUT to a reference load 9 Transmitter raw jitter data must be convolved with a filtering function that represents the worst case CDR tracking BW 2 5 GT s and 5 0 GT s use different filter functions that are defined in the PCI Express Base Specification After the convolution process has been applied the center of the resulting eye must be determined and used as a reference point for obtaining eye voltage and margins 10 For 5 0 GT s de emphasis timing jitter must be removed An additional HPF function must be applied as shown in the PCI Express Base Specification This parameter is measured by accumulating a record length of 10 6 UI while the DUT outputs a compliance pattern TMIN PULSE is defined to be nominally 1 UI wide and is bordered on both sides by pulses of the opposite polarity See the PCI Express Base Specification for more details 11 Measured differentially from 20 to 80 of swing 12
33. 1 21500 1 1 0 0 0 0 1 1 C 3 1 22000 1 1 0 0 0 1 0 0 C 4 1 22500 1 1 0 0 0 1 0 1 C 5 1 23000 1 1 0 0 0 1 1 0 C6 1 23500 1 1 0 0 0 1 1 1 C 7 1 24000 1 1 0 0 1 0 0 0 C 8 1 24500 1 1 0 0 1 0 0 1 C 9 1 25000 1 1 0 0 1 0 1 0 C 1 25500 1 1 0 0 1 0 1 1 C B 1 26000 1 1 0 0 1 1 0 0 C C 1 26500 1 1 0 0 1 1 0 1 1 27000 1 1 0 0 1 1 1 0 1 27500 1 1 0 0 1 1 1 1 F 1 28000 Intel Xeon and Intel Core Processors For Communications Infrastructure May 2012 Datasheet Volume 1 of 2 Document Number 327405 001 87 intel Table 9 1 IMVP7 Voltage Identification Definition Sheet 7 of 8 Electrical Specifications VID7 VID6 VID5 VID4 VID3 VID2 VID1 VIDO HEX Vcc Max 1 1 0 1 0 0 0 0 D 0 1 28500 1 1 0 1 0 0 0 1 D 1 1 29000 1 1 0 1 0 0 1 0 D 2 1 29500 1 1 0 1 0 0 1 1 D 3 1 30000 1 1 0 1 0 1 0 0 D 4 1 30500 1 1 0 1 0 1 0 1 5 1 31000 1 1 0 1 0 1 1 0 6 1 31500 1 1 0 1 0 1 I 1 D 7 1 32000 1 1 0 1 1 0 0 0 8 1 32500 1 1 0 1 1 0 0 1 9 1 33000 1 1 0 1 1 0 1 0 DIA 1 33500 1 1 0 1 1 0 1 1 D B 1 34000 1 1 0 1 1 1 0 0 D C 1 34500 1 1 0 1 1 1 0 1 D D 1 35000 1 1 0 1 1 1 1 0 1 35500 1 1 0 1 1 1 1 D F 1 36000 1 1 1 0 0 0 0 0 E 0 1 36500 1 1 1 0 0 0 0 1 E 1 1 37000 1 iL 1 0 0 0 1 0 E 2 1 37500 1 1 1 0 0 0 1 1 3 1 38000 1 1 1 0 0 1 0 0 E 4 1 38500 1 1 1 0 0 1 0 1 E
34. 10 mV uS di dt Step current 7 5 3 4 Notes 1 The current supplied to the DIMM modules is not included in this specification 2 Long term reliability cannot be assured in conditions above or below Max Min functional limits 3 Step current between 1 amp through 8 5 amps is done in 150nS 4 di dt values are for platform testing only This parameter is not tested on Intel silicon Testing should go up to and include IccMax Table 9 8 System Agent VccsA Supply DC Voltage and Current Specifications Symbol Parameter Min Typ Max Unit Note Voltage for the System Agent and E _ VCCSA_VCCSENCE 0 30 TOLccsA VccsA Tolerance AC DC 5 1 CCMAX_VCCSA Max Current for VccsA Rail 6 1 Thermal Design Current for V CCTDC_VCCSA Rail 3 TBC GESA 6 1 Intel Xeon and Intel Core Processors Communications Infrastructure Datasheet Volume 1 of 2 May 2012 96 Document Number 327405 001 Electrical Specifications intel Table 9 8 System Agent VccsA Supply DC Voltage and Current Specifications Symbol Parameter Min Typ Max Unit Note Slew Rate Voltage Ramp rate dV dT 0 5 10 mV uS 1 di dt Step current 2 A 2 3 Notes 1 Long term reliability cannot assured in conditions above below functional limits
35. 1105C 2115C B915C 725C Target Core Speed GHz 2 0 1 0 2 0 1 5 1 3 Active Cores 4 4 2 2 1 TDP Watts 40 25 25 15 10 Die Type 4 Core 4 Core 2 Core 2 Core 2 Core L3 Cache MB 8 6 3 3 1 5 MemoryChannels 2 2 23 23 1 ECC Memory Yes PCI Express lanes 20 16 PCI Express root 1x16 1x4 or 2x8 1x4 or 1x8 3x4 1x16 or 2x8 or 1 8 2x4 Junction Temperature Ty min 0 C Ty max 100 C Intel Virtualization Technology Yes Intel Hyper Threading Yes Technology Intel Trusted Execution N o Technology Graphics No Intel Turbo Boost No Note T Thermal Design Power TDP is a system design target associated with the maximum component operating temperature specifications TDP values are determined based on typical DC electrical specification and maximum component temperature for a realistic case application running at maximum utilization Intel Xeon and Intel Core Processors For Communications Infrastructure May 2012 Datasheet Volume 1 of 2 Document Number 327405 001 45 n tel Processor SKUs Intel Xeon and Intel Core Processors For Communications Infrastructure Datasheet Volume 1 of 2 May 2012 46 Document Number 327405 001 Power Management n tel 6 0 Power Management This chapter provides information on the following power management topics ACPI States Processor Core Integrated Memory Controller IMC PCI Express Direct
36. 148 Document Number 327405 001 Processor and Package Information n tel 858 Intel Xeon and Intel Core Processors For Communications Infrastructure May 2012 Datasheet Volume 1 of 2 Document Number 327405 001 149 n tel Processor Ball and Package Information Intel Xeon and Intel Core Processors For Communications Infrastructure Datasheet Volume 1 of 2 May 2012 150 Document Number 327405 001 Processor Configuration Registers n tel 11 0 Note Processor Configuration Registers This section contains register information that is specific to the Intel Xeon Intel Core Intel Pentium and Intel Celeron Processors for Communications Infrastructure For other register details see the latest version of the 2nd Generation Intel Core Processor Family Mobile Datasheet Volume 2 The processor does not include the Integrated Display Engine or the Graphics Processor Unit GPU Disregard references to graphics and Intel Turbo Boost in the 2nd Generation Intel Core Processor Family Mobile Datasheet Volume 2 Table 11 1 shows the register related terminology that is used in this document Table 11 1 Register Terminology May 2012 Item Description RO Read Only These bits can only be read by software writes have no effect The value of the bits is determined by the hardware only RW Read Write These bits can be read and written by software
37. AB5 VSS R28 VSS v31 VSS AB6 VSS R30 VSS w2 VSS AB11 VSS R31 VSS w3 VSS AB13 VSS T2 VSS WA VSS AB16 Intel Xeon and Intel Core Processors For Communications Infrastructure May 2012 Datasheet Volume 1 of 2 Document Number 327405 001 139 Processor Package Information Signal Ball Signal Ball Signal Ball vss AB19 vss AE31 vss AJ23 vss AB22 vss AE36 vss AJ26 vss AB25 vss AF6 vss AJ29 vss AB31 vss AF9 vss AJ32 vss AC6 vss AF12 vss AJ33 vss AC31 vss AF15 VSS 34 vss AC32 vss AF25 VSS 35 vss AC33 vss AF27 vss AK6 vss AC34 VSS AF28 vss AK9 vss AC35 vss AF29 vss AK12 vss AC36 vss AF32 vss AK15 vss AD6 vss AF33 vss AK29 vss AD7 vss AF34 VSS AK32 VSS AD8 vss AF35 vss AK36 vss AD9 vss AG6 vss AL1 vss AD12 vss AG9 vss AL2 vss AD16 vss AG12 vss AL3 vss AD19 vss AG15 vss AL4 vss AD20 vss AG17 vss AL5 vss AD22 vss AG20 vss AL6 vss AD23 vss AG23 vss AL7 vss AD24 vss AG26 vss AL8 vss AD26 vss AG29 vss AL9 vss AD27 vss AG32 vss AL10 vss AD30 vss AH1 vss AL11 vss AE1 vss AH2 vss AL12 vss AE2 vss AH3 vss AL13 vss AE3 vss AH4 VSS AL14 VSS 4 VSS AH5 VSS AL17 VSS AE5 VSS AH6 VSS AL20 VSS vss AH9 vss AL21 vss AE7 vss AH12 VSS AL23 VSS AE8 VSS AH15 VSS AL26 VSS AE9 VSS AH29 vss AL29 VSS AE10 VSS AH32 VSS AL30 VSS 11 vss AJ6 vss
38. Adaptive Thermal Monitor However if the system software tries to enable On Demand mode at the same time the TCC is engaged the factory configured duty cycle of the TCC overrides the duty cycle selected by the On Demand mode If the I O based and MSR based On Demand modes are in conflict the duty cycle selected by the 1 0 emulation based On Demand mode takes precedence over the MSR based On Demand Mode MSR Based On Demand Mode If Bit 4 of thelA32 CLOCK MODULATI ON MSR is set to a 1 the processor immediately reduces its power consumption via modulation of the internal core clock independent of the processor temperature The duty cycle of the clock modulation is programmable via Bits 3 1 of the same IA32_ CLOCK MODULATI ON MSR In this mode the duty cycle can be programmed in either 12 596 or 6 2596 increments discoverable via CPU ID Thermal throttling using this method modulates each processor core s clock independently 1 Emulation Based On Demand Mode emulation based clock modulation provides legacy support for operating system software that initiates clock modulation through 1 0 writes to ACPI defined processor clock control registers on the chipset PROC CNT Thermal throttling using this method modulates all processor cores simultaneously Memory Controller Specific Thermal Features The memory controller provides the ability to initiate memory throttling based upon memory temperature The memory temperature can be prov
39. Base Features by SKU on page 45 The primary mechanical difference between the two products is the size of the die on the substrate The pinout package substrate and solder ball pattern are the same between the two packages See the following package drawings for the die size of the two processor packages Figure 10 5 shows the 4 Core Die Mechanical Package and Figure 10 6 shows the 2 Core Die 1 Core Die Mechanical Package The dimensions in the figures are in millimeters Remember to check the size differences between the two dies when designing your thermal solution Intel Xeon and Intel Core Processors For Communications Infrastructure Datasheet Volume 1 of 2 May 2012 146 Document Number 327405 001 Processor and Package Information n tel Figure 10 5 Processor 4 Core Die Mechanical Package re r 6 e amp 5 x lt lt T o E lt t a gy mor E amp 4 12 i E EDEC HIGH TEMPERATURE FLATNESS AS STI SPP 02 CATION ECIFI T Y gt t ONFIDENCE AND
40. Characteristics Tsin D DQ 63 0 DQS 8 0 DQS 8 0 Input Slew Rate 6 5 2 0 V ns 2 System Memory Clock Timings Tck CK Period 1 875 ns Tcu CK High Time 0 8125 ns TeL CK Low Time 0 8125 ns T Skew Between Any System Memory Differential 100 5 SKEW Clock Pair CK CKB P System Memory Command Signal Timings RAS CAS WE MA 14 0 BA 2 0 Edge T Placement Accuracy ps 9 5 3 4 6 System Memory Control Signal Timings CS 1 0 CKE 1 0 ODT 1 0 Edge Placement _ co 145 145 5 9 5 3 6 System Memory Data and Strobe Signal Timings aes ee Ee Valid before DQS 8 0 Rising or Falling 687 5 ps 7 DQ Input Setup plus Hold Time to DQS Rising or E Tsu HD Falling Edge 200 ps 9 6 1 2 7 DQS Edge Placement Accuracy to CK Rising Edge _ AFTER write levelling 250 250 i 8 TwPRE DQS DQS Write Preamble Duration 1 0 Tck Twest DQS DQS Write Postamble Duration 0 5 Tck CK Rising Edge Output Access Time Where a Write Cun X Tposs Command Is Referenced to the First DQS Rising us 4 5 5 6 Edge Intel Xeon and Intel Core Processors For Communications Infrastructure Datasheet Volume 1 of 2 May 2012 104 Document Number 327405 001 Electrical Specifications Table 9 19 DDR3 Electrical Characteristics and AC Timings at 1333 s Vppo 1 5 V x0 075 V Channel A Symbol Parameter
41. F15 VCC G20 VCC E11 PCIE2_RX 0 F16 vss G21 12 vss F17 VCC G22 VSS E13 VSS F18 VCC G23 VCC E14 VCC F19 VSS G24 VCC E15 VCC F20 VCC G25 VSS E16 VSS F21 VCC G26 VIDSOUT E17 VCC F22 VSS G27 VSS E18 VCC F23 VCC G28 VSS E19 VSS F24 VCC G29 PREQ E20 VCC F25 VSS G30 RSVD_11 Intel Xeon and Intel Core Processors For Communications Infrastructure May 2012 Datasheet Volume 1 of 2 Document Number 327405 001 121 Processor Package Information Ball Signal Ball Signal Ball Signal G31 THERMTRIP H36 vss K5 PCIE1_TX 9 G32 vss J1 PCIE_ICOMPI K6 PCIE1_TX 9 G33 RSVD_34 12 vss K7 vss G34 RSVD 32 3 PCIE1_TX 10 K8 PCIE1_TX 3 G35 vss J4 PCIE1_TX 8 K9 PCIE1_TX 3 G36 RSVD_35 J5 PCIE1_TX 8 K10 vss H1 PCIE1_RX 15 6 PCIE1_TX 6 K11 PCIE2_TX 3 H2 vss J7 PCIE1_TX 6 K12 PCIE2_TX 3 H3 vss 18 vss K13 vss H4 VSS J9 PCIE1_TX 2 K14 VCC H5 PCIE1_TX 7 J10 PCIE1_TX 2 K15 H6 vss J11 vss K16 vss H7 PCIE1_TX 5 J12 RSVD_7 K17 VCC H8 PCIE1_TX 5 J13 vss K18 H9 VSS J14 VCC K19 VSS H10 PCIE1_TX 1 J15 K20 H11 PCIE1_TX 1 16 vss K21 H12 vss 17 VCC K22 VSS H13 VSS 118 VCC K23 VCC H14 VCC J19 VSS K24 VCC H15 VCC J20 VCC K25 VSS H16 VSS J21 VCC K26 PRDY H17 VCC 22 55 K27 VSS H18 VCC 23 VCC K28 RSVD_46 H
42. HEX Vcc Max 0 0 0 0 1 0 0 0 0 8 0 28500 0 0 0 0 1 0 0 1 0 9 0 29000 0 0 0 0 1 0 1 0 0 0 29500 0 0 0 0 1 0 1 1 0 0 30000 0 0 0 0 1 1 0 0 Oo Cc 0 30500 0 0 0 0 1 1 0 1 0 31000 0 0 0 0 1 1 1 0 0 E 0 31500 0 0 0 0 1 1 1 1 0 0 32000 0 0 0 1 0 0 0 0 1 0 0 32500 0 0 0 1 0 0 0 1 1 1 0 33000 0 0 0 1 0 0 1 0 112 0 33500 0 0 0 1 0 0 1 1 113 0 34000 0 0 0 1 0 1 0 0 114 0 34500 0 0 0 1 0 1 0 1 115 0 35000 0 0 0 1 0 1 1 0 1 6 0 35500 0 0 0 1 0 1 1 1 1 7 0 36000 0 0 0 1 1 0 0 0 118 0 36500 0 0 0 1 1 0 0 1 119 0 37000 0 0 0 1 1 0 1 0 1 0 37500 0 0 0 1 1 0 1 1 1 0 38000 0 0 0 1 1 1 0 0 1 C 0 38500 0 0 0 1 1 1 0 1 1 D 0 39000 0 0 0 1 1 1 1 0 1 E 0 39500 0 0 0 1 1 1 1 1 1 F 0 40000 0 0 1 0 0 0 0 0 2 0 0 40500 0 0 1 0 0 0 0 1 2 1 0 41000 0 0 1 0 0 0 1 0 2 2 0 41500 0 0 1 0 0 0 1 1 2 3 0 42000 0 0 1 0 0 1 0 0 2 4 0 42500 0 0 1 0 0 1 0 1 2 5 0 43000 0 0 1 0 0 1 1 0 216 0 43500 0 0 1 0 0 1 1 1 2 7 0 44000 0 0 1 0 1 0 0 0 2 8 0 44500 0 0 1 0 1 0 0 1 2 9 0 45000 0 0 1 0 1 0 1 0 2 0 45500 0 0 1 0 1 0 1 1 2 B 0 46000 0 0 1 0 1 1 0 0 2 C 0 46500 0 0 1 0 1 1 0 1 2 D 0 47000 0 0 1 0 1 1 1 0 2 0 47500 0 0 1 0 1 1 1 1 2 0 48000 Intel Xeon Intel Core Processors For Communications Infrastructure May 2012 Datasheet Volume 1 of 2 Document Number 327405 001 83 intel Table 9 1 IMVP7 Voltage Identification Definition Sheet 3 of 8 Electrical Specifications
43. ITS CONTENTS NSENT OF INTEL JRA ISCLOSED IN OR WRITTEN LEW WITHOUT THE s X IFIE NFIDENTIAL INFORMATION NDERF ILL bs RATION CO INTEL Intel Xeon and Intel Core Processors For Communications Infrastructure May 2012 Datasheet Volume 1 of 2 Document Number 327405 001 147 n tel Processor Ball and Package Information Figure 10 6 Processor 2 Core Die 1 Core Die Mechanical Package z a oF 2 PACKAGE MECHANICAL DRAWING SEE DETAIL D TRE TE gt Ee 5 E SA 5 0 oe z H gt 1 H TUNE gt b IE JN i BW WEE MS 5 s x ES 11 9 N LA k m x x EX N EY B KAGE IE SEE DETAIL A DETAIL Intel Xeon and Intel Core Processors For Communications Infrastructure Datasheet Volume 1 of 2 May 2012
44. Media Interface DMI Figure 6 1 Power States CO Active mode C1 Auto halt Auto halt low freq low voltage C3 L1 L2 caches flush clocks off save core states before shutdown C7 similar to C6 L3 flush Intel Xeon and Intel Core Processors For Communications Infrastructure May 2012 Datasheet Volume 1 of 2 Document Number 327405 001 47 6 1 1 Table 6 1 6 1 2 Table 6 2 6 1 3 Table 6 3 Power Management ACPI States Supported The ACPI states supported by the processor are described in this section System States System States State Description G0 S0 Full On Suspend to RAM STR Context saved to memory S3 Hot is not supported by the G1 S3 Cold processor 1 54 Suspend to Disk STD All power lost except wakeup G2 S5 Soft off All power lost except wakeup on PCH Total reboot G3 Mechanical off All power AC and battery removed from system Processor Core Package I dle States Processor Core Package State Support State Description CO Active mode processor executing code C1 AutoHALT state CIE AutoHALT state with lowest frequency and voltage operating point C3 Execution cores in C3 flush their L1 instruction cache L1 data cache and L2 cache to the L3 shared cache Clocks are shut off to each core C6 Execution cores in this state save their architectural state
45. Pull Down Table 8 15 Processor Internal Pull Up Pull Down Signal Name Pull Up Pull Down Rail Value BPM 7 0 Pull Up VCCIO 65 165 Q PRDY Pull Up VCCIO 65 165 Q PREQ Pull Up VCCIO 65 165 Q TCK Pull Down VSS 5 15 kQ TDI Pull Up VCCIO 5 15 kQ 2012 Document Number 327405 001 Intel Xeon and Intel Core Processors For Communications Infrastructure Datasheet Volume 1 of 2 79 intel Table 8 15 Processor Internal Pull Up Pull Down Signal Description Signal Name Pull Up Pull Down Rail Value TMS Pull Up VCCIO 5 15 5 Pull Up VCCIO 5 15 CFG 17 0 Pull Up VCCIO 5 15 85 Intel Xeon and Intel Core Processors For Communications Infrastructure May 2012 Datasheet Volume 1 of 2 80 Document Number 327405 001 m e Electrical Specifications n tel 9 0 9 1 9 2 Caution 9 2 1 May 2012 Electrical Specifications Power and Ground Pins The processor has Vcc Vccio VppQ VCccPLL VccsA and Vss ground inputs for on chip power distribution All power pins must be connected to their respective processor power planes while all Vss pins must be connected to the system ground plane Use of multiple power and ground planes is recommended to reduce I R drop The Vcc pins must be supplied with the voltage determined by the processor Serial Voltage I Dentification SVID interface Table 9 1 specifies the voltage level for
46. RW1C Read Write 1 to Clear These bits can be read and cleared by software Writing a 1 to a bit will clear it while writing a 0 to a bit has no effect Hardware sets these bits RWOC Read Write 0 to Clear These bits can be read and cleared by software Writing a 0 to a bit will clear it while writing a 1 to a bit has no effect Hardware sets these bits RW1S Read Write 1 to Set These bits can be read and set by software Writing a 1 to a bit will set it while writing a 0 to a bit has no effect Hardware clears these bits Reserved and Preserved These bits are reserved for future RW implementations and their value must not be modified by software When writing to these bits software must RsvdP preserve the value read When SW updates a register that has RsvdP fields it must read the register value first so that the appropriate merge between the RsvdP and updated fields will occur Reserved and Zero These bits are reserved for future RW1C implementations SW must RsvdZ use 0 for writes Write Only These bits can only be written by software reads return zero WO NOTE Use of this attribute type is deprecated and can only be used to describe bits without persistent state Read Clear These bits can only be read by software but a read causes the bits to be cleared Hardware sets these bits RG NOTE Use of this attribute type is only allowed on legacy functions as side effects on reads are no
47. There DDR3 is one Chip Select for each SDRAM rank SB_ODT 3 0 On Die Termination Active Termination Control Intel Xeon and Intel Core Processors For Communications Infrastructure May 2012 Datasheet Volume 1 of 2 Document Number 327405 001 73 8 2 Memory Reference and Compensation Table 8 4 Memory Reference and Compensation Signal Description Signal Name Description Direction Buffer Type SM RCOMP 2 0 System Memory I mpedance Compensation SM RCOMP O0 Pull Down to VSS via 140 Q 1 SM RCOMP 1 Pull Down to VSS via 25 5 1 SM RCOMP 2 Pull Down to VSS via 200 Q 1 Analog SM VREF DDR3 Reference Voltage This provides reference voltage to the DDR3 interface and is defined as VDDQ 2 8 3 Reset and Miscellaneous Signals Table 8 5 Signal Name Reset and Miscellaneous Signals Sheet 1 of 2 Description Analog Direction Buffer Type CFG 17 0 Configuration Signals The CFG signals have a default value of 1 if not terminated on the board See the appropriate Platform Design Guide for pull down recommendations when a logic low is desired CFG 1 0 Reserved configuration ball A test point may be placed on the board for this ball CFG 2 PCI Express Static x16 Lane Port1 Numbering Reversal 1 Normal operation default 0 Lane numbers reversed e CFG 3 PCI Express Static x4 Lane Port2 Numbering Reversal 1 Norm
48. Thermal Monitor is not excessively activated Temperature values from the DTS can be retrieved through A software interface via processor Model Specific Register MSR A processor hardware interface as described in Section 7 3 4 Platform Environment Control Interface PECI When temperature is retrieved by processor MSR it is the instantaneous temperature of the given core When temperature is retrieved via PECI it is the average of the highest DTS temperature in the package over a 256 ms time window Intel recommends using the PECI reported temperature for platform thermal control that benefits from averaging such as fan speed control The average DTS temperature may not be a good indicator of package Adaptive Thermal Monitor activation or rapid increases in temperature that triggers the Out of Specification status bit within the PACKAGE THERM STATUS MSR 01B1h and A32 THERM STATUS MSR 19Ch Code execution is halted in C1 C7 Therefore temperature cannot be read via the processor MSR without bringing a core back into CO However temperature can still be monitored through PECI in lower C states except for C7 Intel Xeon and Intel Core Processors For Communications Infrastructure Datasheet Volume 1 of 2 Document Number 327405 001 65 n tel Thermal Management 7 3 1 2 1 7 3 1 3 Note 7 3 1 3 1 Note 7 3 1 3 2 Unlike traditional thermal devices the DTS outputs a temperature relative to the
49. Type Address Offset Default Value Access MAD DIMM CHO Address Decode Channel 0 0 0 MCHBAR MCMAIN 5004 5007h 00600000h RW L Intel Xeon and Intel Core Processors For Communications Infrastructure Datasheet Volume 1 of 2 158 May 2012 Document Number 327405 001 e Processor Configuration Registers n tel Size 32 bits BIOS Optimal Default 00h This register defines channel characteristics number of DIMMs number of ranks size ECC interleave options and ECC options Table 11 11 Address Decode Channel 0 Default RST Bit Access Value PWR Description 31 26 RO Oh Reserved RSVD ECC is active in the channel ECC 00 no ECC active in the channel 01 ECC is active in IO ECC logic is not active In this case on write accesses the data driven on ECC 25 24 RW L 00b Uncore byte is copied from DQ 7 0 to be used in training or l OSAV 10 ECC is disabled in IO but ECC logic is enabled to be used in ECC4ANA mode 11 ECC active in both IO and ECC logic 23 23 RO Oh Reserved RSVD Enhanced Interleave mode Enh_Interleave 22 RW L 1b Uncore 0 off 1 on Rank Interleave RI 21 RW L 1b Rank Interleave 0 off 1 on DIMM B DDR width DBW 20 RW L Ob Uncore DIMM B Width of DDR chips 0 X8 chips 1 X16 chips DIMM A DDR width DAW 19 RW L Uncore DIMM Width of DDR chips 0 X8 chips 1 X16 chips DIMM B number of ranks DBNOR 18 RW L 0b
50. Uncore 0 single rank 1 dual rank DIMM A number of ranks DANOR 17 RW L 0b Uncore 0 single rank 1 dual rank DIMM A select DAS Selects which of the DIMMs is DIMM should be the 16 RW L 0b Uncore larger DIMM 0 DIMM 0 1 DIMM 1 15 8 RW L 00h Wiicore Size of DIMM B DIMM B Size Size of DIMM B 256 MB multiples Size of DIMM A DIMM A Size aS a 90h Uncorg Size of DIMM A 256 MB multiples Intel Xeon and Intel Core Processors For Communications Infrastructure May 2012 Datasheet Volume 1 of 2 Document Number 327405 001 159 intel Processor Configuration Registers 11 10 MAD DIMM_ CH1 Address Decode Channel 1 B D F Type Address Offset Default Value Access Size BIOS Optimal Default 0 0 0 MCHBAR_MCMAIN 5008 500Bh 00600000h RW L 32 bits 00h This register defines channel characteristics number of DIMMs number of ranks size ECC interleave options and ECC options Table 11 12 Address Decode Channel 1 Sheet 1 of 2 Default RST Value PWR Description 31 26 RO Oh Reserved RSVD ECC is active in the channel ECC 00 no ECC active in the channel 01 ECC is active in IO ECC logic is not active In this case on write accesses the data driven 25 24 RW L 00b Uncore on ECC byte is copied from DQ 7 0 to be used in training or IOSAV 10 ECC is disabled in 10 but ECC logic is
51. a power or thermal management event Intel Adaptive Thermal Monitor Enhanced Intel SpeedStep Technology or Low Power States 3 The voltage specification requirements are measured across Vcc sense and Vss sense balls at the socket with a 100 MHz bandwidth oscilloscope 1 5 pF maximum probe capacitance and 1 MQ minimum impedance The maximum length of ground wire on the probe should be less than 5 mm Ensure external noise from the system is not coupled into the oscilloscope probe 4 See the Platform Design Guide for the minimum typical and maximum Vcc allowed for a given current The processor should not be subjected to Vcc and I cc combination wherein Vcc exceeds Vcc max for a given current 5 Processor core VR to designed to electrically support this current 6 Processor VR to designed to thermally support this current indefinitely 7 Measured at Vcc sense and Vss sense processor pins 8 Long term reliability cannot be assured if tolerance ripple and core noise parameters are violated 9 Long term reliability cannot be assured in conditions above or below Max Min functional limits 10 PSx refers to the voltage regulator power state as set by the SVID protocol 11 Step is done 150 ns 12 Slew time for any transient step size 13 Simulated at platform processor pads This parameter is not tested Intel Xeon and Intel Core Processors For Communications Infrastructure May 2012 Datasheet
52. across the Link The receiving Data Link Layer is responsible for checking the integrity of received TLPs and for submitting them to the Transaction Layer for further processing On detection of TLP error s this layer is responsible for requesting retransmission of TLPs until information is correctly received or the Link is determined to have failed The Data Link Layer also generates and consumes packets which are used for Link management functions 3 2 1 3 Physical Layer The Physical Layer includes all circuitry for interface operation including driver and input buffers parallel to serial and serial to parallel conversion PLL s and impedance matching circuitry It also includes logical functions related to interface initialization and maintenance The Physical Layer exchanges data with the Data Link Layer in an implementation specific format and is responsible for converting this to an appropriate serialized format and transmitting it across the Express Link at a frequency and width compatible with the remote device Intel Xeon and Intel Core Processors For Communications Infrastructure May 2012 Datasheet Volume 1 of 2 Document Number 327405 001 31 intel Note Figure 3 4 3 2 3 Interfaces PCI Express Configuration Mechanism All of the PCI Express controllers are mapped through a PCI to PCI bridge structure The controllers for the 16 lanes Port 1 are mapped to the root port of Device 1 The x1
53. are requested both may be retrieved simultaneously since they are ensured to be on opposite channels Use Dual Channel Symmetric mode when both Channel A and Channel B DIMM connectors are populated in any order with the total amount of memory in each channel being the same When both channels are populated with the same memory capacity and the boundary between the dual channel zone and the single channel zone is the top of memory operates completely in Dual Channel Symmetric mode The DRAM device technology and width may vary from one channel to the other Rules for Populating Memory Slots In all modes the frequency of system memory is the lowest frequency of all memory modules placed in the system as determined through the SPD registers on the memory modules The system memory controller supports one or two DIMM connectors per channel The usage of DIMM modules with different latencies is allowed For dual channel modes both channels must have a DIMM connector populated and for single channel mode only a single channel can have an DIMM connector populated Technology Enhancements of Intel Fast Memory Access Intel FMA The following sections describe the J ust in Time Scheduling Command Overlap and Out of Order Scheduling Intel FMA technology enhancements Intel Xeon and Intel Core Processors For Communications Infrastructure Datasheet Volume 1 of 2 May 2012 28 Document Number 327405 001 Interfaces
54. assuming 8 ranks of 8 bank devices Memory organizations Single channel modes Dual channel modes Intel Flex Memory Technology Dual channel symmetric Interleaved Command launch modes of 1n 2n On Die Termination ODT Intel Fast Memory Access Intel FMA Just in Time Command Scheduling Command Overlap Out of Order Scheduling 2 4 2 PCI Express The PCI Express port s are fully compliant to the PCI Express Base Specification Rev 2 0 The following configurations are supported Configuration 1 One 16 lane PCI Express port intended to connect Processor Root Port to PCH End Point One 4 lane PCI Express port intended for I O Four single lane PCI Express ports intended for 1 0 via the PCH Configuration 2 One 8 lane PCI Express port intended to connect Processor Root Port to PCH End Point One 8 lane PCI Express port intended for I O One 4 lane PCI Express port intended for I O Four single lane PCI Express ports intended for 1 0 via the PCH Configuration 3 One 4 lane PCI Express port intended to connect Processor Root Port to PCH End Point Three 4 lane PCI Express port intended for I O Intel Xeon and Intel Core Processors For Communications Infrastructure Datasheet Volume 1 of 2 May 2012 18 Document Number 327405 001 m e Product Overview n tel Four single lane PCI Express ports intended for I O via the
55. aye ta awa tasya EE Ud 45 System State S i pirin 48 Processor Core Package State eee neater nantes 48 Integrated Memory Controller States 0 0 0 ccc 48 PClie LINK States 49 u au 49 S and C State Combinations UU Lau sasaqa ayau aaa uapa kaqpas qana 49 Coordination of Thread Power States at the Core 51 P LVbx to MWAIT CohVerslOn rece rene reri eec tee ble reine ek en e RF PUn enr a a 52 Coordination of Core Power States at the Package 54 5 E 62 Junction Temperature 5 ccc enne 62 Signal Description Buffer eee eee 71 Memory Channel A Era dI 71 Memory Channel sues ex irse bl serbe rati enar s ter bre t erg e ede aga 72 Intel Xeon and Intel Core Processors For Communications Infrastructure Datasheet Volume 1 of 2 Document Number 327405 001 7 U 04 0 0 0 0 0 0 O O O O O O O O O O O O O O O O O FA H3 H
56. before removing core voltage I ntegrated Memory Controller States I ntegrated Memory Controller States State Description Power up CKE asserted Active mode Pre charge Power down CKE deasserted not self refresh with all banks closed Active Power down CKE deasserted not self refresh with minimum one bank active Self Refresh CKE deasserted using device self refresh Intel Xeon and Intel Core Processors For Communications Infrastructure Datasheet Volume 1 of 2 48 May 2012 Document Number 327405 001 Power Management 6 1 4 Table 6 4 6 1 5 Table 6 5 6 1 6 Table 6 6 6 2 May 2012 PCle Link States PCle Link States State Description LO Full on Active transfer state LOs First Active Power Management low power state Low exit latency L1 Lowest Active Power Management Longer exit latency L3 Lowest power state power off Longest exit latency DMI States DMI States State Description LO Full on Active transfer state LOs First Active Power Management low power state Low exit latency L1 Lowest Active Power Management Longer exit latency L3 Lowest power state power off Longest exit latency I nterface State Combinations G S and C State Combinations puce em pcc System Clocks Description C State GO
57. bits 7 0 MCHBAR 4 As this timer is set to a shorter time the MC will have more opportunities to put DDR in power down The minimum recommended value for this register is 15 There is no BIOS hook to set this register Customers who choose to change the value of this register can do it by changing the BIOS For experiments this register can be modified in real time if BIOS did not lock the MC registers Note In APD APD PPD and APD DLL off there is no point in setting the idle counter in the same range as page close idle timer Another option associated with CKE power down is the 5 DLL off When this option is enabled the SBR 1 0 slave DLLs go off when all channel ranks in power down Do not confuse it with the DLL off mode in which the DDR DLLs are off This mode requires you to define the 1 slave DLL wakeup time Intel Xeon and Intel Core Processors For Communications Infrastructure Datasheet Volume 1 of 2 May 2012 58 Document Number 327405 001 intel 6 3 2 1 6 3 2 2 6 3 2 3 6 4 Note Note 6 5 6 6 May 2012 Initialization Role of During power up CKE is the only input to the SDRAM that has its level is recognized other than the DDR3 reset pin once power is applied It must be driven LOW by the DDR controller to make sure the SDRAM components float DQ and DQS during power up CKE signals remain LOW while any reset is active until the BIOS writes to a configurati
58. case with error syndrome field Table 11 9 Channel 1 ECC Error Log Sheet 1 of 2 May 2012 Document Number 327405 001 i Default RST Bit Access Value PWR Description Error Bank Address ERRBANK 31 29 ROS V 000b Powergood This field holds the Bank Address of the read transaction that had the ECC error Error Rank Address ERRRANK 28 27 ROS V 00b Powergood This field holds the Rank ID of the read transaction that had the ECC error Error Chunk ERRCHUNK 26 24 ROS V 000b Powergood Holds the chunk number of the error stored in the register Error Syndrome ERRSYND This field contains the error syndrome A value of FFh 23 16 ROS V 00h Powergood indicates that the error is due to poisoning For ERRSYND definition see Table 11 13 Error Syndrome ERRSYND 15 2 Oh Reserved RSVD Intel Xeon and Intel Core Processors For Communications Infrastructure Datasheet Volume 1 of 2 157 intel Table 11 9 Channel 1 ECC Error Log 0 Sheet 2 of 2 Processor Configuration Registers Bit Access Default Value RST PWR Description RO P 0b Powergood Multiple Bit Error Status MERRSTS This bit is set when an uncorrectable multiple bit error occurs on a memory read data transfer When this bit is set the address that caused the error and the error syndrome are also logged and they are locked until this bit is cleared This bit is cleared
59. determined per rank when it is inactive Each rank has an idle counter The idle counter starts counting as soon as the rank has no accesses and if it expires the rank may enter power down while no new transactions to the rank arrive to queues The idle counter begins counting at the last incoming transaction arrival It is important to understand that since the power down decision is per rank the MC can find many opportunities to power down ranks even while running memory intensive applications and savings are significant may be a few watts according to the DDR specification This is significant when each channel is populated with more ranks Selection of power modes should be according to power performance or thermal tradeoffs of a given system When trying to achieve maximum performance and power or thermal consideration is not an issue use no power down n a system that tries to minimize power consumption try to use the deepest power down mode possible DLL off or APD DLLoff n high performance systems with dense packaging that is complex thermal design the power down mode should be considered in order to reduce the heating and avoid DDR throttling caused by the heating Control of the power mode must be controlled through the BIOS The BIOS selects no powerdown by default There are knobs to change the power down selected mode Another control is the idle timer expiration count This is set through PM PDWN config
60. enabled to be used in ECC4ANA mode 11 ECC active in both IO and ECC logic 23 23 RO Oh Reserved RSVD Enhanced Interleave mode Enh Interleave 22 RW L 1b Uncore 0 off 1 on Rank Interleave RI 21 RW L 1b Uncore 0 off 1 on DIMM B DDR width DBW 20 RW L 00b Uncore DBW DI MM B width of DDR chips 0 X8 chips 1 X16 chips DIMM A DDR width DAW 19 RW L 00b Uncore DAW DIMM A width of DDR chips 0 X8 chips 1 X16 chips DIMM B number of ranks DBNOR 18 RW L Ob Uncore 0 single rank 1 dual rank Intel Xeon and Intel Core Processors For Communications Infrastructure Datasheet Volume 1 of 2 160 May 2012 Document Number 327405 001 Processor Configuration Registers intel Table 11 12 Address Decode Channel 1 Sheet 2 of 2 Note 11 11 Default RST Bit Access Value PWR Description DIMM A number of ranks DANOR 17 RW L Ob Uncore 0 single rank 1 dual rank DIMM A select DAS Selects which of the DIMMs is DIMM A should 16 RW L Ob Uncore be the larger DI MM 0 DIMMO 1 2 DIMM 1 Size of DIMM B DIMM B Size 15 8 RIDE gon Uncore Size of DIMM B 256 MB multiples Size of DIMM A DIMM A Size s RAE Uneore Size of DIMM A 256 MB multiples This document supplements or overrides the 2nd Generation Intel Core Processor Family Mobile Datasheet Volume 1 For all information not contained in this document see the latest ve
61. exceed the 2 maximum junction temperature Tj max limit as measured by the DTS and the critical temperature bit 3 The processor junction temperature is monitored by Digital Temperature Sensors DTS For DTS accuracy see Section 7 3 1 2 1 Digital Thermal Sensor DTS based fan speed control is required to achieve optimal thermal 4 performance Intel recommends full cooling capability well before the DTS reading reaches Tj Max An example of this would be Tj Max 10 5 At Tj of Tj Intel Xeon and Intel Core Processors For Communications Infrastructure May 2012 Datasheet Volume 1 of 2 Document Number 327405 001 61 intel Thermal Management Table 7 1 TDP Specifications Product Number State CPU Core Thermal Units Notes Frequency Design Power Intel Xeon HFM up to 2 0 GHz 40 w 1 5 Processor E3 1125C LFM 800 MHz 22 Intel HFM up to 1 0 GHz 25 w 1 5 Processor E3 1105C LFM 800 MHz 22 Intel Core i3 HFM up to 2 0 GHz 25 w 1 5 Processor 2115C LFM 800 MHz 13 Intel Pentium HFM up to 1 5 GHz 15 W 15 Processor 915 800 MHz 13 d Intel Celeron amp HFM up to 1 3 GHz 10 w 15 Processor 725 LFM 800 MHz 10 T Table 7 2 Junction Temperature Specification Product Number Symbol Min Default Max Units Notes Intel Xeon Processor E3 1125C Intel Xeon Processor E3 1105C Intel
62. in ACPI protocol Storage Conditions SVID A non operational state The processor may be installed in a platform in a tray or loose Processors may be sealed in packaging or exposed to free air Under these conditions processor landings should not be connected to any supply voltages have any I Os biased or receive any clocks Upon exposure to free air i e unsealed packaging or a device removed from packaging material the processor must be handled in accordance with moisture sensitivity labeling MSL as indicated on the packaging material Serial Voltage Identification System Agent Consists of all the uncore functions within the processor other than the cores and cache This includes the integrated memory controller PCle controller PCU etc TDP Thermal Design Power Thermal Design Current is the maximum current that the VR must be TDC thermally capable of sustaining indefinitely in the worst case thermal environment defined for the platform TPM Trusted Platform Module Vec Processor core power supply Vss Processor ground Vit shared cache memory controller and processor 1 0 power rail VDDQ DDR3 power rail VccsA System Agent memory controller DMI and PCle controllers power supply Vccio High Frequency 1 logic power supply VccPLL PLL power supply x1 Refers to a Link or Port with one Physical Lane x4 Refers to a Link or Port with four Physical Lanes x8
63. masked the target core enters the core CO state and the processor enters package CO f the break event is masked the processor attempts to re enter its previous package state f the break event was due to a memory access or snoop request But the platform did not request to keep the processor in a higher package C state the package returns to its previous C state And the platform requests a higher power C state the memory access or snoop request is serviced and the package remains in the higher power C state Table 6 9 shows package C state resolution for a dual core processor Figure 6 4 summarizes package C state transitions Table 6 9 Coordination of Core Power States at the Package Level Package sores ae co 1 C7 CO CO CO CO CO CO c1 co cil cil cil cil co cil C3 C3 C3 P C6 co cil C3 C6 C6 C7 co Ci C6 C7 Notes 1 the package C state will be CIE if all actives cores have also resolved a core C1 state Intel Xeon and Intel Core Processors For Communications Infrastructure Datasheet Volume 1 of 2 May 2012 54 Document Number 327405 001 intel Figure 6 4 Package C State Entry and Exit 6 2 5 1 6 2 5 2 May 2012 Package CO The normal operating state for the processor The processor remains in the normal state when at least one of its cores is in the CO or C1 state or
64. maximum supported operating temperature of the processor TJ MAX regardless of TCC activation offset It is the responsibility of software to convert the relative temperature to an absolute temperature The absolute reference temperature is readable in the TEMPERATURE TARGET MSR 1A2h The temperature returned by the DTS is an implied negative integer indicating the relative offset from TJ MAX The DTS does not report temperatures greater than TJ MAX The DTS relative temperature readout directly impacts the Adaptive Thermal Monitor trigger point When a package DTS indicates that it has reached the TCC activation a reading of 0 0 except when the activation offset is changed the activates and indicates an Adaptive Thermal Monitor event A activation lowers the 1 core frequency voltage or both Changes to the temperature can be detected via two programmable thresholds located in the processor thermal MSRs These thresholds have the capability of generating interrupts via the core s local APIC See the Intel 64 and IA 32 Architectures Software Developer s Manuals for specific register and programming details Digital Thermal Sensor Accuracy Taccuracy The error associated with DTS measurement does not exceed 5 C at TJ MAX The DTS measurement within the entire operating range meets a 5 accuracy Signal processor hot is asserted when the processor core temperature has reac
65. ns 5 6 Edge Intel Xeon and Intel Core Processors For Communications Infrastructure Datasheet Volume 1 of 2 May 2012 106 Document Number 327405 001 Electrical Specifications n tel 9 11 2 PCI Express AC Specification Table 9 21 PCI Express AC Specification Symbol Parameter Min Max Units Figure Notes Unit Interval Gen 1 399 88 400 12 ps Lm ONE Ul or Rx Unit Interval Gen 2 199 94 200 06 ps TTX EYE Minimum Transmission Eye Width 0 75 Ul 6 7 8 9 10 D D TX Out put Rise Fall time 0 125 UI T ald 7 11 PERISEFALE D D TX Out put Rise Fall time 0 15 Ul 2 Minimum Receiver Eye Width 1 0 4 Ul 9 8 12 14 Max Rx Inherent Timing Error 2 0 40 Ul 2 13 Notes 1 See the PCI Express Base Specification for details 2 inherent total timing error for common Refclk architecture 3 The specified UI is equivalent to a tolerance of 300 for each Refclk source Period does not account for SSC induced variations 4 SSC permits a 0 5000 ppm modulation of the clock frequency at a modulation rate not to exceed 33 kHz 5 UI does not account for SSC caused variations 6 Does not include SSC or Refclk jitter Includes Rj at 10712 2 5 GT s and 5 0 GT s use different jitter determination methods 7 Measurements at 5 0 GT s require an oscilloscope with a bandwidth of gt 12 5 GHz
66. of performance Processor numbers differentiate features within each processor family not across different processor families Go to http www intel com products processor 5Fnumber BunnyPeople Celeron Celeron Inside Centrino Centrino Inside Cilk Core Inside i960 Intel the Intel logo Intel AppUp Intel Atom Intel Atom Inside Intel Core Intel Inside Intel Insider the Intel Inside logo Intel NetBurst Intel NetMerge Intel NetStructure Intel SingleDriver Intel SpeedStep Intel Sponsors of Tomorrow the Intel Sponsors of Tomorrow logo Intel StrataFlash Intel vPro Intel XScale InTru the InTru logo the InTru Inside logo InTru soundmark Itanium Itanium Inside MCS MMX Moblin Pentium Pentium Inside Puma skoool the skoool logo Sound Mark The Creators Project The Journey Inside Thunderbolt vPro Inside VTune Xeon and Xeon Inside are trademarks of Intel Corporation in the U S and or other countries Other names and brands may be claimed as the property of others Copyright 2012 Intel Corporation All rights reserved Intel Xeon and Intel Core Processors For Communications Infrastructure Datasheet Volume 1 of 2 May 2012 2 Document Number 327405 001 Revision History Revision History Date Revision Description May 2012 001 Initial release Intel Xeon and Intel Core Processors For Communications Infrastructure May 2012 Datasheet Volume 1 of 2 Document Number
67. outputs maybe left unconnected however this may interfere with some Test Access Port TAP functions complicate debug probing and prevent boundary scan testing A resistor must be used when tying bi directional signals to power or ground When tying any signal to power or ground a resistor will also allow for system testability Resistor values should be within 20 of the impedance of the baseboard trace unless otherwise noted in the appropriate platform design guidelines For details see Table 8 12 Processor Power Signals Signal Groups Signals are grouped by buffer type and similar characteristics as listed in Table 9 3 The buffer type indicates which signaling technology and specifications apply to the signals All the differential signals and selected DDR3 and Control Sideband signals have On Die Termination ODT resistors Some signals do not have ODT and must be terminated on the board Signal Groups Sheet 1 of 3 Signal Group Type Signals System Reference Clock Differential CMOS Input BCLK BCLK DDR3 Reference Clocks SA CK 3 0 SA_CK 3 0 Differential DDR3 Output SB CK 3 0 SB_CK 3 0 DDR3 Command Signals SA RAS amp SB RAS amp SA_CAS SB_CAS SA_WE SB_WE SA_MA 15 0 SB_MA 15 0 Single Ended DDR3 Output SA_BS 2 0 SB_BS 2 0 SM_DRAMRST SA_CS 3 0 SB_CS 3 0 SA_ODT 3 0 SB ODT 3 0 SA CKE 3 0 SB CKE 3 0 Intel Xeon and Intel
68. performance for the lifetime of the processor Vcc Overshoot Specification When transitioning from a high to low current load condition the processor can tolerate short transient overshoot events where Vcc exceeds the HFM_VID voltage This overshoot cannot exceed VID Vos max Vos max is the maximum allowable overshoot above VID These specifications apply to the processor die voltage as measured across the Vcc sense and Vss sense lands Vcc Overshoot Specifications Symbol Parameter Min Max Units Figure Notes Vos Magnitude of Vcc overshoot above VID 50 9 12 1 Tycc_os_ max Time duration of Vcc overshoot above VID 10 Hs 9 12 1 Notes 1 For overshoot SVID is inclusive of the tolerance band TOLvcc and ripple Intel Xeon and Intel Core Processors For Communications Infrastructure Datasheet Volume 1 of 2 Document Number 327405 001 115 intel Electrical Specifications Figure 9 12 Vcc Overshoot Example Waveform Example Overshoot Waveform Voltage V Time Tos Overshoot time above VID Vos Overshoot above VID Note Oscillations below the reference voltage cannot be subtracted from the total overshoot undershoot pulse duration 9 14 2 Overshoot Undershoot Magnitude Magnitude describes the maximum potential difference between a signal and its voltage reference level For the proc
69. specifications 3 Referenced to rising edge of VIDSCLK 4 Minimum edge rate of 0 5V nS 5 High time is measured with respect to 0 3 VCCIO 6 Low time is measured with respect to 0 7 VCCIO 7 Rise time is measured from 0 3 VCCIO to 0 7 VCCIO 8 Fall time is measured 0 7 VCCIO to 0 3 VCCIO 9 Period and duty cycle are measured with respect to 0 5 VCCI O 9 12 Processor AC Timing Waveforms Figure 9 3 through Figure 9 11 are used in conjunction with the AC timing tables Table 9 14 through Table 9 24 Note For Table 9 3 through Table 9 13 the following notes apply 1 All common clock AC timings signals are referenced to the Crossing Voltage VcRoss of the BCLK BCLK at rising edge of BCLK 2 All source synchronous AC timings are referenced to their associated strobe address or data Source synchronous data signals are referenced to the falling edge of their associated data strobe Source synchronous address signals are referenced to the rising and falling edge of their associated address strobe 3 All AC timings for the TAP signals are referenced to the at 0 5 Vccio at the processor balls All TAP signal timings TMS TDI etc are referenced at 0 5 Vccio at the processor die pads 4 All CMOS signal timings are referenced at 0 5 Vccio at the processor pins Intel Xeon and Intel Core Processors For Communications Infrastructure May 2012 Datasheet Volume 1 of 2 Document Number 32740
70. tek rr ss 157 ECCERRLOG1 C1 ECC Error L00971 iren rh pantaq haasi egi eh nee en i ani 158 MAD DIMM CHO Address Decode Channel 0 158 11 10 MAD DIMM CH1 Address Decode Channel 1 160 11 11 Error Detection and nn 161 Crystal Forest Platform Example Block 16 Intel Flex Memory Technology Operation meme 28 PCI Express Layering Dlagratn uuu u tete esee rete er exea ER ERA eh 30 Packet Flow through the Layers r rr meme e enne 31 PCI Express Related Register eect eee teeta 32 Intel Xeon and Intel Core Processors For Communications Infrastructure Datasheet Volume 1 of 2 May 2012 6 Document Number 327405 001 Contents 1 1 1 1 1 1 PPP NJ P F b U NJ F O Q ONU ON FF UN HO i p p p Hp O O O O O O O O O O O O O Q Q O Y J ty E N Q Q Q Q OQ OQ OQ OQ O U Q Q QJ QJ QQ Q CJ E E QN N F I O I L UN P May 2012 PCI Express PCI Port 33 PCle Typ
71. through Table 9 24 list the AC specifications associated with the processor The timings specified in this section should be used in conjunction with the processor signal integrity models provided by Intel Ensure to read all notes associated with a particular timing parameter Intel Xeon and Intel Core Processors For Communications Infrastructure Datasheet Volume 1 of 2 Document Number 327405 001 101 intel Table 9 14 Differential Clocks SSC on Electrical Specifications SSC ON 1CLK lus 0 1 0 1 lus 1CLK Signal Jitter _ssc short ppm Long Ideal DC 356 Jiitter c c Name Abs AvgMin AvgMin Target Long Shore Abs units PerMin AvgMax AvgMax PerMax BCLK 9 849063 9 999063 10 02406 10 02506 10 02607 10 05120 10 20120 ns Notes 1 Ideal DC Target This serves only as an ideal reference target 0 ppm to use for calculating the rest of the period measurement values 0 1 second Measurement Window frequency counter Valuable measurement done using a frequency counter to determine near DC average frequency filtering out all jitter including SSC and cycle to cycle This is used to determine if the system has a frequency static offset caused usually by incorrect crystal crystal loading or incorrect clock configuration 1 0 us Measurement Window scope This measurement is only used in conjunction with clock post processing software Jit3 Advanced for example with fi
72. when the corresponding bit in 0 0 0 PCI ERRSTS is cleared RO P 0b Powergood Correctable Error Status CERRSTS This bit is set when a correctable single bit error occurs on a memory read data transfer When this bit is set the address that caused the error and the error syndrome are also logged and they are locked to further single bit errors until this bit is cleared A multiple bit error that occurs after this bit is set will override the address error syndrome information This bit is cleared when the corresponding bit in 0 0 0 PCI ERRSTS is cleared 11 8 B D F Type Address Offset Default Value Access Size ECCERRLOG1 C1 ECC Error Log 1 0 0 0 MCHBAR 1 44CC 44CFh 00000000h ROS V 32 bits This register is used to store the error status information in ECC enabled configurations along with the error syndrome and the row and column address information of the address block of main memory of which an error single bit or multi bit error has occurred Table 11 10 Channel 1 ECC Error Log 1 Default RST Bit Access Value PWR Description Error Column ERRCOL 31 16 ROS V 0000h Powergood This field holds the DRAM column address of the read transaction that had the ECC error Error Row ERRROW 15 0 ROS V 0000h Powergood This field holds the DRAM row page address of the read transaction that had the ECC error 11 9 B D F
73. when the platform has not granted permission to the processor to go into a low power state Individual cores may be in lower power idle states while the package is in CO Package C1 CIE No additional power reduction actions are taken in the package C1 state However if the CIE sub state is enabled the processor automatically transitions to the lowest supported core clock frequency followed by a reduction in voltage The package enters the C1 low power state when At least one core is in the C1 state The other cores are in a C1 or lower power state The package enters the C1E state when All cores have directly requested CLE via MWAIT C1 with a CIE sub state hint All cores are in a power state lower that C1 C1E but the package low power state is limited to C1 C1E via the PMG CST CONFIG CONTROL MSR All cores have requested C1 using HLT or MWAIT C1 and auto promotion is enabled 1432 MISC ENABLES No notification to the system occurs upon entry to 1 1 Intel Xeon and Intel Core Processors For Communications Infrastructure Datasheet Volume 1 of 2 Document Number 327405 001 55 intel 6 2 5 3 6 2 5 4 6 2 5 5 6 2 5 6 Package C3 State A processor enters the package C3 low power state when At least one core is in the C3 state The other cores are in a C3 or lower power state and the processor has been granted permission by the platform The platform has n
74. zone starts at the lowest address in each channel and is contiguous until the asymmetric zone begins or until the top address of the channel with the smaller capacity is reached In this mode the system runs with one zone of dual channel mode and one zone of single channel mode simultaneously across the whole memory array Channels A and B can be mapped for physical channels 0 and 1 respectively or vice versa however channel A size must be greater or equal to channel B size Intel Xeon and Intel Core Processors For Communications Infrastructure Datasheet Volume 1 of 2 Document Number 327405 001 27 l n tel i Interfaces Figure 3 1 Intel Flex Memory Technology Operation 3 1 3 2 1 Note 3 1 4 3 1 5 TOM Non interleaved access Dual channel interleaved access CHA CH B B The largest physical memory amount of the smaller size memory module C The remaining physical memory amount of the larger size memory module Dual Channel Symmetric Mode Dual Channel Symmetric mode also known as interleaved mode provides maximum performance on real world applications Addresses are ping ponged between the channels after each cache line 64 byte boundary If there are two requests and the second request is to an address on the opposite channel from the first that request can be sent before data from the first request has returned If two consecutive cache lines
75. 07 Miscellaneous AC SpecificationsS r rr 108 TAP Signal Group AC Specifications u uu ursissrerpscaruyiorencsiprcerusrapapascupancurnaduqa 108 SVID Signal Group AC Specifications meme memes 109 VCC Overshoot Specifications u u cece cece eee EEO EEE nemen nena 115 Processor Overshoot Undershoot Specifications 116 Alphabetical Misting a pe upa FU E das 120 Alphabetical Signal 589 iiit E ERE 131 Register Terminology ete v RUE 151 Register Terminology Attribute eee teen 152 Error Status Register M edipi EH cams 152 Error Command Registers asas asas senem sie ese 154 SMI Command R egisSterS Ra naqa ME Kx uu DERE 154 SCIi Command Registers a exe le dad ee edu ete mibi E id 155 Channel Q ECC Error LO Q ii asciutto nex Ph ee randa e RR qawa phu qhapa AE 156 Channel 0 ECO Error Log Daguas pusqa exor ee ka reo ERNE va d Rei ned 157 Channel 1 ECC Error 09 0 ise eter 157 Channel LECC Error Log 1 treiber rtr nett ede xi ce ee Pre cda 158 Address Decode Channel 159 Address Decode Channel L uu u rco eere e rk Pe da rra Y ie E ERR
76. 1 0 A 2 1 05500 1 0 1 0 0 0 1 1 3 1 06000 1 0 1 0 0 1 0 0 A 4 1 06500 1 0 1 0 0 1 0 1 5 1 07000 1 0 1 0 0 1 1 0 6 1 07500 1 0 1 0 0 1 1 1 7 1 08000 Intel Xeon and Intel Core Processors Communications Infrastructure Datasheet Volume 1 of 2 86 May 2012 Document Number 327405 001 Electrical Specifications intel Table 9 1 IMVP7 Voltage Identification Definition Sheet 6 of 8 VID7 VID6 VID5 VID4 VID3 VID2 VID1 VIDO HEX Vcc Max 1 0 1 0 1 0 0 0 8 1 08500 1 0 1 0 1 0 0 1 9 1 09000 1 0 1 0 1 0 1 0 1 09500 1 0 1 0 1 0 1 1 1 10000 1 0 1 0 1 1 0 0 C 1 10500 1 0 1 0 1 1 0 1 A D 1 11000 1 0 1 0 1 1 1 0 A E 1 11500 1 0 1 0 1 1 1 1 A F 1 12000 1 0 1 1 0 0 0 0 B 0 1 12500 1 0 1 1 0 0 0 1 B 1 1 13000 1 0 1 1 0 0 1 0 B 2 1 13500 1 0 1 1 0 0 1 1 3 1 14000 1 0 1 1 0 1 0 0 B 4 1 14500 1 0 1 1 0 1 0 1 B 5 1 15000 1 0 1 1 0 1 1 0 B 6 1 15500 1 0 1 1 0 1 1 1 B 7 1 16000 1 0 1 1 1 0 0 0 8 1 16500 1 0 1 1 1 0 0 1 9 1 17000 1 0 1 1 1 0 1 0 1 17500 1 0 1 1 1 0 1 1 1 18000 1 0 1 1 1 1 0 0 1 18500 1 0 1 1 1 1 0 1 D 1 19000 1 0 1 1 1 1 1 0 B E 1 19500 1 0 1 1 1 1 1 1 B F 1 20000 1 1 0 0 0 0 0 0 1 20500 1 1 0 0 0 0 0 1 C 1 1 21000 1 1 0 0 0 0 1 0 C 2
77. 1 DMI_TX 0 L28 RSVD_49 M33 vss P2 vss L29 TDO M34 CFG 11 P3 vss L30 CFG 1 M35 vss P4 vss L31 CFG 4 M36 CFG 14 P5 vss L32 CFG 5 N1 vss P6 BCLK L33 CFG 16 N2 RSVD_6 P7 BCLK L34 CFG 9 N3 PCIE1_TX 15 P8 vss L35 CFG 13 N4 PCIE1_TX 12 P9 VCCSA L36 vss N5 PCIE1_TX 12 P10 vss M1 PCIE1_TX 14 N6 VSS P11 VCCSA M2 55 7 vss P12 vcc M3 PCIE1_TX 15 N8 VCCIO P13 VSS 4 vss N9 VCCSA P14 5 vss N10 VCCIO P15 M6 PCIE2 TX 0 N11 VSS P16 VSS M7 PCIE2_TX 0 N12 VCC P17 M8 VSS N13 vss P18 VCC M9 VCCSA_VSSSENSE N14 P19 VSS M10 VCCSA_VCCSENSE N15 VCC P20 VCC M11 VCCIO N16 vss P21 M12 VCCIO N17 vcc P22 vss M13 VSS N18 VCC P23 VCC M14 VCC N19 VSS P24 VCC Intel Xeon and Intel Core Processors For Communications Infrastructure May 2012 Datasheet Volume 1 of 2 Document Number 327405 001 123 Processor Package Information Ball Signal Ball Signal Ball Signal P25 vss R30 vss T35 SA_DQ 57 P26 VCC R31 vss T36 SA_DQ 56 P27 VSS R32 SA_DQS 7 U1 DMI_TX 1 P28 VCCIO R33 SA_DQ 59 U2 DMI_TX 2 P29 VCCIO R34 SA_DQ 58 U3 vss P30 vss R35 SA_DQ 62 U4 DMI_RX 2 P31 vss R36 SA DQI63 U5 VSS P32 VSS 1 DMI_TX 1 U6 VSS P33 vss T2 VSS U7 VCCIO P34 VSS T3 DMI_RX 0 U8 VCCIO P35 VSS T4 DMI RX 1 U9 VCCSA P36
78. 12 SCI CMD SCI Command B D F Type 0 0 0 PCI Address Offset CE CFh Default Value 0000h Access RO RW Size 16 bits BIOS Optimal Default 0000h This register enables various errors to generate an SCI DMI special cycle When an error flag is set in the ERRSTS register it can generate an SERR SMI or SCI DMI special cycle when enabled in the ERRCMD SMICMD or SCI CMD registers respectively One and only one message type can be enabled SCI Command Registers Default RST Bit Access Value PWR Description 15 2 RO Oh Reserved RSVD SCI on Multiple Bit DRAM ECC Error DMESMI 1 The Host generates an SCI DMI message when it detects a multiple bit error reported by the DRAM 1 RW Ob Uncore controller 0 Reporting of this condition via SCI messaging is disabled For systems not supporting ECC this bit must be disabled SCI on Single bit ECC Error DSESMI 1 The Host generates an SCI DMI special cycle when the DRAM controller detects a single bit 0 RW Ob Uncore error 0 Reporting of this condition via SCI messaging is disabled For systems that do not support ECC this bit must be disabled ECCERRLOGO ECC Error Log 0 B D F Type 0 0 0 MCHBAR MCO Address Offset 40C8 40CBh Default Value 00000000h Access ROS V Size 32 bits BIOS Optimal Default 0000h This Channel 0 register is used to store the error status information in ECC enabled configurations along with
79. 14 TCK Period 15 ns 1 2 3 4 T15 TDI TMS Setup Time 6 5 ns 9 9 1 2 3 4 T16 TDI TMS Hold Time 6 5 ns 9 9 1 2 3 4 T17 TDO Clock to Output Delay 0 5 ns 9 9 1 2 3 4 T18 TRST Assert Time 2 9 9 1 2 3 4 5 Notes 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 Not 100 tested Specified by design characterization 3 It is recommended that TMS be asserted while TRST is being deasserted 4 Referenced to the rising edge of TCK 5 TRST is synchronized to TCK and asserted for 5 TCK periods while TMS is asserted Intel Xeon and Intel Core Processors For Communications Infrastructure Datasheet Volume 1 of 2 May 2012 108 Document Number 327405 001 Electrical Specifications n tel 9 11 5 SVID Signal Group AC Specifications Table 9 24 SVID Signal Group AC Specifications T Parameter Min Max Unit Notes 2 VIDSCLK period 38 90 ns VIDSOUT output valid delay wrt to BCLK 1 20 9 60 ns VIDSOUT output jitter 3 60 0 65 ns 3 VIDSOUT input setup time 1 00 ns 3 4 VIDSOUT input hold time 3 00 ns 3 4 VIDSCLK High Time 12 00 ns 5 VIDSCLK Low Time 12 00 ns 6 VIDSCLK Rise Time 2 50 ns 7 VIDSCLK Fall Time 2 50 ns 8 Duty Cycle 45 00 55 00 Notes T See the voltage regulator design guidelines for additional information 2 Platform support for SVID transitions is required for the processor to operate within
80. 160 Intel Xeon and Intel Core Processors For Communications Infrastructure Datasheet Volume 1 of 2 May 2012 8 Document Number 327405 001 Contents n tel 11 13 Error Syndrome eee nenne eene 161 Intel Xeon and Intel Core Processors For Communications Infrastructure May 2012 Datasheet Volume 1 of 2 Document Number 327405 001 9 n tel Contents Intel Xeon and Intel Core Processors For Communications Infrastructure Datasheet Volume 1 of 2 May 2012 10 Document Number 327405 001 Introduction 1 0 1 1 1 2 Table 1 1 May 2012 Introduction Purpose Scope Audience This document is to be used by Intel customers in place of the 2nd Generation Intel Core Processor Family Mobile Datasheet Volume 1 document 324803 This document contains the following processor information DC and AC electrical specifications Differential signaling specifications Pinout and signal definitions Interface functional descriptions Additional product feature information Configuration registers pertinent to the implementation and operation of the processor on its respective platform For register details see the latest version of the 2nd Generation Intel Core Processor Family Mobile Datasheet Volume 2 Related Documents See the following documents for additional information Processor Documents Document Documen
81. 19 VSS 24 VCC K29 VSS H20 VCC J25 VSS K30 0 21 26 VCCSA_VID K31 vss H22 vss 27 RSVD_48 K32 CFG 7 H23 VCC 28 55 55 24 VCC J29 RSVD_47 K34 CFG 10 H25 VSS J30 RSVD_57 K35 VSS H26 TRST 31 RSVD_45 K36 RSVD_24 H27 PROC_SELECT J32 vss L1 PCIE1_TX 14 H28 CATERR J33 PECI L2 PCIE1_TX 13 H29 UNCOREPWRGOOD 34 vss L3 vss H30 VSS J35 RSVD_25 L4 PCIE1_TX 11 H31 RESET J36 RSVD_50 L5 PCIE1_TX 11 H32 PROCHOT K1 VSS L6 VSS H33 VSS K2 PCIE1_TX 13 L7 PCIE2_TX 1 H34 RSVD_15 K3 PCIE1_TX 10 L8 PCIE2_TX 1 H35 RSVD_51 K4 VSS L9 VSS Intel Xeon and Intel Core Processors For Communications Infrastructure Datasheet Volume 1 of 2 122 May 2012 Document Number 327405 001 Processor Package Information n tel Ball Signal Ball Signal Ball Signal L10 PCIE2_TX 2 M15 vcc N20 L11 PCIE2_TX 2 M16 VSS N21 VCC L12 RSVD_8 M17 VCC N22 VSS L13 VSS M18 VCC N23 VCC L14 VCC M19 VSS N24 VCC L15 VCC M20 VCC N25 VSS L16 VSS M21 VCC N26 VCC L17 VCC M22 vss N27 vss L18 vcc M23 vcc N28 VCCIO L19 vss M24 vcc N29 VCCIO L20 vcc M25 vss N30 55 121 vcc M26 VCC_SENSE N31 CFG 3 L22 vss M27 VSS_SENSE N32 CFG 6 L23 vcc M28 vss N33 CFG 8 L24 vcc M29 vss N34 CFG 2 L25 vss M30 vss N35 CFG 12 L26 RSVD_55 M31 vss N36 CFG 15 L27 RSVD_56 M32 CFG 17 P
82. 20 Intel Xeon and Intel Core Processors For Communications Infrastructure May 2012 Datasheet Volume 1 of 2 134 Document Number 327405 001 Processor Package Information n tel Signal Ball Signal Ball Signal Ball VCC C21 VCC H23 VCC N23 VCC C23 vcc H24 VCC N24 VCC C24 VCC 114 vcc N26 VCC 014 15 12 015 17 14 017 18 15 vcc D18 vcc 20 vcc P17 VCC D20 VCC 121 vcc P18 VCC D21 VCC 23 vcc P20 VCC D23 VCC 24 VCC P21 VCC D24 VCC K14 VCC P23 VCC E14 VCC K15 VCC P24 VCC E15 VCC K17 VCC P26 VCC E17 VCC K18 VCC R12 VCC E18 VCC K20 VCC R14 VCC E20 VCC K21 VCC R15 VCC E21 VCC K23 VCC R17 VCC E23 VCC K24 VCC R18 VCC E24 VCC L14 VCC R20 VCC F14 VCC L15 VCC R21 VCC F15 VCC L17 VCC R23 VCC F17 VCC L18 VCC R24 VCC F18 VCC L20 VCC R26 VCC F20 VCC L21 VCC T12 VCC F21 VCC L23 VCC T14 VCC F23 VCC L24 VCC T15 VCC F24 VCC M14 VCC T17 VCC G14 VCC M15 VCC T18 VCC G15 VCC M17 VCC T20 VCC G17 VCC M18 VCC T21 VCC G18 VCC M20 VCC T23 VCC G20 VCC M21 VCC T24 VCC G21 VCC M23 VCC T26 VCC G23 VCC M24 VCC 012 G24 vcc N12 VCC U14 H14 14 U15 VCC H15 VCC N15 VCC U17 VCC H17 VCC N17 VCC U18 VCC H18 VCC N18 VCC 020 H20 VCC N20 vcc U21 VCC H21 VCC N21 VCC 023 Intel X
83. 24 15 vcc w20 VCC Y25 55 16 vss W21 VCC Y26 VCC V17 VCC 22 VSS Y27 VCCIO V18 VCC W23 VCC Y28 vss 19 vss w24 VCC Y29 VCCIO 20 vcc 25 VSS Y30 VCCIO V21 vcc w26 VCC Y31 55 V22 VSS W27 VCCIO Y32 VSS V23 VCC w28 VSS Y33 vss 24 vcc w29 VCCIO Y34 vss 25 vss W30 VCCIO 5 vss 26 vcc W31 VSS Y36 vss V27 VSS 32 SA_DQS 6 1 VCCIO V28 VCCI O w33 SA_DQ 52 AA2 VCCI O V29 VCCI O W34 SA_DQ 53 VCCIO VCCIO W35 SA DQI 49 AAA VCCIO 31 vss W36 SA_DQ 48 AA5 VCCIO 32 SA_DQS 6 Y1 VCCIO AA6 VCCIO 33 SA_DQ 51 Y2 VCCIO 7 VCCIO 34 SA_DQ 50 VCCIO AA8 vss V35 SA DQ 54 Y4 VCCIO AA9 VCCSA V36 SA_DQ 55 Y5 VCCIO AA10 VSS W1 DMI TX 3 Y6 VCCIO 11 VSS W2 VSS Y7 VCCIO AA12 VCC w3 VSS Y8 VCCIO AA13 VSS WA VSS Y9 VCCSA AA14 VCC W5 DMI_RX 3 Y10 VSS AA15 VCC w6 vss Y11 VCCSA AA16 VSS W7 VCCIO Y12 VCC AA17 VCC w8 VCCSA Y13 vss AA18 VCC Intel Xeon and Intel Core Processors For Communications Infrastructure May 2012 Datasheet Volume 1 of 2 Document Number 327405 001 125 Processor Package Information Ball Signal Ball Signal Ball Signal AA19 VSS AB24 VCCIO AC29 VCCIO AA20 VCC AB25 VSS AC30 VCCIO AA21 VCC AB26 VCCIO AC31 VSS AA22 VSS AB27 VCCIO AC32 V
84. 24 SA_DQ 37 AJ31 RSVD_33 A33 SA_CKE 0 AR18 SA_DQ 38 AG30 RSVD_34 G33 SA_CKE 1 AP18 SA_DQ 39 AG31 Intel Xeon and Intel Core Processors For Communications Infrastructure May 2012 Datasheet Volume 1 of 2 132 Document Number 327405 001 Processor Package Information intel Signal Ball Signal Ball Signal Ball SA_DQ 4 AF4 SA_DQS 2 AH10 SB_CK 0 AH21 SA_DQ 40 AB36 SA_DQS4 3 AM10 SB_CK 1 21 SA_DQ 41 AB35 SA_DQS 4 AH30 SB_CK 2 AK22 SA_DQ 42 AA34 SA_DQS4 5 AB32 SB_CK 3 AG21 SA_DQ 43 AA33 SA_DQS 6 32 SB_CK 0 AH22 SA_DQ 44 AB33 SA_DQS 7 T32 SB_CK 1 AK21 SA_DQ 45 AB34 SA_DQS 8 AM13 SB_CK 2 AJ22 SA_DQ 46 AA35 SA_ECC_CB 0 AR13 SB_CK 3 AG22 SA_DQ 47 AA36 SA_ECC_CB 1 AT13 SB_CKE 0 AL15 SA_DQ 48 W36 SA_ECC_CB 2 AP14 SB_CKE 1 AG16 SA_DQ 49 W35 SA_ECC_CB 3 AN14 SB_CKE 2 AF16 SA_DQ 5 AF2 SA_ECC_CB 4 AN13 SB_CKE 3 AT16 SA_DQ 50 34 SA_ECC_CB 5 AP13 SB_CS 0 AG25 SA_DQ 51 33 SA_ECC_CB 6 AT14 SB_CS 1 AH27 SA_DQ 52 33 SA_ECC_CB 7 AR14 SB_CS 2 AT27 SA_DQ 53 34 SA_MA 0 AN25 SB_CS 3 AH28 SA_DQ 54 V35 SA MA 1 AM21 SB DIMM VREFDQ AK16 SA DQI 55 36 SA MA 10 AL25 SB DQIO AC3 SA DQ 56 T36 SA MA 11 AK19 SB DQ 1 1 SA_DQ 57 T35 SA MA 12 AN18 SB DQ 10 AK8 SA_DQ 58 R34 SA_MA 13 AM28 SB DQ 11 AK7 SA DQ 59 R33 SA MA 14 AL18
85. 3 SA_ECC_CB 1 14 SA_ECC_CB 6 AT15 VSS Intel Xeon and Intel Core Processors For Communications Infrastructure Datasheet Volume 1 of 2 130 May 2012 Document Number 327405 001 Processor Package Information Table 10 2 Alphabetical Signal Listing ntel Signal Ball Signal Ball Signal Ball BCLK P6 DMI_TX 0 R1 PCIE1_TX 10 J3 BCLK P7 DMI_TX 1 T1 PCIE1_TX 11 15 BPM 0 D28 DMI_TX 2 v2 PCIE1_TX 12 N5 BPM 1 C27 DMI_TX 3 v1 PCIE1_TX 13 K2 2 C26 PCIE_ICOMPI J1 PCIE1_TX 14 M1 BPM 3 D26 PCIE ICOMPO F1 1 1_ 15 M3 BPM 4 A26 PCIE RCOMPO C12 PCIE1_TX 2 10 BPM 5 B26 PCIE1_RX 0 C9 PCIE1_TX 3 K9 BPM 6 E26 PCIE1_RX 1 A9 1 1_ 4 G9 7 F26 PCIE1_RX 10 C4 PCIE1_TX 5 H8 CATERR H28 PCIE1 RX 11 D3 PCIE1_TX 6 7 CFG 0 K30 PCIE1_RX 12 E2 PCIE1_TX 7 G6 CFG 1 L30 PCIE1_RX 13 F4 PCIE1_TX 8 5 CFG 10 K34 PCIE1_RX 14 G3 PCIE1_TX 9 K6 CFG 11 M34 PCIE1_RX 15 G1 PCIE1_TX 0 G11 CFG 12 N35 PCIE1_RX 2 D9 PCIEl TX4 1 H11 CFG 13 L35 PCIE1 RX 3 E7 1 10 14 M36 PCIE1_RX 4 B7 PCIEl TX4 11 L4 CFG 15 N36 PCIE1_RX 5 C6 PCIEl TX4 12 NA CFG 16 L33 PCIE1_RX 6 A5 PCIE1
86. 327405 001 3 Contents 1 0 Introduction aa aqha 11 1 1 Purpose Scope 11 1 2 Related Documents 11 1 3 13 2 0 Product OVerVIeW 15 2 1 Product Feat res su uu oie o e E ia Tres a esce ia Pea waka kamanisa 17 2 2 Processor PR CONUM ANE C ELEME 17 2 3 Supported sese me memes meses nnn 17 2 4 Interface Features socer eren ete 17 2 4 1 System Memory Support 17 24 2 jIPCI EXDr8SS Ri RT aue fan nune UR 18 2 4 3 Direct Media Interface DMI 20 2 4 4 Platform Environment Control Interface 20 2 5 Power Management 21 2541 PROCESSOR CONC FUR DR rac OR aon FO RR 21 DDD gt EORUM 21 2 5 3 Memory Controller erroe eri adie 21 DAT MN PCI EXPROSS EUM 21 25 pawa aaa ahus 21 2 6 Thermal Management
87. 327405 001 Intel Xeon and Intel Core Processors For Communications Infrastructure Datasheet Volume 1 of 2 71 intel Table 8 2 Table 8 3 Memory Channel A Sheet 2 of 2 Signal Description Signal Name Description aisi Butter ype CAS Control Signal Used with SA_RAS and o SA_CAS SA_WE along with SA_CS to define the SRAM DDR3 Commands Data Strobes SA_DQS 7 0 and its complement SA DOSI7 0 signal group make up a differential strobe pair s d The data is captured at the crossing point of i 3 _005 7 0 SA_DQS 7 0 and its SA_DQS 7 0 during read DDR and write transactions Data Strobes SA DQS 8 is the data strobe for the ECC check data bits SA_DQ 71 64 SA_DQS 8 is the complement strobe for the SA_DQS 8 ECC check data bits SA DQ 71 64 1 0 SA DQS 8 The data is captured at the crossing point of DDR3 SA_DQS 8 0 and its SA 005 8 0 during read and write transactions Note Not required for non ECC mode Data Bus Channel A data signal interface to the 1 0 SA DQI63 0 SDRAM data bus DDR3 ECC Data Lines Data Lines for ECC Check Byte 1 0 SA_ECC_CB 7 0 for Channel A DORS Note Not required for non ECC mode Memory Address These signals are used to o SA_MA 15 0 provide the multiplexed row and column address to the SDRAM DDR3 SDRAM Differential Clock Channel A SDRAM Differential clock signal pair The crossing of the SA_CK 3 0 SA om i positive ed
88. 45 which must be left unconnected Terminated RESERVED These pins must be shorted together and tied to VCCP through 24 9 Q RSVD 22 RSVD_33 RSVD 44 1 resistor CMOS PCI Express Based nterface Signals PCI Express Interface Signals Description Direction Buffer Signal Name Type doe inei n a and th d tied to VCCIO ese pins must be shorted together and tied to POIESICOMPO through 24 9 Q 1 resistor PCIE_RCOMPO PCIE1_RX 15 0 PCIE1_RX 15 0 PCI Express Receive Differential Pair I PCI Express PCIE1_TX 15 0 PCIE1_TX 15 0 PCI Express Transmit Differential Pair Express PCIE2_RX 3 0 PCIE2_RX 3 0 PCI Express Receive Differential Pair x4 Port PCI Express PCIE2_TX 3 0 PCIE2 TX4 3 0 PCI Express Transmit Differential Pair x4 Port O PCI Express DMI DMI Processor to PCH Serial I nterface Description Direction Buffer Signal Name Type DMI_RX 3 0 DMI Input from PCH Direct Media Interface DMI_RX 3 0 receive differential pair DMI DMI_TX 3 0 DMI Output to PCH Direct Media Interface 0 DMI_TX 3 0 transmit differential pair DMI Document Number 327405 001 Intel Xeon and Intel Core Processors For Communications Infrastructure Datasheet Volume 1 of 2 75 Table 8 8 8 7 Table 8 9 Note PLL Signals PLL Signals Signal Description Sig
89. 5 001 109 intel Electrical Specifications Figure 9 3 Differential Clock Differential Measurements lt Clock Period Differential gt lt Positive Duty Oyde Differentid gt lt Negative Duty Oyde Differential y 0 0V Qoc a Fall lt lt Ee Exe Fate Fate Mh 150 0 0V MI mex 150 GQOocka Intel Xeon and Intel Core Processors For Communications Infrastructure Datasheet Volume 1 of 2 110 May 2012 Document Number 327405 001 Electrical Specifications Figure 9 4 Differential Clock Single Ended Measurements Y V max Clock Vcross max Vcross min Clock V min Clock Vcross delta Clock Clock Vcross median Clock Clock Vcross AR 75mV Oe NA Vcross median Vcross median 75mV Clock Figure 9 5 DDR3 Command Control and Clock Timing Waveform CK IMC CK IMC BIOS Delay MA BS RAS b CAS WE IMC Tcmd_co Tcmd cs Tcmd_cs lt gt lt Control Signals IMC May 2012 Document Number 327405 001 Intel Xeon and Intel Core Processors For Communications Infrastructure Datasheet Volume 1 of 2 111 n tel Electrical Specifications
90. 5 1 39000 1 1 1 0 0 1 1 0 E 6 1 39500 1 1 1 0 0 1 1 1 E 7 1 40000 1 1 1 0 1 0 0 0 8 1 40500 1 1 1 0 1 0 0 1 9 1 41000 1 1 1 0 1 0 1 0 1 41500 1 1 1 0 1 0 1 1 1 42000 1 1 1 0 1 1 0 0 1 42500 1 1 1 0 1 1 0 1 D 1 43000 1 1 1 0 1 1 1 0 1 43500 1 1 1 0 1 1 1 1 1 44000 1 1 1 1 0 0 0 0 0 1 44500 1 1 1 1 0 0 0 1 1 1 45000 1 1 1 1 0 0 1 0 2 1 45500 1 1 1 1 0 0 1 1 3 1 46000 1 1 1 1 0 1 0 0 4 1 46500 1 1 1 1 0 1 0 1 5 1 47000 1 1 1 1 0 1 1 0 6 1 47500 1 1 1 1 0 1 1 1 7 1 48000 Intel Xeon and Intel Core Processors Communications Infrastructure Datasheet Volume 1 of 2 88 May 2012 Document Number 327405 001 Electrical Specifications Table 9 1 IMVP7 Voltage Identification Definition Sheet 8 of 8 VID7 VID6 VID5 VID4 VID3 VID2 VID1 VIDO HEX Vcc Max 1 1 1 1 1 0 0 0 8 1 48500 1 1 1 1 1 0 0 1 9 1 49000 1 1 1 1 1 0 1 0 1 49500 1 1 1 1 1 0 1 1 1 50000 1 1 1 1 1 1 0 0 1 50500 1 1 1 1 1 1 0 1 D 1 51000 1 1 1 1 1 1 1 0 F E 1 51500 1 1 1 1 1 1 1 1 F F 1 52000 9 5 System Agent SA Vcc VID The VccSA is configured by the processor output pin VCCSA_VID intel VCCSA_VID output default logic state is low for the processor Logic high is reserved for future processor compatibility Note During boot VCCSA is 0 9 volts T
91. 50 C0 Full On Full GO 50 C1 C1E Auto Halt On Auto Halt GO 50 C3 Deep Sleep On Deep Sleep GO so C6 C7 Deep Power Down G1 53 Power off Off except RTC Suspend to RAM G1 54 Power off Off except RTC Suspend to Disk G2 55 Power off Off except RTC Soft Off G3 NA Power off Power off Hard off Processor Core Power Management While executing code Enhanced Intel SpeedStep Technology optimizes the processor s frequency and core voltage based on workload Each frequency and voltage operating point is defined by ACPI as a P state When the processor is not executing code it is idle A low power idle state is defined by ACPI as a C state In general lower power C states have longer entry and exit latencies Document Number 327405 001 Intel Xeon and Intel Core Processors For Communications Infrastructure Datasheet Volume 1 of 2 49 intel 6 2 1 6 2 2 Note Figure 6 2 Power Management Enhanced Intel SpeedStep Technology The following are the key features of Enhanced Intel SpeedStep Technology Multiple frequency and voltage points for optimal performance and power efficiency These operating points are known as P states Frequency selection is software controlled by writing to processor MSRs The voltage is optimized based on the selected frequency and the number of active processor cores If the target frequency is higher than the current frequency Vcc is ramped up in step
92. 6 controller is mapped to Function 0 The x8 controller is mapped to Function 1 The x4 controller is mapped to Function 2 The additional x4 controller for lanes Port 2 is mapped to Device 6 Function 0 Port 2 is not available on 1 Core SKUs see Table 5 1 Base Features by SKU 3 of the 4 controllers create Port 1 and can automatically operate on lower lane width modes allowing up to 3 simultaneous operating devices on these 16 lanes Bifurcation details are described in Section 3 2 3 PCI Express Port Bifurcation and the hardware straps required to enable the x16 x8 and the x4 controllers are described in Section 3 2 4 PCI Express Lanes Connection The fourth controller is a single dedicated controller which creates the x4 Port 2 that enumerates on Device 6 Port 2 can be configured to operate in 1x4 1x2 or 1x1 mode but there are no hardware straps The controllers in Port 1 cannot be used to function with the controller in Port 2 Therefore the x16 lanes of Port 1 must not be combined with the x4 lanes of Port 2 PCI Express Related Register Structures PCI PCI Bridge PCI Express Device Port 1 representing root PCI Express port Device 1 PCI Compatible Host Bridge Device Device 0 Function 0 1 2 PCI PCI Bridge representing root PCI Express port Device 6 PCI Express Port 2 Device Only the 3 controllers Port 1 can
93. 725C 8 E3 1125C 46 E3 1105C 26 ynamic Current step Icc_Dyn_VID1 size in VID1 i3 2115C 24 A 11 12 B915C 18 725C 8 didt VCC ICC Slew Time 150 5 13 50 15 TOLvcc Voltage Tolerance PS1 12 mV 8 10 PS2 PS3 11 5 Intel Xeon and Intel Core Processors For Communications Infrastructure Datasheet Volume 1 of 2 May 2012 94 Document Number 327405 001 Electrical Specifications intel Table 9 5 Processor Core VCC DC Voltage and Current Specifications Sheet 2 of 2 Product Symbol Parameter Number Min Typ Max Unit Note PSO amp Icc gt 15 TDC 30 PSO amp lt 30 Se Ripple Ripple Tolerance S mV 8 10 PS1 13 PS2 7 5 18 5 PS3 7 5 27 5 VOvS_Max Max Overshoot Voltage 50 mV Max Overshoot Time tOvS_Max Duration 10 us VR Step VID resolution 5 mV E3 1125C 1 9 E3 1105C 1 9 Processor Loadline Slope 13 2115C 2 9 B915C 2 9 725C 2 9 Notes 1 These specifications have been updated with characterized data from silicon measurements 2 Each processor is programmed with a maximum valid voltage identification value VID which is set at manufacturing and cannot be altered Individual maximum SVID values are calibrated during manufacturing such that two processors at the same frequency may have different settings within the SVID range This differs from the SVID employed by the processor during
94. AL31 vss AE12 vss AJ9 vss AL32 VSS AE13 VSS AJ12 VSS AM6 VSS AE14 VSS AJ15 VSS AM9 VSS AE29 VSS AJ17 VSS AM12 VSS AE30 VSS AJ20 VSS AM15 Intel Xeon and Intel Core Processors For Communications Infrastructure May 2012 Datasheet Volume 1 of 2 140 Document Number 327405 001 Processor Package Information n tel Signal Ball Signal Ball vss AM30 vss AR26 vss AM33 VSS AR29 VSS AM34 VSS AR34 VSS AM35 VSS AR35 VSS AN1 VSS AT3 VSS AN6 VSS AT6 VSS AN9 VSS AT9 VSS AN12 VSS AT12 VSS AN15 VSS AT15 VSS AN17 VSS AT33 VSS AN20 VSS AT34 VSS AN23 VSS_SENSE M27 VSS AN26 VSS_SENSE_VCCIO AD29 vss AN29 vss AN30 vss AN33 vss AN36 VSS AP1 VSS AP2 VSS AP4 vss AP5 vss AP6 vss AP9 VSS AP12 VSS AP15 VSS AP25 VSS AP30 VSS AP33 VSS AP34 VSS AP35 VSS AP36 VSS AR2 VSS AR3 VSS AR6 VSS ARQ VSS AR12 VSS AR15 VSS AR17 VSS 20 vss AR23 vss AR25 Intel Xeon and Intel Core Processors For Communications Infrastructure May 2012 Datasheet Volume 1 of 2 Document Number 327405 001 141 n tel Processor Ball and Package Information PCIE1 vss vss asap 1 1_ 1 1_ 1 1_ 1 1_ AM 1_ 7 81 Tx 9 TXL11 TX 12 PCIE1_ PCIE PCIEl PCIE2_ 7 TX 6 TX 9 BAS Coke PCIE1_ P
95. AP36 VSS AM27 SA_ODT 2 AN32 SB_DQ 35 AR2 vss AM28 SA_MA 13 AN33 VSS AR3 VSS AM29 VDDQ AN34 SB_DQ 44 AR4 VCCPLL AM30 VSS AN35 SB_DQ 40 AR5 VCCPLL AM31 SB_DQS 4 AN36 VSS AR6 VSS AM32 SB_DQS 4 AP1 vss AR7 SB_DQ 24 Intel Xeon and Intel Core Processors For Communications Infrastructure May 2012 Datasheet Volume 1 of 2 Document Number 327405 001 129 Processor Package Information Ball Signal Ball Signal AR8 SB_DQ 31 AT16 SB_CKE 3 ARQ VSS AT17 VDDQ AR10 SA_DQ 24 AT18 SB MA 14 11 SA DQI31 AT19 SB MA 12 AR12 VSS AT20 VDDQ AR13 SA_ECC_CB 0 AT21 SB_MA 3 AR14 SA ECC CB 7 AT22 SB 2 15 VSS AT23 VDDQ 16 SM VREF AT24 SM RCOMP 1 AR17 VSS AT25 VDDQ AR18 SA_CKE 0 AT26 VDDQ AR19 SB_MA 9 27 SB_CS 2 AR20 VSS AT28 SB_CAS AR21 SA MA 5 AT29 SM RCOMP O AR22 SB MA 1 AT30 SM RCOMPI2 AR23 VSS AT31 SB_DQ 37 AR24 SB_MA O AT32 SB_DQ 39 AR25 VSS VSS AR26 VSS AT34 VSS AR27 SA_BS 0 AR28 SB_ODT 2 AR29 VSS AR30 RSVD_3 AR31 SB_DQ 33 AR32 SB_DQ 38 AR33 RSVD_2 AR34 VSS AR35 VSS AT3 VSS AT4 VCCPLL AT5 VCCPLL AT6 VSS AT7 SB DQ 25 AT8 SB DQ 30 AT9 VSS AT10 SA_DQ 25 11 SA_DQ 30 12 vss AT1
96. B I HB iL O0 N QUN IE iB iB EB ONAUNBWNFO 10 2 11 1 11 2 11 3 11 4 11 5 11 6 11 7 11 8 11 9 11 10 11 11 11 12 5 em D Contents Memory Reference and Compensation rr 74 Reset and Miscellaneous 510 74 PCI Express Interface Signals ctetu err b er ERR ua Us Er TER UR A RERO 75 Processor to PCH Serial 1 eee memes 75 dEEDDIIEM TT 76 ILAP Signal ditus muta eet dup 76 Error and Thermal Protectloh iore Fen tiem orn E versas paka Lr png 77 Power Sequendcihig ERNEA ERIni 78 Processor Power Signals u u saa na dd aad 78 Sense PifiSuuuu e ptt 79 Future Compatibiliibyu T 79 Processor Internal Pull Up Pull Down ccc 79 IMVP7 Voltage Identification Definition cee mmm 82 VGCSA VID GonflglratiOn ccoi i 89 Signal EP 90 Storage Condition Ratings orc eere eter rH RE KEHRT read cera kcu 93 Processor Core VCC DC Voltage and Current Specifications 94 Processor Uncore VCCIO Supply DC Voltage and Current Specifications 96 Memory Controller VDDQ Supply DC Voltage and Curr
97. B_DQS 6 AG33 SB_WE AG24 SB DQ 36 AN31 SB DQS 7 AD32 SM DRAMPWROK AF19 SB DQ 37 AT31 SB DQS 8 14 SM_DRAMRST AN16 SB_DQ 38 AR32 SB_DQS 0 5 SM_RCOMP 0 AT29 SB_DQ 39 AT32 SB_DQS 1 AH7 SM_RCOMP 1 AT24 SB_DQ 4 AC4 SB_DQS 2 AM4 SM_RCOMP 2 AT30 SB DQ 40 AN35 SB_DQS 3 AM7 SM_VREF AP16 SB_DQ 41 AL35 SB_DQS 4 AM31 SM_VREF AR16 SB_DQ 42 AK34 SB_DQS 5 AM36 TCK D30 SB_DQ 43 AK33 SB_DQS 6 AH33 TDI E30 SB DQ 44 AN34 SB_DQS 7 AE32 TDO L29 SB_DQ 45 AL34 SB_DQS 8 AH13 THERMTRIP G31 SB_DQ 46 AL33 SB_ECC_CB 0 AG13 TMS F30 SB_DQ 47 AK35 SB_ECC_CB 1 AG14 TRST H26 SB_DQ 48 AH35 SB_ECC_CB 2 AK13 UNCOREPWRGOOD H29 SB_DQ 49 AH36 SB_ECC_CB 3 AK14 VCC A14 SB_DQ 5 AC2 SB_ECC_CB 4 AF13 VCC A15 SB_DQ 50 AG34 SB_ECC_CB 5 AF14 VCC A17 SB_DQ 51 AF36 SB_ECC_CB 6 AJ13 VCC A18 SB_DQ 52 AJ36 SB_ECC_CB 7 AJ14 VCC A20 SB_DQ 53 AH34 SB_MA 0 AR24 21 SB_DQ 54 AG36 SB_MA 1 AR22 VCC A23 SB_DQ 55 AG35 SB_MA 10 AH24 VCC A24 SB_DQ 56 AE34 SB_MA 11 AG18 VCC B14 SB_DQ 57 AE35 SB_MA 12 AT19 B15 SB_DQ 58 AD34 SB MA 13 AJ28 B17 SB_DQ 59 AD33 SB MA 14 AT18 B18 SB_DQ 6 AD1 SB MA 15 AJ16 VCC B20 SB_DQ 60 AD31 SB_MA 2 AT22 vcc B21 SB_DQ 61 AE33 SB MA 3 AT21 B23 SB_DQ 62 AD35 SB_MA 4 AH19 B24 SB_DQ 63 AD36 SB MA 5 AJ19 VCC C14 SB_DQ 7 AD2 SB MA 6 AH18 15 SB_DQ 8 AG7 SB_MA 7 AG19 VCC C17 SB_DQ 9 AG8 SB_MA 8 AJ18 vcc C18 SB_DQS 0 AD5 SB MA 9 AR19
98. CC check bits are generated 1 per 8 bits of data by XORing a particular combination of the written bits with an associated Check Bit The result of this function creates a syndrome byte that is visible via Error Syndrome ERRSYND ECCERRLOGO CO ECC Error Log 0 or ECCERRLOGO C1 ECC Error Log 0 Table 11 13 provides a lookup of the ERRSYND and defines the failing data bit Table 11 13 Error Syndrome ERRSYND Sheet 1 of 3 May 2012 Syndrome DQ CB ERRSYND Bit Locator Locator 0x00 No Error 0x01 64 CBO Document Number 327405 001 Intel Xeon and Intel Core Processors For Communications Infrastructure Datasheet Volume 1 of 2 161 intel Table 11 13 Error Syndrome ERRSYND Sheet 2 of 3 ERRSYND BitLocator 0x02 65 CB1 0x04 66 CB2 0x07 60 DQ60 0x08 67 CB3 0x0B 36 DQ36 0x0D 27 DQ27 OxOE 3 DQ3 0x10 68 CB4 0x13 55 DQ55 0x15 10 DQ10 0x16 29 DQ29 0x19 45 DQ45 Ox1A 57 DQ57 0x1C 0 DQ0 1 15 2015 0 20 69 5 0 23 39 DQ39 0x25 26 DQ26 0x26 46 DQ46 0x29 61 DQ61 Ox2A 9 DQ9 0x2C 16 DQ16 2 23 2023 0 31 63 2063 0 32 47 2047 0 34 14 0014 0 38 30 2030 0 40 70 CB6 0x43 6 DQ6 0x45 42 DQ42 0x46 62 DQ62 0x49 12 DQ12 4 25 2025 0x4C 32 DQ32 0x4F 51 DQ51 0x51 2 DQ2 0x52 18 DQ18 0x54 34 DQ34 0x58 50 DQ50 0x61 21 DQ21
99. CIE1 RX 10 D7 VSS C5 VSS D8 PCIE1 RX 2 C6 PCIE1 RX 5 D9 PCIE1 RX 2 C7 PCIE1 RX 5 D10 PCIE2_RX 0 C8 VSS D11 PCIE2 RX 1 C9 PCIE1 RX 0 D12 PCIE2 RX 1 C10 PCIE1 RX 0 D13 VSS C11 VSS D14 12 PCIE_RCOMPO D15 VCC May 2012 Document Number 327405 001 Processor Package Information intel Ball Signal Ball Signal Ball Signal D16 vss E21 VCC F26 BPM 7 D17 22 VSS F27 RSVD 43 D18 E23 VCC F28 PROC_DETECT D19 VSS E24 VCC F29 VSS D20 VCC E25 VSS F30 TMS D21 VCC E26 6 1 55 D22 VSS E27 RSVD_41 F32 RSVD_19 D23 VCC E28 PM_SYNC F33 RSVD_16 D24 VCC E29 VIDSCLK F34 vss D25 VSS E30 TDI F35 RSVD_36 D26 3 1 VIDALERT F36 RSVD_17 D27 vss E32 RSVD_37 G1 PCIE1_RX 15 D28 BPM 0 E33 VSS G2 PCIE1_RX 14 D29 RSVD_44 E34 RSVD_38 G3 PCIE1_RX 14 D30 TCK E35 RSVD_18 G4 vss D31 vss E36 vss G5 vss D32 vss F1 PCIE_ICOMPO G6 PCIE1_TX 7 D33 RSVD_39 F2 vss G7 VSS D34 RSVD_20 F3 PCIE1_RX 13 G8 PCIE1_TX 4 D35 VSS F4 PCIE1_RX 13 G9 PCIE1_TX 4 D36 RSVD_40 F5 VSS G10 VSS E1 PCIE1_RX 12 F6 VSS G11 PCIE1_TX 0 E2 PCIE1_RX 12 F7 vss G12 PCIE1_TX 0 E3 vss F8 vss G13 vss E4 PCIE1_RX 8 F9 VSS G14 VCC E5 PCIE1_RX 8 F10 VSS G15 VCC E6 VSS F11 vss G16 vss E7 PCIE1_RX 3 F12 VSS G17 PCIE1_RX 3 F13 vss G18 VCC E9 VSS F14 VCC G19 VSS E10 VSS
100. CIE1_ PCIE2_ PCIE2_ PCIE1 PCIEl 1 1_ 1 2_ WA 4 TXLS TX 3 PCIE1_ PCIE1_ TX 4 TX 3 PCIE1 PCIE1_ 1 o PCIE1 PCIE1_ PCIE2 m re S vss vss vss vss vss vss vss vss vss vss vss Intel Xeon and Intel Core Processors For Communications Infrastructure Datasheet Volume 1 of 2 May 2012 142 Document Number 327405 001 Processor Package Information Figure 10 2 Ball Map Bottom View Upper Right Side w Y AA AB AC AD AE vss 55 55 AL AN SB DQ soi 55 SB DQ SB zs vss VSS VCCPLL VCCPLL AT SB DQI 8 SB DQI 9 55 SA_DQ 16 SA_DQI 22 vss SB DQ S 3 SB DQ S 3 vss SA_DQ S 3 SB DQI 19 vss vss SB _DQ SB DQ SB DQ SB DQ 28 29 24 25 SB _DQ SB DQ SB DQ SB DQ 27 26 31 30 vss 55 55 VSS SA DQ SA 5 DQI 28 29 24 25 VCCPLL vss VCCPLL vss SA_DQ 17 SB ECC _CB 0 SA 23 SB ECC _ 6 SA_DQ S 3 55 SA_DQ S 8 SA_DQI SA_DQ SA DQI SA DQ 27 26 55 55 SA_ECC SA_ECC 31 VSS SA_ECC _CB 4 CB 5 _CB 0 _CB 1 30 VSS SA_ECC SB_ECC _ 1 55 SB 1
101. Core i3 Processor 2115C Tj 0 100 2 3 4 Intel Pentium Processor B915C Intel Celeron Processor 725C Intel Xeon and Intel Core Processors For Communications Infrastructure Datasheet Volume 1 of 2 May 2012 62 Document Number 327405 001 intel 7 3 7 3 1 Note 7 3 1 1 Note 7 3 1 1 1 May 2012 Thermal Management Features This section covers thermal management features for the processor Processor Package Thermal Features This section covers thermal management features for the entire processor complex including the processor core and integrated memory controller hub and is referred to as processor package or package Occasionally the package operates in conditions that exceed its maximum allowable operating temperature This can be due to internal overheating or due to overheating in the entire system In order to protect itself and the system from thermal failure the package is capable of reducing its power consumption and thereby its temperature to attempt to remain within normal operating limits via the Adaptive Thermal Monitor The Adaptive Thermal Monitor can be activated when any package temperature monitored by a digital thermal sensor DTS meets or exceeds its maximum junction temperature specification Tj Ax and asserts PROCHOT The thermal control circuit TCC can be activated prior to Tj max by use of the TCC activation offset The assertion of PROCHOT activates t
102. D F Type 0 0 0 PCI Address Offset CA CBh Default Value 0000h Access RO RW Size 16 bits BIOS Optimal Default 0000h This register controls the Host Bridge responses to various system errors Since the Host Bridge does not have an SERRB signal SERR messages are passed from the Processor to the PCH over DMI When a bit in this register is set a SERR message will be generated on DMI whenever the corresponding flag is set in the ERRSTS register The actual generation of the SERR message is globally enabled for Device 0 via the PCI Command register Intel Xeon and Intel Core Processors For Communications Infrastructure Document Number 327405 001 Datasheet Volume 1 of 2 153 intel Table 11 4 Error Command Registers Processor Configuration Registers Default RST a Bit Access Value PWR Description 15 2 RO Oh Reserved RSVD SERR Multiple Bit DRAM ECC Error DMERR 1 The Host Bridge generates an SERR message over DMI when it detects a multiple bit error reported by the DRAM controller 1 Uncore 0 Reporting of this condition via SERR messaging is disabled For systems not supporting ECC this bit must be disabled SERR on Single bit ECC Error DSERR 1 The Host Bridge generates SERR special cycle over DMI when the DRAM controller detects a single bit error n Uncore 0 Reporting of this condition via SERR messaging is disabled For systems that do not
103. DQS 7 0 and its complement signal group make up a differential strobe pair The 1 0 SB_DQS 7 0 SB_DQS 7 0 data is captured at the crossing point of 3 SB_DQS 7 0 and its SB_DQS 7 0 during read DDR and write transactions Data Strobes SB_DQS 8 is the data strobe for the ECC check data bits SB_DQ 71 64 SB_DQS 8 is the complement strobe for the ECC SB_DQS 8 check data bits SB_DQ 71 64 1 0 SB 005 8 The data is captured at the crossing point of DDR3 T SB_DQS 8 0 and its SB_DQS 8 0 during read and write transactions Note Not required for non ECC mode Data Bus Channel B data signal interface to the 1 0 5 _00163 0 SDRAM data bus DDR3 ECC Data Lines Data Lines for ECC Check Byte 1 0 SB_ECC_CB 7 0 for Channel B 3 Note Not required for non ECC mode DDR Memory Address These signals are used to o SB_MA 15 0 provide the multiplexed row and column address to the SDRAM DDR3 SDRAM Differential Clock Channel B SDRAM _ 3 0 Differential clock signal pair The crossing of the o SB Ck 3 0 positive edge of SB CK and the negative edge of its DDR3 3 0 complement SB CK are used to sample the command and control signals on the SDRAM Clock Enable 1 per rank Used to Initialize the SDRAMs during power up o SB_CKE 3 0 Power down SDRAM ranks DDR3 Place all SDRAM ranks into and out of self refresh during STR Chip Select 1 per rank Used to select particular o SB_CS 3 0 SDRAM components during the active state
104. E ED E e E DE dp ED 8 5p DS DE ES No T T e Intel Xeon and Intel Core Processors For Communications Infrastructure Datasheet Volume 1 of 2 May 2012 34 Document Number 327405 001 Interfaces 3 2 5 Note Table 3 5 Note May 2012 intel Configuring PCle Lanes The controllers in Port 1 cannot be used to function with the controller in Port 2 Therefore the x16 lanes of Port 1 must not be combined with the x4 lanes of Port 2 The following details apply to the 3 controllers in Port 1 as Port 2 cannot be bifurcated The configuration of the PCle bus is statically determined by the pre boot software prior to initialization The pre boot software determines the configuration by looking at the two configuration pins CFG 6 5 that determine whether the additional 2 controllers of the 16 lanes need to be enabled or not These strap values are read upon power up and the pre boot software enables the appropriate number of controllers in use as follows Hardware Straps for PCle Controller Enabling Port 1 Only CFG 6 5 Mode 00 1x8 2x4 01 Reserved 10 2x8 11 default 1x16 No strapping is required to enable the additional four lanes lanes 16 19 in any of the permissible modes as it has a single dedicated controller The CFG 6 5 inputs have a default value of 1 1 if they are not terminated on the board
105. EMPLOYEES OF EACH HARMLESS AGAINST ALL CLAIMS COSTS DAMAGES AND EXPENSES AND REASONABLE ATTORNEYS FEES ARISING OUT OF DIRECTLY OR INDIRECTLY ANY CLAIM OF PRODUCT LIABILITY PERSONAL INJURY OR DEATH ARISING IN ANY WAY OUT OF SUCH MISSION CRITICAL APPLICATION WHETHER OR NOT INTEL OR ITS SUBCONTRACTOR WAS NEGLIGENT IN THE DESIGN MANUFACTURE OR WARNING OF THE INTEL PRODUCT OR ANY OF ITS PARTS Intel may make changes to specifications and product descriptions at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them The information here is subject to change without notice Do not finalize a design with this information The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published specifications Current characterized errata are available on request Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order Copies of documents which have an order number and are referenced in this document or other Intel literature may be obtained by calling 1 800 548 4725 or go to http www intel com en_US_01 Intel processor numbers are not a measure
106. Frequency Mode Non Critical to Function NCTF locations are typically redundant ground or NCTF non critical reserved so the loss of the solder joint continuity at end of life conditions will not affect the overall product functionality Nehalem Intel s 45 nm processor design follow on to the 45 nm Penryn design ODT On Die termination Platform Controller Hub The new 2009 chipset with centralized platform PCH capabilities including the main 1 interfaces along with power management manageability security and storage features Single Instruction Multiple Data SI MD instruction that computes the 128 PCLMULQDQ bit carry less multiplication of two 64 bit operands without generating and propagating carries PECI Platform Environment Control I nterface Processor The 64 bit single core or multi core component package The term processor core refers to Si die itself which can contain multiple execution cores Each execution core has an instruction cache data cache and 256 KB L2 cache All execution cores share the L3 cache Intel Xeon and Intel Core Processors For Communications Infrastructure Datasheet 1 of 2 13 intel Table 1 3 Terminology Sheet 2 of 2 Introduction Term Description PCU Power Control Unit A unit of DRAM corresponding four to eight devices in parallel ignoring Rank ECC These devices are usually but not always mounted on a single side of a DIMM scl System Control Interrupt Used
107. IO Y5 VCCIO AC14 VCC AA20 VCCIO Y6 VCCIO AC15 21 VCCIO Y7 VCCIO AC16 VCC 2 VCCIO Y8 VCCIO AC17 VCC AA24 VCCIO Y27 VCCIO AC18 Intel Xeon and Intel Core Processors For Communications Infrastructure May 2012 Datasheet Volume 1 of 2 136 Document Number 327405 001 Processor Package Information n tel Signal Ball Signal Ball Signal Ball VCCIO AC19 VDDQ AD17 VDDQ AT17 VCCIO AC20 VDDQ AD18 VDDQ AT20 VCCIO AC21 VDDQ AD21 VDDQ AT23 VCCIO AC22 VDDQ AD25 VDDQ AT25 VCCIO AC23 VDDQ AE15 VDDQ AT26 VCCIO AC24 VDDQ AE16 VIDALERT E31 VCCIO AC25 VDDQ AE17 VIDSCLK E29 VCCIO AC26 VDDQ AE18 VIDSOUT G26 VCCIO AC27 VDDQ AE19 VSS A3 VCCIO AC28 VDDQ AE20 VSS A4 VCCIO AC29 VDDQ AE21 VSS A7 VCCIO AC30 VDDQ AE22 vss A10 VCCIO AD10 VDDQ AE23 vss A13 VCCIO AD11 VDDQ AE24 VSS A16 VCCIO SENSE AD28 VDDQ AE25 VSS A19 VCCPLL ARA VDDQ AE26 VSS A22 VCCPLL AR5 VDDQ AE27 VSS A25 VCCPLL AT4 VDDQ AE28 VSS A27 VCCPLL AT5 VDDQ AF17 VSS A32 VCCSA N9 VDDQ AF20 VSS B2 VCCSA P9 VDDQ AF23 VSS B3 VCCSA P11 VDDQ AF24 VSS B6 VCCSA R9 VDDQ AF26 vss B9 VCCSA R11 VDDQ AH17 vss B12 VCCSA T8 VDDQ AH20 VSS B13 VCCSA T11 VDDQ AH23 VSS B16 VCCSA U9 VDDQ AH26 vss B19 VCCSA V9 VDDQ AK17 VSS B22 VCCSA V11 VDDQ AK20 VSS B25 VCCSA W8 VDDQ AK23 VSS B28 VCCSA W11 VDDQ AK26 VSS B29 VCCSA Y9 VDDQ AM17 vss B31 VCC
108. Intel Core Processors For Communications Infrastructure Datasheet Volume 1 of 2 May 2012 156 Document Number 327405 001 Processor Configuration Registers Table 11 8 Channel 0 ECC Error Log 1 11 7 s Default RST NM Bit Access Value PWR Description Error Column ERRCOL 31 16 ROS V 0000h Powergood This field holds the DRAM column address of the read transaction that had the ECC error Error Row ERRROW 15 0 ROS V 0000h Powergood This field holds the DRAM row page address of the read transaction that had the ECC error ECCERRLOGO C1 ECC Error Log O B D F Type Address Offset Default Value Access Size BIOS Optimal Default 0 0 0 MCHBAR MC1 44C8 44CBh 00000000h ROS V 32 bits 0000h This Channel 1 register is used to store the error status information in ECC enabled configurations along with the error syndrome and the rank and bank address information of the address block of main memory of which an error single bit or multi bit error has occurred The address fields represent the address of the first single or the first multiple bit error occurrence after the error flag bits in the ERRSTS register have been cleared by software A multiple bit error will overwrite a single bit error Once the error flag bits are set as a result of an error this bit field is locked and doesn t change as a result of a new error until the error flag is cleared by software Same is the
109. LVL4 I O read to the P BLK or by an MWAIT C7 instruction The core C7 state exhibits the same behavior as the core C6 state unless the core is the last one in the package to enter the C7 state If it is that core is responsible for flushing L3 cache ways The processor supports the C7s substate When an MWAIT C7 command is issued with a C7s sub state hint the entire L3 cache is flushed one step as opposed to flushing the L3 cache in multiple steps Core C7 State support is available for Quad and Dual Core processors Single Core processors do not support Core C7 State C State Auto Demotion In general deeper C states such as C6 or C7 have long latencies and have higher energy entry exit costs The resulting performance and energy penalties become significant when the entry exit frequency of a deeper C state is high Therefore incorrect or inefficient usage of deeper C states have a negative impact on power In order to increase residency and improve power in deeper C states the processor supports C state auto demotion There are two C State auto demotion options C6 C7 to C3 C7 C6 C3 To C1 The decision to demote a core from C6 C7 to C3 or C3 C6 C7 to C1 is based on each core s immediate residency history Upon each core C6 C7 request the core C state is demoted to C3 or C1 until a sufficient amount of residency has been established At that point a core is allowed to go into C3 C6 or C7 Each option can be run concurrently or indi
110. PCI e and DMI 1 2 Vccio 0 25UI 0 275 Vccio 0 25UI 1 2 Notes 1 These specifications are measured at processor 2 See Figure 9 13 for description of allowable Overshoot Undershoot magnitude and duration Figure 9 13 Maximum Acceptable Overshoot Undershoot Waveform Overshoot i i H H H 1 Overshoot lt Duration gt Undershoo Duration H i i VSS pm Undershoot 5 Intel Xeon Intel Core Processors For Communications Infrastructure May 2012 Document Number 327405 001 Datasheet Volume 1 of 2 117 n tel Electrical Specifications Intel Xeon and Intel Core Processors For Communications Infrastructure Datasheet Volume 1 of 2 May 2012 118 Document Number 327405 001 m e Processor Ball and Package Information n tel 10 0 Processor Ball and Package Information 10 1 Processor Ball Assignments Table 10 1 provides a listing of all processor pins ordered alphabetically by ball name Table 10 2 provides a listing of all processor pins ordered alphabetically by ball number Figure 10 1 Figure 10 2 Figure 10 3 and Figure 10 4 show the bottom view of the processor ballmap Intel Xeon and Intel Core Processors For Communications Infrastructure May 2012 Datasheet Volume 1 of 2 Document Number 327405 001 119 intel Table 10 1 Alphabetical Ball Listing Processor Ball and Package Informati
111. PCIE2_TX 1 L8 RSVD 37 E32 SA_CS 0 AK25 PCIE2_TX 2 L10 RSVD 38 E34 SA_CS 1 AN28 PCIE2_TX 3 K11 RSVD 39 D33 SA CS 2 AP28 PECI 33 RSVD_40 D36 SA_CS 3 AK27 PM_SYNC E28 RSVD_41 E27 SA_DIMM_VREFDQ AL16 PRDY K26 RSVD_42 C28 SA_DQ 0 AF3 PREQ G29 RSVD_43 F27 SA_DQ 1 AF1 PROC_DETECT F28 RSVD_44 D29 SA_DQ 10 AK3 PROC_SELECT H27 RSVD_45 J31 SA_DQ 11 AK4 PROCHOT H32 RSVD_46 K28 SA_DQ 12 AJ4 RESET H31 RSVD_47 J29 SA_DQ 13 AJ3 RSVD_1 AF18 RSVD_48 27 SA_DQ 14 AK1 RSVD_10 T6 RSVD_49 L28 SA_DQ 15 AK2 RSVD_11 G30 RSVD_50 36 SA_DQ 16 AG10 RSVD_12 B30 RSVD_51 H35 SA_DQ 17 AG11 RSVD_13 A30 RSVD_52 B35 SA_DQ 18 AK10 RSVD_14 A28 RSVD_53 B32 SA_DQ 19 AK11 RSVD_15 H34 RSVD_54 A34 SA_DQ 2 AG3 RSVD_16 F33 RSVD_55 L26 SA_DQ 20 AF10 RSVD_17 F36 RSVD_56 L27 SA_DQ 21 AF11 RSVD_18 E35 RSVD_57 J30 SA_DQ 22 AJ10 RSVD_19 F32 RSVD_6 N2 SA_DQ 23 AJ11 RSVD_2 AR33 RSVD_7 J12 SA_DQ 24 AR10 RSVD_20 D34 RSVD_8 L12 SA_DQ 25 AT10 RSVD_21 C33 RSVD_9 R6 SA_DQ 26 AP11 RSVD_22 B27 SA_BS 0 AR27 SA_DQ 27 AN11 RSVD_23 C36 SA_BS 1 AM25 SA_DQ 28 AN10 RSVD_24 K36 SA_BS 2 AM18 SA_DQ 29 AP10 RSVD_25 J35 SA_CAS AN27 SA_DQ 3 AG4 RSVD_26 C35 SA_CK 0 AM22 SA_DQ 30 AT11 RSVD_27 C32 _ 1 21 SA_DQ 31 AR11 RSVD_28 B34 SA_CK 2 AN24 SA_DQ 32 AK30 RSVD_29 C31 SA_CK 3 AL24 SA_DQ 33 AJ30 RSVD_3 AR30 SA_CK 0 AL22 SA_DQ 34 AF30 RSVD_30 A31 SA_CK 1 AN22 SA_DQ 35 AF31 RSVD_31 A29 _ 2 24 SA_DQ 36 AK31 RSVD_32 G34 SA_CK 3 AM
112. Refers to a Link or Port with eight Physical Lanes x16 Refers to a Link or Port with sixteen Physical Lanes ss Intel Xeon and Intel Core Processors For Communications Infrastructure Datasheet 1 of 2 14 May 2012 Document Number 327405 001 e Product Overview n tel 2 0 Product Overview The Intel Xeon and Intel Core Processors for Communications Infrastructure is a repackaging of the 2nd Generation Intel Core Mobile Processor family This document addresses pairing the Intel Xeon Intel Core Intel Pentium and Intel Celeron processors with an Intel Platform Controller Hub known as the PCH which is referred to as the Crystal Forest Platform This platform was developed to provide flexible design options powerful processor performance and acceleration services that include Intel QuickAssist Technology Figure 2 1 shows a block diagram of the Crystal Forest Platform Note The Intel Xeon Intel Core Intel Pentium and Intel Celeron processors for this platform are referred to in this document as the processor See Chapter 5 0 fora list of processor SKUs The processor is offered in either a Quad Core Dual Core or Single Core 1284 ball FC BGA Flip Chip Ball Grid Array package All of the processor offerings are fully pin compatible and provided in the same 37 5 x 37 5 mm FCBGA package size with a ball pitch of 1 016 mm The processor is a 64 bit mu
113. SA DQ 37 AK36 VSS AH27 SB_CS 1 32 vss AL1 vss AH28 SB_CS 3 AJ33 VSS AL2 VSS AH29 VSS AJ34 VSS AL3 vss AH30 SA_DQS 4 AJ35 VSS AL4 VSS AH31 SA_DQS 4 AJ36 SB_DQ 52 AL5 VSS AH32 VSS AK1 SA_DQ 14 AL6 vss AH33 SB_DQS 6 AK2 SA_DQ 15 AL7 vss AH34 SB_DQ 53 AK3 SA_DQ 10 18 vss AH35 SB_DQ 48 AK4 SA_DQ 11 19 vss AH36 SB_DQ 49 AK5 SA_DQS 1 AL10 VSS AJ1 SA DQI9 AK6 VSS AL11 VSS AJ2 SA DQI8 AK7 SB DQ 11 AL12 VSS AJ3 SA DQ 13 AK8 SB DQI10 AL13 VSS AJ4 SA DQ 12 AK9 VSS AL14 VSS AJ5 SA DQS 1 AK10 SA_DQ 18 AL15 SB_CKE 0 AJ6 vss AK11 SA_DQ 19 AL16 SA_DIMM_VREFDQ 7 SB_DQ 15 AK12 VSS AL17 VSS 8 SB_DQ 14 AK13 SB_ECC_CB 2 AL18 SA_MA 14 9 VSS AK14 SB_ECC_CB 3 119 SA_MA 8 AJ10 SA_DQ 22 AK15 VSS AL20 VSS 11 SA_DQ 23 AK16 SB DIMM VREFDQ AL21 VSS AJ12 VSS AK17 VDDQ AL22 SA_CK 0 AJ13 5 6 AK18 CKE 2 123 VSS AJ14 SB_ECC_CBI7 AK19 SA_MA 11 AL24 SA CK 3 AJ15 VSS AK20 VDDQ AL25 SA MA 10 AJ16 SB MA 15 AK21 SB_CK 1 AL26 VSS AJi7 VSS AK22 SB_CK 2 127 SA_ODT 0 Intel Xeon and Intel Core Processors For Communications Infrastructure Datasheet Volume 1 of 2 May 2012 128 Document Number 327405 001 e Processor Ball and Package I nformation n tel Ball Signal Ball S
114. SA Y11 VDDQ AM20 vss B33 VCCSA AA9 VDDQ AM23 vss C1 VCCSA AB9 VDDQ AM26 vss C2 VCCSA_VCCSENSE M10 VDDQ AM29 vss 5 VCCSA_VID J26 VDDQ AP17 vss C8 VCCSA VSSSENSE M9 VDDQ AP20 VSS C11 VDDQ AD13 VDDQ AP23 VSS C13 VDDQ AD14 VDDQ AP26 VSS C16 VDDQ AD15 VDDQ AP29 VSS C19 Intel Xeon and Intel Core Processors For Communications Infrastructure May 2012 Datasheet Volume 1 of 2 Document Number 327405 001 137 Processor and Package Information Signal Ball Signal Ball Signal Ball vss C22 vss F22 vss 32 VSS C25 VSS F25 VSS 134 55 29 VSS F29 vss K1 VSS C30 55 1 55 K4 vss C34 vss F34 vss K7 vss D1 vss G4 vss K10 vss D4 vss G5 vss K13 vss D7 vss G7 vss K16 vss D13 VSS G10 VSS K19 VSS D16 VSS G13 VSS K22 VSS D19 VSS G16 VSS K25 VSS D22 VSS G19 VSS K27 VSS D25 VSS G22 VSS K29 VSS D27 VSS G25 VSS K31 VSS D31 VSS G27 VSS K33 VSS D32 VSS G28 VSS K35 VSS D35 VSS G32 vss L3 vss E3 VSS G35 VSS L6 VSS E6 VSS H2 VSS L9 VSS E9 VSS H3 VSS L13 VSS E10 VSS H4 VSS L16 VSS E12 VSS H6 VSS L19 VSS E13 VSS H9 VSS L22 VSS E16 VSS H12 VSS L25 VSS E19 VSS H13 VSS L36 VSS E22 VSS H16 vss M2 VSS E25 VSS H19 VSS M4 VSS E33 VSS H22 VSS M5 VSS E36 VSS H25 VSS M8 VSS F2 VSS H30 VSS M13 VSS F5 VSS H33 VSS M16 VSS F6 VSS H36 VSS M19 VSS F7 VSS 12 55 M22 v
115. SB DQ 12 AF7 SA DQ 6 1 SA MA 15 AP19 SB DQ 13 AF8 SA_DQ 60 T33 SA_MA 2 AF22 SB_DQ 14 AJ8 SA_DQ 61 T34 SA _MA 3 AP22 SB_DQ 15 AJ7 SA_DQ 62 R35 SA MA 4 AF21 SB DQI16 AM3 SA DQI63 R36 SA MA 5 AR21 SB DQI17 AM2 SA DQI7 AG2 SA MA 6 AP21 SB DQI 18 AP3 SA DQI 8 AJ2 SA MAL7 AN19 SB DQ 19 AN5 SA_DQ 9 AJ1 SA MA 8 AL19 SB DQI2 AD3 SA DQS 0 AG5 SA MA 9 AM19 SB_DQ 20 AM1 SA_DQS 1 5 SA ODT 0 AL27 SB DQ 21 5 SA_DQS 2 AH11 SA_ODT 1 AL28 SB_DQ 22 AN2 SA_DQS 3 AM11 SA_ODT 2 AM27 SB_DQ 23 AN3 SA_DQS 4 AH31 SA_ODT 3 AK28 SB_DQ 24 AR7 SA_DQS 5 AA32 SA_RAS AP27 SB DQ 25 AT7 SA DQSI6 32 SA_WE AK24 SB_DQ 26 AP8 SA_DQS 7 R32 SB_BS 0 25 SB_DQ 27 AN8 SA_DQS 8 AM14 SB_BS 1 AJ24 SB_DQ 28 AN7 SA_DQS 0 AF5 SB_BS 2 AH16 SB_DQ 29 AP7 SA_DQS 1 AJ5 SB_CAS AT28 SB_DQ 3 AD4 Intel Xeon and Intel Core Processors For Communications Infrastructure May 2012 Datasheet Volume 1 of 2 Document Number 327405 001 133 Processor Package Information Signal Ball Signal Ball Signal Ball SB_DQ 30 AT8 SB_DQS 1 AH8 SB_ODT 0 AJ27 SB_DQ 31 AR8 SB_DQS 2 AN4 SB_ODT 1 AG27 SB_DQ 32 AP31 SB_DQS 3 AM8 SB_ODT 2 AR28 SB_DQ 33 AR31 SB_DQS 4 AM32 SB_ODT 3 AG28 SB_DQ 34 AP32 SB_DQS 5 AL36 SB_RAS AH25 SB_DQ 35 AN32 S
116. SS AA23 VCC AB28 VCCIO AC33 VSS AA24 VCC AB29 VCCIO AC34 VSS AA25 VSS AB30 VCCIO AC35 VSS AA26 VCC AB31 VSS AC36 VSS AA27 VSS AB32 SA _DQS 5 AD1 SB_DQ 6 AA28 VCCIO AB33 SA_DQ 44 AD2 SB DQI7 AA29 VCCIO AB34 SA DQ 45 AD3 SB DQI2 AA30 VCCIO AB35 SA_DQ 41 AD4 SB_DQ 3 AA31 VSS AB36 SA_DQ 40 AD5 SB_DQS 0 AA32 SA_DQS 5 AC1 SB_DQ 1 AD6 VSS AA33 SA_DQ 43 AC2 SB_DQ 5 AD7 VSS AA34 SA_DQ 42 AC3 SB_DQ 0 AD8 vss AA35 SA_DQ 46 AC4 SB_DQ 4 AD9 VSS AA36 SA_DQ 47 AC5 SB_DQS 0 AD10 VCCIO AB1 vss AC6 vss AD11 VCCIO AB2 vss AC7 VCCIO AD12 VSS AB3 vss AC8 VCCIO AD13 VDDQ AB4 vss AC9 VCCIO AD14 VDDQ AB5 VSS AC10 VCCIO AD15 VDDQ AB6 VSS 11 VCCIO AD16 VSS AB7 VCCIO AC12 VCCIO AD17 VDDQ AB8 VCCIO AC13 VCCIO AD18 VDDQ AB9 VCCSA AC14 VCCIO AD19 VSS AB10 VCCIO 15 VCCIO AD20 VSS AB11 VSS AC16 VCCIO AD21 VDDQ AB12 VCCIO 17 VCCIO AD22 VSS AB13 VSS AC18 VCCIO AD23 VSS AB14 VCCIO AC19 VCCIO AD24 VSS AB15 VCCIO AC20 VCCIO AD25 VDDQ AB16 VSS AC21 VCCIO AD26 VSS AB17 VCCIO AC22 VCCIO AD27 VSS AB18 VCCIO AC23 VCCIO AD28 VCCIO_SENSE AB19 VSS AC24 VCCIO AD29 VSS_SENSE_VCCIO AB20 VCCIO AC25 VCCIO AD30 VSS AB21 VCCIO AC26 VCCIO AD31 SB_DQ 60 AB22 VSS AC27 VCCIO AD32 SB_DQS 7 AB23 VCCIO AC28 VCCIO AD33 SB_DQ 59 Intel Xeon and Intel Core Processors For Commu
117. SS SENSE VCCIO Power Ground Other Single Ended Power Vecio Ground Vss No Connect Test Point RSVD Other PROC_DETECT Intel Xeon and Intel Core Processors For Communications Infrastructure May 2012 Datasheet Volume 1 of 2 Document Number 327405 001 91 intel Table 9 3 9 8 Note 9 9 Electrical Specifications Signal Groups Sheet 3 of 3 Signal Group1 Type Signals PCI Express PCIE_RX 15 0 PCIE_RX 15 0 Differential PCI Express Input PE RX 3 0 PE_RX 3 0 PCIE TX 15 0 PCIE_TX 15 0 Differential PCI Express Output PE TX 3 0 PE TX 3 0 PCIE ICOMPO PCIE ICOMPI Single Ended Analog Input PCIE RCOMPO DMI Differential DMI Input DMI RX 3 0 DMI_RX 3 0 Differential DMI Output TX 3 0 DMI_TX 3 0 Future Compatibility PROC SELECT VCCSA_VID O SA DIMM VREFDQ SB DIMM VREFDQ Notes 1 See Chapter 8 0 for signal description details 2 SA and SB see DDR3 Channel A and DDR3 Channel B 3 All Control Sideband Asynchronous signals are required to be asserted deasserted for at least 10 BCLKs with a maximum Trise Tfall of 6 ns for the processor to recognize the proper signal state See Chapter 9 10 and Chapter 9 11 for the DC and AC specifications 4 The maximum rise fall time of UNCOREPWRGOOD is 20 ns Test Access Port TAP Connect
118. VSS RSVD_3 9 RSVD_2 0 VSS 0 VIDSCL K TDI VIDALE RT RSVD_3 7 55 RSVD_3 8 RSVD_1 RSVD_3 8 VSS VSS TMS vss RSVD 1 9 RSVD 1 6 VSS 6 PREQ RSVD_1 1 THERM TRIP VSS RSVD_3 4 RSVD 3 2 VSS RSVD_1 RSVD_3 5 TRST PROC S 3 ELECT 8 CATERR UNCORE PWRGO 4 VSS B VSS RSVD_5 VSS_SE 6 4 4 NSE vss El CFG 1 RESET 4 PROCH OT vss PEGI RSVD_1 RSVD_5 die 2 1 RSVD_5 VSS 0 CFG 7 CFG 5 CFG 17 EE CFG 11 RSVD 2 CFG 14 CFG 6 CFG 8 CFG 2 CFG 12 CFG 15 A B G H J K L M N P R T U Intel Xeon and Intel Core Processors For Communications Infrastructure Datasheet Volume 1 of 2 May 2012 144 Document Number 327405 001 Processor Package Information Figure 10 4 Ball Map Bottom View Lower Right Side SM_DR SB_MA SB_MA SB_MA SB_MA SA_MA 5 5 MA SA MA SA MA SB MA SA MA CK SB CK SB _ ue SB CK vss SA MA SA CK SA MA SA MA SB MA 21 4 0 1 p 1 6 5 3 SA MA SB CK SB CK SB CK SB SA CK SA CK _ _ 5 5 22 2 3 0 2 2 0 0 11 3 1 2 BS A SB MA SB 5 WE SA CK
119. VSS T5 VSS U10 VSS R1 DMI_TX 0 T6 RSVD_10 U11 VSS R2 VSS T7 VCCIO U12 vcc R3 DMI_RX 0 T8 VCCSA U13 VSS R4 DMI_RX 1 T9 VSS U14 VCC R5 VSS T10 VCCIO U15 VCC R6 RSVD_9 T11 VCCSA U16 vss R7 VCCIO T12 U17 VCC R8 VCCIO T13 vss U18 VCC R9 VCCSA T14 VCC 019 vss R10 vss T15 VCC 020 vcc R11 VCCSA T16 VSS U21 vcc R12 VCC T17 VCC U22 VSS R13 VSS T18 VCC U23 VCC R14 VCC T19 VSS U24 VCC R15 VCC T20 VCC U25 VSS R16 VSS T21 VCC U26 VCC R17 VCC T22 VSS U27 VSS R18 VCC T23 VCC U28 VCCIO R19 vss T24 VCC U29 VCCIO R20 VCC T25 VSS u30 VSS R21 VCC T26 VCC U31 VSS R22 VSS T27 VCCI O U32 vss R23 VCC T28 VSS U33 vss R24 VCC T29 VCCI O U34 VSS R25 VSS T30 vss U35 vss R26 VCC T31 vss U36 VSS R27 VCCIO T32 SA_DQS 7 V1 DMI_TX 3 R28 VSS T33 SA DQI60 v2 DMI_TX 2 R29 VCCIO T34 SA DQI61 v3 vss Intel Xeon and Intel Core Processors For Communications Infrastructure Datasheet Volume 1 of 2 May 2012 124 Document Number 327405 001 Processor Package Information n tel Ball Signal Ball Signal Ball Signal V4 DMI_RX 2 w9 VSS Y14 VCC v5 DMI_RX 3 W10 VCCIO Y15 V6 VSS W11 VCCSA Y16 VSS V7 VCCIO W12 VCC Y17 VCC v8 VCCI O w13 VSS Y18 VCC v9 VCCSA W14 VCC Y19 VSS V10 VSS W15 VCC Y20 VCC V11 VCCSA W16 vss Y21 12 VCC W17 VCC Y22 VSS 13 vss W18 VCC Y23 VCC V14 VCC W19 VSS Y
120. VT d spec and other VT documents can be referenced at http www intel com technology platform technology virtualization index htm Intel VT x Objectives Intel VT x provides hardware acceleration for virtualization of IA platforms Virtual Machine Monitor VMM can use Intel VT x features to provide improved reliable virtualized platform By using Intel VT x a VMM is Robust VMMs no longer need to use paravirtualization or binary translation This means that they will be able to run off the shelf OSs and applications without any special steps Enhanced Intel VT enables VMMs to run 64 bit guest operating systems on IA x86 processors More reliable Due to the hardware support VMMs can now be smaller less complex and more efficient This improves reliability and availability and reduces the potential for software conflicts More secure The use of hardware transitions in the VMM strengthens the isolation of VMs and further prevents corruption of one VM from affecting others on the same system I ntel VT x Features The processor core supports the following Intel VT x features Extended Page Tables EPT EPT is hardware assisted page table virtualization t eliminates VM exits from guest OS to the VMM for shadow page table maintenance Intel Xeon and Intel Core Processors For Communications Infrastructure Datasheet Volume 1 of 2 Document Number 327405 001 39 Technologies V
121. Volume 1 of 2 Document Number 327405 001 95 n tel Electrical Specifications Table 9 6 Processor Uncore Vccio Supply DC Voltage and Current Specifications Symbol Parameter Min Typ Max Unit Note Voltage for the memory controller and Vecio shared cache defined at the motherboard 1 05 V Vccio sENsE and Vss vccio V Tolerance defined across V DC 2 including ripple TOL CCIO CCIO_SENSE 1 celo and Vss_sENSE_VCCIO AC 3 x l cCCMAX VCCIO Max Current for Vccio Rail 8 5 A 1 lectpc_vecio Thermal Design Current TDC for Vccio Rail 8 5 A 1 di dt Step current 2 A 2 3 Slew Rate Voltage Ramp rate dV dT 0 5 10 mV uS 1 Notes 1 Long term reliability cannot be assured in conditions above or below Max Min functional limits 2 Step is done in 100nS 3 di dt values are for platform testing only This parameter is not tested on Intel silicon Testing should go up to and include I ccMax Table 9 7 Memory Controller Vppg Supply DC Voltage and Current Specifications Symbol Parameter Min Typ Max Unit Note Processor 1 supply voltage for DDR3 DC 1 5 Vppo DC AC AC specification V DC 3 TOLppo Tolerance AC 2 3 AC DC 5 CCMAX_VDDQ Max Current for VDDQ Rail 5 1 2 Average Current Vppqo during CCAVG_VDDQ Standby Standby 66 133 mA 2 Slew Rate Voltage Ramp rate dV dT 0 5
122. _TX 13 L2 CFG 17 M32 PCIE1_RX 7 D5 1_ TX4 14 L1 CFG 2 N34 PCIE1_RX 8 E4 PCIE1_TX 15 N3 CFG 3 N31 PCIE1_RX 9 B4 PCIE1_TX 2 J9 CFG A L31 PCIE1_RX 0 C10 PCIE1_TX 3 K8 CFG 5 L32 PCIE1_RX 1 A8 PCIE1_TX 4 G8 CFG 6 N32 PCIE1_RX 10 PCIE1_TX 5 H7 CFG 7 K32 PCIE1_RX 11 D2 PCIE1_TX 6 J6 CFG 8 N33 PCIE1_RX 12 1 PCIE1_TX 7 H5 CFG 9 L34 PCIE1_RX 13 F3 PCIE1_TX 8 J4 DMI_RX 0 R3 PCIE1_RX 14 G2 PCIE1_TX 9 K5 RX 1 RA PCIE1_RX 15 H1 PCIE2 RX 0 E11 RX 2 U4 PCIE1_RX 2 D8 PCIE2_RX 1 D12 DMI_RX 3 V5 PCIE1_RX 3 E8 PCIE2_RX 2 B11 DMI_RX 0 T3 PCIE1_RX 4 B8 PCIE2 RX 3 A12 DMI_RX 1 T4 PCIE1_RX 5 7 PCIE2_RX 0 D10 DMI_RX 2 v4 PCIE1_RX 6 A6 PCIE2_RX 1 D11 DMI_RX 3 w5 PCIE1_RX 7 D6 PCIE2_RX 2 B10 DMI_TX 0 1 PCIE1_RX 8 E5 PCIE2_RX 3 A11 DMI_TX 1 Ul PCIE1 RX4 9 B5 PCIE2 TX 0 M6 DMI TX 2 U2 PCIE1_TX 0 G12 PCIE2 TX 1 L7 DMI TX 3 W1 PCIE1_TX 1 H10 PCIE2_TX 2 L11 Intel Xeon and Intel Core Processors For Communications Infrastructure May 2012 Datasheet Volume 1 of 2 Document Number 327405 001 131 Processor Package Information Signal Ball Signal Ball Signal Ball PCIE2 TX 3 K12 RSVD 35 G36 SA CKE 2 AK18 PCIE2_TX 0 M7 RSVD_ 36 35 SA_CKE 3 AM16
123. able 9 2 specifies the different VCCSA_VID configurations Table 9 2 VCCSA_VID Configuration VCCSA VID Selected VCCSA 0 0 9 V 1 0 8 vi Note 1 2012 Document Number 327405 001 Some of VCCSA configurations are reserved for future Intel processor families Intel Xeon and Intel Core Processors For Communications Infrastructure Datasheet Volume 1 of 2 89 n tel Electrical Specifications Note 9 7 Table 9 3 Reserved or Unused Signals The following are the general types of reserved RSVD signals and connection guidelines RSVD 22 RSVD 33 and RSVD_44 These pins must be shorted together and tied to through 24 9 ohm 1 resistor RSVD 21 1 RSVD 32 23 RSVD 43 34 and RSVD 57 45 these signals should not be connected For more information regarding termination and layout guidelines see the appropriate platform design guide Arbitrary connection of these signals to Vcc Vccio VccsA Vss or to any other signal including each other may result in component malfunction or incompatibility with future processors See Chapter 8 0 Signal Description for a pin listing of the processor and the location of all reserved signals For reliable operation always connect unused inputs or bi directional signals to an appropriate signal level Unused active high inputs should be connected through a resistor to ground Vss Unused
124. abling Hyper Threading Technology via the BIOS for all previous versions of Windows operating systems For more information on Hyper Threading Technology see http www intel com technology platform technology hyper threading Intel Advanced Vector Extensions Intel AVX Intel Advanced Vector Extensions Intel AVX is the latest expansion of the Intel instruction set It extends the Intel Streaming SIMD Extensions SSE from 128 bit vectors into 256 bit vectors Intel AVX addresses the continued need for vector floating point performance in mainstream scientific and engineering numerical applications visual processing recognition data mining synthesis gaming physics cryptography and other areas of applications The enhancement in Intel AVX allows for improved performance due to wider vectors new extensible syntax and rich functionality including the ability to better manage rearrange and sort data For more information AVX see http www intel com software avx Intel Xeon and Intel Core Processors For Communications Infrastructure Datasheet Volume 1 of 2 Document Number 327405 001 41 Technologies 4 4 Intel Advanced Encryption Standard New Instructions Intel AES NI The processor supports Advanced Encryption Standard New Instructions Intel AES NI which are a set of Single Instruction Multiple Data SIMD instructions that enable fast and secure data encryption and decr
125. ace above that starting at 100h is known as extended configuration space PCI Express Enhanced Access Mechanism Accessing the device configuration space in a flat memory mapped fashion Automatic discovery negotiation and training of link out of reset Traditional AGP style traffic asynchronous non snooped PCI X Relaxed ordering Peer segment destination posted write traffic no peer to peer read traffic in Virtual Channel 0 DMI gt PCI Express Port 1 gt PCI Express Port 2 PCI Express Port 1 gt DMI PCI Express Port 2 gt DMI 64 bit downstream address format but the processor never generates an address above 64 GB Bits 63 36 will always be zeros 64 bit upstream address format but the processor responds to upstream read transactions to addresses above 64 GB addresses where any of Bits 63 36 are nonzero with an Unsupported Request response Upstream write transactions to addresses above 64 GB will be dropped Re issues configuration cycles that have been previously completed with the Configuration Retry status PCI Express reference clock is 100 MHz differential clock Power Management Event PME functions Dynamic width capability Message Signaled Interrupt MSI and MSI X messages Polarity inversion Intel Xeon and Intel Core Processors For Communications Infrastructure May 2012 Datasheet Volume 1 of 2 Document Number 327405 001 19 int
126. active Critical Temperature Detection Critical Temperature detection is performed by monitoring the package temperature This feature is intended for graceful shutdown before the THERMTRI P is activated however the processor execution is not guaranteed between critical temperature and THERMTRIP If the package s Adaptive Thermal Monitor is triggered and the temperature remains high a critical temperature status and sticky bit are latched in the PACKAGE THERM STATUS MSR 1B1h and also generates a thermal interrupt if enabled For more details on the interrupt mechanism see the Intel 64 and 1 32 Architectures Software Developer s Manuals Intel Xeon and Intel Core Processors For Communications Infrastructure Datasheet Volume 1 of 2 Document Number 327405 001 67 n tel Thermal Management 7 3 2 7 3 2 1 7 3 2 1 1 7 3 2 1 2 7 3 3 7 3 3 1 7 3 4 Processor Core Specific Thermal Features On Demand Mode The processor provides an auxiliary mechanism that allows system software to force the processor to reduce its power consumption via clock modulation This mechanism is referred to as On Demand mode and is distinct from Adaptive Thermal Monitor and bi directional PROCHOT Processor platforms must not rely on software usage of this mechanism to limit the processor temperature On Demand Mode can be done via processor MSR or chipset I O emulation On Demand Mode may be used in conjunction with the
127. al operation default 0 Lane numbers reversed e CFG 4 Reserved configuration ball A test point may be placed on the board for this ball CFG 6 5 PCI Express Bifurcation 00 1 8 2 x4 PCI Express 01 reserved 10 2 x8 Express 11 1 x16 PCI Express CFG 17 7 Reserved configuration balls A test point may be placed on the board for these balls Note These strap values are read upon power up and the pre boot software enables the appropriate number of controllers and lane orientation See Section 3 2 5 Configuring PCle Lanes and Section 3 2 6 Lane Reversal on PCle Interface for further details CMOS PM_SYNC Power Management Sync A sideband signal to communicate power management status from the platform to the processor CMOS RESET Platform Reset pin driven by the PCH CMOS Intel Xeon and Intel Core Processors For Communications Infrastructure Datasheet Volume 1 of 2 74 May 2012 Document Number 327405 001 Signal Description Table 8 5 8 4 Table 8 6 8 5 Table 8 7 May 2012 Reset and Miscellaneous Signals Sheet 2 of 2 intel Signal Name Description BUSE ON Bufer ype DDR3 DRAM Reset Reset signal from processor 0 SM_DRAMRST to DRAM devices One common to all channels CMOS RSVD_ 21 1 RSVD_ 32 23 RESERVED All signals in this group are RSVD pins No Connect RSVD_ 43 34 RSVD_ 57
128. ate requests using the legacy method of I O reads from the ACPI defined processor clock control registers referred to as P_LVLx This method of requesting C states provides legacy support for operating systems that initiate C state transitions via 1 0 reads For legacy operating systems P_LVLx I O reads are converted within the processor to the equivalent MWAIT C state request Therefore P_LVLx reads do not directly result in reads to the system The feature known as I O MWAIT redirection must be enabled in the BIOS The P LVLx I O Monitor address needs to be set up before using the P LVLx I O read interface Each P LVLx is mapped to the supported MWAIT Cx instruction as follows Intel Xeon and Intel Core Processors For Communications Infrastructure Datasheet Volume 1 of 2 Document Number 327405 001 51 intel Table 6 8 Note 6 2 4 6 2 4 1 6 2 4 2 P LVLx to MWAIT Conversion P LVLx MWAI T Cx Notes P LVL2 MWAIT C3 The P LVL2 base address is defined in the IO CAPTURE MSR P LVL3 MWAIT C6 C6 No sub states allowed P_LVL4 MWAIT C7 C7 No sub states allowed P_LVL5 MWAIT C7 C7 No sub states allowed The BIOS can write to the C state range field of the IO CAPTURE MSR to restrict the range of I O addresses that are trapped and emulate MWAIT like functionality Any P LVLx reads outside of this range does not cause an 1 0 redirection to MWAIT Cx like reque
129. be proven that they are not populated This is due to the fact that when CKE is tristated with an DIMM present the DIMM is not guaranteed to maintain data integrity SCKE tristate should be enabled by BIOS where appropriate since at reset all rows must be assumed to be populated 6 3 2 DRAM Power Management and I nitialization The processor implements extensive support for power management on the SDRAM interface There are four SDRAM operations associated with the Clock Enable CKE signals which the SDRAM controller supports The processor drives four CKE pins to perform these operations The CKE is one of the power save means When CKE is off the internal DDR clock is disabled and the DDR power is reduced The power saving differs according to the selected mode and the DDR type used For more information see the IDD table in the DDR specification The DDR specification defines 3 levels of power down that differ in power saving and in wakeup time 1 Active power down APD This mode is entered if there are open pages when deasserting CKE In this mode the open pages are retained Power saving in this mode is the lowest Power consumption of DDR is defined by IDD3P Exiting this mode is defined by tXP small number of cycles 2 Precharged power down PPD This mode is entered if all banks in DDR are precharged when de asserting CKE Power saving in this mode is intermediate better than APD but less than DLL off Power consumpti
130. channel B Unit Figure Note Max Min System Memory Latency Timings CAS Latency RAS to CAS Delay Pre charge 9 9 9 Trp Command Period Electrical Characteristics TsiR p DQ 63 0 DQS 8 0 DQS 8 0 Input Slew Rate 6 5 2 0 V ns 2 System Memory Clock Timings Tck CK Period 1 50 ns Tcu CK High Time 0 625 ns Low Time 0 625 ns T Skew Between Any System Memory Differential 100 g SKEW Clock Pair CK CKB P System Memory Command Signal Timings RAS CAS WE MA 14 0 BA 2 0 Edge co Placement Accuracy 15 ps A 3 4 6 System Memory Control Signal Timings 5 1 0 CKE 1 0 ODT 1 0 Edge Placement _ 145 145 5 9 5 3 6 System Memory Data and Strobe Signal Timings Valid before DQS 8 0 Rising or Falling 500 ps 7 DQ Input Setup Plus Hold Time to DQS Rising or Tsu HD Falling Edge 200 ps 9 6 1 2 7 DQS Edge Placement Accuracy to CK Rising Edge _ AFTER Write Levelling 250 250 ps 9 8 TwPRE DQS DQS Write Preamble Duration 1 0 Tck Twest DQS DQS Write Postamble Duration 0 5 CK Rising Edge Output Access Time Where Write Cu X T Tposs Command Is Referenced to the First DQS Rising n 4 5 5 6 Edge Intel Xeon and Intel Core Processors For Communications Infrastructure May 2012 Datasheet Volume 1 of 2 Document Number 327405 001 105 intel Electrical Specifications Table 9 20 DDR3 Electr
131. compliant with PCI Express Base Specification Revision 2 0 This section will discuss how these 20 PCI Express lanes can be utilized in various configurations on the platform Intel Xeon and Intel Core Processors For Communications Infrastructure Datasheet Volume 1 of 2 Document Number 327405 001 29 l n tel i Interfaces The processor has four PCI Express controllers that can be independently configured to either Gen 1 or Gen 2 allowing operation at both 2 5 GT s Giga Transfers per second and 5 0 GT s data rates These four PCle devices operate simultaneously which are configurable in the following combinations 1x16 PCI Express Port with 1 x4 PCI Express Port 2 x8 PCI Express Ports with 1 x4 PCI Express Port e 1 x8 PCI Express Ports with 3 x4 PCI Express Ports The 1 Core SKU see Table 5 1 Base Features by SKU only supports 16 PCI Express Ports and a maximum of three PCle devices These three PCle devices operate simultaneously which are configurable in the following combinations 1x16 PCI Express Port 2 x8 PCI Express Ports 1x8 PCI Express Port with 2 x4 PCI Express Ports 3 x4 PCI Express Ports 3 2 1 PCI Express Architecture Compatibility with the PCI addressing model is maintained to ensure that all existing applications and drivers operate unchanged The PCI Express configuration uses standard mechanisms as defined in the PCI Plug and Play specification The initial recovered c
132. d Multiple bit DRAM ECC Error Flag DMERR If this bit is set to 1 a memory read data transfer had an uncorrectable multiple bit error When this bit is set the column row bank and rank that caused the error and the error syndrome are logged in the ECC Error Log register in the channel where the error occurred Once this bit is set the ECCERRLOGx fields are locked until the processor clears this bit by writing a 1 Software uses bits 1 0 to detect whether the logged error address is for a Single bit or a Multiple bit error This bit is reset on PWROK 0 RW1C S 0b Powergood Single bit DRAM ECC Error Flag DSERR If this bit is set to 1 a memory read data transfer had a single bit correctable error and the corrected data was returned to the requesting agent When this bit is set the column row bank and rank where the error occurred and the syndrome of the error are logged in the ECC Error Log register in the channel where the error occurred Once this bit is set the ECCERRLOGx fields are locked to further single bit error updates until the CPU clears this bit by writing a 1 A multiple bit error that occurs after this bit is set will overwrite the ECCERRLOGx fields with the multiple bit error signature and the DMERR bit will also be set A single bit error that occurs after a multibit error will set this bit but will not overwrite the other fields This bit is reset on PWROK ERRCMD Error Command B
133. d Intel Core Processors For Communications Infrastructure Datasheet Volume 1 of 2 May 2012 100 Document Number 327405 001 Electrical Specifications n tel Table 9 13 9 10 2 3 Figure 9 2 9 11 Note May 2012 PECI DC Electrical Limits Sheet 2 of 2 Symbol Definition and Conditions Min Max Units Notes lleak075 leakage current 9 0 75 Vccio 0 13 mA 100 leakage current Vccio 0 10 mA Notes 1 Vccio supplies the PECI interface PECI behavior does not affect V r min max specifications 2 The leakage specification applies to powered devices the PECI bus 3 The PECI buffer internal pull up resistance measured at 0 75 Vccio I nput Device Hysteresis The input buffers in both client and host models must use a Schmitt triggered input design for improved noise immunity Use Figure 9 2 as a guide for input buffer design Input Device Hysteresis Vy TD Maximum Vpe PECI High Range Minimum Vp ysteresis Signal Range Minimum Valid Input Hysteresis 7 J Maximum Vy Minimum PECI Ground AC Specifications The processor timings specified in this section are defined at the processor pads Therefore proper simulation of the signals is the only means to verify proper timing and signal quality See Chapter 10 0 for the processor pin listings and Chapter 8 0 for signal definitions Table 9 14
134. e Developer s Manuals http www intel com products processor manuals index htm 253665 253666 253667 253668 253669 Intel 64 and IA 32 Architectures Software Developer s Manual Documentation Changes http www intel com content www us en architecture and technology 64 ia 32 architectures software developers manual html Intel virtualization Technology Specification for Directed I O Architecture Specification http download intel com technology computing vptech Intel r VT for Direct IO pdf Intel Xeon and Intel Core Processors For Communications Infrastructure Datasheet 1 of 2 12 May 2012 Document Number 327405 001 Introduction 1 3 Table 1 3 May 2012 Terminology Terminology Sheet 1 of 2 Term Description DDR3 Third generation Double Data Rate SDRAM memory technology DMA Direct Memory Access DMI Direct Media Interface DTS Digital Thermal Sensor ECC Error Correction Code Enhanced Intel SpeedStep Technology Execute Disable Bit Technology that provides power management capabilities to laptops The Execute Disable bit allows memory to be marked as executable or non executable when combined with a supporting operating system If code attempts to run in non executable memory the processor raises an error to the operating system This feature can prevent some classes of viruses or worms that exploit buffer overrun vul
135. e following traffic types to or from the PCH DMI gt DRAM DMI gt processor core Virtual Legacy Wires VLWs Resetwarn or MSIs only Processor core gt DMI APIC and MSI interrupt messaging support Message Signaled Interrupt MSI and MSI X messages Downstream SMI SCI and SERR error indication Legacy support for ISA regime protocol PHOLD PHOLDA required for parallel port DMA floppy drive and LPC bus masters DC coupling no capacitors between the processor and the PCH Polarity inversion PCH end to end lane reversal across the link Supports Half Swing low power low voltage 2 4 4 Platform Environment Control Interface The PECI is a one wire interface that provides a communication channel between a PECI client the processor and a PECI master The processors support the PECI 3 0 Specification Intel Xeon and Intel Core Processors For Communications Infrastructure Datasheet Volume 1 of 2 May 2012 20 Document Number 327405 001 e Product Overview n tel 2 5 Power Management Support 2 5 1 Processor Core Full support of ACPI C states as implemented by the following processor C states CO C1 CIE C3 C6 C7 Enhanced Intel SpeedStep Technology 2 5 2 System Full support of the ACPI S states as implemented by the following system S states S0 S3 S4 S5 2 5 3 Memory Controller Conditional self refresh Intel9 Rapid Memory Power Management Intel RMPM
136. ead Only WO Note Mutually exclusive with Variant modifier FW RO Firmware Write The value of these bits can be updated by firmware PCU TAR etc Variant The value of these bits can be updated by EV RO hardware Note RW1C and RC are variant by definition and therefore do not need to be modified ERRSTS Error Status B D F Type Address Offset Default Value Access Size BIOS Optimal Default 0 0 0 PCI C8 C9h 0000h RO RW1C S 16 bits 0000h This register is used to report various error conditions via the SERR DMI messaging mechanism The SERR DMI message is generated on a zero to one transition of any of these flags if enabled by the ERRCMD and PCICMD registers These bits are set regardless of whether or not the SERR is enabled and generated After the error processing is complete the error logging mechanism can be unlocked by clearing the appropriate status bit by software writing a 1 to it Table 11 3 Error Status Register Sheet 1 of 2 i Default RST Bit Access Value PWR Description 15 2 Oh Reserved RSVD Intel Xeon and Intel Core Processors For Communications Infrastructure Datasheet Volume 1 of 2 152 May 2012 Document Number 327405 001 Processor Configuration Registers Table 11 3 Error Status Register Sheet 2 of 2 11 2 May 2012 intel Default RST Bit Access Value PWR Description 1 RW1C S 0b Powergoo
137. eeded to guarantee Receiver detect 8 The Rx DC Common Mode Impedance must be present when the Receiver terminations are first enabled to ensure that the Receiver Detect occurs properly Compensation of this impedance can start immediately and the 15 Rx Common Mode Impedance constrained by RLRX CM to 50 Q 20 must be within the specified range by the time Detect is entered 9 Low impedance defined during signaling Parameter is captured for 5 0 GHz by RLTX DIFF 10 This specification is the same as Vnx EYE 9 10 2 Platform Environmental Control Interface DC Specifications Platform Environmental Control Interface PECI is an Intel proprietary interface that provides a communication channel between Intel processors and chipset components to external Adaptive Thermal Monitor devices The processor contains a Digital Thermal Sensor DTS that reports a relative die temperature as an offset from Thermal Control Circuit TCC activation temperature Temperature sensors located throughout the die are implemented as analog to digital converters calibrated at the factory PECI provides an interface for external devices to read the DTS temperature for thermal management and fan speed control 9 10 2 1 PECI Bus Architecture May 2012 The PECI architecture is based on a wired OR bus which the processor PECI can pull up high with strong drive strength The idle state on the bus is near zero Figure 9 1 demonstrates PECI design and connectivity The h
138. el Product Overview Static lane numbering reversal Does not support dynamic lane reversal as defined optional by the PCI Express Base Specification Rev 2 0 Supports Half Swing low power low voltage mode Note The processor does not support PCI Express Hot Plug 2 4 3 Direct Media nterface DMI DMI 2 0 support Four lanes in each direction 2 5 GT s and 5 0 GT s DMI interface to PCH Gen1 Raw bit rate on the data pins of 2 5 GT s resulting in a real bandwidth per pair of 250 MB s given the 8b 10b encoding used to transmit data across this interface Does not account for packet overhead and link maintenance Gen2 Raw bit rate on the data pins of 5 0 GT s resulting in a real bandwidth per pair of 500 MB s given the 8b 10b encoding used to transmit data across this interface Does not account for packet overhead and link maintenance Maximum theoretical bandwidth on interface of 2 GB s in each direction simultaneously for an aggregate of 4 GB s when DMI x4 Shares 100 MHz PCI Express reference clock 64 bit downstream address format but the processor never generates an address above 64 GB Bits 63 36 will always be zeros 64 bit upstream address format but the processor responds to upstream read transactions to addresses above 64 GB addresses where any of Bits 63 36 are nonzero with an Unsupported Request response Upstream write transactions to addresses above 64 GB will be dropped Supports th
139. enabled It re enables once the processor has stayed out of the C6 or C7 for an preset amount of time Power is saved since this prevents the L3 cache from being re populated only to be immediately flushed again Dynamic L3 Cache Sizing Upon entry into the package C7 state the L3 cache is reduced by N ways until it is completely flushed The number of ways N is dynamically chosen per concurrent C7 entry Similarly upon exit the L3 cache is gradually expanded based on internal heuristics Intel Xeon and Intel Core Processors For Communications Infrastructure Datasheet Volume 1 of 2 May 2012 56 Document Number 327405 001 intel 6 3 I MC Power Management The main memory is power managed during normal operation and in low power ACPI Cx states 6 3 1 Disabling Unused System Memory Outputs Any system memory SM interface signal that goes to a memory module connector in which it is not connected to any actual memory devices such as DIMM connector is unpopulated or is single sided is tri stated The benefits of disabling unused SM signals are Reduced power consumption Reduced possible overshoot undershoot signal quality issues seen by the processor I O buffer receivers caused by reflections from potentially un terminated transmission lines When a given rank is not populated the corresponding chip select and CKE signals are not driven At reset all rows must be assumed to be populated until it can
140. ent Specifications 96 System Agent VCCSA Supply DC Voltage and Current Specifications 96 Processor PLL VCCPLL Supply DC Voltage and Current Specifications 97 DDR3 Signal Group DC Specifications ennemis 97 Control Sideband and TAP Signal Group DC 98 PCI Express DG Specification Sis ana ener eee 99 PEGI DC Electrical Limits ie ei aa 100 Differential Clocks SSC on saa 102 Differential Clocks SSC Off irre 102 Processor Clock Jitter Specifications 102 System Reference Clock DC and AC 102 DDR3 Electrical Characteristics and AC Timings at 1066 MT s VDDQ 1 5 V 30 075 0 Salat Yea eee 104 DDR3 Electrical Characteristics and AC Timings at 1333 MT s VDDO S 1 5 0 075 105 DDR3 Electrical Characteristics AC Timings at 1600 MT s VDDO S 1 5 MFE0 075 106 Express areas 1
141. eon and Intel Core Processors For Communications Infrastructure May 2012 Datasheet Volume 1 of 2 Document Number 327405 001 135 Processor Package Information Signal Ball Signal Ball Signal Ball vcc U24 VCC AA26 VCCIO Y29 vcc U26 VCC_SENSE M26 VCCIO Y30 V12 VCCIO M11 VCCIO AA1 V14 VCCIO M12 VCCIO AA2 V15 VCCIO N8 VCCIO AA3 V17 VCCIO N10 VCCIO AAA vcc 18 VCCIO N28 VCCIO AA5 vcc 20 VCCIO N29 VCCIO AA6 vcc 21 VCCIO P28 VCCIO 7 VCC V23 VCCIO P29 VCCIO AA28 VCC V24 VCCIO R7 VCCIO AA29 vcc 26 VCCIO R8 VCCIO AA30 W12 VCCIO R27 VCCIO AB7 VCC W14 VCCIO R29 VCCIO AB8 W15 VCCIO T7 VCCIO AB10 W17 VCCIO T10 VCCIO AB12 W18 VCCIO T27 VCCI O AB14 vcc w20 VCCIO T29 VCCIO AB15 W21 VCCIO U7 VCCIO AB17 vcc W23 VCCIO u8 VCCIO AB18 vcc w24 VCCIO 028 VCCIO AB20 VCC W26 VCCIO U29 VCCIO AB21 VCC Y12 VCCIO v7 VCCIO AB23 VCC Y14 VCCIO v8 VCCIO AB24 VCC Y15 VCCIO V28 VCCIO AB26 17 VCCIO 29 VCCIO AB27 VCC Y18 VCCIO v30 VCCI O AB28 VCC Y20 VCCIO W7 VCCIO AB29 vcc Y21 VCCIO W10 VCCIO AB30 vcc Y23 VCCIO W27 VCCIO AC7 vcc Y24 VCCIO W29 VCCIO AC8 vcc Y26 VCCIO W30 VCCIO AC9 AA12 VCCIO Y1 VCCIO AC10 14 VCCIO Y2 VCCIO AC11 AA15 VCCIO Y3 VCCIO AC12 AA17 VCCIO Y4 VCCIO AC13 VCC AA18 VCC
142. ermal Monitor event the Adaptive Thermal Monitor utilizes clock modulation Clock modulation is done by alternately turning the clocks off and on at a duty cycle ratio between clock on time and total time specific to the processor The duty cycle is factory configured to 2596 on and 75 off and cannot be modified The period of the duty cycle is configured to 32 microseconds when the TCC is active Cycle times are independent of processor frequency A small amount of hysteresis has been included to prevent excessive clock modulation when the processor temperature is near its maximum operating temperature Once the temperature has dropped below the maximum operating temperature and the hysteresis timer has expired the TCC goes inactive and clock modulation ceases Clock modulation is automatically engaged as part of the TCC activation when the frequency voltage targets are at their minimum settings Processor performance decreases by the same amount as the duty cycle when clock modulation is active Snooping and interrupt processing are performed in the normal manner while the TCC is active Digital Thermal Sensor Each processor execution core has an on die Digital Thermal Sensor DTS which detects the core s instantaneous temperature The DTS is the preferred method of monitoring processor die temperature because t is located near the hottest portions of the die t can accurately track the die temperature and ensure that the Adaptive
143. ershoot 117 Ball Map Bottom View Upper Left Side ssssssssssssseem es 142 Ball Map Bottom View Upper Right 5 r rr 143 Ball Map Bottom View Lower Left Side 144 Ball Map Bottom View Lower Right Side mmm nenne 145 Processor 4 Core Die Mechanical 147 Processor 2 Core Die 1 Core Die Mechanical 148 Processor Documents ere axes sg irren e einge b rcr niter ia d bcn ERR UTR RU RUE 11 Cave Creek PCH DOCUITIGnts 12 Public Specifications 12 eR 13 Supported UDIMM Module Configurations 2 mem 24 Supported SO DIMM Module Configurations 2 r rr 25 Supported Memory Down Configurations 1 cece ns 26 DDR3 System Memory Timing 27 Hardware Straps for Controller Enabling Port 1 35 Hardware Straps for Normal Reversed Operation of PCle 36 Reference Clock ore ect oid REDERNE 37 Base Features SKU L uu a au us aqa asian
144. essor both are referenced to Vss Important The overshoot and undershoot conditions are separate and their impact must be determined independently The pulse magnitude and duration must be used to determine if the overshoot undershoot pulse is within specifications 9 14 3 Overshoot Undershoot Pulse Duration Pulse duration describes the total amount of time that an overshoot undershoot event exceeds the overshoot undershoot reference voltage The total time could encompass several oscillations above the reference voltage Multiple overshoot undershoot pulses within a single overshoot undershoot event may need to be measured to determine the total pulse duration Note Oscillations below the reference voltage cannot be subtracted from the total overshoot undershoot pulse duration Table 9 26 Processor Overshoot Undershoot Specifications Signal Grou Maximum Overshoot Minimum Undershoot Notes 9 Overshoot Duration Undershoot Duration DDR3 1 2 Vppo 0 25 0 15 Vppo 0 25 1 2 Intel Xeon and Intel Core Processors Communications Infrastructure Datasheet Volume 1 of 2 May 2012 116 Document Number 327405 001 Electrical Specifications Table 9 26 Processor Overshoot Undershoot Specifications Signal Grou Maximum Overshoot Minimum Undershoot Notes 9 Overshoot Duration Undershoot Duration Control Sideband and Signals groups 1 18 Vccio 37ns 0 27 Vccio 3ns 12
145. f up to eighteen x8 SDRAM Devices per channel Non ECC Memory Down topology of up to eight x16 DDR3 SDRAM Devices per channel Single and dual channel memory organization modes Memory capacity supported from 512 MB up to 32 GB Using 4 Gb device technologies the largest total memory capacity possible is 32 GB assuming Dual Channel Mode with four x8 double sided dual ranked unbuffered DIMM memory configuration 1 Gb 2 Gb and 4 Gb DDR3 DRAM technologies are supported for x8 and x16 devices Using 4Gb device technology the largest memory capacity possible is 16 GB assuming dual channel mode with two x8 dual ranked un buffered DIMM memory configuration Data burst length of eight for all memory organization modes Memory DDR3 data transfer rates of 1066 MT s 1333 MT s and 1600 MT s Intel Xeon and Intel Core Processors For Communications Infrastructure Datasheet Volume 1 of 2 327405 001 17 tel Product Overview 72 bit wide channels 64 bit data 8 bit ECC 64 bit wide channels without ECC option e DDR3 I O Voltage of 1 5 V Supports ECC and non ECC unbuffered DDR3 DIMMs Mixing of ECC and Non ECC DIMMS is not supported Theoretical maximum memory bandwidth of 17 1 GB s in dual channel mode assuming DDR3 1066 MT s 21 3 GB s in dual channel mode assuming DDR3 1333 MT s 25 6 GB s in dual channel mode assuming DDR3 1600 MT s Up to 64 simultaneous open pages 32 per channel
146. ference Clock Signal Quality Specifications 115 9 13 2 DDR3 Signal Quality 115 9 13 3 1 0 Signal Quality Specifications r rr r 115 Overshoot Undershoot Guidelines 115 9 14 1 VCC Overshoot Specification 115 9 14 2 Overshoot Undershoot Magnitude rr 116 9 14 3 Overshoot Undershoot Pulse Duration rr rr 116 Processor Ball and Package 119 10 1 Processor Ball 1 cee ee ee nemen siemens 119 10 2 Package Mechanical Information sss memes 146 Processor Configuration Registers eem mme 151 ERRSTS Error Status E e CR REIR Ke RET 152 ERRCMD Error Command eene e kx pe un REA RADAR 153 SMICMD SMI Comimand cre eh RR RRRER XR REN ER RENE PPAR Gd 154 SCIECMD SCICOMMANG turns NUR rk QURE RN ER 155 ECCERRLOGO ECC Error Log 0 eee e rc e ni 155 ECCERREOGA CO ECC Error Log 1 rei tenente xx E pan n Ee nA Fen Ran 156 ECCERRLOGO_ Cl ECC Error hog 0 iiie rte tta nennen neben te
147. ge applies to the unassembled component only and does not apply to the shipping media moisture barrier bags or desiccant 4 Component product device storage temperature qualification methods may follow J ESD22 A119 low temp and JESD22 A103 high temp standards when applicable for volatile memory 5 Intel branded products are specified and certified to meet the following temperature and humidity limits that are given as an example only Non Operating Temperature Limit 40 C to 70 C and Humidity 50 to 90 non condensing with a maximum wet bulb of 28 C Post board attach storage temperature limits are not specified for non Intel branded boards 6 The JEDEC J JSTD 020 moisture level rating and associated handling practices apply to all moisture sensitive devices removed from the moisture barrier bag 7 Nominal temperature and humidity conditions and durations are given and tested within the constraints imposed by Tsustained storage and customer shelf life in applicable Intel boxes and bags DC Specifications The processor DC specifications in this section are defined at the processor pins unless noted otherwise See Chapter 10 0 for the processor pin listings and Chapter 8 0 for signal definitions The DC specifications for the DDR3 signals are listed in Table 9 10 Control Sideband and Test Access Port TAP are listed in Table 9 11 Table 9 5 through Table 9 9 lists the DC specifications for the processor and are valid only
148. ge of SA CK and the negative edge of DDR3 3 0 its complement SA_CK are used to sample the command and control signals on the SDRAM Clock Enable 1 per rank Used to Initialize the SDRAMs during power up o SA_CKE 3 0 Power down SDRAM ranks DDR3 Place all SDRAM ranks into and out of self refresh during STR Chip Select 1 per rank Used to select SA CS 3 0 particular SDRAM components during the active state There is one Chip Select for each SDRAM DDR3 rank SA ODT 3 0 On Die Termination Active Termination Control m Memory Channel B Sheet 1 of 2 Signal Name Description Direction Buffer Type SB BS 2 0 Bank Select These signals define which banks are selected within each SDRAM rank DDR3 Write Enable Control Signal Used with o SB_WE SB_RAS and SB_CAS along with SB_CS to define the SDRAM Commands DDR3 RAS Control Signal Used with SB_CAS and o SB_RAS SB_WE along with SB_CS to define the SRAM Commands DDR3 Intel Xeon and Intel Core Processors For Communications Infrastructure May 2012 Datasheet Volume 1 of 2 72 Document Number 327405 001 Signal Description intel Table 8 3 Memory Channel B Sheet 2 of 2 Signal Name Description v Bufer ype CAS Control Signal Used with SB_RAS and o SB_CAS SB_WE along with SB_CS to define the SRAM DDR3 Commands Data Strobes SB_
149. hanism for interrupt delivery This extension is intended primarily to increase processor addressability Specifically x2APIC Retains all key elements of compatibility to the xAPIC architecture delivery modes interrupt and processor priorities interrupt sources interrupt destination types Provides extensions to scale processor addressability for both the logical and physical destination modes Adds new features to enhance performance of interrupt delivery Reduces complexity of logical destination mode interrupt delivery on link based architectures The key enhancements provided by the x2APIC architecture over xAPIC are the following Support for two modes of operation to provide backward compatibility and extensibility for future platform innovations n xAPIC compatibility mode APIC registers are accessed through memory mapped interface to a 4K Byte page identical to the xAPIC architecture Intel Xeon and Intel Core Processors For Communications Infrastructure Datasheet Volume 1 of 2 May 2012 42 Document Number 327405 001 intel n x2APIC mode APIC registers are accessed through Model Specific Register MSR interfaces In this mode the x2APIC architecture provides significantly increased processor addressability and some enhancements on interrupt delivery Increased range of processor addressability in x2APIC mode Physical xAPIC ID field increases from 8 bits
150. he Thermal Control Circuit TCC and causes the processor core to reduce frequency and voltage adaptively The TCC remains active as long as any package temperature exceeds its specified limit Therefore the Adaptive Thermal Monitor continues to reduce the package frequency and voltage until the TCC is de activated If properly configured when an external device asserts PROCHOT the thermal control circuit TCC causes the processor core to reduce frequency and voltage adaptively Adaptive Thermal Monitor is always enabled Adaptive Thermal Monitor The purpose of the Adaptive Thermal Monitor is to reduce processor core power consumption and temperature until it operates at or below its maximum operating temperature according for TCC activation offset Processor core power reduction is achieved by Adjusting the operating frequency via the core ratio multiplier and input voltage via the SVID bus Modulating starting and stopping the internal processor core clocks duty cycle The temperature at which the Adaptive Thermal Monitor activates the Thermal Control Circuit is factory calibrated and is not user configurable The default value is software visible in the TEMPERATURE TARGET 0x1A2 MSR Bits 23 16 The Adaptive Thermal Monitor does not require any additional hardware software drivers or interrupt handling routines The Adaptive Thermal Monitor is not intended as a mechanism to maintain processor TDP The system desig
151. he VR temperature and activate the TCC when the temperature limit of the VR is reached By asserting PROCHOT pulled low and activating the TCC the VR cools down as a result of reduced processor power Intel Xeon and Intel Core Processors For Communications Infrastructure Datasheet Volume 1 of 2 May 2012 66 Document Number 327405 001 intel 7 3 1 3 3 7 3 1 3 4 7 3 1 3 5 7 3 1 3 6 May 2012 consumption Bi directional PROCHOT can allow VR thermal designs to target thermal design current Icctpc instead of maximum current Systems should still provide proper cooling for the VR and rely on bi directional PROCHOT only as a backup in case of system cooling failure Overall the system thermal design should allow the power delivery circuitry to operate within its temperature specification even while the processor is operating at its TDP Thermal Solution Design and PROCHOT Behavior With a properly designed and characterized thermal solution it is anticipated that is only asserted for very short periods of time when running the most power intensive applications The processor performance impact due to these brief periods of TCC activation is expected to be so minor that it would be immeasurable However an under designed thermal solution that is not able to prevent excessive assertion of PROCHOT in the anticipated ambient environment may Cause a noticeable performance loss Resul
152. hed its maximum operating temperature Tj Ax See Figure 7 1 for a timing diagram of the PROCHOT signal assertion relative to the Adaptive Thermal Response Only a single PROCHOT pin exists at a package level When any core arrives at the TCC activation point the PROCHOT signal is asserted PROCHOT assertion policies are independent of Adaptive Thermal Monitor enabling Bus snooping and interrupt latching are active while the TCC is active Bi Directional PROCHOT By default the PROCHOT signal is defined as an output only However the signal may be configured as bi directional When configured as a bi directional signal PROCHOT can be used for thermally protecting other platform components should they overheat as well When PROCHOT is driven by an external device The package immediately transitions to the minimum operation points voltage and frequency supported by the processor cores This is contrary to the internally generated Adaptive Thermal Monitor response Clock modulation is not activated The TCC remains active until the system deasserts PROCHOT The processor can be configured to generate an interrupt upon assertion and deassertion of the PROCHOT signal Toggling PROCHOT more than once in 1 5ms period results in constant Pn state of the processor Voltage Regulator Protection may be used for thermal protection of voltage regulators VR System designers can create a circuit to monitor t
153. hether the bit value is a Logic 0 or Logic 1 PECI also includes variable data transfer rate established with every message The single wire interface provides low board routing overhead for the multiple load connections in the congested routing area near the processor and chipset components Bus speed error checking and low protocol overhead provides adequate link bandwidth and reliability to transfer critical device operating conditions and configuration information Fan Speed Control with Digital Thermal Sensor Digital Thermal Sensor based fan speed control Tran is a recommended feature to achieve optimal thermal performance At the TgAy temperature Intel recommends full cooling capability well before the DTS reading reaches TJ MAX An example of this would be TFAN 10 88 Intel Xeon and Intel Core Processors For Communications Infrastructure Datasheet Volume 1 of 2 Document Number 327405 001 69 n tel Thermal Management Intel Xeon and Intel Core Processors For Communications Infrastructure Datasheet Volume 1 of 2 May 2012 70 Document Number 327405 001 Signal Description 8 0 Table 8 1 8 1 Table 8 2 May 2012 Signal Description This chapter describes the processor signals They are arranged in functional groups according to their associated interface or category The following notations are used to describe the signal type Notations Signal Type In
154. ical Characteristics and AC Timings at 1600 s Vppo 1 5 V x0 075 V Channel A Symbol Parameter ChannerB Unit Figure Note1 9 Max Min System Memory Latency Timings CAS Latency RAS to CAS Delay Pre charge ENTE Command Period Electrical Characteristics p DQ 63 0 DQS 8 0 205 8 0 Input Slew Rate 6 5 2 0 V ns 2 System Memory Clock Timings Tck CK Period 1 25 ns Tcu CK High Time 0 5 ns TeL CK Low Time 0 5 ns T Skew Between Any System Memory Differential 100 SKEW Clock Pair CK CKB System Memory Command Signal Timings RAS CAS WE MA 14 0 BA 2 0 Edge co Placement Accuracy z 125 5 9 3 4 6 System Memory Control Signal Timings CS 1 0 1 0 ODT 1 0 Edge Placement _ 145 145 5 9 5 3 6 System Memory Data and Strobe Signal Timings DQ 63 0 Valid before DQS 8 0 Rising or Fallin a 375 ps 7 DQ Input Setup Plus Hold Time to DQS Rising or Tsu HD Falling Edge 200 ps 9 6 1 2 7 DQS Edge Placement Accuracy to CK Rising Edge _ AFTER Write Levelling 125 125 p 9 7 8 TwPRE DQS DQS Write Preamble Duration 1 0 Tck Twest DQS DQS Write Postamble Duration 0 5 Rising Edge Output Access Time Where Write Cw X Tposs Command Is Referenced to the First DQS Rising dis 4
155. ical Operation 16 Lanes 34 Power States waqu 47 Idle Power Management Breakdown of the Processor Cores 50 Thread and Core C State Entry and Exit r rr 51 Package C State Entry and Exit a nee nenne ener 55 Frequency and Voltage Ordering eee eee memes 64 Example of Host Client Connection 100 Input Device Hysteresis ties ed annari iip bebes ihre a ETENEE REDE 101 Differential Clock Differential Measurements tenet ens 110 Differential Clock Single Ended 111 DDR3 Command Control and Clock Timing Waveform 111 DDR3 Recelver Eye Mask kkaamaawaskasapa 112 DDR3 Clock to DQS Skew Timing Waveform 112 PCI Express Receiver Eye 1 eee eee neta ene 113 TAP Valid Delay Timing Waveform een 113 Test Reset TRST Async Input and PROCHOT Timing Waveform 114 THERMTRIP Power Down Sequence meses nnn 114 VCC Overshoot Example Waveform 116 Maximum Acceptable Overshoot Und
156. ications Infrastructure May 2012 Datasheet Volume 1 of 2 76 Document Number 327405 001 Signal Description 8 8 Error and Thermal Protection Table 8 10 Error and Thermal Protection Signal Name Description Direction Buffer Type CATERR Catastrophic Error This signal indicates that the system has experienced a catastrophic error and cannot continue to operate The processor sets this for non recoverable machine check errors or other unrecoverable internal errors External agents are allowed to assert this pin which causes the processor to take a machine check exception On this processor CATERR is used for signaling the following types of errors Legacy MCERR s CATERR is asserted for 16 BCLKs Legacy IERR s CATERR remains asserted until warm or cold reset CMOS PECI PECI Platform Environment Control Interface A serial sideband interface to the processor it is used primarily for thermal power and error management 1 0 Asynchronous PROCHOT Processor Hot PROCHOT goes active when the processor temperature monitoring sensor s detects that the processor has reached its maximum safe operating temperature This indicates that the processor Thermal Control Circuit TCC has been activated if enabled This signal can also be driven to the processor to activate the TCC CMOS Input Open Drain Output THERMTRIP Thermal Trip The processor protects itself f
157. ided to the memory controller via PECI or can be estimated by the memory controller based upon memory activity The temperature trigger points are programmable by memory mapped 10 registers Programmable Trip Points This memory controller provides programmable critical hot and warm trip points Crossing a critical trip point forces a system shutdown Crossing a hot or warm trip point initiates throttling The amount of memory throttle at each trip point is programmable Platform Environment Control I nterface PECI The Platform Environment Control Interface PECI is a one wire interface that provides a communication channel between Intel processor and chipset components to external monitoring devices The processor implements a PECI interface to allow communication of processor thermal information to other devices on the platform The processor provides a digital thermal sensor DTS for fan speed control The DTS is calibrated at the factory to provide a digital representation of relative processor temperature Averaged DTS values are read via the PECI interface Intel Xeon and Intel Core Processors For Communications Infrastructure Datasheet Volume 1 of 2 May 2012 68 Document Number 327405 001 intel 7 3 4 1 May 2012 The PECI physical layer is a self clocked one wire bus that begins each bit with a driven rising edge from an idle level near zero volts The duration of the signal driven high depends on w
158. ignal Ball Signal AL28 SA_ODT 1 AM33 VSS AP2 vss 129 VSS AM34 VSS AP3 SB_DQ 18 AL30 VSS AM35 VSS AP4 VSS AL31 VSS AM36 SB_DQS 5 AP5 VSS AL32 VSS AN1 VSS AP6 VSS AL33 SB DQ 46 AN2 SB DQI22 AP7 SB DQI29 AL34 SB DQ 45 AN3 SB DQI23 AP8 SB_DQ 26 AL35 SB_DQ 41 AN4 SB_DQS 2 AP9 VSS AL36 SB DQS 5 AN5 SB DQI19 10 SA_DQ 29 1 SB_DQ 20 AN6 vss AP11 SA_DQ 26 AM2 SB_DQ 17 AN7 SB_DQ 28 AP12 VSS AM3 SB_DQ 16 AN8 SB_DQ 27 AP13 SA_ECC_CB 5 AM4 SB_DQS 2 AN9 VSS 14 SA ECC CB 2 AM5 SB DQ 21 AN10 SA_DQ 28 AP15 VSS AM6 VSS AN11 SA_DQ 27 AP16 SM_VREF AM7 SB_DQS 3 AN12 VSS AP17 VDDQ AM8 SB_DQS 3 AN13 SA_ECC_CB 4 AP18 SA_CKE 1 AM9 VSS AN14 SA_ECC_CB 3 AP19 SA MA 15 10 SA 005 3 AN15 VSS 20 VDDQ 11 SA_DQS 3 AN16 SM_DRAMRST AP21 SA_MAT6 AM12 VSS AN17 VSS AP22 SA MA 3 AM13 SA_DQS 8 AN18 SA_MA 12 AP23 VDDQ 14 SA_DQS 8 AN19 SA 7 AP24 SA CK 2 15 VSS AN20 VSS AP25 VSS AM16 SA_CKE 3 AN21 SA_CK 1 AP26 VDDQ AM17 VDDQ AN22 SA_CK 1 AP27 SA_RAS AM18 SA_BS 2 AN23 VSS AP28 SA_CS 2 19 SA MA 9 AN24 SA_CK 2 AP29 VDDQ AM20 VDDQ AN25 SA_MA O AP30 VSS AM21 SA MA 1 AN26 VSS AP31 SB_DQ 32 AM22 SA_CK 0 AN27 SA_CAS AP32 SB_DQ 34 AM23 VDDQ AN28 SA_CS 1 AP33 VSS AM24 SA_CK 3 AN29 VSS AP34 VSS AM25 SA BS 1 AN30 VSS AP35 VSS AM26 VDDQ AN31 SB_DQ 36
159. instances running on the same system offering benefits like system consolidation legacy migration activity partitioning or security 4 1 4 Intel VT d Features The processor supports the following Intel VT d features Memory controller complies with Intel VT d 1 2 specification Intel9 VT d DMA remap engines DMI non high def audio PCI Express Support for root entry context entry and default context 39 bit guest physical address and host physical address widths Support for 4K page sizes only Support for register based fault recording only for single entry only and support for MSI interrupts for faults Support for both leaf and non leaf caching Support for boot protection of default page table Support for non caching of invalid page table entries Support for hardware based flushing of translated but pending writes and pending reads on IOTLB invalidation Support for page selective OTLB invalidation Intel Xeon and Intel Core Processors For Communications Infrastructure Datasheet Volume 1 of 2 May 2012 40 Document Number 327405 001 Technologies 4 1 5 4 2 4 3 May 2012 intel MSI cycles MemWr to address FEEx xxxxh not translated Translation faults result in cycle forwarding to VBIOS region byte enables masked for writes Returned data may be bogus for internal agents interfaces return unsupported request status Interrupt Remapping i
160. intel Intel Xeon and Intel Core Processors For Communications Infrastructure Datasheet Volume 1 of 2 Supporting Intel Xeon Processor E3 1125C Intel Xeon Processor E3 1105C Intel Core i3 Processor 2115C Intel Pentium Processor B915C Intel Celeron Processor 725C Document 324803 2nd Generation I ntel Core Processor Family Mobile Datasheet Volume 2 completes the documentation set and contains additional product information May 2012 Document Number 327405 001 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS NO LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY INTELLECTUAL PROPERTY RIGHTS 15 GRANTED BY THIS DOCUMENT EXCEPT AS PROVIDED IN INTEL S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO SALE AND OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE MERCHANTABILITY OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT A Mission Critical Application is any application in which failure of the Intel Product could result directly or indirectly in personal injury or death SHOULD YOU PURCHASE OR USE INTEL S PRODUCTS FOR ANY SUCH MISSION CRITICAL APPLICATION YOU SHALL INDEMNIFY AND HOLD INTEL AND ITS SUBSIDIARIES SUBCONTRACTORS AND AFFILIATES AND THE DIRECTORS OFFICERS AND
161. ion Due to the voltage levels supported by other components in the Test Access Port TAP logic Intel recommends the processor be first in the TAP chain followed by any other components within the system A translation buffer should be used to connect to the rest of the chain unless one of the other components is capable of accepting an input of the appropriate voltage Two copies of each signal may be required with each driving a different voltage level The processor supports Boundary Scan J TAG IEEE 1149 1 2001 and IEEE 1149 6 2003 standards Some small portion of the 1 pins may support only one of these standards Some of the I O pins may support only one of these standards Storage Conditions Specifications Environmental storage condition limits define the temperature and relative humidity to which the device is exposed to while being stored in a moisture barrier bag The specified storage conditions are for component level prior to board attach Table 9 4 specifies absolute maximum and minimum storage temperature limits which represent the maximum or minimum device condition beyond which damage latent or otherwise may occur The table also specifies sustained storage temperature relative humidity and time duration limits These limits specify the maximum or minimum device storage conditions for a sustained period of time Failure to adhere to the following specifications can affect long term reliability of the processor In
162. irtual Processor IDs VPID Ability to assign a VM ID to tag processor core hardware structures e g TLBs This avoids flushes on VM transitions to give a lower cost VM transition time and an overall reduction in virtualization overhead Guest Preemption Timer Mechanism for a VMM to preempt the execution of a guest OS after an amount of time specified by the VMM The VMM sets a timer value before entering a guest The feature aids VMM developers in flexibility and Quality of Service QoS guarantees Descriptor Table Exiting Descriptor table exiting allows a VMM to protect a guest OS from internal malicious software based attack by preventing relocation of key system data structures like IDT interrupt descriptor table GDT global descriptor table LDT local descriptor table and TSS task segment selector A VMM using this feature can intercept by a VM exit attempts to relocate these data structures and prevent them from being tampered by malicious software 4 1 3 I ntel VT d Objectives The key Intel VT d objectives are domain based isolation and hardware based virtualization A domain can be abstractly defined as an isolated environment in a platform to which a subset of host physical memory is allocated Virtualization allows for the creation of one or more partitions on a single system This could be multiple partitions in the same operating system or there can be multiple operating system
163. ld be launched in a back to back manner to make optimum use of the open memory page This ability to reorder requests on the fly allows the IMC to further reduce latency and increase bandwidth efficiency Memory Type Range Registers MTRRs Enhancement In this processor there are additional 2 MTRRs total 10 MTRRs These additional MTRRs are specially important in supporting larger system memory beyond 4GB Data Scrambling The memory controller incorporates a DDR3 Data Scrambling feature to minimize the impact of excessive di dt on the platform DDR3 VRs due to successive 1 s and 0 s on the data bus Past experience has demonstrated that traffic on the data bus is not random and can have energy concentrated at specific spectral harmonics creating high di dt which is generally limited by data patterns that excite resonance between the package inductance and on die capacitances As a result the memory controller uses a data scrambling feature to create pseudo random patterns on the DDR3 data bus to reduce the impact of any excessive di dt DRAM Clock Generation Every supported DI MM has two differential clock pairs There are total of four clock pairs driven directly by the processor to two DIMMs PCI Express Interface This section describes the PCI Express interface capabilities of the processor See the PCI Express Base Specification for details of PCI Express The processor has a total of 20 PCI Express lanes These lanes are fully
164. le Gen2 x4 0252 ee 058 2 ES 0 oO S o ChA ChB Intel Xeon and Intel Core Processors Communications Infrastructure Datasheet Volume 1 of 2 May 2012 16 Document Number 327405 001 Product Overview 2 1 Product Features 2 2 Processor Details Four two or single execution cores 4C 2C or 1C respectively 32 KB data first level cache L1 for each core parity protected 32 KB instruction first level cache L1 for each core ECC protected 256 KB shared instruction data second level cache L2 for each core ECC protected Up to 8 MB shared instruction data third level cache L3 across all cores ECC protected 2 3 Supported Technologies Intel Virtualization Technology for Directed 1 0 Intel VT d Intel Virtualization Technology Intel VT x Intel Streaming SIMD Extensions 4 1 Intel SSE4 1 Intel Streaming SIMD Extensions 4 2 Intel SSE4 2 Intel Hyper Threading Technology Intel 64 Architecture Execute Disable Bit Intel Advanced Vector Extensions Intel AVX Advanced Encryption Standard New Instructions AES NI PCLMULQDQ Instruction 2 4 Interface Features 2 4 1 System Memory Support May 2012 Document Number One or two channels of DDR3 memory with a maximum of two UDIMMs or two SO DIMMs per channel ECC Memory Down topology o
165. lock Signal Quality Specifications Overshoot Undershoot and Ringback specifications for BCLK BCLK are found in Table 9 26 Overshoot Undershoot and Ringback specifications for the DDR3 Reference Clocks are specified by the DIMM DDR3 Signal Quality Specifications Signal Quality specifications for Differential DDR3 Signals are included as part of the DDR3 DC specifications and DDR3 AC specifications Various scenarios have been simulated to generate a set of layout guidelines which are available in the appropriate platform design guide Signal Quality Specifications Signal Quality specifications for PCle Signals are included as part of the PCle DC specifications and PCle AC specifications Various scenarios have been simulated to generate a set of layout guidelines which are available in the appropriate platform design guide Overshoot Undershoot Guidelines Overshoot or undershoot is the absolute value of the maximum voltage above or below Vss The overshoot undershoot specifications limit transitions beyond Vccio or Vss due to the fast signal edge rates The processor can be damaged by single and or repeated overshoot or undershoot events on any input output or 1 0 buffer if the charge is large enough i e if the over undershoot is great enough Baseboard designs which meet signal integrity and timing requirements and which do not exceed the maximum overshoot or undershoot limits listed in Table 9 26 will insure reliable IO
166. lock speed of 1 25 GHz results in 2 5 Gb s direction which provides a 250 MB s communications channel in each direction 500 MB s total That is nearly twice the data rate of classic PCI The fact that 8b 10b encoding is used accounts for the 250 MB s where quick calculations would imply 300 MB s The external ports support Gen2 speed as well At 5 0 GT s Gen 2 operation results in double the bandwidth per lane as compared to Gen 1 operation When operating with two PCle controllers each controller can be operating at either 2 5 GT s or 5 0 GT s The PCI Express architecture is specified in three layers Transaction Layer Data Link Layer and Physical Layer The partitioning in the component is not necessarily along these same boundaries See Figure 3 2 for the PCI Express Layering Diagram Figure 3 2 PCI Express Layering Diagram Transaction Transaction Data Link Data Link Physical Physical Logical Sub block Electrical Bub block RX TX Logical Sub block Electrical Bub block RX Intel Xeon and Intel Core Processors For Communications Infrastructure Datasheet Volume 1 of 2 May 2012 30 Document Number 327405 001 Interfaces i n tel j PCI Express uses packets to communicate information between components Packets are formed in the Transaction and Data Link Layers to carry the information from the transmitting component to the receiving component As the transmitted packets flow
167. lters LPF 3RD order 1 MHz pole to filter out high frequency jitter FM and show the underlying SSC profile The numbers here bound the SSC min max excursions SSC magnitude 1CLK No Filter Any 1 Period measured with a scope Measured on a real time Oscilloscope using no filters a simple period measurement or a Jit3 period measurement more accurate provides absolute Min Max timing information Table 9 15 Differential Clocks SSC off SSC OFF 1CLK 0 15 0 15 1CLK Jitter c c ppm Ideal DC ppm Jitter c c 2 Signal Name AbsPerMin LongAvgMin target LongAvgMax AbsPerMax Units BCLK 9 849000 9 999000 10 00000 10 00100 10 15100 ns Notes 1 Ideal DC Target This serves only as an ideal reference target Oppm to use for calculating the rest of the period measurement values 2 0 1 second Measurement Window frequency counter Valuable measurement done using a frequency counter to determine near DC average frequency filtering out all jitter including SSC and cycle to cycle This is used to determine if the system has a frequency static offset caused usually by incorrect crystal crystal loading or incorrect clock configuration 3 1CLK No Filter Any 1 Period measured with a scope Measured on a real time Oscilloscope using no filters a simple period measurement or a Jit3 period measurement more accurate provides absolute Min Max timing information Table 9 16 Processor Clock Jitter Specificati
168. lti core processor built on 32 nanometer process technology It supports DDR3 with Error Correction Code ECC and up to 20 Express lanes The processor is based on the Intel micro architecture formerly code named Sandy Bridge and is designed for a two chip platform Included in the processor is an integrated memory controller IMC and integrated I O PCI Express and DMI on a single silicon die This single die solution is known as a monolithic processor The integration of the memory and PCI Express controllers into the processor silicon will benefit 1 intensive applications in the communications segments Note The Intel Xeon Intel Core Intel Pentium and Intel Celeron processors for this platform do not include the Integrated Display Engine or the Graphics Processor Unit GPU Disregard references to graphics and Intel Turbo Boost in the 2nd Generation Intel Core Processor Family Mobile Datasheet Volume 2 Intel Xeon and Intel Core Processors For Communications Infrastructure May 2012 Datasheet Volume 1 of 2 Document Number 327405 001 15 n tel Product Overview Figure 2 1 Crystal Forest Platform Example Block Diagram a o 9 eg u 1 2640 5 lt TE Qe t ili 8 System BIOS 2 Devices gt fe USB 2SATA Conn s TPM Port 80 gt 88 1 25Gbs lane 3 0Gbs SATA LPC PCle Gen2 x16 PC
169. n should provide a thermal solution that can maintain TDP within its intended usage range Frequency Voltage Control Upon TCC activation the processor core attempts to dynamically reduce processor core power by lowering the frequency and voltage operating point The operating points are automatically calculated by the processor core itself and do not require the BIOS to program them as with previous generations of Intel processors The processor core scales the operating points so that Intel Xeon and Intel Core Processors For Communications Infrastructure Datasheet Volume 1 of 2 Document Number 327405 001 63 intel The voltage is optimized according to the temperature the core bus ratio and number of cores in deep C states The core power and temperature are reduced while minimizing performance degradation A small amount of hysteresis has been included to prevent an excessive amount of operating point transitions when the processor temperature is near its maximum operating temperature Once the temperature has dropped below the maximum operating temperature the operating frequency and voltage transition back to the normal system operating point This is illustrated in Figure 7 1 Figure 7 1 Frequency and Voltage Ordering gH PROCHOT Once a target frequency bus ratio is resolved the processor core transitions to the new target automatically On an upward operating point transiti
170. nal Name Description Direction Buffer Type BCLK BCLK Differential bus clock input to the processor and PCI Express Diff Clk TAP Signals TAP Signals Signal Name Description ss Buffer ype Breakpoint and Performance Monitor Signals BPM 7 0 Outputs from the processor that indicate the status 1 0 E of breakpoints and programmable counters used CMOS for monitoring processor performance PRDY PRDY is a processor output used by debug tools to determine processor debug readiness Asynchronous CMOS PREQ PREQ is used by debug tools to request debug operation of processor Asynchronous CMOS TCK Test Clock Provides the clock input for the TCK processor Test Bus also known as the Test Access Port must be driven low allowed to float CMOS during power on Reset TDI Test Data In Transfers serial test data into I TDI the processor TDI provides the serial input needed CMOS for J specification support M TDO Test Data Out transfers serial test data out o TDO of the processor TDO provides the serial output needed for specification support pen Drain TMS TMS Test Mode Select A JTAG specification support signal used debug tools CMOS TRST Test Reset resets the Test Access Port I TRST TAP logic TRST must be driven low during CMOS power on Reset M Intel Xeon and Intel Core Processors For Commun
171. nd on the processor package There is no connection to the processor silicon for this signal System board designers may use this signal to determine if the processor is present 8 10 Processor Power and Ground Signals Table 8 12 Processor Power Signals Signal Name Description Direction Buffer Type VCC Processor core power rail PWR VCCIO Processor power for I O PWR VDDQ Processor 1 supply voltage for DDR3 PWR VCCPLL provides isolated power for internal VCCPLL processor PLLs PWR VCCSA System Agent power supply PWR VIDALERT VIDSCLK and VIDSCLK comprise a VIDSOUT three signal serial synchronous interface used to 1 0 transfer power management information between VIDSCLK the processor and the voltage regulator controllers l VIDALERT This serial VID SVID interface replaces the CMOS parallel VID interface on previous processors Voltage selection for VCCSA This pin must have VCCSA_VID a pull down resistor to ground CMOS VSS Processor ground node GND Intel Xeon and Intel Core Processors For Communications Infrastructure May 2012 Datasheet Volume 1 of 2 78 Document Number 327405 001 Signal Description 8 11 Sense Pins Table 8 13 Sense Pins Signal Name Description dr Buffer ype VCC_SENSE and VSS_SENSE provide an isolated VCC_SENSE low impedance connection to the processor core
172. nerabilities and can thus help improve the overall security of the system See the Intel 64 and IA 32 Architectures Software Developer s Manuals for more detailed information HFM High Frequency Mode IMC Integrated Memory Controller Intel 64 Technology 64 bit memory extensions to the IA 32 architecture Intel TXT Intel Trusted Execution Technology is a versatile set of hardware extensions to Intel processors and chipsets that enhance the digital office platform with security capabilities such as measured launch and protected execution Intel Trusted Execution Technology provides hardware based mechanisms that help protect against software based attacks and protects the confidentiality and integrity of data stored or created on the client PC Intel VT d Intel Virtualization Technology Intel Virtualization Technology Intel VT for Directed 1 0 Intel VT d is a hardware assist under system software Virtual Machine Manager or OS control for enabling 1 0 device virtualization Intel VT d also brings robust security by providing protection from errant DMAs by using DMA remapping a key feature of Intel VT d Processor virtualization which when used in conjunction with Virtual Machine Monitor software enables multiple robust independent software environments inside a single platform Processor Core Document Number 327405 001 lov 1 O Virtualization LFM Low
173. nications Infrastructure Datasheet Volume 1 of 2 126 May 2012 Document Number 327405 001 e Processor Ball and Package I nformation n tel Ball Signal Ball Signal Ball Signal AD34 SB DQ 58 AF3 SA DQIO AG8 SB DQI9 AD35 SB DQ 62 AF4 SA_DQ 4 AG9 vss AD36 SB_DQ 63 AF5 SA DQS4 0 AG10 SA DQ 16 1 vss AF6 vss AG11 SA_DQ 17 AE2 vss AF7 SB_DQ 12 AG12 VSS AE3 vss AF8 SB_DQ 13 AG13 SB_ECC_CB 0 AE4 vss AF9 vss AG14 SB_ECC_CB 1 AE5 vss AF10 SA_DQ 20 AG15 VSS AE6 vss AF11 SA_DQ 21 AG16 SB_CKE 1 AE7 vss AF12 VSS AG17 VSS AE8 VSS AF13 SB_ECC_CB 4 AG18 SB MA 11 AE9 VSS AF14 SB ECC CB 5 AG19 SB MA 7 AE10 VSS AF15 VSS AG20 VSS 11 VSS AF16 SB_CKE 2 AG21 SB_CK 3 AE12 VSS AF17 VDDQ AG22 SB_CK 3 AE13 VSS AF18 RSVD_1 AG23 VSS AE14 VSS AF19 SM_DRAMPWROK AG24 SB_WE AE15 VDDQ AF20 VDDQ AG25 SB_CS 0 AE16 VDDQ AF21 SA MA 4 AG26 VSS AE17 VDDQ AF22 SA_MAT2 AG27 SB_ODT 1 AE18 VDDQ AF23 VDDQ AG28 SB_ODT 3 AE19 VDDQ AF24 VDDQ AG29 VSS AE20 VDDQ AF25 VSS AG30 SA_DQ 38 AE21 VDDQ AF26 VDDQ AG31 SA_DQ 39 AE22 VDDQ AF27 VSS AG32 VSS AE23 VDDQ AF28 VSS AG33 SB_DQS 6 AE24 VDDQ AF29 VSS AG34 SB_DQ 50 AE25 VDDQ AF30 SA_DQ 34 AG35 SB_DQ 55 AE26 VDDQ AF31
174. nput with exceptions for Spread Spectrum Clocking SSC The processor s maximum core frequency is configured during power on reset by using its manufacturing default value This value is the highest core multiplier at which the processor can operate If lower maximum speeds are desired the appropriate ratio can be configured via the FLEX_RATIO MSR PLL Power Supply An on die PLL filter solution is implemented on the processor Serial Voltage Identification SVI D The SVID specifications for the processor Vcc is defined in the VR12 IMVP7 SVID Protocol The processor uses three signals for the serial voltage identification interface to support automatic selection of voltages Table 9 1 specifies the voltage level corresponding to the eight bit VID value transmitted over serial VID A 1 in this table refers to a high voltage level and a 0 refers to a low voltage level If the voltage regulation circuit cannot supply the voltage that is requested the voltage regulator must disable itself VID signals are CMOS push pull drivers The VID codes change due to temperature and or current load changes in order to minimize the power of the part A voltage range is provided in Table 9 1 The specifications are set so that one voltage regulator can operate with all supported frequencies Individual processor VID values may be set during manufacturing so that two devices at the same core frequency may have different default VID settings This i
175. on Ball Signal A3 vss A4 VSS A5 PCIE1 RX 6 A6 PCIE1 RX 6 A7 VSS A8 PCIE1_RX 1 A9 PCIE1 RX 1 A10 55 11 PCIE2_RX 3 A12 PCIE2_RX 3 A13 vss A14 VCC 15 VCC A16 VSS A17 VCC A18 VCC A19 VSS A20 VCC A21 VCC A22 VSS A23 VCC A24 VCC A25 VSS A26 BPM 4 A27 VSS A28 RSVD 14 A29 RSVD 31 A30 RSVD 13 A31 RSVD 30 A32 VSS A33 RSVD 33 A34 RSVD 54 B2 VSS B3 VSS B4 PCIE1_RX 9 B5 PCIE1_RX 9 B6 VSS B7 PCIE1_RX 4 B8 PCIE1_RX 4 Intel Xeon and Intel Core Processors For Communications Infrastructure Datasheet Volume 1 of 2 120 Ball Signal Ball Signal B9 VSS C13 VSS B10 PCIE2_RX 2 C14 VCC B11 PCIE2_RX 2 C15 VCC B12 vss C16 vss B13 vss C17 VCC B14 VCC C18 vcc B15 VCC C19 VSS B16 VSS C20 VCC B17 VCC C21 VCC B18 VCC C22 VSS B19 VSS C23 vcc B20 VCC C24 VCC B21 VCC C25 VSS B22 VSS C26 2 B23 vcc C27 BPM4 1 B24 VCC C28 RSVD_42 B25 vss C29 VSS B26 BPM 5 C30 vss B27 RSVD_22 C31 RSVD_29 B28 vss C32 RSVD_27 B29 vss C33 RSVD_21 B30 RSVD_12 C34 vss B31 vss C35 RSVD_26 B32 RSVD_53 C36 RSVD_23 B33 vss D1 vss B34 RSVD_28 D2 PCIE1_RX 11 B35 RSVD_52 D3 PCIE1_RX 11 1 vss D4 vss C2 VSS D5 PCIE1_RX 7 C3 PCIE1_RX 10 D6 PCIE1_RX 7 C4 P
176. on the voltage transition precedes the frequency transition On a downward transition the frequency transition precedes the voltage transition When transitioning to a target core operating voltage a new SVID code to the voltage regulator is issued The voltage regulator must support dynamic SVID steps to support this method During the voltage change t is necessary to transition through multiple SVID steps to reach the target operating voltage Each step is 5 mV for Intel MVP 7 0 compliant VRs The processor continues to execute instructions However the processor halts instruction execution for frequency transitions Intel Xeon and Intel Core Processors For Communications Infrastructure Datasheet Volume 1 of 2 May 2012 64 Document Number 327405 001 intel 7 3 1 1 2 7 3 1 2 Note May 2012 If a processor load based Enhanced Intel SpeedStep Technology P state transition through MSR write is initiated while the Adaptive Thermal Monitor is active there are two possible outcomes f the P state target frequency is higher than the processor core optimized target frequency the p state transition is deferred until the thermal event has been completed If the P state target frequency is lower than the processor core optimized target frequency the processor transitions to the P state operating point Clock Modulation If the frequency voltage changes are unable to end an Adaptive Th
177. on is defined by IDD2P1 Exiting this mode is defined by tXP Difference from APD mode is that when waking up all page buffers are empty 3 DLL off In this mode the data in DLLs on DDR are off Power saving in this mode is the best among all power modes Power consumption is defined by IDD2P1 Exiting this mode is defined by tXP but also tXPDLL 10 20 according to DDR type cycles until first data transfer is allowed The processor supports 6 different types of power down These different modes are the power down modes supported by DDR3 and combinations of these modes The type of CKE power down is defined by the configuration The options are Intel Xeon and Intel Core Processors For Communications Infrastructure May 2012 Datasheet Volume 1 of 2 Document Number 327405 001 57 intel s 1 No power down 2 APD The rank enters power down as soon as idle timer expires no matter what is the bank status 3 PPD When idle timer expires the MC sends PRE all to rank and then enters powerdown 4 DLL off same as option 2 but DDR is configured to DLL off 5 APD change to PPD APD PPD Begins as option 1 and when all page close timers of the rank are expired it wakes the rank issues PRE all and returns to PPD 6 APD change to DLL off APD_DLLoff Begins as option 1 and when all page close timers of the rank are expired it wakes the rank issues PRE all and returns to DLL off power down The CKE is
178. on is supported DMI Error Flow DMI can only generate SERR in response to errors never SCI SMI MSI PCI INT or GPE Any related SERR activity is associated with Device 0 DMI Link Down The link going down is a fatal unrecoverable error If the data link goes to data link down after the link was up then the DMI link hangs the system by not allowing the link to retrain to prevent data corruption This link behavior is controlled by the PCH Downstream transactions that had been successfully transmitted across the link prior to the link going down may be processed as normal No completions from downstream non posted transactions are returned upstream over the DMI link after a link down event Platform Environment Control I nterface The PECI is a one wire interface that provides a communication channel between a PECI client processor and a PECI master The processor implements a PECI interface to Intel Xeon and Intel Core Processors For Communications Infrastructure Datasheet Volume 1 of 2 May 2012 36 Document Number 327405 001 intel Interfaces Allow communication of processor thermal and other information to the PECI master Read averaged Digital Thermal Sensor DTS values for fan speed control 3 5 Interface Clocking 3 5 1 Internal Clocking Requirements Table 3 7 Reference Clock Reference Input Clock Input Frequency Associated PLL BCLK BCLK
179. on register Using this method CKE is guaranteed to remain inactive for much longer than the specified 200 micro seconds after power and clocks to SDRAM devices are stable Dynamic Power Down Operation Dynamic power down of memory is employed during normal operation Based on idle conditions a given memory rank may be powered down The IMC implements aggressive CKE control to dynamically put the DRAM devices in a power down state The processor core controller can be configured to put the devices in active power down CKE deassertion with open pages or precharge power down CKE deassertion with all pages closed Precharge power down provides greater power savings but has a bigger performance impact since all pages will first be closed before putting the devices in power down mode If dynamic power down is enabled all ranks are powered up before doing a refresh cycle and all ranks are powered down at the end of refresh DRAM 1 Power Management Unused signals should be disabled to save power and reduce electromagnetic interference This includes all signals associated with an unused memory channel Clocks can be controlled on a per DIMM basis Exceptions are made for per DIMM control signals such as CS and ODT for unpopulated DIMM slots The 1 0 buffer for an unused signal should be tri stated output driver disabled the input receiver differential sense amp should be disabled and any DLL circuitry related ONLY to unused
180. onfiguration it supports DIMMs on both channels DIMMs on one channel and memory down configuration on the other channel or memory down configuration on both channels The processor supports up to two DIMMs per channel Very Low Profile VLP UDIMMs are supported wherever UDIMMs are supported However VLP UDIMMSs have not been fully validated Mixing of ECC and Non ECC DIMMs is not supported Intel Xeon and Intel Core Processors For Communications Infrastructure Datasheet Volume 1 of 2 Document Number 327405 001 23 l n tel Interfaces 3 1 1 1 UDIMM Configurations This section describes the UDIMM modules supported The following DDR3 Data Transfer Rates are supported 1066 MT s PC3 8500 1333 MT s PC3 10600 and 1600 MT s PC3 12800 DDR3 UDIMM Modules Raw Card A Single Sided x8 unbuffered non ECC Raw Card B Double Sided x8 unbuffered non ECC Raw Card C Single Sided x16 unbuffered non ECC Raw Card D Single Sided x8 unbuffered ECC Raw Card E Double Sided x8 unbuffered ECC DDR3 DRAM Device Technology Standard 1 Gb 2 Gb and 4 Gb technologies and addressing are supported for x16 and x8 devices There is no support for memory modules with different technologies or capacities on opposite sides of the same memory module If one side of a memory module is populated the other side is either identical or empty Table 3 1 Supported UDI MM Module Configurations 2
181. oning Note For ERRSYND definition see Table 11 13 Error Syndrome ERRSYND 15 2 RO Oh Reserved RSVD Multiple Bit Error Status MERRSTS This bit is set when an uncorrectable multiple bit error occurs on a memory read data transfer When this bit is set the address that caused the error and the error 1 ROS V 0b Powergood syndrome are also logged and they are locked until this bit is cleared This bit is cleared when the corresponding bit in 0 0 0 PCI ERRSTS is cleared Correctable Error Status CERRSTS This bit is set when a correctable single bit error occurs on a memory read data transfer When this bit is set the address that caused the error and the error syndrome are also logged and they are locked to 0 ROS V 0b Powergood further single bit errors until this bit is cleared A multiple bit error that occurs after this bit is set will override the address error syndrome information This bit is cleared when the corresponding bit in 0 0 0 PCI ERRSTS is cleared 11 6 ECCERRLOG1 CO ECC Error Log 1 B D F Type 0 0 0 MCHBAR MCO Address Offset 40CC 40CFh Default Value 00000000h Access ROS V Size 32 bits This register is used to store the error status information in ECC enabled configurations along with the error syndrome and the row and column address information of the address block of main memory of which an error single bit or multi bit error has occurred Intel Xeon and
182. ons cycle cycle Frequency Source Symbol MHz Type ps Destination Notes cc 100 Input Diff 150 processor memory PCl Express 1 Notes 1 On all jitter measurements care should be taken to set the zero crossing voltage for rising edge of the clock to be the point where the edge rate is the fastest Using a Math function Average Derivative Ch1 and set the averages to 64 place the cursors where the slope is the highest on the rising edge usually the lower half of the rising edge This is defined because Flip Chip components prevent probing at the end of the transmission line This will result in a reflection induced ledge in the middle of the rising edge and will significantly increase measured jitter Table 9 17 System Reference Clock DC and AC Specifications Symbol Parameter Signal Min Max Unit Meas Figure Notes Slew_rise Rising Slew Rate Diff 1 5 4 0 V ns Avg 9 3 2 3 Slew fall Falling Slew Rate Diff 1 5 4 0 V ns Avg 9 3 2 3 Slew_var Slew Rate Matching Single Ended 20 Avg 9 4 1 9 VswING Differential Output Swing Diff 300 mV RT 9 3 2 Intel Xeon and Intel Core Processors For Communications Infrastructure Datasheet Volume 1 of 2 May 2012 102 Document Number 327405 001 Electrica Specifications n tel Table 9 17 System Reference Clock DC and AC Specifications
183. or Communications Infrastructure Datasheet Volume 1 of 2 Document Number 327405 001 35 Interfaces Table 3 6 Note 3 3 Note 3 3 1 3 3 2 3 4 Lane Reversal on PCle Interface The PCI Express lanes can be reversed for ease of design and layout Lane reversal is done statically which means that the BIOS needs to configure the reversal before the relevant root port is enabled For the x16 configuration only one reversal option is supported allowing either a straight or a rotated CPU on the motherboard No other combination of partial slot reversal is permitted The reversal on x8 and x4 configurations are applied in a similar fashion The normal or reversed configuration is determined by the configuration pins CFG 2 for PCI express lanes on Port 1 and CFG 3 for lanes on Port 2 A value of 1 on these inputs would indicate normal operation and a 0 would indicate reversed mode of operation as shown in Table 2 Hardware Straps for Normal Reversed Operation of PCle Lanes PCl e Lanes Normal Reversed Port 1 CFG 2 1 CFG 2 0 Port 2 CFG 3 1 CFG 3 20 Performance estimates on early silicon have shown that bandwidth in x16 mode for Gen 2 is approximately twice the bandwidth in x8 mode for read write and read write transaction Direct Media I nterface Direct Media Interface DMI connects the processor and the PCH Next generation DMI2 is supported Only DMI x4 configurati
184. ost originator can be a third party PECI host with one of the PECI clients being the processor PECI device Intel Xeon and Intel Core Processors For Communications Infrastructure Datasheet Volume 1 of 2 Document Number 327405 001 99 intel Electrical Specifications Figure 9 1 Example of PECI Host Client Connection Creci 10pF Node Host Originator PECI Client Additional PECI Clients 9 10 2 2 PECI DC Characteristics The interface operates at a nominal voltage set by Vccio The set of DC electrical specifications shown in Table 9 13 are used with devices normally operating from a Vccio interface supply Vccio nominal levels will vary between processor families All PECI devices will operate at the Vccio level determined by the processor installed in the system Table 9 13 PECI DC Electrical Limits Sheet 1 of 2 Symbol Definition and Conditions Min Max Units Notes Rup Internal pull up resistance 15 45 Ohm 3 Vin Input Voltage Range 0 15 Vccio Vhysteresis Hysteresis 0 1 Vecio N A Vn Negative Edge Threshold Voltage 0 275 Vecio 0 500 Vccio Vp Positive Edge Threshold Voltage 0 550 Vecio 0 725 Vccio Bus Capacitance per Node N A 10 pF Pad Capacitance 0 7 1 8 pF lleak000 leakage current 0V 0 6 mA 25 leakage current 0 25 Vccio 0 4 lleak050 leakage current 9 0 50 Vccio 0 2 mA Intel Xeon an
185. ot granted a request to a package C6 C7 state but has allowed a package C6 state In package C3 state the L3 shared cache is snoopable Package C6 State A processor enters the package C6 low power state when At least one core is in the C6 state The other cores are in a C6 or lower power state and the processor has been granted permission by the platform The platform has not granted a package C7 request but has allowed a C6 package state In package C6 state all cores have saved their architectural state and have had their core voltages reduced to zero volts The L3 shared cache is still powered and snoopable in this state The processor remains in package C6 state as long as any part of the L3 cache is active Package C7 State The processor enters the package C7 low power state when all cores are in the C7 state and the L3 cache is completely flushed The last core to enter the C7 state begins to shrink the L3 cache by N ways until the entire L3 cache has been emptied This allows further power savings Core break events are handled the same way as in package C3 or C6 However snoops are not sent to the processor in package C7 state because the platform by granting the package C7 state has acknowledged that the processor possesses no snoopable information This allows the processor to remain in this low power state and maximize its power savings Upon exit of the package C7 state the L3 cache is not immediately re
186. put Pin Output Pin 1 0 Bi directional Input Output Pin The signal description also includes the type of buffer used for the particular signal Signal Description Buffer Types Signal Description Express interface signals These signals are compatible with Express 2 0 PCI Express Signalling Environment AC Specifications and are AC coupled The buffers are not 3 3 V tolerant See the PCle specification Direct Media Interface signals These signals are compatible with Express 2 0 DMI Signaling Environment AC Specifications but are DC coupled The buffers are not 3 3 V tolerant CMOS CMOS buffers 1 1 V tolerant DDR3 DDR3 buffers 1 5 V tolerant A Analog reference or output May be used as a threshold voltage or for buffer compensation Ref Voltage reference signal Asynchronous Signal has no timing relationship with any reference clock Notes 1 Qualifier for a buffer type System Memory Interface Memory Channel A Sheet 1 of 2 Signal Name Description xd Buffer ype SA BS 2 0 Bank Select These signals define which banks are selected within each SDRAM rank DDR3 Write Enable Control Signal Used with o SA_WE SA_RAS and SA_CAS along with SA_CS to define the SDRAM Commands DDR3 RAS Control Signal Used with SA_CAS and o SA_RAS SA_WE along with SA_CS to define the SRAM Commands DDR3 Document Number
187. re Software Developer s Manual Volume 3A 3B System Programmer s Guide for more information While a core is in C1 CIE state it processes bus snoops and snoops from other threads For more information on CIE see Section 6 2 5 2 Package C1 CIE Intel Xeon and Intel Core Processors For Communications Infrastructure Datasheet Volume 1 of 2 May 2012 52 Document Number 327405 001 intel 6 2 4 3 6 2 4 4 6 2 4 5 Note 6 2 4 6 6 2 5 May 2012 Core C3 State Individual threads of a core can enter the state by initiating a P LVL2 1 0 read to the P BLK or an MWAIT C3 instruction A core in C3 state flushes the contents of its L1 instruction cache L1 data cache and L2 cache to the shared L3 cache while maintaining its architectural state All core clocks are stopped at this point Because the core s caches are flushed the processor does not wake any core that is in the C3 state when either a snoop is detected or when another core accesses cacheable memory Core C6 State Individual threads of a core can enter the state by initiating a P LVL3 1 0 read or an MWAIT C6 instruction Before entering core C6 the core will save its architectural state to a dedicated SRAM Once complete a core will have its voltage reduced to zero volts During exit the core is powered on and its architectural state is restored Core C7 State Individual threads of a core can enter the C7 state by initiating a P_
188. rom catastrophic overheating by use of an internal thermal sensor This sensor is set well above the normal operating temperature to ensure that there are no false trips The processor stops all execution when the junction temperature exceeds approximately 130 C This is signaled to the system by the THERMTRIP pin See the appropriate platform design guide for termination requirements Asynchronous CMOS 2012 Document Number 327405 001 Intel Xeon and Intel Core Processors For Communications Infrastructure Datasheet Volume 1 of 2 77 intel 8 9 Power Sequencing Table 8 11 Power Sequencing Signal Description Signal Name Description Direction Buffer Type SM_DRAMPWROK Processor Input Connects to SM_DRAMPWROK PCH DRAMPWROK Asynchronous CMOS The processor requires this input signal to be a clean indication that the VCCSA VCCIO VAXG and VDDQ power supplies are stable and within specifications This requirement applies regardless of the S state of the processor Clean implies that the signal remains UNCOREPWRGOOD low capable of sinking leakage current without Asynchronous glitches from the time that the power supplies are CMOS turned on until they come within specification The signal must then transition monotonically to a high state This is connected to the PCH PROCPWRGD signal PROC_DETECT PROC_DETECT Processor Detect pulled to grou
189. rsion of the 2nd Generation Intel Core Processor Family Mobile Datasheet Volume 2 Error Detection and Correction If ECC is enabled and DIMMS with ECC are used through an Error Correction Code algorithm the memory controller is able to detect and correct single bit errors or detect multiple bit errors ECC increases the reliability of the DRAM devices by allowing single bit errors to be fixed and detecting multi bit errors but it requires additional bits to store the error correction code The ECC algorithm requires an 8 bit error correction code DIMMs with ECC are 72 bits wide the first 64 bits are for data and the last 8 bits are for the Check Bits Detection of correctable or uncorrectable errors are reported in the ERRSTS Error Status register When either Single bit correctable or Multi bit uncorrectable errors are detected the column row bank and rank that caused the error and the error syndrome are logged in the ECC Error Log registers in the channel where the error occurred Channel 0 and Channel 1 errors are detailed in Section 11 5 ECCERRLOGO CO ECC Error Log 0 Section 11 6 ECCERRLOG1_CO ECC Error Log 1 Section 11 7 ECCERRLOGO C1 ECC Error Log 0 and Section 11 8 ECCERRLOGI C1 ECC Error Log 1 respectively If an uncorrectable error occurs after a correctable error then the address and syndrome information will be replaced with the uncorrectable error information During the write cycle E
190. s shown in the VID range values in Table 9 5 The processor provides the ability to operate while transitioning to an adjacent VID and its associated voltage This represents a DC shift in the loadline Transitions above the maximum specified VID are not permitted Table 9 5 includes VID step sizes and DC shift ranges Minimum and maximum voltages must be maintained The VR utilized must be capable of regulating its output to the value defined by the new VID values issued DC specifications for dynamic VID transitions are included in Table 9 5 while AC specifications are included in Table 9 24 I MVP7 Voltage Identification Definition Sheet 1 of 8 VID7 VID6 VID5 VIDA VID3 VID2 VID1 VIDO HEX Vcc 0 0 0 0 0 0 0 0 0 00000 0 0 0 0 0 0 0 1 0 1 0 25000 0 0 0 0 0 0 1 0 012 0 25500 0 0 0 0 0 0 1 1 0 3 0 26000 0 0 0 0 0 1 0 0 014 0 26500 0 0 0 0 0 1 0 1 0 5 0 27000 0 0 0 0 0 1 1 0 0 6 0 27500 0 0 0 0 0 1 1 1 0 7 0 28000 Intel Xeon and Intel Core Processors Communications Infrastructure Datasheet Volume 1 of 2 May 2012 82 Document Number 327405 001 Electrical Specifications intel Table 9 1 IMVP7 Voltage Identification Definition Sheet 2 of 8 VID7 VID6 VID5 VID4 VID3 VID2 VID1 VIDO
191. s supported Queued invalidation is supported VT d translation bypass address range is supported Pass Through Support for ARI Alternative Requester ID a PCI SIG ECR for increasing the function number count in a PCle device to support IOV devices Intel VT d Features Not Supported The following features are not supported by the processor with Intel VT d No support for PCISIG endpoint caching ATS support for Intel VT d read prefetching snarfing i e translations within a cacheline are not stored in an internal buffer for reuse for subsequent translations No support for advance fault reporting No support for super pages No support for Intel VT d translation bypass address range such usage models need to be resolved with VMM help in setting up the page tables correctly Intel Hyper Threading Technology The processor supports Intel Hyper Threading Technology Intel HT Technology which allows an execution core to function as two logical processors While some execution resources such as caches execution units and buses are shared each logical processor has its own architectural state with its own set of general purpose registers and control registers This feature must be enabled via the BIOS and requires operating system support Intel recommends enabling Hyper Threading Technology with Microsoft Windows 7 Microsoft Windows Vista Microsoft Windows XP Professional Windows XP Home and dis
192. s to an optimized voltage This voltage is signaled by the SVID bus to the voltage regulator Once the voltage is established the PLL locks on to the target frequency If the target frequency is lower than the current frequency the PLL locks to the target frequency then transitions to a lower voltage by signaling the target voltage on the SVID bus All active processor cores share the same frequency and voltage In a multi core processor the highest frequency P state requested amongst all active cores is selected Software requested transitions are accepted at any time If a previous transition is in progress the new transition is deferred until the previous transition is completed The processor controls voltage ramp rates internally to ensure glitch free transitions Because there is low transition latency between P states a significant number of transitions per second are possible Low Power I dle States When the processor is idle low power idle states C states are used to save power More power savings actions are taken for numerically higher C states However higher C states have longer exit and entry latencies Resolution of C states occur at the thread processor core and processor package level Thread level C states are available if Intel Hyper Threading Technology is enabled Long term reliability cannot be assured unless all the Low Power Idle States are enabled Idle Power Management Breakdown of the Proces
193. signals should be disabled The input path must be gated to prevent spurious results due to noise on the unused signals typically handled automatically when input receiver is disabled PCle Power Management Active power management support using LOs and L1 states All inputs and outputs disabled L2 L3 Ready state PCle interface does not support Hot Plug Power impact may be observed when PCle link disable power management state is used DMI Power Management Active power management support using LOs L1 state Thermal Power Management See Section 7 0 Thermal Management on page 61 for all thermal power management related features 5 5 Intel Xeon Intel Core Processors Communications Infrastructure Datasheet Volume 1 of 2 Document Number 327405 001 59 intel Intel Xeon and Intel Core Processors For Communications Infrastructure Datasheet Volume 1 of 2 May 2012 60 Document Number 327405 001 intel 7 0 Thermal Management The thermal solution provides both the component level and the system level thermal management To allow for the optimal operation and long term reliability of Intel processor based systems the system processor thermal solution should be designed so that the processor Remains below the maximum junction temperature TJ MAX specification at the maximum Thermal Design Power TDP Conforms to system constraints such as system acoustics
194. sor Cores Thread 0 Thread 1 Thread 0 Thread 1 Core 0 State Core 1 State Processor Package State Intel Xeon and Intel Core Processors For Communications Infrastructure Datasheet Volume 1 of 2 50 May 2012 Document Number 327405 001 intel Entry and exit of the C States at the thread and core level are shown in Figure 6 3 Figure 6 3 Thread and Core C State Entry and Exit Table 6 7 6 2 3 Note May 2012 Mute HUT MWATT C7 MWAIT C6 P_I LVL4 1 0 Read C1E Enabled MWAIT C3 s P_LVL3 I O Read CES TY O WU While individual threads can request low power C states power saving actions only take place once the core C state is resolved Core C states are automatically resolved by the processor For thread and core C states a transition to and from is required before entering any other C state Coordination of Thread Power States at the Core Level Processor Core Thread 1 C State em co CO CO CO CO ka c1 co cit C11 cil cii 3 co C3 C3 C3 C6 CO 11 C3 C6 c7 CO 11 C3 C6 Requesting Low Power Idle States The primary software interfaces for requesting low power idle states are through the MWAIT instruction with sub state hints and the HLT instruction for C1 and CIE However software may make C st
195. ss F8 VSS J8 VSS M25 vss F9 55 11 55 M28 vss F10 VSS 13 VSS M29 VSS F11 VSS 116 vss M30 VSS F12 VSS J19 VSS M31 VSS F13 VSS 22 vss M33 VSS F16 VSS 25 VSS M35 VSS F19 VSS 128 vss 1 Intel Xeon and Intel Core Processors For Communications Infrastructure May 2012 Datasheet Volume 1 of 2 138 Document Number 327405 001 Processor Package Information n tel Signal Ball Signal Ball Signal Ball vss VSS T5 vss W6 VSS N7 vss T9 vss w9 VSS N11 VSS T13 VSS W13 VSS N13 VSS T16 VSS W16 VSS N16 VSS T19 VSS W19 55 19 vss T22 VSS W22 VSS N22 VSS T25 VSS W25 VSS N25 55 T28 vss W28 vss N27 vss T30 vss W31 vss N30 vss T31 vss Y10 vss P2 vss U3 vss Y13 vss P3 vss U5 vss Y16 vss P4 vss U6 vss Y19 VSS P5 VSS 010 vss Y22 VSS P8 VSS U11 VSS Y25 VSS P10 VSS 013 VSS Y28 vss P13 vss U16 VSS Y31 VSS P16 VSS 019 vss Y32 vss P19 vss U22 vss Y33 vss P22 vss U25 vss Y34 vss P25 vss U27 vss Y35 vss P27 vss U30 VSS Y36 VSS P30 VSS U31 VSS AA8 VSS P31 VSS U32 VSS AA10 vss P32 VSS U33 VSS 11 vss P33 VSS U34 vss AA13 VSS P34 VSS U35 VSS AA16 VSS P35 VSS U36 vss AA19 vss P36 VSS v3 VSS AA22 vss R2 vss V6 vss AA25 VSS R5 VSS V10 VSS AA27 VSS R10 VSS V13 VSS 1 VSS R13 vss V16 vss AB1 vss R16 vss V19 vss AB2 vss R19 vss V22 VSS AB3 vss R22 vss 25 vss AB4 VSS R25 VSS V27 VSS
196. st They fall through like a normal 1 0 instruction When P LVLx instructions are used MWAIT substates cannot be defined The MWAIT substate is always zero if I O MWAIT redirection is used By default P LVLx I O redirections enable the MWAIT break on EFLAGS IF feature which triggers a wakeup on an interrupt even if interrupts are masked by EFLAGS IF Core C states The following are general rules for all core C states unless specified otherwise A core C State is determined by the lowest numerical thread state e g Thread 0 requests C1E while Thread 1 requests resulting in a core CIE state See Table 6 6 G S and C State Combinations A core transitions to CO state when An interrupt occurs There is an access to the monitored address if the state was entered via an MWAIT instruction For core C1 C1E and core and core C6 C7 an interrupt directed toward single thread wakes only that thread However since both threads are no longer at the same core C state the core resolves to CO A system reset re initializes all processor cores Core CO State The normal operating state of a core where code is being executed Core C1 CIE State C1 CIE is a low power state entered when all threads within a core execute HLT or MWAIT C1 C1E instruction A System Management Interrupt SMI handler returns execution to either Normal state or the C1 CIE state See the Intel 64 and IA 32 Architectu
197. support ECC this bit must be disabled 11 3 B D F Type Address Offset Default Value Access Size BIOS Optimal Default SMI CMD SMI Command 0 0 0 PCI CC CDh 0000h RO RW 16 bits 0000h This register enables various errors to generate an SMI DMI special cycle When an error flag is set in the ERRSTS register it can generate an SERR SMI or SCI DMI special cycle when enabled in the ERRCMD SMICMD or SCICMD registers respectively One and only one message type can be enabled Table 11 5 SMI Command Registers Bit Access tat EE Description 15 2 RO Oh Reserved RSVD SMI on Multiple Bit DRAM ECC Error DMESMI 1 The Host generates an SMI message when it detects a multiple bit error reported by the DRAM 1 RW Ob Uncore controller 0 Reporting of this condition via SMI messaging is disabled For systems not supporting ECC this bit must be disabled SMI on Single bit ECC Error DSESMI 1 The Host generates an SMI special cycle when the DRAM controller detects a single bit 0 RW Ob Uncore error 0 Reporting of this condition via SMI messaging is disabled For systems that do not support ECC this bit must be disabled Intel Xeon and Intel Core Processors For Communications Infrastructure Datasheet Volume 1 of 2 154 May 2012 Document Number 327405 001 e Processor Configuration Registers n tel 11 4 Table 11 6 11 5 May 20
198. system skin temperatures and exhaust temperature requirements Caution Thermal specifications given in this chapter are on the component and package level and apply specifically to the processor Operating the processor outside the specified limits may result in permanent damage to the processor and potentially other components in the system 7 1 Thermal Design Power TDP and Junction Temperature The is the maximum sustained power that should used design of the processor thermal solution TDP represents an expected maximum sustained power from realistic applications TDP may be exceeded for short periods of time or if running a power virus workload The processor integrates multiple CPU on a single die This may result in differences in the power distribution across the die and must be considered when designing the thermal solution See the 2nd Generation Intel Core Processor For Communications Infrastructure Thermal Mechanical Design Guide for more details 7 2 Thermal and Power Specifications The following notes apply to Table 7 1 and Table 7 2 Note Definition The TDPs given are not the maximum power the processor can generate Analysis indicates that 1 real applications are unlikely to cause the processor to consume the theoretical maximum power dissipation for sustained periods of time The thermal solution needs to ensure that the processor temperature does not
199. t Number Location 2 2nd Generation Intel Core Processor Family Mobile Datasheet Volume 2 of 324803 http www intel com content dam doc datasheet 2nd gen core family mobile vol 2 datasheet pdf Intel Xeon and Intel Core Processors For Communications Infrastructure Thermal Mechanical Design Guide 327397 http download intel com embedded processors thermalguide 327397 pdf Specification Update Intel Xeon and Intel Core Processors For Communications Infrastructure 327335 http download intel com embedded processor specupdate 327335 pdf Document Number 327405 001 Intel Xeon and Intel Core Processors For Communications Infrastructure Datasheet 1 of 2 11 intel Table 1 2 Public Specifications Introduction Document Document Number Location Advanced Configuration and Power Interface Specification 3 0 http www acpi info PCI Local Bus Specification 3 0 http www pcisig com specifications PCI Express Base Specification Rev 2 0 http www pcisig com DDR3 SDRAM Specification http www jedec org DisplayPort Specification http www vesa org Volume 1 Basic Architecture Volume 2A Instruction Set Reference A M Volume 2B Instruction Set Reference N Z Volume 3A System Programming Guide Volume 3B System Programming Guide Intel 64 and IA 32 Architectures Softwar
200. t desirable RSW1C Read Set Write 1 to Clear These bits can be read and cleared by software Reading a bit will set the bit to 1 Writing a 1 to a bit will clear it while writing a 0 to a bit has no effect Read Clear Write These bits can be read and written by software but a read causes the RCW bits to be cleared NOTE Use of this attribute type is only allowed on legacy functions as side effects on reads are not desirable Table 11 2 lists the modifiers used in conjunction with attributes that are included in the register tables throughout this document Intel Xeon and Intel Core Processors For Communications Infrastructure Datasheet Volume 1 of 2 Document Number 327405 001 151 intel Processor Configuration Registers Table 11 2 Register Terminology Attribute Modifier 11 1 Attribute Modifier Applicable Attribute Description RO with V RW Sticky These bits are only re initialized to their 5 default value Power Good Reset ote Does not apply to constant bits RW1C N D bi RW1S K RW Key These bits control the ability to write other bits identified with a Lock modifier RW Lock Hardware can make these bits Read Only via a AE separate configuration bit or other logic WO Note Mutually exclusive with Once modifier RW Once After reset these bits can only be rewritten by O software once after which they become R
201. t in prolonged operation at or above the specified maximum junction temperature and affect the long term reliability of the processor May be incapable of cooling the processor even when the TCC is active continuously in extreme situations See the 2nd Generation Intel Core Processor For Communications Infrastructure Thermal Mechanical Design Guide for information on implementing the bi directional feature and designing a compliant thermal solution Low Power States and PROCHOT Behavior If the processor enters a low power package idle state such as or C6 C7 with PROCHOT asserted PROCHOT remains asserted until The processor exits the low power state The processor junction temperature drops below the thermal trip point For the package C7 state PROCHOT may deassert for the duration of C7 state residency even if the processor enters the idle state operating at the TCC activation temperature The PECI interface is fully operational during all C states and it is expected that the platform continues to manage processor package core thermals even during idle states by regularly polling for thermal data over PECI THERMTRI P Signal Regardless of enabling the automatic or on demand modes in the event of a catastrophic cooling failure the package automatically shuts down when the silicon has reached an elevated temperature that risks physical damage to the product At this point the THERMTRIP signal is
202. tel Xeon and Intel Core Processors For Communications Infrastructure Datasheet Volume 1 of 2 May 2012 92 Document Number 327405 001 Electrical Specifications n tel Table 9 4 9 10 May 2012 Storage Condition Ratings Symbol Parameter Min Max Notes The non operating device storage temperature Damage latent or otherwise _5 Tabsolute storage may occur when exceeded for any length of 25 C 125 C l 2 3 4 time 1 The ambient storage temperature in shipping LR Tsustained storage media for a sustained period of time 5 C 40 5 6 The ambient storage temperature in shipping 5 Tshort term storage media for a short period of time 20 C 85 C maximum device storage relative RHsustained storage humidity for a sustained period of time 60 24 C 6 7 A prolonged or extended period of time Time sustained storage typically associated with customer shelf life 0 Months e Months l Timeshort term storage A short period of time 0 hours 72 hours Notes 1 Refers to component device that is not assembled in board socket and is not electrically connected to a voltage reference or 1 0 signal 2 Specified temperatures are not to exceed values based data collected Exceptions for surface mount reflow are specified by the applicable JEDEC standard Non adherence may affect processor reliability 3 Tabsolute stora
203. tes apply to Table 9 18 Table 9 19 and Table 9 20 Note Definition 1 Unless otherwise noted all specifications in this table apply to all processor frequencies Timing specifications only depend on the operating frequency of the memory channel and not the maximum rated frequency When the single ended slew rate of the input Data or Strobe signals within a byte group are below 1 0 V ns the Tsu and Typ specifications must be increased by a derrating factor The input single ended slew rate 2 is measured DC to AC levels pc to for rising edges and pc to Ac for falling edges Use the worse case minimum slew rate measured between Data and Strobe within a byte group to determine the required derrating value No derrating is required for single ended slew rates equal to or greater than 1 0 V ns Edge Placement Accuracy EPA The silicon contains digital logic that automatically adjusts the timing relationship 3 between the DDR reference clocks and DDR signals The BIOS initiates a training procedure that will place a given signal appropriately within the clock period The difference in delay between the signal and clock is accurate to within EPA This EPA includes jitter skew within die variation and several other effects 4 Data to Strobe read setup and Data from Strobe read hold minimum requirements specified at the processor pad are determined with the minimum Read DQS DQS delay
204. the error syndrome and the rank and bank address information of the address block of main memory of which an error single bit or multi bit error has occurred The address fields represent the address of the first single or the first multiple bit error occurrence after the error flag bits in the ERRSTS register have been cleared by software A multiple bit error will overwrite a single bit error Intel Xeon and Intel Core Processors For Communications Infrastructure Datasheet Volume 1 of 2 Document Number 327405 001 155 n tel Processor Configuration Registers Once the error flag bits are set as a result of an error this bit field is locked and doesn t change as a result of a new error until the error flag is cleared by software Same is the case with error syndrome field Table 11 7 Channel ECC Error Log 0 Default RST Bit Access Value PWR Description Error Bank Address ERRBANK 31 29 ROS V 000b Powergood This field holds the Bank Address of the read transaction that had the ECC error Error Rank Address ERRRANK 28 27 ROS V 00b Powergood This field holds the Rank ID of the read transaction that had the ECC error Error Chunk ERRCHUNK 26 24 ROS V 000b Powergood Holds the chunk number of the error stored in the register Error Syndrome ERRSYND This field contains the error syndrome A value of FFh 23 16 ROS V 00h Powergood indicates that the error is due to pois
205. the various VIDs Decoupling Guidelines Due to its large number of transistors and high internal clock speeds the processor is capable of generating large current swings between low and full power states To keep voltages within specification output decoupling must be properly designed Design the board to ensure that the voltage provided to the processor remains within the specifications listed in Table 9 5 Failure to do so can result in timing violations or reduced lifetime of the processor Voltage Rail Decoupling The voltage regulator solution must Provide sufficient decoupling to compensate for large current swings generated during different power mode transitions Provide low parasitic resistance from the regulator to the socket Meet voltage and current specifications as defined in Table 9 5 Intel Xeon and Intel Core Processors For Communications Infrastructure Datasheet Volume 1 of 2 Document Number 327405 001 81 m e tel Electrical Specifications 9 3 1 9 4 Note Table 9 1 Processor Clocking BCLK BCLK The processor utilizes a differential clock to generate the processor core s operating frequency memory controller frequency and other internal clocks The processor core frequency is determined by multiplying the processor core ratio by 100 MHz Clock multiplying within the processor is provided by an internal phase locked loop PLL which requires a constant frequency i
206. through the other layers they are extended with additional information necessary to handle packets at those layers At the receiving side the reverse process occurs and packets get transformed from their Physical Layer representation to the Data Link Layer representation and finally for Transaction Layer Packets to the form that can be processed by the Transaction Layer of the receiving device Figure 3 3 Packet Flow through the Layers i Sequences mei n m reme s se on LIIILII LIII _ Transaction Layer Data Link Layer Physica Layer 3 2 1 1 Transaction Layer The upper layer of the PCI Express architecture is the Transaction Layer The Transaction Layer s primary responsibility is the assembly and disassembly of Transaction Layer Packets TLPs TLPs are used to communicate transactions such as read and write as well as certain types of events The Transaction Layer also manages flow control of TLPs 3 2 1 2 Data Link Layer The middle layer in the PCI Express stack the Data Link Layer serves as an intermediate stage between the Transaction Layer and the Physical Layer Responsibilities of Data Link Layer include link management error detection and error correction The transmission side of the Data Link Layer accepts TLPs assembled by the Transaction Layer calculates and applies data protection code and TLP sequence number and submits them to Physical Layer for transmission
207. tion of data signals and clock signals Ringing below receiver thresholds non monotonic signal edges and excessive voltage swings will adversely affect system timings Ringback and signal non monotonically cannot be tolerated since these phenomena may inadvertently advance receiver state machines Excessive signal swings overshoot and undershoot are detrimental to silicon gate oxide integrity and can cause device failure if absolute voltage limits are exceeded Overshoot and undershoot can also cause timing degradation due to the build up of inter symbol interference ISI effects For these reasons it is crucial that the designer work towards a solution that provides acceptable signal quality across all systematic variations encountered in volume manufacturing This section documents signal quality metrics used to derive topology and routing guidelines through simulation All specifications are specified at the processor die pad measurements Specifications for signal quality are for measurements at the processor core only and are only observable through simulation Therefore proper simulation is the only way to verify proper timing and signal quality Intel Xeon and Intel Core Processors For Communications Infrastructure Datasheet Volume 1 of 2 May 2012 114 Document Number 327405 001 m Electrical Specifications n tel 9 13 1 9 13 2 9 13 3 9 14 9 14 1 Table 9 25 May 2012 Input Reference C
208. to 32 bits allowing for interrupt processor addressability up to 4G 1 processors in physical destination mode A processor implementation of x2APIC architecture can support fewer than 32 bits in a software transparent fashion Logical xAPIC ID field increases from 8 bits to 32 bits The 32 bit logical x2API C ID is partitioned into two sub fields a 16 bit cluster ID and a 16 bit logical ID within the cluster Consequently 2 20 16 processors can be addressed in logical destination mode Processor implementations can support fewer than 16 bits in the cluster ID sub field and logical ID sub field in a software agnostic fashion More efficient MSR interface to access APIC registers To enhance inter processor and self directed interrupt delivery as well as the ability to virtualize the local APIC the APIC register set can be accessed only through MSR based interfaces in the x2APIC mode The Memory Mapped IO MMI O interface used by xAPIC is not supported in the x2APIC mode The semantics for accessing APIC registers have been revised to simplify the programming of frequently used APIC registers by system software Specifically the software semantics for using the Interrupt Command Register ICR and End Of Interrupt EOI registers have been modified to allow for more efficient delivery and dispatching of interrupts The x2APIC extensions are made available to system software by enabling the local x2APIC unit in the x2APIC
209. unch mode programming depends on the transfer rate and memory configuration Intel Xeon and Intel Core Processors For Communications Infrastructure Datasheet Volume 1 of 2 May 2012 26 Document Number 327405 001 Interfaces Table 3 4 3 1 3 3 1 3 1 3 1 3 2 Note May 2012 DDR3 System Memory Timing Support Processor DIMMs Per 7 tCL tRCD tRP CWL CMD SKUs Channel tCK tCK tCK tCK Mode MT s 1 DPC 1066 7 7 7 6 1n 2n 4 Core 1 SKUs 986 1333 9 9 9 7 1n 2n 1 DPC only 1600 11 11 11 8 1n 2n 7 7 7 6 1n 2n 1 DPC e 2 Core 2 DPC 8 8 8 6 1n 2n SKUs 1 DPC 2e 1333 9 9 9 7 1n 2n 7 7 7 7 6 1n 2n ae 1 DPC only 1066 5 8 8 8 6 1n 2n Note System memory timing support is based on availability and is subject to change System Memory Organization Modes The processor supports two memory organization modes single channel and dual channel Depending upon how the DIMM Modules are populated in each memory channel a number of different configurations can exist Single Channel Mode In this mode all memory cycles are directed to a single channel Single channel mode is used when either Channel A or Channel B DIMM connectors are populated in any order but not both Dual Channel Mode Intel Flex Memory Technology Mode The processor supports Intel Flex Memory Technology Mode Memory is divided into a symmetric and an asymmetric zone The symmetric
210. upling a 81 Processor Clocking BCLK nemen nnns 82 9 3 1 PLL Power Supply xerit pa teh het Rte eE E E Rea dd 82 Serial Voltage Identification SVID nnn 82 System Agent SA VCC VID EEE EEE nnne EE EE nn nnn 89 Reserved Unused Signals edd dieser do ei vomer pr re EFE Cerea dees 90 90 Test Access Port Connection emen nne ena 92 Storage Conditions Specifications r eee meses ens 92 DC 5 TUE 93 9 10 1 Voltage and Current 94 9 10 2 Platform Environmental Control Interface DC Specifications 99 Specifications saa Gashi ceeds 101 9 11 1 DDR3 AC Specifications 2 0 0 0 nes 103 9 11 2 PCI Express AC Specification mmm 107 9 11 3 Miscellaneous AC Specifications cece een 108 9 11 4 TAP Signal Group AC rr 108 9 11 5 SVID Signal Group AC Specifications 109 Processor AC Timing Waveforms ne 109 Signal Quality eer eerte Pub in eee ween A TTEA 114 9 13 1 Input Re
211. vidually This feature is disabled by default BIOS must enable it in the PMG CST CONFIG CONTROL register The auto demotion policy is also configured by this register Package C States The processor supports CO C1 C1E C3 C6 and C7 power states The following is a summary of the general rules for package C state entry These apply to all package C states unless specified otherwise Intel Xeon and Intel Core Processors For Communications Infrastructure Datasheet Volume 1 of 2 Document Number 327405 001 53 m e n tel Power Management A package C state request is determined by the lowest numerical core C state amongst all cores A package C state is automatically resolved by the processor depending on the core idle power states and the status of the platform components Each core can be at a lower idle power state than the package if the platform does not grant the processor permission to enter a requested package C state The platform may allow additional power savings to be realized in the processor For package C states the processor is not required to enter CO before entering any other C state The processor exits a package C state when a break event is detected Depending on the type of break event the processor does the following f a core break event is received the target core is activated and the break event message is forwarded to the target core f the break event is not
212. while meeting specifications for junction temperature clock frequency and input voltages Read all notes associated with each parameter AC tolerances for all DC rails include dynamic load currents at switching frequencies up to 1 MHZ Intel Xeon and Intel Core Processors For Communications Infrastructure Datasheet Volume 1 of 2 Document Number 327405 001 93 intel Electrical Specifications 9 10 1 Voltage and Current Specifications Note The following specifications and parameters are based on characterized data from silicon measurements Table 9 5 Processor Core VCC DC Voltage and Current Specifications Sheet 1 of 2 Product Symbol Parameter Number Min Typ Max Unit Note E3 1125C 0 8 1 35 VitoR E3 1105C 0 8 1 35 ange for Highes HFM_VID Frequency Mode i3 2115C 0 75 1 3 V 1 2 7 9 B915C 0 70 1 2 725C 0 70 1 2 1125 0 65 0 95 VDR fans t E3 1105C 0 65 0 95 ange for Lowes LFM_VID Frequency Mode i3 2115C 0 65 0 90 V 1 2 9 B915C 0 65 0 90 725C 0 65 0 90 Vcc Vcc for processor core 0 3 1 52 V 2 3 4 E3 1125C 57 1105 33 isang Processor Core i3 2115C 30 A 5 7 9 Ps B915C 23 725C 10 E3 1125C 35 E3 1105C 22 Icc Thermal Design i3 2115C 18 A 6 7 9 B915C 13 725C 8 E3 1125C 28 E3 1105C 28 LFM lec at LFM 13 2115C 15 6 B915C 15 725C 8 E3 1125C 22 E3 1105C 22 TDC tem TDC at LFM 13 2115C 12 A 6 B915C 12
213. xperience excursions above Vccio However input signal drivers must comply with the signal quality specifications Intel Xeon and Intel Core Processors For Communications Infrastructure Datasheet Volume 1 of 2 98 May 2012 Document Number 327405 001 Electrical Specifications Table 9 12 PCI Express DC Specifications Symbol Parameter Min Typ Max Units Notes VTX DIFF p p Differential Peak to Peak Tx Voltage Swing 0 4 0 5 0 6 V 4 Tx AC Peak Common Mode Output Voltage Gen 1 Vix Only p 9 0 8 1 1 2 mV 1 2 5 ZTX DIFF DC DC Differential Tx Impedance Gen 1 Only 80 120 1 9 ZRX DC DC Common Mode Rx Impedance 40 60 1 7 8 ZRX DIFF DC DC Differential Rx Impedance Gen1 Only 80 120 1 Differential Rx Input Peak to Peak Voltage Gen 1 VRX DIFFp p only 0 175 1 2 V 1 3 10 VRX CM AC p Rx AC Peak Common Mode Input Voltage 150 mV 1 6 Notes 1 See the PCI Express Base Specification for details 2 and Vrx ac cm p are defined in the PCI Express Base Specification Measurement is made over at least 10 6 Ul 3 See Figure 9 8 Express Receiver Eye Margins on page 113 4 As measured with compliance test load Defined as 2 V Txp 5 RMS value 6 Measured at Rx pins into a pair of 50 Q terminations into ground Common mode peak voltage is defined by the expression max Vd Vd V CMDC 7 impedance limits n
214. yption based on the Advanced Encryption Standard AES Intel AES NI are valuable for a wide range of cryptographic applications for example applications that perform bulk encryption decryption authentication random number generation and authenticated encryption AES is broadly accepted as the standard for both government and industry applications and is widely deployed in various protocols Intel AES NI consists of six Intel SSE instructions Four instructions namely AESENC AESENCLAST AESDEC and AESDELAST facilitate high performance AES encryption and decryption The other two namely AESIMC and AESKEYGENASSIST support the AES key expansion procedure Together these instructions provide a full hardware for support AES offering security high performance and a great deal of flexibility 4 4 1 PCLMULQDQ Instruction The processor supports the carry less multiplication instruction PCLMULQDQ PCLMULQDQ is a Single Instruction Multiple Data SIMD instruction that computes the 128 bit carry less multiplication of two 64 bit operands without generating and propagating carries Carry less multiplication is an essential processing component of several cryptographic systems and standards Hence accelerating carry less multiplication can significantly contribute to achieving high speed secure computing and communication 4 5 Intel 64 Architecture x2API C The x2APIC architecture extends the xAPIC architecture which provides key mec

Intel Xeon E3-1105C

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