Elixir 4GB PC3-10600
Contents
1. 50 paso M 5954 M Daso q DQS4 0 DMO DM CS Das DOS DM CS Das Das 100 DQ32 N 0 0 M VO 1 DQ33 N VO 1 Daz 02 0034 N 02 N 103 0035 N 0 3 D4 04 104 0036 O 4 005 N 05 0037 N 05 N 106 N O 6 DQ7 N 107 ZQ DQ39 N 107 za n DAST M 5955 bast pass DM DM5 M 3 DM CS Das Das DM CS Das Das 00 0040 N 100 Dag JN 101 DQ41 701 2010 02 2042 N 02 2911 103 D1 0043 N 103 D5 DQ12 N 04 DQ44 N 1 04 2013 105 0045 N 105 2014 N 106 DO46 N 106 0015 N 107 za DQ47 N 07 za 5052 5956 DQS2 DQS6 DM2 DM6 M 3 DM CS Das DOS DM CS Das Das pais N 100 0048 N 100 0017 1 2049 701 pais N 02 0050 02 0019 N 03 02 0051 N 103 D6 0020 N 1 04 0052 N 1 04 0021 N 05 0053 105 0022 N 1 06 0054 N 106 0023 N 1 07 zo a DQ55 N 1 07 za n pass M 5957 M 09 3 0057 DM3 DM7 M 3 DM CS Das Das DM CS Das Das 0024 N 1 00 0056 N 100 DQ25 N 101 DQ57 N VO 1 0026 N 102 pass N 102 0027 N 1 03 D3 0059 N 03 D7 0028 N 1 04 202. N voo 1 0 0 2040 N 1 0 0 N 1 VO 1 0941 701 VO 1 DQ10 02 2 0042 N 02 2 0011 103 D1 1 0 3 D9 DQ43 N D5 013 912 104 VO 4 0044 704 VO 4 0013 705 5 0045 705 5 0014 6 6 5046 N 706 6 pais N 707 za mm 707 za 2947 w za VO7 za DQS2 DQS6 0082 0056 DM2 1 DM6 t DM CS 505 905 DM CS DOS DOS DM CS DOS Das DM CS Das Das DQ16 N 0 1 0 0 DQ48 00 DQ17 N 1 VO 1 DQ49 VO1 VO 1 pais 02 2 0050 o2 2 0019 N Vos D2 1 0 3 D10 DQ51 D6 014 DQ20 N 104 VO 4 DQ52 N 704 VO 4 0021 A 705 5 0053 N 705 5 DQ22 N 06 VO 6 0054 06 DQ23 07 x VO7 za 2055 o7 VO7 0053 6957 m 0053 0057 DM3 t DM7 DM CS Das 09 DM CS DQS DQS DM cS DOS 09 DM CS DQS DOS DQ24 oo voo 0056 N oo DQ25 701 VO 1 0057 701 VO 1 DQ26 02 2 pass 02 2 DQ27 N 1 03 D3 D11 DQ59 JA 103 D7 015 DQ28 N 104 VO 4 704 VO 4 DQ29 5 5 0061 5 5 DQ30 N 1 0 6 5062 N voe 6 07 za Fx VO
3. 25 ck ____ Write leveling setup time from rising CK D tWLS 165 crossing to rising DQS DQS crossing Write leveling hold time from rising 005 DQS tWLH 165 crossing to rising CK crossing Write leveling output delay WLO ___ _____ _ 75 d Write leveling output error 1 0 20 05 2011 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F2G64CB88G7N M2F4G64CB8HG5N 2GB 256M x 64 4GB 512M x 64 PC3 1 0600 PC3 12800 Unbuffered DDR3 SDRAM DIMM Package Dimensions 2GB 1 Rank 256Mx8 DDR3 SDRAMs FRONT 133 35 0 15 elixir SIDE 2 57 Max 30 00 0 5 0 15 i Detail B lt Detail A HUY etai 5 175 47 00 71 00 BACK Detail A Detail B 0 80 0 05 Pul 00110000 1 00 Pitch Units Millimeters Note Device position and scale are only for reference REV 1 0 21 05 2011 1 27 0 07 0 10 TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F2G64CB88G7N M2F4G64CB8HG5N 2GB 256M x 64 4GB 512M x 64 m m PC3 10600 PC3 12800 e IXI r Unbuffered DDR3 SDRAM DIMM Package Dimensions 4GB
4. so ps DOhghimpedane metomCK CK 20 S tDS base Data setup time to DQS DQS referenced to Vih ac Vil ac levels AC175 tDS base Data setup time to DQS DQS referenced to Vih ac Vil ac levels 150 30 tDH base Data hold time from 005 DQS referenced to Vih dc Vil dc levels DC100 DQandDMipupusewidhforeachinput woo vs COURSE PIRE E DOSDOSHdifrenial READ Preamble oo ____ DOS DASE differential READ Postamble eest ____ DOS DASE differential output hightime ___ DOS DOSRdfeemiaowpulow m poss ___ 05 DOSE differential WRITE Preamble o ____ O DOS DOSE differential WRITE Postamble __ 03 ___ Ee ciu DQS and DQS low impedance time tLZ DQS 500 250 K avg Referenced from RL 1 DQS and DQS high impedance time tHZ DQS 250 K avg Referenced from RL BL 2 s oe s _ Saas ojo D m lt lt eu a A DLL locking time A lt e 6 6 p lt lt Internal READ Command to PRECHARGE Command delay tRTPmin max 4nCK 7 5ns REV 1 0 15 05 2011 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice
5. 2 Ranks 256Mx8 DDR3 SDRAMs FRONT 133 35 0 15 gt SIDE Detail A pg ale 5 175 47 00 zn 1 27 40 07 0 10 Detail Detail 250 ET 0 80 0 05 D000 0000006 1 00 Pitch 1 50 0 10 Units Millimeters Note Device position and scale are only for reference REV 1 0 22 05 2011 NANYA TECHNOLOGY CORPORATION reserves the right to change products and specifications without notice M2F2G64CB88G7N M2F4G64CB8HG5N 2GB 256M x 64 4GB 512M x 64 PC3 10600 PC3 12800 Unbuffered DDR3 SDRAM DIMM Revision Log Rev Date Modification 0 1 04 2011 Preliminary Release 1 0 05 2011 Official Release REV 1 0 23 05 2011 elixir NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice
6. M2F2G64CB88G7N M2F4G64CB8HG5N 2GB 256M x 64 4GB 512M x 64 PC3 10600 PC3 12800 e r Unbuffered DDR3 SDRAM DIMM Environmental Requirements TOPR Module Operating Temperature Range ambient 0 to 55 3 Hopr Operating Humidity relative 10 to 90 1 TsrG Storage Temperature Plastic 55 to 100 1 Storage Humidity without condensation 51095 1 Pressure operating amp storage 105 to 69 K Pascal 1 2 Note 1 Stresses greater than those listed may cause permanent damage to the device This is a stress rating only and device functional operation at or above the conditions indicated is not implied Exposure to absolute maximum rating conditions for extended periods may affect reliability 2 Up to 9850 ft 3 The component maximum case temperature shall not exceed the value specified in the component spec Absolute Maximum DC Ratings Voltage on VDD pins relative to Vss 0 4 V 1 975 V V VDDQ Voltage on VDDQ pins relative to Vss 0 4 V 1 975 V V 1 3 Vin Vout Voltage on I O pins relative to Vss 0 4 V 1 975 V V 1 TsrG Storage Temperature 55 to 100 1 2 Note 1 Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied
7. 5ns tCKEmax NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F2G64CB88G7N M2F4G64CB8HG5N 2GB 256M x 64 4GB 512M x 64 PC3 10600 PC3 12800 Unbuffered DDR3 SDRAM DIMM 7 tWRPDEN BL8MRS 4 IWRPDENmax EI CC amon _ tWRAPDEN BL8MRS 4 tWRAPDENmax IWRPDENnin WL 2 WR tOK avg WRPDENmax See tWRAPDEN BCAMRS tWRAPDENmax 2e _ Timing of REF command to Power Down entry tREFPDEN tREFPDENmax tMRSPDENmin tMOD min Timing of MRS command to Power Down entry tMRSPDEN tMRSPDENmax ODT Timings ae NEZ MEN high time without write command ODTH4min 4 ODTH4 with write command and 4 ODTHA4max ODTH8min 6 ODT high time with Write command and BL8 ODTH8 ODTH8max Asynchronous RTT turn on delay tAONPD 2 8 5 Power Down with DLL frozen Asynchronous RTT turn off delay tAOFPD 2 8 5 Power Down with DLL frozen RTT turn on presses S RTT Nom and RTT WR turn off time tAOF 0 3 0 7 tCK avg from ODTLoff reference RTT dynamic change skew tADC ao ___ Write Leveling Timings INNEN ey First DQS DQS rising edge after tWLMRD write leveling mode is programmed DOS DQSH delay after write leveling mode is programmed
8. Vil dc levels Command and Address setup time to CK CK tlS base AC150 1254150 referenced to Vih ac Vil ac levels Control and Address Input pulse width for each input EE EE eee Calibration Timing eee Power up and RESET calibration time Normal operation Full calibration time Ope ck ST Normal operation Short calibration time 12008 ___ _ __ _ ____ Reset Timing __ j tXPRmin max 5nCK tRFC min 10ns Exit Reset from CKE HIGH to a valid command tXPR Self Refresh Timings tXSmin max 5nCK tRFC min 10ns Exit Self Refresh to commands not requiring a locked DLL XS tXSmax tXSDLLmin tDLLK min Exit Self Refresh to commands requiring a locked DLL tXSDLL tXSDLLmax tCKESRmin tCKE min 1 nCK Minimum CKE low width for Self Refresh entry to exit timing tCKESR tCKESRmax Valid Clock Requirement after Self Refresh Entry SRE tCKSREmin max 5 10 ns or Power Down Entry PDE tCKSREmax Valid Clock Requirement before Self Refresh Exit SRX ICKSRX tCKSRXmin max 5 nCK 10 ns or Power Down Exit PDX or Reset Exit tCKSRXmax Power Down Timings Exit Power Down with DLL on to any valid command tXPmin max 3nCK 7 5ns Exit Precharge Power Down with DLL frozen to commands tXPmax not requiring a
9. jp Clock Period Jitter during DLL locking period _ S to Cycle Period sitter __ s Cycle to Cycle Period Jitter during DLL locking period ps __ Ps Cumulative error across 2 cycles JRRGpen Cumulative error across 3eycles __ o e s S Cumulative error across 4 cycles 86 ps S Cumulative error across cycles ERAS Cumulative error across 6 cycles tERRGpe ts ___ ts S Cumulative error across 7 JRRGpe ____ tsps S Cumulative error across 8cycles to tsps S Cumulative erroracross9 cycles erropen tps S Cumwa veemoracrossi0cydes Cumulative error across 11 eRe Cumulative error across i2cydes ERR pe Cumulative error across n 13 14 49 50 cycles tERR nper tERR nperjmini 1 tERR nper max 1 0 68In n tJIT per max P DOS 005 DQ skew per group per access DQoutputholdtimefrmbas pas tH DQlowimpedance ime _ 45 25 s DQ highimpedance time oo 225 tDS base Data setup time to DQS DQS referenced to Vih ac Vil ac levels AC175 tDS base Data setup time to DQS DQS referenced to Vih ac Vil ac levels 150 10 tDH base Data hold time from 005 DQS referenc
10. 12800 Unbuffered DDR3 SDRAM DIMM DDR3 SDRAM Pin Assignment Pin Front _ Back Pin Front Pin Pin Front Pin Back Pin Front Pin Back 1 121 Vss 31 0025 151 Vss 61 2 181 Ai 0041 21 DMS 2 122 004 32 152 ui c 62 182 Vp 92 212 00514 TDOS14 wer NC DOST a NC 000 123 005 0053 153 63 183 V 93 DOSS 213 DOGS 00512 150514 4 001 124 Vss 34 DQS3 154 Vss 64 CKiNC 184 CKO 94 0055 214 Vss 5 Vs 125 35 155 0030 66 185 95 215 0046 6 DOST 126 ph 36 0026 156 0031 66 Vo 186 96 0042 216 0047 7 0050 127 Vss 37 0027 157 Vss 67 Vaerca 187 ey 97 0043 217 Vss 8 128 006 38 158 CBANC 68 tae 188 AO 98 Va 218 0052 9 002 129 007 39 CBO NC 159 5 69 189 Vp 99 0048 219 0053 10 003 130 Vss 40 CB1 NC 160 Vss 70 A10 AP 190 100 0049 220 Vss DM6 11 131 0012 44 Vas 161 DM amp DQS17 74 191 101 Vas 221 00515 TDQS17 NC TDOSIS NC DOS17 NC 12 008 132 42 pase 162 0051 72 192 RAS 102 0056 222 00515 TDOST 15 13 133 Vss 43 0058 163 Vss 73 WE 193 S0 103 0056 223 Vss 14 134 44 Vsg 164 CB6NC 74 CAS 194 Vw 104 Va 224 0054 15 DOSI 135 pd 45 2 165 CB7 NC 75 V 195 105 0050 225 005
11. 4 ODTHA4max ODTH8min 6 ODT high time with Write command and BL8 ODTH8 ODTH8max Asynchronous RTT turn on delay tAONPD 2 8 5 Power Down with DLL frozen Asynchronous RTT turn off delay tAOFPD 2 8 5 Power Down with DLL frozen RTT turn on s RTT Nom and RTT WR turn off time tAOF 0 3 0 7 tCK avg from ODTLoff reference RTT dynamic change skew tADC o ___ Write Leveling Timings Ses Se INNO First DQS DQS rising edge after tWLMRD write leveling mode is programmed 005 005 delay after write leveling mode is programmed WLDOSEN 25 ___ Write leveling setup time from rising CK tWLS 245 crossing to rising 005 DQS crossing Write leveling hold time from rising 005 DQS tWLH 245 crossing to rising CK CK crossing Write leveling output delay WLO ___ fs Write leveling output error Do es 1 0 14 05 2011 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F2G64CB88G7N M2F4G64CB8HG5N 2GB 256M x 64 AGB 512M x 64 PC3 10600 PC3 12800 elixi r Unbuffered DDR3 SDRAM DIMM AC Timing Specifications for DDR3 SDRAM Devices Used on Module 1333MHz 1 Parameter Symbol Units c Minimum Clock Cycle Time DLL Average Clock Period o Reter to Standard Speed Bins ds Average
12. Exposure to absolute maximum rating conditions for extended periods may affect reliability 2 Storage Temperature is the case surface temperature on the center top side of the DRAM For the measurement conditions please refer to JESD51 2 standard 3 VDD and VDDQ must be within 300 mV of each other at all times and VREF must be not greater Operating temperature Conditions Normal Operating Temperature Range 0 to 85 1 Extended Temperature Range 85 to 95 3 Note 1 Operating Temperature TOPER is the case surface temperature on the center top side of the DRAM For measurement conditions please refer to the document JESD51 2 2 The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported During operation the DRAM case temperature must be maintained between 0 to 85 C under all operating conditions 3 Some applications require operation of the DRAM in the Extended Temperature Range between 85 and 95 case temperature Full specifications are supported in this range but the following additional conditions apply a Refresh commands must be doubled in frequency therefore reducing the Refresh interval tREFI to 3 9 us It is also possible to specify a component with 1X refresh to 7 8 5 in the Extended Temperature Range Please refer to supplier data sheet and or the DIMM SPD for option availability b If Self Refresh operation is required in the Extended Temp
13. effect The data strobes associated with one data byte sourced with data transfers In Write mode the data strobe is sourced by the controller and is centered in the data window In Read mode the DQSO 2058 Cross data strobe is sourced by the DDR3 SDRAM and is sent at leading edge of the data window 0050 0058 point DQS signals are complements and timing is relative to the cross point of respective 005 and DAQS If the module is to be operated in single ended strobe mode all DQS signals must be tied on the system board to Vss and DDR3 SDRAM mode registers programmed appropriately BA2 Input Selects which DDR3 SDRAM internal bank of four or eight is activated During a Bank Activate command cycle defines the row address when sampled at the cross point of the rising edge of CK and falling edge of CK During a Read or Write command cycle defines A9 the column address when sampled at the cross point of the rising edge of CK and falling edge of A10 AP CK In addition to the column address AP is used to invoke autoprecharge operation at the end of A11 Input the burst read or write cycle If AP is high autoprecharge is selected and BAO BAn defines the A12 BC bank to be precharged If AP is low autoprecharge is disabled During a Precharge command A13 A15 cycle AP is used in conjunction with BAO BAn to control which bank s to precharge If AP is high all banks will be precharged regardless of the sta
14. high pulsewidth Averagelow pulsewidth _ on ____ Absolute Clock Period tCK abs Max tCK avg max tJIT per max Absolute clock HIGH pulsewidth 043 Absolute clock LOW pulsewidth baes os Clock Period tter stipe ___ Clock Period Jitter during locking period eriw ps S Cycle to Period siter two tops S Cycle to Cycle Period Jitter during DLL locking period NT 0 Duty Cumulative erroracross2cycles tps S Cumulative error across 3oycles _______ JERRGpe aw tps S Cumulative error across 4oycles Cumulative error across 5 cycles Cumulative error across 6 cycles tERR 6per gt Cumulative error across 7 _ _ _______ ps S Cumulative erroracross8cycles Cumulative error across 9 cycles _____ 20 CumuaiveemoracossiOcydes __ 25 25 S Cumulative error across 11 SS 20 tps S Cumulative error across 12cycles ERR zpe Cumulative error across n 13 14 49 50 cycles tERR nper tERR nperjmini tERR nper max 1 0 68In n tJIT per max Ol DAS DASH to DA skew pergroup peraccess ts 15 je S DQouputhol dmetomDQS DOSR _ stag DOlwimpedanetmeomCK CKK
15. os Absolute clock LOW pulsewidth Clock Period sitter __ S Clock Period Jitter during DLL locking period J je S Cycle to Cycle Period siter te S Cycle to Cycle Period Jitter during DLL locking period 10 Duty Cyde ter tsi Ps Cumulative erroracross2cycles Je S Cumulative erroracross3cycles Cumulative error across 4oyoles Cumulative error across Scycles ___ Cumulative erroracross6cycles 20 tps S Cumulative error aoross 7 oyoles __ os S Cumulative eror across 8oyoles HERB ar Cumuaiveemoracoss9cydes 224 ___ 24 S Cumulative error across 10 cycles Cumulative error across 11 cycles Cumulative error across 12 cycles tERR 12per Cumulative error across 13 14 49 50 cycles tERR nper pid pa ua dip o Med permin e tERR nper max 1 0 68In n tJIT per max DOS DQSPioDQskew pergw peracess feasa _ _ DQowpuhod metomDOS ___ DOlowimpdanetmeomCK CKF won S DQhghimedane metomCK CKK zoo ___ ___ S tDS Tem Data setup time to DQS DQS referenced to Vih ac Vil ac le
16. 4CB88G7N M2F4G64CB8HG5N 2GB 256M x 64 4GB 512M x 64 PC3 10600 PC3 12800 Unbuffered DDR3 SDRAM DIMM Functional Block Diagram 4GB 2 Ranks 256 8 DDR3 SDRAMs 51 50 5950 5954 paso t 2984 DMO 1 DM4 1 DM CS 095 7005 DM CS DQS 7505 DM CS DQS 705 DM cS DQS DQS Dao N oo 1 0 0 00 1 0 0 001 MH 01 1 DQ33 N 101 1 paz 2 0034 02 2 M 103 DO D8 DQ35 N 103 D4 yos D12 DQ4 M 4 1 0 4 DQ36 JA 1 0 4 4 DQ5 M 5 5 0037 5 1 0 6 6 0038 6 1 0 6 107 VO7 5939 N o7 yo 7 za 0051 pass 51 t pass DM1 t DM5 DM CS 0505 095 DM cS Das 005 DM CS DQS DM CS 005 DQS
17. 5 16 0051 136 Vss 46 CB3 NC 166 Vss 76 196 A13 106 0051 226 Vss 17 Vs 137 0014 47 167 NC TEST 77 ODTINC 197 V 107 227 18 0010 188 0015 48 168 RESET 78 Vp 198 S3 NC 108 0056 228 0061 19 0011 139 Vss 49 169 CKEUNC 79 S2NC 199 Vss 109 0057 229 Vss DM7 20 Vss 140 0020 50 170 Voo 80 200 DQ36 110 Ves 230 DQS16 TDQS16 NC 21 0016 141 51 171 15 81 0032 201 00937 111 0057 231 DOSTS 150576 22 0017 142 Vss 52 2 172 A14 82 DQ33 202 Vs 112 DQS7 232 Vss DM4 23 Va 143 53 173 Mis 83 203 00513 113 233 0062 NC TDQS13 NE NC DOSTI I NC 24 DOSZ 144 54 V 174 84 DOM 204 00513 114 0058 234 0063 TDOSfi 00513 150513 25 0052 145 Vss 55 11 175 9 85 DQS4 205 Vs 115 0059 235 Vss 26 Vss 146 0022 56 A7 176 Vov 86 Vss 206 0038 116 Vss 236 Vooseo 27 0018 147 57 177 8 87 207 0039 117 SAO 237 SA 28 0019 148 Vss 58 178 A6 88 0035 208 Vs 118 SCL 238 SDA 29 Vss 149 0028 59 A4 179 Von 89 209 0044 119 SA2 239 Vss 0024 150 Daag 60 V 180 90 0040 210 0045 120 Vm 240 Vn Note CK1 CK1 CKE1 51 ODT1 for 428 modules only REV 1 0 05 2011 NANYA TECHNOLOGY CORPORATION reserves the right to change products and specifications without notice M2F2G64CB88G7N M2F4G64CB8HG5N 2GB 256M x 64 4GB 512M x 64 10600 12800 IXI r Unbuf
18. 60 N 1 04 0029 N 1 05 2061 105 0030 1 06 0062 N 06 0031 N 107 20 DQ63 N 07 za n SCL SCL Vobsep SPD sao 3e Ao SPD E 00 07 1 gt 1 SDA Vnerpa 00 07 A2 Vss 00 07 ERES Veerca 9 gt 00 07 idi 2 BAO BA2 SDRAMs 00 07 AO A18 13 SDRAMs 00 07 RAS p RAS SDRAMs 00 07 DDR3 CAS ____________ CAS SDRAMs 00 07 SDRAM gt SDRAMs 00 07 A 13 0 WE SDRAMs 00 07 em 50 W Vr SDRAMs 00 07 p CK SDRAMs 00 07 DDRS CKO gt CK SDRAMs 00 07 SDRAM RESET RESET SDRAMs 00 07 oe Notes 1 DQ to I O wiring is shown as recommended but may be changed 2 DQ DQS DQS ODT DM CKBE S relationships must be maintained as shown 3 For each DRAM a unique ZQ resistor is connected to ground The ZQ resistor is 2400 X196 4 One SPD exists per module REV 1 0 5 05 2011 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F2G6
19. 7 za Dass 707 VO7 DDR3 VopsPp SPD SDRAM Voo Vopa gt 00 015 0 A 13 0 00 015 RAS CAS WE Vss e e 00 015 ODT 1 0 BA 2 0 81150 Veera 00 015 2 gt 2 SDRAMs 00 015 13 SDRAMs 00 015 DDR3 RAS gt RAS SDRAMs 00 015 SDRAM TAS SDRAMs 00 015 gt WE SDRAMs 00 015 Voo SDRAMs 00 07 CKE1 SDRAMs 08 015 ODT SDRAMs 00 07 SDRAMs 08 015 SCL scL CK SDRAMs 00 07 sao 0 SPR gt 50 SDRAMs 00 07 i we cki gt CK SDRAMs 08 015 2 CKI SDRAMs 08 015 REV 1 0 05 2011 p gt Notes RESET SDRAMs D8 D15 1 DQ to I O wiring is shown as recommended but may be changed wr resistor is 2400 1 4 One SPD exists per module DQ DQS DQS ODT DM CKE S relationships must be maintained as shown For each DRAM a unique ZQ resistor is connected to ground The ZQ NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice
20. Exit 123 123 mA IDD2P1 Precharge Power Down Current Fast Exit 299 317 mA IDD2Q Precharge Quiet Standby Current 422 458 mA IDD2N Precharge Standby Current 493 528 mA IDD3P Active Power Down Current 405 422 mA IDD3N Active Standby Current 581 616 mA IDD4R Operating Burst Read Current 1162 1302 MA IDD4W Operating Burst Write Current 1091 1214 mA 19058 Burst Refresh Current 1558 1602 mA IDD6 Self Refresh Current Normal Temperature Range 123 123 1007 Operating Bank Interleave Read Current 1866 1918 mA REV 1 0 9 05 2011 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F2G64CB88G7N M2F4G64CB8HG5N 2GB 256M x 64 4GB 512M x 64 PC3 10600 PC3 12800 e r Unbuffered DDR3 SDRAM DIMM Standard Speed Bins R3 1066MHz DD Parameter symbol Mir Ma Internal read command to first data 13125 _ 20000 _ ms _____ ACT to internal read or write delaytime __ tRCD 13125 bo o ms PRE command period 1 183125 ___ ms _____ ACT to ACT or REF command period 50 625 b 1 ms 0 ACTtoPREcommandperod tRAS 37500 _ REF _ ms _____ EM TEM EE C es CKAVG Reserved ms CWl 5 QtCKAVGQ 1 2 330 mns _____ E CWL CWL 6 CKAVGQ 875 lt 25 ms CWL 6 JCKAVG ___ 1875 25 0 mns Supp
21. GB 256M x 64 4GB 512M x 64 PC3 10600 PC3 12800 Unbuffered DDR3 SDRAM DIMM elixir Ordering Information DDR3 1333 PC3 10600 667MHz 1 5ns CL 9 0083 1600 12800 800MHz 1 25ns 9 CL 11 DDR3 1333 PC3 10600 667MHz 1 5ns CL 9 0083 1600 PC3 12800 800MHz 1 25ns 9 CL 11 Part Number M2F2G64CB88G7N CG M2F2G64CB88G7N DI M2F4G64CB8HG5N CG M2F4G64CB8HG5N DI 256Mx64 1 5V Gold 512Mx64 Pin Description Clock Inputs positive line CK1 0090 0063 Data input output CKO CK1 Clock Inputs negative line DQS0 DQS8 Data strobes CKEO CKE1 Clock Enable DQS0 DQS8 Data strobes complement RAS Row Address Strobe Data Masks CAS Column Address Strobe EVENT Temperature event pin WE Write Enable RESET Reset pin S0 S1 Chip Selects Vnerba Input Output Reference 9 A11 A13 A15 Address Inputs VopsPp SPD and Temp sensor power A10 AP Address Input Auto Precharge SAO SA1 Serial Presence Detect Address Inputs A12 BC Address Input Burst Chop Vtt Termination voltage BAO BA2 SDRAM Bank Address Inputs Vss Ground ODTO ODT1 Active termination control lines Voo Core and I O power SCL Serial Presence Detect Clock Input NC No Connect SDA Serial Presence Detect Data input output REV 1 0 2 05 2011 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F2G64CB88G7N M2F4G64CB8HG5N 2GB 256M x 64 4GB 512M x 64 PC3 10600 PC3
22. K AVG Reserved Reseved _ mns o WL 8 CK AVG 125 ____ lt 15 upported CL Settings upported CWL Settings gt Internal read command to first data ACT to internal read or write delay time PRE command period ACT to ACT or REF command period ACT to PRE command period WL 5 L 5 WL 6 D O m gt n CK AVG CK AVG CK AV CK AVG CK AVG CK AVG CK AVG CK AVG CK AVG CK AVG CK AVG CK AVG CK AVG CK AVG CK AVG CK AVG CK AVG CK AVG WL 5 WL 6 WL 5 WL 6 WL 7 WL 5 WL 6 WL 7 WL 5 WL 6 WL 7 WL 5 WL 6 WL 7 WL 5 WL 6 2 2 ee 1 M REV 1 0 11 05 2011 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F2G64CB88G7N M2F4G64CB8HG5N 2GB 256M x 64 4GB 512M x 64 PC3 10600 PC3 12800 el IXIY Unbuffered DDR3 SDRAM DIMM AC Timing Specifications for DDR3 SDRAM Devices Used on Module 1066MHz 1 Parameter Symbol Units S Minimum Clock Cycle Time DLL off mode Jckouor s ___ ns Average Clock Period Refer to Standard Speed Bin ps o Average high pulsewidth hoew 04 Average low pulsewidth heg ___ oss Max tCK avg max tJIT per max Absolute cock HIGH pulsewidth hones
23. M2F2G64CB88G7N M2F4G64CB8HG5N 2GB 256M x 64 4GB 512M x 64 PC3 10600 PC3 12800 m m elixir Unbuffered DDR3 SDRAM DIMM Delay from start of internal write WTR tWTRmin max 4nCK 7 5ns transaction to internal read command tWTRmax WRITE recovery time Pt es Mode Register Set command cycle time meo oo a tMODmin max 12nCK 15ns Mode Register Set command update delay ACT to internal read or write delaytime command period RP ACT or REF command period to CASH command delay te ok ____ Auto precharge write recovery precharge DALmm roundup tRP tCK avg eek Multi Purpose Register Recovery Time ftwPRR PRECHARGE command period feas Standard Speed Bins tRRDmin max 4nCK 6ns ACTIVE to ACTIVE command period for 1KB page size tRRDmax tRRDmin max 4nCK 7 5ns ACTIVE to ACTIVE command period for 2KB page size tRRDmax Four activate window for 1KB page size bw Four activate window for 2KB page size IFAW Dll a a es Command and Address setup time to CK CK tlS base _ e tlS base AC150 65 125 referenced to Vih ac Vil ac levels Control and Address Input pulse width for each put __ Power up and RESET calbrationtime ____ Normal operation Full calibration time Normal operation Short calibration t
24. M2F2G64CB88G7N M2F4G64CB8HG5N 2GB 256M x 64 4GB 512M x 64 PC3 10600 PC3 12800 Unbuffered DDR3 SDRAM DIMM Based on DDR3 1333 1600 256Mx8 SDRAM G Die Features Performance PC3 10600 PC3 12800 CG DI Unit DIMM CAS Latency 9 11 fck Clock Freqency 667 800 MHz tck Clock Cycle 1 5 1 25 ns fDQ DQ Burst Fregency 1333 1600 Mbps 240 Pin Dual In Line Memory Module UDIMM 256Mx64 2GB 512Mx64 4GB DDR3 Unbuffered DIMM based on 256Mx8 DDR3 SDRAM G Die devices Intended for 667MHz 800MHz applications Inputs and outputs are SSTL 15 compatible Voo 1 5V 0 075V SDRAMs have 8 internal banks for concurrent operation Differential clock inputs Data is read or written on both clock edges DRAM DLL aligns and 005 transitions with clock transitions Address and control signals are fully synchronous to positive clock edge Nominal and Dynamic On Die Termination support Description elixir Programmable Operation DIMM CAS Latency 5 6 7 8 9 10 11 Burst Type Sequential or Interleave Burst Length BC4 BL8 Operation Burst Read and Write Two different termination values Rtt Nom amp Rtt WR 15 10 1 row column rank Addressing for 2GB 15 10 2 row column rank Addressing for 4GB Extended operating temperature rage Auto Self Refresh option Serial Presence Detect Gold contacts SDRAMs are in 78 ball BGA Package RoHS compliance and Halo
25. a valid command tXPR tXPRmax _______ tXSmin max 5nCK tRFC min 10ns Exit Self Refresh to commands not requiring a locked DLL tXS tXSmax tXSDLLmin tDLLK min Exit Self Refresh to commands requiring a locked DLL tXSDLL tXSDLLmax tCKESRmin tCKE min 1 nCK Minimum CKE low width for Self Refresh entry to exit timing tCKESR Valid Clock Requirement after Self Refresh Entry SRE ICKSRE tCKSREmin max 5 nCK 10 ns tCKSREmax tCKESRmax or Power Down Entry PDE A Valid Clock Requirement before Self Refresh Exit SRX tCKSRXmin max 5 nCK 10 ns or Power Down Exit PDX or Reset Exit tCKSRXmax tXPDLLmin max 10nCK 2415 tXPDLLmax Command and Address setup time to CK Exit Power Down with DLL on to any valid command Exit Precharge Power Down with DLL frozen to commands not requiring a locked DLL Exit Precharge Power Down with DLL frozen to commands requiring a locked DLL CKE minimum pulse width tCPDEDmin 1 Command pass disable delay ICPDEDmin In tPDmin tCKE min tPDmax 9 tREFI tACTPDENmin 1 tACTPDEN tACTPDENmax Power Down Entry to Exit Timing Timing of ACT command to Power Down entry Timing of PRE or PREA command to Power Down entry Timing of RD RDA command to Power Down entry REV 1 0 05 2011 tPRPDENmin 1 tPRPDEN tPRPDENmax tRDPDENmin RL 4 1 tRDPDEN tRDPDENmax 19 tCKEmin max 3nCK
26. ed to Vih dc Vil dc levels C100 DQ and DM Input pulse width tor each input E E E DOS DOS differential READ Preamble Rere oo ____ ____ DOS DASE differential READ Postamble os DOS DASE differential outputhightime OSH 04 ___ DOS DOSRdfeemiaowpulow m poss ___ 05 DOSE differential WRITE Preamble o ____ O DOS DOSE differential WRITE Postamble __ 03 005 DQS low impedance time tLZ DQS 450 225 K avg Referenced from RL 1 DQS and 205 high impedance time bg tHZ DQS 225 K avg Referenced from RL BL 2 008 055 055 Dass 027 05 DS poll Ss ojo D m lt lt eu a A DLL locking time A lt e 6 6 p lt lt Internal READ Command to PRECHARGE Command delay tRTPmin max 4nCK 7 5ns REV 1 0 18 05 2011 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F2G64CB88G7N M2F4G64CB8HG5N 2GB 256M x 64 4GB 512M x 64 PC3 10600 PC3 12800 m m elixir Unbuffered DDR3 SDRAM DIMM Delay from start of internal write WTR tWTRmin max 4nCK 7 5ns transaction to internal read command tWTRmax WRITE recovery ti
27. ence RTT dynamic change skew tADC Write Leveling Timings INNEN First DQS DQS rising edge after tWLMRD nCK write leveling mode is programmed 005 005 delay after write leveling mode is programmed WLDOSEN 25 ck ____ Write leveling setup time from rising CK tWLS 195 crossing to rising DQS DQS crossing Write leveling hold time from rising 005 DQS tWLH 195 crossing to rising CK crossing Write leveling output delay WLO po fs Write leveling output error 08 T e i REV 1 0 17 05 2011 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F2G64CB88G7N M2F4G64CB8HG5N 2GB 256M x 64 AGB 512M x 64 PC3 10600 PC3 12800 elixi r Unbuffered DDR3 SDRAM DIMM AC Timing Specifications for DDR3 SDRAM Devices Used on Module 1600MHz 1 pe Parameter Symbol Units Minimum Clock Cycle Time DLL off mode Jckepuor Average Clock Period Refer to Standard Speed Bins des Average high pulse width ooo o JCHeg Wweagelopusewidh law Absolute Clock Period tCK abs Max tCK avg max tJIT per max Absolute clockHIGH pulsewidth tabs 049 Absolute clock LOW pulse width ___ 049 _
28. erature Range then it is mandatory to either use the Manual Self Refresh mode with Extended Temperature Range capability MR2 0b and MR2 A7 1b or enable the optional Auto Self Refresh mode MR2 1b and MR2 A7 06 Please refer to the supplier data sheet and or the DIMM SPD for Auto Self Refresh option availability Extended Temperature Range support and tREFI requirements in the Extended Temperature Range REV 1 0 7 05 2011 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F2G64CB88G7N M2F4G64CB8HG5N 2GB 256M x 64 4GB 512M x 64 10600 12800 r Unbuffered DDR3 SDRAM DIMM DC Electrical Characteristics and Operating Conditions VDD Supply Voltage 1 425 1 575 VDDQ Output Supply Voltage 1 425 1 5 1 575 V T Note 1 Under all conditions VDDQ must be less than or equal to VDD 2 VDDQ tracks with VDD AC parameters are measured with VDD and VDDQ tied together Single Ended AC and DC Input Levels for Command and Address VIH CA DC DC Input Logic High Vref 0 100 Vref 0 100 Vref 0 100 V VIL CA DC DC Input Logic Low VSS Vref 0 100 VSS Vref 0 100 VSS Vref 0 100 V VIH CA AC AC Input Logic High Vref 0 175 Note 2 Vref 0 175 Note 2 Vref 0 175 Note 2 V 1 2 VIL CA AC Input Logic Low Note 2 Vref 0 175 Note 2 Vref 0 175 Note 2 Vref 0 175 V 1 2 VIH CA AC150 AC Input Logic High 0 15 No
29. fered DDR3 SDRAM DIMM Input Output Functional Description Symbol _ Type Polarity Function CKO CK1 red The system clock inputs All address and command lines are sampled on the cross point of the CKO Input oint rising edge of CK and falling edge of CK A Delay Locked Loop DLL circuit is driven from the clock inputs and output timing for read operations is synchronized to the input clock CKEO CKE1 Active Activates the DDR3 SDRAM CK signal when high and deactivates the CK signal when low High deactivating the clocks low initiates the Power Down mode or the Self Refresh mode Active Enables the associated DDR3 SDRAM command decoder when low and disables the command 0 S1 Input Low decoder when high When the command decoder is disabled new commands are ignored but previous operations continue Rank 0 is selected by 50 Rank 1 is selected by 51 RAS CAS WE Input Active When sampled at the positive rising edge of CK and falling edge of CK signals RAS CAS WE Low define the operation to be executed by the SDRAM Active Asserts on die termination for DQ DM DQS and DQS signals if enabled via the DDR3 SDRAM Input High mode register Active The data write masks associated with one data byte In Write mode DM operates as a byte mask DMO DM8 Input High by allowing input data to be written if it is low but blocks the write operation if it is high In Read mode DM lines have no
30. gen free product M2F2G64CB88G7N M2F4G64CB8HGSN are 240 Pin Double Data Rate 3 DDR3 Synchronous DRAM Unbuffered Dual In Line Memory Module UDIMM organized as one rank of 256Mx64 2GB and two ranks of 512Mx64 4GB high speed memory array Modules use eight 256Mx8 2GB 78 ball BGA packaged devices and sixteen 256Mx8 4GB 78 ball BGA packaged devices These DIMMs are manufactured using raw cards developed for broad industry use as reference designs The use of these common design files minimizes electrical variation between suppliers All Elixir DDR3 SDRAM DIMMs provide a high performance flexible 8 byte interface in a 5 25 long space saving footprint The DIMM is intended for use in applications operating of 667MHz 800MHz clock speeds and achieves high speed data transfer rates of 1333Mbps 12800Mbps Prior to any access operation the device CAS latency and burst length operation type must be programmed into the DIMM by address inputs A0 A13 2GB A0 A14 4GB and inputs BAO BA2 using the mode register set cycle The DIMM uses serial presence detect implemented via a serial EEPROM using a standard protocol The first 128 bytes of SPD data are programmed and locked during module assembly The remaining 128 bytes are available for use by the customer REV 1 0 05 2011 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F2G64CB88G7N M2F4G64CB8HG5N 2
31. ime _ i i dicm prn ae tXPRmin max 5nCK tRFC min 10ns Exit Reset from CKE HIGH to a valid command tXPR tXPRmax ________ _______ tXSmin max 5nCK tRFC min 10ns Exit Self Refresh to commands not requiring a locked DLL tXS tXSmax E tXSDLLmin tDLLK min Exit Self Refresh to commands requiring a locked DLL tXSDLL tXSDLLmax mid tCKESRmin tCKE min 1 nCK Minimum CKE low width for Self Refresh entry to exit timing tCKESR Valid Clock Requirement after Self Refresh Entry SRE ICKSRE tCKSREmin max 5 nCK 10 ns tCKSREmax tCKESRmax or Power Down Entry PDE A Valid Clock Requirement before Self Refresh Exit SRX tCKSRXmin max 5 nCK 10 ns or Power Down Exit PDX or Reset Exit tCKSRXmax tXPDLLmin max 10nCK 2415 tXPDLLmax referenced to Vih ac Vil ac levels Command and Address hold time from CK referenced to Vih dc Vil dc levels Command and Address setup time to CK Exit Power Down with DLL on to any valid command Exit Precharge Power Down with DLL frozen to commands not requiring a locked DLL Exit Precharge Power Down with DLL frozen to commands requiring a locked DLL CKE minimum pulse width tCPDEDmin 1 Command pass disable delay ICPDEDmin In tPDmin tCKE min tPDmax 9 tREFI tACTPDENmin 1 tACTPDEN tACTPDENmax Power Down Entry to Exit Timing Timing of ACT c
32. locked DLL Exit Precharge Power Down with DLL frozen to commands tXPDLLmin max 10nCK 24ns requiring a locked DLL tXPDLLmax tCKEmin max 3nCK 5 625ns tCKEmax tCPDEDmin 1 Command pass disable delay tCPDED tCPDEDmin tPDmin tCKE min Power Down Entry to Exit Timing tPDmax 9 tREFI tACTPDENmin 1 Timing of ACT command to Power Down entry tACTPDEN tACTPDENmax tPRPDENmin 1 Timing of PRE or PREA command to Power Down entry tPRPDEN tPRPDENmax tRDPDENmin RL 4 1 Timing of RD RDA command to Power Down entry tRDPDEN tRDPDENmax 1 0 13 05 2011 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice CKE minimum pulse width M2F2G64CB88G7N M2F4G64CB8HG5N 2GB 256M x 64 4GB 512M x 64 PC3 10600 PC3 12800 Unbuffered DDR3 SDRAM DIMM 7 tWRPDEN BL8MRS 4 tWRPDENmax ETC COMME ____ tWRAPDEN BL8MRS 4 tWRAPDENmax WRPDENmin WL 2 WR tOK avg WRPDENmax See tWRAPDEN BCAMRS tWRAPDENmax 2e Timing of REF command to Power Down entry tREFPDEN tREFPDENmax tMRSPDENmin tMOD min Timing of MRS command to Power Down entry tMRSPDEN tMRSPDENmax ODT Timings ODT high time without write command or ODTH4min 4 ODTH4 with write command
33. me o o5 es _ Mode Register Set command cycle time meo oo a tMODmin max 12nCK 15ns Mode Register Set command update delay ACT internal read or write delaytime command period RP ACT or REF command period RP to CASH command delay eeo o a ok ____ Auto precharge write recovery precharge WRerowdupiRP Kavg eek Multi Purpose Register Recovery Time merr PRECHARGE command period eas Standard Speed Bins tRRDmin max 4nCK 6ns ACTIVE to ACTIVE command period for 1KB page size tRRDmax tRRDmin max 4nCK 7 5ns ACTIVE to ACTIVE command period for 2KB page size tRRDmax Four activate window for 1KB page size oo 39 S ps f Four activate window for 2KB page size IFAW ae 4 Command and Address setup time to CK CK tlS base referenced to Vih ac Vil ac levels Command and Address hold time from CK tlH base 120 tlS base AC150 170 referenced to Vih ac Vil ac levels referenced to Vih dc Vil dc levels Control and Address Input pulse width for each input uPW se ps S Calibration Timing Power up and RESET calibrationtime tint S cK ____ Normal operation Full calibrationtime Normal operation Short calbrationtime Reset Timing tXPRmin max 5nCK tRFC min 10ns Exit Reset from CKE HIGH to
34. ommand to Power Down entry Timing of PRE or PREA command to Power Down entry Timing of RD RDA command to Power Down entry REV 1 0 05 2011 tPRPDENmin 1 tPRPDEN tPRPDENmax tRDPDENmin RL 4 1 tRDPDEN tRDPDENmax 16 tCKEmin max 3nCK 5 625ns tCKEmax NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F2G64CB88G7N M2F4G64CB8HG5N 2GB 256M x 64 4GB 512M x 64 PC3 10600 PC3 12800 Unbuffered DDR3 SDRAM DIMM 7 tWRPDEN BL8MRS 4 IWRPDENmax ETC COMME ____ NC tWRAPDEN BL8MRS 4 tWRAPDENmax WL 2 WR tOK avg WRPDENmax See ER tWRAPDEN BCAMRS tWRAPDENmax RIO Em EI Timing of REF command to Power Down entry tREFPDEN tREFPDENmax tMRSPDENmin tMOD min Timing of MRS command to Power Down entry tMRSPDEN tMRSPDENmax ODT Timings s nr e coe pp ODT high time without write command or ODTH4min 4 ODTH4 with write command and 4 ODTH4max ODTH8min 6 ODT high time with Write command and BL8 ODTH8 ODTH8max Asynchronous RTT turn on delay tAONPD 2 8 5 Power Down with DLL frozen Asynchronous RTT turn off delay tAOFPD 2 8 5 Power Down with DLL frozen RTT turn on o o9 ____ ____ 20 s RTT Nom and RTT turn off time tAOF 0 3 0 7 tCK avg from ODTLoff refer
35. orted CL Settings DDR3 1333MHz 13 5 REN 13 125 49 125 to PRE command period RAS 36 000 9 tREFI 3 eserved eserved served served 500 300 eserved eserved eserved eserved 875 eserved Reserved 875 s Reserved eserved 500 eserved eserved 500 iL a CL 5 iL 2 2082822020528 o als 2 5 5 3 2 2 396 o S CWL 5 R ME e O T 2 Bs Ci iL 2 1 NIS CL 10 REV 1 0 10 05 2011 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F2G64CB88G7N M2F4G64CB8HG5N 2GB 256M x 64 4GB 512M x 64 PC3 10600 PC3 12800 Unbuffered DDR3 SDRAM DIMM DDR3 1600MHz 13 75 13 125 13 75 13 125 13 75 13 125 48 75 48 125 7 3 000 38 Reserved Reserved O o Reserved Reseved o 2500 3 300 o Reserved Reserved o Reserved 1 875 Reserved Reseved _ mns o Reserved Reseved ns 4 500 18755 o Reserved Reseved ns Reserved Reseved ns 4 500 1875 _______ CK AVG Reserved Reseved _ ns CK AVG Reserved Reseved Z C
36. s 350 mV peak to peak Differential swing requirement for DQS DQS is 700 mV peak to peak REV 1 0 8 05 2011 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F2G64CB88G7N M2F4G64CB8HG5N 2GB 256M x 64 4GB 512M x 64 10600 12800 r Unbuffered DDR3 SDRAM DIMM Operating Standby and Refresh Currents Tease 0 85 1 5V 0 075V 2GB 1 Rank 256Mx8 DDR3 SDRAMs IDDO Operating One Bank Active Precharge Current IDD1 Operating One Bank Active Read Precharge Current 537 563 mA IDD2PO Precharge Power Down Current Slow Exit 62 62 mA IDD2P1 Precharge Power Down Current Fast Exit 150 158 mA IDD2Q Precharge Quiet Standby Current 211 229 mA IDD2N Precharge Standby Current 246 264 mA IDD3P Active Power Down Current 202 211 mA IDD3N Active Standby Current 290 308 mA IDD4R Operating Burst Read Current 871 994 mA IDDAW Operating Burst Write Current 801 906 mA IDD5B Burst Refresh Current 1267 1294 mA 1206 Self Refresh Current Normal Temperature Range 62 62 mA IDD7 Operating Bank Interleave Read Current 1575 1610 mA Operating Standby and Refresh Currents Tease 0 85 1 5V 0 075V 4GB 2 Ranks 256Mx8 DDR3 SDRAMs IDDO Operating One Bank Active Precharge Current IDD1 Operating One Bank Active Read Precharge Current 827 871 mA IDD2PO Precharge Power Down Current Slow
37. te 2 Vref 0 15 Note 2 Vref 0 15 Note 2 V 1 VIL CA AC150 AC Input Logic Low Note 2 Vref 0 15 Note 2 Vref 0 15 Note 2 Vref 0 15 V 1 Reference Voltage VnetCA DO for ADD CMD 0 49 x VDD 0 51 x VDD 0 49 x VDD 0 51 xVDD 0 49 0 51x VDD V 3 4 Inputs Note 1 For input only pins except RESET Vref VrefCA DC 2 See Overshoot and Undershoot Specifications in the device datasheet 3 The peak noise on VRef may not allow VRef to deviate from VRefDQ DC by more than 1 VDD for reference approx 15 mV 4 For reference approx VDD 2 15 mV Single Ended AC and DC Input Levels for VIH DQ DC DC Input Logic High Vref 0 100 VDD Vref 0 100 VDD Vref 0 100 VDD VIL DQ DC DC Input Logic Low vss Vref 0 100 vss Vref 0 100 vss Vref 0 100 V 1 VIH DQ AC AC Input Logic High Vref 0 175 Note2 Vref 0 15 Note2 Vref 0 15 Note 2 V 1 2 5 VIL DQ AC Input Logic Low Note2 0 175 Note2 Vref 0 15 Note 2 Vref 0 15 V 1 2 5 Voltage for DM 0 49x VDD 0 51xVDD 0 49xVDD 0 51xVDD 049xVDD 0 51xVDD V 3 4 Note 1 For input only pins except RESET Vref VrefDQ DC 2 See Overshoot and Undershoot Specifications in the device datasheet 3 The ac peak noise on VRef may not allow VRef to deviate from VRefDQ DC by more than 1 VDD for reference approx 15 mV 4 For reference approx VDD 2 15 mV 5 Single ended swing requirement for DQS DQS i
38. te of BAO BAn inputs If AP is low then BAO BAn are used to define which bank to precharge DQ63 Input Data Input Output pins Vopspp Vss Supply Power supplies for core I O Serial Presence Detect Temp sensor and ground for the module Reference voltage for 557 15 inputs This is a bidirectional pin used to transfer data into or out of the SPD EEPROM and temp sensor SDA yo A resistor must be connected from the SDA bus line to on the system planar to act as a pull up SCL Input This signal is used to clock data into and out of the SPD EEPROM and Temp sensor SA2 Input Address pins used to select the Serial Presence Detect and Temp sensor base address EVENT Output The EVENT pin is reserved for use to critical module temperature RESET Input This signal resets the DDR3 SDRAM REV 1 0 4 05 2011 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F2G64CB88G7N M2F4G64CB8HG5N 2GB 256M x 64 4GB 512M x 64 10600 12800 X r Unbuffered DDR3 SDRAM DIMM Functional Block Diagram 2GB 1 Rank 256 8 DDR3 SDRAMs
39. tice M2F2G64CB88G7N M2F4G64CB8HG5N 2GB 256M x 64 4GB 512M x 64 PC3 10600 PC3 12800 el Unbuffered DDR3 SDRAM DIMM _ Dilcmgim _ sa ck tRTPmin max 4nCK 7 5ns Internal READ Command to PRECHARGE Command delay tRTPmax Delay from start of internal write tWTRmin max 4nCK 7 5ns transaction to internal read command tWTRmax WRITE recovery time wets Register Set command cycle time eo ooo ck tMODmin max 12nCK 15ns Mode Register Set command update delay tMODmax ACT to internal read or write delaytime eeo PRE command period IO ACT or REF command period CASH command delay bo ck Auto precharge write recovery precharge time WR roundup tRP tCK avg ok Multi Purpose Register Recovery Time ftwPRR toPRECHARGE commandperiod RAS to ACTIVE command period for 1KB page size RRD _ _ tRRDmin max 4nCK 10ns ACTIVE to ACTIVE command period for 2KB page size tRRDmax Four activate window for 1KB page size IFAW Four activate window for 2KB page size IFAW posts Command and Address setup time to CK CK tlS base 125 referenced to Vih ac Vil ac levels Command and Address hold time from CK tIH base 200 referenced to Vih dc
40. vels 175 25 tDS base Data setup time to DQS DQS referenced to Vih ac Vil ac levels 150 75 DH base Data hold time from 005 DQS referenced to Vih dc Vil dc levels DC100 DQandDMiputpusewidhforeachinut __ ew o 0 0 0 T DOSDOSHdifrenial READ Preamble mPRE oo ____ _ DOS DOSE differential READ Postamble Rest os ____ ___ DOS DASE differential output hightime jos os ___ DOS DOSRdferemiaowpulow m poss 08 ___ DOS DOSE differential WRITE Preamble o O DOS DOSE differential WRITE Postamble __ 05 DASE rising edge output access time rising CK CK amp DasCK 0 ____ DQS and DQS low impedance time tLZ DQS 300 tCK avg Referenced from RL 1 DQS and DQS high impedance time tHZ DQS 300 tCK avg Referenced from RL BL 2 DOS DASE differential input low pulse width 045 ___ feo se e DOS DASE rising edge to CK rising edge _________ 5 os 05 edge jos __ o DoS in gs fil Sos Plena DAE ER REV 1 0 12 05 2011 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without no
Download Pdf Manuals
Related Search