Transcend 256MB SDRAM 144Pin SO-DIMM PC133 Unbuffer Non-ECC Memory
Contents
1. 20ns 45ns 128MB 1 5ns 0 8ns 1 5ns NO N O TI Minimum Row Active to Row Activate Minimum RAS to CAS Delay Minimum RAS Pulse Width Density of Each Bank on Module Command Address Setup Time Command Address Hold Time Data Signal Setup Time N ee N O N U oO NO _ _ GO oO N Q9 K Ql Transcend information Inc 144PIN PC133 Unbuffered SO DIMM TS32MSS64V6L 256MB With 16M X 8 CL3 35 Data SignalHoldTime Ts 6 6 3 5 O Go 36 61 Superset Information O Y o 63 Checksumftor Bytes 0 62 0 Bo B 72 Manufacturing Location T a 73 90 Manufacturers Part Number TS32MSS64V6L a ae 99 125 Manufacturer Specific Data o o o o Transcend information Inc ll2. Input capacitance RAS CAS WE Input capacitance CKEO CKE71 Input capacitance CLKO CLK1 Input capacitance CSO CS1 Input capacitance DQM0 DQM 7 Data input output capacitance DQ0 DQ63 Transcend information Inc TS32MSS64V6L 144PIN PC133 Unbuffered SO DIMM 256MB With 16M X 8 CL3 DC CHARACTERISTICS Recommended operating condition unless otherwise noted TA 0 to 70 C Parameter Operating Current One Bank Active Precharge Standby Current in power down mode Precharge Standby Current in non power down mode Active Standby Current in power down mode Active Standby Current in non power down mode One Bank Active Operating Current Burst Mode Value Unit Note _ k p ICC2P_ CKE lt VIL max tCC 10ns a ICC2PS CKE amp CLK lt VIL CKE amp CLK lt VIL max tCC tCC lt hate Se ee eee min CS VIH min t C 10ns mA Input signals are changed one time during 20ns ICC2NS CKE gt VIH min CLK lt VIL max tOC lt Input signals are stable ICC3P CKE lt VIL max tCC 10ns ICC3PS CKE amp CLK lt VIL max tCC Symbol Test Condition ICC1 Burst Length 1 tRC gt tRC min IOL 0mA a Pets nakd CKE gt VIH min CS gt VIH min tCC 10ns Input signals are changed one time during 20ns ICC3NS CKE gt VIH min CLK lt VIL max tCC Input signals are stable IOL 0 mA Refresh current ICCS tRC gt tRC min Self Refresh Current ICC6 CKE lt 0 2V OA mA Note Mo
3. TS32MSS64V6L 144PIN PC133 Unbuffered SO DIMM 256MB With 16M X 8 CL3 Description The TS32MSS64V6L is a 32M bit x 64 Synchronous Dynamic RAM high density memory modules The TS32MSS64V6L consists of 16 pieces of CMOS 16Mx8bits Synchronous DRAMs in WBGA packages and a 2048 bits serial EEPROM on a 144 pin printed circuit board The TS32MSS64V6L is a Dual In Line Memory Module and is intended for mounting into 144 pin edge connector sockets Synchronous design allows precise cycle control with the use of system clock I O transactions are possible on every clock cycle Range of operation frequencies programmable latencies allow the same device to be useful for a variety of high bandwidth high performance memory system applications Features e Performance Range PC 133 e Burst Mode Operation e Auto and Self Refresh e Serial Presence Detect SPD with serial EEPROM e LVTTL compatible inputs and outputs e Single 3 3V 0 3V power supply e MRS cycle with address key programs Latency Access from column address Burst Length 1 2 4 8 and Full Page Data Sequence Sequential amp Interleave e All inputs are sampled at the positive going edge of the system clock Pin Identification Symbol AO A11 BAO BA1 DQ0 DQ63 CLKO CLK1 CKEO CKE1 CSO CS1 RAS ICAS WE DQMO0 7 Vcc Vss SDA SCL NC Function Address inputs select Bank Data inputs outputs Clock Input Clock Enable Input Chip Select Input Row a
4. ddress strobe Column address strobe Write Enable Data Mask Power Supply Ground Serial Address Data I O Serial Clock No Connection Transcend information Inc TS32MSS64V6L Dimension Transcend information Inc Side A I O Iim m U IO W q Millimeters 67 60 0 200 32 80 23 20 4 60 3 30 2 50 4 00 6 00 20 00 31 75 0 200 1 00 0 100 144PIN PC133 Unbuffered SO DIMM gt PCB 09 1330 Inches 2 661 0 008 1 291 0 913 0 181 0 130 0 098 0 157 0 236 0 787 1 250 0 008 0 039 0 004 256MB With 16M X 8 CL3 144PIN PC133 Unbuffered SO DIMM TS32MSS64V6L 256MB With 16M X 8 CL3 Pinouts Pin Pin Pin i Pin i Pin Pin Name No Name No Name No Name No Name No Name Please refer Block Diagram Transcend information Inc 144PIN PC133 Unbuffered SO DIMM TS32MSS64V6L 256MB With 16M X 8 CL3 Block Diagram AO A11 BAOSBAI A0 A11 BA0 1 A0 A11 BA0 1 A0 A11 BA0 1 a DQO 7 DQ0 7 DOOS Dan Deere RAS J mas ICAS CAS 16Mx8 ICAS 16Mx8 li ICAS 16Mx8 WE a Wwe SDRAM SDRAM i oe CSO ae ld CKEO i E TIRS i i AO A11 BAO 1 DQO0 7 RAS CAS 16Mx8 16Mx8 16Mx8 CAS 16Mx8 SDRAM SDRAM SDRAM WE SDRAM CS1 ICS CKE1 CLK1 a A0O A11 BA0 1 DQO 7 RAS CAS 16Mx8 IWE SDRAM ICS CKE CLK SDA SCL This technical information is based on industry standard data and tests believed to be reliable However Transc
5. dule IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap Transcend information Inc 144PIN PC133 Unbuffered SO DIMM TS32MSS64V6L 256MB With 16M X 8 CL3 AC OPERATING TEST CONDITIONS VDD 2 5 VDDQ 2 5 TA 0 to 70 C Parameter Pale nit AC Input levels VIH VIL nput timing measurement reference level nput rise and fall time Output timing measurement reference level Output load condition Output gt Von DC 2 4V lon 2mA Output Z0 50 Ohm VoL DC 0 4V lo 2mA 50pF 50pF 870 Ohm MUA VII T Fig 1 DC Output Load Circuit Fig 2 AC Output Load Circuit OPERATING AC PARAMETER AC operating conditions unless otherwise noted Row active to row active delay tRRD min IRAS to ICAS delay tRCD min Row precharge time tRP min a RAB ria R tive t Row cycle ime _ Operation tRC min 6o astona pio nevoa adaressday eom i e fe Last data in to Active delay SS tDAL min 2CLK tRP O precharge Last data in to burst stop Col address to col address delay Number of valid output data Pt ea 4 Note 1 The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer 2 Minimum delay is required to complete write 3 All parts allow every cycle column address change 4 In case of row precharge interrupt auto p
6. end makes no warranties either expressed or implied as to its accuracy and assume no liability in connection with the use of this product Transcend reserves the right to make changes in specifications at any time without prior notice Transcend information Inc 144PIN PC133 Unbuffered SO DIMM TS32MSS64V6L 256MB With 16M X 8 CL3 ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to Vss Voltage on VDD supply relative to Vss torage temperature Power dissipation 16 hort circuit current Mean time between failure 0 emperature Humidity Burning emperature Cycling Test Note 1 Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded 2 Functional operation should be restricted to recommended operating condition 3 Exposure to higher than recommended voltage for extended periods of time could affect device reliability DC OPERATING CONDITIONS AND CHARACTERISTICS Recommended operating conditions Voltage referenced to Vss 0V TA 0 to 70 C Symbol Min Typ Max Unt Note Note 1 All voltages are referenced to Vss 2 VIH may overshoot to VDD 2 0V for pulse width of lt 4ns with 3 3V VIL may undershoot to 2 0V for pulse width lt 4 0ns with 3 3V Pulse width measured at 50 points with amplitude measured peak to DC reference CAPACITANCE VDD 3 3V TA 23 C f 1MHz VREF 1 4V 200mV Parameter Symbol Min Max Uit Input capacitance A0 A11 BAO BA1
7. ew command can be issued after 2 CLK cycles of MRS 3 Auto refresh functions are as same as CBR refresh of DRAM The automatically precharge without row precharge command is meant by Auto Auto self refresh can be issued only at all banks precharge state 4 BAo BA1 Bank select address If both BAo and BA are Low at read write row active and precharge bank A is selected If both BAo is Low and BA1 is High at read write row active and precharge bank B is selected If both BAo is High and BA1 is Low at read write row active and precharge bank C is selected If both BAo and BA are High at read write row active and precharge bank D is selected If A10 AP is High at row precharge BAo and BAi are ignored and all banks are selected 5 During burst read or write with auto precharge new read write command cannot be issued Another bank read write command can be issued after the end of burst New row active of the associated bank can be issued at tRP after the end of burst 6 Burst stop command is valid at every burst length 7 DQM sampled at positive going edged of a CLK masks the data in at the very CLK Write DQM latency is 0 but makes Hi Z state the data out of 2 CLK cycles after Read DQM latency is 2 Transcend information Inc 144PIN PC133 Unbuffered SO DIMM TS32MSS64V6L 256MB With 16M X 8 CL3 Serial Presence Detect Specification Serial Presence Detect 2
8. recharge and read burst stop Transcend information Inc 144PIN PC133 Unbuffered SO DIMM TS32MSS64V6L 256MB With 16M X 8 CL3 AC CHARACTERISTICS AC operating conditions unless otherwise noted Refer to the individual component not the whole module CLK to valid output delay CLK high pulse width CLK low pulse width Input setup time Input hold time CLK to output in Low Z Note 1 Parameters depend on programmed CAS latency 2 If clock rising time is longer than ns tr 2 0 5 ns should be added to the parameter 3 Assumed input rise and fall time tr amp tf 1ns if tr amp tf is longer than 1ns transient time compensation should be considered i e tr tf 2 1 ns should be added to the parameter Transcend information Inc 144PIN PC133 Unbuffered SO DIMM TS32MSS64V6L 256MB With 16M X 8 CL3 SIMPLIFIED TRUTH TABLE Mode Register Set Refresh ZOONEN ef Bank Active amp Row Addr aa Read amp Auto Precharge Disable Column Address Column Address Auto Precharge Enable AO AQ Write amp Auto Precharge Disable Column Column Address Auto Precharge Enable Address DA z gt DA z Clock Suspend or Active Power ma Precharge Power Down Mode No Operation Command eS aE V Valid X Don t Care H Logic High L Logic Low Note 1 OP Code Operand Code Ao A11 BAo BA1 Program keys MRS 2 MRS can be issued only at all banks precharge state A n
9. z O N ee TI Standard Specification Vendor Part 128bytes 256bytes SDRAM Byte No Function Described Number of Bytes Written into Serial Memory Total Number of Bytes of S P D Memory Fundamental Memory Type Number of Row Addresses on this Assembly Number of Column Addresses on this Assembly Number of Module Banks on this Assembly Data Width of this Assembly Data Width Continuation Voltage Interface Standard of this Assembly SDRAM Cycle Time highest CAS latency SDRAM Access from Clock highest CL DIMM configuration type non parity ECC Refresh Rate Type Primary SDRAM Width Error Checking SDRAM Width Min Clock Delay Back to Back Random Address Burst Lengths Supported Number of banks on each SDRAM device CAS Latency CS Latency Write Latency SDRAM Module Attributes SDRAM Device Attributes General P S O S 2 banks 64bits K LVTTL3 3V 7 5NS 5 4ns DIMM 15 625us Self Refresh N O1 0 11 2 2 lt oe p y K 1 clock 1 2 4 8 amp Full page 4 bank CL2 amp CL3 0 clock 15 m s O O 8 9 O O O clock Non Buffer Prec All Auto Prec R W Burst 23 SDRAM Cycle Time 2 highest CL 10ns 24 SDRAM Access from Clock 2 highest CL 25 SDRAM Cycle Time 3 highest CL 26 SDRAM Access from Clock 3 highest CL Minimum Row Precharge Time NO D gt 21 22 m gt ak ax QI gt O K 20ns 15ns
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