Home

Intel Pentium D 840

1. u Land Name da odati Direction W Land Name oi i Direction N30 VCC Power Other T23 VCC Power Other P1 TESTHI11 Power Other Input T24 VCC Power Other P2 SMI Asynch GTL Input T25 VCC Power Other P3 INIT Asynch GTL Input T26 VCC Power Other P4 VSS Power Other T27 VCC Power Other P5 RESERVED T28 VCC Power Other P6 A4 Source Synch Input Output T29 VCC Power Other P7 VSS Power Other T30 VCC Power Other P8 VCC Power Other U1 VSS Power Other P23 VSS Power Other U2 APO Common Clock Input Output P24 VSS Power Other U3 AP1 Common Clock Input Output P25 VSS Power Other U4 A13 Source Synch Input Output P26 VSS Power Other U5 A12 Source Synch Input Output P27 VSS Power Other U6 A10 Source Synch Input Output P28 VSS Power Other U7 VSS Power Other P29 VSS Power Other U8 VCC Power Other P30 VSS Power Other U23 VCC Power Other R1 COMP3 Power Other Input U24 VCC Power Other R2 VSS Power Other U25 VCC Power Other R3 FERR PBE Asynch GTL Output U26 VCC Power Other R4 A8 Source Synch Input Output U27 VCC Power Other R5 VSS Power Other U28 VCC Power Other R6 ADSTBO Source Synch Input Output U29 VCC Power Other R7 VSS Power Other U30 VCC Power Other R8 VCC Power Other Vi MSID1 Power Other Input R23 VSS Power Other v2 LL_IDO Power Other Output R24 VSS Power Other V3 VSS Power Other R25 VSS Power Other V4 A15 Source Synch Input Output R26 VSS Power Other V5 A14 Source Synch
2. Table 8 2 Balanced Technology Extended BTX Type Boxed Processor TMA Set Points for 3 wire Operation Boxed Processor TMA Set Point GC Boxed Processor Fan Speed Notes When the internal chassis temperature is below or equal to this set point X lt 23 the fan operates at its lowest speed Recommended maximum internal chassis temperature for nominal operating environment When the internal chassis temperature is at this point the fan operates Y 29 between its lowest and highest speeds Recommended maximum internal chassis temperature for worst case operating environment When the internal chassis temperature is above or equal to this set point 1 2235 the fan operates at its highest speed NOTES 1 Set point variance is approximately 1 C from fan heatsink to fan heatsink 102 Datasheet intel Datasheet Balanced Technology Extended BTX Type I Boxed Processor Specifications If the boxed processor TMA 4 pin connector is connected to a 4 pin motherboard header and the motherboard is designed with a fan speed controller with PWM output see Table 8 1 and remote thermal diode measurement capability the boxed processor will operate as described in the following paragraphs As processor power has increased the required thermal solutions have generated increasingly more noise Intel has added an option to the boxed processor that allows system integrators to have a quieter system in the m
3. TESTHI8 cannot be grouped with other TESTHI signals e TESTHI9 cannot be grouped with other TESTHI signals e TESTHII10 cannot be grouped with other TESTHI signals e TESTHI11 cannot be grouped with other TESTHI signals e TESTHI12 cannot be grouped with other TESTHI signals e TESTHI13 cannot be grouped with other TESTHI signals Datasheet Intel 2 5 2 5 1 Table 2 2 2 5 2 Datasheet Electrical Specifications Voltage and Current Specifications Absolute Maximum and Minimum Ratings Table 2 2 specifies absolute maximum and minimum ratings Within functional operation limits functionality and long term reliability can be expected At conditions outside functional operation condition limits but within absolute maximum and minimum ratings neither functionality nor long term reliability can be expected If a device is returned to conditions within functional operation limits after having been subjected to conditions outside these limits but within the absolute maximum and minimum ratings the device may be functional but with its lifetime degraded depending on exposure to conditions exceeding the functional operation condition limits At conditions exceeding absolute maximum and minimum ratings neither functionality nor long term reliability can be expected Moreover if a device is subjected to these conditions for any length of time then when returned to conditions within the functional operating
4. j E instructions e Binary compatible with applications running on previous members of the Intel microprocessor line 13 Streaming SIMD Extensions 3 SSE3 A instructions e Intel NetBurst microarchitecture Enhanced floating point and multimedia unit for enhanced video audio encryption and 3D performance FSB frequency at 800 MHz Pentium D Processors 840 830 and 820 only FSB frequency at 533 MHz Pentium D Processor Power Management capabilities 805 only e Hyper Pipelined Technology W Multiple low power states Advance Dynamic Execution P P e 8 way cache associativity provides improved cache hit rate on load store operations e 775 land Package Very deep out of order execution Enhanced branch prediction The Intel Pentium D processor delivers Intel s advanced powerful processors for desktop PCs that are based on the Intel NetBurst microarchitecture The Pentium D processor is designed to deliver performance across applications and usages where end users can truly appreciate and experience the performance These applications include Internet audio and streaming video image processing video content creation speech 3D CAD games multimedia and multitasking user environments Intel Extended Memory 64 Technology Intel EM64T enables the Pentium D processor to execute operating systems and applications written to take advantage of the Intel EM64T The Pentium D processor 84
5. d 124 00 BS j 4 882 I U i Example PCI i I Connectors 146 57 i 1 A 5 770 1 i i i i A l 242 57 254 00 Pee GE S x 9 550 10 000 a 10 0001 gt wih 15 RS Be mB AS SB P ux039 005 C Ba gs ZG e RES 0 002 0 156 Go za 0 20 25 12 0 25 cke 1 58 Tan Le 1280020010 ed o 0 20 o o08 aB C 0 062 40 008 Mounting Holes 062 10 005 Thermal Specifications This section describes the cooling requirements of the fan heatsink solution used by the boxed processor Boxed Processor Cooling Requirements The boxed processor may be directly cooled with a fan heatsink However meeting the processor s temperature specification is also a function of the thermal design of the entire system and ultimately the responsibility of the system integrator The processor temperature specification is found in Chapter 5 The boxed processor TMA is able to keep the processor temperature within the specifications listed in Table 5 1 for chassis that provide good thermal management For the boxed processor TMA to operate properly it is critical that the airflow provided to the TMA is unimpeded Airflow of the TMA is into the duct and out of the rear of the duct in a linear flow Blocking the airflow to the TMA inlet reduces the cooling efficiency and decreases fan life The air temperature entering the fan should be kept below 35 C Meeting the processor s temperature specification is the responsibility of
6. 71 Land Listing and Signal Descriptions intal Table 4 3 Signal Description Sheet 7 of 8 Name Type Description RSP Input RSP Response Parity is driven by the response agent the agent responsible for completion of the current transaction during assertion of RS 2 0 the signals for which RSP provides parity protection It must connect to the appropriate pins lands of all processor FSB agents A correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low While RS 2 0 000 RSP is also high since this indicates it is not being driven by any agent ensuring correct parity SKTOCC Output SKTOCC Socket Occupied will be pulled to ground by the processor System board designers may use this signal to determine if the processor is present SMI Input SMI System Management Interrupt is asserted asynchronously by system logic On accepting a System Management Interrupt the processor saves the current state and enters System Management Mode SMM An SMI Acknowledge transaction is issued and the processor begins program execution from the SMM handler If SMI is asserted during the de assertion of RESET the processor will tri state its outputs STPCLK Input STPCLK Stop Clock when asserted causes the processor to enter a low power Stop Grant state The processor issues a Stop Grant Acknowledge t
7. AM AL AK AJ AH AG AF AE AD AC AB 45 Land Listing and Signal Descriptions 46 Table 4 1 Alphabetical Land intal Table 4 1 Alphabetical Land Assignments Assignments Land Name send i Direction Land Name a m Direction A3 L5 Source Synch Input Output BCLK1 G28 Clock Input A4 P6 Source Synch Input Output BINIT AD3 Common Clock Input Output A5 M5 Source Synch Input Output BNR C2 Common Clock Input Output AG L4 Source Synch Input Output BOOTSELECT Y1 Power Other Input A7 M4 Source Synch Input Output BPMO AJ2 Common Clock Input Output A8 R4 Source Synch Input Output BPM1 AJ1 Common Clock Input Output A9 amp T5 Source Synch Input Output BPM2 AD2 Common Clock Input Output A10 U6 Source Synch Input Output BPM3 AG2 Common Clock Input Output A11 T4 Source Synch Input Output BPM4 AF2 Common Clock Input Output A12 U5 Source Synch Input Output BPM5 AG3 Common Clock Input Output A13 U4 Source Synch Input Output BPRI G8 Common Clock Input A14 V5 Source Synch Input Output BRO F3 Common Clock Input Output A15 V4 Source Synch Input Output BSELO G29 Power Other Output A16 W5 Source Synch Input Output BSEL1 H30 Power Other Output A17 AB6 Source Synch Input Output BSE
8. DBR Debug Reset is used only in processor systems where no debug port is implemented on the system board DBR is used by a debug port interposer so DBR Output that an in target probe can drive system reset If a debug port is implemented in the system DBR is a no connect in the system DBR is not a processor signal DBSY Data Bus Busy is asserted by the agent responsible for driving data on Input the processor FSB to indicate that the data bus is in use The data bus is Output released after DBSY is de asserted This signal must connect the appropriate pins lands on all processor FSB agents DBSY DEFER is asserted by an agent to indicate that a transaction cannot be ensured in order completion Assertion of DEFER is normally the responsibility of the addressed memory or input output agent This signal must connect the appropriate pins lands of all processor FSB agents DEFER Input DP 3 0 Data parity provide parity protection for the D 63 0 signals They are driven by the agent responsible for driving D 63 0 and must connect the appropriate pins lands of all processor FSB agents Input DP 3 0 Output 68 Datasheet Land Listing and Signal Descriptions Table 4 3 Signal Description Sheet 4 of 8 Name Type Description DRDY Input Output DRDY Data Ready is asserted by the data driver on each data transfer indicating valid data on the data bus In a mul
9. Pentium Processor Extreme Edition and Intel Pentium D Processor Specification Update Enhanced Intel SpeedStep Technology is a technology that creates processor performance states P states P states are power consumption and capability states within the Normal state as shown in Figure 6 1 Enhanced Intel SpeedStep Technology enables real time dynamic switching between frequency and voltage points It alters the performance of the processor by changing the bus to core frequency ratio and voltage This allows the processor to run at different core frequencies and voltages to best serve the performance and power requirements of the processor and system Note that the front side bus is not altered only the internal core frequency is changed To run at reduced power consumption the voltage is altered in step with the bus ratio The following are key features of Enhanced Intel SpeedStep Technology e Voltage Frequency selection is software controlled by writing to processor MSRs Model Specific Registers thus eliminating chipset dependency If the target frequency is higher than the current frequency Vcc is incremented in steps 12 5 mV by placing a new value on the VID signals and the processor shifts to the new frequency Note that the top frequency for the processor can not be exceeded If the target frequency is lower than the current frequency the processor shifts to the new frequency and V c is then decremented in steps 12 5
10. Intel Pentium D Processor 800 Sequence Datasheet On 90 nm Process in the 775 land LGA Package and supporting Intel Extended Memory 64 Technology February 2006 Document Number 307506 003 Contents l n A INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS NO LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT EXCEPT AS PROVIDED IN INTEL S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO SALE AND OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE MERCHANTABILITY OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT INTEL PRODUCTS ARE NOT INTENDED FOR USE IN MEDICAL LIFE SAVING OR LIFE SUSTAINING APPLICATIONS Intel may make changes to specifications and product descriptions at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them The Intel Pentium D processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications Current characterized e
11. Power Other VCC AE15 Power Other VCC AH22 Power Other VCC AE18 Power Other VCC AH25 Power Other VCC AE19 Power Other VCC AH26 Power Other VCC AE21 Power Other VCC AH27 Power Other VCC AE22 Power Other VCC AH28 Power Other VCC AE23 Power Other VCC AH29 Power Other VCC AE9 Power Other VCC AH30 Power Other VCC AF11 Power Other VCC AH8 Power Other VCC AF12 Power Other VCC AH9 Power Other VCC AF14 Power Other VCC AJ11 Power Other VCC AF15 Power Other VCC AJ12 Power Other VCC AF18 Power Other VCC AJ14 Power Other VCC AF19 Power Other VCC AJ15 Power Other VCC AF21 Power Other VCC AJ18 Power Other VCC AF22 Power Other VCC AJ19 Power Other VCC AF8 Power Other VCC AJ21 Power Other VCC AF9 Power Other VCC AJ22 Power Other VCC AG11 Power Other VCC AJ25 Power Other VCC AG12 Power Other VCC AJ26 Power Other VCC AG14 Power Other VCC AJ8 Power Other VCC AG15 Power Other VCC AJ9 Power Other VCC AG18 Power Other VCC AK11 Power Other VCC AG19 Power Other VCC AK12 Power Other 49 Land Listing and Signal Descriptions 50 Table 4 1 Alphabetical Land Assignments intal Table 4 1 Alphabetical Land Assignments Land Name K DE Direction Land Name bana i Direction VCC AK14 Power Other VCC AN14 Pow
12. Power Other VSS AH6 Power Other VSS AE27 Power Other VSS AH7 Power Other VSS AE28 Power Other VSS AJ10 Power Other VSS AE29 Power Other VSS AJ13 Power Other VSS AE30 Power Other VSS AJ16 Power Other VSS AE5 Power Other VSS AJ17 Power Other VSS AE7 Power Other VSS AJ20 Power Other Datasheet Datasheet Table 4 1 Alphabetical Land Assignments Land Listing and Signal Descriptions Table 4 1 Alphabetical Land Assignments Land Name kg mm Direction Land Name sam i a Direction VSS AJ23 Power Other VSS AM24 Power Other VSS AJ24 Power Other VSS AM27 Power Other VSS AJ27 Power Other VSS AM28 Power Other VSS AJ28 Power Other VSS AM4 Power Other VSS AJ29 Power Other VSS AN1 Power Other VSS AJ30 Power Other VSS AN10 Power Other VSS AJ4 Power Other VSS AN13 Power Other VSS AJ7 Power Other VSS AN16 Power Other VSS AK10 Power Other VSS AN17 Power Other VSS AK13 Power Other VSS AN2 Power Other VSS AK16 Power Other VSS AN20 Power Other VSS AK17 Power Other VSS AN23 Power Other VSS AK2 Power Other VSS AN24 Power Other VSS AK20 Power Other VSS AN27 Power Other VSS AK23 Power Other VSS AN28 Power Other VSS AK24 Power Other VSS B1 Power Other VSS AK27 Power Other VSS B11 Power Other VSS AK28 Power Other VSS
13. J26 VCC Power Other M5 A5 Source Synch Input Output J27 VCC Power Other M6 REQ2 Source Synch Input Output J28 VCC Power Other M7 VSS Power Other J29 VCC Power Other M8 VCC Power Other J30 VCC Power Other M23 VCC Power Other K1 LINTO Asynch GTL Input M24 VCC Power Other K2 VSS Power Other M25 VCC Power Other K3 A20M Asynch GTL Input M26 VCC Power Other K4 REQO Source Synch Input Output M27 VCC Power Other K5 VSS Power Other M28 VCC Power Other K6 REQ3 Source Synch Input Output M29 VCC Power Other K7 VSS Power Other M30 VCC Power Other K8 VCC Power Other N1 PWRGOOD Power Other Input K23 VCC Power Other N2 IGNNE Asynch GTL Input K24 VCC Power Other N3 VSS Power Other K25 VCC Power Other N4 RESERVED K26 VCC Power Other N5 RESERVED K27 VCC Power Other N6 VSS Power Other K28 VCC Power Other N7 VSS Power Other K29 VCC Power Other N8 VCC Power Other K30 VCC Power Other N23 VCC Power Other L1 LINT1 Asynch GTL Input N24 VCC Power Other L2 TESTHI13 Asynch GTL Input N25 VCC Power Other L3 VSS Power Other N26 VCC Power Other L4 AG Source Synch Input Output N27 VCC Power Other L5 A3 Source Synch Input Output N28 VCC Power Other L VSS Power Other N29 VCC Power Other 59 Land Listing and Signal Descriptions 60 Table 4 2 Numerical Land Assignment intel Table 4 2 Numerical Land Assignment
14. Power Other VCC Y29 Power Other VCC N29 Power Other VCC Y30 Power Other VCC N30 Power Other VCC Y8 Power Other VCC N8 Power Other VCC_MB REGULATION AN5 Power Other Output VCC P8 Power Other VCC_SENSE AN3 Power Other Output VCC R8 Power Other VCCA A23 Power Other VCC T23 Power Other VCCIOPLL C23 Power Other VCC T24 Power Other VCCPLL D23 Power Other Input VCC T25 Power Other VIDO AM2 Power Other Output VCC T26 Power Other VID1 AL5 Power Other Output VCC T27 Power Other VID2 AM3 Power Other Output VCC T28 Power Other VID3 AL6 Power Other Output VCC T29 Power Other VID4 AK4 Power Other Output VCC T30 Power Other VID5 AL4 Power Other Output VCC T8 Power Other VSS A12 Power Other VCC U23 Power Other VSS A15 Power Other VCC U24 Power Other VSS A18 Power Other VCC U25 Power Other VSS A2 Power Other VCC U26 Power Other VSS A21 Power Other VCC U27 Power Other VSS A24 Power Other VCC U28 Power Other VSS A6 Power Other VCC U29 Power Other VSS A9 Power Other VCC U30 Power Other VSS AA23 Power Other 51 Land Listing and Signal Descriptions 52 Table 4 1 Alphabetical Land Assignments intal Table 4 1 Alphabetical Land Assignments Land Name send ii i Direction Land Name kana mm Direction VSS AA24 Power Other VSS AF10 Powe
15. cooling failure the processor will automatically shut down when the silicon has reached an elevated temperature refer to the THERMTRIP definition in Table 4 3 At this point the FSB signal THERMTRIP will go active and stay active as described in Table 4 3 THERMTRIP activation is independent of processor activity and does not generate any bus cycles TconrtroL and Fan Speed Reduction TCONTROL is a temperature specification based on a temperature reading from the thermal diode The value for TcoNTROL Will be calibrated in manufacturing and configured for each processor When TDIoDE is above TCONTROL then Te must be at or below Tc Max as defined by the thermal profile in Table 5 2 and Figure 5 1 otherwise the processor temperature can be maintained at TCONTROL or lower as measured by the thermal diode The purpose of this feature is to support acoustic optimization through fan speed control Thermal Diode The processor incorporates an on die thermal diode A thermal sensor located on the system board may monitor the die temperature of the processor for thermal management long term die temperature change purposes Table 5 4 and Table 5 5 provide the diode parameter and interface specifications This thermal diode is separate from the Thermal Monitor s thermal sensor and cannot be used to predict the behavior of the Thermal Monitor Table 5 4 Thermal Diode Parameters 82 Symbol Parameter Mi
16. 0 0 0 0 1 0750 1 1 0 0 0 0 1 4500 0 0 0 0 0 0 1 0875 0 1 0 0 0 0 1 4625 1 1 1 1 1 1 VR output off 1 0 1 1 1 1 1 4750 0 1 1 1 1 1 VR output off 0 0 1 1 1 1 1 4875 1 1 1 1 1 0 1 1000 1 0 1 1 1 0 1 5000 0 1 1 1 1 0 1 1125 0 0 1 1 1 0 1 5125 1 1 1 1 0 1 1 1250 1 0 1 1 0 1 1 5250 0 1 1 1 0 1 1 1375 0 0 1 1 0 1 1 5375 1 1 1 1 0 0 1 1500 1 0 1 1 0 0 1 5500 0 1 1 1 0 0 1 1625 0 0 1 1 0 0 1 5625 1 1 1 0 1 1 1 1750 1 0 1 0 1 1 1 5750 0 1 1 0 1 1 1 1875 0 0 1 0 1 1 1 5875 1 1 1 0 1 0 1 2000 1 0 1 0 1 0 1 6000 Datasheet 17 m Electrical Specifications ntal a 2 4 Reserved Unused FC and TESTHI Signals All RESERVED lands must remain unconnected Connection of these lands to Voc Vss VTT or to any other signal including each other can result in component malfunction or incompatibility with future processors See Chapter 4 for a land listing of the processor and the location of all RESERVED lands For reliable operation always connect unused inputs or bidirectional signals to an appropriate signal level In a system level design on die termination has been included on the Pentium D processor to allow signals to be terminated within the processor silicon Most unused GTL inputs should be left as no connects as GIL termination is provided on the processor silicon However see Table 2 8 for details on GTL signals that do not include on die termination Unused active high inputs should be conn
17. 1 Individual processor VID values may be calibrated during manufacturing such that two devices at the same speed may have different VID settings 2 These voltages are targets only A variable voltage source should exist on systems in the event that a different voltage is required See Section 2 3 and Table 2 1 for more information 3 The voltage specification requirements are measured across VCC_SENSE and VSS_SENSE lands at the socket with a 100 MHz bandwidth oscillo scope 1 5 pF maximum probe capacitance and 1 MQ minimum impedance The maximum length of ground wire on the probe should be less than 5 mm Ensure external noise from the system is not coupled into the oscilloscope probe 4 Refer to Table 2 5 and Figure 2 2 for the minimum typical and maximum Vcc allowed for a given current The processor should not be subjected to any Vcc and Icc combination wherein Vgc exceeds Voc max for a given current 20 Datasheet m l ntel e Electrical Specifications 10 11 12 13 14 15 16 775_VR_CONFIG_05A and 775_VR_CONFIG_05B refer to voltage regulator configurations that are defined in the Voltage Regulator Down VRD 10 1 Design Guide For Desktop LGA775 Socket Refer to Table 2 4 and Figure 2 1 for the minimum typical and maximum Vcc allowed for a given current The processor should not be subjected to any Voc and le combination wherein Vogg exceeds Voc max for a given current These frequencies will operate properly in
18. 4 VID 0 150 4 VID 0 163 5 VID 0 175 4 VID 0 188 NOTES 1 The loadline specification includes both static and transient limits except for overshoot allowed as shown in Section 2 5 3 2 This loadline specification shows the deviation from the VID set point 3 The loadlines specify voltage limits at the die measured at the VCC_SENSE and VSS_SENSE lands Voltage regulation feedback for voltage regulator circuits must be taken from processor VCC and VSS lands Refer to the Voltage Regulator Down VRD 10 1 Design Guide For Desktop LGA775 Socket for socket loadline guidelines and VR implementation details 22 Datasheet Electrical Specifications Table 2 5 Vcc Static and Transient Tolerance for 775_VR_CONFIG_05B Pentium D Processor Icc A Voltage Deviation from VID Setting V 2 3 Maximum Voltage Typical Voltage Minimum Voltage 1 30 mQ 1 38 mQ 1 45 ma 0 0 000 0 019 0 038 5 0 007 0 026 0 045 10 0 013 0 033 0 053 15 0 020 0 040 0 060 20 0 026 0 047 0 067 25 0 033 0 053 0 074 30 0 039 0 060 0 082 35 0 046 0 067 0 089 40 0 052 0 074 0 096 45 0 059 0 081 0 103 50 0 065 0 088 0 111 55 0 072 0 095 0 118 60 0 078 0 102 0 125 65 0 085 0 108 0 132 70 0 091 0 115 0 140 75 0 098 0 122 0 147 80 0 101 0 126 0 151 85 0 111 0 136 0 161 90 0 117 0 143 0 169 95 0 12
19. 54 54 6 88 61 4 122 68 2 22 48 2 56 55 0 90 61 8 124 68 6 24 48 6 58 55 4 92 62 2 126 69 0 26 49 0 60 55 8 94 62 6 128 69 4 28 49 4 62 56 2 96 63 0 130 69 8 30 49 8 64 56 6 98 63 4 32 50 2 66 57 0 100 63 8 Figure 5 1 Thermal Profile for the Pentium D Processor with PRB 1 75 0 70 0 y 0 20x 43 8 Tcase C 40 0 tt ttt tt ttt 0 10 20 30 40 50 60 70 80 90 100 110 120 130 Power W Datasheet 77 Thermal Specifications and Design Considerations 78 In Table 5 3 Thermal Profile for the Pentium D Processor with PRB 0 Power Maximum To Power Maximum Te Power Maximum Te Power Maximum Te W C W C W C W C 0 43 2 26 48 9 52 54 6 78 60 4 2 43 6 28 49 4 54 55 1 80 60 8 4 44 1 30 49 8 56 55 5 82 61 2 6 44 5 32 50 2 58 56 0 84 61 7 8 45 0 34 50 7 60 56 4 86 62 1 10 45 4 36 51 1 62 56 8 88 62 6 12 45 8 38 51 6 64 57 3 90 63 0 14 46 3 40 52 0 66 57 7 92 63 4 16 46 7 42 52 4 68 58 2 94 63 9 18 47 2 44 52 9 70 58 6 95 64 1 20 47 6 46 53 3 72 59 0 22 48 0 48 53 8 74 59 5 24 48 5 50 54 2 76 59 9 Figure 5 2 Thermal Profile for the Pentium D Processor with PRB 0 70 0 65 0 y 0 22x 43 2 60 0 amp 3 55 0 KJ 50 0 45 0 40 0 d d d d 10 20 30 40 50 60 70 80 90 Power W Datasheet intel 5 1 2 Thermal S
20. B14 Power Other VSS AK29 Power Other VSS B17 Power Other VSS AK30 Power Other VSS B20 Power Other VSS AK5 Power Other VSS B24 Power Other VSS AK7 Power Other VSS B5 Power Other VSS AL10 Power Other VSS B8 Power Other VSS AL13 Power Other VSS C10 Power Other VSS AL16 Power Other VSS C13 Power Other VSS AL17 Power Other VSS C16 Power Other VSS AL20 Power Other VSS C19 Power Other VSS AL23 Power Other VSS C22 Power Other VSS AL24 Power Other VSS C24 Power Other VSS AL27 Power Other VSS C4 Power Other VSS AL28 Power Other VSS C7 Power Other VSS AL3 Power Other VSS D12 Power Other VSS AL7 Power Other VSS D15 Power Other VSS AM1 Power Other VSS D18 Power Other VSS AM10 Power Other VSS D21 Power Other VSS AM13 Power Other VSS D24 Power Other VSS AM16 Power Other VSS D3 Power Other VSS AM17 Power Other VSS D5 Power Other VSS AM20 Power Other VSS D6 Power Other VSS AM23 Power Other VSS D9 Power Other 53 Land Listing and Signal Descriptions 54 Table 4 1 Alphabetical Land Assignments intal Table 4 1 Alphabetical Land Assignments Land Name SC EE Direction Land Name bana i Direction VSS E11 Power Other VSS H9 Power Other VSS E14 Power Other VSS J4 Power Other VSS E17 Power Other VSS J7 Power Other VSS ES Power Other
21. B3 Common Clock Input IMPSEL F6 Power Other Input RS1 F5 Common Clock Input INIT P3 Asynch GTL Input RS2 A3 Common Clock Input ITP_CLKO AK3 TAP Input RSP HA Common Clock Input ITP_CLK1 AJ3 TAP Input SKTOCC AE8 Power Other Output LINTO K1 Asynch GTL Input SMI P2 Asynch GTL Input LINT1 L1 Asynch GTL Input STPCLK M3 Asynch GTL Input LL_IDO V2 Power Other Output TCK AE TAP Input LL_ID1 AA2 Power Other Output TDI AD1 TAP Input LOCK C3 Common Clock Input Output TDO AF1 TAP Output MCERR AB3 Common Clock Input Output TESTHIO F26 Power Other Input MSIDO Wi Power Other Input TESTHI1 W3 Power Other Input MSID1 Vi Power Other Input TESTHI2 F25 Power Other Input Output or TESTHI3 G25 Power Other Input PROCHOT AL2 Asynch GTL nput Output TESTHI4 G27 Power Other Input PWRGOOD N1 Power Other Input TESTHI5 G26 Power Other Input REQO K4 Source Synch Input Output TESTHI6 G24 Power Other Input REQ1 J5 Source Synch Input Output TESTHI7 F24 Power Other Input REQ2 M6 Source Synch Input Output TESTHI8 G3 Power Other Input REQ3 K6 Source Synch Input Output TESTHI9 G4 Power Other Input REQ4 J6 Source Synch Input Output TESTHI10 H5 Power Other Input RESERVED A20 TESTHI11 P1 Power Other Input RESERVED AC4 TESTHI12 w2 Power Other Input RESERVED AE4 TESTHI13 L2 Asynch GTL Input RESERVED AE6 THERMDA AL1 Power Other RESERVED AH2 THERMDC AK1 Power Other RESERVED C9 THERMTRIP M2 Asynch GTL Output
22. E ima kad oi el PRE CS ze jee sjedi S S e letlslelzi a oO 5 CO Datasheet 37 Package Mechanical Specifications n A Figure 3 4 Processor Package Drawing 3 a gt uv DWG NO 28306 SHT 3 REV 2 lt L 6 eu mE j ois gS soje z Nees ee 000000000 z O00000000 1 Jo O00000000 900000000 o0000000o la 9200000009 000000000 BOS Q00000000 i 000000000 mara Ee 000000000 900000000 gt ss SS me 000000000 ___ 3 ae 0000000990 F 000000000 E 33 27 000000000 S a SZ 0000000090 000000000 S25 s 000000000 O00000000 EE 000000000 2 3 000000000 ao e OOOO Lelelelelelelelelelslelslelelele le elelelelelelelelelslelslelslel 2 oovdooo0o000000000090000000009000000o au OOO00000000000000Q0000000000 ben na 252 z Ere S zz G 25 ze D z gt k CH CH S l o eS a CO 38 Datasheet 3 3 Table 3 1 3 4 Table 3 2 Datasheet Package Mechanical Specifications Processor Component Keep Out Zones The processor may contain components on the substrate that define component keep out zone requirements A thermal and mechanical solution design must not intrude into the required keep out zones Decoupling capacitors are typically mounted to either the topside or land side of the package substrate See Figure 3
23. Power Cable Connector Pin Signal Straight square pin 4 pin terminal housing with 1 GND polarizing ribs and friction locking ramp S GE 0 100 pitch 0 025 square pin width i 4 CONTROL Match with straight pin friction lock header on mainboard Table 8 1 Fan Heatsink Power and Signal Specifications Description Min Typ Max Unit Notes 12 V 12 volt fan power supply 10 2 12 13 8 V IC Peak Fan current draw 1 5 A Fan start up current draw 1 0 2 0 A Fan start up current draw maximum duration 1 0 Second _ _ pulses per fan SENSE SENSE frequency 2 revelution 1 CONTROL 21 25 28 kHz 2 3 NOTES 1 Baseboard should pull this pin up to 5 V with a resistor 2 Open Drain Type Pulse Width Modulated 3 Fan will have a pull up resistor to 4 75 V maximum 5 25 V 100 Datasheet intel Balanced Technology Extended BTX Type I Boxed Processor Specifications Figure 8 5 Balanced Technology Extended BTX Mainboard Power Header Placement 8 3 8 3 1 Datasheet hatched area ra oe ro OH e B 288 Rear Panel I O Example PCI Express 6 35 0 13 Geo Connectors 0 250 0 005 J 0 000 w X 266 70 0 25 1 i igi 10 500 0 010
24. Static and Transient Tolerance for 775_VR_CONFIG_05B Pentium D Processor 23 2 6 VCC Overshoot Specifications eek kaaa 25 2 f FSB Signal GroupS 2 2e 00 na gia snake snake gege daa dai aba a aj Ee 27 2 8 Signal CharacteristiCs ebote add dtd eda dk dk iti 28 2 9 Signal Reference Voltages aaa aaa aaa aaa 28 2 10BSEL 2 0 and VID 5 0 Signal Group DC Specifications eek 29 2 11 GTL Signal Group DC Specification ek 29 2 12PWRGOOD Input and TAP Signal Group DC Specifications aka 30 2 13GTL Asynchronous Signal Group DC Specifications 0 eee 30 2 14VTTPWRGD DC Specifications ooo kakaa kaan 31 2 15BOOTSELECT and MSID 1 0 DC Specifications ave aaa 31 2 16GTL Bus Voltage Definitions sooo adenin a ponad dlana da added na 31 2 17 Core Frequency to FSB Multiplier Configuration 0 aaa 32 2 18BSEL 2 0 Frequency Table for BCLK 1 0 aaa aka kaaa aaa 33 3 1 Processor Loading Specifications ae aka 39 3 2 Package Handling Guidelines A 39 3 3 Processor MaterialS 32 2000 evacuees goa R ka died dA ja dia dia dini 40 4 1 Alphabetical Land Assignment aan 46 4 2 Numerical Land Assignments ionann niaaa AAEE ENTANA ARANE AREARE TAA 56 4 3 Signal Description E 66 5 1 Processor Thermal Specifications aaa 76 5 2 Thermal Profile for the Pentium D Processor with DDT 77 5 3 Thermal Profile for the Pentium D Processor with DD 78 5 4 Thermal Diode Parameters 60a aaaaaaaan
25. The boxed processor will ship with a component thermal solution Refer to Chapter 7 for details on the boxed processor Thermal Specifications To allow for the optimal operation and long term reliability of Intel processor based systems the system processor thermal solution should be designed such that the processor remains within the minimum and maximum case temperature T specifications when operating at or below the Thermal Design Power TDP value listed per frequency in Table 5 1 Thermal solutions not designed to provide this level of thermal capability may affect the long term reliability of the processor and system For more details on thermal solution design refer to the appropriate processor thermal design guidelines The Pentium D processor has a methodology for managing processor temperatures that is intended to support acoustic noise reduction through fan speed control Selection of the appropriate fan speed will be based on the temperature reported by the processor s Thermal Diode If the diode temperature is greater than or equal to TCoNTROL gt then the processor case temperature must remain at or below the temperature as specified by the thermal profile If the diode temperature is less than TCONTROL gt then the case temperature is permitted to exceed the thermal profile but the diode temperature must remain at or below TConTROL Systems that implement fan speed control must be designed to take these conditions into account S
26. Unit Notes Vu Input Low Voltage 0 0 GTLREF 0 10 Vry V 23 Vu Input High Voltage GTLREF 0 10 Mr Vit V 945 Vou Output High Voltage N A Var V 3 5 l t Output Low Current N A Ver 20 Der in A ON MIN d Input Leakage Current N A 200 HA S Output Leakage BR 6 lio Current N A 200 yA Ron Buffer On Resistance 8 12 Q NOTES Ts Unless otherwise noted all specifications in this table apply to all processor frequencies 2 Vis defined as the voltage range at a receiving agent that will be interpreted as a logical low value 3 The Vy referred to in these specifications is the instantaneous Vyr 4 ViHis defined as the voltage range at a receiving agent that will be interpreted as a logical high value 5 Vu and Voy may experience excursions above Ver 6 Leakage to Vgg with land held at Ver Datasheet 29 Electrical Specifications n 2 Table 2 12 PWRGOOD Input and TAP Signal Group DC Specifications Symbol Parameter Min Max Unit Notes 2 Vis Input Hysteresis 200 350 mV 3 Input low to high Vu e Se 0 5 Vir Viys min 0 5 er Moss Man V S Input high to low Vr ge voltage 0 5 Vrr Nues max 0 5 Var Nues wl V S Von Output High Voltage N A Viz V 4 Lu Output Low Current 45 mA S li Input Leakage Current 200 uA g Output Leakage _ 6 ko Current 200 pA Ron Buffer On Resistance 7 12 Q NOTES Unless otherwise noted all specifications in t
27. a locked sequence of transactions LOCK is asserted from the beginning of LOCK Input the first transaction to the end of the last transaction Output When the priority agent asserts BPRI to arbitrate for ownership of the processor FSB it will wait until it observes LOCK de asserted This enables symmetric agents to retain ownership of the processor FSB throughout the bus locked operation and ensure the atomicity of lock 70 Datasheet Land Listing and Signal Descriptions Table 4 3 Signal Description Sheet 6 of 8 Datasheet Name Type Description MCERR Input Output MCERR Machine Check Error is asserted to indicate an unrecoverable error without a bus protocol violation It may be driven by all processor FSB agents MCERR assertion conditions are configurable at a system level Assertion options are defined by the following options Enabled or disabled e Asserted if configured for internal errors along with IERR e Asserted if configured by the request initiator of a bus transaction after it observes an error e Asserted by any bus agent when it observes an error in a bus transaction For more details regarding machine check architecture refer to the A 32 Software Developer s Manual Volume 3 System Programming Guide MSID 1 0 Input MSIDO is used to indicate to the processor whether the platform supports processors with the Platform Requirement Bit PRB se
28. attached hardware for the clip design and is provided only as a mechanical representation Datasheet intel Boxed Processor Specifications Figure 7 4 Overall View Space Requirements for the Boxed Processor 7 1 2 7 1 3 7 2 7 2 1 Datasheet Boxed Processor Fan Heatsink Weight The boxed processor fan heatsink will not weigh more than 550 grams See Chapter 5 and the Intel Pentium D Processor and Intel Pentium Processor Extreme Edition 840 Thermal and Mechanical Design Guidelines for details on the processor weight and heatsink requirements Boxed Processor Retention Mechanism and Heatsink Attach Clip Assembly The boxed processor thermal solution requires a heatsink attach clip assembly to secure the processor and fan heatsink in the baseboard socket The boxed processor will ship with the heatsink attach clip assembly Electrical Requirements Fan Heatsink Power Supply The boxed processor s fan heatsink requires a 12 V power supply An attached fan power cable will be shipped with the boxed processor to draw power from a power header on the baseboard The power cable connector and pinout are shown in Figure 7 5 Baseboards must provide a matched power header to support the boxed processor Table 7 1 contains specifications for the input and output signals at the fan heatsink connector The fan heatsink outputs a SENSE signal that is an open collector output that pulses at a rate of 2 pulses per
29. fan revolution A baseboard pull up resistor provides Voy to match the system board mounted fan speed monitor requirements if applicable Use of the SENSE signal is optional If the SENSE signal is not used pin 3 of the connector should be tied to GND 91 Boxed Processor Specifications 92 in The fan heatsink receives a PWM signal from the motherboard from the 4th pin of the connector labeled as CONTROL The boxed processor s fan heatsink requires a constant 12 V supplied to pin 2 and does not support variable voltage control or 3 pin PWM control The power header on the baseboard must be positioned to allow the fan heatsink power cable to reach it The power header identification and location should be documented in the platform documentation or on the system board itself Figure 7 6 shows the location of the fan power connector relative to the processor socket The baseboard power header should be positioned within 110 mm 4 33 inches from the center of the processor socket Figure 7 5 Boxed Processor Fan Heatsink Power Cable Connector Description Table 7 1 cree Pin Signal GND 12 V SENSE CONTROL FON LO TL EEEE 1234 Straight square pin 4 pin terminal housing with polarizing ribs and friction locking ramp 0 100 pitch 0 025 square pin width Match with straight pin friction lock header on mainboard Boxed_Proc_PwrCable Fan Heatsink Power and Signal Specificati
30. grams See Chapter 3 and the Intel Pentium D Processor and Intel Pentium Processor Extreme Edition 840 Thermal and Mechanical Design Guidelines for details on the processor weight and heatsink requirements 98 Datasheet intel 8 1 3 Balanced Technology Extended BTX Type I Boxed Processor Specifications Boxed Processor Support and Retention Module SRM The boxed processor TMA requires a SRM assembly to attach directly to the chassis base pan and to secure the processor and TMA in the mainboard socket The boxed processor TMA will ship with the heatsink attach clip assembly duct and screws for attachment The SRM must be supplied by the chassis hardware vendor See the Support and Retention Module SRM External Design Requirements Document Balanced Technology Extended BTX System Design Guide and the Intel Pentium D Processor and Intel Pentium Processor Extreme Edition 840 Thermal and Mechanical Design Guidelines for more detailed design information regarding the support and retention module Figure 8 3 Assembly Stack Including the Support and Retention Module 8 2 8 2 1 Datasheet Thermal Module Assembly __ j Heatsink amp Fan f Clip Structural Duct ru Motherboard Electrical Requirements Fan Heatsink Power Supply The boxed processor s fan heatsink requires a 12 V power supply A fan power cable will be shipped with the boxed processor to draw power from a
31. high temperature situation exists i e TCC is active the clocks will be modulated by alternately turning the clocks off and on at a duty cycle specific to the processor typically 30 50 Clocks often will not be off for more than 3 0 microseconds when the TCC is active Cycle times are processor speed dependent and will decrease as processor core frequencies increase A small amount of hysteresis has been included to prevent rapid active inactive transitions of the TCC when the processor temperature is near its maximum operating temperature Once the temperature has dropped below the maximum operating temperature and the hysteresis timer has expired the TCC goes inactive and clock modulation ceases 79 m Thermal Specifications and Design Considerations ntal a 5 2 2 5 2 3 80 With a properly designed and characterized thermal solution it is anticipated that the TCC would only be activated for very short periods of time when running the most power intensive applications The processor performance impact due to these brief periods of TCC activation is expected to be so minor that it would be immeasurable An under designed thermal solution that is not able to prevent excessive activation of the TCC in the anticipated ambient environment may cause a noticeable performance loss and in some cases may result in a Te that exceeds the specified maximum temperature and may affect the long term reliability of the processor In addition a t
32. output only the FORCEPR signal can be driven from an external source to activate the TCC This will prevent one core from asserting the PROCHOT signal of the other core and unnecessarily activating the TCC of that core Refer to Section 5 2 4 for details on the FORCEPR signal Datasheet 5 2 4 Datasheet Thermal Specifications and Design Considerations As a bi directional signal PROCHOT allows for some protection of various components from over temperature situations The PROCHOT signal is bi directional in that it can either signal when the processor either core has reached its maximum operating temperature or be driven from an external source to activate the TCC The ability to activate the TCC via PROCHOT can provide a means for thermal protection of system components Bi directional PROCHOT if enabled can allow VR thermal designs to target maximum sustained current instead of maximum current Systems should still provide proper cooling for the VR and rely on bi directional PROCHOT only as a backup in case of system cooling failure The system thermal design should allow the power delivery circuitry to operate within its temperature specification even while the processor is operating at its Thermal Design Power With a properly designed and characterized thermal solution it is anticipated that bi directional PROCHOT would only be asserted for very short periods of time when running the most power intensive applications An un
33. over a short range of internal chassis temperatures This allows the processor fan to operate at a lower speed and noise level while internal chassis temperatures are low If internal chassis temperature increases beyond a lower set point the fan speed will rise linearly with the internal temperature until the higher set point is reached At that point the fan speed is at its maximum As fan speed increases so does fan noise levels Systems should be designed to provide adequate air around the boxed processor fan heatsink that remains cooler then lower set point These set points represented in Figure 7 9 and Table 7 2 can vary by a few degrees from fan heatsink to fan heatsink The internal chassis temperature should be kept below 39 C Meeting the processor s temperature specification see Chapter 5 is the responsibility of the system integrator The motherboard must supply a constant 12 V to the processor s power header to ensure proper operation of the variable speed fan for the boxed processor Refer to Table 7 1 for the specific requirements Figure 7 9 Boxed Processor Fan Heatsink Set Points Higher Set Point Highest Noise Level Increasing Fan Speed amp Noise Lower Set Point Lowest Noise Level X Y Z Internal Chassis Temperature Degrees C Table 7 2 Fan Heatsink Power and Signal Specifications Boxed Processor Fan Heatsink Set Point C Boxed Processor Fan Speed Notes When the
34. power header on the baseboard The power cable connector and pinout are shown in Figure 8 4 Baseboards must provide a matched power header to support the boxed processor Table 8 1 contains specifications for the input and output signals at the fan heatsink connector The fan heatsink outputs a SENSE signal that is an open collector output that pulses at a rate of 2 pulses per fan revolution A baseboard pull up resistor provides Voy to match the system board mounted fan speed monitor requirements if applicable Use of the SENSE signal is optional If the SENSE signal is not used pin 3 of the connector should be tied to GND 99 m Balanced Technology Extended BTX Type I Boxed Processor Specifications ntal a The fan heatsink receives a PWM signal from the motherboard from the an pin of the connector labeled as CONTROL Note The boxed processor s fan heatsink requires a constant 12 V supplied to pin 2 and does not support variable voltage control or 3 pin PWM control The power header on the baseboard must be positioned to allow the fan heatsink power cable to reach it The power header identification and location should be documented in the platform documentation or on the system board itself Figure 8 5 shows the location of the fan power connector relative to the processor socket The baseboard power header should be positioned within 4 33 inches from the center of the processor socket Figure 8 4 Boxed Processor Fan Heatsink
35. processor These dimensions include Package reference with tolerances total height length width etc IHS parallelism and tilt Land dimensions e Top side and back side component keep out dimensions Reference datums All drawing dimensions are in mm in Guidelines on potential IHS flatness variation with socket load plate actuation and installation of the cooling solution is available in the processor Thermal Mechanical Design Guidelines 35 Package Mechanical Specifications Figure 3 2 Processor Package Drawing 1 401 133HS SNIAYWO WIS LON OG 1 2 31VOS Ta z 90 820 2 ag AJY YIGNON ONIAVYG 3009 39v9_ Jas OTI Il Te 3ziva A8 03JAOYddY NOILO3FOUd 319NV QYIHL KEN Yy 11Y130 ELITI aLva Aa 0349349 SOF weit NIET EEEN e T avaf wm ad enen Yy WG 3937109 HOISSIN 007 o m in3niuvd3a ziva ka aan9 s30 T lee Yy EIS 620 ES DR H 2 In z HGM u 3 90 Ej re JLSVA LI I u 2 200 11000 189 z 5 3 q 2 r800 eoz og EES H JLYYLSANS JOVNOVA ra 999 DLSVE 96 91 H E Er o LNWIV3S SHI e CHE 1800 rel 4 x E S HEES z l
36. selected by a 133 MHz BCLK 1 0 frequency Datasheet intel Electrical Specifications Table 2 18 BSEL 2 0 Frequency Table for BCLK 1 0 2 7 3 Datasheet BSEL2 BSEL1 BSELO FSB Frequency L L L RESERVED L L H 133 MHz L H H RESERVED L H L 200 MHz H L L RESERVED H L H RESERVED H H H RESERVED H H L RESERVED Phase Lock Loop PLL and Filter Vcca and VecIOPLL are power sources required by the PLL clock generators for the Pentium D processor Since these PLLs are analog in nature they require quiet power supplies for minimum jitter Jitter is detrimental to the system it degrades external I O timings as well as internal core timings i e maximum frequency To prevent this degradation these supplies must be low pass filtered from V py The AC low pass requirements with input at Var are as follows e lt 0 2 dB gain in pass band e lt 0 5 dB attenuation in pass band lt 1 Hz e gt 34 dB attenuation from 1 MHz to op MHz e gt 28 dB attenuation from op MHz to core frequency The filter requirements are illustrated in Figure 2 4 33 Electrical Specifications 34 Figure 2 4 Phase Lock Loop PLL Filter Requirements 0 2 dB 0dB 0 5 dB Forbidden Zone 28 dB 34 dB DC 1Hz peak 1MHz 66MHz Passband High Frequency Band fcore NOTES 1 Diagram not to scale 2 No specifications for frequencies beyond fcore core frequency 3 fpeak
37. the VID signals is the reference VR output voltage to be delivered to the processor VCC lands Section 2 5 3 for Vcc overshoot specifications Refer to Table 2 10 for the DC specifications for these signals A minimum voltage for each processor frequency is provided in Table 2 3 Individual processor VID values may be calibrated during manufacturing such that two devices at the same core speed may have different default VID settings This is reflected by the VID Range values provided in Table 2 3 The Pentium D processor uses six voltage identification signals VID 5 0 to support automatic selection of power supply voltages Table 2 1 specifies the voltage level corresponding to the state of VID 5 0 A 1 in this table refers to a high voltage level and a 0 refers to low voltage level If the processor socket is empty VID 5 0 x11111 or the voltage regulation circuit cannot supply the voltage that is requested it must disable itself See the Voltage Regulator Down VRD 10 1 Design Guide For Desktop LGA775 Socket for more details The processor provides the ability to operate while transitioning to an adjacent VID and its associated processor core voltage Vcc This will represent a DC shift in the load line It should be noted that a low to high or high to low voltage state change may result in as many VID transitions as necessary to reach the target core voltage Transitions above the specified VID are not permitted Minimum and
38. the pending break event functionality including the identification of support of the feature and enable disable information refer to volume 3 of the Intel Architecture Software Developer s Manual and the Intel Processor Identification and the CPUID Instruction application note FORCEPR Input The FORCEPR input can be used by the platform to force the processor both cores to activate the Thermal Control Circuit TCC The TCC will remain active until the system de asserts FORCEPR GTLREF 1 0 Input GTLREF 1 0 determine the signal reference level for GTL input signals GTLREF 1 0 are used by the GTL receivers to determine if a signal is a logical 0 or logical 1 GTLREF_SEL Output GTLREF_SEL is used to select the appropriate chipset GTLREF voltage HIT HITM Input Output Input Output HIT Snoop Hit and HITM Hit Modified convey transaction snoop operation results Any FSB agent may assert both HIT and HITM together to indicate that it requires a snoop stall which can be continued by reasserting HIT and HITM together Datasheet 69 Land Listing and Signal Descriptions n Table 4 3 Signal Description Sheet 5 of 8 Name Type Description IERR Internal Error is asserted by a processor as the result of an internal error Assertion of IERR is usually accompanied by a SHUTDOWN transaction on the processor FSB This transaction may optionally be convert
39. the system integrator 101 Balanced Technology Extended BTX Type I Boxed Processor Specifications n 8 3 2 Variable Speed Fan If the boxed processor fan heatsink 4 pin connector is connected to a 3 pin motherboard header it will operate as follows The boxed processor fan will operate at different speeds over a short range of temperatures based on a thermistor located in the fan hub area This allows the boxed processor fan to operate at a lower speed and noise level while thermistor temperatures are low If the thermistor senses a temperatures increase beyond a lower set point the fan speed will rise linearly with the temperature until the higher set point is reached At that point the fan speed is at its maximum As fan speed increases so does fan noise levels These set points are represented in Figure 8 6 and Table 8 2 The internal chassis temperature should be kept below 38 C Meeting the processor s temperature specification see Chapter 5 is the responsibility of the system integrator Note The motherboard must supply a constant 12 V to the processor s power header to ensure proper operation of the variable speed fan for the boxed processor refer to Table 8 1 for the specific requirements Figure 8 6 Boxed Processor TMA Set Points Higher Set Point Highest Noise Level Increasing Fan Speed amp Noise Lower Set Point Lowest Noise Level X Y Z Internal Chassis Temperature Degrees C
40. these signals Request Signals Subphase 1 Subphase 2 A 35 24 APO AP1 A 23 3 AP1 APO REQ 4 0 AP1 APO BCLK 1 0 Input The differential pair BCLK Bus Clock determines the FSB frequency All processor FSB agents must receive these signals to drive their outputs and latch their inputs All external timing parameters are specified with respect to the rising edge of BCLKO crossing VcRoss Datasheet Land Listing and Signal Descriptions Table 4 3 Signal Description Sheet 2 of 8 Datasheet Name Type Description BINIT Input Output BINIT Bus Initialization may be observed and driven by all processor FSB agents and if used must connect the appropriate pins lands of all such agents If the BINIT driver is enabled during power on configuration BINIT is asserted to signal any bus condition that prevents reliable future operation If BINIT observation is enabled during power on configuration and BINIT is sampled asserted symmetric agents reset their bus LOCK activity and bus request arbitration state machines The bus agents do not reset their IOQ and transaction tracking state machines upon observation of BINIT activation Once the BINIT assertion has been observed the bus agents will re arbitrate for the FSB and attempt completion of their bus queue and IOQ entries If BINIT observation is disabled during power on configuration a central agent may handle an asserti
41. to in these specifications refers to instantaneous Vyr All outputs are open drain The maximum output current is based on maximum current handling capability of the buffer and is not specified into the test load Leakage to Vss with land held at Var 10 Leakage to Vrr with land held at 300 mV ONO o 30 Datasheet Table 2 14 VTTPWRGD DC Specifications Electrical Specifications Symbol Parameter Min Typ Max Unit Notes Vu Input Low Voltage 0 3 V Vin Input High Voltage 0 9 V Table 2 15 BOOTSELECT and MSID 1 0 DC Specifications Symbol Parameter Min Typ Max Unit Notes Vit Input Low Voltage 0 24 V 1 Vin Input High Voltage 0 96 V 5 NOTES 1 These parameters are not tested and are based on design simulations 2 6 3 1 GTL Front Side Bus Specifications In most cases termination resistors are not required as these are integrated into the processor silicon See Table 2 8 for details on which GTL signals do not include on die termination Valid high and low levels are determined by the input buffers by comparing with a reference voltage called GTLREF Table 2 16 lists the GTLREF specifications The GTL reference voltage GTLREF must be generated on the motherboard using high precision voltage divider circuits Table 2 16 GTL Bus Voltage Definitions Symbol Parameter Min Typ Max Uni
42. 0 and 830 supporting Enhanced Intel Speedstep technology allows tradeoffs to be made between performance and power consumption The Pentium D processor also includes the Execute Disable Bit capability This feature combined with a supported operating system allows memory to be marked as executable or non executable Datasheet 9 m Contents ntel R 10 Datasheet Note Datasheet Iniroduction Introduction The Intel Pentium D processor extends Intel s Desktop dual core product line The Pentium D processor uses Flip Chip Land Grid Array FC LGA4 package technology and plugs into a 775 land LGA socket referred to as the LGA775 socket The Pentium D processor like the Intel Pentium 4 processor in the 775 land package utilizes the Intel N etBurst microarchitecture and maintains the tradition of compatibility with IA 32 software The Intel Pentium D processor supports Intel Extended Memory 64 Technology Intel EM64T as an enhancement to Intel s A 32 architecture on server and workstation platforms This enhancement enables the processor to execute operating systems and applications written to take advantage of Intel EM64T Further details on the 64 bit extension architecture and programming model can be found in the Intel 64 bit Extension Technology Software Developer s Guide at http developer intel com technology 64bitextensions In this document the Pentium D processor 800 sequence is also refer
43. 00 1 s00 7 2 800 02 0 7 ed a ait SHI 100 800 7 Tor 2 H EIN i gn qa E 1 027 JIWS TL80 S NEIEN z 2 z z Ire ISEE z e apj 1 amp Lg Ss 5 AJIA LNOUS Yy JOLENE Kb KR DO NIE BE END Sp L H ng ai tery Cre ti jl END Er L H DI NIM SLNIWNWOD SIHDN1 T0BHA S SYJLINITTIN MILA WOLLOB MBIA dOL e 3 3 NOILO3S 2 Datasheet 36 Package Mechanical Specifications Figure 3 3 Processor Package Drawing 2 o ro 4 e NO c28306 T al 2 lt Sp 6 Le o oli GE E Gs s Bol eg fee s zs g a BS las LS of SS NI a S m N an 3 S gt E Kt be be Ieleleelelee eelere le lee Le ele Le Lee Le ee e ee e eieie OOO00O00O0OO00000000000000000000000000 2 OQ00000000 oo00000000 a 00000000 900000000 2 000000000 000000000 Ss Q00000000 900000000 pa O00000000 000000000 a Q00000000 000000000 000000000 ____ 00000000 000000000 0900000000 e Q00000000 000000000 b OO0Q0000000 i O0Q0000000 a SE O0Q0Q000000 900000000 Q00000000 000000000 Q00000000 o i 0900000000 00000000 000000000 oooo000000000000000000o00000000009o enle e Jo IS gt IS OOOOOOOOOOOOOOVOVOVOVOVOVOVOVOOOO Eg jesleslesl slssles
44. 000 0 019 0 038 5 0 007 0 026 0 045 10 0 013 0 033 0 053 15 0 020 0 040 0 060 20 0 026 0 047 0 067 25 0 033 0 053 0 074 30 0 039 0 060 0 082 35 0 046 0 067 0 089 40 0 052 0 074 0 096 45 0 059 0 081 0 103 50 0 065 0 088 0 111 55 0 072 0 095 0 118 60 0 078 0 102 0 125 65 0 085 0 108 0 132 70 0 091 0 115 0 140 75 0 098 0 122 0 147 80 0 101 0 126 0 151 85 0 111 0 136 0 161 90 0 117 0 143 0 169 95 0 124 0 150 0 176 100 0 130 0 157 0 183 NOTES 1 The loadline specification includes both static and transient limits except for overshoot allowed as shown in Section 2 5 3 2 This table is intended to aid in reading discrete points on Figure 2 1 3 The loadlines specify voltage limits at the die measured at the VCC_SENSE and VSS_SENSE lands Voltage regulation feedback for voltage regulator circuits must be taken from processor VCC and VSS lands Refer to the Voltage Regulator Down VRD 10 1 Design Guide For Desktop LGA775 Socket for socket loadline guide lines and VR implementation details Datasheet 21 Electrical Specifications n Figure 2 1 Vcc Static and Transient Tolerance for 775_VR_CONFIG_05A Pentium D Processor Icc A VID 0 000 VID 0 013 5 VID 0 025 5 VID 0 038 Vec Maximum VID 0 050 Ba VID 0 063 4 VID 0 075 4 VID 0 088 Vcc Typical Vec V VID 0 100 4 VID 0 113 4 2 VID 0 125 4 Vec Minimum VID 0 138
45. 2 and Figure 3 3 for keep out zones The location and quantity of package capacitors may change due to manufacturing efficiencies but will remain within the component keep in Package Loading Specifications Table 3 1 provides dynamic and static load specifications for the processor package These mechanical maximum load limits should not be exceeded during heatsink assembly shipping conditions or standard use condition Also any mechanical system or component testing should not exceed the maximum limits The processor package substrate should not be used as a mechanical reference or load bearing surface for thermal and mechanical solution The minimum loading specification must be maintained by any thermal and mechanical solutions Processor Loading Specifications Parameter Minimum Maximum Notes Static 80 N 18 lbf 311 N 70 lbf 123 Dynamic m 756 N 170 lbf 1 3 4 NOTES These specifications apply to uniform compressive loading in a direction normal to the processor IHS 2 This is the maximum force that can be applied by a heatsink retention clip The clip must also provide the minimum spec ified load on the processor package 3 These specifications are based on limited testing for design characterization Loading limits are for the package only and does not include the limits of the processor socket 4 Dynamic loading is defined as the sum of the load on the package from a 1 Ib heatsink mass accelerati
46. 23 RESERVED H5 TESTHI10 Power Other Input F24 TESTHI7 Power Other Input H6 VSS Power Other F25 TESTHI2 Power Other Input H7 VSS Power Other F26 TESTHIO Power Other Input H8 VSS Power Other F27 VTT_SEL Power Other Output H9 VSS Power Other F28 BCLKO Clock Input H10 VSS Power Other F29 RESERVED H11 VSS Power Other G1 VSS Power Other H12 VSS Power Other G2 COMP2 Power Other Input H13 VSS Power Other G3 TESTHI8 Power Other Input H14 VSS Power Other G4 TESTHI9 Power Other Input H15 DP1 Common Clock Input Output G5 FC7 Source Synch Output H16 DP2 Common Clock Input Output G6 RESERVED H17 VSS Power Other G7 DEFER Common Clock Input H18 VSS Power Other G8 BPRI Common Clock Input H19 VSS Power Other G9 D16 Source Synch Input Output H20 VSS Power Other G10 RESERVED H21 VSS Power Other G11 DBI1 Source Synch Input Output H22 VSS Power Other G12 DSTBN1 Source Synch Input Output H23 VSS Power Other G13 D27 Source Synch Input Output H24 VSS Power Other G14 D29 Source Synch Input Output H25 VSS Power Other G15 D31 Source Synch Input Output H26 VSS Power Other G16 D32 Source Synch Input Output H27 VSS Power Other G17 D36 Source Synch Input Output H28 VSS Power Other G18 D35 Source Synch Input Output H29 GTLREF_SEL Power Other Output G19 DSTBP2 Source Synch Input Output H30 BSEL1 Power Other Output G20 DSTBN2 Source Synch Input Output Ji VTT OUT LEET Power Other Output G21 D44 Source Synch Input Output J2 FC3 Power Other In
47. 4 0 150 0 176 100 0 130 0 157 0 183 105 0 137 0 163 0 190 110 0 143 0 170 0 198 115 0 150 0 177 0 205 120 0 156 0 184 0 212 125 0 163 0 191 0 219 NOTES 1 2 This table is intended to aid in reading discrete points on Figure 2 2 3 The loadlines specify voltage limits at the die measured at the VCC_SENSE and VSS_SENSE lands Volt age regulation feedback for voltage regulator circuits must be taken from processor VCC and VSS lands Refer to the Voltage Regulator Down VRD 10 1 Design Guide For Desktop LGA775 Socket for socket loadline guidelines and VR implementation details Datasheet The loadline specification includes both static and transient limits except for overshoot allowed as shown in Section 2 5 3 23 Electrical Specifications in Figure 2 2 Vcc Static and Transient Tolerance for 775_VR_CONFIG_05B Pentium D Processor VID 0 000 VID 0 025 VID 0 050 VID 0 075 VID 0 100 Vec V VID 0 125 VID 0 150 VID 0 175 VID 0 200 VID 0 225 Icc A 20 30 40 50 60 70 80 90 100 110 120 Vcc Maximum Vcc Typical Vec Minimum ye 24 Datasheet Intel 2 5 3 Electrical Specifications Vcc Overshoot Specification The Pentium D processor can tolerate short transient overshoot events where V cc exceeds the VID voltage when transitioning from a high to low current load condition This overshoot cannot exceed VID Vos m
48. 4 VCC Power Other AF25 VSS Power Other AE15 VCC Power Other AF26 VSS Power Other AE16 VSS Power Other AF27 VSS Power Other AE17 VSS Power Other AF28 VSS Power Other AE18 VCC Power Other AF29 VSS Power Other AE19 VCC Power Other AF30 VSS Power Other AE20 VSS Power Other AG1 TRST TAP Input AE21 VCC Power Other AG2 BPM3 Common Clock Input Output AE22 VCC Power Other AG3 BPM5 Common Clock Input Output AE23 VCC Power Other AG4 A30 Source Synch Input Output AE24 VSS Power Other AG5 A31 Source Synch Input Output AE25 VSS Power Other AG6 A29 Source Synch Input Output AE26 VSS Power Other AG7 VSS Power Other AE27 VSS Power Other AG8 VCC Power Other AE28 VSS Power Other AG9 VCC Power Other Datasheet Datasheet Table 4 2 Numerical Land Assignment Land Listing and Signal Descriptions Table 4 2 Numerical Land Assignment capa Land Name Reng Direction ia Land Name Weg Cie Direction AG10 VSS Power Other AH21 VCC Power Other AG11 VCC Power Other AH22 VCC Power Other AG12 VCC Power Other AH23 VSS Power Other AG13 VSS Power Other AH24 VSS Power Other AG14 VCC Power Other AH25 VCC Power Other AG15 VCC Power Other AH26 VCC Power Other AG16 VSS Power Other AH27 VCC Power Other AG17 VSS Power Other AH28 VCC Power Other AG18 VCC Power Other AH29 VCC Power Other AG19 VCC Power Other A
49. 9 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 131211 10 9 8 E 54321 gt gt AM AM AL AL AK AK AJ AJ AH AH AG AG gt gt mm Address Common Clock Async Socket LGA775 Quadrants Top View woomnorexrZzzvaiHC lt S lt Z8BBSKE3 woomnorexrgzvnaic lt g lt Z2338 T v D 30 29 28 27 26 25 24 23 22 21 20 1918 17 16 1514131211109 8 7654321 V_ Clocks Data 42 Datasheet m Land Listing and Signal Descriptions ntal a 4 Land Listing and Signal Descriptions This chapter provides the processor land assignment and signal descriptions 4 1 Processor Land Assignments This section contains the land listings for the Intel Pentium D processor The landout footprint is shown in Figure 4 1 and Figure 4 2 These figures represent the landout arranged by land number and they show the physical location of each signal on the package land array top view Table 4 1 is a listing of all processor lands ordered alphabetically by land signal name Table 4 2 is also a listing of all processor lands the ordering is by land number 43 Datasheet Land Listing and Signal Descriptions g g D I n e Figure 4 1 Landout Diagram Top View Left Side 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 AN VCC VCC VSS VSS VCC VCC VSS VSS VCC VCC VSS VCC VCC VSS VSS VCC AM VCC VCC VSS VSS VCC VCC VSS VSS VCC VCC VSS VCC VCC VSS VSS VCC AL VCC VCC VSS VSS VCC VCC V
50. Descriptions 64 Table 4 2 Numerical Land Assignment intel Table 4 2 Numerical Land Assignment Land Signal Buffer i i Land Signal Buffer i i Land Name Type Direction Land Name Type Direction AK2 VSS Power Other AL13 VSS Power Other AK3 ITP_CLKO TAP Input AL14 VCC Power Other AK4 VIDA Power Other Output AL15 VCC Power Other AK5 VSS Power Other AL16 VSS Power Other AK6 FORCEPR Asynch GTL Input AL17 VSS Power Other AK7 VSS Power Other AL18 VCC Power Other AK8 VCC Power Other AL19 VCC Power Other AK9 VCC Power Other AL20 VSS Power Other AK10 VSS Power Other AL21 VCC Power Other AK11 VCC Power Other AL22 VCC Power Other AK12 VCC Power Other AL23 VSS Power Other AK13 VSS Power Other AL24 VSS Power Other AK14 VCC Power Other AL25 VCC Power Other AK15 VCC Power Other AL26 VCC Power Other AK16 VSS Power Other AL27 VSS Power Other AK17 VSS Power Other AL28 VSS Power Other AK18 VCC Power Other AL29 VCC Power Other AK19 VCC Power Other AL30 VCC Power Other AK20 VSS Power Other AM1 VSS Power Other AK21 VCC Power Other AM2 VIDO Power Other Output AK22 Vcc Power Other AM3 VID2 Power Other Output AK23 VSS Power Other AM4 VSS Power Other AK24 VSS Power Other AM5 FC11 Power Other Output AK25 VCC Power Other AM6 VTTPWRGD Power Other Input AK26 VCC Power Other AM7 FC12 P
51. H30 VCC Power Other AG20 VSS Power Other AJ1 BPM1 Common Clock Input Output AG21 VCC Power Other AJ2 BPMO Common Clock Input Output AG22 VCC Power Other AJ3 ITP_CLK1 TAP Input AG23 VSS Power Other AJ4 VSS Power Other AG24 VSS Power Other AJ5 A34 Source Synch Input Output AG25 VCC Power Other AJ6 A35 Source Synch Input Output AG26 VCC Power Other AJ7 VSS Power Other AG27 VCC Power Other AJ8 VCC Power Other AG28 VCC Power Other AJ9 VCC Power Other AG29 VCC Power Other AJ10 VSS Power Other AG30 VCC Power Other AJ11 VCC Power Other AH1 VSS Power Other AJ12 VCC Power Other AH2 RESERVED AJ13 VSS Power Other AH3 VSS Power Other AJ14 VCC Power Other AH4 A32 Source Synch Input Output AJ15 VCC Power Other AH5 A33 Source Synch Input Output AJ16 VSS Power Other AH6 VSS Power Other AJ17 VSS Power Other AH7 VSS Power Other AJ18 VCC Power Other AH8 VCC Power Other AJ19 VCC Power Other AH9 VCC Power Other AJ20 VSS Power Other AH10 VSS Power Other AJ21 VCC Power Other AH11 VCC Power Other AJ22 VCC Power Other AH12 VCC Power Other AJ23 VSS Power Other AH13 VSS Power Other AJ24 VSS Power Other AH14 VCC Power Other AJ25 VCC Power Other AH15 VCC Power Other AJ26 VCC Power Other AH16 VSS Power Other AJ27 VSS Power Other AH17 VSS Power Other AJ28 VSS Power Other AH18 VCC Power Other AJ29 VSS Power Other AH19 VCC Power Other AJ30 VSS Power Other AH20 VSS Power Other AK1 THERMDC Power Other 63 Land Listing and Signal
52. I1 0 frequency The processor bus ratio multiplier will be set at its default ratio during manufacturing The Pentium D processor uses a differential clocking implementation Table 2 17 Core Frequency to FSB Multiplier Configuration 2 7 2 32 oo Sd seal Kata noe ne neue I esti Notes 2 533 MHz FSB 800 MHz FSB 1 14 RESERVED 2 80 GHz 1 15 RESERVED 3 GHz 1 16 RESERVED 3 20 GHz 1 17 RESERVED RESERVED 1 18 RESERVED RESERVED 1 19 RESERVED RESERVED 1 20 2 66 GHz RESERVED 1 21 RESERVED RESERVED NOTES 1 Individual processors operate only at or below the rated frequency 2 Listed frequencies are not necessarily committed production frequencies FSB Frequency Select Signals Upon power up the front side bus frequency is set to the maximum supported by the individual processor BSEL 2 0 are open drain outputs that must be pulled up to Vyr and are used to select the front side bus frequency Refer to Table 2 10 for DC specifications Table 2 18 defines the possible combinations of the signals and the frequency associated with each combination The frequency is determined by the processor s chipset and clock synthesizer Individual processors will only operate at their specified front side bus clock frequency The Pentium D processor 840 830 and 820 operate at 800 MHz FSB frequency selected by a 200 MHz BCLK 1 0 frequency The Pentium processor 805 operates at 533 MHz FSB frequency
53. Input Output R27 VSS Power Other V6 VSS Power Other R28 VSS Power Other V7 VSS Power Other R29 VSS Power Other V8 VCC Power Other R30 VSS Power Other V23 VSS Power Other Ti COMP1 Power Other Input V24 VSS Power Other T2 FC4 Power Other Input V25 VSS Power Other T3 VSS Power Other V26 VSS Power Other T4 A11 Source Synch Input Output V27 VSS Power Other T5 A9 amp Source Synch Input Output V28 VSS Power Other T6 VSS Power Other V29 VSS Power Other T7 VSS Power Other V30 VSS Power Other T8 VCC Power Other Wi MSIDO Power Other Input Datasheet Datasheet Table 4 2 Numerical Land Assignment Land Listing and Signal Descriptions Table 4 2 Numerical Land Assignment i Land Name si jn Direction wie Land Name Weg Cie Direction W2 TESTHI12 Power Other Input AA25 VSS Power Other W3 TESTHI1 Power Other Input AA26 VSS Power Other WA VSS Power Other AA27 VSS Power Other WE A16 Source Synch Input Output AA28 VSS Power Other W6 A18 Source Synch Input Output AA29 VSS Power Other W7 VSS Power Other AA30 VSS Power Other W8 VCC Power Other AB1 VSS Power Other W23 VCC Power Other AB2 IERR Asynch GTL Output W24 VCC Power Other AB3 MCERR Common Clock Input Output W25 VCC Power Other AB4 A26 Source Synch Input Output W26 VCC Power Other AB5 A24 Source Synch Input Output W27 VCC P
54. Inte Pentium D Processor and Intel Pentium Processor Extreme Edition 840 Thermal and Mechanical Design Guidelines http developer intel com design pentiumXE designex 306830 htm Inte Pentium Processor Extreme Edition and Intel Pentium D Processor Specification Update http developer intel com design PentiumXE specupdt 306832 htm Voltage Regulator Down VRD 10 1 Design Guide For Desktop LGA775 Socket http developer intel com design Pentium4 guides 302356 htm LGA775 Socket Mechanical Design Guide http developer intel com design pentium4 guides 302666 htm Inte Architecture Software Developer s Manual Volume 1 Basic Architecture Document 253665 Volume 2A Instruction Set Reference A M Document 253666 Volume 2B Instruction Set Reference N Z Document 253667 Volume 3 System Programming Guide Document 253668 http developer intel com design pentium4 manuals index_new htm 13 Iniroduction 14 Datasheet 2 1 2 2 2 2 1 2 2 2 Datasheet Electrical Specifications Electrical Specifications This chapter describes the electrical characteristics of the processor interfaces and signals DC electrical characteristics are provided Power and Ground Lands The Intel Pentium D processor has 226 VCC power and 273 VSS ground inputs for on chip power distribution All VCC lands must be connected to the processor power plane while all VSS
55. L2 G30 Power Other Output A18 W6 Source Synch Input Output COMPO A13 Power Other Input A19 Y6 Source Synch Input Output COMP1 T1 Power Other Input A20 Y4 Source Synch Input Output COMP2 G2 Power Other Input A20M K3 Asynch GTL Input COMP3 R1 Power Other Input A21 AA4 Source Synch Input Output DO B4 Source Synch Input Output A22 AD6 Source Synch Input Output D1 C5 Source Synch Input Output A23 AAR Source Synch Input Output D2 A4 Source Synch Input Output A24 AB5 Source Synch Input Output D3 C6 Source Synch Input Output A25 AC5 Source Synch Input Output D4 A5 Source Synch Input Output A26 AB4 Source Synch Input Output D5 B6 Source Synch Input Output A27 AF5 Source Synch Input Output D6 B7 Source Synch Input Output A28 AF4 Source Synch Input Output D7 A7 Source Synch Input Output A29 AG6 Source Synch Input Output D8 A10 Source Synch Input Output A30 AG4 Source Synch Input Output D9 A11 Source Synch Input Output A31 AG5 Source Synch Input Output D10 B10 Source Synch Input Output A32 AH4 Source Synch Input Output D11 C11 Source Synch Input Output A33 AH5 Source Synch Input Output D12 D8 Source Synch Input Output A34 AIS Source Synch Input Output D13 B12 Source Synch Input Output A35 AJ6 Source Synch Input Output D14 C12 Source Synch Input Output ADS D2 Common Clock Input Output D15 D11 Sour
56. LT Snoop State HALT Snoop State Grant Snoop State The processor will respond to snoop transactions on the FSB while in Stop Grant state or in HALT Power Down state During a snoop transaction the processor enters the HALT Grant Snoop state The processor will stay in this state until the snoop on the FSB has been serviced whether by the processor or another agent on the FSB After the snoop is serviced the processor will return to the Stop Grant state or HALT Power Down state as appropriate Enhanced HALT Snoop State The Enhanced HALT Snoop State is the default Snoop State when the Enhanced HALT state is enabled via the BIOS The processor will remain in the lower bus ratio and VID operating point of the Enhanced HALT state While in the Enhanced HALT Snoop State snoops are handled the same way as in the HALT Snoop State After the snoop is serviced the processor will return to the Enhanced HALT Power Down state Enhanced Intel SpeedStep Technology Enhanced Intel SpeedStep Technology enables the processor to switch between frequency and voltage points which may result in platform power savings To support this technology the system must support dynamic VID transitions Switching between voltage frequency states is software controlled Not all processors are capable of supporting Enhanced Intel SpeedStep Technology More details on which processor frequencies support this feature will be provided in future releases of the Intel
57. PM3 TRST vec vss vec vcc vss vec vcc vss vss AO A28 vss BPM4 TDO vec vss veo vec vss vcc sktocc vss RSVD VSS rsvp Fo vss TCK VCC VSS A22 ADSTB1 VSS BINIT BPM2 TDI VCC VSS VSS A25 RSVD VSS DBR TMS VCC VSS A17 A24 A26 MCERR IERR VSS VTT_OUT_ VCC VSS VSS A23 A21 VSS LL_ID1 RIGHT BOOT vec vss A19 VSS A20 Fo vss klen VCC VSS A18 A16 VSS TESTHI1 TESTHI12 MSIDO VCC VSS VSS A14 A15 VSS LL_IDO MSID1 VCC VSS A10 A12 A13 AP1 APO VSS vec vss VSS An Au vss FC4 COMP vec vss ADSTBo VSS ABE jedi TI vss COMP3 VCC VSS A4 RSVD VSS INIT SMI TESTHI11 VCC VSS VSS RSVD RSVD VSS IGNNE PWRGOOD THER vec vss REQ2 AS ave stecik voan VSS VCC VSS VSS A3 A6 VSS TESTHI13 LINT1 VCC VSS REQ3 VSS REQO A20M VSS LINTO vec veo vec vcc vec vec voc vss REQ4 REQ1 vss FO22 FC3 VSS VSS VSS VSS VSS VSS VSS VSS VSS TESTHI10 RSP VSS GTLREF1 GTLREFO D29 D27 DSTBN1 DBI1 RSVD D16 BPRI DEFER RSVD FC7 TESTHI9 TESTHI8 COMP2 VSS D28 VSS D24 D23 VSS D18 D17 VSS IMPSEL RS1 VSS BRO FC5 VSS D26 DSTBP1 VSS D21 D19 VSS RSVD RSVD FC20 HITM TRDY VSS RSVD D25 VSS D15 D22 VSS D12 D20 VSS VSS HIT VSS ADS RSVD D52 VSS D14 D11 VSS RSVD DSTBNO VSS D3 Di VSS LOCK BNR DRDY vss poi man vss Dog DSTBPO vss D6 Deg VSS Dog neng DBSY VSS D50 compo vss po past vss mmm Go VSS Du D2 RS2 vss 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Datasheet AN
58. RESERVED D1 TMS AC1 TAP Input RESERVED D14 TRDY E3 Common Clock Input RESERVED D16 TRST AG TAP Input RESERVED E23 VCC AA8 Power Other RESERVED E6 VCC AB8 Power Other RESERVED E7 VCC AC23 Power Other RESERVED F23 VCC AC24 Power Other RESERVED F29 VCC AC25 Power Other RESERVED G10 VCC AC26 Power Other RESERVED N4 Datasheet Datasheet Table 4 1 Alphabetical Land Assignments Land Listing and Signal Descriptions Table 4 1 Alphabetical Land Assignments Land Name xa a sj Direction Land Name s Wel Direction VCC AC27 Power Other VCC AG21 Power Other VCC AC28 Power Other VCC AG22 Power Other VCC AC29 Power Other VCC AG25 Power Other VCC AC30 Power Other VCC AG26 Power Other VCC AC8 Power Other VCC AG27 Power Other VCC AD23 Power Other VCC AG28 Power Other VCC AD24 Power Other VCC AG29 Power Other VCC AD25 Power Other VCC AG30 Power Other VCC AD26 Power Other VCC AG8 Power Other VCC AD27 Power Other VCC AG9 Power Other VCC AD28 Power Other VCC AH11 Power Other VCC AD29 Power Other VCC AH12 Power Other VCC AD30 Power Other VCC AH14 Power Other VCC AD8 Power Other VCC AH15 Power Other VCC AE11 Power Other VCC AH18 Power Other VCC AE12 Power Other VCC AH19 Power Other VCC AE14 Power Other VCC AH21
59. SS VSS VCC VCC VSS VCC VCC VSS VSS VCC AK VSS VSS VSS VSS VCC VCC VSS VSS VCC VCC VSS VCC VCC VSS VSS VCC AJ VSS VSS VSS VSS VCC VCC VSS VSS VCC VCC VSS VCC VCC VSS VSS VCC AH VCC VCC VCC VCC VCC VCC VSS VSS VCC VCC VSS VCC VCC VSS VSS VCC AG VCC VCC VCC VCC VCC VCC VSS VSS VCC VCC VSS VCC VCC VSS VSS VCC AF VSS VSS VSS VSS VSS VSS VSS VSS VCC Vec VSS VCC VCC VSS VSS VCC AE VSS VSS VSS VSS VSS VSS VSS VCC VCC VCC VSS VCC VCC VSS VSS VCC AD VCC VCC VCC VCC VCC VCC VCC VCC AC VCC VCC VCC VCC VCC VCC VCC VCC AB VSS VSS VSS VSS VSS VSS VSS VSS AA VSS VSS VSS VSS VSS VSS VSS VSS Y VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC W v VSS VSS VSS VSS VSS VSS VSS VSS U VCC VCC VCC VCC VCC VCC VCC VCC T VCC VCC VCC VCC VCC VCC VCC VCC R VSS VSS VSS VSS VSS VSS VSS VSS P VSS VSS VSS VSS VSS VSS VSS VSS N VCC VCC VCC VCC VCC VCC VCC VCC M VCC VCC VCC VCC VCC VCC VCC VCC L VSS VSS VSS VSS VSS VSS VSS VSS K VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC DP3 DPO VCC H pseLi ua vss vss vss vss vss vss vss vss vss vss vss vss DP2 pP1 G BSEL2 BSELO BCLK1 TESTHI4 TESTHIS TESTHI TESTHI6 RESET D47 D44 DSTBN2 DSTBP2 D35 D36 Da2 D31 F RS
60. Specifications Most processor Front Side Bus signals use Gunning Transceiver Logic GTL signaling technology This technology provides improved noise margins and reduced ringing through low voltage swings and controlled edge rates Platforms implement a termination voltage level for GTL signals defined as Vyr Because platforms implement separate power planes for each processor and chipset separate Vcc and Vrr supplies are necessary This configuration allows for improved noise tolerance as processor frequency increases Speed enhancements to data and address busses have caused signal integrity considerations and platform design methods to become even more critical than with previous processor families The GTL inputs require a reference voltage GTLREF that is used by the receivers to determine if a signal is a logical 0 or a logical 1 GILREF must be generated on the motherboard see Table 2 16 for GTLREF specifications Termination resistors Rrr for GTL signals are provided on the processor silicon and are terminated to Nr Intel chipsets will also provide on die termination thus eliminating the need to terminate the bus on the motherboard for most GTL signals FSB Signal Groups The FSB signals have been combined into groups by buffer type GTL input signals have differential input buffers that use GTLREF as a reference level In this document the term GTL Input refers to the GTL input group as well as the GTL I O group when r
61. VD BCLKO vTT_SEL TESTHIO TESTHI2 TESTHI7 RSVD vss D43 pas vss pse Daz vss D30 E vss vss vss vss vss Fcio rsvp ase Daz vss pang pag vss paa t D33 D vit wr vrr vr vr vt vss vocetL pas vss pasu peiz vss Dan Rsvp vss c wt vr vr vr vrr vt vss Ke vss D58 pp vss D54 DSTBP3 VSS D51 vrr vit vrt vrt vrr vm vss vssa pes pse vss pen psz vss D55 D53 A vrr vr vr wt wr vm vss veca pezg vss Rsvp pe1 vss Dse DSTBN3 VSS 30 29 28 27 26 25 24 3 om a 20 19 18 17 16 15 44 Datasheet in Figure 4 2 Landout Diagram Top View Right Side Land Listing and Signal Descriptions 14 13 12 11 10 9 8 7 6 5 4 3 2 1 vss_MB_ vcc_mB_ vss_ vcc_ vcc vss vcc vec vss vee vo y Bode a ONAK BEGULATIOK SENSE ees VSS VSS VCC VSS VCC VCC VSS VCC VCC FC12 VTTPWRGD FC11 VSS VID2 VIDO VSS VCC VSS VCC VCC VSS VCC VCC VSS VID3 VID1 VID5 VSS PROCHOT THERMDA VCC VSS VCC VCC VSS VCC VCC VSS FORCEPR VSS VID4 ITP_CLKO VSS THERMDC VCC VSS VCC VCC VSS VCC VCC VSS A35 A34 VSS ITP_CLK1 BPMO BPM1 vec vss vec vcc vss vec vec vss VSS A334 A32 VSS RSVD vss vec vss vec vcc vss vec voc vss A29 A31 A30 BPM5 B
62. VSS K2 Power Other VSS E20 Power Other VSS K5 Power Other VSS E25 Power Other VSS K7 Power Other VSS E26 Power Other VSS L23 Power Other VSS E27 Power Other VSS L24 Power Other VSS E28 Power Other VSS L25 Power Other VSS E29 Power Other VSS L26 Power Other VSS E8 Power Other VSS L27 Power Other VSS F10 Power Other VSS L28 Power Other VSS F13 Power Other VSS L29 Power Other VSS F16 Power Other VSS L3 Power Other VSS F19 Power Other VSS L30 Power Other VSS F22 Power Other VSS L6 Power Other VSS F4 Power Other VSS L7 Power Other VSS F7 Power Other VSS M1 Power Other VSS G1 Power Other VSS M7 Power Other VSS H10 Power Other VSS N3 Power Other VSS H11 Power Other VSS N6 Power Other VSS H12 Power Other VSS N7 Power Other VSS H13 Power Other VSS P23 Power Other VSS H14 Power Other VSS P24 Power Other VSS H17 Power Other VSS P25 Power Other VSS H18 Power Other VSS P26 Power Other VSS H19 Power Other VSS P27 Power Other VSS H20 Power Other VSS P28 Power Other VSS H21 Power Other VSS P29 Power Other VSS H22 Power Other VSS P30 Power Other VSS H23 Power Other VSS P4 Power Other VSS H24 Power Other VSS P7 Power Other VSS H25 Power Other VSS R2 Power Other VSS H26 Power Other VSS R23 Power Other VSS H27 Power Other VSS R24 Power Other VSS H28 Power Other VSS R25 Power Other VSS H3 Power Other VSS R26 Power Other VSS H6 Power Other VSS R27 Power Other VSS H7 Power Othe
63. a system designed for 775_VR_CONFIG_05B processors The power and Ico will be incrementally higher in this configuration due to the improved loadline and resulting higher Voc loc_max is based on the Veg Maximum loadline Refer to Figure 2 1 and Figure 2 2 for details lcc RESET is specified while PWRGOOD and RESET are active The current specified is also for AutoHALT State Icc Stop Grant and Ico Enhanced Halt are specified at Voc max These parameters are based on design characterization and are not tested The maximum instantaneous current the processor will draw while the thermal control circuit is active as indicated by the assertion of PROCHOT is the same as the maximum Icc for the processor Vtr must be provided via a separate voltage source and not be connected to Vcc This specification is measured at the land Baseboard bandwidth is limited to 20 MHz This is maximum total current drawn from V 7 plane by only the processor This specification does not include the current coming from Rrr through the signal line Refer to the Voltage Regulator Down VRD 10 1 Design Guide For Desktop LGA775 Socket to determine the total Irr drawn by the system Table 2 4 Vcc Static and Transient Tolerance for 775_VR_CONFIG_05A Pentium D Processor Icc A Voltage Deviation from VID Setting il gt 3 Maximum Voltage Typical Voltage Minimum Voltage 1 30 mQ 1 38 mQ 1 45 MQ 0 0
64. aaaadannnna ida kaa nakana ddadda dai 82 5 5 Thermal Diode Interface aa aaa aaa kaan 83 6 1 Power On Configuration Option Gionas aka 85 7 1 Fan Heatsink Power and Signal Specifications aeee vka 92 7 2 Fan Heatsink Power and Signal Specifications eena 95 8 1 Fan Heatsink Power and Signal Specifications kakaa 100 8 2 Balanced Technology Extended BTX Type Boxed Processor TMA Set Points for Ee e le EE 102 6 Datasheet m ntel Contents Revision History Revision SS Number Description Date 001 Initial release May 2005 Added Balanced Technology Extended BTX Type Boxed Processor 002 Specifications chapter October 2005 pe Added Intel Pentium D processor 805 specifications Fabnidw 2006 Updated THERMTRIP signal description in Table 4 3 Datasheet Contents i ntel R 8 Datasheet j ntel e Contents Intel Pentium D Processor 800 Sequence Features Available at 3 20 GHz 3 GHz 2 80 GHz and Optimized for 32 bit applications running on 2 66 MHz advanced 32 bit operating systems e Enhanced Intel Speedstep Technology Pentium Two 16 KB Level data caches D processor 840 ne 830 only Two MB Advanced Transfer Caches on die Supports Intel Extended Memory 64 Technology full speed Level 2 L2 cache with 8 way Intel EM64T associativity and Error Correcting Code ECC e Supports Execute Disable Bit capability 144 Streaming SIMD Extensions 2 SSE2
65. adi E Gad 82 6 TEE 85 6 1 Power On Configuration Options aaa 85 6 2 Clock Control and Low Power Gates ea 85 6 2 1 E en EE 86 6 2 2 HALT and Enhanced HALT Powerdown States aaaakaa akan 86 6 2 3 StOp Grant State ance secret dino raaa tesko asa pan tog 87 6 2 4 Enhanced HALT Snoop or HALT Snoop State Grant Snoop State ee 88 6 2 5 Enhanced Intel SpeedStep Technology eeevaaaaaanaaa aaa aaa 88 7 Boxed Processor Specifications eee aaa 89 7 1 Mechanical Specifications 0 aaa 90 7 1 1 Boxed Processor Cooling Solution Dimensions aaa kakaa 90 7 1 2 Boxed Processor Fan Heatsink Weight 91 7 1 3 Boxed Processor Retention Mechanism and Heatsink Attach Clip Assemblly 91 7 2 Electrical Requirements aaa aaa ana 91 7 2 1 Fan Heatsink Power Supply aka aaa 91 7 3 Thermal Specifications 0aaaa aaa 93 7 3 1 Boxed Processor Cooling Heouiremerts kaaa kakaa aaa 93 7 3 2 Variable Speed Fan 95 8 Balanced Technology Extended BTX Type Boxed Processor Gpecfcations 97 8 1 Mechanical Specifications eee aaa 98 8 1 1 Cooling Solution Dimensions aaa aaa 98 8 1 2 Boxed Processor Fan Heatsink Weight 98 8 1 3 Boxed Processor Support and Retention Module GM 99 8 2 Electrical Requirements add i dak dg dei alabat oda dvd dotad 99 8 2 1 Fan Heatsink Power Supply aaa aaa 99 ech Thermal Specifications eege i Ken a e aa E ad ete 101 8 3 1 Boxed Proc
66. age level for the processor VTTPWRGD Input The processor requires this input to determine that the V voltages are stable and within specification 73 Land Listing and Signal Descriptions 74 Datasheet 5 1 Note 5 1 1 Datasheet Thermal Specifications and Design Considerations Thermal Specifications and Design Considerations Processor Thermal Specifications The Intel Pentium D processor requires a thermal solution to maintain temperatures within operating limits as set forth in Section 5 1 1 Any attempt to operate the processor outside these operating limits may result in permanent damage to the processor and potentially other components within the system As processor technology changes thermal management becomes increasingly crucial when building computer systems Maintaining the proper thermal environment is key to reliable long term system operation A complete thermal solution includes both component and system level thermal management features Component level thermal solutions can include active or passive heatsinks attached to the processor Integrated Heat Spreader IHS Typical system level thermal solutions may consist of system fans combined with ducting and venting For more information on designing a component level thermal solution refer to the Intel Pentium D Processor and Intel Pentium Processor Extreme Edition 840 Thermal and Mechanical Design Guidelines
67. ammed from 12 5 on 87 5 off to 87 5 on 12 5 off in 12 5 increments On Demand mode may be used in conjunction with the Thermal Monitor If the system tries to enable On Demand mode at the same time the TCC is engaged the factory configured duty cycle of the TCC will override the duty cycle selected by the On Demand mode PROCHOT Signal An external signal PROCHOT processor hot is asserted when the processor core temperature has reached its maximum operating temperature If the Thermal Monitor is enabled note that the Thermal Monitor must be enabled for the processor to be operating within specification the TCC will be active when PROCHOT is asserted The processor can be configured to generate an interrupt upon the assertion or de assertion of PROCHOT Refer to the Intel Architecture Software Developer s Manuals for specific register and programming details For the Pentium D processor PROCHOT can be configured via BIOS as an output or a bi directional signal As an output PROCHOT Processor Hot will go active when the processor temperature monitoring sensor detects that one or both cores has reached its maximum safe operating temperature This indicates that the processor Thermal Control Circuit TCC has been activated if enabled As an input assertion of PROCHOT by the system will activate the TCC if enabled for both cores The TCC will remain active until the system de asserts PROCHOT If PROCHOT is configured as an
68. and LGA socket Integrated heat spreader IHS A component of the processor package used to enhance the thermal performance of the package Component thermal solutions interface with the processor at the IHS surface Retention mechanism RM Since the LGA775 socket does not include any mechanical features for heatsink attach a retention mechanism is required Component thermal solutions should attach to the processor via a retention mechanism that is independent of the socket Storage conditions Refers to a non operational state The processor may be installed in a platform in a tray or loose Processors may be sealed in packaging or exposed to free air Under these conditions processor lands should not be connected to any supply voltages have any I Os biased or receive any clocks Upon exposure to free air i e unsealed packaging or a device removed from packaging material the processor must be handled in accordance with moisture sensitivity labeling MSL as indicated on the packaging material e Functional operation Refers to normal operating conditions in which all processor specifications including DC AC system bus signal quality mechanical and thermal are satisfied Datasheet 1 2 References Iniroduction Material and concepts available in the following documents may be beneficial when reading this document Table 1 1 References Datasheet Document Document Location
69. ax Vos max iS the maximum allowable overshoot voltage The time duration of the overshoot event must not exceed Tos max Tos max is the maximum allowable time duration above VID These specifications apply to the processor die voltage as measured across the VCC_SENSE and VSS_SENSE lands Table 2 6 Vcc Overshoot Specifications Symbol Parameter Min Typ Max Unit Figure Vos max Magnitude of Vcc overshoot above VID 0 050 V 2 3 Tos max Time duration of Vcc overshoot above VID 25 us 2 3 Figure 2 3 Vcc Overshoot Example Waveform Datasheet Example Overshoot Waveform VID 0 050 2 o D G gt Time Ts Overshoot time above VID Vos Overshoot above VID NOTES 1 Vog is measured overshoot voltage 2 Tos is measured time duration above VID 25 m Electrical Specifications ntal a 2 5 4 2 6 2 6 1 26 Die Voltage Validation Overshoot events on the processor must meet the specifications in Table 2 6 when measured across the VCC_SENSE and VSS_SENSE lands Overshoot events that are lt 10 ns in duration may be ignored These measurements of processor die level overshoot must be taken with a bandwidth limited oscilloscope set to a greater than or equal to 100 MHz bandwidth limit Refer to the Voltage Regulator Down VRD 10 1 Design Guide For Desktop LGA775 Socket for additional voltage regulator validation details Signaling
70. ble 4 2 Numerical Land Assignment intel Table 4 2 Numerical Land Assignment a Land Name da i Direction san Land Name oi a rap Direction AD4 VSS Power Other AE29 VSS Power Other AD5 ADSTB1 Source Synch Input Output AE30 VSS Power Other AD6 A22 Source Synch Input Output AF1 TDO TAP Output AD7 VSS Power Other AF2 BPM4 Common Clock Input Output AD8 VCC Power Other AF3 VSS Power Other AD23 VCC Power Other AF4 A28 Source Synch Input Output AD24 VCC Power Other AF5 A27 Source Synch Input Output AD25 VCC Power Other AF6 VSS Power Other AD26 VCC Power Other AF7 VSS Power Other AD27 VCC Power Other AF8 VCC Power Other AD28 VCC Power Other AF9 VCC Power Other AD29 VCC Power Other AF10 VSS Power Other AD30 VCC Power Other AF11 VCC Power Other AE TCK TAP Input AF12 VCC Power Other AE2 VSS Power Other AF13 VSS Power Other AE3 FC18 Power Other Input AF14 VCC Power Other AE4 RESERVED AF15 VCC Power Other AE5 VSS Power Other AF16 VSS Power Other AE6 RESERVED AF17 VSS Power Other AE7 VSS Power Other AF18 VCC Power Other AE8 SKTOCC Power Other Output AF19 VCC Power Other AE9 VCC Power Other AF20 VSS Power Other AE10 VSS Power Other AF21 VCC Power Other AE11 VCC Power Other AF22 VCC Power Other AE12 VCC Power Other AF23 VSS Power Other AE13 VSS Power Other AF24 VSS Power Other AE1
71. bus Asserting A20M emulates the 8086 processor s address wrap around at the 1 MB boundary Assertion of A20M is only supported in real mode A20M is an asynchronous signal However to ensure recognition of this signal following an Input Output write instruction it must be valid along with the TRDY assertion of the corresponding Input Output write bus transaction ADS Input Output ADS Address Strobe is asserted to indicate the validity of the transaction address on the A 35 3 and REQ 4 0 signals All bus agents observe the ADS activation to begin parity checking protocol checking address decode internal snoop or deferred reply ID match operations associated with the new transaction ADSTBI1 0 Input Output Address strobes are used to latch A 35 3 and REQ 4 0 on their rising and falling edges Strobes are associated with signals as shown below Signals Associated Strobe REQ 4 0 A 16 3 ADSTBO A 35 17 ADSTB1 AP 1 0 Input Output AP 1 0 Address Parity are driven by the request initiator along with ADS A 35 3 and the transaction type on the REQ 4 0 A correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low This allows parity to be high when all the covered signals are high AP 1 0 should connect the appropriate pins lands of all processor FSB agents The following table defines the coverage model of
72. ce Synch Input Output ADSTBO R6 Source Synch Input Output D16 G9 Source Synch Input Output ADSTB1 AD5 Source Synch Input Output D17 F8 Source Synch Input Output APO U2 Common Clock Input Output D18 F9 Source Synch Input Output AP1 U3 Common Clock Input Output D19 E9 Source Synch Input Output BCLKO F28 Clock Input D20 D7 Source Synch Input Output Datasheet Datasheet Table 4 1 Alphabetical Land Land Listing and Signal Descriptions Table 4 1 Alphabetical Land Assignments Assignments Land Name ld Direction Land Name am EEN Direction D21 E10 Source Synch Input Output D61 A19 Source Synch Input Output D22 D10 Source Synch Input Output D62 A22 Source Synch Input Output D23 F11 Source Synch Input Output D63 B22 Source Synch Input Output D24 F12 Source Synch Input Output DBIO A8 Source Synch Input Output D25 D13 Source Synch Input Output DBI1 G11 Source Synch Input Output D26 E13 Source Synch Input Output DBI2 D19 Source Synch Input Output D27 G13 Source Synch Input Output DBI3 C20 Source Synch Input Output D28 F14 Source Synch Input Output DBR AC2 Power Other Output D29 G14 Source Synch Input Output DBSY B2 Common Clock Input Output D30 F15 Sourc
73. condition limits it will either not function or its reliability will be severely degraded Although the processor contains protective circuitry to resist damage from static electric discharge precautions should always be taken to avoid high static voltages or electric fields Processor DC Absolute Maximum Ratings Symbol Parameter Min Max Unit Notes 2 Vec Core voltage with respect to Vss 0 3 1 55 V Vor See Se voltage with 0 3 1 55 v i Te Processor case temperature See Section 5 See Section 5 C TsTORAGE Processor storage temperature 40 85 C 3 4 NOTES 1 For functional operation all processor electrical signal quality mechanical and thermal specifications must be satisfied 2 Excessive overshoot or undershoot on any signal will likely result in permanent damage to the processor 3 Storage temperature is applicable to storage conditions only In this scenario the processor must not receive a clock and no lands can be connected to a voltage bias Storage within these limits will not affect the long term reliability of the device For functional operation refer to the processor case temperature specifications 4 This rating applies to the processor and does not include any tray or packaging DC Voltage and Current Specifications The processor DC specifications in this section are defined at the processor core silicon and not at the package lands unless noted otherwise See Cha
74. d with an unattached TMA Figure 8 2 shows a mechanical representation of the boxed Pentium D processor TMA The physical space requirements and dimensions for the boxed processor with assembled fan heatsink are shown Figure 8 2 Requirements for the Balanced Technology Extended BTX Type I Keep out Volumes 6 5 3 2 PRO CET Te_GRO 1 REVISION HISTORY THIS DRAWING CONTAINS INTEL CORPORATION CONFIDENTIAL INFORMATION IT IS DISCLOSED N CONFIDENCE AND ITS CONTENTS TONE REV DESCRIPTION DATE APPROVED MAY NOT BE DISCLOSED REPRODUCED DISPLAYED OR MODIFIED WITHOUT THE PRIOR WRITTEN CONSENT OF INTEL CORPORATION g INITIAL RELEASE 04 05 04 F F E E im SA D 1385 D 145 24 j 2X 2 5 5 7181 0481 Dar me C 50 09 46 04 C 1 9721 1 8131 2X 11 75 j a 4631 24 ma 862 11 74 462 a E UNLESS OTHERWISE SPECIFIED d DESIGNED BY DATE DEPARTHENT o 2200 Nd COLLEGE BLVD 7 mA a A ALL UNTOLERANCED LINEAR D JONES Od4 05 04 Paene OaS ao 1 aian So La 111 76 pa 6 95 THIRD ANGLE PROJECTION LGA775 VOLUMETRIC BTX A 4 4001 214 16 13 S OA A 0 659 FA KE Am BER Gi DEL Ke re onu SEE NOTES SEE NOTES ome 0 5 DO WOT SCALE DRAWING GHEET oF 6 5 3 2 NOTE The diagram does not show the attached hardware for the clip design and is provided only as a mechanical representation 8 1 2 Boxed Processor Fan Heatsink Weight The boxed processor fan heatsink will not weigh more than 1290
75. der designed thermal solution that is not able to prevent excessive assertion of PROCHOT in the anticipated ambient environment may cause a noticeable performance loss Refer to the Voltage Regulator Down VRD 10 1 Design Guide for Desktop Socket 775 for details on implementing the bi directional PROCHOT feature Contact your Intel representative for further details and documentation FORCEPR Signal Pin The FORCEPR force power reduction input can be used by the platform to cause the processor both cores to activate the TCC If the Thermal Monitor is enabled the TCC will be activated upon the assertion of the FORCEPR signal The TCC will remain active until the system de asserts FORCEPR FORCEPR is an asynchronous input FORCEPR can be used to thermally protect other system components To use the VR as an example when the FORCEPR pin is asserted the TCC circuit in the processor both cores will activate reducing the current consumption of the processor and the corresponding temperature of the VR It should be noted that assertion of the FORCEPR does not automatically assert PROCHOT As mentioned previously the PROCHOT signal is asserted when a high temperature situation is detected A minimum pulse width of 500 us is recommend when the FORCEPR is asserted by the system Sustained activation of the FORCEPR pin may cause noticeable platform performance degradation One application is the thermal protection of voltage regulat
76. e 32 2 7 1 FSB Clock BCLK 1 0 and Processor Clocking aaa 32 2 7 2 FSB Frequency Select Signals AA 32 2 7 3 Phase Lock Loop PLL and Elter 33 3 Package Mechanical Specifications ee aaa 35 3 1 Package Mechanical Drawing aaa 35 3 2 Processor Component Keep Out Zones 39 3 3 Package Loading Specifications eee aaa 39 3 4 Package Handling Guidelnes kaaa kakaa 39 3 5 Package Insertion Specifications eee aaa 40 3 6 Processor Mass Specification eee aaa 40 3 Processor EE 40 38 Processor Mangen egener deeg eege eege A0 SH Processor Cand Coordinates ea EENS ENER edd KAES 42 4 Land Listing and Signal Descriptions eek aaa 43 41 Processor Land e lu 43 4 2 Alphabetical Signals Heterence aaa 66 5 Thermal Specifications and Design Considerations aaa aan 75 5 1 Processor Thermal Specifications eeeka kaaa 75 5 1 1 Thermal Specifications e aka 75 514 2 Thermal Metrology ereinen ddadda adna vata adja ddadda 79 Datasheet 3 Contents ntel m 5 2 Processor Thermal Features aaa ana 79 S21 Thermal MONItor sasa kacaa Dead Rees dake da had akad 79 5 2 2 On Demand Ne 80 5 2 3 PROCHOT Signal arteen naa sees vans tee dosade eda daa gadaba adna boa igda 80 5 2 4 FORGEPR Signal EIER sh aa din e ee divi 81 5 2 5 THERMTRIP Gional aaa aaa 82 5 2 6 TcoNTROL and Fan Speed Reduction aaa anna 82 b 2 7 Thermal Diode e a ii eegen atas aaa i dada
77. e Synch Input Output DEFER G7 _ Common Clock Input D31 G15 Source Synch Input Output DPO J16 Common Clock Input Output D32 G16 Source Synch Input Output DP1 H15 Common Clock Input Output D33 E15 Source Synch Input Output DP2 H16 Common Clock Input Output D34 E16 Source Synch Input Output DP3 J17 Common Clock Input Output D35 G18 Source Synch Input Output DRDY C1 Common Clock Input Output D36 G17 Source Synch Input Output DSTBNO C8 Source Synch Input Output D37 F17 Source Synch Input Output DSTBN1 G12 Source Synch Input Output D38 F18 Source Synch Input Output DSTBN2 G20 Source Synch Input Output D39 E18 Source Synch Input Output DSTBN3 A16 Source Synch Input Output D40 E19 Source Synch Input Output DSTBPO B9 Source Synch Input Output D41 F20 Source Synch Input Output DSTBP1 E12 Source Synch Input Output D42 E21 Source Synch Input Output DSTBP2 G19 Source Synch Input Output D43 F21 Source Synch Input Output DSTBP3 C17 Source Synch Input Output D44 G21 Source Synch Input Output FC3 J2 Power Other Input D45 E22 Source Synch Input Output FC4 T2 Power Other Input D46 D22 Source Synch Input Output FC5 F2 Common Clock Input D47 G22 Source Synch Input Output FC7 G5 Source Synch Output D48 D20 Source Synch Input Output FC10 E24 Power Other Input D49 D17 Source Synch Input Output FC11 AM5 Power Other Ou
78. eceiving Similarly GTL Output refers to the GIL output group as well as the GTL I O group when driving With the implementation of a source synchronous data bus comes the need to specify two sets of timing parameters One set is for common clock signals whose timings are specified with respect to rising edge of BCLKO ADS HIT HITM etc and the second set is for the source synchronous signals that are relative to their respective strobe lines data and address as well as rising edge of BCLKO Asynchronous signals are still present A20M IGNNE etc and can become active at any time during the clock cycle Table 2 7 identifies which signals are common clock source synchronous and asynchronous Datasheet Electrical Specifications Table 2 7 FSB Signal Groups Datasheet Signal Group Type Signals GTL Common Clock Input Synchronous to BCLK 1 0 BPRI DEFER RESET RS 2 0 RSP TRDY AP 1 0 ADS BINIT BNR BPM 5 0 BRO GTL Common Clock I O Synchronous to BCLK 1 0 DBSY DP 3 0 DRDY HIT HITM LOCK MCERR Signals Associated Strobe REQ 4 0 A 16 3 ADSTBO GTL Source Synchronous to assoc A 35 17 ADSTB1 Synchronous I O strobe D 15 0 DBIO DSTBPO DSTBNO D 31 16 DBI1 DSTBP1 DSTBN1 D 47 32 DBI2 DSTBP2 DSTBN2 D 63 48 DBI3 DSTBP3 DSTBN3 GTL Strobes Synchronous to BCLK 1 0 ADSTB 1 0 DSTBP 3 0 DSTBN 3 0 GTL Asy
79. ected through a resistor to ground Vss Unused outputs can be left unconnected however this may interfere with some test access port TAP functions complicate debug probing and prevent boundary scan testing A resistor must be used when tying bidirectional signals to power or ground When tying any signal to power or ground a resistor will also allow for system testability For unused GTL inputs or I O signals use pull up resistors of the same value as the on die termination resistors Rrr Refer to Table 2 16 for more details TAP GIL Asynchronous inputs and GTL Asynchronous outputs do not include on die termination Inputs and used outputs must be terminated on the system board Unused outputs may be terminated on the system board or left unconnected Note that leaving unused outputs unterminated may interfere with some TAP functions complicate debug probing and prevent boundary scan testing FCx signals are signals that are available for compatibility with other processors The TESTHI signals must be tied to the processor V rr using a matched resistor where a matched resistor has a resistance value within 20 of the impedance of the board transmission line traces For example if the trace impedance is 60 then a value between 48 Q and 72 Q is required The TESTHI signals may use individual pull up resistors or be grouped together as detailed below A matched resistor must be used for each group e TESTHI 1 0 e TESTHI 7 2
80. ed to an IERR Output external error signal e g NMI by system core logic The processor will keep IERR asserted until the assertion of RESET This signal does not have on die termination Refer to Section 2 4 for termination requirements IGNNE Ignore Numeric Error is asserted to force the processor to ignore a numeric error and continue to execute noncontrol floating point instructions If IGNNE is de asserted the processor generates an exception on a noncontrol floating point instruction if a previous floating point instruction caused an error IGNNE Input IGNNE has no effect when the NE bit in control register 0 CRO is set IGNNE is an asynchronous signal However to ensure recognition of this signal following an Input Output write instruction it must be valid along with the TRDY assertion of the corresponding Input Output write bus transaction IMPSEL input will determine whether the processor uses a 50 Q or 60 Q buffer IMPSEL Input This pin must be tied to GND on 50 Q platforms and left as NC on 60 Q platforms INIT Initialization when asserted resets integer registers inside the processor without affecting its internal caches or floating point registers The processor then begins execution at the power on Reset vector configured during power on configuration The processor continues to handle snoop INIT Input requests during INIT assertion INIT is an asynchronous signal and must connect the appropr
81. efer to the Voltage Regulator Down VRD 10 1 Design Guide for Desktop Socket 775 for more information The voltage supply for these signals must be valid before the VR can supply Vec to the processor Conversely the VR output must be disabled until the voltage supply for the VID signals becomes valid The VID signals are needed to support the processor voltage specification variations See Table 2 1 for definitions of these signals The VR must supply the voltage that is requested by the signals or disable itself VSS are the ground lands for the processor and should be connected to the system ground plane VSSA Input VSSA is the isolated ground for internal PLLs VSS_SENSE Output VSS_SENSE is an isolated low impedance connection to processor core Vgg It can be used to sense or measure ground near the silicon with little noise VSS_MB_ REGULATION Output This land is provided as a voltage regulator feedback sense point for Vss It is connected internally in the processor package to the sense point land V27 as described in the Voltage Regulator Down VRD 10 1 Design Guide for Desktop Socket 775 VTT Miscellaneous voltage supply VTT_OUT_LEFT VTT_OUT_RIGHT Output The VTT_OUT_LEFT and VTT_OUT_RIGHT signals are included to provide a voltage supply for some signals that require termination to Vrr on the motherboard VTT_SEL Output The VTT_SEL signal is used to select the correct Ver volt
82. en the system deasserts the STPCLK interrupt the processor will return execution to the HALT state While in HALT Power Down state the processor will process bus snoops Enhanced HALT Powerdown State Enhanced HALT is a low power state entered when all logical processors have executed the HALT or MWAIT instructions and Enhanced HALT has been enabled via the BIOS When one of the logical processors executes the HALT instruction that logical processor is halted however the other processor continues normal operation The processor will automatically transition to a lower frequency and voltage operating point before entering the Enhanced HALT state Note that the processor FSB frequency is not altered only the internal core frequency is changed When entering the low power state the processor will first switch to the lower bus ratio and then transition to the lower VID While in Enhanced HALT state the processor will process bus snoops The processor exits the Enhanced HALT state when a break event occurs When the processor exits the Enhanced HALT state it will first transition the VID to the original value and then change the bus ratio back to the original value Stop Grant State When the STPCLK signal is asserted the Stop Grant state of the processor is entered 20 bus clocks after the response phase of the processor issued Stop Grant Acknowledge special bus cycle Since the GTL signals receive power from the FSB these signals s
83. er Other AN4 VSS_SENSE Power Other Output AN22 VCC Power Other AN5 REE OMRON Power Other Output ANE Ke DEE AN24 VSS Power Other AN6 REGULATION Power Other Output AN25 VOC Power Other AN7 FC16 Power Other Output AN26 VCC Power Other AN8 VCC Power Other AN27 VSS Power Other AN9 VCC Power Other AN28 VSS Power Other AN10 VSS Power Other AN29 VCC Power Other AN11 VCC Power Other AN30 VCC Power Other 65 Land Listing and Signal Descriptions 4 2 66 Alphabetical Signals Reference Table 4 3 Signal Description Sheet 1 of 8 Name Type Description A 35 3 Input Output A 35 3 Address define a 2 6_byte physical memory address space In sub phase 1 of the address phase these signals transmit the address of a transaction In sub phase 2 these signals transmit transaction type information These signals must connect the appropriate pins lands of all agents on the processor FSB A 35 3 are protected by parity signals AP 1 0 A 35 3 are source synchronous signals and are latched into the receiving buffers by ADSTB 1 0 On the active to inactive transition of RESET the processor samples a subset of the A 35 3 signals to determine power on configuration See Section 6 1 for more details A20M Input If A20M Address 20 Mask is asserted the processor masks physical address bit 20 A20 before looking up a line in any internal cache and before driving a read write transaction on the
84. er Other VCC AK15 Power Other VCC AN15 Power Other VCC AK18 Power Other VCC AN18 Power Other VCC AK19 Power Other VCC AN19 Power Other VCC AK21 Power Other VCC AN21 Power Other VCC AK22 Power Other VCC AN22 Power Other VCC AK25 Power Other VCC AN25 Power Other VCC AK26 Power Other VCC AN26 Power Other VCC AK8 Power Other VCC AN29 Power Other VCC AK9 Power Other VCC AN30 Power Other VCC AL11 Power Other VCC AN8 Power Other VCC AL12 Power Other VCC AN9 Power Other VCC AL14 Power Other VCC J10 Power Other VCC AL15 Power Other VCC J11 Power Other VCC AL18 Power Other VCC J12 Power Other VCC AL19 Power Other VCC J13 Power Other VCC AL21 Power Other VCC J14 Power Other VCC AL22 Power Other VCC J15 Power Other VCC AL25 Power Other VCC J18 Power Other VCC AL26 Power Other VCC J19 Power Other VCC AL29 Power Other VCC J20 Power Other VCC AL30 Power Other VCC J21 Power Other VCC AL8 Power Other VCC J22 Power Other VCC AL9 Power Other VCC J23 Power Other VCC AM11 Power Other VCC J24 Power Other VCC AM12 Power Other VCC J25 Power Other VCC AM14 Power Other VCC J26 Power Other VCC AM15 Power Other VCC J27 Power Other VCC AM18 Power Other VCC J28 Power Other VCC AM19 Power Other VCC J29 Power Other VCC AM21 Power Other VCC J30 Power Other VCC AM22 Power Other VCC J8 Power Other VCC AM25 Power Other VCC J9 Power Other VCC AM26 Power Other VCC K23 Powe
85. er State Machine 86 7 1 Mechanical Representation of the Boxed Drocessor av 89 7 2 Side View Space Requirements for the Boxed Processor Applies to all four side views 90 7 3 Top View Space Requirements for the Boxed PDrocessor aaa 90 7 4 Overall View Space Requirements for the Boxed Processor aaa 91 7 5 Boxed Processor Fan Heatsink Power Cable Connector Description 92 7 6 Baseboard Power Header Placement Relative to Processor Socket eek 93 7 7 Boxed Processor Fan Heatsink Airspace Keepout Requirements side 1 view 94 7 8 Boxed Processor Fan Heatsink Airspace Keepout Requirements side 2 view 94 7 9 Boxed Processor Fan Heatsink Set PointS eek kaaa aaa 95 8 1 Mechanical Representation of the Boxed Drocessor 97 8 2 Requirements for the Balanced Technology Extended BTX Type Keep out Volumes 98 8 3 Assembly Stack Including the Support and Retention Module kakaa 99 8 4 Boxed Processor Fan Heatsink Power Cable Connector aaa 100 8 5 Balanced Technology Extended BTX Mainboard Power Header Placement hatched area 101 8 6 Boxed Processor TMA Set Points 00 aaa 102 Datasheet 5 Contents ntel m Tables 1 1 Ee 13 2 1 Voltage Identification Definition 000a aaa aaa 17 2 2 Processor DC Absolute Maximum Ratings aeke kaaa aa 19 2 3 Voltage and Current Specifications aaa 20 2 4 VCC Static and Transient Tolerance for 775_VR_CONFIG_05A Pentium D Processor 21 2 5 VCC
86. es part of a binary sequence such as address or data the symbol implies that the signal is inverted For example D 3 0 HLHL refers to a hex A and D 3 0 LHLH also refers to a hex A H High logic level L Low logic level FSB refers to the interface between the processor and system core logic a k a the chipset components The FSB is a multiprocessing interface to processors memory and I O Processor Packaging Terminology Commonly used terms are explained here for clarification Intel Pentium D processor 800 sequence Dual core processor in the FC LGA4 package with two 1 MB L2 caches Processor For this document the term processor is the generic form of the Intel Pentium D processor 800 sequence Keep out zone The area on or near the processor that system design can not use e Intel 945G 945GZ 945P 945PL Express Chipset Family Chipset that supports DDR2 memory technology for the Pentium D processor Intel 955X Express Chipset Chipset that supports DDR2 memory technology for the Pentium D processor e Processor core Processor core die with integrated L2 cache e FC LGA4 package The Pentium D processor is available in a Flip Chip Land Grid Array 4 package consisting of a processor core mounted on a substrate with an integrated heat spreader IHS e LGA775 socket The Pentium D processor mates with the system board through a surface mount 775 l
87. essor Cooling Reouiremerts aaa 101 8 3 2 Variable Speed FAN abe iaren ea jaka panoi tanak dan ik kran 102 9 Debug Tools Specifications kaan 105 9 1 Logic Analyzer Interface LAI 00 ee eecceeeeeeeeeeee eee eeeeeeeeeeseeeaaeeeeeeeaaaeeeeeeeaaaeeeeneeaaeeeeeneaaees 105 9 1 1 Mechanical Consideratons aaa aaa 105 9 1 2 Electrical Considerations aaa naa 105 4 Datasheet j ntel e Contents Figures 2 1 VCC Static and Transient Tolerance for 775_VR_CONFIG_05A Pentium D Processor 22 2 2 VCC Static and Transient Tolerance for 775_VR_CONFIG_05B Pentium D Processor 24 2 3 VCC Overshoot Example Waveform 000 aaa aaa 25 2 4 Phase Lock Loop PLL Filter Heourements AA 34 3 1 Processor Package Assembly Gketrch kakaa aaa 35 3 2 Processor Package Drawing 1 kaaa 36 3 3 Processor Package Drawing 2 eee eden agda i odutala no i Vadi EERSTEN 37 3 4 Processor Package Drawing 3 aaa 38 3 5 Processor Top Side Marking Example Intel Pentium D Processors 840 830 820 40 3 6 Processor Top Side Marking Example Intel Pentium D Processor BOS ia o raka a a dnana ika eiert 41 3 7 Processor Land Coordinates Top View 42 4 1 Landout Diagram Top View Left Side 44 4 2 Landout Diagram Top View Right del 45 5 1 Thermal Profile for the Pentium D Processor with DDT 77 5 2 Thermal Profile for the Pentium D Processor with DH 78 5 3 Case Temperature TC Measurement Location 79 6 1 Processor Low Pow
88. essor Thermal Specifications of etal Core a m KOCH Maximum Tg C Notes 805 2 66 GHz PRB 0 95 5 See Table 5 3 and Figure 5 2 1 2 820 2 80 GHz PRB 0 95 5 See Table 5 3 and Figure 5 2 1 2 830 3 GHz PRB 1 130 5 See Table 5 2 and Figure 5 1 1 2 840 3 20 GHz PRB 1 130 5 See Table 5 2 and Figure 5 1 1 2 NOTES Thermal Design Power TDP should be used for processor thermal solution design targets The TDP is not the maximum pow er that the processor can dissipate 2 This table shows the maximum TDP for a given frequency range Individual processors may have a lower TDP Therefore the maximum T will vary depending on the TDP of the individual processor Refer to thermal profile figure and associated table for the allowed combinations of power and Tc 1 Datasheet l n Thermal Specifications and Design Considerations Table 5 2 Thermal Profile for the Pentium D Processor with PRB 1 Power Maximum Te Power Maximum Te Power Maximum Te Power Maximum Tc W C W C W C W C 0 43 8 34 50 6 68 57 4 102 64 2 2 44 2 36 51 0 70 57 8 104 64 6 4 44 6 38 51 4 72 58 2 106 65 0 6 45 0 40 51 8 74 58 6 108 65 4 8 45 4 42 52 2 76 59 0 110 65 8 10 45 8 44 52 6 78 59 4 112 66 2 12 46 2 46 53 0 80 59 8 114 66 6 14 46 6 48 53 4 82 60 2 116 67 0 16 47 0 50 53 8 84 60 6 118 67 4 18 47 4 52 54 2 86 61 0 120 67 8 20 47 8
89. formation contact your Intel sales representative The ITP700 Debug Port Design Guide is located at http www intel com design xeon guides 249679 htm Logic Analyzer Interface LAI Intel is working with two logic analyzer vendors to provide logic analyzer interfaces LAIs for use in debugging Intel Pentium D processor systems Tektronix and Agilent should be contacted to get specific information about their logic analyzer interfaces The following information is general in nature Specific information must be obtained from the logic analyzer vendor Due to the complexity of Pentium D processor systems the LAI is critical in providing the ability to probe and capture FSB signals There are two sets of considerations to keep in mind when designing a Pentium D processor system that can make use of an LAI mechanical and electrical Mechanical Considerations The LAI is installed between the processor socket and the Pentium D processor The LAI lands plug into the socket while the Pentium D processor lands plug into a socket on the LAI Cabling that is part of the LAI egresses the system to allow an electrical connection between the Pentium D processor and a logic analyzer The maximum volume occupied by the LAI known as the keepout volume as well as the cable egress restrictions should be obtained from the logic analyzer vendor System designers must make sure that the keepout volume remains unobstructed inside the system Note that it
90. hermal Trip indicates the processor junction temperature has reached a level beyond where permanent silicon damage may occur Upon assertion of THERMTRIP the processor will shut off its internal clocks thus halting program execution in an attempt to reduce the processor junction temperature To protect the processor its core voltage Vec must be removed following the assertion of THERMTRIP Driving of the THERMTRIP signal is enabled within 10 us of the assertion of PWRGOOD provided VTTPWRGD VTT and VCC are asserted and is disabled on de assertion of PWRGOOD if VTTPWRGD VTT or VCC are not valid THERMTRIP may also be disabled Once activated THERMTRIP remains latched until PWRGOOD VTTPWRGD VTT or VCC is de asserted While the de assertion of the PWRGOOD VTTPWRGD VTT or VCC signal will de assert THERMTRIP3 if the processor s junction temperature remains at or above the trip level THERMTRIP will again be asserted within 10 us of the assertion of PWRGOOD provided VTTPWRGD VTT and VCC are asserted THERMTRIP should not be sampled until 10 us after PWRGOOD assertion Datasheet Land Listing and Signal Descriptions Table 4 3 Signal Description Sheet 8 of 8 Datasheet Name Type Description TMS Input TMS Test Mode Select is a JTAG specification support signal used by debug tools TRDY Input TRDY Target Ready is asserted by the target to indicate that it is ready to recei
91. hermal solution that is significantly under designed may not be capable of cooling the processor even when the TCC is active continuously Refer to the Intel Pentium D Processor and Intel Pentium Processor Extreme Edition 840 Thermal and Mechanical Design Guidelines for information on designing a thermal solution The duty cycle for the TCC when activated by the Thermal Monitor is factory configured and cannot be modified The Thermal Monitor does not require any additional hardware software drivers or interrupt handling routines On Demand Mode The Pentium D processor provides an auxiliary mechanism that allows system software to force the processor to reduce its power consumption This mechanism is referred to as On Demand mode and is distinct from the Thermal Monitor feature On Demand mode is intended as a means to reduce system level power consumption Systems using the Pentium D processor must not rely on software usage of this mechanism to limit the processor temperature If bit 4 of the ACPI P_CNT Control Register located in the processor IA32_THERM_CONTROL MSR is written to a 1 the processor will immediately reduce its power consumption via modulation starting and stopping of the internal core clock independent of the processor temperature When using On Demand mode the duty cycle of the clock modulation is programmable via bits 3 1 of the same ACPI P_CNT Control Register In On Demand mode the duty cycle can be progr
92. his table apply to all processor frequencies 2 All outputs are open drain 3 Vuyg represents the amount of hysteresis nominally centered about 0 5 Vre for all TAP inputs 4 The Vry referred to in these specifications refers to instantaneous V 5 The maximum output current is based on maximum current handling capability of the buffer and is not specified into the test load 6 Leakage to Vgs with land held at Ver Table 2 13 GTL Asynchronous Signal Group DC Specifications Symbol Parameter Min Max Unit Notes Vu Input Low Voltage 0 0 Vrr 2 0 10 Vrr S 2 3 Vu Input High Voltage Vrr 2 0 10 Mat Vat 3 4 5 6 Voy Output High Voltage M Vir V 8 87 lo Output Low Current Vrr 0 50 R tr Min A 8 ON MIN ly Input Leakage Current N A 200 HA 9 Output Leakage 10 lio Current N A 200 HA Ron Buffer On Resistance 8 12 Q NOTES 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 Vu is defined as the voltage range at a receiving agent that will be interpreted as a logical low value 3 LINTO INTR LINT1 NMI and FORCEPR use GTLREF as a reference voltage For these two signals Vin GTLREF 0 10 VTT and Muss GTLREF 0 10 VTT Vin is defined as the voltage range at a receiving agent that will be interpreted as a logical high value Vin and Voy may experience excursions above Ver The VTT referred
93. hould not be driven allowing the level to return to Mac for minimum power drawn by the termination resistors in this state In addition all other input signals on the FSB should be driven to the inactive state BINIT will not be serviced while the processor is in Stop Grant state The event will be latched and can be serviced by software upon exit from the Stop Grant state RESET will cause the processor to immediately initialize itself but the processor will stay in Stop Grant state A transition back to the Normal state will occur with the de assertion of the STPCLK signal A transition to the HALT Grant Snoop state will occur when the processor detects a snoop on the FSB see Section 6 2 4 While in the Stop Grant State SMI INIT BINIT and LINT 1 0 will be latched by the processor and only serviced when the processor returns to the Normal State Only one occurrence of each event will be recognized upon return to the Normal state While in Stop Grant state the processor will process a FSB snoop 87 Features 6 2 4 6 2 4 1 6 2 4 2 6 2 5 88 Note intel Enhanced HALT Snoop or HALT Snoop State Grant Snoop State The Enhanced HALT Snoop State is used in conjunction with the new Enhanced HALT state If Enhanced HALT state is not enabled in the BIOS the default Snoop State entered will be the HALT Snoop State Refer to the sections below for details on HALT Snoop State Grant Snoop State and Enhanced HA
94. iate pins lands of all processor FSB agents If INIT is sampled active on the active to inactive transition of RESET then the processor executes its Built in Self Test BIST ITP_CLK 1 0 are copies of BCLK that are used only in processor systems where no debug port is implemented on the system board ITP_CLK 1 0 are ITP_CLK 1 0 Input used as BCLK 1 0 references for a debug port implemented on an interposer If a debug port is implemented in the system ITP_CLK 1 0 are no connects in the system These are not processor signals LINT 1 0 Local APIC Interrupt must connect the appropriate pins lands of all APIC Bus agents When the APIC is disabled the LINTO signal becomes INTR a maskable interrupt request signal and LINT1 becomes NMI a nonmaskable interrupt INTR and NMI are backward compatible with the signals of those LINT 1 0 Input names on the Pentium processor Both signals are asynchronous Both of these signals must be software configured via BIOS programming of the APIC register space to be used either as NMI INTR or LINT 1 0 Because the APIC is enabled by default after Reset operation of these signals as LINT 1 0 is the default configuration The LL_ID 1 0 signals are used to select the correct loadline slope for the LL_ID 1 0 Output processor LOCK indicates to the system that a transaction must occur atomically This signal must connect the appropriate pins lands of all processor FSB agents For
95. if existent should be less than 0 05 MHz 4 fcore represents the maximum core frequency supported by the platform Datasheet Package Mechanical Specifications Package Mechanical Specifications The Intel Pentium D processor is packaged in a Flip Chip Land Grid Array FC LGA4 package that interfaces with the motherboard via an LGA775 socket The package consists of a processor core mounted on a substrate land carrier An integrated heat spreader IHS is attached to the package substrate and core and serves as the mating surface for processor component thermal solutions such as a heatsink Figure 3 1 shows a sketch of the processor package components and how they are assembled together Refer to the LGA775 Socket Mechanical Design Guide for complete details on the LGA775 socket The package components shown in Figure 3 1 include the following Integrated Heat Spreader IHS Thermal Interface Material TIM e Processor core die Package substrate e Capacitors Figure 3 1 Processor Package Assembly Sketch 3 1 Note Datasheet Core die TIM IHS i Substrate Capacitors LGA775 Socket System Board a ystem Boar ps NOTE 1 Socket and motherboard are included for reference and are not part of processor package Package Mechanical Drawing The package mechanical drawings are shown in Figure 3 2 and Figure 3 4 The drawings include dimensions necessary to design a thermal solution for the
96. ing BPRI active as asserted by the priority agent causes all other agents to stop issuing new requests unless such requests are part of an ongoing locked operation The priority agent keeps BPRI asserted until all of its requests are completed then releases the bus by de asserting BPRI BRO Input Output BRO drives the BREQO signal in the system and is used by the processor to request the bus During power on configuration this signal is sampled to determine the agent ID 0 This signal does not have on die termination and must be terminated BSEL 2 0 Output The BCLK 1 0 frequency select signals BSEL 2 0 are used to select the processor input clock frequency Table 2 18 defines the possible combinations of the signals and the frequency associated with each combination The required frequency is determined by the processor chipset and clock synthesizer All agents must operate at the same frequency For more information about these signals including termination recommendations refer to Section 2 7 2 COMP 1 0 Analog COMP 1 0 must be terminated to Vgs on the system board using precision resistors COMPI3 2 Analog COMP 3 2 must be terminated to Vgs on the system board using precision resistors 67 Land Listing and Signal Descriptions n Table 4 3 Signal Description Sheet 3 of 8 Name Type Description D 63 0 Data are the data signals These signals pro
97. ingle Logical Processor Mode A31 Symmetric agent arbitration ID BRO RESERVED A 6 3 A8 A 14 13 A 16 30 A 32 35 NOTES 1 Asserting this signal during RESET will select the corresponding option 2 Address signals not identified in this table as configuration options should not be asserted during RESET 3 This mode is not tested Clock Control and Low Power States The processor allows the use of AutoHALT and Stop Grant states to reduce power consumption by stopping the clock to internal sections of the processor depending on each particular state See Figure 6 1 for a visual representation of the processor low power states The Pentium D processor includes support for the Enhanced HALT powerdown state Refer to Figure 6 1 and the following sections 85 Features Figure 6 1 Processor Low Power State Machine 6 2 1 6 2 2 6 2 2 1 86 HALT or MWAIT Instruction and HALT Bus Cycle Generated a iki y gt Enhanced HALT or HALT State re i e i INIT BINIT INTR NMI SMI BCLK running BRUN p RESET FSB interrupts Snoops and interrupts allowed A A x AN amp ES Snoop Snoop STPCLK STPCLK SS Event Event Asserted De asserted Ka AS Occurs Serviced Kod KLE CB Enhanced HALT Snoop or HALT Snoop State BCLK running Service snoops to caches Yy Y Stop Grant State Snop EVEN Der Grant Snoop State BCLK running BCLK running Snoops and inter
98. internal chassis temperature is below or equal to this set point X lt 30 the fan operates at its lowest speed Recommended maximum internal chassis temperature for nominal operating environment When the internal chassis temperature is at this point the fan operates Y 35 between its lowest and highest speeds Recommended maximum internal chassis temperature for worst case operating environment Z gt 39 When the internal chassis temperature is above or equal to this set point S gt the fan operates at its highest speed NOTES 1 Set point variance is approximately 1 C from fan heatsink to fan heatsink Datasheet 95 m Boxed Processor Specifications ntal a 96 If the boxed processor fan heatsink 4 pin connector is connected to a 4 pin motherboard header and the motherboard is designed with a fan speed controller with PWM output For details on CONTROL see Table 7 1 and remote thermal diode measurement capability the boxed processor will operate as follows As processor power has increased the required thermal solutions have generated increasingly more noise Intel has added an option to the boxed processor that allows system integrators to have a quieter system in the most common usage The 4th wire PWM solution provides better control over chassis acoustics This is achieved by more accurate measurement of processor die temperature through the processor s temperature diode Tpropp Fan RPM is modulated
99. is possible that the keepout volume reserved for the LAI may differ from the space normally occupied by the Pentium D processor heatsink If this is the case the logic analyzer vendor will provide a cooling solution as part of the LAI Electrical Considerations The LAI will also affect the electrical performance of the FSB therefore it is critical to obtain electrical load models from each of the logic analyzers to be able to run system level simulations to prove that their tool will work in the system Contact the logic analyzer vendor for electrical specifications and load models for the LAI solution they provide 105 Debug Tools Specifications 106 Datasheet
100. lands must be connected to the system ground plane The processor VCC lands must be supplied with the voltage determined by the processor Voltage IDentification VID lands The Pentium D processor has 24 signals that are denoted as VTT that provide termination for the front side bus and power to the I O buffers A separate supply must be implemented for these lands that meets the Nur specifications outlined in Table 2 3 Decoupling Guidelines Due to its large number of transistors and high internal clock speeds the processor is capable of generating large current swings between low and full power states This may cause voltages on power planes to sag below their minimum values if bulk decoupling is not adequate Larger bulk storage CBULK such as electrolytic or aluminum polymer capacitors supply current during longer lasting changes in current demand by the component such as coming out of an idle condition Similarly they act as a storage well for current when entering an idle condition from a running condition The motherboard must be designed to ensure that the voltage provided to the processor remains within the specifications listed in Table 2 3 Failure to do so can result in timing violations or reduced lifetime of the component For further information and design guidelines refer to the Voltage Regulator Down VRD 10 1 Design Guide For Desktop LGA775 Socket Vcc Decoupling Vcc regulator solutions need to provide sufficient decoupli
101. lock Input D19 DBI2 Source Synch Input Output F3 BRO Common Clock Input Output D20 D48 Source Synch Input Output F4 VSS Power Other D21 VSS Power Other F5 RS1 Common Clock Input D22 D46 Source Synch Input Output F6 IMPSEL Power Other Input D23 VCCPLL Power Other Input F7 VSS Power Other D24 VSS Power Other F8 D17 Source Synch Input Output D25 VTT Power Other F9 D18 Source Synch Input Output D26 VTT Power Other F10 VSS Power Other D27 VTT Power Other F11 D23 Source Synch Input Output D28 VTT Power Other F12 D24 Source Synch Input Output D29 VTT Power Other F13 VSS Power Other D30 VTT Power Other F14 D28 Source Synch Input Output E2 VSS Power Other F15 D30 Source Synch Input Output E3 TRDY Common Clock Input F16 VSS Power Other E4 HITM Common Clock Input Output F17 D37 Source Synch Input Output E5 FC20 Power Other Input F18 D38 Source Synch Input Output 57 Land Listing and Signal Descriptions 58 Table 4 2 Numerical Land Assignment intel Table 4 2 Numerical Land Assignment ee Land Name Di odak Direction sany Land Name oi a mar Direction F19 VSS Power Other H1 GTLREFO Power Other Input F20 D41 Source Synch Input Output H2 GTLREF1 Power Other Input F21 D43 Source Synch Input Output H3 VSS Power Other F22 VSS Power Other H4 RSP Common Clock Input F
102. ly driven high during a logical 0 to 1 transition by the processor GTL asynchronous signals do not have setup or hold time specifications in relation to BCLK 1 0 All of the GTL Asynchronous signals are required to be asserted deasserted for at least six BCLKs in order for the processor to recognize the proper signal state See Section 2 6 3 for the DC specifications for the GTL Asynchronous signal groups See Table 6 2 for additional timing requirements for entering and leaving the low power states 28 Datasheet intel 2 6 3 FSB DC Specifications Electrical Specifications The processor front side bus DC specifications in this section are defined at the processor core pads unless otherwise stated All specifications apply to all frequencies and cache sizes unless otherwise stated Table 2 10 BSEL 2 0 and VID 5 0 Signal Group DC Specifications Symbol Parameter Max Unit Notes 2 Ron BSEL Buffer On Resistance 60 Q Ron VID Buffer On Resistance 60 Q lo Max Land Current 8 mA lo Output Leakage Current 200 uA 3 VoL Voltage Tolerance Ver max V NOTES 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 These parameters are not tested and are based on design simulations 3 Leakage to Vgg with land held at 2 5V Table 2 11 GTL Signal Group DC Specifications Symbol Parameter Min Max
103. mV by changing the target VID through the VID signals Datasheet Note Boxed Processor Specifications Boxed Processor Specifications The Intel Pentium D processor will also be offered as an Intel boxed processor Intel boxed processors are intended for system integrators who build systems from baseboards and standard components The boxed Pentium D processor will be supplied with a cooling solution This chapter documents baseboard and system requirements for the cooling solution that will be supplied with the boxed Pentium D processor This chapter is particularly important for OEMs that manufacture baseboards for system integrators Unless otherwise noted all figures in this chapter are dimensioned in millimeters and inches in brackets Figure 7 1 shows a mechanical representation of a boxed Pentium D processor Drawings in this section reflect only the specifications on the Intel boxed processor product These dimensions should not be used as a generic keep out zone for all cooling solutions It is the system designers responsibility to consider their proprietary cooling solution when designing to the required keep out zone on their system platforms and chassis Refer to the Intel Pentium D Processor and Intel Pentium Processor Extreme Edition 840 Thermal and Mechanical Design Guidelines for further guidance Contact your local Intel Sales Representative for this document Figure 7 1 Mechanical Representation of the Boxed P
104. mal sensors as exemplified by the equation Terror RT N 1 ewer nk q In N where Terror Sensor temperature error N sensor current ratio k Boltzmann Constant q electronic charge Datasheet Table 5 5 Thermal Diode Interface Datasheet Thermal Specifications and Design Considerations Signal Name Land Number Signal Description THERMDA AL diode anode THERMDC AK1 diode cathode 83 Thermal Specifications and Design Considerations 84 Datasheet 6 1 Features Features Power On Configuration Options Several configuration options can be configured by hardware The Intel Pentium D processor samples the hardware configuration at reset on the active to inactive transition of RESET For specifications on these options refer to Table 6 1 The sampled information configures the processor for subsequent operation These configuration options cannot be changed except by another reset All resets reconfigure the processor for reset purposes the processor does not distinguish between a warm reset and a power on reset Table 6 1 Power On Configuration Option Signals 6 2 Datasheet Configuration Option Signal 2 Output tristate SMI Execute BIST INIT In Order Queue pipelining set IOQ depth to 1 A7 Disable MCERR observation A9 Disable BINIT observation A10 APIC Cluster ID 0 3 A 12 11 Disable bus parking A15 S
105. maximum voltages must be maintained as shown in Table 2 4 Table 2 5 and Figure 2 1 Figure 2 2 as measured across the VCC_SENSE and VSS_SENSE lands The VRM or VRD utilized must be capable of regulating its output to the value defined by the new VID DC specifications for dynamic VID transitions are included in Table 2 3 Table 2 4 and Table 2 5 Refer to the Voltage Regulator Down VRD 10 1 Design Guide For Desktop LGA775 Socket for further details Datasheet m l ntel e Electrical Specifications Table 2 1 Voltage Identification Definition VIDS VID4 VID3 VID2 VID1 VIDO VID VID5 VID4 VID3 VID2 VID1 VIDO VID 0 0 1 0 1 0 0 8375 0 1 1 0 1 0 1 2125 1 0 1 0 0 1 0 8500 1 1 1 0 0 1 1 2250 0 0 1 0 0 1 0 8625 0 1 1 0 0 1 1 2375 1 0 1 0 0 0 0 8750 1 1 1 0 0 0 1 2500 0 0 1 0 0 0 0 8875 0 1 1 0 0 0 1 2625 1 0 0 1 1 1 0 9000 1 1 0 1 1 1 1 2750 0 0 0 1 1 1 0 9125 0 1 0 1 1 1 1 2875 1 0 0 1 1 0 0 9250 1 1 0 1 1 0 1 3000 0 0 0 1 1 0 0 9375 0 1 0 1 1 0 1 3125 1 0 0 1 0 1 0 9500 1 1 0 1 0 1 1 3250 0 0 0 1 0 1 0 9625 0 1 0 1 0 1 1 3375 1 0 0 1 0 0 0 9750 1 1 0 1 0 0 1 3500 0 0 0 1 0 0 0 9875 0 1 0 1 0 0 1 3625 1 0 0 0 1 1 1 0000 1 1 0 0 1 1 1 3750 0 0 0 0 1 1 1 0125 0 1 0 0 1 1 1 3875 1 0 0 0 1 0 1 0250 1 1 0 0 1 0 1 4000 0 0 0 0 1 0 1 0375 0 1 0 0 1 0 1 4125 1 0 0 0 0 1 1 0500 1 1 0 0 0 1 1 4250 0 0 0 0 0 1 1 0625 0 1 0 0 0 1 1 4375 1 0
106. mp BCLK 1 0 BPM 5 0 BRO BSEL 2 0 Gs DBSY DEFER Gu Ginen COMP 3 0 FERR PBE IERR IGNNE INIT ae E gt LINTO INTR LINT1 NMI PWRGOOD RESET GU EE HIT SkTOCC SMI STPCLK TDO TESTHI 13 0 THERMDA THERMDC THERMTRIP VID 5 0 PROCHOT REQ 4 0 RS 2 0 RSP TRDY MSIDI SI VTTPWRGD GTLREF 1 0 TCK TDI TRST TMS Open Drain Signals BSEL 2 0 VID 5 0 THERMTRIP FERR PBE IERR BPM 5 0 BRO TDO VTT_SEL LL_ID 1 0 NOTES 1 These signals have a 250 5000 Q pullup to Vrr rather than on die termination 2 Signals that do not have Ry nor are actively driven to their high voltage level Table 2 9 Signal Reference Voltages GTLREF Vrr 2 BPM 5 0 LINTO INTR LINT1 NMI RESET BINIT BNR HIT HITM MCERR PROCHOT ROOTSELECT VTTPWRGD A20M IGNNE BRO A 35 0 ADS ADSTB 1 0 AP 1 0 1 Vu INIT PWRGOOD SMI STPCLK TCK TDI BPRI D 63 0 DBI 3 0 DBSY DEFER TMS mert MSIDI1 0 DP 3 0 DRDY DSTBNI 3 0 DSTBP 3 0 LOCK REQ 4 0 RS 2 0 RSP TRDY NOTES 1 These signals also have hysteresis added to the reference voltage See Table 2 12 for more information 2 6 2 GTL Asynchronous Signals The signals A20M IGNNE INIT SMI and STPCLK utilize CMOS input buffers GTL asynchronous signals follow the same DC requirements as GTL signals however the outputs are not active
107. n Typ Max Unit Notes lew Forward Bias Current 11 187 uA 1 n Diode Ideality Factor 1 0083 1 011 1 023 2 3 4 5 Rr Series Resistance 3 242 3 33 3 594 Q 2 3 6 NOTES Intel does not support or recommend operation of the thermal diode under reverse bias 1 2 Characterized at 75 C 3 Not 100 tested Specified by design characterization 4 The ideality factor n represents the deviation from ideal diode behavior as exemplified by the diode equation lew Is e QV p nkT 1 where Is saturation current q electronic charge Vp voltage across the diode k Boltzmann Constant and T absolute temperature Kelvin 5 Devices found to have an ideality factor of 1 0183 to 1 023 will create a temperature error approximately 2 C higher than the actual temperature To minimize any potential acoustic impact of this temperature error TcontRoL Will be increased by 2 C on these parts 6 The series resistance Rr is provided to allow for a more accurate measurement of the thermal diode temperature Ry as defined includes the pins of the processor but does not include any socket resistance or board trace resistance be tween the socket and the external remote diode thermal sensor RT can be used by remote diode thermal sensors with automatic series resistance cancellation to calibrate out this error term Another application is that a temperature offset can be manually calculated and programmed into an offset register in the remote diode ther
108. nchronous A20M FORCEPR IGNNE INIT LINTO INTR Input LINT1 NMI SMI STPCLK GTE Asynchr nous FERR PBE IERR THERMTRIP Output GTL Asynchronous Input Output PROCHOTH TAP Input Synchronous to TCK TCK TDI TMS TRST TAP Output Synchronous to TCK TDO FSB Clock Clock BCLK 1 0 ITP_CLK 1 0 8 VCC VTT VCCA VCCIOPLL VID 5 0 VSS VSSA GTLREF 1 0 COMP 1 0 COMP 3 2 IMPSEL RESERVED TESTHI 13 0 THERMDA THERMDC Power Other VCC_SENSE VSS_SENSE BSEL 2 0 SKTOCC Owe DBR 5 VTTPWRGD BOOTSELECT PWRGOOD VTT_OUT_LEFT VTT_OUT_RIGHT VTT_SEL LL_ID 1 0 FCx VCC_MB_REGULATION VSS_MB_REGULATION MSID 1 0 VCCPLL NOTES 1 Refer to Section 4 2 for signal descriptions 2 The value of A 16 3 and A 35 17 during the active to inactive edge of RESET defines the processor configuration options See Section 6 1 for details 3 In processor systems where there is no debug port implemented on the system board these signals are used to support a debug port interposer In systems with the debug port implemented on the system board these signals are no connects Table 2 8 outlines the signals which include on die termination Rpr Open drain signals are also included Table 2 9 provides signal reference voltages 27 Electrical Specifications n Table 2 8 Signal Characteristics Signals with R Signals with no R A 35 3 ADS ADSTB 1 0 AP 1 0 BINIT eae ec Ee Weu A20M a
109. nd Assignment cama Land Name Re Direction ia Land Name Weg raniji Direction C24 VSS Power Other E6 RESERVED C25 VTT Power Other E7 RESERVED C26 VTT Power Other E8 VSS Power Other C27 VTT Power Other E9 D19 Source Synch Input Outpu C28 VTT Power Other E10 D21 Source Synch Input Outpu C29 VTT Power Other E11 VSS Power Other C30 VTT Power Other E12 DSTBP1 Source Synch Input Outpu D1 RESERVED E13 D26 Source Synch Input Outpu D2 ADS Common Clock Input Output E14 VSS Power Other D3 VSS Power Other E15 D33 Source Synch Input Outpu D4 HIT Common Clock Input Output E16 D34 Source Synch Input Outpu D5 VSS Power Other E17 VSS Power Other D6 VSS Power Other E18 D39 Source Synch Input Outpu D7 D20 Source Synch Input Output E19 D40 Source Synch Input Outpu D8 D12 Source Synch Input Output E20 VSS Power Other D9 VSS Power Other E21 D42 Source Synch Input Outpu D10 D22 Source Synch Input Output E22 D45 Source Synch Input Outpu D11 D15 Source Synch Input Output E23 RESERVED D12 VSS Power Other E24 FC10 Power Other Input D13 D25 Source Synch Input Output E25 VSS Power Other D14 RESERVED E26 VSS Power Other DIS VSS Power Other E27 VSS Power Other D16 RESERVED E28 VSS Power Other D17 D49 Source Synch Input Output E29 VSS Power Other D18 VSS Power Other F2 FC5 Common C
110. ng capacitance to satisfy the processor voltage specifications This includes bulk capacitance with low effective series resistance ESR to keep the voltage rail within specifications during large swings in load current In addition ceramic decoupling capacitors are required to filter high frequency content generated by the front side bus and processor activity Consult the Voltage Regulator Down VRD 10 1 Design Guide For Desktop LGA775 Socket for further information V 7 Decoupling Decoupling must be provided on the motherboard Decoupling solutions must be sized to meet the expected load To insure compliance with the specifications various factors associated with the power delivery solution must be considered including regulator type power plane and trace sizing and component placement A conservative decoupling solution would consist of a combination of low ESR bulk capacitors and high frequency ceramic capacitors m Electrical Specifications ntal a 2 2 3 2 3 FSB Decoupling The Pentium D processor package integrates signal termination on the die as well as incorporates high frequency decoupling capacitance on the processor package Decoupling must also be provided by the system baseboard for proper GTL bus operation Voltage Identification The Voltage Identification VID specification for the Pentium D processor is defined by the Voltage Regulator Down VRD 10 1 Design Guide For Desktop LGA775 Socket The voltage set by
111. ng system allows memory to be marked as executable or non executable If code attempts to run in non executable memory the processor raises an error to the operating system This feature can prevent some classes of viruses or worms that exploit buffer over run vulnerabilities and can thus help improve the overall security of the system See the Intel Architecture Software Developer s Manual for more detailed information Intel will enable support components for the processor including heatsink heatsink retention mechanism and socket Manufacturability is a high priority hence mechanical assembly may be completed from the top of the baseboard and should not require any special tooling The processor includes an address bus powerdown capability that removes power from the address and data pins when the FSB is not in use This feature is always enabled on the processor Enhanced Intel SpeedStep Technology allows trade offs to be made between performance and power consumptions This may lower average power consumption in conjunction with OS support Iniroduction 1 1 1 1 1 intel Terminology A symbol after a signal name refers to an active low signal indicating a signal is in the active state when driven to a low level For example when RESET is low a reset has been requested Conversely when NMI is high a nonmaskable interrupt has occurred In the case of signals where the name does not imply an active state but describ
112. ng through a 11 ms trapezoidal pulse of 50 g and the maximum static load Package Handling Guidelines Table 3 2 includes a list of guidelines on package handling in terms of recommended maximum loading on the processor IHS relative to a fixed substrate These package handling loads may be experienced during heatsink removal Package Handling Guidelines Parameter Maximum Recommended Notes Shear 311 N 70 lbf nA Tensile 111 N 25 Ibf 2 4 Torque 3 95 N m 35 Ibf in 3 4 NOTES 1 A shear load is defined as a load applied to the IHS in a direction parallel to the IHS top surface 2 A tensile load is defined as a pulling load applied to the IHS in a direction normal to the IHS surface 3 A torque load is defined as a twisting load applied to the IHS in an axis of rotation normal to the IHS top surface 4 These guidelines are based on limited testing for design characterization 39 m Package Mechanical Specifications ntal A 3 5 Package Insertion Specifications The Pentium D processor can be inserted into and removed from a LGA775 socket 15 times The socket should meet the LGA775 requirements detailed in the LGA775 Socket Mechanical Design Guide 3 6 Processor Mass Specification The typical mass of the Pentium D processor is 22 03 g 0 78 oz This mass weight includes all the components that are included in the package 3 7 Processor Materials Table 3 3 lists some of the package component
113. on of BINIT as appropriate to the error handling architecture of the system BNR Input Output BNR Block Next Request is used to assert a bus stall by any bus agent unable to accept new bus transactions During a bus stall the current bus owner cannot issue any new transactions BOOTSELECT Input This input is required to determine whether the processor is installed in a platform that supports the Pentium D processor The processor will not operate if this signal is low This input has a weak internal pull up to Vcc BPML 5 0 Input Output BPM 5 0 Breakpoint Monitor are breakpoint and performance monitor signals They are outputs from the processor that indicate the status of breakpoints and programmable counters used for monitoring processor performance BPM 5 0 should connect the appropriate pins lands of all processor FSB agents BPM4 provides PRDY Probe Ready functionality for the TAP port PRDY is a processor output used by debug tools to determine processor debug readiness BPM5 provides PREQ Probe Request functionality for the TAP port PREQ is used by debug tools to request debug operation of the processor These signals do not have on die termination Refer to Section 2 4 for termination requirements BPRI Input BPRI Bus Priority Request is used to arbitrate for ownership of the processor FSB It must connect the appropriate pins lands of all processor FSB agents Observ
114. ons Description Min Typ Max Unit Notes 12 V 12 volt fan power supply 11 4 12 12 6 V IC Peak fan steady state current draw 3 0 A Average fan steady state current draw 2 0 A Max fan start up current draw 3 0 A Fan start up current draw maximum duration 1 0 Second _ pulses per fan 1 Sense frequency 2 revolution CONTROL frequency 21 25 28 kHz 2 3 NOTES 1 Baseboard should pull this pin up to 5 V with a resistor 2 Open drain type pulse width modulated 3 Fan will have pull up resistor to 4 75 V maximum of 5 25 V Datasheet intel Boxed Processor Specifications Figure 7 6 Baseboard Power Header Placement Relative to Processor Socket 7 3 7 3 1 Note Datasheet R4 33 gt 0 Thermal Specifications This section describes the cooling requirements of the fan heatsink solution utilized by the boxed processor Boxed Processor Cooling Requirements The boxed processor may be directly cooled with a fan heatsink However meeting the processor s temperature specification is also a function of the thermal design of the entire system and ultimately the responsibility of the system integrator The processor temperature specification is found in Chapter 5 of this document The boxed processor fan heatsink is able to keep the processor temperature within the specifications see Table 5 1 in chassis that provide good thermal managemen
115. ors VR System designers can create a circuit to monitor the VR temperature and activate the TCC when the temperature limit of the VR is reached By asserting FORCEPR pulled low and activating the TCC the VR can cool down as a result of reduced processor power consumption FORCEPR can allow VR thermal designs to target maximum sustained current instead of maximum current Systems should still provide proper cooling for the VR and rely on FORCEPR only as a backup in case of system cooling failure The system thermal design should allow the power delivery circuitry to operate within its temperature specification even while the processor is operating at its Thermal Design Power With a properly designed and characterized thermal solution it is anticipated that FORCEPR would only be asserted for very short periods of time when running the most power intensive applications An under designed thermal solution that is not able to prevent excessive assertion of FORCEPR in the anticipated ambient environment may cause a noticeable performance loss Refer to the Voltage Regulator Down VRD 10 1 Design Guide for Desktop Socket 775 for details on implementing the FORCEPR feature Contact your Intel representative for further details and documentation 81 Thermal Specifications and Design Considerations n 5 2 5 5 2 6 5 2 7 THERMTRIP Signal Regardless of whether or not the Thermal Monitor feature is enabled in the event of a catastrophic
116. ost common usage The AR wire PWM solution provides better control over chassis acoustics This is achieved by more accurate measurement of processor die temperature through the processor s temperature diode Tpropp Fan RPM is modulated through the use of an ASIC located on the motherboard that sends out a PWM control signal to the 4h pin of the connector labeled as CONTROL The fan speed is based on a combination of actual processor temperature and thermistor temperature If the new 4 pin active TMA solution is connected to an older 3 pin baseboard processor fan header it will default back to a thermistor controlled mode allowing compatibility with existing 3 pin baseboard designs Under thermistor controlled mode the fan RPM is automatically varied based on the Te temperature measured by a thermistor located at the fan inlet For more details on specific motherboard requirements for 4 wire based fan speed control see the Intel Pentium D Processor and Intel Pentium Processor Extreme Edition 840 Thermal and Mechanical Design Guidelines 103 m Balanced Technology Extended BTX Type I Boxed Processor Specifications l ntel is 104 Datasheet intel 9 1 9 1 1 9 1 2 Datasheet Debug Tools Specifications Debug Tools Specifications Refer to the eXtended Debug Port Debug Port Design Guide for UP and DP Platforms and the ITP700 Debug Port Design Guide for information regarding debug tools specifications For more in
117. ower Other AB6 A17 Source Synch Input Output W28 VCC Power Other AB7 VSS Power Other W29 VCC Power Other AB8 VCC Power Other W30 VCC Power Other AB23 VSS Power Other Y1 BOOTSELECT Power Other Input AB24 VSS Power Other Y2 VSS Power Other AB25 VSS Power Other Y3 FC17 Power Other Input AB26 VSS Power Other Y4 A20 Source Synch Input Output AB27 VSS Power Other Y5 VSS Power Other AB28 VSS Power Other Y6 A19 Source Synch Input Output AB29 VSS Power Other Y7 VSS Power Other AB30 VSS Power Other Y8 VCC Power Other AC1 TMS TAP Input Y23 VCC Power Other AC2 DBR Power Other Output Y24 VCC Power Other AC3 VSS Power Other Y25 VCC Power Other AC4 RESERVED Y26 VCC Power Other AC5 A25 Source Synch Input Output Y27 VCC Power Other AC6 VSS Power Other Y28 VCC Power Other AC7 VSS Power Other Y29 VCC Power Other AC8 VCC Power Other Y30 VCC Power Other AC23 VCC Power Other AA1 VTT_OUT_RIGHT Power Other Output AC24 VCC Power Other AA2 LL_ID1 Power Other Output AC25 VCC Power Other AA3 VSS Power Other AC26 VCC Power Other AAA A21 Source Synch Input Output AC27 VCC Power Other AA5 A23 Source Synch Input Output AC28 VCC Power Other AA6 VSS Power Other AC29 VCC Power Other AA7 VSS Power Other AC30 VCC Power Other AA8 VCC Power Other AD1 TDI TAP Input AA23 VSS Power Other AD2 BPM2 Common Clock Input Output AA24 VSS Power Other AD3 BINIT Common Clock Input Output 61 Land Listing and Signal Descriptions 62 Ta
118. ower Other Output AK27 VSS Power Other AM8 VCC Power Other AK28 VSS Power Other AM9 VCC Power Other AK29 VSS Power Other AM10 VSS Power Other AK30 VSS Power Other AM11 VCC Power Other AL1 THERMDA Power Other AM12 VCC Power Other Output or AM13 VSS Power Other AL2 PROCHOT Asynch GTL Input Output AM14 VCC Power Other AL3 VSS Power Other AM15 VCC Power Other AL4 VID5 Power Other Output AM16 VSS Power Other AL5 VID1 Power Other Output AM17 VSS Power Other AL6 VID3 Power Other Output AM18 VCC Power Other AL7 VSS Power Other AM19 VCC Power Other AL8 VCC Power Other AM20 VSS Power Other AL9 VCC Power Other AM21 VCC Power Other AL10 VSS Power Other AM22 VCC Power Other AL11 VCC Power Other AM23 VSS Power Other AL12 VCC Power Other Datasheet Datasheet Table 4 2 Numerical Land Assignment Land Listing and Signal Descriptions Table 4 2 Numerical Land Assignment i Land Name si Eier Direction WS Land Name Weg Cie Direction AM24 VSS Power Other AN12 VCC Power Other AM25 VCC Power Other AN13 VSS Power Other AM26 VCC Power Other AN14 VCC Power Other AM27 VSS Power Other AN15 VCC Power Other AM28 VSS Power Other AN16 VSS Power Other AM29 VCC Power Other AN17 VSS Power Other AM30 VCC Power Other AN18 VCC Power Other AN1 VSS Power Other AN19 VCC Power Other AN2 VSS Power Other AN20 VSS Power Other AN3 VCC_SENSE Power Other Output AN21 VCC Pow
119. pecifications and Design Considerations Thermal Metrology The maximum and minimum case temperatures T are specified in Table 5 1 These temperature specifications are meant to help ensure proper operation of the processor Figure 5 3 illustrates where Intel recommends T thermal measurements should be made For detailed guidelines on temperature measurement methodology refer to the Intel Pentium D Processor and Intel Pentium Processor Extreme Edition 840 Thermal and Mechanical Design Guidelines Figure 5 3 Case Temperature Tc Measurement Location 5 2 5 2 1 Datasheet Measure Te at this point geometric center of the package 37 5 mm Processor Thermal Features Thermal Monitor The Thermal Monitor feature helps control the processor temperature by activating the TCC when the processor silicon reaches its maximum operating temperature The TCC reduces processor power consumption as needed by modulating starting and stopping the internal processor core clocks The Thermal Monitor feature must be enabled for the processor to be operating within specifications The temperature at which Thermal Monitor activates the thermal control circuit is not user configurable and is not software visible Bus traffic is snooped in the normal manner and interrupt requests are latched and serviced during the time that the clocks are on while the TCC is active When the Thermal Monitor feature is enabled and a
120. pter 4 for the signal definitions and signal assignments Most of the signals on the processor FSB are in the GTL signal group 19 Electrical Specifications Table 2 3 Voltage and Current Specifications Symbol Parameter Min Typ Max Unit Notes VID range VID 1 200 1 400 V 1 Processor number Core Frequency Vec for 775_VR_CONFIG_05B processor Refer to Table 2 5 and v 2 3 4 5 840 3 20 GHz Figure 2 2 830 3 GHz Voc Vec for 775_VR_CONFIG_05A processor PRB 0 Refer to Table 2 4 and y 235 67 820 2 80 GHz Figure 2 1 805 2 66 GHz Icc for 775_VR_CONFIG_05B Pentium D processor PRB 1 loc z A 8 Icc for 775_VR_CONFIG_05A Pentium D processor PRB 0 820 2 80 GHz Kai 100 805 2 66 GHz 100 Icc when PWRGOOD and RESET are active 840 3 20 GHz 125 9 CC_RESET 830 3 GHz 125 A i Icc Stop Grant 10 11 12 SONT 840 830 820 805 3 20 3 2 80 2 66 GHz 65 A Icc Enhanced Halt ENHANOED_HALT 840 830 820 805 3 20 3 2 80 2 66 GHz 50 A Sch Itcc loc TCC active loc A 13 V Vr for 775_VTT_CONFIG_2 processors v 14 15 TI FSB termination voltage DC AC specifications 1 14 1 20 1 26 VTT OUT Ice DC Current that may be drawn from VTT OUT per pin 580 mA ker FSB termination current 4 7 A 12 16 loc_veca loc for PLL lands 120 mA 12 Icc vcciop L Icc for I O PLL land 100 mA 12 ICC_GTLREF loc for GTLREF 200 pA 12 NOTES
121. put G22 D47 Source Synch Input Output J3 FC22 Power Other Input G23 RESET Common Clock Input J4 VSS Power Other G24 TESTHI6 Power Other Input J5 REQ1 Source Synch Input Output G25 TESTHI3 Power Other Input J6 REQ4 Source Synch Input Output G26 TESTHI5 Power Other Input J7 VSS Power Other G27 TESTHI4 Power Other Input J8 VCC Power Other G28 BCLK1 Clock Input J9 VCC Power Other G29 BSELO Power Other Output J10 VCC Power Other G30 BSEL2 Power Other Output J11 VCC Power Other Datasheet Datasheet Table 4 2 Numerical Land Assignment Land Listing and Signal Descriptions Table 4 2 Numerical Land Assignment cam Land Name RAN Direction ia Land Name Weg Cie Direction J12 VCC Power Other L7 VSS Power Other J13 VCC Power Other L8 VCC Power Other J14 VCC Power Other Les VSS Power Other J15 VCC Power Other L24 VSS Power Other J16 DPO Common Clock Input Output L25 VSS Power Other J17 DP3 Common Clock Input Output L26 VSS Power Other J18 VCC Power Other L27 VSS Power Other J19 VCC Power Other L28 VSS Power Other J20 VCC Power Other L29 VSS Power Other J21 VCC Power Other L30 VSS Power Other J22 VCC Power Other Mi VSS Power Other J23 VCC Power Other M2 THERMTRIP Asynch GTL Output J24 VCC Power Other M3 STPCLK Asynch GTL Input J25 VCC Power Other M4 A7 Source Synch Input Output
122. r A19 D61 Source Synch Input Output B30 VTT Power Other A20 RESERVED C1 DRDY Common Clock Input Output A21 VSS Power Other C2 BNR Common Clock Input Output A22 D62 Source Synch Input Output C3 LOCK Common Clock Input Output A23 VCCA Power Other C4 VSS Power Other A24 VSS Power Other C5 Di Source Synch Input Output A25 VTT Power Other C6 D3 Source Synch Input Output A26 VTT Power Other C7 VSS Power Other A27 VTT Power Other c8 DSTBNO Source Synch Input Output A28 VTT Power Other c9 RESERVED A29 VTT Power Other C10 VSS Power Other A30 VTT Power Other C11 D11 Source Synch Input Output B1 VSS Power Other C12 D14 Source Synch Input Output B2 DBSY Common Clock Input Output C13 VSS Power Other B3 RSO Common Clock Input C14 D52 Source Synch Input Output B4 DO Source Synch Input Output C15 D51 Source Synch Input Output B5 VSS Power Other C16 VSS Power Other B6 D5 Source Synch Input Output C17 DSTBP3 Source Synch Input Output B7 D6 Source Synch Input Output C18 D54 Source Synch Input Output B8 VSS Power Other C19 VSS Power Other B9 DSTBPO Source Synch Input Output C20 DBI3 Source Synch Input Output B10 D10 Source Synch Input Output C21 D58 Source Synch Input Output B11 VSS Power Other C22 VSS Power Other B12 D13 Source Synch Input Output C23 VCCIOPLL Power Other Datasheet Datasheet Table 4 2 Numerical Land Assignment Land Listing and Signal Descriptions Table 4 2 Numerical La
123. r Other VCC AM29 Power Other VCC K24 Power Other VCC AM30 Power Other VCC K25 Power Other VCC AM8 Power Other VCC K26 Power Other VCC AM9 Power Other VCC K27 Power Other VCC AN11 Power Other VCC K28 Power Other VCC AN12 Power Other VCC K29 Power Other Datasheet Datasheet Table 4 1 Alphabetical Land Assignments Land Listing and Signal Descriptions Table 4 1 Alphabetical Land Assignments Land Signal Buffer i i Land Signal Buffer i i Land Name Type Direction Land Name Type Direction VCC K30 Power Other VCC U8 Power Other VCC K8 Power Other VCC V8 Power Other VCC L8 Power Other VCC W23 Power Other VCC M23 Power Other VCC W24 Power Other VCC M24 Power Other VCC W25 Power Other VCC M25 Power Other VCC W26 Power Other VCC M26 Power Other VCC W27 Power Other VCC M27 Power Other VCC W28 Power Other VCC M28 Power Other VCC W29 Power Other VCC M29 Power Other VCC W30 Power Other VCC M30 Power Other VCC w8 Power Other VCC M8 Power Other VCC Y23 Power Other VCC N23 Power Other VCC Y24 Power Other VCC N24 Power Other VCC Y25 Power Other VCC N25 Power Other VCC Y26 Power Other VCC N26 Power Other VCC Y27 Power Other VCC N27 Power Other VCC Y28 Power Other VCC N28
124. r Other VSS AA25 Power Other VSS AF13 Power Other VSS AA26 Power Other VSS AF16 Power Other VSS AA27 Power Other VSS AF17 Power Other VSS AA28 Power Other VSS AF20 Power Other VSS AA29 Power Other VSS AF23 Power Other VSS AA3 Power Other VSS AF24 Power Other VSS AA30 Power Other VSS AF25 Power Other VSS AA6 Power Other VSS AF26 Power Other VSS AA7 Power Other VSS AF27 Power Other VSS AB1 Power Other VSS AF28 Power Other VSS AB23 Power Other VSS AF29 Power Other VSS AB24 Power Other VSS AF3 Power Other VSS AB25 Power Other VSS AF30 Power Other VSS AB26 Power Other VSS AF6 Power Other VSS AB27 Power Other VSS AF7 Power Other VSS AB28 Power Other VSS AG10 Power Other VSS AB29 Power Other VSS AG13 Power Other VSS AB30 Power Other VSS AG16 Power Other VSS AB7 Power Other VSS AG17 Power Other VSS AC3 Power Other VSS AG20 Power Other VSS AC6 Power Other VSS AG23 Power Other VSS AC7 Power Other VSS AG24 Power Other VSS AD4 Power Other VSS AG7 Power Other VSS AD7 Power Other VSS AH1 Power Other VSS AE10 Power Other VSS AH10 Power Other VSS AE13 Power Other VSS AH13 Power Other VSS AE16 Power Other VSS AH16 Power Other VSS AE17 Power Other VSS AH17 Power Other VSS AE2 Power Other VSS AH20 Power Other VSS AE20 Power Other VSS AH23 Power Other VSS AE24 Power Other VSS AH24 Power Other VSS AE25 Power Other VSS AH3 Power Other VSS AE26
125. r Other Output VTT_OUT_RIGHT AAT Power Other Output VSS_SENSE AN4 Power Other Output VTT_SEL F27 Power Other Output VSSA B23 Power Other VTTPWRGD AM6 Power Other Input 55 Land Listing and Signal Descriptions 56 Table 4 2 Numerical Land Assignment intel Table 4 2 Numerical Land Assignment a Land Name de jakni Direction ae Land Name all Direction A2 VSS Power Other B13 FC19 Power Other Input A3 RS2 Common Clock Input B14 VSS Power Other A4 D2 Source Synch Input Output B15 D53 Source Synch Input Output A5 D4 Source Synch Input Output B16 D55 Source Synch Input Output A6 VSS Power Other B17 VSS Power Other A7 D7 Source Synch Input Output B18 D57 Source Synch Input Output A8 DBIO Source Synch Input Output B19 D60 Source Synch Input Output AQ VSS Power Other B20 VSS Power Other A10 D8 Source Synch Input Output B21 D59 Source Synch Input Output A11 D9 Source Synch Input Output B22 D63 Source Synch Input Output A12 VSS Power Other B23 VSSA Power Other A13 COMPO Power Other Input B24 VSS Power Other A14 D50 Source Synch Input Output B25 VTT Power Other A15 VSS Power Other B26 VTT Power Other A16 DSTBN3 Source Synch Input Output B27 VTT Power Other A17 D56 Source Synch Input Output B28 VTT Power Other A18 VSS Power Other B29 VTT Power Othe
126. r VSS R28 Power Other VSS H8 Power Other VSS R29 Power Other Datasheet Datasheet Table 4 1 Alphabetical Land Assignments Land Listing and Signal Descriptions Table 4 1 Alphabetical Land Assignments Land Name mm Direction Land Name u m Direction VSS R30 Power Other VTT A25 Power Other VSS R5 Power Other VTT A26 Power Other VSS R7 Power Other VTT A27 Power Other VSS T3 Power Other VTT A28 Power Other VSS T6 Power Other VTT A29 Power Other VSS T7 Power Other VTT A30 Power Other VSS U1 Power Other VTT B25 Power Other VSS U7 Power Other VTT B26 Power Other VSS V23 Power Other VTT B27 Power Other VSS V24 Power Other VTT B28 Power Other VSS V25 Power Other VTT B29 Power Other VSS V26 Power Other VTT B30 Power Other VSS V27 Power Other VTT C25 Power Other VSS V28 Power Other VTT C26 Power Other VSS V29 Power Other VTT C27 Power Other VSS V3 Power Other VTT C28 Power Other VSS V30 Power Other VTT C29 Power Other VSS V6 Power Other VTT C30 Power Other VSS V7 Power Other VTT D25 Power Other VSS WA Power Other VTT D26 Power Other VSS W7 Power Other VTT D27 Power Other VSS Y2 Power Other VTT D28 Power Other VSS Y5 Power Other VTT D29 Power Other VSS NT Power Other VTT D30 Power Other REGULANON AN6 Power Other Output VTT_OUT_LEFT JI Powe
127. ransaction and stops providing internal clock signals to all processor core units except the FSB and APIC units The processor continues to snoop bus transactions and service interrupts while in Stop Grant state When STPCLK is de asserted the processor restarts its internal clock to all units and resumes execution The assertion of STPCLK has no effect on the bus clock STPCLK is an asynchronous input TCK Input TCK Test Clock provides the clock input for the processor Test Bus also known as the Test Access Port TDI Input TDI Test Data In transfers serial test data into the processor TDI provides the serial input needed for JTAG specification support TDO Output TDO Test Data Out transfers serial test data out of the processor TDO provides the serial output needed for JTAG specification support TESTHI 13 0 Input TESTHI 13 0 must be connected to the processor s appropriate power source refer to VTT_OUT_LEFT and VTT_OUT_RIGHT signal description through a resistor for proper processor operation See Section 2 4 for more details THERMDA Other Thermal Diode Anode See Section 5 2 7 THERMDC Other Thermal Diode Cathode See Section 5 2 7 THERMTRIP Output In the event of a catastrophic cooling failure the processor will automatically shut down when the silicon has reached a temperature approximately 20 C above the maximum Te Assertion of THERMTRIP T
128. rder Intel Pentium Intel Xeon Intel NetBurst Intel SpeedStep and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries Other names and brands may be claimed as the property of others Copyright 2005 2006 Intel Corporation 2 Datasheet j ntel e Contents Contents 1 niletfeioj mmm nn re errr err recrecnryrercrcccprerecrrct aS 11 LE ROI OLOGY erect asec ae searches tec i E a i pe e ae a arke 12 1 1 1 Processor Packaging Terminology eaaaaakaa akan 12 UE SEET 13 2 Electrical Specifications isiu david dada nja dai atta nd ati oi 15 2 1 Power and Ground Lands 2 zteeedevsn osovi dakka potanko dada 15 2 2 Decoupling Guidelines aaa kaaa kakaa 15 2 2 4 VOG Ree ne EE 15 222 NTT Decoupling EE 15 2 23 FSBDECOUP NG ME 16 2 3 Voltage kdemficaloN ssni a kad a asd dada 16 2 4 Reserved Unused FC and TESTHI Signals eek aaa 18 2 5 Voltage and Current Specifications eva 19 2 5 1 Absolute Maximum and Minimum Hatngs eee 19 2 5 2 DC Voltage and Current Specifications aaa 19 2 5 3 VCC Overshoot Specification 00 aka 25 2 5 4 Die Voltage Validation a aaa aaa aaa kakaa 26 2 6 SIGNALING SpecificatioS ssec asesan iaiia ddadda a al dean dadaas 26 26 1 FSB Signal Group sceiche 26 2 6 2 GTL Asynchronous Gionals ieira akaa aiaiai aaa aaan aana 28 26 3 FSB DC Specifications AANEREN 29 2 7 eelere Me r
129. red to as the Pentium D processor or simply as the processor The Pentium D processor functions as two physical processors in one package This allows a duplication of execution resources to provide increased system responsiveness in multitasking environments and headroom for next generation multithreaded applications and new usages The Pentium D processor supports all the existing Streaming SIMD Extensions 2 SSE2 and Streaming SIMD Extensions 3 SSE3 Streaming SIMD Extensions 3 SSE3 are 13 additional instructions that further extend the capabilities of Intel processor technology These new instructions enhance the performance of optimized applications for the digital home such as video image processing and media compression technology The processor s Intel NetBurst microarchitecture FSB uses a split transaction deferred reply protocol like the Intel Pentium 4 processor The Intel NetBurst microarchitecture FSB uses Source Synchronous Transfer SST of address and data to improve performance by transferring data four times per bus clock 4X data transfer rate as in AGP 4X Along with the 4X data bus the address bus can deliver addresses two times per bus clock and is referred to as a double clocked or 2X address bus Working together the 4X data bus and 2X address bus provide a data bus bandwidth of up to 6 4 GB s The Pentium D processor includes the Execute Disable Bit capability This feature combined with a supported operati
130. rocessor Datasheet NOTE The airflow of the fan heatsink is into the center and out of the sides of the fan heatsink 89 m Boxed Processor Specifications ntel a 7 1 7 1 1 Mechanical Specifications Boxed Processor Cooling Solution Dimensions This section documents the mechanical specifications of the boxed Pentium D processor The boxed processor will be shipped with an unattached fan heatsink Figure 7 1 shows a mechanical representation of the boxed Pentium D processor Clearance is required around the fan heatsink to ensure unimpeded airflow for proper cooling The physical space requirements and dimensions for the boxed processor with assembled fan heatsink are shown in Figure 7 2 Side View and Figure 7 3 Top View The airspace requirements for the boxed processor fan heatsink must also be incorporated into new baseboard and system designs Airspace requirements are shown in Figure 7 7 and Figure 7 8 Note that some figures have centerlines shown marked with alphabetic designations to clarify relative dimensioning Figure 7 2 Side View Space Requirements for the Boxed Processor Applies to all four side Figure 7 3 Top View Space Requirements for the Boxed Processor 90 views 3 74 ES 95 0 Ch A 3 2 81 3 0 39 0 98 noo E BE 3 74 95 0 D 3 74 95 0 y NOTES 1 Diagram does not show the
131. rrata are available on request Alntel processor numbers are not a measure of performance Processor numbers differentiate features within each processor family not across different processor families Over time processor numbers will increment based on changes in clock speed cache FSB or other features and increments are not intended to represent proportional or quantitative increases in any particular feature Current roadmap processor number progression is not necessarily representative of future roadmaps See http www intel com products processor_number for details Intel Extended Memory 64 Technology Intel EM64T requires a computer system with a processor chipset BIOS operating system device drivers and applications enabled for Intel EM64T Processor will not operate including 32 bit operation without an Intel EM64T enabled BIOS Performance will vary depending on your hardware and software configurations See http www intel com info em64t for more information including details on which processors support EM64T or consult with your system vendor for more information Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a supporting operating system Check with your PC manufacturer on whether your system delivers Execute Disable Bit functionality Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product o
132. rupts allowed 4 Snoop Event Serviced Service snoops to caches v Normal State This is the normal operating state for the processor HALT and Enhanced HALT Powerdown States The Pentium D processor supports the HALT or Enhanced HALT powerdown state The Enhanced HALT Powerdown state is configured and enabled via the BIOS The Enhanced HALT state is a lower power state as compared to the Stop Grant State If Enhanced HALT is not enabled the default Powerdown state entered will be HALT Refer to the sections below for details about the HALT and Enhanced HALT states HALT Powerdown State HALT is a low power state entered when all the logical processors have executed the HALT or MWAIT instructions When one of the logical processors executes the HALT instruction that logical processor is halted however the other processor continues normal operation The processor will transition to the Normal state upon the occurrence of SMI BINIT INIT or LINT 1 0 NMI INTR RESET will cause the processor to immediately initialize itself The return from a System Management Interrupt SMI handler can be to either Normal Mode or the HALT Power Down state See the Intel Architecture Software Developer s Manual Volume III System Programmer s Guide for more information Datasheet 6 2 2 2 6 2 3 Datasheet Features The system can generate a STPCLK while the processor is in the HALT Power Down state Wh
133. s and associated materials Table 3 3 Processor Materials Component Material Integrated Heat Spreader IHS Nickel Plated Copper Substrate Fiber Reinforced Resin Substrate Lands Gold Plated Copper 3 8 Processor Markings Figure 3 5 and Figure 3 6 show the topside markings on the processor for the Pentium D processor 800 sequence These diagrams are to aid in the identification of the Pentium D processor Figure 3 5 Processor Top Side Marking Example Intel Pentium D Processors 840 830 8 Brand Processor Number S Spec Country of Assy Frequency L2 Cache Bus 840 SLxxx COO ije 3 20GHZ 2M 800 05B FPO Unique Unit Identifier 2 D Matrix Mark ATPO Serial 40 Datasheet Package Mechanical Specifications Figure 3 6 Processor Top Side Marking Example Intel Pentium D Processor 805 Datasheet Brand Processor Number S Spec Country of Assy Frequency L2 Cache Bus 775_VR_CONFIG_05x FPO Pb free SLI designator 2 D Matrix Mark INTEL 04 XXXXXXXX 805 SLxxx COO 2 66GHZ 2M 533 05A FPO e4 Unique Unit Identifier ATPO Serial 41 Package Mechanical Specifications n 3 9 Processor Land Coordinates Figure 3 7 shows the top view of the processor land coordinates The coordinates are referred to throughout the document to identify processor lands Figure 3 7 Processor Land Coordinates Top View Voc Ves 30 2
134. s used to protect internal circuits against voltage sequencing issues It should be driven high throughout boundary scan operation REQ 4 0 Input Output REQ 4 0 Request Command must connect the appropriate pins lands of all processor FSB agents They are asserted by the current bus owner to define the currently active transaction type These signals are source synchronous to ADSTBO Refer to the AP 1 0 signal description for a details on parity checking of these signals RESET Input Asserting the RESET signal resets the processor to a known state and invalidates its internal caches without writing back any of their contents For a power on Reset RESET must stay active for at least one millisecond after Vcc and BCLK have reached their proper specifications On observing active RESET all FSB agents will de assert their outputs within two clocks RESET must not be kept asserted for more than 10 ms while PWRGOOD is asserted A number of bus signals are sampled at the active to inactive transition of RESET for power on configuration These configuration options are described in the Section 6 1 This signal does not have on die termination and must be terminated on the system board RS 2 0 Input RS 2 0 Response Status are driven by the response agent the agent responsible for completion of the current transaction and must connect the appropriate pins lands of all processor FSB agents
135. system requirements for the TMA that will be supplied with the boxed Pentium D processor This chapter is particularly important for OEMs that manufacture mainboards for system integrators Unless otherwise noted all figures in this chapter are dimensioned in millimeters and inches in brackets Drawings in this section reflect only the specifications on the boxed Intel processor product These dimensions should not be used as a generic keep out zone for all cooling solutions It is the system designer s responsibility to consider their proprietary cooling solution when designing to the required keep out zone on their system platforms and chassis Refer to the Intel Pentium D Processor and Intel Pentium Processor Extreme Edition 840 Thermal and Mechanical Design Guidelines for further guidance Figure 8 1 Mechanical Representation of the Boxed Processor Datasheet NOTE The duct clip heatsink and fan can differ from this drawing representation however the basic shape and size will remain the same 97 Balanced Technology Extended BTX Type I Boxed Processor Specifications in e ER e 8 1 Mechanical Specifications 8 1 1 Cooling Solution Dimensions This section documents the mechanical specifications of the boxed Pentium D processor TMA The boxed processor will be shippe
136. t A processor with PRB 1 will only boot if its MSIDO pin is electrically low A processor with PRB 0 will ignore this input MSID1 is ignored by the processor PROCHOT Output Input Output For the Pentium D processor PROCHOT can be configured via BIOS as an output or a bi directional signal As an output PROCHOT Processor Hot will go active when the processor temperature monitoring sensor detects that one or both cores has reached its maximum safe operating temperature This indicates that the processor Thermal Control Circuit TCC has been activated if enabled As a bi directional signal assertion of PROCHOT by the system will activate the TCC if enabled for both cores The TCC will remain active until the system de asserts PROCHOT See Section 5 2 3 for more details PWRGOOD Input PWRGOOD Power Good is a processor input The processor requires this signal to be a clean indication that the clocks and power supplies are stable and within their specifications Clean implies that the signal will remain low capable of sinking leakage current without glitches from the time that the power supplies are turned on until they come within specification The signal must then transition monotonically to a high state PWRGOOD can be driven inactive at any time but clocks and power must again be stable before a subsequent rising edge of PWRGOOD The PWRGOOD signal must be supplied to the processor it i
137. t For the boxed processor fan heatsink to operate properly it is critical that the airflow provided to the fan heatsink is unimpeded Airflow of the fan heatsink is into the center and out of the sides of the fan heatsink Airspace is required around the fan to ensure that the airflow through the fan heatsink is not blocked Blocking the airflow to the fan heatsink reduces the cooling efficiency and decreases fan life Figure 7 7 and Figure 7 8 illustrate an acceptable airspace clearance for the fan heatsink The air temperature entering the fan should be kept below 39 C A Thermally Advantaged Chassis with an Air Guide 1 1 is recommended to meet the 39 C requirement Again meeting the processor s temperature specification is the responsibility of the system integrator The processor fan is the primary source of airflow for cooling the Vcc voltage regulator Dedicated voltage regulator cooling components may be necessary if the selected fan is not capable of keeping regulator components below maximum rated temperatures 93 m Boxed Processor Specifications ntal a Figure 7 8 Boxed Processor Fan Heatsink Airspace Keepout Requirements side 2 view 94 Datasheet m l ntel e Boxed Processor Specifications R 7 3 2 Variable Speed Fan If the boxed processor fan heatsink 4 pin connector is connected to a 3 pin motherboard header it will operate as follows The boxed processor fan will operate at different speeds
138. through the use of an ASIC located on the motherboard that sends out a PWM control signal to the 4th pin of the connector labeled as CONTROL The fan speed is based on the actual processor temperature instead of internal ambient chassis temperatures If the new 4 pin active fan heat sink solution is connected to an older 3 pin baseboard processor fan header it will default back to a thermistor controlled mode This allows compatibility with existing 3 pin baseboard designs Under thermistor controlled mode the fan RPM is automatically varied based on the Tier temperature measured by a thermistor located at the fan inlet For more details on specific motherboard requirements for 4 wire based fan speed control see the Intel Pentium D Processor and Intel Pentium Processor Extreme Edition 840 Thermal and Mechanical Design Guidelines Datasheet intel Note Note Balanced Technology Extended BTX Type I Boxed Processor Specifications Balanced Technology Extended BTX Type I Boxed Processor Specifications The Intel Pentium D processor will also be offered as an boxed Intel processor Boxed Intel processors are intended for system integrators who build systems from largely standard components The boxed Intel Pentium D processor will be supplied with a cooling solution known as the Thermal Module Assembly TMA Figure 8 1 shows a mechanical representation of a boxed Pentium D processor This chapter documents mainboard and
139. ti common clock data transfer DRDY may be de asserted to insert idle clocks This signal must connect the appropriate pins lands of all processor FSB agents DSTBN 3 0 Input Output DSTBN 3 0 are the data strobes used to latch in D 63 0 Signals Associated Strobe D 15 0 DBIO DSTBNO D 31 16 DBI1 DSTBN1 D 47 32 DBI2 DSTBN2 D 63 48 DBI3 DSTBN3 DSTBP 3 0 Input Output DSTBP 3 0 are the data strobes used to latch in D 63 0 Signals Associated Strobe D 15 0 DBIO DSTBPO D 31 16 DBI1 DSTBP1 D 47 32 DBI2 DSTBP2 D 63 48 DBI3 DSTBP3 FCx Other FC signals are signals that are available for compatibility with other processors FERR PBE Output FERR PBE floating point error pending break event is a multiplexed signal and its meaning is qualified by STPCLK When STPCLK is not asserted FERR PBE indicates a floating point error and will be asserted when the processor detects an unmasked floating point error When STPCLK is not asserted FERR PBE is similar to the ERROR signal on the Intel 387 coprocessor and is included for compatibility with systems using MS DOS type floating point error reporting When STPCLK is asserted an assertion of FERR PBE indicates that the processor has a pending break event waiting for service The assertion of FERR PBE indicates that the processor should be returned to the Normal state For additional information on
140. tput D50 A14 Source Synch Input Output FC12 AM7 Power Other Output D51 C15 Source Synch Input Output FC16 AN7 Power Other Output D52 C14 Source Synch Input Output FC17 Y3 Power Other Input D53 B15 Source Synch Input Output FC18 AE3 Power Other Input D54 C18 Source Synch Input Output FC19 B13 Power Other Input D55 B16 Source Synch Input Output FC20 E5 Power Other Input D56 A17 Source Synch Input Output FC22 J3 Power Other Input D57 B18 Source Synch Input Output FERR PBE R3 Asynch GTL Output D58 C21 Source Synch Input Output FORCEPR AK6 Asynch GTL Input D59 B21 Source Synch Input Output GTLREF_SEL H29 Power Other Output D60 B19 Source Synch Input Output GTLREFO H1 Power Other Input 47 Land Listing and Signal Descriptions 48 Table 4 1 Alphabetical Land Assignments intal Table 4 1 Alphabetical Land Assignments Land Signal Buffer i i Land Signal Buffer i i Land Name Type Direction Land Name Type Direction GTLREF1 H2 Power Other Input RESERVED N5 HIT D4 Common Clock Input Output RESERVED P5 HITM EA Common Clock Input Output RESERVED G6 IERR AB2 Asynch GTL Output RESET G23 Common Clock Input IGNNE N2 Asynch GTL Input RSO
141. ts Notes GTLREF_PU GTLREF pull up resistor 124 0 99 124 124 1 01 Q 2 GTLREF_PD GTLREF pull down resistor 210 0 99 210 210 1 01 Q 2 On die pullup for _ 3 Tous BOOTSELECT signal 290 2000 Q 60 Q Platform Termination 4 Resistance i 20 58 9 Rrr 50 Q Platform Termination 4 Resistance a 45 se S 60 Q Platform COMP 5 Resistance 59 8 60 4 61 Q A 50 Q Platf COMP Q Platform 5 Resistance 49 9 0 99 49 9 49 9 1 01 Q 60 Q Platform COMP 5 Resistarice 59 8 60 4 61 Q Dee 50 Q Platf COMP Q Platform 5 Resistance 49 9 0 99 49 9 49 9 1 01 Q NOTES RUD 509 or 609 buffer and Ry value g resistors are to Vss Datasheet Unless otherwise noted all specifications in this table apply to all processor frequencies GTLREF is to be generated from Ver by a voltage divider of 1 resistors one divider for each GTLREF land These pull ups are to Vrr Rr is the on die termination resistance measured at V77 2 of the GTL output driver The IMPSEL pin is used to select a COMP resistance must be provided on the system board with 1 resistors COMP 1 0 resistors are to Vss COMP 3 2 31 m Electrical Specifications ntel a 2 7 2 7 1 Clock Specifications FSB Clock BCLK 1 0 and Processor Clocking BCLKI1 0 directly controls the FSB interface speed as well as the core frequency of the processor AS in previous generation processors the Pentium D processor core frequency is a multiple of the BCLK
142. ve a write or implicit writeback data transfer TRDY must connect ihe appropriate pins lands of all FSB agents TRST Input TRST Test Reset resets the Test Access Port TAP logic TRST must be driven low during power on Reset Refer to the eXtended Debug Port Debug Port Design Guide for UP and DP Platforms for complete implementation details VCC VCCA Input Input VCC are the power pins for the processor The voltage supplied to these pins is determined by the VID 5 0 pins VCCA provides isolated power for the internal processor core PLLs VCCIOPLL Input VCCIOPLL provides isolated power for internal processor FSB PLLs VCCPLL VCC_SENSE Input Output VCCPLL is available for compatibility with future processors VCC_SENSE is an isolated low impedance connection to processor core power Vcc It can be used to sense or measure voltage near the silicon with little noise VCC_MB_ REGULATION Output This land is provided as a voltage regulator feedback sense point for Vec It is connected internally in the processor package to the sense point land U27 as described in the Voltage Regulator Down VRD 10 1 Design Guide for Desktop Socket 775 VID 5 0 VSS Output Input VID 5 0 Voltage ID signals are used to support automatic selection of power supply voltages Vcc These are open drain signals that are driven by the processor and must be pulled up on the motherboard R
143. vide a 64 bit data path between the processor FSB agents and must connect the appropriate pins lands on all such agents The data driver asserts DRDY to indicate a valid data transfer D 63 0 are quad pumped signals and will thus be driven four times in a common clock period D 63 0 are latched off the falling edge of both DSTBP 3 0 and DSTBN 3 0 Each group of 16 data signals correspond to a pair of one DSTBP and one DSTBN The following table shows the grouping of data signals to data strobes and DBI Quad Pumped Signal Groups DSTBN DSTBP Input D 63 0 Gelee Data Group DBI D 15 0 0 0 D 31 16 1 1 D 47 32 2 2 D 63 48 3 3 Furthermore the DBI signals determine the polarity of the data signals Each group of 16 data signals corresponds to one DBI signal When the DBI signal is active the corresponding data group is inverted and therefore sampled active high DBI 3 0 Data Bus Inversion are source synchronous and indicate the polarity of the D 63 0 signals The DBI 3 0 signals are activated when the data on the data bus is inverted If more than half the data bits within a 16 bit group would have been asserted electrically low the bus agent may invert the data bus signals for that particular sub phase for that 16 bit group DBI 3 0 Assignment To Data Bus Input DBI 3 0 Outpui Bus Signal Data Bus Signals DBI3 D 63 48 DBI2 D 47 32 DBI1 D 31 16 DBIO D 15 0
144. ystems that do not alter the fan speed only need to ensure the case temperature meets the thermal profile specifications To determine a processor s case temperature specification based on the thermal profile it is necessary to accurately measure processor power dissipation Intel has developed a methodology for accurate power measurement that correlates to Intel test temperature and voltage conditions 75 m Thermal Specifications and Design Considerations ntal a 76 Refer to the Intel Pentium D Processor and Intel Pentium Processor Extreme Edition 840 Thermal and Mechanical Design Guidelines and the Processor Power Characterization Methodology for the details of this methodology The case temperature is defined at the geometric top center of the processor IHS Analysis indicates that real applications are unlikely to cause the processor to consume maximum power dissipation for sustained periods of time Intel recommends that complete thermal solution designs target the Thermal Design Power TDP indicated in Table 5 1 instead of the maximum processor power consumption The Thermal Monitor feature is intended to help protect the processor in the unlikely event that an application exceeds the TDP recommendation for a sustained period of time For more details on the usage of this feature refer to Section 5 2 In all cases the Thermal Monitor feature must be enabled for the processor to remain within specification Table 5 1 Proc

Intel Pentium D 840

Contents

Download Pdf Manuals

Related Search

Related Contents