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pro.point 10.8V Li-ION Specifications

1. 8 1 0 10 6 2 0 10 79 83 311 327 000000 0 50 BSC RECOMMENDED SOLDER PAD LAYOUT 12345 6 7 8 9 1011 12 13 14 15 16 17 18 19 20 21 22 23 24 1 10 6 0 62 T0368 DAA 0433 236 244 us 1 je 8 Y C i gt n 0 50 0 17 0 27 2 0100 0 09 0 20 045 079 _ f 0197 7 i Ie 0067 0106 005 045 emm 0035 008 018 029 BSC TYP 002 006 NOTE 1 CONTROLLING DIMENSION MILLIMETERS MILLIMETERS 2 DIMENSIONS ARE IN INCHES 3 DRAWING NOT TO SCALE DIMENSIONS DO NOT INCLUDE MOLD FLASH MOLD FLASH SHALL NOT EXCEED 152mm 006 PER SIDE DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH INTERLEAD FLASH SHALL NOT EXCEED 254mm 010 PER SIDE 1760f Information furnished by Linear Technology Corporation is believed to be accurate and reliable y LIFIEAD However no responsibility is assumed for its use Linear Technology Corporation makes no represen 4 TECHNOLOGY tation that the interconnection of its circuits as described herein will not infringe on existing patent rights LTC 1760 PART NUMBER DESCRIPT
2. 60 TIME MINUTES 80 100 120 140 16 BAT1 INITIAL CAPACITY 0 BAT2 INITIAL CAPACITY 90 PROGRAMMED CHARGER CURRENT 3A PROGRAMMED CHARGER VOLTAGE 16 8V Current ChargingCurrent mA 60 3500 3000 2500 gt LNSHHND AYALLVE e e v 0 0 1760 604 Charging Current Accuracy 12 0 11 0 10 0 800 1600 2400 3200 ChargingCurrent mA 4000 1760 602 Dual Battery Discharge Time vs Sequential Battery Discharge Li lon V BATTERY VOLTAGE 9 0 8 0 UENTIAL 0 20 40 60 80 100 120 140 160 180 TIME MINUTES BATTERY TYPE 10 8V Li lon MOLTECH NI2020 LOAD CURRENT 3A 1760 605 BATTERY VOLTAGE V 3500 3000 2500 2000 15 14 13 12 11 10 15 14 13 12 11 10 Dual Battery Charge Time vs Sequential Battery Charging SEQUENTIAL BAT CURRENT CURRENT DUAL 100 MINUTES 50 100 150 TIME MINUTES 200 250 300 BATTERY TYPE 10 8V Li Ion MOLTECH NI2020 REQUESTED CURRENT 3A REQUESTED VOLTAGE 12 3V MAX CHARGER CURRENT 4 1A 1760 603 Dual Battery Dischage Time vs Sequential Battery Discharge NiM
3. 18 2 3 4 BIGO NSC EL 19 2 3 5 Batten Mode CAOS EET 19 2 3 6 PERCENT CEDE 19 2 3 7 Current ierit tenerte emerat eunti e n 20 2 3 8 ChargingGurrent ee brem o eedem Sn ied n hacen mpra b d 20 2 3 9 redierit 20 2 930 AlanmWarning CNG sium ancienne acc dere irt dan d tn ara a fid 20 2 3 11 AleMtRESPONSE ccena ORE ERE EROR ERROR FERE ERR CERTE DERE de 21 24 SMBus Dual Port 1 2 2 70 2 00220012 100000000000000000000000 000000000000 tnter tette teretes tas 21 2 5 LTG1760 SMBus Controller ODGratlOl 5 rtr ani a tetuer heces 22 2 6 LTC1760 SMBALERT Operation c cccccscsssscssesescssescscsscscesssesesnssesvesesvssesesssnssssvaveseaveseassneasasaseseavesessesessasseeasavaseuseceseasseeasasaceceseses 24 3 Charging Algorithm Overview ccccssssssesscssssessssssssssesscsssscsssssssssscsessessssessssasassussesscsessassasassussssssssssasensauasssssssscseausssasansassssesseasanees 24 3 1 Wake Up Charging Initiation sese rennen tenente tenete tnter tenens 24 3 2 0 Et 24 3 3 Wake Up Charging Current and Voltage Limits sse tentent nennen 25 3 4 Controlled Cha
4. is the impedance of the battery s thermistor to ground 54 9k RXA 1 13k Sample calculation of Isargryx with Vycco 5 2V Thermistor Impedance Rrux Q Thermistor Range Isaretyx uA 100k OVER RANGE 1 05 3 3k IDEAL RANGE 42 2 400 UNDER RANGE 218 2 Vvcce Riuimit PU pu is the typical pull up impedance at and li irr 34k is the value of the resistance from jit to GND IS the value of the resistance from lj jr to GND is the current used for communicating with the SMBus Host and depends on the amount of bus traffic S the current used for communicating with Battery or Battery2 390u 0 0155 5 425uA IsMBALERT IS defined in Electrical Characteristics sample calculation of Ipci with two Li lon batteries 400 30K Voce 5 2V and no SMBus Host communication cH1 lvcc2 Act Isarety1 2 ISMB 15 BAT _ 2 ISMBALERT 1 3MA 700uA 218uA 218uA 81 81uA QuA 5 4uA 5 4uA OuA 2 62mA The total operating current through BAT1 and BAT2 when AC is not present Noac 1 given by NOAC lvcc2 sarety1 IsareTy2 ISMB 1 BAT1
5. Ifyou are using a dual MOSFET package with both MOSFETs in series you must cut the package power rating in half again and recalculate PMOSFETDUAL 2 AIuax If you use identical MOSFETs for both battery paths voltage drops will track over a wide current range The LTC1760 linear 25mV CV drop regulation will not occur until the current has dropped below 25mV 2 RDS ON MAX However if you try to use the above equation to determine Rps on to force linear mode at full current the MOSFET Rps on Value becomes unreasonably low for MOSFETs available at this time The need for the LTC1760 voltage drop regulation only comes into play for parallel battery configurations that terminate charge or discharge using voltage At first this seems to be a problem but there are several factors helping out RpS ON MAX ILINEARMAX 1 When batteries are in parallel current sharing the current flow through any one battery is less than if it is running stand alone 2 Most batteries that charge in constant voltage mode such as Li ion charge terminate at a current value of 1760f 38 yo TECHNOLOGY LIC 1760 APPLICATIONS INFORMATION C 10 or less which is well within the linear operation range of the MOSFETs 3 Voltage tracking for the discharge process does not need such precise voltage tracking values The LTC1760 has two transient conditions that force the discharge path P channel MOSFETs to have two additional
6. h09 Description This function is used by the LTC1760 to read the actual cell pack voltage Purpose Allows the LTC1760 to determine the cell pack voltage and close the charging voltage servo loop SMBus Protocol Read Word LTC1760 reads Battery 1 or Battery 2 as an SMBus Master Output unsigned integer battery terminal voltage in milli volts Refer to Section 2 2 for bit mapping Units mV Range 0 to 65 535 mV 1760f AL Up 19 LTC 1760 OPERATION 2 3 7 Current 0 Description This function is used by the LTC1760 to read the actual current being supplied through the battery terminals Purpose Allows the LTC1760 to determine how much current a battery is receiving through its terminals and close the charging current servo loop SMBus Protocol Read Word LTC1760 reads Battery 1 or Battery 2 as an SMBus Master Output signed integer 2 s complement charge dis charge rate in mA increments positive for charge nega tive for discharge Refer to Section 2 2 for bit mapping Units mA Range 0 to 32 767 mA for charge or 0 to 32 768 mA for discharge 2 3 8 ChargingCurrent 114 Description This function is used by the LTC1760 to read the Smart Battery s desired charging current Purpose Allows the LTC1760 to determine the maximum charging current SMBus Protocol Read Word LTC1760 reads Battery 1 or Battery 2 as an SMBus Master Output unsigne
7. 5 2 SMBALERT where Igar is defined in Electrical Characteristics lvcc2 aco s defined in Electrical Characteristics Isaretyx is the current used to test the battery thermistor connected to SAFETY1 or SAFETY2 IsaFETYX 2 64 Vycco RXB is the impedance of the battery s thermistor to ground RXB 54 9 Sample calculation of Isargry with Vycco 5 2 Thermistor Impedance Q Thermistor Range Isaretyx 400 UNDER_RANGE 2 9 S the current used for communicat ing with Battery1 or Battery2 when AC in not present 300uA 0 00687 2 404uA is the current used for communicating with the SMBus Host and depends on the amount of bus traffic Sample calculation with two Li lon batteries 400 2 5 2V and no SMBus Host communication IBAT_NOAC lvcc2 Isarety1 2 IsmB SMB_BAT1_AC0 5 2 ISMBALERT 175uA 80uA 2 9uA 2 9uA OuA 2 4uA 2 4uA 265uA 1760f 36 TECHNOLOGY LTC 1760 APPLICATIONS INFORMATION Calculating IC Power Dissipation The power dissipation of the LTC1760 is dependent upon the gate charge of and Qgg Refer to Typical Application The gate charge is determined from the manufacturer s data sheet and is dependent upon both
8. TECHNOLOGY FEATURES SMBus Charger Selector for Two Smart Batteries Voltage and Current Accuracy within 0 2 of Value Reported by Battery Simplifies Construction of Smart Battery System Manager Includes All SMBus Charger V1 1 Safety Features Supports Autonomous Operation without a Host Allows Both Batteries to Discharge Simultaneously into Single Load with Low Loss Ideal Diode SMBus Switching for Dual Batteries with Alarm Monitoring for Charging Battery at All Times Pin Programmable Limits for Maximum Charge Current and Voltage Improve Safety Fast Autonomous Power Path Switching lt 10us Low Loss Simultaneous Charging of Two Batteries gt 95 Efficient Synchronous Buck Charger AC Adapter Current Limiting Maximizes Charge Rate SMBus Accelerator Improves SMBus Timing Available in 48 Lead TSSOP Package APPLICATIONS Portable Computers and Instruments Standalone Dual Smart Battery Chargers Battery Backup Systems AQ LTC 1760 Dual Smart Battery system Manager DESCRIPTION The LTC 1760 Smart Battery System Manager is a highly integrated level 3 battery charger and selector intended for products using dual smart batteries Three SMBus inter faces allow the LTC1760 to servo to the internal voltage and currents measured by the batteries while allowing an SMBus Host to monitor either battery s status Charging accuracy is determined by the battery s internal voltage and current measurement typicall
9. 1 Logic Levels SCL SCL1 SCL2 SDA SDA1 0 8 V SDA2 Input Low Voltage Vi SCL SCL1 SCL2 SDA SDA1 2 1 V SDA2 Input High Voltage Viu SCL SCL1 SCL2 SDA SDA1 Vespa Vspat 8011 5 5 SDA2 Input Leakage Current Vspa 2 0 8V SCL SCL1 SCL2 SDA SDA1 Vspa Vspat 1 Vspa2 5 5 SDA2 Input Leakage Current Vaci 2 2 1V IPULLUP SCL1 SDA1 SCL2 SDA2 Pull Up Vspa1 Vsci Vspa 0 4V 165 220 350 Current When Not Connected to 4 85V and 5 55V Current is Through SMBus Host Internal Series Resistor and Schottky to SCL1 SDA1 SCL2 SDA2 Vespa Vspa2 0 8V 300 Q Series Impedance to Host SMBus SCL SDA Output Low Voltage Vo IPULLUP 350uA 0 4 V LTC1760 Driving the Pin SCL1 SDA1 SCL2 SDA2 Pullup lpuLLup Internal to LTC1760 0 4 V Output Low Voltage VOL LTC1760 Driving the Pin with Battery SMBus not Connected to Host SMBus SCL1 SDA1 SCL2 SDA2 3504A on Host Side 0 4 V Output Low Voltage VoL LTC1760 Driving the Pin with Battery SMBus Connected to Host SMBus 1760f LTC 1760 ELECTRICAL CHARACTERISTICS The e denotes the specifications which apply over the full operating temperature range otherwise specifications are at TA 25 C Vpcin 20V 12V Vear 12V Vypps 3 3V 5 2V unless otherwise noted SYMBOL PARAMETER C
10. 28V 15 35 60 mV GCH1 GCH2 Active Regulation Vacux Vscux 1 5V loc SRO Max Source Current 2 uA loc SNK Max Sink Current 2 VCHMIN BATX Voltage Below Which 3 5 47 V Charging is Inhibited Does Not Apply to Wake Up Mode PowerPath Switches Blanking Period after UVLO Trip Switches Held Off 250 ms Blanking Period after LOPWR Trip Switches in 3 Diode Mode 1 sec toNPO GB10 GB20 GDCO Turn On Time Ves lt 3V from Time of Battery DC e 5 10 uS Removal or LOPWR Indication Cj 3000pF torrPo GB10 GB20 GDCO Turn Off Time Vas gt 1V from Time of Battery DC e 3 i us Removal or LOPWR Indication Cj 3000pF Vpono Output Gate Clamp Voltage ILoap 19A GB10 Highest Vscp 10 4 75 6 25 7 V GB20 Highest Vgaro or Vacp VGB20 4 75 6 25 7 V GDCO Highest Vpcin or Venco 4 75 6 25 7 V Vporro Output Gate Off Voltage ligAp 25uA GB10 Highest Vaar1 or Vscp Vag10 0 18 0 25 V GB20 Highest Vgaro or Vscp 20 0 18 0 25 V GDCO Highest Vpcin Vscp Vapco 0 18 0 25 V PowerPath Switch Reverse Vscp 0r Vscp VpciN e 5 20 60 mV Turn Off Voltage 6V lt 28V Vrp PowerPath Switch Forward VgATX Vscp Vocin e 0 25 50 mV Regulation Voltage 6V lt 28V GDCI GB1I GB2 Active Regulation Note 3 loP SRC Source Current 4 uA loP SNK Sink Current 75 uA 1760f 4 LINEAR LTC 1760 ELECTRICAL CHARACTERISTICS The e den
11. conditions permit charging 1760f eu TECHNOLOGY LTC 1760 OPERATION TERMINATE_CHARGE_RESERVED Bit The read only TERMINATE_CHARGE_RESERVED bit is used by the LTC1760 to determine if charging may con tinue Allowed values are b1 The LTC1760 will not charge this battery b0 The LTC1760 may charge this battery if other conditions permit charging OVER TEMP ALARM Bit The read only OVER TEMP ALARM is used by the LTC1760 to determine if charging may continue Allowed values are b1 The LTC1760 will not charge this battery b0 The LTC1760 may charge this battery if other conditions permit charging TERMINATE DISCHARGE ALARM Bit The read only TERMINATE DISCHARGE ALARM bit is used by the LTC1760 to determine if discharge from the battery is still allowed This is used for power path man agement and battery calibration Allowed values are b1 The LTC1760 will terminate calibration and should try to not use this battery in the power path When all other power paths fail the LTC1760 will ignore this alarm and still try to supply system power from this source 0 The LTC1760 may continue discharging this battery FULLY DISCHARGED Bit The read only FULLY DISCHARGED bit is used by the LTC1760 to determine if discharge from the battery is still allowed This is used for power path management and battery calibration Allowed values are b1 The LTC1760 will terminate calibration and sh
12. setting ripple current is Al 0 4 In no case should Al exceed 0 6 1 due to limits imposed by IREV and 1760f 34 LTC 1760 APPLICATIONS INFORMATION CA1 Remember the maximum Al occurs at the maxi mum input voltage In practice 10uH is the lowest value recommended for use Charger Switching Power MOSFET and Diode Selection Two external power MOSFETs must be selected for use with the LTC1760 charger An N channel MOSFET for the top main switch and an N channel MOSFET for the bottom synchronous switch The peak to peak gate drive levels are set by the Voc voltage This voltage is typically 5 2V Consequently logic level threshold MOSFETs must be used Pay close atten tion to the Bypss specification for the MOSFETs as well many of thelogic level MOSFETs are limited to 30V or less Selection criteria for the power MOSFETs include the ON resistance Rps on reverse transfer capacitance input voltage and maximum output current The LTC1760 charger is always operating in continuous mode so the duty cycles for the top and bottom MOSFETs are given by Main Switch Duty Cycle Vgyt Vin Synchronous Switch Duty Cycle Viy Vout Vin The MOSFET power dissipations at maximum output current are given by Vour Vin Imax 2 1 k Vin Imax Crss f Vin Vour Vin Imax 2 1 Ros on Where SAT is the temperature dependency of R
13. 20 Power Supply for SMBus Accelerators Also used in conjunction with MODE pin to modify the LTC1760 operating mode GND Pin 24 Ground for Low Power Circuitry Pin 25 The Voc Power Supply is used Primarily to Power Internal Logic Circuitry Must be connected to Vec PGND Pin 38 High Current Ground Return for BGATE Driver Vcc Pin 40 Internal Regulator Output Bypass this output with at least a 2uF to 4 7uF capacitor Do not use this regulator output to supply external circuitry except as shown in the application circuit SBS Interface Pins SCL2 Pin 17 SMBus Clock Signal to Smart Battery 2 Do not connect to an external pull up The LTC1760 connects this pin to an internal pull up Ipyi up when required SCL Pin 18 SMBus Clock Signal to SMBus Host Also used to determine flashing rate for stand alone charge indicators Requires an external pullup to Vpps normal SMBus operating mode Connected to internal SMBus accelerator SCL1 Pin 19 SMBus Clock Signal to Smart Battery 1 00 not connect to an external pull up The LTC1760 connects this pin to an internal pull up Ipyi up when required SDA2 Pin 21 SMBus Data Signal to Smart Battery 2 Do not connect to an external pull up The LTC1760 connects this pin to an internal pull up IpuLLup when required SDA Pin 22 SMBus Data Signal to SMBus Host Also used to indicate charging status of Battery 2 Requires an external pullup to Vpps Conn
14. BGATE 6821 11 38 PGND LOPWR 12 37 COMP1 Vsgr 13 36 CLP 14 35 CSP Iser 15 34 CSN DCDIV 16 33 ViIMIT SCL2 17 32 ILimit SCL 18 31 TH1B SCL1 19 30 TH1A Vpps 20 29 SMBALERT SDA2 21 28 TH2A SDA 22 27 TH2B SDA1 23 26 MODE GND 24 25 2 FW PACKAGE 48 LEAD PLASTIC TSSOP Tymax 125 C Oja 110 C W Consult LTC Marketing for parts specified with wider operating temperature ranges ELECTRICAL CHARACTERISTICS The e denotes the specifications which apply over the full operating temperature range otherwise specifications are at TA 25 C 20V 12V Vear 12V Vypps 3 3V Vycc2 5 2V unless otherwise noted SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Supply and Reference DCIN Operating Range DCIN Selected 6 28 V IcHo DCIN Operating Current Not Charging DCIN Selected Note 10 1 1 5 mA lcu Charging DCIN Selected Note 10 1 3 2 mA lvcc2 Voce Operating Current AC Present Note 11 0 75 1 mA lvcc2_aco AC Not Present Note 11 75 100 uA Battery Operating Voltage Range Battery Selected PowerPath Function 6 28 V Battery Selected Charging Function Note 2 0 28 V Battery Drain Current Battery Selected Not Charging Vpciy OV Note 10 175 uA us Diodes Forward Voltage Vrpc DCIN to Vpi us lycc 10mA 0 8 V Veet to Vpi us OMA 0 7 V Vepo BAT2 to ys lycc 0mA 0 7 V VrscN SCN to Vpi us lycc O
15. Forum Smart Battery Data Specification Revision 1 1 SBS Implementers Forum Smart Battery Charger Specification Revision 1 1 SBS Implementers Forum System Management Bus Specification Revision 1 1 SBS Implementers Forum I2C Bus and How to Use it V1 0 Philips Semiconductor 1760f 13 LTC 1760 OPERATION 2 2 Data Bit Definition of Supported SMBus Functions vg 18539 1435399 OV 5 0NOSHSA 911 03 3838 S 5 1NS3d 5 0009 10 3 04 5 zi Imos Q3Au3838 S S INJS3Hd 1909919 1530038 E 2NOISYIA I e 03 3838 S 8 1953991 isanoay avava 8 cNoSHAODI e 03 0383 S 8 live 5 LIGIHNI ONISHVHD 5 gt Q3wBS3M aanuasay S eo m 95 804 98 5 Blo d3MBe3u o 5 a8 61 8 ivdgnvo 5 E 03133933 aanyasay S EZB 0343534 gt 99 1 5 909 5 868 live Ad vmod S Hvd3lvugvo 5 gt Q3MBS3H 03 3838 S 888 5 avgav S 8 jo 0393533 Q3Au3S38 S meg oc 6198 Ad 0 ed alvugnvo e 4 jo 03 83534 aanuasay S vive ad yamdd tvg e je 0 539 939 S 8 live 83534 gt Q3wBS3H aanuasay S ea 5 2178 8 5 5 o
16. MODE and Vpps Levels CONDITION LTC1760 OPERATING MODE Vwopt Vyss SCL Clock for Status Indicators Vvops lt Vit ypps SDA Battery 2 Status SMBALERT Battery 1 Status Vwopt Vvss SCL SDA SMBALERT Normal Operation Vypps gt LTC1760 Charging Inhibited Vwopt Vvss SCL SDA Ignored and May Float Low SMBALERT Normal Operation SCL1 SDA1 SCL2 and SDA2 Normal Operation and Charging is Allowed Vypps lt Vit vpps Vvss Normal Operation on all Pins Charging is Allowed Vypps gt Vit vpps 6 1 Stand Alone Charge Indication When MODE is tied to GND and Vypps lt Vii the function of SDA SMBALERT and SCL are changed as described below SDA is an output and is used to monitor charging status of Battery 2 Allowed valued are Low Battery 2 is charging High Battery 2 not charging AC is not present or battery is not present Blinking Battery 2 charge complete AC is present battery is present and not charging SMBALERT is used to monitor charging status of Bat tery1 Allowed valued are Low Battery 1 is charging High Battery 1 not charging AC is not present or battery is not present Blinking Battery 1 charge complete AC is present battery is present and not charging SCL is an input and is used to determine the blinking rate of SDA and SMBALERT Tie SCL high if blinking is not desired This will provide two different states
17. floating boot strap capacitor C4 This capacitor is normally recharged from Vcc through an external diode when the top MOSFET is turned off As Viy decreases towards the selected battery voltage the converter will attempt to turn on the top MOSFET continuously dropout A dropout timer detects this condition and forces the top MOSFET to turn off and the bottom MOSFET on for about 200ns at 40us intervals to recharge the bootstrap capacitor 7 1 Charge MUX Switches The equivalent circuit of a charge MUX switch driver is shown in Figure 5 If the charger controller is not enabled the charge MUX drivers will drive the gate and source of DCIN 10V CHARGE PUMPED Figure 5 Charge MUX Switch Driver Equivalent Circuit the series connected MOSFETs to a low voltage and the switch is off When the charger controller is on the charge MUX driver will keep the MOSFETs off until the voltage at CSN rises at least 35mV above the battery voltage GCH1 is then driven with an error amplifier EAC until the voltage between BAT1 and CSN satisfies the error amplifier or until GCH1 is clamped by the internal Zener diode The time required to close the switch could be quite long many ms due to the small currents output by the error amp and depending upon the size of the MOSFET switch If the voltage at CSN decreases below Vgar 20mV a comparator CC quickly turns off the MOSFETs to prevent reverse current from flowing in the switches In e
18. of Output voltages This activity is diagrammed in Figure 4 The peak inductor current at which resets the SR latch is controlled by the voltage on is in turn controlled by several loops depending upon the situation 1760f 29 LTC 1760 OPERATION TGATE i gt l torr BGATE OFF eh POINT SET BY VOLTAGE INDUCTOR CURRENT Figure 4 at hand The average current control loop converts the voltage between CSP and BAT to a representative current Error amp CA2 compares this current against the desired current programmed by the Ipac atthe Isgr pin and adjusts for the desired voltage across Rsgysr The voltage at BAT is divided down by an internal resistor divider set by the Vp4c and is used by error amp EA to decrease ly if the divider voltage is above the 0 8V reference The amplifier CL1 monitors and limits the input current normally from the AC adapter to a preset level 100 mV At input current limit CL1 will decrease the voltage and thus reduce battery charging current An over voltage comparator OV guards against transient overshoots gt 7 5 In this case the top MOSFET is turned off until the over voltage condition is cleared This feature is useful for batteries which load dump them selves by opening their protection switch to perform functions such as calibration or pulse mode charging The top MOSFET driver is powered from a
19. the gate voltage swing and the drain voltage swing of the FET fosc Isarety1 ISAFETY2 where IpciN 5 1 2 are defined in the previous section Example Vvec 5 2V Vocin 19V fosc 345kHz 15nC 2 62 1 1 ISAFETY2 218 190mW Capacitors Capacitor C7 is used to filter the delta sigma modulation frequency components to a level which is essentially DC Acceptable voltage ripple at ISET is about 10mVp p Since the period of the delta sigma switch closure is about 10 5 and the internal IDAC resistor is 18 77k the ripple voltage can be approximated by Veer PEE Tax Rser C7 Then the equation to extract C7 is cz Rset 0 8 0 01 18 77k 10us 0 043uF In order to prevent overshoot during start up transients the time constant associated with C7 must be shorter than the time constant of C5 at the pin If C7 is increased to improve ripple rejection then C5 should be increased proportionally and charger response time to average cur rent variation will degrade Capacitors Cp and Cp are used to filter the VDAC delta sigma modulation frequency components to a level which is essentially DC Cg is the primary filter capacitor and CB1 is
20. the common output of the charger MUX switches CSP Pin 35 Current Amplifier CA1 Input This pin and the CSN pin measurethe voltage across the sense resistor to provide the instantaneous current signals re quired for both peak and average current mode operation COMP1 Pin 37 This is the Compensation Node for the Amplifier CL1 A capacitor is required from this pin to GND if input current amplifier CL1 is used At input adapter current limit this node rises to 1V By forcing COMP1 to GND amplifier CL1 will be defeated no adapter current limit COMP1 can source 10uA BGATE Pin 39 Drives the Gate of the Bottom External MOSFET of the Battery Charger Buck Converter SW Pin42 Connected to Source of Top External MOSFET Switch Used as reference for top gate driver BOOST Pin 43 Supply to Topside Floating Driver The bootstrap capacitor is returned to this pin Voltage swing at this pin is from a diode drop below Vec to DCIN Voc TGATE Pin 44 Drives the Gate of the Top External MOSFET of the Battery Charger Buck Converter SCH1 Pin 45 SCH2 Pin 48 Charger MUX Switch Source Returns These two pins are connected to the sources of 03 04 and 09 010 see Typical Applications A small pull down current source returns these nodes to OV when the switches are turned off GCH1 Pin 46 GCH2 Pin 47 Charger MUX Switch Gate Drives These two pins drive the gates of the back to back N channel switch pairs
21. used to provide a zero in the response to cancel the pole associated with Cg Acceptable voltage ripple at Vez is about 10mVp p Since the period of the delta sigma switch closure TA is about 11us and the internal VDAC resistor Ryser is 7 2kQ the ripple voltage can be ap proximated by Tay Ryser C Then the equation to extract Cp Cg is AWstr Veer T Cay Cgo _ RysetAWset Cp should be 10x to 20x Cp to divide the ripple voltage present at the charger output Therefore Cg 0 01 uF and Cp 0 1uF are good starting values In order to prevent overshoot during start up transients the time constant associated with Cg must be shorter than the time constant of C5 at the pin If Cgo is increased to improve ripple rejection then C5 should be increased proportionally and charger response time to voltage variation will degrade Input and Output Capacitors In the 4A Lithium Battery Charger Typical Application section the input capacitor Ciy is assumed to absorb all input switching ripple current in the converter so it must have adequate ripple current rating Worst case RMS ripple current will be equal to one half of output charging current Actual capacitance value is not critical Solid tantalum low ESR capacitors have high ripple current rating in a relatively small surface mount package but caution must be used when tantalum capacitors are used for input o
22. 0 1 0 1 0 1 0 1 0 1 0 110 1 0 1 0 1 0 1 ChargingVoltage Master Read 700001 011 8 h15 Value Nj O iD TID eee ee gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt 0 1 0 1 0 1 0 1 0A 0 1 0 1 0 1 0 1 0 1 0 1 0 110 1 0 1 0 1 0 1 AlarmWarning Master 710001 011 8116 Status e z 5 a gt 6 c5 a ao 35 X CC uu gu dE us SEeEsi eaieege2igeaee SEES 2a Be Se BBB Read 0 1 0A 0 1 0 110 1 0 1 0 1 0 1 0 1 0 1 0 1 0 110 1 0 1 0 1 0 1 AlertResponse Slave Read 7730001 100 N A Register see 1 Byte S S S S S S a a a a a GO a i L LL LAIAL LLAI ee CC cc L L c lt 1 Read byte format h14 is returned as the interrupt address of the LTC1760 1760f nee 15 LTC 1760 OPERATION 2 3 Description of Supported SMBus Functions The functions are described as follows Function Name command code Description A brief description of the function Purpose The purpose of the function and an example where appropriate SMBus Protocol Refer to Section 2 5 and to the SMBus specification for more details Input Output or Input Output A description of the data supplied to or returned by the f
23. 1623 HOST Figure 10 CONDITIONING LOAD 1760 F10 Unique Configuration Information This section summarizes unique LTC1760 configurations that allow some LTC1760 features to be eliminated These configurations may be selected in any combination with out adversely affecting LTC1760 operation Refer to the Typical Application circuit diagram located at the back of this data sheet 1760f 39 LTC 1760 APPLICATIONS INFORMATION A Single Battery Configuration Tolimitthe LTC1760 to a single battery modify the battery slot to be eliminated as follows 1 Remove both FETs Q5 Q6 or Q7 Q8 involved in the charge path 2 Remove both FETS 03 04 or 09 Q10 involved in the discharge path 3 Remove the thermistor sensing resistors R1A R1B or R2A R2B 4 Short the thermistor sense lines together at the IC 5 Remove the diode D2 or D3 as required 6 Unless otherwise specified leave the unused pins of the LTC1760 floating B No Short Circuit Protection Configuration 1 Replace Rsc with a short C No LOPWR Protection 1 Remove resistors R2 and R3 connected to LOPWR and tie LOPWR to the Vec pin D No DC Path Configuration To remove the DC input as part of the power path choices to support the load 1 Remove both FETs Q1 and Q2 involved in the DC path 2 Unless otherwise specified leave the unused pins of the LTC1760 floating E No Charge Configuration To permanentl
24. 20 this pin drives the gate of the P channel switch connected to the BAT2 input CLP Pin 36 This is the Positive Input to the Supply Current Limiting Amplifier CL1 The threshold is set at 100mV above the voltage at the DCIN pin When used to limit supply current a filter is needed to filter out the switching noise Battery Charging Related Pin 13 The Tap Point of a Programmable Resistor Divider which Provides Battery Voltage Feedback to the Charger A capacitor from CSN to and one from Vset to GND provide necessary compensation and filtering for the voltage loop Pin 14 This is the Control Signal of the Inner Loop of the Current Mode PWM Higher corresponds to higher charging current in normal operation A capacitor of atleast 0 1uFto GND filters out PWM ripple Typical full scale output current is 30uA Nominal voltage range for this pin is OV to 2 4V Pin 15 A Capacitor from Isgr to GND is Required to Filter Higher Frequency Components from the Delta Sigma IDAC Pin 32 An external resistor Ry is connected between this pin and GND The value of the external resistor programs the range and resolution of the pro grammed charger current Pin 33 An external resistor Ry jyrr is connected between this pin and GND The value of the external resistor programs the range and resolution of the voltage DAC CSN Pin 34 Current Amplifier CA1 Input Connectthisto
25. 300 TIME MINUTES BATTERY TYPE 10 8V Li lon MOLTECH 2020 REQUESTED CURRENT 3A REQUESTED VOLTAGE 12 3V MAX CHARGER CURRENT 4 1A 1760 TAOS 1760f LTC 1760 ABSOLUTE MAXIMUM RATINGS Note 1 Voltage from DCIN SCP SCN CLP SW to 32V 0 3 V Voltage from SCH1 SCH2 to GND 28V 0 3 V Voltage from BOOST to OND 37V 0 3V CSP CSN BAT1 BAT2 to GND 28V 0 3V LOPWR DCDIV to GND 10V 0 3V Voltage from Veco Vpps to GND 7V 0 3 V SDA1 SDA2 SDA SCL1 SCL2 SCL SMBALERT 7V 0 3V MODE TON setti s Vcco 0 3V 0 3V GOMPT to 5V 0 3V Maximum DC Current Into Pin SDA1 SDA2 SDA SCL1 SCL2 SCL 3mA TELA 5 102uA Operating Ambient Temperature Note 6 0 to 70 C Operating Junction Temperature 40 to 125 C Storage Temperature 65 to 150 C Lead Temperature Soldering 10 sec 300 C PACKAGE ORDER INFORMATION TOP VIEW ORDER PART Vetus 1 48 SCH2 NUMBER BAT2 2 47 GCH2 BAT1 3 46 GCH1 SCN 4 45 SCH1 LTC1760CFW SCP 5 44 TGATE GDCO 6 43 BOOST 6001 7 42 SW GB10 8 41 DCIN GBil 9 40 Voc GB20 10 39
26. 6 0 225 0 5 2 7 0 033 0 241 0 5 3 0 030 0 27 0 5 Values shown above are rounded to nearest standard value Extending System to More than 2 Batteries The LTC1760 can be extended to manage systems with more than 3 sources of power Contact Linear Technology Applications Engineering for more information Charge Termination Issues Batteries with constant current charging and voltage based charger termination might experience problems with reductions of charger current caused by adapter limiting It is recommended that input limiting feature be defeated in such cases Consult the battery manufacturer for information on how your battery terminates charging Setting Charger Output Current Limit The LTC1760 current DAC and the PWM analog circuitry must coordinate the setting of the charger current Failure to do so will result in incorrect charge currents Table 2 Recommended Resistor Values Imax Rsense 2 1 Rsense 1 1 0 100 0 25 0 2 0 05 0 25 10k 3 0 025 0 5 33k 4 0 025 0 5 Open Warning DO NOT CHANGE THE VALUE OF Rj DURING OPERA TION The value must remain fixed and track the Rsense value at all times Changing the current setting can result in currents that greatly exceed the requested value and potentially damage the battery or overload the wall adapter if no input current limiting is provided Setting Charger Output Voltage Limit The value of an exter
27. 6195 1 05 1125 vas 195 1304 Vna snas 1760f 23 LTC 1760 OPERATION 2 6 LTC1760 SMBALERT Operation The SMBALERT pin allows the LTC1760 to signal to the SMBus Host that there has been a change of status This pin is asserted low whenever there is a change in battery presence AC presence or after a power on reset event This pin is cleared during an Alert Response or any of the following reads BatterySystemState BatterySystemStateCont BatterySystemInfo or LTC 3 Charging Algorithm Overview 3 1 Wake Up Charging Initiation The following conditions must be met in order to allow wake up charging 1 The battery thermistor must be COLD RANGE IDEAL RANGE or UNDER RANGE 2 AC must be present 3 BatterySystemStateCont C HARGING_INHIBIT must be de asserted or low 4 Hardware controlled charging inhibit must be de asserted MODE not low with Vpps high Wake up charging initiates when a newly inserted battery does not respond to any LTC1760 master read com mands Only one battery will wake up charge at a time When two batteries are inserted and both require wake up charging Battery 1 will wake up charge first Battery 2 will only wake up charge when Battery 1 terminates wake up charging Wake up charging takes priority over controlled charging this prevents one battery from tying up the charger when it would be advantageous to dual charge two deeply discharged batteries
28. Edge e 250 ns Setup Time tsy par SDA to SCL Falling Edge Hold Time e 300 ns Slave Clocking in Data tup paT ttimeout_sme The LTC1760 will Release the SMBus e 25 35 ms and Terminate the Current Master or Slave Command if the Command is not Completed Before this Time Note 1 Absolute Maximum Ratings are those values beyond which the life of a device may be impaired Note 2 Battery voltage must be adequate to drive gates of power path P channel FET switches This does not affect charging voltage of the battery which can be zero volts during wake up charging Note 3 DCIN BAT2 are held at 12V and GB11 GB2I are forced to 10 5V SCP is set at 12V to measure source current at GDCI GB11 and GB2I SCP is set at 11 9V to measure sink current at GDCI GB11 and GB2l Note 4 Extrapolated from testing with 50pF Note 5 Accuracy dependent upon external sense resistor and compensation components Note 6 The LTC1760C is guaranteed to meet specified performance from 0 C to 70 C and is designed characterized and expected to meet specified performance at 40 C and 85 C but is not tested at these extended temperature limits Note 7 Charger servos to the value reported by a Voltage query This is the internal cell voltage measured by the battery electronics and may be lower than the terminal voltage See Operation Section 3 6 for more information Note 8 C is the combined capacitan
29. GB20 GDCIGDCO CHARGE GCH1 SMBALERT SCH1 GCH2 MODE SCH2 Vpps BAT AC_PRESENT SMBus BAT2 INTERFACE SCL1 VPLUS SDA2 Voc SAFETY SIGNAL DECODER GND DCDIV PowerPath CONTROLLER LOPWR DCIN OSCILLATOR LOW DROP BGATE gt DETECT 0 4155 100mV 0 1760 BD 1760f 11 LTC 1760 TABLE OF CONTENTS For Operation Section 1 13 2 The SMBUS Interface ada rn etm eer nm pedem 13 2 1 SMBus Interface Overview cesscsssscsssssessssesscscsssssssscsssscscscsussesssssassssussesssscssasusassussssesecseassnsaususscsusscseasansasassasssssssensaneasacseseusass 13 2 2 Data Bit Definition of Supported SMBUS Functions c ccccesestesesesceseecesesesnesssescesesvssesssuesssssvssesvesessesesessscsnsaceseseecesessasaneasaceceseeses 14 2 3 Description of Supported SMBus Functions A 16 2 3 1 Batteryoystemotate ors ces sunt rere redii rre reife eed erae de d ee rete ce a 16 2 3 2 BatterysystemstateCont 102 17 2 3 3 BatterySystemlnfo 404 210 30 2 0 0 06000 000 080 08
30. H BAT2 VOLTAGE DUAL BATI VOLTAGE BAT2 SEQUENTIAL 16 INUTES 0 20 40 60 80 100 120 140 TIME MINUTES BATTERY TYPE 12V NiMH MOLTECH NJ1020 LOAD 33W 1760 606 17601 7 LTC 1760 TYPICAL PERFORMANCE CHARACTERISTICS Efficiency vs Charging Current Load Dump Load Regulation 100 14 12 4 90 12 12 3 80 Vin 20V m VDAC 12 29V 12 2 0 IDAC 3000mA E go LOAD CURRENT 1 121 gt z 8 Ta 25 C lt 5 E 50 12 0 o gt 6 gt 40 LOAD 11 9 mE 5 4 CONNECTED E 11 8 Vin 20V 20 LOAD VDAC 12 288V 11 7 IDAC 4000mA 10 DISCONNECTED 25 C 0 116 i 0 0 025 010 050 25 4 0 4 2 0 2 6 8 10 12 14 16 0 1000 2000 3000 4000 lour A TIME ms CHARGE CURRENT mA 1760 G07 1760 G08 1760 G09 Power Path Switching 1 and 2 SMBus Accelerator Operation 16 73 CLoap 20uF Vec 5V 15 TILoap 0 8A 200pF TA 25 C TA 25 C 14 13 CN LTC1760 11 gt 5 10 RuLLup 15k 4 7 9 LOPWR 8 Loto THRESHOLD 7 6 50 40 30 20 10 0 10 20 30 40 50 1us DIV TIME
31. ION COMMENTS LT1571 1 5A Switching Regulator Battery Charger 500kHz or 200kHz Switching Frequency for Small Design LTC1733 Li lon Linear Charger with Thermal Regulation Will Not Overheat Standalone Charger Complete Charger LT1769 2A Switching Regulator Battery Charger Monolithic 20 Lead TSSOP 28 Lead SSOP Packages LTC1960 Dual Battery Charger Selector with SPI 11 Bit Vpac 0 8 Voltage Accuracy 10 Bit for 5 Current Accuracy LTC4006 Small High Efficiency Fixed Voltage Constant Current Constant Voltage Switching Regulator Lithium lon Battery Charger with Termination Timer AC Adapter Current Limit and SafetySignal Sensor in a Small 16 Pin Package LTC4007 High Efficiency Programmable Voltage Complete Charger for 3 or 4 Cell Lithium lon Batteries Battery Charger with Termination AC Adapter Current Limit SafetySignal Sensor and Indicator Outputs LTC4008 High Efficiency Programmable Voltage Constant Current Constant Voltage Switching Regulator Current Battery Charger Resistor Voltage Current Programming AC Adapter Current Limit and SafetySignal Sensor LTC4100 Smart Battery Charger Controller SMBus Rev 1 1 Compliant Linear Technology Corporation 1630 McCarthy Blvd Milpitas CA 95035 7417 408 432 1900 FAX 408 434 0507 www linear com 1760f LT TP 1004 1K PRINTED IN USA TECHNOLOGY LINEAR TECHNOLOGY CORPORATION 2003
32. MA 0 7 V UVLO Undervoltage Lockout Threshold ys Ramping Down Measured at Vp ys to GND e 3 5 V Wee Regulator Output Voltage e 49 5 2 5 5 V VipR Vcc Load Regulation lycc OMA to 10mA e 0 2 1 Switching Regulator VToL Voltage Accuracy With Respect to Voltage Reported by Battery 32 32 mV lt Requested Voltage lt Vi iir 2 LTC 1760 ELECTRICAL CHARACTERISTICS The e denotes the specifications which apply over the full operating temperature range otherwise specifications are at Ty 25 C 20V 12V Vear 12V Vypps 3 3V 5 21 unless otherwise noted SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Iro Current Accuracy With Respect to Current Reported by Battery 4mV Rsense lt Requested Current lt lj Min Note 12 0 Short to GND e 2 2 mA 10k 1 e 4 4 mA 33k 1 e 8 8 mA Rit iir Open or Short lj iir to Voco e 8 8 mA fosc Regulator Switching Frequency 255 300 345 kHz fpo Regulator Switching Frequency in Low Duty Cycle 299 20 25 kHz Dropout Mode DCmax Regulator Maximum Duty Cycle 99 99 5 Maximum Current Sense Threshold Vit 2 2V 140 155 190 mV ISNS CA1 Input Bias Current Vesp gt 5V 150 CMSL CA1 I4 Input Common Mode Low 0 V CMSH CA1 14 Input Common Mode Hig
33. ONDITIONS MIN TYP MAX UNITS SCL SCL1 SCL2 SDA SDA1 SDA2 Vvcc2 OV Vypps OV e 2 uA SMBALERT Power Down Leakage Vect VspA Vspat Vspa2 VSMBALERT 5 5 SMBALERT Output Low Voltage VoL IpuLLup 500uA e 0 4 V SMBALERT Output Pull Up Current VSMBALERT 0 4V 3 5 10 17 5 uA Vit 00 Vpps Input Low Voltage Vii e 1 5 V Vpps Input High Voltage Viu e 2 6 V Operating Voltage e 3 5 5 V Vpps Operating Current Vspa Vypps Vypps 5V 18 Vit MODE MODE Input Low Voltage Vi Vycco 4 85V e Vycc2 0 3 V VIH_MODE MODE Input High Voltage Vvec2 4 85V Vycco 0 7 V MODE Input Current MODE 0 7V 4 85V e 1 1 MODE Input Current lj MODE 0 3V 4 85V e 1 1 Charger Timing trIMEOUT Timeout for Wake Up Charging and e 140 175 210 Sec Controlled Charging tauery Sampling Rate Used by the LTC1760 to 1 sec Update Charging Parameters SMBus Timing SCL Serial Clock High Period tyigu At Iputtup 350uA 150pF Note 8 e 4 us SCL Serial Clock Low Period ti ow At Iputtup 350uA 150pF Note 8 e 4 7 us SDA SCL Rise Time t Ci oap 150pF RPU 9 31k Note 8 1000 ns SDA SCL Fall Time 4 Ci gap 150pF RPU 9 31k Note 8 300 ns SMBus Accelerator Trip Voltage Range e 0 8 1 42 V Start Condition Setup Time tsy srA e 4 7 us Start Condition Hold Time typ sta 4 us SDA to SCL Rising
34. Q3 Q4 and Q9 Q10 between the charger output and the two batteries see Typical Applications External Power Supply Pins Vetus Pin 1 Supply The Vp ys pin is connected via four internal diodes to the DCIN SCN BAT1 and BAT2 pins Bypass this pin with 0 1uF capacitor and a 1uF capacitor See Typical Applications for complete circuit BAT1 Pin 3 Pin 2 These two pins are the inputs from the two batteries for power to the LTC1760 LOPWR Pin 12 LOPWR Comparator Input from Exter nal Resistor Divider Connected from SCN to GND If the voltage at LOPWR pin is lower than the LOPWR com parator threshold then system power has failed and power is autonomously switched to a higher voltage source if available 1760f LTC 1760 PIN FUNCTIONS DCDIV Pin 16 DCDIV Comparator Input from External Resistor Divider Connected from DCIN to GND If the voltage at DCDIV pin is above the DCDIV comparator threshold then the AC_PRESENT bit is set and the wall adapter power is considered to be adequate to charge the batteries If DCDIV is taken more than 1 8V above Vec then all of the power path switches are latched off until all power is removed DCIN Pin 41 Supply External DC power source A 0 1uF bypass capacitor must be connected to this pin as close as possible No series resistance is allowed since the adapter current limit comparator input is also this pin Internal Power Supply Pins Vpps Pin
35. Section 2 2 for bit mapping AC PRESENT Bit The read only PRESENT bit is used to show the user the status of AC availability to power the system It may be used internally by the SMBus Host in conjunction with other information to determine when it is appropriate to allow a battery conditioning cycle Whenever there is a change in the AC status the LTC1760 asserts SMBALERT low In response the system has to read this register to determine the actual presence of AC The LTC1760 uses the DCDIV pin to measure the presence of AC Allowed values are b1 The LTC1760 has determined that AC is present bO The LTC1760 has determined that AC is not present POWER_NOT_GOOD Bit The read only POWER_NOT_GOOD bit is used to show that the voltage delivered to the system load is inadequate This is determined by the comparator on the LOPWR pin Allowed values are b1 The LTC1760 has determined that the voltage delivered to the system load is inadequate b0 The LTC1760 has determined that the voltage delivered to the system load is adequate CALIBRATE_REQUEST_SUPPORT Bit The read only CALIBRATE REQUEST SUPPORT bit is always set to indicate that the LTC1760 has a mechanism to determine when any ofthe attached batteries are in need of a calibration cycle 1760f 17 LTC 1760 OPERATION CALIBRATE_REQUEST Bit The read only CALIBRATE_REQUEST bit is set whenever the LTC1760 has determined that one or m
36. T_GOOD is high 13 The emergency off feature has been asserted using the DCDIV input pin Whenever changing conditions cause either battery to stop charging charging is stopped immediately for all batteries and the voltage and current algorithms are reset to zero Charging is not resumed until all the conditions for controlled charging are met 3 6 Controlled Charging Current and Voltage Programming The LTC1760 monitors the requested and actual current in each battery and increases the programmed current un less one of the following conditions is met a The actual current exceeds the requested current in either battery b The total programmed current equals the maximum of the two requested currents 32 and LTC TURBO is de asserted or low Only one battery is charging and the programmed current equals the requested current lj jyqi7 32 d The total programmed current equals lj The programmed current is updated every tquery It is changed by the difference between the actual and re quested currents LTC TURBO provides a mechanism for the SMBus Host to put additional current into both batteries Normally the LTC1760 will limit the current into both batteries to the maximum ofthe two requested currents lj jy1 32 When LTC TURBO is asserted this restriction is removed allowing the charger to output as much as jur into both batteries Whenever changing conditions cause either battery to st
37. The LTC1760 will attempt to reinitiate wake up charging on both batteries after the SMBus Host asserts BatterySystemStateCont CHARGER POR or a power on reset event This will reset any wake up charging safety timers and is equivalent to removing and reinserting both batteries The LTC1760 will attempt to reinitiate wake up charging on a battery if the battery is not being charged the thermistor is reporting IDEAL RANGE and the battery fails to respond to an SMBus query This is an important feature for handling deeply discharged NiMh batteries These batteries may begin to talk while being charged and go silent once charging has stopped Wake up charging is disabled if the battery thermistor is COLD RANGE or UNDER RANGE and the battery has been charged for longer than tTiMEOUT 3 2 Wake Up Charging Termination The LTC1760 will terminate wake up charging when any of the following conditions are met 1 Battery removal thermistor indicating OVER RANGE 2 AC is removed 3 The SMBus Host issues a calibration request by setting BatterySystemStateCont CALIBRATE high 4 Any response to an LTC1760 master read of ChargingCurrent Current ChargingVoltage or Volt age Note that the LTC1760 ignores all writes from the battery 5 Any of the following AlarmWarning bits asserted high OVER_CHARGED_ALARM TERMINATE_CHARGE_ALARM TERMINATE_CHARGE_RESERVED OVER_TEMP_ALARM Note that the LTC1760 ignores all writes from t
38. W uuu cccscscssesesesescssescsssscsuescsescssesssuescsusssssscsseavasescsusssasassssssasesesseseasasansasavssesceseasassneasaceceseaees 29 6 4 Charging SMBUS HOS 29 7 Battery Charger Controller 29 71 Charge MUX 30 7 2 30 8 PowerPath Controll8r reprehen eidcm t pred ar nn mte iei i P fem orare dane dt 31 8 1 Autonomous PowerPath Switching tentent trennen tente tenens 31 8 2 ctr ete ten tre nr nt e db mn a et EE 31 8 3 Emergency ees 32 8 4 PowerUp Staley sce PO M m 32 9 32 The CurrentDAGBIOCIG sod cerner terere tere 32 1760f 12 LY LTC 1760 OPERATION Refer to Block Diagram and Typical Application Figure 1 Overview The LTC1760 is composed of an SMBus interface with dual port capability a sequencer for managing system power and the charging and discharging of two batteries abattery charger controller charge mux controller power path controller a 10 bit current DAC and 11 bit voltage DAC Vpac When coupled with optional syste
39. Word Input Output word Refer to Section 2 2 for bit mapping SMB_BAT 4 1 The read write SMB_BAT 4 1 nibble is used by the SMBus Host to select with which individual battery to communi cate or to determine with which individual battery it is communicating For example an application that displays the remaining capacity of all batteries would write to this nibble to individually select each battery in turn and get its capacity Allowed values are b0010 SMBus Host is communicating with Battery 2 b0001 SMBus Host is communicating with Battery 1 Power On Reset Value To change this nibble set only one of the lower two bits of this nibble high All other values will simply be ignored POWER_BY_BAT 4 1 The read only POWER_BY_BAT 4 1 nibble is used by the SMBus Host to determine which battery s is powering the system All writes to this nibble will be ignored Allowed values are p0011 System being powered by Battery 2 and Battery 1 simultaneously b0010 System being powered by Battery 2 b0001 System being powered by Battery 1 b0000 System being powered by AC 1760f 16 TECHNOLOGY LIC 1760 OPERATION CHARGE 4 1 The read only CHARGE BAT 4 1 nibble is used by the SMBus Host to determine which if any battery is being charged All writes to this nibble will be ignored Allowed values are b0011 Battery 2 and Battery 1 being charged b0010 Battery 2 is bei
40. abilize and then re verts back tothe PowerPath switch configuration requested by the PowerPath Management Algorithm A power fail counter is incremented to indicate that a failure has oc curred If the power fail counter equals a value of 3 then the the Autonomous PowerPath Controller sets the switches to 3 Diode mode and BatterySystem StateCont POWER_NOT_GOOD will be set provided the LOPWR comparator is still detecting alow power event This is athree strikes and you re out process which is intended to debouncethe POWER NOT GOOD indicator The power fail counter is reset when battery or AC presence change 8 2 Short Circuit Protection Short circuit protection operates in both a current mode and a voltage mode If the voltage between SCP and SCN exceeds the short circuit comparator threshold Vrsc for more than 15ms then all of the PowerPath switches are turned off and BatterySystemState Cont POWER NOT GOOD is set Similarly if the voltage at SCN falls below 3V for more than 15ms then all of the PowerPath switches are turned off and POWER NOT GOODis set high The POWER NOT GOOD bitis reset by removing all power sources and allowing the voltage at Vp ys to fall below the UVLO threshold If the POWER NOT GOOD bit is set charging is disabled until Vpi us exceeds the UVLO threshold and the Charger Algo rithm allows charging to resume When a hard short circuit occurs it might pull all of the power sources down to near OV pote
41. aving a duty cycle value of 1 8 Therefore the maximum output current pro vided by the chargeris 1 8 The delta sigma output gates this low duty cycle signal on and off The delta sigma shift registers are then clocked ata slower rate about 40ms bit so that the charger has time to settle to the 8 value VcsP VcsN Q FROM CA1 TO ITH 54 VALUE MODULATOR 10 BITS 1760 F08 Figure 8 Current Dac Operation 1760f 32 TECHNOLOGY LTC 1760 APPLICATIONS INFORMATION Automatic Current Sharing In a dual parallel charge configuration the LTC1760 does notactually control the current flowing into each individual battery The capacity or Amp Hour rating of each battery determines how the charger current is shared This auto matic steering of current is what allows both batteries to reach their full capacity points at the same time In other words given all other things equal charge termination will happen simultaneously A battery can be modeled as a huge capacitor and hence governed by the same laws C dV dt where The current flowing through the capacitor C Capacity rating of battery using amp hour values instead of capacitance dV Change in voltage dt Change in time The equivalent model of a set or parallel batteries is a set of parallel capacitors Since they are in parallel the change in voltage over change intime is the same for both batte
42. ble and allows the user to perform expanded Smart Battery System Manager functions Purpose Used by the SMBus Host to determine the version of the LTC1760 and to program and monitor TURBO and POWER OFF special functions SMBus Protocol Read or Write Word Input Output word Refer to Section 2 2 for bit mapping POWER OFF Bit This read write bit allows the LTC1760 to turn off all power path sources Allowed values b1 All power path sources are off b0 All power path sources are enabled Power On Reset Value TURBO Bit This read write bit allows the LTC1760 to enter TURBO charging mode Allowed values 1 Turbo Charging mode enabled b0 Turbo Charging mode disabled Power On Reset Value LTC Version 3 0 Nibble This read only nibblealways returns b0001 asthe LTC1760 version 2 3 5 BatteryMode 103 Description This function is used by the LTC1760 to read the Battery Mode register Purpose Allows the LTC1760 to determine if a battery requires a conditioning calibration cycle SMBus Protocol Read Word LTC1760 reads Battery 1 or Battery 2 as an SMBus Master Input Output word Refer to Section 2 2 for bit mapping CONDITION FLAG Bit The CONDITION FLAG bit is set whenever the battery requires calibration Allowed values b1 Battery requires calibration Also known as a Condition Cycle Request 0 Battery does not require calibration 2 3 6 Voltage
43. ce on the host s SMBus connection and the selected battery s SMBus connection Note 9 C is the maximum allowed combined capacitance on THxA THxB and the battery s SafetySignalx connections 6 LTC 1760 ELECTRICAL CHARACTERISTICS Note 10 Does not include current supplied by Vec to Vcco lucco Ac1 OF lvcc2_aco Note 11 Measured with thermistors not present and removed and SMBALERT 1 See Applications Information section Calculating IC Operating Current for example on how to calculate total IC operating current Note 12 Requested currents below 44mV Rsense may not servo correctly due to charger offsets The charging current for requested currents below for values of Rsense 4mV Rsense will be between 4mV Rsense and Requested Current 8mA Refer to Applications Information Setting Charger Output Current Limit Note 13 This limit is greater than the absolute maximum for the charger Therefore there is no effective limitation for the voltage when this option is selected TYPICAL PERFORMANCE CHARACTERISTICS Charging Voltage Accuracy 0 a a Voltage ChargingVoltage mV N 9564 ChargingVo 25 4 700 7132 11996 14428 tage mV 168 1760 601 Dual Charging Batteries with Different Charge State BATTERY VOLTAGE V
44. d integer maximum charger output current in mA Refer to Section 2 2 for bit mapping Units mA Range 0 to 65 534 mA 2 3 9 ChargingVoltage 115 Description This function is used by the LTC1760 to read the Smart Battery s desired charging voltage Purpose Allows the LTC1760 to determine the maximum charging voltage SMBus Protocol Read Word LTC1760 reads Battery 1 or Battery 2 as an SMBus Master Output unsigned integer charger output voltage in mV Refer to Section 2 2 for bit mapping Units mV Range 0 to 65 534 mV 2 3 10 AlarmWarning 116 Description This function is used by the LTC1760 to read the Smart Battery alarm register Purpose Allows the LTC1760to determine the state of all applicable alarm flags SMBus Protocol Read Word LTC1760 reads Battery 1 or Battery 2 as an SMBus Master Output unsigned integer Refer to Section 2 2 for bit mapping OVER CHARGED ALARM Bit Theread only OVER CHARGED ALARM bit is used by the LTC1760 to determine if charging may continue Allowed values are b1 The LTC1760 will not charge this battery b0 The LTC1760 may charge this battery if other conditions permit charging TERMINATE CHARGE ALARM Bit The read only TERMINATE CHARGE ALARM bit is used by the LTC1760 to determine if charging may continue Allowed values are b1 The LTC1760 will not charge this battery b0 The LTC1760 may charge this battery if other
45. d off the two outputs are driven to the higher of the two voltages present across the input SCP terminals of the switch When the switch is instructed to turn on the output side driver immediately drives the gate of the output PFET approximately 6V below the highest of the voltages present atthe input SCP When the output PFET turns on the voltage at SCP will be pulled up to a diode drop below the source voltage by the bulk diode of the input PFET If the source voltage is more than 25mV above SCP EAP will drive the gate of the input PFET low until the input PFET turns on and reduces the voltage across the input SCP to the EAP set point or until the Zener clamp engages to limit the voltage applied to the input PFET If the source voltage drops more than 20mV below SCP then comparator CP turns on SWP to quickly prevent large reverse current in the switch This operation mimics a diode with a low forward voltage drop LES to Loan 1760 F06 Figure 6 PowerPath Driver Equivalent Circuit 8 1 Autonomous PowerPath Switching The LOPWR comparator monitors the voltage at the load through the resistor divider from pin SCN If LTC POWER_OFF is low and the LOPWR comparator trips then all of the switches are turned on 3 Diode mode by the Autonomous PowerPath Controller to ensure that the system is powered from the source with the highest volt age The Autonomous PowerPath Controller waits approxi mately 1second to allow power to st
46. during the dead time which could cost as much as 1 in efficiency A 1A Schottky is generally a good size for 4A regulators due to the relatively small average current Larger diodes can result in additional transition losses due to their larger junction capacitance The diode may be omitted if the efficiency loss can be tolerated Calculating IC Operating Current This section shows how to use the values supplied in the Electrical Characteristics table to estimate operating cur rent for a given application The total IC operating current through DCIN when AC is presentand batteries are charging Ipciy is given by IpciN cH1 lvcc2 Act 1 1 Isargr2 lvLiM ls vB 15 _ 1 5 _ 2 lSMBALERT where Icu1 is defined in Electrical Characteristics s defined in Electrical Characteristics IsareTyy is the current used to testthe battery thermistor connected to SAFETY1 OR SAFETY2 For thermistors that are OVER RANGE ISAFETYX 2 64 Vycco RXB For thermistors that are COLD RANGE Isargrvx 4 64 Vycco RXB 1760f 35 LTC 1760 APPLICATIONS INFORMATION For thermistors that are IDEAL RANGE 1 4 64 Vycco RXB 2 64 Vycco For thermistors that are HOT RANGE IsareTyx 4 64 Vycco RXB 4 64 Vycco
47. ected to internal SMBus accelerator SDA1 Pin 23 SMBus Data Signal to Smart Battery 1 Do not connect to an external pull up The LTC 1760 connects this to an internal pull up when required MODE Pin 26 Used in conjunction with Vpps to allow SCL SDA and SMBALERT to indicate charging status May also be used as a hardware charge inhibit TH2B Pin 27 Thermistor Force Sense Connection to Smart Battery 2 SafetySignal Connect to Battery 2 ther mistor through resistor network shown in Typical Application TH2A Pin 28 Thermistor Force Sense Connection to Smart Battery 2 SafetySignal Connect to Battery 2 ther mistor through resistor network shown in Typical Application SMBALERT Pin 29 Active Low Interrupt Pin Signals SMBus Host that there has been a change of status in battery or AC presence Open drain with weak current source pull up to Vcco with Schottky to allow it to be pulled to 5V externally Also used to indicate charging Status of Battery 1 TH1A Pin 30 Thermistor Force Sense Connection to Smart Battery 1 SafetySignal Connect to Battery 1 ther mistor through resistor network shown in Typical Application TH1B Pin 31 Thermistor Force Sense Connection to Smart Battery 1 SafetySignal Connect to Battery 1 ther mistor through resistor network shown in Typical Application 1760f 10 TECHNOLOGY LTC 1760 BLOCK DIAGRAM 68116810 GB2I
48. eeded True analog control is used with closed loop feedback ensuring that adapter load current remains within limits Amplifier CL1 in Figure 9 senses the voltage across connected between the CLP and DCIN pins When this voltage ex ceeds 100mV the amplifier will override programmed charging current to limit adapter current to 100mV Rcj A lowpass filter formed by 5kQ and 0 1uF is required to eliminate switching noise If the current limit is not used CLP should be connected to DCIN AC ADAPTER INPUT Vin 1760 F09 100mV Reo MA ADAPTER CURRENT LIMIT Figure 9 Setting Input Current Limit To set the input current limit you need to know the minimum wall adapter current rating Subtract 5 for the input current limit tolerance and use that current to deter mine the resistor value Re 100mV li iw lii y Adapter Min Current Adapter Min Current 5 1760f AY MER 33 LTC 1760 APPLICATIONS INFORMATION As is often the case the wall adapter will usually have at leasta 10 current limit margin and many times one simply set the adapter current limit value to the actual adapter rating see Table 1 Table 1 Common Rc Resistor Values Adapter RCL Value RCL Power RCL Power Rating A 2 1 Dissipation W Rating W 1 5 0 06 0 135 0 25 1 8 0 05 0 162 0 25 2 0 045 0 18 0 25 2 3 0 039 0 206 0 25 2 5 0 03
49. erySystem State POWER BY BAT 4 1 interprets power path conditions Power Reporting for Batteries Being Calibrated AC PRESENT CALIBRATE BAT2 CALIBRATE 2 BY BAT 4 1 1 0 0 130000 1 0 1 730001 1 1 0 130010 States not shown not allowed Power Reporting as a Function of Battery Presence AC PRESENT PRESENT BAT2 PRESENT BAT1 POWER BY BAT 4 1 1 X X b0000 0 0 0 b0000 0 0 1 b0001 0 1 0 b0010 0 1 1 b0011 Power Reporting with PRESENT Low and both Batteries Present as a Function of Power Alarms BATTERY 2 BATTERY 1 POWER ALARM POWER ALARM AC PRESENT NOTE 1 NOTE 1 POWER BY BAT 4 1 0 0 0 b0011 0 0 1 b0010 0 1 0 b0001 0 1 1 b0011 1 X X 130000 Note 1 A power alarm means that ALARM has returned TERMINATE_DISCHARGE 1 or FULLY_DISCHARGED_ALARM 1 Power Reporting When BatterySystemStateCont POWER_NOT_GOOD is High and the LTC1760 has Autonomously Entered 3 Diode Mode AC PRESENT PRESENT BAT2 PRESENT BAT1 POWER BY BAT 4 1 0 0 0 b0000 0 0 1 b0001 0 1 0 b0010 0 1 1 b0011 1 0 0 130000 1 0 1 130000 1 1 0 130000 1 1 1 130000 17601 LI MER 27 LTC 1760 OPERATION 5 Battery Calibration Conditioning Calibration allows the SMBus Host to fully discharge a battery for conditioning purposes The SMBus Host may determine the battery to be d
50. f 8 Jo 034338 Q3 u3S38 S cc 61 8 8 5 e je 03wBS3M Q3 43838 S 71 8 8 5 0343534 e Jo 30 43 04 aaAyasay 5 solze zg E ee 5 SEIZE Se 5 Ze 5 ba 58 aS E E g e E 2 2 2 5 2 EIE s g N 56 ARE 88 2 cs ac c e wa na 5 5 pc E E 5 EA 5 5 85 A A A JE 5 E 1760f LY 14 LTC 1760 OPERATION Data Bit or Nibble Definition Allowed Values LTC1760 SMBus Command Data See section 2 3 for Details Function Mode Access Address Code Type 015 014 013 012 011 010 009 008 007 006 005 004 003 002 001 000 Current Master Read 7 00001_011 8 h0a Value lt 2 2 2 3 2 0 1 0 1 0 1 0 11 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 110 1 0 1 0 1 0 1 Voltage Master Read 700001 011 8109 Value C O Are iD TION C lt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt 0 1 0 1 0 1 0 1 0A 0 1 0 1 0 1 0 1 0 1 0 1 0 110 1 0 1 0 1 0 1 ChargingCurrent Master Read 7 b0001 011 8714 Value O C OIN qo O TIO N C 07 0 A CO C C Cc Sf eee BE eee ec SEE 0 1 0 1 0 1 0 110 1 0 1
51. g calibrated CALIBRATE must be 1 b0001 Battery 1 is being calibrated CALIBRATE must be 1 b0000 No batteries are being calibrated Allowed write values are b0010 Select Battery 2 for calibration b0001 Select Battery 1 for calibration b0000 Allow LTC1760 to choose battery to be calibrated All other values will simply be ignored This provides a mechanism to update the other BatterySystemStateCont bits without altering this nibble 2 3 3 BatterySysteminfo h04 Description The SMBus Host uses this command to determine the capabilities of the LTC1760 Purpose Allows the SMBus Host to determine the number of batteries the LTC1760 supports as well as the specifica tion revision implemented by the LTC1760 SMBus Protocol Read Word Input Output word Refer to Section 2 2 for bit mapping BATTERIES SUPPORTED Nibble The read only BATTERIES SUPPORTED nibble is used by the SMBus Host to determine how many batteries the LTC1760 can support The two battery LTC1760 always returns b0011 for this nibble 1760f 18 TECHNOLOGY LTC 1760 OPERATION BATTERY_SYSTEM_REVISION Nibble The read only BATTERY_SYSTEM_REVISION nibble re ports the version of the Smart Battery System Manager Specification supported LTC1760 returns b1000 for this nibble indicating Version 1 0 without optional PEC support 2 3 4 LTC h3c Description This function returns the LTC Version nib
52. h 0 2 V Vout CL1 Turn On Threshold 95 100 105 mV e 94 100 108 mV TGATE Transition Time TG t TGATE Rise Time Ci oap 3300pF 10 to 90 50 90 ns TG t TGATE Fall Time CLoap 3300pF 10 to 90 50 90 ns BGATE Transition Time BG tr BGATE Rise Time CLoap 3300pF 10 to 90 50 90 ns BG t BGATE Fall Time CLoap 3300pF 10 to 90 40 80 ns Trip Points VIR DCDIV LOPWR Threshold Vpcpiv OF Falling 1 166 1 19 1 215 V Vruvs DCDIV LOPWR Hysteresis Voltage Vpcpiv Vi oewn Rising 30 mV lgyr DCDIV LOPWR Input Bias Current OF Vi opwn 1 19V 20 200 nA Short Circuit Comparator Threshold Vscp Vsen Vec 5V e 90 100 115 mV Veto Fast Power Path Turn Off Threshold Vpcpiv Rising from 6 7 7 9 V Vovsp Overvoltage Shutdown Threshold as a Rising from 0 8V until TGATE BGATE 107 Percent of Programmed Charger Voltage Stop Switching DACs Ins Ipac Resolution Guaranteed Monotonic 10 Bits Ipac Pulse Period lip Normal Mode 6 10 15 us tii ow Wake Up Mode 50 ms Charging Current Granularity Short to GND 1 mA 10k 1 2 mA 33k 1 4 mA Open or Short limit to Veco 4 mA IWAKE UP Wake Up Charging Current Note 5 60 80 100 mA Charging Current Limit 0 Short to GND e 980 1000 1070 mA 10k 1 e 1960 2000 2140 mA 33k 1 e 2490 3000 3210 mA Open or Short limit to Veco e 3920 4000 4280
53. he battery Each battery s charge alarm is cached inside the LTC1 760 This bit will be set when any of the upper four bits of the battery s AlarmWarning response are set This bit will remain set if a subsequent AlarmWarning fails to re spond The cached alarm will be cleared by any of the following conditions a Associated battery is removed b A subsequent AlarmWarning clears all charge alarm bits for the associated battery C A power on reset event d The SMBus Host asserts BatterySystemStateCont CHARGER POR high 1760f 24 TECHNOLOGY LIC 1760 OPERATION 6 An SMBus Host write asserts the LTC1760 BatterySystemStateCont CHARGING_INHIBIT high 7 Hardware controlled charging inhibit is asserted MODE low with Vpps high 8 The thermistor of the battery being charged indicates COLD RANGE and the battery has been charged for longer than timeout 9 The thermistor of the battery being charged indicates UNDER RANGE and the battery has been charged for longer than tTIMEOUT 10 The thermistor of the battery being charged indicates HOT RANGE 11 Any SMBus communication line is grounded for longer than tquery 12 BatterySystemStateCont POWER_NOT_GOOD is high 13 The emergency off feature has been asserted using the DCDIV input pin 3 3 Wake Up Charging Current and Voltage Limits The wake up charging current is fixed at Iwaxe yp for all values of lj Wake up charging uses the
54. ious section to preserve battery intended for calibra tion The SMBus Host must only set the calibration bit once per calibration TheLTC1760 will discharge the selected battery as long as the calibration is in progress CALIBRATE high Updates to the cached BatteryMode CONDITION FLAG will be inhibited while CALIBRATE is asserted This means that discharge of the battery will continue even if the battery clears the CONDITION FLAG 5 3 Terminating Calibration of Selected Battery Calibration will end when CALIBRATE is cleared CALI BRATE will be cleared when AC is removed The battery being calibrated is removed When the battery being calibrated is removed the LTC1760 will automatically calibrate the other battery if it is requesting calibration e BatterySystemStateCont POWER NOT GOOD is high The battery sets Alarm Warning TERMINATE DISCHARGE high The battery sets Alarm Warning FULLY DISCHARGED high A zero is written to the CALIBRATE bit TheLTC1760 will attemptto initiate a charge cycle after the discharge cycle is completed 1760f 28 TECHNOLOGY LTC 1760 OPERATION 6 MODE Pin Operation The MODE pin is a multifunction pin that allows the LTC1760 to 1 display charging status in stand alone Operation 2 activate hardware charge inhibit 3 charge when SCL and SDA are low and 4 charge with an SMBus Host Summary of SDA SCL and SMBALERT Operation as a Function of
55. ischarged or allow the LTC1760 to choose based on the batteries request to be conditioned 5 1 Selecting a Battery to be Calibrated Option 1 SMBus Host chooses battery to be calibrated using BatterySystemStateCont CALIBRATE_BAT 4 1 Allowed values b0001 Set CALIBRATE_BAT1 Only has an effect if Battery 1 BatteryMode CONDITION FLAG is high May not be updated if a calibration is in progress b0010 Set CALIBRATE_BAT2 Only has an effect if Battery 2 BatteryMode CONDITION FLAG is high May not be updated if a calibration is in progress b0000 Clears CALIBRATE_BAT1 and CALIBRATE BAT2andallows LTC1760to chose Power on reset default May not be updated if a calibration is in progress Option 2 SMBus Host allows LTC1760 to choose battery to be calibrated BatterySystemStateCont CALIBRATE BAT 4 1 00000 See previous option TheLTC1760 determines that the battery requires calibra tion by reading BatteryMode CONDITION FLAG This flag is cached in the LTC1760 The LTC1760 sets BatterySystemStateCont CALIBRATE REQUEST high TheLTC1760 will always select the battery that is request ing calibration If both batteries are requesting calibration the LTC1760 will select Battery 1 If neither battery is requesting calibration then calibration cannot occur 9 2 Initiating Calibration of Selected Battery The SMBus Host initiates a calibration by writing to BatterySystemStateCont CALIBRATE Follow rules of the prev
56. lock shift register afterthe rising SCL edge Datais clocked out ofthe SMBus Control block shift register after the falling edge of SCL The LTC1760 acting as a slave will acknowledge ACK each byte of serial data The Command byte will be NACKed if an invalid command code is transmitted to the LTC1760 The SMBus Controller must respond if ad dressed as a combined Smart Battery System Manager Address 14 A valid address includes a legal Read Write bit The SMBus Controller will ignore invalid data although the data transmission with the invalid data will still be ACK ed When the LTC1760 acting as a bus master receives a NACK it will terminate the transmission and provide a STOP condition on the bus Detection of a STOP condition power on reset or SMBus time out will reset the controller to an initial state at any time The LTC1760 supports ARA Word Write and Word Read protocols as an SMBus slave The LTC1760 supports Word Read protocol as an SMBus master Refer to System Management Bus Specification for complete description of required operation and symbols 22 LTC 1760 OPERATION q 5 Juang paysanbay 104 Z Ag Mayeg 09 1911 aunbl4 19 190 WN SnglNS S S S 1198 S S a q uoneanBijuo9 2 10 peau e sajajduio eju 1 YM uonearunuiuo 5921915 09 1211 2 841614 9705
57. low current mode described in Section 10 The wake up charging voltage is not limited by the Vi jr function 3 4 Controlled Charging Initiation All of the following conditions must be met in order to allow controlled charging of a given battery One or both batteries may be control charged at a time 1 The battery thermistor must be COLD RANGE IDEAL RANGE or UNDER RANGE 2 AC must be present 3 BatterySystemStateCont C HARGING_INHIBIT must be de asserted or low 4 Hardware controlled charging inhibit must be de asserted MODE not low with Vpps high 5 The battery responds to an LTC1760 master read of Alarm with all charge alarms deasserted 6 The battery responds to an LTC1760 master read of ChargingVoltage with a non zero voltage request value 7 The battery responds to an LTC1760 master read of Voltage 8 The battery responds to an LTC1760 master read of ChargingCurrent with a non zero current request value 9 The battery responds to an LTC1760 master read of Current The following charging related functions are polled each Alarm ChargingVoltage Voltage ChargingCurrent and Current 3 5 Controlled Charging Termination The LTC1760 will terminate controlled charging when any of the following conditions are met 1 Battery removal or thermistor indicating OVER RANGE 2 AC removal 3 The SMBus Host issues a calibration request by setting BatterySystemS
58. lowed when POWER OFF is asserted high 4 2 Power By Algorithm When No Battery is Being Calibrated The LTC1760 will always attempt to maintain system power The preferred configuration isto remain in 3 Diode mode In 3 Diode mode power will be provided by BAT1 BAT2 and DCIN with the source at the highest voltage potential automatically providing all the power Sources at similar voltage potentials will share power based on their capacity Thefollowing conditions will causethe LTC1760to modity its preferred power by algorithm 1 A battery issues a terminate discharge alarm and PRESENT is high The LTC1760 will select the other battery and DCIN to power the system 2 A battery issues a terminate discharge alarm and AC PRESENT is low LTC1760 will select the other battery to power the system 3 A battery issues a terminate discharge alarm PRESENT is low and the other battery is not present or has previously alarmed The LTC1760 will autono mously try to restore power by entering 3 Diode mode The 3 Diode mode will ignore TERMINATE DISCHARGE and FULLY DISCHARGED alarms 4 3 Power By Algorithm When a Battery is Being Calibrated During battery calibration the battery being calibrated is the only device powering the system This will be reflected in the reported POWER BY 4 1 bits See Section 5 for more information on battery calibration 4 4 Power By Reporting The following tables illustrate how Batt
59. lse rating will allow the MOSFET to blow to the open circuit condition instantly like a fuse Typically there is no outward sign of failure because it happens so fast Please measure the surge current for all discharge power paths under worse case conditions and consult the MOSFET data sheet for the limitations Voltage sources with the highest voltage and the most bulk capacitance are often the biggest risk Specifically the MOSFETs in the wall adapter path with wall adapters of high voltage large bulk capacitance and low resistance DC cables between the adapter and device are the most common failures Remember to on yuse the rea wall adapter with a produc tion DC power cord when performing the wall adapter path test The use of alaboratory power supply is unrealistic for this test and will force you to over specify the MOSFET ratings A battery pack usually has enough series resis tance to limit the peak current or are too low in voltage to create enough instantaneous power to damage their re spective power path MOSFETs Conditioning Systems With Large Loads In systems where the load is too large to be used for conditioning a single battery it may be necessary to bypass the built in calibrate function and simply switch in an external load A convenient way to accomplish this task is by using an SMBus based LTC 1623 load switch control ler See Figure 10 PowerPath TO MUX LOAD CHARGE 1701760 SMBus I SMBus TO FROM LTC
60. m software for generating composite battery information it forms a complete Smart Battery System Manager for charging and selecting two smart batteries The battery charger is controlled by the sequencer which uses the level 3 SMBus interface to read ChargingVoltage Volt age ChargingCurrent Current Alarm and BatteryMode This information together with thermistor measurements allows the sequencer to select the charg ing battery and safely servo on voltage and current Charging can be accomplished only if the voltage at DCDIV indicates that sufficient voltage is available from the input power source usually an AC adapter The charge mux which selects the battery to be charged is capable of charging both batteries simultaneously The charge mux switch drivers are configured to allow charger current to share between the two batteries and to prevent current from flowing in a reverse direction in the switch The amount of current that each battery receives will depend upon the relative capacity of each battery and the battery voltage This can result in significantly shorter charging times up to 50 for Li lon batteries than sequential charging of each battery The sequencer also selects which of the pairs of PFET switches will provide power to the system load If the system voltage drops below the threshold set by the LOPWR resistor divider then all of the output side PFETs are turned on quickly The input side PFETs act as di
61. mA VRES Vpac Resolution Guaranteed Monotonic 5V lt Vgar lt 25V 11 Bits 1760f AY MER LTC 1760 ELECTRICAL CHARACTERISTICS The e denotes the specifications which apply over the full operating temperature range otherwise specifications are at Ty 25 C Vpein 20V Vgar 12V Vegart 12V Vypps 3 3V 5 2V unless otherwise noted SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Vpac Granularity 16 mV VLIMIT Charging Voltage Limit 9 Short Vi yr to GND e 9400 8432 8464 mV Vote 7 10k 1 e 12608 12640 12672 mV 33k 1 e 16832 16864 16896 mV 100k 1 21024 21056 21088 mV Open or Short Vi to Vcco Note 13 32768 mV Charge Mux Switches toNC GCH1 GCH2 Turn On Time Vscux gt 3V Ci oAD 3000pF 5 10 ms torre GCH1 GCH2 Turn Off Time Vacux Vscux lt 1V from Time of 15 us lt Veatx 30mV 3000pF VcoN CH Gate Clamp Voltage GCH1 5 5 8 7 GCH2 Vech Vscue 5 5 8 7 CH Gate Off Voltage 10uA GCH1 0 8 0 4 0 V GCH2 Vech 0 8 0 4 0 V Vroc CH Switch Reverse Turn Off Voltage OV 28V 5 20 40 Vrc CH Switch Forward Regulation Voltage VcsN Vparx OV Vgarx
62. nal resistor connected from the pin to GND determines one of five voltage limits that are applied to the charger output value See Table 3 These limits provide a measure of safety with a hardware restric tion on charging voltage which cannot be overridden by software This voltage sets the limit that will be applied to the battery as reported by battery Since the battery internal voltage monitor pointis the actual cell voltage you may see higher voltages up to 512mV higher at the external charger terminals due to the voltage servo loop action See Operations section 3 6 for more information on the voltage servo system Table 3 Recommended Resistor Values for Ryj iw Vmax Ryu 1 Up to 8 4V 0Q Short to ground Up to 12 6V 10k Up to 16 8V 33k Up to 21 0V 100k Up to 32 7V No Limit Open or short to Inductor Selection Higher operating frequencies allow the use of smaller inductor and capacitor values A higher frequency gener ally results in lower efficiency because of MOSFET gate charge losses In addition the effect of inductor value on ripple current and low current operation must also be considered The inductor ripple current Al decreases with higher frequency and increases with higher Viy 1 Al m ViN Accepting larger values of Al allows the use of low inductances but results in higher output voltage ripple and greater core losses A reasonable starting point for
63. ng charged b0001 Battery 1 is being charged b0000 No Battery being charged An indication that multiple batteries are being charged simultaneously does not indicate that the batteries are being charged at the same rate or that they will complete their charge at the same time To actually determine when an individual battery will be fully charged use the SMB BAT 4 1 nibble to individually select the battery of interest and read the TimeToFull value PRESENT BAT 4 1 The read only PRESENT BAT 4 1 nibble is used by the SMBus Host to determine how many and which batteries are present All writes to this nibble will be ignored Allowed values are b0011 Battery 2 and Battery 1 are present b0010 Battery 2 is present b0001 Battery 1 is present b0000 No batteries are present 2 3 2 BatterySystemStateCont h02 Description This function returns additional state information of the LTC1760 and provides an interface to prohibit charging This command also removes any requirement for the SMBus Host to communicate directly with the charger to obtain AC presence information When the LTC1760 is used access to the charger address h12 is blocked Purpose Used by the SMBus Host to retrieve additional state information from the LTC1760 and the overall system power configuration It may also be used by the system to prohibit any battery charging SMBus Protocol Read or Write Word Input Output word Refer to
64. nnected to the SMBus of either battery by setting the SMB BAT 4 1 nibble Arbitration is handled by stretch ing an SMBus start sequence when a bus collision might occur Whenever configurations are switched the LTC1760 will generate a harmless SMBus reset on SMB1 and SMB2 as required The four possible configurations are illus trated in Figure 1 Sample SMBus communications are shown in Figures 2 and 3 1760f 21 LTC 1760 OPERATION LTC1760 SMBus CONTROLLER HOST LTC1760 AND BAT1 CAN COMMUNICATE BAT2 ORIGINATED COMMANDS ARE IGNORED 1a O O LTC1760 SMBus CONTROLLER HOST LTC1760 AND BAT2 CAN COMMUNICATE BAT1 ORIGINATED COMMANDS ARE IGNORED 1c O LTC1760 SMBus CONTROLLER LTC1760 AND BAT2 CAN COMMUNICATE HOST AND BAT1 ORIGINATED COMMANDS ARE STRETCHED IF THE LTC1760 IS COMMUNICATING WITH BAT2 1b LTC1760 SMBus CONTROLLER LTC1760 AND BAT1 CAN COMMUNICATE HOST AND BAT2 ORIGINATED COMMANDS ARE STRETCHED IF THE LTC1760 IS COMMUNICATING WITH 1d 1760 01 SMB INCLUDES SCL AND SDA SMB1 INCLUDES SCL1 AND SDA1 AND SMB2 INCLUDES SCL2 AND SDA2 Figure 1 Switch Configurations Used by the LTC1760 for Managing Dual Port Battery Communication 2 5 LTC1760 SMBus Controller Operation SMBus communication with the LTC1760 is handled by the SMBus Controller a sub block of the SMBus Interface Data is clocked into the SMBus Controller b
65. ntials The capacitors on Vcc and Vp ys must be large enough to keep the circuit operating correctly during the 15ms short circuit event The charger will stop within a few microseconds leaving a small current which must be provided by the capacitor Vpi ys The recommended minimum values 1uF on 1760f 31 LTC 1760 OPERATION and 2uF on Vcc including tolerances should keep the LTC1760 operating above the UVLO trip voltage long enough to perform the short circuit function when the input voltages are greater than 8V Increasing the capaci tor across to 4 7uF will allow operation down to the recommended 6V minimum 8 3 Emergency Turn Off All of the PowerPath switches can be forced off by setting the DCDIV pin to a voltage between 8V and 10V This will have the same effect as a short circuit event DCDIV must be less than 5V and Vp ys must decrease below the UVLO threshold to re enable the PowerPath switches The LTC1760 can recover from this condition without remov ing power Contact Applications Engineering for more information 8 4 Power Up Strategy All three PowerPath switches are turned on after Vp js exceeds the UVLO threshold for more than 250ms This delay is to prevent oscillation from aturn on transient near the UVLO threshold 9 The Voltage DAC Block The voltage DAC VDAC is adelta sigma modulator which controls the effective value of an internal resistor Ryser 7 2k used
66. odes in this mode and power is taken from the highest voltage source available at the DCIN BAT1 or BAT2 inputs The input side powerpath switch driverthat is delivering power then closes its input switch to reduce the power dissipa tion in the PFET bulk diode In effect this system provides diode like behavior from the FET switches without the attendant high power dissipation from diodes The HOST is informed of this 3 Diode mode status when it polls the powerpath status register via the SMBus interface High speed powerpath switching at the LOPWR trip point is handled autonomously Simultaneous discharge of both batteries is supported The switch drivers prevent reverse current flow in the switches and automatically discharge both batteries into the load sharing current according to the relative capacity ofthe batteries Simultaneous dual discharge can increase battery operating time by up to 1096 by reducing losses in the switches and reducing internal battery losses associ ated with high discharge rates 2 The SMBus Interface 2 1 SMBus Interface Overview The SMBus interface allows the LTC1760 to communicate with two batteries and the SMBus Host The SMBus Interface supports true dual port operation by allowing the SMBus Host to be connected to the SMBus of either battery The LTC1760 is able to operate as an SMBus master or slave device References Smart Battery System Manager Specification Revision 1 1 SBS Implementers
67. op charging the current algorithm is reset to zero The LTC1760 monitors the requested and actual voltages in each battery and increases the programmed voltage by 16mV each tquery unless one of the following conditions are met a The actual voltage exceeds the requested voltage in either battery b The actual voltage exceeds This is an extremely important feature of the LTC1760 since it allows the charger to servo on the internal cell voltage of the battery as determined by the Smart Battery This voltage may be significantly lower than the battery pack terminal voltage which is used by all Level 2 chargers The advantage for the LTC1760 is improved charge time safety and a more completely charged battery The voltage correction cannot exceed the minimum re quested voltage by more than 512mV When decrementing the programmed voltage is reduced by 16mV each tqygry Whenever changing conditions cause either battery to stop charging the voltage algorithm is reset to zero 1760f 26 TECHNOLOGY LIC 1760 OPERATION 4 System Power Management Algorithm and Battery Calibration 4 1 Turning Off System Power The LTC1760 allows the user to turn off system power using the LTC POWER OFF bit When POWER OFF is asserted high all power management functions are by passed and the LTC1760 will turn off DCIN BAT2 and BAT1 power paths This feature allows the user to power down the system Charging is still al
68. opper that connects to the input capacitor ground before tying back into system ground General Rules 7 Connection of switching ground to system ground or internal ground plane should be single point Ifthe system has an internal system ground plane a good way to do this is to cluster vias into a single star point to make the connection 8 Route analog ground as a trace tied back to IC ground analog ground pin if present before connecting to any other ground Avoid using the system ground plane CAD trick make analog ground a separate ground net and use a 0Q resistor to tie analog ground to system ground 9 A good rule of thumb for via count for a given high current path is to use 0 5A per via Be consistent 10 If possible place all the parts listed above on the same PCB layer 11 Copper fills or pours are good for all power connec tions except as noted above in Rule 3 You can also use copper planes on multiple layers in parallel too this helps with thermal management and lower trace induc tance improving EMI performance further 12 For best current programming accuracy provide a Kelvin connection from Rsengg to CSP and BAT See Figure 12 as an example It is important to keep the parasitic capacitance on the Rr CSP and BAT pins to a minimum The traces connecting these pins to their respective resistors should be as short as possible DIRECTION OF CHARGING CURRENT gt Figure 12 Kelvin Sensing of Cha
69. ore of the connected batteries need a calibration cycle Allowed values are b1 The LTC1760 has determined that one or both batteries requires calibration b0 The LTC1760 has determined that no batteries require calibration CHARGING INHIBIT Bit The read write CHARGING INHIBIT is used by the SMBus Host to inhibit charging or to determine if charging is inhibited This bit is also set if MODE is used to inhibit charging Allowed values are b1 The LTC1760 must not allow any battery charging to occur 0 The LTC1760 may charge batteries as needed Power On Reset Value CHARGER POR Bit The read write CHARGER POR bit is used to force a charger power on reset Writing a 1 to this bit will cause a charger power on reset with the following effects Charging will be turned off and wake up charging will be resumed This is the same as if the batteries were removed and then reinserted The three minute wake up watchdog timer will be restarted Writing a 0 to this bit has no effect A read of this bit always returns a 0 CALIBRATE Bit The read write CALIBRATE bit is used either to show the status of battery calibration cycles in the LTC1760 or to begin or end a calibration cycle CALIBRATE BAT 4 1 Nibble The read write CALIBRATE_BAT 4 1 nibble is used by the SMBus Host to select the battery to be calibrated or to determine which individual battery is being calibrated Allowed read values are b0010 Battery 2 is bein
70. otes the specifications which apply over the full operating temperature range otherwise specifications are at Ty 25 C 20V 12V Vear 12V Vypps 3 3V 5 21 unless otherwise noted SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS toNPI Gate B11 B2I DCI Turn On Time Vas lt 3 3000pF Note 4 300 uS torrPl Gate 1 21 0 Turn Off Time Vas gt 1V Ci oap 3000pF Note 4 10 uS Input Gate Clamp Voltage ILoap 19A GB1I Highest 1 or Vscp 4 75 6 7 7 5 V GB2I Highest or Vscp 4 75 6 7 7 5 V GDCI Highest Vpcin Vscp 4 75 6 7 75 V Vporri Input Gate Off Voltage lLoap 25uA GB1I Highest Vgar4 or Vscp Vesti 0 18 0 25 V 6821 Highest Vgar Vscp Vago 0 18 0 25 V GDCI Highest Vpcin or Vscp Venci 0 18 0 25 V Thermistor Thermistor Trip CLOAD MAX 300pF Note 9 95 100 105 kQ COLD RANGE OVER RANGE R2A 11300 1 R1B R2B 54900Q 1 Thermistor Trip CLoap max 300pF Note 9 28 5 30 32 5 kQ IDEAL RANGE COLD RANGE R2A 11300 1 R1B R2B 54900Q 1 Thermistor Trip CLoap max 300pF Note 9 2 85 3 3 15 kQ HOT RANGE IDEAL RANGE R2A 11300 1 R1B R2B 549000 1 Thermistor Trip CLoap max 300pF Note 9 425 500 575 Q UNDER RANGE HOT RANGE R1A R2A 11300 1 R1B R2B 549000
71. ould try to not use this battery in the power path When all other power paths fail the LTC1760 will ignore this alarm and still try to supply system power from this source b0 The LTC1760 may continue discharging this battery 2 3 11 AlertResponse Description The SMBus Host uses the Alert Response Address ARA to quickly identify the generator of an SMBALERT event Purpose The LTC1760 will respond to an ARA if the SMBALERT signal is actively pulling down the SMBALERT bus The LTC1760 will follow the prioritization reporting as defined in the System Management Bus Specification SMBus Protocol A 7 bit Addressable Device Responds to an ARA Output The device address will be sent to the SMBus Host The LTC1760 device address is 0x14 or 0 0 if just looking at the 7 bit address field Thefollowing events will cause the LTC1760 to pull down the SMBALERT bus through the SMBALERT pin Change of PRESENT in the BatterySystemStateCont function Change of BATTERY PRESENT in the BatterySystemState function Internal power on reset condition Refer to Section 2 2 for bit mapping 2 4 SMBus Dual Port Operation The SMBus Interface includes the LTC1760 s SMBus controller as well as circuitry to arbitrate and connect the battery and SMBus Host interfaces The SMBus controller generates and interprets all LTC1760 SMBus functions The dual port operation allows the SMBus Host to be co
72. parameters to consider The parameters are gate charge and single pulse power capability When the LTC1760 senses a LOW_POWER event all the P channel MOSFETs are turned on simultaneously to allow voltage recovery due to a loss of a given power source However there is a delay in the time it takes to turn onallthe MOSFETs Slow MOSFETs will require more bulk capacitance to hold up all the system s power supply function during the transition and fast MOSFET will require less bulk capacitance The transition speed of a MOSFET to an on or off state is a direct function of the MOSFET gate charge t Qeate lprive lprive is the fixed drive current into the gate from the LTC1760 and t is the time it takes to move that charge to a new state and change the MOSFET conduction mode Hence time is directly related to Since goes up with MOSFETs of lower Rps on choosing such MOSFETs has acounterproductive increase in gate charge making the MOSFET slower Please note that the LTC1760 recovery time specification only refers to the time it takes for the voltage to recover to the level just prior to the LOW_POWER event as opposed to full voltage The single pulse current rating of MOSFET is important when a short circuit takes place The MOSFET must survive a 15ms overload MOSFETs of lower MOSFETs that use more powerful thermal packages will have a high power surge rating Using too small of a pu
73. ps oy and is a constant inversely related to the gate drive current Both MOSFETs have I R losses while the topside N channel equation includes an additional term for transi tion losses which are highest at high input voltages For Vin 20V the high current efficiency generally improves with larger MOSFETs while for Viy gt 20V the transition losses rapidly increase to the point that the use of a higher Rps on device with lower Cgss actually provides higher efficiency The synchronous MOSFET losses are greatest at high input voltage or during a short circuit when the duty cycle in this switch is nearly 100 The term 1 SAT is generally given for a MOSFET in the form of a normalized vs Temperature curve but 0 005 C can be used as an approximation for low voltage MOSFETs Crss is usually specified in the MOSFET characteristics The constant k 1 7 can be used to estimate the contribu tions of the two terms in the main switch dissipation equation If the LTC 1760 charger is to operate in low dropout mode or with a high duty cycle greater than 85 then the topside N channel efficiency generally improves with a larger MOSFET Using asymmetrical MOSFETs may achieve cost savings or efficiency gains The Schottky diode D1 shown in the Typical Application conducts during the dead time between the conduction of the two power MOSFETs This prevents the body diode of the bottom MOSFET from turning on and storing charge
74. r output bypass High input surge currents can be created when the adapter is hot plugged to the charger or when a battery is connected to the charger Solid tantalum capacitors have a known failure mechanism when subjected to very high turn on surge currents Only Kemet T495 series of Surge Robust low ESR tantalums are rated for high surge conditions such as battery to ground 1760f 3 LTC 1760 APPLICATIONS INFORMATION The relatively high ESR of an aluminum electrolytic for C15 located at the AC adapter input terminal is helpful in reducing ringing during the hot plug event Refer to AN88 for more information Highest possible voltage rating on the capacitor will mini mize problems Consult with the manufacturer before use Alternatives include new high capacity ceramic at least 20uF from Tokin United Chemi Con Marcon et al Other alternative capacitors include OSCON capacitors from Sanyo The output capacitor Cour is also assumed to absorb output switching current ripple The general formula for capacitor current is 0 29 Vern E L1 f IRMS For example 19V Vgar 12 6V L1 10uH and f 300kHz Ing 0 414 EMI considerations usually make it desirable to minimize ripple current in the battery leads and beads or inductors may be added to increase battery impedance atthe 300kHz switching frequency Switching ripple current splits be tween the battery and the outpu
75. rging ee Er nm prt hm m Een red c 25 3 5 Controlled Charging Termination 25 3 6 Controlled Charging Current and Voltage Programming ccccsssessscssescssesssecsesescssescessssseessscscsueecesssssneasacscsseavsseseesessssscensaceeseaees 26 4 System Power Management Algorithm and Battery Calibration sese 27 4 1 TUNING OM SYSTEM POWE on 27 4 2 Power By Algorithm When No Battery is Being Calibrated sse 27 4 3 Power By Algorithm When a Battery is Being Calibrated sse 27 4 4 Power s mrt tete rit erheben 27 5 Battery Calibration Conditioning 28 5 1 Selecting a Battery Calibrated 1 5 d an o ier dead arre teens 28 5 2 Initiating Calibration of Selected Battery ccccccesssscsescscsscscsscsssscsssescssescsussssssssssscsssavsssssssssssscsssssessueaseueasseeasasasuesceseacasensacseeceees 28 5 3 Terminating Calibration of Selected Battery coa db ah en dm naddnndaladhhasdnalewha 28 6 MODE Pin O cassis sec crier Peer 29 6 1 Stand Alone Charge i 29 6 2 Hardware Charge 29 6 3 Charging When SCL and SDA LO
76. rging Current Important Safety Notes Although every effort is made to meet and exceed all required SMBus Charger V1 1 safety features it is the responsibility of the battery pack to protect itself from excessive currents or voltages The LTC1760 is not itself safety device Consult your battery pack manufacturer for more information 1760f 41 LTC 1760 TYPICAL APPLICATION Application for a Dual Battery System 12 6V 4A prot nro en nn nn a a a a 1 1 PowerPath MUX 1000 LTC1760 VpLus GDCI GDCO GB1I GB10 9 21 GB20 SCP SCN LOPWR CSN CSP SW BOOST TGATE BGATE 45i EAT PGND TH2A TH2B SCL2 SDA2 TH1A TH1B R1A 1 13k SAFETY 1 SCL1 SDA1 BAT1 BAT2 BAT d D2 d D3 16 15 R11 1k D4 R 18 C6 C4 0 22uF 0055 20uF cg azur 088 aD DI rangt 0 47uF _R6 1 MUX 1000 a4 ag i Si6928 516928 010 516928 01 MBR130T3 02 IN4148 TYPE Q1 Q2 05 Q6 Q7 08 Si4925DY 03 04 Q9 Q10 QTG QBG FDS6912A 1760 02 17601 42 7 ECHNOLOGY LTC 1760 PACKAGE DESCRIPTION FW Package 48 Lead Plastic TSSOP 6 1mm Reference LTC DWG 05 08 1651 12 40 12 60 gt n 488 496 OO D O 0 252929 uc 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
77. ries one and two dV dtgAr4 dV dtgato From here we can simplify 1 dV dt 1 2 2 2 1 Atthis point you can see that the current divides as the ratio of the two batteries capacity ratings The sum of the current into both batteries is the same as the current being supply by the charger This is independent of the mode of the charger CC or CV IcHRG 1 2 From here we solve for the actual current for each battery IBAT2 2 IBaT1 IcHRe 1 2 Please note that the actual observed current sharing will vary from manufacturer s claimed capacity ratings since it is actual physical capacity rating at the time of charge Capacity rating will change with age and use and hence the current sharing ratios can change over time Adapter Limiting An important feature of the LTC1760 is the ability to automatically adjust charging current to a level which avoids overloading the wall adapter This allows the prod uct to operate at the same time that batteries are being charged without complex load management algorithms Additionally batteries will automatically be charged at the maximum possible rate of which the adapter is capable This feature is created by sensing total adapter output current and adjusting charging current downward if a preset adapter current limit is exc
78. s must not be used to make this connection 2 The control IC needs to be close to the switching FET s gate terminals Keep the gate drive signals shortfor a clean FET drive This includes IC supply pins that connect to the switching FET source pins The IC can be placed on the opposite side of the PCB relative to above 3 Place inductor input as close as possible to switching FET s output connection Minimize the surface area of this trace Make the trace width the minimum amount needed to support current no copper fills or pours Avoid run ning the connection using multiple layers in parallel Minimize capacitance from this node to any other trace or plane 1760f 40 TECHNOLOGY LTC 1760 APPLICATIONS INFORMATION SWITCH NODE NU VBAT HIGH FREQUENCY CIN 4 CIRCULATING D1 Z Cour 1760 F10 Figure 11 High Speed Switching Path 4 Place the output current sense resistor right next to the inductor output but oriented such that the IC s current sense feedback traces going to resistor are not long The feedback traces need to be routed together as a single pair on the same layer at any given time with smallest trace Spacing possible Locate any filter component on these traces next to the IC and not at the sense resistor location 5 Place output capacitors nextto the sense resistor output and ground 6 Output capacitor ground connections need to feed into same c
79. ssence this system performs as a low forward voltage diode Operation is identical for BAT2 7 2 Dual Charging Note that the charge MUX switch drivers will operate together to allow both batteries to be charged simulta neously If both charge MUX switch drivers are enabled only the battery with the lowest voltage will be charged until its voltage rises to equal the higher voltage battery The charge current will then share between the batteries according to the capacity of each battery When batteries are controlled charging only batteries with voltages above are allowed to charge When a battery is wake up charging this restriction does not apply 1760f 30 TECHNOLOGY LTC 1760 OPERATION 8 PowerPath Controller The PowerPath switches are turned on and off by the power management algorithm The external PFETs are usually connected as an input switch and an output switch The output switch PFET is connected in series with the input PFET and the positive side of the short circuit sensing resistor Rec The input switch is connected in series between the power source and the output PFET The PowerPath switch driver equivalent circuit is shown in Figure 6 The output PFET is driven ON or OFF by the output side driver controlling pin GB10 The gate ofthe input PFET is driven by an error amplifier which monitors the voltage between the input power source BAT1 in this case and SCP If the switch is turne
80. t capacitor depending on the ESR of the output capacitor and the battery imped ance Ifthe ESR of Couris 0 20 and the battery impedance is raised to 40 with a bead or inductor only 5 of the current ripple will flow in the battery Power Path and Charge MUX MOSFET Selection Three pairs of P channel MOSFETs must be used with the wall adapter and the two battery discharge paths Two pairs of N channel MOSFETs must be used with the battery charge path The nominal gate drive levels are set by the clamp drive voltage of their respective control circuitry This voltage is typically 6 25V Consequently logic level threshold MOSFETs must be used Pay close attention to the Bypss specification for the MOSFETs as well many of the logic level MOSFETs are limited to 30V or less Selection criteria for the power MOSFETs include the ON resistance input voltage and maximum output current For the N channel charge path the maximum current is the maximum programmed current to be used For the P channel discharge path maximum current typi cally occurs at end of life of the battery when using only one battery The upper limit of value is a function of the actual power dissipation capability of a given MOSFET package that must take into account the PCB layout As a starting point without knowing what the PCB dissipation capability would be derate the package power rating by a factor of two PMOSFET Rps ONMAX 2
81. tateCont CALIBRATE high 4 LTC1760 master read of ChargingCurrent return ing a zero current request 5 An LTC1760 master read of ChargingVoltage return ing a zero voltage request 6 Any of the following AlarmWarning bits asserted high OVER_CHARGED_ALARM TERMINATE_CHARGE_ALARM TERMINATE_CHARGE_RESERVED OVER_TEMP_ALARM Note that the LTC1760 ignores all writes from the battery Each battery s charge alarm is cached inside the LTC1 760 This bit will be set when any of the upper four bits of the battery s AlarmWarning response are set 1760f 25 LTC 1760 OPERATION This bit will remain set if a subsequent AlarmWarning fails to respond The cached alarm will be cleared by any of the following conditions a Associated battery is removed b A subsequent AlarmWarning clears all charge alarm bits for the associated battery c A power on reset event d The SMBus Host asserts BatterySystemStateCont CHARGER_POR high 7 An SMBus Host write asserts the LTC1760 BatterySystemStateCont CHARGING_INHIBIT high 8 Hardware controlled charging inhibit is asserted MODE low with Vpps high 9 The SMBus of the battery being charged has stopped acknowledging SMBus read commands for longer than tTIMEOUT 10 The thermistor of the battery being charged indicates HOT RANGE 11 Any SMBus communication line is grounded for longer than tquery 12 BatterySystemStateCont POWER_NO
82. to indicate charging output low and not charging output high 6 2 Hardware Charge Inhibit When MODE is tied to GND and Vypps Viu vpps charging is inhibited and BatterySystemStateCont CHARGING_INHIBIT will report a logic high 6 3 Charging When SCL And SDA Are Low When MODE is tied to Vcc and Vpps lt Vit SDA and SCL are not used and will not interfere with LTC1760 battery communication This feature allows the LTC1760 to autonomously charge when SCL and SDA are not available This scenario might occur when SMBus Host has powered down and is no longer pulling up on SCL and SDA 6 4 Charging With an SMBus Host When Mode is tied to Vcc and Vypps gt Vi SDA and SCL are used to communicate with the SMBus Host 7 Battery Charger Controller The LTC1760 charger controller uses a constant off time current mode step down architecture During normal op eration the top MOSFET is turned on each cycle when the oscillator sets the SR latch and turned off when the main current comparator resets the SR latch While the top MOSFET is off the bottom MOSFET is turned on until either the inductor current trips the current comparator or the beginning ofthe next cycle The oscillator uses the equation torr Vocin Veat Vocin fosc to set the bottom MOSFET on time The result is quasi constant frequency operation where the converter fre quency remains nearly constant over a wide range
83. to program the maximum charger voltage Figure 7 is a simplified diagram of the VDAC operation The delta sigma modulator and switch SWV convert the VDAC value to a variable resistance equal to 11 8 2047 In regulation VsET is servo driven to the 0 8V reference voltage VREF SWV mw VA 1760 FO7 Figure 7 Voltage DAC Operation Capacitors Cp and Cg2 are used to average the voltage present at the pin as well as provide a zero in the voltage loop to help stability and transient response time to voltage variations 10 The Current DAC Block The current DAC is a delta sigma modulator which controls the effective value of an internal resistor Rser 18 77k used to program the maximum charger current Figure 8 is simplified diagram of the DAC opera tion The delta sigma modulator and switch convert the IDAC value to a variable resistance equal to 1 25 IDACyatuey 1023 In regulation Isgr is servo driven to the 0 8V reference voltage Vper and the current from is matched against a current derived from the voltage between pins CSP and CSN This current is Vesp 3k Therefore programmed current is Iche 0 8 Veer 3K Rsus Rser 1023 102 3mV Rsus IDAC va ug 1023 During wake up current operation the current DAC enters alow current mode The current DAC output is pulse width modulated with a high frequency clock h
84. unction Whenever the LTC1760 encounters a valid command with invalid data it ACK s the command and ignores the invalid data For example if an attempt is made to select battery A and to simultaneously communicate with the system host the LTC1760 will just ignore the request 2 3 1 BatterySystemState 1101 Description This function returns the present state of the LTC1760 and allows access to individual batteries The information is broken into four nibbles that report Which battery is communicating with the SMBus Host Which battery s if any or AC is powering the system Which battery s is connected to the Smart Charger Which battery s is present The LTC1760 provides a mechanism to notify the system whenever there is a change in its state Specifically the LTC1760 provides the system with a notification when ever e Abattery is added or removed Polling or SMBALERT e AC power is connected or disconnected Polling or SMBALERT e The LTC1760 autonomously changes the configura tion of the battery s supplying power Polling only e The LTC1760 autonomously changes the configura tion of the battery s being charged Polling only Purpose Used by the SMBus Host to determine the present state of the LTC1760 and the attached batteries It also may be used to determine the state of the battery system after the LTC1760 notifies the SMBus Host of a change via SMBALERT SMBus Protocol Read or Write
85. us 1960 G10 1760 G11 Input Power Related GDCO Pin 6 DCIN Output Switch Gate Drive Together SCN Pin 4 PowerPath Current Sensing Negative Input This pin should be connected directly to the bottom output side of the low valued resistor in series with the three PowerPath switch pairs for detecting short circuit currentevents Also powers the LTC1760 internal circuitry when all other sources are absent SCP Pin 5 PowerPath Current Sensing Positive Input This pin should be connected directly to the top switch side of the low valued resistor in series with the three PowerPath switch pairs for detecting short circuit cur rent events with GDCI this pin drives the gate of the P channel switch in series with the DCIN input switch GDCI Pin 7 DCIN Input Switch Gate Drive Together with GDCO this pin drives the gate of the P channel switch connected to the DCIN input GB10 Pin 8 BAT1 Output Switch Gate Drive Together with GB11 this pin drives the gate of the P channel switch in series with the BAT1 input switch GB11 Pin 9 BAT1 Input Switch Gate Drive Together with GB10 this pin drives the gate of the P channel switch connected to the BAT1 input 1760f 8 LTC 1760 PIN FUNCTIONS GB20 Pin 10 BAT2 Output Switch Gate Drive Together with GB2I this pin drives the gate of the P channel switch in series with the BAT2 input switch 6821 Pin 11 BAT2 Input Switch Gate Drive Together with GB
86. y better than 0 29 A proprietary PowerPath architecture supports simulta neous charging or discharging of both batteries Typical battery run times are extended by up to 10 while charging times are reduced by up to 50 The LTC1760 automatically switches between power sources in less than 10us to prevent power interruption upon battery or wall adapter removal The LTC1760 implements all elements of a version 1 1 Smart Battery System Manager except for the genera tion of composite battery information An internal multi plexer cleanly switches the SMBus Host to either of the two attached Smart Batteries without generating partial messages to batteries or SMBus Host Thermistors on both batteries are automatically monitored for tempera ture and disconnection information SafetySignal 7 LTC and LT are registered trademarks of Linear Technology Corporation PowerPath is a trademark of Linear Technology Corporation Protected by U S Patents including 5723970 6650174 TYPICAL APPLICATION Dual Battery Charger Selector System Architecture SYSTEM POWER SMBus HOST Dual vs Sequential Charging T T 3000 BAT2 2500 CURRENT HN CURRENT 15000 SEQUENTIAL 1500 1000 50 amp 0 8 3500 3000 BATI 2500 CURRENT _pato 3 2000 CURRENT DUAL 1500 1000 ai 2 MINUTES gt 0 50 100 150 200 250
87. y disable the battery charger function 1 Remove ALL FETs involved in the charge path Q3 04 09 Q10 2 Remove switching FETs QTG QBG diode D1 and inductor L1 3 Remove diodes D2 D3 D4 capacitors C4 Cour and Resistor R11 and Rsense 4 Reduce capacitor to 0 1 uF 5 Remove all components connected to COMP1 Verr ITH Limit and Vi irr pins 6 Short lj yr and Vj mit to Ves 6 Remove R1 C1 but short CLP to DCIN Replace with a short trace connection 7 Short CSP to CSN but leave the combination floating 8 Unless otherwise specified leave the unused pins of the LTC1760 floating F No DC Path And No Charge Configuration To limit the LTC1760 to battery discharge functions only merge the previous two configurations with the following 1 Remove 2 Remove resistors tied to DCDIV and ground DCDIV PCB Layout Considerations For maximum efficiency the switch node rise and fall times should be minimized To prevent magnetic and electrical field radiation and high frequency resonant prob lems proper layout of the components connected to the IC is essential See Figure 11 Here is a PCB layout priority list for proper layout Layout the PCB using this specific order 1 Input capacitors need to be placed as close as possible to switching FET s supply and ground connections Short est copper trace connections possible These parts must be on the same layer of copper Via

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