King Mongkut`s University of Technology Thonburi
Contents
1. Using the right click on the right sub window to select Initial ize the Chain we get the JTAG chain as shown in Figure 12 23 Choose cancel when there is a pop up menu appears 12 Right click on the XC3S200 device Then choosing the Assign new configuration file the window similar to Figure 12 24 appear Browse to the project directory to chose the lt deign_ name gt bit file Click OK 13 After the configuration has been assigned right click on the XC3S200 again This time choose Program to program the configuration file to the chip After some time the Program Success ful should appear If the program is failed consult the Lab s supervisor 14 Perform the experiment to test whether or not the hardware is working correctly Experiment 2 4 bit binary adder high level VHDL code Repeat Step 2 14 but name the project high level adder and use the source files from the di rectory lt shared directory gt src binaryadder high level instead Experiment 3 4 bit binary counter Repeat Step 2 14 but name the project counter and use the source files from the directory lt shared directory gt src counter instead Experiment 4 4 bit LFSR Repeat Step 2 14 but name the project lfsr and use the source files from the directory lt shared directory gt src lfsr instead Points of Discussion 1 Explain in your own words what you have learnt from t2. B 3 Al2 Bi2 A 1 B 1 A Q B 0 7 w m m O CO m m OS s a b c co ab bc ac 0 0 0 0 l 1 1 1 mm m m JA Figure 12 6 Ripple carry 4 bit binary adder In charge Faculty Staff Asst Prof Dr Pinit Kumhom 12 7 King Mongkut s University of Technology Thonburi Faculty of Engineering l Department of Electronic and Telecommunication Engineering ENE EIE 312 Electronic Engineering Laboratory for 3rd year students of the Electrical Communication and Electronic Engineering Curriculum Library ieee use 1eee std_logic_1164 all1 entity add4 is port a b in std_logic_vector 3 downto cl in std_logic S out std_logic_vector 4 downto end add4 architecture struct of add4 is component FA port a b c in std_logic S CO out std_logic end component signal c std_logic_vector 4 downto begin struct FA_gen for i in to 3 generate FA_i FA port map a acl b gt b i C gt CCL S SCi co gt c 1 1 end generate FA_gen c lt ci S 4 lt c 4 end struct Figure 12 7 VHDL code for ripple carry 4 bit binary adder System 1 A 4 bit Binary Adder A 4 bit binary adder is a system with two 4 bit inputs coded as binary number for representing natu ral number O to 15 In addition another 1 bit input representing an external carry in whose value is either O or 1 is added The output is a 5 bit that stored the sum of t
3. Pinit Kumhom 12 17 King Mongkut s University of Technology Thonburi Faculty of Engineering Department of Electronic and Telecommunication Engineering ENE EIE 312 Electronic Engineering Laboratory for 3rd year students of the Electrical Communication and Electronic Engineering Curriculum b gt File Edit View Project Source Process Tools Window Layout Help Daal a amp iS Bxlmoa AAP PRFAWD mA S ye ate ee En Desi Ogx Design Overview See w 2 Summary yy View Implementation HA Simulation 2 lige Propane 2 Module Level Utilization Select the des g to spina cra igi Clock Report S EF xc3s50 5tql44 add4 tb beh add4 tb vhd G Static Timing 5 Errors and Warnings E Parser Messages Synthesis Messages Translation Messages Map Messages Place and Route Messages C Timing Messages Bitgen Messages Rov 5 All Implementation Messages Processes add4_tb beh ad ISim Simulator D meere binin Syntax E roperties E Enable Message Filtering Gptona Design Summary Contents E Show Clock Report E Show Failing Constraints E Show Warnings E Show Errors Simulate Behavioral Model Process Window F set 83 on Ae Owes x Console Gp INFO HDLCompiler 1061 Parsing VHDL file D S1GiA ripple adder add4 ripple vhd into library work 4G INFO HDLCompiler 1061 Parsing VHD
4. 12 14 King Mongkut s University of Technology Thonburi Faculty of Engineering l Department of Electronic and Telecommunication Engineering ENE EIE 312 Electronic Engineering Laboratory for 3rd year students of the Electrical Communication and Electronic Engineering Curriculum Since the ports of the lfsr4 and count4 are the same and they both are a kind of counters they testbench is the same except the unit under test part of the testbench Library ieee use 1eee std_logic_1164 all1 entity Lfsr4 is port clk rst_n in std_logic count in std_logic q out std_logic_vector 3 downto end 1lfsr4 architecture beh of Lfsr4 is constant SEED std_logic_vector 3 downto 0001 non zero initial value Signal q_reg q_next std_logic_vector 3 downto Signal fb zero fzero std_logic begin struct 4 bit register process clk rst_n begin process if rst_n then asynchronous reset active Low q_reg lt SEED set output to a random seed elsif clk event and clk 1 then rising clock edge q_reg lt q_next end if end process XOR network fb lt q_reg xor q_reg 1 Insert 0000 when q_reg 3 downto 1 0001 zero lt 1 when q_req 3 downto 1 000 else Q fzero lt fb xor zero Shifting q_next lt fzero amp q_reg 3 downto 1 Output q lt std_logic_vector q_reg end beh Figure 12 13 VHDL code for 4 bit LFSR with
5. 7 0000 00 User Constraints constant b v input array 0 to 7 0001 00 Create Timing Constraints constant ci v std logic _vector 0 to 7 VO Pin Planning PlanAhead Pre Synthesis constant s v output array 0 to 7 I O Pin Planning PlanAhead Post Synthesis begin beh Floorplan Area 1O Logic PlanAhead Unit Under Test instantiation Synthesize XST mnie mas H Implement Design port map Generate Programming File EY o no eh Processes add4 struct a 2 22 v D Libraries E Design Summary Bl add4_tb vhd B po gt Waiting for 2 sub compilation s to finish Compiled 7 VHDL Units Built simulation executable D S51G1A ripple adder add4 tb isim _beh exe Fuse Memory Usage 110940 KB Li E Console x Errors E Warnings 4 Find in Files Results Ln32Col16 VHDL File Edit Tools Window Layout View Help B aA A ak x A O X a Sv0Planning PRek Elaborated Design 5 RTL Netlist EEN ma EA a Hf Package x Device x 31 FA_gen 0 FA_i FA FA_gen 1 FA_i FA FA_gen 2 FA_i FA FA_gen 3 FA_i FA G8 SERRE I O Port Properties gt 2 D d Name c Dimm mhi mama Tanam akh General Attributes Configure amp Properties Clock Regions Name Direction Neg Diff Pair Fixed I O Std B E All ports 14 a w a 4 Input default LVCMO525 2 500 a 3 Input
6. F 5 default LVCM0O525 2 500 al2 Input 5 default LVCMOS25 2 500 ali Input 4 default LVCMOS25 2 500 alo Input i 4 default LVCMOS25 2 500 eB b 4 Input 4 default LVCM0O525 2 500 b 3 Input 4 default LVCMOS25 2 500 D biz Input P60 4 default LVCMOS25 2 500 bi Input i 4 default LVCMOS25 2 500 Input P68 E 4 default LVCMOS25 2 500 Output default LVCMOS25 2 500 Output P78 R 3 default LVCMOS25 2 500 Output P76 3 default LVCMOS25 2 500 Output P69 4 default LVCMOS25 2 500 Output P77 3 default LVCMOS25 2 500 Output P70 E 4 default LVCMOS25 2 500 Scalar ports 1 dint vcoosz5 2 500 WH E Td Console 9 Package Pins Figure 12 21 PlanAhead s window for editing the Pin s assignment for the I O ports In charge Faculty Staff Asst Prof Dr Pinit Kumhom 12 20 esoo King Mongkut s University of Technology Thonburi KM l Faculty of Engineering l Department of Electronic and Telecommunication Engineering ENE EIE 312 Electronic Engineering Laboratory for 3rd year students of the Electrical Communication and Electronic Engineering Curriculum 10 Run Generate Programming File The configuration file named as lt design name gt bit e g add4 bit should be generated inside the project s directory 11 Run Manage Configuration Project IMPACT The window similar to Figure 12 22 appears after doubling on the Boundary Scan
7. chip Physical Design Simulation 6 Timing analysis Verification Figure 12 1 FPGA based digital design methodology In charge Faculty Staff Asst Prof Dr Pinit Kumhom 12 1 esoo King Mongkut s University of Technology Thonburi KM l Faculty of Engineering Department of Electronic and Telecommunication Engineering ENE EIE 312 Electronic Engineering Laboratory for 3rd year students of the Electrical Communication and Electronic Engineering Curriculum Step 1a System Modeling Using HDL The goal in this step is to model the system using a HDL in our case we use VHDL The job of de signer is to specify the system and use VHDL to describe it in such a way that it can be synthesized into a logic level circuit later Most of designer s time should be spent in this step whereas VHDL programs are produced as needed Knowledge and skills needed in this step are VHDL fundamental digital system text editor and problem solving skills In this laboratory we ll use three digital sys tems as examples Simulation Experiment foe Week a ra Output observ er e g logic analyzer A stimulus generator or Output observer test vector generator VHDL utility VHDL utility routines routines A stimulus e g signal generators Wave editors Human A physical Circuit hardware Circuit s output Circuit s A model of input the hardware e
8. of Electronic and Telecommunication Engineering ENE EIE 312 Electronic Engineering Laboratory for 3rd year students of the Electrical Communication and Electronic Engineering Curriculum Testbench for the 4 bit counter Verifying a counter is to check that it counts correctly Figure 12 13 shows an example of such testbench Again the unit under test count4 component must be instantiated Unlike the adder testbench we generated all input signals including the clock signal clk the reset signal rst_n and count control count Notice that we use one process to generate clock and the other to generate rst_n and count XOR Network shifting 4 bit register clk rst_n a Block diagram of a 4 bit LFSR b Gate level circuit of the 4 bit LFSR Figure 12 12 a Block diagram of the 4 bit LFSR b Gate level circuit System 3 4 bit Linear Feedback Shift Register LSFR Linear feedback shift registers LSFR are used mostly for implementing error correcting codes Moreover another major application of LFSR is to generate uniform pseudorandom numbers Figure 12 12 shows the functional block diagram of the 4 bit LSFR that can generate 15 non zero numbers that look like random numbers The VHDL code for the 4 bit LFSR is shown in Figure 12 13 with ad dition of inserting the zero so that all 16 numbers are generated and the count control count In charge Faculty Staff Asst Prof Dr Pinit Kumhom
9. of add4 is Signal a_u b_u s_u unsigned 5 downto begin beh a_u lt unsigned amp a amp 1 a_u a 3 aC2Z at1 ac 1 b_u lt unsigned amp b amp c1 b_u bC3 bC2Z bC1 b ci s_u lt a_u b_u SUu au bu S lt std_logic_vector s_u 5 downto 1 ignore bit 0 end beh Figure 12 9 High level VHDL code for 4 bit binary adder Testbench for 4 bit binary adder To verify whether a VHDL model of a system work correctly or not we design a VHDL testbench probram that includes the unit under test UUT the input vectors and output monitoring Figure 12 10 shows an example of testbench for the 4 bit binary adder The first part in the testbench is the instantiation of the unit under test which must be de clared as component in the archtecture s declaration area The second part involves the test vectors Notice that the input signals are declared as a b ci and the output signals are s and co Then the test vectors a b and ci are declared as constants a v b v and ci v which are array of 8 values of a b and ci respectively Also the corresponding correct results are declared as constant s v In other word in this example we choose to store the test vectors instead of generating them Since we need to store a and b which is the std_logic vector 3 downto 0 we declare user defined type as input array and declared array of s vas the output array The third part is the running me
10. when 110 gt abc 110 S lt co lt 1 when others gt abc 111 S lt 1 CO lt 1 end case end process end truth_table Figure 12 8 A VHDL code for full adder Notice that the first design of the 4 bit binary adder has the longest propagation delay equal to 4 the number of bits This is not good if the number of bits increases This problem can be solved with the carry look ahead unit or fast carry unit that generates the carry of every bit Fortunate ly in some FPGA chips such fast carry chain unit is integrated inside the chip The first design may not use the fast carry chain because we synthesize decompose the system to be the ripple carray system Therefore to use the fast carry unit we will let the software tool does the synthesis by modeling the system with high level HDL as shown in Figure 12 9 In charge Faculty Staff Asst Prof Dr Pinit Kumhom 12 9 King Mongkut s University of Technology Thonburi Faculty of Engineering l Department of Electronic and Telecommunication Engineering ENE EIE 312 Electronic Engineering Laboratory for 3rd year students of the Electrical Communication and Electronic Engineering Curriculum Library ieee use 1eee std_logic_1164 alLl1 use 1eee numeric_std alLL entity add4 is port a b in std_logic_vector 3 downto ci in std_logic S out std_logic_vector 4 downto end add4 architecture beh
11. 1 Pinit Kumhom Xilinx s ISE and WebPack a laboratory note ENE EIE 312 Electronic Engineering Lab Department of Electronic and Telecommunication Faculty of Engineering KMUTT 2555 2 APEX Discovery Ill Development Board User Manual a technical manual http www ailogictechnology com download FPGA 20Discovery 20III 20XC3S200F F4 20Boar d 20Manual pdf References 1 Wakerly John Digital Design Principle and Practices 4th Edition Pearson International Edition 2005 2 Chu Pong P RTL Hardware Design Using VHDL i edition Wiley Interscience A John Wiley amp Sons Inc Publication 2006 Equipment and Devices 1 A PC computer with Xilinx s Webpack software installed 3 Digital Oscilloscope with logic analyzer 2 FPGA development board In charge Faculty Staff Asst Prof Dr Pinit Kumhom 12 6 King Mongkut s University of Technology Thonburi Faculty of Engineering l Department of Electronic and Telecommunication Engineering ENE EIE 312 Electronic Engineering Laboratory for 3rd year students of the Electrical Communication and Electronic Engineering Curriculum Procedure Step 1 System Modeling VHDL Coding and Testbench program In this experiment students will have a chance to go through the design steps of modern digital system design as shown in Fig 12 1 using 3 examples as follows 5 bit outputs encoded as binary number where S lt A B Ci A 3
12. All rights reserved Figure 12 3 a General FPGA chip structure and b example of programmable or configurable logic block CLB Step 6 Optional Detail Simulation or Timing Analysis Since the implementation step gives us the actual hardware structure and delay information we can simulate the system again to see not only does whether it works correctly or not but also the timing Usually this simulation will take a longer time Therefore for small systems we may skip the step or in some cases only the timing is analyzed to see whether or not it meets the require ment In charge Faculty Staff Asst Prof Dr Pinit Kumhom 12 4 King Mongkut s University of Technology Thonburi Faculty of Engineering l Department of Electronic and Telecommunication Engineering ENE EIE 312 Electronic Engineering Laboratory for 3rd year students of the Electrical Communication and Electronic Engineering Curriculum Step 7 Device Program In this step the configuration file is transferred or programmed into the FPGA chip via the JTAG communication There are two choices in this step First we program the configuration file directly to the FPGA chip However this configuration will disappear when the power is off Therefore in real application of FPGA the configuration file is stored inn an EEPROM or flash memory that con nects directly to the JTAG ports of the FPGA chip Then whenever the power is turned on the pre stored con
13. King Mongkut s University of Technology Thonburi Faculty of Engineering l Department of Electronic and Telecommunication Engineering ENE EIE 312 Electronic Engineering Laboratory for 3rd year students of the Electrical Communication and Electronic Engineering Curriculum Experiment 12 Electronic Design Automation EDA for Digital Design Using VHDL and FPGA Objectives 1 To understand modern digital design methodology based on VHDL and FPGA 2 To practice using Electronic Design Automation EDA tools including simulation synthesis and implementation for digital design based on VHDL and FPGA Background Theory Due to the advance of the IC technology digital systems have become very complex As a result digital design has become very involved process and advance tools are required Modern digital de sign relies on a set of software programs collectively called EDA tools by which a model of a digital system can be simulated or synthesized before being implemented into a real hardware such as FPGA Field Programmable Gate Array chip for testing A digital system is usually modeled using a Hardware Description Language HDL such as VHDL which stands for Very high speed IC HDL and Verilog Figure 12 1 shows an FPGA based digital system design methodology which includes the following steps synthesis fe Netist Configuration 5 file 7 Device Delay programming file FPGA
14. L file D S1G1A ripple adder add4 tb vhd into library work GJ INFO ProjectMgmt Parsing design hierarchy completed successfully El console Errors J Warnings igi Findin Fies Results Figure 12 18 ISE s Simulation View 5 Run the ISE simulation to simulate the add4 tb After the simulation is loaded many windows including the Instance and Process the Simulation objects the waveform and the Con sole windows show up inside the same frame The waveform window the one with the black background plots signal values against the hardware time the horizontal axis which is an imagi nary time under which the hardware under test is assumed to be working type restart lt enter gt in the command window the one with lsim cursor which order the simulation to reset the hardware time to zero current time 0 Then type run lt Max_time gt lt enter gt for running the simulation where Max time is the hardware time for the simulation to progress from the current time For example run 1000 ns to order the simulation to execute until the hardware time reaches current time 1000 ns In charge Faculty Staff Asst Prof Dr Pinit Kumhom 12 18 King Mongkut s University of Technology Thonburi Faculty of Engineering l Department of Electronic and Telecommunication Engineering ENE EIE 312 Electronic Engineering Laboratory for 3rd year students of
15. chanism usine the process statement In each round of the process each index value of index i the input vectors are set a gt a v i b gt b v i c gt ci_vii Then the statement wait for 100 ns means that the time scale moves 100 ns Then the output s In charge Faculty Staff Asst Prof Dr Pinit Kumhom 12 10 King Mongkut s University of Technology Thonburi Faculty of Engineering l Department of Electronic and Telecommunication Engineering ENE EIE 312 Electronic Engineering Laboratory for 3rd year students of the Electrical Communication and Electronic Engineering Curriculum is compared with s_ v i which is the correct answer If the answer is not correct the simulation will stop using the assertion statement otherwise the simulation continues library ieee use ieee std_logic_1164 all entity add4_tb is end add4_tb architecture beh of add4_tb is component add4 port a b in std_logic_vector 3 downto ci in std_logic S out std_logic_vector 4 downto end component Signal a b std_logic_vector 3 downto Signal ci std_logic Signal s std_logic_vector 4 downto Test vectors type input_array is array natural range lt of std_logic_vector 3 downto type output_array is array natural range lt of std_logic_vector 4 downto constant a_v input_array to 7 0000 010 100 110 1000 1010 1100 1110 c
16. figuration file will be transferred into the FPGA chip 0 1 0008 Leet Figure 12 4 FPGA Discovery Ill by APEX 2 Step 8 Hardware Test The final step is to test whether the actual hardware is working correctly as designed Usually a de velopment board is required to perform this testing In other words the chip that was being pro grammed in the previous step is on a development board which includes input devices such as switches and output devices such as LED and 7 segment LED display In testing we must connect the input ports of the design to input devices of the board and the output ports to the output de In charge Faculty Staff Asst Prof Dr Pinit Kumhom 12 5 esoo King Mongkut s University of Technology Thonburi KM l Faculty of Engineering Department of Electronic and Telecommunication Engineering ENE EIE 312 Electronic Engineering Laboratory for 3rd year students of the Electrical Communication and Electronic Engineering Curriculum vices This should be done in the implementation step Figure 12 4 shows a picture of development board called FPGA Discovery Ill by APEX Thailand Notes Students are expected to study the attached material entitled VHDL A Walkthrough Tutori al and the reference textbook Also a brief lecture will be carried out by the lab supervisor at the beginning of the lab and there may be a quiz on the topic at the beginning of the lab session Attachments
17. g VHDL code Circuit s output Circuit s input a Testing by experiment b Verifying by simulation Figure 12 2 Concept of testbench program of verification using simulation Step 1b Testbench Program The goal is this step is to write a VHDL program called testbench which will be used in the func tional simulation step A testbench is a VHDL program in which a design under test DUT that is modeled in Step 1a is instantiated The input ports of the DUT are fed by a set of test vectors that either stored or generated inside the testbench The DUT s output ports are compared with the cor rect responses stored inside the testbench Figure 12 2 shows the concept of testbench In charge Faculty Staff Asst Prof Dr Pinit Kumhom 12 2 esoo King Mongkut s University of Technology Thonburi KM l Faculty of Engineering l Department of Electronic and Telecommunication Engineering ENE EIE 312 Electronic Engineering Laboratory for 3rd year students of the Electrical Communication and Electronic Engineering Curriculum Step 2 Functional Simulation The goal in this step is to verify that the designed system the VHDL model from Step 1a is working correctly based on its function specification For example if the designed system is a 4 bit binary adder it must add two numbers together correctly This is prepared during the testbench coding in Step 1b In other words the appropriated test vectors must be desi
18. gned for verifying the system Once the test vectors are decided they are integrated in the testbench Therefore in this step a designer basically setting up the simulation tool for the design under test then compile and run it Most works that needs to be done in this step occur when the VHDL codes contain errors either compile time errors or run time errors Designer needs to correct the compile time errors first be fore simulating the system If all results are correct the designed system is good for the next step but if there exist error cases designer needs to go back to Step 1a to correct the errors These two Steps should be repeated until no errors exist Step 3 Synthesis The goal in this step is to synthesize the verified system into gate level or logic level circuit using a synthesis tool Unlike the simulation step the testbench is not required in this step The resulting gate level circuit is called netlist which is usually written in a standard netlist format including the HDL format Step 4 Optional Gate level Simulation There is a chance that the synthesized gate level circuit may not work correctly As a result it should be verified by simulation using the same testbench from Step 1b However in some cases where the system is not complicated we may skip this Step and go directly to the implementation step Step 5 Implementation In this step the gate level circuit will be mapped into the structure of t
19. he 3 inputs Figure 12 5 shows the specification of the system One way to design this 4 bit binary adder is to decompose the system into 4 1 bit adders called full adders connected in cascade as shown in Figure 12 6 The VHDL program that model this design is shown in Figure 12 7 in which the FA component is the full adder whose VHDL code is shown in Figure 12 8 In charge Faculty Staff Asst Prof Dr Pinit Kumhom 12 8 King Mongkut s University of Technology Thonburi Faculty of Engineering l Department of Electronic and Telecommunication Engineering ENE EIE 312 Electronic Engineering Laboratory for 3rd year students of the Electrical Communication and Electronic Engineering Curriculum library ieee use 1eee std_Logic_1164 all1 entity FA is port a b c in std_logic S CO out std_logic end FA architecture truth_table of FA is signal fa_in std_logic_vector 2 downto begin struct prepare inputs fa_in lt a amp ba amp c The FA truth table impLmentation process fa_in begin process case fa_in is when 000 gt abc 000 S lt 0 co lt 0 when 001 gt abc 001 S lt amp 1 co lt 0 when 010 gt abc 010 S lt 1 co lt when 011 gt abc 011 S lt 0 cCOo lt 1 when 100 gt abc 100 S lt 1 co lt when 101 gt abc 101 S lt 0 CO lt 1
20. he synthesis report especially the device s utili zation part 9 Run the Implement If there is no error record the device s utilization again Compare it with one from the synthesis step In charge Faculty Staff Asst Prof Dr Pinit Kumhom 12 19 sosoo King Mongkut s University of Technology Thonburi Faculty of Engineering Department of Electronic and Telecommunication Engineering ENE EIE 312 Electronic Engineering Laboratory for 3rd year students of the Electrical Communication and Electronic Engineering Curriculum B File Edit View Project Source Process Tools Window Layout Help DVEARBILIEXSBxloe VAS BRAsAA BATAAN PILS Design X O Fx Fij View Implementation HA Simulation amp Hierarchy GE s3 ripple adder S EA xc3s50 5tql44 y add4 struct add4_ripple vhd p library ieee use ieee std logic_1164 all entity add4_tb is end add4_tb on wb Wh architecture beh of add4 tb is component add4 port a b in std_logic_vector 3 downto 0 ci in std logic s out std _ logic_vector 4 downto 0 end component Signal a b std_logic _vector 3 downto 0 Signal ci std logic Q No Processes Running Signal s std_logic vector 4 downto 0 Test vectors type input_array is array natural range lt gt of st x Design Summary Reports type output_array is array natural range lt gt of Design Utilities constant a v input_array 0 to
21. he target hardware For FPGA implementation the first step is to translate the gate level circuit into FPGA structure which is arranged as an array of programmable or configurable logic blocks CLBs that are connected via programmable switching blocks as shown in Figure 12 3 The result from the translation is a circuit of the programmable units which in turn will be placed to the target FPGA chip then routing the connections Because of these placing and routing works this step is also known as the place and route step The final result is called a configuration file and delay file that provides delay infor mation of the system In charge Faculty Staff Asst Prof Dr Pinit Kumhom 12 3 King Mongkut s University of Technology Thonburi Faculty of Engineering l Department of Electronic and Telecommunication Engineering ENE EIE 312 Electronic Engineering Laboratory for 3rd year students of the Electrical Communication and Electronic Engineering Curriculum Programmable interconnect C Programmable logic block O I O pad OOOOOOO0O00000 From Digital Design Principles and Practices Fourth Edition John F Wakerly ISBN 0 13 186389 4 2006 Pearson Education Inc Upper Saddle River NJ All rights reserved C1 C4 F3 F F1 F4 F2 F1 K CLK From Digital Design Principles and Practices Fourth Edition John F Wakerly ISBN 0 13 186389 4 2006 Pearson Education Inc Upper Saddle River NJ
22. his set of experiments in term of VHDL modeling design methodology EDA tools development boards etc Discuss the differences between the simulation and the actual testing of hardware Discuss the differences between the simulation and synthesis Discuss the differences between the synthesis results and the implementation results a ee Consult the manual of the XC3S200 to learn more about the FPGA chip using in this experi ment and discuss it in the report In charge Faculty Staff Asst Prof Dr Pinit Kumhom 12 21 King Mongkut s University of Technology Thonburi Faculty of Engineering Department of Electronic and Telecommunication Engineering ENE EIE 312 Electronic Engineering Laboratory for 3rd year students of the Electrical Communication and Electronic Engineering Curriculum GB ISE iMPACT P 40xd BoundaryScan oO oOo ef el eS Edit View Operations Output Debug Window Help Dem Gexelst ee iMPACT Flows O amp x 8 Boundary Scan B SystemACE Create PROM File PROM File Format H WebTalk Data Right click to Add Device or Initialize JTAG chain Available Operations are v b No Cable Connection NoFileOpen Figure 12 22 Example of the iMPACT window IR ISE iMPACT P 40xd Boundary Scan eos x i File Edit View Operations 23 Boundary Scan SystemACE Create PROM File PROM File Format WebTalk Data A
23. ject Property Name Evaluation Development Board Product Category Family Device Package Speed Top Level Source Type Synthesis Tool Simulator Preferred Lanquage Property Specification in Project File Manual Compile Order VHDL Source Analysis Standard Enable Message Filtering Value he Create new project pop up menu None Specified All Spartan3 XC3 200 TQ144 4 HDL PMMMEIE XST VHDL Verilog ISim VHDL Verilog VHDL Store all values m VHDL 93 amaaa A Figure 12 15 Example of the Project setting pop up menu In charge Faculty Staff Asst Prof Dr Pinit Kumhom 12 16 King Mongkut s University of Technology Thonburi Faculty of Engineering Department of Electronic and Telecommunication Engineering ENE EIE 312 Electronic Engineering Laboratory for 3rd year students of the Electrical Communication and Electronic Engineering Curriculum Click Next Then the Project setting pop up menu as shown in Figure 12 15 appears Choose the setting to be the same as those shown in Figure 12 15 After clicking Next the summary menu will show up Click Finish File Edit View Project Source Process T Dangl Design jj View eat Implementation GA si amp Hierarchy GE ripple adder EA xc3s50 5tql44 are Empty View The view currently co
24. n std_logic q out std_logic_vector 3 downto end count4 architecture beh of count4 is Signal q_reg q_next q_inc unsigned 3 downto begin struct 4 bit register process clk rst_n begin process if rst_n then asynchronous reset active Low g_reg lt others gt set all output to 0 elsif clk event and clk 1 then rising clock edge q_reg lt q_next end if end process incrementer g_inc lt q_reg 1 2 to 1 MUX q_next lt q_inc when count 1 else g_reg Output q lt std_logic_vector q_reg end beh Figure 12 12 VHDL code for the 4 bit binary counter In charge Faculty Staff Asst Prof Dr Pinit Kumhom 12 12 King Mongkut s University of Technology Thonburi Faculty of Engineering l Department of Electronic and Telecommunication Engineering ENE EIE 312 Electronic Engineering Laboratory for 3rd year students of the Electrical Communication and Electronic Engineering Curriculum System 2 4 bit Counter Counter is an important sequential module because it can be used as timer which is required in many applications The basic functional block of a binary counter consists of a register an incre menter and a multiplexor MUX as shown in Figure 12 11 A VHDL program of a 4 bit binary counter cyclically count 0 to 15 is shown in Figure 12 12 Library ieee use 1eee std_logic_1164 alL1 entity count4_tb is entity without ports e
25. nd count4_tb a test bench architecture beh of count4_tb is component count4 port clk rst_n in std_logic count in std_logic q out std_logic_vector 3 downto end component signal clk std_logic Signal rst_n count std_logic Signal q std_logic_vector 3 downto begin struct Unit Under Test uut count4 port map clk rst_n count q initialize to 0 or 1 Clock generator for simulation process begin process wait for 50 ns clk lt not clk end process infinite Loop wait for half cycle flip clk value Control mechanism changing the control signals rst_n and count No output checking monitor the output by human process infinite Loop begin process rst_n lt activate reset count lt deactivate count wait for 100 ns rst_n lt 1 deactivate reset wait for 200 ns no count for 2 clocks count lt 1 activate count wait for 500 ns count for 5 clocks count lt deactivate count wait for 300 ns no count for 3 clocks count lt 1 activate count wait for 1500 ns count for 15 clocks go back to the beginning end process end beh Figure 12 13 Testbench code for simulating the 4 bit binary counter In charge Faculty Staff Asst Prof Dr Pinit Kumhom 12 13 esoo King Mongkut s University of Technology Thonburi KM l Faculty of Engineering l Department
26. ntains no files You can add files to the project using the toolbar at left commands from the Project menu and by using the Design Files and Libraries panels Figure 12 16 The Add copy files button 3 Click on the icon Add copy of files see Figure 12 16 for adding source files of the project the pop up menu similar to Figure 12 17 appears _ Add Copy of Source x CDi Je Ex 312Digitallab3 src gt binaryadder ripple 5 Search ripple p Organize New folder v 0 Documents Name Date modified Type Size Music d A add4_ripple 11 9 2012 4 05 PM Text Document Pictures wor vid add4_tb 11 9 2012 6 48 PM Text Document ideos _ FA 11 8 2012 6 34PM Text Document rs Homegroup 1 jE Computer amp Local Disk C ca data D cw Local Disk E amp Local Disk K oa 4 int t File name FA add4_ripple add4_tb vy Sources bt vhd vhdl v l v Figure 12 17 Example of the Add copy of files pop up menu From the pop up window browse to the directory lt shared directory gt src binaryadder ripple in the shared folder Then choose all files in the di rectory see Figure 12 16 Click Open then notice the change in the ISE 4 Choose the Simulation view see Figure 12 18 Then compile the add4 tb vhd If there ex ists syntax errors correct them In charge Faculty Staff Asst Prof Dr
27. onstant b_v input_array to 7 0001 0 11 0101 111 1001 1011 1101 1111 constant ci_v std_logic_vector to 7 01010101 constant s_v output_array to 7 00001 00110 1001 1110 10001 10110 11001 11110 begin beh Unit Undet Test instantiation uut add4 port map a gt aA b gt D ci ci S gt S Test Loop process begin process for i in to 7 Loop set the inputs a lt a_v 1 b lt b_v i Cl lt ci_ v i wait wait for 100 ns assert s S_v 1 report Output is not correct severity failure end Loop 1 end process end beh Figure 12 10 Testbench for add4 the 4 bit binary adder In charge Faculty Staff Asst Prof Dr Pinit Kumhom 12 11 King Mongkut s University of Technology Thonburi Faculty of Engineering l Department of Electronic and Telecommunication Engineering ENE EIE 312 Electronic Engineering Laboratory for 3rd year students of the Electrical Communication and Electronic Engineering Curriculum 4 4 bit q q next q reg Incrementer Y a o Seg disp y xtl a a e i es e e a a eae es on oe d count clk rst _n 4 bit binary counter Figure 12 11 Functional block diagram of 4 bit binary counter Library ieee use 1eee std_logic_1164 all1 use 1eee numeric_std allL entity count4 is port clk rst_n in std_logic count i
28. the Electrical Communication and Electronic Engineering Curriculum Sim P 40xd Defaultavefe S eo sx File Edit View Simulation Window Layout Help D2 a amp x B Oloa a a A O17 A TS amp APBFA A wE 23r t e gt G gt oz 1 00us Ge Il C Re aunch Instances and Processes O amp X Objects O gx Simulation Objects for add4_tb 1 i l 1 f a a S Instance and Process Name I add4 tb Object Name Value std_logic 1164 B aB 0 0100 De ci 0101 2 o 00001 00110 01001 01110 10001 10410 11001 11110 00001 00110 01001 i_v 0 01010101 0000 o01C 0001 0011 _ 01010101 R s_v 0 7 00001 003 g a 0100 0110 1000 10410 1100 1110 0000 0010 0011 0101 0111 1001 1011 1101 1111 0001 0011 4 m p 4 m 4 m 4 Ay Instanc Ey Memory II gt 4 m E Default wcfg Console 1 X1 550 400 ns x ISim does not yet support tracing of constant and generic multi dimensional arrays Simulator is doing circuit initialization process Finished circuit initialization process ISim gt restart ISim gt run 1000 ns Simulator is doing circuit initialization process Finished circuit initialization process Isim gt Console A Compilation Log Breakpoints im Find in Files Results f it Search Results Sim Time 1 000 000 ps Figure 12 19 Example of the ISim s window display If the simulation exits before it reaches the 1000 ns
29. time it means that there exists a wrong re sult at the time the simulation exit otherwise all results are corrected An error can be either that the wrong answer is stored or that the output response is wrong If no error is found click the full view button Move the mouse pointer to a button to see what it is The full view button is in the middle of the window Figure 12 19 shows the full view of the simulation results of the add4 after the run 1000 ns command when there is no error Synthesis and Implementation 6 Choose the Implementation button on the top of the ISE window The ISE window should change to something similar to Figure 12 20 7 In the process window expand the User constraints button in the window Then double click to run the I O Pin Planning PlanAhead Pre Synthesis The PlanAhead s window similar to Figure 12 21 should show up You might need to wait for quite a long time Edit the Ports site of all ports to the appropriate pins which must be planned ahead by consulting the develop ment board s manual Attachment 2 For the pin setup that shows in Figure 12 21 we use the DIP switch number 1 2 3 4 for the input port a the DIP SW number 5 8 for the input port b the PB1 switch for the input port ci and the LED number L7 L3 L2 L1 LO for the output port s 8 Run the Synthesis If there is no error record t
30. vailable Operations are a Get Device ID Get Device Signature Usercode m Read Device Status Manufacturer s ID Xilinx xcf0is Version 4G INFO iMPACT 1777 Reading D Xilinx 14 3 ISE_DS ISE xcf data xcf01s bsd 4G INFO iMPACT 501 1 Added Device xcf0is successfully PROGRESS END End Operation Elapsed time 0 sec E crese OETA WOR Configuration Parallel II 200 KHz A LPT1 Figure 12 23 The iMPACT window showing the JTAG chain of the Discovery Ill board In charge Faculty Staff Asst Prof Dr Pinit Kumhom 12 22
31. zero insertion and count control Experiment 1 4 bit ripple carry binary adder Function Simulation 1 Create a new directory in drive D with the name S lt m gt G lt n gt where m is chosen from 1 2 3 or depending on your class session and n is the number of your group e g S1G1A session 1 group 1A 2 Open the Xilinx s ISE program Then choose the Create new project menu to create a new project A pop up menu similar to Figure 12 14 appears Enter ripple adder as the name and click on the on the right of the Location line to browse to the directory created in Step 1 In charge Faculty Staff Asst Prof Dr Pinit Kumhom 12 15 King Mongkut s University of Technology Thonburi Faculty of Engineering Department of Electronic and Telecommunication Engineering ENE EIE 312 Electronic Engineering Laboratory for 3rd year students of the Electrical Communication and Electronic Engineering Curriculum Create New Project Specify project location and type Enter a name locations and comment for the project Names ripple adder Location D S1G 1A yipple adder Working Directory D S1G1A yipple adder Description Select the type of top4evel source for the Topevel source type project Figure 12 14 Example of t aa New Project Wizard Project Settings Specify device and project properties Select the device and design flow for the pro
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