Datasheet - Texas Instruments
Contents
1. Dv A OH Lv A OH CV AOM EVAOM cBAOMW 02ACH FIADH 99404 E OA OSH 50404 0 L3AO8 C3AOMH S3AOMH 94404 030 F3OXH 230XMH 930 020 L2O0XSW 220 20XH POOKY S20X3 9820XH HOXM tHOXH FHOXH SHOXH S8HOXH vOXH LVOXM EVOXM SVOXM 9vOXM 2984 21 4 1020 vedo 6 o alf3 vilA xJo uo asugjmeden p 18 0 00 uo ace 2 56281 uo maueanbar eaugpadus papua ojDrs uto 06 1 SSA K TX RX LIT FLINKSV10BT UM Rev 0 6 5 16 2008 National Semiconductor Corporation Flat Panel Displays Page 39 of 40 FPD Link Evaluation Kit User Manual MEO 0220650 juauin2or XN3 O300W 19300 LII FLINK3V10BT TX RX National Semiconductor Corporation cO 5 oa2. 5 gt gt gt P L L b b b b j gt b b gt j gt gt gt l gt rj PP Pr gt gt gt gt ck a 3 a F a 3 3 E a 8 a a XY 544 202520650 lt pepue wyo pt tm LSSA 4 ce in m ea 23XH EOXOM COXOSW L23XH LOXOMH 023XM 02XOS OC XC LOXOSH 5 LHSSA I83XM E 83XM 983XM 4 11012 eSSA coon 03x04 P3XOMH S3XOH ESSA 40 Bv OH 55 FISA Lv3XM rv3x4 SV3JXM 03O0XM L30XM 30XM EJOXM LOO 9qgaxas 9gxogy 03 5 03X4 BXOM 08XO 933XH 9 wxOM SVXOMH T33XH t 33XutvxXOMd 33XH L33X8 033XH 0v x OW cOcto06SC 900XM 02AO08020XH
3. 101 901 sesu aoed ine 8 02 0 ELIA JO 8 uid Jeau aoe 82 uiuo 0 ha lt lt 580 LM 10 Sz seau 3jni ganro aree BEJ lt lt a 90 1110 pz LZ Suid Jeau soe Inge 11110 Lg Suid Jesu anez cho EL FL WHO 0 100N C pe LO 10 Sud Jeau Inge ce Ec WHO 0 E 100A i 30 52 uid Jeau ange BED bt LE MUO 0 VLOCAZE ed lt lt TX RX LIT FLINKSV10BT UM Rev 0 6 5 16 2008 National Semiconductor Corporation Flat Panel Displays Page 31 of 40 v 1 ddy 0 20590 NIX121 MIL ST TX RX FPD Link Evaluation Kit User Manual PSAo JON 1591 WYO gs o pasn LLH uBnoag py 54015158 anii S806 05 1 Um m LT LT noc 230095 Z O O sear 25 694 wo 5 O LEUTE 5 9945 vor canc
4. ai 401200005 Od 33 asn 01 2 JOTA Ld DUE H1O8 uo g wd oj p wid ALC WOM433 PJeoquo asn ol 155 s31ON apu 12043 pepnonjsury apes vas 4 2905 1 431 peas MS vs LV0S TVNH3LIN ex did 2 105 s Hs L p pnosusur F F MOL OPLY 2105 1os lt VM SN 2126 OV LV V Gdf LF Dt Lf 19 uid Jesu 300 09 300A ee ________________________________________ eee LIT FLINK3V10BT TX RX UM Rev 0 6 5 16 2008 Page 29 of 40 National Semiconductor Corporation Flat Panel Displays peog yj sddy 1022020650 VeXOO Tgxod oj 3403399 areg IND peuous ez pue uid 111 11 PPE NOLLdO ILON H3S FPD Link Evaluation Kit User Manual 03 1 723 1 B3Xl WIXL 10004121 80 1 DOKL HOXL 55 ROO HXOU M 121 YAOU JAOU 52201 Cox 0D GO Cw ur wp 03 03 e e
5. 001 LE LDZD unjonot B unjonot iy LOZO unjopot ma 1020 E woggi EH LDZD 01 eu Logg weno VAIM A m et J ED NIXH Y 1 NEH MIX B XIN NIY wya OG Z 1 ER NIXH MIX M MIX M NIXM FOAM 250 ae AIM NP WYO OG 2 3 ALH 0 os 3 NIXH 4 JAH n NIXM XH TNIH TOM NIXM 55 M PabnoJus zxz j VXIM NIXH op cmi EX WEE NIXH Ej axis NIXY lt NIXM WAXY wp NISH ez iz LL NIH jUXH vAIM NIXH NIXE NIXH JAH NIXH MISH 1 NIXH OAH 3 JAH zj TX RX LIT FLINK3V10BT UM Rev 0 6 5 16 2008 National Semiconductor Corporation Flat Panel Displays Page 37 of 40 FPD Link Evaluat
6. zxz aal dapes vas lt lt 7 evds 1 5 vas TVNH3INI ZXF did 8 4 5 YOS SSA LE 10 0 220000 i pepnonjsum Y P E 125 L12S 1VNH3LNI OV LV Lid 13gv1 139 1 EOM LO AT or LAAT 0112 Lf yo 8 Jeau 7539 1 SSSHL NO 30 355A assa LIT FLINK3V10BT TX RX UM Rev 0 6 5 16 2008 Page 36 of 40 National Semiconductor Corporation Flat Panel Displays FPD Link Evaluation Kit User Manual peog owsg 5449 206620854 pauous pue uid 111 111 Wua 2 32N3H343H NIXT2 3 vMA x m uo asen jeyuasayip wyo DD 1 S310N 100317 jo 10 LLT L3 sasodand 10 sped 111 11 41 11 sey 04 LON Od ce gud pue py suid uondo 1171 1111 S310N Yas OXI Co OIE KIN IKIH 5 V3xH 3XIH NEM 12984 NIM 12H 3008 ATH lt Goxt GAB qe 9OXB D IH BOXH de
7. 77531 gt Z50XL 0 Mar setae St Sg 0 30 1 Star on 0350 ow aes sl SP Ax sp EMI Z o 20031 SENG gwig Savio Eldi Fr r TOOXL oo zidr SETER 6 22 0 Sy r 8 00 168 rr T T ouo 20031 28 400 n ouo OLdf T rar Sx Erdi 000x1 aur 0331 avwa 930XL SAI oo 33015740270 O war SSOXLSVAM SO OF Z33X1bVXKM 1 O T orar gt OF sar 51 Oxley 209 3 1 Sul OF 22001 CjOXD 833 1 LYXIG ZO 11 0 3 1 Oca 030 1 SSA jn g j LIT FLINK3V10BT UM Rev 0 6 5 16 2008 National Semiconductor Corporation Flat Panel Displays Page 32 of 40 FPD Link Evaluation Kit User Manual
8. x 1 sddy 102290650 XN3 0300 19300 LII FLINK3V10BT TX RX UM Rev 0 6 5 16 2008 National Semiconductor Corporation Page 33 of 40 Flat Panel Displays FPD Link Evaluation Kit User Manual Rx PCB Schematic EEE peog 202520650 9210 pepusjs asy 2 1 SHON LNOAYT 2 Pas 60070 zo 35 0 6 ISALT zo Pas 650070 E in en om aqwsY P f T a AJ 5 i Fi L HEN I m P X Lcd LII FLINK3V10BT TX RX National Semiconductor Corporation cO 385 oos oa x o Flat Panel Displays FPD Link Evaluation Kit User Manual v ACH v A OM Gv ACH 0 2 SBAOH 98104 02 COAOH 2AOM 92104 eQqAOM O AGM FIACH
9. eg fe LE 61 11 SL l LE B 8 93 1 03X1 B3XL 3l 1n 00 901 BOXL BOWL WORL gt JAGO Xd 83X1 33y1 auxi 03xX1 13 1 23X1 XL qxog 1 121 1n0W121 EELS WIEL 1001121 1001121 30X1 201 ORL BOXI e D on 0X1 Oo 2 4400 3400 JAQ WX HXCKI goad wA CG BAC 3400 OACKC 3400 lt 994 LIT FLINK3V10BT TX RX UM Rev 0 6 5 16 2008 National Semiconductor Corporation Flat Panel Displays Page 30 of 40 FPD Link Evaluation Kit User Manual x sddv 102850650 SSA 06 ud jeu Jnzz 6 T od 0 947 Ln go ZZ uid SE E 91 Gk zir uuu 0 lt 0 00 LM Jo Z uid eeu aner et 0 lt lt 188 ha SSA sO LLL exei 401 040107 Ange 820 92 z WHO 0 lt lt IKOGA bed
10. LOOXMH SOAOH EQOXH FOOXH 5 5SOQOXH OOXM gOAOH 920XM OC AOH LOACH Laoxu ZHOXMH FHOXH SQAOH 580 LdSSA bod VOX 0VOXY LVOXH tVOXH 5 9VOXd SSA Jad r uid c urd Jeau 5 T SION InOAVT H Pelar s z 2 1 uid jeau Vds E Ldr 1unow m LON LNOAWT xx 4 55 gt lt l or s S 03GDNW SETTE XN3 03qONW 33xs vxId Mid taxy 33X8 vxIH 8 4 03 Q3X4 23XH 49x14 423XH 23XH 23XH B3XM 014 483XH _ B3XM 8 V3XM 914 4V3XH o WAXY 3XIH iH Wax 3 N 4 2 4 1 2 L PIT 2707 5 IGSA Z100A b 185A SSA 3OXM V IH 3OXH 00 8 SAIN 8 OXY SAIH GOXH 2 2AIH B 05 5 2OXN 2AIH 5AM 20x4 9 vas HOXMH 0 Al 8 OAIY OAM BOXY E SSA H30ONN ANZ lt I300W
11. o Flat Panel Displays IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries reserve the right to make corrections modifications enhancements improvements and other changes to its products and services at any time and to discontinue any product or service without notice Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete All products are sold subject to Tl s terms and conditions of sale supplied at the time of order acknowledgment TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with Tl s standard warranty Testing and other quality control techniques are used to the extent Tl deems necessary to support this warranty Except where mandated by government requirements testing of all parameters of each product is not necessarily performed Tl assumes no liability for applications assistance or customer product design Customers are responsible for their products and applications using components To minimize the risks associated with customer products and applications customers should provide adequate design and operating safeguards TI does not warrant or represent that any license either express or implied is granted under any TI patent right copyright mask work right or other TI intellectual property right relating to any combinati
12. ROXA1 RXEE1 ROYA1 RXOE1 ROXA2 RXEE2 ROYA2 RXOE2 GND JP68 ROXA3 RXEE3 ROYA3 RXOE3 GND XD RXEB JP67 ROXA4 RXEE4 ROYA4 RXOE4 6 YD RXOB JP66 ROXAS RXEES 5 RXOE5 JP65 ROXA6 RXEE6 6 RXOE6 NN JP64 ROXBO RXEDO ROYBO RXODO 9 GND JP63 ROXB1 RXED1 RXOD1 10 YC RXOC XC JP62 ROXB2 RXED2 JP26 2 RXOD2 RXOC ROXB3 RXED3 ROYB3 RXOD3 GND ROXB4 RXED4 ROYB4 RXOD4 GND ROXB5 RXED5 ROYB5 RXOD5 YB RXOD ROXB6 RXED6 ROYB6 RXOD6 YB RXOD ROXC0 RXEC0 ROYCO GND ROXC1 RXEC1 ROYC1 RXOC1 GND ROXC2 RXEC2 ROYC2 RXOC2 YA RXOE 43 ROXC3 RXEC3 ROYC3 RXOC3 YA RXOE ROXC4 RXEC4 ROYC4 RXOC4 GND 5 RXEC5 ROYC5 RXOC5 GND ROXC6 RXEC6 6 RXOC6 CK RCLKIN ROXD0 RXEB0 ROYDO CK RCLKIN ROXD1 RXEB1 ROYD1 RXOB1 GND 49 ROXD2 RXEB2 ROYD2 RXOB2 GND ROXD3 RXEB3 ROYD3 RXOB3 ROXD4 RXEB4 ROYD4 RXOB4 ROXD5 RXEB5 ROYD5 RXOB5 ROXD6 RXEB6 ROYD6 RXOB6 RXEA0 RXOA0 ROXE1 RXEA1 ROYE1 RXOA1 JP40 ROXE2 RXEA2 JP5 ROYE2 RXOA2 ROXE3 RXEA3 ROYE3 RXOA3 ROXE4 RXEA4 ROYE4 RXOA4 ROXE5 RXEA5 ROYE5 RXOA5 ROXE6 RXEA6 ROYE6 RXOA6 National Semiconductor Corporation LIT FLINK3V10BT TX RX Flat Panel Displays UM Rev 0 6 5
13. JP54 DIYC4 TXOC4 JP55 DIYC5 5 JP56 DIYC6 TXOC6 JP57 DIYD0 TXOB0 JP58 DIYD1 TXOB1 JP59 DIYD2 TXOB2 JP60 DIYD3 TXOB3 JP61 DIYD4 TXOB4 JP62 DIYD5 TXOB5 JP63 DIYD6 TXOB6 DIXE0 TXEA0 JP29 JP65 JP66 JP67 JP32 DIYE3 TXOA3 JP68 JP69 JP70 m REF Pin REF Pin Name 6 YD TXOB 31 XD TXEB 8 33 GN YC TXOC 36 GND GND 37 YB TXOD _40 GND 2 GND 4 GND GND 42 YB TXOD XB TXED YA TXOE TXEA O z lt m O gt lt O gt 2 pu TXCLK TCLKIN National Semiconductor Corporation LIT FLINKSV10BT TX RX Flat Panel Displays UM Rev 0 6 5 16 2008 Page 9 of 40 FPD Link Evaluation Kit User Manual Bill of Materials Transmitter DS90C3201 Apps TX Demo Board Bill Of Materials Item O gt 8a 8b 8c 10 11 12 13 14 15 16 17 Qty 2 11 11 70 Revision 0c 18 2005 17 00 16 Reference Part C1 C2 2 2uF 5 40 0 1uF C4 C6 C7 C8 C9 C12 C21 22UF C22 C25 C28 C29 C38 C39 C42 10 13 16 18 19 23 0 1uF 26 30 34 36 37 11 14 15 17 20 24 0 01uF C27 C31 C32 C33 C35 C41 0 01uF 1 2 32VDC1A JP74 2 Pin Header JP1 JP21 21X2 Pin Header JP22 JP49 28X2 Pin Header JP50 JP71 22X2 Pin Header
14. National Semiconductor FPD Link Demonstration Kit User Manual P N FLINK3V10BT TX RX Hev 0 6 Flat Panel Displays National Semiconductor Corporation LIT FLINKSV10OBT TX RX 5 16 2008 Page 1 of 40 FPD Link Evaluation Kit User Manual Table of Contents TABLE OF CONTENT 9 e e 255 2 2 INTRODUCTIONS 2 61085055 3 CONTENTS OF THE EVALUATION 4 FPD LINK TYPICAL APPLICATION 4 HOW TO SET UP THE EVALUATION KILL l 6 POWER CONNECTION tmo cm RENS 6 FPD LINK TRANSMITTER BOARD DESCRIPTION 7 CONFIGURATION SETTINGS FOR THE TX BOARD niii nnns rasa assa asas asas acria san inns 8 TX LVTTL LVCMOS AND LVDS PINOUT IDC CONNECTOR a 9 BOM BILL OF MATERIALS TRANSMITTER PCOB 10 RX FPD EINK RECEIVER BOARD J Q J nied 12 CONFIGURATION SETTINGS FOR THE RX BOARD 13 Rx LVDS PINOUT AND LVTTL LVCMOS IDC CONNECTOR sese 14 BOM BILL OF MATERIALS RECEIVER 15 TYPI
15. RES HDC 0805 DIP 8 DIP 6 128ldTQFP VJX128A LIT FLINKSV1OBT TX RX UM Rev 0 6 5 16 2008 Page 11 of 40 FPD Link Evaluation Kit User Manual Rx FPD Link Receiver Board Reference JP1 to JP71 provides access to the 70 bit LVTTL LVCMOS and clock outputs The FPD Link Receiver board is powered externally from the J4 and J5 connectors shown below For the receiver to be operational the Power Down PWDN switch on S2 must be set Rising or falling edge reference clock is also selected by S2 tied to HIGH rising or LOW falling Other device features and configurations can be programmed 2 wire serial interface interface through 74 The 50 pin IDC connector J1 provides the interface for LVDS signals for the Receiver board TDK EMC common mode filters have been added in series on the LVDS signals for high frequency noise suppression Note Vcc and Gnd MUST 5 J2 J3 4 94 95 be applied externally here D LVDS INPUTS 2 VTTL LVCMOS OUTPUTS 3 FUNCTION CONTROLS 4 POWER SUPPLY 5 2 WIRE INTERFACE 2 JP1 JP28 T 2 JP29 JP50 d 2 JP51 JP71 3 COPYRIGHT C 2005 National Semiconductor DS90C3202 APPS RX DEMO BOARD LIT FLINK3V10BT TX RX UM Rev 0 6 5 16 2008 5 3 12 of 40 FPD Link Evaluation Kit User Manual Configuration Settings for the Rx Board Reference Description ___ Closed
16. savas pasn ZLY asen sped zgsj ZLM 10151544 1080 asn 01 1 43S 033XM cade ee KS L33Xu Pos eS 55 aaXu 90840 0 eazy 2141 yuddo 195 2 Sec Scat 99108 Of Ser vaxo P03Xu st Iii prt ae zd 0010 F 85 694 a8 Em ES LOXOH L23XM toss 125 tus bp EPIS LR PO3XM Ew SOXOM SO3XM SS xi 225 990 zyrusdo lt gt 04 0 TOs 0 0 No 050 500510 5 ae 74800 4512 00880 pakon oy POXON Pea L 810 vae Up uddo 0 082 9 558 10020800 SOXON 912 6 9 F Erd M 1 0 lt LO Sorte 84 CERT A 5 949 ewaxy L 3o Tt E19 Sog da Sv3XM 59 ABI F 89 Siri PH 40 Ow TZwAOH 2 32AOH puedo
17. 9 EB0 OB9 represents EVEN pixel data 8 conventional color mapping National Semiconductor Corporation LIT FLINKSV10BT TX RX Flat Panel Displays UM Rev 0 6 5 16 2008 Page 19 of 40 FPD Link Evaluation Kit User Manual LVDS Data Mapping ons TCLK OUT RCLK IN COLOR BIT GB9 RXOA TXOB RXOB RXOC TXOD RXOD 4 ODD 1 Pixel TXEA _ ond p RXEA EVEN 2 Pixel TXEB RXEB TXEC EVEN RXEC TXED RXED TXEE RXEE TCLK OUT RCLK IN COLOR BIT MSB RGB9 RGB8 RXOA TXOB RXOB TXOC RXOC TXOD RXOD RGB0 TXOE RXOE Figure 2 Single 10 Bit Input Mapping JEIDA Compatible National Semiconductor Corporation LIT FLINK3V10BT TX RX Flat Panel Displays UM Rev 0 6 5 16 2008 Page 20 of 40 FPD Link Evaluation Kit User Manual LVDS Data Mapping TCLK OUT RCLK IN RXOA RXOB TXOC RXOC TXOD RXOD TCLK OUT RCLK IN RXOA TXOB RXOB TXOC RXOC TXOD RXOD TCLK OUT RCLK IN RXOA TXOB RXOB TXOC RXOC MSB 8687 LSB MSB RGBO_ Figure 3b Single 8 Bit Input Mapping Alternative Color Mapping Figure 4 Single 6 Bit Input Mapping National Semiconductor Corporation LIT FLINK3V10BT TX R
18. JP72 JP73 JP77 JP78 3 pin Jumper JP76 JP75 IDC2X2 Unshrouded JP79 HEADER 4x1 JP80 3 pin Jumper OPEN J1 IDC25X2 Shrouded J2 J3 J4 95 BANANA J6 DIP 4X2 L1 L2 L3 L4 L5 L6 L7 L8 Z 90 ohm L9 L10 L11 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 49 90hmOPEN National Semiconductor Corporation Flat Panel Displays PCB Footprint CAP EIA B CAP HDC 1206 CAP EIA D CAP HDC 0603 CAP HDC 0603 CAP HDC 0805 Fuse 0603 1608 Header 2P Header 42P Header 56P Header 44P JUMP 3P CON HDR 4P A HDR 4P IDC 50 CON BANANA S DIP 8 20mm x 12mm RES HDC 0201 LIT FLINK3V10BT TX RX UM Rev 0 6 5 16 2008 Page 10 of 40 18 19 20 21 22 23 24 25 26 27 FPD Link Evaluation Kit User Manual 15 16 17 18 19 20 R21 R22 R23 R24 R25 R26 R27 R28 R29 R30 R31 R32 R33 R34 R35 R36 R37 R38 R39 R40 R41 R42 R43 R44 R45 R46 R47 R48 R49 R50 R51 R52 R53 R54 R55 R56 R57 R58 R59 R60 R61 R62 R63 R64 R65 R66 R67 R68 69 70 R71 R72 R73 74 5 6 77 78 79 R80 R81 R82 R83 R84 R85 R86 R87 R88 R89 R90 R91 R92 R95 R96 R97 R93 R94 R98 R99 R100 R101 R102 R103 R104 R105 R106 R107 R108 R109 R110 S1 S2 U1 49 90hmOPEN 10K OPEN 0 Ohm 0805 OPEN 1000hm 0805 0 Ohm 0402 4 75K 10K SW DIP 4 SW DIP 3 DS90C3201 National Semiconductor Corporation Flat Panel Displays RES HDC 0805 RES HDC 0805 RES HDC 0805 RES HDC 0805 RES HDC 0402 RES HDC 0805
19. L LMOGA dOGA TR 105 vos 554 evodA dada TIGA TX RX LIT FLINKSV10BT UM Rev 0 6 5 16 2008 National Semiconductor Corporation Flat Panel Displays Page 35 of 40 FPD Link Evaluation Kit User Manual Sdd 20220650 juatunao 5 Yu mol SLOW LNOAYT P 2 e Woudaa SA 3 3LON 43S HJO V3H evo 4 2725 ______ ___ A L 3SSA whe 300A jadiuir T lt en g d Jeau Ldf gdr HLOg Sadwn Aue arowa P idf 4 2 0 433 ppauuossip ol 2L 1 0 7 HLOG uo uid oj p uid H id apis puer ubu uo 57 2 WONd33 ewa xa 15 uuo3 OY THOM sr aui aug 4400 elg SI YOLKS aug uat Ldf 108 uo uid en si uongrsod t ur si ayy 1 Jokar 10 28 2 NO034d33 asn o z 14 H1Og uo z ALC WOMd33 asn 85 YIN 155 uonaajoud 103
20. 16 2008 Page 14 of 40 FPD Link Evaluation Kit User Manual BOM Bill of Materials Receiver PCB DS90C3202 APPS RX Demo Board Bill Of Materials Item N 9a 9b 9c 10 11 Qty 2 71 10 10 Revision 1 16 2005 13 19 22 Reference Part 4 1 2 2uF C2 C5 C108 0 1uF C3 C6 C35 C36 C41 C42 22UF 47 52 55 62 63 64 110 7 8 9 10 11 12 13 0402 14 15 16 17 18 19 20 21 22 23 24 25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C65 C66 C67 68 69 70 71 72 73 74 75 76 77 78 79 C80 C81 C82 C83 C84 C85 86 87 88 89 90 91 92 93 94 95 96 97 C98 C99 C100 C101 C102 C103 C104 C105 C106 C107 37 39 43 46 48 51 0 01 C53 C57 C59 C61 38 40 44 45 49 50 0 1uF C54 C56 C58 C60 C109 0 01uF F2 F1 32VDC1A JP79 2 Pin Header JP1 JP28 28X2 Pin Header JP29 JP50 22X2 Pin Header JP51 JP71 21X2 Pin Header JP72 JP73 JP75 JP76 3 pin Jumper JP74 HEADER 4x1 National Semiconductor Corporation Flat Panel Displays PCB Footprint CAP EIA B CAP HDC 1206 CAP EIA D CAP HDC 0402 CAP HDC 0603 CAP HDC 0603 CAP HDC 0805 Fuse 0603 1608 Header 2P Header 56P Header 44P Header 42P JUMP 3P HDR 4P LIT FLINK3V10BT TX RX UM Rev 0 6 5 16 2008 Page 15 of 40 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 71 FPD Link Evalu
21. 52 tied to HIGH rising LOW falling Other device features configurations can be programmed via 2 wire serial interface through JP 79 The 50 pin IDC connector J1 provides the interface for LVDS signals for the Receiver board common mode filters have been added in series on the LVDS signals for high frequency noise suppression 4 Jo Ja 5 5 Note Vcc and MUST be applied externally here LVDS OUTPUTS 2 LVTTL LVCMOS INTPUTS FUNCTION CONTROLS 4 POWER SUPPLY JP1 JP21 2 5 2 WIRE JP22 JP49 2 M wu mus 3 5 pz z Z ae pz pz pz z z JP50 JP71 muna mmu m mmmmmmmmm si 0 COPYRIGHT 2005 National Semiconductor DS90C3201 APPS TX DEMO BOARD assy 059063201 REV FLINK3V10BT TX RX Flat Panel Displays 4 UM Rev 0 6 5 5 16 2008 7 of 40 96 S2 FPD Link Evaluation Kit User Manual Configuration Settings for the Tx Board Reference Description Open Closed WRITE PORT 2 wire Serial Interface Write Enabled Write Protected J74 Write Protect o Default setting for 474 is set Open to VSS Write Enabled S1 Transmitter Features Selection Description 1 H 581 ENable Bank Disabl
22. IDONW TIL TSSA 30Yw COL L OOXL DOKL BOXL 80 1 VOXL WORL ISSA 181611 OAYSSY spen 065 5 p pepus e Buis 05 TUDI 93x10 exl L3XIC 03XIQ EOXIKC 92x10 FAXIO 0510 saxa LvXIO LIT FLINK3V10BT TX RX Rev 0 6 5 16 2008 National Semiconductor Corporation Flat Panel Displays Page 28 of 40 FPD Link Evaluation Kit User Manual x sddw 102850650 3ssA c uid T lt i san eI H m WOud33 J LON H35fl H3QvaiH 2705 4 2125 2551 3554 2 bial uid HL pue due IONd33 4393 PJeoquo 13ouuo3sip 0 pug adf uo g uid aj p urd HOSS dt WOMd33 WO d33 pue gdr H1O8 uo
23. WRITE PORT 2 wire Serial Interface Write Enabled Write Protected 479 Write Protect o Default setting for J79 is set Open to VSS Write Enabled S2 Receiver Features Selection Description L 52 Bank Disabled Enabled MODE1 ODD Data Channels Default MODEO EVEN Data Channels Default s RFB Rising or Falling Data Falling Rising SIISE OU 29042 PWDNB PoWerDowN Bar Powers Operational Down Default S2 External EEPROM Slave Address Reference Description S1 __ Default LOW Default LOW Default LOW Default setting for S1 is set to all LOW External EEPROM Slave Address A 2 0 2000 National Semiconductor Corporation LIT FLINKSV10BT TX RX Flat Panel Displays UM Rev 0 6 5 16 2008 Page 13 of 40 FPD Link Evaluation Kit User Manual Rx LVDS Pinout and LVTTL LVCMOS by IDC Connector The following two figures illustrate how the Rx outputs are mapped to the IDC connectors JP1 to JP71 Note labels are also printed on the demo boards The LVDS 50 pin IDC connector J1 pinout is also shown LVDS INPUTS J1 BANK X OUTPUTS BANK Y OUTPUTS ODD Data Channels EVEN Data Channels EVEN Data Channels ODD Data Channels REF Pin Name No REF Pin Name XE RXEA YE RXOA YE RXOA Symbol Symbol REF Pin Name REF Pin Name RXEE0 JP35 ROYAO RXOEO
24. CAL CONNECTION AND TEST EQUIPMENTI A 17 TWO WIRE SERIAL COMMUNICATION INTERFACE DESCRIPTION 19 EN DS IDATA NAPPING cc 19 EV DS onnar kumi yanapa 20 EV DS DATA MAPPING G unakunaqa eens evade eaters 21 O Bip a u u u u nu 22 TROUBLESHOOTING 222 a ea a a ae 24 ADDITIONAL INFORMATION uuu 2004 352254 44 25 5 S 25 S55 2125 52 42252 252222222 220213222202 20 202 0 203220 22 2224232 222012022 200 222222222 22223 20 22212222 2 0 25222 222522 20 26 National Semiconductor Corporation LIT FLINK3V10BT TX RX Flat Panel Displays UM Rev 0 6 5 16 2008 Page 2 of 40 FPD Link Evaluation Kit User Manual Introduction National Semiconductors Flat Panel Displays FPD Link evaluation kit contains a Transmitter Tx board a Receiver Rx board along with interfacing cables This kit will demonstrate the chipsets interfacing from test equipment or a graphics controller using Low Voltage Differential Signaling LVDS to a receiver board The DS90C3201 DS90C3202 are 10 bit color Transmi
25. LIT FLINKSV10BT TX RX Flat Panel Displays UM Rev 0 6 5 16 2008 Page 25 of 40 FPD Link Evaluation Kit User Manual Appendix National Semiconductor Corporation LIT FLINK3V10BT TX RX Flat Panel Displays UM Rev 0 6 5 16 2008 Page 26 of 40 FPD Link Evaluation Kit User Manual Tx PCB Schematic peog oua x1 sddy 102520680 Jequinw 9102 n5 zo z T eprs ics ca pas sseuxorurn 860070 n gt Pas 0020 7 zo eue d zo z I eprs ________ lt s _6___ T H4 1 pseog 2 p4eoq sake 1 LIT FLINK3V10BT TX RX National Semiconductor Corporation cO 5 ooh oa x 9 Flat Panel Displays FPD Link Evaluation Kit User Manual 554 uid s a m a ip 1 sddw 02520650 1 mug ii 4 0 171 4 1 1 2100 LUC SSA v ALL ev LU E ACC ira HS 0 Lod od us J og 55 SSA b LOOM TOL 5T
26. X Flat Panel Displays UM Rev 0 6 5 16 2008 Page 21 of 40 FPD Link Evaluation Kit User Manual 6 bit 8 bit 10 bit Application TXCLK OUT RCLK IN Differential lt lt 1 cycle LVDS Data Outputs Inputs Single LVDS Data Mappinc 1 EO RO _ L Et j ___22 00 ___ G _ EA j B _ ES j Alternative Input Color Mapping National Semiconductor Corporation LIT FLINK3V10BT TX RX Flat Panel Displays UM Rev 0 6 5 16 2008 Page 22 of 40 FPD Link Evaluation Kit User Manual Dual LVDS Data Mappino ODD Pixel Data TXE RXE EVEN Pixel Data __85 9 R9 BO Gi G Gi G5 G G G Bi 04 G2 Ge Bi 2 64 Ge G2 G2 B2 G3 G5 G3 G7 B2 G3 G5 G3 G7 B3 G4 G6 G4 G8 B3 G4 G6 G4 G8 4 G5 G7 G5 G9 B4 G5 G7 G5 G9 B5 BO B2 BO B4 B5 BO B2 BO B4 B6 B1 B3 5 B6 B1 3 B1 B CO C2 D R6 Di R D Ge D 101 07 D4 86 D Bf 87 D _ E __22 ES __24 _ E Fo Alternative Input Color Mapping National Semiconductor Corporation LIT FLINK3V10BT TX RX Flat Panel Displays UM Rev 0 6 5 16 2008 Page 23 of 40 FPD Link Evaluation Kit User Manual Troubleshooting If the demo boards
27. ation Kit User Manual JP78 JP77 IDC2X2 Unshrouded JP80 3 pin Jumper OPEN J1 IDC25X2 Shrouded J2 J3 J4 J5 BANANA J6 DIP 4X2 L1 L2 L3 L4 L5 L6 L7 L8 Z 90 ohm L9 L10 L11 R1 R2 R3 R4 R5 R6 R7 R8 100 0201 R9 R10 R11 R12 R13 R14 R15 R16 R17 0201 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 R30 R31 R32 R33 R34 R35 R36 R37 R38 R39 R40 R41 R42 R43 R44 R45 R46 R47 R48 R49 R50 R51 R52 R53 R54 R55 R56 R57 R58 R59 R60 R61 R62 R63 R64 R65 R66 R67 R68 R69 R70 R71 R72 R73 R74 R75 R76 R77 R78 R79 R80 R81 R82 R83 10K OPEN R84 0 Ohm 0805 OPEN R85 R86 R87 R88 R89 R90 0 Ohm 0402 R91 R92 R95 R96 R93 R94 R97 R98 R103 4 75 104 105 106 99 100 101 102 107 10K 108 109 51 SW DIP 3 S2 SW DIP 4 U1 DS90C3202 National Semiconductor Corporation Flat Panel Displays CON HDR 4P A JUMP 3P IDC 50 CON BANANA S DIP 8 20mm x 12mm RES HDC 0201 RES HDC 0201 RES HDC 0805 RES HDC 0805 RES HDC 0402 RES HDC 0805 RES HDC 0805 DIP 6 DIP 8 128lIdTQFP VJX128A LIT FLINK3V10BT TX RX UM Rev 0 6 5 16 2008 Page 16 of 40 FPD Link Evaluation Kit User Manual Typical Connection and Test Equipment The following is a list of typical test equipment that may be used to generate signals for the TX inputs 1 Digital Video Source for generation of specific display timing such as Digital Video Processor or Graphics Controller with digital RGB LVTTL output 2 Astro System
28. duces current draw when the link is not required Other device features and configurations can be programmed via 2 wire serial interface National Semiconductor Corporation LIT FLINKSV10OBT TX RX Flat Panel Displays UM Rev 0 6 5 16 2008 Page 3 of 40 FPD Link Evaluation Kit User Manual Contents of the Evaluation Kit 1 One Transmitter board with the DS90C3201 2 One Receiver board with the DS90C3202 3 One 50 pin IDC Flat Ribbon Cable 4 Evaluation Kit Documentation this manual 5 DS90C3201 3202 Datasheet FPD Link Typical Application VSYNC VSYNC 2 rdc A nw F Host Display PC Graphics Board Video Processor LCD Monitor LCD TV Digital TV LVDS p 5 i Pixel D Pixel Data DS90C3201 5 Pairs DS90C3202 Clock FPD Link FPD Link Bo la Transmitter Receiver _ gt LVDS Clock Video Processor Board Input An alog 26 Processor Digital Video Input e Graphics Controller FPD Link Tx Video NTSC PAL Input Decoder LVCMOS LVTLL LCD Monitor LCD TV Digital TV FPD Link Rx y LVCMOS LVTLL LCD Drivers p LCD Controller gt Timing Custom Logic Figure 1b Typical FPD Link System Diagram National Semiconductor Corporation LIT FLINK3V10BT TX RX Flat Panel Display
29. e Ea WORE TVOXLP3AIQd O pi zd 22502 0 1 494 EINO oh ctdr 2006 6 9997 ee SoA VOR at 5 Edr ar ge 13 00 gt WOXL 2 Otdf TE Fala roar O34 Ov CHE QvOXL 0344 SSA ci ele of ele ob ole i e LI s 5 LI LI i wd z z z OOF moa 90 90 0 amp c i t9d 2 20 0980 1 c y83X1 vaxia 2 9 9 o4 2997 ce SOA SORE V o 288 ra blu z TH DEL TBH XL Mall 7 ar BOKL 80xl Sgar 183X1 gx lt o 4 6597 qA 20 12801 ZHOXIZOAK D83X1DCXEI 9 Sd IBOXl S SZdr OBCEL 08 Tzar 923 1 400 1 3040 Oa Lzdr soari Z o 971 1220415947045 c5 EXKL O T gt O T ozar 23 1 POM ir I 701 t 2091 oripa 9 97 eldar zO3XL
30. ecifically governing such use Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications and acknowledge and agree that they are solely responsible for all legal regulatory and safety related requirements concerning their products and any use of TI products in such safety critical applications notwithstanding any applications related information or support that may be provided by TI Further Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in such safety critical applications TI products are neither designed nor intended for use military aerospace applications or environments unless the TI products are specifically designated by TI as military grade or enhanced plastic Only products designated by TI as military grade meet military specifications Buyers acknowledge and agree that any such use of TI products which TI has not designated as military grade is solely at the Buyer s risk and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use TI products are neither designed nor intended for use in automotive applications or environments unless the specific products are designated by TI as compliant with ISO TS 16949 requirements Buyers acknowledge and agree that if they use any non designated products in automotive applications TI will not be responsib
31. ed Enabled MODE1 Data Channels Default ENX ENable X Bank Disabled Enabled MODEO EVEN Data Channels Default strobe Default Down Default S2 External EEPROM Slave Address Reference Description 52 __ Default LOW Default LOW AO Slave Address 0 Default LOW Default setting for S2 is set to all LOW External EEPROM Slave Address 2 01 000 National Semiconductor Corporation LIT FLINKSV10BT TX RX Flat Panel Displays UM Rev 0 6 5 16 2008 Page 8 of 40 FPD Link Evaluation Kit User Manual Tx LVTTL LVCMOS and LVDS Pinout by IDC Connector The following two figures illustrate how the Tx inputs are mapped to the IDC connectors to JP71 Note labels are also printed on the demo boards LVDS outputs for the 50 pin IDC J1 connector pinout are also shown BANK X INPUTS BANK Y INPUTS LVDS OUTPUTS J1 EVEN Data Channels ODD Data Channels ODD Data Channels EVEN Data Channels Symbol Symbol pin Name No REF in Name 7 DIYA1 TXOE1 JP38 DIXA2 JP3 DIYA2 TXOE2 DIXA2 2 JP39 DIYA3 JP40 DIYA4 TXOE4 JP41 DIYA5 TXOES JP42 DIYA6 TXOE6 JP43 DIYB0 TXOD0 JP44 DIYB1 TXOD1 4 45 DIYB2 TXOD2 JP46 DIYB3 TXOD3 JP47 DIYB4 TXOD4 JP48 DIYB5 TXOD5 JP49 DIYB6 TXOD6 JP50 DIYC0 TXOC0 JP51 DIYC1 TXOC1 JP52 DIYC2 TXOC2 JP53 DIYC3 TXOC3
32. eiver board to the panel Note Refer Page 19 for suggested mapping schemes A scramble cable may be required 4 Power for the Tx and Rx boards must be supplied externally through Power Jack VDD Grounds for both boards are connected through Power Jack VSS see section below 5 2 wire serial interface for external EEPROM circuitry power is supplied through Power jack VDDE and Ground for Power Jack VSSE Power Connection he Iransmitter and Receiver boards must be powered by supplying power externally through J2 VDD 93 VSS on Transmitter Board and J4 VDD and J5 VSS on Receiver board The maximum voltage that should ever be applied to the FPD Link Transmitter D890C3201 or Receiver 0590 3202 VDD terminal is 4V MAXIMUM Optional EEPROM circuitry power is supplied through J4 VDDE J5 VSSE or JP79 on Transmitter Board and J2 VDDE J3 VSSE or JP74 on Receiver Board National Semiconductor Corporation LIT FLINKSV10OBT TX RX Flat Panel Displays UM Rev 0 6 5 16 2008 Page 6 of 40 FPD Link Evaluation Kit User Manual FPD Link Transmitter Board Description JP1 to JP71 IDC connectors accepts 70 bits LVTTL LVCMOS RGB data along with the clock input The FPD Link Transmitter board is powered externally from the J2 43 connectors shown below For the transmitter to be operational the Power Down PWDN switch 52 must be set HIGH Rising or falling edge reference clock is also selected by
33. gister values are programmed and stored in an onboard EEPROM via a two wire serial interface and a PC compatible system Upon power up default control register values will be loaded into Tx Rx Otherwise registers may be programmed directly from the EEPROM into the Tx Rx control registers via this same two wire serial interface method LVDS Data Mapping The FPD Link Receiver which receives video data and timing through 10 pairs of LVDS channels plus 1 LVDS clock to provide 30 bit dual color depth The Transmitter converts L VT TL LVCMOS parallel lines into ten serialized LVDS data pairs plus a LVDS clock The video data stream is then converted to LVTTL LVCMOS parallel data The device accepts 10 bit 8 bit 6 bit single dual input data mapping as shown and also supports the JEIDA standard for 10 bit LVDS Single Dual Single Dual Single Dual 10 bit MSB R9 9 9 09 9 9 B9 OB9 EB9 OR8 ER8 08 _ 8 EG8 OB8 EB8 8 bit MSB OR6 ER6 6 EG6 OB6 6 6 bitMSB 5 OR5 ER5 GS 5 5 5 5 5 ________ R4 4 G4 OG4 EG4 B4 R3 ORS ER3 OB3 EB3 R2 2 2 G2 OG2 EG2 B2 2 2 RI ORI ER G1 OGI EG LSB RO GO OGO EGO BO OBO EBO Note ORO ORS OG0 OG9 OBO OBO represents ODD pixel data ERO ORS9
34. ion Kit User Manual peog 0Zgr206S0O Jano uo sud pajer2osse oj 21915504 4122154 se aso 2 se wyo 04192 9FH SSA Lr119 96 W ld 411 ganto Jnzz SED T 86 it zorg MUO 0 FOGA lt lt M Lr jo 58 uid anzz Bar Xs uid azz 250 F oj 15 ZOPM NO 0 lt lt SSA Lio 91 uid 40 440107 anzz T sg 86 A e SALON LM yo ag uid Jeau angg DEL OF CORD uuo 0 lt lt EHOOA A82 14021 jo 2 uid Jeau CHO rS WU 0 lt lt TUGOM i Lm jo 52 uid Jesu Ane P3 corp WHO 0 lt lt LOCA 965 SSA LN 9 5 sud Jeau angg cosa lt LO JO 61 Suid Jesu arnee lt lt 1110 001 uid Jeau 2 TX RX LIT FLINK3V10BT UM Rev 0 6 5 16 2008 National Semiconductor Corporation Flat Panel Displays Page 38 of 40 VLOCAZE ld FPD Link Evaluation Kit User Manual SSA peog xH Sdd 202 00630 JO 10151591
35. le for any failure to meet such requirements Following are URLs where you can obtain information on other Texas Instruments products and application solutions Products Applications Audio www ti com audio Automotive and Transportation www ti com automotive Amplifiers amplifier ti com Communications and Telecom www ti com communications Data Converters dataconverter ti com Computers and Peripherals www ti com computers DLP Products www dlp com Consumer Electronics www ti com consumer apps DSP dsp ti com Energy and Lighting www ti com energy Clocks and Timers www ti com clocks Industrial www ti com industrial Interface interface ti com Medical www ti com medical Logic logic ti com Security www ti com security Power Mgmt power ti com Space Avionics and Defense www ti com space avionics defense Microcontrollers microcontroller ti com Video and Imaging www ti com video RFID www ti rfid com OMAP Mobile Processors www ti com omap Wireless Connectivity www ti com wirelessconnectivity TI Community Home Page e2e ti com Mailing Address Texas Instruments Post Office Box 655303 Dallas Texas 75265 Copyright 2012 Texas Instruments Incorporated
36. not performing properly use the following as a guide for quick solutions to potential problems If the problem persists please contact the local Sales Representative for assistance rag CHECKS Check that Power and Ground are connected to both Tx AND Rx boards Check the supply voltage typical 3 3 and also current draw with both Tx and Rx boards should be about 100mA with clock and one data bit at 135 2 3 Verify input clock and input data signals meet requirements VIL VIH tset thold Also verify that data is strobed on the selected rising falling RFB pin edge the clock 4 Check that Jumpers and Switches are set correctly 5 Check that the cable is properly connected TROUBLESHOOTING CHART Problem There is only the output clock There is no output data No output data and clock Power ground input data and input clock are connected correctly but no outputs The devices are pulling more than 1 current After powering up the demo boards the power supply reads less than 3V when it is set to 3 3V National Semiconductor Corporation Solution Make sure the data is applied to the correct input pin Make sure data is valid at the input Make sure Power is on Input data and clock are active and connected correctly Make sure that the cable is secured to both demo boards Check the Power Down pins of both boards and make sure that the devices are enabled PD Vcc f
37. nterface Digital RGB Contoller JU Cable A TTL to Panel e c e e i e Contents of Demo Kit Graphics Controller Video Processor Board Figure 2 Typical FPD Link Setup of LCD Panel Application National Semiconductor Corporation LIT FLINK3V10BT TX RX Flat Panel Displays UM Rev 0 6 5 16 2008 Page 17 of 40 FPD Link Evaluation Kit User Manual The picture below shows a typical test set up using a generator and scope Transmitter Receiver Board Board 00 00 00 00 2 000 1000 a SI 100 d Digital RGB AA ABA A A RRRA 1005 LVDS In
38. on machine or process in which TI products or services are used Information published by TI regarding third party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof Use of such information may require a license from a third party under the patents or other intellectual property of the third party or a license from Tl under the patents or other intellectual property of TI Reproduction of Tl information in Tl data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties conditions limitations and notices Reproduction of this information with alteration is an unfair and deceptive business practice TI is not responsible or liable for such altered documentation Information of third parties may be subject to additional restrictions Resale of Tl products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice is not responsible or liable for any such statements Tl products are not authorized for use in safety critical applications such as life support where a failure of the TI product would reasonably be expected to cause severe personal injury or death unless officers of the parties have executed an agreement sp
39. or operation Check for shorts in the cables connecting the TX and RX boards Use a larger power supply that will provide enough current for the demo boards a 500mA power supply is recommended LIT FLINK38V10BT TX RX UM Rev 0 6 5 16 2008 Page 24 of 40 Flat Panel Displays FPD Link Evaluation Kit User Manual Additional Information For more information FPD Link Transmitters Receivers refer to the National s LVDS website at www national com appinfo fpd Equipment References Note Please note that the following references are supplied only as a courtesy to our valued customers It is not intended to be an endorsement of any particular equipment supplier Digital Video Pattern Generator Astro Systems VG 835 or equivalent Astro Systems 425 5 Victory Blvd Suite A Burbank CA 91502 Phone 818 848 7722 Fax 818 848 7799 WWW astro systems com EEPROM Programming FDI PC I2C kit or equivalent Future Designs Inc 2702 Triana Boulevard SW Huntsville AL 35805 oales 800 278 0293 Information 256 883 1240 FAX 256 883 1241 www teamfdi com Optional EMI Filters TDK Chip Beads or equivalent TDK Corporation of America 1740 Technology Drive Suite 510 san Jose CA 95110 Phone 408 437 9585 Fax 408 437 9591 www component tdk com Local U S A direct contact Kazuhiko Kevin Umeda Phone 408 467 5222 Email kumeda tdktca com National Semiconductor Corporation
40. s UM Rev 0 6 5 16 2008 Page 4 of 40 FPD Link Evaluation Kit User Manual The diagrams above illustrate the use of the Chipset Tx Rx in a Host to Flat Panel Interface Chipsets support up to 18 bit 24 bit and 30 bit color depth TFT LCD Panels for any VGA 640X480 SVGA 800X600 XGA 1024X768 WXGA 1280X768 SXGA 1280X1024 SXGA 1400X1050 HDTV 1920X1080 resolutions Refer to the proper datasheet information on Chipsets Tx Rx provided on each board for more detailed information National Semiconductor Corporation LIT FLINK3V10BT TX RX Flat Panel Displays UM Rev 0 6 5 16 2008 Page 5 of 40 FPD Link Evaluation Kit User Manual How to set up the Evaluation Kit The PCB routing for the Tx input pins TxIN have been laid out to accept incoming data from IDC connectors The TxOUT RxIN interface uses a 50 pin IDC connector through a IDC ribbon cable Please follow these steps to set up the evaluation kit for bench testing and performance measurements 1 Connect one end the 50 pin IDC cable to the transmitter board and the other end to the receiver board Longer lengths can be used 2 Jumpers and switches have been configured at the factory they should not require any changes for operation of the chipset See text on Configuration settings for more details 3 From the Video Decoder board connect a flat cable not supplied to the transmitter board and connect another flat cable not supplied from the rec
41. s VG 835 This video generator be used for both video signal sources for 10 bit Digital RGB and 10 bit LVDS 3 Any other signal video generator that generates the correct input levels as specified in the datasheet 4 Optional Logic Analyzer or Oscilloscope The following is a list of typically test equipment that may be used to monitor the output signals from the 1 LCD Display Panel which supports digital RGB LVTTL inputs 2 Astro Systems VG 835 This video generator be used for both video signal sources for 10 bit Digital RGB and 10 bit LVDS 3 Optional Logic Analyzer or Oscilloscope 4 Any SCOPE with 50 Ohm inputs or high impedance probes LVDS signals may be easily measured with high impedance high bandwidth differential probes such as the TEK P6247 or P6248 differential probes EEPROM Programming 1 Future Designs Inc PC I2C KIT This kit interfaces with IBM PC Compatible and allows bi directional communications with 2 wire serial interface peripherals The picture below shows a typical test set up using a Graphics Controller and LCD Panel Transmitter Receiver Board Board 00 00 00 00 Er iT gt LCD Panel Digital RGB TTL C from Graphic LVDS I
42. tertace 4 D4 gt d gs TN Cable mum PC Compatible Logic Analyzer Oscilloscope Contents of Demo Kit Digital RGB 0110 IO IN o o 8 Digital Video Source Figure 3 Typical FPD Link Test Setup for Evaluation National Semiconductor Corporation LIT FLINK3V10BT TX RX Flat Panel Displays UM Rev 0 6 5 16 2008 Page 18 of 40 FPD Link Evaluation Kit User Manual Two Wire Serial Communication Interface Description Optional 2 wire serial interface programming allows fine tuning in development and production environments The DS90C3201 3202 is programmed through a 2 wire serial interface The 2 wire protocol features a serial clock S2CLK and a bi directional serial data line S2DATA DS90C3201 3202 operates as slave the Serial Bus so the S2CLK line is an input no clock is generated by the DS90C3201 3202 DS90C3201 3202 has a fixed 7 bit slave address which is set to 111111074 7C h 1111100 for DS903201 3202 respectively The Interface connector 79 Tx and 74 Rx is a 4 pin connector pin header for interfacing with external EEPROM J79 Tx JP74 Rx is designed to interface with the FDI 12 kit through connector or an equivalent type as described Re
43. tter and Receiver chipset designed to transmit data at clocks speeds from 8 to 135 MHz Using a 10 bit color depth system the 30 bit RGB color produces over 1 07 billion colors to represent high definition displays in their most natural color The dual high speed LVDS channels supports single pixel in single pixel out and dual pixel in dual pixel out transmission modes The Transmitter board accepts LVITL LVCMOS RGB signals from the graphics controller along with the clock signal The LVDS Transmitter converts the LVITL LVCMOS parallel lines into ten serialized LVDS data pairs plus a LVDS clock The serial data streams toggle at 3 5 times the clock rate With an input clock at 135 MHz the maximum transmission rate of each LVDS line is 945Mbps for an aggregate throughput rate of 9 45Gbps This allows the 10 bit color LVDS Receiver to support resolutions up to HDTV The Receiver board accepts the LVDS serialized data streams plus clock and converts the data back into parallel LVTTL LVCMOS RGB signals and clock for the panel timing controller The user needs to provide the proper RGB inputs and clock to the Transmitter and also provide a proper interface from the Receiver output to the LCD panel or test equipment The transmitter and receiver boards can be used to evaluate device parameters A cable conversion board or harness scramble may be necessary depending on type of cable connector interface used A power down feature is also provided that re
Download Pdf Manuals
Related Search