Evaluation System User`s Manual
Contents
1. MCLK is low The resulting output signal as shown in the example timing for a Black Level 5V and a Video 4V is a signal toggling between 5V and 4V with the EMCLK BLACK LEVEL 5 xxx VIDEO V OUTx FIGURE 6 BASIC FUNCTION OF ANALOG SWITCH To be able to test the XRD9818 for DNL amp INL type specifications a sine wave generator can be connected to the Video input that has its peaks at 5V and 2V This will cause the output of the XRD9818 to generate a digital sinewave that goes from zero code to full scale under the following conditions CCD mode GS 0 gain 1x and offset reg adjusted to correct for any system offsets A reset pulse can be added to the emulated CCD signal by the use of the clamping amplifier U8 It operates on the same principle as the EL4331 but has a faster settling time The reset pulse can be adjusted by the input levels to the device The clocking is done by the RSCLK provided from the FPGA An example of an emulated CCD signal with reset pulse is shown below in Figure 7 43 00 Y E Ch2 1 00 V Mjd0 0ns A Ch E 2 00V 17 Feb 2004 ih 11 2000ns 12 05 14 FIGURE 7 EXAMPLE OF CCD EMULTOR OUTPUT WITH RESET PULSE XRD9818EVAL EVALUATION SYSTEM USER MANUAL REV 1 0 0 3 6 Digital Output Interface The interface to a Logic Analyzer is a 17x2 header S5 Z EXAR It provides 16 bits of data latch clock and individual ground for each signal The rising edge of the latch clock i2. VAL SCHEMATICS FIGURE 8 XRD9818 amp SPARTAN II Z EXAR HEADER 4X2 svez smsa sves BSAMFAe maus ri amp Red Input K Green Input A n Bue Input Commen Ref Input VDDA3v i K CMREF amp capP Souen VDpAav 1 2 3 HEADER 3 ADCO S ADCO I ADCO ZI XRD9818 Spartan Il FPGA XC2850 8 amp RESETCLK KEMctk 3 Idella CONNECT AGND BAR AGND BAR 3 ack sbn HAORCAD PROJECTS 9818 9818EVAL_3A DSN rie XRD9818 amp Spartan Il Document Number XRD9818EVAL Bate Monday March 24 2003 Oscilator_o EMCLK gt gt high gt black level low gt video level BLACK LEVEL AGND RED VIDEO JUMPER gt gt Re
3. XRD9818EVAL Z EXAR EVALUATION SYSTEM USER MANUAL REV 1 0 0 XRD9818EVAL Evaluation System User Manual ET E CA o RR Or T Oh usse ais E l H PLA 17 Ys alba EITHER D 02232095020020 a A 1 i so HET 00 S oo YEE XAR uiu XRD9818EVAL REVISION A 3 CH 16 BIT LINEAR CCD CIS MARCH 2003 TEIL imm ZZ EXAR XRD9818EVAL EVALUATION SYSTEM USER MANUAL REV 1 0 0 1 0 FEATURES e XRD9818 28 pin TSSOP e FPGA Xilinx Spartan Il XC2S50 e In System PROM XC18V01 e Graphical User Interface GUI with 25 pin Din Connector for a Standard Parallel Port Interface e Single Oscillator for Complete Timing Generation and Control Analog Switch EL4331 for Emulating CCD Signals e Clamping Amplifier AD8036 for Reset Pulse Emulation e Line Clamp Control for 40 000 Pixels e De Multiplexed Output Provided on a 17 pin Header including a Digital Output Clock 2 0 GENERAL DESCRIPTION The XRD9818EVAL board is designed to be a test platform that provides a means to evaluate the performance and functionality of the XRD9818ACG The eval board contains a Xilinx FPGA that provides all timing signals required for the proper operation of the XRD9818ACG The timing and functionality of the FPGA will adjust and conform to the mode of operation of the XRD9818ACG A Graphical User Interface GUI allows the evaluation platform to be configured to setup and test the XRD9818ACG in any of its possible modes of opera
4. ain and Offset controls for the individual channels Red Green and Blue registers O thru 5 are controlled here To modify the gain or offset values simply click on the bit you want to change It will toggle between a 1 and a 0 The register value in HEX is shown just to the right To zero out the register contents reset to default value simply set the O bit just to the right of the register value For the definition of the gain and offset registers see the XRD9818 data sheet 3 1 2 Mode Options This section sets the variables defined in the XRD9818 s MODE 1 register Channel selection clamp level output data format gain range select imager mode and line clamp operation are defined by the pull down tabs Not only is the XRD9818 s internal MODE 1 register is programmed but the FPGA will automatically adjust the System timing where needed to evaluate the device in the desired configuration For the definition of the MODE 1 register see the XRD9818 data sheet 3 1 3 Delay Registers They set the internal delays added to the BSAMP VSAMP ADCLK and ADCO data output delay Delays can be added to the sampling clocks BSAMP VSAMP amp ADCLK and data valid to help maximize performance of the XRD9818 and it s flexibility to externally applied timing For the definition of the delay registers see the XRD9818 data sheet 3 1 4 Polarity Options amp Control Options This section sets the variables defined in the XRD9818 s MODE 2 register The
5. d Input JUMPER US gt gt Green Input EL4331C JUMPER gt gt Blue Input AGND BLU VIDEO 3 Common Ref Input AU M JUMPER RESETCLK gt RESET PULSE LEVEL R34 AD8036 AGND open BLACKLEVEL R36 140 H ORCAD PROJECTS 9818 9818EVAL_3A DSN A Title Tout Pixel Emulator Circuitry with Reset Pulse Bize Document Number B XRD9818EVAL ate Monday March 24 2003 C22 lt 2 z lt oc LLI o 2 Lu ke o gt 0 z o ke lt 2 lt gt U eo S D Ko FIGURE 9 CCD EMULATOR l st gt DI ceo co o a tc x lt x gt Lu T co o a tc x EVALUATION SYSTEM USER MANUAL REV 1 0 0 FIGURE 10 POWER AND BYPASS CIRCUITRY POWER AND BYPASS CIRCUITRY BANNANA PLUGS SV VCC US LT1174 IN C29 10uF C81 T 22uF AGND AGND CMREF X H ORCAD PROJECTS 9818 9818EVAL_3A DSN Title Power amp Decoupling Ge B Document Number XRD9818EVAL ate Wednesday April 30 2003 10
6. ns that relate to various register functions of the XRD9818 and control features of the evaluation system Color Options Mode Options Delay Registers Polarity Options Control Options CPLD Options and Register Dump Any changes become activated when the Update button is hit XRD9818 Test xj File m Color Options Mode Options Register Dump Red Green Blue Line Clam Clamp Level Select reen Blue lor SS m S PGA yau D CCD CIS Gain Select rs mager ain selec Dynamic Offset Byte Nibble Mode Input Mux Ch Select DM 0 91T 0 0 91919 0 oo Byte Output 3 Channels DI m Delay Registers Polarity Options r Control Options BSMP Rise Delay BSMP Fall Delay ADC polarity Power Down Chip o of of of of o o o of o LCLMP polarity Tri state Output op GO Cr CX CO C0 Cl P CO P2 C VSMP Rise Delay VSMP Fall Delay BSMP polarity BOUE o d d d d o o of of of KE e VSMP polarity Read Back ADC Delay ADCO Delay CPLD Options d d d d d d of o oj o Color Grab fan Channels Reset CPLD FIGURE 3 XRD9818 GUI GRAPHICAL USER INTERFACE Z EXAR XRD9818EVAL EVALUATION SYSTEM USER MANUAL REV 1 0 0 Configurations can be saved and reloaded via the File pull down control located in the upper left hand corner of the GUI display FIGURE 4 XRD9818 Test File df o ol o o ol o t 3 1 1 Color Options The XRD9818 s G
7. om the 9818 s internal registers If the evaluation platforms is performing a readback operation the first clock after SCS goes high is required to latch the parallel data output from the 9818 and the next 10 clocks shift out the register content data msb first XRD9818 GUI Write Read Timing A E E A ENA dc as a2 A1 AO dc D9 DB D7 D6 D5 D4 D3 D2 D1 DO D9 D8 D7 D6 D5 D4 D3 D2 D1 DO gt lt gt Address Write Data Read Data FIGURE 5 XRD9818EVAL GUI INTERFACE TIMING Z EXAR XRD9818EVAL EVALUATION SYSTEM USER MANUAL REV 1 0 0 3 5 CCD Emulator Circuitry The emulation circuitry is intended to provide a pseudo CCD signal in order to evaluate the XRD9818 when configured for CCD operation This is accomplished by the use of an analog switch EL4331C as seen in the evaluation board schematic The basic function of the EL4331C U5 is to switch each channels output between the its two inputs signals according to the polarity of the EMCLK timing signal The inputs for each channel will be used to emulate the black reference level and video level of a CCD signal If you look at the Figure 6 below you will see that the EMCLK connects the Black Level INxA pins 3 6 12 of U5 input to the output when high and the Video input INxB pins 4 5 11 of U5 when the E
8. ontrol information from the GUI and performs the appropriate write read operation with the XRD9818 In addition to configuring the XRD9818 it will provide the appropriate timing signals to the evaluation system required to operate the XRD9818 in that mode For example if the XRD9818 is configured for 3 CH CCD mode and nibble output operation the FPGA will provide the correct timing adjustments to the ADCLK BSAMP VSAMP emulator clks and 16bit out latch with sample clock so that the user does not need to adjust any of their equipment 3 3 In System PROM XC18V01 The FPGA can be programmed in two ways A standard JTAG header is provided to allow programming each time the XRD9818EVAL is powered up Or an in system PROM is provided to automatically program the FPGA upon power up The JTAG header allows flexibility to provide verilog source codes for customer verification 3 4 25 DIN Parallel Connector for PC Interface The 25 DIN connector establishes the connection for the GUI control over the XRD9818EVAL through the parallel port of a PC The GUI provides all serial port configurations XRD9818 plus options for controlling the XRD9818EVAL When selecting options through the GUI the program bursts the FPGA input with the pattern shown below in Figure 5 Please note that the pattern is not the same as the serial write pattern to the serial timing port of the XRD9818 The extra SCLK s after SCS goes back high are required for a readback operation fr
9. polarity of the input timing to the XRD9818 can be individually set to be either active high default or active low Power down and output enable are set via the Control Options interface 3 1 5 Register Dump The internal register configuration of the XRD9818 can be read back via the register dump When the ReadBack button is hit the register configuration is read and displayed in hex The registers are listed from top to bottom by address A description of the readback operation is described in the XRD9818 data sheet 3 1 6 CPLD options The channel output sample clock is defined by the Color Grab The Xilinx FPGA provides a data valid clock to the data header S5 to be used to sample the output data For example if the XRD9818 is being operated in 3 CH mode all three channel s output data is sampled when the Color Grab is set to All Channels Individual channel outputs can be sampled while in 3 CH operation by selecting the appropriate option If Red Channel is selected the CPLD supplies a sample clock only when the red channel data is available at S5 The Reset CPLD button is for use upon initialization of the evaluation platform or if a system reset is needed XRD9818EVAL Z EXAR EVALUATION SYSTEM USER MANUAL REV 1 0 0 3 2 Spartan Il FPGA XC2S50 At the heart of the evaluation platform is the Spartan Il The FPGA provides the timing control and pattern generation for the complete evaluation of the XRD9836 It reads the c
10. s intended to identify when data is valid 4 0 EVALUATION BOARD POWER JUMPER AND HEADER INFORMATION IDENTIFIER B1 3V TABLE 1 DESCRIPTION Eval Board Power 3 3V typically B2 GND Eval Board Ground B3 5V_VCC Positive Power Supply for Pixel Emulator B4 5V_VEE Negative Power Supply for Pixel Emulator J1 J7 External Timing Jumpers Used when external timing is applied and FPGA is not used to supply system timing J8 J9 amp J10 Emulator Input Jumpers Series jumpers to connect isolate XRD9818 analog inputs J11 Emulator Reset Pulse Jumper Used to create Reset pulse as part of emulated CCD pixel input J12 amp J13 XRD9818 Power Jumpers Used to Isolate the XRD9818 from Eval Board for IDD measurements S1 Analog Input Header Used to ground XRD9818 analog inputs S2 Reference Header Test points for CAPP CAPN amp CMREF S3 GPIO Header General purpose pins that can be used for debug of FPGA S4 JTAG Header JTAG header used to program PROM amp FPGA S5 Data Output Header Logic analyzer header for reconstructed 16bit digital outputs P1 Parallel Port Interface 5 0 REWORK INFORMATION Jumper near U3 PROM to supply power VDD3V to pins 18 19 amp 20 25 pin Din Connector standard parallel port interface for GUI control XRD9818EVAL REV 1 0 0 EVALUATION SYSTEM USER MANUAL 6 0 XRD9818E
11. tion The evaluation system contains emulation circuitry that provides a pseudo CCD signal including a reset pulse if desired XILINX CCD Emulator EXAR XRD9818ACG EL4331 amp AD8036 SPARTAN II XC2S50 ADCLK XR_LOAD XR SCLK XR SDI ADCO 7 0 EMCLK RPCLK DOUT 16 0 DCLK MCLK FIGURE 1 SIMPLIFIED BLOCK DIAGRAM OF XRD9818EVAL GUI Interface Ocillator Master Clock XRD9818EVAL Z EXAR EVALUATION SYSTEM USER MANUAL REV 1 0 0 3 0 XRD9818EVAL APPLICATION PLATFORM The XRD9818EVAL is an evaluation PCB layout designed to test functionality and performance of the XRD9818 The evaluation platform is controlled via a GUI interface on a PC and requires only power supplies inputs to the CCD emulator and test equipment Logic Analyzer Oscilloscope in order to evaluate most of the functional and performance aspects of the XRD9818 The following sections describe the functional blocks that make up the XRD9818EVAL system 3 1 Graphical User Interface GUI The GUI provides all serial port configurations for the XRD9818 plus options for controlling the XRD9818EVAL setup To use the XRD9818 GUI simply run XRD9818 exe file and initiate Start Test located in the TEST pull down menu File Test Help Start Test RW Registers FicURE 2 OPEN XRD98181 GUI The GUI is broken into 7 sectio
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