Cree MOSFET Evaluation Kit User`s Manual KIT8020
Contents
1. as JA m mm mm nm lt Q mmm Ww KI I8020 CRD 8FF121 P 1 CREE MOSFET Evaluation Kit User s Manual REVA CREE Power Applications 10 31 2014 This document is prepared as a user reference guide to install and operate CREE evaluation hardware Safety Note Cree designed evaluation hardware is meant to be an evaluation tool in a lab setting for Cree components and to be handled and operated by highly qualified technicians or engineers The hardware is not designed to meet any particular safety standards and the tool is not a production qualified assembly CREEO vs E di Wo Introduction This Evaluation EVL Board model number CRD 8FF1217P 1 2 is to demonstrate the high performance of CREE 1200V SiC MOSFET and SiC Schottky diodes SBD with standard TO 247 package It can be easily configured for several topologies from the basic phase leg configuration This EVL board can be used for the following purposes e Evaluate the SiC MOSFET performance during switching events and steady state operation Easily configure different topologies with SiC MOSFET and SiC diodes Functional testing with SiC MOSFET for example double pulse test to measure switching losses E and E PCB layout example for driving SiC MOSFET and SiC diode Gate drive reference design for a TO 247 SiC MOSFET This user manual will include information on the EVL board architecture hardware configuration Cree SiC power devices and an example application when usi2. 1096 Ceramic X7R 10 C0603 C1206 C1210 C1210 C1210C221JGGACTU Kemet CAP CER 220PF 2KV 5 NPO 1210 220pF C1210C221JGGACTU CAP CER 220PF 2KV 5 NPO 1210 HVDC 7808 female M5 30A 6P MECH CON2 GND 7808 female M5 30A 6P MECH MID PT 7808 female M5 30A 6P MECH Gate Drverios 25 2101 10pin 2 54mm male MECH GND 7808 female M5 30A 6P MECH n C4D20120D C4D20120D CREE 1200V 20A IN5819HW 1N5819HW 7 F DIODE SCHOTTKY 40V 1A SOD123 C4D20120D C4D20120D CREE 1200V 20A 1N5819HW 220pF 7 c c c c 1 c c N c NJ N N c cic c cic nicicicic c n mim TI mm mm mio qna Ov 7 CON4 N CY CY QOINIQ NA O 0100 III O O OINININ ms es at oy os t 2 Z Z P wjojuw N o u1 W NM O ul UJ T U N T T A un Q a SE O A rri A au uw 3 e a o O 2 e i Qiwoia juwvo AIA DNIAIATAILAITOATATOAIATAITONA a a NIADAINIAININIAINIAININ NJN N N Ojo cios eee se e ja NIIN NIN IN UJ UJ THR smo THR 1N5819HW 7 F DIODE SCHOTTKY 40V 1A SOD123 LN SMD SMD SMD SMD SMD SMD SMD SMD SMD SMD SMD SMD SMD HR HR HR HR SMD SMD SMD SMD HR SMD HR MD SMD SMD HR HR SMD e s EE 44 45 46 47 C4D02120E C4D02120E 1200V 2A podres wire x2 for Id connect MECH eg si exe Rm eg wo xe Lem wo ae m p eg wo a B x Lem wo ees 1
3. 47k gt i 5V VCC R20 mn R0603 R1206 s o Y SOD 123 ZD8 7 Vi VCC RTN H DISABLE gt SRI TP p 9015 A DI VigLst vig s2 D2 O C4D20120D 1N5819HW E TO 247 n Si8233 5 Ve SOIC ON LI 4 BV VCC al 013 V C0603 7 GND mill pill Note 918233 Input ouput Title Input HS CON4 7 HS PWM signal 5V max Main board Si lab Input LS CON4 8 LS PWM signal 5V max Bize Document Number DISABLE CON4 9 5V disable 0V enable A4 SiC MOSFET EVL Board CRD 8FF1217P 2 a Say Sente A0 Gate Driver input Circuit in this area the grounding is isolated T Nw o Component list of CRD 8FF1217P 2 Part PCB Value Part number Brand Description Type Ref a fe a fo sje we ea 0 1nF Ceramic COG 10 33pF Ceramic COG 1096 Ceramic X7R 1096 Ceramic X7R 1096 Ceramic X7R 1096 ceramic X7R 10 Footprint UJ SMD SMD SMD SMD SMD SMD SMD Ceramic X7R 10 SMD Ceramic X7R 1096 SMD Ceramic X7R 1096 SMD C1206 Ceramic X7R 1096 SMD Ceramic X7R 1096 SMD B32653A1103K EPCOS CAP FILM 10nF 1 6KVDC RADIAL PP THR B32653A1103K CAP FILM 10nF 1 6KVDC RADIAL PP THR B32654A1104K CAP FILM 0 1UF 1 6KVDC RADIAL PP THR B32774D1505K CAP FILM SUF 1 3KVDC RADIAL PP THR SMD SMD SMD SMD 10nF 10nF 8 9 0 T T T C18 5uF T Ceramic X7R
4. ag Run Sample E 10 0v aiv By 1 0G 179 acqs RL 5 0k QEED 10 0v aiv 1MO Ay 100mM Auto September 17 2014 17 18 46 Tox lt x Mask Math MyScope Analyze Utilities Help Edit Vertical Horiziaca Trig Display Cursors Measure A A oar scd rre nuce ED 200v div 1MQ Ey 500M sz RMS 165 2mV AQ Y 145v 100ns div 5 0GS s 200ps pt Triggered Auto Run Sample 1 100mV div 500 84 500M ea Max 230 0mv mE 10 0V div B 1 0G 168 acas RL 5 0k Figure 11 Vgs Id and Vds waveforms at 9KW loading Ch1 low side Vds yellow 200v div Ch2 low side Id blue 100mv 0 01310hm div Ch3 low side Vgs pink 10v div Ch4 high side Vgs green 10v div carre E N7 File Edit Vertical Horizaca Trig Display Cursors Measure Mask Math MyScope Analyze Uiiites Help 7 Tai x Gp 200v div 1MO By 500M Ey rus 39 45A A 142v 100ns div 5 0GS s 200ps pt Ea 10 0A div 500 By 500M Max 40 6A Triggered Auto Run Sample Qu 10 0v aiv By 1 0G 195 acqs RL 5 0k Qu 10 0V div 1MO By 100M Auto September 18 2014 10 53 17 File Edit Vertical Horiziac Trig Display Cursors Measure Mask Math MyScope Analyze Utiities Help 5 T k x LL sl AFA Ex ssi SR 1MQ 8 500M rus 297A Rip 142v 10 0usidiv 1 06S s 1 0ns pt EY 10 0A div 500 By 1 06 Max 41 0A Triggered Run Sample SD Mi 8y 1 06 3 616 acqs RL 100k ww 10 0V div 1MQ Ey 100M Auto
5. bridge converter and bi directional DC DC converter can be configured For H bridge with different control architecture the phase shift full bridge resonant LLC ZVS converter and single phase DC AC converter can all be achieved For bi directional DC DC converter it can achieve either Buck from port 1 to port 2 or Boost from port2 to port 1 Furthermore with three EVL boards it can even be set up as a three phase DC AC inverter for some motor drive or inverter applications Table 1 The EVL board topology configuration Option One Step down voltage or Syn Buck converter phase leg topology w o or Phase leg bridge anti parallel diodes topology without anti SiC Body diode used parallel diodes Connect inductor L with CON3 as output CON1 INPUT CON3 OUTPUT CON2 CON5 GND Option Two Phase leg bridge topology with anti parallel SiC SBD Option Three Non syn Buck converter Option Four Syn Boost converter Phase leg switching with external anti parallel diode SiC SBD used CON1 CON3 Input output depends on which topology apply to board CON2 CON5 GND Step down voltage Connect inductor L with CON3 as output CON1 INPUT CON3 OUTPUT CON
6. ee WT oe CON4 Driver 22 27 2101 Molex 10pin 2 54mm male inp TOA BO CONSGND 7808 on 808 no EE DE IDA o E capsam ere RP tig O 247 Ema Tl E as i A IEEE M1 for Id connect to GND 3701 c EET C2M0025120D CREE 25 mQ 1200 V SIC MOSFET THR T0 247 38 02 Peer C2M0025120D CREE 25 mQ 1200 V SiC MOSFET THR TO 247 do RI BRI Res lo Re SMD R1206 DRI y Res 1 SMD R1206 41 fis 10k testi MP 18208 130 L Bes 1 9MD R0603 SMD RO603 R8 Ines 19 RMD RD Ro k Res MD R1206 48 RIO 30 Resid SMD RO 49 R11 240 Resi J SMDROO03 5012 Mk Resid ISMD R1206 513 BR RResi w SMD ROO3 0020 CRD 8FF121 P 1 UN V a n u a e JJ i R1 R1 WV NINNIN o N 1IO O CO INIA U Un Un A JJ NO UJ M M M M M M k k o eed O OR S4 10RF1 dor 0 OHM 2W 196 WW O S4 10RF1 c id OOHM2WI SWW Vg LS 546 4027 RS Vig LS1 5020 keystone V lg LS2 5020 keystone 5464027 R Vg HS 546 4027 R 546 4027 R lg HS1 5020 Keystone round 1pin test point MECH lg HS2 5020 keystone round 1pin test point MECH ke
7. more effective and easy the BNC connectors are added on the board to measure both Vgs and Vds waveforms for the SiC MOSFET Q1 and Q2 A current test point with two unpopulated through hole contacts is available to measure the drain current through the low side switch A jumper JM1 can be inserted to the test point and measure current using current probe In addition coaxial shunts http www tandmresearch com are recommended for accurate current measurements with less delay time this can minimize the stray inductance on the switching loops and achieve accurate switching loss measurement Also some test points are added between gate resistors for measuring the voltage across the gate resistors Thus it can estimate the gate current lg to the SiC MOSFET 4 2 Connectors For the connectors CON1 CON2 CON3 and CON5 are power trace connectors and their definitions are depending on the different topology as described in Table 1 CON4 is for the signal logic inputs and supply voltage for ICs The definition of CON4 for each pin is shown in Table 2 Table 2 Pin definitions for connector CON4 CRD 8FF1217P 1 CRD 8FF1217P 2 Connector CON4 Pin 5 see et H2Vdc Oo Pim Input HS RTN gnal input for for Q2 5 Tapar Ti signal input oro a tape a a NM RIN GND for 5V O gt O 4 3 Board design A SiC device is a fast switching device and it is important to maximize SiC s high performance and minimize ringing with fast switching T
8. side Vgs waveform a x100 HV probe is used to measure low side Vds e waveform and a differential probe is used to measure high side Vgs waveform All probes must be placed as close as possible to reduce incorrect ringing due to probe placement e Place the power inductor as close as possible to connect at CON3 to reduce the switching node loop area and a 1uF 1200V film capacitors is connected between the output of inductor and ground connector CONS e A 12W AC fan is used to cool the heatsink and inductor when measuring waveforms and taking thermal measurements e ARCsnubber is added on the drain to source to damp high dv dt ringing on the switching node and slow the high dv dt e Acapacitance 1nF is added between gate to source terminal to shunt the miller current from drain to gate This external capacitor will introduce low impedance path for Cdv dt from miller capacitance effect and reduce the ringing on the gate pins e Use ofa ferrite bead FB on the gate pin of TO 247 MOSFETs will introduce high impedance on the gate path for MHz high frequency and reduce the Vgs ringing e Reduce the stray capacitance of inductor with single layer structure O D 120hm 1N5819HW 5ohm El FB N 5ohm G 220pF 1nF S D a 1N5819HW Tonm Sohm G 220pF 1nF S Q Figure 10 Gate drive and RC snubber configuration 6 3 Test data The switching waveforms are shown in the below figures In the operation of the synchronous Buck
9. 03 3 Input LS RTN gt H GND ACPLAWG46 a R1206 C1206 Id x R0603 SOD 123 COM L1 VCC VCC_RTN SV ZD3 S0D 123 CHOKE CM NEELS I I I a pcs Ver al i a gt this area a PCB Ver A Input HS ie ground wu BOM Ver is a n I Gate Driver input Input HSRIN isolated Title Main board Avago I Input LS Document Number Rev Input LS RTN M SiC MOSFET EVL Board CRD 8FF1217P 1 DateSunday September 21 2014 e Component list of CRD 8FF1217P 1 Value Part number Brand ah di PCB 1 BD Bead 74270011 Ce 1 o 0 Ceramic cog 10 sM 1E1206 6 uF Ceramic COG 10 SMD C0603 7 C6 NuF To Ceramic X7R 10 SMD C1206 8 07 22uF j CeramiC X7R 10 SMD C0603 9 C8 jOlu Ceramic X7R 10 SMD C0603 Tolo B3pE Ceramic COG 1095 T8MD C0603 11 C1O J0 1uE Ceramic X7R 10 SMD C0603 Malti aze Ceramic XTR 10 MD 1906 131C12 Mt eramic X7R 10 SMD C1206 SMD C0603 SMD C0603 BE Ceram COG 1008 h la ur 1 731 eramic X7R 1096 060 eeramie X78 1096 m SMD C0603 fr de uo ZR 10 SMD C0603 FILM a 1 6KVDC THR CAP FILM SUF 1 3KVDC Mfr ha SMD C0603 Bei jam 10 2060603 0 0 female Ma 204 6E ETE un ae
10. 2 CON5 GND Step up voltage Connect inductor L with CON3 as input CON1 OUTPUT CON3 INPUT CON2 CON5 GND 1 IT IT A Option Five Non syn Boost converter Option Six Diode bridge Option Seven H bridge topology configuration using two EVL boards Option Eight Bi directional DC DC converter Step up voltage Connect inductor L with CON3 as input CON1 OUTPUT CON3 INPUT CON2 CCON5 GND Bridge diode with SiC SBD CON1 OUTPUT Positive CON3 INPUT CON2 CON5 OUTPUT Negative Full bridge converter with Phase shift or resonant single phase DC AC inverter Port 1 is input and port 2 is output with Buck converter Q2 of EVL2 is constantly turn on and Q1 of EVL2 is constantly turn off Port 1 is output and port 2 is input with Boost converter Q2 of EVL1 is constantly turn on and Q1 of EVL2 is constantly turn off e JI s CU O CU D J escription The above figures give top view of the EVL board the top right is CRD 8FF1217P 1 and the top left is CRD 8FF1217P 2 The picture highlights key test points and connectors on the boards 4 1 Test points To make testing
11. 217P 2 version The EVL board size is 124mmx120mmx40mm not including heatsink Different types of heatsinks can be assembled depending on your cooling requirements Figure SA shows the board attached with a 120mmx120mmx45mm heatsink on the bottom of PCB board as an example SiC devices are horizontal with the PCB board however users can choose any type of heatsink that works with the standard TO 247 package Figure 5b gives another example for a vertical heatsink attachment with PCB board and SiC power devices Figure 5a Cree EVL board assembly 1 is shown on left See Appendix for assembly parts information Figure 5b Cree EVL board picture with a vertical heatsink for TO 247 package 3 Configurations The EVL board can be adaptable to implement difference topologies when using the different configurations of SiC MOSFETs and SiC diodes It is possible to test several topologies with this board synchronous Buck non synchronous Buck carre S Ns or high side Buck synchronous Boost non synchronous Boost half phase leg bridge converter H bridge converter 2x EVLboards and bi directionalbuck boostconverters Table 1 summarizesthe possibletopologiesthatcanbeimplemented using this EVL board For the phase leg configuration it can either use discrete anti parallel SiC SBD or body diode of SiC MOSFET thusthebodydiodeofSiCMOSFETcanbeevaluatedwithoutanti parallel diodewithoptiononeinthebelowtable With double EVL boards H
12. FETs are available from Cree with standard drain to source on state resistor 25mohm 40mohm 80mohm 160mohm and 280mohm 6 Example Application and Measurements 6 1 Board Setup In order to demonstrate the EVL with SiC devices a synchronous phase leg Buck converter configuration is used as an example to evaluate the performance of the SiC EVL board This is option one configuration on table 1 The table below gives the electrical parameters Please note the switching frequency is at 40KHZ in this case due to the design limitation of the available inductor but it does not mean the switching frequency is limited to 40KHZ Because of low switching losses of SiC MOSFET the switching frequency can increase to higher without sacrificing much switching losses when using SiC MOSFET The purpose of 40KHZ setting is competing with 1200V Si IGBT for inverter application with this phase leg configuration which frequency is normally ranged from 15KHZ to 20KHZ In the testing two 25mohm SiC MOSFETs are assembled on the PCB board with heatsink for both high side Q2 and low side Q1 The figure gives the test setup with EVL boards The signal generators are used to generate high side and low side PWM signals with Input_HS and Input_LS Note that the dead time period must be applied to the input signal between Input HS and Input LS for CRD 8FF1217P 1 For CRD 8FF1217P 2 the dead time function is integrated into the drive ICs at this example a 450ns dead time is s
13. IT IT A Ss smD p smD p smD SMD NENNEN smD SS smD p smo p smD Do SMD fem S p smo e smD Ss smo smD smD NENNEN SMD mM smD i smo smD smD 0 N k k 00 fra uo a iS a TN a Mo o EN Sw E Sw NM suo 1k 1M 1M 1M 1M R1206 R1206 R1206 R1206 R1206 R1206 R4524 R4524 R24 N a ES EN AE RSEN En ou lt lt TP10 N 5 1V UJ s po pu s pos jsw lsmwsomwm o Additional component list for the example testing in section 6 QTY Part number Description aaa ee heat sink 120mm x 123mm Heat sink for whole PCB board 320303B047 24 Aavid Need drill hole for mountino EE O MEN ous MEME A ana at 4 ome 4 d dM o uq DOd rQ ana at 4 orne S K NAAA SEAN PO QE Screw Phillips head M3x10mm for TO For SiC device assembly 4 247 mounting o oa Gas 4 AOS 218 247 1 elektronik hole TO 247 25 x 21x 1 VAR a DUDE dci for TO 247 mountino 60 66 68 69 80 NININININI INTO a l l lalalalalalalolololololo sl olol Go Ro h fS NO NIN y pay Ea CSI a e a ololJlalulsiwln a Slolo JI alw Ww N SOjuljolulal ual afwin S 8 8 8 8 8 8 8 8 slala 3 2 2 3 3 2 2 E lala NININIOGAlLOAINININMN DIDIO VIDI DIDIOIA ololo olololo lolol lo 2 Ww Ww WwW Ov o o wi t wt ot oo oo NINMINININININI NI wWwlw
14. September 18 2014 10 52 50 Gap 200v div 1MQ 8 500M d 100ns div 5 0GS s 200ps pt QE 10 0A div 500 Ay 500M Triggered Run Sample Lay 10 0V div By OG 229 acqs RL 5 0k Qu 10 0v div 1MO By 100M Auto September 18 2014 10 53 02 Figure 12 Vgs Inductor current IL and Vds waveforms at 9KW loading Ch1 low side Vds yellow 200v div Ch2 inductor current IL 10A div Ch3 low side Vgs pink 10v div Ch4 high side Vgs green 10v div Essa are LN m EF m m feum ao Ww The EVL board s maximum efficiency in this configuration is around 98 9 at 4KW half load using the Yokogawa WT3000 to measure it It includes losses from the inductor switching devices and capacitors Considering the high switching frequency 40kHz and high duty cycle 50 the efficiency is high compared to conventional Si IGBT solutions 288 711 13 9138 599 748 6 77469 A 98 8669 4 01707 Figure 13 Efficiency data for this EVL board Figure 14shows the thermal performance for this EVL board at full load 9KW after 30 minutes of continuous operation The test condition is at room temperature with open frame and 12W fan cooling the heatsink and inductor It demonstrates high performance of SiC MOSFET with low temperature low losses and high switching frequency Ea Figure 14 Thermal photo for this EVL board 7 Reference 1 C2M0025120D datasheet Cree Inc 2 C4D20120D datasheet Cree Inc 3 Performance Evaluation
15. converter the low side body diode conducts before low side MOSFET is turned on thus this low side MOSFET operates in Zero Voltage Switching ZVS mode and high side MOSFET operates in hard switching mode However high dv dt during fast transient of high side MOSFET will affect the operational behavior of the low side MOSFET and the charge stored in miller capacitance will be transferred via its gate loop inducing some spurious gate voltage in this topology The above methods mentioned in section 6 2 will help to damp this noise and reduce the ringing on the gate and drain to source Note that the incorrect test method itself may also introduce some noises from oscilloscope measurement but it is sometimes not a true representation of the actual transient events on the switching devices carre S i Wo Tex x File Edit Vertical Horiziaca Trig Display Cursors Measure Mask Math MyScope Analyze Utilities Help E Nt i a a D 200V div 4MQ 500M Gp RMS 222 7mV Ap V 14 8v 10 0us div 1 0GS s 1 0ns pt Triggered Auto Run Sample 1 GG 100mv div 502 By 1 06 ta Max 538 0mV UD 10 0V div By 1 06 273 acqs RL 100k UD 10 0v div 1MO By 100M Auto September 17 2014 17 18 34 File Edi Vertical Horiziaca Trig Display Cursors Measure Mask Math MyScope Analyze Utilities Help E 100ns div 5 0GS s 200ps pt GD 200v div 1MO 84 500M Gea RMS 370 5mV 2 QE 100mv div 500 Ey 500M Max 538 0mv
16. et and there is no need for additional dead time between Input HS and Input LS in CRD 8FF1217P 2 For CRD 8FF1217P 2 the disable pin 4 8 of CON4 should connect to ground of input 5V DC supply to enable gate signal to outputs This disable pin can control the on off of the board after the input is power up Table 3 Electrical parameters Parameters lt IT8020 CRD 8FF1217P 1_UM Rev A e 12V E VCC DC supply VCC_RTN J gt Cin or 5o Input HS l DC source Input HS RTN PWM signal nn pa LE RL generator PA Input LS gt Input LS RTN Gate drive o 22V DC supply 22V_VCC_IN o 22V VCC RTN 5V T VCC DC supply J gt VCC RTN C e Cin T 600V Do Input HS DC source Disable PWM signal RL generator SU Input_LS J gt VCC_RTN Gate drive 0 Lm NN Fiqure 8 Bench test setup of the EVL boards 6 2 Measurements To maximize the accuracy of the measurements when using the EVL board some suggestions are listed below e Usea highly accurate 0 01310hm shunt recommend SDN series shunt resistors from T amp M Research to measure the low side current waveform as shown below in Figure 9 This can help to shorten the current sense loop Figure 9 Low side current measurement e ABNC probe is connected to measure low
17. he EVL board introduces some design approaches to minimize the ringing on the board e The gate drive and logic signal are put on top of the PCB board while the main power trace and switching devices are put on the bottom layer There is no crossover or overlap between gate signal and switching power trace which can minimize high dv dt and di dt noise influence from the switching node to gate signal REZO Wo Four de coupling film capacitors with valued 10nF 10nF 0 1uF and 5uFare placed close to the SiC devices it can reduce high frequency switching loop and bypass noise within switching loop The layout of gate drive circuitry is designed with symmetric trace distance which can introduce balance impendence on the gate drive Also the gate drive is placed as close as possible to the SiC MOSFETs The power trace layout is optimized to reduce the switching loops 5 SIC Devices SiC devices including SiC MOSFET and SiC Schottky diodes are recognized as next generation wide bandgap devices It can provide fast switching with less loss compared to conventional Si devices Cree www cree com power is the world s leading manufacturer of silicon carbide Schottky diodes and MOSFETs for efficient power conversion The standard TO 247 package 1200V SiC MOSFETs and SiC SBDs are available to order or apply for free samples at Cree website in order to evaluate SiC power devices with this EVL board The different on state resistor Rds on MOS
18. lwlwlwl wlwlw s Comments Shunt resistor for current Id measuremen ELO N7 Heat sink hole drilling diagram for the example testing in Section 6 120 0mm lt q 114 0mm E e pe E o 6 0mm Total 8 holes all hole is JM3 And the depth is 4mm E E a eo um E a y Fo E E e 114 0mm LO E pe 0 0 orgin 120 0mm
19. ng this board e Please note that JM1 as shown in Figure 1 is open circuit It is necessary to short this with a wire or insert a shunt as shown in 2 Board Overview The EVL board s general block diagram is shown in Figure 1 There is a phase leg which can include two SiC MOSFETs Q1 and Q2 with half bridge phase leg configuration and two anti parallel SiC Schottky diodes D1 and D3 with Q1 and Q2 The gate drive block with electrical isolation is designed on the board to drive SiC MOSFET Q1 and Q2 There are four power trace connectors CON1 CON2 CON3 and CON5 and one 10 pin signal supply voltage connector CON4 on board SiC Phase leg block OCON1 VCC Input PWM Signal OCON3 Enable CON2 CON5 Figure 1 General block diagram of Cree Discrete SiC EVL board There are two versions of this EVL board The first version with model number CRD 8FF1217P 1 includes two 2 5A gate driver integrating opto coupler from Avago ACPL W346 and two 2W isolation DC DC converters from Mornsun G1212S 2W for both high side and low side individually The 2W DC DC converter with 12V Vcc input generates 24V Vcc_out output voltage with 6KVDC isolation that is supplying voltage to W346 on a push pull gate drive of the secondary side as shown in Figure 2 In this circuit a 5V zener in parallel with 1uF capacitor is used to generate 5V Vgs voltage for the SiC MOSFET where turn off and turn on Vgs voltage is equal to 24V 5V 19V Note
20. rough the bootstrap diode D5 from the VDD 22V Vcc power supply as shown by the red dashed line This is provided by VDDA when SW is pulled to a higher voltage by high side switch Q2 the VDDA supply floats and the bootstrap diode reverses bias and blocks the rail voltage and supply high side drive shown as blue dashed line The bootstrap diode D5 must withstand high blocking voltage with low reverse recovery current to minimize noise In this board a Cree 1200V SiC Schottky diode C4D02120E is used Also a 5V zener with 1uF is in series with a Vg trace on both the high side and low side which can generate 5V Vgs voltage for SiC MOSFET turn off The bootstrap circuit has the advantage of being simple and low cost but has some limitations Duty cycle and on time is limited by the need to refresh the charge in the bootstrap capacitor which limits the topology application for this second version of the EVL board when duty cycle is variable However it can work well on most topologies with fixed duty cycle such as phase shift full bridge or LLC resonant converter The Si8233 has an integrated dead time function with a resistor to ground used to set So the input signals do not need additional dead time on this version VCC Input PWM Signal zm Enable CON4 Vcc ju O CON3 Disable D LS I P Figure 3 CRD 8FF1217P 2 Block diagram with Si8233 e Figure 4 Simplified bootstrap drive circuit on CRD 8FF1
21. s of Hard Switching Interleaved DC DC Boost Converter with New Generation Silicon Carbide MOSFETs Available in Cree website http www cree com Power Document Library 4 Design Considerations for Designing with Cree SiC Modules Part 1 Understanding the Effects of Parasitic Inductance Available in Cree website http www cree com Power Document Library 5 Design Considerations for Designing with Cree SiC Modules Part 2 Understanding the Effects of Parasitic Inductance Available in Cree website http www cree com Power Document Library e 8 Appendix Schematic of CRD 8FF1217P 1 CON1 TP10 1 HV VCC ET HVDC Clr C18 C19 C20 R17 R18 R19 R20 1M 1M 1M 1M 10nF 10nF OtuF 5uF lt R1206 R1206 R1206 R1206 R16 5R1 R0603 22V_VCC_HS e R15 1 EE e A 5R1 R0603 GND R1206 R1206 C14 C15 0 1uF 2 2UF C0603 C0603 SOD 123 VCC_RTN gt Tp TP8 E d L Vig HS1 Vig HS2 G12129 2W 1N5819HW VEE mid HS SOD 123 L L TP5 e R11 1 6 Input HS gt Anode i Vcc a M a C4D20120D R0603 33pF NC Vout TO 247 3 R10 Edie Cathode Gnd Input HS RTN gt H 130 ACPL W346 R0603 CON3 I V ZD6 s0D 123 V g VEE mid HS R14 me Vt VS HS 5R1 R0603 i 22V VCC LS R9 R1206 El U3 zx io TP6 1 vee gt win a 5R1 R0603 C8 C7 TP1 0 1UF ST 22uF TS T SEP en Vg LS D1 VCC RINL gt EN 1N5819HW TO 247 I R5 Input LS gt l 240 R0603 o RA C06
22. that a SiC MOSFET can be turned off with zero voltage and the 5V turn off voltage helps with faster turn off and lower turn off losses It also improves dv dt inducted self turn on and noise immunity during transient periods with more headroom from Vgs turn on threshold voltage The first version can implement any PWM signal to drive the SiC phase leg block if the board is operating in synchronous mode with a high side MOSFET and a low side MOSFET the input signals must have additional dead time to avoid shoot through REZO VCC Input PWM Signal Enable pem O9 CON1 ACPL W346 X rf Hee Nd nm CON4 E 3E Figure 2 CRD 8FF1217P 1 Block diagram with ACPL W346 The second version with model number CRD 8FF1217P 2 includes a single isolated high side and low side driver from Silicon Labs Si8233 to drive both high side and low side MOSFETs together as shown in Figure 3 The Vcc with 5V input to Si8233 is a supply voltage for logic on the primary side and 22V Vcc with 22V input is supply voltage for a push pull driver on secondary side The driver IC has two independent sink sources with 5KVrms withstand voltage The 22V voltage is to directly supply VDD to low side drive for Vg LS while for high side supply voltage a bootstrap drive circuit is used to supply Vcc on the high side Figure 4 shows the bootstrap drive circuit When O1 is turned on and SW is pulled down to the ground the bootstrap capacitor C7 charges th
23. ystone round 1pin test point_____ MECH e J I NA IN Uu B J U EEE Un UY N2 383 U U U 00 4 O NO I ex JJ N N INININININININ O O OV Ov IOIO YU Un O71 O1 Un O1 Un Un 33 5 jaja pos jo e S 6 218 RS S sa V_VCC keystone round 1pin test point MECH ACPLW346 060E Avago SMD ACPL W346 060E Avago MD SS Mom W G1212S 2W Mornsun T TS ma wom nr 9 ZD1 24V 124V 350mW 1 80 ZD2 5 1V 5 1V 350mW 1 SMD 81 7D3 514 J 5 1V 350mW 196 82 ZD4 aV 24V 350mW 196 83 7D5 51V 5 1V 350mW 196 84 7D6 51V o 5 1V350mW 1 85 7D7 25V 25 350MW 2 86 25V 1 125V 350mW 296 KIT8020 CRD 8FF12 16 CREIO Wo Schematic of CRD 8FF1217P 2 22 VCC CON 22 VCC HVDC Cio _1C16 C17 1018 gt pos Rod R5 2 ROG 1M 1M 1M 10nF 10nF 0 1uF SuF 2 VCC RTN R1206 R1206 R1206 5 R1206 R1206 C1206 CON3 1 R22 a 1k MID PT 22V_VCC VEE_HS mid MEN R28 R27 1M 1M GND R1206 R1206 R10 Input HS gt VEE LS VEE HS mid 330 R18 mi ROD e RQ 5R1 R1206 47k Gate signal C0603 ine 22 NCC an SOD 123 DC SV Max L Vig Hst vigHs DA VCC RTN EJ mm X R5 R1206 VEE HS mid Q2 E R4524 Input LS gt C4D02120 w D5 C6 1uF Em Ww D3 Wc i n C1206 R si d CAD20120D R003 5R1 SRI 2 T0 247 Spr
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