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ATOM1 : MPC860 ATM Microcode User`s Manual

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1. f Input Parameters none A Output Parameters none EA I kk ko kCKCKCKCkCkCk kk kk kk KR KR kk ko kk kk ee koX AAAI I I I koe e void go forever hile 1 1 loop forever End of go_forever End File MPC860 ATOMI User s Manual 1 0 48 No Restriction on Circulation HOW TO REACH US USA EUROPE LOCATIONS NOT LISTED M otorola Literature Distribution P O Box 5405 Denver Colorado 80217 1 800 521 6274 or 480 768 2130 J APAN M otorola J apan Ltd SPS Technical Information Center 3 20 1 M inami Azabu M inato ku Tokyo 106 8573 J apan 81 3 3440 3569 ASIA PACIFIC Motorola Semiconductors H K Ltd Silicon Harbour Centre 2 Dai King Street Tai Po Industrial Estate Tai Po N T Hong Kong 852 26668334 HOME PAGE http motorola com semiconductors MOTOROLA Information in this document is provided solely to enable system and software implementers to use Motoro There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated integrated circuits based on the information in this document a products circuits or Motorola reserves the right to make
2. Last Modified 23 July 1996 Rev 0 Filename atoml c T C Copyright Motorola Inc 1996 x Written by Kevin Godfrey Motorola EKB i Revision History 0 Initial software
3. BOR I K Definitions FR ke ek ke X f typedef unsigned char ubyte typedef unsigned short uhalf typedef unsigned long uword Microtec PowerPC compiler treats char variables as bytes short integers as 16 bit quantities half words and integers as 32 bit quantities words MPC860 ATOMI User s Manual 1 0 36 No Restriction on Circulation RK KKK kK KKK 860ADS Board memory Map define PQUICC 0x2200000 PowerQUICC address 0x2200000 Lo define BDArea 0x2202c00 BD space starts at 0x2202c00 256 bytes define ARXBDO 0x2202c00 ATOM1 rx BDs start at 0x2202c00 define ATXBDO 0x2202c40 ATOM1 tx BDs start at 0x2202c40 24 define TXBUFF 0x340000 ATOM1 tx Buffers start at 0x340000 m define RXBUFF 0x350000 ATOM1 rx Buffers start at 0x350000 define ADS brd cntr 0x2100000 860ADS board control registers start at 0x2100000 f ceee ATOMI Demo Buffer Sizes Limits etc eeeeeeeex define BUFFSIZI 52 ATM buffer size 52 bytes define MAXBUFF 9 Maximum number of buffers 10 define SI RAM SIZE 128 128 words of SI RAM define MAXBDAREA 128 256 bytes of BD space define NO 0 define YES 1 LH T Define PowerQUICC Registers and Parameter RA
4. Associated Documentation x PowerQUICC ATOM1 User s Manual DATE 23 July 1996 REV 1 0 Target System Motorola 860ADS board running MPCbug T I aaa a AAA ee A AAA AA ee A AAA AA I I He He He This software initialises SCCl to transmit and receive ATM cells SCC1 runs ATOM1 microcode Ping Pong demonstration code is included to demonstrate receive and transmit buffer handling and CRC 32 calculations The ATOM1 microcode is loaded by other means before running this program To demonstrate ATOM1 receiver an external loopback is required between L1TXDA and LIRXDA or the 860ADS board can be connected to another PowerQUICC running ATOM1 microcode External clock and synchronisation signals are required
5. ATM cells 5 byte header 48 bytes payload Configuration ATOM1 SCCs Mode Frequency Ratio Ent 1 ATM SCC1 ATOM1 No Scrambling 1 3 1 ATM SCC1 ATOM1 Scrambling 1 4 5 2 ATM SCC1 2 ATOM1 No Scrambling 1 8 2 ATM SCC1 2 ATOM1 Scrambling 1 10 o dd 3 ATM SCC1 2 3 ATOM1 No Scrambling 1 10 3 ATM SCC1 2 3 ATOM1 Scrambling 1 14 4 ATM SCC1 2 3 4 ATOM1 No Scrambling 1 13 4 ATM SCC1 2 3 4 ATOM Scrambling 1 19 Table 8 ATOMI Performance MPC860 ATOMI User s Manual 1 0 28 No Restriction on Circulation ATOM1 SCC Other SCCs S Configuration Frequency Frequency Per SCC Mode SCC Mode Frequency Ratio Ratio ATOM1 1 12 SCC1 No Scrambling note 1 SCC2 3 4 HDLC 1 8 1 ATM ATOM1 1 12 T MHz 3 HDLC ATOM1 1 390 kamari SCC1 No Scrambling 1 3 5 SCC2 3 4 HDLC note 2 SCC i 15 SCC2 34 HDLC ee Scrambling note 2 ATOM1 1 ATM SCC1 No Scrambling 1 6 SCC2 Ethernet 1 2 5 1 Ethernet ATOMI 25 MHz channel SCC1 1 7 SCC2 Ethernet 1 2 5 Scrambling 1 ATM SCC ATOM1 1 12 SCC2 Ethernet 1 2 5 1 Ethernet No Scrambling note 1 SCC3 HDLC 14 nea Z 1 HDLC ATOM1 1 12 SCC2 Ethernet 1 2 5 hannel SCC1 cb Scrambling note 1 SCC3 HDLC 1 5 ATOM1 1 ATM SCC1 No Scrambling 1 2 5 SCC2 Ethernet 1 4 1 Ethernet A 40 MHz channel SCC1 1 3
6. ha MPC860 ATOMI User s Manual 1 0 37 No Restriction on Circulation struct PIP regs vol vol vol vol vol vol latil latil latil latil latil latil ha struct SI regs vol vol vol vol vol vol latil latil latil latil latil latil Le Le Le Le Le Le Le Le Le Le Le struct SCC_regs vol vol vol vol vol vol vol vol latil latil latil latil latil latil latil latil ha Le Le Le Le Le Le uword ubyte ubyte ubyte ubyte uword uword uword uword uword half half half half half half half byte byte gegcggcggEgagaeg reservedl PIPC reserved2 PTPR PBDIR PBPAR reserved3 PBODR PBDAT SIMODE SIGMR reservedl SISTR SICMR reserved2 SICR SIRP GSMRL GSMRH PSMR reservedl TODR DSR SCCE reserved2 SCC reserved3 SCCS ATOM1 SCC Parameter RAM struct ATOMI vol vol vol VOL VOL VOL VOL vol VOL VOL vol VOL VOL vol VOL VOL VOL VOL vol VOL VOL atil atil latil atil atil atil atil latil atil atil latil atil atil latil atil atil atil atil latil atil atil Le Le Le Le Le Le Le Le Le Le Le Le Le Le Le Le Le Le Le Le _Params uhalf half byte byte half word word half half uword uword uword uhalf uhalf uword uhalf uhalf uhalf uhalf uword uword
7. amp Logic 4 Byt SDMA Bus Write Cycle 48 Bytes Payload SDACK1 Output Signal SDACK2 Output Signal MATCH Input Signal Figure 13 ATOM1 CAM Interface The user selects the pin to be used as the MATCH input from the port B PB31 PB16 pins using the CAM_PORT parameter Multiple CAMs can be connected to a single SCC running ATOM1 by using multiple MATCH inputs ATOMI looks for one or more of the MATCH inputs to be active The port B pins being used as the MATCH input must be configured as input ports using the port B configuration registers PBPAR and PBDIR MPC860 ATOMI User s Manual 1 0 26 No Restriction on Circulation When ATOMI is operating on several SCCs concurrently each may be connected to a CAM To distinguish between the SDMA cycles for each SCC each receiver function codes should be programmed to a different value When the CAM interface is operating with ATOM1 the Ethernet CAM interface can still be used The CAM control logic will need to check the function codes and SDACK signals to determine which SCC has initiated a particular bus cycle and enable the appropriate CAM chip 8 LOADING amp CONFIGURING ATOMI Before operation the ATOM1 microcode must be loaded into the MPC860 s internal RAM The microcode is delivered in a file of S records ready to download to a Motorola 860ADS board and a general PowerPC assembly code file Further details of 860ADS download procedures are g
8. ARXBuff bytecnt 0 Initialisation is complete so enable SCC1 for ATM Reception SCC1 gt GSMRL 0x00000030 SCC1 Enabled Wait until synchronisation has been achieved before proceeding Remember that an external loopback between the L1TXDA and L1RXDA pins must be provided otherwise we stay in this loop forever f while SCC1 gt SCCE amp 0x0040 0x0000 T Now Enter the ATOM1 Ping Pong Demonstration EKKE I KKK kK kkk ATOM1 PING PONG SOFTWARE Fe ke ke ke ke ke A FI A AR AA KKK I Ek ko HR KR HRK KR ee ko ko A AAA AA I He eee ex x This routine uses SCCl to transmit and receive ATM cells in a game of ping pong It is assumed that SCC1 is either connected with an external loopback or to another QUADs board also running this ping pong software i Ef SCC1 must be initialised before running this loop see code above EJ The ping pong game is played with two cells transmitted and received at a time Each cell is checked to see that the received CRC 32 is correct 7 ay MPC860 ATOMI User s Manual 1 0 41 No Restriction on Circulation The PA15 pin is driven high by software for the duration of the single cell CRC 32 calculations to allow an external counter or the CRC 32 calculation duration oscilloscape to measur I A RRA AK E ko ko ko kk KICK Kok ke kk KR ee ke kk AAA AA
9. ATOM gt HEAD1 0 Cell Header Look Up Table Entry 1 ATOM gt HEAD2 0 Cell Header Look Up Table Entry 2 ATOM gt HEAD3 0 Cell Header Look Up Table Entry 3 ATOM gt HEAD4 0 Cell Header Look Up Table Entry 4 ATOM gt HEAD5 0 Cell Header Look Up Table Entry 5 ATOM gt HEAD 6 0 Cell Header Look Up Table Entry 6 ATOM gt HEAD7 0 Cell Header Look Up Table Entry 7 ATOM gt HEAD8 0 Cell Header Look Up Table Entry 8 ATOM gt HEAD9 0 Cell Header Look Up Table Entry 9 ATOM gt HEAD10 0 Cell Header Look Up Table Entry 10 ATOM gt HEAD11 0 Cell Header Look Up Table Entry 11 ATOM gt HEAD12 0 Cell Header Look Up Table Entry 12 ATOM gt HEAD13 0 Cell Header Look Up Table Entry 13 ATOM gt HEAD14 0 Cell Header Look Up Table Entry 14 ATOM gt HEAD15 0 Cell Header Look Up Table Entry 15 ATOM gt HEAD16 0x12345679 Cell Header Look Up Table Entry 16 HEADMASK and HEAD16 are set up for use in the ping pong demonstration End of atom init I kk kk KCKCKCkCkCkCkCkCkCk A A ARR kk ee kk X AAA I I koe e jus ATOM1 TRANSMIT amp RECEIVE BD INITIALISATION ROUTINE ee I A RR AA KK ee ke kk A RA AA ee A A AAA I I He He e e x Function name BD_init I ko ko kCKCKCkCkCkC kk kk Ck ee ko ko kk AA kk ke kk ko kk ee A A AA AA I I koe e This routine initialises an ATOM1 tra
10. 1 25 equates to 1 MHz at 25 MHz Table 10 CRC 32 Calculator Performance 10 ATOMI DISK STRUCTURE ATOMI is shipped on a PC format disk Figure 14 shows the disk structure The microcode is held in the UCODE directory and demonstration software is stored in the DEMO directory ATOM1 SRX is the S record microcode file for the QUADS board memory map ATOMI SRC is an assembly code file for the ATOMI microcode that can be assembled and linked to any system memory map The file ATOMI C contains the C source code for the initialisation and ping pong demonstration software given in Appendix B ATOM1 and ATOM1 CMD are the makefiles for the C demonstration software and ATOMI X is the ELF file of the demonstration software ready to download to a 860ADS board MPC860 ATOMI User s Manual 1 0 30 No Restriction on Circulation 860ATOM1 860UCODE 860DEMO README ATOM1 SRX ATOM1 ATOM1 SRC ATOM1 CMD ATOM1 C ATOM1 X Figure 14 ATOMI Disk Structure 11 MPC860 MASK SET APPLICABILITY ATOM 1 microcode operates on all revisions of the MPC860 The ATOM microcode can be used in conjunction with the QMC protocol for multi channel operation on an MPC860MH with a reduction in the total number of QMC channels available due to the RAM microcode 12 ORDERING INFORMATION The ATOM1 package contains relocatable ATOM1 obj
11. 3 3 1 Serial Interface Registers The SI registers SIMODE SIGMR and SICR should be programmed for the required interface standard and the user must configure the SI RAM pointer SIRP as required in the system An example of programming the SI registers for connection to a line interface device with common transmit and receive clocks is shown in Table 2 In this example ATOM1 is running on SCC1 Note the timeslot assigner TSA must not be enabled in SIGMR until the SI RAM and other registers have been configured Register User Writes hex SIMODE Serial Interface Mode Register 0000 0058 SIGMR Serial Interface Global Mode Register 04 SICR Serial Interface Clock Route Register 0000 0040 Table 2 MPC860 Serial Interface Programming Example 3 3 2 Serial Interface RAM ATOMI can use the MPC860 TSA with independent receiver and transmitter routing RAM tables An example of programming these two tables for back to back ATM cell transmission and reception is given in Table 3 TDM A is used and data is routed to SCC1 Other SCCs and TDM B may be used For debug purposes all four SI strobes are asserted during various timeslots L1ST1 during cell header transmission L1ST2 on HEC transmission L1ST3 during cell header reception and L1ST4 on HEC reception SI RAM Entry User Writes hex Strobe Asserted Remarks RxAO 104E L1ST3 Receive four bytes of cell header Rx A 1 2042 L1ST4 Receive one byte
12. ATOMI SCC Parameter RAM Memory Map ss 14 Table 7 ATOMI CRC 32 Calculator Parameter RAM Memory Map 20 Table 8 ATOMY Performance aoo ei a tire eMe pad Td 28 Table 9 ATOM and other Protocol Performance ss 29 Table 10 CRC 32 Calculator Performance oid ss rtr Feds oa ei inter 30 LIST OF FIGURES Figure 1 Typical ATOM Application System uite ett e een 6 Figure 2 ATOMLRE EER Sm a a e ar 9 Figure 3 ATOMEPSMR Se a ne a an aaa a AN AA aa 10 Figure 4 ATOMISCCE eea te a au Ease e A ARC OC 11 Figure 5 AS TATUS risit ae WATOA IA WA a a att ERE WANA 17 Figure 6 HEAIDMLASK 15 5 2 t ee ie ertt t ebbe ede er tar teils 18 Figure 7 FEADAN Seinen tuneren TS A Ritter dei dot e it ane 18 Figure 8 ATOM1 Transmit Buffer and BD Queue Example 22 Figure 9 ATOM1 Receive Buffer Descriptor ss 23 Figure 10 ATOMT Transmit Butler Descriptor sien sete besides ps tesi kee 23 Figure 11 Transmit BUffer oe ea C En Totus sta ne wins tia etta she te E DAT 24 Figure 12 Mixed Voice and Data Transmission Example sss 25 Figure 13 ATOM1 CAM Interface ee 26 Figure l4 ATOMTDIskStructutens sn piii quen ais ep Mp Aaa 31 Figure 15 ATOMI Transmitter Procedure ee 32 Figure 16 ATM Cell Payload Scrambling Mechanism ees 33 Figure 17 ATOM Receiver Procedure er ee tenait ent oath ennt eon naa repro Rua ad 34 Figure 18 Cell Delineation State Diagram ee 35 MPC860 ATOMI User s Manual 1 0 4 No Res
13. Cell Header Look Up Table Entry 7 Cell Header Look Up Table Entry 8 Cell Header Look Up Table Entry 9 Cell Header Look Up Table Entry 10 Cell Header Look Up Table Entry 11 Cell Header Look Up Table Entry 12 Cell Header Look Up Table Entry 13 Cell Header Look Up Table Entry 14 Cell Header Look Up Table Entry 15 Cell Header Look Up Table Entry 16 CRC 32 calculator pointer CRC 32 calculator counter register CRC 32 calculator Function Code CRC 32 calculator preset and result register No Restriction on Circulation struct SCC regs uhalf SIRAM uhalf BDSpace uhalf ATXBD uhalf ARXBD ubyte ATXBuff ubyte ARXBuff uword SDCR void main Local Variables int bytecnt int count int txcount int pperror SCC1 struct ATOM1 Params ATOMI 1 struct CRC32 calculator CRC32 Jr px y Ai JF 4 Pointer to Pointer to Pointer to Pointer to Pointer to Pointer to 256 bytes of SI routing RAM start of 256 byte BD space ATOM1 ATOM1 x BD Queue Rx BD Queue ATOM1 ATOM1 x data queue Rx data queue SDMA configuration register General byte counting variable 32 bit General counting variable 32 bit 0 rxcount 0 Ping Pong receive and transmit cell counters 0 Ping pong error flag Initialise Memory Pointers CP stru
14. HEC Transmit HEC Byte Transmit Data Cell Calculate Data Cell HEC Transmit Transmit Data Cell Payload Transmit Empty Cell Payload Yes Skip Next BD No Data Cell Ready Figure 15 ATOM1 Transmitter Procedure MPC860 ATOMI User s Manual 1 0 32 No Restriction on Circulation A1 2 ATM Cell Payload Scrambling ATOM1 provides a scrambling option on a per line basis for cell payload bytes using the polynomial X 1 Figure 16 illustrates the payload transmitter and receiver scrambling mechanism used by ATOMI Transmit Data Receive Data 43 Bit Delay 43 Bit Delay Transmitter Receiver Figure 16 ATM Cell Payload Scrambling Mechanism The context of the transmit and receive scrambling mechanism is independent of the cell s virtual connection The seed value for the scrambling algorithm for a particular cell is obtained from the 43 cell payload bits transmitted or received immediately prior to the current cell Two consecutive cells may be from different connections and scrambling mechanism ignores this A1 3 ATOM1 Receiver Figure 17 shows the ATOMI receiver procedure After start up when MRBLR is zero the HEC delineation procedure begins see below Once complete cell reception commences For each cell received the HEC is checked and if incorrect the cell is usually received It is not received only when the receiver losses cell delineation In the
15. HEC field Rx A 2 007E Receive first sixteen bytes of cell payload Rx A3 007E Receive second sixteen bytes of cell payload Rx 4 007F Receive final sixteen bytes of cell payload TxAO 044E L1ST1 Transmit four bytes of cell header Tx A 1 0842 L1ST2 Transmit one byte HEC field Table 3 Serial Interface RAM Programming Example MPC860 ATOMI User s Manual 1 0 12 No Restriction on Circulation SI RAM Entry User Writes hex Strobe Asserted Remarks Tx A2 007E Transmit first sixteen bytes of cell payload TxA3 007E Transmit second sixteen bytes of cell payload Tx A 4 007F Transmit final sixteen bytes of cell payload Table 3 Serial Interface RAM Programming Example 3 4 Parallel Port Registers For ATOMI operation over TDM A the MPC860 parallel port pins should be set up to interface to external signals as shown in Table 4 The TSA strobes and SDMA Acknowledge pins are shown and common receive and transmit clocks are used Signal Pin Direction LITXDA PA Output L1RXDA PA8 Input L1RSYNCA PC4 Input L1RCLKA PA7 Input L1ST1 PB19 Output L1ST2 PB18 Output L1ST3 PB17 Output L1ST4 PB16 Output SDACK1 PC5 Output SDACK2 PC7 Output Table 4 ATOM1 TDM A Port Pin Requirements To achieve this Table 5 shows an example of how the port registers may be programmed Register User Writes hex
16. Mj MOTOROLA ATOMI MPC860 ATM Microcode Document Reference User s Manual Version Comments Release date 1 0 First Release 23rd July 1996 Motorola reserves the right to make changes without further notice to any product herein to improve reliability function or design Motorola does not assume any liability arising out of the application or use of any product circuit or software described herein neither does it convey any license under its patent rights nor the rights of others Motorola products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support life or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur Should Buyer purchase or use Motorola products for any such intended or unauthorized application Buyer shall indemnify and hold Motorola and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part Motorola and the Motorola logo are registered trademarks of M
17. cell is an empty cell the payload is discarded If there is a header match using internal the header lookup table then the cell payload is received When the external CAM option is enabled the cell is received before the CAM match is checked Operation continues in this manner until the Restart Reception command or a FIFO overrun error occurs or the user disables the SCC receiver Received cells may have their payloads descrambled as described earlier A1 4 HEC Delineation Mechanism ATOMI applies the cell delineation mechanism specified in 1 432 and shown in Figure 18 to synchronise to the incoming cell stream The SDH based physical layer values for alpha and delta 7 and 6 respectively are used by ATOMI At start up the hunt mode is entered where the CRC 8 value is calculated on each incoming word When this matches the next received byte it is assumed that the HEC is found and the state machine advances to the presync state Because the hunt state only finds a HEC field that is aligned to the start of reception it can take up to four correct cells to leave the hunt state MPC860 ATOMI User s Manual 1 0 33 No Restriction on Circulation ATOM1 Rx Start MRBLR 0 Y es Goto Transparent Mode ROM Microcode Apply HEC Cell Delineated 7 gt NO Delineation lt Receive Cell Loss of Delineation Discard Cell Payload mu Header Match NN Receive and Store Cell Payload Close Buffer
18. commands are given through the Command Register and operate as with other protocols except Restart Reception The ATOM1 commands to initialise the receiver and transmitter parameters operate the same as for other SCC protocols If the initialisation commands are given during cell transmission and reception cell synchronisation will be lost The Stop Transmit Command stops cell transmission immediately and the transmit line goes high To stop transmission of data cells but continue with empty cells the user must wait for the transmit BD queue to empty The commands are run by writing the command and channel number to the PowerQUICC s Command Register CR The op codes for the initialisation Stop Transmit and Restart Transmit command are the same as for the PowerQUICC s other protocols The op code for the Restart Reception command is and the CRC 32 calculator 1111 All other bits in the CR remain unchanged Command execution latency for the initialisation Stop Transmit and Restart Transmit command are the same as for the PowerQUICC s other protocols The Restart Reception command is executed when the current cell being received is complete and execution time therefore depends on the data rate and when the command is given For all commands ATOM1 clears the FLG bit in the CR to indicate completion of the command 5 1 Restart Reception Command The Restart Reception Command is similar to Enter Hunt Mode If ATOM1 is currently receivin
19. eegecceoeog5ge AVERSION CAM PORT RX BUFF1 TX BUFF1 MPC860 ATOMI User s Manual 1 0 S S S S S S S S PIP Configuration Register PIP Timing Parameter Register Port B Data Direction Register Port B Pin Assignment Register Port B Open Drain Register Port B Data Register SI mode register SI global mode register SI status register SI command register SI clock route SI RAM pointer CC General Mode Register lower long word CC General Mode Register upper long word CC protocol specific mode register CC tx on demand register CC data sync register CC event register CC mask register CC status register ATOM1 rx BD Base Address ATOM1 tx BD Base Address ATOM1 SDMA rx Function Code ATOM1 SDMA tx Function Code Transparent receiver max buffer length ATOM1 rx internal state storage ATOM1 rx data pointer ATOM1 rx BD Pointer ATOM1 rx counter Receiver Temporary Storage ATOM1 tx internal state storage ATOM1 tx data pointer ATOM1 tx BD pointer ATOM1 tx counter Transmitter Temporary Storage Receiver Synchronisation Alp
20. go forever sub routine so that the debugger returns to the command line uA go forever End of Main MPC860 ATOMI User s Manual 1 0 43 No Restriction on Circulation I kk kCKCKCKCICkCk kk kk KK KO ko ko ko kk KICK kk kc ke kk ee ke kk X AAA I koe e e yA POWEROUICC PARALLEL PORT CONFIGURATION ay I A RR AAA ee A A AA AA ee A A AAA I koe e ee Function name config_parallel_ports J CREEK ko kk RRA AA ee ko kk A AA AA ee A X AAA I I I He He ee Configure PowerQUICC Parallel Ports as follows EJ L1TXDA PA9 Transmit data output LIRXDA PAB8 Receive data input LIRSYNCA PC4 Synchronisation input A LIRCLKA PAT Clock input LISTI PB19 TSA strobe output L1ST2 PB18 TSA strobe output L1ST3 PB17 TSA strobe output Ai L1ST4 PB16 TSA strobe output yA SDACK1 PC5 SDMA cycle output yA SDACK2 PC7 SDMA cycle output PA15 PA15 CRC 32 PIO output pin for software use ki PB31 PB31 CAM MATCH PIO input pin xf J CREEK A RR AAA ee A AAA AA ee A AAA AA koe e ee Input Parameters global data structures PIP PortA and PortC JE Output Parameters PIP PortA and PortC modified X I kk kCKCKCKCkCkCkCkCkCkCk A KICK kk kc kk kk ee ko kk AA AA I I I I koe e e void config parallel ports PIP gt PIPC 0x0000 PIP configuration register PortA gt PADAT 0 is Port A data register PortA
21. gt SIGMR 0x04 Enable TDMA End of config_tsa I ko kk RRA AA ee A A AA AA ee A A AA AA I I I I He He ee fx POWERQUICC RAM MICROCODE CONFIGURATION amp INITIALISATION I kk kCKCKCKCkCkCkCkCkCkCk ee ko kk KICK Kok kk kk kk ee ke kk AAA AA koe ee Function name config ucode Kikii CK ee ko kk KICK kk k ko kk kk ee ko koX AA AA I I I koe ee Configure CP control registers and enable RAM microcode BI kk kCKCKCKCKCkCk kk kk ee ke HRK kk kk kk ee ko koX AAA I I koe e ke Input Parameters global data structure CP x L Output Parameters CP modified MPC860 ATOMI User s Manual 1 0 45 No Restriction on Circulation JR 7 BI A A RA AK I iii OK ee kk X AA AA I I OK koe ee ex void config ucode CP gt RCTR1 0x8056 RISC Controller Trap Register 1 CP gt RCTR2 0x8076 RISC Controller Trap Register 2 CP gt RCTR3 0x8036 RISC Controller Trap Register 3 CP gt RCTR4 0x8818 RISC Controller Trap Register 4 CP gt RCCR 0x0002 1K RAM microcode now running End of config_ucode Kikii ee A A AA AA ee A A A AAA I I I He He ee js ATOM SCC CONFIGURATION amp INITIALISATION x I kk kk KCKCKCkCkCkCkCk kk ee ke ko KICK Kok ke ke kk kk ee ke kk X AAA koi koe ee Function name atom init pA BI kk iii iii iii ee ko ko KK AA kk ke ke kk kk ee ko koX A AAA I I I koe e This routine initialises an SCC to t
22. or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part MOTOROLA and the Stylized M Logo are registered in the US Patent and Trademark Office All other prodi uct or service names are the property of their respective owners Motorola Inc is an Equal Opportunity Affirmative Action Employer Motorola Inc 1996 M PC860ATOM 1UM D Rev 1 7 1996
23. timers are unavailable when ATOMI is running and the TIME and TIMEP bits must be cleared in the RCCR 3 1 2 CP Control Registers The user must configure RISC Controller Trap registers as shown in Table 1 Address Name Description User Writes hex REGB 5CC RCTR1 RISC Controller Trap Register 1 8056 REGB 5CE RCTR2 RISC Controller Trap Register 2 8076 REGB 5D0 RCTR3 RISC Controller Trap Register 3 8036 REGB 5D2 RCTR4 RISC Controller Trap Register 4 8818 Table 1 RISC Control Registers 3 2 SCC Registers ATOM1 operates using an SCC and is enabled in the SCC s General SCC Mode Register GSMR The clock source is configured in the serial interface registers see section 3 3 1 MPC860 ATOMI User s Manual 1 0 9 No Restriction on Circulation 3 2 1 General SCC Mode Register GSMR ATOM1 requires the following bits to be set in the GSMR TRX TTX CDP CTSP CDS and CTSS To enable ATOM1 s transmit and receive functions the ENT and ENR bits must be set when the initialisation sequence has been completed Full GSMR details are given in the MPC860 User s Manual Additionally the REVD bit in the GSMR bit 18 changes function to become the CAM control bit when ATOM1 is running CAM 0 Use the internal address table for address matching 1 Use the external CAM for address matching To enable an SCC to run ATOMI the SCC must be in transparent mode and have MRBLR 0 When MRBLR is programmed with a
24. 1 432 with Alpha 7 and Delta 6 to locate and maintain cell synchronisation During reception ATOM1 updates the ALPHA and DELTA parameter locations and the user must not write to these locations There is no need to initialise these locations 4 0 9 Version Number AVERSION During operation ATOMI writes a version number to AVERSION The current version number of ATOM1 on the PowerQUICC stored in AVERSION is 0081 4 0 10 CAM Port Selection CAM_PORT When the CAM interface is enabled the user should set one or more bits in CAM PORT to select which of the PowerQUICC s Port B pins is the match input or inputs for this SCC CAM PORT is a 16 bit parameter where bit 15 of CAM PORT corresponds to PB31 bit 15 to PB30 etc as shown below 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PB16 PB17 PB18 PB19 PB20 PB21 PB22 PB23 PB24 PB25 PB26 PB27 PB28 PB29 PB30 PB31 MPC860 ATOMI User s Manual 1 0 16 No Restriction on Circulation 4 0 11 Empty Cell Data EHEAD and EPAYLOAD ATOM1 transmits and receives empty cells using EHEAD and EPAYLOAD On transmission an empty cell is made up by transmitting EHEAD once calculating and transmitting a HEC and transmitting EPAYLOAD twelve times On reception the incoming header is compared with EHEAD to check for empty cells and EPAYLOAD is not used The user is free to select whatever empty cell header and payload values are re
25. 2 bit SRAM 32 bit DRAM Interface Figure 1 Typical ATOM1 Application System 1 2 MPC860SCCs ATOM1 can operate on any MPC860 SCC and can simultaneously operate on any two three or all four SCCs To maintain the performance of ATOM it is recommended that the highest speed connection operates on SCC1 and the lowest speed connection on SCC4 ATOM1 uses the SCC in transparent mode with microcode performing ATM cell functions When ATOMI is loaded and RAM microcode is enabled transparent mode operation is available on any SCC other than ones running ATOMI 1 3 Conventions The reader is assumed to be familiar with the PowerQUICC and ATM For further information about the PowerQUICC please refer to the MPC860 User s Manual Full details of the ATM protocols can be found in the relevant ITU T recommendations and the ATM Forum UNI document listed at the end of this manual MPC860 ATOMI User s Manual 1 0 6 No Restriction on Circulation In this manual the term user is used to describe the CPU software that drives ATOM In the MPC860 this is the on chip PowerPC core 2 ATOMI OPERATION ATOM1 transmits and receives 53 byte ATM cells as defined in the ATM Forum UNI specification ATOMI also handles NNI cells Cells are transmitted from a single queue and the user has full control over each cell s GFC VPI VCI PT CLP and payload fields ATOM1 generates and inserts the cell HEC field on transmission and checks and strips it on rece
26. Base 98 HEAD13 Word Cell Header Look Up Table Entry 13 UD SCC Base 9C HEAD14 Word Cell Header Look Up Table Entry 14 UD SCC Base AO HEAD15 Word Cell Header Look Up Table Entry 15 UD SCC Base A4 HEAD16 Word Cell Header Look Up Table Entry 16 UD UD User Defined Table 6 ATOMI SCC Parameter RAM Memory Map 4 0 1 BD Queue Pointers RBASE and TBASE The user configures RBASE and TBASE to define the starting location of the receive and transmit BD queues in the dual port RAM Further information is given in the MPC860 User s Manual 4 0 2 SCC Function Code Registers RFCR and TFCR The user configures RFCR and TFCR to define the SDMA function code pin settings during SDMA transfers Further information is given in the MPC860 User s Manual 4 0 3 Transparent Mode Receive Maximum Buffer Length MRBLR To run ATOMI on an SCC the user must program that SCC s MRBLR to zero When MRBLR is programmed with a non zero value the SCC operates in transparent mode as described in the MPC860 User s Manual 4 0 4 SCC Internal State Parameters RSTATE and TSTATE ATOM1 uses RSTATE and TSTATE to store internal state variables and flags during operation The user must not write to these locations MPC860 ATOMI User s Manual 1 0 15 No Restriction on Circulation 4 0 5 BD and Buffer Pointers R PTR RBD PTR T PTR and TBD PTR During cell transmission and reception ATOMI uses R PTR RBD PTR T PTR and TBD PTR as pointers to the curr
27. M Buffer Descriptor and Buffer Queues RN 21 6 2 Receive Buffer Descriptor and Data Buffer pp 22 6 3 Transmit Buffer Descriptor and Data Buffer pp 23 6 3 1 Transmit Bandwidth Reservation 54 4 9 0e Reese i pese eres Oda etd dnd d 24 YA ATOM LEAM INTEREACE noia raent i a 26 8 LOADING amp CONFIGURING ATOMI Nt 27 9 PERFORMANCE iia ia ZA 9 1 Command Execution Waona ai 29 9 2 CRC 32 Calculation Ex cution cin e Iti Ie nee s ii HRS e anus SAN SI Ee lies 30 ID ATOME DISK STRUCTURE S addis ob Va a d a e ne 30 11 MPC860 MASK SET APPLICABILITY toc Mes e RO ERAI aM Nate nia 31 I2 ORDERING INFORMATION ann imite qe uve Rit bodea dead Uso Qi ave in 31 I3 REEERENGES tension tiet ae oa eas 31 Appendix 1 STATE MACHINE DE TAIES ssa esse aee dd 32 ATOMI TESESEOHIOE oe o hour oh nd EE R s 32 ATM Cell Payload Scrambling pp 33 ATONEL RECEIVE net ete ee Gus R RS 33 HEC Delineation Mechanism sc asco oor orae P abest o pot iet iduadu pde 33 Appendix 2 ATOMI DEMONSTRATION SOFTWARE pp 36 MPC860 ATOMI User s Manual 1 0 3 No Restriction on Circulation LIST OF TABLES Table 1 RISC Control Resist fs scie tad pdt tardes deest e puta anaes 9 Table 2 MPC860 Serial Interface Programming Example 12 Table 3 Serial Interface RAM Programming Example 2 12 Table 4 ATOM1 TDM A Port Pin Requirements iss d e teat enter a er ricetta dtr 13 Table 5 MPC860 Port Register Programming ss 13 Table 6
28. M Data Structures struct CP regs volatile uhalf CR Command Register uhalf reservedl volatile uhalf RCCR RISC Configuration Register uhalf reserved2 uword reserved3 volatile uhalf RCTR1 RISC Controller Trap Register 1 volatile uhalf RCTR2 RISC Controller Trap Register 2 volatile uhalf RCTR3 gt RISC Controller Trap Register 3 volatile uhalf RCTR4 RISC Controller Trap Register 4 uhalf reserved4 volatile uhalf RTER H RISC Timers Event Register used by CRC 32 calculator uhalf reserveds volatile uhalf RTMR j RISC Timers Mask Register struct Int regs volatile uword CICR CP Interrupt Control Register volatile uword CIPR CP Interrupt Pending Register volatile uword CIMR CP Interrupt Mask Register volatile uword CISR j CP Interrupt In Service Register struct PortA regs volatile uhalf PADIR H Port A Data Direction Register volatile uhalf PAPAR E Port A Pin Assignment Register volatile uhalf PAODR Port A Open Drain Register volatile uhalf PADAT A Port A Data Register struct PortC regs volatile uhalf PCDIR Port C Data Direction Register volatile uhalf PCPAR gt Port C Pin Assignment Register volatile uhalf PCSO Port C Special Option Register volatile uhalf PCDAT Port C Data Register volatile uhalf PCINT Port C Interrupt Control Register
29. PIPC PIP Configuration Register 0000 PADIR Port A Data Direction Register 00C1 PAPAR Port A Pin Assignment Register 01CO PAODR Port A Open Drain Register 0000 PBDIR Port B Data Direction Register 0000 0000 PBPAR Port B Pin Assignment Register 0000 F000 PBODR Port B Open Drain Register 0000 PCDIR Port C Data Direction Register 0500 PCPAR Port C Pin Assignment Register 0D00 PCSO Port C Special Option Register 0000 PCINT Port C Interrupt Control Register 0000 Table 5 MPC860 Port Register Programming MPC860 ATOMI User s Manual 1 0 13 No Restriction on Circulation 4 ATOMI SCC PARAMETER RAM When ATOMI operates on a particular SCC the SCC parameter RAM memory map is that shown in Table 6 The user must initialize the parameter RAM with the values given after reset or when re initializing ATOMI Address Name Width Description User Writes hex SCC Base 00 RBASE Halfword Receive BD Base Address UD SCC Base 02 TBASE Halfword Transmit BD Base Address UD SCC Base 04 RFCR Byte Receive Function Code UD SCC Base 05 TFCR Byte Transmit Function Code UD SCC Base 06 MRBLR Halfword Transparent Rx Max Buffer Length 0000 SCC Base 08 RSTATE Word Receiver Internal State use init rx tx command SCC Base 0C R_PTR Word Receiver Internal Data Pointer SCC Base 10 RBD_PTR Halfword Receive BD Pointer use init rx tx command SCC Base 12 R_CNT Halfword Recei
30. SCC2 Ethernet 1 4 Scrambling 1 ATM SCC ATOM1 1 19 SCC2 Ethernet 1 4 1 Ethernet No Scrambling note 3 SCC3 HDLC 1 3 in Z 1 HDLC ATOM1 11 SCC2 Ethernet 1 4 channel SCC1 3 Scrambling note 3 SCC3 HDLC 1 4 Notes 1 A frequency ratio of 1 12 equates to 2 048 MHz at 25 MHz 2 A frequency ratio of 1 390 equates to 64 KHz at 25 MHz 3 A frequency ratio of 1 19 equates to 2 048 MHz at 40 MHz Table 9 ATOMI and other Protocol Performance This data traffic in the experiments represents typical worst case scenarios for real life applications where PowerQUICC data structures were organised to maximise performance All frames were restricted to single buffers that were aligned to word addresses and receive frame address comparisons were disabled The Ethernet figures quoted in Table 8 are for half duplex operation The frequency ratios quoted are between the main PowerQUICC clock and SCC bit clock 9 1 Command Execution Latency When ATOM1 is operating typical and worst case command execution latencies are slightly longer than when only the standard ROM microcodes are running 1 The experimental Ethernet data rate was 5 Mbps full duplex which equates to 10 Mbps on a conventional half duplex Ethernet system MPC860 ATOMI User s Manual 1 0 29 No Restriction on Circulation Note The ATOMI Restart Reception command is not executed until ATOM1 processes the end of the current cell being received Therefore command latency for the Rest
31. Synchronisation Delta Counter ATOM CAM PORT 0x0001 CAM MATCH signal on PB31 ATOM gt RX_BUFF1 RXBUFF Receive Buffer Area Start Pointer ATOM gt TX_BUFF1 TXBUFE Transmit Buffer Page Start Pointer MPC860 ATOMI User s Manual 1 0 46 No Restriction on Circulation ATOM gt EHEAD 0x01000000 Empty Cell Header little endian ATOM gt EPAYLOAD 0x6a6a6a6a Empty Cell Payload ATOM gt RSTUFF 0 Receive Data Stuffing Location ATOM gt SHUFFLESTATE 0 Receive Data Stuffing State ATOM gt RHECTEMP 0x00ff Preset rx temp HEC storage area ATOM gt THECTE 0 Temporary HEC storage area ATOM gt ASTATUS 0 ATOM1 status word ATOM NMA HEAD 0 Non Matching Address Cell Header ATOM NMA CNT 0 Non Matching Address Cell Counter ATOM HEC ERR 0 HEC Error Counter ATOM gt RSCRAI 0 Receiver Scrambling Storage ATOM gt RSCRAMI 0 Receiver Scrambling Storage ATOM gt TSCRAI 0 Transmitter Scrambling Storage ATOM gt TSCRAM1 0 Transmitter Scrambling Storage ATOM gt HEADMASK Oxfffffffe Cell Header Comparison Mask
32. TATUS Halfword ATOM1 status halfword 0000 SCC Base 4C NMA HEAD Word Non Matching Address Cell Header SCC Base 50 NMA CNT Halfword Non Matching Address Cell Counter 0000 SCC Base 52 HEC ERR Halfword HEC Error Counter 0000 MPC860 ATOMI User s Manual 1 0 Table 6 ATOMI SCC Parameter RAM Memory Map 14 No Restriction on Circulation Address Name Width Description User Writes hex SCC Base 54 RSCRAM Word Receiver Scrambling Storage SCC Base 4 58 RSCRAM1 Word SCC Base 5C TSCRAM Word Transmitter Scrambling Storage SCC Base 60 TSCRAM1 Word SCC Base 64 HEADMASK Word Cell Header Comparison Mask UD SCC Base 68 HEAD1 Word Cell Header Look Up Table Entry 1 UD SCC Base 6C HEAD2 Word Cell Header Look Up Table Entry 2 UD SCC Base 70 HEAD3 Word Cell Header Look Up Table Entry 3 UD SCC Base 74 HEAD4 Word Cell Header Look Up Table Entry 4 UD SCC Base 78 HEAD5 Word Cell Header Look Up Table Entry 5 UD SCC Base 7C HEAD6 Word Cell Header Look Up Table Entry 6 UD SCC Base 80 HEAD7 Word Cell Header Look Up Table Entry 7 UD SCC Base 84 HEAD8 Word Cell Header Look Up Table Entry 8 UD SCC Base 88 HEAD9 Word Cell Header Look Up Table Entry 9 UD SCC Base 8C HEAD10 Word Cell Header Look Up Table Entry 10 UD SCC Base 90 HEAD11 Word Cell Header Look Up Table Entry 11 UD SCC Base 94 HEAD12 Word Cell Header Look Up Table Entry 12 UD SCC
33. The ATOM structures are better suited to handling numerous small data buffers as is required in ATM The BDs are just two bytes long instead of the normal eight byte BDs and buffers are fixed length Data buffers are scattered in receive and transmit buffer memory areas each 16K bytes located anywhere in the processor s memory map MPC860 ATOMI User s Manual 1 0 8 No Restriction on Circulation 3 REGISTERS ATOM1 requires several general MPC860 and SCC registers to be configured for operation and reports status in SCC registers 3 1 General Registers All the MPC860 general registers SIM memory controller chip select SDMA etc must be configured as described in the MPC860 User s Manual with the exception of the CP Control Registers and RISC Controller Configuration Register Interrupts are generated by ATOMI and the MPC860 interrupt controller must be configured by the user see the MPC860 User s Manual 3 1 1 RISC Controller Configuration Register RCCR The MPC860 s RCCR controls microcode operation To run ATOMI the RCCR should be set as shown in Figure 2 Further details are given in the MPC860 User s Manual 0 1 2 7 8 9 10 11 12 13 14 15 TIME TIMEP EX1M EXOM EX1P EIEE SCD ERAM ATOM1 0 0 0 0 0 0 0 0 0 1 0 Figure 2 ATOM1 RCCR Setting RCCR bit 14 enables the ATOM1 RAM microcode operation and this should not be done until ATOMI and the MPC860 are initialized Note the RISC
34. alculator is a command which ATOMI interprets by working through a data buffer generating the required CRC 32 sequence 2 4 PDH amp SDH Physical Layer Signalling amp OAM Functions PDH and SDH framing physical layer signalling and OAM functions are not provided by ATOMI but the user can handle these by routing the PDH SDH OAM signalling and overhead timeslots to one of the PowerQUICC s SMCs or another SCC 2 5 Traffic Control ATOMI transmits cells from it s single transmission gueue in the order that they are presented Itis the user s responsibility to apply traffic management technigues to avoid congestion and breaking the UPC rules if the connection data rate is less than the transmit bit rate Failure to apply these technigues may result in bursty traffic on open connections When ATOM1 s transmit queue is empty ATOMI will automatically transmit empty cells 2 6 Physical Interface The ATOMI microcode is independent of the physical interface standard used Generally one of the PowerQUICC s TDM ports will be used with ATOM1 to allow easy connection to an E1 or T1 line interface device Other serial interfaces are not precluded and may be selected when programming the MPC860 serial interface This User s Manual describes the TDM interface using the Time Slot Assigner TSA 2 7 Buffer Descriptor and Buffer Structures ATOM1 uses an optimized version of the standard MPC860 data buffer and buffer descriptor BD structures
35. allel Port Registers uenti ter HO ntn ES RR ESSE ATAQUES seed eA E Sant ke Pda e Rea aeg 13 4 ATOMI SCC PARAMETER RAM nn a E IRRE RSS 14 4 0 1 BD Queue Pointers RBASE and TBASE en 15 4 0 2 SCC Function Code Registers RFCR and TFCR eee 15 4 0 3 Transparent Mode Receive Maximum Buffer Length MRBLR 15 4 0 4 SCC Internal State Parameters RSTATE and TSTATE ees 15 4 0 5 BD and Buffer Pointers R_PTR RBD PTR T PTR and TBD PTR 16 4 0 6 Transmit and Receive Buffer Queue Start Pointers TX BUFFI RX_BUFF1 16 4 0 7 Buffer Counters R_CNT and T CNT eese eene 16 4 0 8 Receiver Delineation Counters ALPHA and DELTA pp 16 4 0 9 Version Number AVERSION S00 re i a aa a 16 4 0 10 CAM Port Selection CAM PORT ss 16 4 0 11 Empty Cell Data EHEAD and EPAYLOAD ss 17 4 0 12 Status Information ASTATUS me enne 17 4 0 13 Non Matching Header Storage and Counter NMA HEAD and NMA CNT 17 4 0 14 HEC Error Counter HEC BERRY nn ann Pie i oeil 18 4 0 15 Incoming Header Mask and Look up Table HEADMASK and HEADn 18 4 0 16 Temporary Data Storage acu de co dn itii eee c ah Baad 18 MPC860 ATOMI User s Manual 1 0 2 No Restriction on Circulation 5 ATOMEPCONNLANDS lens tin oi nr 19 5 1 Restart Reception Command isis 1 persi an tia erui dei Seti wai 19 5 2 CRC 22 Walia AE a dd EN 20 6 BUFFER DESCRIPTORS amp BUFFERS ee 21 6 1 ATO
36. and loaded into the tenth transmit buffer the Skip bit is cleared and the Ready bit set The voice cell is then transmitted with a maximum delay of nine cells Queue of Data 10 Tx BDs Transmission Task Controls Nine BDs Data Tx Task Tx BD 1 Tx BD2 Tx BD3 Tx BD 4 Tx BD 5 Tx BD6 Tx BD 7 Tx BD8 Tx BD 9 Tx BD 10 Internal Data Transmission Queue Incoming Data Traffic Bursty Voice Tx Task Incoming Voice Traffic Regular Voice Transmission Task Controls One BD Single Cell for Transmission Figure 12 Mixed Voice and Data Transmission Example MPC860 ATOMI User s Manual 1 0 25 No Restriction on Circulation 7 ATOMI CAM INTERFACE Figure 13 shows the ATOM1 CAM interface and a timing diagram illustrating operation Operation is similar to the Ethernet CAM interface see the MPC860 User s Manual for further details The SDACK1 signal delimits a header write cycle on the data bus and SDACK2 delimits payload write cycles Both SDACK1 and SDACK2 are asserted during the final payload write cycle ATOMI samples the MATCH signal during the last data transfer of the cell ET ATM gp TSA SCC me SDMA RAM MPC860 PowerQUICC PowerPC Core SDACK1 amp CAM MATCH SDACK2 FC 3 0 x CAM Control
37. and Update BD Figure 17 ATOM I Receiver Procedure MPC860 ATOMI User s Manual 1 0 34 No Restriction on Circulation Initial Entry Point Dac m Alpha 7 Consecutive Incorrect HECs HUNT 4 Byte by 4 Byte Search for Single Correct Correct HEC HEC Restart Reception Command Single Incorrect SYNCH Cell by Cell Verification of HECs PRESYNC Cell by Cell Search for Correct HECs Command Delta 6 Consecutive Correct HECs Figure 18 Cell Delineation State Diagram I 432 specifies that the hunt state searches for a correct HEC on a bit by bit basis but ATOM1 uses a word by word search For G 804 framing of ATM cells the HEC field is always aligned with the E1 or T1 frame octet timeslots so bit by bit searching is not required To ease implementation this was taken a stage further and ATOM1 uses a word by word search Over the course of four cells received 212 bytes with correct HECs there will be one matching and aligned HEC This is the point where the state machine jumps to the presync state In the presync state ATOMI has detected cell boundaries and is verifying that they are correct ATOM1 leaves the presync state after a single cell with an incorrect HEC is received or the Restart Reception command is given When six consecutive cells with valid HECs are received ATOM1 jumps to the sync state and begins reception The state machine advances immediately after recepti
38. ansmitted a CRC 32 or NMA error will result on reception because a different data cell was transmitted BD init ATXBD BD init ATXBD 1 YI N ES NO NO TXBUFF TXBUFF 4 O NO NO TXBUFF TXBUFF 0 BD init ATXBD 2 NO NO YES TXBUFF TXBUFF 0 txcount txcount 2 Increment transmit cell counter Incoming cell headers a Ti checked in the header lookup table HEADMASK and HEAD16 were set up for in atom init called earlier while SCC1 gt SCCE amp 0x00f5 0x0000 Wait for reception of first cell or error if SCCI gt SCCE amp 0x00f4 0x0000 On error set error flag rxcount rxcount 1 Otherwise increment rx counter else pperror 1 No Restriction on Circulation SCC1 gt SCCE Oxffff Clear SCCEL while SCC1 gt SCCE amp 0x00f5 0x0000 Wait for reception of second cell or error if SCC1 gt SCCE amp 0x00f4 0x0000 On error set error flag rxcount rxcount 1 Otherwise increment rx counter else pperror 1 Check that the first received cell has the correct AAL5 CRC 32 value CRC32 gt CRC_PTR RXBUFF 4 CRC32 gt CRC_CNT 44 CRC32 gt CRC_FC 0x10 Use Motorola byte ordering big endian CRC32 2CRC RESULT 0 Result register must be preset to zero at the start CP gt RTER 0x8000 RTER is us
39. art Reception command depends on when the command is given and data rate 9 2 CRC 32 Calculation Execution Table 10 shows the results of some performance characterisation experiments where ATOMI is running on one or more SCCs while CRC 32 calculations are also running The PowerQUICC s CP runs the CRC 32 calculator as its lowest priority task so the duration of a calculation varies depending on the exact loading and state of the CP The CRC 32 calculations were run over a buffer of 44 bytes representing the AALS5 payload of a single cell AAL5 frame with start of the data buffer aligned to a word address All results shown in Table 10 are for system operation at 25MHz and can be scaled for operation at other frequencies Configuration ATOM1 SCCs Mode Frequency Ratio Prices Duration 1 ATM SCC1 ATOM1 No Scrambling 1 12 note 1 20 24 us 1 ATM SCC1 ATOM Scrambling 1 12 note 1 20 28 us 2 ATM SCC1 2 ATOM No Scrambling 1 12 note 1 28 37 us 2 ATM SCC1 2 ATOM1 Scrambling 1 12 note 1 52 72 us 3 ATM SCC1 2 3 ATOM t No Scrambling 1 12 note 1 52 76 us 3 ATM SCC1 2 3 ATOM1 No Scrambling 1 25 note 2 23 30 us 3 ATM SCC1 2 3 ATOM1 Scrambling 1 25 note 2 27 52 us 4 ATM SCC1 2 3 4 ATOM1 No Scrambling 1 25 note 2 26 34 us 4 ATM SCC1 2 3 4 ATOM1 Scrambling 1 25 note 2 40 65 us Notes 1 A frequency ratio of 1 12 equates to 2 083 MHz at 25 MHz 2 A frequency ratio of
40. as shown in Table 7 The user must initialize the CRC 32 parameter RAM with the values given after reset or when re initializing ATOMI Address Name Width Description User Writes hex DPRBASE DBO CRC_PTR Word CRC 32 Calculator Pointer UD DPRBASE DB4 CRC_CNT Halfword CRC 32 Calculator Counter UD DPRBASE DB6 CRC_FC Byte CRC 32 Calculator Function Code UD DPRBASE DB8 CRC RESULT Word GROS Calculator Seed Value and 0000 0000 or UD UD User Defined Table 7 ATOM1 CRC 32 Calculator Parameter RAM Memory Map To start a CRC 22 calculation the CRC PTR CRC CNT CRC RESULT and CRC FC parameters must be initialised to give the start address of the data block for the calculation block length starting CRC 32 seed and function code ATOM1 reads and writes these four parameters during a CRC 32 calculation so they must not be altered by the user while the calculation is in progress The CRC_PTR may be programmed with any address that corresponds to the start of the CRC 32 buffer in memory The length of the buffer must be programmed into the CRC_CNT parameter If CRC_CNT is zero at the start of the command ATOM1 will run a Restart Reception command rather than the CRC 32 calculator The CRC_RESULT parameter must be preset to zero at the start of a new CRC 32 calculation On completion of the calculation CRC_RESULT holds the resulting 32 bit CRC value At the beginning of a CRC 32 calculation CRC_RESULT ma
41. bits masked before the comparison The user must maintain enough open channels to receive OAM and signalling cells User software must handle OAM and signalling cells 2 2 Cell Delineation The user must provide synchronisation signals to the PowerQUICC and octet align incoming cells to the synchronisation signals ATOMI provide SDH PDH oriented cell delineation using the HEC mechanism defined in 1 432 on an octet basis The synchronisation signals need not delimit the start of cell but must be octet aligned with incoming cells When using E1 and T1 ATM links the cells are always octet aligned see ITU G 804 and synchronisation signals are provided by the E1 and T1 interface devices MPC860 ATOMI User s Manual 1 0 7 No Restriction on Circulation When reception commences ATOMI takes a short while to acquire correct cell delineation Once ATOM1 has locked to the incoming cell stream it remains locked unless there are excessive errors An interrupt is generated whenever the cell lock status changes and a status bit will indicate the current delineation status Further details of the cell delineation mechanism are given in Appendix A 2 3 AAL Frame Check Sequences To increase software throughput of AAL5 frames a CRC 32 calculator is included This is not an integral part of the cell transmission and reception process in order that CRC 32 sequences may be calculated across long AAL5 frames made up of interleaved ATM cells The CRC 32 c
42. changes without further notice to any products herein Motorola makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Mo any liability arising out of the application or use of any product or circuit and specifically disclaims any and orola assume all liability including without limitation consequential or incidental damages Typical parameters that may be provided in Motorola data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s echnical experts Motorola does not convey any license under its patent rights nor the rights of others Motorola products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur Should Buyer purchase or use Motorola produc s for any such unintended or unauthorized application Buyer shall indemnify and hold Motorola and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorn ey fees arising out of directly
43. ct CP regs Intr struct Int regs PortA struct PortA regs PortC struct PortC regs PIP struct PIP regs SI struct SI regs SUC struct SCC regs ATOM1 1 struct ATOM1 Params CRC32 struct CRC32 calculator SDCR uword SIRAM uhalf PQUICC 0x0c00 ATXBD uhalf ATXBDO ARXBD uhalf ARXBDO ATXBuff ubyte TXBUFF ARXBuff ubyte RXBUFF BDSpace uhalf BDArea Configure PowerQUICC Parallel Ports config parallel ports Reset PowerQUICC CP gt RCCR 0 CP gt CR 0x8001 CPM Clear RCCR i Reset CPM Configure Serial Interface and TSA config_tsa Disable all interrupts MPC860 ATOMI User s Manual 1 0 PQUICC 0x9c0 PQUICC 0x940 PQUICC 0x950 PQUICC 0x960 PQUICC 0xab0 PQUICC 0xae0 PQUICC 0xa00 PQUICC 0x3c00 PQUICC 0x3db0 PQUICC 0x030 40 No Restriction on Circulation Intr CIMR 0 Initialise and enable RAM microcode config ucode Configure SCC1 for ATOM1 atom init SCC1 ATOMI 1 CP gt CR 0x0001 Initialise SCCl rx and tx parameters Configure ATOM1 Data Buffers amp Buffer Descriptors Clear out the whole BD area for count 0 count MAXBDAREA count BDSpacet 0 BDSpace uhalf BDArea Clear receive buffer area for bytecnt 0 bytecnt lt MAXBUFF BUFFSIZE bytecnt
44. cy would be too high MPC860 ATOMI User s Manual 1 0 24 No Restriction on Circulation The transmit bandwidth reservation system avoids this problem by allowing selected BDs to be reserved for the voice transmission When ten BDs are allocated to the data and voice transmission software tasks nine can be assigned for data and one for voice This reserves 10 of the transmission bandwidth for voice channels The reservation mechanism uses the Skip bit in the transmit BD As ATOM1 processes the transmit BD queue it transmits cells where the Skip bit is zero When a BD with the Skip is encountered it is skipped and an empty cell is transmitted in its place In the mixed data and voice example the data transmission software can control nine of the ten BDs and set their Ready bits to initiate transmission The voice transmission software reserves one BD by setting its Skip bit When a voice cell is ready for transmission the voice transmission software inserts the header and payload in the relevant transmit data buffer clears the Skip bit and sets the Ready bit Next time that ATOMI checks this BD it will see only the Ready bit set and therefore transmit the voice cell Figure 12 illustrates this example The tenth transmit BD is reserved for voice traffic While the voice transmission task is constructing an ATM cell and has nothing in the transmit BD queue it reserves bandwidth by setting the Skip bit When the voice cell has been constructed
45. d void void void void config parallel ports config tsa config ucode atom init struct SCC regs BD init uhalf go forever int Define Pointers to PowerQUICC struct struct struct struct struct struct CP regs Int regs POrtA regs PortC regs PIP regs SI regs EGP Intr PortA PortC PIP SI int int Empty Cell Empty Cell Header Payload Receive Data Stuffing Location struct ATOM1 Params uword uword Registers and SCC Parameter RAM YA MPC860 ATOMI User s Manual 1 0 39 Receive Data Stuffing State Temporary HEC storage area Temporary HEC storage area ATOM1 status word Non Matching Address Cell Header Non Matching Address Cell Counter HEC Error Counter Receiver Scrambling Storage Receiver Scrambling Storage Transmitter Scrambling Storage Transmitter Scrambling Storage Cell Header Comparison Mask Cell Header Look Up Table Entry 1 Cell Header Look Up Table Entry 2 Cell Header Look Up Table Entry 3 Cell Header Look Up Table Entry 4 Cell Header Look Up Table Entry 5 Cell Header Look Up Table Entry 6
46. e HEADn table the user may define fewer The final location in the table is denoted with the Last bit being set When multiple HEADn locations are being used the user should take care because the look up table can overlap other peripheral areas in memory see the MPC860 User s Manual for further details If the look up table is extended to overlap other peripheral s parameter RAM areas the other peripherals cannot be used The bit locations for the HEADn locations are shown in Figure 7 Bit 31 should be written with zero except for the last entry in the table 0 3 4 11 12 27 28 30 31 GFC VPI VCI PT Last Figure 7 HEADn ATOMI searches the HEADn table sequentially so the headers for the most frequently connections should be at the beginning of the table 4 0 16 Temporary Data Storage During ATM cell transmission and reception ATOM1 uses RTEMP TTEMP RSTUFF RHECTEMP THECTEMP RSCRAM RSCRAMI TSCRAM and TSCRAMI to store temporary data This data is for internal use and the user must not write to these locations MPC860 ATOMI User s Manual 1 0 18 No Restriction on Circulation 5 ATOM1 COMMANDS The following commands are understood by ATOM1 e Initialise Receiver and Transmitter Parameters e Initialise Receiver Parameters e Initialise Transmitter Parameters e Stop Transmit Restart Transmit Restart Reception e CRC 32 Calculator Execution of other SCC commands may cause errant behaviour All
47. e data buffer from the start of the 16K byte transmit data area ATOMI transmits the ATM cell stored in the transmit buffer and automatically inserts the HEC Data buffers are all 52 bytes long with the first four bytes being the cell header as shown in Figure 11 The first byte of the buffer is the first byte to be transmitted GFC VPI VCI PT CLP Payload Payload Payload Figure 11 Transmit Buffer 6 3 1 Transmit Bandwidth Reservation ATOMI includes a mechanism to reserve transmit bandwidth to aid tasks that require low latency transmission An example of such a system might be one that simultaneously handles voice and data transmissions the data transmission task can queue a large number of ATM cells that are not delay sensitive while the voice transmission circuit has less traffic but must be serviced at regular intervals The mixed voice and data example is used here to illustrate the bandwidth reservation system In most systems the number of transmit and receive buffer descriptors and buffers per SCC is fixed when the system software is designed For example the ATOMI transmit queue may be fixed at ten buffers The data transmission software can maintain its own software queue that may hold several hundred cells The voice task must transmit each cell as soon as it is generated and not store them in a queue If the voice cells were to be placed at the end of the software data transmission queue the laten
48. ect code object code for the 860ADS board a User s Manual and demonstration software for the 860ADS board ATOM1 is available on DOS media by using the following part number MPC860SWATM1 DOS PC disk 13 REFERENCES MPC860 User s Manual Motorola 1996 ITU 1 432 B ISDN User Network Interface Physical Layer Specification 1991 ATM Forum User Network Interface Specification version 3 0 1993 Draft Recommendation ITU G 804 ATM Cell Mapping into Plesiochronous Digital Hierarchy PDH 1993 5 ITU 1 363 B ISDN ATM Adaptation Layer Specification Ae NN HM MPC860 ATOMI User s Manual 1 0 31 No Restriction on Circulation Appendix 1 STATE MACHINE DETAILS A1 1 ATOM1 Transmitter Figure 15 shows the ATOMI transmitter procedure After start up when MRBLR is zero an empty cell is transmitted before the first transmit BD is polled If the BD has the Skip bit set an empty cell is transmitted and the transmitter moves to the next BD If the BD is ready a user defined ATM cell is transmitted otherwise another empty cell is transmitted Operation continues in this manner until the Stop Transmit command or a FIFO underrun error occurs of the user disables the SCC transmitter The transmitted cells may have their payloads scrambled as described below h Goto Transparent MRBLR 0 Mode ROM Microcode Yes Transmit Empty Cell Transmit Data Cell Header Transmit Empty Cell Header Calculate Empty Cell
49. ed cell delineation and is receiving cells 4 0 13 Non Matching Header Storage and Counter NMA HEAD and NMA CNT When a cell is received with a non matching header the header minus the HEC is written to NMA HEAD NMA CNT is incremented and the NMA bit set in the SCCE NMA HEAD isa MPC860 ATOMI User s Manual 1 0 17 No Restriction on Circulation location where headers from non matching cells are logged and NMA_CNT is a counter of non matching cells The user is free to read and clear NMA CNT at any time 4 0 14 HEC Error Counter HEC ERR HEC ERR is a 16 bit counter of incoming cells with HEC errors The user is free to read and clear HEC ERR at any time 4 0 15 Incoming Header Mask and Look up Table HEADMASK and HEADn When the CAM option is disabled ATOM1 masks the header of each incoming cell with HEADMASK and then searches for the result in the HEADn table When a match is found the cell is received otherwise the cell header is logged in NMA HEAD and the remainder of the cell is discarded The HEADMASK masking process uses a bitwise AND function so bits can be masked out by clearing the relevant bit in HEADMASK The bit locations for HEADMASK are shown in Figure 6 Bit 31 must always be written with zero 0 3 4 11 12 27 28 30 31 GFC VPI VCI PT 0 Figure 6 HEADMASK The result of the masking is then compared with each of the HEADn values starting with HEAD1 Although sixteen locations are shown in th
50. ed to indicate that a CRC 32 calculation has completed CP gt CR 0Ox0f01 Start the CRC 32 calculation PortA gt PADAT 0x0001 Set PA15 pin while CP gt CR 0x0f00 Wait for the CP command to complete while CP gt RTER 0x8000 Wait for the CRC32 calculator to complete PortA gt PADAT 0x0000 Reset PA15 pin If incorrect CRC32 receiver set error flag if CRC32 gt CRC RESULT 0x864d7f99 pperror 1 Check that the second received cell has the correct AAL5 CRC 32 value CRC32 gt CRC_PTR RXBUFF 0x44 CRC32 gt CRC_CNT 44 CRC32 gt CRC_FC 0x10 Use Motorola byte ordering big endian CRC32 2CRC RESULT 0 Result register must be preset to zero at the start CP gt RTER 0x8000 RTER is used to indicate that a CRC 32 calculation has completed CP gt CR Ox0f01 Start the CRC 32 calculation PortA gt PADAT 0x0001 Set PA15 pin while CP gt CR 0x0f00 Wait for the CP command to complete while CP gt RTER 0x8000 Wait for the CRC32 calculator to complete PortA gt PADAT 0x0000 Reset PA15 pin If incorrect CRC32 receiver set error flag if CRC32 gt CRC RESULT 0x864d7f99 pperror 1 The while loop is only left when an error occurs so go to a loop forever By jumping to a function a breakpoint can be easily set on the
51. ent BD and data locations RBD PTR and TBD PTR point to the current or next BD to use and need to be initialized with the Init Rx Tx command to point to the locations given in RBASE and TBASE R PTR and T PTR point to the next data location in memory When ATOM is operating these locations should not be written by the user Further information is given in the MPC860 User s Manual 4 0 6 Transmit and Receive Buffer Queue Start Pointers TX BUFF1 RX BUFF1 The user configures TX BUFF1 and RX_BUFF1 to define the starting location of the transmit and receive buffer areas in main memory This is the starting address of the 16K byte areas where transmit and receive buffers reside TK BUFF1 and RX_BUFF1 must be word aligned addresses bits 31 and 30 must be zero TX BUFF1 and RX_BUFF1 can be dynamically changed provided that care is taken to synchronise the buffer queues held in user software and the queues that the PowerQUICC s CP sees The CPM reads TX BUFF1 and RX BUFFI every time that it opens a data buffer so it is advised that the transmit and receive queues are allowed to empty before TX BUFFI1 and RX BUFFI are changed 4 0 7 Buffer Counters R_CNT and T CNT During ATM cell transmission and reception ATOMI uses R CNT and T CNT to count the number of bytes transmitter or received The user must not write to these locations 4 0 8 Receiver Delineation Counters ALPHA and DELTA ATOM1 applies the HEC delineation mechanism described in
52. g an empty cell cell delineation is immediately lost and the resynchronisation process begins If the current cell being received is a data or control cell being received or discarded by ATOM1 the current buffer is closed and cell delineation is lost at the end of the cell The Enter Hunt Mode command should not be used with ATOMI To restart the receiver immediately regardless of the current state the Init Rx Parameter command can be used MPC860 ATOMI User s Manual 1 0 19 No Restriction on Circulation The Restart Reception Command and the CRC 32 Calculator share the same op code in the command register To issue a Restart Reception Command the user must ensure that the current CRC 22 calculation is complete and the CRC_CNT parameter is zero 5 2 CRC 32 Calculator The CRC 32 Calculator command calculates the 32 bit CRC sequence used in AAL5 frames on a data buffer defined by a pointer and length Multiple buffers may be strung together by the user to calculate the CRC 32 value over a large AAL5 frame made up of multiple CRC 32 buffers ITU 1 363 gives more details and examples of AAL5 CRC calculations Note The PowerQUICC s CP runs the ATOM1 CRC 32 calculator as its lowest priority task High traffic throughput on the SCCs and other CP activity will adversely affect the CRC 32 calculator s performance The ATOM1 CRC 32 calculator replaces four parameters in PowerQUICC s RISC Timer Parameter RAM area starting at DPRBASE DBO
53. gt PADIR O0x00c1 Port A data direction register PortA gt PAPAR 0x01c0 Port A pin assignment register PortA gt PAODR 0 Port A open drain register PortC PCDIR 0x0500 Port C data direction register PortC gt PCPAR 0x0d00 Port C pin assignment register PortC gt PCSO 0 Port C secial option register PortC PCINT 0 Port C interrupt control register PIP gt PBDIR 0x00000000 Port B data direction register PIP gt PBPAR 0x0000f000 Port B pin assignment register PIP PBODR 0 Port B open drain register End of config_parallel_ports I A RRA AA ee A A AA AA ee A A AA AA I I I He He ee ya POWEROUICC TSA CONFIGURATION amp INITIALISATION A I A A RR AA KK ko ko ko kk AA Kok kk KR KR ee A A AAA I koe e Function name config_tsa I ko kk RR AAA ee A A AA AA ee AA AAA I I I He He He He xe x Configure Serial Interface and TSA as follows E 1 TDMA used to tx and rx 53 byte ATM cells via SCCI and SCC2 Le yx Common rx and tx clock and synchronisation signals IE Tx data on falling clock edges and rx on rising edges A ya Frame sync signal recognised on a rising clock edge I A RR AAA Ck Ck CK CK E ko ko ko KR kk ko kk kk ee ko koX AAA I I koe e e Input Parameters global data structure SI and pointer SIRAM xf MPC860 ATOMI User s Manual 1 0 44 No Restriction on Circulation x La Output Parameters SI
54. ha Counter Receiver Synchronisation Delta Counter ATOM1 version number ATOM1 CAM Port Mask Receive Buffer Area Start Pointer Transmit Buffer Page Start Pointer 38 No Restriction on Circulation vol VOL VOL VOL VOL latil vol VOL latil vol VOL VOL VOL VOL latil vol VOL VOL VOL VOL latil vol VOL VOL VOL VOL VOL VOL latil vol VOL latil vol Vol Vol VOL VOL latil atil atil atil atil atil atil atil atil atil atil atil atil atil atil atil atil atil atil atil atil atil atil atil Le Le Le Le Le Le Le Le Le Le Le Le Le Le Le Le Le Le Le Le Le Le Le Le Le Le Le Le Le Le ati Le struct CRC32 calculator volatile volatile volatile volatile uword EHEAD uword EPAYLOAD uword RSTUFF uhalf SHUFFLESTATE uhalf RHECTEMP uhalf THECTEMP uhalf ASTATUS uword NMA HEAD uhalf NMA CNT uhalf HEC ERR uword RSCRAI uword RSCRAMI uword TSCRAI uword TSCRAMI uword HEADMASK uword HEAD1 uword HEAD2 uword HEAD3 uword HEAD4 uword HEAD5 uword HEAD6 uword HEAD7 uword HEADS uword HEAD9 uword HEAD10 uword HEAD11 uword HEAD12 uword HEAD13 uword HEAD14 uword HEAD15 uword HEAD16 uword CRC_PTR uhalf CRC CNT A ubyte CRC FC A ubyte reservedl uword CRC RESULT Declare Functions void voi
55. iven in the 860ADS User s Manual The ATOM1 microcode occupies the internal RAM blocks DPRBASE 2000 to DPRBASE 23FF and DPRBASE 2F00 to DPRBASE 2FFF These areas are unavailable for use by the user Once the ATOMI1 microcode is loaded into the MPC860 s internal RAM it is initialized as follows Configure SDMA Configure parallel ports Configure serial interface Enable TSA Configure CP registers Enable RAM microcode Configure SCC registers Configure GSMR PSMR SCCE and SCCM to select required operation 8 Configure ATOMI parameter RAM 9 Initialize queue of empty receive BDs and buffers 10 Clear transmit BDs 11 Enable SCC by setting ENT and ENR bits in the GSMR lower word ND O1 PWN rnm Once initialisation is complete ATOM1 can be controlled through the transmit and receive BD queues and commands Example source code for initialisation and operation of ATOM1 is given in Appendix B 9 PERFORMANCE Tables 8 and 9 show the results of some performance characterisation experiments where ATOM1 is run concurrently with other SCCs All results are for zero wait state access to memory In the experiments all SCCs were continually transmitting and receiving data cells no commands or CRC 32 calculations and frames of the following size MPC860 ATOMI User s Manual 1 0 27 No Restriction on Circulation HDLC frames Ethernet frames 24 bytes data 2 bytes CRC 64 bytes data 4 bytes CRC
56. koe eee x Configure tx buffer area with AAL5 sample frame given in I 363 appendix ATXBuff 0 0x12 ATXBuff 1 0x34 ATXBuff 2 0x56 ATXBuff 3 0x78 YA Cell header 0212345678 x Not an OAM cell 7 AAL5 single cell frame payload consists 40 bytes of zero CPCS UU 0 MPC860 ATOM1 User s Manual 1 0 42 length 40 and CRC32 0x864d7f99 7 for bytecnt 4 bytecnt 44 bytecnt ATXBuff bytecnt ATXBuff bytecn ATXBuff bytecn ATXBuff bytecn ATXBuff bytecn ct ct ct ct ATXBuff bytecn ATXBuff bytecn ATXBuff bytecn ATXBuff bytecn CF oct ct ect pperror 0 while pperror 0 xl SCC1 gt SCCE Oxffff 0x00 AALS frame payload x00 AAL5 frame control long word 0x00000028 x00 x00 x28 O x86 AAL5 frame CRC x4d RE f x99 C9 O Clear SCCE1 Set up two RX BDs with Int and Wrap bits set in the second BD init ARXBD BD init ARXBD 1 Tx two ATM cells NI NI O YES NO RXBUFF RXBUFF 0 O YES YES RXBUFF RXBUFF 0x40 Three TX BDs are set up but only two cells transmitted because the SKIP bit is set in the first Wrap bit set in the third descriptor No interrupts generated If the buffer with the SKIP bit set is tr
57. l AAL protocols e Handles serial data rates up to 8 Mbps with a 25 MHz PowerQUICC and up to 16 Mbps with a 50 MHz PowerQUICC e Any or all of the PowerQUICC s SCCs can simultaneously handle ATM cells e Transmit and receive data buffers located in main memory e On transmission ATOM1 constructs the cell header and appends the user defined payload e Bandwidth reservation option in the transmit queue to allow mixing of data and isochronous services e On reception ATOM verifies incoming cell headers and strips the HEC before passing the cell to the user e Automatic empty cell transmission when there are no pending data transfers e Receiver filters and discards empty cells and those with non matching addresses CAM support on reception for handling many connections User controlled cell scrambling option Incoming cells with incorrect HECs are received and marked as such e A CRC 22 calculator is available to reduce processor performance requirements when MPC860 ATOMI User s Manual 1 0 5 No Restriction on Circulation handling AALS cells e Standard PowerQUICC features are available when ATOM1 is running ETATM E1 ATM Line Transceiver RISC CP PowerPC Core SIM Relay Driver E1 ATM E1 ATM Line 5 Transceiver 2 Frame E Dual Port RAM Relay Frame o oO E System 14 SDMAS UART RS 232 2 IDMAs Generator Interrupt Memory EM Controller Controller MPC860 PowerQUICC System ys System Boot ROM 3
58. modified WA Za e I Ok ko ko kCKCKCKCkCkCk kk kk CK KR HRK ARR KR ee ko ke kk A AAA koi koe ee void config tsa int count SI registers SI gt SIGMR 0x00 Disable SI SI gt SIMODE 0x00000058 SI mode register without loopback SI SIMODE 0x00000858 SI mode register with TSA loopback SI gt SICR 0x00004040 SI clock route Clear SI RAM for count 0 count lt SI_RAM SIZE count STRAM 0x0000 SIRAM SIRAM uhalf PQUICC 0x0c00 Configure SI RAM L1ST1 asserted during the first 4 tx bytes cell header except HEC L1ST2 asserted during the fifth tx byte HEC L1ST3 asserted during the first 4 rx bytes cell header except HEC L1ST4 asserted during the fifth rx byte HEC SIRAM 0 Ox104e Rx cell header SCC1 SIRAM 2 0x2042 Rx cell HEC SCC1 SIRAM 4 Ox007e Rx cell payload 16 bytes SCC1 SIRAM 6 0x007e Rx cell payload 16 bytes SCC1 SIRAM 8 Ox007f Rx cell payload 16 bytes SCC1 SIRAM 0x80 0x044e Tx cell header SCC1 y SIRAM 0x82 0x0842 Tx cell HEC SCC1 SIRAM 0x84 0x007e Tx cell payload 16 bytes SCC1 SIRAM 0x86 0x007e Tx cell payload 16 bytes SCC1 SIRAM 0x88 0x007f Tx cell payload 16 bytes SCC1 Enable SI SI
59. must be reset by the user writing a one MPC860 ATOMI User s Manual 1 0 10 No Restriction on Circulation Bits 0 7 are set by the SCC hardware and some unused bits may be set The user should mask interrupts from all unused bits in the SCCM Bits 8 15 are set by ATOMI to indicate events that it has detected see Figure 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 eur eer occ nma sync Fito ec oam 8v 1x mx Figure 4 ATOM1 SCCE RX A cell has been received and a receive buffer used This bit is set on completion of reception TX A cell has been transmitted and a transmit buffer used BSY A cell was received and discarded due to lack of receive buffers OAM A control cell OAM or reserved for future use as indicated by the PT field been received and a receive buffer used This bit is set on completion of reception When this bit is set the RX bit is also set but about 10 system clocks later HEC A cell has been received with a HEC error This bit is also set when the SYNC bit is set The HEC bit is set as soon as a HEC error is detected it does not wait until the complete cell is received FIFO A transmit FIFO underrun or receive FIFO overrun error has occurred See ASTATUS for the exact status SYNC ATOMI has lost or gained cell delineation NMA ATOMI received a cell with a non matching address DCC The carrier sense status as generated by the DPLL has changed See description of the Tran
60. n a copy of the address pointer for each receive BD in the receive queue MPC860 ATOMI User s Manual 1 0 22 No Restriction on Circulation 4 5 6 7 8 9 10 11 12 13 14 15 E Ww A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 Empty Receive BD as Written by User E Ww OAM ERR HEC Used Receive BD after reception of a Cell Figure 9 ATOMI Receive Buffer Descriptor E Empty Control bit set by the user to indicate that the associated buffer is empty and ATOM1 can receive a cell into it W Wrap Control bit set by the user to wrap the receive BD queue after this BD I Interrupt Control bit set by the user When a cell is received into the buffer associated with this A18 A29 Address OAM OAM Cell ERR HEC Error HEC HEC Byte BD a receive interrupt is generated Address offset to the start of the data buffer from the start of the 16K byte receive data area Status bit set by ATOM1 The associated cell is an OAM or reserved cell cell PT field 1xx Status bit set by ATOM1 The associated cell was received with an error in the header as detected by the HEC check Byte containing the received cell s HEC field ATOM1 stores received ATM cells in receive buffers after removing the HEC Receive data buffers have the same structure as transmit buffers The first byte of the buffer is the first byte received the GFC field and part of the VPI The HEC field is removed and stored in the
61. non zero value the SCC operates in transparent mode Mixed mode operation of an SCC where the transmitter runs ATOMI and the receiver is in transparent mode or vice versa running ATOM1 is not allowed When ATOM1 is loaded and running the maximum serial performance of an SCC in transparent mode is reduced very slightly 3 2 2 Protocol Specific Mode Register PSMR The SCC Protocol Specific Mode Register PSMR controls various SCC functions that are protocol specific Before enabling ATOM1 the user should initialize the PSMR The PSMR should only be written when the transmitter and receiver are disabled otherwise erratic behaviour could result For ATOMI the PSMR is used to control the scrambling and HEC coset functions of both the transmitter and receiver see Figure 3 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Figure 3 ATOM1 PSMR SCRAM 0 Disable cell payload scrambling during transmission and reception 1 Enable cell payload scrambling during transmission and reception COSET 0 Do not apply the HEC coset rules 1 Apply the HEC coset to all transmitted and received cells 3 2 3 SCC Event Register SCCE The SCC event register SCCE contains status bits for events recognized by ATOMI and the SCC circuitry Whenever a bit is set in the SCCE an interrupt to the user is generated unless the corresponding bit in the SCC Mask register SCCM is set All bits in the SCCE are sticky bits they are set by the SCC hardware or ATOM and
62. nsmit or receive BD 7 I kk KCKCKCKCkCkCkCkCkCkCk Ck ee ko kk CK CKCkCkC kk ko KR ee A A AA K KR OK koi koe e e Input Parameters Pointer to the BD ah yA Flags for Skip Interrupt and Wrap bits The adresses of the start of data buffer ud JR area and the actual data buffer within that area to tx LA WA Output Parameters BD queue modified yA LA I ee A RR AAA I KR ko ko kk CKCKCKCkC kk ke kk kk ee RER RH I I IH He He e ex f void BD init new BD skip i rupt wrap page address uhalf new BD int Skip i rupt wrap uword page address MPC860 ATOMI User s Manual 1 0 47 No Restriction on Circulation uhalf BD contents BD contents 0x8000 if skip 0 BD contents BD contents 0x4000 Set tx BD skip bit if i rupt 0 BD contents BD contents 0x1000 Set BD interrupt bit if wrap 0 BD contents BD contents 0x2000 Set BD wrap bit Append address BD contents BD contents uhalf address page gt gt 2 new BD BD contents End of BD init I A RRA AK A A AA AA ee ke kk A AA AA I I I koe e ATOMI ENDLESS LOOP ROUTINE J CREEK A RRA AK A AAA AA ee A A AAA I I He e ee Function name go_forever I He ko kk CKCKCKCkCkCkCkCk kk A KICK Kok k ko kk kk ee kk AAA AA I koe ee This routine simply loops forever and provides a way for the WA target board to breakpoint easily
63. on of the sixth correct HEC and is not delayed until the end of the cell This means that five cells with valid HECs are discarded and the sixth is received into a data buffer In the synch state ATOMI receives data and control cells and discards incoming empty cells When a stream of cells with incorrect HECSs are received the first six consecutive cells are received and on reception of the seventh incorrect HEC ATOM1 immediately jumps to the hunt state and does nor receive the cell with the seventh incorrect HEC ATOM1 also jumps to the hunt state after the Restart Reception command When cell payload scrambling is enabled the descrambler will self synchronise with the incoming data after 43 bits Hence after starting the receiver the descrambler will attain synchronisation during reception of the first cell in the presync state MPC860 ATOMI User s Manual 1 0 35 No Restriction on Circulation Appendix 2 ATOMI DEMONSTRATION SOFTWARE This appendix contains demonstration software for ATOM1 The software is assembled for use on the QUADS board and assumes that the ATOM1 microcode is downloaded separately Before running this software the user should either link two QUADS boards both running ATOMI or externally loopback the master MPC860 transmitter and receiver on one QUADS board V CREEK ko kk RRA AK A AAA IC Kok ke kk kk ee ke kk AAA AA ko ke ee ATOMI Microcode Initialisation and Ping Pong Software
64. otorola i M MOTOROLA MPC860 ATOM User s Manual 1 0 No Restriction on Circulation TABLE OF CONTENTS 1 INTRODUCTION siessen tr rd oe aoee ASA ESA ia oksaa 5 1 1 Key Features of ATOMI wizi Ini aia e its URP aata 5 1 2 NIDCSOU SCUS S ane AA test Orbit eM ere DEC e dL LS utm uad 6 1 3 CONVENTIONS AA 6 Zi ATOMT OPERATION ini na i RE OE d e LU ku UA 7 2 1 Number or Connections ose 0 ee te ae mp Packs Lc DE 7 2 2 Cell Dele OD see ee ee a E aA 7 2 3 AAL Frame Check S quenees i dd i neon et Relate cued 8 24 PDH amp SDH Physical Layer Signalling amp OAM Functions ee 8 2 9 LARG Control ER ee de RE ee es ed a E 8 2 6 Physical MIAGE ER ee ee TA MAANA AWATA AA ee 8 2 7 Buffer Descriptor and Buffer Structures er 8 3 REGISTERS un tated 9 3 1 General R gisterS sono ee a ui 9 3 1 1 RISC Controller Configuration Register RCCR Ne 9 3 1 2 CP Control Registers ee MAA AA AA AAA 9 3 2 D C ROPISIGTS 0 dd quen taa A uerus rU 9 22 1 General SCC Mode Register GIS MB Nt 10 322 Protocol Specific Mode Register PSMR eese 10 323 SCC Event Register SCC b soo NES nd A Sun ue 10 3 2 4 BOC Mask Register SC OM iors ee ee ie eeo qute qvos teal sende en det ed 11 O9 BCC Status Register S CE S as nee ne aaa dtes tuu R 11 3 3 S rial Interface met NI KE PM 11 3 3 1 Serial Interface Registers ii 12 33 2 Serial Interface RAM 000 0 s a wai 12 3 4 Par
65. ption An option is included to apply the HEC coset pattern binary 01010101 to transmitted and received cells ATOM1 performs cell rate adaptation to the capacity of the transmission link by the inserting empty cells when no cells are queued by the user On reception ATOM1 ignores empty cells The user can define the empty cell to be either an unassigned or idle cell Received cells with HEC errors are received and marked as such The HEC is passed to the user to allow user software to implement HEC correction algorithms as required ATOMI does not attempt to correct any HEC errors ATOM1 provides an option to scramble data on transmission and receive scrambled data using the X1 scrambling algorithm The first cell to be transmitted by ATOMI after initialisation will not be correctly scrambled because there is no valid data in the 43 bit delay line ATOM1 always transmits an empty cell first therefore avoiding data corruption On reception the descrambling algorithm self synchronises before the HEC delineation process is complete and cell reception begins 2 1 Number of Connections ATOM1 transmits one cell at a time on the virtual connection specified for that cell The user can transmit ATM cells with the whole range of the cell s address field VCI and VPI combined ATOM1 receives cells after matching the cell header with a header look up table or an external CAM The internal look up table has up to 16 entries and cell headers can have
66. quired the ATM Forum UNI Specification states that unassigned cells should be transmitted while the ITU mandates use of idle cells The user must write the EHEAD and EPAYLOAD parameters as required and these two locations must be written in little endian byte order Unassigned cells are used as empty cells when EHEAD 0000 0000 and idle cells when EHEAD 0100 0000 In both cases EPAYLOAD should be initialised to 6A6A 6A64A 4 0 12 Status Information ASTATUS The ATOM1 Status parameter provides the user with additional status information concerning FIFO errors and receiver synchronisation status ASTATUS is shown in Figure 5 El Figure 5 ASTATUS Bits in the upper byte is set by ATOMI and cleared by the user Bits in the lower byte are set and cleared by ATOMI During initialisation the user must clear all bits in ASTATUS During operation the user can read and clear write zero to the upper byte but must only read the lower byte FIFO overruns and underruns are reported in the SCCE FIFO bit and further information is given in the ORUN and URUN bits ORUN 0 No Receiver FIFO Overrun 1 Receiver FIFO Overrun URUN 0 No transmitter FIFO underrun 1 Transmitter FIFO underrun Each change in state of the receiver cell delineation is reported in the SCCE SYNC bit The LOCK bit shows the current delineation status LOCK 0 The ATOMI receiver is out of synchronisation and is not receiving cells 1 The ATOMI receiver has gain
67. ransmit and receive ATM cells The SCC is configured but not enabled FI kk kCKCKCKCkCkCk kk kk ee A AAA Kok kc kk ko kk ee RIRE KR I I I IH He He ee Input Parameters Pointers to the SCC register SCC parameter RAM and CP register data structures 5 Accesses global data structure CP Ya Ay Output Parameters CP modified A TA x I He AR AAA KK ee ko kCKCKCK IC kk ko kk KR ee A A A AA K I I IH He e e void atom_init SCC ATOM struct SCC_regs ESCE struct ATOMI Params ATOM SCC registers SCC gt GSMRL 0 SCC Disabled SCC gt GSMRH 0x00001F80 Set sync and transparent bits SCC gt GSMRH 0x00003F80 Enable CAM and Set sync and transparent bits SCC gt PSMR 0 Disable scrambling and HEC coset SCC PSMR 0x2100 s Enable scrambling and HEC coset SCC SCC 0 Mask out interrupts SCC gt SCCE Oxffff Clear SCC event register Configure SCC parameter RAM for ATOM1 ATOM gt RBASE ARXBDO PQUICC Rx BD Base Address ATOM gt TBASE ATXBDO PQUICC Tx BD Base Address ATOM gt RFCR 0x13 Use Motorola byte ordering big endian ATOM gt TFCR 0x15 Use Motorola byte ordering big endian ATOM gt MRBLR 0 Transparent Receiver Max Buffer Length ATOM gt ALPHA 0 Receiver Synchronisation Alpha Counter ATOM gt DELTA 0 Receiver
68. receive BD 6 3 Transmit Buffer Descriptor and Data Buffer Transmit BDs are two bytes long as shown in Figure 10 Each BD is linked to one buffer that must hold the complete ATM cell to be transmitted Transmit buffers may be scattered around a 16K byte area of memory but must start on a word aligned address If the start address of a buffer is at the very end of the 16K byte area for example the transmit BD is programmed with 8FFF then the end of the transmit cell will be 48 bytes outside of the 16K byte area R SKIP W A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 Figure 10 ATOM1 Transmit Buffer Descriptor MPC860 ATOMI User s Manual 1 0 23 No Restriction on Circulation R Ready Control bit set by the user to initiate transmission of the associated cell ATOMI clears the Ready bit when the associated buffer has been transmitted SKIP Skip BD Control bit set by the user When ATOM encounters a transmit BD with the Skip bit set an empty cell is transmitted and control passes to the next BD When the Skip bit is set the Ready bit is ignored W Wrap Control bit set by the user to wrap the transmit BD queue after this BD I Interrupt Control bit set by the user When the cell associated with this BD is transmitted a transmit interrupt is generated This bit is ignored when the Skip bit is also set A18 A29 Address Address offset to the start of th
69. s and control halfword Buffer length and pointer fields are not implemented as for other PowerQUICC serial protocols BDs are located in the PowerQUICC s dual port RAM All data buffers have a fixed length of 52 bytes and are located within 16K byte buffer areas in memory Receive BD1 is associated with buffer 1 receive BD2 with buffer 2 etc Transmit and receive buffers are scattered within a 16K byte memory area and use an eleven bit pointer within the transmit BD to locate the buffer exactly The transmitter and receiver each use different 16K byte buffer areas which may be located anywhere in memory 6 1 ATOM1 Buffer Descriptor and Buffer Queues Figure 8 shows an example of the transmitter BD and data buffer queues and the pointers associated with them In this example there are 20 BDs each linked to a buffer TBASE points to the start of the BD queue and TX_BUFF1 points to the start of the buffer area ATOM1 calculates the exact start address of a transmit buffer by adding TX BUFFI to the address field in the transmit BD Buffers may thus be scattered randomly throughout the 16K byte area MPC860 ATOMI User s Manual 1 0 21 No Restriction on Circulation Queue of 20 Queue of 20 Tx BDs Transmit Buffers TX BUFF1 TBASE Tx Buffer 1 Address Offset in Tx BD2 ee Tx Buffer 2 Tx Buffer 3 T_CNT T_PTR Tx Buffer 20 Tx Buffer 19 16K Byte Buffer Area Figure 8 ATOM1 Transmi
70. sparent Mode SCCE in the MPC860 User s Manual GLT A clock glitch was detected by the SCC on the transmit clock See description of the Transparent Mode SCCE in the MPC860 User s Manual GLR A clock glitch was detected by the SCC on the receive clock See description of the Transparent Mode SCCE in the MPC860 User s Manual 3 2 4 SCC Mask Register SCCM The SCCM has the same bit definitions as the SCCE and allows the user to mask interrupts Further details are given in the MPC860 User s Manual 3 2 5 SCC Status Register SCCS The function of the SCCS register is unchanged when ATOM1 uses an SCC 3 3 Serial Interface ATOMI may use the MPC860 s serial interface SI in any mode although the time division multiplex mode to allows easy connection to El and T1 line interface devices This section of MPC860 ATOMI User s Manual 1 0 11 No Restriction on Circulation the User s Manual concentrates on the TDM interface although use of other serial interfaces is not precluded It is the user s responsibility to ensure that incoming cells are octet aligned with the SI handshake or synchronisation pulses ATOMI will then apply the cell HEC delineation mechanism correctly and synchronise with the incoming cell stream ATOMI can use either of the MPC860 TDM ports Programming information is given here for use of TDM A and can easily be converted for TDM B Further information about the SI is given in the MPC860 User s Manual
71. t Buffer and BD Queue Example In this example the first two buffers have been transmitted and ATOM1 has advanced the TBD_PTR pointer to point at the current BD Similarly the T PTR pointer has been advanced to point to the current data being transmitted by ATOMI T CNT is the offset of T PTR from the start of the data buffer When the end of the BD queue is reached TBD PTR is wrapped back by loading it from TBASE Receive BD and buffer queues follow the same structure as shown here for transmission 6 2 Receive Buffer Descriptor and Data Buffer Receive BDs are two bytes long as shown in Figure 9 Each BD is linked to one buffer that can hold a received ATM cell Receive buffers may be scattered around a 16K byte area of memory but each buffer must start on a word aligned address If the start address of a buffer is at the very end of the 16K byte area for example the BD is programmed with 8FFF then the end of the received cell will be 48 bytes outside of the 16K byte area When the user prepares an empty receive BD the address pointer to the start of the data buffer must be written into the BD When the Empty bit is set ownership if the BD is handed over from the user to the PowerQUICC s CP and the user must not modify any part of the BD Once a cell is received and ATOM returns the BD and buffer to the user the address pointer field is replaced with OAM and error status flags and the HEC of the incoming cell User software must maintai
72. triction on Circulation ATOMI Asynchronous Transfer Mode Microcode for the PowerQUICC 1 INTRODUCTION ATOM1 is an MPC860 RAM based microcode that provides physical layer ATM functions by converting one or more of the PowerQUICC s serial communication controllers SCCs into an ATM cell transmitter and receiver ATOMI provides the user with cell streaming facilities cell reception and transmission and event indications The user can add AAL functions to ATOMI using software The primary application of ATOM1 is intended to be G 804 plesiochronous digital hierarchy PDH and synchronous digital hierarchy SDH E1 and DS1 ATM equipment Such equipment is used for signalling and low rate data transfer and may be part of the telecommunications infrastructure or terminal equipment Figure 1 shows an ATM communications module built around the PowerQUICC running an ATOM1 microcode This module could be a board within a larger system or part of a larger ATM board The ATOMI1 microcode runs on the PowerQUICC s RISC communications processor CP and is stored in the dual port RAM The user interface to ATOMI is through buffer descriptors located in the PowerQUICC s dual port RAM and data buffers located in external memory The PowerQUICC s PowerPC core controls the module and memory using the on chip memory controller and other integration features 1 1 Key Features of ATOMI The key features of ATOMI are e Cell transmission and reception for al
73. ve Internal Byte Counter SCC Base 14 RTEMP Word Receiver Temporary Data Storage SCC Base 18 TSTATE Word Transmitter Internal State use init rx tx command SCC Base 1C SCC Base 20 T_PTR TBD_PTR Word Halfword Transmit Internal Data Pointer Transmit BD Pointer use init rx tx command SCC Base 22 T_CNT Halfword Transmit Internal Byte Counter SCC Base 24 TTEMP Word Transmitter Temporary Data Storage SCC Base 28 ALPHA Halfword Receiver Delineation Alpha Counter SCC Base 2A DELTA Halfword Receiver Delineation Delta Counter SCC Base 2C AVERSION Halfword ATOM 1 Version Number SCC Base 2E CAM PORT Halfword CAM Port B Mask SCC Base 30 RX_BUFF1 Word Receive Buffer Area Start Address SCC Base 34 TX_BUFF1 Word Transmit Buffer Area Start Address SCC Base 38 EHEAD Word Empty Cell Header little endian byte format 0000 0000 or 0100 0000 SCC Base 3C EPAYLOAD Word Empty Cell Payload little endian byte format Receive Data Stuffing Location 53 6A6A 6A6A SCC Base 40 RSTUFF Word to 52 byte conversion SCC Base 44 SHUFFLESTATE Halfword Receiver Data Shuffling State 0000 SCC Base 46 RHECTEMP Halfword Temporary HEC Storage SCC Base 48 THECTEMP Halfword Temporary HEC storage area SCC Base 4A AS
74. y be programmed with the result of a previous CRC 32 calculation if buffers are being strung together The user configures CRC_FC to define the SDMA function code pin settings when the SDMA reads the CRC 32 buffer Further information is given in the MPC860 User s Manual MPC860 ATOMI User s Manual 1 0 20 No Restriction on Circulation A CRC 32 calculation is started by writing 0F01 to the command register When the command has been accepted and CRC 32 processing begins ATOMI clears the FLG bit in the command register Processing continues through the whole CRC 32 buffer and when the calculation is complete ATOM sets bit 0 in the RISC Timer Even Register RTER This can be used to generate a processor interrupt by programming the PowerQUICC s interrupt controller Bit 0 of the RTER should be cleared before a CRC 32 calculation is started 6 BUFFER DESCRIPTORS amp BUFFERS ATOM1 uses a modified version of the standard MPC860 BD and buffer data structure better suited to the high number of and small size of ATM cells There is a single transmit BD queue and a single receive queue Associated with each BD queue is a buffer queue All ATOM1 BDs are two bytes long and buffers are all 52 bytes long These BD and buffer sizes maximise the number of BDs that can be located in the PowerQUICC s dual port RAM when the ATOM1 microcode is also present and running The BDs are a subset of the standard PowerQUICC BDs containing only a 16 bit statu

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